Merge Cavium Octeon SDK 2.0 Simple Executive; this brings some fixes and new

facilities as well as support for the Octeon 2 family of SoCs.

XXX Note that with our antediluvian assembler, we can't support some Octeon 2
    instructions and fall back to using the old ones instead.

259 files changed, 278322 insertions, 126603 deletions

diff --git a/sys/contrib/octeon-sdk/README.txt b/sys/contrib/octeon-sdk/README.txt
deleted file mode 100644
index 553c46d..0000000
--- a/sys/contrib/octeon-sdk/README.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Readme for the Octeon Executive Library
-
-
-The Octeon Executive Library provides runtime support and hardware 
-abstraction for the Octeon processor.  The executive is composed of the 
-libcvmx.a library as well as header files that provide  
-functionality with inline functions.
-
-
-Usage:
-
-The libcvmx.a library is built for every application as part of the
-application build. (Please refer to the 'related pages' section of the 
-HTML documentation for more information on the build system.)  
-Applications using the executive should include the header files from
-$OCTEON_ROOT/target/include and link against the library that is built in 
-the local obj directory. Each file using the executive 
-should include the following two header files in order:
-
-#include "cvmx-config.h"
-#include "cvmx.h"
-
-The cvmx-config.h file contains configuration information for the 
-executive and is generated by the cvmx-config script from an 
-'executive-config.h' file. A sample version of this file is provided 
-in the executive directory as 'executive-config.h.template'.  
-
-Copy this file to 'executive-config.h' into the 'config' subdirectory 
-of the application directory and customize as required by the application. 
-Applications that don't use any simple executive functionality can omit 
-the cvmx-config.h header file. Please refer to the examples for a 
-demonstration of where to put the executive-config.h file and for an
-example of generated cvmx-config.h.
-
-For file specific information please see the documentation within the 
-source files or the HTML documentation provided in docs/html/index.html.
-The HTML documentation is automatically generated by Doxygen from the 
-source files.
-
-
-
-==========================================================================
-Please see the release notes for version specific information.
diff --git a/sys/contrib/octeon-sdk/cvmip.h b/sys/contrib/octeon-sdk/cvmip.h
index a8ac16d..b3aa6b0 100644
--- a/sys/contrib/octeon-sdk/cvmip.h
+++ b/sys/contrib/octeon-sdk/cvmip.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -48,7 +50,7 @@
  *
  * Definitions for the Internet Protocol (IP) support.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-abi.h b/sys/contrib/octeon-sdk/cvmx-abi.h
index 0711558..93d71b3 100644
--- a/sys/contrib/octeon-sdk/cvmx-abi.h
+++ b/sys/contrib/octeon-sdk/cvmx-abi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file defines macros for use in determining the current calling ABI.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
 */
 
 #ifndef __CVMX_ABI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-access-native.h b/sys/contrib/octeon-sdk/cvmx-access-native.h
index af95390..962671c 100644
--- a/sys/contrib/octeon-sdk/cvmx-access-native.h
+++ b/sys/contrib/octeon-sdk/cvmx-access-native.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  * Functions for accessing memory and CSRs on Octeon when we are compiling
@@ -81,9 +83,24 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr)
         cvmx_warn_if(ptr==NULL, "cvmx_ptr_to_phys() passed a NULL pointer\n");
 
 #ifdef CVMX_BUILD_FOR_UBOOT
-    /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
-    ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
-    return(CAST64(ptr) & 0x7FFFFFFF);
+    uint64_t uboot_tlb_ptr_to_phys(void *ptr);
+
+    if (((uint32_t)ptr) < 0x80000000)
+    {
+        /* Handle useg (unmapped due to ERL) here*/
+        return(CAST64(ptr) & 0x7FFFFFFF);
+    }
+    else if (((uint32_t)ptr) < 0xC0000000)
+    {
+        /* Here we handle KSEG0/KSEG1 _pointers_.  We know we are dealing
+        ** with 32 bit only values, so we treat them that way.  Note that
+        ** a cvmx_phys_to_ptr(cvmx_ptr_to_phys(X)) will not return X in this case,
+        ** but the physical address of the KSEG0/KSEG1 address. */
+        return(CAST64(ptr) & 0x1FFFFFFF);
+    }
+    else
+        return(uboot_tlb_ptr_to_phys(ptr));   /* Should not get get here in !TLB case */
+
 #endif
 
 #ifdef __linux__
@@ -166,14 +183,49 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
 
 #ifdef CVMX_BUILD_FOR_UBOOT
-    /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
-    ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
+#if !CONFIG_OCTEON_UBOOT_TLB
     if (physical_address >= 0x80000000)
         return NULL;
     else
         return CASTPTR(void, (physical_address & 0x7FFFFFFF));
 #endif
 
+    /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
+    ** which can have a physical address above the 32 bit address space.  1-1 mappings are used
+    ** to allow the low 2 GBytes to be accessed as in error level.
+    **
+    ** NOTE:  This conversion can cause problems in u-boot, as users may want to enter addresses
+    ** like 0xBFC00000 (kseg1 boot bus address), which is a valid 64 bit physical address,
+    ** but is likely intended to be a boot bus address. */
+
+    if (physical_address < 0x80000000)
+    {
+        /* Handle useg here.  ERL is set, so useg is unmapped.  This is the only physical
+        ** address range that is directly addressable by u-boot. */
+        return CASTPTR(void, physical_address);
+    }
+    else
+    {
+	DECLARE_GLOBAL_DATA_PTR;
+        extern char uboot_start;
+        /* Above 0x80000000 we can only support one case - a physical address
+        ** that is mapped for u-boot code/data.  We check against the u-boot mem range,
+        ** and return NULL if it is out of this range.
+        */
+        if (physical_address >= gd->bd->bi_uboot_ram_addr
+            && physical_address < gd->bd->bi_uboot_ram_addr + gd->bd->bi_uboot_ram_used_size)
+        {
+            return ((char *)&uboot_start + (physical_address - gd->bd->bi_uboot_ram_addr));
+        }
+        else
+            return(NULL);
+    }
+
+    if (physical_address >= 0x80000000)
+        return NULL;
+    else
+#endif
+
 #ifdef __linux__
     if (sizeof(void*) == 8)
     {
@@ -199,7 +251,8 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
     if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
         return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
-    else if ((physical_address >= 0x410000000ull) && (physical_address < 0x420000000ull))
+    else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
+                                                       (physical_address < 0x420000000ull))
         return CASTPTR(void, physical_address - 0x400000000ull);
     else
         return CASTPTR(void, physical_address);
@@ -464,7 +517,7 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
     /* Perform an immediate read after every write to an RSL register to force
         the write to complete. It doesn't matter what RSL read we do, so we
         choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
-    if ((csr_addr >> 40) == (0x800118))
+    if (((csr_addr >> 40) & 0x7ffff) == (0x118))
         cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT);
 }
 
@@ -503,7 +556,7 @@ static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
 
 
 /**
- * Number of the Core on which the program is currently running. 
+ * Number of the Core on which the program is currently running.
  *
  * @return Number of cores
  */
@@ -548,53 +601,36 @@ static inline int cvmx_dpop(uint64_t val)
 
 
 /**
- * Provide current cycle counter as a return value
+ * @deprecated
+ * Provide current cycle counter as a return value. Deprecated, use
+ * cvmx_clock_get_count(CVMX_CLOCK_CORE) to get cycle counter.
  *
  * @return current cycle counter
  */
 static inline uint64_t cvmx_get_cycle(void)
 {
-#if defined(CVMX_ABI_O32)
-    uint32_t tmp_low, tmp_hi;
-
-    asm volatile (
-               "   .set push                    \n"
-               "   .set mips64r2                \n"
-               "   .set noreorder               \n"
-               "   rdhwr %[tmpl], $31           \n"
-               "   dsrl  %[tmph], %[tmpl], 32   \n"
-               "   sll   %[tmpl], 0             \n"
-               "   sll   %[tmph], 0             \n"
-               "   .set pop                 \n"
-                  : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
-
-    return(((uint64_t)tmp_hi << 32) + tmp_low);
-#else
-    uint64_t cycle;
-    CVMX_RDHWR(cycle, 31);
-    return(cycle);
-#endif
+    return cvmx_clock_get_count(CVMX_CLOCK_CORE);
 }
 
 
 /**
- * Reads a chip global cycle counter.  This counts CPU cycles since
- * chip reset.  The counter is 64 bit.
- * This register does not exist on CN38XX pass 1 silicion
+ * @deprecated
+ * Reads a chip global cycle counter.  This counts SCLK cycles since
+ * chip reset.  The counter is 64 bit. This function is deprecated as the rate
+ * of the global cycle counter is different between Octeon+ and Octeon2, use
+ * cvmx_clock_get_count(CVMX_CLOCK_SCLK) instead. For Octeon2, the clock rate
+ * of SCLK may be differnet than the core clock.
  *
  * @return Global chip cycle count since chip reset.
  */
 static inline uint64_t cvmx_get_cycle_global(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
-        return 0;
-    else
-        return cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
+    return cvmx_clock_get_count(CVMX_CLOCK_IPD);
 }
 
 
 /**
- * Wait for the specified number of cycle
+ * Wait for the specified number of core clock cycles
  *
  * @param cycles
  */
@@ -616,7 +652,7 @@ static inline void cvmx_wait(uint64_t cycles)
  */
 static inline void cvmx_wait_usec(uint64_t usec)
 {
-    uint64_t done = cvmx_get_cycle() + usec * cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+    uint64_t done = cvmx_get_cycle() + usec * cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
     while (cvmx_get_cycle() < done)
     {
         /* Spin */
@@ -625,6 +661,22 @@ static inline void cvmx_wait_usec(uint64_t usec)
 
 
 /**
+ * Wait for the specified number of io clock cycles
+ *
+ * @param cycles
+ */
+static inline void cvmx_wait_io(uint64_t cycles)
+{
+    uint64_t done = cvmx_clock_get_count(CVMX_CLOCK_SCLK) + cycles;
+
+    while (cvmx_clock_get_count(CVMX_CLOCK_SCLK) < done)
+    {
+        /* Spin */
+    }
+}
+
+
+/**
  * Perform a soft reset of Octeon
  *
  * @return
diff --git a/sys/contrib/octeon-sdk/cvmx-access.h b/sys/contrib/octeon-sdk/cvmx-access.h
index d0da7ca..c1206dd 100644
--- a/sys/contrib/octeon-sdk/cvmx-access.h
+++ b/sys/contrib/octeon-sdk/cvmx-access.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  * Function prototypes for accessing memory and CSRs on Octeon.
@@ -138,7 +140,7 @@ CVMX_FUNCTION void cvmx_send_single(uint64_t data);
 CVMX_FUNCTION void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr);
 
 /**
- * Number of the Core on which the program is currently running. 
+ * Number of the Core on which the program is currently running.
  *
  * @return Number of cores
  */
@@ -165,23 +167,28 @@ CVMX_FUNCTION uint32_t cvmx_pop(uint32_t val);
 CVMX_FUNCTION int cvmx_dpop(uint64_t val);
 
 /**
- * Provide current cycle counter as a return value
+ * @deprecated
+ * Provide current cycle counter as a return value. Deprecated, use
+ * cvmx_clock_get_count(CVMX_CLOCK_CORE) to get cycle counter.
  *
  * @return current cycle counter
  */
 CVMX_FUNCTION uint64_t cvmx_get_cycle(void);
 
 /**
- * Reads a chip global cycle counter.  This counts CPU cycles since
- * chip reset.  The counter is 64 bit.
- * This register does not exist on CN38XX pass 1 silicion
+ * @deprecated
+ * Reads a chip global cycle counter.  This counts SCLK cycles since
+ * chip reset.  The counter is 64 bit. This function is deprecated as the rate
+ * of the global cycle counter is different between Octeon+ and Octeon2, use
+ * cvmx_clock_get_count(CVMX_CLOCK_SCLK) instead. For Octeon2, the clock rate
+ * of SCLK may be differnet than the core clock.
  *
  * @return Global chip cycle count since chip reset.
  */
-CVMX_FUNCTION uint64_t cvmx_get_cycle_global(void);
+CVMX_FUNCTION uint64_t cvmx_get_cycle_global(void) __attribute__((deprecated));
 
 /**
- * Wait for the specified number of cycle
+ * Wait for the specified number of core clock cycles
  *
  * @param cycles
  */
@@ -195,6 +202,13 @@ CVMX_FUNCTION void cvmx_wait(uint64_t cycles);
 CVMX_FUNCTION void cvmx_wait_usec(uint64_t usec);
 
 /**
+ * Wait for the specified number of io clock cycles
+ *
+ * @param cycles
+ */
+CVMX_FUNCTION void cvmx_wait_io(uint64_t cycles);
+
+/**
  * Perform a soft reset of Octeon
  *
  * @return
diff --git a/sys/contrib/octeon-sdk/cvmx-address.h b/sys/contrib/octeon-sdk/cvmx-address.h
index 096a68a..daaf6a4 100644
--- a/sys/contrib/octeon-sdk/cvmx-address.h
+++ b/sys/contrib/octeon-sdk/cvmx-address.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  * Typedefs and defines for working with Octeon physical addresses.
@@ -63,29 +65,27 @@ typedef enum {
    CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
 } cvmx_mips_xkseg_space_t;
 
-// decodes <14:13> of a kseg3 window address
+  /* decodes <14:13> of a kseg3 window address */
 typedef enum {
    CVMX_ADD_WIN_SCR = 0L,
-   CVMX_ADD_WIN_DMA = 1L,   // see cvmx_add_win_dma_dec_t for further decode
+   CVMX_ADD_WIN_DMA = 1L,   /* see cvmx_add_win_dma_dec_t for further decode */
    CVMX_ADD_WIN_UNUSED = 2L,
    CVMX_ADD_WIN_UNUSED2 = 3L
 } cvmx_add_win_dec_t;
 
-// decode within DMA space
+  /* decode within DMA space */
 typedef enum {
-   CVMX_ADD_WIN_DMA_ADD = 0L,     // add store data to the write buffer entry, allocating it if necessary
-   CVMX_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
-                                     // store data must be normal DRAM memory space address in this case
-   CVMX_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
-                                     // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents
-   CVMX_ADD_WIN_DMA_SENDIO = 3L,  // send out the write buffer entry as an IO write
-                                     // store data must be normal IO space address in this case
-   CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
-                                        // no write buffer data needed/used
+   CVMX_ADD_WIN_DMA_ADD = 0L,     /* add store data to the write buffer entry, allocating it if necessary */
+   CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */
+   /* store data must be normal DRAM memory space address in this case */
+   CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */
+   /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
+   CVMX_ADD_WIN_DMA_SENDIO = 3L,  /* send out the write buffer entry as an IO write */
+   /* store data must be normal IO space address in this case */
+   CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */
+   /* no write buffer data needed/used */
 } cvmx_add_win_dma_dec_t;
 
-
-
 /**
  *   Physical Address Decode
  *
@@ -116,63 +116,63 @@ typedef union {
    struct {
       cvmx_mips_space_t          R   : 2;
       uint64_t               offset :62;
-   } sva; // mapped or unmapped virtual address
+   } sva; /* mapped or unmapped virtual address */
 
    struct {
       uint64_t               zeroes :33;
       uint64_t               offset :31;
-   } suseg; // mapped USEG virtual addresses (typically)
+   } suseg; /* mapped USEG virtual addresses (typically) */
 
    struct {
       uint64_t                ones  :33;
       cvmx_mips_xkseg_space_t   sp   : 2;
       uint64_t               offset :29;
-   } sxkseg; // mapped or unmapped virtual address
+   } sxkseg; /* mapped or unmapped virtual address */
 
    struct {
-      cvmx_mips_space_t          R   : 2; // CVMX_MIPS_SPACE_XKPHYS in this case
-      uint64_t                 cca  : 3; // ignored by octeon
+      cvmx_mips_space_t          R   : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
+      uint64_t                 cca  : 3; /* ignored by octeon */
       uint64_t                 mbz  :10;
-      uint64_t                  pa  :49; // physical address
-   } sxkphys; // physical address accessed through xkphys unmapped virtual address
+      uint64_t                  pa  :49; /* physical address */
+   } sxkphys; /* physical address accessed through xkphys unmapped virtual address */
 
    struct {
       uint64_t                 mbz  :15;
-      uint64_t                is_io : 1; // if set, the address is uncached and resides on MCB bus
-      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
-      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t                is_io : 1; /* if set, the address is uncached and resides on MCB bus */
+      uint64_t                 did  : 8; /* the hardware ignores this field when is_io==0, else device ID */
+      uint64_t                unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
       uint64_t               offset :36;
-   } sphys; // physical address
+   } sphys; /* physical address */
 
    struct {
-      uint64_t               zeroes :24; // techically, <47:40> are dont-cares
-      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t               zeroes :24; /* techically, <47:40> are dont-cares */
+      uint64_t                unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
       uint64_t               offset :36;
-   } smem; // physical mem address
+   } smem; /* physical mem address */
 
    struct {
       uint64_t                 mem_region  :2;
       uint64_t                 mbz  :13;
-      uint64_t                is_io : 1; // 1 in this case
-      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
-      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t                is_io : 1; /* 1 in this case */
+      uint64_t                 did  : 8; /* the hardware ignores this field when is_io==0, else device ID */
+      uint64_t                unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
       uint64_t               offset :36;
-   } sio; // physical IO address
+   } sio; /* physical IO address */
 
    struct {
       uint64_t                ones   : 49;
-      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_SCR (0) in this case
+      cvmx_add_win_dec_t   csrdec : 2;    /* CVMX_ADD_WIN_SCR (0) in this case */
       uint64_t                addr   : 13;
-   } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3
+   } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */
 
-   // there should only be stores to IOBDMA space, no loads
+   /* there should only be stores to IOBDMA space, no loads */
    struct {
       uint64_t                ones   : 49;
-      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_DMA (1) in this case
+      cvmx_add_win_dec_t   csrdec : 2;    /* CVMX_ADD_WIN_DMA (1) in this case */
       uint64_t                unused2: 3;
       cvmx_add_win_dma_dec_t type : 3;
       uint64_t                addr   : 7;
-   } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3
+   } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */
 
    struct {
       uint64_t                didspace : 24;
@@ -203,8 +203,8 @@ typedef union {
 #define CVMX_FULL_DID(did,subdid)           (((did) << 3) | (subdid))
 
 
-// from include/ncb_rsl_id.v
-#define CVMX_OCT_DID_MIS 0ULL   // misc stuff
+   /* from include/ncb_rsl_id.v */
+#define CVMX_OCT_DID_MIS 0ULL   /* misc stuff */
 #define CVMX_OCT_DID_GMX0 1ULL
 #define CVMX_OCT_DID_GMX1 2ULL
 #define CVMX_OCT_DID_PCI 3ULL
@@ -217,7 +217,7 @@ typedef union {
 #define CVMX_OCT_DID_PKT 10ULL
 #define CVMX_OCT_DID_TIM 11ULL
 #define CVMX_OCT_DID_TAG 12ULL
-// the rest are not on the IO bus
+   /* the rest are not on the IO bus */
 #define CVMX_OCT_DID_L2C 16ULL
 #define CVMX_OCT_DID_LMC 17ULL
 #define CVMX_OCT_DID_SPX0 18ULL
diff --git a/sys/contrib/octeon-sdk/cvmx-agl-defs.h b/sys/contrib/octeon-sdk/cvmx-agl-defs.h
new file mode 100644
index 0000000..2138f90
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-agl-defs.h
@@ -0,0 +1,4615 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-agl-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon agl.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_AGL_TYPEDEFS_H__
+#define __CVMX_AGL_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
+}
+#else
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
+}
+#else
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC()
+static inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
+}
+#else
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
+}
+#else
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
+}
+#else
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
+}
+#else
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
+}
+#else
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
+}
+#else
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_AGL_PRTX_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
+#endif
+
+/**
+ * cvmx_agl_gmx_bad_reg
+ *
+ * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong
+ *
+ *
+ * Notes:
+ * OUT_OVR[0], LOSTSTAT[0], OVRFLW, TXPOP, TXPSH    will be reset when MIX0_CTL[RESET] is set to 1.
+ * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.
+ * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+union cvmx_agl_gmx_bad_reg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_bad_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t txpsh1                       : 1;  /**< TX FIFO overflow (MII1) */
+	uint64_t txpop1                       : 1;  /**< TX FIFO underflow (MII1) */
+	uint64_t ovrflw1                      : 1;  /**< RX FIFO overflow (MII1) */
+	uint64_t txpsh                        : 1;  /**< TX FIFO overflow (MII0) */
+	uint64_t txpop                        : 1;  /**< TX FIFO underflow (MII0) */
+	uint64_t ovrflw                       : 1;  /**< RX FIFO overflow (MII0) */
+	uint64_t reserved_27_31               : 5;
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow */
+	uint64_t reserved_24_25               : 2;
+	uint64_t loststat                     : 2;  /**< TX Statistics data was over-written
+                                                         In MII/RGMII, one bit per port
+                                                         TX Stats are corrupted */
+	uint64_t reserved_4_21                : 18;
+	uint64_t out_ovr                      : 2;  /**< Outbound data FIFO overflow */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t out_ovr                      : 2;
+	uint64_t reserved_4_21                : 18;
+	uint64_t loststat                     : 2;
+	uint64_t reserved_24_25               : 2;
+	uint64_t statovr                      : 1;
+	uint64_t reserved_27_31               : 5;
+	uint64_t ovrflw                       : 1;
+	uint64_t txpop                        : 1;
+	uint64_t txpsh                        : 1;
+	uint64_t ovrflw1                      : 1;
+	uint64_t txpop1                       : 1;
+	uint64_t txpsh1                       : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_agl_gmx_bad_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t txpsh1                       : 1;  /**< TX FIFO overflow (MII1) */
+	uint64_t txpop1                       : 1;  /**< TX FIFO underflow (MII1) */
+	uint64_t ovrflw1                      : 1;  /**< RX FIFO overflow (MII1) */
+	uint64_t txpsh                        : 1;  /**< TX FIFO overflow (MII0) */
+	uint64_t txpop                        : 1;  /**< TX FIFO underflow (MII0) */
+	uint64_t ovrflw                       : 1;  /**< RX FIFO overflow (MII0) */
+	uint64_t reserved_27_31               : 5;
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow */
+	uint64_t reserved_23_25               : 3;
+	uint64_t loststat                     : 1;  /**< TX Statistics data was over-written
+                                                         TX Stats are corrupted */
+	uint64_t reserved_4_21                : 18;
+	uint64_t out_ovr                      : 2;  /**< Outbound data FIFO overflow */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t out_ovr                      : 2;
+	uint64_t reserved_4_21                : 18;
+	uint64_t loststat                     : 1;
+	uint64_t reserved_23_25               : 3;
+	uint64_t statovr                      : 1;
+	uint64_t reserved_27_31               : 5;
+	uint64_t ovrflw                       : 1;
+	uint64_t txpop                        : 1;
+	uint64_t txpsh                        : 1;
+	uint64_t ovrflw1                      : 1;
+	uint64_t txpop1                       : 1;
+	uint64_t txpsh1                       : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_bad_reg_cn52xx    cn52xxp1;
+	struct cvmx_agl_gmx_bad_reg_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t txpsh                        : 1;  /**< TX FIFO overflow */
+	uint64_t txpop                        : 1;  /**< TX FIFO underflow */
+	uint64_t ovrflw                       : 1;  /**< RX FIFO overflow */
+	uint64_t reserved_27_31               : 5;
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow */
+	uint64_t reserved_23_25               : 3;
+	uint64_t loststat                     : 1;  /**< TX Statistics data was over-written
+                                                         TX Stats are corrupted */
+	uint64_t reserved_3_21                : 19;
+	uint64_t out_ovr                      : 1;  /**< Outbound data FIFO overflow */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t out_ovr                      : 1;
+	uint64_t reserved_3_21                : 19;
+	uint64_t loststat                     : 1;
+	uint64_t reserved_23_25               : 3;
+	uint64_t statovr                      : 1;
+	uint64_t reserved_27_31               : 5;
+	uint64_t ovrflw                       : 1;
+	uint64_t txpop                        : 1;
+	uint64_t txpsh                        : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_bad_reg_cn56xx    cn56xxp1;
+	struct cvmx_agl_gmx_bad_reg_s         cn63xx;
+	struct cvmx_agl_gmx_bad_reg_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;
+
+/**
+ * cvmx_agl_gmx_bist
+ *
+ * AGL_GMX_BIST = GMX BIST Results
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_bist
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t status                       : 25; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.inb.fif_bnk_ext0
+                                                         - 5: gmx#.inb.fif_bnk_ext1
+                                                         - 6: gmx#.inb.fif_bnk_ext2
+                                                         - 7: gmx#.inb.fif_bnk_ext3
+                                                         - 8: gmx#.outb.fif.fif_bnk0
+                                                         - 9: gmx#.outb.fif.fif_bnk1
+                                                         - 10: RAZ
+                                                         - 11: RAZ
+                                                         - 12: gmx#.outb.fif.fif_bnk_ext0
+                                                         - 13: gmx#.outb.fif.fif_bnk_ext1
+                                                         - 14: RAZ
+                                                         - 15: RAZ
+                                                         - 16: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 17: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 18: RAZ
+                                                         - 19: RAZ
+                                                         - 20: gmx#.csr.drf20x32m2_bist
+                                                         - 21: gmx#.csr.drf20x48m2_bist
+                                                         - 22: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 23: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 24: RAZ */
+#else
+	uint64_t status                       : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_agl_gmx_bist_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t status                       : 10; /**< BIST Results.
+                                                          HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.drf128x78m1_bist
+                                                         - 1: gmx#.outb.fif.drf128x71m1_bist
+                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 3: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 4: 0
+                                                         - 5: 0
+                                                         - 6: gmx#.csr.drf20x80m1_bist
+                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 9: 0 */
+#else
+	uint64_t status                       : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_bist_cn52xx       cn52xxp1;
+	struct cvmx_agl_gmx_bist_cn52xx       cn56xx;
+	struct cvmx_agl_gmx_bist_cn52xx       cn56xxp1;
+	struct cvmx_agl_gmx_bist_s            cn63xx;
+	struct cvmx_agl_gmx_bist_s            cn63xxp1;
+};
+typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;
+
+/**
+ * cvmx_agl_gmx_drv_ctl
+ *
+ * AGL_GMX_DRV_CTL = GMX Drive Control
+ *
+ *
+ * Notes:
+ * NCTL, PCTL, BYP_EN    will be reset when MIX0_CTL[RESET] is set to 1.
+ * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_drv_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_drv_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t byp_en1                      : 1;  /**< Compensation Controller Bypass Enable (MII1) */
+	uint64_t reserved_45_47               : 3;
+	uint64_t pctl1                        : 5;  /**< AGL PCTL (MII1) */
+	uint64_t reserved_37_39               : 3;
+	uint64_t nctl1                        : 5;  /**< AGL NCTL (MII1) */
+	uint64_t reserved_17_31               : 15;
+	uint64_t byp_en                       : 1;  /**< Compensation Controller Bypass Enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t pctl                         : 5;  /**< AGL PCTL */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 5;  /**< AGL NCTL */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t byp_en                       : 1;
+	uint64_t reserved_17_31               : 15;
+	uint64_t nctl1                        : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t pctl1                        : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t byp_en1                      : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_agl_gmx_drv_ctl_s         cn52xx;
+	struct cvmx_agl_gmx_drv_ctl_s         cn52xxp1;
+	struct cvmx_agl_gmx_drv_ctl_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t byp_en                       : 1;  /**< Compensation Controller Bypass Enable */
+	uint64_t reserved_13_15               : 3;
+	uint64_t pctl                         : 5;  /**< AGL PCTL */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 5;  /**< AGL NCTL */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t byp_en                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_drv_ctl_cn56xx    cn56xxp1;
+};
+typedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t;
+
+/**
+ * cvmx_agl_gmx_inf_mode
+ *
+ * AGL_GMX_INF_MODE = Interface Mode
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_inf_mode
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_inf_mode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t en                           : 1;  /**< Interface Enable */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_agl_gmx_inf_mode_s        cn52xx;
+	struct cvmx_agl_gmx_inf_mode_s        cn52xxp1;
+	struct cvmx_agl_gmx_inf_mode_s        cn56xx;
+	struct cvmx_agl_gmx_inf_mode_s        cn56xxp1;
+};
+typedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t;
+
+/**
+ * cvmx_agl_gmx_prt#_cfg
+ *
+ * AGL_GMX_PRT_CFG = Port description
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_prtx_cfg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_prtx_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t tx_idle                      : 1;  /**< TX Machine is idle */
+	uint64_t rx_idle                      : 1;  /**< RX Machine is idle */
+	uint64_t reserved_9_11                : 3;
+	uint64_t speed_msb                    : 1;  /**< Link Speed MSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t burst                        : 1;  /**< Half-Duplex Burst Enable
+                                                         Only valid for 1000Mbs half-duplex operation
+                                                          0 = burst length of 0x2000 (halfdup / 1000Mbs)
+                                                          1 = burst length of 0x0    (all other modes) */
+	uint64_t tx_en                        : 1;  /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all packet cycles will appear as
+                                                         inter-frame cycles. */
+	uint64_t rx_en                        : 1;  /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all packet cycles will appear as
+                                                         inter-frame cycles. */
+	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation) */
+	uint64_t duplex                       : 1;  /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+	uint64_t speed                        : 1;  /**< Link Speed LSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved */
+	uint64_t en                           : 1;  /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+	uint64_t en                           : 1;
+	uint64_t speed                        : 1;
+	uint64_t duplex                       : 1;
+	uint64_t slottime                     : 1;
+	uint64_t rx_en                        : 1;
+	uint64_t tx_en                        : 1;
+	uint64_t burst                        : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t speed_msb                    : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rx_idle                      : 1;
+	uint64_t tx_idle                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_agl_gmx_prtx_cfg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t tx_en                        : 1;  /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all MII cycles will appear as
+                                                         inter-frame cycles. */
+	uint64_t rx_en                        : 1;  /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all MII cycles will appear as
+                                                         inter-frame cycles. */
+	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = Reserved */
+	uint64_t duplex                       : 1;  /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+	uint64_t speed                        : 1;  /**< Link Speed
+                                                         0 = 10/100Mbs operation
+                                                         1 = Reserved */
+	uint64_t en                           : 1;  /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+	uint64_t en                           : 1;
+	uint64_t speed                        : 1;
+	uint64_t duplex                       : 1;
+	uint64_t slottime                     : 1;
+	uint64_t rx_en                        : 1;
+	uint64_t tx_en                        : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn52xxp1;
+	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn56xx;
+	struct cvmx_agl_gmx_prtx_cfg_cn52xx   cn56xxp1;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn63xx;
+	struct cvmx_agl_gmx_prtx_cfg_s        cn63xxp1;
+};
+typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam0
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam0
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam0_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam1
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam1
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam1_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam2
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam2
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam2_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam3
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam3
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam3_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam4
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam4
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam4_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam5
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam5
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam5_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam_en
+ *
+ * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_adr_cam_en
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t en                           : 8;  /**< CAM Entry Enables */
+#else
+	uint64_t en                           : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_cam_en_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;
+
+/**
+ * cvmx_agl_gmx_rx#_adr_ctl
+ *
+ * AGL_GMX_RX_ADR_CTL = Address Filtering Control
+ *
+ *
+ * Notes:
+ * * ALGORITHM
+ *   Here is some pseudo code that represents the address filter behavior.
+ *
+ *      @verbatim
+ *      bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ *        ASSERT(prt >= 0 && prt <= 3);
+ *        if (is_bcst(dmac))                               // broadcast accept
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
+ *          return REJECT;
+ *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
+ *          return ACCEPT;
+ *
+ *        cam_hit = 0;
+ *
+ *        for (i=0; i<8; i++) [
+ *          if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
+ *            continue;
+ *          uint48 unswizzled_mac_adr = 0x0;
+ *          for (j=5; j>=0; j--) [
+ *             unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
+ *          ]
+ *          if (unswizzled_mac_adr == dmac) [
+ *            cam_hit = 1;
+ *            break;
+ *          ]
+ *        ]
+ *
+ *        if (cam_hit)
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ *        else
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
+ *      ]
+ *      @endverbatim
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_adr_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t cam_mode                     : 1;  /**< Allow or deny DMAC address filter
+                                                         0 = reject the packet on DMAC address match
+                                                         1 = accept the packet on DMAC address match */
+	uint64_t mcst                         : 2;  /**< Multicast Mode
+                                                         0 = Use the Address Filter CAM
+                                                         1 = Force reject all multicast packets
+                                                         2 = Force accept all multicast packets
+                                                         3 = Reserved */
+	uint64_t bcst                         : 1;  /**< Accept All Broadcast Packets */
+#else
+	uint64_t bcst                         : 1;
+	uint64_t mcst                         : 2;
+	uint64_t cam_mode                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn52xx;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn52xxp1;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn56xx;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_adr_ctl_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;
+
+/**
+ * cvmx_agl_gmx_rx#_decision
+ *
+ * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
+ *
+ *
+ * Notes:
+ * As each byte in a packet is received by GMX, the L2 byte count is compared
+ * against the AGL_GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
+ * from the beginning of the L2 header (DMAC).  In normal operation, the L2
+ * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any
+ * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]).
+ *
+ * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
+ * packet and would require UDD skip length to account for them.
+ *
+ *                                                 L2 Size
+ * Port Mode             <=AGL_GMX_RX_DECISION bytes (default=24)  >AGL_GMX_RX_DECISION bytes (default=24)
+ *
+ * MII/Full Duplex       accept packet                             apply filters
+ *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
+ *
+ * MII/Half Duplex       drop packet                               apply filters
+ *                       packet is unconditionally dropped         accept packet based on DMAC
+ *
+ * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_decision
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_decision_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t cnt                          : 5;  /**< The byte count to decide when to accept or filter
+                                                         a packet. */
+#else
+	uint64_t cnt                          : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_decision_s    cn52xx;
+	struct cvmx_agl_gmx_rxx_decision_s    cn52xxp1;
+	struct cvmx_agl_gmx_rxx_decision_s    cn56xx;
+	struct cvmx_agl_gmx_rxx_decision_s    cn56xxp1;
+	struct cvmx_agl_gmx_rxx_decision_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_decision_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;
+
+/**
+ * cvmx_agl_gmx_rx#_frm_chk
+ *
+ * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
+ *
+ *
+ * Notes:
+ * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_frm_chk
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_frm_chk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t niberr                       : 1;  /**< Nibble error */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with packet data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with MII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
+	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
+	struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_frm_chk_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;
+
+/**
+ * cvmx_agl_gmx_rx#_frm_ctl
+ *
+ * AGL_GMX_RX_FRM_CTL = Frame Control
+ *
+ *
+ * Notes:
+ * * PRE_STRP
+ *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
+ *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
+ *   core as part of the packet.
+ *
+ *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
+ *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
+ *   are skipped when locating the start of the L2 header for DMAC and Control
+ *   frame recognition.
+ *
+ * * CTL_BCK/CTL_DRP
+ *   These bits control how the HW handles incoming PAUSE packets.  Here are
+ *   the most common modes of operation:
+ *     CTL_BCK=1,CTL_DRP=1   - HW does it all
+ *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
+ *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
+ *
+ *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
+ *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
+ *   would constitute an exception which should be handled by the processing
+ *   cores.  PAUSE packets should not be forwarded.
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_frm_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
+                                                         When PTP_MODE is set, a 64-bit timestamp will be
+                                                         prepended to every incoming packet. The timestamp
+                                                         bytes are added to the packet in such a way as to
+                                                         not modify the packet's receive byte count.  This
+                                                         implies that the AGL_GMX_RX_JABBER,
+                                                         AGL_GMX_RX_FRM_MIN, AGL_GMX_RX_FRM_MAX,
+                                                         AGL_GMX_RX_DECISION, AGL_GMX_RX_UDD_SKP, and the
+                                                         AGL_GMX_RX_STATS_* do not require any adjustment
+                                                         as they operate on the received packet size.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */
+	uint64_t reserved_11_11               : 1;
+	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets */
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PRE_STRP should be set to
+                                                         account for the variable nature of the PREAMBLE.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is less strict.
+                                                         AGL will begin the frame at the first SFD.
+                                                         PRE_FREE must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_STRP must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send a valid 802.3
+                                                         PREAMBLE to begin every frame. AGL checks that a
+                                                         valid PREAMBLE is received (based on PRE_FREE).
+                                                         When a problem does occur within the PREAMBLE
+                                                         seqeunce, the frame is marked as bad and not sent
+                                                         into the core.  The AGL_GMX_RX_INT_REG[PCTERR]
+                                                         interrupt is also raised. */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t pre_align                    : 1;
+	uint64_t null_dis                     : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t ptp_mode                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD
+                                                         PRE_FREE must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_STRP must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t pre_align                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
+	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
+	struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_frm_ctl_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;
+
+/**
+ * cvmx_agl_gmx_rx#_frm_max
+ *
+ * AGL_GMX_RX_FRM_MAX = Frame Max length
+ *
+ *
+ * Notes:
+ * When changing the LEN field, be sure that LEN does not exceed
+ * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
+ * are within the maximum length parameter to be rejected because they exceed
+ * the AGL_GMX_RX_JABBER[CNT] limit.
+ *
+ * Notes:
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_frm_max
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_frm_max_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t len                          : 16; /**< Byte count for Max-sized frame check
+                                                         AGL_GMX_RXn_FRM_CHK[MAXERR] enables the check
+                                                         for port n.
+                                                         If enabled, failing packets set the MAXERR
+                                                         interrupt and the MIX opcode is set to OVER_FCS
+                                                         (0x3, if packet has bad FCS) or OVER_ERR (0x4, if
+                                                         packet has good FCS).
+                                                         LEN <= AGL_GMX_RX_JABBER[CNT] */
+#else
+	uint64_t len                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn52xx;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn52xxp1;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn56xx;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_frm_max_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;
+
+/**
+ * cvmx_agl_gmx_rx#_frm_min
+ *
+ * AGL_GMX_RX_FRM_MIN = Frame Min length
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_frm_min
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_frm_min_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t len                          : 16; /**< Byte count for Min-sized frame check
+                                                         AGL_GMX_RXn_FRM_CHK[MINERR] enables the check
+                                                         for port n.
+                                                         If enabled, failing packets set the MINERR
+                                                         interrupt and the MIX opcode is set to UNDER_FCS
+                                                         (0x6, if packet has bad FCS) or UNDER_ERR (0x8,
+                                                         if packet has good FCS). */
+#else
+	uint64_t len                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn52xx;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn52xxp1;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn56xx;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_frm_min_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;
+
+/**
+ * cvmx_agl_gmx_rx#_ifg
+ *
+ * AGL_GMX_RX_IFG = RX Min IFG
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_ifg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_ifg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ifg                          : 4;  /**< Min IFG (in IFG*8 bits) between packets used to
+                                                         determine IFGERR. Normally IFG is 96 bits.
+                                                         Note in some operating modes, IFG cycles can be
+                                                         inserted or removed in order to achieve clock rate
+                                                         adaptation. For these reasons, the default value
+                                                         is slightly conservative and does not check upto
+                                                         the full 96 bits of IFG. */
+#else
+	uint64_t ifg                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn52xx;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn52xxp1;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn56xx;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn56xxp1;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn63xx;
+	struct cvmx_agl_gmx_rxx_ifg_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;
+
+/**
+ * cvmx_agl_gmx_rx#_int_en
+ *
+ * AGL_GMX_RX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_int_en
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex             |             NS */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed              |             NS */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus             |             NS */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< Packet reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble)              |             NS */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_int_en_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< MII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
+	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
+	struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn63xx;
+	struct cvmx_agl_gmx_rxx_int_en_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
+
+/**
+ * cvmx_agl_gmx_rx#_int_reg
+ *
+ * AGL_GMX_RX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * (1) exceptions will only be raised to the control processor if the
+ *     corresponding bit in the AGL_GMX_RX_INT_EN register is set.
+ *
+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received
+ *     packet's workQ entry.  The AGL_GMX_RX_FRM_CHK register provides a bit mask
+ *     for configuring which conditions set the error.
+ *
+ * (3) in half duplex operation, the expectation is that collisions will appear
+ *     as MINERRs.
+ *
+ * (4) JABBER - An RX Jabber error indicates that a packet was received which
+ *              is longer than the maximum allowed packet as defined by the
+ *              system.  GMX will truncate the packet at the JABBER count.
+ *              Failure to do so could lead to system instabilty.
+ *
+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
+ *              AGL_GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
+ *              > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
+ *
+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN.
+ *
+ * (8) ALNERR - Indicates that the packet received was not an integer number of
+ *              bytes.  If FCS checking is enabled, ALNERR will only assert if
+ *              the FCS is bad.  If FCS checking is disabled, ALNERR will
+ *              assert in all non-integer frame cases.
+ *
+ * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
+ *                  is assumed by the receiver when the received
+ *                  frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR
+ *
+ * (A) LENERR - Length errors occur when the received packet does not match the
+ *              length field.  LENERR is only checked for packets between 64
+ *              and 1500 bytes.  For untagged frames, the length must exact
+ *              match.  For tagged frames the length or length+4 must match.
+ *
+ * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
+ *              Does not check the number of PREAMBLE cycles.
+ *
+ * (C) OVRERR - Not to be included in the HRM
+ *
+ *              OVRERR is an architectural assertion check internal to GMX to
+ *              make sure no assumption was violated.  In a correctly operating
+ *              system, this interrupt can never fire.
+ *
+ *              GMX has an internal arbiter which selects which of 4 ports to
+ *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
+ *              then each port will typically push a tick every 8 cycles - if
+ *              the packet interface is going as fast as possible.  If there
+ *              are four ports, they push every two cycles.  So that's the
+ *              assumption.  That the inbound module will always be able to
+ *              consume the tick before another is produced.  If that doesn't
+ *              happen - that's when OVRERR will assert.
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RGMII inbound LinkDuplex             |             NS */
+	uint64_t phy_spd                      : 1;  /**< Change in the RGMII inbound LinkSpeed              |             NS */
+	uint64_t phy_link                     : 1;  /**< Change in the RGMII inbound LinkStatus             |             NS */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< Packet reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble)              |             NS */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Packet Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< MII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with MII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
+	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
+	struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_int_reg_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;
+
+/**
+ * cvmx_agl_gmx_rx#_jabber
+ *
+ * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate
+ *
+ *
+ * Notes:
+ * CNT must be 8-byte aligned such that CNT[2:0] == 0
+ *
+ *   The packet that will be sent to the packet input logic will have an
+ *   additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and
+ *   AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
+ *   defined as...
+ *
+ *        max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8)
+ *
+ *   Be sure the CNT field value is at least as large as the
+ *   AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause
+ *   packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected
+ *   because they exceed the CNT limit.
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_jabber
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_jabber_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Byte count for jabber check
+                                                         Failing packets set the JABBER interrupt and are
+                                                         optionally sent with opcode==JABBER
+                                                         GMX will truncate the packet to CNT bytes
+                                                         CNT >= AGL_GMX_RX_FRM_MAX[LEN] */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn52xx;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn52xxp1;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn56xx;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn56xxp1;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn63xx;
+	struct cvmx_agl_gmx_rxx_jabber_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;
+
+/**
+ * cvmx_agl_gmx_rx#_pause_drop_time
+ *
+ * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_pause_drop_time
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t status                       : 16; /**< Time extracted from the dropped PAUSE packet */
+#else
+	uint64_t status                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
+	struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t;
+
+/**
+ * cvmx_agl_gmx_rx#_rx_inbnd
+ *
+ * AGL_GMX_RX_INBND = RGMII InBand Link Status
+ *
+ *
+ * Notes:
+ * These fields are only valid if the attached PHY is operating in RGMII mode
+ * and supports the optional in-band status (see section 3.4.1 of the RGMII
+ * specification, version 1.3 for more information).
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_rx_inbnd
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t duplex                       : 1;  /**< RGMII Inbound LinkDuplex                           |             NS
+                                                         0=half-duplex
+                                                         1=full-duplex */
+	uint64_t speed                        : 2;  /**< RGMII Inbound LinkSpeed                            |             NS
+                                                         00=2.5MHz
+                                                         01=25MHz
+                                                         10=125MHz
+                                                         11=Reserved */
+	uint64_t status                       : 1;  /**< RGMII Inbound LinkStatus                           |             NS
+                                                         0=down
+                                                         1=up */
+#else
+	uint64_t status                       : 1;
+	uint64_t speed                        : 2;
+	uint64_t duplex                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn63xx;
+	struct cvmx_agl_gmx_rxx_rx_inbnd_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_ctl
+ *
+ * AGL_GMX_RX_STATS_CTL = RX Stats Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rxx_stats_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rd_clr                       : 1;  /**< RX Stats registers will clear on reads */
+#else
+	uint64_t rd_clr                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_ctl_s   cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_octs
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_octs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of received good packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_ctl
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_octs_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of received pause packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_dmac
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_octs_dmac
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of filtered dmac packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_drp
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_octs_drp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of dropped packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts
+ *
+ * AGL_GMX_RX_STATS_PKTS
+ *
+ * Count of good received packets - packets that are not recognized as PAUSE
+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or
+ * have any other OPCODE (FCS, Length, etc).
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_pkts
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of received good packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_bad
+ *
+ * AGL_GMX_RX_STATS_PKTS_BAD
+ *
+ * Count of all packets received with some error that were not dropped
+ * either due to the dmac filter or lack of room in the receive FIFO.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_pkts_bad
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of bad packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_ctl
+ *
+ * AGL_GMX_RX_STATS_PKTS_CTL
+ *
+ * Count of all packets received that were recognized as Flow Control or
+ * PAUSE packets.  PAUSE packets with any kind of error are counted in
+ * AGL_GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
+ * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
+ * increments regardless of whether the packet is dropped.  Pause packets
+ * will never be counted in AGL_GMX_RX_STATS_PKTS.  Packets dropped due the dmac
+ * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_pkts_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of received pause packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_dmac
+ *
+ * AGL_GMX_RX_STATS_PKTS_DMAC
+ *
+ * Count of all packets received that were dropped by the dmac filter.
+ * Packets that match the DMAC will be dropped and counted here regardless
+ * of if they were bad packets.  These packets will never be counted in
+ * AGL_GMX_RX_STATS_PKTS.
+ *
+ * Some packets that were not able to satisify the DECISION_CNT may not
+ * actually be dropped by Octeon, but they will be counted here as if they
+ * were dropped.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_pkts_dmac
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of filtered dmac packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_drp
+ *
+ * AGL_GMX_RX_STATS_PKTS_DRP
+ *
+ * Count of all packets received that were dropped due to a full receive
+ * FIFO.  This counts good and bad packets received - all packets dropped by
+ * the FIFO.  It does not count packets dropped by the dmac or pause packet
+ * filters.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_stats_pkts_drp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of dropped packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
+	struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;
+
+/**
+ * cvmx_agl_gmx_rx#_udd_skp
+ *
+ * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
+ *
+ *
+ * Notes:
+ * (1) The skip bytes are part of the packet and will be sent down the NCB
+ *     packet interface and will be handled by PKI.
+ *
+ * (2) The system can determine if the UDD bytes are included in the FCS check
+ *     by using the FCSSEL field - if the FCS check is enabled.
+ *
+ * (3) Assume that the preamble/sfd is always at the start of the frame - even
+ *     before UDD bytes.  In most cases, there will be no preamble in these
+ *     cases since it will be MII to MII communication without a PHY
+ *     involved.
+ *
+ * (4) We can still do address filtering and control packet filtering is the
+ *     user desires.
+ *
+ * (5) UDD_SKP must be 0 in half-duplex operation unless
+ *     AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear.  If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set,
+ *     then UDD_SKP will normally be 8.
+ *
+ * (6) In all cases, the UDD bytes will be sent down the packet interface as
+ *     part of the packet.  The UDD bytes are never stripped from the actual
+ *     packet.
+ *
+ * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rxx_udd_skp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rxx_udd_skp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t fcssel                       : 1;  /**< Include the skip bytes in the FCS calculation
+                                                         0 = all skip bytes are included in FCS
+                                                         1 = the skip bytes are not included in FCS */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t len                          : 7;  /**< Amount of User-defined data before the start of
+                                                         the L2 data.  Zero means L2 comes first.
+                                                         Max value is 64. */
+#else
+	uint64_t len                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t fcssel                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn52xx;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn52xxp1;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn56xx;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn56xxp1;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn63xx;
+	struct cvmx_agl_gmx_rxx_udd_skp_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;
+
+/**
+ * cvmx_agl_gmx_rx_bp_drop#
+ *
+ * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rx_bp_dropx
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rx_bp_dropx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mark                         : 6;  /**< Number of 8B ticks to reserve in the RX FIFO.
+                                                         When the FIFO exceeds this count, packets will
+                                                         be dropped and not buffered.
+                                                         MARK should typically be programmed to 2.
+                                                         Failure to program correctly can lead to system
+                                                         instability. */
+#else
+	uint64_t mark                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn52xx;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn52xxp1;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn56xx;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn63xx;
+	struct cvmx_agl_gmx_rx_bp_dropx_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;
+
+/**
+ * cvmx_agl_gmx_rx_bp_off#
+ *
+ * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rx_bp_offx
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rx_bp_offx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mark                         : 6;  /**< Water mark (8B ticks) to deassert backpressure */
+#else
+	uint64_t mark                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn52xx;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn52xxp1;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn56xx;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn63xx;
+	struct cvmx_agl_gmx_rx_bp_offx_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;
+
+/**
+ * cvmx_agl_gmx_rx_bp_on#
+ *
+ * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_rx_bp_onx
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rx_bp_onx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t mark                         : 9;  /**< Hiwater mark (8B ticks) for backpressure. */
+#else
+	uint64_t mark                         : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn52xx;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn52xxp1;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn56xx;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn56xxp1;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn63xx;
+	struct cvmx_agl_gmx_rx_bp_onx_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;
+
+/**
+ * cvmx_agl_gmx_rx_prt_info
+ *
+ * AGL_GMX_RX_PRT_INFO = state information for the ports
+ *
+ *
+ * Notes:
+ * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rx_prt_info
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rx_prt_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t drop                         : 2;  /**< Port indication that data was dropped */
+	uint64_t reserved_2_15                : 14;
+	uint64_t commit                       : 2;  /**< Port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 2;
+	uint64_t reserved_2_15                : 14;
+	uint64_t drop                         : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn52xx;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn52xxp1;
+	struct cvmx_agl_gmx_rx_prt_info_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t drop                         : 1;  /**< Port indication that data was dropped */
+	uint64_t reserved_1_15                : 15;
+	uint64_t commit                       : 1;  /**< Port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 1;
+	uint64_t reserved_1_15                : 15;
+	uint64_t drop                         : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn63xx;
+	struct cvmx_agl_gmx_rx_prt_info_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;
+
+/**
+ * cvmx_agl_gmx_rx_tx_status
+ *
+ * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status
+ *
+ *
+ * Notes:
+ * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_rx_tx_status
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_rx_tx_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t tx                           : 2;  /**< Transmit data since last read */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t rx                           : 2;  /**< Receive data since last read */
+#else
+	uint64_t rx                           : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t tx                           : 2;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn52xx;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn52xxp1;
+	struct cvmx_agl_gmx_rx_tx_status_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t tx                           : 1;  /**< Transmit data since last read */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t rx                           : 1;  /**< Receive data since last read */
+#else
+	uint64_t rx                           : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t tx                           : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn63xx;
+	struct cvmx_agl_gmx_rx_tx_status_s    cn63xxp1;
+};
+typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;
+
+/**
+ * cvmx_agl_gmx_smac#
+ *
+ * AGL_GMX_SMAC = Packet SMAC
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_smacx
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_smacx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t smac                         : 48; /**< The SMAC field is used for generating and
+                                                         accepting Control Pause packets */
+#else
+	uint64_t smac                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_smacx_s           cn52xx;
+	struct cvmx_agl_gmx_smacx_s           cn52xxp1;
+	struct cvmx_agl_gmx_smacx_s           cn56xx;
+	struct cvmx_agl_gmx_smacx_s           cn56xxp1;
+	struct cvmx_agl_gmx_smacx_s           cn63xx;
+	struct cvmx_agl_gmx_smacx_s           cn63xxp1;
+};
+typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;
+
+/**
+ * cvmx_agl_gmx_stat_bp
+ *
+ * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_stat_bp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_stat_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t bp                           : 1;  /**< Current BP state */
+	uint64_t cnt                          : 16; /**< Number of cycles that BP has been asserted
+                                                         Saturating counter */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t bp                           : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_agl_gmx_stat_bp_s         cn52xx;
+	struct cvmx_agl_gmx_stat_bp_s         cn52xxp1;
+	struct cvmx_agl_gmx_stat_bp_s         cn56xx;
+	struct cvmx_agl_gmx_stat_bp_s         cn56xxp1;
+	struct cvmx_agl_gmx_stat_bp_s         cn63xx;
+	struct cvmx_agl_gmx_stat_bp_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;
+
+/**
+ * cvmx_agl_gmx_tx#_append
+ *
+ * AGL_GMX_TX_APPEND = Packet TX Append Control
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_append
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_append_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t force_fcs                    : 1;  /**< Append the Ethernet FCS on each pause packet
+                                                         when FCS is clear.  Pause packets are normally
+                                                         padded to 60 bytes.  If
+                                                         AGL_GMX_TX_MIN_PKT[MIN_SIZE] exceeds 59, then
+                                                         FORCE_FCS will not be used. */
+	uint64_t fcs                          : 1;  /**< Append the Ethernet FCS on each packet */
+	uint64_t pad                          : 1;  /**< Append PAD bytes such that min sized */
+	uint64_t preamble                     : 1;  /**< Prepend the Ethernet preamble on each transfer */
+#else
+	uint64_t preamble                     : 1;
+	uint64_t pad                          : 1;
+	uint64_t fcs                          : 1;
+	uint64_t force_fcs                    : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_append_s      cn52xx;
+	struct cvmx_agl_gmx_txx_append_s      cn52xxp1;
+	struct cvmx_agl_gmx_txx_append_s      cn56xx;
+	struct cvmx_agl_gmx_txx_append_s      cn56xxp1;
+	struct cvmx_agl_gmx_txx_append_s      cn63xx;
+	struct cvmx_agl_gmx_txx_append_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;
+
+/**
+ * cvmx_agl_gmx_tx#_clk
+ *
+ * AGL_GMX_TX_CLK = RGMII TX Clock Generation Register
+ *
+ *
+ * Notes:
+ * Normal Programming Values:
+ *  (1) RGMII, 1000Mbs   (AGL_GMX_PRT_CFG[SPEED]==1), CLK_CNT == 1
+ *  (2) RGMII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 50/5
+ *  (3) MII,   10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 1
+ *
+ * RGMII Example:
+ *  Given a 125MHz PLL reference clock...
+ *   CLK_CNT ==  1 ==> 125.0MHz TXC clock period (8ns* 1)
+ *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)
+ *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_clk
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_clk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t clk_cnt                      : 6;  /**< Controls the RGMII TXC frequency                   |             NS
+                                                         TXC(period) =
+                                                          rgm_ref_clk(period)*CLK_CNT */
+#else
+	uint64_t clk_cnt                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_clk_s         cn63xx;
+	struct cvmx_agl_gmx_txx_clk_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;
+
+/**
+ * cvmx_agl_gmx_tx#_ctl
+ *
+ * AGL_GMX_TX_CTL = TX Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t xsdef_en                     : 1;  /**< Enables the excessive deferral check for stats
+                                                         and interrupts */
+	uint64_t xscol_en                     : 1;  /**< Enables the excessive collision check for stats
+                                                         and interrupts */
+#else
+	uint64_t xscol_en                     : 1;
+	uint64_t xsdef_en                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_ctl_s         cn52xx;
+	struct cvmx_agl_gmx_txx_ctl_s         cn52xxp1;
+	struct cvmx_agl_gmx_txx_ctl_s         cn56xx;
+	struct cvmx_agl_gmx_txx_ctl_s         cn56xxp1;
+	struct cvmx_agl_gmx_txx_ctl_s         cn63xx;
+	struct cvmx_agl_gmx_txx_ctl_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;
+
+/**
+ * cvmx_agl_gmx_tx#_min_pkt
+ *
+ * AGL_GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_min_pkt
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_min_pkt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t min_size                     : 8;  /**< Min frame in bytes before the FCS is applied
+                                                         Padding is only appened when
+                                                         AGL_GMX_TX_APPEND[PAD] for the coresponding packet
+                                                         port is set. Packets will be padded to
+                                                         MIN_SIZE+1 The reset value will pad to 60 bytes. */
+#else
+	uint64_t min_size                     : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn52xx;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn52xxp1;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn56xx;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn56xxp1;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn63xx;
+	struct cvmx_agl_gmx_txx_min_pkt_s     cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;
+
+/**
+ * cvmx_agl_gmx_tx#_pause_pkt_interval
+ *
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent
+ *
+ *
+ * Notes:
+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ *
+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ *
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ *
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_pause_pkt_interval
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t interval                     : 16; /**< Arbitrate for a pause packet every (INTERVAL*512)
+                                                         bit-times.
+                                                         Normally, 0 < INTERVAL < AGL_GMX_TX_PAUSE_PKT_TIME
+                                                         INTERVAL=0, will only send a single PAUSE packet
+                                                         for each backpressure event */
+#else
+	uint64_t interval                     : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t;
+
+/**
+ * cvmx_agl_gmx_tx#_pause_pkt_time
+ *
+ * AGL_GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field
+ *
+ *
+ * Notes:
+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ *
+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ *
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ *
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ *
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_pause_pkt_time
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< The pause_time field placed is outbnd pause pkts
+                                                         pause_time is in 512 bit-times
+                                                         Normally, TIME > AGL_GMX_TX_PAUSE_PKT_INTERVAL */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
+	struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;
+
+/**
+ * cvmx_agl_gmx_tx#_pause_togo
+ *
+ * AGL_GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_pause_togo
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_pause_togo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< Amount of time remaining to backpressure */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn52xx;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn52xxp1;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn56xx;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn63xx;
+	struct cvmx_agl_gmx_txx_pause_togo_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;
+
+/**
+ * cvmx_agl_gmx_tx#_pause_zero
+ *
+ * AGL_GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_pause_zero
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_pause_zero_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t send                         : 1;  /**< When backpressure condition clear, send PAUSE
+                                                         packet with pause_time of zero to enable the
+                                                         channel */
+#else
+	uint64_t send                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn52xx;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn52xxp1;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn56xx;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn63xx;
+	struct cvmx_agl_gmx_txx_pause_zero_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;
+
+/**
+ * cvmx_agl_gmx_tx#_soft_pause
+ *
+ * AGL_GMX_TX_SOFT_PAUSE = Packet TX Software Pause
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_soft_pause
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_soft_pause_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< Back off the TX bus for (TIME*512) bit-times
+                                                         for full-duplex operation only */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn52xx;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn52xxp1;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn56xx;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn56xxp1;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn63xx;
+	struct cvmx_agl_gmx_txx_soft_pause_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat0
+ *
+ * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat0
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t xsdef                        : 32; /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive deferal */
+	uint64_t xscol                        : 32; /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive collision.  Defined by
+                                                         AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+	uint64_t xscol                        : 32;
+	uint64_t xsdef                        : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat0_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat0_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat0_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat0_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat0_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat0_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat1
+ *
+ * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL  / AGL_GMX_TX_STATS_MCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat1
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t scol                         : 32; /**< Number of packets sent with a single collision */
+	uint64_t mcol                         : 32; /**< Number of packets sent with multiple collisions
+                                                         but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+	uint64_t mcol                         : 32;
+	uint64_t scol                         : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat1_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat1_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat1_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat1_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat1_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat1_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat2
+ *
+ * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS
+ *
+ *
+ * Notes:
+ * - Octect counts are the sum of all data transmitted on the wire including
+ *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
+ *   counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat2
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Number of total octets sent on the interface.
+                                                         Does not count octets from frames that were
+                                                         truncated due to collisions in halfdup mode. */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat2_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat2_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat2_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat2_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat2_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat2_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat3
+ *
+ * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat3
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pkts                         : 32; /**< Number of total frames sent on the interface.
+                                                         Does not count frames that were truncated due to
+                                                          collisions in halfdup mode. */
+#else
+	uint64_t pkts                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat3_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat3_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat3_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat3_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat3_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat3_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat4
+ *
+ * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat4
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist1                        : 32; /**< Number of packets sent with an octet count of 64. */
+	uint64_t hist0                        : 32; /**< Number of packets sent with an octet count
+                                                         of < 64. */
+#else
+	uint64_t hist0                        : 32;
+	uint64_t hist1                        : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat4_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat4_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat4_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat4_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat4_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat4_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat5
+ *
+ * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat5
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist3                        : 32; /**< Number of packets sent with an octet count of
+                                                         128 - 255. */
+	uint64_t hist2                        : 32; /**< Number of packets sent with an octet count of
+                                                         65 - 127. */
+#else
+	uint64_t hist2                        : 32;
+	uint64_t hist3                        : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat5_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat5_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat5_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat5_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat5_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat5_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat6
+ *
+ * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat6
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist5                        : 32; /**< Number of packets sent with an octet count of
+                                                         512 - 1023. */
+	uint64_t hist4                        : 32; /**< Number of packets sent with an octet count of
+                                                         256 - 511. */
+#else
+	uint64_t hist4                        : 32;
+	uint64_t hist5                        : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat6_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat6_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat6_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat6_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat6_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat6_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat7
+ *
+ * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat7
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist7                        : 32; /**< Number of packets sent with an octet count
+                                                         of > 1518. */
+	uint64_t hist6                        : 32; /**< Number of packets sent with an octet count of
+                                                         1024 - 1518. */
+#else
+	uint64_t hist6                        : 32;
+	uint64_t hist7                        : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat7_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat7_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat7_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat7_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat7_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat7_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat8
+ *
+ * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST  / AGL_GMX_TX_STATS_BCST
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
+ *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
+ *   as per the 802.3 frame definition.  If the system requires additional data
+ *   before the L2 header, then the MCST and BCST counters may not reflect
+ *   reality and should be ignored by software.
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat8
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat8_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mcst                         : 32; /**< Number of packets sent to multicast DMAC.
+                                                         Does not include BCST packets. */
+	uint64_t bcst                         : 32; /**< Number of packets sent to broadcast DMAC.
+                                                         Does not include MCST packets. */
+#else
+	uint64_t bcst                         : 32;
+	uint64_t mcst                         : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat8_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat8_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat8_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat8_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat8_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat8_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stat9
+ *
+ * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_txx_stat9
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stat9_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t undflw                       : 32; /**< Number of underflow packets */
+	uint64_t ctl                          : 32; /**< Number of Control packets (PAUSE flow control)
+                                                         generated by GMX.  It does not include control
+                                                         packets forwarded or generated by the PP's. */
+#else
+	uint64_t ctl                          : 32;
+	uint64_t undflw                       : 32;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stat9_s       cn52xx;
+	struct cvmx_agl_gmx_txx_stat9_s       cn52xxp1;
+	struct cvmx_agl_gmx_txx_stat9_s       cn56xx;
+	struct cvmx_agl_gmx_txx_stat9_s       cn56xxp1;
+	struct cvmx_agl_gmx_txx_stat9_s       cn63xx;
+	struct cvmx_agl_gmx_txx_stat9_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;
+
+/**
+ * cvmx_agl_gmx_tx#_stats_ctl
+ *
+ * AGL_GMX_TX_STATS_CTL = TX Stats Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_stats_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_stats_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rd_clr                       : 1;  /**< Stats registers will clear on reads */
+#else
+	uint64_t rd_clr                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn52xx;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn52xxp1;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn56xx;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn56xxp1;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn63xx;
+	struct cvmx_agl_gmx_txx_stats_ctl_s   cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;
+
+/**
+ * cvmx_agl_gmx_tx#_thresh
+ *
+ * AGL_GMX_TX_THRESH = Packet TX Threshold
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+union cvmx_agl_gmx_txx_thresh
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_txx_thresh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t cnt                          : 6;  /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the packet interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the packet interface and must never
+                                                         be set below 4.  This register cannot exceed the
+                                                         the TX FIFO depth which is 128, 8B entries. */
+#else
+	uint64_t cnt                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_agl_gmx_txx_thresh_s      cn52xx;
+	struct cvmx_agl_gmx_txx_thresh_s      cn52xxp1;
+	struct cvmx_agl_gmx_txx_thresh_s      cn56xx;
+	struct cvmx_agl_gmx_txx_thresh_s      cn56xxp1;
+	struct cvmx_agl_gmx_txx_thresh_s      cn63xx;
+	struct cvmx_agl_gmx_txx_thresh_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;
+
+/**
+ * cvmx_agl_gmx_tx_bp
+ *
+ * AGL_GMX_TX_BP = Packet TX BackPressure Register
+ *
+ *
+ * Notes:
+ * BP[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * BP[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_tx_bp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t bp                           : 2;  /**< Port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+	uint64_t bp                           : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_bp_s           cn52xx;
+	struct cvmx_agl_gmx_tx_bp_s           cn52xxp1;
+	struct cvmx_agl_gmx_tx_bp_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t bp                           : 1;  /**< Port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+	uint64_t bp                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_tx_bp_cn56xx      cn56xxp1;
+	struct cvmx_agl_gmx_tx_bp_s           cn63xx;
+	struct cvmx_agl_gmx_tx_bp_s           cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;
+
+/**
+ * cvmx_agl_gmx_tx_col_attempt
+ *
+ * AGL_GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_tx_col_attempt
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_col_attempt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t limit                        : 5;  /**< Collision Attempts */
+#else
+	uint64_t limit                        : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn52xx;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn52xxp1;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn56xx;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn56xxp1;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn63xx;
+	struct cvmx_agl_gmx_tx_col_attempt_s  cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;
+
+/**
+ * cvmx_agl_gmx_tx_ifg
+ *
+ * Common
+ *
+ *
+ * AGL_GMX_TX_IFG = Packet TX Interframe Gap
+ *
+ * Notes:
+ * Notes:
+ * * Programming IFG1 and IFG2.
+ *
+ *   For half-duplex systems that require IEEE 802.3 compatibility, IFG1 must
+ *   be in the range of 1-8, IFG2 must be in the range of 4-12, and the
+ *   IFG1+IFG2 sum must be 12.
+ *
+ *   For full-duplex systems that require IEEE 802.3 compatibility, IFG1 must
+ *   be in the range of 1-11, IFG2 must be in the range of 1-11, and the
+ *   IFG1+IFG2 sum must be 12.
+ *
+ *   For all other systems, IFG1 and IFG2 can be any value in the range of
+ *   1-15.  Allowing for a total possible IFG sum of 2-30.
+ *
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+union cvmx_agl_gmx_tx_ifg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_ifg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ifg2                         : 4;  /**< 1/3 of the interframe gap timing
+                                                         If CRS is detected during IFG2, then the
+                                                         interFrameSpacing timer is not reset and a frame
+                                                         is transmited once the timer expires. */
+	uint64_t ifg1                         : 4;  /**< 2/3 of the interframe gap timing
+                                                         If CRS is detected during IFG1, then the
+                                                         interFrameSpacing timer is reset and a frame is
+                                                         not transmited. */
+#else
+	uint64_t ifg1                         : 4;
+	uint64_t ifg2                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_ifg_s          cn52xx;
+	struct cvmx_agl_gmx_tx_ifg_s          cn52xxp1;
+	struct cvmx_agl_gmx_tx_ifg_s          cn56xx;
+	struct cvmx_agl_gmx_tx_ifg_s          cn56xxp1;
+	struct cvmx_agl_gmx_tx_ifg_s          cn63xx;
+	struct cvmx_agl_gmx_tx_ifg_s          cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;
+
+/**
+ * cvmx_agl_gmx_tx_int_en
+ *
+ * AGL_GMX_TX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+union cvmx_agl_gmx_tx_int_en
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t reserved_18_19               : 2;
+	uint64_t late_col                     : 2;  /**< TX Late Collision */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral (halfdup mode only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions (halfdup mode only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_19               : 2;
+	uint64_t ptp_lost                     : 2;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_int_en_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t late_col                     : 2;  /**< TX Late Collision */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral (MII/halfdup mode only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions (MII/halfdup mode only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow (MII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_tx_int_en_cn52xx  cn52xxp1;
+	struct cvmx_agl_gmx_tx_int_en_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t late_col                     : 1;  /**< TX Late Collision */
+	uint64_t reserved_13_15               : 3;
+	uint64_t xsdef                        : 1;  /**< TX Excessive deferral (MII/halfdup mode only) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t xscol                        : 1;  /**< TX Excessive collisions (MII/halfdup mode only) */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t undflw                       : 1;  /**< TX Underflow (MII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t xscol                        : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t xsdef                        : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t late_col                     : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_tx_int_en_cn56xx  cn56xxp1;
+	struct cvmx_agl_gmx_tx_int_en_s       cn63xx;
+	struct cvmx_agl_gmx_tx_int_en_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;
+
+/**
+ * cvmx_agl_gmx_tx_int_reg
+ *
+ * AGL_GMX_TX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+union cvmx_agl_gmx_tx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t ptp_lost                     : 2;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t reserved_18_19               : 2;
+	uint64_t late_col                     : 2;  /**< TX Late Collision */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral (halfdup mode only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions (halfdup mode only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_19               : 2;
+	uint64_t ptp_lost                     : 2;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t late_col                     : 2;  /**< TX Late Collision */
+	uint64_t reserved_14_15               : 2;
+	uint64_t xsdef                        : 2;  /**< TX Excessive deferral (MII/halfdup mode only) */
+	uint64_t reserved_10_11               : 2;
+	uint64_t xscol                        : 2;  /**< TX Excessive collisions (MII/halfdup mode only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t undflw                       : 2;  /**< TX Underflow (MII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 2;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t xscol                        : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t xsdef                        : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t late_col                     : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn52xx;
+	struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
+	struct cvmx_agl_gmx_tx_int_reg_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t late_col                     : 1;  /**< TX Late Collision */
+	uint64_t reserved_13_15               : 3;
+	uint64_t xsdef                        : 1;  /**< TX Excessive deferral (MII/halfdup mode only) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t xscol                        : 1;  /**< TX Excessive collisions (MII/halfdup mode only) */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t undflw                       : 1;  /**< TX Underflow (MII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t xscol                        : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t xsdef                        : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t late_col                     : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn63xx;
+	struct cvmx_agl_gmx_tx_int_reg_s      cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;
+
+/**
+ * cvmx_agl_gmx_tx_jam
+ *
+ * AGL_GMX_TX_JAM = Packet TX Jam Pattern
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_tx_jam
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_jam_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t jam                          : 8;  /**< Jam pattern */
+#else
+	uint64_t jam                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_jam_s          cn52xx;
+	struct cvmx_agl_gmx_tx_jam_s          cn52xxp1;
+	struct cvmx_agl_gmx_tx_jam_s          cn56xx;
+	struct cvmx_agl_gmx_tx_jam_s          cn56xxp1;
+	struct cvmx_agl_gmx_tx_jam_s          cn63xx;
+	struct cvmx_agl_gmx_tx_jam_s          cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;
+
+/**
+ * cvmx_agl_gmx_tx_lfsr
+ *
+ * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_tx_lfsr
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_lfsr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t lfsr                         : 16; /**< The current state of the LFSR used to feed random
+                                                         numbers to compute truncated binary exponential
+                                                         backoff. */
+#else
+	uint64_t lfsr                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn52xx;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn52xxp1;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn56xx;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn56xxp1;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn63xx;
+	struct cvmx_agl_gmx_tx_lfsr_s         cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;
+
+/**
+ * cvmx_agl_gmx_tx_ovr_bp
+ *
+ * AGL_GMX_TX_OVR_BP = Packet TX Override BackPressure
+ *
+ *
+ * Notes:
+ * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_gmx_tx_ovr_bp
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_ovr_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t en                           : 2;  /**< Per port Enable back pressure override */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t bp                           : 2;  /**< Port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ign_full                     : 2;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t bp                           : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t en                           : 2;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn52xx;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn52xxp1;
+	struct cvmx_agl_gmx_tx_ovr_bp_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t en                           : 1;  /**< Per port Enable back pressure override */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t bp                           : 1;  /**< Port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t ign_full                     : 1;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t bp                           : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t en                           : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn56xx;
+	struct cvmx_agl_gmx_tx_ovr_bp_cn56xx  cn56xxp1;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn63xx;
+	struct cvmx_agl_gmx_tx_ovr_bp_s       cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;
+
+/**
+ * cvmx_agl_gmx_tx_pause_pkt_dmac
+ *
+ * AGL_GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_tx_pause_pkt_dmac
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t dmac                         : 48; /**< The DMAC field placed is outbnd pause pkts */
+#else
+	uint64_t dmac                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;
+
+/**
+ * cvmx_agl_gmx_tx_pause_pkt_type
+ *
+ * AGL_GMX_TX_PAUSE_PKT_TYPE = Packet TX Pause Packet TYPE field
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+union cvmx_agl_gmx_tx_pause_pkt_type
+{
+	uint64_t u64;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t type                         : 16; /**< The TYPE field placed is outbnd pause pkts */
+#else
+	uint64_t type                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
+	struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+};
+typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;
+
+/**
+ * cvmx_agl_prt#_ctl
+ *
+ * AGL_PRT_CTL = AGL Port Control
+ *
+ *
+ * Notes:
+ * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1.
+ * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+union cvmx_agl_prtx_ctl
+{
+	uint64_t u64;
+	struct cvmx_agl_prtx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t drv_byp                      : 1;  /**< Bypass the compensation controller and use
+                                                         DRV_NCTL and DRV_PCTL
+                                                         Note: the reset value was changed from pass1
+                                                         to pass2. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t cmp_pctl                     : 6;  /**< PCTL drive strength from the compensation ctl */
+	uint64_t reserved_54_55               : 2;
+	uint64_t cmp_nctl                     : 6;  /**< NCTL drive strength from the compensation ctl */
+	uint64_t reserved_46_47               : 2;
+	uint64_t drv_pctl                     : 6;  /**< PCTL drive strength to use in bypass mode
+                                                         Reset value of 19 is for 50 ohm termination */
+	uint64_t reserved_38_39               : 2;
+	uint64_t drv_nctl                     : 6;  /**< NCTL drive strength to use in bypass mode
+                                                         Reset value of 15 is for 50 ohm termination */
+	uint64_t reserved_29_31               : 3;
+	uint64_t clk_set                      : 5;  /**< The clock delay as determined by the DLL */
+	uint64_t clkrx_byp                    : 1;  /**< Bypass the RX clock delay setting
+                                                         Skews RXC from RXD,RXCTL in RGMII mode
+                                                         By default, HW internally shifts the RXC clock
+                                                         to sample RXD,RXCTL assuming clock and data and
+                                                         sourced synchronously from the link partner.
+                                                         In MII mode, the CLKRX_BYP is forced to 1. */
+	uint64_t reserved_21_22               : 2;
+	uint64_t clkrx_set                    : 5;  /**< RX clock delay setting to use in bypass mode
+                                                         Skews RXC from RXD in RGMII mode */
+	uint64_t clktx_byp                    : 1;  /**< Bypass the TX clock delay setting
+                                                         Skews TXC from TXD,TXCTL in RGMII mode
+                                                         Skews RXC from RXD,RXCTL in RGMII mode
+                                                         By default, clock and data and sourced
+                                                         synchronously.
+                                                         In MII mode, the CLKRX_BYP is forced to 1. */
+	uint64_t reserved_13_14               : 2;
+	uint64_t clktx_set                    : 5;  /**< TX clock delay setting to use in bypass mode
+                                                         Skews TXC from TXD in RGMII mode */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dllrst                       : 1;  /**< DLL Reset */
+	uint64_t comp                         : 1;  /**< Compensation Enable */
+	uint64_t enable                       : 1;  /**< Port Enable
+                                                         Note: the reset value was changed from pass1
+                                                         to pass2. */
+	uint64_t clkrst                       : 1;  /**< Clock Tree Reset */
+	uint64_t mode                         : 1;  /**< Port Mode
+                                                         MODE must be set the same for all ports in which
+                                                         AGL_PRTx_CTL[ENABLE] is set.
+                                                         0=RGMII
+                                                         1=MII */
+#else
+	uint64_t mode                         : 1;
+	uint64_t clkrst                       : 1;
+	uint64_t enable                       : 1;
+	uint64_t comp                         : 1;
+	uint64_t dllrst                       : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t clktx_set                    : 5;
+	uint64_t reserved_13_14               : 2;
+	uint64_t clktx_byp                    : 1;
+	uint64_t clkrx_set                    : 5;
+	uint64_t reserved_21_22               : 2;
+	uint64_t clkrx_byp                    : 1;
+	uint64_t clk_set                      : 5;
+	uint64_t reserved_29_31               : 3;
+	uint64_t drv_nctl                     : 6;
+	uint64_t reserved_38_39               : 2;
+	uint64_t drv_pctl                     : 6;
+	uint64_t reserved_46_47               : 2;
+	uint64_t cmp_nctl                     : 6;
+	uint64_t reserved_54_55               : 2;
+	uint64_t cmp_pctl                     : 6;
+	uint64_t reserved_62_62               : 1;
+	uint64_t drv_byp                      : 1;
+#endif
+	} s;
+	struct cvmx_agl_prtx_ctl_s            cn63xx;
+	struct cvmx_agl_prtx_ctl_s            cn63xxp1;
+};
+typedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-app-hotplug.c b/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
new file mode 100644
index 0000000..6145134
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
@@ -0,0 +1,402 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Provides APIs for applications to register for hotplug. It also provides 
+ * APIs for requesting shutdown of a running target application. 
+ *
+ * <hr>$Revision: $<hr>
+ */
+
+#include "cvmx-app-hotplug.h"
+#include "cvmx-spinlock.h"
+
+//#define DEBUG 1
+
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+
+static CVMX_SHARED cvmx_spinlock_t cvmx_app_hotplug_sync_lock = { CVMX_SPINLOCK_UNLOCKED_VAL };
+static CVMX_SHARED cvmx_spinlock_t cvmx_app_hotplug_lock = { CVMX_SPINLOCK_UNLOCKED_VAL };
+static CVMX_SHARED cvmx_app_hotplug_info_t *cvmx_app_hotplug_info_ptr = NULL;
+
+static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32], void *user_arg);
+static void __cvmx_app_hotplug_sync(void);
+static void __cvmx_app_hotplug_reset(void);
+
+/**
+ * This routine registers an application for hotplug. It installs a handler for
+ * any incoming shutdown request. It also registers a callback routine from the
+ * application. This callback is invoked when the application receives a 
+ * shutdown notification. 
+ *
+ * This routine only needs to be called once per application. 
+ *
+ * @param fn      Callback routine from the application. 
+ * @param arg     Argument to the application callback routine. 
+ * @return        Return 0 on success, -1 on failure
+ *
+ */
+int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
+{
+    /* Find the list of applications launched by bootoct utility. */
+
+    if (!(cvmx_app_hotplug_info_ptr = cvmx_app_hotplug_get_info(cvmx_sysinfo_get()->core_mask)))
+    {
+        /* Application not launched by bootoct? */
+        printf("ERROR: cmvx_app_hotplug_register() failed\n");
+        return -1;
+    }
+
+    /* Register the callback */
+    cvmx_app_hotplug_info_ptr->data = CAST64(arg);
+    cvmx_app_hotplug_info_ptr->shutdown_callback = CAST64(fn);
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n", 
+                  cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid);
+#endif
+
+    cvmx_interrupt_register(CVMX_IRQ_MBOX0, __cvmx_app_hotplug_shutdown, NULL);
+
+    return 0;
+}
+
+/**
+ * Activate the current application core for receiving hotplug shutdown requests. 
+ *
+ * This routine makes sure that each core belonging to the application is enabled 
+ * to receive the shutdown notification and also provides a barrier sync to make
+ * sure that all cores are ready. 
+ */
+int cvmx_app_hotplug_activate(void)
+{
+    /* Make sure all application cores are activating */
+    __cvmx_app_hotplug_sync();
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+
+    if (!cvmx_app_hotplug_info_ptr)
+    {
+        cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
+        printf("ERROR: This application is not registered for hotplug\n");
+	return -1;
+    }
+
+    /* Enable the interrupt before we mark the core as activated */
+    cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+
+    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1<<cvmx_get_core_num());
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n", 
+                 cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid, 
+                 sizeof(*cvmx_app_hotplug_info_ptr));
+#endif
+
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
+
+    return 0;
+}
+
+/**
+ * This routine is only required if cvmx_app_hotplug_shutdown_request() was called
+ * with wait=0. This routine waits for the application shutdown to complete. 
+ *
+ * @param coremask     Coremask the application is running on. 
+ * @return             0 on success, -1 on error
+ *
+ */
+int cvmx_app_hotplug_shutdown_complete(uint32_t coremask)
+{
+    cvmx_app_hotplug_info_t *hotplug_info_ptr;
+
+    if (!(hotplug_info_ptr = cvmx_app_hotplug_get_info(coremask)))
+    {
+        printf("\nERROR: Failed to get hotplug info for coremask: 0x%x\n", (unsigned int)coremask);
+        return -1;
+    }
+
+    while(!hotplug_info_ptr->shutdown_done);
+
+    /* Clean up the hotplug info region for this app */
+    bzero(hotplug_info_ptr, sizeof(*hotplug_info_ptr));
+
+    return 0;
+}
+
+/**
+ * Disable recognition of any incoming shutdown request. 
+ */
+
+void cvmx_app_hotplug_shutdown_disable(void)
+{
+    cvmx_interrupt_mask_irq(CVMX_IRQ_MBOX0);
+}
+
+/**
+ * Re-enable recognition of incoming shutdown requests.
+ */
+
+void cvmx_app_hotplug_shutdown_enable(void)
+{
+    cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+}
+
+/*
+ * ISR for the incoming shutdown request interrupt. 
+ */
+static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+    uint32_t flags;
+
+    cvmx_interrupt_mask_irq(CVMX_IRQ_MBOX0);
+
+    /* Clear the interrupt */
+    cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 1);
+
+    /* Make sure the write above completes */
+    cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
+
+    if (!cvmx_app_hotplug_info_ptr)
+    {
+        printf("ERROR: Application is not registered for hotplug!\n");
+        return;
+    }
+
+    if (cvmx_app_hotplug_info_ptr->hotplug_activated_coremask != sys_info_ptr->core_mask)
+    {
+        printf("ERROR: Shutdown requested when not all app cores have activated hotplug\n"
+	       "Application coremask: 0x%x Hotplug coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask, 
+	       (unsigned int)cvmx_app_hotplug_info_ptr->hotplug_activated_coremask);
+	return;
+    }
+
+    /* Call the application's own callback function */
+    ((void(*)(void*))(long)cvmx_app_hotplug_info_ptr->shutdown_callback)(CASTPTR(void *, cvmx_app_hotplug_info_ptr->data));
+
+    __cvmx_app_hotplug_sync();
+
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    {
+        bzero(cvmx_app_hotplug_info_ptr, sizeof(*cvmx_app_hotplug_info_ptr));
+#ifdef DEBUG
+        cvmx_dprintf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
+#endif
+        cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+    }
+
+    flags = cvmx_interrupt_disable_save();
+
+    __cvmx_app_hotplug_sync();
+
+    /* Reset the core */
+    __cvmx_app_hotplug_reset();
+}
+
+/*
+ * Reset the core. We just jump back to the reset vector for now. 
+ */
+void __cvmx_app_hotplug_reset(void)
+{
+    /* Code from SecondaryCoreLoop from bootloader, sleep until we recieve
+       a NMI. */
+    __asm__ volatile (
+        ".set noreorder      \n"
+	"\tsync               \n"
+	"\tnop               \n"
+        "1:\twait            \n"
+        "\tb 1b              \n"
+	"\tnop               \n"             
+	".set reorder        \n"
+	:: 
+    );
+}
+
+/* 
+ * We need a separate sync operation from cvmx_coremask_barrier_sync() to
+ * avoid a deadlock on state.lock, since the application itself maybe doing a
+ * cvmx_coremask_barrier_sync(). 
+ */
+static void __cvmx_app_hotplug_sync(void)
+{
+    static CVMX_SHARED volatile uint32_t sync_coremask = 0;
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_sync_lock);
+    
+    sync_coremask |= cvmx_coremask_core(cvmx_get_core_num());
+
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
+
+    while (sync_coremask != sys_info_ptr->core_mask);
+}
+
+#endif /* CVMX_BUILD_FOR_LINUX_USER */
+
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
+ * application running on the given coremask. 
+ *
+ * @param coremask     Coremask of application. 
+ * @return             Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+{
+    const struct cvmx_bootmem_named_block_desc *block_desc;
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+    int i;
+
+    block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
+
+    if (!block_desc)
+    {
+        printf("ERROR: Hotplug info region is not setup\n");
+        return NULL;
+    }
+    else
+
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+    {
+        size_t pg_sz = sysconf(_SC_PAGESIZE), size;
+        off_t offset;
+        char *vaddr;
+        int fd;
+
+        if ((fd = open("/dev/mem", O_RDWR)) == -1) {
+            perror("open");
+            return NULL;
+        }
+
+        /*
+         * We need to mmap() this memory, since this was allocated from the 
+         * kernel bootup code and does not reside in the RESERVE32 region.
+         */
+        size = CVMX_APP_HOTPLUG_INFO_REGION_SIZE + pg_sz-1;
+        offset = block_desc->base_addr & ~(pg_sz-1);
+        if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED) 
+        {
+            perror("mmap");
+            return NULL;
+        }
+
+        hgp = (cvmx_app_hotplug_global_t *)(vaddr + ( block_desc->base_addr & (pg_sz-1)));
+    }
+#else
+    hgp = cvmx_phys_to_ptr(block_desc->base_addr);
+#endif
+
+    hip = hgp->hotplug_info_array;
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n", 
+                  block_desc->base_addr, hgp);
+#endif
+
+    /* Look for the current app's info */
+
+    for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
+    {
+        if (hip[i].coremask == coremask)
+	{
+#ifdef DEBUG
+	    cvmx_dprintf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", 
+	                 i, hip[i].coremask, hip[i].valid);
+#endif
+
+	    return &hip[i];
+	}
+    }
+
+    return NULL;
+}
+
+/**
+ * This routine sends a shutdown request to a running target application. 
+ *
+ * @param coremask     Coremask the application is running on. 
+ * @param wait         1 - Wait for shutdown completion
+ *                     0 - Do not wait
+ * @return             0 on success, -1 on error
+ *
+ */
+
+int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait) 
+{
+    int i;
+    cvmx_app_hotplug_info_t *hotplug_info_ptr;
+
+    if (!(hotplug_info_ptr = cvmx_app_hotplug_get_info(coremask)))
+    {
+        printf("\nERROR: Failed to get hotplug info for coremask: 0x%x\n", (unsigned int)coremask);
+        return -1;
+    }
+
+    if (!hotplug_info_ptr->shutdown_callback)
+    {
+        printf("\nERROR: Target application has not registered for hotplug!\n");
+        return -1;
+    }
+
+    if (hotplug_info_ptr->hotplug_activated_coremask != coremask)
+    {
+        printf("\nERROR: Not all application cores have activated hotplug\n");
+        return -1;
+    }
+
+    /* Send IPIs to all application cores to request shutdown */
+    for (i=0; i<CVMX_MAX_CORES; i++) {
+    	if (coremask & (1<<i))
+		cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
+    }
+
+    if (wait)
+    {
+        while (!hotplug_info_ptr->shutdown_done);    
+
+        /* Clean up the hotplug info region for this application */
+        bzero(hotplug_info_ptr, sizeof(*hotplug_info_ptr));
+    }
+
+    return 0;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-app-hotplug.h b/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
new file mode 100644
index 0000000..bfa62f8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
@@ -0,0 +1,103 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Header file for the hotplug APIs
+ *
+ * <hr>$Revision:  $<hr>
+ */
+
+#ifndef __CVMX_APP_HOTPLUG_H__
+#define __CVMX_APP_HOTPLUG_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#else
+#include "cvmx.h"
+#include "cvmx-coremask.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-bootmem.h"
+#endif
+
+#define CVMX_APP_HOTPLUG_MAX_APPS 32
+#define CVMX_APP_HOTPLUG_MAX_APPNAME_LEN 256
+
+typedef struct cvmx_app_hotplug_info
+{
+   char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
+   uint32_t coremask;
+   uint32_t volatile hotplug_activated_coremask;
+   int32_t  valid;
+   int32_t volatile shutdown_done;
+   uint64_t shutdown_callback;
+   uint64_t data;
+} cvmx_app_hotplug_info_t;
+
+struct cvmx_app_hotplug_global
+{
+   uint32_t avail_coremask;
+   cvmx_app_hotplug_info_t hotplug_info_array[CVMX_APP_HOTPLUG_MAX_APPS];
+};
+
+typedef struct cvmx_app_hotplug_global cvmx_app_hotplug_global_t;
+
+int cvmx_app_hotplug_shutdown_request(uint32_t, int);
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t);
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+int cvmx_app_hotplug_register(void(*)(void*), void*);
+int cvmx_app_hotplug_activate(void);
+void cvmx_app_hotplug_shutdown_disable(void);
+void cvmx_app_hotplug_shutdown_enable(void);
+#endif
+
+#define CVMX_APP_HOTPLUG_INFO_REGION_SIZE  sizeof(cvmx_app_hotplug_global_t)
+#define CVMX_APP_HOTPLUG_INFO_REGION_NAME  "cvmx-app-hotplug-block"
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_APP_HOTPLUG_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init-linux.c b/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
index ed83b50..73726df 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
+++ b/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  * Simple executive application initialization for Linux user space. This
@@ -59,7 +61,7 @@
  * -# Most hardware can only be initialized once. Unless you're very careful,
  *      this also means you Linux application can only run once.
  *
- * <hr>$Revision: 41757 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 #define _GNU_SOURCE
@@ -107,11 +109,6 @@ extern uint64_t linux_mem32_max;
 extern uint64_t linux_mem32_wired;
 extern uint64_t linux_mem32_offset;
 
-#define MIPS_CAVIUM_XKPHYS_READ	   2010	/* XKPHYS */
-#define MIPS_CAVIUM_XKPHYS_WRITE	   2011	/* XKPHYS */
-
-static CVMX_SHARED int32_t warn_count;
-
 /**
  * This function performs some default initialization of the Octeon executive.  It initializes
  * the cvmx_bootmem memory allocator with the list of physical memory shared by the bootloader.
@@ -134,17 +131,17 @@ int cvmx_user_app_init(void)
  * library printf for output. It also makes sure that two
  * calls to simprintf provide atomic output.
  *
- * @param fmt    Format string in the same format as printf.
+ * @param format  Format string in the same format as printf.
  */
-void simprintf(const char *fmt, ...)
+void simprintf(const char *format, ...)
 {
     CVMX_SHARED static cvmx_spinlock_t simprintf_lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER;
     va_list ap;
 
     cvmx_spinlock_lock(&simprintf_lock);
     printf("SIMPRINTF(%d): ", (int)cvmx_get_core_num());
-    va_start(ap, fmt);
-    vprintf(fmt, ap);
+    va_start(ap, format);
+    vprintf(format, ap);
     va_end(ap);
     cvmx_spinlock_unlock(&simprintf_lock);
 }
@@ -325,7 +322,10 @@ int main(int argc, const char *argv[])
     CVMX_SHARED static int32_t pending_fork;
     unsigned long cpumask;
     unsigned long cpu;
-    int lastcpu = 0;
+    int firstcpu = 0;
+    int firstcore = 0;
+
+    cvmx_linux_enable_xkphys_access(0);
 
     cvmx_sysinfo_linux_userspace_initialize();
 
@@ -344,7 +344,7 @@ int main(int argc, const char *argv[])
     }
 
     setup_cvmx_shared();
-    cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_ptr);
+    cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
 
     /* Check to make sure the Chip version matches the configured version */
     octeon_model_version_check(cvmx_get_proc_id());
@@ -359,37 +359,40 @@ int main(int argc, const char *argv[])
     cvmx_sysinfo_t *system_info = cvmx_sysinfo_get();
 
     cvmx_atomic_set32(&pending_fork, 1);
-    for (cpu=0; cpu<16; cpu++)
+
+    /* Get the lowest logical cpu */
+    firstcore = ffsl(cpumask) - 1;
+    cpumask ^= (1<<(firstcore));
+    while (1)
     {
-        if (cpumask & (1<<cpu))
+        if (cpumask == 0)
         {
-            /* Turn off the bit for this CPU number. We've counted him */
-            cpumask ^= (1<<cpu);
-            /* If this is the last CPU to run on, use this process instead of forking another one */
-            if (cpumask == 0)
-            {
-                lastcpu = 1;
-                break;
-            }
-            /* Increment the number of CPUs running this app */
-            cvmx_atomic_add32(&pending_fork, 1);
-            /* Flush all IO streams before the fork. Otherwise any buffered
-                data in the C library will be duplicated. This results in
-                duplicate output from a single print */
-            fflush(NULL);
-            /* Fork a process for the new CPU */
-            int pid = fork();
-            if (pid == 0)
-            {
-                break;
-            }
-            else if (pid == -1)
-            {
-                perror("Fork failed");
-                exit(errno);
-            }
+            cpu = firstcore;
+            firstcpu = 1;
+            break;
         }
-    }
+        cpu = ffsl(cpumask) - 1;
+        /* Turn off the bit for this CPU number. We've counted him */
+        cpumask ^= (1<<cpu);
+        /* Increment the number of CPUs running this app */
+         cvmx_atomic_add32(&pending_fork, 1);
+        /* Flush all IO streams before the fork. Otherwise any buffered
+           data in the C library will be duplicated. This results in
+           duplicate output from a single print */
+        fflush(NULL);
+        /* Fork a process for the new CPU */
+        int pid = fork();
+        if (pid == 0)
+        {
+            break;
+        }
+        else if (pid == -1)
+        {
+            perror("Fork failed");
+            exit(errno);
+        }
+     }
+
 
     /* Set affinity to lock me to the correct CPU */
     cpumask = (1<<cpu);
@@ -404,7 +407,7 @@ int main(int argc, const char *argv[])
     cvmx_atomic_add32(&pending_fork, -1);
     if (cvmx_atomic_get32(&pending_fork) == 0)
         cvmx_dprintf("Active coremask = 0x%x\n", system_info->core_mask);
-    if (lastcpu)
+    if (firstcpu)
         system_info->init_core = cvmx_get_core_num();
     cvmx_spinlock_unlock(&mask_lock);
 
@@ -413,27 +416,7 @@ int main(int argc, const char *argv[])
 
     cvmx_coremask_barrier_sync(system_info->core_mask);
 
-    int ret = sysmips(MIPS_CAVIUM_XKPHYS_WRITE, getpid(), 3, 0);
-    if (ret != 0) {
-	 int32_t w = cvmx_atomic_fetch_and_add32(&warn_count, 1);
-	 if (!w) {
-	      switch(errno) {
-	      case EINVAL:
-		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
-			  "  Did you configure your kernel with both:\n"
-			  "     CONFIG_CAVIUM_OCTEON_USER_MEM_PER_PROCESS *and*\n"
-			  "     CONFIG_CAVIUM_OCTEON_USER_IO_PER_PROCESS?");
-		   break;
-	      case EPERM:
-		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
-			  "  Are you running as root?");
-		   break;
-	      default:
-		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed");
-		   break;
-	      }
-	 }
-    }
+    cvmx_linux_enable_xkphys_access(1);
 
     int result = appmain(argc, argv);
 
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.c b/sys/contrib/octeon-sdk/cvmx-app-init.c
index 8769218..885e36e 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init.c
+++ b/sys/contrib/octeon-sdk/cvmx-app-init.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 #include <stdio.h>
 #include <stdint.h>
 #include <stdlib.h>
@@ -52,14 +54,15 @@
 #include "cvmx-sysinfo.h"
 #include "cvmx-bootmem.h"
 #include "cvmx-uart.h"
-#include "cvmx-ciu.h"
 #include "cvmx-coremask.h"
 #include "cvmx-core.h"
 #include "cvmx-interrupt.h"
 #include "cvmx-ebt3000.h"
+#include "cvmx-sim-magic.h"
+#include "cvmx-debug.h"
 #include "../../bootloader/u-boot/include/octeon_mem_map.h"
 
-int cvmx_debug_uart;
+int cvmx_debug_uart = -1;
 
 /**
  * @file
@@ -114,7 +117,7 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
         sys_info_ptr->stack_top = cvmx_bootinfo_ptr->stack_top;
         sys_info_ptr->stack_size = cvmx_bootinfo_ptr->stack_size;
         sys_info_ptr->init_core = cvmx_get_core_num();
-        sys_info_ptr->phy_mem_desc_ptr = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, cvmx_bootinfo_ptr->phy_mem_desc_addr));
+        sys_info_ptr->phy_mem_desc_addr = cvmx_bootinfo_ptr->phy_mem_desc_addr;
         sys_info_ptr->exception_base_addr = cvmx_bootinfo_ptr->exception_base_addr;
         sys_info_ptr->cpu_clock_hz  = cvmx_bootinfo_ptr->eclock_hz;
         sys_info_ptr->dram_data_rate_hz  = cvmx_bootinfo_ptr->dclock_hz * 2;
@@ -129,7 +132,7 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
         if (cvmx_bootinfo_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1)
             sys_info_ptr->console_uart_num = 1;
 
-        if (cvmx_bootinfo_ptr->dram_size > 16*1024*1024)
+        if (cvmx_bootinfo_ptr->dram_size > 32*1024*1024)
             sys_info_ptr->system_dram_size = (uint64_t)cvmx_bootinfo_ptr->dram_size;  /* older bootloaders incorrectly gave this in bytes, so don't convert */
         else
             sys_info_ptr->system_dram_size = (uint64_t)cvmx_bootinfo_ptr->dram_size * 1024 * 1024;  /* convert from Megabytes to bytes */
@@ -140,7 +143,8 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
             sys_info_ptr->led_display_base_addr = cvmx_bootinfo_ptr->led_display_base_addr;
         }
         else if (sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT3000 ||
-                 sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT5800)
+                 sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT5800 ||
+                 sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT5810)
         {
             /* Default these variables so that users of structure can be the same no
             ** matter what version fo boot info block the bootloader passes */
@@ -178,48 +182,12 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
     {
         printf("ERROR: Incompatible CVMX descriptor passed by bootloader: %d.%d\n",
                (int)cvmx_bootinfo_ptr->major_version, (int)cvmx_bootinfo_ptr->minor_version);
-        while (1);
+        exit(-1);
     }
 }
 
 
 /**
- * Interrupt handler for debugger Control-C interrupts.
- *
- * @param irq_number IRQ interrupt number
- * @param registers  CPU registers at the time of the interrupt
- * @param user_arg   Unused user argument
- */
-static void process_debug_interrupt(int irq_number, uint64_t registers[32], void *user_arg)
-{
-    int uart = irq_number - CVMX_IRQ_UART0;
-    cvmx_uart_lsr_t lsrval;
-
-    /* Check for a Control-C interrupt from the debugger. This loop will eat
-        all input received on the uart */
-    lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
-    while (lsrval.s.dr)
-    {
-        int c = cvmx_read_csr(CVMX_MIO_UARTX_RBR(uart));
-        if (c == '\003')
-        {
-            register uint64_t tmp;
-            fflush(stderr);
-            fflush(stdout);
-            /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
-                set the MCD0 to be not masked by this core so we know
-                the signal is received by someone */
-            asm volatile (
-                "dmfc0 %0, $22\n"
-                "ori   %0, %0, 0x1110\n"
-                "dmtc0 %0, $22\n"
-                : "=r" (tmp));
-        }
-        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
-    }
-}
-
-/**
  * Interrupt handler for calling exit on Control-C interrupts.
  *
  * @param irq_number IRQ interrupt number
@@ -309,6 +277,7 @@ void __cvmx_app_init(uint64_t app_desc_addr)
 
     /* app info structure used by the simple exec */
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+    int breakflag = 0;
 
     if (cvmx_coremask_first_core(app_desc_ptr->core_mask))
     {
@@ -316,8 +285,7 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         if (app_desc_ptr->desc_version < 6)
         {
             printf("Obsolete bootloader, can't run application\n");
-            while (1)
-                ;
+            exit(-1);
         }
         else
         {
@@ -332,95 +300,59 @@ void __cvmx_app_init(uint64_t app_desc_addr)
     }
     cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
-    /* All cores need to enable MCD0 signals if the debugger flag is set */
-    if (sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG)
+    breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
+
+    /* No need to initialize bootmem, interrupts, interrupt handler and error handler
+       if version does not match. */
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
     {
-        /* Set all cores to stop on MCD0 signals */
-        uint64_t tmp;
-        asm volatile(
-            "dmfc0 %0, $22, 0\n"
-            "or %0, %0, 0x1100\n"
-            "dmtc0 %0, $22, 0\n" : "=r" (tmp));
+        /* Check to make sure the Chip version matches the configured version */
+        uint32_t chip_id = cvmx_get_proc_id();
+        /* Make sure we can properly run on this chip */
+        octeon_model_version_check(chip_id);
     }
 
     cvmx_interrupt_initialize();
 
     if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
     {
-        /* Check to make sure the Chip version matches the configured version */
-        uint32_t chip_id = cvmx_get_proc_id();
-	int debugflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG;
-	int breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
-	int uart;
+        int break_uart = 0;
+        unsigned int i;
 
         /* Intialize the bootmem allocator with the descriptor that was provided by
-        ** the bootloader
-        ** IMPORTANT:  All printfs must happen after this since PCI console uses named
-        ** blocks.
-        */
-        cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_ptr);
-
-        /* Make sure we can properly run on this chip */
-        octeon_model_version_check(chip_id);
+         * the bootloader
+         * IMPORTANT:  All printfs must happen after this since PCI console uses named
+         * blocks.
+         */
+        cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
+        if (breakflag && cvmx_debug_booted())
+        {
+            printf("ERROR: Using debug and break together in not supported.\n");
+            while (1)
+                ;
+        }
 
-	/* Default to the second uart port.  Set this even if debug was
-	   not passed.  The idea is that if the program crashes one would
-	   be able to break in on uart1 even without debug.  */
-	cvmx_debug_uart = 1;
-        /* If the debugger flag is set, setup the uart Control-C interrupt
-            handler */
-        if (debugflag)
+        /* Search through the arguments for a break=X or a debug=X. */
+        for (i = 0; i < app_desc_ptr->argc; i++)
         {
-            /* Search through the arguments for a debug=X */
-            unsigned int i;
-            for (i=0; i<app_desc_ptr->argc; i++)
-            {
-                const char *argv = CASTPTR(const char, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, app_desc_ptr->argv[i]));
-                if (strncmp(argv, "debug=", 6) == 0)
-                {
-                    /* Use the supplied uart as an override */
-                    cvmx_debug_uart = atoi(argv+6);
-                    break;
-                }
-            }
-	    cvmx_interrupt_register(CVMX_IRQ_UART0+cvmx_debug_uart, process_debug_interrupt, NULL);
-	    uart = cvmx_debug_uart;
-	}
-	else if (breakflag)
-	{
-            unsigned int i;
-	    int32_t *trampoline = CASTPTR(int32_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, BOOTLOADER_DEBUG_TRAMPOLINE));
-	    /* Default to the first uart port. */
-	    uart = 0;
-
-            /* Search through the arguments for a break=X */
-            for (i = 0; i < app_desc_ptr->argc; i++)
-            {
-                const char *argv = CASTPTR(const char, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, app_desc_ptr->argv[i]));
-                if (strncmp(argv, "break=", 6) == 0)
-                {
-                    /* Use the supplied uart as an override */
-                    uart = atoi(argv+6);
-                    break;
-                }
-            }
+            const char *argv = CASTPTR(const char, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, app_desc_ptr->argv[i]));
+            if (strncmp(argv, "break=", 6) == 0)
+                break_uart = atoi(argv + 6);
+            else if (strncmp(argv, "debug=", 6) == 0)
+                cvmx_debug_uart = atoi(argv + 6);
+        }
 
-	    /* On debug exception, call exit_on_break from all cores. */
-	    *trampoline = (int32_t)(long)&exit_on_break;
-	    cvmx_interrupt_register(CVMX_IRQ_UART0 + uart, process_break_interrupt, NULL);
-	}
-	if (debugflag || breakflag)
-	{
-            /* Enable uart interrupts for debugger Control-C processing */
-            cvmx_uart_ier_t ier;
-            ier.u64 = cvmx_read_csr(CVMX_MIO_UARTX_IER(uart));
-            ier.s.erbfi = 1;
-            cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64);
-
-            cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0+uart);
+        if (breakflag)
+        {
+            int32_t *trampoline = CASTPTR(int32_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, BOOTLOADER_DEBUG_TRAMPOLINE));
+            /* On debug exception, call exit_on_break from all cores. */
+            *trampoline = (int32_t)(long)&exit_on_break;
+            cvmx_uart_enable_intr(break_uart, process_break_interrupt);
         }
     }
 
+    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
     /* Clear BEV now that we have installed exception handlers. */
     uint64_t tmp;
     asm volatile (
@@ -443,6 +375,11 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         "dmtc0 %0, $22, 0\n" : "=r" (tmp));
 
     CVMX_SYNC;
+
+    /* Now intialize the debug exception handler as BEV is cleared. */
+    if (!breakflag)
+        cvmx_debug_init();
+
     /* Synchronise all cores at this point */
     cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
@@ -470,11 +407,6 @@ int cvmx_user_app_init(void)
         printf("BIST FAILURE: COP0_CACHE_ERR: 0x%llx\n", (unsigned long long)bist_val);
         bist_errors++;
     }
-    /* Clear parity error bits */
-    CVMX_MF_CACHE_ERR(bist_val);
-    bist_val &= ~0x7ull;
-    CVMX_MT_CACHE_ERR(bist_val);
-
 
     mask = 0xfc00000000000000ull;
     CVMX_MF_CVM_MEM_CTL(bist_val);
@@ -485,29 +417,16 @@ int cvmx_user_app_init(void)
         bist_errors++;
     }
 
-    /* Clear DCACHE parity error bit */
-    bist_val = 0;
-    CVMX_MF_DCACHE_ERR(bist_val);
-
-    mask =     0x18ull;
-    bist_val = cvmx_read_csr(CVMX_L2D_ERR);
-    if (bist_val & mask)
-    {
-        printf("ERROR: ECC error detected in L2 Data, L2D_ERR: 0x%llx\n", (unsigned long long)bist_val);
-        cvmx_write_csr(CVMX_L2D_ERR, bist_val); /* Clear error bits if set */
-    }
-    bist_val = cvmx_read_csr(CVMX_L2T_ERR);
-    if (bist_val & mask)
-    {
-        printf("ERROR: ECC error detected in L2 Tags, L2T_ERR: 0x%llx\n", (unsigned long long)bist_val);
-        cvmx_write_csr(CVMX_L2T_ERR, bist_val); /* Clear error bits if set */
-    }
-
-
     /* Set up 4 cache lines of local memory, make available from Kernel space */
     CVMX_MF_CVM_MEM_CTL(tmp);
     tmp &= ~0x1ffull;
     tmp |= 0x104ull;
+    /* Set WBTHRESH=4 as per Core-14752 errata in cn63xxp1.X. */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        tmp &= ~(0xfull << 11);
+        tmp |= 4 << 11;
+    }
     CVMX_MT_CVM_MEM_CTL(tmp);
 
 
@@ -519,11 +438,9 @@ int cvmx_user_app_init(void)
     {
         printf("ERROR: 1-1 TLB mappings configured and oversize application loaded.\n");
         printf("ERROR: Either 1-1 TLB mappings must be disabled or application size reduced.\n");
-        while (1)
-            ;
+        exit(-1);
     }
 
-
     /* Create 1-1 Mappings for all DRAM up to 8 gigs, excluding the low 1 Megabyte.  This area
     ** is reserved for the bootloader and exception vectors.  By not mapping this area, NULL pointer
     ** dereferences will be caught with TLB exceptions.  Exception handlers should be written
@@ -549,67 +466,62 @@ int cvmx_user_app_init(void)
 #endif
     cvmx_core_add_fixed_tlb_mapping(0x8000000ULL, 0x8000000ULL, 0xc000000ULL, CVMX_TLB_PAGEMASK_64M);
 
-    /* Create 1-1 mapping for next 256 megs
-    ** bottom page is not valid */
-    cvmx_core_add_fixed_tlb_mapping_bits(0x400000000ULL, 0, 0x410000000ULL  | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, CVMX_TLB_PAGEMASK_256M);
-
-    /* Map from 0.5 up to the installed memory size in 512 MByte chunks.  If this loop runs out of memory,
-    ** the NULL pointer detection can be disabled to free up more TLB entries. */
-    if (cvmx_sysinfo_get()->system_dram_size > 0x20000000ULL)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
     {
-        for (base_addr = 0x20000000ULL; base_addr <= (cvmx_sysinfo_get()->system_dram_size - 0x20000000ULL); base_addr += 0x20000000ULL)
+        for (base_addr = 0x20000000ULL; base_addr < (cvmx_sysinfo_get()->system_dram_size + 0x10000000ULL); base_addr += 0x20000000ULL)
         {
             if (0 > cvmx_core_add_fixed_tlb_mapping(base_addr,  base_addr,  base_addr + 0x10000000ULL, CVMX_TLB_PAGEMASK_256M))
             {
                 printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
-                while (1);    /* Hang here, as expected memory mappings aren't set up if this fails */
+                /* Exit from here, as expected memory mappings aren't set
+                   up if this fails */
+		exit(-1);
             }
         }
     }
+    else
+    {
+        /* Create 1-1 mapping for next 256 megs
+        ** bottom page is not valid */
+        cvmx_core_add_fixed_tlb_mapping_bits(0x400000000ULL, 0, 0x410000000ULL  | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, CVMX_TLB_PAGEMASK_256M);
 
-
+        /* Map from 0.5 up to the installed memory size in 512 MByte chunks.  If this loop runs out of memory,
+        ** the NULL pointer detection can be disabled to free up more TLB entries. */
+        if (cvmx_sysinfo_get()->system_dram_size > 0x20000000ULL)
+        {
+            for (base_addr = 0x20000000ULL; base_addr <= (cvmx_sysinfo_get()->system_dram_size - 0x20000000ULL); base_addr += 0x20000000ULL)
+            {
+                if (0 > cvmx_core_add_fixed_tlb_mapping(base_addr,  base_addr,  base_addr + 0x10000000ULL, CVMX_TLB_PAGEMASK_256M))
+                {
+                    printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
+                    /* Exit from here, as expected memory mappings
+                       aren't set up if this fails */
+                    exit(-1);
+                }
+            }
+        }
+    }
 #endif
 
 
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
-    cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_ptr);
+    cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
 
     return(0);
 }
 
 void __cvmx_app_exit(void)
 {
-    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
-    {
-       uint64_t val;
-       uint64_t mask, expected;
-       int bist_errors = 0;
-
-       mask =     0x1ull;
-       expected = 0x0ull;
-       CVMX_MF_DCACHE_ERR(val);
-       val = (val & mask) ^ expected;
-       if (val)
-       {
-           printf("DCACHE Parity error: 0x%llx\n", (unsigned long long)val);
-           bist_errors++;
-       }
-
-       mask =     0x18ull;
-       expected = 0x0ull;
-       val = cvmx_read_csr(CVMX_L2D_ERR);
-       val = (val & mask) ^ expected;
-       if (val)
-       {
-           printf("L2 Parity error: 0x%llx\n", (unsigned long long)val);
-           bist_errors++;
-       }
-
-
-       while (1)
-           ;
+    cvmx_debug_finish();
 
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+	CVMX_BREAK;
     }
+    /* Hang forever, until more appropriate stand alone simple executive
+       exit() is implemented */
+
+    while (1);
 }
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.h b/sys/contrib/octeon-sdk/cvmx-app-init.h
index 8b43bcf..1138e2c 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init.h
+++ b/sys/contrib/octeon-sdk/cvmx-app-init.h
@@ -1,50 +1,52 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  * Header file for simple executive application initialization.  This defines
  * part of the ABI between the bootloader and the application.
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 
@@ -73,8 +75,7 @@ extern "C" {
 ** must be incremented, and the minor version should be reset
 ** to 0.
 */
-typedef struct
-{
+struct cvmx_bootinfo {
     uint32_t major_version;
     uint32_t minor_version;
 
@@ -121,7 +122,9 @@ typedef struct
 #endif
 
 
-} cvmx_bootinfo_t;
+};
+
+typedef struct cvmx_bootinfo cvmx_bootinfo_t;
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST			(1ull << 0)
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET		(1ull << 1)
@@ -166,6 +169,15 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_CB5601         = 26,
     CVMX_BOARD_TYPE_CB5200         = 27,
     CVMX_BOARD_TYPE_GENERIC        = 28,   /* Special 'generic' board type, supports many boards */
+    CVMX_BOARD_TYPE_EBH5610        = 29,
+    CVMX_BOARD_TYPE_LANAI2_A       = 30,
+    CVMX_BOARD_TYPE_LANAI2_U       = 31,
+    CVMX_BOARD_TYPE_EBB5600        = 32,
+    CVMX_BOARD_TYPE_EBB6300        = 33,
+    CVMX_BOARD_TYPE_NIC_XLE_10G    = 34,
+    CVMX_BOARD_TYPE_LANAI2_G       = 35,
+    CVMX_BOARD_TYPE_EBT5810        = 36,
+    CVMX_BOARD_TYPE_NIC10E         = 37,
     CVMX_BOARD_TYPE_MAX,
 
     /* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
@@ -193,8 +205,16 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_CUST_GCT108      = 10012,
     CVMX_BOARD_TYPE_CUST_AGS109      = 10013,
     CVMX_BOARD_TYPE_CUST_GCT110      = 10014,
+    CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER  = 10015,
+    CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER= 10016,
+    CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX  = 10017,
+    CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX  = 10018,
+    CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX= 10019,
+    CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX= 10020,
 #if defined(OCTEON_VENDOR_LANNER)
-    CVMX_BOARD_TYPE_CUST_LANNER_MR730= 10021,
+    CVMX_BOARD_TYPE_CUST_LANNER_MR730	= 10021,
+#else
+    CVMX_BOARD_TYPE_CUST_L2_ZINWELL     = 10021,
 #endif
     CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
@@ -206,6 +226,20 @@ enum cvmx_board_types_enum {
 #endif
     CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
 
+
+    /* Range for IO modules */
+    CVMX_BOARD_TYPE_MODULE_MIN          = 30001,
+    CVMX_BOARD_TYPE_MODULE_PCIE_RC_4X   = 30002,
+    CVMX_BOARD_TYPE_MODULE_PCIE_EP_4X   = 30003,
+    CVMX_BOARD_TYPE_MODULE_SGMII_MARVEL = 30004,
+    CVMX_BOARD_TYPE_MODULE_SFPPLUS_BCM  = 30005,
+    CVMX_BOARD_TYPE_MODULE_SRIO         = 30006,
+    CVMX_BOARD_TYPE_MODULE_EBB5600_QLM0 = 30007,
+    CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1 = 30008,
+    CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2 = 30009,
+    CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3 = 30010,
+    CVMX_BOARD_TYPE_MODULE_MAX          = 31000,
+
     /* The remaining range is reserved for future use. */
 };
 enum cvmx_chip_types_enum {
@@ -253,6 +287,15 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
         /* Customer boards listed here */
@@ -275,9 +318,18 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
 #if defined(OCTEON_VENDOR_LANNER)
 	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR730)
+#else
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
 #endif
+
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
 
         /* Customer private range */
@@ -286,6 +338,19 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
 	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR320)
 #endif
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
+
+        /* Module range */
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_MIN)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_PCIE_RC_4X)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_PCIE_EP_4X)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_SGMII_MARVEL)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_SFPPLUS_BCM)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_SRIO)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_EBB5600_QLM0)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MODULE_MAX)
     }
     return "Unsupported Board";
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-asm.h b/sys/contrib/octeon-sdk/cvmx-asm.h
index f25d9b2..2377bb7 100644
--- a/sys/contrib/octeon-sdk/cvmx-asm.h
+++ b/sys/contrib/octeon-sdk/cvmx-asm.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,77 @@
 
 
 
+
 /**
  * @file
  *
  * This is file defines ASM primitives for the executive.
 
- * <hr>$Revision: 42280 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  *
  */
 #ifndef __CVMX_ASM_H__
 #define __CVMX_ASM_H__
 
+#define COP0_INDEX	$0,0	/* TLB read/write index */
+#define COP0_RANDOM	$1,0	/* TLB random index */
+#define COP0_ENTRYLO0	$2,0	/* TLB entryLo0 */
+#define COP0_ENTRYLO1	$3,0	/* TLB entryLo1 */
+#define COP0_CONTEXT	$4,0	/* Context */
+#define COP0_PAGEMASK	$5,0	/* TLB pagemask */
+#define COP0_PAGEGRAIN	$5,1	/* TLB config for max page sizes */
+#define COP0_WIRED	$6,0	/* TLB number of wired entries */
+#define COP0_HWRENA	$7,0	/* rdhw instruction enable per register */
+#define COP0_BADVADDR	$8,0	/* Bad virtual address */
+#define COP0_COUNT	$9,0	/* Mips count register */
+#define COP0_CVMCOUNT	$9,6	/* Cavium count register */
+#define COP0_CVMCTL	$9,7	/* Cavium control */
+#define COP0_ENTRYHI	$10,0	/* TLB entryHi */
+#define COP0_COMPARE	$11,0	/* Mips compare register */
+#define COP0_POWTHROTTLE $11,6	/* Power throttle register */
+#define COP0_CVMMEMCTL	$11,7	/* Cavium memory control */
+#define COP0_STATUS	$12,0	/* Mips status register */
+#define COP0_INTCTL	$12,1	/* Useless (Vectored interrupts) */
+#define COP0_SRSCTL	$12,2	/* Useless (Shadow registers) */
+#define COP0_CAUSE	$13,0	/* Mips cause register */
+#define COP0_EPC	$14,0	/* Exception program counter */
+#define COP0_PRID	$15,0	/* Processor ID */
+#define COP0_EBASE	$15,1	/* Exception base */
+#define COP0_CONFIG	$16,0	/* Misc config options */
+#define COP0_CONFIG1	$16,1	/* Misc config options */
+#define COP0_CONFIG2	$16,2	/* Misc config options */
+#define COP0_CONFIG3	$16,3	/* Misc config options */
+#define COP0_WATCHLO0	$18,0	/* Address watch registers */
+#define COP0_WATCHLO1	$18,1	/* Address watch registers */
+#define COP0_WATCHHI0	$19,0	/* Address watch registers */
+#define COP0_WATCHHI1	$19,1	/* Address watch registers */
+#define COP0_XCONTEXT	$20,0	/* OS context */
+#define COP0_MULTICOREDEBUG $22,0 /* Cavium debug */
+#define COP0_DEBUG	$23,0	/* Debug status */
+#define COP0_DEPC	$24,0	/* Debug PC */
+#define COP0_PERFCONTROL0 $25,0	/* Performance counter control */
+#define COP0_PERFCONTROL1 $25,2	/* Performance counter control */
+#define COP0_PERFVALUE0	$25,1	/* Performance counter */
+#define COP0_PERFVALUE1	$25,3	/* Performance counter */
+#define COP0_CACHEERRI	$27,0	/* I cache error status */
+#define COP0_CACHEERRD	$27,1	/* D cache error status */
+#define COP0_TAGLOI	$28,0	/* I cache tagLo */
+#define COP0_TAGLOD	$28,2	/* D cache tagLo */
+#define COP0_DATALOI	$28,1	/* I cache dataLo */
+#define COP0_DATALOD	$28,3	/* D cahce dataLo */
+#define COP0_TAGHI	$29,2	/* ? */
+#define COP0_DATAHII	$29,1	/* ? */
+#define COP0_DATAHID	$29,3	/* ? */
+#define COP0_ERROREPC	$30,0	/* Error PC */
+#define COP0_DESAVE	$31,0	/* Debug scratch area */
+
+/* This header file can be included from a .S file.  Keep non-preprocessor
+   things under !__ASSEMBLER__.  */
+#ifndef __ASSEMBLER__
+
+#include "octeon-model.h"
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -61,11 +121,23 @@ extern "C" {
 #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
 #define CVMX_TMP_STR2(x) #x
 
+#if !OCTEON_IS_COMMON_BINARY()
+ #if CVMX_COMPILED_FOR(OCTEON_CN63XX)
+   #define CVMX_CAVIUM_OCTEON2
+ #endif
+#endif
+
 /* other useful stuff */
 #define CVMX_BREAK asm volatile ("break")
 #define CVMX_SYNC asm volatile ("sync" : : :"memory")
 /* String version of SYNCW macro for using in inline asm constructs */
-#define CVMX_SYNCW_STR "syncw\nsyncw\n"
+#define CVMX_SYNCW_STR_OCTEON2 "syncw\n"
+#ifdef CVMX_CAVIUM_OCTEON2
+ #define CVMX_SYNCW_STR CVMX_SYNCW_STR_OCTEON2
+#else
+ #define CVMX_SYNCW_STR "syncw\nsyncw\n"
+#endif /* CVMX_CAVIUM_OCTEON2 */
+
 #ifdef __OCTEON__
     #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
@@ -75,13 +147,20 @@ extern "C" {
         errata Core-401. This can cause a single syncw to not enforce
         ordering under very rare conditions. Even if it is rare, better safe
         than sorry */
-    #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory")
+    #define CVMX_SYNCW_OCTEON2 asm volatile ("syncw\n" : : :"memory")
+    #ifdef CVMX_CAVIUM_OCTEON2
+     #define CVMX_SYNCW CVMX_SYNCW_OCTEON2
+    #else
+     #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory")
+    #endif /* CVMX_CAVIUM_OCTEON2 */
 #if defined(VXWORKS) || defined(__linux__)
-    /* Define new sync instructions to be normal SYNC instructions for
-        operating systems that use threads */
-    #define CVMX_SYNCWS CVMX_SYNCW
-    #define CVMX_SYNCS  CVMX_SYNC
-    #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+        /* Define new sync instructions to be normal SYNC instructions for
+           operating systems that use threads */
+        #define CVMX_SYNCWS CVMX_SYNCW
+        #define CVMX_SYNCS  CVMX_SYNC
+        #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+        #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2
+        #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2
 #else
     #if defined(CVMX_BUILD_FOR_TOOLCHAIN)
         /* While building simple exec toolchain, always use syncw to
@@ -89,15 +168,24 @@ extern "C" {
         #define CVMX_SYNCWS CVMX_SYNCW
         #define CVMX_SYNCS  CVMX_SYNC
         #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+        #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2
+        #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2
     #else
         /* Again, just like syncw, we may need two syncws instructions in a row due
-            errata Core-401 */
-        #define CVMX_SYNCWS asm volatile ("syncws\nsyncws\n" : : :"memory")
+           errata Core-401. Only one syncws is required for Octeon2 models */
         #define CVMX_SYNCS asm volatile ("syncs" : : :"memory")
-        #define CVMX_SYNCWS_STR "syncws\nsyncws\n"
+        #define CVMX_SYNCWS_OCTEON2 asm volatile ("syncws\n" : : :"memory")
+        #define CVMX_SYNCWS_STR_OCTEON2 "syncws\n"
+        #ifdef CVMX_CAVIUM_OCTEON2
+          #define CVMX_SYNCWS CVMX_SYNCWS_OCTEON2
+          #define CVMX_SYNCWS_STR CVMX_SYNCWS_STR_OCTEON2
+        #else
+          #define CVMX_SYNCWS asm volatile ("syncws\nsyncws\n" : : :"memory")
+          #define CVMX_SYNCWS_STR "syncws\nsyncws\n"
+        #endif /* CVMX_CAVIUM_OCTEON2 */
     #endif
 #endif
-#else
+#else /* !__OCTEON__ */
     /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
     #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
@@ -106,6 +194,8 @@ extern "C" {
     #define CVMX_SYNCWS CVMX_SYNCW
     #define CVMX_SYNCS  CVMX_SYNC
     #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+    #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW
+    #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR
 #endif
 #define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) )
 #define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
@@ -137,6 +227,12 @@ extern "C" {
 #define CVMX_ICACHE_INVALIDATE2 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } // flush stores, invalidate entire icache
 #define CVMX_DCACHE_INVALIDATE  { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } // complete prefetches, invalidate entire dcache
 
+#define CVMX_CACHE(op, address, offset) asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) )
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) // fetch and lock the state.
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) // unlock the state.
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) // invalidate the cache block and clear the USED bits for the block
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) // load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register
+
 /* new instruction to make RC4 run faster */
 #define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2))
 
@@ -232,7 +328,7 @@ extern "C" {
     ASM_STMT ("rdhwr\t%0,$" CVMX_TMP_STR(regstr) : "=d"(_v));		\
     result = (__typeof(result))_v;					\
   }})
-  
+
 
 
 #  define CVMX_RDHWR(result, regstr) CVMX_RDHWRX(result, regstr, asm volatile)
@@ -408,18 +504,67 @@ extern "C" {
 #define CVMX_MF_AES_KEY(val,pos)    asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
 #define CVMX_MF_AES_KEYLENGTH(val)  asm volatile ("dmfc2 %[rt],0x0110"                   : [rt] "=d" (val) :               ) // read the keylen
 #define CVMX_MF_AES_DAT0(val)       asm volatile ("dmfc2 %[rt],0x0111"                   : [rt] "=d" (val) :               ) // first piece of input data
-/* GFM COP2 macros */
-/* index can be 0 or 1 */
-#define CVMX_MF_GFM_MUL(val, index)     asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(index) : [rt] "=d" (val) :               )
-#define CVMX_MF_GFM_POLY(val)           asm volatile ("dmfc2 %[rt],0x025e"                      : [rt] "=d" (val) :               )
-#define CVMX_MF_GFM_RESINP(val, index)  asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(index) : [rt] "=d" (val) :               )
 
-#define CVMX_MT_GFM_MUL(val, index)     asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(index) :                 : [rt] "d" (val))
-#define CVMX_MT_GFM_POLY(val)           asm volatile ("dmtc2 %[rt],0x025e"                      :                 : [rt] "d" (val))
-#define CVMX_MT_GFM_RESINP(val, index)  asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(index) :                 : [rt] "d" (val))
-#define CVMX_MT_GFM_XOR0(val)           asm volatile ("dmtc2 %[rt],0x025c"                      :                 : [rt] "d" (val))
-#define CVMX_MT_GFM_XORMUL1(val)        asm volatile ("dmtc2 %[rt],0x425d"                      :                 : [rt] "d" (val))
+// GFM
 
+// pos can be 0-1
+#define CVMX_MF_GFM_MUL(val,pos)             asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MF_GFM_POLY(val)                asm volatile ("dmfc2 %[rt],0x025e"                    : [rt] "=d" (val) :               )
+// pos can be 0-1
+#define CVMX_MF_GFM_RESINP(val,pos)          asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-1
+#define CVMX_MF_GFM_RESINP_REFLECT(val,pos)  asm volatile ("dmfc2 %[rt],0x005a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+
+// pos can be 0-1
+#define CVMX_MT_GFM_MUL(val,pos)             asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_POLY(val)                asm volatile ("dmtc2 %[rt],0x025e"                    :                 : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_GFM_RESINP(val,pos)          asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_XOR0(val)                asm volatile ("dmtc2 %[rt],0x025c"                    :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_XORMUL1(val)             asm volatile ("dmtc2 %[rt],0x425d"                    :                 : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_GFM_MUL_REFLECT(val,pos)     asm volatile ("dmtc2 %[rt],0x0058+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MT_GFM_XOR0_REFLECT(val)        asm volatile ("dmtc2 %[rt],0x005c"                    :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_XORMUL1_REFLECT(val)     asm volatile ("dmtc2 %[rt],0x405d"                    :                 : [rt] "d" (val))
+
+// SNOW 3G
+
+// pos can be 0-7
+#define CVMX_MF_SNOW3G_LFSR(val,pos)    asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-2
+#define CVMX_MF_SNOW3G_FSM(val,pos)     asm volatile ("dmfc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MF_SNOW3G_RESULT(val)      asm volatile ("dmfc2 %[rt],0x0250"                    : [rt] "=d" (val) :               )
+
+// pos can be 0-7
+#define CVMX_MT_SNOW3G_LFSR(val,pos)    asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+// pos can be 0-2
+#define CVMX_MT_SNOW3G_FSM(val,pos)     asm volatile ("dmtc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+#define CVMX_MT_SNOW3G_RESULT(val)      asm volatile ("dmtc2 %[rt],0x0250"                    : : [rt] "d" (val))
+#define CVMX_MT_SNOW3G_START(val)       asm volatile ("dmtc2 %[rt],0x404d"                    : : [rt] "d" (val))
+#define CVMX_MT_SNOW3G_MORE(val)        asm volatile ("dmtc2 %[rt],0x404e"                    : : [rt] "d" (val))
+
+// SMS4
+
+// pos can be 0-1
+#define CVMX_MF_SMS4_IV(val,pos)	asm volatile ("dmfc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-1
+#define CVMX_MF_SMS4_KEY(val,pos)	asm volatile ("dmfc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-1
+#define CVMX_MF_SMS4_RESINP(val,pos)	asm volatile ("dmfc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MT_SMS4_DEC_CBC0(val)	asm volatile ("dmtc2 %[rt],0x010c"                   : : [rt] "d" (val))
+#define CVMX_MT_SMS4_DEC_CBC1(val)	asm volatile ("dmtc2 %[rt],0x311d"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_DEC0(val)		asm volatile ("dmtc2 %[rt],0x010e"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_DEC1(val)		asm volatile ("dmtc2 %[rt],0x311f"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_ENC_CBC0(val)	asm volatile ("dmtc2 %[rt],0x0108"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_ENC_CBC1(val)	asm volatile ("dmtc2 %[rt],0x3119"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_ENC0(val)		asm volatile ("dmtc2 %[rt],0x010a"      : : [rt] "d" (val))
+#define CVMX_MT_SMS4_ENC1(val)		asm volatile ("dmtc2 %[rt],0x311b"      : : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_SMS4_IV(val,pos)	asm volatile ("dmtc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_SMS4_KEY(val,pos)	asm volatile ("dmtc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_SMS4_RESINP(val,pos)	asm volatile ("dmtc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : : [rt] "d" (val))
 
 /* check_ordering stuff */
 #if 0
@@ -436,19 +581,25 @@ extern "C" {
 
 #define CVMX_MT_CYCLE(src)         asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src))
 
-#define CVMX_MF_CACHE_ERR(val)            asm volatile ("dmfc0 %[rt],$27,0" :  [rt] "=d" (val):)
-#define CVMX_MF_DCACHE_ERR(val)           asm volatile ("dmfc0 %[rt],$27,1" :  [rt] "=d" (val):)
-#define CVMX_MF_CVM_MEM_CTL(val)          asm volatile ("dmfc0 %[rt],$11,7" :  [rt] "=d" (val):)
-#define CVMX_MF_CVM_CTL(val)              asm volatile ("dmfc0 %[rt],$9,7"  :  [rt] "=d" (val):)
-#define CVMX_MT_CACHE_ERR(val)            asm volatile ("dmtc0 %[rt],$27,0" : : [rt] "d" (val))
-#define CVMX_MT_DCACHE_ERR(val)           asm volatile ("dmtc0 %[rt],$27,1" : : [rt] "d" (val))
-#define CVMX_MT_CVM_MEM_CTL(val)          asm volatile ("dmtc0 %[rt],$11,7" : : [rt] "d" (val))
-#define CVMX_MT_CVM_CTL(val)              asm volatile ("dmtc0 %[rt],$9,7"  : : [rt] "d" (val))
+#define VASTR(...) #__VA_ARGS__
+
+#define CVMX_MF_COP0(val, cop0)           asm volatile ("dmfc0 %[rt]," VASTR(cop0) : [rt] "=d" (val));
+#define CVMX_MT_COP0(val, cop0)           asm volatile ("dmtc0 %[rt]," VASTR(cop0) : : [rt] "d" (val));
+
+#define CVMX_MF_CACHE_ERR(val)            CVMX_MF_COP0(val, COP0_CACHEERRI)
+#define CVMX_MF_DCACHE_ERR(val)           CVMX_MF_COP0(val, COP0_CACHEERRD)
+#define CVMX_MF_CVM_MEM_CTL(val)          CVMX_MF_COP0(val, COP0_CVMMEMCTL)
+#define CVMX_MF_CVM_CTL(val)              CVMX_MF_COP0(val, COP0_CVMCTL)
+#define CVMX_MT_CACHE_ERR(val)            CVMX_MT_COP0(val, COP0_CACHEERRI)
+#define CVMX_MT_DCACHE_ERR(val)           CVMX_MT_COP0(val, COP0_CACHEERRD)
+#define CVMX_MT_CVM_MEM_CTL(val)          CVMX_MT_COP0(val, COP0_CVMMEMCTL)
+#define CVMX_MT_CVM_CTL(val)              CVMX_MT_COP0(val, COP0_CVMCTL)
 
 /* Macros for TLB */
 #define CVMX_TLBWI                       asm volatile ("tlbwi" : : )
 #define CVMX_TLBWR                       asm volatile ("tlbwr" : : )
 #define CVMX_TLBR                        asm volatile ("tlbr" : : )
+#define CVMX_TLBP                        asm volatile ("tlbp" : : )
 #define CVMX_MT_ENTRY_HIGH(val)          asm volatile ("dmtc0 %[rt],$10,0" : : [rt] "d" (val))
 #define CVMX_MT_ENTRY_LO_0(val)          asm volatile ("dmtc0 %[rt],$2,0" : : [rt] "d" (val))
 #define CVMX_MT_ENTRY_LO_1(val)          asm volatile ("dmtc0 %[rt],$3,0" : : [rt] "d" (val))
@@ -464,12 +615,18 @@ extern "C" {
 #define CVMX_MF_PAGEMASK(val)            asm volatile ("mfc0 %[rt],$5,0" :  [rt] "=d" (val):)
 #define CVMX_MF_PAGEGRAIN(val)           asm volatile ("mfc0 %[rt],$5,1" :  [rt] "=d" (val):)
 #define CVMX_MF_TLB_WIRED(val)           asm volatile ("mfc0 %[rt],$6,0" :  [rt] "=d" (val):)
+#define CVMX_MF_TLB_INDEX(val)           asm volatile ("mfc0 %[rt],$0,0" :  [rt] "=d" (val):)
 #define CVMX_MF_TLB_RANDOM(val)          asm volatile ("mfc0 %[rt],$1,0" :  [rt] "=d" (val):)
 #define TLB_DIRTY   (0x1ULL<<2)
 #define TLB_VALID   (0x1ULL<<1)
 #define TLB_GLOBAL  (0x1ULL<<0)
 
 
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+/* Macros to PUSH and POP Octeon2 ISA. */
+#define CVMX_PUSH_OCTEON2    asm volatile (".set push\n.set arch=octeon2")
+#define CVMX_POP_OCTEON2     asm volatile (".set pop")
+#endif
 
 /* assembler macros to guarantee byte loads/stores are used */
 /* for an unaligned 16-bit access (these use AT register) */
@@ -510,4 +667,6 @@ extern "C" {
 }
 #endif
 
+#endif	/* __ASSEMBLER__ */
+
 #endif /* __CVMX_ASM_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-asx.h b/sys/contrib/octeon-sdk/cvmx-asx.h
deleted file mode 100644
index 4a49a04b..0000000
--- a/sys/contrib/octeon-sdk/cvmx-asx.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * Interface to the ASX hardware.
- *
- * <hr>$Revision: 41586 $<hr>
- */
-
-#ifndef __CVMX_ASX_H__
-#define __CVMX_ASX_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif
-
diff --git a/sys/contrib/octeon-sdk/cvmx-asx0-defs.h b/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
new file mode 100644
index 0000000..42115db
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
@@ -0,0 +1,147 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-asx0-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon asx0.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_ASX0_TYPEDEFS_H__
+#define __CVMX_ASX0_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
+}
+#else
+#define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
+}
+#else
+#define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull))
+#endif
+
+/**
+ * cvmx_asx0_dbg_data_drv
+ *
+ * ASX_DBG_DATA_DRV
+ *
+ */
+union cvmx_asx0_dbg_data_drv
+{
+	uint64_t u64;
+	struct cvmx_asx0_dbg_data_drv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t pctl                         : 5;  /**< These bits control the driving strength of the dbg
+                                                         interface. */
+	uint64_t nctl                         : 4;  /**< These bits control the driving strength of the dbg
+                                                         interface. */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_asx0_dbg_data_drv_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t pctl                         : 4;  /**< These bits control the driving strength of the dbg
+                                                         interface. */
+	uint64_t nctl                         : 4;  /**< These bits control the driving strength of the dbg
+                                                         interface. */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn38xx;
+	struct cvmx_asx0_dbg_data_drv_cn38xx  cn38xxp2;
+	struct cvmx_asx0_dbg_data_drv_s       cn58xx;
+	struct cvmx_asx0_dbg_data_drv_s       cn58xxp1;
+};
+typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
+
+/**
+ * cvmx_asx0_dbg_data_enable
+ *
+ * ASX_DBG_DATA_ENABLE
+ *
+ */
+union cvmx_asx0_dbg_data_enable
+{
+	uint64_t u64;
+	struct cvmx_asx0_dbg_data_enable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< A 1->0 transistion, turns the dbg interface OFF. */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_asx0_dbg_data_enable_s    cn38xx;
+	struct cvmx_asx0_dbg_data_enable_s    cn38xxp2;
+	struct cvmx_asx0_dbg_data_enable_s    cn58xx;
+	struct cvmx_asx0_dbg_data_enable_s    cn58xxp1;
+};
+typedef union cvmx_asx0_dbg_data_enable cvmx_asx0_dbg_data_enable_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-asxx-defs.h b/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
new file mode 100644
index 0000000..0791d1b
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
@@ -0,0 +1,1382 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-asxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon asxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_ASXX_TYPEDEFS_H__
+#define __CVMX_ASXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000180ull);
+}
+#else
+#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000188ull);
+}
+#else
+#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000190ull);
+}
+#else
+#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_asx#_gmii_rx_clk_set
+ *
+ * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
+ *
+ */
+union cvmx_asxx_gmii_rx_clk_set
+{
+	uint64_t u64;
+	struct cvmx_asxx_gmii_rx_clk_set_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< Setting to place on the RXCLK (GMII receive clk)
+                                                         delay line.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_gmii_rx_clk_set_s    cn30xx;
+	struct cvmx_asxx_gmii_rx_clk_set_s    cn31xx;
+	struct cvmx_asxx_gmii_rx_clk_set_s    cn50xx;
+};
+typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
+
+/**
+ * cvmx_asx#_gmii_rx_dat_set
+ *
+ * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
+ *
+ */
+union cvmx_asxx_gmii_rx_dat_set
+{
+	uint64_t u64;
+	struct cvmx_asxx_gmii_rx_dat_set_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< Setting to place on the RXD (GMII receive data)
+                                                         delay lines.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_gmii_rx_dat_set_s    cn30xx;
+	struct cvmx_asxx_gmii_rx_dat_set_s    cn31xx;
+	struct cvmx_asxx_gmii_rx_dat_set_s    cn50xx;
+};
+typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
+
+/**
+ * cvmx_asx#_int_en
+ *
+ * ASX_INT_EN = Interrupt Enable
+ *
+ */
+union cvmx_asxx_int_en
+{
+	uint64_t u64;
+	struct cvmx_asxx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
+	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
+	uint64_t ovrflw                       : 4;  /**< RX FIFO overflow on RMGII port */
+#else
+	uint64_t ovrflw                       : 4;
+	uint64_t txpop                        : 4;
+	uint64_t txpsh                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_asxx_int_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t txpop                        : 3;  /**< TX FIFO underflow on RMGII port */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t ovrflw                       : 3;  /**< RX FIFO overflow on RMGII port */
+#else
+	uint64_t ovrflw                       : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txpop                        : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t txpsh                        : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_int_en_cn30xx        cn31xx;
+	struct cvmx_asxx_int_en_s             cn38xx;
+	struct cvmx_asxx_int_en_s             cn38xxp2;
+	struct cvmx_asxx_int_en_cn30xx        cn50xx;
+	struct cvmx_asxx_int_en_s             cn58xx;
+	struct cvmx_asxx_int_en_s             cn58xxp1;
+};
+typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
+
+/**
+ * cvmx_asx#_int_reg
+ *
+ * ASX_INT_REG = Interrupt Register
+ *
+ */
+union cvmx_asxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_asxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
+	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
+	uint64_t ovrflw                       : 4;  /**< RX FIFO overflow on RMGII port */
+#else
+	uint64_t ovrflw                       : 4;
+	uint64_t txpop                        : 4;
+	uint64_t txpsh                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_asxx_int_reg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t txpop                        : 3;  /**< TX FIFO underflow on RMGII port */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t ovrflw                       : 3;  /**< RX FIFO overflow on RMGII port */
+#else
+	uint64_t ovrflw                       : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txpop                        : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t txpsh                        : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_int_reg_cn30xx       cn31xx;
+	struct cvmx_asxx_int_reg_s            cn38xx;
+	struct cvmx_asxx_int_reg_s            cn38xxp2;
+	struct cvmx_asxx_int_reg_cn30xx       cn50xx;
+	struct cvmx_asxx_int_reg_s            cn58xx;
+	struct cvmx_asxx_int_reg_s            cn58xxp1;
+};
+typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
+
+/**
+ * cvmx_asx#_mii_rx_dat_set
+ *
+ * ASX_MII_RX_DAT_SET = GMII Clock delay setting
+ *
+ */
+union cvmx_asxx_mii_rx_dat_set
+{
+	uint64_t u64;
+	struct cvmx_asxx_mii_rx_dat_set_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< Setting to place on the RXD (MII receive data)
+                                                         delay lines.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_mii_rx_dat_set_s     cn30xx;
+	struct cvmx_asxx_mii_rx_dat_set_s     cn50xx;
+};
+typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
+
+/**
+ * cvmx_asx#_prt_loop
+ *
+ * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
+ *
+ */
+union cvmx_asxx_prt_loop
+{
+	uint64_t u64;
+	struct cvmx_asxx_prt_loop_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ext_loop                     : 4;  /**< External Loopback Enable
+                                                         0 = No Loopback (TX FIFO is filled by RMGII)
+                                                         1 = RX FIFO drives the TX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - core clock > 250MHZ
+                                                             - rxc must not deviate from the +-50ppm
+                                                             - if txc>rxc, idle cycle may drop over time */
+	uint64_t int_loop                     : 4;  /**< Internal Loopback Enable
+                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
+                                                         1 = TX FIFO drives the RX FIFO
+                                                         Note, in internal loop-back mode, the RGMII link
+                                                         status is not used (since there is no real PHY).
+                                                         Software cannot use the inband status. */
+#else
+	uint64_t int_loop                     : 4;
+	uint64_t ext_loop                     : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_asxx_prt_loop_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t ext_loop                     : 3;  /**< External Loopback Enable
+                                                         0 = No Loopback (TX FIFO is filled by RMGII)
+                                                         1 = RX FIFO drives the TX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - core clock > 250MHZ
+                                                             - rxc must not deviate from the +-50ppm
+                                                             - if txc>rxc, idle cycle may drop over time */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t int_loop                     : 3;  /**< Internal Loopback Enable
+                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
+                                                         1 = TX FIFO drives the RX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - GMX_TX_CLK[CLK_CNT] must be 1
+                                                         Note, in internal loop-back mode, the RGMII link
+                                                         status is not used (since there is no real PHY).
+                                                         Software cannot use the inband status. */
+#else
+	uint64_t int_loop                     : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t ext_loop                     : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_prt_loop_cn30xx      cn31xx;
+	struct cvmx_asxx_prt_loop_s           cn38xx;
+	struct cvmx_asxx_prt_loop_s           cn38xxp2;
+	struct cvmx_asxx_prt_loop_cn30xx      cn50xx;
+	struct cvmx_asxx_prt_loop_s           cn58xx;
+	struct cvmx_asxx_prt_loop_s           cn58xxp1;
+};
+typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
+
+/**
+ * cvmx_asx#_rld_bypass
+ *
+ * ASX_RLD_BYPASS
+ *
+ */
+union cvmx_asxx_rld_bypass
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_bypass_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t bypass                       : 1;  /**< When set, the rld_dll setting is bypassed with
+                                                         ASX_RLD_BYPASS_SETTING */
+#else
+	uint64_t bypass                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_asxx_rld_bypass_s         cn38xx;
+	struct cvmx_asxx_rld_bypass_s         cn38xxp2;
+	struct cvmx_asxx_rld_bypass_s         cn58xx;
+	struct cvmx_asxx_rld_bypass_s         cn58xxp1;
+};
+typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
+
+/**
+ * cvmx_asx#_rld_bypass_setting
+ *
+ * ASX_RLD_BYPASS_SETTING
+ *
+ */
+union cvmx_asxx_rld_bypass_setting
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_bypass_setting_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< The rld_dll setting bypass value */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rld_bypass_setting_s cn38xx;
+	struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
+	struct cvmx_asxx_rld_bypass_setting_s cn58xx;
+	struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
+};
+typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
+
+/**
+ * cvmx_asx#_rld_comp
+ *
+ * ASX_RLD_COMP
+ *
+ */
+union cvmx_asxx_rld_comp
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_comp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t pctl                         : 5;  /**< PCTL Compensation Value
+                                                         These bits reflect the computed compensation
+                                                          values from the built-in compensation circuit. */
+	uint64_t nctl                         : 4;  /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_asxx_rld_comp_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t pctl                         : 4;  /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+	uint64_t nctl                         : 4;  /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn38xx;
+	struct cvmx_asxx_rld_comp_cn38xx      cn38xxp2;
+	struct cvmx_asxx_rld_comp_s           cn58xx;
+	struct cvmx_asxx_rld_comp_s           cn58xxp1;
+};
+typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
+
+/**
+ * cvmx_asx#_rld_data_drv
+ *
+ * ASX_RLD_DATA_DRV
+ *
+ */
+union cvmx_asxx_rld_data_drv
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_data_drv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t pctl                         : 4;  /**< These bits specify a driving strength (positive
+                                                         integer) for the RLD I/Os when the built-in
+                                                         compensation circuit is bypassed. */
+	uint64_t nctl                         : 4;  /**< These bits specify a driving strength (positive
+                                                         integer) for the RLD I/Os when the built-in
+                                                         compensation circuit is bypassed. */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_asxx_rld_data_drv_s       cn38xx;
+	struct cvmx_asxx_rld_data_drv_s       cn38xxp2;
+	struct cvmx_asxx_rld_data_drv_s       cn58xx;
+	struct cvmx_asxx_rld_data_drv_s       cn58xxp1;
+};
+typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
+
+/**
+ * cvmx_asx#_rld_fcram_mode
+ *
+ * ASX_RLD_FCRAM_MODE
+ *
+ */
+union cvmx_asxx_rld_fcram_mode
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_fcram_mode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t mode                         : 1;  /**< Memory Mode
+                                                         - 0: RLDRAM
+                                                         - 1: FCRAM */
+#else
+	uint64_t mode                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_asxx_rld_fcram_mode_s     cn38xx;
+	struct cvmx_asxx_rld_fcram_mode_s     cn38xxp2;
+};
+typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
+
+/**
+ * cvmx_asx#_rld_nctl_strong
+ *
+ * ASX_RLD_NCTL_STRONG
+ *
+ */
+union cvmx_asxx_rld_nctl_strong
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_nctl_strong_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t nctl                         : 5;  /**< Duke's drive control */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rld_nctl_strong_s    cn38xx;
+	struct cvmx_asxx_rld_nctl_strong_s    cn38xxp2;
+	struct cvmx_asxx_rld_nctl_strong_s    cn58xx;
+	struct cvmx_asxx_rld_nctl_strong_s    cn58xxp1;
+};
+typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
+
+/**
+ * cvmx_asx#_rld_nctl_weak
+ *
+ * ASX_RLD_NCTL_WEAK
+ *
+ */
+union cvmx_asxx_rld_nctl_weak
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_nctl_weak_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t nctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rld_nctl_weak_s      cn38xx;
+	struct cvmx_asxx_rld_nctl_weak_s      cn38xxp2;
+	struct cvmx_asxx_rld_nctl_weak_s      cn58xx;
+	struct cvmx_asxx_rld_nctl_weak_s      cn58xxp1;
+};
+typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
+
+/**
+ * cvmx_asx#_rld_pctl_strong
+ *
+ * ASX_RLD_PCTL_STRONG
+ *
+ */
+union cvmx_asxx_rld_pctl_strong
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_pctl_strong_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t pctl                         : 5;  /**< Duke's drive control */
+#else
+	uint64_t pctl                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rld_pctl_strong_s    cn38xx;
+	struct cvmx_asxx_rld_pctl_strong_s    cn38xxp2;
+	struct cvmx_asxx_rld_pctl_strong_s    cn58xx;
+	struct cvmx_asxx_rld_pctl_strong_s    cn58xxp1;
+};
+typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
+
+/**
+ * cvmx_asx#_rld_pctl_weak
+ *
+ * ASX_RLD_PCTL_WEAK
+ *
+ */
+union cvmx_asxx_rld_pctl_weak
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_pctl_weak_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t pctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
+#else
+	uint64_t pctl                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rld_pctl_weak_s      cn38xx;
+	struct cvmx_asxx_rld_pctl_weak_s      cn38xxp2;
+	struct cvmx_asxx_rld_pctl_weak_s      cn58xx;
+	struct cvmx_asxx_rld_pctl_weak_s      cn58xxp1;
+};
+typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
+
+/**
+ * cvmx_asx#_rld_setting
+ *
+ * ASX_RLD_SETTING
+ *
+ */
+union cvmx_asxx_rld_setting
+{
+	uint64_t u64;
+	struct cvmx_asxx_rld_setting_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t dfaset                       : 5;  /**< RLD ClkGen DLL Setting(debug) */
+	uint64_t dfalag                       : 1;  /**< RLD ClkGen DLL Lag Error(debug) */
+	uint64_t dfalead                      : 1;  /**< RLD ClkGen DLL Lead Error(debug) */
+	uint64_t dfalock                      : 1;  /**< RLD ClkGen DLL Lock acquisition(debug) */
+	uint64_t setting                      : 5;  /**< RLDCK90 DLL Setting(debug) */
+#else
+	uint64_t setting                      : 5;
+	uint64_t dfalock                      : 1;
+	uint64_t dfalead                      : 1;
+	uint64_t dfalag                       : 1;
+	uint64_t dfaset                       : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_asxx_rld_setting_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< This is the read-only true rld dll_setting. */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn38xx;
+	struct cvmx_asxx_rld_setting_cn38xx   cn38xxp2;
+	struct cvmx_asxx_rld_setting_s        cn58xx;
+	struct cvmx_asxx_rld_setting_s        cn58xxp1;
+};
+typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
+
+/**
+ * cvmx_asx#_rx_clk_set#
+ *
+ * ASX_RX_CLK_SET = RGMII Clock delay setting
+ *
+ *
+ * Notes:
+ * Setting to place on the open-loop RXC (RGMII receive clk)
+ * delay line, which can delay the recieved clock. This
+ * can be used if the board and/or transmitting device
+ * has not otherwise delayed the clock.
+ *
+ * A value of SETTING=0 disables the delay line. The delay
+ * line should be disabled unless the transmitter or board
+ * does not delay the clock.
+ *
+ * Note that this delay line provides only a coarse control
+ * over the delay. Generally, it can only reliably provide
+ * a delay in the range 1.25-2.5ns, which may not be adequate
+ * for some system applications.
+ *
+ * The open loop delay line selects
+ * from among a series of tap positions. Each incremental
+ * tap position adds a delay of 50ps to 135ps per tap, depending
+ * on the chip, its temperature, and the voltage.
+ * To achieve from 1.25-2.5ns of delay on the recieved
+ * clock, a fixed value of SETTING=24 may work.
+ * For more precision, we recommend the following settings
+ * based on the chip voltage:
+ *
+ *    VDD           SETTING
+ *  -----------------------------
+ *    1.0             18
+ *    1.05            19
+ *    1.1             21
+ *    1.15            22
+ *    1.2             23
+ *    1.25            24
+ *    1.3             25
+ */
+union cvmx_asxx_rx_clk_setx
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_clk_setx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< Setting to place on the open-loop RXC delay line */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_rx_clk_setx_s        cn30xx;
+	struct cvmx_asxx_rx_clk_setx_s        cn31xx;
+	struct cvmx_asxx_rx_clk_setx_s        cn38xx;
+	struct cvmx_asxx_rx_clk_setx_s        cn38xxp2;
+	struct cvmx_asxx_rx_clk_setx_s        cn50xx;
+	struct cvmx_asxx_rx_clk_setx_s        cn58xx;
+	struct cvmx_asxx_rx_clk_setx_s        cn58xxp1;
+};
+typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
+
+/**
+ * cvmx_asx#_rx_prt_en
+ *
+ * ASX_RX_PRT_EN = RGMII Port Enable
+ *
+ */
+union cvmx_asxx_rx_prt_en
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_prt_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+	uint64_t prt_en                       : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_asxx_rx_prt_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+	uint64_t prt_en                       : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_rx_prt_en_cn30xx     cn31xx;
+	struct cvmx_asxx_rx_prt_en_s          cn38xx;
+	struct cvmx_asxx_rx_prt_en_s          cn38xxp2;
+	struct cvmx_asxx_rx_prt_en_cn30xx     cn50xx;
+	struct cvmx_asxx_rx_prt_en_s          cn58xx;
+	struct cvmx_asxx_rx_prt_en_s          cn58xxp1;
+};
+typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
+
+/**
+ * cvmx_asx#_rx_wol
+ *
+ * ASX_RX_WOL = RGMII RX Wake on LAN status register
+ *
+ */
+union cvmx_asxx_rx_wol
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_wol_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t status                       : 1;  /**< Copy of PMCSR[15] - PME_status */
+	uint64_t enable                       : 1;  /**< Copy of PMCSR[8]  - PME_enable */
+#else
+	uint64_t enable                       : 1;
+	uint64_t status                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_asxx_rx_wol_s             cn38xx;
+	struct cvmx_asxx_rx_wol_s             cn38xxp2;
+};
+typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
+
+/**
+ * cvmx_asx#_rx_wol_msk
+ *
+ * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
+ *
+ */
+union cvmx_asxx_rx_wol_msk
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_wol_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t msk                          : 64; /**< Bytes to include in the CRC signature */
+#else
+	uint64_t msk                          : 64;
+#endif
+	} s;
+	struct cvmx_asxx_rx_wol_msk_s         cn38xx;
+	struct cvmx_asxx_rx_wol_msk_s         cn38xxp2;
+};
+typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
+
+/**
+ * cvmx_asx#_rx_wol_powok
+ *
+ * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
+ *
+ */
+union cvmx_asxx_rx_wol_powok
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_wol_powok_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t powerok                      : 1;  /**< Power OK */
+#else
+	uint64_t powerok                      : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_asxx_rx_wol_powok_s       cn38xx;
+	struct cvmx_asxx_rx_wol_powok_s       cn38xxp2;
+};
+typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
+
+/**
+ * cvmx_asx#_rx_wol_sig
+ *
+ * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
+ *
+ */
+union cvmx_asxx_rx_wol_sig
+{
+	uint64_t u64;
+	struct cvmx_asxx_rx_wol_sig_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t sig                          : 32; /**< CRC signature */
+#else
+	uint64_t sig                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_asxx_rx_wol_sig_s         cn38xx;
+	struct cvmx_asxx_rx_wol_sig_s         cn38xxp2;
+};
+typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
+
+/**
+ * cvmx_asx#_tx_clk_set#
+ *
+ * ASX_TX_CLK_SET = RGMII Clock delay setting
+ *
+ *
+ * Notes:
+ * Setting to place on the open-loop TXC (RGMII transmit clk)
+ * delay line, which can delay the transmited clock. This
+ * can be used if the board and/or transmitting device
+ * has not otherwise delayed the clock.
+ *
+ * A value of SETTING=0 disables the delay line. The delay
+ * line should be disabled unless the transmitter or board
+ * does not delay the clock.
+ *
+ * Note that this delay line provides only a coarse control
+ * over the delay. Generally, it can only reliably provide
+ * a delay in the range 1.25-2.5ns, which may not be adequate
+ * for some system applications.
+ *
+ * The open loop delay line selects
+ * from among a series of tap positions. Each incremental
+ * tap position adds a delay of 50ps to 135ps per tap, depending
+ * on the chip, its temperature, and the voltage.
+ * To achieve from 1.25-2.5ns of delay on the recieved
+ * clock, a fixed value of SETTING=24 may work.
+ * For more precision, we recommend the following settings
+ * based on the chip voltage:
+ *
+ *    VDD           SETTING
+ *  -----------------------------
+ *    1.0             18
+ *    1.05            19
+ *    1.1             21
+ *    1.15            22
+ *    1.2             23
+ *    1.25            24
+ *    1.3             25
+ */
+union cvmx_asxx_tx_clk_setx
+{
+	uint64_t u64;
+	struct cvmx_asxx_tx_clk_setx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t setting                      : 5;  /**< Setting to place on the open-loop TXC delay line */
+#else
+	uint64_t setting                      : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_asxx_tx_clk_setx_s        cn30xx;
+	struct cvmx_asxx_tx_clk_setx_s        cn31xx;
+	struct cvmx_asxx_tx_clk_setx_s        cn38xx;
+	struct cvmx_asxx_tx_clk_setx_s        cn38xxp2;
+	struct cvmx_asxx_tx_clk_setx_s        cn50xx;
+	struct cvmx_asxx_tx_clk_setx_s        cn58xx;
+	struct cvmx_asxx_tx_clk_setx_s        cn58xxp1;
+};
+typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
+
+/**
+ * cvmx_asx#_tx_comp_byp
+ *
+ * ASX_TX_COMP_BYP = RGMII Clock delay setting
+ *
+ */
+union cvmx_asxx_tx_comp_byp
+{
+	uint64_t u64;
+	struct cvmx_asxx_tx_comp_byp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_asxx_tx_comp_byp_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t bypass                       : 1;  /**< Compensation bypass */
+	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
+	uint64_t nctl                         : 4;  /**< NCTL Compensation Value (see Duke) */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 4;
+	uint64_t bypass                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_tx_comp_byp_cn30xx   cn31xx;
+	struct cvmx_asxx_tx_comp_byp_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
+	uint64_t nctl                         : 4;  /**< NCTL Compensation Value (see Duke) */
+#else
+	uint64_t nctl                         : 4;
+	uint64_t pctl                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn38xx;
+	struct cvmx_asxx_tx_comp_byp_cn38xx   cn38xxp2;
+	struct cvmx_asxx_tx_comp_byp_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t bypass                       : 1;  /**< Compensation bypass */
+	uint64_t reserved_13_15               : 3;
+	uint64_t pctl                         : 5;  /**< PCTL Compensation Value (see Duke) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 5;  /**< NCTL Compensation Value (see Duke) */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t bypass                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn50xx;
+	struct cvmx_asxx_tx_comp_byp_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t pctl                         : 5;  /**< PCTL Compensation Value (see Duke) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 5;  /**< NCTL Compensation Value (see Duke) */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn58xx;
+	struct cvmx_asxx_tx_comp_byp_cn58xx   cn58xxp1;
+};
+typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
+
+/**
+ * cvmx_asx#_tx_hi_water#
+ *
+ * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
+ *
+ */
+union cvmx_asxx_tx_hi_waterx
+{
+	uint64_t u64;
+	struct cvmx_asxx_tx_hi_waterx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t mark                         : 4;  /**< TX FIFO HiWatermark to stall GMX
+                                                         Value of 0 maps to 16
+                                                         Reset value changed from 10 in pass1
+                                                         Pass1 settings (assuming 125 tclk)
+                                                         - 325-375: 12
+                                                         - 375-437: 11
+                                                         - 437-550: 10
+                                                         - 550-687:  9 */
+#else
+	uint64_t mark                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_asxx_tx_hi_waterx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t mark                         : 3;  /**< TX FIFO HiWatermark to stall GMX
+                                                         Value 0 maps to 8. */
+#else
+	uint64_t mark                         : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_tx_hi_waterx_cn30xx  cn31xx;
+	struct cvmx_asxx_tx_hi_waterx_s       cn38xx;
+	struct cvmx_asxx_tx_hi_waterx_s       cn38xxp2;
+	struct cvmx_asxx_tx_hi_waterx_cn30xx  cn50xx;
+	struct cvmx_asxx_tx_hi_waterx_s       cn58xx;
+	struct cvmx_asxx_tx_hi_waterx_s       cn58xxp1;
+};
+typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
+
+/**
+ * cvmx_asx#_tx_prt_en
+ *
+ * ASX_TX_PRT_EN = RGMII Port Enable
+ *
+ */
+union cvmx_asxx_tx_prt_en
+{
+	uint64_t u64;
+	struct cvmx_asxx_tx_prt_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+	uint64_t prt_en                       : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_asxx_tx_prt_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+	uint64_t prt_en                       : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_asxx_tx_prt_en_cn30xx     cn31xx;
+	struct cvmx_asxx_tx_prt_en_s          cn38xx;
+	struct cvmx_asxx_tx_prt_en_s          cn38xxp2;
+	struct cvmx_asxx_tx_prt_en_cn30xx     cn50xx;
+	struct cvmx_asxx_tx_prt_en_s          cn58xx;
+	struct cvmx_asxx_tx_prt_en_s          cn58xxp1;
+};
+typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-atomic.h b/sys/contrib/octeon-sdk/cvmx-atomic.h
index 6446130..7ec5c23 100644
--- a/sys/contrib/octeon-sdk/cvmx-atomic.h
+++ b/sys/contrib/octeon-sdk/cvmx-atomic.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file provides atomic operations
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
@@ -353,18 +355,48 @@ static inline int64_t cvmx_atomic_fetch_and_add64_nosync(int64_t *ptr, int64_t i
 {
     uint64_t tmp, ret;
 
-    __asm__ __volatile__(
-    ".set noreorder          \n"
-    "1: lld   %[tmp], %[val] \n"
-    "   move  %[ret], %[tmp] \n"
-    "   daddu %[tmp], %[inc] \n"
-    "   scd   %[tmp], %[val] \n"
-    "   beqz  %[tmp], 1b     \n"
-    "   nop                  \n"
-    ".set reorder            \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [inc] "r" (incr)
-    : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+	CVMX_PUSH_OCTEON2;
+	if (__builtin_constant_p(incr) && incr == 1)
+	{
+	    __asm__ __volatile__(
+		"laid  %0,(%2)"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr) : "memory");
+	}
+	else if (__builtin_constant_p(incr) && incr == -1)
+        {
+	    __asm__ __volatile__(
+		"ladd  %0,(%2)"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr) : "memory");
+        }
+        else
+        {
+	    __asm__ __volatile__(
+		"laad  %0,(%2),%3"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr), "r" (incr) : "memory");
+        }
+	CVMX_POP_OCTEON2;
+    }
+    else
+    {
+#endif
+        __asm__ __volatile__(
+            ".set noreorder          \n"
+            "1: lld   %[tmp], %[val] \n"
+            "   move  %[ret], %[tmp] \n"
+            "   daddu %[tmp], %[inc] \n"
+            "   scd   %[tmp], %[val] \n"
+            "   beqz  %[tmp], 1b     \n"
+            "   nop                  \n"
+            ".set reorder            \n"
+            : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+            : [inc] "r" (incr)
+            : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    }
+#endif
 
     return (ret);
 }
@@ -408,18 +440,48 @@ static inline int32_t cvmx_atomic_fetch_and_add32_nosync(int32_t *ptr, int32_t i
 {
     uint32_t tmp, ret;
 
-    __asm__ __volatile__(
-    ".set noreorder         \n"
-    "1: ll   %[tmp], %[val] \n"
-    "   move %[ret], %[tmp] \n"
-    "   addu %[tmp], %[inc] \n"
-    "   sc   %[tmp], %[val] \n"
-    "   beqz %[tmp], 1b     \n"
-    "   nop                 \n"
-    ".set reorder           \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [inc] "r" (incr)
-    : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+	CVMX_PUSH_OCTEON2;
+	if (__builtin_constant_p(incr) && incr == 1)
+	{
+	    __asm__ __volatile__(
+		"lai  %0,(%2)"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr) : "memory");
+	}
+	else if (__builtin_constant_p(incr) && incr == -1)
+        {
+	    __asm__ __volatile__(
+		"lad  %0,(%2)"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr) : "memory");
+        }
+        else
+        {
+	    __asm__ __volatile__(
+		"laa  %0,(%2),%3"
+		: "=r" (ret), "+m" (ptr) : "r" (ptr), "r" (incr) : "memory");
+        }
+	CVMX_POP_OCTEON2;
+    }
+    else
+    {
+#endif
+        __asm__ __volatile__(
+            ".set noreorder         \n"
+            "1: ll   %[tmp], %[val] \n"
+            "   move %[ret], %[tmp] \n"
+            "   addu %[tmp], %[inc] \n"
+            "   sc   %[tmp], %[val] \n"
+            "   beqz %[tmp], 1b     \n"
+            "   nop                 \n"
+            ".set reorder           \n"
+            : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+            : [inc] "r" (incr)
+            : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    }
+#endif
 
     return (ret);
 }
@@ -538,9 +600,8 @@ static inline uint64_t cvmx_atomic_fetch_and_bclr64_nosync(uint64_t *ptr, uint64
     "   beqz %[tmp], 1b     \n"
     "   nop                 \n"
     ".set reorder           \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [msk] "r" (mask)
-    : "memory");
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret), [msk] "+r" (mask)
+    : : "memory");
 
     return (ret);
 }
@@ -572,9 +633,8 @@ static inline uint32_t cvmx_atomic_fetch_and_bclr32_nosync(uint32_t *ptr, uint32
     "   beqz %[tmp], 1b     \n"
     "   nop                 \n"
     ".set reorder           \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [msk] "r" (mask)
-    : "memory");
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret), [msk] "+r" (mask)
+    : : "memory");
 
     return (ret);
 }
@@ -596,17 +656,47 @@ static inline uint64_t cvmx_atomic_swap64_nosync(uint64_t *ptr, uint64_t new_val
 {
     uint64_t tmp, ret;
 
-    __asm__ __volatile__(
-    ".set noreorder         \n"
-    "1: lld  %[ret], %[val] \n"
-    "   move %[tmp], %[new_val] \n"
-    "   scd  %[tmp], %[val] \n"
-    "   beqz %[tmp],  1b    \n"
-    "   nop                 \n"
-    ".set reorder           \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [new_val] "r"  (new_val)
-    : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+	CVMX_PUSH_OCTEON2;
+	if (__builtin_constant_p(new_val) && new_val == 0)
+	{
+	    __asm__ __volatile__(
+		"lacd  %0,(%1)"
+		: "=r" (ret) : "r" (ptr) : "memory");
+	}
+	else if (__builtin_constant_p(new_val) && new_val == ~0ull)
+        {
+	    __asm__ __volatile__(
+		"lasd  %0,(%1)"
+		: "=r" (ret) : "r" (ptr) : "memory");
+        }
+        else
+        {
+	    __asm__ __volatile__(
+		"lawd  %0,(%1),%2"
+		: "=r" (ret) : "r" (ptr), "r" (new_val) : "memory");
+        }
+	CVMX_POP_OCTEON2;
+    }
+    else
+    {
+#endif
+        __asm__ __volatile__(
+            ".set noreorder         \n"
+            "1: lld  %[ret], %[val] \n"
+            "   move %[tmp], %[new_val] \n"
+            "   scd  %[tmp], %[val] \n"
+            "   beqz %[tmp],  1b    \n"
+            "   nop                 \n"
+            ".set reorder           \n"
+            : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+            : [new_val] "r"  (new_val)
+            : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    }
+#endif
 
     return (ret);
 }
@@ -628,17 +718,47 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
 {
     uint32_t tmp, ret;
 
-    __asm__ __volatile__(
-    ".set noreorder         \n"
-    "1: ll   %[ret], %[val] \n"
-    "   move %[tmp], %[new_val] \n"
-    "   sc   %[tmp], %[val] \n"
-    "   beqz %[tmp],  1b    \n"
-    "   nop                 \n"
-    ".set reorder           \n"
-    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
-    : [new_val] "r"  (new_val)
-    : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+	CVMX_PUSH_OCTEON2;
+	if (__builtin_constant_p(new_val) && new_val == 0)
+	{
+	    __asm__ __volatile__(
+		"lac  %0,(%1)"
+		: "=r" (ret) : "r" (ptr) : "memory");
+	}
+	else if (__builtin_constant_p(new_val) && new_val == ~0u)
+        {
+	    __asm__ __volatile__(
+		"las  %0,(%1)"
+		: "=r" (ret) : "r" (ptr) : "memory");
+        }
+        else
+        {
+	    __asm__ __volatile__(
+		"law  %0,(%1),%2"
+		: "=r" (ret) : "r" (ptr), "r" (new_val) : "memory");
+        }
+	CVMX_POP_OCTEON2;
+    }
+    else
+    {
+#endif
+        __asm__ __volatile__(
+        ".set noreorder         \n"
+        "1: ll   %[ret], %[val] \n"
+        "   move %[tmp], %[new_val] \n"
+        "   sc   %[tmp], %[val] \n"
+        "   beqz %[tmp],  1b    \n"
+        "   nop                 \n"
+        ".set reorder           \n"
+        : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+        : [new_val] "r"  (new_val)
+        : "memory");
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+    }
+#endif
 
     return (ret);
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-bootloader.h b/sys/contrib/octeon-sdk/cvmx-bootloader.h
index c1097aa..caf4609 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootloader.h
+++ b/sys/contrib/octeon-sdk/cvmx-bootloader.h
@@ -1,43 +1,45 @@
 /***********************license start***************
- *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
+
 #ifndef __CVMX_BOOTLOADER__
 #define __CVMX_BOOTLOADER__
 
@@ -48,7 +50,7 @@
  *
  * Bootloader definitions that are shared with other programs
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 
@@ -65,17 +67,18 @@
 #define BOOTLOADER_HEADER_MAX_SIZE      0x200 /* limited by the space to the next exception handler */
 
 #define BOOTLOADER_HEADER_CURRENT_MAJOR_REV 1
-#define BOOTLOADER_HEADER_CURRENT_MINOR_REV 1 
+#define BOOTLOADER_HEADER_CURRENT_MINOR_REV 2
+/* Revision history
+* 1.1  Initial released revision. (SDK 1.9)
+* 1.2  TLB based relocatable image (SDK 2.0)
+*
+*
+*/
 
 /* offsets to struct bootloader_header fields for assembly use */
-#define MAGIC_OFFST     8
-#define HCRC_OFFST      12
-#define HLEN_OFFST      16
-#define DLEN_OFFST      24
-#define DCRC_OFFST      28
-#define GOT_OFFST       48
+#define GOT_ADDRESS_OFFSET       48
 
-#define LOOKUP_STEP 8192
+#define LOOKUP_STEP (64*1024)
 
 #ifndef __ASSEMBLY__
 typedef struct bootloader_header
@@ -86,7 +89,7 @@ typedef struct bootloader_header
                             */
     uint32_t    nop_instr;  /* Must be 0x0 */
     uint32_t    magic; /* Magic number to identify header */
-    uint32_t    hcrc;  /* CRC of all of header excluding this field */ 
+    uint32_t    hcrc;  /* CRC of all of header excluding this field */
 
     uint16_t    hlen;  /* Length of header in bytes */
     uint16_t    maj_rev;  /* Major revision */
@@ -99,12 +102,11 @@ typedef struct bootloader_header
     uint32_t    flags;
     uint16_t    image_type;  /* Defined in bootloader_image_t enum */
     uint16_t    resv0;       /* pad */
- 
-    /* The next 4 fields are placed in compile-time, not by the utility */
-    uint32_t    got_address;   /* compiled got address position in the image */
-    uint32_t    got_num_entries; /* number of got entries */
-    uint32_t    compiled_start;  /* compaled start of the image address */
-    uint32_t    image_start;     /* relocated start of image address */
+
+    uint32_t    reserved1;
+    uint32_t    reserved2;
+    uint32_t    reserved3;
+    uint32_t    reserved4;
 
     char        comment_string[BOOTLOADER_HEADER_COMMENT_LEN];  /* Optional, for descriptive purposes */
     char        version_string[BOOTLOADER_HEADER_VERSION_LEN];  /* Optional, for descriptive purposes */
@@ -118,7 +120,7 @@ typedef struct bootloader_header
 
 typedef enum
 {
-    BL_HEADER_IMAGE_UKNOWN = 0x0,
+    BL_HEADER_IMAGE_UNKNOWN = 0x0,
     BL_HEADER_IMAGE_STAGE2,  /* Binary bootloader stage2 image (NAND boot) */
     BL_HEADER_IMAGE_STAGE3,  /* Binary bootloader stage3 image (NAND boot)*/
     BL_HEADER_IMAGE_NOR,     /* Binary bootloader for NOR boot */
@@ -136,6 +138,8 @@ typedef enum
 ** by stage1 and stage2. */
 #define MAX_NAND_SEARCH_ADDR   0x400000
 
+/* Maximum address to look for start of normal bootloader */
+#define MAX_NOR_SEARCH_ADDR   0x100000
 
 /* Defines for RAM based environment set by the host or the previous bootloader
 ** in a chain boot configuration. */
diff --git a/sys/contrib/octeon-sdk/cvmx-bootmem.c b/sys/contrib/octeon-sdk/cvmx-bootmem.c
index 55aea60..2873bc0 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootmem.c
+++ b/sys/contrib/octeon-sdk/cvmx-bootmem.c
@@ -1,62 +1,72 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52119 $<hr>
  *
  */
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#endif
 #include "cvmx.h"
-#include "cvmx-spinlock.h"
 #include "cvmx-bootmem.h"
+#endif
+typedef uint32_t cvmx_spinlock_t;
 
 
 //#define DEBUG
 
-
+#define ULL unsigned long long
 #undef	MAX
 #define MAX(a, b)  (((a) > (b)) ? (a) : (b))
 
@@ -65,7 +75,192 @@
 
 #define ALIGN_ADDR_UP(addr, align)     (((addr) + (~(align))) & (align))
 
-static CVMX_SHARED cvmx_bootmem_desc_t *cvmx_bootmem_desc = NULL;
+/**
+ * This is the physical location of a cvmx_bootmem_desc_t
+ * structure in Octeon's memory. Note that dues to addressing
+ * limits or runtime environment it might not be possible to
+ * create a C pointer to this structure.
+ */
+static CVMX_SHARED uint64_t cvmx_bootmem_desc_addr = 0;
+
+/**
+ * This macro returns the size of a member of a structure.
+ * Logically it is the same as "sizeof(s::field)" in C++, but
+ * C lacks the "::" operator.
+ */
+#define SIZEOF_FIELD(s, field) sizeof(((s*)NULL)->field)
+
+/**
+ * This macro returns a member of the cvmx_bootmem_desc_t
+ * structure. These members can't be directly addressed as
+ * they might be in memory not directly reachable. In the case
+ * where bootmem is compiled with LINUX_HOST, the structure
+ * itself might be located on a remote Octeon. The argument
+ * "field" is the member name of the cvmx_bootmem_desc_t to read.
+ * Regardless of the type of the field, the return type is always
+ * a uint64_t.
+ */
+#define CVMX_BOOTMEM_DESC_GET_FIELD(field)                          \
+    __cvmx_bootmem_desc_get(cvmx_bootmem_desc_addr,                 \
+        offsetof(cvmx_bootmem_desc_t, field),                       \
+        SIZEOF_FIELD(cvmx_bootmem_desc_t, field))
+
+/**
+ * This macro writes a member of the cvmx_bootmem_desc_t
+ * structure. These members can't be directly addressed as
+ * they might be in memory not directly reachable. In the case
+ * where bootmem is compiled with LINUX_HOST, the structure
+ * itself might be located on a remote Octeon. The argument
+ * "field" is the member name of the cvmx_bootmem_desc_t to write.
+ */
+#define CVMX_BOOTMEM_DESC_SET_FIELD(field, value)                   \
+    __cvmx_bootmem_desc_set(cvmx_bootmem_desc_addr,                 \
+        offsetof(cvmx_bootmem_desc_t, field),                       \
+        SIZEOF_FIELD(cvmx_bootmem_desc_t, field), value)
+
+/**
+ * This macro returns a member of the
+ * cvmx_bootmem_named_block_desc_t structure. These members can't
+ * be directly addressed as they might be in memory not directly
+ * reachable. In the case where bootmem is compiled with
+ * LINUX_HOST, the structure itself might be located on a remote
+ * Octeon. The argument "field" is the member name of the
+ * cvmx_bootmem_named_block_desc_t to read. Regardless of the type
+ * of the field, the return type is always a uint64_t. The "addr"
+ * parameter is the physical address of the structure.
+ */
+#define CVMX_BOOTMEM_NAMED_GET_FIELD(addr, field)                   \
+    __cvmx_bootmem_desc_get(addr,                                   \
+        offsetof(cvmx_bootmem_named_block_desc_t, field),           \
+        SIZEOF_FIELD(cvmx_bootmem_named_block_desc_t, field))
+
+/**
+ * This macro writes a member of the cvmx_bootmem_named_block_desc_t
+ * structure. These members can't be directly addressed as
+ * they might be in memory not directly reachable. In the case
+ * where bootmem is compiled with LINUX_HOST, the structure
+ * itself might be located on a remote Octeon. The argument
+ * "field" is the member name of the
+ * cvmx_bootmem_named_block_desc_t to write. The "addr" parameter
+ * is the physical address of the structure.
+ */
+#define CVMX_BOOTMEM_NAMED_SET_FIELD(addr, field, value)            \
+    __cvmx_bootmem_desc_set(addr,                                   \
+        offsetof(cvmx_bootmem_named_block_desc_t, field),           \
+        SIZEOF_FIELD(cvmx_bootmem_named_block_desc_t, field), value)
+
+/**
+ * This function is the implementation of the get macros defined
+ * for individual structure members. The argument are generated
+ * by the macros inorder to read only the needed memory.
+ *
+ * @param base   64bit physical address of the complete structure
+ * @param offset Offset from the beginning of the structure to the member being
+ *               accessed.
+ * @param size   Size of the structure member.
+ *
+ * @return Value of the structure member promoted into a uint64_t.
+ */
+static inline uint64_t __cvmx_bootmem_desc_get(uint64_t base, int offset, int size)
+{
+    base = (1ull << 63) | (base + offset);
+    switch (size)
+    {
+        case 4:
+            return cvmx_read64_uint32(base);
+        case 8:
+            return cvmx_read64_uint64(base);
+        default:
+            return 0;
+    }
+}
+
+/**
+ * This function is the implementation of the set macros defined
+ * for individual structure members. The argument are generated
+ * by the macros in order to write only the needed memory.
+ *
+ * @param base   64bit physical address of the complete structure
+ * @param offset Offset from the beginning of the structure to the member being
+ *               accessed.
+ * @param size   Size of the structure member.
+ * @param value  Value to write into the structure
+ */
+static inline void __cvmx_bootmem_desc_set(uint64_t base, int offset, int size, uint64_t value)
+{
+    base = (1ull << 63) | (base + offset);
+    switch (size)
+    {
+        case 4:
+            cvmx_write64_uint32(base, value);
+            break;
+        case 8:
+            cvmx_write64_uint64(base, value);
+            break;
+        default:
+            break;
+    }
+}
+
+/**
+ * This function retrieves the string name of a named block. It is
+ * more complicated than a simple memcpy() since the named block
+ * descriptor may not be directly accessable.
+ *
+ * @param addr   Physical address of the named block descriptor
+ * @param str    String to receive the named block string name
+ * @param len    Length of the string buffer, which must match the length
+ *               stored in the bootmem descriptor.
+ */
+static void CVMX_BOOTMEM_NAMED_GET_NAME(uint64_t addr, char *str, int len)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+    int l = len;
+    char *ptr = str;
+    addr |= (1ull << 63);
+    addr += offsetof(cvmx_bootmem_named_block_desc_t, name);
+    while (l--)
+        *ptr++ = cvmx_read64_uint8(addr++);
+    str[len] = 0;
+#else
+    extern void octeon_remote_read_mem(void *buffer, uint64_t physical_address, int length);
+    addr += offsetof(cvmx_bootmem_named_block_desc_t, name);
+    octeon_remote_read_mem(str, addr, len);
+    str[len] = 0;
+#endif
+}
+
+/**
+ * This function stores the string name of a named block. It is
+ * more complicated than a simple memcpy() since the named block
+ * descriptor may not be directly accessable.
+ *
+ * @param addr   Physical address of the named block descriptor
+ * @param str    String to store into the named block string name
+ * @param len    Length of the string buffer, which must match the length
+ *               stored in the bootmem descriptor.
+ */
+static void CVMX_BOOTMEM_NAMED_SET_NAME(uint64_t addr, const char *str, int len)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+    int l = len;
+    addr |= (1ull << 63);
+    addr += offsetof(cvmx_bootmem_named_block_desc_t, name);
+    while (l--)
+    {
+        if (l)
+            cvmx_write64_uint8(addr++, *str++);
+        else
+            cvmx_write64_uint8(addr++, 0);
+    }
+#else
+    extern void octeon_remote_write_mem(uint64_t physical_address, const void *buffer, int length);
+    char zero = 0;
+    addr += offsetof(cvmx_bootmem_named_block_desc_t, name);
+    octeon_remote_write_mem(addr, str, len-1);
+    octeon_remote_write_mem(addr+len-1, &zero, 1);
+#endif
+}
 
 /* See header file for descriptions of functions */
 
@@ -92,7 +287,101 @@ static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr)
     return(cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63)));
 }
 
+/**
+ * Check the version information on the bootmem descriptor
+ *
+ * @param exact_match
+ *               Exact major version to check against. A zero means
+ *               check that the version supports named blocks.
+ *
+ * @return Zero if the version is correct. Negative if the version is
+ *         incorrect. Failures also cause a message to be displayed.
+ */
+static int __cvmx_bootmem_check_version(int exact_match)
+{
+    int major_version;
+#ifdef CVMX_BUILD_FOR_LINUX_HOST
+    if (!cvmx_bootmem_desc_addr)
+        cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x24100);
+#endif
+    major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version);
+    if ((major_version > 3) || (exact_match && major_version != exact_match))
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: 0x%llx\n",
+            major_version, (int)CVMX_BOOTMEM_DESC_GET_FIELD(minor_version),
+            (ULL)cvmx_bootmem_desc_addr);
+        return -1;
+    }
+    else
+        return 0;
+}
+
+/**
+ * Get the low level bootmem descriptor lock. If no locking
+ * is specified in the flags, then nothing is done.
+ *
+ * @param flags  CVMX_BOOTMEM_FLAG_NO_LOCKING means this functions should do
+ *               nothing. This is used to support nested bootmem calls.
+ */
+static inline void __cvmx_bootmem_lock(uint32_t flags)
+{
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+    {
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+        /* Unfortunately we can't use the normal cvmx-spinlock code as the
+            memory for the bootmem descriptor may be not accessable by a C
+            pointer. We use a 64bit XKPHYS address to access the memory
+            directly */
+        uint64_t lock_addr = (1ull << 63) | (cvmx_bootmem_desc_addr + offsetof(cvmx_bootmem_desc_t, lock));
+        unsigned int tmp;
+
+        __asm__ __volatile__(
+        ".set noreorder         \n"
+        "1: ll   %[tmp], 0(%[addr])\n"
+        "   bnez %[tmp], 1b     \n"
+        "   li   %[tmp], 1      \n"
+        "   sc   %[tmp], 0(%[addr])\n"
+        "   beqz %[tmp], 1b     \n"
+        "   nop                \n"
+        ".set reorder           \n"
+        : [tmp] "=&r" (tmp)
+        : [addr] "r" (lock_addr)
+        : "memory");
+#endif
+    }
+}
+
+/**
+ * Release the low level bootmem descriptor lock. If no locking
+ * is specified in the flags, then nothing is done.
+ *
+ * @param flags  CVMX_BOOTMEM_FLAG_NO_LOCKING means this functions should do
+ *               nothing. This is used to support nested bootmem calls.
+ */
+static inline void __cvmx_bootmem_unlock(uint32_t flags)
+{
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+    {
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+        /* Unfortunately we can't use the normal cvmx-spinlock code as the
+            memory for the bootmem descriptor may be not accessable by a C
+            pointer. We use a 64bit XKPHYS address to access the memory
+            directly */
+        uint64_t lock_addr = (1ull << 63) | (cvmx_bootmem_desc_addr + offsetof(cvmx_bootmem_desc_t, lock));
+
+        CVMX_SYNCW;
+        __asm__ __volatile__("sw $0, 0(%[addr])\n"
+        :: [addr] "r" (lock_addr)
+        : "memory");
+        CVMX_SYNCW;
+#endif
+    }
+}
 
+/* Some of the cvmx-bootmem functions dealing with C pointers are not supported
+    when we are compiling for CVMX_BUILD_FOR_LINUX_HOST. This ifndef removes
+    these functions when they aren't needed */
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
 /* This functions takes an address range and adjusts it as necessary to
 ** match the ABI that is currently being used.  This is required to ensure
 ** that bootmem_alloc* functions only return valid pointers for 32 bit ABIs */
@@ -152,6 +441,9 @@ void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_t min_a
     else
         return NULL;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_bootmem_alloc_range);
+#endif
 
 void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment)
 {
@@ -163,8 +455,11 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
 {
     return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_bootmem_alloc);
+#endif
 
-void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, char *name)
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
 {
     int64_t addr;
 
@@ -176,23 +471,36 @@ void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t
         return NULL;
 
 }
-void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, char *name)
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, address, address + size, 0, name));
 }
-void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name));
 }
 
-int cvmx_bootmem_free_named(char *name)
+int cvmx_bootmem_free_named(const char *name)
 {
     return(cvmx_bootmem_phy_named_block_free(name, 0));
 }
+#endif
 
-cvmx_bootmem_named_block_desc_t * cvmx_bootmem_find_named_block(char *name)
+const cvmx_bootmem_named_block_desc_t *cvmx_bootmem_find_named_block(const char *name)
 {
-    return(cvmx_bootmem_phy_named_block_find(name, 0));
+    /* FIXME: Returning a single static object is probably a bad thing */
+    static cvmx_bootmem_named_block_desc_t desc;
+    uint64_t named_addr = cvmx_bootmem_phy_named_block_find(name, 0);
+    if (named_addr)
+    {
+        desc.base_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_addr, base_addr);
+        desc.size = CVMX_BOOTMEM_NAMED_GET_FIELD(named_addr, size);
+        strncpy(desc.name, name, sizeof(desc.name));
+        desc.name[sizeof(desc.name)-1] = 0;
+        return &desc;
+    }
+    else
+        return NULL;
 }
 
 void cvmx_bootmem_print_named(void)
@@ -200,11 +508,7 @@ void cvmx_bootmem_print_named(void)
     cvmx_bootmem_phy_named_block_print();
 }
 
-#if defined(__linux__) && defined(CVMX_ABI_N32)
-cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
-#endif
-
-int cvmx_bootmem_init(void *mem_desc_ptr)
+int cvmx_bootmem_init(uint64_t mem_desc_addr)
 {
     /* Verify that the size of cvmx_spinlock_t meets our assumptions */
     if (sizeof(cvmx_spinlock_t) != 4)
@@ -212,75 +516,8 @@ int cvmx_bootmem_init(void *mem_desc_ptr)
         cvmx_dprintf("ERROR: Unexpected size of cvmx_spinlock_t\n");
         return(-1);
     }
-
-    /* Here we set the global pointer to the bootmem descriptor block.  This pointer will
-    ** be used directly, so we will set it up to be directly usable by the application.
-    ** It is set up as follows for the various runtime/ABI combinations:
-    ** Linux 64 bit: Set XKPHYS bit
-    ** Linux 32 bit: use mmap to create mapping, use virtual address
-    ** CVMX 64 bit:  use physical address directly
-    ** CVMX 32 bit:  use physical address directly
-    ** Note that the CVMX environment assumes the use of 1-1 TLB mappings so that the physical addresses
-    ** can be used directly
-    */
-    if (!cvmx_bootmem_desc)
-    {
-#if defined(CVMX_BUILD_FOR_LINUX_USER) && defined(CVMX_ABI_N32)
-        void *base_ptr;
-        /* For 32 bit, we need to use mmap to create a mapping for the bootmem descriptor */
-        int dm_fd = open("/dev/mem", O_RDWR);
-        if (dm_fd < 0)
-        {
-            cvmx_dprintf("ERROR opening /dev/mem for boot descriptor mapping\n");
-            return(-1);
-        }
-
-        base_ptr = mmap(NULL,
-                        sizeof(cvmx_bootmem_desc_t) + sysconf(_SC_PAGESIZE),
-                        PROT_READ | PROT_WRITE,
-                        MAP_SHARED,
-                        dm_fd,
-                        ((off_t)mem_desc_ptr) & ~(sysconf(_SC_PAGESIZE) - 1));
-
-        if (MAP_FAILED == base_ptr)
-        {
-            cvmx_dprintf("Error mapping bootmem descriptor!\n");
-            close(dm_fd);
-            return(-1);
-        }
-
-        /* Adjust pointer to point to bootmem_descriptor, rather than start of page it is in */
-        cvmx_bootmem_desc =  (cvmx_bootmem_desc_t*)((char*)base_ptr + (((off_t)mem_desc_ptr) & (sysconf(_SC_PAGESIZE) - 1)));
-
-        /* Also setup mapping for named memory block desc. while we are at it.  Here we must keep another
-        ** pointer around, as the value in the bootmem descriptor is shared with other applications. */
-        base_ptr = mmap(NULL,
-                        sizeof(cvmx_bootmem_named_block_desc_t) * cvmx_bootmem_desc->named_block_num_blocks + sysconf(_SC_PAGESIZE),
-                        PROT_READ | PROT_WRITE,
-                        MAP_SHARED,
-                        dm_fd,
-                        ((off_t)cvmx_bootmem_desc->named_block_array_addr) & ~(sysconf(_SC_PAGESIZE) - 1));
-
-        close(dm_fd);
-
-        if (MAP_FAILED == base_ptr)
-        {
-            cvmx_dprintf("Error mapping named block descriptor!\n");
-            return(-1);
-        }
-
-        /* Adjust pointer to point to named block array, rather than start of page it is in */
-        linux32_named_block_array_ptr = (cvmx_bootmem_named_block_desc_t*)((char*)base_ptr + (((off_t)cvmx_bootmem_desc->named_block_array_addr) & (sysconf(_SC_PAGESIZE) - 1)));
-
-#elif (defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(CVMX_BUILD_FOR_LINUX_USER)) && defined(CVMX_ABI_64)
-        /* Set XKPHYS bit */
-        cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr));
-#else
-        cvmx_bootmem_desc = (cvmx_bootmem_desc_t*)mem_desc_ptr;
-#endif
-    }
-
-
+    if (!cvmx_bootmem_desc_addr)
+        cvmx_bootmem_desc_addr = mem_desc_addr;
     return(0);
 }
 
@@ -316,15 +553,11 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
 
 #ifdef DEBUG
     cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n",
-           (unsigned long long)req_size, (unsigned long long)address_min, (unsigned long long)address_max, (unsigned long long)alignment);
+           (ULL)req_size, (ULL)address_min, (ULL)address_max, (ULL)alignment);
 #endif
 
-    if (cvmx_bootmem_desc->major_version > 3)
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+    if (__cvmx_bootmem_check_version(0))
         goto error_out;
-    }
 
     /* Do a variety of checks to validate the arguments.  The allocator code will later assume
     ** that these checks have been made.  We validate that the requested constraints are not
@@ -369,9 +602,8 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
 
     /* Walk through the list entries - first fit found is returned */
 
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-    head_addr = cvmx_bootmem_desc->head_addr;
+    __cvmx_bootmem_lock(flags);
+    head_addr = CVMX_BOOTMEM_DESC_GET_FIELD(head_addr);
     ent_addr = head_addr;
     while (ent_addr)
     {
@@ -381,7 +613,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
         if (cvmx_bootmem_phy_get_next(ent_addr) && ent_addr > cvmx_bootmem_phy_get_next(ent_addr))
         {
             cvmx_dprintf("Internal bootmem_alloc() error: ent: 0x%llx, next: 0x%llx\n",
-                   (unsigned long long)ent_addr, (unsigned long long)cvmx_bootmem_phy_get_next(ent_addr));
+                   (ULL)ent_addr, (ULL)cvmx_bootmem_phy_get_next(ent_addr));
             goto error_out;
         }
 
@@ -430,10 +662,9 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
                 else
                 {
                     /* head of list being returned, so update head ptr */
-                    cvmx_bootmem_desc->head_addr = cvmx_bootmem_phy_get_next(ent_addr);
+                    CVMX_BOOTMEM_DESC_SET_FIELD(head_addr, cvmx_bootmem_phy_get_next(ent_addr));
                 }
-                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-                    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+                __cvmx_bootmem_unlock(flags);
                 return(desired_min_addr);
             }
 
@@ -458,8 +689,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
     }
 error_out:
     /* We didn't find anything, so return error */
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_unlock(flags);
     return(-1);
 }
 
@@ -472,23 +702,18 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
     int retval = 0;
 
 #ifdef DEBUG
-    cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n", (unsigned long long)phy_addr, (unsigned long long)size);
+    cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n", (ULL)phy_addr, (ULL)size);
 #endif
-    if (cvmx_bootmem_desc->major_version > 3)
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+    if (__cvmx_bootmem_check_version(0))
         return(0);
-    }
 
     /* 0 is not a valid size for this allocator */
     if (!size)
         return(0);
 
 
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-    cur_addr = cvmx_bootmem_desc->head_addr;
+    __cvmx_bootmem_lock(flags);
+    cur_addr = CVMX_BOOTMEM_DESC_GET_FIELD(head_addr);
     if (cur_addr == 0 || phy_addr < cur_addr)
     {
         /* add at front of list - special case with changing head ptr */
@@ -499,7 +724,7 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
             /* Add to front of existing first block */
             cvmx_bootmem_phy_set_next(phy_addr, cvmx_bootmem_phy_get_next(cur_addr));
             cvmx_bootmem_phy_set_size(phy_addr, cvmx_bootmem_phy_get_size(cur_addr) + size);
-            cvmx_bootmem_desc->head_addr = phy_addr;
+            CVMX_BOOTMEM_DESC_SET_FIELD(head_addr, phy_addr);
 
         }
         else
@@ -507,7 +732,7 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
             /* New block before first block */
             cvmx_bootmem_phy_set_next(phy_addr, cur_addr);  /* OK if cur_addr is 0 */
             cvmx_bootmem_phy_set_size(phy_addr, size);
-            cvmx_bootmem_desc->head_addr = phy_addr;
+            CVMX_BOOTMEM_DESC_SET_FIELD(head_addr, phy_addr);
         }
         retval = 1;
         goto bootmem_free_done;
@@ -575,8 +800,7 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
     retval = 1;
 
 bootmem_free_done:
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_unlock(flags);
     return(retval);
 
 }
@@ -587,11 +811,13 @@ void cvmx_bootmem_phy_list_print(void)
 {
     uint64_t addr;
 
-    addr = cvmx_bootmem_desc->head_addr;
-    cvmx_dprintf("\n\n\nPrinting bootmem block list, descriptor: %p,  head is 0x%llx\n",
-           cvmx_bootmem_desc, (unsigned long long)addr);
-    cvmx_dprintf("Descriptor version: %d.%d\n", (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version);
-    if (cvmx_bootmem_desc->major_version > 3)
+    addr = CVMX_BOOTMEM_DESC_GET_FIELD(head_addr);
+    cvmx_dprintf("\n\n\nPrinting bootmem block list, descriptor: 0x%llx,  head is 0x%llx\n",
+           (ULL)cvmx_bootmem_desc_addr, (ULL)addr);
+    cvmx_dprintf("Descriptor version: %d.%d\n",
+        (int)CVMX_BOOTMEM_DESC_GET_FIELD(major_version),
+        (int)CVMX_BOOTMEM_DESC_GET_FIELD(minor_version));
+    if (CVMX_BOOTMEM_DESC_GET_FIELD(major_version) > 3)
     {
         cvmx_dprintf("Warning: Bootmem descriptor version is newer than expected\n");
     }
@@ -602,9 +828,9 @@ void cvmx_bootmem_phy_list_print(void)
     while (addr)
     {
         cvmx_dprintf("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
-               (unsigned long long)addr,
-               (unsigned long long)cvmx_bootmem_phy_get_size(addr),
-               (unsigned long long)cvmx_bootmem_phy_get_next(addr));
+               (ULL)addr,
+               (ULL)cvmx_bootmem_phy_get_size(addr),
+               (ULL)cvmx_bootmem_phy_get_next(addr));
         addr = cvmx_bootmem_phy_get_next(addr);
     }
     cvmx_dprintf("\n\n");
@@ -618,155 +844,130 @@ uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size)
 
     uint64_t available_mem = 0;
 
-    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-    addr = cvmx_bootmem_desc->head_addr;
+    __cvmx_bootmem_lock(0);
+    addr = CVMX_BOOTMEM_DESC_GET_FIELD(head_addr);
     while (addr)
     {
         if (cvmx_bootmem_phy_get_size(addr) >= min_block_size)
             available_mem += cvmx_bootmem_phy_get_size(addr);
         addr = cvmx_bootmem_phy_get_next(addr);
     }
-    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_unlock(0);
     return(available_mem);
 
 }
 
 
 
-cvmx_bootmem_named_block_desc_t * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags)
+uint64_t cvmx_bootmem_phy_named_block_find(const char *name, uint32_t flags)
 {
-    unsigned int i;
-    cvmx_bootmem_named_block_desc_t *named_block_array_ptr;
-
+    uint64_t result = 0;
 
 #ifdef DEBUG
     cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name);
 #endif
-    /* Lock the structure to make sure that it is not being changed while we are
-    ** examining it.
-    */
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
-#if defined(__linux__) && !defined(CONFIG_OCTEON_U_BOOT)
-#ifdef CVMX_ABI_N32
-    /* Need to use mmapped named block pointer in 32 bit linux apps */
-extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
-    named_block_array_ptr = linux32_named_block_array_ptr;
-#else
-    /* Use XKPHYS for 64 bit linux */
-    named_block_array_ptr = (cvmx_bootmem_named_block_desc_t *)cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
-#endif
-#else
-    /* Simple executive case. (and u-boot)
-    ** This could be in the low 1 meg of memory that is not 1-1 mapped, so we need use XKPHYS/KSEG0 addressing for it */
-    named_block_array_ptr = CASTPTR(cvmx_bootmem_named_block_desc_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,cvmx_bootmem_desc->named_block_array_addr));
-#endif
-
-#ifdef DEBUG
-    cvmx_dprintf("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n", named_block_array_ptr);
-#endif
-    if (cvmx_bootmem_desc->major_version == 3)
+    __cvmx_bootmem_lock(flags);
+    if (!__cvmx_bootmem_check_version(3))
     {
-        for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++)
+        int i;
+        uint64_t named_block_array_addr = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_array_addr);
+        int num_blocks = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_num_blocks);
+        int name_length = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_name_len);
+        uint64_t named_addr = named_block_array_addr;
+        for (i = 0; i < num_blocks; i++)
         {
-            if ((name && named_block_array_ptr[i].size && !strncmp(name, named_block_array_ptr[i].name, cvmx_bootmem_desc->named_block_name_len - 1))
-                || (!name && !named_block_array_ptr[i].size))
+            uint64_t named_size = CVMX_BOOTMEM_NAMED_GET_FIELD(named_addr, size);
+            if (name && named_size)
             {
-                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-                    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
-                return(&(named_block_array_ptr[i]));
+                char name_tmp[name_length];
+                CVMX_BOOTMEM_NAMED_GET_NAME(named_addr, name_tmp, name_length);
+                if (!strncmp(name, name_tmp, name_length - 1))
+                {
+                    result = named_addr;
+                    break;
+                }
+            }
+            else if (!name && !named_size)
+            {
+                result = named_addr;
+                break;
             }
+            named_addr += sizeof(cvmx_bootmem_named_block_desc_t);
         }
     }
-    else
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
-    }
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
-    return(NULL);
+    __cvmx_bootmem_unlock(flags);
+    return result;
 }
 
-int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
+int cvmx_bootmem_phy_named_block_free(const char *name, uint32_t flags)
 {
-    cvmx_bootmem_named_block_desc_t *named_block_ptr;
+    uint64_t named_block_addr;
 
-    if (cvmx_bootmem_desc->major_version != 3)
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+    if (__cvmx_bootmem_check_version(3))
         return(0);
-    }
 #ifdef DEBUG
     cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name);
 #endif
 
     /* Take lock here, as name lookup/block free/name free need to be atomic */
-    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_lock(flags);
 
-    named_block_ptr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
-    if (named_block_ptr)
+    named_block_addr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    if (named_block_addr)
     {
+        uint64_t named_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, base_addr);
+        uint64_t named_size = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, size);
 #ifdef DEBUG
-        cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s, base: 0x%llx, size: 0x%llx\n", name, (unsigned long long)named_block_ptr->base_addr, (unsigned long long)named_block_ptr->size);
+        cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s, base: 0x%llx, size: 0x%llx\n",
+            name, (ULL)named_addr, (ULL)named_size);
 #endif
-        __cvmx_bootmem_phy_free(named_block_ptr->base_addr, named_block_ptr->size, CVMX_BOOTMEM_FLAG_NO_LOCKING);
-        named_block_ptr->size = 0;
+        __cvmx_bootmem_phy_free(named_addr, named_size, CVMX_BOOTMEM_FLAG_NO_LOCKING);
         /* Set size to zero to indicate block not used. */
+        CVMX_BOOTMEM_NAMED_SET_FIELD(named_block_addr, size, 0);
     }
-
-    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
-    return(!!named_block_ptr);  /* 0 on failure, 1 on success */
+    __cvmx_bootmem_unlock(flags);
+    return(!!named_block_addr);  /* 0 on failure, 1 on success */
 }
 
 
 
 
 
-int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, char *name, uint32_t flags)
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, const char *name, uint32_t flags)
 {
     int64_t addr_allocated;
-    cvmx_bootmem_named_block_desc_t *named_block_desc_ptr;
+    uint64_t named_block_desc_addr;
 
 #ifdef DEBUG
     cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: 0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
-                 (unsigned long long)size,
-                 (unsigned long long)min_addr,
-                 (unsigned long long)max_addr,
-                 (unsigned long long)alignment,
+                 (ULL)size,
+                 (ULL)min_addr,
+                 (ULL)max_addr,
+                 (ULL)alignment,
                  name);
 #endif
-    if (cvmx_bootmem_desc->major_version != 3)
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
-        return(-1);
-    }
 
+    if (__cvmx_bootmem_check_version(3))
+        return(-1);
 
     /* Take lock here, as name lookup/block alloc/name add need to be atomic */
 
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
-    /* Get pointer to first available named block descriptor */
-    named_block_desc_ptr = cvmx_bootmem_phy_named_block_find(NULL, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    __cvmx_bootmem_lock(flags);
 
-    /* Check to see if name already in use, return error if name
-    ** not available or no more room for blocks.
-    */
-    if (cvmx_bootmem_phy_named_block_find(name, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr)
+    named_block_desc_addr = cvmx_bootmem_phy_named_block_find(name, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    if (named_block_desc_addr)
     {
-        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-            cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+        __cvmx_bootmem_unlock(flags);
         return(-1);
     }
 
+    /* Get pointer to first available named block descriptor */
+    named_block_desc_addr = cvmx_bootmem_phy_named_block_find(NULL, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    if (!named_block_desc_addr)
+    {
+        __cvmx_bootmem_unlock(flags);
+        return(-1);
+    }
 
     /* Round size up to mult of minimum alignment bytes
     ** We need the actual size allocated to allow for blocks to be coallesced
@@ -777,15 +978,12 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uin
     addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
     if (addr_allocated >= 0)
     {
-        named_block_desc_ptr->base_addr = addr_allocated;
-        named_block_desc_ptr->size = size;
-        strncpy(named_block_desc_ptr->name, name, cvmx_bootmem_desc->named_block_name_len);
-        named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+        CVMX_BOOTMEM_NAMED_SET_FIELD(named_block_desc_addr, base_addr, addr_allocated);
+        CVMX_BOOTMEM_NAMED_SET_FIELD(named_block_desc_addr, size, size);
+        CVMX_BOOTMEM_NAMED_SET_NAME(named_block_desc_addr, name, CVMX_BOOTMEM_DESC_GET_FIELD(named_block_name_len));
     }
 
-    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
-        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
-
+    __cvmx_bootmem_unlock(flags);
     return(addr_allocated);
 }
 
@@ -794,45 +992,34 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uin
 
 void cvmx_bootmem_phy_named_block_print(void)
 {
-    unsigned int i;
+    int i;
     int printed = 0;
 
-#if defined(__linux__) && !defined(CONFIG_OCTEON_U_BOOT)
-#ifdef CVMX_ABI_N32
-    /* Need to use mmapped named block pointer in 32 bit linux apps */
-extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
-    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = linux32_named_block_array_ptr;
-#else
-    /* Use XKPHYS for 64 bit linux */
-    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = (cvmx_bootmem_named_block_desc_t *)cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
-#endif
-#else
-    /* Simple executive case. (and u-boot)
-    ** This could be in the low 1 meg of memory that is not 1-1 mapped, so we need use XKPHYS/KSEG0 addressing for it */
-    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = CASTPTR(cvmx_bootmem_named_block_desc_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,cvmx_bootmem_desc->named_block_array_addr));
-#endif
+    uint64_t named_block_array_addr = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_array_addr);
+    int num_blocks = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_num_blocks);
+    int name_length = CVMX_BOOTMEM_DESC_GET_FIELD(named_block_name_len);
+    uint64_t named_block_addr = named_block_array_addr;
+
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_bootmem_phy_named_block_print, desc addr: %p\n", cvmx_bootmem_desc);
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_print, desc addr: 0x%llx\n",
+        (ULL)cvmx_bootmem_desc_addr);
 #endif
-    if (cvmx_bootmem_desc->major_version != 3)
-    {
-        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
-               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+    if (__cvmx_bootmem_check_version(3))
         return;
-    }
     cvmx_dprintf("List of currently allocated named bootmem blocks:\n");
-    for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++)
+    for (i = 0; i < num_blocks; i++)
     {
-        if (named_block_array_ptr[i].size)
+        uint64_t named_size = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, size);
+        if (named_size)
         {
+            char name_tmp[name_length];
+            uint64_t named_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, base_addr);
+            CVMX_BOOTMEM_NAMED_GET_NAME(named_block_addr, name_tmp, name_length);
             printed++;
             cvmx_dprintf("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
-                   named_block_array_ptr[i].name,
-                   (unsigned long long)named_block_array_ptr[i].base_addr,
-                   (unsigned long long)named_block_array_ptr[i].size,
-                   i);
-
+                   name_tmp, (ULL)named_addr, (ULL)named_size, i);
         }
+        named_block_addr += sizeof(cvmx_bootmem_named_block_desc_t);
     }
     if (!printed)
     {
@@ -845,18 +1032,20 @@ extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
 /* Real physical addresses of memory regions */
 #define OCTEON_DDR0_BASE    (0x0ULL)
 #define OCTEON_DDR0_SIZE    (0x010000000ULL)
-#define OCTEON_DDR1_BASE    (0x410000000ULL)
+#define OCTEON_DDR1_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x20000000ULL : 0x410000000ULL)
 #define OCTEON_DDR1_SIZE    (0x010000000ULL)
-#define OCTEON_DDR2_BASE    (0x020000000ULL)
-#define OCTEON_DDR2_SIZE    (0x3e0000000ULL)
-#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
+#define OCTEON_DDR2_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x30000000ULL : 0x20000000ULL)
+#define OCTEON_DDR2_SIZE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x7d0000000ULL : 0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 32*1024*1024*1024ULL : 16*1024*1024*1024ULL)
 int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer)
 {
     uint64_t cur_block_addr;
     int64_t addr;
+    int i;
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init (arg desc ptr: %p, cvmx_bootmem_desc: %p)\n", desc_buffer, cvmx_bootmem_desc);
+    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init (arg desc ptr: %p, cvmx_bootmem_desc: 0x%llx)\n",
+        desc_buffer, (ULL)cvmx_bootmem_desc_addr);
 #endif
 
     /* Descriptor buffer needs to be in 32 bit addressable space to be compatible with
@@ -873,21 +1062,27 @@ int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_
         cvmx_dprintf("ERROR: requested memory size too large, truncating to maximum size\n");
     }
 
-    if (cvmx_bootmem_desc)
+    if (cvmx_bootmem_desc_addr)
         return 1;
 
     /* Initialize cvmx pointer to descriptor */
-    cvmx_bootmem_init(desc_buffer);
-
-    /* Set up global pointer to start of list, exclude low 64k for exception vectors, space for global descriptor */
-    memset(cvmx_bootmem_desc, 0x0, sizeof(cvmx_bootmem_desc_t));
-    /* Set version of bootmem descriptor */
-    cvmx_bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
-    cvmx_bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+    cvmx_bootmem_init(cvmx_ptr_to_phys(desc_buffer));
+#else
+    cvmx_bootmem_init((unsigned long)desc_buffer);
+#endif
 
-    cur_block_addr = cvmx_bootmem_desc->head_addr = (OCTEON_DDR0_BASE + low_reserved_bytes);
+    /* Fill the bootmem descriptor */
+    CVMX_BOOTMEM_DESC_SET_FIELD(lock, 0);
+    CVMX_BOOTMEM_DESC_SET_FIELD(flags, 0);
+    CVMX_BOOTMEM_DESC_SET_FIELD(head_addr, 0);
+    CVMX_BOOTMEM_DESC_SET_FIELD(major_version, CVMX_BOOTMEM_DESC_MAJ_VER);
+    CVMX_BOOTMEM_DESC_SET_FIELD(minor_version, CVMX_BOOTMEM_DESC_MIN_VER);
+    CVMX_BOOTMEM_DESC_SET_FIELD(app_data_addr, 0);
+    CVMX_BOOTMEM_DESC_SET_FIELD(app_data_size, 0);
 
-    cvmx_bootmem_desc->head_addr = 0;
+    /* Set up global pointer to start of list, exclude low 64k for exception vectors, space for global descriptor */
+    cur_block_addr = (OCTEON_DDR0_BASE + low_reserved_bytes);
 
     if (mem_size <= OCTEON_DDR0_SIZE)
     {
@@ -913,24 +1108,30 @@ int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_
 frees_done:
 
     /* Initialize the named block structure */
-    cvmx_bootmem_desc->named_block_name_len = CVMX_BOOTMEM_NAME_LEN;
-    cvmx_bootmem_desc->named_block_num_blocks = CVMX_BOOTMEM_NUM_NAMED_BLOCKS;
-    cvmx_bootmem_desc->named_block_array_addr = 0;
+    CVMX_BOOTMEM_DESC_SET_FIELD(named_block_name_len, CVMX_BOOTMEM_NAME_LEN);
+    CVMX_BOOTMEM_DESC_SET_FIELD(named_block_num_blocks, CVMX_BOOTMEM_NUM_NAMED_BLOCKS);
+    CVMX_BOOTMEM_DESC_SET_FIELD(named_block_array_addr, 0);
 
     /* Allocate this near the top of the low 256 MBytes of memory */
     addr = cvmx_bootmem_phy_alloc(CVMX_BOOTMEM_NUM_NAMED_BLOCKS * sizeof(cvmx_bootmem_named_block_desc_t),0, 0x10000000, 0 ,CVMX_BOOTMEM_FLAG_END_ALLOC);
     if (addr >= 0)
-        cvmx_bootmem_desc->named_block_array_addr = addr;
+        CVMX_BOOTMEM_DESC_SET_FIELD(named_block_array_addr, addr);
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init: named_block_array_addr: 0x%llx)\n", (unsigned long long)cvmx_bootmem_desc->named_block_array_addr);
+    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init: named_block_array_addr: 0x%llx)\n",
+        (ULL)addr);
 #endif
-    if (!cvmx_bootmem_desc->named_block_array_addr)
+    if (!addr)
     {
         cvmx_dprintf("FATAL ERROR: unable to allocate memory for bootmem descriptor!\n");
         return(0);
     }
-    memset((void *)(unsigned long)cvmx_bootmem_desc->named_block_array_addr, 0x0, CVMX_BOOTMEM_NUM_NAMED_BLOCKS * sizeof(cvmx_bootmem_named_block_desc_t));
+    for (i=0; i<CVMX_BOOTMEM_NUM_NAMED_BLOCKS; i++)
+    {
+        CVMX_BOOTMEM_NAMED_SET_FIELD(addr, base_addr, 0);
+        CVMX_BOOTMEM_NAMED_SET_FIELD(addr, size, 0);
+        addr += sizeof(cvmx_bootmem_named_block_desc_t);
+    }
 
     return(1);
 }
@@ -938,15 +1139,17 @@ frees_done:
 
 void cvmx_bootmem_lock(void)
 {
-    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_lock(0);
 }
 
 void cvmx_bootmem_unlock(void)
 {
-    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    __cvmx_bootmem_unlock(0);
 }
 
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
 void *__cvmx_bootmem_internal_get_desc_ptr(void)
 {
-    return(cvmx_bootmem_desc);
+    return cvmx_phys_to_ptr(cvmx_bootmem_desc_addr);
 }
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-bootmem.h b/sys/contrib/octeon-sdk/cvmx-bootmem.h
index b44ea02..2f07990 100644
--- a/sys/contrib/octeon-sdk/cvmx-bootmem.h
+++ b/sys/contrib/octeon-sdk/cvmx-bootmem.h
@@ -1,51 +1,53 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -89,14 +91,14 @@ typedef struct
 ** Note: This structure must be naturally 64 bit aligned, as a single
 ** memory image will be used by both 32 and 64 bit programs.
 */
-typedef struct
+struct cvmx_bootmem_named_block_desc
 {
     uint64_t base_addr;     /**< Base address of named block */
     uint64_t size;          /**< Size actually allocated for named block (may differ from requested) */
     char name[CVMX_BOOTMEM_NAME_LEN];   /**< name of named block */
-} cvmx_bootmem_named_block_desc_t;
-
+};
 
+typedef struct cvmx_bootmem_named_block_desc cvmx_bootmem_named_block_desc_t;
 
 /* Current descriptor versions */
 #define CVMX_BOOTMEM_DESC_MAJ_VER   3   /* CVMX bootmem descriptor major version */
@@ -127,10 +129,10 @@ typedef struct
  * Initialize the boot alloc memory structures. This is
  * normally called inside of cvmx_user_app_init()
  *
- * @param mem_desc_ptr	Address of the free memory list
+ * @param mem_desc_addr	Address of the free memory list
  * @return
  */
-extern int cvmx_bootmem_init(void *mem_desc_ptr);
+extern int cvmx_bootmem_init(uint64_t mem_desc_addr);
 
 
 /**
@@ -190,7 +192,7 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_
  *
  * @return pointer to block of memory, NULL on error
  */
-extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name);
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name);
 
 
 
@@ -207,7 +209,7 @@ extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *n
  *
  * @return pointer to block of memory, NULL on error
  */
-extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, char *name);
+extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, const char *name);
 
 
 
@@ -226,7 +228,7 @@ extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, c
  *
  * @return pointer to block of memory, NULL on error
  */
-extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, char *name);
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name);
 
 /**
  * Frees a previously allocated named bootmem block.
@@ -236,7 +238,7 @@ extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, ui
  * @return 0 on failure,
  *         !0 on success
  */
-extern int cvmx_bootmem_free_named(char *name);
+extern int cvmx_bootmem_free_named(const char *name);
 
 
 /**
@@ -247,7 +249,7 @@ extern int cvmx_bootmem_free_named(char *name);
  * @return pointer to named block descriptor on success
  *         0 on failure
  */
-cvmx_bootmem_named_block_desc_t * cvmx_bootmem_find_named_block(char *name);
+const cvmx_bootmem_named_block_desc_t *cvmx_bootmem_find_named_block(const char *name);
 
 
 
@@ -310,7 +312,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
  *
  * @return physical address of block allocated, or -1 on failure
  */
-int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, char *name, uint32_t flags);
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, const char *name, uint32_t flags);
 
 
 /**
@@ -319,13 +321,13 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uin
  *
  * @param name   Name of memory block to find.
  *               If NULL pointer given, then finds unused descriptor, if available.
- * @param flags     Flags to control options for the allocation.
+ * @param flags  Flags to control options for the allocation.
  *
- * @return Pointer to memory block descriptor, NULL if not found.
- *         If NULL returned when name parameter is NULL, then no memory
- *         block descriptors are available.
+ * @return Physical address of the memory block descriptor, zero if not
+ *         found. If zero returned when name parameter is NULL, then no
+ *         memory block descriptors are available.
  */
-cvmx_bootmem_named_block_desc_t * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
+uint64_t cvmx_bootmem_phy_named_block_find(const char *name, uint32_t flags);
 
 
 /**
@@ -349,7 +351,7 @@ uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size);
  * @return 0 on failure
  *         1 on success
  */
-int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
+int cvmx_bootmem_phy_named_block_free(const char *name, uint32_t flags);
 
 /**
  * Frees a block to the bootmem allocator list.  This must
diff --git a/sys/contrib/octeon-sdk/cvmx-ciu-defs.h b/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
new file mode 100644
index 0000000..05c03ff
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
@@ -0,0 +1,5527 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-ciu-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon ciu.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_CIU_TYPEDEFS_H__
+#define __CVMX_CIU_TYPEDEFS_H__
+
+#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC()
+static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007C0ull);
+}
+#else
+#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
+#endif
+#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC()
+static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000110ull);
+}
+#else
+#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+		cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16;
+}
+#else
+#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32)))))
+		cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC()
+static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000007D0ull);
+}
+#else
+#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
+#endif
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
+#endif
+#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
+#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#endif
+#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC()
+static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000780ull);
+}
+#else
+#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC()
+static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000788ull);
+}
+#else
+#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC()
+static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000790ull);
+}
+#else
+#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
+static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000760ull);
+}
+#else
+#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000768ull);
+}
+#else
+#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000770ull);
+}
+#else
+#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
+#endif
+#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
+#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000758ull);
+}
+#else
+#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#endif
+#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
+#endif
+
+/**
+ * cvmx_ciu_bist
+ */
+union cvmx_ciu_bist
+{
+	uint64_t u64;
+	struct cvmx_ciu_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bist                         : 5;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_ciu_bist_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t bist                         : 4;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_bist_cn30xx           cn31xx;
+	struct cvmx_ciu_bist_cn30xx           cn38xx;
+	struct cvmx_ciu_bist_cn30xx           cn38xxp2;
+	struct cvmx_ciu_bist_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t bist                         : 2;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn50xx;
+	struct cvmx_ciu_bist_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t bist                         : 3;  /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_bist_cn52xx           cn52xxp1;
+	struct cvmx_ciu_bist_cn30xx           cn56xx;
+	struct cvmx_ciu_bist_cn30xx           cn56xxp1;
+	struct cvmx_ciu_bist_cn30xx           cn58xx;
+	struct cvmx_ciu_bist_cn30xx           cn58xxp1;
+	struct cvmx_ciu_bist_s                cn63xx;
+	struct cvmx_ciu_bist_s                cn63xxp1;
+};
+typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
+
+/**
+ * cvmx_ciu_block_int
+ *
+ * CIU_BLOCK_INT = CIU Blocks Interrupt
+ *
+ * The interrupt lines from the various chip blocks.
+ */
+union cvmx_ciu_block_int
+{
+	uint64_t u64;
+	struct cvmx_ciu_block_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_43_63               : 21;
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         See CIU_INT_SUM1[PTP] */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t dfm                          : 1;  /**< DFM interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_34_39               : 6;
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
+                                                         See SRIO1_INT_REG */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG */
+	uint64_t reserved_31_31               : 1;
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t reserved_29_29               : 1;
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_27_27               : 1;
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t reserved_23_24               : 2;
+	uint64_t asxpcs0                      : 1;  /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t reserved_18_19               : 2;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t gmx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t agl                          : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t reserved_34_39               : 6;
+	uint64_t dfm                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_ciu_block_int_s           cn63xx;
+	struct cvmx_ciu_block_int_s           cn63xxp1;
+};
+typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t;
+
+/**
+ * cvmx_ciu_dint
+ */
+union cvmx_ciu_dint
+{
+	uint64_t u64;
+	struct cvmx_ciu_dint_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dint                         : 16; /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu_dint_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t dint                         : 1;  /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_dint_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dint                         : 2;  /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_dint_s                cn38xx;
+	struct cvmx_ciu_dint_s                cn38xxp2;
+	struct cvmx_ciu_dint_cn31xx           cn50xx;
+	struct cvmx_ciu_dint_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t dint                         : 4;  /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_dint_cn52xx           cn52xxp1;
+	struct cvmx_ciu_dint_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t dint                         : 12; /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_dint_cn56xx           cn56xxp1;
+	struct cvmx_ciu_dint_s                cn58xx;
+	struct cvmx_ciu_dint_s                cn58xxp1;
+	struct cvmx_ciu_dint_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t dint                         : 6;  /**< Send DINT pulse to PP vector */
+#else
+	uint64_t dint                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_dint_cn63xx           cn63xxp1;
+};
+typedef union cvmx_ciu_dint cvmx_ciu_dint_t;
+
+/**
+ * cvmx_ciu_fuse
+ */
+union cvmx_ciu_fuse
+{
+	uint64_t u64;
+	struct cvmx_ciu_fuse_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t fuse                         : 16; /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu_fuse_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t fuse                         : 1;  /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_fuse_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t fuse                         : 2;  /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_fuse_s                cn38xx;
+	struct cvmx_ciu_fuse_s                cn38xxp2;
+	struct cvmx_ciu_fuse_cn31xx           cn50xx;
+	struct cvmx_ciu_fuse_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t fuse                         : 4;  /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_fuse_cn52xx           cn52xxp1;
+	struct cvmx_ciu_fuse_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t fuse                         : 12; /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_fuse_cn56xx           cn56xxp1;
+	struct cvmx_ciu_fuse_s                cn58xx;
+	struct cvmx_ciu_fuse_s                cn58xxp1;
+	struct cvmx_ciu_fuse_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t fuse                         : 6;  /**< Physical PP is present */
+#else
+	uint64_t fuse                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_fuse_cn63xx           cn63xxp1;
+};
+typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t;
+
+/**
+ * cvmx_ciu_gstop
+ */
+union cvmx_ciu_gstop
+{
+	uint64_t u64;
+	struct cvmx_ciu_gstop_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t gstop                        : 1;  /**< GSTOP bit */
+#else
+	uint64_t gstop                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_gstop_s               cn30xx;
+	struct cvmx_ciu_gstop_s               cn31xx;
+	struct cvmx_ciu_gstop_s               cn38xx;
+	struct cvmx_ciu_gstop_s               cn38xxp2;
+	struct cvmx_ciu_gstop_s               cn50xx;
+	struct cvmx_ciu_gstop_s               cn52xx;
+	struct cvmx_ciu_gstop_s               cn52xxp1;
+	struct cvmx_ciu_gstop_s               cn56xx;
+	struct cvmx_ciu_gstop_s               cn56xxp1;
+	struct cvmx_ciu_gstop_s               cn58xx;
+	struct cvmx_ciu_gstop_s               cn58xxp1;
+	struct cvmx_ciu_gstop_s               cn63xx;
+	struct cvmx_ciu_gstop_s               cn63xxp1;
+};
+typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
+
+/**
+ * cvmx_ciu_int#_en0
+ *
+ * Notes:
+ * CIU_INT0_EN0:  PP0 /IP2
+ * CIU_INT1_EN0:  PP0 /IP3
+ * ...
+ * CIU_INT6_EN0:  PP3/IP2
+ * CIU_INT7_EN0:  PP3/IP3
+ * (hole)
+ * CIU_INT32_EN0: PCI /IP
+ */
+union cvmx_ciu_intx_en0
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCIe/sRIO interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t reserved_47_47               : 1;
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t reserved_47_47               : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_intx_en0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_intx_en0_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_intx_en0_cn38xx       cn38xxp2;
+	struct cvmx_ciu_intx_en0_cn30xx       cn50xx;
+	struct cvmx_ciu_intx_en0_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en0_cn52xx       cn52xxp1;
+	struct cvmx_ciu_intx_en0_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en0_cn56xx       cn56xxp1;
+	struct cvmx_ciu_intx_en0_cn38xx       cn58xx;
+	struct cvmx_ciu_intx_en0_cn38xx       cn58xxp1;
+	struct cvmx_ciu_intx_en0_cn52xx       cn63xx;
+	struct cvmx_ciu_intx_en0_cn52xx       cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
+
+/**
+ * cvmx_ciu_int#_en0_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN0 register
+ *
+ */
+union cvmx_ciu_intx_en0_w1c
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en0_w1c_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en0_w1c_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en0_w1c_s        cn56xx;
+	struct cvmx_ciu_intx_en0_w1c_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en0_w1c_cn52xx   cn63xx;
+	struct cvmx_ciu_intx_en0_w1c_cn52xx   cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
+
+/**
+ * cvmx_ciu_int#_en0_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN0 register
+ *
+ */
+union cvmx_ciu_intx_en0_w1s
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en0_w1s_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox/PCIe/sRIO interrupt
+                                                         enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en0_w1s_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en0_w1s_s        cn56xx;
+	struct cvmx_ciu_intx_en0_w1s_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en0_w1s_cn52xx   cn63xx;
+	struct cvmx_ciu_intx_en0_w1s_cn52xx   cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
+
+/**
+ * cvmx_ciu_int#_en1
+ *
+ * Notes:
+ * @verbatim
+ * PPx/IP2 will be raised when...
+ *
+ *    n = x*2
+ *    PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ *
+ * PPx/IP3 will be raised when...
+ *
+ *    n = x*2 + 1
+ *    PPx/IP3 =  |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ *
+ * PCI/INT will be raised when...
+ *
+ *    PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0])
+ * @endverbatim
+ */
+union cvmx_ciu_intx_en1
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en1_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t wdog                         : 1;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_intx_en1_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t wdog                         : 2;  /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_intx_en1_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_intx_en1_cn38xx       cn38xxp2;
+	struct cvmx_ciu_intx_en1_cn31xx       cn50xx;
+	struct cvmx_ciu_intx_en1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en1_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn52xxp1;
+	struct cvmx_ciu_intx_en1_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en1_cn56xx       cn56xxp1;
+	struct cvmx_ciu_intx_en1_cn38xx       cn58xx;
+	struct cvmx_ciu_intx_en1_cn38xx       cn58xxp1;
+	struct cvmx_ciu_intx_en1_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en1_cn63xx       cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
+
+/**
+ * cvmx_ciu_int#_en1_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN1 register
+ *
+ */
+union cvmx_ciu_intx_en1_w1c
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en1_w1c_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to clear SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en1_w1c_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en1_w1c_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en1_w1c_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en1_w1c_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to clear SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en1_w1c_cn63xx   cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
+
+/**
+ * cvmx_ciu_int#_en1_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN1 register
+ *
+ */
+union cvmx_ciu_intx_en1_w1s
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en1_w1s_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to set SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en1_w1s_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en1_w1s_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en1_w1s_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en1_w1s_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to set SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en1_w1s_cn63xx   cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
+
+/**
+ * cvmx_ciu_int#_en4_0
+ *
+ * Notes:
+ * CIU_INT0_EN4_0:   PP0  /IP4
+ * CIU_INT1_EN4_0:   PP1  /IP4
+ * ...
+ * CIU_INT11_EN4_0:  PP11 /IP4
+ */
+union cvmx_ciu_intx_en4_0
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt enable */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt enable */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt enable */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt enable */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt enable */
+	uint64_t timer                        : 4;  /**< General timer interrupt enables */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt enable */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Two UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< 16 work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_0_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t reserved_47_47               : 1;
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t reserved_47_47               : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn50xx;
+	struct cvmx_ciu_intx_en4_0_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_0_cn52xx     cn52xxp1;
+	struct cvmx_ciu_intx_en4_0_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_0_cn56xx     cn56xxp1;
+	struct cvmx_ciu_intx_en4_0_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_0_cn58xx     cn58xxp1;
+	struct cvmx_ciu_intx_en4_0_cn52xx     cn63xx;
+	struct cvmx_ciu_intx_en4_0_cn52xx     cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
+
+/**
+ * cvmx_ciu_int#_en4_0_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN4_0 register
+ *
+ */
+union cvmx_ciu_intx_en4_0_w1c
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_0_w1c_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Write 1 to clear Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to clear IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to clear POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to clear 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to clear General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to clear IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to clear GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to clear Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to clear RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to clear TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to clear PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to clear PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to clear UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to clear mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to clear GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_0_w1c_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_0_w1c_s      cn56xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
+
+/**
+ * cvmx_ciu_int#_en4_0_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN4_0 register
+ *
+ */
+union cvmx_ciu_intx_en4_0_w1s
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_0_w1s_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Write 1 to set Boot bus DMA engines Interrupt
+                                                         enable */
+	uint64_t mii                          : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+                                                         enable */
+	uint64_t ipdppthr                     : 1;  /**< Write 1 to set IPD per-port counter threshold
+                                                         interrupt enable */
+	uint64_t powiq                        : 1;  /**< Write 1 to set POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< Write 1 to set 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< Write 1 to set USB EHCI or OHCI Interrupt */
+	uint64_t timer                        : 4;  /**< Write 1 to set General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< Write 1 to set IPD QOS packet drop interrupt
+                                                         enable */
+	uint64_t gmx_drp                      : 2;  /**< Write 1 to set GMX packet drop interrupt enable */
+	uint64_t trace                        : 1;  /**< Write 1 to set Trace buffer interrupt enable */
+	uint64_t rml                          : 1;  /**< Write 1 to set RML Interrupt enable */
+	uint64_t twsi                         : 1;  /**< Write 1 to set TWSI Interrupt enable */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< Write 1s to set PCIe/sRIO MSI enables */
+	uint64_t pci_int                      : 4;  /**< Write 1s to set PCIe INTA/B/C/D enables */
+	uint64_t uart                         : 2;  /**< Write 1s to set UART interrupt enables */
+	uint64_t mbox                         : 2;  /**< Write 1s to set mailbox interrupt enables */
+	uint64_t gpio                         : 16; /**< Write 1s to set GPIO interrupt enables */
+	uint64_t workq                        : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_0_w1s_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_0_w1s_s      cn56xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t reserved_44_44               : 1;
+	uint64_t pci_msi                      : 4;  /**< PCI MSI */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox/PCI interrupts */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t reserved_44_44               : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
+
+/**
+ * cvmx_ciu_int#_en4_1
+ *
+ * Notes:
+ * PPx/IP4 will be raised when...
+ * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
+ */
+union cvmx_ciu_intx_en4_1
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_1_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t wdog                         : 2;  /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn50xx;
+	struct cvmx_ciu_intx_en4_1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_1_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn52xxp1;
+	struct cvmx_ciu_intx_en4_1_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_1_cn56xx     cn56xxp1;
+	struct cvmx_ciu_intx_en4_1_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_1_cn58xx     cn58xxp1;
+	struct cvmx_ciu_intx_en4_1_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< DFA interrupt enable */
+	uint64_t key                          : 1;  /**< KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt enable */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en4_1_cn63xx     cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
+
+/**
+ * cvmx_ciu_int#_en4_1_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN4_1 register
+ *
+ */
+union cvmx_ciu_intx_en4_1_w1c
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_1_w1c_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to clear SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_1_w1c_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to clear MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to clear DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to clear LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to clear SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to clear SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to clear PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to clear PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to clear PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to clear AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to clear GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to clear DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to clear SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to clear USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to clear DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to clear KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to clear RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to clear TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to clear ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to clear PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to clear PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to clear IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to clear L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to clear POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to clear FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to clear IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to clear MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to clear NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to clear RGMII/MII/MIX Interface 1
+                                                         Interrupt enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
+
+/**
+ * cvmx_ciu_int#_en4_1_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN4_1 register
+ *
+ */
+union cvmx_ciu_intx_en4_1_w1s
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_en4_1_w1s_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to set SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_en4_1_w1s_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< Watchdog summary interrupt enable vector */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< Watchdog summary interrupt enable vectory */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< Write 1 to set MIO RST interrupt enable */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< Write 1 to set DFM interrupt enable */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< Write 1 to set LMC0 interrupt enable */
+	uint64_t srio1                        : 1;  /**< Write 1 to set SRIO1 interrupt enable */
+	uint64_t srio0                        : 1;  /**< Write 1 to set SRIO0 interrupt enable */
+	uint64_t pem1                         : 1;  /**< Write 1 to set PEM1 interrupt enable */
+	uint64_t pem0                         : 1;  /**< Write 1 to set PEM0 interrupt enable */
+	uint64_t ptp                          : 1;  /**< Write 1 to set PTP interrupt enable */
+	uint64_t agl                          : 1;  /**< Write 1 to set AGL interrupt enable */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< Write 1 to set GMX0 interrupt enable */
+	uint64_t dpi                          : 1;  /**< Write 1 to set DPI interrupt enable */
+	uint64_t sli                          : 1;  /**< Write 1 to set SLI interrupt enable */
+	uint64_t usb                          : 1;  /**< Write 1 to set USB UCTL0 interrupt enable */
+	uint64_t dfa                          : 1;  /**< Write 1 to set DFA interrupt enable */
+	uint64_t key                          : 1;  /**< Write 1 to set KEY interrupt enable */
+	uint64_t rad                          : 1;  /**< Write 1 to set RAD interrupt enable */
+	uint64_t tim                          : 1;  /**< Write 1 to set TIM interrupt enable */
+	uint64_t zip                          : 1;  /**< Write 1 to set ZIP interrupt enable */
+	uint64_t pko                          : 1;  /**< Write 1 to set PKO interrupt enable */
+	uint64_t pip                          : 1;  /**< Write 1 to set PIP interrupt enable */
+	uint64_t ipd                          : 1;  /**< Write 1 to set IPD interrupt enable */
+	uint64_t l2c                          : 1;  /**< Write 1 to set L2C interrupt enable */
+	uint64_t pow                          : 1;  /**< Write 1 to set POW err interrupt enable */
+	uint64_t fpa                          : 1;  /**< Write 1 to set FPA interrupt enable */
+	uint64_t iob                          : 1;  /**< Write 1 to set IOB interrupt enable */
+	uint64_t mio                          : 1;  /**< Write 1 to set MIO boot interrupt enable */
+	uint64_t nand                         : 1;  /**< Write 1 to set NAND Flash Controller interrupt
+                                                         enable */
+	uint64_t mii1                         : 1;  /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+                                                         enable */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
+};
+typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t;
+
+/**
+ * cvmx_ciu_int#_sum0
+ */
+union cvmx_ciu_intx_sum0
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_sum0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-11
+                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3
+                                                         Note that WDOG_SUM only summarizes the SUM/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCIe/sRIO internal interrupts for entries 32-33
+                                                          which equal CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_sum0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t reserved_47_47               : 1;
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-1.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t reserved_47_47               : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_intx_sum0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-3.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_intx_sum0_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-31.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_intx_sum0_cn38xx      cn38xxp2;
+	struct cvmx_ciu_intx_sum0_cn30xx      cn50xx;
+	struct cvmx_ciu_intx_sum0_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-7.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3
+                                                         Note that WDOG_SUM only summarizes the SUM/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-7
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_sum0_cn52xx      cn52xxp1;
+	struct cvmx_ciu_intx_sum0_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-23.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-23
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_sum0_cn56xx      cn56xxp1;
+	struct cvmx_ciu_intx_sum0_cn38xx      cn58xx;
+	struct cvmx_ciu_intx_sum0_cn38xx      cn58xxp1;
+	struct cvmx_ciu_intx_sum0_cn52xx      cn63xx;
+	struct cvmx_ciu_intx_sum0_cn52xx      cn63xxp1;
+};
+typedef union cvmx_ciu_intx_sum0 cvmx_ciu_intx_sum0_t;
+
+/**
+ * cvmx_ciu_int#_sum4
+ */
+union cvmx_ciu_intx_sum4
+{
+	uint64_t u64;
+	struct cvmx_ciu_intx_sum4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This bit is set when any bit is set in
+                                                         CIU_BLOCK_INT. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN4_1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN4_1 is set, where x
+                                                         is the same as x in this CIU_INTx_SUM4.
+                                                         PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
+                                                         Note that WDOG_SUM only summarizes the SUM/EN4_1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-5
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_intx_sum4_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t mpi                          : 1;  /**< MPI/SPI interrupt */
+	uint64_t pcm                          : 1;  /**< PCM/TDM interrupt */
+	uint64_t usb                          : 1;  /**< USB interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t reserved_47_47               : 1;
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM4 where x=0-1. */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t reserved_47_47               : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t pcm                          : 1;
+	uint64_t mpi                          : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn50xx;
+	struct cvmx_ciu_intx_sum4_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN4_1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN4_1 is set, where x
+                                                         is the same as x in this CIU_INTx_SUM4.
+                                                         PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
+                                                         Note that WDOG_SUM only summarizes the SUM/EN4_1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-3
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_intx_sum4_cn52xx      cn52xxp1;
+	struct cvmx_ciu_intx_sum4_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt */
+	uint64_t mii                          : 1;  /**< MII Interface Interrupt */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB Interrupt */
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         These registers report WDOG to IP4 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-11
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_intx_sum4_cn56xx      cn56xxp1;
+	struct cvmx_ciu_intx_sum4_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t timer                        : 4;  /**< General timer interrupts */
+	uint64_t key_zero                     : 1;  /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop */
+	uint64_t gmx_drp                      : 2;  /**< GMX packet drop */
+	uint64_t trace                        : 1;  /**< L2C has the CMB trace buffer */
+	uint64_t rml                          : 1;  /**< RML Interrupt */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt */
+	uint64_t wdog_sum                     : 1;  /**< Watchdog summary
+                                                         These registers report WDOG to IP4 */
+	uint64_t pci_msi                      : 4;  /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+	uint64_t pci_int                      : 4;  /**< PCI INTA/B/C/D */
+	uint64_t uart                         : 2;  /**< Two UART interrupts */
+	uint64_t mbox                         : 2;  /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 2;
+	uint64_t ipd_drp                      : 1;
+	uint64_t key_zero                     : 1;
+	uint64_t timer                        : 4;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn58xx;
+	struct cvmx_ciu_intx_sum4_cn58xx      cn58xxp1;
+	struct cvmx_ciu_intx_sum4_cn52xx      cn63xx;
+	struct cvmx_ciu_intx_sum4_cn52xx      cn63xxp1;
+};
+typedef union cvmx_ciu_intx_sum4 cvmx_ciu_intx_sum4_t;
+
+/**
+ * cvmx_ciu_int33_sum0
+ */
+union cvmx_ciu_int33_sum0
+{
+	uint64_t u64;
+	struct cvmx_ciu_int33_sum0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bootdma                      : 1;  /**< Boot bus DMA engines Interrupt
+                                                         See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+	uint64_t mii                          : 1;  /**< RGMII/MII/MIX Interface 0 Interrupt
+                                                         See MIX0_ISR */
+	uint64_t ipdppthr                     : 1;  /**< IPD per-port counter threshold interrupt
+                                                         See IPD_PORT_QOS_INT* */
+	uint64_t powiq                        : 1;  /**< POW IQ interrupt
+                                                         See POW_IQ_INT */
+	uint64_t twsi2                        : 1;  /**< 2nd TWSI Interrupt
+                                                         See MIO_TWS1_INT */
+	uint64_t reserved_57_58               : 2;
+	uint64_t usb                          : 1;  /**< USB EHCI or OHCI Interrupt
+                                                         See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+	uint64_t timer                        : 4;  /**< General timer interrupts
+                                                         Set any time the corresponding CIU timer expires */
+	uint64_t reserved_51_51               : 1;
+	uint64_t ipd_drp                      : 1;  /**< IPD QOS packet drop interrupt
+                                                         Set any time PIP/IPD drops a packet */
+	uint64_t reserved_49_49               : 1;
+	uint64_t gmx_drp                      : 1;  /**< GMX packet drop interrupt
+                                                         Set any time corresponding GMX drops a packet */
+	uint64_t trace                        : 1;  /**< Trace buffer interrupt
+                                                         See TRA_INT_STATUS */
+	uint64_t rml                          : 1;  /**< RML Interrupt
+                                                         This interrupt will assert if any bit within
+                                                         CIU_BLOCK_INT is asserted. */
+	uint64_t twsi                         : 1;  /**< TWSI Interrupt
+                                                         See MIO_TWS0_INT */
+	uint64_t wdog_sum                     : 1;  /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-11.
+                                                         PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3
+                                                         Note that WDOG_SUM only summarizes the SUM/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+	uint64_t pci_msi                      : 4;  /**< PCIe/sRIO MSI
+                                                         See SLI_MSI_RCVn for bit <40+n> */
+	uint64_t pci_int                      : 4;  /**< PCIe INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the SLI chapter of the spec */
+	uint64_t uart                         : 2;  /**< Two UART interrupts
+                                                         See MIO_UARTn_IIR[IID] for bit <34+n> */
+	uint64_t mbox                         : 2;  /**< A read-only copy of CIU_PCI_INTA[INT] */
+	uint64_t gpio                         : 16; /**< 16 GPIO interrupts */
+	uint64_t workq                        : 16; /**< 16 work queue interrupts
+                                                         See POW_WQ_INT[WQ_INT]
+                                                          1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+	uint64_t workq                        : 16;
+	uint64_t gpio                         : 16;
+	uint64_t mbox                         : 2;
+	uint64_t uart                         : 2;
+	uint64_t pci_int                      : 4;
+	uint64_t pci_msi                      : 4;
+	uint64_t wdog_sum                     : 1;
+	uint64_t twsi                         : 1;
+	uint64_t rml                          : 1;
+	uint64_t trace                        : 1;
+	uint64_t gmx_drp                      : 1;
+	uint64_t reserved_49_49               : 1;
+	uint64_t ipd_drp                      : 1;
+	uint64_t reserved_51_51               : 1;
+	uint64_t timer                        : 4;
+	uint64_t usb                          : 1;
+	uint64_t reserved_57_58               : 2;
+	uint64_t twsi2                        : 1;
+	uint64_t powiq                        : 1;
+	uint64_t ipdppthr                     : 1;
+	uint64_t mii                          : 1;
+	uint64_t bootdma                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_int33_sum0_s          cn63xx;
+	struct cvmx_ciu_int33_sum0_s          cn63xxp1;
+};
+typedef union cvmx_ciu_int33_sum0 cvmx_ciu_int33_sum0_t;
+
+/**
+ * cvmx_ciu_int_dbg_sel
+ */
+union cvmx_ciu_int_dbg_sel
+{
+	uint64_t u64;
+	struct cvmx_ciu_int_dbg_sel_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t sel                          : 3;  /**< Selects if all or the specific interrupt is
+                                                         presented on the debug port.
+                                                         0=erst_n
+                                                         1=start_bist
+                                                         2=toggle at sclk/2 freq
+                                                         3=All PP interrupt bits are ORed together
+                                                         4=Only the selected PP/IRQ is selected */
+	uint64_t reserved_10_15               : 6;
+	uint64_t irq                          : 2;  /**< Which IRQ to select
+                                                         0=IRQ2
+                                                         1=IRQ3
+                                                         2=IRQ4 */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t pp                           : 3;  /**< Which PP to select */
+#else
+	uint64_t pp                           : 3;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t irq                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t sel                          : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_ciu_int_dbg_sel_s         cn63xx;
+};
+typedef union cvmx_ciu_int_dbg_sel cvmx_ciu_int_dbg_sel_t;
+
+/**
+ * cvmx_ciu_int_sum1
+ */
+union cvmx_ciu_int_sum1
+{
+	uint64_t u64;
+	struct cvmx_ciu_int_sum1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
+                                                         See SRIO1_INT_REG */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t wdog                         : 16; /**< 6 watchdog interrupts */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} s;
+	struct cvmx_ciu_int_sum1_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t wdog                         : 1;  /**< 1 watchdog interrupt */
+#else
+	uint64_t wdog                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_int_sum1_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t wdog                         : 2;  /**< 2 watchdog interrupts */
+#else
+	uint64_t wdog                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_int_sum1_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t wdog                         : 16; /**< 16 watchdog interrupts */
+#else
+	uint64_t wdog                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_ciu_int_sum1_cn38xx       cn38xxp2;
+	struct cvmx_ciu_int_sum1_cn31xx       cn50xx;
+	struct cvmx_ciu_int_sum1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t nand                         : 1;  /**< NAND Flash Controller */
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< 4 watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_int_sum1_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t mii1                         : 1;  /**< Second MII Interrupt */
+	uint64_t usb1                         : 1;  /**< Second USB Interrupt */
+	uint64_t uart2                        : 1;  /**< Third UART interrupt */
+	uint64_t reserved_4_15                : 12;
+	uint64_t wdog                         : 4;  /**< 4 watchdog interrupts */
+#else
+	uint64_t wdog                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t uart2                        : 1;
+	uint64_t usb1                         : 1;
+	uint64_t mii1                         : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn52xxp1;
+	struct cvmx_ciu_int_sum1_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t wdog                         : 12; /**< 12 watchdog interrupts */
+#else
+	uint64_t wdog                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_int_sum1_cn56xx       cn56xxp1;
+	struct cvmx_ciu_int_sum1_cn38xx       cn58xx;
+	struct cvmx_ciu_int_sum1_cn38xx       cn58xxp1;
+	struct cvmx_ciu_int_sum1_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rst                          : 1;  /**< MIO RST interrupt
+                                                         See MIO_RST_INT */
+	uint64_t reserved_57_62               : 6;
+	uint64_t dfm                          : 1;  /**< DFM Interrupt
+                                                         See DFM_FNT_STAT */
+	uint64_t reserved_53_55               : 3;
+	uint64_t lmc0                         : 1;  /**< LMC0 interrupt
+                                                         See LMC0_INT */
+	uint64_t srio1                        : 1;  /**< SRIO1 interrupt
+                                                         See SRIO1_INT_REG, SRIO1_INT2_REG */
+	uint64_t srio0                        : 1;  /**< SRIO0 interrupt
+                                                         See SRIO0_INT_REG, SRIO0_INT2_REG */
+	uint64_t pem1                         : 1;  /**< PEM1 interrupt
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+	uint64_t pem0                         : 1;  /**< PEM0 interrupt
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+	uint64_t ptp                          : 1;  /**< PTP interrupt
+                                                         Set when HW decrements MIO_PTP_EVT_CNT to zero */
+	uint64_t agl                          : 1;  /**< AGL interrupt
+                                                         See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+	uint64_t reserved_37_45               : 9;
+	uint64_t agx0                         : 1;  /**< GMX0 interrupt
+                                                         See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
+                                                         PCS0_INT*_REG, PCSX0_INT_REG */
+	uint64_t dpi                          : 1;  /**< DPI interrupt
+                                                         See DPI_INT_REG */
+	uint64_t sli                          : 1;  /**< SLI interrupt
+                                                         See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+	uint64_t usb                          : 1;  /**< USB UCTL0 interrupt
+                                                         See UCTL0_INT_REG */
+	uint64_t dfa                          : 1;  /**< DFA interrupt
+                                                         See DFA_ERROR */
+	uint64_t key                          : 1;  /**< KEY interrupt
+                                                         See KEY_INT_SUM */
+	uint64_t rad                          : 1;  /**< RAD interrupt
+                                                         See RAD_REG_ERROR */
+	uint64_t tim                          : 1;  /**< TIM interrupt
+                                                         See TIM_REG_ERROR */
+	uint64_t zip                          : 1;  /**< ZIP interrupt
+                                                         See ZIP_ERROR */
+	uint64_t pko                          : 1;  /**< PKO interrupt
+                                                         See PKO_REG_ERROR */
+	uint64_t pip                          : 1;  /**< PIP interrupt
+                                                         See PIP_INT_REG */
+	uint64_t ipd                          : 1;  /**< IPD interrupt
+                                                         See IPD_INT_SUM */
+	uint64_t l2c                          : 1;  /**< L2C interrupt
+                                                         See L2C_INT_REG */
+	uint64_t pow                          : 1;  /**< POW err interrupt
+                                                         See POW_ECC_ERR */
+	uint64_t fpa                          : 1;  /**< FPA interrupt
+                                                         See FPA_INT_SUM */
+	uint64_t iob                          : 1;  /**< IOB interrupt
+                                                         See IOB_INT_SUM */
+	uint64_t mio                          : 1;  /**< MIO boot interrupt
+                                                         See MIO_BOOT_ERR */
+	uint64_t nand                         : 1;  /**< NAND Flash Controller interrupt
+                                                         See NDF_INT */
+	uint64_t mii1                         : 1;  /**< RGMII/MII/MIX Interface 1 Interrupt
+                                                         See MIX1_ISR */
+	uint64_t reserved_6_17                : 12;
+	uint64_t wdog                         : 6;  /**< 6 watchdog interrupts */
+#else
+	uint64_t wdog                         : 6;
+	uint64_t reserved_6_17                : 12;
+	uint64_t mii1                         : 1;
+	uint64_t nand                         : 1;
+	uint64_t mio                          : 1;
+	uint64_t iob                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t l2c                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pip                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t key                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t sli                          : 1;
+	uint64_t dpi                          : 1;
+	uint64_t agx0                         : 1;
+	uint64_t reserved_37_45               : 9;
+	uint64_t agl                          : 1;
+	uint64_t ptp                          : 1;
+	uint64_t pem0                         : 1;
+	uint64_t pem1                         : 1;
+	uint64_t srio0                        : 1;
+	uint64_t srio1                        : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t reserved_53_55               : 3;
+	uint64_t dfm                          : 1;
+	uint64_t reserved_57_62               : 6;
+	uint64_t rst                          : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_int_sum1_cn63xx       cn63xxp1;
+};
+typedef union cvmx_ciu_int_sum1 cvmx_ciu_int_sum1_t;
+
+/**
+ * cvmx_ciu_mbox_clr#
+ */
+union cvmx_ciu_mbox_clrx
+{
+	uint64_t u64;
+	struct cvmx_ciu_mbox_clrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bits                         : 32; /**< On writes, clr corresponding bit in MBOX register
+                                                         on reads, return the MBOX register */
+#else
+	uint64_t bits                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu_mbox_clrx_s           cn30xx;
+	struct cvmx_ciu_mbox_clrx_s           cn31xx;
+	struct cvmx_ciu_mbox_clrx_s           cn38xx;
+	struct cvmx_ciu_mbox_clrx_s           cn38xxp2;
+	struct cvmx_ciu_mbox_clrx_s           cn50xx;
+	struct cvmx_ciu_mbox_clrx_s           cn52xx;
+	struct cvmx_ciu_mbox_clrx_s           cn52xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cn56xx;
+	struct cvmx_ciu_mbox_clrx_s           cn56xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cn58xx;
+	struct cvmx_ciu_mbox_clrx_s           cn58xxp1;
+	struct cvmx_ciu_mbox_clrx_s           cn63xx;
+	struct cvmx_ciu_mbox_clrx_s           cn63xxp1;
+};
+typedef union cvmx_ciu_mbox_clrx cvmx_ciu_mbox_clrx_t;
+
+/**
+ * cvmx_ciu_mbox_set#
+ */
+union cvmx_ciu_mbox_setx
+{
+	uint64_t u64;
+	struct cvmx_ciu_mbox_setx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bits                         : 32; /**< On writes, set corresponding bit in MBOX register
+                                                         on reads, return the MBOX register */
+#else
+	uint64_t bits                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu_mbox_setx_s           cn30xx;
+	struct cvmx_ciu_mbox_setx_s           cn31xx;
+	struct cvmx_ciu_mbox_setx_s           cn38xx;
+	struct cvmx_ciu_mbox_setx_s           cn38xxp2;
+	struct cvmx_ciu_mbox_setx_s           cn50xx;
+	struct cvmx_ciu_mbox_setx_s           cn52xx;
+	struct cvmx_ciu_mbox_setx_s           cn52xxp1;
+	struct cvmx_ciu_mbox_setx_s           cn56xx;
+	struct cvmx_ciu_mbox_setx_s           cn56xxp1;
+	struct cvmx_ciu_mbox_setx_s           cn58xx;
+	struct cvmx_ciu_mbox_setx_s           cn58xxp1;
+	struct cvmx_ciu_mbox_setx_s           cn63xx;
+	struct cvmx_ciu_mbox_setx_s           cn63xxp1;
+};
+typedef union cvmx_ciu_mbox_setx cvmx_ciu_mbox_setx_t;
+
+/**
+ * cvmx_ciu_nmi
+ */
+union cvmx_ciu_nmi
+{
+	uint64_t u64;
+	struct cvmx_ciu_nmi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t nmi                          : 16; /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu_nmi_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t nmi                          : 1;  /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_nmi_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t nmi                          : 2;  /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_nmi_s                 cn38xx;
+	struct cvmx_ciu_nmi_s                 cn38xxp2;
+	struct cvmx_ciu_nmi_cn31xx            cn50xx;
+	struct cvmx_ciu_nmi_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t nmi                          : 4;  /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_nmi_cn52xx            cn52xxp1;
+	struct cvmx_ciu_nmi_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t nmi                          : 12; /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_nmi_cn56xx            cn56xxp1;
+	struct cvmx_ciu_nmi_s                 cn58xx;
+	struct cvmx_ciu_nmi_s                 cn58xxp1;
+	struct cvmx_ciu_nmi_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t nmi                          : 6;  /**< Send NMI pulse to PP vector */
+#else
+	uint64_t nmi                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_nmi_cn63xx            cn63xxp1;
+};
+typedef union cvmx_ciu_nmi cvmx_ciu_nmi_t;
+
+/**
+ * cvmx_ciu_pci_inta
+ */
+union cvmx_ciu_pci_inta
+{
+	uint64_t u64;
+	struct cvmx_ciu_pci_inta_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t intr                         : 2;  /**< PCIe/sRIO interrupt
+                                                         These bits are observed in CIU_INTX_SUM0<33:32>
+                                                         where X=32-33 */
+#else
+	uint64_t intr                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_ciu_pci_inta_s            cn30xx;
+	struct cvmx_ciu_pci_inta_s            cn31xx;
+	struct cvmx_ciu_pci_inta_s            cn38xx;
+	struct cvmx_ciu_pci_inta_s            cn38xxp2;
+	struct cvmx_ciu_pci_inta_s            cn50xx;
+	struct cvmx_ciu_pci_inta_s            cn52xx;
+	struct cvmx_ciu_pci_inta_s            cn52xxp1;
+	struct cvmx_ciu_pci_inta_s            cn56xx;
+	struct cvmx_ciu_pci_inta_s            cn56xxp1;
+	struct cvmx_ciu_pci_inta_s            cn58xx;
+	struct cvmx_ciu_pci_inta_s            cn58xxp1;
+	struct cvmx_ciu_pci_inta_s            cn63xx;
+	struct cvmx_ciu_pci_inta_s            cn63xxp1;
+};
+typedef union cvmx_ciu_pci_inta cvmx_ciu_pci_inta_t;
+
+/**
+ * cvmx_ciu_pp_dbg
+ */
+union cvmx_ciu_pp_dbg
+{
+	uint64_t u64;
+	struct cvmx_ciu_pp_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ppdbg                        : 16; /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu_pp_dbg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t ppdbg                        : 1;  /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_pp_dbg_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t ppdbg                        : 2;  /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_pp_dbg_s              cn38xx;
+	struct cvmx_ciu_pp_dbg_s              cn38xxp2;
+	struct cvmx_ciu_pp_dbg_cn31xx         cn50xx;
+	struct cvmx_ciu_pp_dbg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ppdbg                        : 4;  /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_pp_dbg_cn52xx         cn52xxp1;
+	struct cvmx_ciu_pp_dbg_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t ppdbg                        : 12; /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_pp_dbg_cn56xx         cn56xxp1;
+	struct cvmx_ciu_pp_dbg_s              cn58xx;
+	struct cvmx_ciu_pp_dbg_s              cn58xxp1;
+	struct cvmx_ciu_pp_dbg_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t ppdbg                        : 6;  /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+	uint64_t ppdbg                        : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_pp_dbg_cn63xx         cn63xxp1;
+};
+typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t;
+
+/**
+ * cvmx_ciu_pp_poke#
+ *
+ * Notes:
+ * Any write to a CIU_PP_POKE register clears any pending interrupt generated
+ * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set
+ * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8).
+ *
+ * Reads to this register will return the associated CIU_WDOG register.
+ */
+union cvmx_ciu_pp_pokex
+{
+	uint64_t u64;
+	struct cvmx_ciu_pp_pokex_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t poke                         : 64; /**< Reserved */
+#else
+	uint64_t poke                         : 64;
+#endif
+	} s;
+	struct cvmx_ciu_pp_pokex_s            cn30xx;
+	struct cvmx_ciu_pp_pokex_s            cn31xx;
+	struct cvmx_ciu_pp_pokex_s            cn38xx;
+	struct cvmx_ciu_pp_pokex_s            cn38xxp2;
+	struct cvmx_ciu_pp_pokex_s            cn50xx;
+	struct cvmx_ciu_pp_pokex_s            cn52xx;
+	struct cvmx_ciu_pp_pokex_s            cn52xxp1;
+	struct cvmx_ciu_pp_pokex_s            cn56xx;
+	struct cvmx_ciu_pp_pokex_s            cn56xxp1;
+	struct cvmx_ciu_pp_pokex_s            cn58xx;
+	struct cvmx_ciu_pp_pokex_s            cn58xxp1;
+	struct cvmx_ciu_pp_pokex_s            cn63xx;
+	struct cvmx_ciu_pp_pokex_s            cn63xxp1;
+};
+typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t;
+
+/**
+ * cvmx_ciu_pp_rst
+ *
+ * Contains the reset control for each PP.  Value of '1' will hold a PP in reset, '0' will release.
+ * Resets to 0xffff when PCI boot is enabled, 0xfffe otherwise.
+ */
+union cvmx_ciu_pp_rst
+{
+	uint64_t u64;
+	struct cvmx_ciu_pp_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t rst                          : 15; /**< PP Rst for PP's 5-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 15;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ciu_pp_rst_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_ciu_pp_rst_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t rst                          : 1;  /**< PP Rst for PP1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_ciu_pp_rst_s              cn38xx;
+	struct cvmx_ciu_pp_rst_s              cn38xxp2;
+	struct cvmx_ciu_pp_rst_cn31xx         cn50xx;
+	struct cvmx_ciu_pp_rst_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t rst                          : 3;  /**< PP Rst for PP's 11-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 3;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_pp_rst_cn52xx         cn52xxp1;
+	struct cvmx_ciu_pp_rst_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t rst                          : 11; /**< PP Rst for PP's 11-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 11;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xx;
+	struct cvmx_ciu_pp_rst_cn56xx         cn56xxp1;
+	struct cvmx_ciu_pp_rst_s              cn58xx;
+	struct cvmx_ciu_pp_rst_s              cn58xxp1;
+	struct cvmx_ciu_pp_rst_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t rst                          : 5;  /**< PP Rst for PP's 5-1 */
+	uint64_t rst0                         : 1;  /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+	uint64_t rst0                         : 1;
+	uint64_t rst                          : 5;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_pp_rst_cn63xx         cn63xxp1;
+};
+typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t;
+
+/**
+ * cvmx_ciu_qlm0
+ *
+ * Notes:
+ * This register is only reset by cold reset.
+ *
+ */
+union cvmx_ciu_qlm0
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t g2bypass                     : 1;  /**< QLM0 PCIE Gen2 tx bypass enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2deemph                     : 5;  /**< QLM0 PCIE Gen2 tx bypass de-emphasis value */
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2margin                     : 5;  /**< QLM0 PCIE Gen2 tx bypass margin (amplitude) value */
+	uint64_t reserved_32_39               : 8;
+	uint64_t txbypass                     : 1;  /**< QLM0 transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLM0 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM0 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM0 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_39               : 8;
+	uint64_t g2margin                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2deemph                     : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2bypass                     : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm0_s                cn63xx;
+	struct cvmx_ciu_qlm0_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t txbypass                     : 1;  /**< QLM0 transmitter bypass enable */
+	uint64_t reserved_20_30               : 11;
+	uint64_t txdeemph                     : 4;  /**< QLM0 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM0 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM0 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 4;
+	uint64_t reserved_20_30               : 11;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t;
+
+/**
+ * cvmx_ciu_qlm1
+ *
+ * Notes:
+ * This register is only reset by cold reset.
+ *
+ */
+union cvmx_ciu_qlm1
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t g2bypass                     : 1;  /**< QLM1 PCIE Gen2 tx bypass enable */
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2deemph                     : 5;  /**< QLM1 PCIE Gen2 tx bypass de-emphasis value */
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2margin                     : 5;  /**< QLM1 PCIE Gen2 tx bypass margin (amplitude) value */
+	uint64_t reserved_32_39               : 8;
+	uint64_t txbypass                     : 1;  /**< QLM1 transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLM1 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM1 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM1 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_39               : 8;
+	uint64_t g2margin                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t g2deemph                     : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t g2bypass                     : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm1_s                cn63xx;
+	struct cvmx_ciu_qlm1_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t txbypass                     : 1;  /**< QLM1 transmitter bypass enable */
+	uint64_t reserved_20_30               : 11;
+	uint64_t txdeemph                     : 4;  /**< QLM1 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM1 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM1 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 4;
+	uint64_t reserved_20_30               : 11;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t;
+
+/**
+ * cvmx_ciu_qlm2
+ *
+ * Notes:
+ * This register is only reset by cold reset.
+ *
+ */
+union cvmx_ciu_qlm2
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t txbypass                     : 1;  /**< QLM2 transmitter bypass enable */
+	uint64_t reserved_21_30               : 10;
+	uint64_t txdeemph                     : 5;  /**< QLM2 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM2 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM2 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 5;
+	uint64_t reserved_21_30               : 10;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ciu_qlm2_s                cn63xx;
+	struct cvmx_ciu_qlm2_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t txbypass                     : 1;  /**< QLM2 transmitter bypass enable */
+	uint64_t reserved_20_30               : 11;
+	uint64_t txdeemph                     : 4;  /**< QLM2 transmitter bypass de-emphasis value */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txmargin                     : 5;  /**< QLM2 transmitter bypass margin (amplitude) value */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t lane_en                      : 4;  /**< QLM2 lane enable mask */
+#else
+	uint64_t lane_en                      : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t txmargin                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t txdeemph                     : 4;
+	uint64_t reserved_20_30               : 11;
+	uint64_t txbypass                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_ciu_qlm2 cvmx_ciu_qlm2_t;
+
+/**
+ * cvmx_ciu_qlm_dcok
+ */
+union cvmx_ciu_qlm_dcok
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm_dcok_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t qlm_dcok                     : 4;  /**< Re-assert dcok for each QLM. The value in this
+                                                         field is "anded" with the pll_dcok pin and then
+                                                         sent to each QLM (0..3). */
+#else
+	uint64_t qlm_dcok                     : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ciu_qlm_dcok_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t qlm_dcok                     : 2;  /**< Re-assert dcok for each QLM. The value in this
+                                                         field is "anded" with the pll_dcok pin and then
+                                                         sent to each QLM (0..3). */
+#else
+	uint64_t qlm_dcok                     : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_qlm_dcok_cn52xx       cn52xxp1;
+	struct cvmx_ciu_qlm_dcok_s            cn56xx;
+	struct cvmx_ciu_qlm_dcok_s            cn56xxp1;
+};
+typedef union cvmx_ciu_qlm_dcok cvmx_ciu_qlm_dcok_t;
+
+/**
+ * cvmx_ciu_qlm_jtgc
+ */
+union cvmx_ciu_qlm_jtgc
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm_jtgc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t mux_sel                      : 2;  /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+	uint64_t bypass                       : 4;  /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+	uint64_t bypass                       : 4;
+	uint64_t mux_sel                      : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clk_div                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_ciu_qlm_jtgc_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t mux_sel                      : 1;  /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t bypass                       : 2;  /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+	uint64_t bypass                       : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t mux_sel                      : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t clk_div                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_qlm_jtgc_cn52xx       cn52xxp1;
+	struct cvmx_ciu_qlm_jtgc_s            cn56xx;
+	struct cvmx_ciu_qlm_jtgc_s            cn56xxp1;
+	struct cvmx_ciu_qlm_jtgc_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t clk_div                      : 3;  /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t mux_sel                      : 2;  /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t bypass                       : 3;  /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+	uint64_t bypass                       : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t mux_sel                      : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clk_div                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_qlm_jtgc_cn63xx       cn63xxp1;
+};
+typedef union cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgc_t;
+
+/**
+ * cvmx_ciu_qlm_jtgd
+ */
+union cvmx_ciu_qlm_jtgd
+{
+	uint64_t u64;
+	struct cvmx_ciu_qlm_jtgd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+	uint64_t reserved_44_60               : 17;
+	uint64_t select                       : 4;  /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+	uint64_t reserved_37_39               : 3;
+	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
+	uint64_t shft_reg                     : 32; /**< QLM JTAG shift register */
+#else
+	uint64_t shft_reg                     : 32;
+	uint64_t shft_cnt                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t select                       : 4;
+	uint64_t reserved_44_60               : 17;
+	uint64_t update                       : 1;
+	uint64_t shift                        : 1;
+	uint64_t capture                      : 1;
+#endif
+	} s;
+	struct cvmx_ciu_qlm_jtgd_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+	uint64_t reserved_42_60               : 19;
+	uint64_t select                       : 2;  /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+	uint64_t reserved_37_39               : 3;
+	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
+	uint64_t shft_reg                     : 32; /**< QLM JTAG shift register */
+#else
+	uint64_t shft_reg                     : 32;
+	uint64_t shft_cnt                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t select                       : 2;
+	uint64_t reserved_42_60               : 19;
+	uint64_t update                       : 1;
+	uint64_t shift                        : 1;
+	uint64_t capture                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_qlm_jtgd_cn52xx       cn52xxp1;
+	struct cvmx_ciu_qlm_jtgd_s            cn56xx;
+	struct cvmx_ciu_qlm_jtgd_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+	uint64_t reserved_37_60               : 24;
+	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
+	uint64_t shft_reg                     : 32; /**< QLM JTAG shift register */
+#else
+	uint64_t shft_reg                     : 32;
+	uint64_t shft_cnt                     : 5;
+	uint64_t reserved_37_60               : 24;
+	uint64_t update                       : 1;
+	uint64_t shift                        : 1;
+	uint64_t capture                      : 1;
+#endif
+	} cn56xxp1;
+	struct cvmx_ciu_qlm_jtgd_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t capture                      : 1;  /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+	uint64_t shift                        : 1;  /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+	uint64_t update                       : 1;  /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+	uint64_t reserved_43_60               : 18;
+	uint64_t select                       : 3;  /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+	uint64_t reserved_37_39               : 3;
+	uint64_t shft_cnt                     : 5;  /**< QLM JTAG shift count (encoded in -1 notation) */
+	uint64_t shft_reg                     : 32; /**< QLM JTAG shift register */
+#else
+	uint64_t shft_reg                     : 32;
+	uint64_t shft_cnt                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t select                       : 3;
+	uint64_t reserved_43_60               : 18;
+	uint64_t update                       : 1;
+	uint64_t shift                        : 1;
+	uint64_t capture                      : 1;
+#endif
+	} cn63xx;
+	struct cvmx_ciu_qlm_jtgd_cn63xx       cn63xxp1;
+};
+typedef union cvmx_ciu_qlm_jtgd cvmx_ciu_qlm_jtgd_t;
+
+/**
+ * cvmx_ciu_soft_bist
+ */
+union cvmx_ciu_soft_bist
+{
+	uint64_t u64;
+	struct cvmx_ciu_soft_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_bist                    : 1;  /**< Reserved */
+#else
+	uint64_t soft_bist                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_soft_bist_s           cn30xx;
+	struct cvmx_ciu_soft_bist_s           cn31xx;
+	struct cvmx_ciu_soft_bist_s           cn38xx;
+	struct cvmx_ciu_soft_bist_s           cn38xxp2;
+	struct cvmx_ciu_soft_bist_s           cn50xx;
+	struct cvmx_ciu_soft_bist_s           cn52xx;
+	struct cvmx_ciu_soft_bist_s           cn52xxp1;
+	struct cvmx_ciu_soft_bist_s           cn56xx;
+	struct cvmx_ciu_soft_bist_s           cn56xxp1;
+	struct cvmx_ciu_soft_bist_s           cn58xx;
+	struct cvmx_ciu_soft_bist_s           cn58xxp1;
+	struct cvmx_ciu_soft_bist_s           cn63xx;
+	struct cvmx_ciu_soft_bist_s           cn63xxp1;
+};
+typedef union cvmx_ciu_soft_bist cvmx_ciu_soft_bist_t;
+
+/**
+ * cvmx_ciu_soft_prst
+ */
+union cvmx_ciu_soft_prst
+{
+	uint64_t u64;
+	struct cvmx_ciu_soft_prst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t host64                       : 1;  /**< PCX Host Mode Device Capability (0=32b/1=64b) */
+	uint64_t npi                          : 1;  /**< When PCI soft reset is asserted, also reset the
+                                                         NPI and PNI logic */
+	uint64_t soft_prst                    : 1;  /**< Resets the PCIe/sRIO logic in all modes, not just
+                                                         RC mode. The reset value is based on the
+                                                         corresponding MIO_RST_CTL[PRTMODE] CSR field:
+                                                          If PRTMODE == 0, then SOFT_PRST resets to 0
+                                                          If PRTMODE != 0, then SOFT_PRST resets to 1
+                                                         When OCTEON is configured to drive the PERST*_L
+                                                         chip pin (ie. MIO_RST_CTL0[RST_DRV] is set), this
+                                                         controls the PERST*_L chip pin. */
+#else
+	uint64_t soft_prst                    : 1;
+	uint64_t npi                          : 1;
+	uint64_t host64                       : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_ciu_soft_prst_s           cn30xx;
+	struct cvmx_ciu_soft_prst_s           cn31xx;
+	struct cvmx_ciu_soft_prst_s           cn38xx;
+	struct cvmx_ciu_soft_prst_s           cn38xxp2;
+	struct cvmx_ciu_soft_prst_s           cn50xx;
+	struct cvmx_ciu_soft_prst_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_prst                    : 1;  /**< Reset the PCI bus.  Only works when Octane is
+                                                         configured as a HOST. When OCTEON is a PCI host
+                                                         (i.e. when PCI_HOST_MODE = 1), This controls
+                                                         PCI_RST_L. Refer to section 10.11.1. */
+#else
+	uint64_t soft_prst                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn52xx;
+	struct cvmx_ciu_soft_prst_cn52xx      cn52xxp1;
+	struct cvmx_ciu_soft_prst_cn52xx      cn56xx;
+	struct cvmx_ciu_soft_prst_cn52xx      cn56xxp1;
+	struct cvmx_ciu_soft_prst_s           cn58xx;
+	struct cvmx_ciu_soft_prst_s           cn58xxp1;
+	struct cvmx_ciu_soft_prst_cn52xx      cn63xx;
+	struct cvmx_ciu_soft_prst_cn52xx      cn63xxp1;
+};
+typedef union cvmx_ciu_soft_prst cvmx_ciu_soft_prst_t;
+
+/**
+ * cvmx_ciu_soft_prst1
+ */
+union cvmx_ciu_soft_prst1
+{
+	uint64_t u64;
+	struct cvmx_ciu_soft_prst1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_prst                    : 1;  /**< Resets the PCIe/sRIO logic in all modes, not just
+                                                         RC mode. The reset value is based on the
+                                                         corresponding MIO_RST_CTL[PRTMODE] CSR field:
+                                                          If PRTMODE == 0, then SOFT_PRST resets to 0
+                                                          If PRTMODE != 0, then SOFT_PRST resets to 1
+                                                         When OCTEON is configured to drive the PERST*_L
+                                                         chip pin (ie. MIO_RST_CTL1[RST_DRV] is set), this
+                                                         controls the PERST*_L chip pin. */
+#else
+	uint64_t soft_prst                    : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_soft_prst1_s          cn52xx;
+	struct cvmx_ciu_soft_prst1_s          cn52xxp1;
+	struct cvmx_ciu_soft_prst1_s          cn56xx;
+	struct cvmx_ciu_soft_prst1_s          cn56xxp1;
+	struct cvmx_ciu_soft_prst1_s          cn63xx;
+	struct cvmx_ciu_soft_prst1_s          cn63xxp1;
+};
+typedef union cvmx_ciu_soft_prst1 cvmx_ciu_soft_prst1_t;
+
+/**
+ * cvmx_ciu_soft_rst
+ */
+union cvmx_ciu_soft_rst
+{
+	uint64_t u64;
+	struct cvmx_ciu_soft_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t soft_rst                     : 1;  /**< Resets Octeon
+                                                         When soft reseting Octeon from a remote PCIe/sRIO
+                                                         host, always read CIU_SOFT_RST (and wait for
+                                                         result) before writing SOFT_RST to '1'. */
+#else
+	uint64_t soft_rst                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_ciu_soft_rst_s            cn30xx;
+	struct cvmx_ciu_soft_rst_s            cn31xx;
+	struct cvmx_ciu_soft_rst_s            cn38xx;
+	struct cvmx_ciu_soft_rst_s            cn38xxp2;
+	struct cvmx_ciu_soft_rst_s            cn50xx;
+	struct cvmx_ciu_soft_rst_s            cn52xx;
+	struct cvmx_ciu_soft_rst_s            cn52xxp1;
+	struct cvmx_ciu_soft_rst_s            cn56xx;
+	struct cvmx_ciu_soft_rst_s            cn56xxp1;
+	struct cvmx_ciu_soft_rst_s            cn58xx;
+	struct cvmx_ciu_soft_rst_s            cn58xxp1;
+	struct cvmx_ciu_soft_rst_s            cn63xx;
+	struct cvmx_ciu_soft_rst_s            cn63xxp1;
+};
+typedef union cvmx_ciu_soft_rst cvmx_ciu_soft_rst_t;
+
+/**
+ * cvmx_ciu_tim#
+ */
+union cvmx_ciu_timx
+{
+	uint64_t u64;
+	struct cvmx_ciu_timx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t one_shot                     : 1;  /**< One-shot mode */
+	uint64_t len                          : 36; /**< Timeout length in core clock cycles
+                                                         Periodic interrupts will occur every LEN+1 core
+                                                         clock cycles when ONE_SHOT==0
+                                                         Timer disabled when LEN==0 */
+#else
+	uint64_t len                          : 36;
+	uint64_t one_shot                     : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_ciu_timx_s                cn30xx;
+	struct cvmx_ciu_timx_s                cn31xx;
+	struct cvmx_ciu_timx_s                cn38xx;
+	struct cvmx_ciu_timx_s                cn38xxp2;
+	struct cvmx_ciu_timx_s                cn50xx;
+	struct cvmx_ciu_timx_s                cn52xx;
+	struct cvmx_ciu_timx_s                cn52xxp1;
+	struct cvmx_ciu_timx_s                cn56xx;
+	struct cvmx_ciu_timx_s                cn56xxp1;
+	struct cvmx_ciu_timx_s                cn58xx;
+	struct cvmx_ciu_timx_s                cn58xxp1;
+	struct cvmx_ciu_timx_s                cn63xx;
+	struct cvmx_ciu_timx_s                cn63xxp1;
+};
+typedef union cvmx_ciu_timx cvmx_ciu_timx_t;
+
+/**
+ * cvmx_ciu_wdog#
+ */
+union cvmx_ciu_wdogx
+{
+	uint64_t u64;
+	struct cvmx_ciu_wdogx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t gstopen                      : 1;  /**< GSTOPEN */
+	uint64_t dstop                        : 1;  /**< DSTOP */
+	uint64_t cnt                          : 24; /**< Number of 256-cycle intervals until next watchdog
+                                                         expiration.  Cleared on write to associated
+                                                         CIU_PP_POKE register. */
+	uint64_t len                          : 16; /**< Watchdog time expiration length
+                                                         The 16 bits of LEN represent the most significant
+                                                         bits of a 24 bit decrementer that decrements
+                                                         every 256 cycles.
+                                                         LEN must be set > 0 */
+	uint64_t state                        : 2;  /**< Watchdog state
+                                                         number of watchdog time expirations since last
+                                                         PP poke.  Cleared on write to associated
+                                                         CIU_PP_POKE register. */
+	uint64_t mode                         : 2;  /**< Watchdog mode
+                                                         0 = Off
+                                                         1 = Interrupt Only
+                                                         2 = Interrupt + NMI
+                                                         3 = Interrupt + NMI + Soft-Reset */
+#else
+	uint64_t mode                         : 2;
+	uint64_t state                        : 2;
+	uint64_t len                          : 16;
+	uint64_t cnt                          : 24;
+	uint64_t dstop                        : 1;
+	uint64_t gstopen                      : 1;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} s;
+	struct cvmx_ciu_wdogx_s               cn30xx;
+	struct cvmx_ciu_wdogx_s               cn31xx;
+	struct cvmx_ciu_wdogx_s               cn38xx;
+	struct cvmx_ciu_wdogx_s               cn38xxp2;
+	struct cvmx_ciu_wdogx_s               cn50xx;
+	struct cvmx_ciu_wdogx_s               cn52xx;
+	struct cvmx_ciu_wdogx_s               cn52xxp1;
+	struct cvmx_ciu_wdogx_s               cn56xx;
+	struct cvmx_ciu_wdogx_s               cn56xxp1;
+	struct cvmx_ciu_wdogx_s               cn58xx;
+	struct cvmx_ciu_wdogx_s               cn58xxp1;
+	struct cvmx_ciu_wdogx_s               cn63xx;
+	struct cvmx_ciu_wdogx_s               cn63xxp1;
+};
+typedef union cvmx_ciu_wdogx cvmx_ciu_wdogx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ciu.h b/sys/contrib/octeon-sdk/cvmx-ciu.h
deleted file mode 100644
index aca6c4f..0000000
--- a/sys/contrib/octeon-sdk/cvmx-ciu.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * Interface to the hardware Interrupt Unit.
- *
- * <hr>$Revision: 41586 $<hr>
- */
-
-#ifndef __CVMX_CIU_H__
-#define __CVMX_CIU_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-clock.c b/sys/contrib/octeon-sdk/cvmx-clock.c
new file mode 100644
index 0000000..dfc17c3
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-clock.c
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to Core, IO and DDR Clock.
+ *
+ * <hr>$Revision: 45089 $<hr>
+*/
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#endif
+#include "cvmx.h"
+#endif
+
+#ifndef CVMX_BUILD_FOR_UBOOT
+static uint64_t rate_eclk = 0;
+static uint64_t rate_sclk = 0;
+static uint64_t rate_dclk = 0;
+#endif
+
+/**
+ * Get clock rate based on the clock type.
+ *
+ * @param clock - Enumeration of the clock type.
+ * @return      - return the clock rate.
+ */
+uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
+{
+    const uint64_t REF_CLOCK = 50000000;
+
+#ifdef CVMX_BUILD_FOR_UBOOT
+    uint64_t rate_eclk = 0;
+    uint64_t rate_sclk = 0;
+    uint64_t rate_dclk = 0;
+#endif
+
+    if (cvmx_unlikely(!rate_eclk))
+    {
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+        {
+            cvmx_npei_dbg_data_t npei_dbg_data;
+            npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+            rate_eclk =  REF_CLOCK * npei_dbg_data.s.c_mul;
+            rate_sclk = rate_eclk;
+        }
+        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        {
+            cvmx_mio_rst_boot_t mio_rst_boot;
+            mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+            rate_eclk =  REF_CLOCK * mio_rst_boot.s.c_mul;
+            rate_sclk = REF_CLOCK * mio_rst_boot.s.pnr_mul;
+        }
+        else
+        {
+            cvmx_dbg_data_t dbg_data;
+            dbg_data.u64 = cvmx_read_csr(CVMX_DBG_DATA);
+            rate_eclk =  REF_CLOCK * dbg_data.s.c_mul;
+            rate_sclk = rate_eclk;
+        }
+    }
+
+    switch (clock)
+    {
+        case CVMX_CLOCK_SCLK:
+        case CVMX_CLOCK_TIM:
+        case CVMX_CLOCK_IPD:
+            return rate_sclk;
+
+        case CVMX_CLOCK_RCLK:
+        case CVMX_CLOCK_CORE:
+            return rate_eclk;
+
+        case CVMX_CLOCK_DDR:
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(__OCTEON_NEWLIB__)
+            if (cvmx_unlikely(!rate_dclk))
+                rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
+#endif
+            return rate_dclk;
+    }
+
+    cvmx_dprintf("cvmx_clock_get_rate: Unknown clock type\n");
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_clock_get_rate);
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-clock.h b/sys/contrib/octeon-sdk/cvmx-clock.h
new file mode 100644
index 0000000..8d74731
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-clock.h
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to Core, IO and DDR Clock.
+ *
+ * <hr>$Revision: 45089 $<hr>
+*/
+
+#ifndef __CVMX_CLOCK_H__
+#define __CVMX_CLOCK_H__
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-lmcx-defs.h>
+#else
+#include "cvmx.h"
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of different Clocks in Octeon.
+ */
+typedef enum{
+    CVMX_CLOCK_RCLK,        /**< Clock used by cores, coherent bus and L2 cache. */
+    CVMX_CLOCK_SCLK,        /**< Clock used by IO blocks. */
+    CVMX_CLOCK_DDR,         /**< Clock used by DRAM */
+    CVMX_CLOCK_CORE,        /**< Alias for CVMX_CLOCK_RCLK */
+    CVMX_CLOCK_TIM,         /**< Alias for CVMX_CLOCK_SCLK */
+    CVMX_CLOCK_IPD,         /**< Alias for CVMX_CLOCK_SCLK */
+} cvmx_clock_t;
+
+/**
+ * Get cycle count based on the clock type.
+ *
+ * @param clock - Enumeration of the clock type.
+ * @return      - Get the number of cycles executed so far.
+ */
+static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
+{
+    switch(clock)
+    {
+        case CVMX_CLOCK_RCLK:
+        case CVMX_CLOCK_CORE:
+        {
+#ifndef __mips__
+            return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+#elif defined(CVMX_ABI_O32)
+            uint32_t tmp_low, tmp_hi;
+
+            asm volatile (
+               "   .set push                    \n"
+               "   .set mips64r2                \n"
+               "   .set noreorder               \n"
+               "   rdhwr %[tmpl], $31           \n"
+               "   dsrl  %[tmph], %[tmpl], 32   \n"
+               "   sll   %[tmpl], 0             \n"
+               "   sll   %[tmph], 0             \n"
+               "   .set pop                 \n"
+                  : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
+
+            return(((uint64_t)tmp_hi << 32) + tmp_low);
+#else
+            uint64_t cycle;
+            CVMX_RDHWR(cycle, 31);
+            return(cycle);
+#endif
+        }
+
+        case CVMX_CLOCK_SCLK:
+        case CVMX_CLOCK_TIM:
+        case CVMX_CLOCK_IPD:
+            return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+
+        case CVMX_CLOCK_DDR:
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
+            else
+                return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));
+    }
+
+    cvmx_dprintf("cvmx_clock_get_count: Unknown clock type\n");
+    return 0;
+}
+
+extern uint64_t cvmx_clock_get_rate(cvmx_clock_t clock);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_CLOCK_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-cmd-queue.c b/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
index f82a31d..23617b8 100644
--- a/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
+++ b/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,25 +42,45 @@
 
 
 
+
 /**
  * @file
  *
  * Support functions for managing command queues used for
  * various hardware blocks.
  *
- * <hr>$Revision: 42150 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#else
 #include "cvmx.h"
+#include "cvmx-bootmem.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
 #include "cvmx-fpa.h"
 #include "cvmx-cmd-queue.h"
-#include "cvmx-bootmem.h"
+#endif
+
 
 /**
  * This application uses this pointer to access the global queue
  * state. It points to a bootmem named block.
  */
-CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr = NULL;
-
+CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(__cvmx_cmd_queue_state_ptr);
+#endif
 
 /**
  * @INTERNAL
@@ -78,7 +99,7 @@ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
         return CVMX_CMD_QUEUE_SUCCESS;
 
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#if CONFIG_CAVIUM_RESERVE32
+#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
     if (octeon_reserve32_memory)
         __cvmx_cmd_queue_state_ptr = cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
                                                               octeon_reserve32_memory,
@@ -94,7 +115,7 @@ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
         memset(__cvmx_cmd_queue_state_ptr, 0, sizeof(*__cvmx_cmd_queue_state_ptr));
     else
     {
-        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
+        const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
         if (block_desc)
             __cvmx_cmd_queue_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
         else
@@ -149,17 +170,17 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
     {
         if (max_depth != (int)qstate->max_depth)
         {
-            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different max_depth (%d).\n", (int)qstate->max_depth);
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different max_depth (%d).\n", (int)qstate->max_depth);
             return CVMX_CMD_QUEUE_INVALID_PARAM;
         }
         if (fpa_pool != qstate->fpa_pool)
         {
-            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different FPA pool (%u).\n", qstate->fpa_pool);
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different FPA pool (%u).\n", qstate->fpa_pool);
             return CVMX_CMD_QUEUE_INVALID_PARAM;
         }
         if ((pool_size>>3)-1 != qstate->pool_size_m1)
         {
-            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different FPA pool size (%u).\n", (qstate->pool_size_m1+1)<<3);
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different FPA pool size (%u).\n", (qstate->pool_size_m1+1)<<3);
             return CVMX_CMD_QUEUE_INVALID_PARAM;
         }
         CVMX_SYNCWS;
@@ -275,11 +296,18 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
             // FIXME: Implement other lengths
             return 0;
         case CVMX_CMD_QUEUE_DMA_BASE:
+            if (octeon_has_feature(OCTEON_FEATURE_NPEI))
             {
                 cvmx_npei_dmax_counts_t dmax_counts;
                 dmax_counts.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS(queue_id & 0x7));
                 return dmax_counts.s.dbell;
             }
+            else
+            {
+                cvmx_dpi_dmax_counts_t dmax_counts;
+                dmax_counts.u64 = cvmx_read_csr(CVMX_DPI_DMAX_COUNTS(queue_id & 0x7));
+                return dmax_counts.s.dbell;
+            }
         case CVMX_CMD_QUEUE_END:
             return CVMX_CMD_QUEUE_INVALID_PARAM;
     }
@@ -289,7 +317,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
 
 /**
  * Return the command buffer to be written to. The purpose of this
- * function is to allow CVMX routine access t othe low level buffer
+ * function is to allow CVMX routine access to the low level buffer
  * for initial hardware setup. User applications should not call this
  * function directly.
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-cmd-queue.h b/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
index f5ba5f3..29c0d256 100644
--- a/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
+++ b/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -60,7 +62,7 @@
  * commands.
  *
  * Even though most software will never directly interact with
- * cvmx-cmd-queue, knowledge of its internal working can help
+ * cvmx-cmd-queue, knowledge of its internal workings can help
  * in diagnosing performance problems and help with debugging.
  *
  * Command queue pointers are stored in a global named block
@@ -86,16 +88,17 @@
  * internal cycle counter to completely eliminate any causes of
  * bus traffic.
  *
- * <hr> $Revision: 42150 $ <hr>
+ * <hr> $Revision: 50049 $ <hr>
  */
 
 #ifndef __CVMX_CMD_QUEUE_H__
 #define __CVMX_CMD_QUEUE_H__
 
-#ifndef CVMX_DONT_INCLUDE_CONFIG
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 #include "executive-config.h"
 #include "cvmx-config.h"
 #endif
+
 #include "cvmx-fpa.h"
 
 #ifdef	__cplusplus
@@ -130,7 +133,7 @@ typedef enum
 } cvmx_cmd_queue_id_t;
 
 /**
- * Command write operations can fail if the comamnd queue needs
+ * Command write operations can fail if the command queue needs
  * a new buffer and the associated FPA pool is empty. It can also
  * fail if the number of queued command words reaches the maximum
  * set at initialization.
@@ -153,14 +156,14 @@ typedef struct
     uint64_t base_ptr_div128: 29;   /**< Top of command buffer pointer shifted 7 */
     uint64_t unused2        : 6;
     uint64_t pool_size_m1   : 13;   /**< FPA buffer size in 64bit words minus 1 */
-    uint64_t index          : 13;   /**< Number of comamnds already used in buffer */
+    uint64_t index          : 13;   /**< Number of commands already used in buffer */
 } __cvmx_cmd_queue_state_t;
 
 /**
- * This structure contains the global state of all comamnd queues.
+ * This structure contains the global state of all command queues.
  * It is stored in a bootmem named block and shared by all
- * applications running on Octeon. Tickets are stored in a differnet
- * cahce line that queue information to reduce the contention on the
+ * applications running on Octeon. Tickets are stored in a different
+ * cache line that queue information to reduce the contention on the
  * ll/sc used to get a ticket. If this is not the case, the update
  * of queue state causes the ll/sc to fail quite often.
  */
@@ -209,7 +212,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
 
 /**
  * Return the command buffer to be written to. The purpose of this
- * function is to allow CVMX routine access t othe low level buffer
+ * function is to allow CVMX routine access to the low level buffer
  * for initial hardware setup. User applications should not call this
  * function directly.
  *
@@ -292,8 +295,12 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, __cvmx_cm
  */
 static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
 {
-    qptr->now_serving++;
-    CVMX_SYNCWS;
+    uint8_t ns;
+
+    ns = qptr->now_serving + 1;
+    CVMX_SYNCWS; /* Order queue manipulation with respect to the unlock.  */
+    qptr->now_serving = ns;
+    CVMX_SYNCWS; /* nudge out the unlock. */
 }
 
 
@@ -320,7 +327,7 @@ static inline __cvmx_cmd_queue_state_t *__cvmx_cmd_queue_get_state(cvmx_cmd_queu
 
 /**
  * Write an arbitrary number of command words to a command queue.
- * This is a generic function; the fixed number of comamnd word
+ * This is a generic function; the fixed number of command word
  * functions yield higher performance.
  *
  * @param queue_id  Hardware command queue to write to
@@ -329,7 +336,7 @@ static inline __cvmx_cmd_queue_state_t *__cvmx_cmd_queue_get_state(cvmx_cmd_queu
  *                  updates. If you don't use this locking you must ensure
  *                  exclusivity some other way. Locking is strongly recommended.
  * @param cmd_count Number of command words to write
- * @param cmds      Array of comamnds to write
+ * @param cmds      Array of commands to write
  *
  * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
  */
@@ -377,7 +384,7 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t q
     {
         uint64_t *ptr;
         int count;
-        /* We need a new comamnd buffer. Fail if there isn't one available */
+        /* We need a new command buffer. Fail if there isn't one available */
         uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
         if (cvmx_unlikely(new_buffer == NULL))
         {
@@ -466,7 +473,7 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
         /* Figure out how many command words will fit in this buffer. One
             location will be needed for the next buffer pointer */
         int count = qptr->pool_size_m1 - qptr->index;
-        /* We need a new comamnd buffer. Fail if there isn't one available */
+        /* We need a new command buffer. Fail if there isn't one available */
         uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
         if (cvmx_unlikely(new_buffer == NULL))
         {
@@ -557,7 +564,7 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
         /* Figure out how many command words will fit in this buffer. One
             location will be needed for the next buffer pointer */
         int count = qptr->pool_size_m1 - qptr->index;
-        /* We need a new comamnd buffer. Fail if there isn't one available */
+        /* We need a new command buffer. Fail if there isn't one available */
         uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
         if (cvmx_unlikely(new_buffer == NULL))
         {
diff --git a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
index 3a3c43e..0b03655 100644
--- a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
+++ b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
index af65496..ecd8b5a 100644
--- a/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
+++ b/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 #ifndef __CVMX_CN3010_EVB_HS5_H__
 #define __CVMX_CN3010_EVB_HS5_H__
 
@@ -49,7 +51,7 @@
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-compactflash.c b/sys/contrib/octeon-sdk/cvmx-compactflash.c
index eca620a..c5123fb 100644
--- a/sys/contrib/octeon-sdk/cvmx-compactflash.c
+++ b/sys/contrib/octeon-sdk/cvmx-compactflash.c
@@ -1,42 +1,44 @@
 /***********************license start***************
- *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
+
 #include "cvmx.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-compactflash.h"
@@ -49,20 +51,20 @@
 /**
  * Convert nanosecond based time to setting used in the
  * boot bus timing register, based on timing multiple
- * 
- * 
+ *
+ *
  */
 static uint32_t ns_to_tim_reg(int tim_mult, uint32_t nsecs)
 {
 	uint32_t val;
 
 	/* Compute # of eclock periods to get desired duration in nanoseconds */
-	val = FLASH_RoundUP(nsecs * (cvmx_sysinfo_get()->cpu_clock_hz/1000000), 1000);
-	
+	val = FLASH_RoundUP(nsecs * (cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000), 1000);
+
 	/* Factor in timing multiple, if not 1 */
 	if (tim_mult != 1)
 		val = FLASH_RoundUP(val, tim_mult);
-	
+
 	return (val);
 }
 
@@ -86,7 +88,7 @@ uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data,
             return 0;
 
         word53_field_valid = ident_data[53];
-        word63_mwdma = ident_data[63]; 
+        word63_mwdma = ident_data[63];
         word163_adv_timing_info = ident_data[163];
 
 	dma_tim.u64 = 0;
@@ -146,31 +148,31 @@ uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data,
 			To = 80;
 			Td = 55;
 			Tkr = 20;
-			
+
 			oe_a = Td + 20;  // Td (Seem to need more margin here....
 			oe_n = MAX(To - oe_a, Tkr);  // Tkr from cf spec, lengthened to meet To
-			
+
 			// oe_n + oe_h must be >= To (cycle time)
 			dma_acks = 0; //Ti
 			dma_ackh = 5; // Tj
-			
+
 			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
-			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+			pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
 			break;
 		case 3:
 			To = 100;
 			Td = 65;
 			Tkr = 20;
-			
+
 			oe_a = Td + 20;  // Td (Seem to need more margin here....
 			oe_n = MAX(To - oe_a, Tkr);  // Tkr from cf spec, lengthened to meet To
-			
+
 			// oe_n + oe_h must be >= To (cycle time)
 			dma_acks = 0; //Ti
 			dma_ackh = 5; // Tj
-			
+
 			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
-			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+			pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
 			break;
 		case 2:
 			// +20 works
@@ -190,11 +192,11 @@ uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data,
 			// oe_n + oe_h must be >= To (cycle time)
 			dma_acks = 0 + 20; //Ti
 			dma_ackh = 5; // Tj
-			
+
 			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
-			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+			pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
                         // no fudge needed on pause
-			
+
 			break;
 		case 1:
 		case 0:
@@ -206,24 +208,24 @@ uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data,
 
         if (mwdma_mode_ptr)
             *mwdma_mode_ptr = mwdma_mode;
-	
+
 	dma_tim.s.dmack_pi = 1;
-	
+
 	dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
 	dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
-	
+
 	dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, dma_acks);
-	dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); 
-	
+	dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
+
 	dma_tim.s.dmarq = dma_arq;
 	dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
-	
+
 	dma_tim.s.rd_dly = 0; /* Sample right on edge */
-	
+
 	/*  writes only */
 	dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
 	dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
-	
+
 #if 0
 	cvmx_dprintf("ns to ticks (mult %d) of %d is: %d\n", TIM_MULT, 60, ns_to_tim_reg(60));
 	cvmx_dprintf("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
@@ -335,7 +337,7 @@ void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode)
             break;
     }
     /* Convert times in ns to clock cycles, rounding up */
-    clocks_us = FLASH_RoundUP((uint64_t)cvmx_sysinfo_get()->cpu_clock_hz, 1000000);
+    clocks_us = FLASH_RoundUP(cvmx_clock_get_rate(CVMX_CLOCK_SCLK), 1000000);
 
     /* Convert times in clock cycles, rounding up. Octeon parameters are in
         minus one notation, so take off one after the conversion */
diff --git a/sys/contrib/octeon-sdk/cvmx-compactflash.h b/sys/contrib/octeon-sdk/cvmx-compactflash.h
index dd6d9cf..b07512b 100644
--- a/sys/contrib/octeon-sdk/cvmx-compactflash.h
+++ b/sys/contrib/octeon-sdk/cvmx-compactflash.h
@@ -1,43 +1,45 @@
 /***********************license start***************
- *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
+
 #ifndef __CVMX_COMPACTFLASH_H__
 #define __CVMX_COMPACTFLASH_H__
 #ifdef	__cplusplus
diff --git a/sys/contrib/octeon-sdk/cvmx-core.c b/sys/contrib/octeon-sdk/cvmx-core.c
index 43d8eee..6afbad2 100644
--- a/sys/contrib/octeon-sdk/cvmx-core.c
+++ b/sys/contrib/octeon-sdk/cvmx-core.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,25 @@
 
 
 
+
 /**
  * @file
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49862 $<hr>
  *
  */
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-core.h>
+#else
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-core.h"
+#endif
 
 
 /**
@@ -64,21 +72,15 @@
  * @param lo1    lo1 register value
  * @param page_mask   pagemask register value
  *
- * @return Success: TLB index used (0-31) or (0-63) for OCTEON Plus
- *         Failure: -1
+ * @return Success: TLB index used (0-31 Octeon, 0-63 Octeon+, or 0-127
+ *         Octeon2). Failure: -1
  */
 int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
 {
     uint32_t index;
-    uint32_t index_limit = 31;
-
-    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
-    {
-        index_limit=63;
-    }
 
     CVMX_MF_TLB_WIRED(index);
-    if (index >= index_limit)
+    if (index >= (unsigned int)cvmx_core_get_tlb_entries())
     {
         return(-1);
     }
@@ -145,3 +147,16 @@ int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_
     return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
 
 }
+
+/**
+ * Return number of TLB entries.
+ */
+int cvmx_core_get_tlb_entries(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        return 32;
+    else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        return 64;
+    else
+        return 128;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-core.h b/sys/contrib/octeon-sdk/cvmx-core.h
index e498c57..3f59761 100644
--- a/sys/contrib/octeon-sdk/cvmx-core.h
+++ b/sys/contrib/octeon-sdk/cvmx-core.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -117,6 +119,10 @@ typedef enum
     CVMX_CORE_PERF_SYNC      = 56,   /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
     CVMX_CORE_PERF_SYNCIOB   = 57,   /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
     CVMX_CORE_PERF_SYNCW     = 58,   /**< Number of SYNCWs */
+    /* Added in CN63XX */
+    CVMX_CORE_PERF_ERETMIS   = 64,   /**< D/eret mispredicts */
+    CVMX_CORE_PERF_LIKMIS    = 65,   /**< Branch likely mispredicts */
+    CVMX_CORE_PERF_HAZTR     = 66,   /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */
     CVMX_CORE_PERF_MAX               /**< This not a counter, just a marker for the highest number */
 } cvmx_core_perf_t;
 
@@ -128,15 +134,27 @@ typedef union
     uint32_t u32;
     struct
     {
+#if __BYTE_ORDER == __BIG_ENDIAN
         uint32_t m              : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
         uint32_t w              : 1; /**< Set to 1 indicating coutners are 64 bit */
-        uint32_t reserved_11_29 :19;
-        cvmx_core_perf_t event  : 6; /**< Selects the event to be counted by the corresponding Counter Register */
+        uint32_t reserved_11_29 :15;
+        cvmx_core_perf_t event  :10; /**< Selects the event to be counted by the corresponding Counter Register */
         uint32_t ie             : 1; /**< Count in interrupt context */
         uint32_t u              : 1; /**< Count in user mode */
         uint32_t s              : 1; /**< Count in supervisor mode */
         uint32_t k              : 1; /**< Count in kernel mode */
         uint32_t ex             : 1; /**< Count in exception context */
+#else
+	uint32_t ex             : 1;
+        uint32_t k              : 1;
+        uint32_t s              : 1;
+        uint32_t u              : 1;
+        uint32_t ie             : 1;
+        uint32_t event          :10;
+        uint32_t reserved_11_29 :15;
+        uint32_t w              : 1;
+        uint32_t m              : 1;
+#endif
     } s;
 } cvmx_core_perf_control_t;
 
@@ -159,6 +177,10 @@ int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_
 int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
 int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
 
+/**
+ * Return number of TLB entries.
+ */
+int cvmx_core_get_tlb_entries(void);
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-coremask.c b/sys/contrib/octeon-sdk/cvmx-coremask.c
index 5574c83..8c59075 100644
--- a/sys/contrib/octeon-sdk/cvmx-coremask.c
+++ b/sys/contrib/octeon-sdk/cvmx-coremask.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -49,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-coremask.h b/sys/contrib/octeon-sdk/cvmx-coremask.h
index 132e462..d0c5825 100644
--- a/sys/contrib/octeon-sdk/cvmx-coremask.h
+++ b/sys/contrib/octeon-sdk/cvmx-coremask.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -49,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-crypto.c b/sys/contrib/octeon-sdk/cvmx-crypto.c
new file mode 100644
index 0000000..46223fb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-crypto.c
@@ -0,0 +1,78 @@
+
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper utilities for enabling crypto.
+ *
+ * <hr>$Revision: $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+int cvmx_crypto_dormant_enable(uint64_t key)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_CRYPTO))
+        return 1;
+
+    if (octeon_has_feature(OCTEON_FEATURE_DORM_CRYPTO)) {
+        cvmx_rnm_eer_key_t v;
+        v.s.key = key;
+        cvmx_write_csr(CVMX_RNM_EER_KEY, v.u64);
+    }
+
+    return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
+}
+
+uint64_t cvmx_crypto_dormant_dbg(void)
+{
+    cvmx_rnm_eer_dbg_t dbg;
+
+    if (!octeon_has_feature(OCTEON_FEATURE_DORM_CRYPTO))
+        return 0;
+
+    dbg.u64 = cvmx_read_csr(CVMX_RNM_EER_DBG);
+    return dbg.s.dat;
+}
+
+
diff --git a/sys/contrib/octeon-sdk/cvmx-crypto.h b/sys/contrib/octeon-sdk/cvmx-crypto.h
new file mode 100644
index 0000000..c601431
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-crypto.h
@@ -0,0 +1,70 @@
+
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper utilities for enabling crypto.
+ *
+ * <hr>$Revision: $<hr>
+ */
+
+#ifndef __CVMX_CRYPTO_H__
+#define __CVMX_CRYPTO_H__
+/**
+ * Enable the dormant crypto functions.  If crypto is not already
+ * enabled and it is possible to enable it, write the enable key.
+ *
+ * @param key  The dormant crypto enable key value.
+ *
+ * @return true if crypto is (or has been) enabled.
+ */
+extern int cvmx_crypto_dormant_enable(uint64_t key);
+
+/**
+ * Read the crypto dormant debug value.
+ *
+ * @return The RNM_EER_DBG.DAT value, or zero if the feature is not
+ * enabled.
+ */
+extern uint64_t cvmx_crypto_dormant_dbg(void);
+
+#endif /* __CVMX_CRYPTO_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-addresses.h b/sys/contrib/octeon-sdk/cvmx-csr-addresses.h
deleted file mode 100644
index e9ba13e..0000000
--- a/sys/contrib/octeon-sdk/cvmx-csr-addresses.h
+++ /dev/null
@@ -1,15490 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Configuration and status register (CSR) address and for
- * Octeon. Include cvmx-csr.h instead of this file directly.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision: 41586 $<hr>
- *
- */
-#ifndef __CVMX_CSR_ADDRESSES_H__
-#define __CVMX_CSR_ADDRESSES_H__
-
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-#include "cvmx-warn.h"
-#endif
-
-#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
-static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
-}
-
-#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
-static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
-}
-
-#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC()
-static inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
-}
-
-#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC()
-static inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
-}
-
-static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + (offset&1)*8;
-}
-
-#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
-static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
-}
-
-#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
-static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
-}
-
-static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + (offset&1)*2048;
-}
-
-#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
-static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + (offset&1)*2048;
-}
-
-#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
-}
-
-#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
-}
-
-#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
-}
-
-#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
-}
-
-#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
-}
-
-#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
-}
-
-#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
-}
-
-#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
-}
-
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
-}
-
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
-static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
-}
-
-#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
-static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
-}
-
-#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
-static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
-}
-
-static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000180ull) + (block_id&0)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000188ull) + (block_id&0)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000190ull) + (block_id&0)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + (block_id&1)*0x8000000ull;
-}
-
-#define CVMX_CIU_BIST CVMX_CIU_BIST_FUNC()
-static inline uint64_t CVMX_CIU_BIST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000730ull);
-}
-
-#define CVMX_CIU_DINT CVMX_CIU_DINT_FUNC()
-static inline uint64_t CVMX_CIU_DINT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000720ull);
-}
-
-#define CVMX_CIU_FUSE CVMX_CIU_FUSE_FUNC()
-static inline uint64_t CVMX_CIU_FUSE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000728ull);
-}
-
-#define CVMX_CIU_GSTOP CVMX_CIU_GSTOP_FUNC()
-static inline uint64_t CVMX_CIU_GSTOP_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000710ull);
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000200ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000002200ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000006200ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000208ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000002208ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
-        cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000006208ull) + (offset&63)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + (offset&15)*16;
-}
-
-static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
-        cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000000ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + (offset&15)*8;
-}
-
-#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
-static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000108ull);
-}
-
-static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset&15)*8;
-}
-
-static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset&15)*8;
-}
-
-#define CVMX_CIU_NMI CVMX_CIU_NMI_FUNC()
-static inline uint64_t CVMX_CIU_NMI_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000718ull);
-}
-
-#define CVMX_CIU_PCI_INTA CVMX_CIU_PCI_INTA_FUNC()
-static inline uint64_t CVMX_CIU_PCI_INTA_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000750ull);
-}
-
-#define CVMX_CIU_PP_DBG CVMX_CIU_PP_DBG_FUNC()
-static inline uint64_t CVMX_CIU_PP_DBG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000708ull);
-}
-
-static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset&15)*8;
-}
-
-#define CVMX_CIU_PP_RST CVMX_CIU_PP_RST_FUNC()
-static inline uint64_t CVMX_CIU_PP_RST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000700ull);
-}
-
-#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
-static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000760ull);
-}
-
-#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
-static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000768ull);
-}
-
-#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
-static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000770ull);
-}
-
-#define CVMX_CIU_SOFT_BIST CVMX_CIU_SOFT_BIST_FUNC()
-static inline uint64_t CVMX_CIU_SOFT_BIST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000738ull);
-}
-
-#define CVMX_CIU_SOFT_PRST CVMX_CIU_SOFT_PRST_FUNC()
-static inline uint64_t CVMX_CIU_SOFT_PRST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000748ull);
-}
-
-#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
-static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000758ull);
-}
-
-#define CVMX_CIU_SOFT_RST CVMX_CIU_SOFT_RST_FUNC()
-static inline uint64_t CVMX_CIU_SOFT_RST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000740ull);
-}
-
-static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000480ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset&15)*8;
-}
-
-#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
-static inline uint64_t CVMX_DBG_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
-}
-
-#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
-static inline uint64_t CVMX_DFA_BST0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
-}
-
-#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
-static inline uint64_t CVMX_DFA_BST1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
-}
-
-#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
-static inline uint64_t CVMX_DFA_CFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000000ull);
-}
-
-#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
-static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001370000000000ull);
-}
-
-#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000210ull);
-}
-
-#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000080ull);
-}
-
-#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000208ull);
-}
-
-#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000090ull);
-}
-
-#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000268ull);
-}
-
-#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000078ull);
-}
-
-#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000260ull);
-}
-
-#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000070ull);
-}
-
-#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000088ull);
-}
-
-#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
-static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000218ull);
-}
-
-#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
-static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001370600000000ull);
-}
-
-#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
-static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001370200000000ull);
-}
-
-#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
-static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000200ull);
-}
-
-#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
-static inline uint64_t CVMX_DFA_ERR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000028ull);
-}
-
-#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
-static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000008ull);
-}
-
-#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
-static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000010ull);
-}
-
-#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
-static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000060ull);
-}
-
-#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
-static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000030ull);
-}
-
-#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
-static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000038ull);
-}
-
-#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
-static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000018ull);
-}
-
-#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
-static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000020ull);
-}
-
-#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
-static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000068ull);
-}
-
-#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
-static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000040ull);
-}
-
-#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
-static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000048ull);
-}
-
-#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
-static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000050ull);
-}
-
-#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
-static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180030000058ull);
-}
-
-#define CVMX_FPA_BIST_STATUS CVMX_FPA_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_FPA_BIST_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800280000E8ull);
-}
-
-#define CVMX_FPA_CTL_STATUS CVMX_FPA_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_FPA_CTL_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180028000050ull);
-}
-
-#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
-static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180028000000ull);
-}
-
-#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
-static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180028000058ull);
-}
-
-#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
-#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
-#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
-#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
-#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
-#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
-#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
-static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
-        cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180028000008ull) + (offset&7)*8 - 8*1;
-}
-
-static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
-        cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180028000060ull) + (offset&7)*8 - 8*1;
-}
-
-#define CVMX_FPA_INT_ENB CVMX_FPA_INT_ENB_FUNC()
-static inline uint64_t CVMX_FPA_INT_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180028000048ull);
-}
-
-#define CVMX_FPA_INT_SUM CVMX_FPA_INT_SUM_FUNC()
-static inline uint64_t CVMX_FPA_INT_SUM_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180028000040ull);
-}
-
-#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
-#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
-#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
-#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
-#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
-#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
-#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
-#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
-static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180028000098ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + (offset&7)*8;
-}
-
-#define CVMX_FPA_QUE_ACT CVMX_FPA_QUE_ACT_FUNC()
-static inline uint64_t CVMX_FPA_QUE_ACT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180028000138ull);
-}
-
-#define CVMX_FPA_QUE_EXP CVMX_FPA_QUE_EXP_FUNC()
-static inline uint64_t CVMX_FPA_QUE_EXP_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180028000130ull);
-}
-
-#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC()
-static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800280000D8ull);
-}
-
-#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC()
-static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800280000E0ull);
-}
-
-static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000030ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000028ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000060ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080005F8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((offset&15) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id&0)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000208ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
-}
-
-static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000780ull) + ((offset&1) + (block_id&0)*0x0ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004C0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004E0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004B0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000680ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800080004B8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000800ull) + (offset&15)*8;
-}
-
-#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
-static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
-}
-
-static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + (offset&3)*8;
-}
-
-#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
-static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
-}
-
-#define CVMX_GPIO_INT_CLR CVMX_GPIO_INT_CLR_FUNC()
-static inline uint64_t CVMX_GPIO_INT_CLR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000898ull);
-}
-
-#define CVMX_GPIO_RX_DAT CVMX_GPIO_RX_DAT_FUNC()
-static inline uint64_t CVMX_GPIO_RX_DAT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000880ull);
-}
-
-#define CVMX_GPIO_TX_CLR CVMX_GPIO_TX_CLR_FUNC()
-static inline uint64_t CVMX_GPIO_TX_CLR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000890ull);
-}
-
-#define CVMX_GPIO_TX_SET CVMX_GPIO_TX_SET_FUNC()
-static inline uint64_t CVMX_GPIO_TX_SET_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001070000000888ull);
-}
-
-static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
-        cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000000900ull) + (offset&31)*8 - 8*16;
-}
-
-#define CVMX_IOB_BIST_STATUS CVMX_IOB_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_IOB_BIST_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F00007F8ull);
-}
-
-#define CVMX_IOB_CTL_STATUS CVMX_IOB_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_IOB_CTL_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000050ull);
-}
-
-#define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
-}
-
-#define CVMX_IOB_FAU_TIMEOUT CVMX_IOB_FAU_TIMEOUT_FUNC()
-static inline uint64_t CVMX_IOB_FAU_TIMEOUT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000000ull);
-}
-
-#define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
-}
-
-#define CVMX_IOB_INB_CONTROL_MATCH CVMX_IOB_INB_CONTROL_MATCH_FUNC()
-static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000078ull);
-}
-
-#define CVMX_IOB_INB_CONTROL_MATCH_ENB CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC()
-static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000088ull);
-}
-
-#define CVMX_IOB_INB_DATA_MATCH CVMX_IOB_INB_DATA_MATCH_FUNC()
-static inline uint64_t CVMX_IOB_INB_DATA_MATCH_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000070ull);
-}
-
-#define CVMX_IOB_INB_DATA_MATCH_ENB CVMX_IOB_INB_DATA_MATCH_ENB_FUNC()
-static inline uint64_t CVMX_IOB_INB_DATA_MATCH_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000080ull);
-}
-
-#define CVMX_IOB_INT_ENB CVMX_IOB_INT_ENB_FUNC()
-static inline uint64_t CVMX_IOB_INT_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000060ull);
-}
-
-#define CVMX_IOB_INT_SUM CVMX_IOB_INT_SUM_FUNC()
-static inline uint64_t CVMX_IOB_INT_SUM_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000058ull);
-}
-
-#define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
-}
-
-#define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
-}
-
-#define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
-}
-
-#define CVMX_IOB_OUTB_CONTROL_MATCH CVMX_IOB_OUTB_CONTROL_MATCH_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000098ull);
-}
-
-#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F00000A8ull);
-}
-
-#define CVMX_IOB_OUTB_DATA_MATCH CVMX_IOB_OUTB_DATA_MATCH_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000090ull);
-}
-
-#define CVMX_IOB_OUTB_DATA_MATCH_ENB CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F00000A0ull);
-}
-
-#define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
-}
-
-#define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
-}
-
-#define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
-static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
-}
-
-#define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
-static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
-}
-
-#define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
-static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
-}
-
-#define CVMX_IPD_1ST_MBUFF_SKIP CVMX_IPD_1ST_MBUFF_SKIP_FUNC()
-static inline uint64_t CVMX_IPD_1ST_MBUFF_SKIP_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000000ull);
-}
-
-#define CVMX_IPD_1st_NEXT_PTR_BACK CVMX_IPD_1st_NEXT_PTR_BACK_FUNC()
-static inline uint64_t CVMX_IPD_1st_NEXT_PTR_BACK_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000150ull);
-}
-
-#define CVMX_IPD_2nd_NEXT_PTR_BACK CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC()
-static inline uint64_t CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000158ull);
-}
-
-#define CVMX_IPD_BIST_STATUS CVMX_IPD_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_IPD_BIST_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F00000007F8ull);
-}
-
-#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC()
-static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
-}
-
-#define CVMX_IPD_CLK_COUNT CVMX_IPD_CLK_COUNT_FUNC()
-static inline uint64_t CVMX_IPD_CLK_COUNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000338ull);
-}
-
-#define CVMX_IPD_CTL_STATUS CVMX_IPD_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_IPD_CTL_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000018ull);
-}
-
-#define CVMX_IPD_INT_ENB CVMX_IPD_INT_ENB_FUNC()
-static inline uint64_t CVMX_IPD_INT_ENB_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000160ull);
-}
-
-#define CVMX_IPD_INT_SUM CVMX_IPD_INT_SUM_FUNC()
-static inline uint64_t CVMX_IPD_INT_SUM_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000168ull);
-}
-
-#define CVMX_IPD_NOT_1ST_MBUFF_SKIP CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC()
-static inline uint64_t CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000008ull);
-}
-
-#define CVMX_IPD_PACKET_MBUFF_SIZE CVMX_IPD_PACKET_MBUFF_SIZE_FUNC()
-static inline uint64_t CVMX_IPD_PACKET_MBUFF_SIZE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000010ull);
-}
-
-#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC()
-static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000358ull);
-}
-
-static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
-        cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + (offset&63)*8 - 8*36;
-}
-
-static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + (offset&63)*8 - 8*36;
-}
-
-static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
-        cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
-        cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
-        cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319))))))
-        cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + (offset&511)*8;
-}
-
-#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC()
-static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000348ull);
-}
-
-#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC()
-static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000350ull);
-}
-
-#define CVMX_IPD_PTR_COUNT CVMX_IPD_PTR_COUNT_FUNC()
-static inline uint64_t CVMX_IPD_PTR_COUNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000320ull);
-}
-
-#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC()
-static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000340ull);
-}
-
-#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
-#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
-#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
-#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
-#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
-#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
-#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
-#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
-static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + (offset&7)*8;
-}
-
-#define CVMX_IPD_QUE0_FREE_PAGE_CNT CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC()
-static inline uint64_t CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000330ull);
-}
-
-#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC()
-static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F00000002D8ull);
-}
-
-#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
-static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
-}
-
-#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
-#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
-#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
-#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
-#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
-#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
-#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
-#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
-static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + (offset&7)*8;
-}
-
-#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC()
-static inline uint64_t CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000148ull);
-}
-
-#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC()
-static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000170ull);
-}
-
-#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
-static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
-}
-
-#define CVMX_IPD_WQE_FPA_QUEUE CVMX_IPD_WQE_FPA_QUEUE_FUNC()
-static inline uint64_t CVMX_IPD_WQE_FPA_QUEUE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000020ull);
-}
-
-#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC()
-static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00014F0000000360ull);
-}
-
-#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
-static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180020000018ull);
-}
-
-#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180020000010ull);
-}
-
-#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
-static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180020000008ull);
-}
-
-#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
-static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180020000000ull);
-}
-
-#define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC()
-static inline uint64_t CVMX_L2C_BST0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
-}
-
-#define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC()
-static inline uint64_t CVMX_L2C_BST1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
-}
-
-#define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC()
-static inline uint64_t CVMX_L2C_BST2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
-}
-
-#define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
-static inline uint64_t CVMX_L2C_CFG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000000ull);
-}
-
-#define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC()
-static inline uint64_t CVMX_L2C_DBG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000030ull);
-}
-
-#define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC()
-static inline uint64_t CVMX_L2C_DUT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000050ull);
-}
-
-#define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC()
-static inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000C8ull);
-}
-
-#define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC()
-static inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000D0ull);
-}
-
-#define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC()
-static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180080000100ull);
-}
-
-#define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC()
-static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000F8ull);
-}
-
-#define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC()
-static inline uint64_t CVMX_L2C_LCKBASE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000058ull);
-}
-
-#define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC()
-static inline uint64_t CVMX_L2C_LCKOFF_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000060ull);
-}
-
-#define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC()
-static inline uint64_t CVMX_L2C_LFB0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000038ull);
-}
-
-#define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC()
-static inline uint64_t CVMX_L2C_LFB1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000040ull);
-}
-
-#define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC()
-static inline uint64_t CVMX_L2C_LFB2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000048ull);
-}
-
-#define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC()
-static inline uint64_t CVMX_L2C_LFB3_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800000B8ull);
-}
-
-#define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC()
-static inline uint64_t CVMX_L2C_OOB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_OOB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000D8ull);
-}
-
-#define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC()
-static inline uint64_t CVMX_L2C_OOB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000E0ull);
-}
-
-#define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC()
-static inline uint64_t CVMX_L2C_OOB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000E8ull);
-}
-
-#define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC()
-static inline uint64_t CVMX_L2C_OOB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000F0ull);
-}
-
-#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
-#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
-#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
-#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
-#define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC()
-static inline uint64_t CVMX_L2C_PFCTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000090ull);
-}
-
-static inline uint64_t CVMX_L2C_PFCX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180080000098ull) + (offset&3)*8;
-}
-
-#define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC()
-static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800800000C0ull);
-}
-
-#define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
-static inline uint64_t CVMX_L2C_SPAR0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000068ull);
-}
-
-#define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC()
-static inline uint64_t CVMX_L2C_SPAR1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180080000070ull);
-}
-
-#define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC()
-static inline uint64_t CVMX_L2C_SPAR2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180080000078ull);
-}
-
-#define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC()
-static inline uint64_t CVMX_L2C_SPAR3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180080000080ull);
-}
-
-#define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC()
-static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000088ull);
-}
-
-#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
-static inline uint64_t CVMX_L2D_BST0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000780ull);
-}
-
-#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
-static inline uint64_t CVMX_L2D_BST1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000788ull);
-}
-
-#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
-static inline uint64_t CVMX_L2D_BST2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000790ull);
-}
-
-#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
-static inline uint64_t CVMX_L2D_BST3_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000798ull);
-}
-
-#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
-static inline uint64_t CVMX_L2D_ERR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000010ull);
-}
-
-#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
-static inline uint64_t CVMX_L2D_FADR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000018ull);
-}
-
-#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
-static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000020ull);
-}
-
-#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
-static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000028ull);
-}
-
-#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
-static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
-}
-
-#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
-static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
-}
-
-#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
-static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
-}
-
-#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
-static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
-}
-
-#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
-static inline uint64_t CVMX_L2T_ERR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180080000008ull);
-}
-
-#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
-static inline uint64_t CVMX_LED_BLINK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
-}
-
-#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
-static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
-}
-
-#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
-static inline uint64_t CVMX_LED_CYLON_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
-}
-
-#define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
-static inline uint64_t CVMX_LED_DBG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
-}
-
-#define CVMX_LED_EN CVMX_LED_EN_FUNC()
-static inline uint64_t CVMX_LED_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
-}
-
-#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
-static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
-}
-
-#define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
-static inline uint64_t CVMX_LED_PRT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
-}
-
-#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
-static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
-}
-
-static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + (offset&1)*16;
-}
-
-static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + (offset&1)*16;
-}
-
-static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000028ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000010ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000090ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000070ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000068ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000B8ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000018ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000088ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000C0ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000050ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000048ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000000ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000008ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000060ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000058ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000040ull) + (block_id&0)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000A8ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000B0ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000140ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000148ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000100ull) + ((offset&3) + (block_id&1)*0xC000000ull)*8;
-}
-
-static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800880000A0ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000078ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000030ull) + (block_id&1)*0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
-        cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180088000080ull) + (block_id&1)*0x60000000ull;
-}
-
-#define CVMX_MIO_BOOT_BIST_STAT CVMX_MIO_BOOT_BIST_STAT_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_BIST_STAT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800000000F8ull);
-}
-
-#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
-}
-
-static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000100ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000138ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000150ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000120ull) + (offset&3)*8;
-}
-
-#define CVMX_MIO_BOOT_ERR CVMX_MIO_BOOT_ERR_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_ERR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800000000A0ull);
-}
-
-#define CVMX_MIO_BOOT_INT CVMX_MIO_BOOT_INT_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_INT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800000000A8ull);
-}
-
-#define CVMX_MIO_BOOT_LOC_ADR CVMX_MIO_BOOT_LOC_ADR_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_LOC_ADR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000000090ull);
-}
-
-static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000080ull) + (offset&1)*8;
-}
-
-#define CVMX_MIO_BOOT_LOC_DAT CVMX_MIO_BOOT_LOC_DAT_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_LOC_DAT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000000098ull);
-}
-
-#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
-}
-
-static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000000ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000040ull) + (offset&7)*8;
-}
-
-#define CVMX_MIO_BOOT_THR CVMX_MIO_BOOT_THR_FUNC()
-static inline uint64_t CVMX_MIO_BOOT_THR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800000000B0ull);
-}
-
-static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001520ull) + (offset&3)*8;
-}
-
-#define CVMX_MIO_FUS_DAT0 CVMX_MIO_FUS_DAT0_FUNC()
-static inline uint64_t CVMX_MIO_FUS_DAT0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001400ull);
-}
-
-#define CVMX_MIO_FUS_DAT1 CVMX_MIO_FUS_DAT1_FUNC()
-static inline uint64_t CVMX_MIO_FUS_DAT1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001408ull);
-}
-
-#define CVMX_MIO_FUS_DAT2 CVMX_MIO_FUS_DAT2_FUNC()
-static inline uint64_t CVMX_MIO_FUS_DAT2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001410ull);
-}
-
-#define CVMX_MIO_FUS_DAT3 CVMX_MIO_FUS_DAT3_FUNC()
-static inline uint64_t CVMX_MIO_FUS_DAT3_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001418ull);
-}
-
-#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
-static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001550ull);
-}
-
-#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
-static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001420ull);
-}
-
-#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
-static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001580ull);
-}
-
-#define CVMX_MIO_FUS_PROG CVMX_MIO_FUS_PROG_FUNC()
-static inline uint64_t CVMX_MIO_FUS_PROG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001510ull);
-}
-
-#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
-static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001518ull);
-}
-
-#define CVMX_MIO_FUS_RCMD CVMX_MIO_FUS_RCMD_FUNC()
-static inline uint64_t CVMX_MIO_FUS_RCMD_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001500ull);
-}
-
-#define CVMX_MIO_FUS_SPR_REPAIR_RES CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC()
-static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001548ull);
-}
-
-#define CVMX_MIO_FUS_SPR_REPAIR_SUM CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC()
-static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001540ull);
-}
-
-#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
-static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001578ull);
-}
-
-#define CVMX_MIO_FUS_WADR CVMX_MIO_FUS_WADR_FUNC()
-static inline uint64_t CVMX_MIO_FUS_WADR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180000001508ull);
-}
-
-#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
-static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000168ull);
-}
-
-#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
-static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000170ull);
-}
-
-#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
-static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000178ull);
-}
-
-#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
-static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001448ull);
-}
-
-#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
-static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
-        cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001440ull);
-}
-
-static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001010ull) + (offset&1)*512;
-}
-
-static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001000ull) + (offset&1)*512;
-}
-
-static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001018ull) + (offset&1)*512;
-}
-
-static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001008ull) + (offset&1)*512;
-}
-
-#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
-static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000488ull);
-}
-
-#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
-static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000480ull);
-}
-
-#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000520ull);
-}
-
-#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000450ull);
-}
-
-#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
-static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000708ull);
-}
-
-#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
-static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000408ull);
-}
-
-#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000410ull);
-}
-
-#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000418ull);
-}
-
-#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000428ull);
-}
-
-#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000420ull);
-}
-
-#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000430ull);
-}
-
-#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000400ull);
-}
-
-#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
-static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000608ull);
-}
-
-#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
-static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000530ull);
-}
-
-#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000620ull);
-}
-
-#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000438ull);
-}
-
-#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000630ull);
-}
-
-#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000610ull);
-}
-
-#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000638ull);
-}
-
-#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
-static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000618ull);
-}
-
-#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
-static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000700ull);
-}
-
-#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
-static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000600ull);
-}
-
-#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000528ull);
-}
-
-#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000440ull);
-}
-
-#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
-static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000538ull);
-}
-
-static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000888ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000880ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000920ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000850ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000808ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000810ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000818ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000828ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000820ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000830ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000800ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000930ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000838ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000928ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000840ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000000938ull) + (offset&1)*1024;
-}
-
-static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100078ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100020ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100050ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100030ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100028ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100010ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100018ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100048ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100040ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100038ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100000ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100008ull) + (offset&1)*2048;
-}
-
-static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000100058ull) + (offset&1)*2048;
-}
-
-#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
-static inline uint64_t CVMX_MPI_CFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000001000ull);
-}
-
-static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
-        cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000001080ull) + (offset&15)*8;
-}
-
-#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
-static inline uint64_t CVMX_MPI_STS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000001008ull);
-}
-
-#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
-static inline uint64_t CVMX_MPI_TX_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000001010ull);
-}
-
-#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
-static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000018ull);
-}
-
-#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
-static inline uint64_t CVMX_NDF_CMD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000000ull);
-}
-
-#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
-static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000030ull);
-}
-
-#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
-static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000010ull);
-}
-
-#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
-static inline uint64_t CVMX_NDF_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000020ull);
-}
-
-#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
-static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000028ull);
-}
-
-#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
-static inline uint64_t CVMX_NDF_MISC_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000008ull);
-}
-
-#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
-static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070001000038ull);
-}
-
-static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000000ull + (offset&31)*16;
-}
-
-#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
-#endif
-    return 0x0000000000000580ull;
-}
-
-#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
-static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
-#endif
-    return 0x0000000000000680ull;
-}
-
-#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
-static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
-#endif
-    return 0x0000000000000250ull;
-}
-
-#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
-static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
-#endif
-    return 0x0000000000000260ull;
-}
-
-#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
-#endif
-    return 0x0000000000000570ull;
-}
-
-#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
-static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
-#endif
-    return 0x0000000000003C00ull;
-}
-
-#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
-static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
-#endif
-    return 0x00000000000005F0ull;
-}
-
-#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
-static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
-#endif
-    return 0x0000000000000510ull;
-}
-
-#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
-static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
-#endif
-    return 0x0000000000000500ull;
-}
-
-#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
-static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
-#endif
-    return 0x00000000000005C0ull;
-}
-
-#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
-static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
-#endif
-    return 0x00000000000005D0ull;
-}
-
-static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000450ull + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000003B0ull + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000400ull + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000004A0ull + (offset&7)*16;
-}
-
-#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
-#endif
-    return 0x00000000000005E0ull;
-}
-
-#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
-#endif
-    return 0x00000000000003A0ull;
-}
-
-#define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
-#endif
-    return 0x00000000000005B0ull;
-}
-
-#define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n");
-#endif
-    return 0x00000000000006C0ull;
-}
-
-#define CVMX_NPEI_DMA_STATE1_P1 CVMX_NPEI_DMA_STATE1_P1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE1_P1_FUNC(void)
-{
-    return 0x0000000000000680ull;
-}
-
-#define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n");
-#endif
-    return 0x00000000000006D0ull;
-}
-
-#define CVMX_NPEI_DMA_STATE2_P1 CVMX_NPEI_DMA_STATE2_P1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE2_P1_FUNC(void)
-{
-    return 0x0000000000000690ull;
-}
-
-#define CVMX_NPEI_DMA_STATE3_P1 CVMX_NPEI_DMA_STATE3_P1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE3_P1_FUNC(void)
-{
-    return 0x00000000000006A0ull;
-}
-
-#define CVMX_NPEI_DMA_STATE4_P1 CVMX_NPEI_DMA_STATE4_P1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE4_P1_FUNC(void)
-{
-    return 0x00000000000006B0ull;
-}
-
-#define CVMX_NPEI_DMA_STATE5_P1 CVMX_NPEI_DMA_STATE5_P1_FUNC()
-static inline uint64_t CVMX_NPEI_DMA_STATE5_P1_FUNC(void)
-{
-    return 0x00000000000006C0ull;
-}
-
-#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000000560ull;
-}
-
-#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
-static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
-#endif
-    return 0x0000000000003CE0ull;
-}
-
-#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
-static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
-#endif
-    return 0x0000000000000550ull;
-}
-
-#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000000540ull;
-}
-
-#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
-static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
-#endif
-    return 0x0000000000003CD0ull;
-}
-
-#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
-static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
-#endif
-    return 0x0000000000000590ull;
-}
-
-#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
-static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
-#endif
-    return 0x0000000000000530ull;
-}
-
-#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
-static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
-#endif
-    return 0x0000000000003CC0ull;
-}
-
-#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
-static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
-#endif
-    return 0x0000000000000600ull;
-}
-
-#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
-static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
-#endif
-    return 0x0000000000000610ull;
-}
-
-#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
-static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
-#endif
-    return 0x00000000000004F0ull;
-}
-
-static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
-        cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000340ull + (offset&31)*16 - 16*12;
-}
-
-#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
-#endif
-    return 0x0000000000003C50ull;
-}
-
-#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
-#endif
-    return 0x0000000000003C60ull;
-}
-
-#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
-#endif
-    return 0x0000000000003C70ull;
-}
-
-#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
-#endif
-    return 0x0000000000003C80ull;
-}
-
-#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
-#endif
-    return 0x0000000000003C10ull;
-}
-
-#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
-#endif
-    return 0x0000000000003C20ull;
-}
-
-#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
-#endif
-    return 0x0000000000003C30ull;
-}
-
-#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
-#endif
-    return 0x0000000000003C40ull;
-}
-
-#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
-#endif
-    return 0x0000000000003CA0ull;
-}
-
-#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
-#endif
-    return 0x0000000000003CF0ull;
-}
-
-#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
-#endif
-    return 0x0000000000003D00ull;
-}
-
-#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
-#endif
-    return 0x0000000000003D10ull;
-}
-
-#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
-#endif
-    return 0x0000000000003D20ull;
-}
-
-#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
-#endif
-    return 0x0000000000003D30ull;
-}
-
-#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
-#endif
-    return 0x0000000000003D40ull;
-}
-
-#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
-#endif
-    return 0x0000000000003D50ull;
-}
-
-#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
-#endif
-    return 0x0000000000003D60ull;
-}
-
-#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
-static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
-#endif
-    return 0x0000000000003C90ull;
-}
-
-#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
-static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
-#endif
-    return 0x0000000000003D70ull;
-}
-
-#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
-static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
-#endif
-    return 0x0000000000003CB0ull;
-}
-
-#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
-static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
-#endif
-    return 0x0000000000000650ull;
-}
-
-#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
-static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
-#endif
-    return 0x0000000000000660ull;
-}
-
-#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
-static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
-#endif
-    return 0x0000000000000670ull;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000002400ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000002800ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000002C00ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000003000ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000003400ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000003800ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000001400ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000001800ull + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000001C00ull + (offset&31)*16;
-}
-
-#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
-#endif
-    return 0x0000000000001110ull;
-}
-
-#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000001130ull;
-}
-
-#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
-#endif
-    return 0x00000000000010B0ull;
-}
-
-#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
-#endif
-    return 0x00000000000010A0ull;
-}
-
-#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
-#endif
-    return 0x0000000000001090ull;
-}
-
-#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
-#endif
-    return 0x0000000000001080ull;
-}
-
-#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
-#endif
-    return 0x0000000000001150ull;
-}
-
-#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000001000ull;
-}
-
-#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
-#endif
-    return 0x0000000000001190ull;
-}
-
-#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
-#endif
-    return 0x0000000000001020ull;
-}
-
-#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
-#endif
-    return 0x0000000000001100ull;
-}
-
-#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
-#endif
-    return 0x00000000000006B0ull;
-}
-
-static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000002000ull + (offset&31)*16;
-}
-
-#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
-#endif
-    return 0x00000000000006A0ull;
-}
-
-#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
-#endif
-    return 0x00000000000011A0ull;
-}
-
-#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
-#endif
-    return 0x0000000000001070ull;
-}
-
-#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
-#endif
-    return 0x0000000000001160ull;
-}
-
-#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
-#endif
-    return 0x00000000000010D0ull;
-}
-
-#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000001010ull;
-}
-
-#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
-#endif
-    return 0x00000000000010E0ull;
-}
-
-#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
-#endif
-    return 0x0000000000000690ull;
-}
-
-#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
-#endif
-    return 0x0000000000001050ull;
-}
-
-#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
-#endif
-    return 0x0000000000001180ull;
-}
-
-#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
-#endif
-    return 0x0000000000001040ull;
-}
-
-#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
-#endif
-    return 0x0000000000001030ull;
-}
-
-#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
-#endif
-    return 0x0000000000001120ull;
-}
-
-#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
-static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000001140ull;
-}
-
-#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
-static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
-#endif
-    return 0x0000000000000520ull;
-}
-
-#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
-static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
-#endif
-    return 0x0000000000000270ull;
-}
-
-#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
-static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
-#endif
-    return 0x0000000000000620ull;
-}
-
-#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
-static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
-#endif
-    return 0x0000000000000630ull;
-}
-
-#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
-static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
-#endif
-    return 0x0000000000000640ull;
-}
-
-#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
-static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
-#endif
-    return 0x0000000000000380ull;
-}
-
-#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
-static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
-#endif
-    return 0x0000000000000210ull;
-}
-
-#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
-static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
-#endif
-    return 0x0000000000000240ull;
-}
-
-#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
-static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
-#endif
-    return 0x0000000000000200ull;
-}
-
-#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
-static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
-#endif
-    return 0x0000000000000220ull;
-}
-
-#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
-static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
-#endif
-    return 0x0000000000000230ull;
-}
-
-#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
-#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
-#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
-#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
-static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + (offset&3)*16;
-}
-
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
-static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + (offset&3)*8;
-}
-
-#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
-}
-
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
-static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + (offset&3)*8;
-}
-
-#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
-static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
-}
-
-#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
-}
-
-#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
-static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
-}
-
-#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
-static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
-}
-
-#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
-static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
-}
-
-#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
-static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
-}
-
-#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
-static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
-}
-
-#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
-static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
-}
-
-#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
-static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
-}
-
-#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
-static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
-}
-
-#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
-static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
-}
-
-#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
-static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
-}
-
-#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
-static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
-}
-
-#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
-static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
-}
-
-#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
-static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
-}
-
-#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
-#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
-#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
-#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
-static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6))))))
-        cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + (offset&7)*8 - 8*3;
-}
-
-#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
-static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
-#endif
-    return 0x0000000000000190ull;
-}
-
-#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
-static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
-}
-
-#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
-#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
-#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
-#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
-static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + (offset&3)*8;
-}
-
-#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
-static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
-}
-
-#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
-#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
-#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
-#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
-#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
-#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
-#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
-#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
-#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
-#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
-#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
-#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
-#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
-#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
-#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
-#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
-static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + (offset&31)*4;
-}
-
-#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
-static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
-}
-
-#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
-static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
-}
-
-#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
-}
-
-#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
-}
-
-#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
-}
-
-#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
-}
-
-#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
-}
-
-#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
-}
-
-#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
-}
-
-#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
-}
-
-#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
-}
-
-#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
-}
-
-#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
-}
-
-#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
-}
-
-#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
-}
-
-#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
-}
-
-#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
-}
-
-#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
-}
-
-#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
-}
-
-#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
-}
-
-#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
-}
-
-#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
-}
-
-#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
-}
-
-#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
-}
-
-#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
-}
-
-#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
-}
-
-#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
-}
-
-#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
-}
-
-#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
-}
-
-#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
-}
-
-#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
-}
-
-#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
-}
-
-#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
-}
-
-#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
-static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
-}
-
-#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
-static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
-}
-
-#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
-static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
-}
-
-#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
-static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
-}
-
-#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
-static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
-}
-
-#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
-static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
-}
-
-#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
-static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
-}
-
-#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
-static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
-}
-
-#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
-static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
-}
-
-#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
-static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
-}
-
-#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
-static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
-}
-
-#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
-static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
-}
-
-#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
-static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
-}
-
-#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
-static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
-}
-
-#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
-static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
-}
-
-static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + (offset&3)*8;
-}
-
-static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + (offset&3)*8;
-}
-
-#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
-static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
-}
-
-#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
-#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
-#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
-#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
-static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + (offset&3)*16;
-}
-
-#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
-static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
-}
-
-#define CVMX_PCIEEP_CFG000 CVMX_PCIEEP_CFG000_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG000_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG000 not supported on this chip\n");
-#endif
-    return 0x0000000000000000ull;
-}
-
-#define CVMX_PCIEEP_CFG001 CVMX_PCIEEP_CFG001_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG001_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG001 not supported on this chip\n");
-#endif
-    return 0x0000000000000004ull;
-}
-
-#define CVMX_PCIEEP_CFG002 CVMX_PCIEEP_CFG002_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG002_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG002 not supported on this chip\n");
-#endif
-    return 0x0000000000000008ull;
-}
-
-#define CVMX_PCIEEP_CFG003 CVMX_PCIEEP_CFG003_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG003_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG003 not supported on this chip\n");
-#endif
-    return 0x000000000000000Cull;
-}
-
-#define CVMX_PCIEEP_CFG004 CVMX_PCIEEP_CFG004_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG004_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG004 not supported on this chip\n");
-#endif
-    return 0x0000000000000010ull;
-}
-
-#define CVMX_PCIEEP_CFG004_MASK CVMX_PCIEEP_CFG004_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG004_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG004_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000010ull;
-}
-
-#define CVMX_PCIEEP_CFG005 CVMX_PCIEEP_CFG005_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG005_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG005 not supported on this chip\n");
-#endif
-    return 0x0000000000000014ull;
-}
-
-#define CVMX_PCIEEP_CFG005_MASK CVMX_PCIEEP_CFG005_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG005_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG005_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000014ull;
-}
-
-#define CVMX_PCIEEP_CFG006 CVMX_PCIEEP_CFG006_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG006_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG006 not supported on this chip\n");
-#endif
-    return 0x0000000000000018ull;
-}
-
-#define CVMX_PCIEEP_CFG006_MASK CVMX_PCIEEP_CFG006_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG006_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG006_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000018ull;
-}
-
-#define CVMX_PCIEEP_CFG007 CVMX_PCIEEP_CFG007_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG007_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG007 not supported on this chip\n");
-#endif
-    return 0x000000000000001Cull;
-}
-
-#define CVMX_PCIEEP_CFG007_MASK CVMX_PCIEEP_CFG007_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG007_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG007_MASK not supported on this chip\n");
-#endif
-    return 0x000000008000001Cull;
-}
-
-#define CVMX_PCIEEP_CFG008 CVMX_PCIEEP_CFG008_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG008_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG008 not supported on this chip\n");
-#endif
-    return 0x0000000000000020ull;
-}
-
-#define CVMX_PCIEEP_CFG008_MASK CVMX_PCIEEP_CFG008_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG008_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG008_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000020ull;
-}
-
-#define CVMX_PCIEEP_CFG009 CVMX_PCIEEP_CFG009_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG009_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG009 not supported on this chip\n");
-#endif
-    return 0x0000000000000024ull;
-}
-
-#define CVMX_PCIEEP_CFG009_MASK CVMX_PCIEEP_CFG009_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG009_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG009_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000024ull;
-}
-
-#define CVMX_PCIEEP_CFG010 CVMX_PCIEEP_CFG010_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG010_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG010 not supported on this chip\n");
-#endif
-    return 0x0000000000000028ull;
-}
-
-#define CVMX_PCIEEP_CFG011 CVMX_PCIEEP_CFG011_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG011_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG011 not supported on this chip\n");
-#endif
-    return 0x000000000000002Cull;
-}
-
-#define CVMX_PCIEEP_CFG012 CVMX_PCIEEP_CFG012_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG012_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG012 not supported on this chip\n");
-#endif
-    return 0x0000000000000030ull;
-}
-
-#define CVMX_PCIEEP_CFG012_MASK CVMX_PCIEEP_CFG012_MASK_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG012_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG012_MASK not supported on this chip\n");
-#endif
-    return 0x0000000080000030ull;
-}
-
-#define CVMX_PCIEEP_CFG013 CVMX_PCIEEP_CFG013_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG013_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG013 not supported on this chip\n");
-#endif
-    return 0x0000000000000034ull;
-}
-
-#define CVMX_PCIEEP_CFG015 CVMX_PCIEEP_CFG015_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG015_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG015 not supported on this chip\n");
-#endif
-    return 0x000000000000003Cull;
-}
-
-#define CVMX_PCIEEP_CFG016 CVMX_PCIEEP_CFG016_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG016_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG016 not supported on this chip\n");
-#endif
-    return 0x0000000000000040ull;
-}
-
-#define CVMX_PCIEEP_CFG017 CVMX_PCIEEP_CFG017_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG017_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG017 not supported on this chip\n");
-#endif
-    return 0x0000000000000044ull;
-}
-
-#define CVMX_PCIEEP_CFG020 CVMX_PCIEEP_CFG020_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG020_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG020 not supported on this chip\n");
-#endif
-    return 0x0000000000000050ull;
-}
-
-#define CVMX_PCIEEP_CFG021 CVMX_PCIEEP_CFG021_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG021_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG021 not supported on this chip\n");
-#endif
-    return 0x0000000000000054ull;
-}
-
-#define CVMX_PCIEEP_CFG022 CVMX_PCIEEP_CFG022_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG022_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG022 not supported on this chip\n");
-#endif
-    return 0x0000000000000058ull;
-}
-
-#define CVMX_PCIEEP_CFG023 CVMX_PCIEEP_CFG023_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG023_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG023 not supported on this chip\n");
-#endif
-    return 0x000000000000005Cull;
-}
-
-#define CVMX_PCIEEP_CFG028 CVMX_PCIEEP_CFG028_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG028_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG028 not supported on this chip\n");
-#endif
-    return 0x0000000000000070ull;
-}
-
-#define CVMX_PCIEEP_CFG029 CVMX_PCIEEP_CFG029_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG029_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG029 not supported on this chip\n");
-#endif
-    return 0x0000000000000074ull;
-}
-
-#define CVMX_PCIEEP_CFG030 CVMX_PCIEEP_CFG030_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG030_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG030 not supported on this chip\n");
-#endif
-    return 0x0000000000000078ull;
-}
-
-#define CVMX_PCIEEP_CFG031 CVMX_PCIEEP_CFG031_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG031_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG031 not supported on this chip\n");
-#endif
-    return 0x000000000000007Cull;
-}
-
-#define CVMX_PCIEEP_CFG032 CVMX_PCIEEP_CFG032_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG032_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG032 not supported on this chip\n");
-#endif
-    return 0x0000000000000080ull;
-}
-
-#define CVMX_PCIEEP_CFG033 CVMX_PCIEEP_CFG033_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG033_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG033 not supported on this chip\n");
-#endif
-    return 0x0000000000000084ull;
-}
-
-#define CVMX_PCIEEP_CFG034 CVMX_PCIEEP_CFG034_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG034_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG034 not supported on this chip\n");
-#endif
-    return 0x0000000000000088ull;
-}
-
-#define CVMX_PCIEEP_CFG037 CVMX_PCIEEP_CFG037_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG037_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG037 not supported on this chip\n");
-#endif
-    return 0x0000000000000094ull;
-}
-
-#define CVMX_PCIEEP_CFG038 CVMX_PCIEEP_CFG038_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG038_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG038 not supported on this chip\n");
-#endif
-    return 0x0000000000000098ull;
-}
-
-#define CVMX_PCIEEP_CFG039 CVMX_PCIEEP_CFG039_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG039_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG039 not supported on this chip\n");
-#endif
-    return 0x000000000000009Cull;
-}
-
-#define CVMX_PCIEEP_CFG040 CVMX_PCIEEP_CFG040_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG040_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG040 not supported on this chip\n");
-#endif
-    return 0x00000000000000A0ull;
-}
-
-#define CVMX_PCIEEP_CFG041 CVMX_PCIEEP_CFG041_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG041_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG041 not supported on this chip\n");
-#endif
-    return 0x00000000000000A4ull;
-}
-
-#define CVMX_PCIEEP_CFG042 CVMX_PCIEEP_CFG042_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG042_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG042 not supported on this chip\n");
-#endif
-    return 0x00000000000000A8ull;
-}
-
-#define CVMX_PCIEEP_CFG064 CVMX_PCIEEP_CFG064_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG064_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG064 not supported on this chip\n");
-#endif
-    return 0x0000000000000100ull;
-}
-
-#define CVMX_PCIEEP_CFG065 CVMX_PCIEEP_CFG065_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG065_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG065 not supported on this chip\n");
-#endif
-    return 0x0000000000000104ull;
-}
-
-#define CVMX_PCIEEP_CFG066 CVMX_PCIEEP_CFG066_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG066_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG066 not supported on this chip\n");
-#endif
-    return 0x0000000000000108ull;
-}
-
-#define CVMX_PCIEEP_CFG067 CVMX_PCIEEP_CFG067_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG067_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG067 not supported on this chip\n");
-#endif
-    return 0x000000000000010Cull;
-}
-
-#define CVMX_PCIEEP_CFG068 CVMX_PCIEEP_CFG068_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG068_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG068 not supported on this chip\n");
-#endif
-    return 0x0000000000000110ull;
-}
-
-#define CVMX_PCIEEP_CFG069 CVMX_PCIEEP_CFG069_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG069_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG069 not supported on this chip\n");
-#endif
-    return 0x0000000000000114ull;
-}
-
-#define CVMX_PCIEEP_CFG070 CVMX_PCIEEP_CFG070_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG070_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG070 not supported on this chip\n");
-#endif
-    return 0x0000000000000118ull;
-}
-
-#define CVMX_PCIEEP_CFG071 CVMX_PCIEEP_CFG071_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG071_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG071 not supported on this chip\n");
-#endif
-    return 0x000000000000011Cull;
-}
-
-#define CVMX_PCIEEP_CFG072 CVMX_PCIEEP_CFG072_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG072_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG072 not supported on this chip\n");
-#endif
-    return 0x0000000000000120ull;
-}
-
-#define CVMX_PCIEEP_CFG073 CVMX_PCIEEP_CFG073_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG073_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG073 not supported on this chip\n");
-#endif
-    return 0x0000000000000124ull;
-}
-
-#define CVMX_PCIEEP_CFG074 CVMX_PCIEEP_CFG074_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG074_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG074 not supported on this chip\n");
-#endif
-    return 0x0000000000000128ull;
-}
-
-#define CVMX_PCIEEP_CFG448 CVMX_PCIEEP_CFG448_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG448_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG448 not supported on this chip\n");
-#endif
-    return 0x0000000000000700ull;
-}
-
-#define CVMX_PCIEEP_CFG449 CVMX_PCIEEP_CFG449_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG449_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG449 not supported on this chip\n");
-#endif
-    return 0x0000000000000704ull;
-}
-
-#define CVMX_PCIEEP_CFG450 CVMX_PCIEEP_CFG450_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG450_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG450 not supported on this chip\n");
-#endif
-    return 0x0000000000000708ull;
-}
-
-#define CVMX_PCIEEP_CFG451 CVMX_PCIEEP_CFG451_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG451_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG451 not supported on this chip\n");
-#endif
-    return 0x000000000000070Cull;
-}
-
-#define CVMX_PCIEEP_CFG452 CVMX_PCIEEP_CFG452_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG452_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG452 not supported on this chip\n");
-#endif
-    return 0x0000000000000710ull;
-}
-
-#define CVMX_PCIEEP_CFG453 CVMX_PCIEEP_CFG453_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG453_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG453 not supported on this chip\n");
-#endif
-    return 0x0000000000000714ull;
-}
-
-#define CVMX_PCIEEP_CFG454 CVMX_PCIEEP_CFG454_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG454_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG454 not supported on this chip\n");
-#endif
-    return 0x0000000000000718ull;
-}
-
-#define CVMX_PCIEEP_CFG455 CVMX_PCIEEP_CFG455_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG455_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG455 not supported on this chip\n");
-#endif
-    return 0x000000000000071Cull;
-}
-
-#define CVMX_PCIEEP_CFG456 CVMX_PCIEEP_CFG456_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG456_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG456 not supported on this chip\n");
-#endif
-    return 0x0000000000000720ull;
-}
-
-#define CVMX_PCIEEP_CFG458 CVMX_PCIEEP_CFG458_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG458_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG458 not supported on this chip\n");
-#endif
-    return 0x0000000000000728ull;
-}
-
-#define CVMX_PCIEEP_CFG459 CVMX_PCIEEP_CFG459_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG459_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG459 not supported on this chip\n");
-#endif
-    return 0x000000000000072Cull;
-}
-
-#define CVMX_PCIEEP_CFG460 CVMX_PCIEEP_CFG460_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG460_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG460 not supported on this chip\n");
-#endif
-    return 0x0000000000000730ull;
-}
-
-#define CVMX_PCIEEP_CFG461 CVMX_PCIEEP_CFG461_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG461_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG461 not supported on this chip\n");
-#endif
-    return 0x0000000000000734ull;
-}
-
-#define CVMX_PCIEEP_CFG462 CVMX_PCIEEP_CFG462_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG462_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG462 not supported on this chip\n");
-#endif
-    return 0x0000000000000738ull;
-}
-
-#define CVMX_PCIEEP_CFG463 CVMX_PCIEEP_CFG463_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG463_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG463 not supported on this chip\n");
-#endif
-    return 0x000000000000073Cull;
-}
-
-#define CVMX_PCIEEP_CFG464 CVMX_PCIEEP_CFG464_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG464_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG464 not supported on this chip\n");
-#endif
-    return 0x0000000000000740ull;
-}
-
-#define CVMX_PCIEEP_CFG465 CVMX_PCIEEP_CFG465_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG465_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG465 not supported on this chip\n");
-#endif
-    return 0x0000000000000744ull;
-}
-
-#define CVMX_PCIEEP_CFG466 CVMX_PCIEEP_CFG466_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG466_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG466 not supported on this chip\n");
-#endif
-    return 0x0000000000000748ull;
-}
-
-#define CVMX_PCIEEP_CFG467 CVMX_PCIEEP_CFG467_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG467_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG467 not supported on this chip\n");
-#endif
-    return 0x000000000000074Cull;
-}
-
-#define CVMX_PCIEEP_CFG468 CVMX_PCIEEP_CFG468_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG468_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG468 not supported on this chip\n");
-#endif
-    return 0x0000000000000750ull;
-}
-
-#define CVMX_PCIEEP_CFG490 CVMX_PCIEEP_CFG490_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG490_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG490 not supported on this chip\n");
-#endif
-    return 0x00000000000007A8ull;
-}
-
-#define CVMX_PCIEEP_CFG491 CVMX_PCIEEP_CFG491_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG491_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG491 not supported on this chip\n");
-#endif
-    return 0x00000000000007ACull;
-}
-
-#define CVMX_PCIEEP_CFG492 CVMX_PCIEEP_CFG492_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG492_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG492 not supported on this chip\n");
-#endif
-    return 0x00000000000007B0ull;
-}
-
-#define CVMX_PCIEEP_CFG516 CVMX_PCIEEP_CFG516_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG516_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG516 not supported on this chip\n");
-#endif
-    return 0x0000000000000810ull;
-}
-
-#define CVMX_PCIEEP_CFG517 CVMX_PCIEEP_CFG517_FUNC()
-static inline uint64_t CVMX_PCIEEP_CFG517_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PCIEEP_CFG517 not supported on this chip\n");
-#endif
-    return 0x0000000000000814ull;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000000ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000004ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000008ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000000Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000010ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000014ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000018ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000001Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000020ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000024ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000028ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000002Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000030ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000034ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000038ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000003Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000040ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000044ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000050ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000054ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000058ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000005Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000070ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000074ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000078ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000007Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000080ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000084ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000088ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000008Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000090ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000094ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000098ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000009Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000A0ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000A4ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000A8ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000100ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000104ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000108ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000010Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000110ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000114ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000118ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000011Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000120ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000124ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000128ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000012Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000130ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000134ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000700ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000704ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000708ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000070Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000710ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000714ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000718ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000071Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000720ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000728ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000072Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000730ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000734ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000738ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000073Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000740ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000744ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000748ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000074Cull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000750ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000007A8ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000007ACull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000007B0ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000810ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000814ull + (offset&1)*0;
-}
-
-static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000100ull + (offset&31)*4;
-}
-
-#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC()
-static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n");
-#endif
-    return 0x00000000000001C0ull;
-}
-
-#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC()
-static inline uint64_t CVMX_PCI_CFG00_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n");
-#endif
-    return 0x0000000000000000ull;
-}
-
-#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC()
-static inline uint64_t CVMX_PCI_CFG01_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n");
-#endif
-    return 0x0000000000000004ull;
-}
-
-#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC()
-static inline uint64_t CVMX_PCI_CFG02_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n");
-#endif
-    return 0x0000000000000008ull;
-}
-
-#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC()
-static inline uint64_t CVMX_PCI_CFG03_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n");
-#endif
-    return 0x000000000000000Cull;
-}
-
-#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC()
-static inline uint64_t CVMX_PCI_CFG04_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n");
-#endif
-    return 0x0000000000000010ull;
-}
-
-#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC()
-static inline uint64_t CVMX_PCI_CFG05_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n");
-#endif
-    return 0x0000000000000014ull;
-}
-
-#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC()
-static inline uint64_t CVMX_PCI_CFG06_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n");
-#endif
-    return 0x0000000000000018ull;
-}
-
-#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC()
-static inline uint64_t CVMX_PCI_CFG07_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n");
-#endif
-    return 0x000000000000001Cull;
-}
-
-#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC()
-static inline uint64_t CVMX_PCI_CFG08_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n");
-#endif
-    return 0x0000000000000020ull;
-}
-
-#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC()
-static inline uint64_t CVMX_PCI_CFG09_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n");
-#endif
-    return 0x0000000000000024ull;
-}
-
-#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC()
-static inline uint64_t CVMX_PCI_CFG10_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n");
-#endif
-    return 0x0000000000000028ull;
-}
-
-#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC()
-static inline uint64_t CVMX_PCI_CFG11_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n");
-#endif
-    return 0x000000000000002Cull;
-}
-
-#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC()
-static inline uint64_t CVMX_PCI_CFG12_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n");
-#endif
-    return 0x0000000000000030ull;
-}
-
-#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC()
-static inline uint64_t CVMX_PCI_CFG13_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n");
-#endif
-    return 0x0000000000000034ull;
-}
-
-#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC()
-static inline uint64_t CVMX_PCI_CFG15_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n");
-#endif
-    return 0x000000000000003Cull;
-}
-
-#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC()
-static inline uint64_t CVMX_PCI_CFG16_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n");
-#endif
-    return 0x0000000000000040ull;
-}
-
-#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC()
-static inline uint64_t CVMX_PCI_CFG17_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n");
-#endif
-    return 0x0000000000000044ull;
-}
-
-#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC()
-static inline uint64_t CVMX_PCI_CFG18_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n");
-#endif
-    return 0x0000000000000048ull;
-}
-
-#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC()
-static inline uint64_t CVMX_PCI_CFG19_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n");
-#endif
-    return 0x000000000000004Cull;
-}
-
-#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC()
-static inline uint64_t CVMX_PCI_CFG20_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n");
-#endif
-    return 0x0000000000000050ull;
-}
-
-#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC()
-static inline uint64_t CVMX_PCI_CFG21_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n");
-#endif
-    return 0x0000000000000054ull;
-}
-
-#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC()
-static inline uint64_t CVMX_PCI_CFG22_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n");
-#endif
-    return 0x0000000000000058ull;
-}
-
-#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC()
-static inline uint64_t CVMX_PCI_CFG56_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n");
-#endif
-    return 0x00000000000000E0ull;
-}
-
-#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC()
-static inline uint64_t CVMX_PCI_CFG57_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n");
-#endif
-    return 0x00000000000000E4ull;
-}
-
-#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC()
-static inline uint64_t CVMX_PCI_CFG58_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n");
-#endif
-    return 0x00000000000000E8ull;
-}
-
-#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC()
-static inline uint64_t CVMX_PCI_CFG59_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n");
-#endif
-    return 0x00000000000000ECull;
-}
-
-#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC()
-static inline uint64_t CVMX_PCI_CFG60_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n");
-#endif
-    return 0x00000000000000F0ull;
-}
-
-#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC()
-static inline uint64_t CVMX_PCI_CFG61_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n");
-#endif
-    return 0x00000000000000F4ull;
-}
-
-#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC()
-static inline uint64_t CVMX_PCI_CFG62_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n");
-#endif
-    return 0x00000000000000F8ull;
-}
-
-#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC()
-static inline uint64_t CVMX_PCI_CFG63_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n");
-#endif
-    return 0x00000000000000FCull;
-}
-
-#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC()
-static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n");
-#endif
-    return 0x00000000000001B8ull;
-}
-
-#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC()
-static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n");
-#endif
-    return 0x000000000000018Cull;
-}
-
-static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000080ull + (offset&3)*8;
-}
-
-#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
-#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
-static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000A0ull + (offset&1)*8;
-}
-
-#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
-#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
-static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000A4ull + (offset&1)*8;
-}
-
-#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
-#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
-static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x00000000000000B0ull + (offset&1)*4;
-}
-
-#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
-#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
-#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
-#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
-static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000084ull + (offset&3)*8;
-}
-
-#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC()
-static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n");
-#endif
-    return 0x0000000000000038ull;
-}
-
-#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC()
-static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n");
-#endif
-    return 0x00000000000001A0ull;
-}
-
-#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC()
-static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n");
-#endif
-    return 0x0000000000000030ull;
-}
-
-#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC()
-static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n");
-#endif
-    return 0x0000000000000198ull;
-}
-
-#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC()
-static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n");
-#endif
-    return 0x00000000000000F0ull;
-}
-
-#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
-#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
-#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
-#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
-static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000040ull + (offset&3)*16;
-}
-
-#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
-#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
-#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
-#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
-static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000048ull + (offset&3)*16;
-}
-
-#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
-#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
-#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
-#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
-static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x000000000000004Cull + (offset&3)*16;
-}
-
-#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
-#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
-#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
-#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
-static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset);
-#endif
-    return 0x0000000000000044ull + (offset&3)*16;
-}
-
-#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC()
-static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n");
-#endif
-    return 0x0000000000000180ull;
-}
-
-#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC()
-static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n");
-#endif
-    return 0x0000000000000184ull;
-}
-
-#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC()
-static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n");
-#endif
-    return 0x0000000000000188ull;
-}
-
-#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC()
-static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000000B0ull);
-}
-
-#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC()
-static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n");
-#endif
-    return 0x00000000000001A8ull;
-}
-
-#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC()
-static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n");
-#endif
-    return 0x00000000000001B0ull;
-}
-
-#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC()
-static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n");
-#endif
-    return 0x0000000000000008ull;
-}
-
-#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC()
-static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n");
-#endif
-    return 0x0000000000000020ull;
-}
-
-#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC()
-static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n");
-#endif
-    return 0x0000000000000000ull;
-}
-
-#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC()
-static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n");
-#endif
-    return 0x0000000000000010ull;
-}
-
-#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC()
-static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n");
-#endif
-    return 0x0000000000000018ull;
-}
-
-static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010018ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010020ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010028ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010068ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010060ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010058ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010010ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010030ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010050ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010048ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010080ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010088ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010090ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010098ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010040ull) + (offset&3)*16384;
-}
-
-static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010000ull) + (offset&1)*16384;
-}
-
-static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010038ull) + (offset&1)*16384;
-}
-
-static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001070000010008ull) + (offset&1)*16384;
-}
-
-static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
-        cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
-}
-
-static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
-}
-
-static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
-}
-
-static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + (offset&31)*16;
-}
-
-#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
-}
-
-#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
-}
-
-#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
-}
-
-#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
-}
-
-#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
-}
-
-#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
-}
-
-#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
-}
-
-#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
-}
-
-#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + (offset&7)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
-        cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + (offset&7)*16;
-}
-
-#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE1_P1 CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE2_P1 CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE3_P1 CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE4_P1 CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
-}
-
-#define CVMX_PEXP_NPEI_DMA_STATE5_P1 CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
-}
-
-#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
-}
-
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
-}
-
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
-}
-
-#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
-        cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + (offset&31)*16 - 16*12;
-}
-
-#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
-}
-
-#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
-}
-
-#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
-}
-
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
-}
-
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
-}
-
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
-}
-
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + (offset&31)*16;
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + (offset&31)*16;
-}
-
-#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
-}
-
-static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + (offset&31)*16;
-}
-
-#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
-}
-
-#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
-}
-
-#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
-}
-
-#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
-}
-
-#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
-}
-
-#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
-}
-
-#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
-}
-
-#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
-static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
-}
-
-#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
-static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
-}
-
-#define CVMX_PIP_BIST_STATUS CVMX_PIP_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_PIP_BIST_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000000ull);
-}
-
-static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + (offset&1)*8;
-}
-
-static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + (offset&3)*8;
-}
-
-#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
-static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
-}
-
-#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
-static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
-}
-
-static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + (offset&1)*8;
-}
-
-#define CVMX_PIP_GBL_CFG CVMX_PIP_GBL_CFG_FUNC()
-static inline uint64_t CVMX_PIP_GBL_CFG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000028ull);
-}
-
-#define CVMX_PIP_GBL_CTL CVMX_PIP_GBL_CTL_FUNC()
-static inline uint64_t CVMX_PIP_GBL_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000020ull);
-}
-
-#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
-static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
-}
-
-#define CVMX_PIP_INT_EN CVMX_PIP_INT_EN_FUNC()
-static inline uint64_t CVMX_PIP_INT_EN_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000010ull);
-}
-
-#define CVMX_PIP_INT_REG CVMX_PIP_INT_REG_FUNC()
-static inline uint64_t CVMX_PIP_INT_REG_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000008ull);
-}
-
-#define CVMX_PIP_IP_OFFSET CVMX_PIP_IP_OFFSET_FUNC()
-static inline uint64_t CVMX_PIP_IP_OFFSET_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000060ull);
-}
-
-static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
-        cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + (offset&63)*8;
-}
-
-static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + (offset&7)*8;
-}
-
-#define CVMX_PIP_RAW_WORD CVMX_PIP_RAW_WORD_FUNC()
-static inline uint64_t CVMX_PIP_RAW_WORD_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A00000B0ull);
-}
-
-#define CVMX_PIP_SFT_RST CVMX_PIP_SFT_RST_FUNC()
-static inline uint64_t CVMX_PIP_SFT_RST_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000030ull);
-}
-
-static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + (offset&63)*80;
-}
-
-static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + (offset&63)*80;
-}
-
-#define CVMX_PIP_STAT_CTL CVMX_PIP_STAT_CTL_FUNC()
-static inline uint64_t CVMX_PIP_STAT_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000018ull);
-}
-
-static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + (offset&63)*32;
-}
-
-static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + (offset&63)*32;
-}
-
-static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
-        cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + (offset&63)*32;
-}
-
-static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
-        cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + (offset&63)*8;
-}
-
-#define CVMX_PIP_TAG_MASK CVMX_PIP_TAG_MASK_FUNC()
-static inline uint64_t CVMX_PIP_TAG_MASK_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000070ull);
-}
-
-#define CVMX_PIP_TAG_SECRET CVMX_PIP_TAG_SECRET_FUNC()
-static inline uint64_t CVMX_PIP_TAG_SECRET_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000068ull);
-}
-
-#define CVMX_PIP_TODO_ENTRY CVMX_PIP_TODO_ENTRY_FUNC()
-static inline uint64_t CVMX_PIP_TODO_ENTRY_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00011800A0000078ull);
-}
-
-#define CVMX_PKO_MEM_COUNT0 CVMX_PKO_MEM_COUNT0_FUNC()
-static inline uint64_t CVMX_PKO_MEM_COUNT0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001080ull);
-}
-
-#define CVMX_PKO_MEM_COUNT1 CVMX_PKO_MEM_COUNT1_FUNC()
-static inline uint64_t CVMX_PKO_MEM_COUNT1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001088ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG0 CVMX_PKO_MEM_DEBUG0_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001100ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG1 CVMX_PKO_MEM_DEBUG1_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001108ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG10 CVMX_PKO_MEM_DEBUG10_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG10_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001150ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG11 CVMX_PKO_MEM_DEBUG11_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG11_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001158ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG12 CVMX_PKO_MEM_DEBUG12_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG12_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001160ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG13 CVMX_PKO_MEM_DEBUG13_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG13_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001168ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050001170ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG2 CVMX_PKO_MEM_DEBUG2_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001110ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG3 CVMX_PKO_MEM_DEBUG3_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG3_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001118ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG4 CVMX_PKO_MEM_DEBUG4_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG4_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001120ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG5 CVMX_PKO_MEM_DEBUG5_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG5_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001128ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG6 CVMX_PKO_MEM_DEBUG6_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG6_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001130ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG7 CVMX_PKO_MEM_DEBUG7_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG7_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001138ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG8 CVMX_PKO_MEM_DEBUG8_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG8_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001140ull);
-}
-
-#define CVMX_PKO_MEM_DEBUG9 CVMX_PKO_MEM_DEBUG9_FUNC()
-static inline uint64_t CVMX_PKO_MEM_DEBUG9_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001148ull);
-}
-
-#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
-static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050001010ull);
-}
-
-#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
-static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050001018ull);
-}
-
-#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
-static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050001020ull);
-}
-
-#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
-static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050001028ull);
-}
-
-#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
-static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001000ull);
-}
-
-#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
-static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050001008ull);
-}
-
-#define CVMX_PKO_REG_BIST_RESULT CVMX_PKO_REG_BIST_RESULT_FUNC()
-static inline uint64_t CVMX_PKO_REG_BIST_RESULT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000080ull);
-}
-
-#define CVMX_PKO_REG_CMD_BUF CVMX_PKO_REG_CMD_BUF_FUNC()
-static inline uint64_t CVMX_PKO_REG_CMD_BUF_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000010ull);
-}
-
-static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000028ull) + (offset&1)*8;
-}
-
-#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
-static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000020ull);
-}
-
-static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000038ull) + (offset&1)*8;
-}
-
-#define CVMX_PKO_REG_DEBUG0 CVMX_PKO_REG_DEBUG0_FUNC()
-static inline uint64_t CVMX_PKO_REG_DEBUG0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000098ull);
-}
-
-#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
-static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
-}
-
-#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
-static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
-}
-
-#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
-static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
-}
-
-#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
-static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000050ull);
-}
-
-#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
-static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000058ull);
-}
-
-#define CVMX_PKO_REG_ERROR CVMX_PKO_REG_ERROR_FUNC()
-static inline uint64_t CVMX_PKO_REG_ERROR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000088ull);
-}
-
-#define CVMX_PKO_REG_FLAGS CVMX_PKO_REG_FLAGS_FUNC()
-static inline uint64_t CVMX_PKO_REG_FLAGS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000000ull);
-}
-
-#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
-static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000018ull);
-}
-
-#define CVMX_PKO_REG_INT_MASK CVMX_PKO_REG_INT_MASK_FUNC()
-static inline uint64_t CVMX_PKO_REG_INT_MASK_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000090ull);
-}
-
-#define CVMX_PKO_REG_QUEUE_MODE CVMX_PKO_REG_QUEUE_MODE_FUNC()
-static inline uint64_t CVMX_PKO_REG_QUEUE_MODE_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000048ull);
-}
-
-#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
-static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180050000100ull);
-}
-
-#define CVMX_PKO_REG_READ_IDX CVMX_PKO_REG_READ_IDX_FUNC()
-static inline uint64_t CVMX_PKO_REG_READ_IDX_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180050000008ull);
-}
-
-#define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
-static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
-}
-
-#define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
-static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000398ull);
-}
-
-#define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
-static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000218ull);
-}
-
-#define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
-static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000220ull);
-}
-
-static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000340ull) + (offset&7)*8;
-}
-
-#define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
-static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000388ull);
-}
-
-#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
-static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000238ull);
-}
-
-#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
-static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000240ull);
-}
-
-static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + (offset&7)*8;
-}
-
-#define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
-static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000228ull);
-}
-
-#define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
-static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000210ull);
-}
-
-#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
-static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
-        cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000230ull);
-}
-
-static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
-        cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000000ull) + (offset&15)*8;
-}
-
-static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + (offset&7)*8;
-}
-
-static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000180ull) + (offset&7)*8;
-}
-
-#define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
-static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000390ull);
-}
-
-#define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
-static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000380ull);
-}
-
-static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
-        cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000300ull) + (offset&7)*8;
-}
-
-#define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
-static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000200ull);
-}
-
-static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000100ull) + (offset&15)*8;
-}
-
-#define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
-static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001670000000208ull);
-}
-
-static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000080ull) + (offset&15)*8;
-}
-
-static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
-        cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001670000000280ull) + (offset&15)*8;
-}
-
-#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
-static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070001000ull);
-}
-
-#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
-static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070001008ull);
-}
-
-#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
-static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070001010ull);
-}
-
-#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
-static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000080ull);
-}
-
-#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
-static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000008ull);
-}
-
-#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
-static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000000ull);
-}
-
-#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000100ull);
-}
-
-#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000108ull);
-}
-
-#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000150ull);
-}
-
-#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000158ull);
-}
-
-#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000160ull);
-}
-
-#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000110ull);
-}
-
-#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000118ull);
-}
-
-#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000120ull);
-}
-
-#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000128ull);
-}
-
-#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000130ull);
-}
-
-#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000138ull);
-}
-
-#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000140ull);
-}
-
-#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
-static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000148ull);
-}
-
-#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
-static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000088ull);
-}
-
-#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
-static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000090ull);
-}
-
-#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
-static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000010ull);
-}
-
-#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
-static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
-        cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180070000018ull);
-}
-
-#define CVMX_RNM_BIST_STATUS CVMX_RNM_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_RNM_BIST_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180040000008ull);
-}
-
-#define CVMX_RNM_CTL_STATUS CVMX_RNM_CTL_STATUS_FUNC()
-static inline uint64_t CVMX_RNM_CTL_STATUS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180040000000ull);
-}
-
-static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset&1)*256;
-}
-
-static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset&1)*256;
-}
-
-static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset&1)*256;
-}
-
-static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset&1)*256;
-}
-
-static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
-        cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n", offset);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset&1)*256;
-}
-
-#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
-static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
-        cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000388ull);
-}
-
-#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
-static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
-        cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000380ull);
-}
-
-static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000340ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000348ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000350ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000368ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000370ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000358ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000320ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000318ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000308ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000300ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000310ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000338ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000330ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000328ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000360ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000200ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000218ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000000ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000208ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000220ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000228ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000608ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000688ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000600ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000690ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000610ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000698ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000618ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000400ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
-}
-
-static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000628ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000630ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000648ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000680ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000638ull) + (block_id&1)*0x8000000ull;
-}
-
-static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180090000640ull) + (block_id&1)*0x8000000ull;
-}
-
-#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC()
-static inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058001100ull);
-}
-
-#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC()
-static inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058001108ull);
-}
-
-#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC()
-static inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058001110ull);
-}
-
-#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC()
-static inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058001000ull);
-}
-
-#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC()
-static inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058001008ull);
-}
-
-#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC()
-static inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058000080ull);
-}
-
-#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC()
-static inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058000088ull);
-}
-
-#define CVMX_TIM_REG_FLAGS CVMX_TIM_REG_FLAGS_FUNC()
-static inline uint64_t CVMX_TIM_REG_FLAGS_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058000000ull);
-}
-
-#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC()
-static inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058000090ull);
-}
-
-#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC()
-static inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void)
-{
-    return CVMX_ADD_IO_SEG(0x0001180058000008ull);
-}
-
-#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
-static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
-}
-
-#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
-static inline uint64_t CVMX_TRA_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
-}
-
-#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
-static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
-}
-
-#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
-static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
-}
-
-#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
-}
-
-#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
-}
-
-#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
-static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
-}
-
-#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
-static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
-}
-
-#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
-static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
-}
-
-#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
-static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
-}
-
-#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
-static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
-}
-
-#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
-}
-
-#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
-}
-
-#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
-}
-
-#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
-}
-
-#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
-}
-
-#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
-}
-
-#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
-}
-
-#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
-}
-
-#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
-}
-
-#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
-static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
-}
-
-static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((offset&7) + (block_id&1)*0x40000000000ull)*4;
-}
-
-static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
-}
-
-static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
-        cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + ((offset&7) + (block_id&1)*0x100000000ull)*4096;
-}
-
-static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + (block_id&1)*0x10000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180068000010ull) + (block_id&1)*0x10000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + (block_id&1)*0x100000000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180068000008ull) + (block_id&1)*0x10000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180068000000ull) + (block_id&1)*0x10000000ull;
-}
-
-static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(
-        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
-        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
-        cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180068000018ull) + (block_id&1)*0x10000000ull;
-}
-
-#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
-static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000080ull);
-}
-
-#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
-static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000008ull);
-}
-
-#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
-static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000000ull);
-}
-
-#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
-static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
-}
-
-#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
-static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000098ull);
-}
-
-#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
-static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000088ull);
-}
-
-#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
-static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
-{
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
-        cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
-#endif
-    return CVMX_ADD_IO_SEG(0x0001180038000090ull);
-}
-
-
-#endif /* __CVMX_CSR_ADDRESSES_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c b/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
index a5af6a1..6850c31 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,20 +42,22 @@
 
 
 
+
 /**
  * @file
  *
  * Utility functions for working with the CSR database
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49507 $<hr>
  */
-#include "cvmx.h"
-#include "cvmx-csr-db.h"
-
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-    #define PRINTF printk
+#define PRINTF printk
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-csr-db.h>
 #else
-    #define PRINTF printf
+#define PRINTF printf
+#include "cvmx.h"
+#include "cvmx-csr-db.h"
 #endif
 
 /**
@@ -84,6 +87,8 @@ int cvmx_db_get_chipindex(int identifier)
             return 2;
         case 0x000d0700: /* CN52XX */
             return 10;
+        case 0x000d9000: /* CN63XX */
+            return 11;
     }
 
     /* Next try PCI device IDs */
@@ -109,6 +114,8 @@ int cvmx_db_get_chipindex(int identifier)
             return 8;
         case 0x0080177d: /* CN52XX Pass 2 */
             return 10;
+        case 0x0090177d: /* CN63XX Pass 1 */
+            return 11;
     }
 
     /* Default to Pass 3 if we don't know */
@@ -142,6 +149,28 @@ const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name
 }
 #endif
 
+static void __cvmx_csr_db_decode_csr(int chip, int index, uint64_t value)
+{
+    int field;
+    int csr = cvmx_csr_db_addresses[chip][index].csroff;
+    PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)cvmx_csr_db_addresses[chip][index].address, (unsigned long long)value);
+    for (field=cvmx_csr_db[chip][csr].fieldoff+cvmx_csr_db[chip][csr].numfields-1; field>=cvmx_csr_db[chip][csr].fieldoff; field--)
+    {
+        uint64_t v = (value >> cvmx_csr_db_fields[chip][field].startbit);
+        if(cvmx_csr_db_fields[chip][field].sizebits < 64)
+            v = v & ~((~0x0ull) << cvmx_csr_db_fields[chip][field].sizebits);
+        if (cvmx_csr_db_fields[chip][field].sizebits == 1)
+            PRINTF("  [   %2d] %-20s = %10llu (0x%llx)\n",
+                cvmx_csr_db_fields[chip][field].startbit, cvmx_csr_db_fields[chip][field].name,
+                (unsigned long long)v, (unsigned long long)v);
+        else
+            PRINTF("  [%2d:%2d] %-20s = %10llu (0x%llx)\n",
+                cvmx_csr_db_fields[chip][field].startbit + cvmx_csr_db_fields[chip][field].sizebits - 1,
+                cvmx_csr_db_fields[chip][field].startbit,
+                cvmx_csr_db_fields[chip][field].name,
+                (unsigned long long)v, (unsigned long long)v);
+    }
+}
 
 /**
  * Decode a CSR value into named bitfields. The model can either
@@ -161,26 +190,29 @@ void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value)
     while (cvmx_csr_db_addresses[chip][index].name)
     {
         if (cvmx_csr_db_addresses[chip][index].address == address)
+            __cvmx_csr_db_decode_csr(chip, index, value);
+        index++;
+    }
+}
+
+/**
+ * Decode a CSR value into named bitfields. The model can either
+ * be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param name       CSR name to decode
+ * @param value      Value to decode
+ */
+void cvmx_csr_db_decode_by_name(int identifier, const char *name, uint64_t value)
+{
+    int chip = cvmx_db_get_chipindex(identifier);
+    int index=0;
+    while (cvmx_csr_db_addresses[chip][index].name)
+    {
+        if (strcasecmp(name, cvmx_csr_db_addresses[chip][index].name) == 0)
         {
-            int field;
-            int csr = cvmx_csr_db_addresses[chip][index].csroff;
-            PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)address, (unsigned long long)value);
-            for (field=cvmx_csr_db[chip][csr].fieldoff+cvmx_csr_db[chip][csr].numfields-1; field>=cvmx_csr_db[chip][csr].fieldoff; field--)
-            {
-                uint64_t v = (value >> cvmx_csr_db_fields[chip][field].startbit);
-                if(cvmx_csr_db_fields[chip][field].sizebits < 64)
-                    v = v & ~((~0x0ull) << cvmx_csr_db_fields[chip][field].sizebits);
-		if (cvmx_csr_db_fields[chip][field].sizebits == 1)
-                    PRINTF("  [   %2d] %-20s = %10llu (0x%llx)\n",
-                        cvmx_csr_db_fields[chip][field].startbit, cvmx_csr_db_fields[chip][field].name,
-                        (unsigned long long)v, (unsigned long long)v);
-                else
-                    PRINTF("  [%2d:%2d] %-20s = %10llu (0x%llx)\n",
-                        cvmx_csr_db_fields[chip][field].startbit + cvmx_csr_db_fields[chip][field].sizebits - 1,
-                        cvmx_csr_db_fields[chip][field].startbit,
-                        cvmx_csr_db_fields[chip][field].name,
-                        (unsigned long long)v, (unsigned long long)v);
-            }
+            __cvmx_csr_db_decode_csr(chip, index, value);
+            break;
         }
         index++;
     }
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.c b/sys/contrib/octeon-sdk/cvmx-csr-db.c
index ef44fac..48316e3 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.c
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db.c
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  *
@@ -44,11 +46,16 @@
  *
  * This file is auto generated. Do not edit.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-csr-db.h>
+#else
 #include "cvmx-csr-db.h"
+#endif
 
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
 	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
@@ -632,72 +639,72 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800B0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800B8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_RX_WOL"                 ,	   0x11800B0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX1_RX_WOL"                 ,	   0x11800B8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX0_RX_WOL_MSK"             ,	   0x11800B0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_RX_WOL_MSK"             ,	   0x11800B8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_RX_WOL_POWOK"           ,	   0x11800B0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX1_RX_WOL_POWOK"           ,	   0x11800B8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX0_RX_WOL_SIG"             ,	   0x11800B0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX1_RX_WOL_SIG"             ,	   0x11800B8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800b8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800b8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800b8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800b0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800b8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800b0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800b8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800b0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800b8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800b0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800b8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800b0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800b8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800b0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800b8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800b0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800b8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800b0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800b8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800b0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800b8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RLD_SETTING"            ,	   0x11800b0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RLD_SETTING"            ,	   0x11800b8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800b0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800b8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800b8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800b8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800b8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800b8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_RX_WOL"                 ,	   0x11800b0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_RX_WOL"                 ,	   0x11800b8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_RX_WOL_MSK"             ,	   0x11800b0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_RX_WOL_MSK"             ,	   0x11800b8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_RX_WOL_POWOK"           ,	   0x11800b0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_RX_WOL_POWOK"           ,	   0x11800b8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_RX_WOL_SIG"             ,	   0x11800b0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX1_RX_WOL_SIG"             ,	   0x11800b8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800b0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800b8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800b8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800b8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800b8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800b8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800b0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800b8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800b8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800b8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800b8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800b8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800b0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800b0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
@@ -712,12 +719,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
@@ -728,12 +735,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN0"               ,	   0x10700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN0"               ,	   0x10700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN0"               ,	   0x10700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN0"               ,	   0x10700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN0"               ,	   0x10700000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN0"               ,	   0x10700000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
@@ -745,12 +752,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
@@ -761,12 +768,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT26_EN1"               ,	   0x10700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT27_EN1"               ,	   0x10700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT28_EN1"               ,	   0x10700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT29_EN1"               ,	   0x10700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT30_EN1"               ,	   0x10700000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT31_EN1"               ,	   0x10700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
@@ -788,36 +795,36 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
@@ -841,18 +848,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE12"               ,	   0x10700000005e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE13"               ,	   0x10700000005e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE14"               ,	   0x10700000005f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE15"               ,	   0x10700000005f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
 	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
@@ -877,9 +884,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
-	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"DFA_BST0"                    ,	   0x11800300007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"DFA_BST1"                    ,	   0x11800300007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
 	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
 	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
 	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
@@ -896,7 +903,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
 	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
 	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
@@ -917,15 +924,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
@@ -934,14 +941,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
@@ -984,22 +991,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
@@ -1120,22 +1127,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
@@ -1144,14 +1151,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
@@ -1160,22 +1167,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
@@ -1208,8 +1215,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
@@ -1245,205 +1252,205 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
@@ -1452,22 +1459,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
 	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
@@ -1488,140 +1495,140 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14f0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14f0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14f0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14f0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14f0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14f0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14f0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14f0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14f0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14f0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14f0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14f0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14f00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14f00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14f00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
@@ -1630,11 +1637,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
@@ -1649,35 +1656,35 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
 	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
@@ -1694,9 +1701,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
@@ -1717,7 +1724,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
 	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
 	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
 	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
@@ -1730,204 +1737,204 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
-	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
-	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
-	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
-	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
-	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
-	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	335},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
-	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	355},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	356},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	357},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	358},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	359},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	360},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	361},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	362},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	363},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	384},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	335},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT2"             ,	   0x11f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT3"             ,	   0x11f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	355},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	356},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	357},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	358},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	359},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	360},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	361},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	362},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	363},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	384},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
 	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
 	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
 	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
-	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INSTR_COUNT3"            ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	390},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	391},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	391},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	392},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	393},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	394},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	393},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	394},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
 	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
@@ -1940,721 +1947,721 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
 	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
 	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
-	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
-	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	399},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	400},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	401},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	399},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	400},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	401},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	405},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	406},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	407},
 	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	408},
 	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	409},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_CRC_CTL0"                ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_CRC_CTL1"                ,	   0x11800a0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_CRC_IV0"                 ,	   0x11800a0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_CRC_IV1"                 ,	   0x11800a0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT4"              ,	   0x11800a0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT5"              ,	   0x11800a0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT6"              ,	   0x11800a00009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT7"              ,	   0x11800a0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT8"              ,	   0x11800a0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT9"              ,	   0x11800a0000ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT10"             ,	   0x11800a0000b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT11"             ,	   0x11800a0000b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT12"             ,	   0x11800a0000bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT13"             ,	   0x11800a0000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT14"             ,	   0x11800a0000c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT15"             ,	   0x11800a0000cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT20"             ,	   0x11800a0000e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT21"             ,	   0x11800a0000e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT22"             ,	   0x11800a0000ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT23"             ,	   0x11800a0000f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT24"             ,	   0x11800a0000f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT25"             ,	   0x11800a0000fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT26"             ,	   0x11800a0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT27"             ,	   0x11800a0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT28"             ,	   0x11800a00010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT29"             ,	   0x11800a0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT30"             ,	   0x11800a0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT31"             ,	   0x11800a00011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT4"              ,	   0x11800a0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT5"              ,	   0x11800a0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT6"              ,	   0x11800a00009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT7"              ,	   0x11800a0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT8"              ,	   0x11800a0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT9"              ,	   0x11800a0000ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT10"             ,	   0x11800a0000b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT11"             ,	   0x11800a0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT12"             ,	   0x11800a0000bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT13"             ,	   0x11800a0000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT14"             ,	   0x11800a0000c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT15"             ,	   0x11800a0000cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT20"             ,	   0x11800a0000e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT21"             ,	   0x11800a0000e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT22"             ,	   0x11800a0000ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT23"             ,	   0x11800a0000f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT24"             ,	   0x11800a0000f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT25"             ,	   0x11800a0000fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT26"             ,	   0x11800a0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT27"             ,	   0x11800a0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT28"             ,	   0x11800a00010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT29"             ,	   0x11800a0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT30"             ,	   0x11800a0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT31"             ,	   0x11800a00011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT4"              ,	   0x11800a0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT5"              ,	   0x11800a00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT6"              ,	   0x11800a00009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT7"              ,	   0x11800a0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT8"              ,	   0x11800a0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT9"              ,	   0x11800a0000ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT10"             ,	   0x11800a0000b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT11"             ,	   0x11800a0000b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT12"             ,	   0x11800a0000bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT13"             ,	   0x11800a0000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT14"             ,	   0x11800a0000c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT15"             ,	   0x11800a0000cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT20"             ,	   0x11800a0000e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT21"             ,	   0x11800a0000ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT22"             ,	   0x11800a0000ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT23"             ,	   0x11800a0000f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT24"             ,	   0x11800a0000f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT25"             ,	   0x11800a0000fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT26"             ,	   0x11800a0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT27"             ,	   0x11800a0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT28"             ,	   0x11800a00010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT29"             ,	   0x11800a0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT30"             ,	   0x11800a0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT31"             ,	   0x11800a00011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT4"              ,	   0x11800a0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT5"              ,	   0x11800a00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT6"              ,	   0x11800a00009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT7"              ,	   0x11800a0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT8"              ,	   0x11800a0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT9"              ,	   0x11800a0000ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT10"             ,	   0x11800a0000b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT11"             ,	   0x11800a0000b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT12"             ,	   0x11800a0000bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT13"             ,	   0x11800a0000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT14"             ,	   0x11800a0000c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT15"             ,	   0x11800a0000cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT20"             ,	   0x11800a0000e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT21"             ,	   0x11800a0000ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT22"             ,	   0x11800a0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT23"             ,	   0x11800a0000f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT24"             ,	   0x11800a0000f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT25"             ,	   0x11800a0000fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT26"             ,	   0x11800a0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT27"             ,	   0x11800a0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT28"             ,	   0x11800a00010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT29"             ,	   0x11800a0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT30"             ,	   0x11800a0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT31"             ,	   0x11800a00011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT4"              ,	   0x11800a0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT5"              ,	   0x11800a00009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT6"              ,	   0x11800a0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT7"              ,	   0x11800a0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT8"              ,	   0x11800a0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT9"              ,	   0x11800a0000af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT10"             ,	   0x11800a0000b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT11"             ,	   0x11800a0000b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT12"             ,	   0x11800a0000be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT13"             ,	   0x11800a0000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT14"             ,	   0x11800a0000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT15"             ,	   0x11800a0000cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT20"             ,	   0x11800a0000e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT21"             ,	   0x11800a0000eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT22"             ,	   0x11800a0000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT23"             ,	   0x11800a0000f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT24"             ,	   0x11800a0000fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT25"             ,	   0x11800a0000ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT26"             ,	   0x11800a0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT27"             ,	   0x11800a0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT28"             ,	   0x11800a00010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT29"             ,	   0x11800a0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT30"             ,	   0x11800a0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT31"             ,	   0x11800a00011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT4"              ,	   0x11800a0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT5"              ,	   0x11800a00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT6"              ,	   0x11800a0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT7"              ,	   0x11800a0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT8"              ,	   0x11800a0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT9"              ,	   0x11800a0000af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT10"             ,	   0x11800a0000b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT11"             ,	   0x11800a0000b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT12"             ,	   0x11800a0000be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT13"             ,	   0x11800a0000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT14"             ,	   0x11800a0000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT15"             ,	   0x11800a0000cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT20"             ,	   0x11800a0000e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT21"             ,	   0x11800a0000eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT22"             ,	   0x11800a0000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT23"             ,	   0x11800a0000f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT24"             ,	   0x11800a0000fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT25"             ,	   0x11800a0000ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT26"             ,	   0x11800a0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT27"             ,	   0x11800a0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT28"             ,	   0x11800a00010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT29"             ,	   0x11800a0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT30"             ,	   0x11800a0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT31"             ,	   0x11800a00011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT4"              ,	   0x11800a0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT5"              ,	   0x11800a00009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT6"              ,	   0x11800a0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT7"              ,	   0x11800a0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT8"              ,	   0x11800a0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT9"              ,	   0x11800a0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT10"             ,	   0x11800a0000b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT11"             ,	   0x11800a0000ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT12"             ,	   0x11800a0000bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT13"             ,	   0x11800a0000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT14"             ,	   0x11800a0000c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT15"             ,	   0x11800a0000ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT20"             ,	   0x11800a0000e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT21"             ,	   0x11800a0000ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT22"             ,	   0x11800a0000f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT23"             ,	   0x11800a0000f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT24"             ,	   0x11800a0000fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT25"             ,	   0x11800a0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT26"             ,	   0x11800a0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT27"             ,	   0x11800a00010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT28"             ,	   0x11800a00010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT29"             ,	   0x11800a0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT30"             ,	   0x11800a0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT31"             ,	   0x11800a00011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT4"              ,	   0x11800a0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT5"              ,	   0x11800a00009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT6"              ,	   0x11800a0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT7"              ,	   0x11800a0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT8"              ,	   0x11800a0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT9"              ,	   0x11800a0000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT10"             ,	   0x11800a0000b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT11"             ,	   0x11800a0000ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT12"             ,	   0x11800a0000bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT13"             ,	   0x11800a0000c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT14"             ,	   0x11800a0000c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT15"             ,	   0x11800a0000ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT20"             ,	   0x11800a0000e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT21"             ,	   0x11800a0000ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT22"             ,	   0x11800a0000f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT23"             ,	   0x11800a0000f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT24"             ,	   0x11800a0000fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT25"             ,	   0x11800a0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT26"             ,	   0x11800a0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT27"             ,	   0x11800a00010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT28"             ,	   0x11800a00010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT29"             ,	   0x11800a0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT30"             ,	   0x11800a0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT31"             ,	   0x11800a00011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT4"              ,	   0x11800a0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT5"              ,	   0x11800a00009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT6"              ,	   0x11800a0000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT7"              ,	   0x11800a0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT8"              ,	   0x11800a0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT9"              ,	   0x11800a0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT10"             ,	   0x11800a0000b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT11"             ,	   0x11800a0000bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT12"             ,	   0x11800a0000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT13"             ,	   0x11800a0000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT14"             ,	   0x11800a0000ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT15"             ,	   0x11800a0000cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT20"             ,	   0x11800a0000e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT21"             ,	   0x11800a0000ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT22"             ,	   0x11800a0000f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT23"             ,	   0x11800a0000f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT24"             ,	   0x11800a0000fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT25"             ,	   0x11800a0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT26"             ,	   0x11800a0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT27"             ,	   0x11800a00010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT28"             ,	   0x11800a0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT29"             ,	   0x11800a0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT30"             ,	   0x11800a00011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT31"             ,	   0x11800a00011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT4"              ,	   0x11800a0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT5"              ,	   0x11800a00009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT6"              ,	   0x11800a0000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT7"              ,	   0x11800a0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT8"              ,	   0x11800a0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT9"              ,	   0x11800a0000b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT10"             ,	   0x11800a0000b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT11"             ,	   0x11800a0000bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT12"             ,	   0x11800a0000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT13"             ,	   0x11800a0000c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT14"             ,	   0x11800a0000ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT15"             ,	   0x11800a0000cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT20"             ,	   0x11800a0000e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT21"             ,	   0x11800a0000ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT22"             ,	   0x11800a0000f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT23"             ,	   0x11800a0000f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT24"             ,	   0x11800a0000fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT25"             ,	   0x11800a0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT26"             ,	   0x11800a0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT27"             ,	   0x11800a00010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT28"             ,	   0x11800a0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT29"             ,	   0x11800a0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT30"             ,	   0x11800a00011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT31"             ,	   0x11800a00011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800a0001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800a0001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800a0001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800a0001af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800a0001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800a0001b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800a0001b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800a0001b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800a0001b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800a0001bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800a0001bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800a0001bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800a0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800a0001cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800a0001cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800a0001cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800a0001d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800a0001d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800a0001d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800a0001d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800a0001d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800a0001db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800a0001dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800a0001df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800a0001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800a0001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800a0001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800a0001ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800a0001b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800a0001b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800a0001b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800a0001b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800a0001b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800a0001ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800a0001bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800a0001be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800a0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800a0001ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800a0001cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800a0001ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800a0001d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800a0001d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800a0001d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800a0001d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800a0001d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800a0001da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800a0001dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800a0001de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800a0001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800a0001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800a0001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800a0001ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800a0001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800a0001b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800a0001b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800a0001b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800a0001b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800a0001ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800a0001bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800a0001be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800a0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800a0001ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800a0001cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800a0001ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800a0001d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800a0001d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800a0001d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800a0001d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800a0001d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800a0001da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800a0001dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800a0001de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
@@ -2688,7 +2695,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	476},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	477},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
@@ -2719,22 +2726,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
 	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
 	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
@@ -2767,34 +2774,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
@@ -2804,8 +2811,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
 	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
 	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
-	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
-	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
 	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
 	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
 	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
@@ -2860,18 +2867,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
@@ -2892,18 +2899,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
 	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
 	{"STX0_ARB_CTL"                ,	   0x1180090000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
@@ -2916,12 +2923,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
 	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
 	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
-	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
-	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"STX0_INT_MSK"                ,	   0x11800900006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"STX1_INT_MSK"                ,	   0x11800980006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
 	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
 	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
-	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
-	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"STX0_INT_SYNC"               ,	   0x11800900006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"STX1_INT_SYNC"               ,	   0x11800980006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
 	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
 	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
 	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
@@ -2944,18 +2951,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
@@ -2976,18 +2983,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
 	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
 	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
@@ -3010,30 +3017,30 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
@@ -3986,7 +3993,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"Q3FUS"                       ,	0,	34,	240,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	34,	1,	240,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_256K"                   ,	35,	1,	240,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_63"              ,	36,	28,	240,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	240,	"RO",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
 	{"SEC_INTENA"                  ,	1,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
 	{"DED_INTENA"                  ,	2,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
@@ -4047,7 +4054,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"INORDER_MWF"                 ,	13,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	256,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	256,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	256,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	256,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
@@ -5222,9 +5229,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"WIDX2"                       ,	0,	17,	451,	"RO",	1,	0,	0,	0ull},
 	{"RIDX2"                       ,	17,	17,	451,	"RO",	1,	0,	0,	0ull},
 	{"WIDX"                        ,	34,	17,	451,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	451,	"RAZ",	1,	1,	0,	0},
 	{"RIDX"                        ,	0,	17,	452,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	452,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	453,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	40,	16,	453,	"RO",	1,	0,	0,	0ull},
 	{"POOL"                        ,	56,	3,	453,	"RO",	1,	0,	0,	0ull},
@@ -5245,7 +5252,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"QOS"                         ,	22,	3,	456,	"RO",	1,	0,	0,	0ull},
 	{"ACTIVE"                      ,	25,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"CHK_MODE"                    ,	26,	1,	456,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_27"              ,	27,	1,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"CBUF_FRE"                    ,	28,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"XFER_DWR"                    ,	29,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"XFER_WOR"                    ,	30,	1,	456,	"RO",	1,	0,	0,	0ull},
@@ -5261,11 +5268,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"WORK_MIN"                    ,	4,	3,	457,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	7,	1,	457,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFM"                    ,	8,	3,	457,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	457,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	458,	"RO",	1,	0,	0,	0ull},
 	{"START"                       ,	16,	33,	458,	"RO",	1,	0,	0,	0ull},
 	{"DWB"                         ,	49,	9,	458,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	458,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	458,	"RO",	1,	1,	0,	0},
 	{"QCB_RIDX"                    ,	0,	6,	459,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	459,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	459,	"RO",	1,	0,	0,	0ull},
@@ -5276,9 +5283,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"STATIC_Q"                    ,	3,	1,	460,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	460,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	460,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	460,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	460,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	460,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	460,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	460,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	461,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	461,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	461,	"WR0",	1,	0,	0,	0ull},
@@ -5290,9 +5297,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"S_TAIL"                      ,	63,	1,	461,	"WR0",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	462,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	462,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	462,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	462,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	462,	"RAZ",	1,	1,	0,	0},
 	{"PSB"                         ,	0,	7,	463,	"RO",	1,	0,	0,	0ull},
 	{"PDB"                         ,	7,	4,	463,	"RO",	1,	0,	0,	0ull},
 	{"QCB"                         ,	11,	2,	463,	"RO",	1,	0,	0,	0ull},
@@ -5305,39 +5312,39 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"RIF"                         ,	20,	1,	463,	"RO",	1,	0,	0,	0ull},
 	{"COUNT"                       ,	21,	1,	463,	"RO",	1,	0,	0,	0ull},
 	{"PSB2"                        ,	22,	5,	463,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_63"              ,	27,	37,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	463,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	464,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	464,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	464,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	464,	"RAZ",	1,	1,	0,	0},
 	{"REFIN"                       ,	0,	1,	465,	"R/W",	0,	0,	1ull,	1ull},
 	{"INVRES"                      ,	1,	1,	465,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE"                      ,	0,	32,	466,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	1,	0,	0},
 	{"IV"                          ,	0,	32,	467,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
 	{"RESERVED_32_63"              ,	32,	32,	467,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	17,	468,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	468,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	469,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	469,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	470,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	470,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	471,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	471,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	471,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	472,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	472,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	473,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	473,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	474,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	474,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	474,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	474,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	475,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	475,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	475,	"RO",	0,	0,	0ull,	0ull},
@@ -5652,11 +5659,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"CNT"                         ,	0,	32,	538,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_32_63"              ,	32,	32,	538,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	0,	22,	539,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	539,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	539,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	539,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	539,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	539,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	540,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	540,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	540,	"RO",	1,	0,	0,	0ull},
@@ -5664,32 +5671,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"RESERVED_7_7"                ,	7,	1,	541,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	541,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	541,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	541,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	541,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	542,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	542,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	542,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	542,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	542,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	543,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	543,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	543,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	543,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	543,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	543,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	544,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	544,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	544,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	544,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	544,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	545,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	545,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	545,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	546,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	546,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	546,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	547,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	548,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	548,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	549,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	549,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	549,	"RO",	0,	0,	0ull,	0ull},
@@ -5834,27 +5841,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
 	{"RESERVED_20_63"              ,	20,	44,	568,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	569,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	569,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	569,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	569,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	570,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	570,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	570,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	570,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	570,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	571,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	571,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	571,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	572,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	572,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	572,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	572,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	572,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	572,	"RO",	0,	0,	15360ull,	15360ull},
-	{"RESERVED_48_63"              ,	48,	16,	572,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	572,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	573,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	573,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	573,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	574,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	574,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	575,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	575,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
@@ -6472,23 +6479,23 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800b0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800b0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
@@ -6528,9 +6535,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"DFA_BST0"                    ,	   0x11800300007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"DFA_BST1"                    ,	   0x11800300007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
 	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"DFA_DDR2_ADDR"               ,	   0x1180030000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
 	{"DFA_DDR2_BUS"                ,	   0x1180030000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
@@ -6551,20 +6558,20 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
 	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
 	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
@@ -6573,11 +6580,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
 	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
@@ -6594,12 +6601,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
@@ -6645,27 +6652,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
@@ -6678,93 +6685,93 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
@@ -6782,8 +6789,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
-	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
-	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
@@ -6796,71 +6803,71 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
 	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
 	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
@@ -6869,11 +6876,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
 	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
@@ -6885,10 +6892,10 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
@@ -6907,9 +6914,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
@@ -6930,7 +6937,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
 	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
 	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
 	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
@@ -6948,206 +6955,206 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
 	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
 	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
 	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
 	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
 	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
 	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
 	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	308},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	348},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	349},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	350},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	351},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	352},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	353},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	355},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	308},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	348},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	349},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	350},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	351},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	352},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	353},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	355},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	356},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	356},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	361},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	362},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	362},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	363},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	364},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	365},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	364},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	365},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	366},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	366},
 	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	367},
 	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	367},
 	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	368},
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	368},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	370},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	371},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	372},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	374},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	375},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	370},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	371},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	372},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	374},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	375},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	376},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	377},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	378},
@@ -7156,348 +7163,348 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_DMA_CFG"                ,	   0x107000001c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_INT_ENA"                ,	   0x107000001c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
 	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
 	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM3_INT_SUM"                ,	   0x107000001c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
 	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
 	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
 	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_RXADDR"                 ,	   0x107000001c068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
 	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
 	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
 	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
-	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
-	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
-	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
-	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
-	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
-	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
-	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
-	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
-	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
-	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
-	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
-	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
-	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
-	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
-	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM3_RXCNT"                  ,	   0x107000001c060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_RXMSK0"                 ,	   0x107000001c0c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_RXMSK1"                 ,	   0x107000001c0c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_RXMSK2"                 ,	   0x107000001c0d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM3_RXMSK3"                 ,	   0x107000001c0d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM3_RXMSK4"                 ,	   0x107000001c0e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM3_RXMSK5"                 ,	   0x107000001c0e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM3_RXMSK6"                 ,	   0x107000001c0f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM3_RXMSK7"                 ,	   0x107000001c0f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
 	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
-	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM3_RXSTART"                ,	   0x107000001c058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
-	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM3_TDM_CFG"                ,	   0x107000001c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
-	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM3_TDM_DBG"                ,	   0x107000001c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
 	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
 	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
-	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM3_TXADDR"                 ,	   0x107000001c050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
 	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
 	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
 	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
-	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM3_TXCNT"                  ,	   0x107000001c048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
 	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
 	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
 	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
-	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM3_TXMSK0"                 ,	   0x107000001c080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
 	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
 	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
 	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
-	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM3_TXMSK1"                 ,	   0x107000001c088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
 	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
-	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM3_TXMSK2"                 ,	   0x107000001c090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
 	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
 	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
-	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
-	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
-	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
-	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
-	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
-	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
-	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
-	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
-	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
-	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
-	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
-	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
-	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
-	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
-	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
-	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
-	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM3_TXMSK3"                 ,	   0x107000001c098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM3_TXMSK4"                 ,	   0x107000001c0a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM3_TXMSK5"                 ,	   0x107000001c0a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM3_TXMSK6"                 ,	   0x107000001c0b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM3_TXMSK7"                 ,	   0x107000001c0b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
 	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
 	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
 	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
-	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"PCM3_TXSTART"                ,	   0x107000001c040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
 	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
 	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
 	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
 	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
 	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
 	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
@@ -7526,7 +7533,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	471},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	471},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	472},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	474},
@@ -7543,22 +7550,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
 	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
 	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
@@ -7591,34 +7598,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
@@ -7636,174 +7643,174 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	558},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	559},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	560},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	561},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	562},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	563},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	564},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	565},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	567},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	572},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	573},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	574},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	575},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	576},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	578},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	558},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	559},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	560},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	561},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	562},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	563},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	564},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	565},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	567},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	572},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	573},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	574},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	575},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	576},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	578},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	596},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	598},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	596},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	598},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
 	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
@@ -8751,7 +8758,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"RESERVED_34_63"              ,	34,	30,	215,	"RAZ",	0,	0,	0ull,	0ull},
 	{"Q3FUS"                       ,	0,	34,	216,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_128K"                   ,	34,	1,	216,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	216,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	216,	"RO",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
 	{"SEC_INTENA"                  ,	1,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
 	{"DED_INTENA"                  ,	2,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
@@ -10061,9 +10068,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"WIDX2"                       ,	0,	17,	450,	"RO",	1,	0,	0,	0ull},
 	{"RIDX2"                       ,	17,	17,	450,	"RO",	1,	0,	0,	0ull},
 	{"WIDX"                        ,	34,	17,	450,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	450,	"RO",	1,	0,	0,	0ull},
 	{"RIDX"                        ,	0,	17,	451,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	451,	"RO",	1,	0,	0,	0ull},
 	{"PTR"                         ,	0,	40,	452,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	40,	16,	452,	"RO",	1,	0,	0,	0ull},
 	{"POOL"                        ,	56,	3,	452,	"RO",	1,	0,	0,	0ull},
@@ -10084,7 +10091,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"QOS"                         ,	22,	3,	455,	"RO",	1,	0,	0,	0ull},
 	{"ACTIVE"                      ,	25,	1,	455,	"RO",	1,	0,	0,	0ull},
 	{"CHK_MODE"                    ,	26,	1,	455,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_27"              ,	27,	1,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	455,	"RO",	1,	0,	0,	0ull},
 	{"CBUF_FRE"                    ,	28,	1,	455,	"RO",	1,	0,	0,	0ull},
 	{"XFER_DWR"                    ,	29,	1,	455,	"RO",	1,	0,	0,	0ull},
 	{"XFER_WOR"                    ,	30,	1,	455,	"RO",	1,	0,	0,	0ull},
@@ -10100,11 +10107,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"WORK_MIN"                    ,	4,	3,	456,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	7,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFM"                    ,	8,	3,	456,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	456,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	0,	16,	457,	"RO",	1,	0,	0,	0ull},
 	{"START"                       ,	16,	33,	457,	"RO",	1,	0,	0,	0ull},
 	{"DWB"                         ,	49,	9,	457,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	457,	"RO",	1,	1,	0,	0},
 	{"QCB_RIDX"                    ,	0,	6,	458,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	458,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	458,	"RO",	1,	0,	0,	0ull},
@@ -10114,9 +10121,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"QOS"                         ,	0,	3,	459,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_Q"                    ,	3,	1,	459,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	459,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	459,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	459,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	459,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	459,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	459,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	460,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	460,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	460,	"WR0",	1,	0,	0,	0ull},
@@ -10128,9 +10135,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"S_TAIL"                      ,	63,	1,	460,	"WR0",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	461,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	461,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	461,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	461,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	461,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	461,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	461,	"RAZ",	1,	1,	0,	0},
 	{"PSB"                         ,	0,	7,	462,	"RO",	1,	0,	0,	0ull},
 	{"PDB"                         ,	7,	4,	462,	"RO",	1,	0,	0,	0ull},
 	{"QCB"                         ,	11,	2,	462,	"RO",	1,	0,	0,	0ull},
@@ -10143,32 +10150,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"RIF"                         ,	20,	1,	462,	"RO",	1,	0,	0,	0ull},
 	{"COUNT"                       ,	21,	1,	462,	"RO",	1,	0,	0,	0ull},
 	{"PSB2"                        ,	22,	5,	462,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_63"              ,	27,	37,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	462,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	463,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	463,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	463,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	463,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	463,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	17,	464,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	464,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	466,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	466,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	467,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	467,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	467,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	468,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	468,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	468,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	469,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	470,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	470,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	470,	"RAZ",	1,	1,	0,	0},
 	{"ADR"                         ,	0,	1,	471,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND"                        ,	1,	1,	471,	"RO",	0,	0,	0ull,	0ull},
 	{"NBR0"                        ,	2,	1,	471,	"RO",	0,	0,	0ull,	0ull},
@@ -10282,11 +10289,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"PENDING"                     ,	17,	1,	496,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	496,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	497,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	497,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	497,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	497,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	497,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	497,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	498,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	498,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	498,	"RO",	1,	0,	0,	0ull},
@@ -10294,32 +10301,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	499,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	499,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	499,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	499,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	500,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	500,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	500,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	501,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	501,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	501,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	501,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	501,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	501,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	501,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	502,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	502,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	502,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	502,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	502,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	503,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	503,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	504,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	504,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	505,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	506,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	506,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	506,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	506,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	507,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	507,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	507,	"RO",	0,	0,	0ull,	0ull},
@@ -11000,27 +11007,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
 	{"RESERVED_38_63"              ,	38,	26,	601,	"RAZ",	1,	1,	0,	0},
 	{"ZIP_CTL"                     ,	0,	4,	602,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	602,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	602,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	602,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	603,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	603,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	603,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	603,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	603,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	603,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	604,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	604,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	604,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	605,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	605,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	605,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	605,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	605,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	605,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	605,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	605,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	606,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	606,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	606,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	607,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	607,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	607,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	608,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	608,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
@@ -11592,24 +11599,24 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800B0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800b0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800b0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800b0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
@@ -11639,21 +11646,21 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
@@ -11662,11 +11669,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
 	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
@@ -11683,12 +11690,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
 	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
 	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
@@ -11734,27 +11741,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
 	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
 	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
@@ -11767,95 +11774,95 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
 	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
 	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
-	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_TX_CLK_MSK000"          ,	   0x1180008000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"GMX0_TX_CLK_MSK001"          ,	   0x1180008000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
@@ -11873,8 +11880,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
-	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
-	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
@@ -11887,69 +11894,69 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
 	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
 	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
@@ -11958,11 +11965,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
 	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
@@ -11974,10 +11981,10 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
@@ -11998,9 +12005,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
@@ -12021,7 +12028,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
 	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
 	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
 	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
@@ -12039,190 +12046,190 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
 	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	267},
 	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
 	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
 	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
 	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
-	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
-	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
-	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
-	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
-	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
 	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	269},
 	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	272},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	273},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	274},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	275},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	290},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	306},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	307},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	308},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	309},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	310},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	311},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	312},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	313},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	314},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	315},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	316},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	317},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	336},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	272},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	273},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	274},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	275},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	290},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	306},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	307},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	308},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	309},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	310},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	311},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	312},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	313},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	314},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	315},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	316},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	317},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	336},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	337},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	341},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	342},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	343},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	343},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	344},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	346},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	346},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	347},
 	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	348},
 	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	349},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	351},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	352},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	351},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	352},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	357},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	358},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	359},
@@ -12231,348 +12238,348 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
 	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
 	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
-	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCM3_DMA_CFG"                ,	   0x107000001c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
 	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
 	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
 	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
-	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"PCM3_INT_ENA"                ,	   0x107000001c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
 	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
 	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
 	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"PCM3_INT_SUM"                ,	   0x107000001c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
 	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
 	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
 	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
-	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"PCM3_RXADDR"                 ,	   0x107000001c068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
 	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
 	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
 	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
-	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
-	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
-	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM3_RXCNT"                  ,	   0x107000001c060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM3_RXMSK0"                 ,	   0x107000001c0c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM3_RXMSK1"                 ,	   0x107000001c0c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM3_RXMSK2"                 ,	   0x107000001c0d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM3_RXMSK3"                 ,	   0x107000001c0d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM3_RXMSK4"                 ,	   0x107000001c0e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM3_RXMSK5"                 ,	   0x107000001c0e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM3_RXMSK6"                 ,	   0x107000001c0f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM3_RXMSK7"                 ,	   0x107000001c0f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
 	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
-	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM3_RXSTART"                ,	   0x107000001c058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
-	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM3_TDM_CFG"                ,	   0x107000001c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
-	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM3_TDM_DBG"                ,	   0x107000001c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
-	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM3_TXADDR"                 ,	   0x107000001c050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
 	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
 	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
-	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM3_TXCNT"                  ,	   0x107000001c048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
 	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
 	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
 	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM3_TXMSK0"                 ,	   0x107000001c080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
 	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_TXMSK1"                 ,	   0x107000001c088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
 	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_TXMSK2"                 ,	   0x107000001c090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
 	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
 	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
 	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_TXMSK3"                 ,	   0x107000001c098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_TXMSK4"                 ,	   0x107000001c0a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM3_TXMSK5"                 ,	   0x107000001c0a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_TXMSK6"                 ,	   0x107000001c0b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_TXMSK7"                 ,	   0x107000001c0b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
 	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_TXSTART"                ,	   0x107000001c040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
 	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
 	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
 	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
 	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
 	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
@@ -12601,7 +12608,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
@@ -12617,22 +12624,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	459},
 	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
@@ -12665,34 +12672,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
@@ -12710,147 +12717,147 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	488},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	489},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	490},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	491},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	494},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	498},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	501},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	502},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	503},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	504},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	505},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	488},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	489},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	490},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	491},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	494},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	498},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	501},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	502},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	503},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	504},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	505},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	543},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	544},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	545},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	546},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	547},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	548},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	549},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	550},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	551},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	552},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	553},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	554},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	555},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	556},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	557},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	558},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	559},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	543},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	544},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	545},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	546},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	547},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	548},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	549},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	550},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	551},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	552},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	553},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	554},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	555},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	556},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	557},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	558},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	559},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
 	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
@@ -13663,7 +13670,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"RESERVED_34_63"              ,	34,	30,	195,	"RAZ",	0,	0,	0ull,	0ull},
 	{"Q3FUS"                       ,	0,	34,	196,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_64K"                    ,	34,	1,	196,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	196,	"RO",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
 	{"SEC_INTENA"                  ,	1,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
 	{"DED_INTENA"                  ,	2,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
@@ -14935,9 +14942,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"WIDX2"                       ,	0,	17,	431,	"RO",	1,	0,	0,	0ull},
 	{"RIDX2"                       ,	17,	17,	431,	"RO",	1,	0,	0,	0ull},
 	{"WIDX"                        ,	34,	17,	431,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	431,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	431,	"RO",	1,	0,	0,	0ull},
 	{"RIDX"                        ,	0,	17,	432,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	432,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	432,	"RO",	1,	0,	0,	0ull},
 	{"PTR"                         ,	0,	40,	433,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	40,	16,	433,	"RO",	1,	0,	0,	0ull},
 	{"POOL"                        ,	56,	3,	433,	"RO",	1,	0,	0,	0ull},
@@ -14958,7 +14965,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"QOS"                         ,	22,	3,	436,	"RO",	1,	0,	0,	0ull},
 	{"ACTIVE"                      ,	25,	1,	436,	"RO",	1,	0,	0,	0ull},
 	{"CHK_MODE"                    ,	26,	1,	436,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_27"              ,	27,	1,	436,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	436,	"RO",	1,	0,	0,	0ull},
 	{"CBUF_FRE"                    ,	28,	1,	436,	"RO",	1,	0,	0,	0ull},
 	{"XFER_DWR"                    ,	29,	1,	436,	"RO",	1,	0,	0,	0ull},
 	{"XFER_WOR"                    ,	30,	1,	436,	"RO",	1,	0,	0,	0ull},
@@ -14974,11 +14981,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"WORK_MIN"                    ,	4,	3,	437,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	7,	1,	437,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFM"                    ,	8,	3,	437,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	437,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	437,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	0,	16,	438,	"RO",	1,	0,	0,	0ull},
 	{"START"                       ,	16,	33,	438,	"RO",	1,	0,	0,	0ull},
 	{"DWB"                         ,	49,	9,	438,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	438,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	438,	"RO",	1,	1,	0,	0},
 	{"QCB_RIDX"                    ,	0,	6,	439,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	439,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	439,	"RO",	1,	0,	0,	0ull},
@@ -14988,9 +14995,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"QOS"                         ,	0,	3,	440,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_Q"                    ,	3,	1,	440,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	440,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_5_7"                ,	5,	3,	440,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	440,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	440,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	440,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	440,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	441,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	441,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	441,	"WR0",	1,	0,	0,	0ull},
@@ -15002,9 +15009,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"S_TAIL"                      ,	63,	1,	441,	"WR0",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	442,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	442,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	442,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	442,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	442,	"RAZ",	1,	1,	0,	0},
 	{"PSB"                         ,	0,	7,	443,	"RO",	1,	0,	0,	0ull},
 	{"PDB"                         ,	7,	4,	443,	"RO",	1,	0,	0,	0ull},
 	{"QCB"                         ,	11,	2,	443,	"RO",	1,	0,	0,	0ull},
@@ -15017,32 +15024,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"RIF"                         ,	20,	1,	443,	"RO",	1,	0,	0,	0ull},
 	{"COUNT"                       ,	21,	1,	443,	"RO",	1,	0,	0,	0ull},
 	{"PSB2"                        ,	22,	5,	443,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_63"              ,	27,	37,	443,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	443,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	444,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	444,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	444,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	444,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	444,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	444,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	17,	445,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	445,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	445,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	446,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	446,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	447,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	447,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	447,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	448,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	448,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	448,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	448,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	449,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	449,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	449,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	449,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	450,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	450,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	451,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	451,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	451,	"RAZ",	1,	1,	0,	0},
 	{"ADR"                         ,	0,	1,	452,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND"                        ,	1,	1,	452,	"RO",	0,	0,	0ull,	0ull},
 	{"NBR0"                        ,	2,	1,	452,	"RO",	0,	0,	0ull,	0ull},
@@ -15160,11 +15167,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"PENDING"                     ,	17,	1,	477,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	477,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	478,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	478,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	478,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	478,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	478,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	478,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	479,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	479,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	479,	"RO",	1,	0,	0,	0ull},
@@ -15172,32 +15179,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	480,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	480,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	480,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	480,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	481,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	481,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	481,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	481,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	482,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	482,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	482,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	482,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	482,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	482,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	483,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	483,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	483,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	483,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	484,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	484,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	485,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	485,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	485,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	485,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	486,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	486,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	486,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	487,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	487,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	487,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	487,	"RAZ",	1,	1,	0,	0},
 	{"INEPINT"                     ,	0,	16,	488,	"RO",	0,	0,	0ull,	0ull},
 	{"OUTEPINT"                    ,	16,	16,	488,	"RO",	0,	0,	0ull,	0ull},
 	{"INEPMSK"                     ,	0,	16,	489,	"R/W",	0,	0,	0ull,	0ull},
@@ -16331,72 +16338,72 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800B0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800B8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_RX_WOL"                 ,	   0x11800B0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX1_RX_WOL"                 ,	   0x11800B8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX0_RX_WOL_MSK"             ,	   0x11800B0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_RX_WOL_MSK"             ,	   0x11800B8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_RX_WOL_POWOK"           ,	   0x11800B0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX1_RX_WOL_POWOK"           ,	   0x11800B8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX0_RX_WOL_SIG"             ,	   0x11800B0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX1_RX_WOL_SIG"             ,	   0x11800B8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800b8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800b8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800b8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800b0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800b8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800b0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800b8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800b0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800b8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800b0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800b8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800b0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800b8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800b0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800b8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800b0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800b8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800b0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800b8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800b0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800b8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RLD_SETTING"            ,	   0x11800b0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RLD_SETTING"            ,	   0x11800b8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800b0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800b8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800b8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800b8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800b8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800b8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_RX_WOL"                 ,	   0x11800b0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_RX_WOL"                 ,	   0x11800b8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_RX_WOL_MSK"             ,	   0x11800b0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_RX_WOL_MSK"             ,	   0x11800b8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_RX_WOL_POWOK"           ,	   0x11800b0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_RX_WOL_POWOK"           ,	   0x11800b8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_RX_WOL_SIG"             ,	   0x11800b0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX1_RX_WOL_SIG"             ,	   0x11800b8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800b0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800b8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800b8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800b8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800b8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800b8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800b0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800b8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800b8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800b8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800b8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800b8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800b0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800b0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
@@ -16411,12 +16418,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
@@ -16427,12 +16434,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN0"               ,	   0x10700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN0"               ,	   0x10700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN0"               ,	   0x10700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN0"               ,	   0x10700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN0"               ,	   0x10700000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN0"               ,	   0x10700000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
@@ -16444,12 +16451,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
@@ -16460,12 +16467,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT26_EN1"               ,	   0x10700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT27_EN1"               ,	   0x10700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT28_EN1"               ,	   0x10700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT29_EN1"               ,	   0x10700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT30_EN1"               ,	   0x10700000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT31_EN1"               ,	   0x10700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
@@ -16487,36 +16494,36 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
@@ -16540,18 +16547,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
-	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE12"               ,	   0x10700000005e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE13"               ,	   0x10700000005e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE14"               ,	   0x10700000005f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE15"               ,	   0x10700000005f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
 	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
@@ -16576,9 +16583,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
-	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"DFA_BST0"                    ,	   0x11800300007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"DFA_BST1"                    ,	   0x11800300007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
 	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
 	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
 	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
@@ -16595,7 +16602,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
 	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
 	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
@@ -16616,15 +16623,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
@@ -16633,14 +16640,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
@@ -16683,22 +16690,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
@@ -16819,22 +16826,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
@@ -16843,14 +16850,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
@@ -16859,22 +16866,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
@@ -16907,8 +16914,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
@@ -16941,210 +16948,210 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
@@ -17153,24 +17160,24 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
 	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
@@ -17191,145 +17198,145 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14f0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14f0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14f0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14f0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14f0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14f0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14f0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14f0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14f0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14f0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14f0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14f0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14f00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14f00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14f00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
@@ -17338,11 +17345,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
@@ -17357,35 +17364,35 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
@@ -17403,9 +17410,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
@@ -17426,7 +17433,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
 	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
 	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
 	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
@@ -17441,204 +17448,204 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
-	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
-	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
-	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
-	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
-	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
-	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
-	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	394},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT2"             ,	   0x11f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT3"             ,	   0x11f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	394},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
 	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
 	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
 	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
-	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INSTR_COUNT3"            ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	400},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	401},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	401},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	402},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	404},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	404},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
 	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
@@ -17651,722 +17658,722 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
 	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
 	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	409},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	410},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	411},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	413},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	409},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	410},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	411},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	413},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	415},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	416},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	417},
 	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	418},
 	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	419},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_CRC_CTL0"                ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_CRC_CTL1"                ,	   0x11800a0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_CRC_IV0"                 ,	   0x11800a0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_CRC_IV1"                 ,	   0x11800a0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT4"              ,	   0x11800a0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT5"              ,	   0x11800a0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT6"              ,	   0x11800a00009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT7"              ,	   0x11800a0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT8"              ,	   0x11800a0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT9"              ,	   0x11800a0000ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT10"             ,	   0x11800a0000b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT11"             ,	   0x11800a0000b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT12"             ,	   0x11800a0000bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT13"             ,	   0x11800a0000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT14"             ,	   0x11800a0000c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT15"             ,	   0x11800a0000cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT20"             ,	   0x11800a0000e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT21"             ,	   0x11800a0000e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT22"             ,	   0x11800a0000ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT23"             ,	   0x11800a0000f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT24"             ,	   0x11800a0000f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT25"             ,	   0x11800a0000fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT26"             ,	   0x11800a0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT27"             ,	   0x11800a0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT28"             ,	   0x11800a00010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT29"             ,	   0x11800a0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT30"             ,	   0x11800a0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT31"             ,	   0x11800a00011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT4"              ,	   0x11800a0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT5"              ,	   0x11800a0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT6"              ,	   0x11800a00009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT7"              ,	   0x11800a0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT8"              ,	   0x11800a0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT9"              ,	   0x11800a0000ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT10"             ,	   0x11800a0000b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT11"             ,	   0x11800a0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT12"             ,	   0x11800a0000bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT13"             ,	   0x11800a0000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT14"             ,	   0x11800a0000c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT15"             ,	   0x11800a0000cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT20"             ,	   0x11800a0000e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT21"             ,	   0x11800a0000e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT22"             ,	   0x11800a0000ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT23"             ,	   0x11800a0000f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT24"             ,	   0x11800a0000f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT25"             ,	   0x11800a0000fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT26"             ,	   0x11800a0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT27"             ,	   0x11800a0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT28"             ,	   0x11800a00010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT29"             ,	   0x11800a0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT30"             ,	   0x11800a0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT31"             ,	   0x11800a00011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT4"              ,	   0x11800a0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT5"              ,	   0x11800a00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT6"              ,	   0x11800a00009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT7"              ,	   0x11800a0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT8"              ,	   0x11800a0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT9"              ,	   0x11800a0000ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT10"             ,	   0x11800a0000b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT11"             ,	   0x11800a0000b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT12"             ,	   0x11800a0000bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT13"             ,	   0x11800a0000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT14"             ,	   0x11800a0000c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT15"             ,	   0x11800a0000cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT20"             ,	   0x11800a0000e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT21"             ,	   0x11800a0000ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT22"             ,	   0x11800a0000ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT23"             ,	   0x11800a0000f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT24"             ,	   0x11800a0000f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT25"             ,	   0x11800a0000fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT26"             ,	   0x11800a0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT27"             ,	   0x11800a0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT28"             ,	   0x11800a00010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT29"             ,	   0x11800a0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT30"             ,	   0x11800a0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT31"             ,	   0x11800a00011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT4"              ,	   0x11800a0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT5"              ,	   0x11800a00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT6"              ,	   0x11800a00009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT7"              ,	   0x11800a0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT8"              ,	   0x11800a0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT9"              ,	   0x11800a0000ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT10"             ,	   0x11800a0000b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT11"             ,	   0x11800a0000b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT12"             ,	   0x11800a0000bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT13"             ,	   0x11800a0000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT14"             ,	   0x11800a0000c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT15"             ,	   0x11800a0000cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT20"             ,	   0x11800a0000e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT21"             ,	   0x11800a0000ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT22"             ,	   0x11800a0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT23"             ,	   0x11800a0000f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT24"             ,	   0x11800a0000f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT25"             ,	   0x11800a0000fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT26"             ,	   0x11800a0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT27"             ,	   0x11800a0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT28"             ,	   0x11800a00010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT29"             ,	   0x11800a0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT30"             ,	   0x11800a0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT31"             ,	   0x11800a00011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT4"              ,	   0x11800a0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT5"              ,	   0x11800a00009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT6"              ,	   0x11800a0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT7"              ,	   0x11800a0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT8"              ,	   0x11800a0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT9"              ,	   0x11800a0000af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT10"             ,	   0x11800a0000b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT11"             ,	   0x11800a0000b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT12"             ,	   0x11800a0000be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT13"             ,	   0x11800a0000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT14"             ,	   0x11800a0000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT15"             ,	   0x11800a0000cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT20"             ,	   0x11800a0000e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT21"             ,	   0x11800a0000eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT22"             ,	   0x11800a0000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT23"             ,	   0x11800a0000f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT24"             ,	   0x11800a0000fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT25"             ,	   0x11800a0000ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT26"             ,	   0x11800a0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT27"             ,	   0x11800a0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT28"             ,	   0x11800a00010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT29"             ,	   0x11800a0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT30"             ,	   0x11800a0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT31"             ,	   0x11800a00011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT4"              ,	   0x11800a0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT5"              ,	   0x11800a00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT6"              ,	   0x11800a0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT7"              ,	   0x11800a0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT8"              ,	   0x11800a0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT9"              ,	   0x11800a0000af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT10"             ,	   0x11800a0000b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT11"             ,	   0x11800a0000b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT12"             ,	   0x11800a0000be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT13"             ,	   0x11800a0000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT14"             ,	   0x11800a0000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT15"             ,	   0x11800a0000cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT20"             ,	   0x11800a0000e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT21"             ,	   0x11800a0000eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT22"             ,	   0x11800a0000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT23"             ,	   0x11800a0000f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT24"             ,	   0x11800a0000fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT25"             ,	   0x11800a0000ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT26"             ,	   0x11800a0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT27"             ,	   0x11800a0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT28"             ,	   0x11800a00010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT29"             ,	   0x11800a0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT30"             ,	   0x11800a0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT31"             ,	   0x11800a00011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT4"              ,	   0x11800a0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT5"              ,	   0x11800a00009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT6"              ,	   0x11800a0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT7"              ,	   0x11800a0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT8"              ,	   0x11800a0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT9"              ,	   0x11800a0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT10"             ,	   0x11800a0000b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT11"             ,	   0x11800a0000ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT12"             ,	   0x11800a0000bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT13"             ,	   0x11800a0000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT14"             ,	   0x11800a0000c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT15"             ,	   0x11800a0000ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT20"             ,	   0x11800a0000e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT21"             ,	   0x11800a0000ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT22"             ,	   0x11800a0000f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT23"             ,	   0x11800a0000f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT24"             ,	   0x11800a0000fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT25"             ,	   0x11800a0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT26"             ,	   0x11800a0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT27"             ,	   0x11800a00010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT28"             ,	   0x11800a00010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT29"             ,	   0x11800a0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT30"             ,	   0x11800a0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT31"             ,	   0x11800a00011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT4"              ,	   0x11800a0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT5"              ,	   0x11800a00009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT6"              ,	   0x11800a0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT7"              ,	   0x11800a0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT8"              ,	   0x11800a0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT9"              ,	   0x11800a0000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT10"             ,	   0x11800a0000b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT11"             ,	   0x11800a0000ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT12"             ,	   0x11800a0000bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT13"             ,	   0x11800a0000c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT14"             ,	   0x11800a0000c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT15"             ,	   0x11800a0000ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT20"             ,	   0x11800a0000e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT21"             ,	   0x11800a0000ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT22"             ,	   0x11800a0000f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT23"             ,	   0x11800a0000f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT24"             ,	   0x11800a0000fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT25"             ,	   0x11800a0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT26"             ,	   0x11800a0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT27"             ,	   0x11800a00010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT28"             ,	   0x11800a00010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT29"             ,	   0x11800a0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT30"             ,	   0x11800a0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT31"             ,	   0x11800a00011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT4"              ,	   0x11800a0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT5"              ,	   0x11800a00009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT6"              ,	   0x11800a0000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT7"              ,	   0x11800a0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT8"              ,	   0x11800a0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT9"              ,	   0x11800a0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT10"             ,	   0x11800a0000b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT11"             ,	   0x11800a0000bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT12"             ,	   0x11800a0000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT13"             ,	   0x11800a0000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT14"             ,	   0x11800a0000ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT15"             ,	   0x11800a0000cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT20"             ,	   0x11800a0000e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT21"             ,	   0x11800a0000ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT22"             ,	   0x11800a0000f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT23"             ,	   0x11800a0000f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT24"             ,	   0x11800a0000fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT25"             ,	   0x11800a0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT26"             ,	   0x11800a0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT27"             ,	   0x11800a00010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT28"             ,	   0x11800a0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT29"             ,	   0x11800a0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT30"             ,	   0x11800a00011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT31"             ,	   0x11800a00011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT4"              ,	   0x11800a0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT5"              ,	   0x11800a00009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT6"              ,	   0x11800a0000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT7"              ,	   0x11800a0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT8"              ,	   0x11800a0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT9"              ,	   0x11800a0000b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT10"             ,	   0x11800a0000b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT11"             ,	   0x11800a0000bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT12"             ,	   0x11800a0000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT13"             ,	   0x11800a0000c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT14"             ,	   0x11800a0000ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT15"             ,	   0x11800a0000cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT20"             ,	   0x11800a0000e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT21"             ,	   0x11800a0000ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT22"             ,	   0x11800a0000f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT23"             ,	   0x11800a0000f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT24"             ,	   0x11800a0000fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT25"             ,	   0x11800a0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT26"             ,	   0x11800a0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT27"             ,	   0x11800a00010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT28"             ,	   0x11800a0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT29"             ,	   0x11800a0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT30"             ,	   0x11800a00011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT31"             ,	   0x11800a00011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800a0001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800a0001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800a0001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800a0001af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800a0001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800a0001b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800a0001b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800a0001b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800a0001b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800a0001bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800a0001bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800a0001bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800a0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800a0001cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800a0001cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800a0001cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800a0001d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800a0001d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800a0001d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800a0001d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800a0001d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800a0001db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800a0001dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800a0001df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800a0001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800a0001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800a0001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800a0001ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800a0001b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800a0001b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800a0001b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800a0001b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800a0001b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800a0001ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800a0001bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800a0001be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800a0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800a0001ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800a0001cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800a0001ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800a0001d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800a0001d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800a0001d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800a0001d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800a0001d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800a0001da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800a0001dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800a0001de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800a0001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800a0001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800a0001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800a0001ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800a0001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800a0001b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800a0001b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800a0001b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800a0001b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800a0001ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800a0001bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800a0001be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800a0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800a0001ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800a0001cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800a0001ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800a0001d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800a0001d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800a0001d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800a0001d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800a0001d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800a0001da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800a0001dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800a0001de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
@@ -18400,7 +18407,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
@@ -18431,22 +18438,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
 	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
 	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	497},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	498},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
@@ -18479,34 +18486,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
@@ -18516,8 +18523,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
 	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
 	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
-	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
-	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
 	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
 	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
 	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
@@ -18572,18 +18579,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
@@ -18604,18 +18611,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
-	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
 	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
 	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
 	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
@@ -18632,12 +18639,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
 	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
 	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
-	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
-	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"STX0_INT_MSK"                ,	   0x11800900006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"STX1_INT_MSK"                ,	   0x11800980006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
 	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
 	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
-	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
-	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"STX0_INT_SYNC"               ,	   0x11800900006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"STX1_INT_SYNC"               ,	   0x11800980006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
 	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
 	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
 	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
@@ -18660,18 +18667,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
@@ -18692,18 +18699,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
@@ -18726,30 +18733,30 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
@@ -19747,7 +19754,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"Q3FUS"                       ,	0,	34,	247,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	34,	1,	247,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_256K"                   ,	35,	1,	247,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_63"              ,	36,	28,	247,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	247,	"RO",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
 	{"SEC_INTENA"                  ,	1,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
 	{"DED_INTENA"                  ,	2,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
@@ -19808,7 +19815,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"INORDER_MWF"                 ,	13,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	263,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	263,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	263,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	263,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	263,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
@@ -21053,9 +21060,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"WIDX2"                       ,	0,	17,	462,	"RO",	1,	0,	0,	0ull},
 	{"RIDX2"                       ,	17,	17,	462,	"RO",	1,	0,	0,	0ull},
 	{"WIDX"                        ,	34,	17,	462,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	462,	"RAZ",	1,	1,	0,	0},
 	{"RIDX"                        ,	0,	17,	463,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	463,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	464,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	40,	16,	464,	"RO",	1,	0,	0,	0ull},
 	{"POOL"                        ,	56,	3,	464,	"RO",	1,	0,	0,	0ull},
@@ -21076,7 +21083,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"QOS"                         ,	22,	3,	467,	"RO",	1,	0,	0,	0ull},
 	{"ACTIVE"                      ,	25,	1,	467,	"RO",	1,	0,	0,	0ull},
 	{"CHK_MODE"                    ,	26,	1,	467,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_27"              ,	27,	1,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	467,	"RO",	1,	0,	0,	0ull},
 	{"CBUF_FRE"                    ,	28,	1,	467,	"RO",	1,	0,	0,	0ull},
 	{"XFER_DWR"                    ,	29,	1,	467,	"RO",	1,	0,	0,	0ull},
 	{"XFER_WOR"                    ,	30,	1,	467,	"RO",	1,	0,	0,	0ull},
@@ -21092,11 +21099,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"WORK_MIN"                    ,	4,	3,	468,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	7,	1,	468,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFM"                    ,	8,	3,	468,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	468,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	469,	"RO",	1,	0,	0,	0ull},
 	{"START"                       ,	16,	33,	469,	"RO",	1,	0,	0,	0ull},
 	{"DWB"                         ,	49,	9,	469,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	469,	"RO",	1,	1,	0,	0},
 	{"QCB_RIDX"                    ,	0,	6,	470,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	470,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	470,	"RO",	1,	0,	0,	0ull},
@@ -21107,9 +21114,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"STATIC_Q"                    ,	3,	1,	471,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	471,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	471,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	471,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	471,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	471,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	472,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	472,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	472,	"WR0",	1,	0,	0,	0ull},
@@ -21121,9 +21128,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"S_TAIL"                      ,	63,	1,	472,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	473,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	473,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	473,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	473,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	473,	"RAZ",	1,	1,	0,	0},
 	{"PSB"                         ,	0,	7,	474,	"RO",	1,	0,	0,	0ull},
 	{"PDB"                         ,	7,	4,	474,	"RO",	1,	0,	0,	0ull},
 	{"QCB"                         ,	11,	2,	474,	"RO",	1,	0,	0,	0ull},
@@ -21136,39 +21143,39 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"RIF"                         ,	20,	1,	474,	"RO",	1,	0,	0,	0ull},
 	{"COUNT"                       ,	21,	1,	474,	"RO",	1,	0,	0,	0ull},
 	{"PSB2"                        ,	22,	5,	474,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_27_63"              ,	27,	37,	474,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	474,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	475,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	475,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	475,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	475,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	475,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	475,	"RAZ",	1,	1,	0,	0},
 	{"REFIN"                       ,	0,	1,	476,	"R/W",	0,	0,	1ull,	1ull},
 	{"INVRES"                      ,	1,	1,	476,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_2_63"               ,	2,	62,	476,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE"                      ,	0,	32,	477,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	477,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	477,	"RAZ",	1,	1,	0,	0},
 	{"IV"                          ,	0,	32,	478,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
 	{"RESERVED_32_63"              ,	32,	32,	478,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	17,	479,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_17_63"              ,	17,	47,	479,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	479,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	480,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	480,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	480,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	481,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	481,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	482,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	482,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	483,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	483,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	483,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	484,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	484,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	485,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	485,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	485,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	486,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	486,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	486,	"RO",	0,	0,	0ull,	0ull},
@@ -21494,11 +21501,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"CNT"                         ,	0,	32,	551,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_32_63"              ,	32,	32,	551,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	0,	22,	552,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	552,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	552,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	552,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	552,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	552,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	553,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	553,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	553,	"RO",	1,	0,	0,	0ull},
@@ -21506,32 +21513,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	554,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	554,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	554,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	554,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	554,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	555,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	555,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	555,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	555,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	555,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	556,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	556,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	556,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	556,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	556,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	556,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	557,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	557,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	557,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	557,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	557,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	558,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	558,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	558,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	559,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	559,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	559,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	560,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	560,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	560,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	561,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	561,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	561,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	561,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	562,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	562,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	562,	"RO",	0,	0,	0ull,	0ull},
@@ -21676,27 +21683,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
 	{"RESERVED_20_63"              ,	20,	44,	581,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	582,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	582,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	582,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	582,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	583,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	583,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	583,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	583,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	583,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	583,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	584,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	584,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	584,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	585,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	585,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	585,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	585,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	585,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	585,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	585,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	585,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	586,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	586,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	586,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	587,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	587,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	587,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	588,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	588,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
@@ -22308,62 +22315,62 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800b8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800b8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800b8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800b0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800b8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800b0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800b8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800b0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800b8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800b0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800b8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800b0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800b8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800b0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800b8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800b0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800b8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800b0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800b8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_SETTING"            ,	   0x11800b0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_SETTING"            ,	   0x11800b8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800b0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800b8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800b8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800b8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800b8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800b8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800b0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800b8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800b8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800b8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800b8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800b8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800b0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800b8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800b8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800b8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800b8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800b8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800b0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800b0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
@@ -22378,12 +22385,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
@@ -22394,12 +22401,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT26_EN0"               ,	   0x10700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT27_EN0"               ,	   0x10700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT28_EN0"               ,	   0x10700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT29_EN0"               ,	   0x10700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT30_EN0"               ,	   0x10700000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT31_EN0"               ,	   0x10700000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
@@ -22411,12 +22418,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
@@ -22427,45 +22434,45 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT26_EN1"               ,	   0x10700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT27_EN1"               ,	   0x10700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT28_EN1"               ,	   0x10700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT29_EN1"               ,	   0x10700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT30_EN1"               ,	   0x10700000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT31_EN1"               ,	   0x10700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT12_EN4_0"             ,	   0x1070000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT13_EN4_0"             ,	   0x1070000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT14_EN4_0"             ,	   0x1070000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT15_EN4_0"             ,	   0x1070000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT12_EN4_1"             ,	   0x1070000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT13_EN4_1"             ,	   0x1070000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT14_EN4_1"             ,	   0x1070000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT15_EN4_1"             ,	   0x1070000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT12_EN4_0"             ,	   0x1070000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT13_EN4_0"             ,	   0x1070000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT14_EN4_0"             ,	   0x1070000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT15_EN4_0"             ,	   0x1070000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT12_EN4_1"             ,	   0x1070000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT13_EN4_1"             ,	   0x1070000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT14_EN4_1"             ,	   0x1070000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT15_EN4_1"             ,	   0x1070000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
@@ -22486,52 +22493,52 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT12_SUM4"              ,	   0x1070000000C60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT13_SUM4"              ,	   0x1070000000C68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT14_SUM4"              ,	   0x1070000000C70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT15_SUM4"              ,	   0x1070000000C78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_SUM4"              ,	   0x1070000000c60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_SUM4"              ,	   0x1070000000c68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_SUM4"              ,	   0x1070000000c70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_SUM4"              ,	   0x1070000000c78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
@@ -22555,18 +22562,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE12"               ,	   0x10700000005e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE13"               ,	   0x10700000005e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE14"               ,	   0x10700000005f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE15"               ,	   0x10700000005f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
 	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
@@ -22591,9 +22598,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
 	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
 	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
-	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"DFA_BST0"                    ,	   0x11800300007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"DFA_BST1"                    ,	   0x11800300007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
 	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
 	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	47},
 	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	48},
@@ -22611,7 +22618,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
 	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
 	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
@@ -22632,15 +22639,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
@@ -22649,14 +22656,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
@@ -22699,22 +22706,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
@@ -22843,22 +22850,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
@@ -22867,14 +22874,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
@@ -22883,22 +22890,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
@@ -22931,8 +22938,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
@@ -22965,210 +22972,210 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
@@ -23177,38 +23184,38 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_TX_SPI_ROUND000"        ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND001"        ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND002"        ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND003"        ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND016"        ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND017"        ,	   0x1180008000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX_SPI_ROUND018"        ,	   0x1180008000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
@@ -23229,18 +23236,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_TX_SPI_ROUND001"        ,	   0x1180010000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND002"        ,	   0x1180010000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND003"        ,	   0x1180010000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND016"        ,	   0x1180010000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND017"        ,	   0x1180010000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND018"        ,	   0x1180010000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
@@ -23257,8 +23264,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GMX1_TX_SPI_ROUND029"        ,	   0x1180010000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND030"        ,	   0x1180010000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX_SPI_ROUND031"        ,	   0x1180010000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
 	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
@@ -23279,145 +23286,145 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14f0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14f0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14f0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14f0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14f0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14f0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14f0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14f0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14f0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14f0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14f0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14f0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14f00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14f00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14f00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
@@ -23426,11 +23433,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
@@ -23445,35 +23452,35 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
@@ -23490,14 +23497,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
@@ -23518,7 +23525,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
@@ -23540,206 +23547,206 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
-	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
-	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
-	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
-	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	405},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_COMP_CTL"                ,	   0x11f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT2"             ,	   0x11f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT3"             ,	   0x11f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
+	{"PCI_CNT_REG"                 ,	   0x11f00000011b8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	405},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
 	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
 	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
 	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
-	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INSTR_COUNT3"            ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	411},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	412},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	412},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	413},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	415},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	415},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
 	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
@@ -23752,722 +23759,722 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
 	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
 	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
-	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
-	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	420},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	421},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	422},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	425},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	420},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	421},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	422},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	425},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	426},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	427},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	428},
 	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	429},
 	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	430},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_CRC_CTL0"                ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_CRC_CTL1"                ,	   0x11800a0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_CRC_IV0"                 ,	   0x11800a0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_CRC_IV1"                 ,	   0x11800a0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT4"              ,	   0x11800a0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT5"              ,	   0x11800a0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT6"              ,	   0x11800a00009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT7"              ,	   0x11800a0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT8"              ,	   0x11800a0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT9"              ,	   0x11800a0000ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT10"             ,	   0x11800a0000b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT11"             ,	   0x11800a0000b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT12"             ,	   0x11800a0000bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT13"             ,	   0x11800a0000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT14"             ,	   0x11800a0000c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT15"             ,	   0x11800a0000cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT20"             ,	   0x11800a0000e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT21"             ,	   0x11800a0000e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT22"             ,	   0x11800a0000ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT23"             ,	   0x11800a0000f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT24"             ,	   0x11800a0000f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT25"             ,	   0x11800a0000fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT26"             ,	   0x11800a0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT27"             ,	   0x11800a0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT28"             ,	   0x11800a00010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT29"             ,	   0x11800a0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT30"             ,	   0x11800a0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT31"             ,	   0x11800a00011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT4"              ,	   0x11800a0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT5"              ,	   0x11800a0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT6"              ,	   0x11800a00009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT7"              ,	   0x11800a0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT8"              ,	   0x11800a0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT9"              ,	   0x11800a0000ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT10"             ,	   0x11800a0000b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT11"             ,	   0x11800a0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT12"             ,	   0x11800a0000bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT13"             ,	   0x11800a0000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT14"             ,	   0x11800a0000c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT15"             ,	   0x11800a0000cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT20"             ,	   0x11800a0000e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT21"             ,	   0x11800a0000e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT22"             ,	   0x11800a0000ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT23"             ,	   0x11800a0000f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT24"             ,	   0x11800a0000f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT25"             ,	   0x11800a0000fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT26"             ,	   0x11800a0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT27"             ,	   0x11800a0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT28"             ,	   0x11800a00010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT29"             ,	   0x11800a0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT30"             ,	   0x11800a0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT31"             ,	   0x11800a00011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT4"              ,	   0x11800a0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT5"              ,	   0x11800a00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT6"              ,	   0x11800a00009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT7"              ,	   0x11800a0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT8"              ,	   0x11800a0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT9"              ,	   0x11800a0000ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT10"             ,	   0x11800a0000b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT11"             ,	   0x11800a0000b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT12"             ,	   0x11800a0000bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT13"             ,	   0x11800a0000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT14"             ,	   0x11800a0000c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT15"             ,	   0x11800a0000cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT20"             ,	   0x11800a0000e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT21"             ,	   0x11800a0000ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT22"             ,	   0x11800a0000ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT23"             ,	   0x11800a0000f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT24"             ,	   0x11800a0000f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT25"             ,	   0x11800a0000fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT26"             ,	   0x11800a0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT27"             ,	   0x11800a0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT28"             ,	   0x11800a00010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT29"             ,	   0x11800a0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT30"             ,	   0x11800a0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT31"             ,	   0x11800a00011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT4"              ,	   0x11800a0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT5"              ,	   0x11800a00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT6"              ,	   0x11800a00009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT7"              ,	   0x11800a0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT8"              ,	   0x11800a0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT9"              ,	   0x11800a0000ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT10"             ,	   0x11800a0000b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT11"             ,	   0x11800a0000b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT12"             ,	   0x11800a0000bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT13"             ,	   0x11800a0000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT14"             ,	   0x11800a0000c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT15"             ,	   0x11800a0000cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT20"             ,	   0x11800a0000e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT21"             ,	   0x11800a0000ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT22"             ,	   0x11800a0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT23"             ,	   0x11800a0000f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT24"             ,	   0x11800a0000f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT25"             ,	   0x11800a0000fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT26"             ,	   0x11800a0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT27"             ,	   0x11800a0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT28"             ,	   0x11800a00010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT29"             ,	   0x11800a0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT30"             ,	   0x11800a0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT31"             ,	   0x11800a00011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT4"              ,	   0x11800a0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT5"              ,	   0x11800a00009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT6"              ,	   0x11800a0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT7"              ,	   0x11800a0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT8"              ,	   0x11800a0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT9"              ,	   0x11800a0000af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT10"             ,	   0x11800a0000b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT11"             ,	   0x11800a0000b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT12"             ,	   0x11800a0000be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT13"             ,	   0x11800a0000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT14"             ,	   0x11800a0000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT15"             ,	   0x11800a0000cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT20"             ,	   0x11800a0000e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT21"             ,	   0x11800a0000eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT22"             ,	   0x11800a0000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT23"             ,	   0x11800a0000f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT24"             ,	   0x11800a0000fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT25"             ,	   0x11800a0000ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT26"             ,	   0x11800a0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT27"             ,	   0x11800a0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT28"             ,	   0x11800a00010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT29"             ,	   0x11800a0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT30"             ,	   0x11800a0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT31"             ,	   0x11800a00011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT4"              ,	   0x11800a0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT5"              ,	   0x11800a00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT6"              ,	   0x11800a0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT7"              ,	   0x11800a0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT8"              ,	   0x11800a0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT9"              ,	   0x11800a0000af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT10"             ,	   0x11800a0000b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT11"             ,	   0x11800a0000b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT12"             ,	   0x11800a0000be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT13"             ,	   0x11800a0000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT14"             ,	   0x11800a0000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT15"             ,	   0x11800a0000cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT20"             ,	   0x11800a0000e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT21"             ,	   0x11800a0000eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT22"             ,	   0x11800a0000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT23"             ,	   0x11800a0000f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT24"             ,	   0x11800a0000fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT25"             ,	   0x11800a0000ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT26"             ,	   0x11800a0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT27"             ,	   0x11800a0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT28"             ,	   0x11800a00010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT29"             ,	   0x11800a0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT30"             ,	   0x11800a0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT31"             ,	   0x11800a00011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT4"              ,	   0x11800a0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT5"              ,	   0x11800a00009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT6"              ,	   0x11800a0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT7"              ,	   0x11800a0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT8"              ,	   0x11800a0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT9"              ,	   0x11800a0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT10"             ,	   0x11800a0000b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT11"             ,	   0x11800a0000ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT12"             ,	   0x11800a0000bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT13"             ,	   0x11800a0000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT14"             ,	   0x11800a0000c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT15"             ,	   0x11800a0000ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT20"             ,	   0x11800a0000e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT21"             ,	   0x11800a0000ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT22"             ,	   0x11800a0000f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT23"             ,	   0x11800a0000f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT24"             ,	   0x11800a0000fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT25"             ,	   0x11800a0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT26"             ,	   0x11800a0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT27"             ,	   0x11800a00010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT28"             ,	   0x11800a00010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT29"             ,	   0x11800a0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT30"             ,	   0x11800a0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT31"             ,	   0x11800a00011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT4"              ,	   0x11800a0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT5"              ,	   0x11800a00009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT6"              ,	   0x11800a0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT7"              ,	   0x11800a0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT8"              ,	   0x11800a0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT9"              ,	   0x11800a0000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT10"             ,	   0x11800a0000b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT11"             ,	   0x11800a0000ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT12"             ,	   0x11800a0000bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT13"             ,	   0x11800a0000c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT14"             ,	   0x11800a0000c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT15"             ,	   0x11800a0000ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT20"             ,	   0x11800a0000e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT21"             ,	   0x11800a0000ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT22"             ,	   0x11800a0000f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT23"             ,	   0x11800a0000f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT24"             ,	   0x11800a0000fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT25"             ,	   0x11800a0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT26"             ,	   0x11800a0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT27"             ,	   0x11800a00010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT28"             ,	   0x11800a00010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT29"             ,	   0x11800a0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT30"             ,	   0x11800a0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT31"             ,	   0x11800a00011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT4"              ,	   0x11800a0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT5"              ,	   0x11800a00009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT6"              ,	   0x11800a0000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT7"              ,	   0x11800a0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT8"              ,	   0x11800a0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT9"              ,	   0x11800a0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT10"             ,	   0x11800a0000b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT11"             ,	   0x11800a0000bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT12"             ,	   0x11800a0000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT13"             ,	   0x11800a0000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT14"             ,	   0x11800a0000ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT15"             ,	   0x11800a0000cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT20"             ,	   0x11800a0000e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT21"             ,	   0x11800a0000ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT22"             ,	   0x11800a0000f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT23"             ,	   0x11800a0000f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT24"             ,	   0x11800a0000fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT25"             ,	   0x11800a0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT26"             ,	   0x11800a0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT27"             ,	   0x11800a00010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT28"             ,	   0x11800a0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT29"             ,	   0x11800a0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT30"             ,	   0x11800a00011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT31"             ,	   0x11800a00011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT4"              ,	   0x11800a0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT5"              ,	   0x11800a00009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT6"              ,	   0x11800a0000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT7"              ,	   0x11800a0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT8"              ,	   0x11800a0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT9"              ,	   0x11800a0000b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT10"             ,	   0x11800a0000b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT11"             ,	   0x11800a0000bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT12"             ,	   0x11800a0000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT13"             ,	   0x11800a0000c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT14"             ,	   0x11800a0000ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT15"             ,	   0x11800a0000cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT20"             ,	   0x11800a0000e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT21"             ,	   0x11800a0000ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT22"             ,	   0x11800a0000f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT23"             ,	   0x11800a0000f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT24"             ,	   0x11800a0000fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT25"             ,	   0x11800a0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT26"             ,	   0x11800a0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT27"             ,	   0x11800a00010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT28"             ,	   0x11800a0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT29"             ,	   0x11800a0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT30"             ,	   0x11800a00011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT31"             ,	   0x11800a00011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800a0001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800a0001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800a0001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800a0001af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800a0001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800a0001b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800a0001b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800a0001b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800a0001b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800a0001bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800a0001bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800a0001bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800a0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800a0001cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800a0001cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800a0001cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800a0001d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800a0001d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800a0001d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800a0001d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800a0001d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800a0001db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800a0001dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800a0001df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800a0001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800a0001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800a0001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800a0001ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800a0001b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800a0001b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800a0001b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800a0001b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800a0001b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800a0001ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800a0001bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800a0001be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800a0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800a0001ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800a0001cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800a0001ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800a0001d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800a0001d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800a0001d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800a0001d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800a0001d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800a0001da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800a0001dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800a0001de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800a0001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800a0001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800a0001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800a0001ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800a0001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800a0001b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800a0001b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800a0001b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800a0001b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800a0001ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800a0001bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800a0001be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800a0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800a0001ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800a0001cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800a0001ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800a0001d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800a0001d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800a0001d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800a0001d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800a0001d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800a0001da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800a0001dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800a0001de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
@@ -24494,9 +24501,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
 	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
 	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
 	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
@@ -24504,7 +24511,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	500},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	500},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	502},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
@@ -24536,22 +24543,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
 	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
 	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	512},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	513},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
@@ -24584,34 +24591,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
@@ -24621,8 +24628,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
 	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
 	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
-	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
-	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
 	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
 	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
 	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
@@ -24675,18 +24682,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
@@ -24707,18 +24714,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
-	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
 	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
 	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
@@ -24735,12 +24742,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
 	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
 	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
-	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
-	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"STX0_INT_MSK"                ,	   0x11800900006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"STX1_INT_MSK"                ,	   0x11800980006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
 	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
-	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"STX0_INT_SYNC"               ,	   0x11800900006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"STX1_INT_SYNC"               ,	   0x11800980006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
 	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
 	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
 	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
@@ -24763,18 +24770,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
@@ -24795,18 +24802,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
-	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
 	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
 	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
@@ -24829,31 +24836,31 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
@@ -25903,7 +25910,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"Q3FUS"                       ,	0,	34,	248,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_1024K"                  ,	34,	1,	248,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	35,	1,	248,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	248,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	248,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	2,	248,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_39_63"              ,	39,	25,	248,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
@@ -25965,7 +25972,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"INORDER_MWF"                 ,	13,	1,	264,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	264,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	264,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	264,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
@@ -27255,9 +27262,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"BACK"                        ,	59,	4,	469,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	469,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	470,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	470,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	470,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	470,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	471,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	471,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	471,	"RO",	1,	0,	0,	0ull},
@@ -27265,7 +27272,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"SOP"                         ,	18,	1,	471,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	471,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	471,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	471,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	0,	16,	472,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	472,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	472,	"RO",	1,	0,	0,	0ull},
@@ -27304,7 +27311,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"CURR_SIZ"                    ,	19,	16,	477,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	35,	29,	477,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	0,	11,	478,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	478,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	479,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	479,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	479,	"RO",	1,	0,	0,	0ull},
@@ -27315,13 +27322,13 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"STATIC_Q"                    ,	3,	1,	480,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	480,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	480,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	480,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	480,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	480,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	481,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	481,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	481,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	481,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	482,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	482,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	482,	"WR0",	1,	0,	0,	0ull},
@@ -27333,9 +27340,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"S_TAIL"                      ,	63,	1,	482,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	483,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	483,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	483,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	483,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	483,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	484,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	4,	484,	"RO",	1,	0,	0,	0ull},
 	{"PRT_QSB"                     ,	8,	3,	484,	"RO",	1,	0,	0,	0ull},
@@ -27350,16 +27357,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"OUT_CRC"                     ,	30,	1,	484,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	31,	1,	484,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	32,	1,	484,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_33_63"              ,	33,	31,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	484,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	485,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	485,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	485,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	485,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	485,	"RAZ",	1,	1,	0,	0},
 	{"REFIN"                       ,	0,	1,	486,	"R/W",	0,	0,	1ull,	1ull},
 	{"INVRES"                      ,	1,	1,	486,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_2_63"               ,	2,	62,	486,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE"                      ,	0,	32,	487,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	1,	1,	0,	0},
 	{"IV"                          ,	0,	32,	488,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
 	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	489,	"RO",	0,	0,	0ull,	0ull},
@@ -27369,27 +27376,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"PARITY"                      ,	0,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	493,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	494,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	494,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	494,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	495,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	495,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	496,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	497,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	497,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	498,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	498,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	499,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	499,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	499,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	500,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	500,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	500,	"RO",	0,	0,	0ull,	0ull},
@@ -27724,11 +27731,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"CNT"                         ,	0,	32,	564,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_32_63"              ,	32,	32,	564,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	0,	22,	565,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	565,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	565,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	565,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	565,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	565,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	566,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	566,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	566,	"RO",	1,	0,	0,	0ull},
@@ -27736,32 +27743,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"RESERVED_7_7"                ,	7,	1,	567,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	567,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	567,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	567,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	567,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	568,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	568,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	568,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	568,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	568,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	569,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	569,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	569,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	569,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	569,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	569,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	570,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	570,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	570,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	570,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	570,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	571,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	571,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	571,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	572,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	572,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	572,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	573,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	573,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	573,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	574,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	574,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	574,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	574,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	575,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	575,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	575,	"RO",	0,	0,	0ull,	0ull},
@@ -27782,9 +27789,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"RPTR"                        ,	8,	8,	577,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	577,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	578,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	578,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	578,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	578,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	578,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	579,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	579,	"RAZ",	0,	0,	0ull,	0ull},
@@ -27914,27 +27921,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
 	{"RESERVED_20_63"              ,	20,	44,	595,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	596,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	596,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	596,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	596,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	597,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	597,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	597,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	597,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	597,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	597,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	598,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	598,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	598,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	599,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	599,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	599,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	599,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	599,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	599,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	599,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	599,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	600,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	600,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	600,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	601,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	601,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	601,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	602,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	602,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
@@ -28556,62 +28563,62 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800b8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800b8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800b8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800b0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800b8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800b0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800b8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800b0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800b8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800b0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800b8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800b0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800b8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800b0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800b8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800b0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800b8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800b0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800b8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_SETTING"            ,	   0x11800b0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_SETTING"            ,	   0x11800b8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800b0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800b8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800b8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800b8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800b8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800b8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800b0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800b8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800b8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800b8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800b8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800b8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800b0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800b8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800b8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800b8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800b8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800b8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800b0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800b0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
@@ -28626,12 +28633,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
@@ -28642,12 +28649,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
-	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT26_EN0"               ,	   0x10700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT27_EN0"               ,	   0x10700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT28_EN0"               ,	   0x10700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT29_EN0"               ,	   0x10700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT30_EN0"               ,	   0x10700000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT31_EN0"               ,	   0x10700000003f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
 	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
@@ -28659,12 +28666,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT16_EN0_W1C"           ,	   0x1070000002300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT17_EN0_W1C"           ,	   0x1070000002310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT18_EN0_W1C"           ,	   0x1070000002320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
@@ -28675,12 +28682,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN0_W1C"           ,	   0x1070000002370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT24_EN0_W1C"           ,	   0x1070000002380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT25_EN0_W1C"           ,	   0x1070000002390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT26_EN0_W1C"           ,	   0x10700000023A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT27_EN0_W1C"           ,	   0x10700000023B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT28_EN0_W1C"           ,	   0x10700000023C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT29_EN0_W1C"           ,	   0x10700000023D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT30_EN0_W1C"           ,	   0x10700000023E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
-	{"CIU_INT31_EN0_W1C"           ,	   0x10700000023F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT26_EN0_W1C"           ,	   0x10700000023a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT27_EN0_W1C"           ,	   0x10700000023b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT28_EN0_W1C"           ,	   0x10700000023c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT29_EN0_W1C"           ,	   0x10700000023d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT30_EN0_W1C"           ,	   0x10700000023e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT31_EN0_W1C"           ,	   0x10700000023f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
 	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
@@ -28692,12 +28699,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT16_EN0_W1S"           ,	   0x1070000006300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT17_EN0_W1S"           ,	   0x1070000006310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT18_EN0_W1S"           ,	   0x1070000006320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
@@ -28708,12 +28715,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN0_W1S"           ,	   0x1070000006370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT24_EN0_W1S"           ,	   0x1070000006380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT25_EN0_W1S"           ,	   0x1070000006390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT26_EN0_W1S"           ,	   0x10700000063A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT27_EN0_W1S"           ,	   0x10700000063B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT28_EN0_W1S"           ,	   0x10700000063C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT29_EN0_W1S"           ,	   0x10700000063D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT30_EN0_W1S"           ,	   0x10700000063E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
-	{"CIU_INT31_EN0_W1S"           ,	   0x10700000063F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT26_EN0_W1S"           ,	   0x10700000063a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT27_EN0_W1S"           ,	   0x10700000063b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT28_EN0_W1S"           ,	   0x10700000063c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT29_EN0_W1S"           ,	   0x10700000063d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT30_EN0_W1S"           ,	   0x10700000063e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT31_EN0_W1S"           ,	   0x10700000063f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
 	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
@@ -28725,12 +28732,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
@@ -28741,12 +28748,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
-	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT26_EN1"               ,	   0x10700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT27_EN1"               ,	   0x10700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT28_EN1"               ,	   0x10700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT29_EN1"               ,	   0x10700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT30_EN1"               ,	   0x10700000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT31_EN1"               ,	   0x10700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
 	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
@@ -28758,12 +28765,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT16_EN1_W1C"           ,	   0x1070000002308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT17_EN1_W1C"           ,	   0x1070000002318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT18_EN1_W1C"           ,	   0x1070000002328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
@@ -28774,12 +28781,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN1_W1C"           ,	   0x1070000002378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT24_EN1_W1C"           ,	   0x1070000002388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT25_EN1_W1C"           ,	   0x1070000002398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT26_EN1_W1C"           ,	   0x10700000023A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT27_EN1_W1C"           ,	   0x10700000023B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT28_EN1_W1C"           ,	   0x10700000023C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT29_EN1_W1C"           ,	   0x10700000023D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT30_EN1_W1C"           ,	   0x10700000023E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
-	{"CIU_INT31_EN1_W1C"           ,	   0x10700000023F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT26_EN1_W1C"           ,	   0x10700000023a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT27_EN1_W1C"           ,	   0x10700000023b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT28_EN1_W1C"           ,	   0x10700000023c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT29_EN1_W1C"           ,	   0x10700000023d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT30_EN1_W1C"           ,	   0x10700000023e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT31_EN1_W1C"           ,	   0x10700000023f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
 	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
@@ -28791,12 +28798,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT16_EN1_W1S"           ,	   0x1070000006308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT17_EN1_W1S"           ,	   0x1070000006318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT18_EN1_W1S"           ,	   0x1070000006328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
@@ -28807,109 +28814,109 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT23_EN1_W1S"           ,	   0x1070000006378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT24_EN1_W1S"           ,	   0x1070000006388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT25_EN1_W1S"           ,	   0x1070000006398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT26_EN1_W1S"           ,	   0x10700000063A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT27_EN1_W1S"           ,	   0x10700000063B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT28_EN1_W1S"           ,	   0x10700000063C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT29_EN1_W1S"           ,	   0x10700000063D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT30_EN1_W1S"           ,	   0x10700000063E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT31_EN1_W1S"           ,	   0x10700000063F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN1_W1S"           ,	   0x10700000063a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN1_W1S"           ,	   0x10700000063b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN1_W1S"           ,	   0x10700000063c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN1_W1S"           ,	   0x10700000063d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN1_W1S"           ,	   0x10700000063e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN1_W1S"           ,	   0x10700000063f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
 	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT12_EN4_0"             ,	   0x1070000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT13_EN4_0"             ,	   0x1070000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT14_EN4_0"             ,	   0x1070000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT15_EN4_0"             ,	   0x1070000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
-	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT12_EN4_0_W1C"         ,	   0x1070000002D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT13_EN4_0_W1C"         ,	   0x1070000002D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT14_EN4_0_W1C"         ,	   0x1070000002D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT15_EN4_0_W1C"         ,	   0x1070000002D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
-	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT12_EN4_0_W1S"         ,	   0x1070000006D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT13_EN4_0_W1S"         ,	   0x1070000006D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT14_EN4_0_W1S"         ,	   0x1070000006D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT15_EN4_0_W1S"         ,	   0x1070000006D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT12_EN4_1"             ,	   0x1070000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT13_EN4_1"             ,	   0x1070000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT14_EN4_1"             ,	   0x1070000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT15_EN4_1"             ,	   0x1070000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
-	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT12_EN4_1_W1C"         ,	   0x1070000002D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT13_EN4_1_W1C"         ,	   0x1070000002D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT14_EN4_1_W1C"         ,	   0x1070000002D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT15_EN4_1_W1C"         ,	   0x1070000002D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT12_EN4_1_W1S"         ,	   0x1070000006D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT13_EN4_1_W1S"         ,	   0x1070000006D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT14_EN4_1_W1S"         ,	   0x1070000006D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"CIU_INT15_EN4_1_W1S"         ,	   0x1070000006D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN4_0"             ,	   0x1070000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN4_0"             ,	   0x1070000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN4_0"             ,	   0x1070000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN4_0"             ,	   0x1070000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT12_EN4_0_W1C"         ,	   0x1070000002d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT13_EN4_0_W1C"         ,	   0x1070000002d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT14_EN4_0_W1C"         ,	   0x1070000002d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT15_EN4_0_W1C"         ,	   0x1070000002d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT12_EN4_0_W1S"         ,	   0x1070000006d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT13_EN4_0_W1S"         ,	   0x1070000006d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT14_EN4_0_W1S"         ,	   0x1070000006d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT15_EN4_0_W1S"         ,	   0x1070000006d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT12_EN4_1"             ,	   0x1070000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT13_EN4_1"             ,	   0x1070000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT14_EN4_1"             ,	   0x1070000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT15_EN4_1"             ,	   0x1070000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT12_EN4_1_W1C"         ,	   0x1070000002d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT13_EN4_1_W1C"         ,	   0x1070000002d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT14_EN4_1_W1C"         ,	   0x1070000002d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT15_EN4_1_W1C"         ,	   0x1070000002d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT12_EN4_1_W1S"         ,	   0x1070000006d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT13_EN4_1_W1S"         ,	   0x1070000006d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT14_EN4_1_W1S"         ,	   0x1070000006d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT15_EN4_1_W1S"         ,	   0x1070000006d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
@@ -28930,52 +28937,52 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT12_SUM4"              ,	   0x1070000000C60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT13_SUM4"              ,	   0x1070000000C68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT14_SUM4"              ,	   0x1070000000C70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
-	{"CIU_INT15_SUM4"              ,	   0x1070000000C78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT12_SUM4"              ,	   0x1070000000c60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT13_SUM4"              ,	   0x1070000000c68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT14_SUM4"              ,	   0x1070000000c70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT15_SUM4"              ,	   0x1070000000c78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
-	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
@@ -28999,18 +29006,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
-	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE12"               ,	   0x10700000005e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE13"               ,	   0x10700000005e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE14"               ,	   0x10700000005f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE15"               ,	   0x10700000005f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
 	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	46},
 	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	47},
@@ -29035,9 +29042,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
 	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
 	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
-	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"DFA_BST0"                    ,	   0x11800300007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_BST1"                    ,	   0x11800300007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
 	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
 	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
@@ -29055,7 +29062,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
 	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
 	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
@@ -29076,15 +29083,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
@@ -29093,14 +29100,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
@@ -29143,22 +29150,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
@@ -29287,22 +29294,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
@@ -29311,14 +29318,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
@@ -29327,22 +29334,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
@@ -29375,8 +29382,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
@@ -29409,210 +29416,210 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
-	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
@@ -29621,38 +29628,38 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX_SPI_ROUND000"        ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND001"        ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND002"        ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND003"        ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND016"        ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND017"        ,	   0x1180008000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX_SPI_ROUND018"        ,	   0x1180008000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
@@ -29673,18 +29680,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_TX_SPI_ROUND001"        ,	   0x1180010000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND002"        ,	   0x1180010000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND003"        ,	   0x1180010000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND016"        ,	   0x1180010000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND017"        ,	   0x1180010000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND018"        ,	   0x1180010000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
@@ -29701,8 +29708,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GMX1_TX_SPI_ROUND029"        ,	   0x1180010000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND030"        ,	   0x1180010000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX_SPI_ROUND031"        ,	   0x1180010000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
 	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
@@ -29723,145 +29730,145 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14f0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14f0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14f0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14f0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14f0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14f0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14f0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14f0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14f0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14f0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14f0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14f0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14f00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14f00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14f00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
@@ -29870,11 +29877,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
@@ -29889,35 +29896,35 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
@@ -29932,17 +29939,17 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
@@ -29963,7 +29970,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
@@ -29986,206 +29993,206 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
-	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	365},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
-	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
-	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	404},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	405},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	406},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	407},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	408},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	409},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	410},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	411},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	412},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	413},
-	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	415},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11f00000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11f00000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11f00000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11f00000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_COMP_CTL"                ,	   0x11f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	365},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11f0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11f0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11f00000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11f0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11f0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT2"             ,	   0x11f0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT3"             ,	   0x11f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	404},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	405},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	406},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	407},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	408},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	409},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	410},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	411},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	412},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	413},
+	{"PCI_CNT_REG"                 ,	   0x11f00000011b8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	415},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
 	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
 	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
 	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
-	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INSTR_COUNT3"            ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	421},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	422},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	422},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	423},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	425},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	425},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
 	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
@@ -30198,722 +30205,722 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
 	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
 	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
-	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
-	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	430},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	431},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	432},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	433},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	434},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	435},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	430},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	431},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	432},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	433},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	434},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	435},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	436},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	437},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	438},
 	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	439},
 	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	440},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
-	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
-	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_CRC_CTL0"                ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_CRC_CTL1"                ,	   0x11800a0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_CRC_IV0"                 ,	   0x11800a0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_CRC_IV1"                 ,	   0x11800a0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG4"                ,	   0x11800a0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG5"                ,	   0x11800a0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG6"                ,	   0x11800a0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG7"                ,	   0x11800a0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG8"                ,	   0x11800a0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG9"                ,	   0x11800a0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG10"               ,	   0x11800a0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG11"               ,	   0x11800a0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG12"               ,	   0x11800a0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG13"               ,	   0x11800a0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG14"               ,	   0x11800a0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG15"               ,	   0x11800a0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG20"               ,	   0x11800a00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG21"               ,	   0x11800a00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG22"               ,	   0x11800a00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG23"               ,	   0x11800a00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG24"               ,	   0x11800a00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG25"               ,	   0x11800a00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG26"               ,	   0x11800a00002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG27"               ,	   0x11800a00002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG28"               ,	   0x11800a00002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG29"               ,	   0x11800a00002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG30"               ,	   0x11800a00002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG31"               ,	   0x11800a00002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG4"                ,	   0x11800a0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG5"                ,	   0x11800a0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG6"                ,	   0x11800a0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG7"                ,	   0x11800a0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG8"                ,	   0x11800a0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG9"                ,	   0x11800a0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG10"               ,	   0x11800a0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG11"               ,	   0x11800a0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG12"               ,	   0x11800a0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG13"               ,	   0x11800a0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG14"               ,	   0x11800a0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG15"               ,	   0x11800a0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG20"               ,	   0x11800a00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG21"               ,	   0x11800a00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG22"               ,	   0x11800a00004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG23"               ,	   0x11800a00004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG24"               ,	   0x11800a00004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG25"               ,	   0x11800a00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG26"               ,	   0x11800a00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG27"               ,	   0x11800a00004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG28"               ,	   0x11800a00004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG29"               ,	   0x11800a00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG30"               ,	   0x11800a00004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG31"               ,	   0x11800a00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT4"              ,	   0x11800a0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT5"              ,	   0x11800a0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT6"              ,	   0x11800a00009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT7"              ,	   0x11800a0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT8"              ,	   0x11800a0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT9"              ,	   0x11800a0000ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT10"             ,	   0x11800a0000b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT11"             ,	   0x11800a0000b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT12"             ,	   0x11800a0000bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT13"             ,	   0x11800a0000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT14"             ,	   0x11800a0000c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT15"             ,	   0x11800a0000cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT20"             ,	   0x11800a0000e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT21"             ,	   0x11800a0000e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT22"             ,	   0x11800a0000ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT23"             ,	   0x11800a0000f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT24"             ,	   0x11800a0000f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT25"             ,	   0x11800a0000fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT26"             ,	   0x11800a0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT27"             ,	   0x11800a0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT28"             ,	   0x11800a00010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT29"             ,	   0x11800a0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT30"             ,	   0x11800a0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT31"             ,	   0x11800a00011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT4"              ,	   0x11800a0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT5"              ,	   0x11800a0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT6"              ,	   0x11800a00009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT7"              ,	   0x11800a0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT8"              ,	   0x11800a0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT9"              ,	   0x11800a0000ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT10"             ,	   0x11800a0000b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT11"             ,	   0x11800a0000b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT12"             ,	   0x11800a0000bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT13"             ,	   0x11800a0000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT14"             ,	   0x11800a0000c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT15"             ,	   0x11800a0000cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT20"             ,	   0x11800a0000e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT21"             ,	   0x11800a0000e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT22"             ,	   0x11800a0000ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT23"             ,	   0x11800a0000f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT24"             ,	   0x11800a0000f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT25"             ,	   0x11800a0000fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT26"             ,	   0x11800a0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT27"             ,	   0x11800a0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT28"             ,	   0x11800a00010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT29"             ,	   0x11800a0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT30"             ,	   0x11800a0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT31"             ,	   0x11800a00011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT4"              ,	   0x11800a0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT5"              ,	   0x11800a00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT6"              ,	   0x11800a00009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT7"              ,	   0x11800a0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT8"              ,	   0x11800a0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT9"              ,	   0x11800a0000ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT10"             ,	   0x11800a0000b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT11"             ,	   0x11800a0000b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT12"             ,	   0x11800a0000bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT13"             ,	   0x11800a0000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT14"             ,	   0x11800a0000c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT15"             ,	   0x11800a0000cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT20"             ,	   0x11800a0000e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT21"             ,	   0x11800a0000ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT22"             ,	   0x11800a0000ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT23"             ,	   0x11800a0000f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT24"             ,	   0x11800a0000f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT25"             ,	   0x11800a0000fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT26"             ,	   0x11800a0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT27"             ,	   0x11800a0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT28"             ,	   0x11800a00010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT29"             ,	   0x11800a0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT30"             ,	   0x11800a0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT31"             ,	   0x11800a00011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT4"              ,	   0x11800a0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT5"              ,	   0x11800a00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT6"              ,	   0x11800a00009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT7"              ,	   0x11800a0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT8"              ,	   0x11800a0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT9"              ,	   0x11800a0000ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT10"             ,	   0x11800a0000b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT11"             ,	   0x11800a0000b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT12"             ,	   0x11800a0000bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT13"             ,	   0x11800a0000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT14"             ,	   0x11800a0000c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT15"             ,	   0x11800a0000cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT20"             ,	   0x11800a0000e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT21"             ,	   0x11800a0000ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT22"             ,	   0x11800a0000ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT23"             ,	   0x11800a0000f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT24"             ,	   0x11800a0000f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT25"             ,	   0x11800a0000fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT26"             ,	   0x11800a0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT27"             ,	   0x11800a0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT28"             ,	   0x11800a00010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT29"             ,	   0x11800a0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT30"             ,	   0x11800a0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT31"             ,	   0x11800a00011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT4"              ,	   0x11800a0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT5"              ,	   0x11800a00009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT6"              ,	   0x11800a0000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT7"              ,	   0x11800a0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT8"              ,	   0x11800a0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT9"              ,	   0x11800a0000af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT10"             ,	   0x11800a0000b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT11"             ,	   0x11800a0000b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT12"             ,	   0x11800a0000be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT13"             ,	   0x11800a0000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT14"             ,	   0x11800a0000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT15"             ,	   0x11800a0000cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT20"             ,	   0x11800a0000e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT21"             ,	   0x11800a0000eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT22"             ,	   0x11800a0000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT23"             ,	   0x11800a0000f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT24"             ,	   0x11800a0000fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT25"             ,	   0x11800a0000ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT26"             ,	   0x11800a0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT27"             ,	   0x11800a0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT28"             ,	   0x11800a00010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT29"             ,	   0x11800a0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT30"             ,	   0x11800a0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT31"             ,	   0x11800a00011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT4"              ,	   0x11800a0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT5"              ,	   0x11800a00009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT6"              ,	   0x11800a0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT7"              ,	   0x11800a0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT8"              ,	   0x11800a0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT9"              ,	   0x11800a0000af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT10"             ,	   0x11800a0000b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT11"             ,	   0x11800a0000b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT12"             ,	   0x11800a0000be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT13"             ,	   0x11800a0000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT14"             ,	   0x11800a0000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT15"             ,	   0x11800a0000cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT20"             ,	   0x11800a0000e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT21"             ,	   0x11800a0000eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT22"             ,	   0x11800a0000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT23"             ,	   0x11800a0000f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT24"             ,	   0x11800a0000fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT25"             ,	   0x11800a0000ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT26"             ,	   0x11800a0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT27"             ,	   0x11800a0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT28"             ,	   0x11800a00010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT29"             ,	   0x11800a0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT30"             ,	   0x11800a0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT31"             ,	   0x11800a00011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT4"              ,	   0x11800a0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT5"              ,	   0x11800a00009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT6"              ,	   0x11800a0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT7"              ,	   0x11800a0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT8"              ,	   0x11800a0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT9"              ,	   0x11800a0000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT10"             ,	   0x11800a0000b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT11"             ,	   0x11800a0000ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT12"             ,	   0x11800a0000bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT13"             ,	   0x11800a0000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT14"             ,	   0x11800a0000c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT15"             ,	   0x11800a0000ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT20"             ,	   0x11800a0000e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT21"             ,	   0x11800a0000ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT22"             ,	   0x11800a0000f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT23"             ,	   0x11800a0000f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT24"             ,	   0x11800a0000fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT25"             ,	   0x11800a0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT26"             ,	   0x11800a0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT27"             ,	   0x11800a00010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT28"             ,	   0x11800a00010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT29"             ,	   0x11800a0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT30"             ,	   0x11800a0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT31"             ,	   0x11800a00011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT4"              ,	   0x11800a0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT5"              ,	   0x11800a00009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT6"              ,	   0x11800a0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT7"              ,	   0x11800a0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT8"              ,	   0x11800a0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT9"              ,	   0x11800a0000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT10"             ,	   0x11800a0000b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT11"             ,	   0x11800a0000ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT12"             ,	   0x11800a0000bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT13"             ,	   0x11800a0000c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT14"             ,	   0x11800a0000c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT15"             ,	   0x11800a0000ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT20"             ,	   0x11800a0000e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT21"             ,	   0x11800a0000ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT22"             ,	   0x11800a0000f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT23"             ,	   0x11800a0000f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT24"             ,	   0x11800a0000fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT25"             ,	   0x11800a0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT26"             ,	   0x11800a0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT27"             ,	   0x11800a00010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT28"             ,	   0x11800a00010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT29"             ,	   0x11800a0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT30"             ,	   0x11800a0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT31"             ,	   0x11800a00011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT4"              ,	   0x11800a0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT5"              ,	   0x11800a00009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT6"              ,	   0x11800a0000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT7"              ,	   0x11800a0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT8"              ,	   0x11800a0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT9"              ,	   0x11800a0000b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT10"             ,	   0x11800a0000b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT11"             ,	   0x11800a0000bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT12"             ,	   0x11800a0000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT13"             ,	   0x11800a0000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT14"             ,	   0x11800a0000ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT15"             ,	   0x11800a0000cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT20"             ,	   0x11800a0000e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT21"             ,	   0x11800a0000ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT22"             ,	   0x11800a0000f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT23"             ,	   0x11800a0000f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT24"             ,	   0x11800a0000fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT25"             ,	   0x11800a0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT26"             ,	   0x11800a0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT27"             ,	   0x11800a00010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT28"             ,	   0x11800a0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT29"             ,	   0x11800a0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT30"             ,	   0x11800a00011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT31"             ,	   0x11800a00011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT4"              ,	   0x11800a0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT5"              ,	   0x11800a00009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT6"              ,	   0x11800a0000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT7"              ,	   0x11800a0000a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT8"              ,	   0x11800a0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT9"              ,	   0x11800a0000b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT10"             ,	   0x11800a0000b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT11"             ,	   0x11800a0000bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT12"             ,	   0x11800a0000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT13"             ,	   0x11800a0000c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT14"             ,	   0x11800a0000ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT15"             ,	   0x11800a0000cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT20"             ,	   0x11800a0000e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT21"             ,	   0x11800a0000ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT22"             ,	   0x11800a0000f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT23"             ,	   0x11800a0000f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT24"             ,	   0x11800a0000fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT25"             ,	   0x11800a0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT26"             ,	   0x11800a0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT27"             ,	   0x11800a00010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT28"             ,	   0x11800a0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT29"             ,	   0x11800a0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT30"             ,	   0x11800a00011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT31"             ,	   0x11800a00011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800a0001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800a0001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800a0001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800a0001af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800a0001b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800a0001b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800a0001b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800a0001b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800a0001b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800a0001bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800a0001bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800a0001bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800a0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800a0001cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800a0001cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800a0001cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800a0001d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800a0001d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800a0001d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800a0001d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800a0001d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800a0001db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800a0001dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800a0001df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800a0001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800a0001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800a0001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800a0001ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800a0001b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800a0001b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800a0001b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800a0001b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800a0001b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800a0001ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800a0001bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800a0001be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800a0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800a0001ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800a0001cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800a0001ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800a0001d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800a0001d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800a0001d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800a0001d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800a0001d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800a0001da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800a0001dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800a0001de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800a0001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800a0001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800a0001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800a0001ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800a0001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800a0001b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800a0001b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800a0001b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800a0001b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800a0001ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800a0001bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800a0001be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800a0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800a0001ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800a0001cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800a0001ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800a0001d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800a0001d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800a0001d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800a0001d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800a0001d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800a0001da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800a0001dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800a0001de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
@@ -30940,9 +30947,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
 	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
 	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
 	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
@@ -30950,7 +30957,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	512},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	513},
@@ -30982,22 +30989,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
 	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	522},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	523},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
@@ -31030,34 +31037,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
@@ -31067,8 +31074,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
 	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
 	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
-	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
-	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
 	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
 	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
 	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
@@ -31121,18 +31128,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
@@ -31153,18 +31160,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
-	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
 	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
 	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
 	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
@@ -31181,12 +31188,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
 	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
 	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
-	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
-	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"STX0_INT_MSK"                ,	   0x11800900006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"STX1_INT_MSK"                ,	   0x11800980006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
 	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
 	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
-	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
-	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"STX0_INT_SYNC"               ,	   0x11800900006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"STX1_INT_SYNC"               ,	   0x11800980006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
 	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
 	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
 	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
@@ -31209,18 +31216,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
@@ -31241,18 +31248,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
-	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
 	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
 	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
 	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
@@ -31275,31 +31282,31 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	612},
@@ -32422,7 +32429,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"Q3FUS"                       ,	0,	34,	256,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_1024K"                  ,	34,	1,	256,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	35,	1,	256,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	256,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	2,	256,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_39_63"              ,	39,	25,	256,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
@@ -32484,7 +32491,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"INORDER_MWF"                 ,	13,	1,	272,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	272,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	272,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	272,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
@@ -33784,9 +33791,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"BACK"                        ,	59,	4,	479,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	479,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	480,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	480,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	480,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	480,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	481,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	481,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	481,	"RO",	1,	0,	0,	0ull},
@@ -33794,7 +33801,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"SOP"                         ,	18,	1,	481,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	481,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	481,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	481,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	0,	16,	482,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	482,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	482,	"RO",	1,	0,	0,	0ull},
@@ -33833,7 +33840,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"CURR_SIZ"                    ,	19,	16,	487,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	35,	29,	487,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	0,	11,	488,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	488,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	488,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	489,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	489,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	489,	"RO",	1,	0,	0,	0ull},
@@ -33844,13 +33851,13 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"STATIC_Q"                    ,	3,	1,	490,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	490,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	490,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	490,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	490,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	490,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	490,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	490,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	491,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	491,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	491,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	491,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	491,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	491,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	492,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	492,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	492,	"WR0",	1,	0,	0,	0ull},
@@ -33862,9 +33869,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"S_TAIL"                      ,	63,	1,	492,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	493,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	493,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	493,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	493,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	493,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	494,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	4,	494,	"RO",	1,	0,	0,	0ull},
 	{"PRT_QSB"                     ,	8,	3,	494,	"RO",	1,	0,	0,	0ull},
@@ -33879,16 +33886,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"OUT_CRC"                     ,	30,	1,	494,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	31,	1,	494,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	32,	1,	494,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_33_63"              ,	33,	31,	494,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	494,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	495,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	495,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	495,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	495,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	495,	"RAZ",	1,	1,	0,	0},
 	{"REFIN"                       ,	0,	1,	496,	"R/W",	0,	0,	1ull,	1ull},
 	{"INVRES"                      ,	1,	1,	496,	"R/W",	0,	0,	1ull,	1ull},
 	{"RESERVED_2_63"               ,	2,	62,	496,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE"                      ,	0,	32,	497,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	497,	"RAZ",	1,	1,	0,	0},
 	{"IV"                          ,	0,	32,	498,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
 	{"RESERVED_32_63"              ,	32,	32,	498,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	499,	"RO",	0,	0,	0ull,	0ull},
@@ -33898,27 +33905,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"PARITY"                      ,	0,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	504,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	504,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	505,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	505,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	505,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	506,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	506,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	507,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	507,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	507,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	508,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	508,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	509,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	509,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	509,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	509,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	510,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	510,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	510,	"RO",	0,	0,	0ull,	0ull},
@@ -34253,11 +34260,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"CNT"                         ,	0,	32,	574,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_32_63"              ,	32,	32,	574,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	0,	22,	575,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	575,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	575,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	575,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	575,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	575,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	575,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	575,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	575,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	576,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	576,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	576,	"RO",	1,	0,	0,	0ull},
@@ -34265,32 +34272,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	577,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	577,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	577,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	577,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	577,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	578,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	578,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	578,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	578,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	578,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	579,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	579,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	579,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	579,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	579,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	579,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	580,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	580,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	580,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	580,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	580,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	581,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	581,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	581,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	582,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	582,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	582,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	583,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	583,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	583,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	584,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	584,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	584,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	584,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	585,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	585,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	585,	"RO",	0,	0,	0ull,	0ull},
@@ -34311,9 +34318,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"RPTR"                        ,	8,	8,	587,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	587,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	588,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	588,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	588,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	588,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	588,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	588,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	588,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	589,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	589,	"RAZ",	0,	0,	0ull,	0ull},
@@ -34443,27 +34450,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
 	{"RESERVED_20_63"              ,	20,	44,	605,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	606,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	606,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	606,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	606,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	607,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	607,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	607,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	607,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	607,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	607,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	608,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	608,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	608,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	609,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	609,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	609,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	609,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	609,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	609,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	609,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	609,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	610,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	610,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	610,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	611,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	611,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	611,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	612,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	612,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
@@ -34931,83 +34938,83 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
 	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1364,	1,	2288},
 	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1365,	2,	2289},
 	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1366,	2,	2291},
-	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1367,	2,	2293},
-	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1368,	24,	2295},
-	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1369,	4,	2319},
-	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1370,	5,	2323},
-	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1371,	5,	2328},
-	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1372,	2,	2333},
-	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1373,	1,	2335},
-	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1374,	1,	2336},
-	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1375,	5,	2337},
-	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1376,	2,	2342},
-	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1377,	1,	2344},
-	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1378,	1,	2345},
-	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1379,	4,	2346},
-	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1380,	2,	2350},
-	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1381,	2,	2352},
-	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1382,	1,	2354},
-	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1383,	1,	2355},
-	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1384,	2,	2356},
-	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1385,	3,	2358},
-	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1386,	2,	2361},
-	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1387,	2,	2363},
-	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1388,	4,	2365},
-	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1389,	10,	2369},
-	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1390,	12,	2379},
-	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1391,	7,	2391},
-	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1392,	2,	2398},
-	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1393,	1,	2400},
-	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1394,	2,	2401},
-	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1395,	7,	2403},
-	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1396,	11,	2410},
-	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1397,	19,	2421},
-	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1398,	11,	2440},
-	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1399,	17,	2451},
-	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1400,	12,	2468},
-	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1401,	22,	2480},
-	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1402,	3,	2502},
-	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1403,	3,	2505},
-	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1404,	1,	2508},
-	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1405,	1,	2509},
-	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1406,	1,	2510},
-	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1407,	1,	2511},
-	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1408,	3,	2512},
-	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1409,	14,	2515},
-	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1410,	14,	2529},
-	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1411,	14,	2543},
-	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1412,	9,	2557},
-	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1413,	9,	2566},
-	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1414,	6,	2575},
-	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1415,	1,	2581},
-	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1416,	1,	2582},
-	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1417,	1,	2583},
-	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1418,	1,	2584},
-	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1419,	2,	2585},
-	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1420,	1,	2587},
-	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1421,	6,	2588},
-	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1422,	6,	2594},
-	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1423,	13,	2600},
-	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1424,	5,	2613},
-	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1425,	8,	2618},
-	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1426,	19,	2626},
-	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1427,	3,	2645},
-	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1428,	1,	2648},
-	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1429,	1,	2649},
-	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1430,	3,	2650},
-	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1431,	3,	2653},
-	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1432,	3,	2656},
-	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1433,	4,	2659},
-	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1434,	4,	2663},
-	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1435,	4,	2667},
-	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1436,	7,	2671},
-	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1437,	5,	2678},
-	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1438,	5,	2683},
-	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1439,	4,	2688},
-	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1440,	4,	2692},
-	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1441,	4,	2696},
-	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1442,	1,	2700},
-	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1443,	1,	2701},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1367,	2,	2293},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1368,	24,	2295},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1369,	4,	2319},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1370,	5,	2323},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1371,	5,	2328},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1372,	2,	2333},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1373,	1,	2335},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1374,	1,	2336},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1375,	5,	2337},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1376,	2,	2342},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1377,	1,	2344},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1378,	1,	2345},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1379,	4,	2346},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1380,	2,	2350},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1381,	2,	2352},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1382,	1,	2354},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1383,	1,	2355},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1384,	2,	2356},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1385,	3,	2358},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1386,	2,	2361},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1387,	2,	2363},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1388,	4,	2365},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1389,	10,	2369},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1390,	12,	2379},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1391,	7,	2391},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1392,	2,	2398},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1393,	1,	2400},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1394,	2,	2401},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1395,	7,	2403},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1396,	11,	2410},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1397,	19,	2421},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1398,	11,	2440},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1399,	17,	2451},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1400,	12,	2468},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1401,	22,	2480},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1402,	3,	2502},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1403,	3,	2505},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1404,	1,	2508},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1405,	1,	2509},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1406,	1,	2510},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1407,	1,	2511},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1408,	3,	2512},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1409,	14,	2515},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1410,	14,	2529},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1411,	14,	2543},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1412,	9,	2557},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1413,	9,	2566},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1414,	6,	2575},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1415,	1,	2581},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1416,	1,	2582},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1417,	1,	2583},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1418,	1,	2584},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1419,	2,	2585},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1420,	1,	2587},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1421,	6,	2588},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1422,	6,	2594},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1423,	13,	2600},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1424,	5,	2613},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1425,	8,	2618},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1426,	19,	2626},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1427,	3,	2645},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1428,	1,	2648},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1429,	1,	2649},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1430,	3,	2650},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1431,	3,	2653},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1432,	3,	2656},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1433,	4,	2659},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1434,	4,	2663},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1435,	4,	2667},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1436,	7,	2671},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1437,	5,	2678},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1438,	5,	2683},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1439,	4,	2688},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1440,	4,	2692},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1441,	4,	2696},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1442,	1,	2700},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1443,	1,	2701},
 	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1444,	2,	2702},
 	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1446,	24,	2704},
 	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1448,	4,	2728},
@@ -35374,77 +35381,77 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
-	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
-	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
-	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
-	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
-	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
-	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
-	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800e00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800e00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
@@ -35459,12 +35466,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
@@ -35484,12 +35491,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
@@ -35499,30 +35506,30 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
@@ -35543,36 +35550,36 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
@@ -35592,14 +35599,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
 	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
 	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
@@ -35624,7 +35631,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
 	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
 	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
@@ -35645,15 +35652,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
@@ -35662,16 +35669,16 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX1_CLK_EN"                 ,	   0x11800100007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
@@ -35714,22 +35721,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
@@ -35834,22 +35841,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
@@ -35858,14 +35865,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
@@ -35874,22 +35881,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
@@ -35922,8 +35929,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
@@ -35931,205 +35938,205 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
@@ -36138,14 +36145,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
@@ -36168,232 +36175,232 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_128_CNT"        ,	   0x14F0000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_129_CNT"        ,	   0x14F0000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_130_CNT"        ,	   0x14F0000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_131_CNT"        ,	   0x14F0000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_132_CNT"        ,	   0x14F0000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_133_CNT"        ,	   0x14F0000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_134_CNT"        ,	   0x14F0000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_135_CNT"        ,	   0x14F0000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_136_CNT"        ,	   0x14F0000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_137_CNT"        ,	   0x14F0000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_138_CNT"        ,	   0x14F0000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_139_CNT"        ,	   0x14F0000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_140_CNT"        ,	   0x14F0000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_141_CNT"        ,	   0x14F0000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_142_CNT"        ,	   0x14F0000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_143_CNT"        ,	   0x14F0000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_144_CNT"        ,	   0x14F0000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_145_CNT"        ,	   0x14F0000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_146_CNT"        ,	   0x14F0000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_147_CNT"        ,	   0x14F0000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_148_CNT"        ,	   0x14F0000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_149_CNT"        ,	   0x14F0000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_150_CNT"        ,	   0x14F0000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_151_CNT"        ,	   0x14F0000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_152_CNT"        ,	   0x14F0000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_153_CNT"        ,	   0x14F0000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_154_CNT"        ,	   0x14F0000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_155_CNT"        ,	   0x14F0000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_156_CNT"        ,	   0x14F0000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_157_CNT"        ,	   0x14F0000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_158_CNT"        ,	   0x14F0000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_159_CNT"        ,	   0x14F0000000D80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_PORT_QOS_INT2"           ,	   0x14F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"L2C_INT_STAT"                ,	   0x11800800000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
 	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
 	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
-	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
-	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_OOB"                     ,	   0x11800800000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_OOB1"                    ,	   0x11800800000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_OOB2"                    ,	   0x11800800000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_OOB3"                    ,	   0x11800800000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
-	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2C_PPGRP"                   ,	   0x11800800000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
 	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
@@ -36406,101 +36413,101 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"LMC1_BIST_CTL"               ,	   0x11800E80000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"LMC1_BIST_RESULT"            ,	   0x11800E80000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC1_BIST_CTL"               ,	   0x11800e80000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC1_BIST_RESULT"            ,	   0x11800e80000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"LMC1_COMP_CTL"               ,	   0x11800E8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC1_COMP_CTL"               ,	   0x11800e8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"LMC1_CTL"                    ,	   0x11800E8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LMC1_CTL"                    ,	   0x11800e8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"LMC1_CTL1"                   ,	   0x11800E8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC1_CTL1"                   ,	   0x11800e8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"LMC1_DCLK_CNT_HI"            ,	   0x11800E8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC1_DCLK_CNT_HI"            ,	   0x11800e8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
 	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"LMC1_DCLK_CNT_LO"            ,	   0x11800E8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"LMC0_DCLK_CTL"               ,	   0x11800880000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
-	{"LMC1_DCLK_CTL"               ,	   0x11800E80000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC1_DCLK_CNT_LO"            ,	   0x11800e8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LMC0_DCLK_CTL"               ,	   0x11800880000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC1_DCLK_CTL"               ,	   0x11800e80000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
 	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"LMC1_DDR2_CTL"               ,	   0x11800E8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LMC1_DDR2_CTL"               ,	   0x11800e8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
 	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"LMC1_DELAY_CFG"              ,	   0x11800E8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LMC1_DLL_CTL"                ,	   0x11800E80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC1_DELAY_CFG"              ,	   0x11800e8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC1_DLL_CTL"                ,	   0x11800e80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
 	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"LMC1_DUAL_MEMCFG"            ,	   0x11800E8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x11800e8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"LMC1_ECC_SYND"               ,	   0x11800E8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LMC1_ECC_SYND"               ,	   0x11800e8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
 	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"LMC1_FADR"                   ,	   0x11800E8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LMC1_FADR"                   ,	   0x11800e8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
 	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"LMC1_IFB_CNT_HI"             ,	   0x11800E8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC1_IFB_CNT_HI"             ,	   0x11800e8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
 	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"LMC1_IFB_CNT_LO"             ,	   0x11800E8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC1_IFB_CNT_LO"             ,	   0x11800e8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
 	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"LMC1_MEM_CFG0"               ,	   0x11800E8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC1_MEM_CFG0"               ,	   0x11800e8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"LMC1_MEM_CFG1"               ,	   0x11800E8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC1_MEM_CFG1"               ,	   0x11800e8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
-	{"LMC1_OPS_CNT_HI"             ,	   0x11800E8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC1_OPS_CNT_HI"             ,	   0x11800e8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"LMC1_OPS_CNT_LO"             ,	   0x11800E8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"LMC1_PLL_CTL"                ,	   0x11800E80000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"LMC1_PLL_STATUS"             ,	   0x11800E80000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC1_OPS_CNT_LO"             ,	   0x11800e8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC1_PLL_CTL"                ,	   0x11800e80000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC1_PLL_STATUS"             ,	   0x11800e80000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
 	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800E8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800e8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
 	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
-	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800E8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800e8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800E8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800E8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800E8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800E8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
-	{"LMC1_RODT_COMP_CTL"          ,	   0x11800E80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800e8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800e8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800e8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800e8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_RODT_COMP_CTL"          ,	   0x11800e80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
-	{"LMC1_RODT_CTL"               ,	   0x11800E8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC1_RODT_CTL"               ,	   0x11800e8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
-	{"LMC1_WODT_CTL0"              ,	   0x11800E8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC1_WODT_CTL0"              ,	   0x11800e8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"LMC1_WODT_CTL1"              ,	   0x11800E8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
-	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"LMC1_WODT_CTL1"              ,	   0x11800e8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
 	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
 	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
 	{"MIO_BOOT_DMA_CFG2"           ,	   0x1180000000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
@@ -36513,8 +36520,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"MIO_BOOT_DMA_TIM2"           ,	   0x1180000000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
@@ -36535,7 +36542,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
@@ -36562,55 +36569,55 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
 	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
 	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
@@ -36624,232 +36631,232 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
 	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
 	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
-	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
-	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	409},
-	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	410},
-	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	411},
-	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	412},
-	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	413},
-	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
-	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
-	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
-	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
-	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
-	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
-	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
-	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
-	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
-	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
-	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	423},
-	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
-	{"NPEI_DMA_STATE1_P1"          ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
-	{"NPEI_DMA_STATE2_P1"          ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
-	{"NPEI_DMA_STATE3_P1"          ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
-	{"NPEI_DMA_STATE4_P1"          ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
-	{"NPEI_DMA_STATE5_P1"          ,	   0x11F00000086C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
-	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
-	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
-	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
-	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
-	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
-	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
-	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
-	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
-	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
-	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
-	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
-	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
-	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
-	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
-	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
-	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
-	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
-	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
-	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11f0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11f0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11f0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11f0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11f0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11f0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11f0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11f0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11f0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11f0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11f00000080a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11f00000080b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11f00000080c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11f00000080d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11f00000080e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11f00000080f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11f0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11f0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11f0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11f0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11f0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11f0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11f0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11f0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11f0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11f0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11f00000081a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11f00000081b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11f00000081c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11f00000081d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11f00000081e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11f00000081f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BIST_STATUS"            ,	   0x11f0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	409},
+	{"NPEI_CTL_PORT0"              ,	   0x11f0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	410},
+	{"NPEI_CTL_PORT1"              ,	   0x11f0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	411},
+	{"NPEI_CTL_STATUS"             ,	   0x11f0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	412},
+	{"NPEI_CTL_STATUS2"            ,	   0x11f000000bc00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	413},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11f00000085f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
+	{"NPEI_DBG_DATA"               ,	   0x11f0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
+	{"NPEI_DBG_SELECT"             ,	   0x11f0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11f0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11f0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11f0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11f0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11f0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA0_DBELL"             ,	   0x11f00000083b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA1_DBELL"             ,	   0x11f00000083c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA2_DBELL"             ,	   0x11f00000083d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA3_DBELL"             ,	   0x11f00000083e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA4_DBELL"             ,	   0x11f00000083f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11f0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11f0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11f0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11f0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11f0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA0_NADDR"             ,	   0x11f00000084a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA1_NADDR"             ,	   0x11f00000084b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA2_NADDR"             ,	   0x11f00000084c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA3_NADDR"             ,	   0x11f00000084d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA4_NADDR"             ,	   0x11f00000084e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11f00000085c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11f00000085d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA_CNTS"               ,	   0x11f00000085e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	423},
+	{"NPEI_DMA_CONTROL"            ,	   0x11f00000083a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA_STATE1_P1"          ,	   0x11f0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA_STATE2_P1"          ,	   0x11f0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_DMA_STATE3_P1"          ,	   0x11f00000086a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_DMA_STATE4_P1"          ,	   0x11f00000086b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_DMA_STATE5_P1"          ,	   0x11f00000086c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_INT_ENB"                ,	   0x11f0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_INT_ENB2"               ,	   0x11f000000bcd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_INT_INFO"               ,	   0x11f0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_INT_SUM"                ,	   0x11f0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11f0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11f0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11f00000084f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11f0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11f0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11f00000082a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11f00000082b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11f00000082c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11f00000082d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11f00000082e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11f00000082f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11f0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11f0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11f0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11f0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11f0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11f0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11f0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11f0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MSI_ENB0"               ,	   0x11f000000bc50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_MSI_ENB1"               ,	   0x11f000000bc60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_MSI_ENB2"               ,	   0x11f000000bc70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_MSI_ENB3"               ,	   0x11f000000bc80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_MSI_RCV0"               ,	   0x11f000000bc10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_MSI_RCV1"               ,	   0x11f000000bc20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_MSI_RCV2"               ,	   0x11f000000bc30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MSI_RCV3"               ,	   0x11f000000bc40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11f000000bca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11f000000bc90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11f000000bcb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11f0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11f0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11f0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11f0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_SCRATCH_1"              ,	   0x11f0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_STATE1"                 ,	   0x11f0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_STATE2"                 ,	   0x11f0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_STATE3"                 ,	   0x11f0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
 	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	457},
 	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	458},
 	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	459},
 	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	460},
 	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	461},
-	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
-	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	463},
-	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	464},
-	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	465},
-	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	466},
-	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	467},
-	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	468},
-	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	469},
-	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
-	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
-	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
-	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
-	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
-	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
-	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
-	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
-	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
-	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
-	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
-	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
-	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
-	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
-	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
-	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
-	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
-	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
-	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
-	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
-	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
-	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
-	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
-	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
-	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
-	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
-	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
-	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
-	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
-	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
-	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
-	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
-	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
-	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
-	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
-	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
-	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
-	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
-	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
-	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
-	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
-	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
-	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
-	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
-	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
-	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
-	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
-	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
-	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
-	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
-	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
-	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
-	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
-	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
-	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
-	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
-	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
-	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
-	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
-	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
-	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
-	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
-	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
-	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
-	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
-	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
-	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
-	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
-	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
-	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"NPEI_WINDOW_CTL"             ,	   0x11f0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	463},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	464},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	465},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	466},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	467},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	468},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	469},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
 	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	540},
 	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	540},
 	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	541},
 	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	541},
 	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	542},
 	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	542},
-	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
-	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
 	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	544},
 	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	544},
 	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	545},
 	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	545},
 	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	546},
 	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	546},
-	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
-	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
 	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
 	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
 	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
 	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
 	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
 	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
-	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
-	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
 	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
 	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
 	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
 	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
 	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
 	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
-	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
-	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
 	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
 	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
 	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
@@ -36860,62 +36867,62 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
 	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
 	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
-	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
-	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
 	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
 	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
 	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
 	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
 	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
 	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
-	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
-	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
 	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
 	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
 	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
 	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
 	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
 	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
-	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
-	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
 	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
 	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
 	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
 	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
 	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
 	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
-	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
-	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
-	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
-	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
-	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
-	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
-	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
-	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
 	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
 	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
 	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
 	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
 	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
 	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
-	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
-	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
 	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
 	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
 	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
 	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
 	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
 	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
-	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
-	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
 	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
 	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
 	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
 	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
 	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
 	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
-	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
-	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
 	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
 	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
 	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
@@ -36926,603 +36933,603 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
 	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
 	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
-	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
-	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
 	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
 	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
 	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
 	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
 	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
 	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
-	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
-	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
 	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
 	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
 	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
 	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
-	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
-	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
 	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
 	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
 	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
 	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
-	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
-	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
 	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
 	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
 	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
 	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
 	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
 	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
-	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
-	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
 	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
 	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
-	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
-	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
-	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
-	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
-	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
-	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
 	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
 	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
 	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
 	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
-	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS1_AN000_ADV_REG"          ,	   0x11800B8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS1_AN001_ADV_REG"          ,	   0x11800B8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS1_AN002_ADV_REG"          ,	   0x11800B8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS1_AN003_ADV_REG"          ,	   0x11800B8001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
-	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800B8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800B8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800B8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800B8001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
-	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800B8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800B8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800B8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800B8001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
-	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800B8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800B8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800B8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800B8001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
-	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS1_INT000_EN_REG"          ,	   0x11800B8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS1_INT001_EN_REG"          ,	   0x11800B8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS1_INT002_EN_REG"          ,	   0x11800B8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS1_INT003_EN_REG"          ,	   0x11800B8001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
-	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS1_INT000_REG"             ,	   0x11800B8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS1_INT001_REG"             ,	   0x11800B8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS1_INT002_REG"             ,	   0x11800B8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS1_INT003_REG"             ,	   0x11800B8001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
-	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800B8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800B8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800B8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800B8001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
-	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS1_LOG_ANL000_REG"         ,	   0x11800B8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS1_LOG_ANL001_REG"         ,	   0x11800B8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS1_LOG_ANL002_REG"         ,	   0x11800B8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS1_LOG_ANL003_REG"         ,	   0x11800B8001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS1_MISC000_CTL_REG"        ,	   0x11800B8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS1_MISC001_CTL_REG"        ,	   0x11800B8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS1_MISC002_CTL_REG"        ,	   0x11800B8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS1_MISC003_CTL_REG"        ,	   0x11800B8001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800B8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800B8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800B8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800B8001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS1_MR000_STATUS_REG"       ,	   0x11800B8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS1_MR001_STATUS_REG"       ,	   0x11800B8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS1_MR002_STATUS_REG"       ,	   0x11800B8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS1_MR003_STATUS_REG"       ,	   0x11800B8001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS1_RX000_STATES_REG"       ,	   0x11800B8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS1_RX001_STATES_REG"       ,	   0x11800B8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS1_RX002_STATES_REG"       ,	   0x11800B8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS1_RX003_STATES_REG"       ,	   0x11800B8001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS1_RX000_SYNC_REG"         ,	   0x11800B8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS1_RX001_SYNC_REG"         ,	   0x11800B8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS1_RX002_SYNC_REG"         ,	   0x11800B8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS1_RX003_SYNC_REG"         ,	   0x11800B8001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800B8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800B8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800B8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800B8001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800B8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800B8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800B8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800B8001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS1_TX000_STATES_REG"       ,	   0x11800B8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS1_TX001_STATES_REG"       ,	   0x11800B8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS1_TX002_STATES_REG"       ,	   0x11800B8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS1_TX003_STATES_REG"       ,	   0x11800B8001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800B8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800B8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800B8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800B8001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
-	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
-	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
-	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
-	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
-	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
-	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
-	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
-	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
-	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
-	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
-	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
-	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
-	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
-	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
-	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
-	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
-	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
-	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
-	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
-	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
-	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
-	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
-	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
-	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
-	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
-	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
-	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
-	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
-	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
-	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
-	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
-	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
-	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
-	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
-	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
-	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
-	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
-	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
-	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
-	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
-	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
-	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
-	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
-	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b8001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b8001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b8001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b8001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b8001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT000_REG"             ,	   0x11800b8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT001_REG"             ,	   0x11800b8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT002_REG"             ,	   0x11800b8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT003_REG"             ,	   0x11800b8001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b8001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b8001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b8001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b8001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b8001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b8001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b8001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b8001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b8001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b8001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b8001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX1_INT_REG"               ,	   0x11800b8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PESC0_BIST_STATUS"           ,	   0x11800c8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PESC1_BIST_STATUS"           ,	   0x11800d0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800c8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800d0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PESC0_CFG_RD"                ,	   0x11800c8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PESC1_CFG_RD"                ,	   0x11800d0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PESC0_CFG_WR"                ,	   0x11800c8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PESC1_CFG_WR"                ,	   0x11800d0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800c8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800d0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PESC0_CTL_STATUS"            ,	   0x11800c8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PESC1_CTL_STATUS"            ,	   0x11800d0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800c8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800d0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC0_DBG_INFO"              ,	   0x11800c8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC1_DBG_INFO"              ,	   0x11800d0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800c80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800d00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800c8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800d0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800c8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800d0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800c8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800d0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800c8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800d0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800c8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800c8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800c8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800c8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800d0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800d0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800d0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800d0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800c8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800c8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800c8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800c8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800d0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800d0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800d0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800d0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800c8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800d0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
@@ -37549,9 +37556,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
 	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
 	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
 	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
@@ -37561,7 +37568,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
@@ -37576,14 +37583,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
 	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
 	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
-	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
-	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
 	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
 	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
@@ -37599,22 +37606,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
 	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
 	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
@@ -37647,34 +37654,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
 	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
 	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
 	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
@@ -37720,175 +37727,175 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	820},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	821},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	822},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	823},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	826},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	820},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	821},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	822},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	823},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	826},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	874},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	875},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	876},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	877},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	878},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	879},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	880},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	881},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	882},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	874},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	875},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	876},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	877},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	878},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	879},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	880},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	881},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	882},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
 	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	900},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
@@ -39142,7 +39149,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"Q3FUS"                       ,	0,	34,	294,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_1024K"                  ,	34,	1,	294,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	35,	1,	294,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	294,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	3,	294,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_40_63"              ,	40,	24,	294,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
@@ -39214,7 +39221,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"INORDER_MWF"                 ,	13,	1,	312,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	312,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	312,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	312,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	312,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	312,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
@@ -39777,7 +39784,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"BAR2_ESX"                    ,	2,	2,	410,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	410,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	410,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	410,	"R/W",	0,	0,	1ull,	1ull},
@@ -39794,7 +39801,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"BAR2_ESX"                    ,	2,	2,	411,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	411,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	411,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	411,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	411,	"R/W",	0,	0,	1ull,	1ull},
@@ -39920,16 +39927,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"PCNT"                        ,	17,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTIME"                       ,	18,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_AERI"                     ,	19,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_20_20"              ,	20,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_20"              ,	20,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_SE"                       ,	21,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_22_22"              ,	22,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_WAKE"                     ,	23,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_PMEI"                     ,	24,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_HPINT"                    ,	25,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_AERI"                     ,	26,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_SE"                       ,	28,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_29_29"              ,	29,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_29"              ,	29,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_WAKE"                     ,	30,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_PMEI"                     ,	31,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_HPINT"                    ,	32,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
@@ -39983,16 +39990,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"PCNT"                        ,	17,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTIME"                       ,	18,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_AERI"                     ,	19,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_20_20"              ,	20,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_20"              ,	20,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_SE"                       ,	21,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_22_22"              ,	22,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_WAKE"                     ,	23,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_PMEI"                     ,	24,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C0_HPINT"                    ,	25,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_AERI"                     ,	26,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_27_27"              ,	27,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_SE"                       ,	28,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_29_29"              ,	29,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_29"              ,	29,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_WAKE"                     ,	30,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_PMEI"                     ,	31,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
 	{"C1_HPINT"                    ,	32,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
@@ -40045,16 +40052,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"DTIME1"                      ,	14,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"RESERVED_15_18"              ,	15,	4,	433,	"RAZ",	0,	0,	0ull,	0ull},
 	{"C0_AERI"                     ,	19,	1,	433,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_20_20"              ,	20,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C0_SE"                       ,	21,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_22"              ,	22,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C0_WAKE"                     ,	23,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C0_PMEI"                     ,	24,	1,	433,	"RO",	0,	0,	0ull,	0ull},
 	{"C0_HPINT"                    ,	25,	1,	433,	"RO",	0,	0,	0ull,	0ull},
 	{"C1_AERI"                     ,	26,	1,	433,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_27_27"              ,	27,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C1_SE"                       ,	28,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_29_29"              ,	29,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C1_WAKE"                     ,	30,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"C1_PMEI"                     ,	31,	1,	433,	"RO",	0,	0,	0ull,	0ull},
 	{"C1_HPINT"                    ,	32,	1,	433,	"RO",	0,	0,	0ull,	0ull},
@@ -41600,9 +41607,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"BACK"                        ,	59,	4,	701,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	701,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	702,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	702,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	702,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	702,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	702,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	702,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	703,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	703,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	703,	"RO",	1,	0,	0,	0ull},
@@ -41610,7 +41617,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"SOP"                         ,	18,	1,	703,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	703,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	703,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	703,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	703,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	704,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	704,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	704,	"RO",	1,	0,	0,	0ull},
@@ -41643,7 +41650,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"CURR_SIZ"                    ,	0,	8,	710,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	8,	40,	710,	"RO",	1,	0,	0,	0ull},
 	{"NXT_INFLT"                   ,	48,	6,	710,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	710,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	710,	"RAZ",	1,	1,	0,	0},
 	{"QID_BASE"                    ,	0,	8,	711,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFF"                     ,	8,	4,	711,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFMAX"                  ,	12,	4,	711,	"RO",	1,	0,	0,	0ull},
@@ -41656,7 +41663,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"PREEMPTER"                   ,	28,	1,	711,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFTHS"                  ,	29,	4,	711,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFRES"                  ,	33,	4,	711,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	711,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	712,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	712,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	712,	"RO",	1,	0,	0,	0ull},
@@ -41668,35 +41675,35 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"S_TAIL"                      ,	4,	1,	713,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	713,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTEE"                   ,	6,	1,	713,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	713,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	713,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	713,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTER"                   ,	28,	1,	713,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	713,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	713,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	714,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	714,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	714,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	714,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	714,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	714,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	715,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	715,	"R/W",	1,	0,	0,	0ull},
 	{"BP_PORT"                     ,	10,	6,	715,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	715,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	715,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	715,	"R/W",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	61,	1,	715,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	715,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	715,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	716,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	716,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	716,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	716,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	716,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	716,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	716,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	717,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	717,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	717,	"RAZ",	1,	1,	0,	0},
 	{"RATE_PKT"                    ,	8,	24,	717,	"R/W",	1,	0,	0,	0ull},
 	{"RATE_WORD"                   ,	32,	19,	717,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	717,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	717,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	718,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	718,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	718,	"RAZ",	1,	1,	0,	0},
 	{"RATE_LIM"                    ,	8,	24,	718,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	718,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	718,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	719,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	719,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	719,	"WR0",	1,	0,	0,	0ull},
@@ -41708,9 +41715,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"S_TAIL"                      ,	63,	1,	719,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	720,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	720,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	720,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	720,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	720,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	721,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	2,	721,	"RO",	1,	0,	0,	0ull},
 	{"PRT_CTL"                     ,	6,	2,	721,	"RO",	1,	0,	0,	0ull},
@@ -41726,11 +41733,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"OUT_DAT"                     ,	32,	1,	721,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	33,	1,	721,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	34,	1,	721,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	721,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	721,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	722,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	722,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	722,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	722,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	722,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	723,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	724,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	725,	"RO",	0,	0,	0ull,	0ull},
@@ -41745,33 +41752,33 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"ENGINE7"                     ,	28,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE8"                     ,	32,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE9"                     ,	36,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_40_63"              ,	40,	24,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	727,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	10,	728,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	728,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	728,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	729,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	730,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	730,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	730,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	731,	"R/W",	0,	0,	2ull,	2ull},
 	{"MODE1"                       ,	3,	3,	731,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_6_63"               ,	6,	58,	731,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	731,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	732,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	732,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	733,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	733,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	733,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	734,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	734,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	735,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	735,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	735,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	735,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	736,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	736,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	736,	"RO",	0,	0,	0ull,	0ull},
@@ -41876,7 +41883,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"NCB_INB"                     ,	2,	2,	762,	"RO",	1,	0,	0,	0ull},
 	{"NCB_OUB"                     ,	4,	1,	762,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	5,	1,	762,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	762,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	762,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	763,	"R/W",	0,	1,	0ull,	0},
 	{"SIZE"                        ,	33,	13,	763,	"R/W",	0,	1,	0ull,	0},
 	{"POOL"                        ,	46,	3,	763,	"R/W",	0,	1,	0ull,	0},
@@ -41891,11 +41898,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"OWORDPV"                     ,	6,	1,	765,	"RO",	1,	1,	0,	0},
 	{"OWORDQV"                     ,	7,	1,	765,	"RO",	1,	1,	0,	0},
 	{"IWIDX"                       ,	8,	6,	765,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	765,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	765,	"RO",	1,	1,	0,	0},
 	{"IRIDX"                       ,	16,	6,	765,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	765,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	765,	"RO",	1,	1,	0,	0},
 	{"LOOP"                        ,	32,	25,	765,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	765,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	765,	"RO",	1,	1,	0,	0},
 	{"CWORD"                       ,	0,	64,	766,	"RO",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	767,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	767,	"RO",	1,	1,	0,	0},
@@ -41906,16 +41913,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"WC"                          ,	10,	1,	768,	"RO",	1,	1,	0,	0},
 	{"P"                           ,	11,	1,	768,	"RO",	1,	1,	0,	0},
 	{"Q"                           ,	12,	1,	768,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	768,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	768,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	15,	769,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	769,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	769,	"RAZ",	1,	1,	0,	0},
 	{"OWORDP"                      ,	0,	64,	770,	"RO",	1,	1,	0,	0},
 	{"OWORDQ"                      ,	0,	64,	771,	"RO",	1,	1,	0,	0},
 	{"RWORD"                       ,	0,	64,	772,	"RO",	1,	1,	0,	0},
 	{"N0CREDS"                     ,	0,	4,	773,	"RO",	0,	0,	8ull,	0ull},
 	{"N1CREDS"                     ,	4,	4,	773,	"RO",	0,	0,	8ull,	0ull},
 	{"POWCREDS"                    ,	8,	2,	773,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	773,	"RAZ",	1,	1,	0,	0},
 	{"FPACREDS"                    ,	12,	2,	773,	"RO",	0,	0,	1ull,	0ull},
 	{"WCCREDS"                     ,	14,	2,	773,	"RO",	0,	0,	0ull,	0ull},
 	{"NIWIDX0"                     ,	16,	4,	773,	"RO",	1,	1,	0,	0},
@@ -41929,12 +41936,12 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"NIRVAL7"                     ,	43,	5,	773,	"RO",	1,	1,	0,	0},
 	{"NIRQUE7"                     ,	48,	2,	773,	"RO",	1,	1,	0,	0},
 	{"NIROPC7"                     ,	50,	3,	773,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	773,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	774,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	774,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	56,	8,	774,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	0,	15,	775,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	775,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	775,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	776,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	776,	"RO",	1,	1,	0,	0},
 	{"FLAGS"                       ,	56,	8,	776,	"RO",	1,	1,	0,	0},
@@ -41944,16 +41951,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"Q"                           ,	17,	1,	777,	"RO",	1,	1,	0,	0},
 	{"INI"                         ,	18,	1,	777,	"RO",	1,	1,	0,	0},
 	{"EOD"                         ,	19,	1,	777,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	777,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	777,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	778,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	778,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	778,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	779,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	779,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	779,	"RAZ",	1,	1,	0,	0},
 	{"COEFFS"                      ,	0,	8,	780,	"R/W",	0,	0,	29ull,	29ull},
 	{"RESERVED_8_63"               ,	8,	56,	780,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INDEX"                       ,	0,	16,	781,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	16,	16,	781,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	781,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	781,	"RAZ",	1,	1,	0,	0},
 	{"MEM"                         ,	0,	1,	782,	"RO",	0,	0,	0ull,	0ull},
 	{"RRC"                         ,	1,	1,	782,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_2_63"               ,	2,	62,	782,	"RAZ",	1,	1,	0,	0},
@@ -41991,11 +41998,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"PENDING"                     ,	17,	1,	788,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	788,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	789,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	789,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	789,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	789,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	789,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	789,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	789,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	789,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	789,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	790,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	790,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	790,	"RO",	1,	0,	0,	0ull},
@@ -42003,32 +42010,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"RESERVED_7_7"                ,	7,	1,	791,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	791,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	791,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	791,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	791,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	792,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	792,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	792,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	792,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	792,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	793,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	793,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	793,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	793,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	793,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	793,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	794,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	794,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	794,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	794,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	795,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	795,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	796,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	796,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	797,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	797,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	798,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	798,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	798,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	799,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	799,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	799,	"RO",	0,	0,	0ull,	0ull},
@@ -42049,9 +42056,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"RPTR"                        ,	8,	8,	801,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	801,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	802,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	802,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	802,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	802,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	802,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	802,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	802,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	803,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	803,	"RAZ",	0,	0,	0ull,	0ull},
@@ -42726,27 +42733,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
 	{"TXRISETUNE"                  ,	63,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	895,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	895,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	895,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	895,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	896,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	896,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	896,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	896,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	896,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	896,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	897,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	897,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	897,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	898,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	898,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	898,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	898,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	898,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	898,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	898,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	898,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	899,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	899,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	899,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	900,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	900,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	901,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	901,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
@@ -43277,83 +43284,83 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
 	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1925,	1,	2636},
 	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1926,	2,	2637},
 	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1927,	2,	2639},
-	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1928,	2,	2641},
-	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1929,	24,	2643},
-	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1930,	4,	2667},
-	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1931,	5,	2671},
-	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1932,	5,	2676},
-	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1933,	2,	2681},
-	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1934,	1,	2683},
-	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1935,	1,	2684},
-	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1936,	5,	2685},
-	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1937,	2,	2690},
-	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1938,	1,	2692},
-	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1939,	1,	2693},
-	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1940,	4,	2694},
-	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1941,	2,	2698},
-	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1942,	2,	2700},
-	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1943,	1,	2702},
-	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1944,	1,	2703},
-	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1945,	2,	2704},
-	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1946,	3,	2706},
-	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1947,	2,	2709},
-	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1948,	2,	2711},
-	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1949,	4,	2713},
-	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1950,	10,	2717},
-	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1951,	12,	2727},
-	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1952,	7,	2739},
-	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1953,	2,	2746},
-	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1954,	1,	2748},
-	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1955,	2,	2749},
-	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1956,	7,	2751},
-	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1957,	11,	2758},
-	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1958,	19,	2769},
-	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1959,	11,	2788},
-	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1960,	17,	2799},
-	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1961,	12,	2816},
-	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1962,	22,	2828},
-	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1963,	3,	2850},
-	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1964,	3,	2853},
-	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1965,	1,	2856},
-	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1966,	1,	2857},
-	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1967,	1,	2858},
-	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1968,	1,	2859},
-	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1969,	3,	2860},
-	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1970,	14,	2863},
-	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1971,	14,	2877},
-	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1972,	14,	2891},
-	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1973,	9,	2905},
-	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1974,	9,	2914},
-	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1975,	6,	2923},
-	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1976,	1,	2929},
-	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1977,	1,	2930},
-	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1978,	1,	2931},
-	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1979,	1,	2932},
-	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1980,	2,	2933},
-	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1981,	1,	2935},
-	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1982,	6,	2936},
-	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1983,	6,	2942},
-	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1984,	13,	2948},
-	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1985,	5,	2961},
-	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1986,	8,	2966},
-	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1987,	19,	2974},
-	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1988,	3,	2993},
-	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1989,	1,	2996},
-	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1990,	1,	2997},
-	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1991,	3,	2998},
-	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1992,	3,	3001},
-	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1993,	3,	3004},
-	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1994,	4,	3007},
-	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1995,	4,	3011},
-	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1996,	4,	3015},
-	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1997,	7,	3019},
-	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1998,	5,	3026},
-	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1999,	5,	3031},
-	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2000,	4,	3036},
-	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2001,	4,	3040},
-	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2002,	4,	3044},
-	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2003,	1,	3048},
-	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2004,	1,	3049},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1928,	2,	2641},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1929,	24,	2643},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1930,	4,	2667},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1931,	5,	2671},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1932,	5,	2676},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1933,	2,	2681},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1934,	1,	2683},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1935,	1,	2684},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1936,	5,	2685},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1937,	2,	2690},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1938,	1,	2692},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1939,	1,	2693},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1940,	4,	2694},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1941,	2,	2698},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1942,	2,	2700},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1943,	1,	2702},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1944,	1,	2703},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1945,	2,	2704},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1946,	3,	2706},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1947,	2,	2709},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1948,	2,	2711},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1949,	4,	2713},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1950,	10,	2717},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1951,	12,	2727},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1952,	7,	2739},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1953,	2,	2746},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1954,	1,	2748},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1955,	2,	2749},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1956,	7,	2751},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1957,	11,	2758},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1958,	19,	2769},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1959,	11,	2788},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1960,	17,	2799},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1961,	12,	2816},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1962,	22,	2828},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1963,	3,	2850},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1964,	3,	2853},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1965,	1,	2856},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1966,	1,	2857},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1967,	1,	2858},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1968,	1,	2859},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1969,	3,	2860},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1970,	14,	2863},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1971,	14,	2877},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1972,	14,	2891},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1973,	9,	2905},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1974,	9,	2914},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1975,	6,	2923},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1976,	1,	2929},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1977,	1,	2930},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1978,	1,	2931},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1979,	1,	2932},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1980,	2,	2933},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1981,	1,	2935},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1982,	6,	2936},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1983,	6,	2942},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1984,	13,	2948},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1985,	5,	2961},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1986,	8,	2966},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1987,	19,	2974},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1988,	3,	2993},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1989,	1,	2996},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1990,	1,	2997},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1991,	3,	2998},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1992,	3,	3001},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1993,	3,	3004},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1994,	4,	3007},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1995,	4,	3011},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1996,	4,	3015},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1997,	7,	3019},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1998,	5,	3026},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1999,	5,	3031},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2000,	4,	3036},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2001,	4,	3040},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2002,	4,	3044},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2003,	1,	3048},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2004,	1,	3049},
 	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2005,	2,	3050},
 	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2007,	24,	3052},
 	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2009,	4,	3076},
@@ -43723,77 +43730,77 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
-	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
-	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
-	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
-	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
-	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
-	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
-	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800e00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800e00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
@@ -43808,12 +43815,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
-	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT12_EN0"               ,	   0x10700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT13_EN0"               ,	   0x10700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT14_EN0"               ,	   0x10700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT15_EN0"               ,	   0x10700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
 	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
@@ -43833,12 +43840,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT16_EN0_W1C"           ,	   0x1070000002300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT17_EN0_W1C"           ,	   0x1070000002310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT18_EN0_W1C"           ,	   0x1070000002320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
@@ -43858,12 +43865,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
 	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
 	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
 	{"CIU_INT16_EN0_W1S"           ,	   0x1070000006300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
 	{"CIU_INT17_EN0_W1S"           ,	   0x1070000006310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
 	{"CIU_INT18_EN0_W1S"           ,	   0x1070000006320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
@@ -43883,12 +43890,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT12_EN1"               ,	   0x10700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT13_EN1"               ,	   0x10700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT14_EN1"               ,	   0x10700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT15_EN1"               ,	   0x10700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
@@ -43908,12 +43915,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT16_EN1_W1C"           ,	   0x1070000002308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT17_EN1_W1C"           ,	   0x1070000002318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT18_EN1_W1C"           ,	   0x1070000002328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
@@ -43933,12 +43940,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT16_EN1_W1S"           ,	   0x1070000006308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT17_EN1_W1S"           ,	   0x1070000006318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT18_EN1_W1S"           ,	   0x1070000006328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
@@ -43948,78 +43955,78 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT22_EN1_W1S"           ,	   0x1070000006368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT23_EN1_W1S"           ,	   0x1070000006378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
@@ -44040,36 +44047,36 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000c30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000c38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000c40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000c48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000c50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000c58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
 	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
 	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
-	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
 	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
 	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
 	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
@@ -44089,14 +44096,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
 	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
 	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
-	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE6"                ,	   0x10700000005b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE7"                ,	   0x10700000005b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE8"                ,	   0x10700000005c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE9"                ,	   0x10700000005c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE10"               ,	   0x10700000005d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE11"               ,	   0x10700000005d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
 	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
 	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
 	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
@@ -44121,7 +44128,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
 	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
 	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
@@ -44142,15 +44149,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
@@ -44159,18 +44166,18 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
-	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
-	{"GMX1_CLK_EN"                 ,	   0x11800100007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
 	{"GMX1_HG2_CONTROL"            ,	   0x1180010000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
-	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_INF_MODE"               ,	   0x11800100007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
 	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
@@ -44215,22 +44222,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
 	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
@@ -44335,22 +44342,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
@@ -44359,14 +44366,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
@@ -44375,22 +44382,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
@@ -44425,8 +44432,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX1_RX_HG2_STATUS"          ,	   0x1180010000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
@@ -44434,209 +44441,209 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC001"                ,	   0x1180010000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC003"                ,	   0x1180010001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800100005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX1_TX000_CBFC_XON"         ,	   0x11800100005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800100005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800100005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
 	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
 	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
-	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
-	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
 	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
 	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
-	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX1_TX_BP"                  ,	   0x11800100004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
 	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
-	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
 	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
 	{"GMX1_TX_HG2_REG1"            ,	   0x1180010000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
 	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
@@ -44649,14 +44656,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
 	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
-	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
-	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
 	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
 	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
@@ -44679,272 +44686,272 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
-	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_128_CNT"        ,	   0x14F0000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_129_CNT"        ,	   0x14F0000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_130_CNT"        ,	   0x14F0000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_131_CNT"        ,	   0x14F0000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_132_CNT"        ,	   0x14F0000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_133_CNT"        ,	   0x14F0000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_134_CNT"        ,	   0x14F0000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_135_CNT"        ,	   0x14F0000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_136_CNT"        ,	   0x14F0000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_137_CNT"        ,	   0x14F0000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_138_CNT"        ,	   0x14F0000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_139_CNT"        ,	   0x14F0000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_140_CNT"        ,	   0x14F0000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_141_CNT"        ,	   0x14F0000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_142_CNT"        ,	   0x14F0000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_143_CNT"        ,	   0x14F0000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_144_CNT"        ,	   0x14F0000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_145_CNT"        ,	   0x14F0000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_146_CNT"        ,	   0x14F0000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_147_CNT"        ,	   0x14F0000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_148_CNT"        ,	   0x14F0000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_149_CNT"        ,	   0x14F0000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_150_CNT"        ,	   0x14F0000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_151_CNT"        ,	   0x14F0000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_152_CNT"        ,	   0x14F0000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_153_CNT"        ,	   0x14F0000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_154_CNT"        ,	   0x14F0000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_155_CNT"        ,	   0x14F0000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_156_CNT"        ,	   0x14F0000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_157_CNT"        ,	   0x14F0000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_158_CNT"        ,	   0x14F0000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_159_CNT"        ,	   0x14F0000000D80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_256_CNT"        ,	   0x14F0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_257_CNT"        ,	   0x14F0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_258_CNT"        ,	   0x14F0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_259_CNT"        ,	   0x14F00000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_260_CNT"        ,	   0x14F00000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_261_CNT"        ,	   0x14F00000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_262_CNT"        ,	   0x14F00000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_263_CNT"        ,	   0x14F00000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_264_CNT"        ,	   0x14F00000010C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_265_CNT"        ,	   0x14F00000010D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_266_CNT"        ,	   0x14F00000010D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_267_CNT"        ,	   0x14F00000010E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_268_CNT"        ,	   0x14F00000010E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_269_CNT"        ,	   0x14F00000010F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_270_CNT"        ,	   0x14F00000010F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_271_CNT"        ,	   0x14F0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_272_CNT"        ,	   0x14F0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_273_CNT"        ,	   0x14F0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_274_CNT"        ,	   0x14F0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_275_CNT"        ,	   0x14F0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_276_CNT"        ,	   0x14F0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_277_CNT"        ,	   0x14F0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_278_CNT"        ,	   0x14F0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_279_CNT"        ,	   0x14F0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_280_CNT"        ,	   0x14F0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_281_CNT"        ,	   0x14F0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_282_CNT"        ,	   0x14F0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_283_CNT"        ,	   0x14F0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_284_CNT"        ,	   0x14F0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_285_CNT"        ,	   0x14F0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_286_CNT"        ,	   0x14F0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_287_CNT"        ,	   0x14F0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
-	{"IPD_PORT_QOS_INT2"           ,	   0x14F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
-	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
-	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
-	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
-	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
-	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
-	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	265},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	266},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14f00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14f0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14f0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14f0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14f0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14f0000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14f0000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14f0000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14f0000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14f0000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14f0000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14f0000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14f0000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14f0000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14f0000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14f0000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14f0000000ce0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14f0000000ce8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14f0000000cf0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14f0000000cf8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14f0000000d00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14f0000000d08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14f0000000d10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14f0000000d18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14f0000000d20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14f0000000d28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14f0000000d30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14f0000000d38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14f0000000d40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14f0000000d48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14f0000000d50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14f0000000d58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14f0000000d60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14f0000000d68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14f0000000d70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14f0000000d78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14f0000000d80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	265},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	266},
 	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
 	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
 	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
 	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
-	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
-	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
 	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2C_INT_STAT"                ,	   0x11800800000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
 	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
 	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
-	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
-	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
-	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
-	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2C_OOB"                     ,	   0x11800800000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2C_OOB1"                    ,	   0x11800800000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2C_OOB2"                    ,	   0x11800800000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"L2C_OOB3"                    ,	   0x11800800000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
-	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"L2C_PPGRP"                   ,	   0x11800800000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
 	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
 	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
@@ -44957,103 +44964,103 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
-	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
-	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
-	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
-	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
-	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
-	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
-	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"LMC1_BIST_CTL"               ,	   0x11800E80000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
-	{"LMC1_BIST_RESULT"            ,	   0x11800E80000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LED_BLINK"                   ,	   0x1180000001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LED_CLK_PHASE"               ,	   0x1180000001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LED_CYLON"                   ,	   0x1180000001af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LED_DBG"                     ,	   0x1180000001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LED_EN"                      ,	   0x1180000001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LED_POLARITY"                ,	   0x1180000001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LED_PRT"                     ,	   0x1180000001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LED_PRT_FMT"                 ,	   0x1180000001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_UDD_CNT0"                ,	   0x1180000001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LED_UDD_CNT1"                ,	   0x1180000001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LED_UDD_DAT0"                ,	   0x1180000001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LED_UDD_DAT1"                ,	   0x1180000001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC1_BIST_CTL"               ,	   0x11800e80000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC1_BIST_RESULT"            ,	   0x11800e80000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"LMC1_COMP_CTL"               ,	   0x11800E8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC1_COMP_CTL"               ,	   0x11800e8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
-	{"LMC1_CTL"                    ,	   0x11800E8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC1_CTL"                    ,	   0x11800e8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
-	{"LMC1_CTL1"                   ,	   0x11800E8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC1_CTL1"                   ,	   0x11800e8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
 	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
-	{"LMC1_DCLK_CNT_HI"            ,	   0x11800E8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC1_DCLK_CNT_HI"            ,	   0x11800e8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
 	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"LMC1_DCLK_CNT_LO"            ,	   0x11800E8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"LMC0_DCLK_CTL"               ,	   0x11800880000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"LMC1_DCLK_CTL"               ,	   0x11800E80000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC1_DCLK_CNT_LO"            ,	   0x11800e8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC0_DCLK_CTL"               ,	   0x11800880000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC1_DCLK_CTL"               ,	   0x11800e80000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
 	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
-	{"LMC1_DDR2_CTL"               ,	   0x11800E8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC1_DDR2_CTL"               ,	   0x11800e8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC1_DELAY_CFG"              ,	   0x11800E8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
-	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
-	{"LMC1_DLL_CTL"                ,	   0x11800E80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_DELAY_CFG"              ,	   0x11800e8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_DLL_CTL"                ,	   0x11800e80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
 	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
-	{"LMC1_DUAL_MEMCFG"            ,	   0x11800E8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x11800e8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
 	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
-	{"LMC1_ECC_SYND"               ,	   0x11800E8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC1_ECC_SYND"               ,	   0x11800e8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
 	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"LMC1_FADR"                   ,	   0x11800E8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"LMC1_FADR"                   ,	   0x11800e8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
 	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
-	{"LMC1_IFB_CNT_HI"             ,	   0x11800E8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"LMC1_IFB_CNT_HI"             ,	   0x11800e8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
 	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
-	{"LMC1_IFB_CNT_LO"             ,	   0x11800E8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"LMC1_IFB_CNT_LO"             ,	   0x11800e8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
 	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
-	{"LMC1_MEM_CFG0"               ,	   0x11800E8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"LMC1_MEM_CFG0"               ,	   0x11800e8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
-	{"LMC1_MEM_CFG1"               ,	   0x11800E8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
-	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
-	{"LMC1_NXM"                    ,	   0x11800E80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"LMC1_MEM_CFG1"               ,	   0x11800e8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"LMC1_NXM"                    ,	   0x11800e80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
-	{"LMC1_OPS_CNT_HI"             ,	   0x11800E8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"LMC1_OPS_CNT_HI"             ,	   0x11800e8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"LMC1_OPS_CNT_LO"             ,	   0x11800E8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
-	{"LMC1_PLL_CTL"                ,	   0x11800E80000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
-	{"LMC1_PLL_STATUS"             ,	   0x11800E80000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"LMC1_OPS_CNT_LO"             ,	   0x11800e8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"LMC1_PLL_CTL"                ,	   0x11800e80000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"LMC1_PLL_STATUS"             ,	   0x11800e80000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
 	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
-	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800E8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800e8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
 	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
-	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800E8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800e8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
 	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
 	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
 	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
 	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
-	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800E8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
-	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800E8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
-	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800E8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
-	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800E8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
-	{"LMC1_RODT_COMP_CTL"          ,	   0x11800E80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800e8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800e8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800e8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800e8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"LMC1_RODT_COMP_CTL"          ,	   0x11800e80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
-	{"LMC1_RODT_CTL"               ,	   0x11800E8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"LMC1_RODT_CTL"               ,	   0x11800e8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
-	{"LMC1_WODT_CTL0"              ,	   0x11800E8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"LMC1_WODT_CTL0"              ,	   0x11800e8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
-	{"LMC1_WODT_CTL1"              ,	   0x11800E8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
-	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"LMC1_WODT_CTL1"              ,	   0x11800e8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
 	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
 	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
 	{"MIO_BOOT_DMA_CFG2"           ,	   0x1180000000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
@@ -45066,13 +45073,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
 	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
 	{"MIO_BOOT_DMA_TIM2"           ,	   0x1180000000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
 	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
-	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
 	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
 	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
 	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
@@ -45089,7 +45096,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
@@ -45116,55 +45123,55 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
 	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
 	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
 	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	413},
 	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	414},
@@ -45178,588 +45185,588 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	422},
 	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
 	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	424},
-	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
-	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
-	{"NPEI_BIST_STATUS2"           ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
-	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
-	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
-	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
-	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
-	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
-	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
-	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
-	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
-	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
-	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
-	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
-	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
-	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
-	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
-	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
-	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
-	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11F00000085B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
-	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
-	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
-	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
-	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
-	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
-	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
-	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
-	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
-	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
-	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
-	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
-	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
-	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
-	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
-	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
-	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
-	{"NPEI_MSI_W1C_ENB0"           ,	   0x11F000000BCF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
-	{"NPEI_MSI_W1C_ENB1"           ,	   0x11F000000BD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
-	{"NPEI_MSI_W1C_ENB2"           ,	   0x11F000000BD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
-	{"NPEI_MSI_W1C_ENB3"           ,	   0x11F000000BD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
-	{"NPEI_MSI_W1S_ENB0"           ,	   0x11F000000BD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
-	{"NPEI_MSI_W1S_ENB1"           ,	   0x11F000000BD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MSI_W1S_ENB2"           ,	   0x11F000000BD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
-	{"NPEI_MSI_W1S_ENB3"           ,	   0x11F000000BD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
-	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
-	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11F000000BD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
-	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
-	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
-	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
-	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
-	{"NPEI_PKT0_CNTS"              ,	   0x11F000000A400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT1_CNTS"              ,	   0x11F000000A410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT2_CNTS"              ,	   0x11F000000A420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT3_CNTS"              ,	   0x11F000000A430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT4_CNTS"              ,	   0x11F000000A440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT5_CNTS"              ,	   0x11F000000A450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT6_CNTS"              ,	   0x11F000000A460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT7_CNTS"              ,	   0x11F000000A470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT8_CNTS"              ,	   0x11F000000A480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT9_CNTS"              ,	   0x11F000000A490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT10_CNTS"             ,	   0x11F000000A4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT11_CNTS"             ,	   0x11F000000A4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT12_CNTS"             ,	   0x11F000000A4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT13_CNTS"             ,	   0x11F000000A4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT14_CNTS"             ,	   0x11F000000A4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT15_CNTS"             ,	   0x11F000000A4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT16_CNTS"             ,	   0x11F000000A500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT17_CNTS"             ,	   0x11F000000A510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT18_CNTS"             ,	   0x11F000000A520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT19_CNTS"             ,	   0x11F000000A530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT20_CNTS"             ,	   0x11F000000A540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT21_CNTS"             ,	   0x11F000000A550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT22_CNTS"             ,	   0x11F000000A560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT23_CNTS"             ,	   0x11F000000A570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT24_CNTS"             ,	   0x11F000000A580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT25_CNTS"             ,	   0x11F000000A590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT26_CNTS"             ,	   0x11F000000A5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT27_CNTS"             ,	   0x11F000000A5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT28_CNTS"             ,	   0x11F000000A5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT29_CNTS"             ,	   0x11F000000A5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT30_CNTS"             ,	   0x11F000000A5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT31_CNTS"             ,	   0x11F000000A5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_PKT0_IN_BP"             ,	   0x11F000000B800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT1_IN_BP"             ,	   0x11F000000B810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT2_IN_BP"             ,	   0x11F000000B820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT3_IN_BP"             ,	   0x11F000000B830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT4_IN_BP"             ,	   0x11F000000B840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT5_IN_BP"             ,	   0x11F000000B850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT6_IN_BP"             ,	   0x11F000000B860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT7_IN_BP"             ,	   0x11F000000B870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT8_IN_BP"             ,	   0x11F000000B880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT9_IN_BP"             ,	   0x11F000000B890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT10_IN_BP"            ,	   0x11F000000B8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT11_IN_BP"            ,	   0x11F000000B8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT12_IN_BP"            ,	   0x11F000000B8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT13_IN_BP"            ,	   0x11F000000B8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT14_IN_BP"            ,	   0x11F000000B8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT15_IN_BP"            ,	   0x11F000000B8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT16_IN_BP"            ,	   0x11F000000B900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT17_IN_BP"            ,	   0x11F000000B910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT18_IN_BP"            ,	   0x11F000000B920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT19_IN_BP"            ,	   0x11F000000B930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT20_IN_BP"            ,	   0x11F000000B940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT21_IN_BP"            ,	   0x11F000000B950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT22_IN_BP"            ,	   0x11F000000B960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT23_IN_BP"            ,	   0x11F000000B970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT24_IN_BP"            ,	   0x11F000000B980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT25_IN_BP"            ,	   0x11F000000B990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT26_IN_BP"            ,	   0x11F000000B9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT27_IN_BP"            ,	   0x11F000000B9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT28_IN_BP"            ,	   0x11F000000B9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT29_IN_BP"            ,	   0x11F000000B9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT30_IN_BP"            ,	   0x11F000000B9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT31_IN_BP"            ,	   0x11F000000B9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11F000000A800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11F000000A810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11F000000A820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11F000000A830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11F000000A840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11F000000A850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11F000000A860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11F000000A870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11F000000A880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11F000000A890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11F000000A8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11F000000A8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11F000000A8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11F000000A8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11F000000A8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11F000000A8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11F000000A900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11F000000A910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11F000000A920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11F000000A930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11F000000A940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11F000000A950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11F000000A960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11F000000A970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11F000000A980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11F000000A990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11F000000A9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11F000000A9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11F000000A9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11F000000A9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11F000000A9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11F000000A9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11F000000AC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11F000000AC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11F000000AC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11F000000AC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11F000000AC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11F000000AC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11F000000AC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11F000000AC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11F000000AC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11F000000AC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11F000000ACA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11F000000ACB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11F000000ACC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11F000000ACD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11F000000ACE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11F000000ACF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11F000000AD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11F000000AD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11F000000AD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11F000000AD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11F000000AD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11F000000AD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11F000000AD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11F000000AD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11F000000AD80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11F000000AD90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11F000000ADA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11F000000ADB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11F000000ADC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11F000000ADD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11F000000ADE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11F000000ADF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11F000000B000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11F000000B010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11F000000B020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11F000000B030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11F000000B040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11F000000B050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11F000000B060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11F000000B070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11F000000B080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11F000000B090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11F000000B0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11F000000B0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11F000000B0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11F000000B0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11F000000B0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11F000000B0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11F000000B100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11F000000B110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11F000000B120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11F000000B130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11F000000B140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11F000000B150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11F000000B160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11F000000B170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11F000000B180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11F000000B190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11F000000B1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11F000000B1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11F000000B1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11F000000B1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11F000000B1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11F000000B1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11F000000B400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11F000000B410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11F000000B420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11F000000B430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11F000000B440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11F000000B450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11F000000B460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11F000000B470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11F000000B480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11F000000B490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11F000000B4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11F000000B4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11F000000B4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11F000000B4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11F000000B4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11F000000B4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11F000000B500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11F000000B510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11F000000B520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11F000000B530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11F000000B540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11F000000B550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11F000000B560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11F000000B570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11F000000B580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11F000000B590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11F000000B5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11F000000B5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11F000000B5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11F000000B5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11F000000B5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11F000000B5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11F0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11F0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11F0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11F0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11F0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11F0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11F0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11F0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11F0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11F0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11F00000094A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11F00000094B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11F00000094C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11F00000094D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11F00000094E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11F00000094F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11F0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11F0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11F0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11F0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11F0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11F0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11F0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11F0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11F0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11F0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11F00000095A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11F00000095B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11F00000095C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11F00000095D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11F00000095E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11F00000095F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11F0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11F0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11F0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11F0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11F0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11F0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11F0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11F0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11F0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11F0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11F00000098A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11F00000098B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11F00000098C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11F00000098D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11F00000098E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11F00000098F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11F0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11F0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11F0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11F0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11F0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11F0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11F0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11F0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11F0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11F0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11F00000099A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11F00000099B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11F00000099C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11F00000099D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11F00000099E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11F00000099F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11F0000009CA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11F0000009CB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11F0000009CC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11F0000009CD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11F0000009CE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11F0000009CF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11F0000009D00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11F0000009D10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11F0000009D20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11F0000009D30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11F0000009D40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11F0000009D50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11F0000009D60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11F0000009D70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11F0000009D80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11F0000009D90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11F0000009DA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11F0000009DB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11F0000009DC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11F0000009DD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11F0000009DE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11F0000009DF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_PKT_CNT_INT"            ,	   0x11F0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
-	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11F0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
-	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11F00000090B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
-	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11F00000090A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
-	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11F0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
-	{"NPEI_PKT_DPADDR"             ,	   0x11F0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
-	{"NPEI_PKT_IN_BP"              ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11F000000A000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11F000000A010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11F000000A020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11F000000A030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11F000000A040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11F000000A050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11F000000A060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11F000000A070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11F000000A080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11F000000A090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11F000000A0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11F000000A0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11F000000A0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11F000000A0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11F000000A0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11F000000A0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11F000000A100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11F000000A110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11F000000A120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11F000000A130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11F000000A140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11F000000A150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11F000000A160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11F000000A170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11F000000A180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11F000000A190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11F000000A1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11F000000A1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11F000000A1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11F000000A1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11F000000A1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11F000000A1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11F00000091A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11F0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT_INSTR_ENB"          ,	   0x11F0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11F0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11F0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT_INT_LEVELS"         ,	   0x11F0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT_IPTR"               ,	   0x11F0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
-	{"NPEI_PKT_OUT_BMODE"          ,	   0x11F00000090D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
-	{"NPEI_PKT_OUT_ENB"            ,	   0x11F0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
-	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11F0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
-	{"NPEI_PKT_PCIE_PORT"          ,	   0x11F00000090E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
-	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
-	{"NPEI_PKT_SLIST_ES"           ,	   0x11F0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
-	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11F0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_SLIST_NS"           ,	   0x11F0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
-	{"NPEI_PKT_SLIST_ROR"          ,	   0x11F0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
-	{"NPEI_PKT_TIME_INT"           ,	   0x11F0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
-	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11F0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
-	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
-	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
-	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
-	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
-	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11f0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11f0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11f0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11f0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11f0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11f0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11f0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11f0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11f0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11f0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11f00000080a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11f00000080b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11f00000080c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11f00000080d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11f00000080e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11f00000080f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11f0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11f0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11f0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11f0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11f0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11f0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11f0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11f0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11f0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11f0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11f00000081a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11f00000081b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11f00000081c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11f00000081d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11f00000081e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11f00000081f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BIST_STATUS"            ,	   0x11f0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_BIST_STATUS2"           ,	   0x11f0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_CTL_PORT0"              ,	   0x11f0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_CTL_PORT1"              ,	   0x11f0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_CTL_STATUS"             ,	   0x11f0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_CTL_STATUS2"            ,	   0x11f000000bc00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11f00000085f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_DBG_DATA"               ,	   0x11f0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_DBG_SELECT"             ,	   0x11f0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11f0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11f0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11f0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11f0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11f0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA0_DBELL"             ,	   0x11f00000083b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA1_DBELL"             ,	   0x11f00000083c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA2_DBELL"             ,	   0x11f00000083d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA3_DBELL"             ,	   0x11f00000083e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA4_DBELL"             ,	   0x11f00000083f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11f0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11f0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11f0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11f0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11f0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA0_NADDR"             ,	   0x11f00000084a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA1_NADDR"             ,	   0x11f00000084b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA2_NADDR"             ,	   0x11f00000084c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA3_NADDR"             ,	   0x11f00000084d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA4_NADDR"             ,	   0x11f00000084e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11f00000085c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11f00000085d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_DMA_CNTS"               ,	   0x11f00000085e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_DMA_CONTROL"            ,	   0x11f00000083a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11f00000085b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_INT_A_ENB"              ,	   0x11f0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_INT_A_ENB2"             ,	   0x11f000000bce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_INT_A_SUM"              ,	   0x11f0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_INT_ENB"                ,	   0x11f0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_INT_ENB2"               ,	   0x11f000000bcd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_INT_INFO"               ,	   0x11f0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_INT_SUM"                ,	   0x11f0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_INT_SUM2"               ,	   0x11f000000bcc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11f0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11f0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11f00000084f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11f0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11f0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11f00000082a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11f00000082b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11f00000082c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11f00000082d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11f00000082e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11f00000082f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11f0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11f0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11f0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11f0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11f0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11f0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11f0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11f0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MSI_ENB0"               ,	   0x11f000000bc50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_MSI_ENB1"               ,	   0x11f000000bc60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_MSI_ENB2"               ,	   0x11f000000bc70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_MSI_ENB3"               ,	   0x11f000000bc80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_MSI_RCV0"               ,	   0x11f000000bc10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_MSI_RCV1"               ,	   0x11f000000bc20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_MSI_RCV2"               ,	   0x11f000000bc30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_MSI_RCV3"               ,	   0x11f000000bc40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11f000000bca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
+	{"NPEI_MSI_W1C_ENB0"           ,	   0x11f000000bcf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
+	{"NPEI_MSI_W1C_ENB1"           ,	   0x11f000000bd00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
+	{"NPEI_MSI_W1C_ENB2"           ,	   0x11f000000bd10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
+	{"NPEI_MSI_W1C_ENB3"           ,	   0x11f000000bd20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
+	{"NPEI_MSI_W1S_ENB0"           ,	   0x11f000000bd30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"NPEI_MSI_W1S_ENB1"           ,	   0x11f000000bd40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MSI_W1S_ENB2"           ,	   0x11f000000bd50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
+	{"NPEI_MSI_W1S_ENB3"           ,	   0x11f000000bd60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11f000000bc90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
+	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11f000000bd70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11f000000bcb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11f0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11f0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11f0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
+	{"NPEI_PKT0_CNTS"              ,	   0x11f000000a400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT1_CNTS"              ,	   0x11f000000a410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT2_CNTS"              ,	   0x11f000000a420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT3_CNTS"              ,	   0x11f000000a430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT4_CNTS"              ,	   0x11f000000a440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT5_CNTS"              ,	   0x11f000000a450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT6_CNTS"              ,	   0x11f000000a460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT7_CNTS"              ,	   0x11f000000a470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT8_CNTS"              ,	   0x11f000000a480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT9_CNTS"              ,	   0x11f000000a490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT10_CNTS"             ,	   0x11f000000a4a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT11_CNTS"             ,	   0x11f000000a4b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT12_CNTS"             ,	   0x11f000000a4c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT13_CNTS"             ,	   0x11f000000a4d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT14_CNTS"             ,	   0x11f000000a4e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT15_CNTS"             ,	   0x11f000000a4f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT16_CNTS"             ,	   0x11f000000a500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT17_CNTS"             ,	   0x11f000000a510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT18_CNTS"             ,	   0x11f000000a520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT19_CNTS"             ,	   0x11f000000a530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT20_CNTS"             ,	   0x11f000000a540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT21_CNTS"             ,	   0x11f000000a550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT22_CNTS"             ,	   0x11f000000a560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT23_CNTS"             ,	   0x11f000000a570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT24_CNTS"             ,	   0x11f000000a580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT25_CNTS"             ,	   0x11f000000a590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT26_CNTS"             ,	   0x11f000000a5a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT27_CNTS"             ,	   0x11f000000a5b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT28_CNTS"             ,	   0x11f000000a5c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT29_CNTS"             ,	   0x11f000000a5d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT30_CNTS"             ,	   0x11f000000a5e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT31_CNTS"             ,	   0x11f000000a5f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT0_IN_BP"             ,	   0x11f000000b800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT1_IN_BP"             ,	   0x11f000000b810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT2_IN_BP"             ,	   0x11f000000b820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT3_IN_BP"             ,	   0x11f000000b830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT4_IN_BP"             ,	   0x11f000000b840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT5_IN_BP"             ,	   0x11f000000b850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT6_IN_BP"             ,	   0x11f000000b860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT7_IN_BP"             ,	   0x11f000000b870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT8_IN_BP"             ,	   0x11f000000b880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT9_IN_BP"             ,	   0x11f000000b890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT10_IN_BP"            ,	   0x11f000000b8a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT11_IN_BP"            ,	   0x11f000000b8b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT12_IN_BP"            ,	   0x11f000000b8c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT13_IN_BP"            ,	   0x11f000000b8d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT14_IN_BP"            ,	   0x11f000000b8e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT15_IN_BP"            ,	   0x11f000000b8f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT16_IN_BP"            ,	   0x11f000000b900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT17_IN_BP"            ,	   0x11f000000b910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT18_IN_BP"            ,	   0x11f000000b920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT19_IN_BP"            ,	   0x11f000000b930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT20_IN_BP"            ,	   0x11f000000b940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT21_IN_BP"            ,	   0x11f000000b950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT22_IN_BP"            ,	   0x11f000000b960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT23_IN_BP"            ,	   0x11f000000b970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT24_IN_BP"            ,	   0x11f000000b980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT25_IN_BP"            ,	   0x11f000000b990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT26_IN_BP"            ,	   0x11f000000b9a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT27_IN_BP"            ,	   0x11f000000b9b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT28_IN_BP"            ,	   0x11f000000b9c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT29_IN_BP"            ,	   0x11f000000b9d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT30_IN_BP"            ,	   0x11f000000b9e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT31_IN_BP"            ,	   0x11f000000b9f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11f000000a800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11f000000a810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11f000000a820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11f000000a830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11f000000a840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11f000000a850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11f000000a860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11f000000a870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11f000000a880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11f000000a890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11f000000a8a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11f000000a8b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11f000000a8c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11f000000a8d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11f000000a8e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11f000000a8f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11f000000a900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11f000000a910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11f000000a920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11f000000a930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11f000000a940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11f000000a950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11f000000a960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11f000000a970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11f000000a980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11f000000a990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11f000000a9a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11f000000a9b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11f000000a9c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11f000000a9d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11f000000a9e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11f000000a9f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11f000000ac00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11f000000ac10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11f000000ac20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11f000000ac30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11f000000ac40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11f000000ac50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11f000000ac60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11f000000ac70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11f000000ac80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11f000000ac90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11f000000aca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11f000000acb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11f000000acc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11f000000acd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11f000000ace0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11f000000acf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11f000000ad00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11f000000ad10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11f000000ad20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11f000000ad30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11f000000ad40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11f000000ad50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11f000000ad60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11f000000ad70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11f000000ad80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11f000000ad90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11f000000ada0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11f000000adb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11f000000adc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11f000000add0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11f000000ade0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11f000000adf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11f000000b000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11f000000b010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11f000000b020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11f000000b030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11f000000b040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11f000000b050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11f000000b060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11f000000b070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11f000000b080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11f000000b090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11f000000b0a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11f000000b0b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11f000000b0c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11f000000b0d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11f000000b0e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11f000000b0f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11f000000b100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11f000000b110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11f000000b120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11f000000b130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11f000000b140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11f000000b150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11f000000b160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11f000000b170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11f000000b180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11f000000b190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11f000000b1a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11f000000b1b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11f000000b1c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11f000000b1d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11f000000b1e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11f000000b1f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11f000000b400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11f000000b410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11f000000b420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11f000000b430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11f000000b440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11f000000b450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11f000000b460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11f000000b470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11f000000b480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11f000000b490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11f000000b4a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11f000000b4b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11f000000b4c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11f000000b4d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11f000000b4e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11f000000b4f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11f000000b500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11f000000b510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11f000000b520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11f000000b530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11f000000b540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11f000000b550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11f000000b560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11f000000b570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11f000000b580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11f000000b590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11f000000b5a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11f000000b5b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11f000000b5c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11f000000b5d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11f000000b5e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11f000000b5f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11f0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11f0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11f0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11f0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11f0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11f0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11f0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11f0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11f0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11f0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11f00000094a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11f00000094b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11f00000094c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11f00000094d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11f00000094e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11f00000094f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11f0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11f0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11f0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11f0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11f0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11f0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11f0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11f0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11f0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11f0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11f00000095a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11f00000095b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11f00000095c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11f00000095d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11f00000095e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11f00000095f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11f0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11f0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11f0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11f0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11f0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11f0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11f0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11f0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11f0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11f0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11f00000098a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11f00000098b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11f00000098c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11f00000098d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11f00000098e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11f00000098f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11f0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11f0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11f0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11f0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11f0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11f0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11f0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11f0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11f0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11f0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11f00000099a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11f00000099b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11f00000099c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11f00000099d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11f00000099e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11f00000099f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11f0000009ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11f0000009cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11f0000009cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11f0000009cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11f0000009ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11f0000009cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11f0000009d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11f0000009d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11f0000009d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11f0000009d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11f0000009d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11f0000009d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11f0000009d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11f0000009d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11f0000009d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11f0000009d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11f0000009da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11f0000009db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11f0000009dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11f0000009dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11f0000009de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11f0000009df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT_CNT_INT"            ,	   0x11f0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
+	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11f0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
+	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11f00000090b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
+	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11f00000090a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
+	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11f0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
+	{"NPEI_PKT_DPADDR"             ,	   0x11f0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
+	{"NPEI_PKT_IN_BP"              ,	   0x11f00000086b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11f000000a000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11f000000a010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11f000000a020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11f000000a030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11f000000a040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11f000000a050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11f000000a060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11f000000a070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11f000000a080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11f000000a090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11f000000a0a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11f000000a0b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11f000000a0c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11f000000a0d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11f000000a0e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11f000000a0f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11f000000a100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11f000000a110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11f000000a120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11f000000a130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11f000000a140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11f000000a150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11f000000a160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11f000000a170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11f000000a180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11f000000a190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11f000000a1a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11f000000a1b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11f000000a1c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11f000000a1d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11f000000a1e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11f000000a1f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11f00000086a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11f00000091a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11f0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT_INSTR_ENB"          ,	   0x11f0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11f0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11f0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT_INT_LEVELS"         ,	   0x11f0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT_IPTR"               ,	   0x11f0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
+	{"NPEI_PKT_OUT_BMODE"          ,	   0x11f00000090d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
+	{"NPEI_PKT_OUT_ENB"            ,	   0x11f0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
+	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11f0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
+	{"NPEI_PKT_PCIE_PORT"          ,	   0x11f00000090e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
+	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11f0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
+	{"NPEI_PKT_SLIST_ES"           ,	   0x11f0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
+	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11f0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_SLIST_NS"           ,	   0x11f0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
+	{"NPEI_PKT_SLIST_ROR"          ,	   0x11f0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
+	{"NPEI_PKT_TIME_INT"           ,	   0x11f0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
+	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11f0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11f0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
+	{"NPEI_SCRATCH_1"              ,	   0x11f0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
+	{"NPEI_STATE1"                 ,	   0x11f0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
+	{"NPEI_STATE2"                 ,	   0x11f0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
+	{"NPEI_STATE3"                 ,	   0x11f0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
 	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	520},
 	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	521},
 	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	522},
 	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	523},
 	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	524},
-	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
-	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
-	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
-	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
-	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
-	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
-	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
-	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
-	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
-	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
-	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
-	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
-	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
-	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
-	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
-	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
-	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
-	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
-	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
-	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
-	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
-	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
-	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
-	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
-	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
-	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
-	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
-	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
-	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
-	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
-	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
-	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
-	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
-	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
-	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
-	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
-	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
-	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
-	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
-	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
-	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
-	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
-	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
-	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
-	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
-	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
-	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
-	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
-	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
-	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
-	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
-	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
-	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
-	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
-	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
-	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
-	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
-	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
-	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
-	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
-	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
-	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
-	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
-	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
-	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
-	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
-	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
-	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
-	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
-	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
-	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
-	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
-	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
-	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
-	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
-	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
-	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
-	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"NPEI_WINDOW_CTL"             ,	   0x11f0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
 	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
 	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
 	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
 	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
-	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
-	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
 	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
 	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
 	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
 	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
 	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
 	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
-	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
-	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
 	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
 	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
 	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
 	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
 	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
 	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
-	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
-	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
 	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
 	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
 	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
 	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
 	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
 	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
-	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
-	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
 	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
 	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
 	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
@@ -45770,62 +45777,62 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
 	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
 	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
-	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
-	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
 	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
 	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
 	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
 	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
 	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
 	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
-	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
-	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
 	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
 	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
 	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
 	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
 	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
 	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
-	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
-	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
 	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
 	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
 	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
 	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
 	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
 	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
-	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
-	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
-	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
-	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
-	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
-	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
-	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
-	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
 	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
 	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
 	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
 	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
 	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
 	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
-	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
-	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
 	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
 	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
 	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
 	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
 	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
 	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
-	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
-	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
 	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
 	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
 	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
 	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
 	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
 	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
-	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
-	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
 	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
 	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
 	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
@@ -45836,666 +45843,666 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
 	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
 	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
-	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
-	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
 	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
 	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
 	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
 	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
 	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
 	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
-	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
-	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
 	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
 	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
 	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
 	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
-	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
-	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
 	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
 	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
 	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
 	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
 	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
 	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
-	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
-	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
 	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
 	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
 	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
 	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
 	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
 	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
-	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
-	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
 	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
 	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
-	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
-	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
-	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
-	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
-	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
-	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
 	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
 	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
 	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
 	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
-	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS1_AN000_ADV_REG"          ,	   0x11800B8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS1_AN001_ADV_REG"          ,	   0x11800B8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS1_AN002_ADV_REG"          ,	   0x11800B8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS1_AN003_ADV_REG"          ,	   0x11800B8001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800B8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800B8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800B8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800B8001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800B8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800B8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800B8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800B8001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800B8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800B8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800B8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800B8001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS1_INT000_EN_REG"          ,	   0x11800B8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS1_INT001_EN_REG"          ,	   0x11800B8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS1_INT002_EN_REG"          ,	   0x11800B8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS1_INT003_EN_REG"          ,	   0x11800B8001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS1_INT000_REG"             ,	   0x11800B8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS1_INT001_REG"             ,	   0x11800B8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS1_INT002_REG"             ,	   0x11800B8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS1_INT003_REG"             ,	   0x11800B8001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800B8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800B8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800B8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800B8001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS1_LOG_ANL000_REG"         ,	   0x11800B8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS1_LOG_ANL001_REG"         ,	   0x11800B8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS1_LOG_ANL002_REG"         ,	   0x11800B8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS1_LOG_ANL003_REG"         ,	   0x11800B8001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS1_MISC000_CTL_REG"        ,	   0x11800B8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS1_MISC001_CTL_REG"        ,	   0x11800B8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS1_MISC002_CTL_REG"        ,	   0x11800B8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS1_MISC003_CTL_REG"        ,	   0x11800B8001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800B8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800B8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800B8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800B8001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS1_MR000_STATUS_REG"       ,	   0x11800B8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS1_MR001_STATUS_REG"       ,	   0x11800B8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS1_MR002_STATUS_REG"       ,	   0x11800B8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS1_MR003_STATUS_REG"       ,	   0x11800B8001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS1_RX000_STATES_REG"       ,	   0x11800B8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS1_RX001_STATES_REG"       ,	   0x11800B8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS1_RX002_STATES_REG"       ,	   0x11800B8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS1_RX003_STATES_REG"       ,	   0x11800B8001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS1_RX000_SYNC_REG"         ,	   0x11800B8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS1_RX001_SYNC_REG"         ,	   0x11800B8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS1_RX002_SYNC_REG"         ,	   0x11800B8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS1_RX003_SYNC_REG"         ,	   0x11800B8001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800B8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800B8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800B8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800B8001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800B8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800B8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800B8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800B8001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS1_TX000_STATES_REG"       ,	   0x11800B8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS1_TX001_STATES_REG"       ,	   0x11800B8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS1_TX002_STATES_REG"       ,	   0x11800B8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS1_TX003_STATES_REG"       ,	   0x11800B8001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800B8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800B8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800B8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800B8001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
-	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
-	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
-	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
-	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
-	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
-	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
-	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
-	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
-	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
-	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
-	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
-	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
-	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
-	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
-	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
-	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
-	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
-	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
-	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
-	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
-	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
-	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
-	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
-	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
-	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
-	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
-	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
-	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
-	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
-	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
-	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
-	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800b8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800b8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800b8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800b8001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800b8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800b8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800b8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800b8001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800b8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800b8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800b8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800b8001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800b8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800b8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800b8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800b8001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800b8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800b8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800b8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800b8001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT000_REG"             ,	   0x11800b8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT001_REG"             ,	   0x11800b8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT002_REG"             ,	   0x11800b8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT003_REG"             ,	   0x11800b8001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800b8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800b8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800b8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800b8001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800b8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800b8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800b8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800b8001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800b8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800b8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800b8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800b8001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800b8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800b8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800b8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800b8001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800b8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800b8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800b8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800b8001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800b8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800b8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800b8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800b8001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800b8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800b8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800b8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800b8001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800b8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800b8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800b8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800b8001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800b8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800b8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800b8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800b8001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800b8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800b8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800b8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800b8001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800b8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800b8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800b8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800b8001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800b8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800b8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800b8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800b8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800b8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800b8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCSX1_INT_REG"               ,	   0x11800b8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800b8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800b8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800b8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800b8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800b8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800b8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800b8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800b8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PESC0_BIST_STATUS"           ,	   0x11800c8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PESC1_BIST_STATUS"           ,	   0x11800d0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800c8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800d0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PESC0_CFG_RD"                ,	   0x11800c8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PESC1_CFG_RD"                ,	   0x11800d0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PESC0_CFG_WR"                ,	   0x11800c8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PESC1_CFG_WR"                ,	   0x11800d0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800c8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800d0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PESC0_CTL_STATUS"            ,	   0x11800c8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PESC1_CTL_STATUS"            ,	   0x11800d0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800c8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800d0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PESC0_DBG_INFO"              ,	   0x11800c8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PESC1_DBG_INFO"              ,	   0x11800d0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800c80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800d00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800c8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800d0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800c8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800d0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800c8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800d0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800c8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800d0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800c8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800c8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800c8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800c8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800d0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800d0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800d0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800d0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800c8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800c8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800c8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800c8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800d0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800d0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800d0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800d0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800c8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800d0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG16"               ,	   0x11800a0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG17"               ,	   0x11800a0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG18"               ,	   0x11800a0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG19"               ,	   0x11800a0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG16"               ,	   0x11800a0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG17"               ,	   0x11800a0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG18"               ,	   0x11800a0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG19"               ,	   0x11800a0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT16"             ,	   0x11800a0000d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT17"             ,	   0x11800a0000d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT18"             ,	   0x11800a0000da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT19"             ,	   0x11800a0000df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT16"             ,	   0x11800a0000d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT17"             ,	   0x11800a0000d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT18"             ,	   0x11800a0000da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT19"             ,	   0x11800a0000df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT16"             ,	   0x11800a0000d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT17"             ,	   0x11800a0000d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT18"             ,	   0x11800a0000db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT19"             ,	   0x11800a0000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT16"             ,	   0x11800a0000d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT17"             ,	   0x11800a0000d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT18"             ,	   0x11800a0000db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT19"             ,	   0x11800a0000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT16"             ,	   0x11800a0000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT17"             ,	   0x11800a0000d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT18"             ,	   0x11800a0000dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT19"             ,	   0x11800a0000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT16"             ,	   0x11800a0000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT17"             ,	   0x11800a0000d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT18"             ,	   0x11800a0000dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT19"             ,	   0x11800a0000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT16"             ,	   0x11800a0000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT17"             ,	   0x11800a0000d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT18"             ,	   0x11800a0000dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT19"             ,	   0x11800a0000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT16"             ,	   0x11800a0000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT17"             ,	   0x11800a0000d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT18"             ,	   0x11800a0000dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT19"             ,	   0x11800a0000e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT16"             ,	   0x11800a0000d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT17"             ,	   0x11800a0000d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT18"             ,	   0x11800a0000de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT19"             ,	   0x11800a0000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT16"             ,	   0x11800a0000d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT17"             ,	   0x11800a0000d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT18"             ,	   0x11800a0000de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT19"             ,	   0x11800a0000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800a0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800a0001c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800a0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800a0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800a0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800a0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800a0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800a0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800a0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800a0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800a0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800a0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
@@ -46522,9 +46529,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
 	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
 	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
 	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
@@ -46534,7 +46541,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	802},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	802},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	803},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	804},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	805},
@@ -46549,14 +46556,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	807},
 	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	808},
 	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	809},
-	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
-	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
 	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	811},
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	812},
 	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	813},
@@ -46572,22 +46579,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
 	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
 	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	817},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	818},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
@@ -46620,34 +46627,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
 	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
 	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
 	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
@@ -46693,175 +46700,175 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	886},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	887},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	888},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	889},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	892},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	896},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	899},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	886},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	887},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	888},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	889},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	892},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	896},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	899},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	940},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	941},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	942},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	943},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	944},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	945},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	946},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	947},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	948},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	949},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	950},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	951},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	952},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	953},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	940},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	941},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	942},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	943},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	944},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	945},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	946},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	947},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	948},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	949},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	950},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	951},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	952},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	953},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
 	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
 	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
 	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
 	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
-	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
 	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
 	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
 	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
@@ -48240,7 +48247,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"Q3FUS"                       ,	0,	34,	309,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_1024K"                  ,	34,	1,	309,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_512K"                   ,	35,	1,	309,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	309,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	309,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	3,	309,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_40_63"              ,	40,	24,	309,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
@@ -48312,7 +48319,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"INORDER_MWF"                 ,	13,	1,	327,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	327,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	327,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	327,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	327,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	327,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
@@ -48900,7 +48907,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"BAR2_ESX"                    ,	2,	2,	428,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	428,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	428,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	428,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	428,	"R/W",	0,	0,	1ull,	1ull},
@@ -48917,7 +48924,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"BAR2_ESX"                    ,	2,	2,	429,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	429,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	429,	"R/W",	0,	0,	1ull,	1ull},
@@ -49249,7 +49256,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"DMA1DBO"                     ,	5,	1,	451,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA2DBO"                     ,	6,	1,	451,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA3DBO"                     ,	7,	1,	451,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_8"                ,	8,	1,	451,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	451,	"RO",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	451,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA1FI"                      ,	10,	1,	451,	"RO",	0,	0,	0ull,	0ull},
 	{"DCNT0"                       ,	11,	1,	451,	"RO",	0,	0,	0ull,	0ull},
@@ -50973,9 +50980,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"BACK"                        ,	59,	4,	767,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	767,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	768,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	768,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	768,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	768,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	768,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	768,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	769,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	769,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	769,	"RO",	1,	0,	0,	0ull},
@@ -50983,7 +50990,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"SOP"                         ,	18,	1,	769,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	769,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	769,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	769,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	769,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	770,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	770,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	770,	"RO",	1,	0,	0,	0ull},
@@ -51016,7 +51023,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"CURR_SIZ"                    ,	0,	8,	776,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	8,	40,	776,	"RO",	1,	0,	0,	0ull},
 	{"NXT_INFLT"                   ,	48,	6,	776,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	776,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	776,	"RAZ",	1,	1,	0,	0},
 	{"QID_BASE"                    ,	0,	8,	777,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFF"                     ,	8,	4,	777,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFMAX"                  ,	12,	4,	777,	"RO",	1,	0,	0,	0ull},
@@ -51029,7 +51036,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"PREEMPTER"                   ,	28,	1,	777,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFTHS"                  ,	29,	4,	777,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFRES"                  ,	33,	4,	777,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	777,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	777,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	778,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	778,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	778,	"RO",	1,	0,	0,	0ull},
@@ -51041,35 +51048,35 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"S_TAIL"                      ,	4,	1,	779,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	779,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTEE"                   ,	6,	1,	779,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	779,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	779,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	779,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTER"                   ,	28,	1,	779,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	779,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	779,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	780,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	780,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	780,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	780,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	780,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	780,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	781,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	781,	"R/W",	1,	0,	0,	0ull},
 	{"BP_PORT"                     ,	10,	6,	781,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	781,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	781,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	781,	"R/W",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	61,	1,	781,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	781,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	781,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	782,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	782,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	782,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	782,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	782,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	783,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	783,	"RAZ",	1,	1,	0,	0},
 	{"RATE_PKT"                    ,	8,	24,	783,	"R/W",	1,	0,	0,	0ull},
 	{"RATE_WORD"                   ,	32,	19,	783,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	783,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	784,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	784,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	784,	"RAZ",	1,	1,	0,	0},
 	{"RATE_LIM"                    ,	8,	24,	784,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	784,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	784,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	785,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	785,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	785,	"WR0",	1,	0,	0,	0ull},
@@ -51081,9 +51088,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"S_TAIL"                      ,	63,	1,	785,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	786,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	786,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	786,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	786,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	786,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	786,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	786,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	787,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	2,	787,	"RO",	1,	0,	0,	0ull},
 	{"PRT_CTL"                     ,	6,	2,	787,	"RO",	1,	0,	0,	0ull},
@@ -51099,11 +51106,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"OUT_DAT"                     ,	32,	1,	787,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	33,	1,	787,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	34,	1,	787,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	787,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	787,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	788,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	788,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	788,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	788,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	788,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	788,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	789,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	790,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	791,	"RO",	0,	0,	0ull,	0ull},
@@ -51118,33 +51125,33 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"ENGINE7"                     ,	28,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE8"                     ,	32,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE9"                     ,	36,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_40_63"              ,	40,	24,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	793,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	10,	794,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	794,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	795,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	796,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	796,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	797,	"R/W",	0,	0,	2ull,	2ull},
 	{"MODE1"                       ,	3,	3,	797,	"R/W",	0,	0,	2ull,	2ull},
-	{"RESERVED_6_63"               ,	6,	58,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	797,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	798,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	799,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	799,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	799,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	800,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	800,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	800,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	801,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	801,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	801,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	801,	"RAZ",	1,	1,	0,	0},
 	{"ADR0"                        ,	0,	1,	802,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR1"                        ,	1,	1,	802,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND0"                       ,	2,	1,	802,	"RO",	0,	0,	0ull,	0ull},
@@ -51249,7 +51256,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"NCB_INB"                     ,	2,	2,	828,	"RO",	1,	0,	0,	0ull},
 	{"NCB_OUB"                     ,	4,	1,	828,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	5,	1,	828,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	828,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	828,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	829,	"R/W",	0,	1,	0ull,	0},
 	{"SIZE"                        ,	33,	13,	829,	"R/W",	0,	1,	0ull,	0},
 	{"POOL"                        ,	46,	3,	829,	"R/W",	0,	1,	0ull,	0},
@@ -51264,11 +51271,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"OWORDPV"                     ,	6,	1,	831,	"RO",	1,	1,	0,	0},
 	{"OWORDQV"                     ,	7,	1,	831,	"RO",	1,	1,	0,	0},
 	{"IWIDX"                       ,	8,	6,	831,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	831,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	831,	"RO",	1,	1,	0,	0},
 	{"IRIDX"                       ,	16,	6,	831,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	831,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	831,	"RO",	1,	1,	0,	0},
 	{"LOOP"                        ,	32,	25,	831,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	831,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	831,	"RO",	1,	1,	0,	0},
 	{"CWORD"                       ,	0,	64,	832,	"RO",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	833,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	833,	"RO",	1,	1,	0,	0},
@@ -51279,16 +51286,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"WC"                          ,	10,	1,	834,	"RO",	1,	1,	0,	0},
 	{"P"                           ,	11,	1,	834,	"RO",	1,	1,	0,	0},
 	{"Q"                           ,	12,	1,	834,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	834,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	834,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	15,	835,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	835,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	835,	"RAZ",	1,	1,	0,	0},
 	{"OWORDP"                      ,	0,	64,	836,	"RO",	1,	1,	0,	0},
 	{"OWORDQ"                      ,	0,	64,	837,	"RO",	1,	1,	0,	0},
 	{"RWORD"                       ,	0,	64,	838,	"RO",	1,	1,	0,	0},
 	{"N0CREDS"                     ,	0,	4,	839,	"RO",	0,	0,	8ull,	0ull},
 	{"N1CREDS"                     ,	4,	4,	839,	"RO",	0,	0,	8ull,	0ull},
 	{"POWCREDS"                    ,	8,	2,	839,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	839,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	839,	"RAZ",	1,	1,	0,	0},
 	{"FPACREDS"                    ,	12,	2,	839,	"RO",	0,	0,	1ull,	0ull},
 	{"WCCREDS"                     ,	14,	2,	839,	"RO",	0,	0,	0ull,	0ull},
 	{"NIWIDX0"                     ,	16,	4,	839,	"RO",	1,	1,	0,	0},
@@ -51302,12 +51309,12 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"NIRVAL7"                     ,	43,	5,	839,	"RO",	1,	1,	0,	0},
 	{"NIRQUE7"                     ,	48,	2,	839,	"RO",	1,	1,	0,	0},
 	{"NIROPC7"                     ,	50,	3,	839,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	839,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	839,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	840,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	840,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	56,	8,	840,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	0,	15,	841,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	841,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	841,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	842,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	842,	"RO",	1,	1,	0,	0},
 	{"FLAGS"                       ,	56,	8,	842,	"RO",	1,	1,	0,	0},
@@ -51317,16 +51324,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"Q"                           ,	17,	1,	843,	"RO",	1,	1,	0,	0},
 	{"INI"                         ,	18,	1,	843,	"RO",	1,	1,	0,	0},
 	{"EOD"                         ,	19,	1,	843,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	843,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	843,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	844,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	844,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	845,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	845,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	845,	"RAZ",	1,	1,	0,	0},
 	{"COEFFS"                      ,	0,	8,	846,	"R/W",	0,	0,	29ull,	29ull},
 	{"RESERVED_8_63"               ,	8,	56,	846,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INDEX"                       ,	0,	16,	847,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	16,	16,	847,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	847,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	847,	"RAZ",	1,	1,	0,	0},
 	{"MEM"                         ,	0,	1,	848,	"RO",	0,	0,	0ull,	0ull},
 	{"RRC"                         ,	1,	1,	848,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_2_63"               ,	2,	62,	848,	"RAZ",	1,	1,	0,	0},
@@ -51364,11 +51371,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"PENDING"                     ,	17,	1,	854,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	854,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	855,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	855,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	855,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	855,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	855,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	855,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	855,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	855,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	855,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	856,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	856,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	856,	"RO",	1,	0,	0,	0ull},
@@ -51376,32 +51383,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	857,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	857,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	857,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	857,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	857,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	858,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	858,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	858,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	858,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	858,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	859,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	859,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	859,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	859,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	859,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	859,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	860,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	860,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	860,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	860,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	860,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	861,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	861,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	861,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	862,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	862,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	862,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	863,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	863,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	863,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	864,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	864,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	864,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	864,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	865,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	865,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	865,	"RO",	0,	0,	0ull,	0ull},
@@ -51422,9 +51429,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"RPTR"                        ,	8,	8,	867,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	867,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	868,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	868,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	868,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	868,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	868,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	868,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	868,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	869,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	869,	"RAZ",	0,	0,	0ull,	0ull},
@@ -52099,27 +52106,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
 	{"TXRISETUNE"                  ,	63,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
 	{"ZIP_CTL"                     ,	0,	4,	961,	"RO",	1,	0,	0,	0ull},
 	{"ZIP_CORE"                    ,	4,	27,	961,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_31_63"              ,	31,	33,	961,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	961,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	962,	"R/W",	0,	0,	0ull,	0ull},
 	{"SIZE"                        ,	33,	13,	962,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	46,	3,	962,	"R/W",	0,	0,	0ull,	0ull},
 	{"DWB"                         ,	49,	9,	962,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_58_63"              ,	58,	6,	962,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	962,	"RAZ",	1,	1,	0,	0},
 	{"RESET"                       ,	0,	1,	963,	"RAZ",	0,	0,	0ull,	0ull},
 	{"FORCECLK"                    ,	1,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	963,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	963,	"RAZ",	1,	1,	0,	0},
 	{"DISABLED"                    ,	0,	1,	964,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_7"                ,	1,	7,	964,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	964,	"RAZ",	1,	1,	0,	0},
 	{"CTXSIZE"                     ,	8,	12,	964,	"RO",	0,	0,	1536ull,	1536ull},
 	{"ONFSIZE"                     ,	20,	12,	964,	"RO",	0,	0,	512ull,	512ull},
 	{"DEPTH"                       ,	32,	16,	964,	"RO",	0,	0,	31744ull,	31744ull},
-	{"RESERVED_48_63"              ,	48,	16,	964,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	964,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	14,	965,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_14_63"              ,	14,	50,	965,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	965,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	966,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	966,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	966,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	967,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	967,	"RAZ",	1,	1,	0,	0},
 	{NULL,0,0,0,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
@@ -52709,24 +52716,24 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800B0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800b0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800b0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800b0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800b0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800b0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_PRT_LOOP"               ,	   0x11800b0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800b0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800b0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800b0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800b0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800b0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800b0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800b0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800b0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800b0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800b0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800b0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800b0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
@@ -52741,17 +52748,17 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
 	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
@@ -52772,21 +52779,21 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
 	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
 	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
-	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"DBG_DATA"                    ,	   0x11f00000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
@@ -52795,11 +52802,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
 	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
@@ -52816,12 +52823,12 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
 	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
@@ -52864,27 +52871,27 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
@@ -52897,95 +52904,95 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
 	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
-	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
 	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
-	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_TX_CLK_MSK000"          ,	   0x1180008000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_TX_CLK_MSK001"          ,	   0x1180008000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
 	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
@@ -53003,8 +53010,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
-	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
-	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
@@ -53017,71 +53024,71 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
 	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
 	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
@@ -53090,11 +53097,11 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
 	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
@@ -53106,13 +53113,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
-	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
@@ -53129,15 +53136,15 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
-	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
@@ -53158,7 +53165,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
@@ -53181,209 +53188,209 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
 	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
 	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
 	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
 	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
-	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT4"                    ,	   0x10700000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT5"                    ,	   0x10700000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT6"                    ,	   0x10700000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT7"                    ,	   0x10700000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT8"                    ,	   0x10700000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
 	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
 	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
-	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
-	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
-	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
-	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
-	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
-	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
-	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
-	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
-	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
-	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
-	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
-	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
-	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
-	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
-	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
-	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
-	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
-	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
-	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
-	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
-	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
-	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
-	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
-	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	300},
-	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
-	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
-	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
-	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
-	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
-	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
-	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
-	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
-	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
-	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
-	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
-	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
-	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	308},
-	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
-	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
-	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
-	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
-	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
-	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
-	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
-	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
-	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
-	{"PCI_BIST_REG"                ,	   0x11F00000011C0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	317},
-	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
-	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
-	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
-	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
-	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
-	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
-	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
-	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
-	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
-	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
-	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
-	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
-	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
-	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
-	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
-	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
-	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
-	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
-	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
-	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
-	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
-	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
-	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
-	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
-	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
-	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
-	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
-	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
-	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
-	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
-	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	348},
-	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	349},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11f0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11f0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11f00000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11f00000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_BIST_STATUS"             ,	   0x11f00000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11f00000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_COMP_CTL"                ,	   0x11f0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"NPI_CTL_STATUS"              ,	   0x11f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"NPI_DBG_SELECT"              ,	   0x11f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"NPI_DMA_CONTROL"             ,	   0x11f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_HIGHP_DBELL"             ,	   0x11f0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11f0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_INPUT_CONTROL"           ,	   0x11f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_INT_ENB"                 ,	   0x11f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_INT_SUM"                 ,	   0x11f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_LOWP_DBELL"              ,	   0x11f0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11f0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MSI_RCV"                 ,	   0x11f0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	300},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11f0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11f00000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	308},
+	{"NPI_PCI_READ_CMD"            ,	   0x11f0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11f00000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11f0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11f00000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_SIZE_INPUT0"             ,	   0x11f0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_SIZE_INPUT1"             ,	   0x11f0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_WIN_READ_TO"             ,	   0x11f00000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"PCI_BAR1_INDEX0"             ,	   0x11f0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX1"             ,	   0x11f0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX2"             ,	   0x11f0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX3"             ,	   0x11f000000110cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX4"             ,	   0x11f0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX5"             ,	   0x11f0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX6"             ,	   0x11f0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX7"             ,	   0x11f000000111cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX8"             ,	   0x11f0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX9"             ,	   0x11f0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX10"            ,	   0x11f0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX11"            ,	   0x11f000000112cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX12"            ,	   0x11f0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX13"            ,	   0x11f0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX14"            ,	   0x11f0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX15"            ,	   0x11f000000113cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX16"            ,	   0x11f0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX17"            ,	   0x11f0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX18"            ,	   0x11f0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX19"            ,	   0x11f000000114cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX20"            ,	   0x11f0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX21"            ,	   0x11f0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX22"            ,	   0x11f0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX23"            ,	   0x11f000000115cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX24"            ,	   0x11f0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX25"            ,	   0x11f0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX26"            ,	   0x11f0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX27"            ,	   0x11f000000116cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX28"            ,	   0x11f0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX29"            ,	   0x11f0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX30"            ,	   0x11f0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX31"            ,	   0x11f000000117cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BIST_REG"                ,	   0x11f00000011c0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	317},
+	{"PCI_CFG00"                   ,	   0x11f0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
+	{"PCI_CFG01"                   ,	   0x11f0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
+	{"PCI_CFG02"                   ,	   0x11f0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
+	{"PCI_CFG03"                   ,	   0x11f000000180cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
+	{"PCI_CFG04"                   ,	   0x11f0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
+	{"PCI_CFG05"                   ,	   0x11f0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
+	{"PCI_CFG06"                   ,	   0x11f0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
+	{"PCI_CFG07"                   ,	   0x11f000000181cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG08"                   ,	   0x11f0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG09"                   ,	   0x11f0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG10"                   ,	   0x11f0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG11"                   ,	   0x11f000000182cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG12"                   ,	   0x11f0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG13"                   ,	   0x11f0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG15"                   ,	   0x11f000000183cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG16"                   ,	   0x11f0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG17"                   ,	   0x11f0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG18"                   ,	   0x11f0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CFG19"                   ,	   0x11f000000184cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
+	{"PCI_CFG20"                   ,	   0x11f0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
+	{"PCI_CFG21"                   ,	   0x11f0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
+	{"PCI_CFG22"                   ,	   0x11f0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
+	{"PCI_CFG56"                   ,	   0x11f00000018e0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
+	{"PCI_CFG57"                   ,	   0x11f00000018e4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
+	{"PCI_CFG58"                   ,	   0x11f00000018e8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
+	{"PCI_CFG59"                   ,	   0x11f00000018ecull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
+	{"PCI_CFG60"                   ,	   0x11f00000018f0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
+	{"PCI_CFG61"                   ,	   0x11f00000018f4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
+	{"PCI_CFG62"                   ,	   0x11f00000018f8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
+	{"PCI_CFG63"                   ,	   0x11f00000018fcull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
+	{"PCI_CNT_REG"                 ,	   0x11f00000011b8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	348},
+	{"PCI_CTL_STATUS_2"            ,	   0x11f000000118cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	349},
 	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
 	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
-	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
-	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
-	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
-	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
-	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
-	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
+	{"PCI_DMA_CNT0"                ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
+	{"PCI_DMA_CNT1"                ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
+	{"PCI_DMA_INT_LEV0"            ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
+	{"PCI_DMA_INT_LEV1"            ,	              0xacull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
+	{"PCI_DMA_TIME0"               ,	              0xb0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
+	{"PCI_DMA_TIME1"               ,	              0xb4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
 	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	354},
-	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	354},
+	{"PCI_INSTR_COUNT1"            ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCI,	32,	354},
 	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	355},
-	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
+	{"PCI_INT_ENB2"                ,	   0x11f00000011a0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
 	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	357},
-	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	358},
-	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_INT_SUM2"                ,	   0x11f0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	358},
+	{"PCI_MSI_RCV"                 ,	              0xf0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
 	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
 	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
 	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	361},
 	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	361},
 	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	362},
 	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	362},
-	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
-	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
-	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	364},
-	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	365},
-	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	366},
-	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
-	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	368},
-	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	369},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
+	{"PCI_READ_CMD_6"              ,	   0x11f0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	364},
+	{"PCI_READ_CMD_C"              ,	   0x11f0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	365},
+	{"PCI_READ_CMD_E"              ,	   0x11f0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	366},
+	{"PCI_READ_TIMEOUT"            ,	   0x11f00000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCI_SCM_REG"                 ,	   0x11f00000011a8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	368},
+	{"PCI_TSR_REG"                 ,	   0x11f00000011b0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	369},
 	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	370},
 	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	371},
 	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	372},
@@ -53392,354 +53399,354 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
-	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM3_DMA_CFG"                ,	   0x107000001c018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
 	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
-	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM3_INT_ENA"                ,	   0x107000001c020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
 	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
-	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM3_INT_SUM"                ,	   0x107000001c028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
 	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
-	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM3_RXADDR"                 ,	   0x107000001c068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
 	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
 	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
 	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
-	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
-	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
-	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
-	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
-	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
-	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
-	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
-	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
-	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
-	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_RXCNT"                  ,	   0x107000001c060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM3_RXMSK0"                 ,	   0x107000001c0c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_RXMSK1"                 ,	   0x107000001c0c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_RXMSK2"                 ,	   0x107000001c0d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM3_RXMSK3"                 ,	   0x107000001c0d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_RXMSK4"                 ,	   0x107000001c0e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM3_RXMSK5"                 ,	   0x107000001c0e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_RXMSK6"                 ,	   0x107000001c0f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_RXMSK7"                 ,	   0x107000001c0f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
 	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
-	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_RXSTART"                ,	   0x107000001c058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
 	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
 	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
 	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
-	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM3_TDM_CFG"                ,	   0x107000001c010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
 	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
 	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
 	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
-	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM3_TDM_DBG"                ,	   0x107000001c030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
 	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
 	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
 	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
-	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM3_TXADDR"                 ,	   0x107000001c050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
 	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
 	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
 	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
-	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM3_TXCNT"                  ,	   0x107000001c048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
 	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
 	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
 	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
-	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM3_TXMSK0"                 ,	   0x107000001c080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
 	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
-	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM3_TXMSK1"                 ,	   0x107000001c088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
 	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
-	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM3_TXMSK2"                 ,	   0x107000001c090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
 	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
 	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
-	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
-	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
-	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
-	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
-	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
-	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
-	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
-	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
-	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
-	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
-	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
-	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
-	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
-	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
-	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
-	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
-	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM3_TXMSK3"                 ,	   0x107000001c098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM3_TXMSK4"                 ,	   0x107000001c0a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM3_TXMSK5"                 ,	   0x107000001c0a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM3_TXMSK6"                 ,	   0x107000001c0b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM3_TXMSK7"                 ,	   0x107000001c0b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
 	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
-	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM3_TXSTART"                ,	   0x107000001c040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
 	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
 	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
 	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
 	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
 	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
 	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
-	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
@@ -53761,9 +53768,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
 	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
 	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
 	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
@@ -53771,7 +53778,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	471},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	472},
@@ -53789,22 +53796,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	477},
 	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
 	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
@@ -53837,34 +53844,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
 	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
 	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
 	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
@@ -53882,147 +53889,147 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	560},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	560},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
 	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
@@ -54900,7 +54907,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"Q3FUS"                       ,	0,	34,	198,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_64K"                    ,	34,	1,	198,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_32K"                    ,	35,	1,	198,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	198,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	3,	198,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_40_63"              ,	40,	24,	198,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
@@ -56310,9 +56317,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"BACK"                        ,	59,	4,	441,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	441,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	442,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	442,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	442,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	442,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	443,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	443,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	443,	"RO",	1,	0,	0,	0ull},
@@ -56320,7 +56327,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"SOP"                         ,	18,	1,	443,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	443,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	443,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	443,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	443,	"RO",	1,	0,	0,	0ull},
 	{"SIZE"                        ,	0,	16,	444,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	444,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	444,	"RO",	1,	0,	0,	0ull},
@@ -56359,7 +56366,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"CURR_SIZ"                    ,	19,	16,	449,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	35,	29,	449,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	0,	11,	450,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_11_63"              ,	11,	53,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	450,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	451,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	451,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	451,	"RO",	1,	0,	0,	0ull},
@@ -56370,13 +56377,13 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"STATIC_Q"                    ,	3,	1,	452,	"RO",	1,	0,	0,	0ull},
 	{"S_TAIL"                      ,	4,	1,	452,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	452,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	452,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	452,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_28_63"              ,	28,	36,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	452,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	453,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	453,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	453,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	453,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	453,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	453,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	454,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	454,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	454,	"WR0",	1,	0,	0,	0ull},
@@ -56388,9 +56395,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"S_TAIL"                      ,	63,	1,	454,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	455,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	455,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	455,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	455,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	455,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	456,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	4,	456,	"RO",	1,	0,	0,	0ull},
 	{"PRT_QSB"                     ,	8,	3,	456,	"RO",	1,	0,	0,	0ull},
@@ -56405,11 +56412,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"OUT_CRC"                     ,	30,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	31,	1,	456,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	32,	1,	456,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_33_63"              ,	33,	31,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	456,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	457,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	457,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	457,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	457,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	457,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	458,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	459,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	460,	"RO",	0,	0,	0ull,	0ull},
@@ -56417,27 +56424,27 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"PARITY"                      ,	0,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	462,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	463,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	463,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
 	{"MODE1"                       ,	3,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	464,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	465,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	465,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	466,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	466,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	467,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	468,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	468,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	468,	"RAZ",	1,	1,	0,	0},
 	{"ADR"                         ,	0,	1,	469,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND"                        ,	1,	1,	469,	"RO",	0,	0,	0ull,	0ull},
 	{"NBR0"                        ,	2,	1,	469,	"RO",	0,	0,	0ull,	0ull},
@@ -56569,11 +56576,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"PENDING"                     ,	17,	1,	495,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	495,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	496,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	496,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	496,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	496,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	496,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	496,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	497,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	497,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	497,	"RO",	1,	0,	0,	0ull},
@@ -56581,32 +56588,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	498,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	498,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	498,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	498,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	498,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	499,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	499,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	499,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	499,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	500,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	500,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	500,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	501,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	501,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	501,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	501,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	501,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	502,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	502,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	502,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	503,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	504,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	504,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	505,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	505,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	1,	0,	0},
 	{"INEPINT"                     ,	0,	16,	506,	"RO",	0,	0,	0ull,	0ull},
 	{"OUTEPINT"                    ,	16,	16,	506,	"RO",	0,	0,	0ull,	0ull},
 	{"INEPMSK"                     ,	0,	16,	507,	"R/W",	0,	0,	0ull,	0ull},
@@ -57626,83 +57633,83 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
 	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	985,	1,	2414},
 	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	986,	2,	2415},
 	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	987,	2,	2417},
-	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	988,	2,	2419},
-	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	989,	24,	2421},
-	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	990,	4,	2445},
-	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	991,	5,	2449},
-	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	992,	5,	2454},
-	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	993,	2,	2459},
-	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	994,	1,	2461},
-	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	995,	1,	2462},
-	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	996,	5,	2463},
-	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	997,	2,	2468},
-	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	998,	1,	2470},
-	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	999,	1,	2471},
-	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1000,	4,	2472},
-	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1001,	2,	2476},
-	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1002,	2,	2478},
-	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1003,	1,	2480},
-	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1004,	1,	2481},
-	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1005,	2,	2482},
-	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1006,	3,	2484},
-	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1007,	2,	2487},
-	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1008,	2,	2489},
-	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1009,	4,	2491},
-	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1010,	10,	2495},
-	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1011,	12,	2505},
-	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1012,	7,	2517},
-	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1013,	2,	2524},
-	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1014,	1,	2526},
-	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1015,	2,	2527},
-	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1016,	7,	2529},
-	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1017,	11,	2536},
-	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1018,	19,	2547},
-	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1019,	11,	2566},
-	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1020,	17,	2577},
-	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1021,	12,	2594},
-	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1022,	22,	2606},
-	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1023,	3,	2628},
-	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1024,	3,	2631},
-	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1025,	1,	2634},
-	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1026,	1,	2635},
-	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1027,	1,	2636},
-	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1028,	1,	2637},
-	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1029,	3,	2638},
-	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1030,	14,	2641},
-	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1031,	14,	2655},
-	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1032,	14,	2669},
-	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1033,	9,	2683},
-	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1034,	9,	2692},
-	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1035,	6,	2701},
-	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1036,	1,	2707},
-	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1037,	1,	2708},
-	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1038,	1,	2709},
-	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1039,	1,	2710},
-	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1040,	2,	2711},
-	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1041,	1,	2713},
-	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1042,	6,	2714},
-	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1043,	6,	2720},
-	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1044,	13,	2726},
-	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1045,	5,	2739},
-	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1046,	8,	2744},
-	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1047,	19,	2752},
-	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1048,	3,	2771},
-	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1049,	1,	2774},
-	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1050,	1,	2775},
-	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1051,	3,	2776},
-	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1052,	3,	2779},
-	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1053,	3,	2782},
-	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1054,	4,	2785},
-	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1055,	4,	2789},
-	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1056,	4,	2793},
-	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1057,	7,	2797},
-	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1058,	5,	2804},
-	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1059,	5,	2809},
-	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1060,	4,	2814},
-	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1061,	4,	2818},
-	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1062,	4,	2822},
-	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1063,	1,	2826},
-	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1064,	1,	2827},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	988,	2,	2419},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	989,	24,	2421},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	990,	4,	2445},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	991,	5,	2449},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	992,	5,	2454},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	993,	2,	2459},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	994,	1,	2461},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	995,	1,	2462},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	996,	5,	2463},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	997,	2,	2468},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	998,	1,	2470},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	999,	1,	2471},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1000,	4,	2472},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1001,	2,	2476},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1002,	2,	2478},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1003,	1,	2480},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1004,	1,	2481},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1005,	2,	2482},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1006,	3,	2484},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1007,	2,	2487},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1008,	2,	2489},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1009,	4,	2491},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1010,	10,	2495},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1011,	12,	2505},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1012,	7,	2517},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1013,	2,	2524},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1014,	1,	2526},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1015,	2,	2527},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1016,	7,	2529},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1017,	11,	2536},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1018,	19,	2547},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1019,	11,	2566},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1020,	17,	2577},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1021,	12,	2594},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1022,	22,	2606},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1023,	3,	2628},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1024,	3,	2631},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1025,	1,	2634},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1026,	1,	2635},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1027,	1,	2636},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1028,	1,	2637},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1029,	3,	2638},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1030,	14,	2641},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1031,	14,	2655},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1032,	14,	2669},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1033,	9,	2683},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1034,	9,	2692},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1035,	6,	2701},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1036,	1,	2707},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1037,	1,	2708},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1038,	1,	2709},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1039,	1,	2710},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1040,	2,	2711},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1041,	1,	2713},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1042,	6,	2714},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1043,	6,	2720},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1044,	13,	2726},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1045,	5,	2739},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1046,	8,	2744},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1047,	19,	2752},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1048,	3,	2771},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1049,	1,	2774},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1050,	1,	2775},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1051,	3,	2776},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1052,	3,	2779},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1053,	3,	2782},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1054,	4,	2785},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1055,	4,	2789},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1056,	4,	2793},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1057,	7,	2797},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1058,	5,	2804},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1059,	5,	2809},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1060,	4,	2814},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1061,	4,	2818},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1062,	4,	2822},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1063,	1,	2826},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1064,	1,	2827},
 	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1065,	2,	2828},
 	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1067,	24,	2830},
 	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1069,	4,	2854},
@@ -57797,398 +57804,398 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
 	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1277,	4,	3406},
 	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1281,	5,	3410},
 	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1285,	8,	3415},
-	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1287,	2,	3423},
-	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1289,	5,	3425},
-	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1291,	10,	3430},
-	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1293,	2,	3440},
-	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	7,	3442},
-	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1297,	7,	3449},
-	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	6,	3456},
-	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1301,	5,	3462},
-	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1303,	5,	3467},
-	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	3,	3472},
-	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1307,	6,	3475},
-	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1309,	9,	3481},
-	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1311,	3,	3490},
-	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1313,	9,	3493},
-	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1315,	13,	3502},
-	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1317,	15,	3515},
-	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1319,	2,	3530},
-	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1321,	2,	3532},
-	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	2,	3534},
-	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	16,	3536},
-	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	2,	3552},
-	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	32,	3554},
-	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1331,	32,	3586},
-	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1333,	5,	3618},
-	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1335,	2,	3623},
-	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	2,	3625},
-	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1339,	2,	3627},
-	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1341,	2,	3629},
-	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1349,	2,	3631},
-	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1357,	8,	3633},
-	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1359,	2,	3641},
-	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1360,	4,	3643},
-	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1364,	16,	3647},
-	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1365,	16,	3663},
-	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1366,	3,	3679},
-	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1368,	8,	3682},
-	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1369,	22,	3690},
-	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1370,	6,	3712},
-	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	14,	3718},
-	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	14,	3732},
-	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	2,	3746},
-	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	28,	3748},
-	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1382,	25,	3776},
-	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1390,	2,	3801},
-	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1454,	4,	3803},
-	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1462,	9,	3807},
-	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1470,	2,	3816},
-	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1471,	2,	3818},
-	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1472,	2,	3820},
-	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1480,	2,	3822},
-	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1488,	2,	3824},
-	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1496,	2,	3826},
-	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1504,	2,	3828},
-	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1512,	2,	3830},
-	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1520,	2,	3832},
-	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1528,	2,	3834},
-	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1536,	2,	3836},
-	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1544,	2,	3838},
-	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1552,	2,	3840},
-	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1553,	2,	3842},
-	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1561,	2,	3844},
-	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1569,	2,	3846},
-	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1577,	2,	3848},
-	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1641,	2,	3850},
-	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1642,	3,	3852},
-	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1643,	3,	3855},
-	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1644,	2,	3858},
-	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1645,	2,	3860},
-	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1646,	4,	3862},
-	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1647,	5,	3866},
-	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1648,	4,	3871},
-	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1649,	8,	3875},
-	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1650,	4,	3883},
-	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1651,	5,	3887},
-	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1652,	1,	3892},
-	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1653,	5,	3893},
-	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1654,	1,	3898},
-	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1655,	13,	3899},
-	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1656,	4,	3912},
-	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1657,	13,	3916},
-	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1658,	6,	3929},
-	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1659,	9,	3935},
-	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	4,	3944},
-	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1661,	7,	3948},
-	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1662,	5,	3955},
-	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1663,	5,	3960},
-	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1664,	4,	3965},
-	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1665,	9,	3969},
-	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1666,	5,	3978},
-	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1667,	16,	3983},
-	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1668,	4,	3999},
-	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1669,	1,	4003},
-	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1670,	1,	4004},
-	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1671,	1,	4005},
-	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1672,	1,	4006},
-	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	1673,	11,	4007},
-	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1674,	2,	4018},
-	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1675,	4,	4020},
-	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1676,	5,	4024},
-	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1677,	3,	4029},
-	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1678,	4,	4032},
-	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1679,	2,	4036},
-	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1680,	3,	4038},
-	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1681,	3,	4041},
-	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1682,	12,	4044},
-	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1683,	2,	4056},
-	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1684,	13,	4058},
-	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1685,	3,	4071},
-	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1686,	2,	4074},
-	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1694,	2,	4076},
-	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1695,	2,	4078},
-	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1696,	2,	4080},
-	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1697,	2,	4082},
-	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1705,	2,	4084},
-	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1706,	2,	4086},
-	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1707,	2,	4088},
-	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1708,	10,	4090},
-	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1712,	5,	4100},
-	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1720,	10,	4105},
-	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1728,	2,	4115},
-	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1729,	2,	4117},
-	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1730,	2,	4119},
-	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1738,	3,	4121},
-	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1739,	6,	4124},
-	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1755,	5,	4130},
-	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1756,	7,	4135},
-	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1772,	2,	4142},
-	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	1,	4144},
-	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1789,	1,	4145},
-	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1790,	1,	4146},
-	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1791,	5,	4147},
-	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1792,	5,	4152},
-	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1793,	4,	4157},
-	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1794,	10,	4161},
-	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1795,	1,	4171},
-	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	3,	4172},
-	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1797,	7,	4175},
-	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1798,	2,	4182},
-	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1799,	1,	4184},
-	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1800,	1,	4185},
-	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1801,	1,	4186},
-	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1802,	18,	4187},
-	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1803,	3,	4205},
-	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	2,	4208},
-	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1805,	3,	4210},
-	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	7,	4213},
-	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1807,	2,	4220},
-	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	2,	4222},
-	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1809,	2,	4224},
-	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1810,	3,	4226},
-	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1811,	3,	4229},
-	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1812,	7,	4232},
-	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1813,	10,	4239},
-	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1815,	6,	4249},
-	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1817,	2,	4255},
-	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	4,	4257},
-	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	4,	4261},
-	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	6,	4265},
-	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	3,	4271},
-	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	5,	4274},
-	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	4,	4279},
-	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	6,	4283},
-	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	4,	4289},
-	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	2,	4293},
-	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1830,	4,	4295},
-	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	2,	4299},
-	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1832,	3,	4301},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	4,	4304},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	12,	4308},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	3,	4320},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1836,	5,	4323},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	2,	4328},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	2,	4330},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1839,	18,	4332},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	12,	4350},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1841,	6,	4362},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1842,	5,	4368},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1843,	1,	4373},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1844,	2,	4374},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1845,	2,	4376},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1846,	18,	4378},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1847,	12,	4396},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1848,	6,	4408},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1849,	2,	4414},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1850,	2,	4416},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1851,	18,	4418},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1852,	12,	4436},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1853,	6,	4448},
-	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1854,	2,	4454},
-	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1856,	2,	4456},
-	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1858,	8,	4458},
-	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1860,	11,	4466},
-	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1862,	15,	4477},
-	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1872,	8,	4492},
-	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1882,	8,	4500},
-	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1884,	4,	4508},
-	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1894,	15,	4512},
-	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1904,	6,	4527},
-	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1914,	6,	4533},
-	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1916,	4,	4539},
-	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1926,	2,	4543},
-	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1934,	6,	4545},
-	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1936,	4,	4551},
-	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1938,	1,	4555},
-	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1940,	1,	4556},
-	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1942,	1,	4557},
-	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1944,	7,	4558},
-	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1946,	1,	4565},
-	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1948,	14,	4566},
-	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1950,	10,	4580},
-	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1952,	14,	4590},
-	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1954,	32,	4604},
-	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1956,	32,	4636},
-	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1958,	2,	4668},
-	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1960,	4,	4670},
-	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1962,	13,	4674},
-	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1964,	10,	4687},
-	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1966,	10,	4697},
-	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1968,	2,	4707},
-	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1970,	6,	4709},
-	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1972,	5,	4715},
-	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1974,	6,	4720},
-	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1976,	5,	4726},
-	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1978,	1,	4731},
-	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1980,	13,	4732},
-	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1982,	2,	4745},
-	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1984,	2,	4747},
-	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1986,	11,	4749},
-	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2002,	3,	4760},
-	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2004,	12,	4763},
-	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2020,	12,	4775},
-	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2036,	6,	4787},
-	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2052,	4,	4793},
-	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2068,	2,	4797},
-	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2070,	2,	4799},
-	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2072,	15,	4801},
-	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2074,	2,	4816},
-	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2076,	3,	4818},
-	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2078,	1,	4821},
-	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2094,	6,	4822},
-	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2096,	8,	4828},
-	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2098,	15,	4836},
-	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2100,	6,	4851},
-	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2102,	2,	4857},
-	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2104,	2,	4859},
-	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2106,	2,	4861},
-	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2108,	2,	4863},
-	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2110,	2,	4865},
-	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2112,	2,	4867},
-	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2114,	2,	4869},
-	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2116,	2,	4871},
-	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2118,	2,	4873},
-	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2120,	2,	4875},
-	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2122,	2,	4877},
-	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2124,	2,	4879},
-	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2126,	2,	4881},
-	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2128,	2,	4883},
-	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2130,	2,	4885},
-	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2132,	2,	4887},
-	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2134,	7,	4889},
-	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2136,	34,	4896},
-	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2138,	34,	4930},
-	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2140,	35,	4964},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1286,	2,	3423},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1287,	5,	3425},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1288,	10,	3430},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1289,	2,	3440},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1290,	7,	3442},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1291,	7,	3449},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1292,	6,	3456},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1293,	5,	3462},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1294,	5,	3467},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	3,	3472},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1296,	6,	3475},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1297,	9,	3481},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1298,	3,	3490},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	9,	3493},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1300,	13,	3502},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1302,	15,	3515},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1304,	2,	3530},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1306,	2,	3532},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1308,	2,	3534},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1310,	16,	3536},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1312,	2,	3552},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1314,	32,	3554},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1316,	32,	3586},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1318,	5,	3618},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1320,	2,	3623},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1322,	2,	3625},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1324,	2,	3627},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1326,	2,	3629},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1334,	2,	3631},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1342,	8,	3633},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1344,	2,	3641},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1345,	4,	3643},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1349,	16,	3647},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1350,	16,	3663},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1351,	3,	3679},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1353,	8,	3682},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1354,	22,	3690},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1355,	6,	3712},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1356,	14,	3718},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1357,	14,	3732},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1358,	2,	3746},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1359,	28,	3748},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1367,	25,	3776},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1375,	2,	3801},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1439,	4,	3803},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1447,	9,	3807},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1455,	2,	3816},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1456,	2,	3818},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1457,	2,	3820},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1465,	2,	3822},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1473,	2,	3824},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1481,	2,	3826},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1489,	2,	3828},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1497,	2,	3830},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1505,	2,	3832},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1513,	2,	3834},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1521,	2,	3836},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1529,	2,	3838},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1537,	2,	3840},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1538,	2,	3842},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1546,	2,	3844},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1554,	2,	3846},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1562,	2,	3848},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1626,	2,	3850},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1627,	3,	3852},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1628,	3,	3855},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1629,	2,	3858},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1630,	2,	3860},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1631,	4,	3862},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1632,	5,	3866},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1633,	4,	3871},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1634,	8,	3875},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1635,	4,	3883},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1636,	5,	3887},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1637,	1,	3892},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1638,	5,	3893},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1639,	1,	3898},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1640,	13,	3899},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1641,	4,	3912},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1642,	13,	3916},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1643,	6,	3929},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1644,	9,	3935},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1645,	4,	3944},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1646,	7,	3948},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1647,	5,	3955},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1648,	5,	3960},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1649,	4,	3965},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1650,	9,	3969},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1651,	5,	3978},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1652,	16,	3983},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1653,	4,	3999},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1654,	1,	4003},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1655,	1,	4004},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1656,	1,	4005},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1657,	1,	4006},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	1658,	11,	4007},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1659,	2,	4018},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	4,	4020},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1661,	5,	4024},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1662,	3,	4029},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1663,	4,	4032},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1664,	2,	4036},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1665,	3,	4038},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1666,	3,	4041},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1667,	12,	4044},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1668,	2,	4056},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1669,	13,	4058},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1670,	3,	4071},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1671,	2,	4074},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1679,	2,	4076},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1680,	2,	4078},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1681,	2,	4080},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1682,	2,	4082},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1690,	2,	4084},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1691,	2,	4086},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1692,	2,	4088},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1693,	10,	4090},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1697,	5,	4100},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1705,	10,	4105},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1713,	2,	4115},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1714,	2,	4117},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1715,	2,	4119},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1723,	3,	4121},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1724,	6,	4124},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1740,	5,	4130},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1741,	7,	4135},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1757,	2,	4142},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1773,	1,	4144},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1774,	1,	4145},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1775,	1,	4146},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1776,	5,	4147},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1777,	5,	4152},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1778,	4,	4157},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1779,	10,	4161},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1780,	1,	4171},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1781,	3,	4172},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1782,	7,	4175},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1783,	2,	4182},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1784,	1,	4184},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1785,	1,	4185},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1786,	1,	4186},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1787,	18,	4187},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	3,	4205},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1789,	2,	4208},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1790,	3,	4210},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1791,	7,	4213},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1792,	2,	4220},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1793,	2,	4222},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1794,	2,	4224},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1795,	3,	4226},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	3,	4229},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1797,	7,	4232},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1798,	10,	4239},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1800,	6,	4249},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1802,	2,	4255},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	4,	4257},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	4,	4261},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	6,	4265},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1809,	3,	4271},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1810,	5,	4274},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1811,	4,	4279},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1812,	6,	4283},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1813,	4,	4289},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1814,	2,	4293},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1815,	4,	4295},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1816,	2,	4299},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1817,	3,	4301},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	4,	4304},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	12,	4308},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1820,	3,	4320},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	5,	4323},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1822,	2,	4328},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	2,	4330},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	18,	4332},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	12,	4350},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	6,	4362},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	5,	4368},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	1,	4373},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	2,	4374},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1830,	2,	4376},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	18,	4378},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1832,	12,	4396},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	6,	4408},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	2,	4414},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	2,	4416},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1836,	18,	4418},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	12,	4436},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	6,	4448},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1839,	2,	4454},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1841,	2,	4456},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1843,	8,	4458},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1845,	11,	4466},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1847,	15,	4477},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1857,	8,	4492},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1867,	8,	4500},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1869,	4,	4508},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1879,	15,	4512},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1889,	6,	4527},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1899,	6,	4533},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1901,	4,	4539},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1911,	2,	4543},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1919,	6,	4545},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1921,	4,	4551},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1923,	1,	4555},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1925,	1,	4556},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1927,	1,	4557},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1929,	7,	4558},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1931,	1,	4565},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1933,	14,	4566},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1935,	10,	4580},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1937,	14,	4590},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1939,	32,	4604},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1941,	32,	4636},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1943,	2,	4668},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1945,	4,	4670},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1947,	13,	4674},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1949,	10,	4687},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1951,	10,	4697},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1953,	2,	4707},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1955,	6,	4709},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1957,	5,	4715},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1959,	6,	4720},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1961,	5,	4726},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1963,	1,	4731},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1965,	13,	4732},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1967,	2,	4745},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1969,	2,	4747},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1971,	11,	4749},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1987,	3,	4760},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	1989,	12,	4763},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2005,	12,	4775},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2021,	6,	4787},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2037,	4,	4793},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2053,	2,	4797},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2055,	2,	4799},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2057,	15,	4801},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2059,	2,	4816},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2061,	3,	4818},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2063,	1,	4821},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2079,	6,	4822},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2081,	8,	4828},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2083,	15,	4836},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2085,	6,	4851},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2087,	2,	4857},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2089,	2,	4859},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2091,	2,	4861},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2093,	2,	4863},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2095,	2,	4865},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2097,	2,	4867},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2099,	2,	4869},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2101,	2,	4871},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2103,	2,	4873},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2105,	2,	4875},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2107,	2,	4877},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2109,	2,	4879},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2111,	2,	4881},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2113,	2,	4883},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2115,	2,	4885},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2117,	2,	4887},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2119,	7,	4889},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2121,	34,	4896},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2123,	34,	4930},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2125,	35,	4964},
 	{NULL,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_PRT1_CFG"            ,	   0x11800E0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800E0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800E0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800E0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800E0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800E00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800E00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800E0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800E0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX1_DECISION"        ,	   0x11800E0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800E0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800E0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800E0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800E0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX1_IFG"             ,	   0x11800E0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800E0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800E0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX1_JABBER"          ,	   0x11800E0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800E0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800E0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800E0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800E0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800E00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800E00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800E0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800E00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800E0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800E00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800E00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800E0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800E0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800E0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800E0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
-	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_SMAC1"               ,	   0x11800E0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX1_APPEND"          ,	   0x11800E0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX1_CTL"             ,	   0x11800E0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800E0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800E0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800E0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800E0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800E0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800E0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX1_STAT0"           ,	   0x11800E0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX1_STAT1"           ,	   0x11800E0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX1_STAT2"           ,	   0x11800E0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX1_STAT3"           ,	   0x11800E0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX1_STAT4"           ,	   0x11800E0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX1_STAT5"           ,	   0x11800E0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX1_STAT6"           ,	   0x11800E0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX1_STAT7"           ,	   0x11800E0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX1_STAT8"           ,	   0x11800E0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX1_STAT9"           ,	   0x11800E0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800E0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX1_THRESH"          ,	   0x11800E0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
-	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
-	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
-	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
-	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
-	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
-	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800e00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800e00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
@@ -58211,14 +58218,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
 	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
@@ -58228,10 +58235,10 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
@@ -58264,20 +58271,20 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
 	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
 	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
@@ -58286,13 +58293,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
-	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
 	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
 	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
@@ -58314,14 +58321,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
@@ -58374,34 +58381,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
 	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
 	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
 	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
@@ -58419,120 +58426,120 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
 	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
-	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
 	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
 	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
 	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
@@ -58552,186 +58559,186 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
-	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
-	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
-	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
-	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
 	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
-	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"L2C_INT_STAT"                ,	   0x11800800000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
 	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
 	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
-	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
-	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"L2C_OOB"                     ,	   0x11800800000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"L2C_OOB1"                    ,	   0x11800800000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"L2C_OOB2"                    ,	   0x11800800000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_OOB3"                    ,	   0x11800800000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
-	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_PPGRP"                   ,	   0x11800800000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
 	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
@@ -58742,13 +58749,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
-	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
-	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
@@ -58756,7 +58763,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
 	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
 	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
-	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
 	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
 	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
@@ -58766,20 +58773,20 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
 	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
 	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
 	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
 	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
@@ -58788,8 +58795,8 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
 	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
 	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
@@ -58810,7 +58817,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
@@ -58837,55 +58844,55 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
 	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
 	{"MIO_UART2_DLH"               ,	   0x1180000000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
 	{"MIO_UART2_DLL"               ,	   0x1180000000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
 	{"MIO_UART2_FAR"               ,	   0x1180000000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
@@ -58937,230 +58944,230 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	411},
 	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
 	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
-	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
-	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
-	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
-	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
-	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
-	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	418},
-	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
-	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
-	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
-	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
-	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
-	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
-	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
-	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
-	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
-	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
-	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
-	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
-	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
-	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
-	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
-	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
-	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
-	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
-	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
-	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
-	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
-	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
-	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
-	{"NPEI_DMA_STATE1_P1"          ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
-	{"NPEI_DMA_STATE2_P1"          ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
-	{"NPEI_DMA_STATE3_P1"          ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
-	{"NPEI_DMA_STATE4_P1"          ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
-	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
-	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
-	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
-	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
-	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
-	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
-	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
-	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
-	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
-	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
-	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
-	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
-	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
-	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
-	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
-	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
-	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
-	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
-	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
-	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
-	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
-	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
-	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
-	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
-	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11f0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11f0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11f0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11f0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11f0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11f0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11f0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11f0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11f0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11f0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11f00000080a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11f00000080b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11f00000080c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11f00000080d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11f00000080e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11f00000080f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11f0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11f0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11f0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11f0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11f0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11f0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11f0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11f0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11f0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11f0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11f00000081a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11f00000081b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11f00000081c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11f00000081d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11f00000081e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11f00000081f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BIST_STATUS"            ,	   0x11f0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
+	{"NPEI_CTL_PORT0"              ,	   0x11f0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
+	{"NPEI_CTL_PORT1"              ,	   0x11f0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
+	{"NPEI_CTL_STATUS"             ,	   0x11f0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_CTL_STATUS2"            ,	   0x11f000000bc00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	418},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11f00000085f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DBG_DATA"               ,	   0x11f0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DBG_SELECT"             ,	   0x11f0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11f0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11f0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11f0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11f0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA0_DBELL"             ,	   0x11f00000083b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA1_DBELL"             ,	   0x11f00000083c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA2_DBELL"             ,	   0x11f00000083d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA3_DBELL"             ,	   0x11f00000083e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11f0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11f0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11f0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11f0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA0_NADDR"             ,	   0x11f00000084a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA1_NADDR"             ,	   0x11f00000084b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA2_NADDR"             ,	   0x11f00000084c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA3_NADDR"             ,	   0x11f00000084d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11f00000085c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11f00000085d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_DMA_CNTS"               ,	   0x11f00000085e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_DMA_CONTROL"            ,	   0x11f00000083a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_DMA_STATE1_P1"          ,	   0x11f0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_DMA_STATE2_P1"          ,	   0x11f0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_DMA_STATE3_P1"          ,	   0x11f00000086a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_DMA_STATE4_P1"          ,	   0x11f00000086b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_INT_A_ENB"              ,	   0x11f0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_INT_A_ENB2"             ,	   0x11f000000bce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_INT_A_SUM"              ,	   0x11f0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
+	{"NPEI_INT_ENB"                ,	   0x11f0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_INT_ENB2"               ,	   0x11f000000bcd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_INT_SUM"                ,	   0x11f0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_INT_SUM2"               ,	   0x11f000000bcc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11f0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11f0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11f00000084f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11f0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11f0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11f00000082a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11f00000082b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11f00000082c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11f00000082d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11f00000082e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11f00000082f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11f0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11f0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11f0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11f0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11f0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11f0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11f0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11f0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MSI_ENB0"               ,	   0x11f000000bc50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_MSI_ENB1"               ,	   0x11f000000bc60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_MSI_ENB2"               ,	   0x11f000000bc70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_MSI_ENB3"               ,	   0x11f000000bc80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_MSI_RCV0"               ,	   0x11f000000bc10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_MSI_RCV1"               ,	   0x11f000000bc20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_MSI_RCV2"               ,	   0x11f000000bc30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_MSI_RCV3"               ,	   0x11f000000bc40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11f000000bca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11f000000bc90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11f000000bcb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11f0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11f0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11f0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11f0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_SCRATCH_1"              ,	   0x11f0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_STATE1"                 ,	   0x11f0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_STATE2"                 ,	   0x11f0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_STATE3"                 ,	   0x11f0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
 	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	464},
 	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	465},
 	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	466},
 	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	467},
 	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	468},
-	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
-	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
-	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
-	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
-	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
-	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
-	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
-	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
-	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
-	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
-	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
-	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
-	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
-	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
-	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
-	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
-	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
-	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
-	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
-	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
-	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
-	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
-	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
-	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
-	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
-	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
-	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
-	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
-	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
-	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
-	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
-	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
-	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
-	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
-	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
-	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
-	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
-	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
-	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
-	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
-	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
-	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
-	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
-	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
-	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
-	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
-	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
-	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
-	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
-	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
-	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
-	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
-	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
-	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
-	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
-	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
-	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
-	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
-	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
-	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
-	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
-	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
-	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
-	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
-	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
-	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
-	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
-	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
-	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
-	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
-	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
-	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
-	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
-	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
-	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
-	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
-	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
-	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"NPEI_WINDOW_CTL"             ,	   0x11f0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
 	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
 	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
 	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
 	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
 	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
 	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
-	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
-	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
 	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
 	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
 	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
 	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
 	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
 	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
-	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
-	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
 	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
 	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
 	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
 	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
 	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
 	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
-	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
-	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
 	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
 	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
 	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
 	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
 	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
 	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
-	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
-	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
 	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
 	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
 	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
@@ -59171,62 +59178,62 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
 	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
 	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
-	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
-	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
 	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
 	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
 	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
 	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
 	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
 	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
-	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
-	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
 	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
 	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
 	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
 	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
 	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
 	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
-	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
-	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
 	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
 	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
 	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
 	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
 	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
 	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
-	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
-	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
-	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
-	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
-	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
-	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
-	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
-	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
 	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
 	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
 	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
 	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
 	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
 	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
-	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
-	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
 	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
 	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
 	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
 	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
 	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
 	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
-	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
-	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
 	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
 	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
 	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
 	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
 	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
 	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
-	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
-	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
 	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
 	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
 	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
@@ -59237,477 +59244,462 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
 	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
 	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
-	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
-	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
 	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
 	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
 	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
 	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
 	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
-	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
-	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
 	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
 	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
 	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
 	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
-	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
-	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
 	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
 	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
 	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
 	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
 	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
 	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
-	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
-	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
 	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
 	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
 	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
 	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
 	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
 	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
-	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
-	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
 	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
 	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
-	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
-	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
-	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
-	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
-	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
-	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
 	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
 	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
 	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
 	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
-	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
-	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
-	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
-	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
-	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
-	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
-	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
-	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
-	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
-	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
-	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
-	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
-	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
-	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
-	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
-	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
-	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
-	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
-	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
-	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
-	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
-	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
-	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
-	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
-	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
-	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
-	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
-	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
-	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
-	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
-	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
-	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
-	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
-	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
-	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
-	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
-	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
-	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
-	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
-	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
-	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
-	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
-	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
-	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
-	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
-	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
-	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
-	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
-	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
-	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
-	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
-	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
-	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
-	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
-	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
-	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
-	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
-	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
-	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
-	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
-	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
-	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
-	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
-	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
-	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
-	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
-	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
-	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
-	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
-	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
-	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
-	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
-	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
-	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
-	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
-	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
-	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
-	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC0_BIST_STATUS"           ,	   0x11800c8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC1_BIST_STATUS"           ,	   0x11800d0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800c8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800d0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC0_CFG_RD"                ,	   0x11800c8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC1_CFG_RD"                ,	   0x11800d0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC0_CFG_WR"                ,	   0x11800c8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC1_CFG_WR"                ,	   0x11800d0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800c8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800d0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC0_CTL_STATUS"            ,	   0x11800c8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC1_CTL_STATUS"            ,	   0x11800d0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800c8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800d0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_DBG_INFO"              ,	   0x11800c8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_DBG_INFO"              ,	   0x11800d0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800c80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800d00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800c8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800d0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800c8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800d0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800c8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800d0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800c8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800d0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800c8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800c8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800c8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800c8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800d0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800d0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800d0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800d0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800c8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800c8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800c8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800c8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800d0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800d0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800d0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800d0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800c8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800d0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
@@ -59734,9 +59726,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
 	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
 	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
 	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
@@ -59746,7 +59738,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
@@ -59761,14 +59753,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
 	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
 	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
-	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
-	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
 	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
 	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	756},
@@ -59776,22 +59768,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
 	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
 	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	760},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	761},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
@@ -59824,34 +59816,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
 	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
 	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
 	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
@@ -59897,309 +59889,309 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC1_DAINT"                 ,	   0x17F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
-	{"USBC1_DAINTMSK"              ,	   0x17F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC1_DCFG"                  ,	   0x17F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC1_DCTL"                  ,	   0x17F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC1_DIEPCTL000"            ,	   0x17F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC1_DIEPCTL001"            ,	   0x17F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC1_DIEPCTL002"            ,	   0x17F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC1_DIEPCTL003"            ,	   0x17F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC1_DIEPCTL004"            ,	   0x17F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC1_DIEPINT000"            ,	   0x17F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC1_DIEPINT001"            ,	   0x17F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC1_DIEPINT002"            ,	   0x17F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC1_DIEPINT003"            ,	   0x17F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC1_DIEPINT004"            ,	   0x17F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
-	{"USBC1_DIEPMSK"               ,	   0x17F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC1_DIEPTSIZ000"           ,	   0x17F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC1_DIEPTSIZ001"           ,	   0x17F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC1_DIEPTSIZ002"           ,	   0x17F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC1_DIEPTSIZ003"           ,	   0x17F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC1_DIEPTSIZ004"           ,	   0x17F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC1_DOEPCTL000"            ,	   0x17F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC1_DOEPCTL001"            ,	   0x17F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC1_DOEPCTL002"            ,	   0x17F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC1_DOEPCTL003"            ,	   0x17F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC1_DOEPCTL004"            ,	   0x17F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC1_DOEPINT000"            ,	   0x17F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC1_DOEPINT001"            ,	   0x17F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC1_DOEPINT002"            ,	   0x17F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC1_DOEPINT003"            ,	   0x17F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC1_DOEPINT004"            ,	   0x17F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
-	{"USBC1_DOEPMSK"               ,	   0x17F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC1_DOEPTSIZ000"           ,	   0x17F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC1_DOEPTSIZ001"           ,	   0x17F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC1_DOEPTSIZ002"           ,	   0x17F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC1_DOEPTSIZ003"           ,	   0x17F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC1_DOEPTSIZ004"           ,	   0x17F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC1_DPTXFSIZ001"           ,	   0x17F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC1_DPTXFSIZ002"           ,	   0x17F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC1_DPTXFSIZ003"           ,	   0x17F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC1_DPTXFSIZ004"           ,	   0x17F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
-	{"USBC1_DSTS"                  ,	   0x17F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
-	{"USBC1_DTKNQR1"               ,	   0x17F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
-	{"USBC1_DTKNQR2"               ,	   0x17F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
-	{"USBC1_DTKNQR3"               ,	   0x17F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
-	{"USBC1_DTKNQR4"               ,	   0x17F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
-	{"USBC1_GAHBCFG"               ,	   0x17F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
-	{"USBC1_GHWCFG1"               ,	   0x17F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
-	{"USBC1_GHWCFG2"               ,	   0x17F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
-	{"USBC1_GHWCFG3"               ,	   0x17F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
-	{"USBC1_GHWCFG4"               ,	   0x17F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
-	{"USBC1_GINTMSK"               ,	   0x17F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
-	{"USBC1_GINTSTS"               ,	   0x17F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
-	{"USBC1_GNPTXFSIZ"             ,	   0x17F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
-	{"USBC1_GNPTXSTS"              ,	   0x17F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
-	{"USBC1_GOTGCTL"               ,	   0x17F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
-	{"USBC1_GOTGINT"               ,	   0x17F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
-	{"USBC1_GRSTCTL"               ,	   0x17F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC1_GRXFSIZ"               ,	   0x17F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
-	{"USBC1_GRXSTSPD"              ,	   0x17F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC1_GRXSTSPH"              ,	   0x17F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC1_GRXSTSRD"              ,	   0x17F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC1_GRXSTSRH"              ,	   0x17F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC1_GSNPSID"               ,	   0x17F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
-	{"USBC1_GUSBCFG"               ,	   0x17F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
-	{"USBC1_HAINT"                 ,	   0x17F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
-	{"USBC1_HAINTMSK"              ,	   0x17F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR000"             ,	   0x17F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR001"             ,	   0x17F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR002"             ,	   0x17F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR003"             ,	   0x17F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR004"             ,	   0x17F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR005"             ,	   0x17F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR006"             ,	   0x17F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC1_HCCHAR007"             ,	   0x17F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
-	{"USBC1_HCFG"                  ,	   0x17F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT000"              ,	   0x17F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT001"              ,	   0x17F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT002"              ,	   0x17F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT003"              ,	   0x17F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT004"              ,	   0x17F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT005"              ,	   0x17F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT006"              ,	   0x17F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC1_HCINT007"              ,	   0x17F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK000"           ,	   0x17F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK001"           ,	   0x17F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK002"           ,	   0x17F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK003"           ,	   0x17F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK004"           ,	   0x17F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK005"           ,	   0x17F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK006"           ,	   0x17F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC1_HCINTMSK007"           ,	   0x17F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT000"             ,	   0x17F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT001"             ,	   0x17F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT002"             ,	   0x17F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT003"             ,	   0x17F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT004"             ,	   0x17F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT005"             ,	   0x17F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT006"             ,	   0x17F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC1_HCSPLT007"             ,	   0x17F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ000"             ,	   0x17F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ001"             ,	   0x17F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ002"             ,	   0x17F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ003"             ,	   0x17F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ004"             ,	   0x17F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ005"             ,	   0x17F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ006"             ,	   0x17F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC1_HCTSIZ007"             ,	   0x17F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
-	{"USBC1_HFIR"                  ,	   0x17F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
-	{"USBC1_HFNUM"                 ,	   0x17F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
-	{"USBC1_HPRT"                  ,	   0x17F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
-	{"USBC1_HPTXFSIZ"              ,	   0x17F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
-	{"USBC1_HPTXSTS"               ,	   0x17F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO000"          ,	   0x17F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO001"          ,	   0x17F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO002"          ,	   0x17F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO003"          ,	   0x17F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO004"          ,	   0x17F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO005"          ,	   0x17F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO006"          ,	   0x17F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC1_NPTXDFIFO007"          ,	   0x17F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
-	{"USBC1_PCGCCTL"               ,	   0x17F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"USBN1_BIST_STATUS"           ,	   0x11800780007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC1_DAINT"                 ,	   0x17f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC1_DAINTMSK"              ,	   0x17f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC1_DCFG"                  ,	   0x17f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC1_DCTL"                  ,	   0x17f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL000"            ,	   0x17f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL001"            ,	   0x17f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL002"            ,	   0x17f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL003"            ,	   0x17f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL004"            ,	   0x17f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT000"            ,	   0x17f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT001"            ,	   0x17f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT002"            ,	   0x17f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT003"            ,	   0x17f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT004"            ,	   0x17f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC1_DIEPMSK"               ,	   0x17f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ000"           ,	   0x17f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ001"           ,	   0x17f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ002"           ,	   0x17f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ003"           ,	   0x17f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ004"           ,	   0x17f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL000"            ,	   0x17f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL001"            ,	   0x17f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL002"            ,	   0x17f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL003"            ,	   0x17f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL004"            ,	   0x17f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT000"            ,	   0x17f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT001"            ,	   0x17f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT002"            ,	   0x17f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT003"            ,	   0x17f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT004"            ,	   0x17f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC1_DOEPMSK"               ,	   0x17f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ000"           ,	   0x17f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ001"           ,	   0x17f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ002"           ,	   0x17f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ003"           ,	   0x17f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ004"           ,	   0x17f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ001"           ,	   0x17f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ002"           ,	   0x17f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ003"           ,	   0x17f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ004"           ,	   0x17f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC1_DSTS"                  ,	   0x17f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC1_DTKNQR1"               ,	   0x17f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC1_DTKNQR2"               ,	   0x17f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC1_DTKNQR3"               ,	   0x17f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC1_DTKNQR4"               ,	   0x17f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC1_GAHBCFG"               ,	   0x17f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC1_GHWCFG1"               ,	   0x17f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC1_GHWCFG2"               ,	   0x17f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC1_GHWCFG3"               ,	   0x17f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC1_GHWCFG4"               ,	   0x17f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC1_GINTMSK"               ,	   0x17f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC1_GINTSTS"               ,	   0x17f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC1_GNPTXFSIZ"             ,	   0x17f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC1_GNPTXSTS"              ,	   0x17f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC1_GOTGCTL"               ,	   0x17f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC1_GOTGINT"               ,	   0x17f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC1_GRSTCTL"               ,	   0x17f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC1_GRXFSIZ"               ,	   0x17f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC1_GRXSTSPD"              ,	   0x17f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC1_GRXSTSPH"              ,	   0x17f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC1_GRXSTSRD"              ,	   0x17f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC1_GRXSTSRH"              ,	   0x17f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC1_GSNPSID"               ,	   0x17f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC1_GUSBCFG"               ,	   0x17f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC1_HAINT"                 ,	   0x17f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC1_HAINTMSK"              ,	   0x17f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR000"             ,	   0x17f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR001"             ,	   0x17f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR002"             ,	   0x17f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR003"             ,	   0x17f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR004"             ,	   0x17f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR005"             ,	   0x17f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR006"             ,	   0x17f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR007"             ,	   0x17f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC1_HCFG"                  ,	   0x17f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT000"              ,	   0x17f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT001"              ,	   0x17f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT002"              ,	   0x17f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT003"              ,	   0x17f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT004"              ,	   0x17f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT005"              ,	   0x17f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT006"              ,	   0x17f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT007"              ,	   0x17f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK000"           ,	   0x17f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK001"           ,	   0x17f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK002"           ,	   0x17f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK003"           ,	   0x17f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK004"           ,	   0x17f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK005"           ,	   0x17f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK006"           ,	   0x17f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK007"           ,	   0x17f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT000"             ,	   0x17f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT001"             ,	   0x17f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT002"             ,	   0x17f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT003"             ,	   0x17f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT004"             ,	   0x17f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT005"             ,	   0x17f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT006"             ,	   0x17f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT007"             ,	   0x17f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ000"             ,	   0x17f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ001"             ,	   0x17f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ002"             ,	   0x17f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ003"             ,	   0x17f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ004"             ,	   0x17f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ005"             ,	   0x17f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ006"             ,	   0x17f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ007"             ,	   0x17f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
+	{"USBC1_HFIR"                  ,	   0x17f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
+	{"USBC1_HFNUM"                 ,	   0x17f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
+	{"USBC1_HPRT"                  ,	   0x17f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
+	{"USBC1_HPTXFSIZ"              ,	   0x17f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
+	{"USBC1_HPTXSTS"               ,	   0x17f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO000"          ,	   0x17f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO001"          ,	   0x17f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO002"          ,	   0x17f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO003"          ,	   0x17f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO004"          ,	   0x17f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO005"          ,	   0x17f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO006"          ,	   0x17f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO007"          ,	   0x17f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
+	{"USBC1_PCGCCTL"               ,	   0x17f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"USBN1_BIST_STATUS"           ,	   0x11800780007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
 	{"USBN1_CLK_CTL"               ,	   0x1180078000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
-	{"USBN1_CTL_STATUS"            ,	   0x17F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
-	{"USBN1_DMA0_INB_CHN0"         ,	   0x17F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
-	{"USBN1_DMA0_INB_CHN1"         ,	   0x17F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
-	{"USBN1_DMA0_INB_CHN2"         ,	   0x17F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
-	{"USBN1_DMA0_INB_CHN3"         ,	   0x17F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
-	{"USBN1_DMA0_INB_CHN4"         ,	   0x17F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
-	{"USBN1_DMA0_INB_CHN5"         ,	   0x17F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
-	{"USBN1_DMA0_INB_CHN6"         ,	   0x17F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
-	{"USBN1_DMA0_INB_CHN7"         ,	   0x17F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
-	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
-	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
-	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
-	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
-	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
-	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
-	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
-	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
-	{"USBN1_DMA_TEST"              ,	   0x17F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN1_CTL_STATUS"            ,	   0x17f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN1_DMA0_INB_CHN0"         ,	   0x17f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN1_DMA0_INB_CHN1"         ,	   0x17f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN1_DMA0_INB_CHN2"         ,	   0x17f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN1_DMA0_INB_CHN3"         ,	   0x17f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN1_DMA0_INB_CHN4"         ,	   0x17f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN1_DMA0_INB_CHN5"         ,	   0x17f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN1_DMA0_INB_CHN6"         ,	   0x17f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN1_DMA0_INB_CHN7"         ,	   0x17f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
+	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
+	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
+	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
+	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
+	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
+	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
+	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
+	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
+	{"USBN1_DMA_TEST"              ,	   0x17f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
 	{"USBN1_INT_ENB"               ,	   0x1180078000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	902},
@@ -61458,7 +61450,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"Q3FUS"                       ,	0,	34,	288,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_256K"                   ,	34,	1,	288,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_128K"                   ,	35,	1,	288,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	288,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	3,	288,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_40_63"              ,	40,	24,	288,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
@@ -61504,7 +61496,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"INORDER_MWF"                 ,	13,	1,	293,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	293,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	293,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
@@ -62147,7 +62139,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"BAR2_ESX"                    ,	2,	2,	415,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	415,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	415,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	415,	"R/W",	0,	0,	1ull,	1ull},
@@ -62164,7 +62156,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"BAR2_ESX"                    ,	2,	2,	416,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	416,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	416,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	416,	"R/W",	0,	0,	1ull,	1ull},
@@ -62242,7 +62234,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"DMA1_ENB"                    ,	35,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA2_ENB"                    ,	36,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA3_ENB"                    ,	37,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_38_63"              ,	38,	26,	429,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_38_63"              ,	38,	26,	429,	"RO",	1,	1,	0,	0},
 	{"RESERVED_0_4"                ,	0,	5,	430,	"RAZ",	0,	0,	0ull,	0ull},
 	{"D3_REQST"                    ,	5,	5,	430,	"RO",	0,	1,	0ull,	0},
 	{"D2_REQST"                    ,	10,	5,	430,	"RO",	0,	1,	0ull,	0},
@@ -62287,7 +62279,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"DMA1DBO"                     ,	5,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA2DBO"                     ,	6,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA3DBO"                     ,	7,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_8_8"                ,	8,	1,	437,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	437,	"R/W",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA1FI"                      ,	10,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
 	{"DCNT0"                       ,	11,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
@@ -62351,7 +62343,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"DMA1DBO"                     ,	5,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA2DBO"                     ,	6,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA3DBO"                     ,	7,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_8_8"                ,	8,	1,	438,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	438,	"R/W",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
 	{"DMA1FI"                      ,	10,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
 	{"DCNT0"                       ,	11,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
@@ -62414,7 +62406,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"DMA1DBO"                     ,	5,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DMA2DBO"                     ,	6,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DMA3DBO"                     ,	7,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_8"                ,	8,	1,	439,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	439,	"R/W",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DMA1FI"                      ,	10,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DCNT0"                       ,	11,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
@@ -62475,7 +62467,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"DMA1DBO"                     ,	5,	1,	440,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA2DBO"                     ,	6,	1,	440,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA3DBO"                     ,	7,	1,	440,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_8"                ,	8,	1,	440,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	440,	"RO",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	440,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA1FI"                      ,	10,	1,	440,	"RO",	0,	0,	0ull,	0ull},
 	{"DCNT0"                       ,	11,	1,	440,	"RO",	0,	0,	0ull,	0ull},
@@ -64082,9 +64074,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"BACK"                        ,	59,	4,	710,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	710,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	711,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	711,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	711,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	711,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	712,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	712,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	712,	"RO",	1,	0,	0,	0ull},
@@ -64092,7 +64084,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"SOP"                         ,	18,	1,	712,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	712,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	712,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	712,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	712,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	713,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	713,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	713,	"RO",	1,	0,	0,	0ull},
@@ -64125,7 +64117,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"CURR_SIZ"                    ,	0,	8,	719,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	8,	40,	719,	"RO",	1,	0,	0,	0ull},
 	{"NXT_INFLT"                   ,	48,	6,	719,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	719,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	719,	"RAZ",	1,	1,	0,	0},
 	{"QID_BASE"                    ,	0,	8,	720,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFF"                     ,	8,	4,	720,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFMAX"                  ,	12,	4,	720,	"RO",	1,	0,	0,	0ull},
@@ -64138,7 +64130,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"PREEMPTER"                   ,	28,	1,	720,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFTHS"                  ,	29,	4,	720,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFRES"                  ,	33,	4,	720,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	720,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	721,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	721,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	721,	"RO",	1,	0,	0,	0ull},
@@ -64150,35 +64142,35 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"S_TAIL"                      ,	4,	1,	722,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	722,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTEE"                   ,	6,	1,	722,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	722,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	722,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTER"                   ,	28,	1,	722,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	722,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	723,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	723,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	723,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	723,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	723,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	723,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	724,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	724,	"R/W",	1,	0,	0,	0ull},
 	{"BP_PORT"                     ,	10,	6,	724,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	724,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	724,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	724,	"R/W",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	61,	1,	724,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	724,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	724,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	725,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	725,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	725,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	725,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	725,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	725,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	725,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	726,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	726,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	726,	"RAZ",	1,	1,	0,	0},
 	{"RATE_PKT"                    ,	8,	24,	726,	"R/W",	1,	0,	0,	0ull},
 	{"RATE_WORD"                   ,	32,	19,	726,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	726,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	726,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	727,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	727,	"RAZ",	1,	1,	0,	0},
 	{"RATE_LIM"                    ,	8,	24,	727,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	727,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	728,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	728,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	728,	"WR0",	1,	0,	0,	0ull},
@@ -64190,9 +64182,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"S_TAIL"                      ,	63,	1,	728,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	729,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	729,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	729,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	729,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	729,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	730,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	2,	730,	"RO",	1,	0,	0,	0ull},
 	{"PRT_CTL"                     ,	6,	2,	730,	"RO",	1,	0,	0,	0ull},
@@ -64208,11 +64200,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"OUT_DAT"                     ,	32,	1,	730,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	33,	1,	730,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	34,	1,	730,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	730,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	730,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	731,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	731,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	731,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	731,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	731,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	731,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	732,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	733,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	734,	"RO",	0,	0,	0ull,	0ull},
@@ -64227,33 +64219,33 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"ENGINE7"                     ,	28,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENGINE8"                     ,	32,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE9"                     ,	36,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_40_63"              ,	40,	24,	736,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	736,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	10,	737,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	737,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	737,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	738,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	738,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	739,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	739,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	739,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	740,	"R/W",	0,	0,	2ull,	2ull},
 	{"MODE1"                       ,	3,	3,	740,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	740,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	740,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	741,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	741,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	742,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	742,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	742,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	743,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	743,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	744,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	744,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	744,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	744,	"RAZ",	1,	1,	0,	0},
 	{"ADR"                         ,	0,	1,	745,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND"                        ,	1,	1,	745,	"RO",	0,	0,	0ull,	0ull},
 	{"NBR0"                        ,	2,	1,	745,	"RO",	0,	0,	0ull,	0ull},
@@ -64361,7 +64353,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"NCB_INB"                     ,	2,	2,	771,	"RO",	1,	0,	0,	0ull},
 	{"NCB_OUB"                     ,	4,	1,	771,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	5,	1,	771,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	771,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	771,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	772,	"R/W",	0,	1,	0ull,	0},
 	{"SIZE"                        ,	33,	13,	772,	"R/W",	0,	1,	0ull,	0},
 	{"POOL"                        ,	46,	3,	772,	"R/W",	0,	1,	0ull,	0},
@@ -64376,11 +64368,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"OWORDPV"                     ,	6,	1,	774,	"RO",	1,	1,	0,	0},
 	{"OWORDQV"                     ,	7,	1,	774,	"RO",	1,	1,	0,	0},
 	{"IWIDX"                       ,	8,	6,	774,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	774,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	774,	"RO",	1,	1,	0,	0},
 	{"IRIDX"                       ,	16,	6,	774,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	774,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	774,	"RO",	1,	1,	0,	0},
 	{"LOOP"                        ,	32,	25,	774,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	774,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	774,	"RO",	1,	1,	0,	0},
 	{"CWORD"                       ,	0,	64,	775,	"RO",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	776,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	776,	"RO",	1,	1,	0,	0},
@@ -64391,16 +64383,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"WC"                          ,	10,	1,	777,	"RO",	1,	1,	0,	0},
 	{"P"                           ,	11,	1,	777,	"RO",	1,	1,	0,	0},
 	{"Q"                           ,	12,	1,	777,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	777,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	777,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	15,	778,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	778,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	778,	"RAZ",	1,	1,	0,	0},
 	{"OWORDP"                      ,	0,	64,	779,	"RO",	1,	1,	0,	0},
 	{"OWORDQ"                      ,	0,	64,	780,	"RO",	1,	1,	0,	0},
 	{"RWORD"                       ,	0,	64,	781,	"RO",	1,	1,	0,	0},
 	{"N0CREDS"                     ,	0,	4,	782,	"RO",	0,	0,	8ull,	0ull},
 	{"N1CREDS"                     ,	4,	4,	782,	"RO",	0,	0,	8ull,	0ull},
 	{"POWCREDS"                    ,	8,	2,	782,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	782,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	782,	"RAZ",	1,	1,	0,	0},
 	{"FPACREDS"                    ,	12,	2,	782,	"RO",	0,	0,	1ull,	0ull},
 	{"WCCREDS"                     ,	14,	2,	782,	"RO",	0,	0,	0ull,	0ull},
 	{"NIWIDX0"                     ,	16,	4,	782,	"RO",	1,	1,	0,	0},
@@ -64414,12 +64406,12 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"NIRVAL7"                     ,	43,	5,	782,	"RO",	1,	1,	0,	0},
 	{"NIRQUE7"                     ,	48,	2,	782,	"RO",	1,	1,	0,	0},
 	{"NIROPC7"                     ,	50,	3,	782,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	782,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	782,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	783,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	783,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	56,	8,	783,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	0,	15,	784,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	784,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	784,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	785,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	785,	"RO",	1,	1,	0,	0},
 	{"FLAGS"                       ,	56,	8,	785,	"RO",	1,	1,	0,	0},
@@ -64429,16 +64421,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"Q"                           ,	17,	1,	786,	"RO",	1,	1,	0,	0},
 	{"INI"                         ,	18,	1,	786,	"RO",	1,	1,	0,	0},
 	{"EOD"                         ,	19,	1,	786,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	786,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	786,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	787,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	787,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	788,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	788,	"RAZ",	1,	1,	0,	0},
 	{"COEFFS"                      ,	0,	8,	789,	"R/W",	0,	0,	29ull,	29ull},
 	{"RESERVED_8_63"               ,	8,	56,	789,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INDEX"                       ,	0,	16,	790,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	16,	16,	790,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	790,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	790,	"RAZ",	1,	1,	0,	0},
 	{"MEM"                         ,	0,	1,	791,	"RO",	0,	0,	0ull,	0ull},
 	{"RRC"                         ,	1,	1,	791,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_2_63"               ,	2,	62,	791,	"RAZ",	1,	1,	0,	0},
@@ -64476,11 +64468,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"PENDING"                     ,	17,	1,	797,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	797,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	798,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	798,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	798,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	798,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	798,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	798,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	799,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	799,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	799,	"RO",	1,	0,	0,	0ull},
@@ -64488,32 +64480,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"RESERVED_7_7"                ,	7,	1,	800,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	800,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	800,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	800,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	801,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	801,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	801,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	801,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	801,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	802,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	802,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	802,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	802,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	802,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	802,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	802,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	803,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	803,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	803,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	803,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	803,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	804,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	804,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	804,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	805,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	805,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	805,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	805,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	805,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	806,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	806,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	806,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	807,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	807,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	807,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	807,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	808,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	808,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	808,	"RO",	0,	0,	0ull,	0ull},
@@ -64534,9 +64526,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
 	{"RPTR"                        ,	8,	8,	810,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	810,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	811,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	811,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	811,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	811,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	811,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	811,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	811,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	812,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	812,	"RAZ",	0,	0,	0ull,	0ull},
@@ -65754,83 +65746,83 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
 	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1454,	1,	2787},
 	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1455,	2,	2788},
 	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1456,	2,	2790},
-	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1457,	2,	2792},
-	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1458,	24,	2794},
-	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1459,	4,	2818},
-	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1460,	5,	2822},
-	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1461,	5,	2827},
-	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1462,	2,	2832},
-	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1463,	1,	2834},
-	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1464,	1,	2835},
-	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1465,	5,	2836},
-	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1466,	2,	2841},
-	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1467,	1,	2843},
-	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1468,	1,	2844},
-	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1469,	4,	2845},
-	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1470,	2,	2849},
-	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1471,	2,	2851},
-	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1472,	1,	2853},
-	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1473,	1,	2854},
-	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1474,	2,	2855},
-	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1475,	3,	2857},
-	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1476,	2,	2860},
-	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1477,	2,	2862},
-	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1478,	4,	2864},
-	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1479,	10,	2868},
-	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1480,	12,	2878},
-	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1481,	7,	2890},
-	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1482,	2,	2897},
-	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1483,	1,	2899},
-	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1484,	2,	2900},
-	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1485,	7,	2902},
-	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1486,	11,	2909},
-	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1487,	19,	2920},
-	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1488,	11,	2939},
-	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1489,	17,	2950},
-	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1490,	12,	2967},
-	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1491,	22,	2979},
-	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1492,	3,	3001},
-	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1493,	3,	3004},
-	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1494,	1,	3007},
-	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1495,	1,	3008},
-	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1496,	1,	3009},
-	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1497,	1,	3010},
-	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1498,	3,	3011},
-	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1499,	14,	3014},
-	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1500,	14,	3028},
-	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1501,	14,	3042},
-	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1502,	9,	3056},
-	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1503,	9,	3065},
-	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1504,	6,	3074},
-	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1505,	1,	3080},
-	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1506,	1,	3081},
-	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1507,	1,	3082},
-	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1508,	1,	3083},
-	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1509,	2,	3084},
-	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1510,	1,	3086},
-	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1511,	6,	3087},
-	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1512,	6,	3093},
-	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1513,	13,	3099},
-	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1514,	5,	3112},
-	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1515,	8,	3117},
-	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1516,	19,	3125},
-	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1517,	3,	3144},
-	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1518,	1,	3147},
-	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1519,	1,	3148},
-	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1520,	3,	3149},
-	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1521,	3,	3152},
-	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1522,	3,	3155},
-	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1523,	4,	3158},
-	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1524,	4,	3162},
-	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1525,	4,	3166},
-	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1526,	7,	3170},
-	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1527,	5,	3177},
-	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1528,	5,	3182},
-	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1529,	4,	3187},
-	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1530,	4,	3191},
-	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1531,	4,	3195},
-	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1532,	1,	3199},
-	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1533,	1,	3200},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1457,	2,	2792},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1458,	24,	2794},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1459,	4,	2818},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1460,	5,	2822},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1461,	5,	2827},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1462,	2,	2832},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1463,	1,	2834},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1464,	1,	2835},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1465,	5,	2836},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1466,	2,	2841},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1467,	1,	2843},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1468,	1,	2844},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1469,	4,	2845},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1470,	2,	2849},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1471,	2,	2851},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1472,	1,	2853},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1473,	1,	2854},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1474,	2,	2855},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1475,	3,	2857},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1476,	2,	2860},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1477,	2,	2862},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1478,	4,	2864},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1479,	10,	2868},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1480,	12,	2878},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1481,	7,	2890},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1482,	2,	2897},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1483,	1,	2899},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1484,	2,	2900},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1485,	7,	2902},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1486,	11,	2909},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1487,	19,	2920},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1488,	11,	2939},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1489,	17,	2950},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1490,	12,	2967},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1491,	22,	2979},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1492,	3,	3001},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1493,	3,	3004},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1494,	1,	3007},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1495,	1,	3008},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1496,	1,	3009},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1497,	1,	3010},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1498,	3,	3011},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1499,	14,	3014},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1500,	14,	3028},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1501,	14,	3042},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1502,	9,	3056},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1503,	9,	3065},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1504,	6,	3074},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1505,	1,	3080},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1506,	1,	3081},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1507,	1,	3082},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1508,	1,	3083},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1509,	2,	3084},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1510,	1,	3086},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1511,	6,	3087},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1512,	6,	3093},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1513,	13,	3099},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1514,	5,	3112},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1515,	8,	3117},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1516,	19,	3125},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1517,	3,	3144},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1518,	1,	3147},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1519,	1,	3148},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1520,	3,	3149},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1521,	3,	3152},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1522,	3,	3155},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1523,	4,	3158},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1524,	4,	3162},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1525,	4,	3166},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1526,	7,	3170},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1527,	5,	3177},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1528,	5,	3182},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1529,	4,	3187},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1530,	4,	3191},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1531,	4,	3195},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1532,	1,	3199},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1533,	1,	3200},
 	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1534,	2,	3201},
 	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1536,	24,	3203},
 	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1538,	4,	3227},
@@ -65925,398 +65917,398 @@ static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
 	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1746,	4,	3779},
 	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1750,	5,	3783},
 	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1754,	8,	3788},
-	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1756,	2,	3796},
-	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1758,	5,	3798},
-	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1760,	10,	3803},
-	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1762,	2,	3813},
-	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1764,	7,	3815},
-	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1766,	7,	3822},
-	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1768,	6,	3829},
-	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1770,	5,	3835},
-	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1772,	5,	3840},
-	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1774,	3,	3845},
-	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1776,	6,	3848},
-	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1778,	9,	3854},
-	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1780,	5,	3863},
-	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1782,	10,	3868},
-	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1784,	14,	3878},
-	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1786,	15,	3892},
-	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	2,	3907},
-	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1790,	2,	3909},
-	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1792,	2,	3911},
-	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1794,	16,	3913},
-	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	3,	3929},
-	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1798,	32,	3932},
-	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1800,	32,	3964},
-	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1802,	5,	3996},
-	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	2,	4001},
-	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	2,	4003},
-	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	2,	4005},
-	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1810,	2,	4007},
-	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	2,	4009},
-	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	8,	4011},
-	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	2,	4019},
-	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	4,	4021},
-	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	16,	4025},
-	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	16,	4041},
-	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	3,	4057},
-	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	8,	4060},
-	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	22,	4068},
-	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1839,	6,	4090},
-	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	14,	4096},
-	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1841,	14,	4110},
-	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1842,	2,	4124},
-	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1843,	28,	4126},
-	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1855,	25,	4154},
-	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1867,	2,	4179},
-	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1931,	4,	4181},
-	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1939,	9,	4185},
-	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1947,	2,	4194},
-	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1948,	2,	4196},
-	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1949,	2,	4198},
-	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1961,	2,	4200},
-	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1973,	2,	4202},
-	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1985,	2,	4204},
-	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1997,	2,	4206},
-	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2009,	2,	4208},
-	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2021,	2,	4210},
-	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2033,	2,	4212},
-	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2045,	2,	4214},
-	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2057,	2,	4216},
-	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2069,	2,	4218},
-	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2070,	2,	4220},
-	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2082,	2,	4222},
-	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2094,	2,	4224},
-	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2106,	2,	4226},
-	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	2,	4228},
-	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2171,	3,	4230},
-	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	3,	4233},
-	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	2,	4236},
-	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	2,	4238},
-	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2175,	4,	4240},
-	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	5,	4244},
-	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	4,	4249},
-	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	8,	4253},
-	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	4,	4261},
-	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	5,	4265},
-	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	1,	4270},
-	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	5,	4271},
-	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	1,	4276},
-	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2184,	13,	4277},
-	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	4,	4290},
-	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	13,	4294},
-	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2187,	6,	4307},
-	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2188,	9,	4313},
-	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	4,	4322},
-	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2190,	7,	4326},
-	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2191,	5,	4333},
-	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2192,	5,	4338},
-	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2193,	4,	4343},
-	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2194,	9,	4347},
-	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2195,	5,	4356},
-	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2196,	16,	4361},
-	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2197,	4,	4377},
-	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2198,	1,	4381},
-	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2199,	1,	4382},
-	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2200,	1,	4383},
-	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2201,	1,	4384},
-	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	2202,	11,	4385},
-	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2203,	2,	4396},
-	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2204,	4,	4398},
-	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2205,	5,	4402},
-	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2206,	3,	4407},
-	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2207,	4,	4410},
-	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2208,	2,	4414},
-	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2209,	3,	4416},
-	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2210,	3,	4419},
-	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2211,	12,	4422},
-	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2212,	2,	4434},
-	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2213,	13,	4436},
-	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2214,	3,	4449},
-	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2215,	2,	4452},
-	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2223,	2,	4454},
-	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2224,	2,	4456},
-	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2225,	2,	4458},
-	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2226,	2,	4460},
-	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2234,	2,	4462},
-	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2235,	2,	4464},
-	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2236,	2,	4466},
-	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2237,	10,	4468},
-	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2241,	5,	4478},
-	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2249,	10,	4483},
-	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2257,	2,	4493},
-	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2258,	2,	4495},
-	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2259,	2,	4497},
-	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2267,	3,	4499},
-	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2268,	6,	4502},
-	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2284,	5,	4508},
-	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2285,	7,	4513},
-	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2301,	2,	4520},
-	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	1,	4522},
-	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2318,	1,	4523},
-	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	1,	4524},
-	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2320,	5,	4525},
-	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	5,	4530},
-	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2322,	4,	4535},
-	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	10,	4539},
-	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2324,	1,	4549},
-	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	3,	4550},
-	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2326,	7,	4553},
-	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2327,	2,	4560},
-	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2328,	1,	4562},
-	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2329,	1,	4563},
-	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2330,	1,	4564},
-	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2331,	18,	4565},
-	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2332,	3,	4583},
-	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2333,	2,	4586},
-	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2334,	3,	4588},
-	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2335,	7,	4591},
-	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2336,	2,	4598},
-	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	2,	4600},
-	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2338,	2,	4602},
-	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	3,	4604},
-	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2340,	3,	4607},
-	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	7,	4610},
-	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2342,	10,	4617},
-	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	6,	4627},
-	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	2,	4633},
-	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	4,	4635},
-	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	4,	4639},
-	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	6,	4643},
-	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	3,	4649},
-	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	5,	4652},
-	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	4,	4657},
-	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	6,	4661},
-	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	4,	4667},
-	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4671},
-	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	4,	4673},
-	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	2,	4677},
-	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	3,	4679},
-	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	4,	4682},
-	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	12,	4686},
-	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	3,	4698},
-	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	5,	4701},
-	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	2,	4706},
-	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	2,	4708},
-	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2368,	18,	4710},
-	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2369,	12,	4728},
-	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2370,	6,	4740},
-	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2371,	5,	4746},
-	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2372,	1,	4751},
-	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	2,	4752},
-	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2374,	2,	4754},
-	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	18,	4756},
-	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2376,	12,	4774},
-	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	6,	4786},
-	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	2,	4792},
-	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	2,	4794},
-	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	18,	4796},
-	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	12,	4814},
-	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	6,	4826},
-	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2383,	2,	4832},
-	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2385,	2,	4834},
-	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2387,	8,	4836},
-	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2389,	11,	4844},
-	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2391,	15,	4855},
-	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2401,	8,	4870},
-	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2411,	8,	4878},
-	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2413,	4,	4886},
-	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2423,	15,	4890},
-	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2433,	6,	4905},
-	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2443,	6,	4911},
-	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2445,	4,	4917},
-	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2455,	2,	4921},
-	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2463,	6,	4923},
-	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2465,	4,	4929},
-	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2467,	1,	4933},
-	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2469,	1,	4934},
-	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2471,	1,	4935},
-	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2473,	7,	4936},
-	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2475,	1,	4943},
-	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2477,	14,	4944},
-	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2479,	10,	4958},
-	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2481,	14,	4968},
-	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2483,	32,	4982},
-	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2485,	32,	5014},
-	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2487,	2,	5046},
-	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2489,	4,	5048},
-	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2491,	13,	5052},
-	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2493,	10,	5065},
-	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2495,	10,	5075},
-	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2497,	2,	5085},
-	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2499,	6,	5087},
-	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2501,	5,	5093},
-	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2503,	6,	5098},
-	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2505,	5,	5104},
-	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2507,	1,	5109},
-	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2509,	13,	5110},
-	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2511,	2,	5123},
-	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2513,	2,	5125},
-	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2515,	11,	5127},
-	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2531,	3,	5138},
-	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2533,	12,	5141},
-	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2549,	12,	5153},
-	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2565,	6,	5165},
-	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2581,	4,	5171},
-	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2597,	2,	5175},
-	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2599,	2,	5177},
-	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2601,	15,	5179},
-	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2603,	2,	5194},
-	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2605,	3,	5196},
-	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2607,	1,	5199},
-	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2623,	6,	5200},
-	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2625,	8,	5206},
-	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2627,	15,	5214},
-	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2629,	6,	5229},
-	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2631,	2,	5235},
-	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2633,	2,	5237},
-	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2635,	2,	5239},
-	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2637,	2,	5241},
-	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2639,	2,	5243},
-	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2641,	2,	5245},
-	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2643,	2,	5247},
-	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2645,	2,	5249},
-	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2647,	2,	5251},
-	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2649,	2,	5253},
-	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2651,	2,	5255},
-	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2653,	2,	5257},
-	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2655,	2,	5259},
-	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2657,	2,	5261},
-	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2659,	2,	5263},
-	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2661,	2,	5265},
-	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2663,	7,	5267},
-	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2665,	34,	5274},
-	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2667,	34,	5308},
-	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2669,	35,	5342},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1755,	2,	3796},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1756,	5,	3798},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1757,	10,	3803},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1758,	2,	3813},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1759,	7,	3815},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1760,	7,	3822},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1761,	6,	3829},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1762,	5,	3835},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1763,	5,	3840},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1764,	3,	3845},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1765,	6,	3848},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1766,	9,	3854},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1767,	5,	3863},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1768,	10,	3868},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1769,	14,	3878},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1771,	15,	3892},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1773,	2,	3907},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1775,	2,	3909},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1777,	2,	3911},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1779,	16,	3913},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1781,	3,	3929},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1783,	32,	3932},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1785,	32,	3964},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1787,	5,	3996},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1789,	2,	4001},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1791,	2,	4003},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1793,	2,	4005},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1795,	2,	4007},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1803,	2,	4009},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1811,	8,	4011},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1813,	2,	4019},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1814,	4,	4021},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	16,	4025},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	16,	4041},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1820,	3,	4057},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1822,	8,	4060},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	22,	4068},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	6,	4090},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	14,	4096},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	14,	4110},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	2,	4124},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	28,	4126},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	25,	4154},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1852,	2,	4179},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1916,	4,	4181},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1924,	9,	4185},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1932,	2,	4194},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1933,	2,	4196},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1934,	2,	4198},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1946,	2,	4200},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1958,	2,	4202},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1970,	2,	4204},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1982,	2,	4206},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1994,	2,	4208},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2006,	2,	4210},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2018,	2,	4212},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2030,	2,	4214},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2042,	2,	4216},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2054,	2,	4218},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2055,	2,	4220},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2067,	2,	4222},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2079,	2,	4224},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2091,	2,	4226},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2155,	2,	4228},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2156,	3,	4230},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2157,	3,	4233},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2158,	2,	4236},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2159,	2,	4238},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2160,	4,	4240},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2161,	5,	4244},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2162,	4,	4249},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2163,	8,	4253},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2164,	4,	4261},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2165,	5,	4265},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2166,	1,	4270},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2167,	5,	4271},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2168,	1,	4276},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2169,	13,	4277},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	4,	4290},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2171,	13,	4294},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	6,	4307},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	9,	4313},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	4,	4322},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2175,	7,	4326},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	5,	4333},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	5,	4338},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	4,	4343},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	9,	4347},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	5,	4356},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	16,	4361},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	4,	4377},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	1,	4381},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2184,	1,	4382},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	1,	4383},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	1,	4384},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	2187,	11,	4385},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2188,	2,	4396},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	4,	4398},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2190,	5,	4402},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2191,	3,	4407},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2192,	4,	4410},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2193,	2,	4414},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2194,	3,	4416},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2195,	3,	4419},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2196,	12,	4422},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2197,	2,	4434},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2198,	13,	4436},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2199,	3,	4449},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2200,	2,	4452},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2208,	2,	4454},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2209,	2,	4456},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2210,	2,	4458},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2211,	2,	4460},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2219,	2,	4462},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2220,	2,	4464},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2221,	2,	4466},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2222,	10,	4468},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2226,	5,	4478},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2234,	10,	4483},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2242,	2,	4493},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2243,	2,	4495},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2244,	2,	4497},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2252,	3,	4499},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2253,	6,	4502},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2269,	5,	4508},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2270,	7,	4513},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2286,	2,	4520},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2302,	1,	4522},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2303,	1,	4523},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2304,	1,	4524},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2305,	5,	4525},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2306,	5,	4530},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2307,	4,	4535},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2308,	10,	4539},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2309,	1,	4549},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2310,	3,	4550},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2311,	7,	4553},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2312,	2,	4560},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2313,	1,	4562},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2314,	1,	4563},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2315,	1,	4564},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2316,	18,	4565},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	3,	4583},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2318,	2,	4586},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	3,	4588},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2320,	7,	4591},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	2,	4598},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2322,	2,	4600},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	2,	4602},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2324,	3,	4604},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	3,	4607},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2326,	7,	4610},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2327,	10,	4617},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2329,	6,	4627},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2331,	2,	4633},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2333,	4,	4635},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2335,	4,	4639},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	6,	4643},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2338,	3,	4649},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	5,	4652},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2340,	4,	4657},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	6,	4661},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2342,	4,	4667},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2343,	2,	4671},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	4,	4673},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	2,	4677},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	3,	4679},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	4,	4682},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	12,	4686},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	3,	4698},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	5,	4701},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4706},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	2,	4708},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	18,	4710},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	12,	4728},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	6,	4740},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	5,	4746},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	1,	4751},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4752},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	2,	4754},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	18,	4756},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	12,	4774},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	6,	4786},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4792},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	2,	4794},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	18,	4796},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	12,	4814},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	6,	4826},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2368,	2,	4832},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2370,	2,	4834},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2372,	8,	4836},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2374,	11,	4844},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2376,	15,	4855},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2386,	8,	4870},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2396,	8,	4878},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2398,	4,	4886},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2408,	15,	4890},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2418,	6,	4905},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2428,	6,	4911},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2430,	4,	4917},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2440,	2,	4921},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2448,	6,	4923},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2450,	4,	4929},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2452,	1,	4933},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2454,	1,	4934},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2456,	1,	4935},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2458,	7,	4936},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2460,	1,	4943},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2462,	14,	4944},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2464,	10,	4958},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2466,	14,	4968},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2468,	32,	4982},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2470,	32,	5014},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2472,	2,	5046},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2474,	4,	5048},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2476,	13,	5052},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2478,	10,	5065},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2480,	10,	5075},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2482,	2,	5085},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2484,	6,	5087},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2486,	5,	5093},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2488,	6,	5098},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2490,	5,	5104},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2492,	1,	5109},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2494,	13,	5110},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2496,	2,	5123},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2498,	2,	5125},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2500,	11,	5127},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2516,	3,	5138},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2518,	12,	5141},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2534,	12,	5153},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2550,	6,	5165},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2566,	4,	5171},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2582,	2,	5175},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2584,	2,	5177},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2586,	15,	5179},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2588,	2,	5194},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2590,	3,	5196},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2592,	1,	5199},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2608,	6,	5200},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2610,	8,	5206},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2612,	15,	5214},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2614,	6,	5229},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2616,	2,	5235},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2618,	2,	5237},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2620,	2,	5239},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2622,	2,	5241},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2624,	2,	5243},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2626,	2,	5245},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2628,	2,	5247},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2630,	2,	5249},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2632,	2,	5251},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2634,	2,	5253},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2636,	2,	5255},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2638,	2,	5257},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2640,	2,	5259},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2642,	2,	5261},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2644,	2,	5263},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2646,	2,	5265},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2648,	7,	5267},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2650,	34,	5274},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2652,	34,	5308},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2654,	35,	5342},
 	{NULL,0,0,0,0,0}
 };
 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
-	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
-	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
-	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
-	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
-	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_PRT1_CFG"            ,	   0x11800E0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
-	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800E0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
-	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800E0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
-	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800E0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
-	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800E0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
-	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800E00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
-	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800E00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
-	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800E0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
-	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800E0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
-	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX1_DECISION"        ,	   0x11800E0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
-	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800E0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
-	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800E0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
-	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800E0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
-	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800E0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
-	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX1_IFG"             ,	   0x11800E0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
-	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800E0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
-	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800E0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
-	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX1_JABBER"          ,	   0x11800E0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
-	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800E0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
-	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800E0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
-	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800E0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
-	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800E0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
-	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800E00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
-	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800E00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
-	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800E0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
-	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800E00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
-	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800E0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
-	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800E00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
-	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800E00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
-	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800E0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
-	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800E0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
-	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800E0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
-	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800E0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
-	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
-	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
-	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_SMAC1"               ,	   0x11800E0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
-	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
-	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX1_APPEND"          ,	   0x11800E0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
-	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX1_CTL"             ,	   0x11800E0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
-	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800E0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
-	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800E0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
-	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800E0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
-	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800E0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
-	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800E0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
-	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800E0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
-	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX1_STAT0"           ,	   0x11800E0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
-	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX1_STAT1"           ,	   0x11800E0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
-	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX1_STAT2"           ,	   0x11800E0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
-	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX1_STAT3"           ,	   0x11800E0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
-	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX1_STAT4"           ,	   0x11800E0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
-	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX1_STAT5"           ,	   0x11800E0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
-	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX1_STAT6"           ,	   0x11800E0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
-	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX1_STAT7"           ,	   0x11800E0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
-	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX1_STAT8"           ,	   0x11800E0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
-	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX1_STAT9"           ,	   0x11800E0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
-	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800E0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
-	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX1_THRESH"          ,	   0x11800E0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
-	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
-	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
-	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
-	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
-	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
-	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
-	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
-	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
-	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
-	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800e00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800e00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
 	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
 	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
 	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
@@ -66375,30 +66367,30 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
 	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
-	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
-	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
-	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
-	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
-	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
-	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
-	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
 	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
@@ -66408,10 +66400,10 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
 	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
-	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
-	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
 	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
 	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
 	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
@@ -66444,20 +66436,20 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
 	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
 	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
-	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
 	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
 	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
 	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
 	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
-	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
-	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
@@ -66466,13 +66458,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
 	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
 	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
-	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
-	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_WART_CTL"                ,	   0x11800280000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_WART_STATUS"             ,	   0x11800280000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
 	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
 	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
-	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
 	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
-	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
 	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
 	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
 	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
@@ -66495,14 +66487,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
 	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
-	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
-	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
-	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
 	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
 	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
@@ -66555,34 +66547,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
 	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
-	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
-	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
-	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
 	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
 	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
-	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
-	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
 	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
 	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
-	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
-	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
-	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
 	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
 	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
@@ -66600,122 +66592,122 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
 	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
-	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
 	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
 	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
 	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
 	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
-	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
 	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
 	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
-	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
 	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
 	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
-	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
-	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
 	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
-	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
 	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
-	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
 	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
-	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
 	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
-	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
 	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
-	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
 	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
-	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
 	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
-	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
 	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
-	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
 	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
-	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
 	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
-	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
 	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
-	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
 	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
-	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
 	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
 	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
-	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
-	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
-	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
-	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
-	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
-	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
-	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
 	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
 	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
-	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
 	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
 	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
-	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
 	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
-	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
 	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
 	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
 	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
 	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
 	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
 	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
-	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
-	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
-	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
-	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
 	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
 	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
 	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
@@ -66735,227 +66727,227 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
 	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
 	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
-	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
-	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
 	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
 	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
 	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
 	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
-	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
-	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
-	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
-	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
-	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
-	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
-	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
-	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
-	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
-	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
-	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
-	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
-	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
-	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
-	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
-	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
-	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
-	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
-	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
-	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
-	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
-	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
-	{"IOB_TO_CMB_CREDITS"          ,	   0x11800F00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
-	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
-	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
-	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
-	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
-	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
-	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
-	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
-	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
-	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
-	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
-	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
-	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
-	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
-	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
-	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
-	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
-	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_256_CNT"        ,	   0x14F0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_257_CNT"        ,	   0x14F0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_258_CNT"        ,	   0x14F0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_259_CNT"        ,	   0x14F00000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_260_CNT"        ,	   0x14F00000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_261_CNT"        ,	   0x14F00000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_262_CNT"        ,	   0x14F00000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_263_CNT"        ,	   0x14F00000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_264_CNT"        ,	   0x14F00000010C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_265_CNT"        ,	   0x14F00000010D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_266_CNT"        ,	   0x14F00000010D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_267_CNT"        ,	   0x14F00000010E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_268_CNT"        ,	   0x14F00000010E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_269_CNT"        ,	   0x14F00000010F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_270_CNT"        ,	   0x14F00000010F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_271_CNT"        ,	   0x14F0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_272_CNT"        ,	   0x14F0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_273_CNT"        ,	   0x14F0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_274_CNT"        ,	   0x14F0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_275_CNT"        ,	   0x14F0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_276_CNT"        ,	   0x14F0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_277_CNT"        ,	   0x14F0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_278_CNT"        ,	   0x14F0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_279_CNT"        ,	   0x14F0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_280_CNT"        ,	   0x14F0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_281_CNT"        ,	   0x14F0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_282_CNT"        ,	   0x14F0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_283_CNT"        ,	   0x14F0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_284_CNT"        ,	   0x14F0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_285_CNT"        ,	   0x14F0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_286_CNT"        ,	   0x14F0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_287_CNT"        ,	   0x14F0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
-	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
-	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
-	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
-	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
-	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
-	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
-	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
-	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
-	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
-	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
-	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
-	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
-	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
-	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
-	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
-	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
-	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
-	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
-	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"L2C_BST0"                    ,	   0x11800800007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"L2C_BST1"                    ,	   0x11800800007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"L2C_BST2"                    ,	   0x11800800007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
 	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
 	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
 	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
-	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
-	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
 	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
-	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_INT_STAT"                ,	   0x11800800000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
 	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
 	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
 	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
 	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
 	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
-	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
-	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
-	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
-	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
-	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"L2C_LFB3"                    ,	   0x11800800000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"L2C_OOB"                     ,	   0x11800800000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2C_OOB1"                    ,	   0x11800800000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"L2C_OOB2"                    ,	   0x11800800000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"L2C_OOB3"                    ,	   0x11800800000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
 	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
-	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC1"                    ,	   0x11800800000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC2"                    ,	   0x11800800000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC3"                    ,	   0x11800800000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
 	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
-	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2C_PPGRP"                   ,	   0x11800800000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
 	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
 	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
 	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
@@ -66966,13 +66958,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
 	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
 	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
-	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
-	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
-	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
-	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"L2D_FUS0"                    ,	   0x11800800007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"L2D_FUS1"                    ,	   0x11800800007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"L2D_FUS2"                    ,	   0x11800800007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"L2D_FUS3"                    ,	   0x11800800007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
 	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
-	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
-	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
 	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
 	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
 	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
@@ -66980,7 +66972,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
 	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
 	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
-	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
 	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
 	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
 	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
@@ -66988,23 +66980,23 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
 	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
 	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
-	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
 	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
 	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
-	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
-	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
 	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
 	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
 	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
 	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
-	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
 	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
 	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
 	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
-	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
-	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
 	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
 	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
@@ -67013,13 +67005,13 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
 	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
 	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
-	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
-	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
 	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
 	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
 	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
 	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
-	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
 	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
 	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
@@ -67036,7 +67028,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
 	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
 	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
-	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
 	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
 	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
 	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
@@ -67066,55 +67058,55 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
 	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
 	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
-	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
 	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
-	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
 	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
-	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
 	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
-	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
-	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
-	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
 	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
-	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
 	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
-	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
 	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
-	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
 	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
-	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
 	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
-	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
 	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
-	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
 	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
-	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
-	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
-	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
 	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
-	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
-	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
-	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
 	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
-	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
-	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
-	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
-	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
-	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
-	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
-	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
-	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
-	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
-	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
-	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
-	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
-	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
 	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
-	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
 	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
-	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
 	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
-	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
 	{"MIO_UART2_DLH"               ,	   0x1180000000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
 	{"MIO_UART2_DLL"               ,	   0x1180000000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
 	{"MIO_UART2_FAR"               ,	   0x1180000000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
@@ -67174,590 +67166,590 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	435},
 	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	436},
 	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	437},
-	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
-	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
-	{"NPEI_BIST_STATUS2"           ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
-	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
-	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
-	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
-	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
-	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
-	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
-	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
-	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
-	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
-	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
-	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
-	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
-	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
-	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
-	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
-	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
-	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
-	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
-	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
-	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11F00000085B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
-	{"NPEI_DMA_STATE1"             ,	   0x11F00000086C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
-	{"NPEI_DMA_STATE2"             ,	   0x11F00000086D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
-	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
-	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
-	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
-	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
-	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
-	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
-	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
-	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
-	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
-	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
-	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
-	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
-	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
-	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
-	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
-	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
-	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
-	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
-	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
-	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
-	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
-	{"NPEI_MSI_W1C_ENB0"           ,	   0x11F000000BCF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
-	{"NPEI_MSI_W1C_ENB1"           ,	   0x11F000000BD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
-	{"NPEI_MSI_W1C_ENB2"           ,	   0x11F000000BD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
-	{"NPEI_MSI_W1C_ENB3"           ,	   0x11F000000BD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
-	{"NPEI_MSI_W1S_ENB0"           ,	   0x11F000000BD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
-	{"NPEI_MSI_W1S_ENB1"           ,	   0x11F000000BD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
-	{"NPEI_MSI_W1S_ENB2"           ,	   0x11F000000BD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
-	{"NPEI_MSI_W1S_ENB3"           ,	   0x11F000000BD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
-	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
-	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11F000000BD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
-	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
-	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
-	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
-	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
-	{"NPEI_PKT0_CNTS"              ,	   0x11F000000A400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT1_CNTS"              ,	   0x11F000000A410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT2_CNTS"              ,	   0x11F000000A420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT3_CNTS"              ,	   0x11F000000A430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT4_CNTS"              ,	   0x11F000000A440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT5_CNTS"              ,	   0x11F000000A450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT6_CNTS"              ,	   0x11F000000A460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT7_CNTS"              ,	   0x11F000000A470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT8_CNTS"              ,	   0x11F000000A480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT9_CNTS"              ,	   0x11F000000A490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT10_CNTS"             ,	   0x11F000000A4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT11_CNTS"             ,	   0x11F000000A4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT12_CNTS"             ,	   0x11F000000A4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT13_CNTS"             ,	   0x11F000000A4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT14_CNTS"             ,	   0x11F000000A4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT15_CNTS"             ,	   0x11F000000A4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT16_CNTS"             ,	   0x11F000000A500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT17_CNTS"             ,	   0x11F000000A510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT18_CNTS"             ,	   0x11F000000A520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT19_CNTS"             ,	   0x11F000000A530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT20_CNTS"             ,	   0x11F000000A540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT21_CNTS"             ,	   0x11F000000A550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT22_CNTS"             ,	   0x11F000000A560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT23_CNTS"             ,	   0x11F000000A570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT24_CNTS"             ,	   0x11F000000A580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT25_CNTS"             ,	   0x11F000000A590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT26_CNTS"             ,	   0x11F000000A5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT27_CNTS"             ,	   0x11F000000A5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT28_CNTS"             ,	   0x11F000000A5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT29_CNTS"             ,	   0x11F000000A5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT30_CNTS"             ,	   0x11F000000A5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT31_CNTS"             ,	   0x11F000000A5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
-	{"NPEI_PKT0_IN_BP"             ,	   0x11F000000B800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT1_IN_BP"             ,	   0x11F000000B810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT2_IN_BP"             ,	   0x11F000000B820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT3_IN_BP"             ,	   0x11F000000B830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT4_IN_BP"             ,	   0x11F000000B840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT5_IN_BP"             ,	   0x11F000000B850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT6_IN_BP"             ,	   0x11F000000B860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT7_IN_BP"             ,	   0x11F000000B870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT8_IN_BP"             ,	   0x11F000000B880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT9_IN_BP"             ,	   0x11F000000B890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT10_IN_BP"            ,	   0x11F000000B8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT11_IN_BP"            ,	   0x11F000000B8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT12_IN_BP"            ,	   0x11F000000B8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT13_IN_BP"            ,	   0x11F000000B8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT14_IN_BP"            ,	   0x11F000000B8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT15_IN_BP"            ,	   0x11F000000B8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT16_IN_BP"            ,	   0x11F000000B900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT17_IN_BP"            ,	   0x11F000000B910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT18_IN_BP"            ,	   0x11F000000B920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT19_IN_BP"            ,	   0x11F000000B930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT20_IN_BP"            ,	   0x11F000000B940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT21_IN_BP"            ,	   0x11F000000B950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT22_IN_BP"            ,	   0x11F000000B960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT23_IN_BP"            ,	   0x11F000000B970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT24_IN_BP"            ,	   0x11F000000B980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT25_IN_BP"            ,	   0x11F000000B990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT26_IN_BP"            ,	   0x11F000000B9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT27_IN_BP"            ,	   0x11F000000B9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT28_IN_BP"            ,	   0x11F000000B9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT29_IN_BP"            ,	   0x11F000000B9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT30_IN_BP"            ,	   0x11F000000B9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT31_IN_BP"            ,	   0x11F000000B9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
-	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11F000000A800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11F000000A810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11F000000A820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11F000000A830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11F000000A840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11F000000A850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11F000000A860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11F000000A870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11F000000A880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11F000000A890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11F000000A8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11F000000A8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11F000000A8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11F000000A8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11F000000A8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11F000000A8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11F000000A900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11F000000A910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11F000000A920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11F000000A930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11F000000A940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11F000000A950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11F000000A960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11F000000A970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11F000000A980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11F000000A990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11F000000A9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11F000000A9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11F000000A9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11F000000A9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11F000000A9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11F000000A9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
-	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11F000000AC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11F000000AC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11F000000AC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11F000000AC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11F000000AC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11F000000AC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11F000000AC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11F000000AC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11F000000AC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11F000000AC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11F000000ACA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11F000000ACB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11F000000ACC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11F000000ACD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11F000000ACE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11F000000ACF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11F000000AD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11F000000AD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11F000000AD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11F000000AD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11F000000AD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11F000000AD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11F000000AD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11F000000AD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11F000000AD80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11F000000AD90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11F000000ADA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11F000000ADB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11F000000ADC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11F000000ADD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11F000000ADE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11F000000ADF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
-	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11F000000B000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11F000000B010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11F000000B020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11F000000B030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11F000000B040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11F000000B050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11F000000B060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11F000000B070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11F000000B080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11F000000B090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11F000000B0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11F000000B0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11F000000B0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11F000000B0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11F000000B0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11F000000B0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11F000000B100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11F000000B110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11F000000B120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11F000000B130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11F000000B140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11F000000B150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11F000000B160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11F000000B170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11F000000B180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11F000000B190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11F000000B1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11F000000B1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11F000000B1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11F000000B1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11F000000B1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11F000000B1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
-	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11F000000B400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11F000000B410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11F000000B420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11F000000B430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11F000000B440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11F000000B450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11F000000B460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11F000000B470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11F000000B480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11F000000B490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11F000000B4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11F000000B4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11F000000B4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11F000000B4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11F000000B4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11F000000B4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11F000000B500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11F000000B510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11F000000B520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11F000000B530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11F000000B540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11F000000B550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11F000000B560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11F000000B570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11F000000B580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11F000000B590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11F000000B5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11F000000B5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11F000000B5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11F000000B5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11F000000B5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11F000000B5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
-	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11F0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11F0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11F0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11F0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11F0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11F0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11F0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11F0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11F0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11F0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11F00000094A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11F00000094B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11F00000094C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11F00000094D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11F00000094E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11F00000094F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11F0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11F0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11F0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11F0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11F0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11F0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11F0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11F0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11F0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11F0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11F00000095A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11F00000095B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11F00000095C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11F00000095D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11F00000095E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11F00000095F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
-	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11F0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11F0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11F0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11F0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11F0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11F0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11F0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11F0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11F0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11F0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11F00000098A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11F00000098B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11F00000098C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11F00000098D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11F00000098E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11F00000098F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11F0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11F0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11F0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11F0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11F0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11F0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11F0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11F0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11F0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11F0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11F00000099A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11F00000099B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11F00000099C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11F00000099D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11F00000099E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11F00000099F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
-	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11F0000009CA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11F0000009CB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11F0000009CC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11F0000009CD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11F0000009CE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11F0000009CF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11F0000009D00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11F0000009D10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11F0000009D20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11F0000009D30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11F0000009D40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11F0000009D50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11F0000009D60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11F0000009D70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11F0000009D80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11F0000009D90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11F0000009DA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11F0000009DB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11F0000009DC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11F0000009DD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11F0000009DE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11F0000009DF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
-	{"NPEI_PKT_CNT_INT"            ,	   0x11F0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
-	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11F0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
-	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11F00000090B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
-	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11F00000090A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
-	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11F0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
-	{"NPEI_PKT_DPADDR"             ,	   0x11F0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
-	{"NPEI_PKT_IN_BP"              ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
-	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11F000000A000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11F000000A010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11F000000A020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11F000000A030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11F000000A040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11F000000A050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11F000000A060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11F000000A070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11F000000A080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11F000000A090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11F000000A0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11F000000A0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11F000000A0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11F000000A0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11F000000A0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11F000000A0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11F000000A100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11F000000A110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11F000000A120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11F000000A130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11F000000A140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11F000000A150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11F000000A160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11F000000A170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11F000000A180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11F000000A190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11F000000A1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11F000000A1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11F000000A1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11F000000A1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11F000000A1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11F000000A1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
-	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
-	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11F00000091A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
-	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11F0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
-	{"NPEI_PKT_INSTR_ENB"          ,	   0x11F0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
-	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11F0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
-	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11F0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
-	{"NPEI_PKT_INT_LEVELS"         ,	   0x11F0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
-	{"NPEI_PKT_IPTR"               ,	   0x11F0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
-	{"NPEI_PKT_OUT_BMODE"          ,	   0x11F00000090D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
-	{"NPEI_PKT_OUT_ENB"            ,	   0x11F0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	520},
-	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11F0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	521},
-	{"NPEI_PKT_PCIE_PORT"          ,	   0x11F00000090E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	522},
-	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	523},
-	{"NPEI_PKT_SLIST_ES"           ,	   0x11F0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	524},
-	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11F0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
-	{"NPEI_PKT_SLIST_NS"           ,	   0x11F0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	526},
-	{"NPEI_PKT_SLIST_ROR"          ,	   0x11F0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	527},
-	{"NPEI_PKT_TIME_INT"           ,	   0x11F0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	528},
-	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11F0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	529},
-	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	530},
-	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	531},
-	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	532},
-	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	533},
-	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	534},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11f0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11f0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11f0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11f0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11f0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11f0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11f0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11f0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11f0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11f0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11f00000080a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11f00000080b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11f00000080c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11f00000080d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11f00000080e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11f00000080f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11f0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11f0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11f0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11f0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11f0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11f0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11f0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11f0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11f0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11f0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11f00000081a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11f00000081b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11f00000081c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11f00000081d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11f00000081e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11f00000081f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BIST_STATUS"            ,	   0x11f0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_BIST_STATUS2"           ,	   0x11f0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_CTL_PORT0"              ,	   0x11f0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_CTL_PORT1"              ,	   0x11f0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_CTL_STATUS"             ,	   0x11f0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_CTL_STATUS2"            ,	   0x11f000000bc00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11f00000085f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_DBG_DATA"               ,	   0x11f0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_DBG_SELECT"             ,	   0x11f0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11f0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11f0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11f0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11f0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11f0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA0_DBELL"             ,	   0x11f00000083b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA1_DBELL"             ,	   0x11f00000083c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA2_DBELL"             ,	   0x11f00000083d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA3_DBELL"             ,	   0x11f00000083e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA4_DBELL"             ,	   0x11f00000083f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11f0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11f0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11f0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11f0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11f0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA0_NADDR"             ,	   0x11f00000084a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA1_NADDR"             ,	   0x11f00000084b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA2_NADDR"             ,	   0x11f00000084c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA3_NADDR"             ,	   0x11f00000084d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA4_NADDR"             ,	   0x11f00000084e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11f00000085c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11f00000085d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_DMA_CNTS"               ,	   0x11f00000085e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_DMA_CONTROL"            ,	   0x11f00000083a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11f00000085b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_DMA_STATE1"             ,	   0x11f00000086c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_DMA_STATE2"             ,	   0x11f00000086d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_INT_A_ENB"              ,	   0x11f0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_INT_A_ENB2"             ,	   0x11f000000bce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_INT_A_SUM"              ,	   0x11f0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_INT_ENB"                ,	   0x11f0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_INT_ENB2"               ,	   0x11f000000bcd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_INT_INFO"               ,	   0x11f0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
+	{"NPEI_INT_SUM"                ,	   0x11f0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
+	{"NPEI_INT_SUM2"               ,	   0x11f000000bcc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11f0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11f0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11f00000084f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11f0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11f0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11f00000082a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11f00000082b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11f00000082c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11f00000082d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11f00000082e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11f00000082f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11f0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11f0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11f0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11f0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11f0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11f0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11f0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11f0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MSI_ENB0"               ,	   0x11f000000bc50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
+	{"NPEI_MSI_ENB1"               ,	   0x11f000000bc60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
+	{"NPEI_MSI_ENB2"               ,	   0x11f000000bc70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
+	{"NPEI_MSI_ENB3"               ,	   0x11f000000bc80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
+	{"NPEI_MSI_RCV0"               ,	   0x11f000000bc10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
+	{"NPEI_MSI_RCV1"               ,	   0x11f000000bc20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
+	{"NPEI_MSI_RCV2"               ,	   0x11f000000bc30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
+	{"NPEI_MSI_RCV3"               ,	   0x11f000000bc40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11f000000bca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_MSI_W1C_ENB0"           ,	   0x11f000000bcf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_MSI_W1C_ENB1"           ,	   0x11f000000bd00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_MSI_W1C_ENB2"           ,	   0x11f000000bd10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_MSI_W1C_ENB3"           ,	   0x11f000000bd20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_MSI_W1S_ENB0"           ,	   0x11f000000bd30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_MSI_W1S_ENB1"           ,	   0x11f000000bd40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_MSI_W1S_ENB2"           ,	   0x11f000000bd50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_MSI_W1S_ENB3"           ,	   0x11f000000bd60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11f000000bc90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
+	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11f000000bd70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11f000000bcb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11f0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11f0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11f0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
+	{"NPEI_PKT0_CNTS"              ,	   0x11f000000a400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT1_CNTS"              ,	   0x11f000000a410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT2_CNTS"              ,	   0x11f000000a420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT3_CNTS"              ,	   0x11f000000a430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT4_CNTS"              ,	   0x11f000000a440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT5_CNTS"              ,	   0x11f000000a450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT6_CNTS"              ,	   0x11f000000a460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT7_CNTS"              ,	   0x11f000000a470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT8_CNTS"              ,	   0x11f000000a480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT9_CNTS"              ,	   0x11f000000a490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT10_CNTS"             ,	   0x11f000000a4a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT11_CNTS"             ,	   0x11f000000a4b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT12_CNTS"             ,	   0x11f000000a4c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT13_CNTS"             ,	   0x11f000000a4d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT14_CNTS"             ,	   0x11f000000a4e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT15_CNTS"             ,	   0x11f000000a4f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT16_CNTS"             ,	   0x11f000000a500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT17_CNTS"             ,	   0x11f000000a510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT18_CNTS"             ,	   0x11f000000a520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT19_CNTS"             ,	   0x11f000000a530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT20_CNTS"             ,	   0x11f000000a540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT21_CNTS"             ,	   0x11f000000a550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT22_CNTS"             ,	   0x11f000000a560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT23_CNTS"             ,	   0x11f000000a570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT24_CNTS"             ,	   0x11f000000a580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT25_CNTS"             ,	   0x11f000000a590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT26_CNTS"             ,	   0x11f000000a5a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT27_CNTS"             ,	   0x11f000000a5b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT28_CNTS"             ,	   0x11f000000a5c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT29_CNTS"             ,	   0x11f000000a5d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT30_CNTS"             ,	   0x11f000000a5e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT31_CNTS"             ,	   0x11f000000a5f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT0_IN_BP"             ,	   0x11f000000b800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT1_IN_BP"             ,	   0x11f000000b810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT2_IN_BP"             ,	   0x11f000000b820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT3_IN_BP"             ,	   0x11f000000b830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT4_IN_BP"             ,	   0x11f000000b840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT5_IN_BP"             ,	   0x11f000000b850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT6_IN_BP"             ,	   0x11f000000b860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT7_IN_BP"             ,	   0x11f000000b870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT8_IN_BP"             ,	   0x11f000000b880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT9_IN_BP"             ,	   0x11f000000b890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT10_IN_BP"            ,	   0x11f000000b8a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT11_IN_BP"            ,	   0x11f000000b8b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT12_IN_BP"            ,	   0x11f000000b8c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT13_IN_BP"            ,	   0x11f000000b8d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT14_IN_BP"            ,	   0x11f000000b8e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT15_IN_BP"            ,	   0x11f000000b8f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT16_IN_BP"            ,	   0x11f000000b900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT17_IN_BP"            ,	   0x11f000000b910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT18_IN_BP"            ,	   0x11f000000b920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT19_IN_BP"            ,	   0x11f000000b930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT20_IN_BP"            ,	   0x11f000000b940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT21_IN_BP"            ,	   0x11f000000b950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT22_IN_BP"            ,	   0x11f000000b960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT23_IN_BP"            ,	   0x11f000000b970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT24_IN_BP"            ,	   0x11f000000b980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT25_IN_BP"            ,	   0x11f000000b990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT26_IN_BP"            ,	   0x11f000000b9a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT27_IN_BP"            ,	   0x11f000000b9b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT28_IN_BP"            ,	   0x11f000000b9c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT29_IN_BP"            ,	   0x11f000000b9d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT30_IN_BP"            ,	   0x11f000000b9e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT31_IN_BP"            ,	   0x11f000000b9f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11f000000a800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11f000000a810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11f000000a820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11f000000a830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11f000000a840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11f000000a850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11f000000a860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11f000000a870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11f000000a880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11f000000a890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11f000000a8a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11f000000a8b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11f000000a8c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11f000000a8d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11f000000a8e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11f000000a8f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11f000000a900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11f000000a910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11f000000a920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11f000000a930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11f000000a940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11f000000a950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11f000000a960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11f000000a970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11f000000a980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11f000000a990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11f000000a9a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11f000000a9b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11f000000a9c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11f000000a9d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11f000000a9e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11f000000a9f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11f000000ac00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11f000000ac10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11f000000ac20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11f000000ac30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11f000000ac40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11f000000ac50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11f000000ac60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11f000000ac70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11f000000ac80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11f000000ac90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11f000000aca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11f000000acb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11f000000acc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11f000000acd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11f000000ace0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11f000000acf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11f000000ad00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11f000000ad10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11f000000ad20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11f000000ad30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11f000000ad40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11f000000ad50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11f000000ad60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11f000000ad70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11f000000ad80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11f000000ad90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11f000000ada0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11f000000adb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11f000000adc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11f000000add0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11f000000ade0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11f000000adf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11f000000b000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11f000000b010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11f000000b020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11f000000b030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11f000000b040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11f000000b050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11f000000b060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11f000000b070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11f000000b080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11f000000b090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11f000000b0a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11f000000b0b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11f000000b0c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11f000000b0d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11f000000b0e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11f000000b0f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11f000000b100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11f000000b110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11f000000b120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11f000000b130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11f000000b140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11f000000b150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11f000000b160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11f000000b170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11f000000b180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11f000000b190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11f000000b1a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11f000000b1b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11f000000b1c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11f000000b1d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11f000000b1e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11f000000b1f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11f000000b400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11f000000b410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11f000000b420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11f000000b430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11f000000b440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11f000000b450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11f000000b460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11f000000b470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11f000000b480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11f000000b490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11f000000b4a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11f000000b4b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11f000000b4c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11f000000b4d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11f000000b4e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11f000000b4f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11f000000b500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11f000000b510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11f000000b520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11f000000b530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11f000000b540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11f000000b550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11f000000b560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11f000000b570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11f000000b580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11f000000b590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11f000000b5a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11f000000b5b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11f000000b5c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11f000000b5d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11f000000b5e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11f000000b5f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11f0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11f0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11f0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11f0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11f0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11f0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11f0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11f0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11f0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11f0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11f00000094a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11f00000094b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11f00000094c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11f00000094d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11f00000094e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11f00000094f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11f0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11f0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11f0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11f0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11f0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11f0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11f0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11f0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11f0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11f0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11f00000095a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11f00000095b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11f00000095c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11f00000095d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11f00000095e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11f00000095f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11f0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11f0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11f0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11f0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11f0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11f0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11f0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11f0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11f0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11f0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11f00000098a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11f00000098b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11f00000098c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11f00000098d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11f00000098e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11f00000098f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11f0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11f0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11f0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11f0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11f0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11f0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11f0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11f0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11f0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11f0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11f00000099a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11f00000099b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11f00000099c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11f00000099d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11f00000099e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11f00000099f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11f0000009c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11f0000009ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11f0000009cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11f0000009cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11f0000009cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11f0000009ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11f0000009cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11f0000009d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11f0000009d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11f0000009d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11f0000009d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11f0000009d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11f0000009d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11f0000009d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11f0000009d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11f0000009d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11f0000009d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11f0000009da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11f0000009db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11f0000009dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11f0000009dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11f0000009de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11f0000009df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT_CNT_INT"            ,	   0x11f0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
+	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11f0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
+	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11f00000090b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
+	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11f00000090a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
+	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11f0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
+	{"NPEI_PKT_DPADDR"             ,	   0x11f0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
+	{"NPEI_PKT_IN_BP"              ,	   0x11f00000086b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
+	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11f000000a000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11f000000a010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11f000000a020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11f000000a030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11f000000a040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11f000000a050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11f000000a060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11f000000a070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11f000000a080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11f000000a090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11f000000a0a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11f000000a0b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11f000000a0c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11f000000a0d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11f000000a0e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11f000000a0f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11f000000a100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11f000000a110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11f000000a120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11f000000a130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11f000000a140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11f000000a150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11f000000a160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11f000000a170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11f000000a180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11f000000a190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11f000000a1a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11f000000a1b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11f000000a1c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11f000000a1d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11f000000a1e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11f000000a1f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11f00000086a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
+	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11f00000091a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
+	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11f0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
+	{"NPEI_PKT_INSTR_ENB"          ,	   0x11f0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
+	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11f0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
+	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11f0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
+	{"NPEI_PKT_INT_LEVELS"         ,	   0x11f0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
+	{"NPEI_PKT_IPTR"               ,	   0x11f0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
+	{"NPEI_PKT_OUT_BMODE"          ,	   0x11f00000090d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
+	{"NPEI_PKT_OUT_ENB"            ,	   0x11f0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	520},
+	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11f0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	521},
+	{"NPEI_PKT_PCIE_PORT"          ,	   0x11f00000090e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	522},
+	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11f0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	523},
+	{"NPEI_PKT_SLIST_ES"           ,	   0x11f0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	524},
+	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11f0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
+	{"NPEI_PKT_SLIST_NS"           ,	   0x11f0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	526},
+	{"NPEI_PKT_SLIST_ROR"          ,	   0x11f0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	527},
+	{"NPEI_PKT_TIME_INT"           ,	   0x11f0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	528},
+	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11f0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	529},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11f0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	530},
+	{"NPEI_SCRATCH_1"              ,	   0x11f0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	531},
+	{"NPEI_STATE1"                 ,	   0x11f0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	532},
+	{"NPEI_STATE2"                 ,	   0x11f0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	533},
+	{"NPEI_STATE3"                 ,	   0x11f0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	534},
 	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	535},
 	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	536},
 	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	537},
 	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	538},
 	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	539},
-	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	540},
-	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
-	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
-	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
-	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
-	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
-	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
-	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
-	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
-	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
-	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
-	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
-	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
-	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
-	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
-	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
-	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
-	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
-	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
-	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
-	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
-	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
-	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
-	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
-	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
-	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
-	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
-	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
-	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
-	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
-	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
-	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
-	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
-	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
-	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
-	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
-	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
-	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
-	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
-	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
-	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
-	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
-	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
-	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
-	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
-	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
-	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
-	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
-	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
-	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
-	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
-	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
-	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
-	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
-	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
-	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
-	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
-	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
-	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
-	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
-	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
-	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
-	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
-	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
-	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
-	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
-	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
-	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
-	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
-	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
-	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
-	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
-	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
-	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
-	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
-	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
-	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
-	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"NPEI_WINDOW_CTL"             ,	   0x11f0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	540},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
 	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
 	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
 	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
 	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
 	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
 	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
-	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
-	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
 	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
 	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
 	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
 	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
 	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
 	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
-	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
-	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
 	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
 	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
 	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
 	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
 	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
 	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
-	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
-	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
 	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
 	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
 	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
 	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
 	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
 	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
-	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
-	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
 	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
 	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
 	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
@@ -67768,62 +67760,62 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
 	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
 	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
-	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
-	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
 	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
 	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
 	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
 	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
 	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
 	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
-	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
-	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
 	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
 	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
 	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
 	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
 	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
 	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
-	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
-	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
 	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
 	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
 	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
 	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
 	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
 	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
-	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
-	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
-	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
-	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
-	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
-	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
-	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
-	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
 	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
 	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
 	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
 	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
 	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
 	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
-	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
-	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
 	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
 	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
 	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
 	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
 	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
 	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
-	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
-	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
 	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
 	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
 	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
 	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
 	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
 	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
-	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
-	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
 	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
 	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
 	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
@@ -67834,537 +67826,522 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
 	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
 	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
-	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
-	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
 	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
 	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
 	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
 	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
 	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
 	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
-	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
-	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
 	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
 	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
 	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
 	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
-	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
-	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
 	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
 	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
 	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
 	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
 	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
 	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
-	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
-	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
 	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
 	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
 	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
 	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
 	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
 	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
-	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
-	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
 	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
 	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
-	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
-	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
-	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
-	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
-	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
-	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
 	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
 	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
 	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
 	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
-	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
-	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
-	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
-	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
-	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
-	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
-	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
-	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
-	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
-	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
-	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
-	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
-	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
-	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
-	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
-	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
-	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
-	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
-	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
-	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
-	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
-	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
-	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
-	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
-	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
-	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
-	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
-	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
-	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
-	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
-	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
-	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
-	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
-	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
-	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
-	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
-	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
-	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
-	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
-	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
-	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
-	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
-	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
-	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
-	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
-	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
-	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
-	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
-	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
-	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
-	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
-	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
-	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
-	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
-	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
-	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
-	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
-	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
-	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
-	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
-	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
-	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
-	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
-	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
-	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
-	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
-	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
-	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
-	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
-	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
-	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
-	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
-	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
-	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
-	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
-	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
-	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
-	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
-	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
-	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
-	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
-	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
-	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
-	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
-	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
-	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
-	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
-	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
-	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
-	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
-	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
-	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
-	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
-	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
-	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
-	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
-	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
-	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
-	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
-	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
-	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
-	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
-	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
-	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
-	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
-	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
-	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
-	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
-	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_BIST_STATUS"           ,	   0x11800c8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC1_BIST_STATUS"           ,	   0x11800d0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800c8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800d0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PESC0_CFG_RD"                ,	   0x11800c8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PESC1_CFG_RD"                ,	   0x11800d0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PESC0_CFG_WR"                ,	   0x11800c8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PESC1_CFG_WR"                ,	   0x11800d0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800c8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800d0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PESC0_CTL_STATUS"            ,	   0x11800c8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PESC1_CTL_STATUS"            ,	   0x11800d0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800c8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800d0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PESC0_DBG_INFO"              ,	   0x11800c8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PESC1_DBG_INFO"              ,	   0x11800d0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800c80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800d00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800c8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800d0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800c8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800d0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800c8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800d0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800c8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800d0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800c8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800c8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800c8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800c8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800d0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800d0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800d0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800d0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800c8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800c8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800c8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800c8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800d0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800d0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800d0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800d0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800c8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800d0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800a0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
 	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
 	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
 	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
@@ -68391,9 +68368,9 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
 	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
 	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
-	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
-	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
-	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
 	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
 	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
 	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
@@ -68403,7 +68380,7 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
 	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
 	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
-	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
 	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	817},
 	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	818},
 	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
@@ -68418,14 +68395,14 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
 	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	822},
 	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
-	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
-	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
 	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
 	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
 	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
@@ -68433,22 +68410,22 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
 	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
 	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
-	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
-	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
 	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
 	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
 	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
 	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
-	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
-	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
-	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
-	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
 	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
 	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
 	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
@@ -68481,34 +68458,34 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
 	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
 	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
-	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
 	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
 	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
 	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
 	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
-	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
 	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
 	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
 	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
@@ -68554,309 +68531,309 @@ static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
 	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
 	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
 	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
-	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
-	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
-	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
-	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
-	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
-	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
-	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
-	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
-	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
-	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
-	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
-	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
-	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
-	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
-	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
-	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
-	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
-	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
-	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
-	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
-	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
-	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
-	{"USBC1_DAINT"                 ,	   0x17F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
-	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
-	{"USBC1_DAINTMSK"              ,	   0x17F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
-	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
-	{"USBC1_DCFG"                  ,	   0x17F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
-	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
-	{"USBC1_DCTL"                  ,	   0x17F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
-	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC1_DIEPCTL000"            ,	   0x17F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC1_DIEPCTL001"            ,	   0x17F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC1_DIEPCTL002"            ,	   0x17F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC1_DIEPCTL003"            ,	   0x17F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC1_DIEPCTL004"            ,	   0x17F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
-	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC1_DIEPINT000"            ,	   0x17F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC1_DIEPINT001"            ,	   0x17F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC1_DIEPINT002"            ,	   0x17F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC1_DIEPINT003"            ,	   0x17F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC1_DIEPINT004"            ,	   0x17F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
-	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
-	{"USBC1_DIEPMSK"               ,	   0x17F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
-	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC1_DIEPTSIZ000"           ,	   0x17F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC1_DIEPTSIZ001"           ,	   0x17F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC1_DIEPTSIZ002"           ,	   0x17F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC1_DIEPTSIZ003"           ,	   0x17F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC1_DIEPTSIZ004"           ,	   0x17F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
-	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC1_DOEPCTL000"            ,	   0x17F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC1_DOEPCTL001"            ,	   0x17F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC1_DOEPCTL002"            ,	   0x17F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC1_DOEPCTL003"            ,	   0x17F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC1_DOEPCTL004"            ,	   0x17F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
-	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC1_DOEPINT000"            ,	   0x17F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC1_DOEPINT001"            ,	   0x17F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC1_DOEPINT002"            ,	   0x17F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC1_DOEPINT003"            ,	   0x17F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC1_DOEPINT004"            ,	   0x17F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
-	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
-	{"USBC1_DOEPMSK"               ,	   0x17F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
-	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC1_DOEPTSIZ000"           ,	   0x17F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC1_DOEPTSIZ001"           ,	   0x17F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC1_DOEPTSIZ002"           ,	   0x17F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC1_DOEPTSIZ003"           ,	   0x17F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC1_DOEPTSIZ004"           ,	   0x17F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
-	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC1_DPTXFSIZ001"           ,	   0x17F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC1_DPTXFSIZ002"           ,	   0x17F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC1_DPTXFSIZ003"           ,	   0x17F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC1_DPTXFSIZ004"           ,	   0x17F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
-	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
-	{"USBC1_DSTS"                  ,	   0x17F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
-	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
-	{"USBC1_DTKNQR1"               ,	   0x17F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
-	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
-	{"USBC1_DTKNQR2"               ,	   0x17F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
-	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
-	{"USBC1_DTKNQR3"               ,	   0x17F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
-	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
-	{"USBC1_DTKNQR4"               ,	   0x17F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
-	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
-	{"USBC1_GAHBCFG"               ,	   0x17F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
-	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
-	{"USBC1_GHWCFG1"               ,	   0x17F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
-	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
-	{"USBC1_GHWCFG2"               ,	   0x17F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
-	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
-	{"USBC1_GHWCFG3"               ,	   0x17F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
-	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
-	{"USBC1_GHWCFG4"               ,	   0x17F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
-	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
-	{"USBC1_GINTMSK"               ,	   0x17F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
-	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
-	{"USBC1_GINTSTS"               ,	   0x17F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
-	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC1_GNPTXFSIZ"             ,	   0x17F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
-	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
-	{"USBC1_GNPTXSTS"              ,	   0x17F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
-	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC1_GOTGCTL"               ,	   0x17F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
-	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC1_GOTGINT"               ,	   0x17F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
-	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC1_GRSTCTL"               ,	   0x17F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
-	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC1_GRXFSIZ"               ,	   0x17F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
-	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
-	{"USBC1_GRXSTSPD"              ,	   0x17F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
-	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
-	{"USBC1_GRXSTSPH"              ,	   0x17F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
-	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
-	{"USBC1_GRXSTSRD"              ,	   0x17F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
-	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
-	{"USBC1_GRXSTSRH"              ,	   0x17F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
-	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
-	{"USBC1_GSNPSID"               ,	   0x17F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
-	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC1_GUSBCFG"               ,	   0x17F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
-	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
-	{"USBC1_HAINT"                 ,	   0x17F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
-	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
-	{"USBC1_HAINTMSK"              ,	   0x17F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
-	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR000"             ,	   0x17F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR001"             ,	   0x17F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR002"             ,	   0x17F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR003"             ,	   0x17F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR004"             ,	   0x17F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR005"             ,	   0x17F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR006"             ,	   0x17F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC1_HCCHAR007"             ,	   0x17F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
-	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
-	{"USBC1_HCFG"                  ,	   0x17F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
-	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT000"              ,	   0x17F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT001"              ,	   0x17F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT002"              ,	   0x17F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT003"              ,	   0x17F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT004"              ,	   0x17F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT005"              ,	   0x17F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT006"              ,	   0x17F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC1_HCINT007"              ,	   0x17F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
-	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK000"           ,	   0x17F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK001"           ,	   0x17F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK002"           ,	   0x17F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK003"           ,	   0x17F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK004"           ,	   0x17F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK005"           ,	   0x17F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK006"           ,	   0x17F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC1_HCINTMSK007"           ,	   0x17F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
-	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT000"             ,	   0x17F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT001"             ,	   0x17F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT002"             ,	   0x17F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT003"             ,	   0x17F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT004"             ,	   0x17F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT005"             ,	   0x17F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT006"             ,	   0x17F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC1_HCSPLT007"             ,	   0x17F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
-	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ000"             ,	   0x17F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ001"             ,	   0x17F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ002"             ,	   0x17F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ003"             ,	   0x17F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ004"             ,	   0x17F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ005"             ,	   0x17F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ006"             ,	   0x17F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC1_HCTSIZ007"             ,	   0x17F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
-	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
-	{"USBC1_HFIR"                  ,	   0x17F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
-	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
-	{"USBC1_HFNUM"                 ,	   0x17F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
-	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
-	{"USBC1_HPRT"                  ,	   0x17F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
-	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
-	{"USBC1_HPTXFSIZ"              ,	   0x17F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
-	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
-	{"USBC1_HPTXSTS"               ,	   0x17F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
-	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO000"          ,	   0x17F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO001"          ,	   0x17F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO002"          ,	   0x17F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO003"          ,	   0x17F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO004"          ,	   0x17F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO005"          ,	   0x17F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO006"          ,	   0x17F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC1_NPTXDFIFO007"          ,	   0x17F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
-	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
-	{"USBC1_PCGCCTL"               ,	   0x17F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
-	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
-	{"USBN1_BIST_STATUS"           ,	   0x11800780007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"USBC0_DAINT"                 ,	   0x16f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC1_DAINT"                 ,	   0x17f0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC0_DAINTMSK"              ,	   0x16f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC1_DAINTMSK"              ,	   0x17f001000081cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC0_DCFG"                  ,	   0x16f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC1_DCFG"                  ,	   0x17f0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC0_DCTL"                  ,	   0x16f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC1_DCTL"                  ,	   0x17f0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC0_DIEPCTL000"            ,	   0x16f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL001"            ,	   0x16f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL002"            ,	   0x16f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL003"            ,	   0x16f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL004"            ,	   0x16f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL000"            ,	   0x17f0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL001"            ,	   0x17f0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL002"            ,	   0x17f0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL003"            ,	   0x17f0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL004"            ,	   0x17f0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPINT000"            ,	   0x16f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT001"            ,	   0x16f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT002"            ,	   0x16f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT003"            ,	   0x16f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT004"            ,	   0x16f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT000"            ,	   0x17f0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT001"            ,	   0x17f0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT002"            ,	   0x17f0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT003"            ,	   0x17f0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT004"            ,	   0x17f0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPMSK"               ,	   0x16f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC1_DIEPMSK"               ,	   0x17f0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ000"           ,	   0x17f0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ001"           ,	   0x17f0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ002"           ,	   0x17f0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ003"           ,	   0x17f0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ004"           ,	   0x17f0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DOEPCTL000"            ,	   0x16f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL001"            ,	   0x16f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL002"            ,	   0x16f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL003"            ,	   0x16f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL004"            ,	   0x16f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL000"            ,	   0x17f0010000b00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL001"            ,	   0x17f0010000b20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL002"            ,	   0x17f0010000b40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL003"            ,	   0x17f0010000b60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL004"            ,	   0x17f0010000b80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPINT000"            ,	   0x16f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT001"            ,	   0x16f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT002"            ,	   0x16f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT003"            ,	   0x16f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT004"            ,	   0x16f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT000"            ,	   0x17f0010000b08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT001"            ,	   0x17f0010000b28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT002"            ,	   0x17f0010000b48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT003"            ,	   0x17f0010000b68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT004"            ,	   0x17f0010000b88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPMSK"               ,	   0x16f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC1_DOEPMSK"               ,	   0x17f0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ000"           ,	   0x17f0010000b10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ001"           ,	   0x17f0010000b30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ002"           ,	   0x17f0010000b50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ003"           ,	   0x17f0010000b70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ004"           ,	   0x17f0010000b90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ001"           ,	   0x17f0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ002"           ,	   0x17f0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ003"           ,	   0x17f001000010cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ004"           ,	   0x17f0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DSTS"                  ,	   0x16f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC1_DSTS"                  ,	   0x17f0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC0_DTKNQR1"               ,	   0x16f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC1_DTKNQR1"               ,	   0x17f0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC0_DTKNQR2"               ,	   0x16f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC1_DTKNQR2"               ,	   0x17f0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC0_DTKNQR3"               ,	   0x16f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC1_DTKNQR3"               ,	   0x17f0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC0_DTKNQR4"               ,	   0x16f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC1_DTKNQR4"               ,	   0x17f0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC0_GAHBCFG"               ,	   0x16f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC1_GAHBCFG"               ,	   0x17f0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC0_GHWCFG1"               ,	   0x16f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC1_GHWCFG1"               ,	   0x17f0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC0_GHWCFG2"               ,	   0x16f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC1_GHWCFG2"               ,	   0x17f0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC0_GHWCFG3"               ,	   0x16f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC1_GHWCFG3"               ,	   0x17f001000004cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC0_GHWCFG4"               ,	   0x16f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC1_GHWCFG4"               ,	   0x17f0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC0_GINTMSK"               ,	   0x16f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC1_GINTMSK"               ,	   0x17f0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC0_GINTSTS"               ,	   0x16f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC1_GINTSTS"               ,	   0x17f0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC1_GNPTXFSIZ"             ,	   0x17f0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_GNPTXSTS"              ,	   0x16f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC1_GNPTXSTS"              ,	   0x17f001000002cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC0_GOTGCTL"               ,	   0x16f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC1_GOTGCTL"               ,	   0x17f0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_GOTGINT"               ,	   0x16f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC1_GOTGINT"               ,	   0x17f0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_GRSTCTL"               ,	   0x16f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC1_GRSTCTL"               ,	   0x17f0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_GRXFSIZ"               ,	   0x16f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC1_GRXFSIZ"               ,	   0x17f0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_GRXSTSPD"              ,	   0x16f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC1_GRXSTSPD"              ,	   0x17f0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC0_GRXSTSPH"              ,	   0x16f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC1_GRXSTSPH"              ,	   0x17f0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC0_GRXSTSRD"              ,	   0x16f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC1_GRXSTSRD"              ,	   0x17f001004001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC0_GRXSTSRH"              ,	   0x16f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC1_GRXSTSRH"              ,	   0x17f001000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC0_GSNPSID"               ,	   0x16f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC1_GSNPSID"               ,	   0x17f0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC0_GUSBCFG"               ,	   0x16f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC1_GUSBCFG"               ,	   0x17f001000000cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_HAINT"                 ,	   0x16f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBC1_HAINT"                 ,	   0x17f0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBC0_HAINTMSK"              ,	   0x16f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
+	{"USBC1_HAINTMSK"              ,	   0x17f0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
+	{"USBC0_HCCHAR000"             ,	   0x16f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR001"             ,	   0x16f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR002"             ,	   0x16f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR003"             ,	   0x16f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR004"             ,	   0x16f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR005"             ,	   0x16f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR006"             ,	   0x16f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR007"             ,	   0x16f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR000"             ,	   0x17f0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR001"             ,	   0x17f0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR002"             ,	   0x17f0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR003"             ,	   0x17f0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR004"             ,	   0x17f0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR005"             ,	   0x17f00100005a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR006"             ,	   0x17f00100005c0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR007"             ,	   0x17f00100005e0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCFG"                  ,	   0x16f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
+	{"USBC1_HCFG"                  ,	   0x17f0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
+	{"USBC0_HCINT000"              ,	   0x16f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT001"              ,	   0x16f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT002"              ,	   0x16f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT003"              ,	   0x16f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT004"              ,	   0x16f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT005"              ,	   0x16f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT006"              ,	   0x16f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT007"              ,	   0x16f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT000"              ,	   0x17f0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT001"              ,	   0x17f0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT002"              ,	   0x17f0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT003"              ,	   0x17f0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT004"              ,	   0x17f0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT005"              ,	   0x17f00100005a8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT006"              ,	   0x17f00100005c8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT007"              ,	   0x17f00100005e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINTMSK000"           ,	   0x16f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK001"           ,	   0x16f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK002"           ,	   0x16f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK003"           ,	   0x16f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK004"           ,	   0x16f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK005"           ,	   0x16f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK006"           ,	   0x16f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK007"           ,	   0x16f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK000"           ,	   0x17f001000050cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK001"           ,	   0x17f001000052cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK002"           ,	   0x17f001000054cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK003"           ,	   0x17f001000056cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK004"           ,	   0x17f001000058cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK005"           ,	   0x17f00100005acull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK006"           ,	   0x17f00100005ccull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK007"           ,	   0x17f00100005ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCSPLT000"             ,	   0x16f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT001"             ,	   0x16f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT002"             ,	   0x16f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT003"             ,	   0x16f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT004"             ,	   0x16f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT005"             ,	   0x16f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT006"             ,	   0x16f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT007"             ,	   0x16f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT000"             ,	   0x17f0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT001"             ,	   0x17f0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT002"             ,	   0x17f0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT003"             ,	   0x17f0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT004"             ,	   0x17f0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT005"             ,	   0x17f00100005a4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT006"             ,	   0x17f00100005c4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT007"             ,	   0x17f00100005e4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCTSIZ000"             ,	   0x16f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ001"             ,	   0x16f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ002"             ,	   0x16f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ003"             ,	   0x16f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ004"             ,	   0x16f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ005"             ,	   0x16f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ006"             ,	   0x16f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ007"             ,	   0x16f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ000"             ,	   0x17f0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ001"             ,	   0x17f0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ002"             ,	   0x17f0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ003"             ,	   0x17f0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ004"             ,	   0x17f0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ005"             ,	   0x17f00100005b0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ006"             ,	   0x17f00100005d0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ007"             ,	   0x17f00100005f0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HFIR"                  ,	   0x16f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
+	{"USBC1_HFIR"                  ,	   0x17f0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
+	{"USBC0_HFNUM"                 ,	   0x16f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
+	{"USBC1_HFNUM"                 ,	   0x17f0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
+	{"USBC0_HPRT"                  ,	   0x16f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
+	{"USBC1_HPRT"                  ,	   0x17f0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
+	{"USBC0_HPTXFSIZ"              ,	   0x16f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
+	{"USBC1_HPTXFSIZ"              ,	   0x17f0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
+	{"USBC0_HPTXSTS"               ,	   0x16f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
+	{"USBC1_HPTXSTS"               ,	   0x17f0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO000"          ,	   0x17f0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO001"          ,	   0x17f0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO002"          ,	   0x17f0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO003"          ,	   0x17f0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO004"          ,	   0x17f0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO005"          ,	   0x17f0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO006"          ,	   0x17f0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO007"          ,	   0x17f0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_PCGCCTL"               ,	   0x16f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
+	{"USBC1_PCGCCTL"               ,	   0x17f0010000e00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"USBN1_BIST_STATUS"           ,	   0x11800780007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
 	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
 	{"USBN1_CLK_CTL"               ,	   0x1180078000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
-	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
-	{"USBN1_CTL_STATUS"            ,	   0x17F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
-	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
-	{"USBN1_DMA0_INB_CHN0"         ,	   0x17F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
-	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
-	{"USBN1_DMA0_INB_CHN1"         ,	   0x17F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
-	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
-	{"USBN1_DMA0_INB_CHN2"         ,	   0x17F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
-	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
-	{"USBN1_DMA0_INB_CHN3"         ,	   0x17F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
-	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
-	{"USBN1_DMA0_INB_CHN4"         ,	   0x17F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
-	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
-	{"USBN1_DMA0_INB_CHN5"         ,	   0x17F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
-	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
-	{"USBN1_DMA0_INB_CHN6"         ,	   0x17F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
-	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
-	{"USBN1_DMA0_INB_CHN7"         ,	   0x17F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
-	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
-	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
-	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
-	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
-	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
-	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
-	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
-	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
-	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
-	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
-	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
-	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
-	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
-	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
-	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
-	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
-	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
-	{"USBN1_DMA_TEST"              ,	   0x17F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
+	{"USBN0_CTL_STATUS"            ,	   0x16f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN1_CTL_STATUS"            ,	   0x17f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN1_DMA0_INB_CHN0"         ,	   0x17f0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN1_DMA0_INB_CHN1"         ,	   0x17f0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN1_DMA0_INB_CHN2"         ,	   0x17f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
+	{"USBN1_DMA0_INB_CHN3"         ,	   0x17f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
+	{"USBN1_DMA0_INB_CHN4"         ,	   0x17f0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
+	{"USBN1_DMA0_INB_CHN5"         ,	   0x17f0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
+	{"USBN1_DMA0_INB_CHN6"         ,	   0x17f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
+	{"USBN1_DMA0_INB_CHN7"         ,	   0x17f0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
+	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17f0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
+	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17f0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
+	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
+	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
+	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17f0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
+	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17f0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
+	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
+	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
+	{"USBN0_DMA_TEST"              ,	   0x16f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
+	{"USBN1_DMA_TEST"              ,	   0x17f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
 	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
 	{"USBN1_INT_ENB"               ,	   0x1180078000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
 	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
@@ -70251,7 +70228,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"Q3FUS"                       ,	0,	34,	300,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_256K"                   ,	34,	1,	300,	"RO",	0,	0,	0ull,	0ull},
 	{"CRIP_128K"                   ,	35,	1,	300,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_36_36"              ,	36,	1,	300,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	300,	"RO",	0,	0,	0ull,	0ull},
 	{"EMA_CTL"                     ,	37,	3,	300,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_40_63"              ,	40,	24,	300,	"RAZ",	0,	0,	0ull,	0ull},
 	{"ECC_ENA"                     ,	0,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
@@ -70297,7 +70274,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"INORDER_MWF"                 ,	13,	1,	305,	"RAZ",	0,	0,	0ull,	0ull},
 	{"R2R_SLOT"                    ,	14,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
 	{"RDIMM_ENA"                   ,	15,	1,	305,	"R/W",	0,	1,	0ull,	0},
-	{"RESERVED_16_17"              ,	16,	2,	305,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	305,	"R/W",	0,	0,	0ull,	0ull},
 	{"MAX_WRITE_BATCH"             ,	18,	4,	305,	"R/W",	0,	0,	8ull,	8ull},
 	{"XOR_BANK"                    ,	22,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
 	{"SLOW_SCF"                    ,	23,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
@@ -71037,7 +71014,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"BAR2_ESX"                    ,	2,	2,	441,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	441,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	441,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	441,	"R/W",	0,	0,	1ull,	1ull},
@@ -71054,7 +71031,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"BAR2_ESX"                    ,	2,	2,	442,	"R/W",	0,	1,	0ull,	0},
 	{"BAR2_ENB"                    ,	4,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
 	{"PTLP_RO"                     ,	5,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
-	{"RESERVED_6_6"                ,	6,	1,	442,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
 	{"CTLP_RO"                     ,	7,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
 	{"INTA_MAP"                    ,	8,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTB_MAP"                    ,	10,	2,	442,	"R/W",	0,	0,	1ull,	1ull},
@@ -71398,7 +71375,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"DMA1DBO"                     ,	5,	1,	466,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA2DBO"                     ,	6,	1,	466,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA3DBO"                     ,	7,	1,	466,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_8_8"                ,	8,	1,	466,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_8_8"                ,	8,	1,	466,	"RO",	1,	1,	0,	0},
 	{"DMA0FI"                      ,	9,	1,	466,	"RO",	0,	0,	0ull,	0ull},
 	{"DMA1FI"                      ,	10,	1,	466,	"RO",	0,	0,	0ull,	0ull},
 	{"DCNT0"                       ,	11,	1,	466,	"RO",	0,	0,	0ull,	0ull},
@@ -73117,9 +73094,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"BACK"                        ,	59,	4,	781,	"RO",	1,	0,	0,	0ull},
 	{"I"                           ,	63,	1,	781,	"RO",	1,	0,	0,	0ull},
 	{"PTRS2"                       ,	0,	17,	782,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	782,	"RAZ",	1,	1,	0,	0},
 	{"PTRS1"                       ,	32,	17,	782,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	782,	"RAZ",	1,	1,	0,	0},
 	{"MOD"                         ,	0,	3,	783,	"RO",	1,	0,	0,	0ull},
 	{"CNT"                         ,	3,	13,	783,	"RO",	1,	0,	0,	0ull},
 	{"CHK"                         ,	16,	1,	783,	"RO",	1,	0,	0,	0ull},
@@ -73127,7 +73104,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"SOP"                         ,	18,	1,	783,	"RO",	1,	0,	0,	0ull},
 	{"UID"                         ,	19,	3,	783,	"RO",	1,	0,	0,	0ull},
 	{"MAJ"                         ,	22,	1,	783,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	783,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	16,	784,	"RO",	1,	0,	0,	0ull},
 	{"SEGS"                        ,	16,	6,	784,	"RO",	1,	0,	0,	0ull},
 	{"CMD"                         ,	22,	14,	784,	"RO",	1,	0,	0,	0ull},
@@ -73160,7 +73137,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"CURR_SIZ"                    ,	0,	8,	790,	"RO",	1,	0,	0,	0ull},
 	{"CURR_PTR"                    ,	8,	40,	790,	"RO",	1,	0,	0,	0ull},
 	{"NXT_INFLT"                   ,	48,	6,	790,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_54_63"              ,	54,	10,	790,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	790,	"RAZ",	1,	1,	0,	0},
 	{"QID_BASE"                    ,	0,	8,	791,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFF"                     ,	8,	4,	791,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFMAX"                  ,	12,	4,	791,	"RO",	1,	0,	0,	0ull},
@@ -73173,7 +73150,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"PREEMPTER"                   ,	28,	1,	791,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFTHS"                  ,	29,	4,	791,	"RO",	1,	0,	0,	0ull},
 	{"QID_OFFRES"                  ,	33,	4,	791,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_37_63"              ,	37,	27,	791,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	791,	"RO",	1,	0,	0,	0ull},
 	{"QCB_RIDX"                    ,	0,	6,	792,	"RO",	1,	0,	0,	0ull},
 	{"QCB_WIDX"                    ,	6,	6,	792,	"RO",	1,	0,	0,	0ull},
 	{"BUF_PTR"                     ,	12,	33,	792,	"RO",	1,	0,	0,	0ull},
@@ -73185,35 +73162,35 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"S_TAIL"                      ,	4,	1,	793,	"RO",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	5,	1,	793,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTEE"                   ,	6,	1,	793,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_7_7"                ,	7,	1,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	793,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	8,	20,	793,	"RO",	1,	0,	0,	0ull},
 	{"PREEMPTER"                   ,	28,	1,	793,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_29_63"              ,	29,	35,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	793,	"RAZ",	1,	1,	0,	0},
 	{"PTRS3"                       ,	0,	17,	794,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_17_31"              ,	17,	15,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	794,	"RAZ",	1,	1,	0,	0},
 	{"PTRS0"                       ,	32,	17,	794,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_49_63"              ,	49,	15,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	794,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	795,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	795,	"R/W",	1,	0,	0,	0ull},
 	{"BP_PORT"                     ,	10,	6,	795,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_16_52"              ,	16,	37,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	795,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	795,	"R/W",	1,	0,	0,	0ull},
 	{"STATIC_P"                    ,	61,	1,	795,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_62_63"              ,	62,	2,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	795,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	796,	"R/W",	1,	0,	0,	0ull},
 	{"EID"                         ,	6,	4,	796,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_10_52"              ,	10,	43,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	796,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	796,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	796,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	797,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	797,	"RAZ",	1,	1,	0,	0},
 	{"RATE_PKT"                    ,	8,	24,	797,	"R/W",	1,	0,	0,	0ull},
 	{"RATE_WORD"                   ,	32,	19,	797,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_51_63"              ,	51,	13,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	797,	"RAZ",	1,	1,	0,	0},
 	{"PID"                         ,	0,	6,	798,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_6_7"                ,	6,	2,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	798,	"RAZ",	1,	1,	0,	0},
 	{"RATE_LIM"                    ,	8,	24,	798,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	1,	0,	0},
 	{"QUEUE"                       ,	0,	7,	799,	"R/W",	1,	0,	0,	0ull},
 	{"PORT"                        ,	7,	6,	799,	"WR0",	1,	0,	0,	0ull},
 	{"INDEX"                       ,	13,	3,	799,	"WR0",	1,	0,	0,	0ull},
@@ -73225,9 +73202,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"S_TAIL"                      ,	63,	1,	799,	"R/W",	1,	0,	0,	0ull},
 	{"QID"                         ,	0,	7,	800,	"R/W",	1,	0,	0,	0ull},
 	{"PID"                         ,	7,	6,	800,	"WR0",	1,	0,	0,	0ull},
-	{"RESERVED_13_52"              ,	13,	40,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	800,	"RAZ",	1,	1,	0,	0},
 	{"QOS_MASK"                    ,	53,	8,	800,	"R/W",	1,	0,	0,	0ull},
-	{"RESERVED_61_63"              ,	61,	3,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	800,	"RAZ",	1,	1,	0,	0},
 	{"DAT_PTR"                     ,	0,	4,	801,	"RO",	1,	0,	0,	0ull},
 	{"DAT_DAT"                     ,	4,	2,	801,	"RO",	1,	0,	0,	0ull},
 	{"PRT_CTL"                     ,	6,	2,	801,	"RO",	1,	0,	0,	0ull},
@@ -73243,11 +73220,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"OUT_DAT"                     ,	32,	1,	801,	"RO",	1,	0,	0,	0ull},
 	{"IOB"                         ,	33,	1,	801,	"RO",	1,	0,	0,	0ull},
 	{"CSR"                         ,	34,	1,	801,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_35_63"              ,	35,	29,	801,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	801,	"RAZ",	1,	1,	0,	0},
 	{"SIZE"                        ,	0,	13,	802,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_13_19"              ,	13,	7,	802,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	802,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	20,	3,	802,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_23_63"              ,	23,	41,	802,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	802,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	64,	803,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	804,	"RO",	0,	0,	0ull,	0ull},
 	{"ASSERTS"                     ,	0,	64,	805,	"RO",	0,	0,	0ull,	0ull},
@@ -73262,33 +73239,33 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"ENGINE7"                     ,	28,	4,	807,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENGINE8"                     ,	32,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
 	{"ENGINE9"                     ,	36,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
-	{"RESERVED_40_63"              ,	40,	24,	807,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	807,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	10,	808,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_63"              ,	10,	54,	808,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	808,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	809,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	809,	"RAZ",	1,	1,	0,	0},
 	{"ENA_PKO"                     ,	0,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENA_DWB"                     ,	1,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
 	{"STORE_BE"                    ,	2,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	3,	1,	810,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	810,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	810,	"RAZ",	1,	1,	0,	0},
 	{"MODE0"                       ,	0,	3,	811,	"R/W",	0,	0,	2ull,	2ull},
 	{"MODE1"                       ,	3,	3,	811,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	811,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	811,	"RAZ",	1,	1,	0,	0},
 	{"PARITY"                      ,	0,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
 	{"DOORBELL"                    ,	1,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
 	{"CURRZERO"                    ,	2,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	812,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	812,	"RAZ",	1,	1,	0,	0},
 	{"MODE"                        ,	0,	2,	813,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	813,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	813,	"RAZ",	1,	1,	0,	0},
 	{"QID7"                        ,	0,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
 	{"IDX3"                        ,	1,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_2_63"               ,	2,	62,	814,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	814,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	815,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	815,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	815,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	815,	"RAZ",	1,	1,	0,	0},
 	{"ADR"                         ,	0,	1,	816,	"RO",	0,	0,	0ull,	0ull},
 	{"PEND"                        ,	1,	1,	816,	"RO",	0,	0,	0ull,	0ull},
 	{"NBR0"                        ,	2,	1,	816,	"RO",	0,	0,	0ull,	0ull},
@@ -73396,7 +73373,7 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"NCB_INB"                     ,	2,	2,	842,	"RO",	1,	0,	0,	0ull},
 	{"NCB_OUB"                     ,	4,	1,	842,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	5,	1,	842,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_6_63"               ,	6,	58,	842,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	842,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	33,	843,	"R/W",	0,	1,	0ull,	0},
 	{"SIZE"                        ,	33,	13,	843,	"R/W",	0,	1,	0ull,	0},
 	{"POOL"                        ,	46,	3,	843,	"R/W",	0,	1,	0ull,	0},
@@ -73411,11 +73388,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"OWORDPV"                     ,	6,	1,	845,	"RO",	1,	1,	0,	0},
 	{"OWORDQV"                     ,	7,	1,	845,	"RO",	1,	1,	0,	0},
 	{"IWIDX"                       ,	8,	6,	845,	"RO",	1,	1,	0,	0},
-	{"RESERVED_14_15"              ,	14,	2,	845,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	845,	"RO",	1,	1,	0,	0},
 	{"IRIDX"                       ,	16,	6,	845,	"RO",	1,	1,	0,	0},
-	{"RESERVED_22_31"              ,	22,	10,	845,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	845,	"RO",	1,	1,	0,	0},
 	{"LOOP"                        ,	32,	25,	845,	"RO",	1,	1,	0,	0},
-	{"RESERVED_57_63"              ,	57,	7,	845,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	845,	"RO",	1,	1,	0,	0},
 	{"CWORD"                       ,	0,	64,	846,	"RO",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	847,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	847,	"RO",	1,	1,	0,	0},
@@ -73426,16 +73403,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"WC"                          ,	10,	1,	848,	"RO",	1,	1,	0,	0},
 	{"P"                           ,	11,	1,	848,	"RO",	1,	1,	0,	0},
 	{"Q"                           ,	12,	1,	848,	"RO",	1,	1,	0,	0},
-	{"RESERVED_13_63"              ,	13,	51,	848,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	848,	"RAZ",	1,	1,	0,	0},
 	{"ASSERTS"                     ,	0,	15,	849,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	849,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	849,	"RAZ",	1,	1,	0,	0},
 	{"OWORDP"                      ,	0,	64,	850,	"RO",	1,	1,	0,	0},
 	{"OWORDQ"                      ,	0,	64,	851,	"RO",	1,	1,	0,	0},
 	{"RWORD"                       ,	0,	64,	852,	"RO",	1,	1,	0,	0},
 	{"N0CREDS"                     ,	0,	4,	853,	"RO",	0,	0,	8ull,	0ull},
 	{"N1CREDS"                     ,	4,	4,	853,	"RO",	0,	0,	8ull,	0ull},
 	{"POWCREDS"                    ,	8,	2,	853,	"RO",	0,	0,	2ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	853,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	853,	"RAZ",	1,	1,	0,	0},
 	{"FPACREDS"                    ,	12,	2,	853,	"RO",	0,	0,	1ull,	0ull},
 	{"WCCREDS"                     ,	14,	2,	853,	"RO",	0,	0,	0ull,	0ull},
 	{"NIWIDX0"                     ,	16,	4,	853,	"RO",	1,	1,	0,	0},
@@ -73449,12 +73426,12 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"NIRVAL7"                     ,	43,	5,	853,	"RO",	1,	1,	0,	0},
 	{"NIRQUE7"                     ,	48,	2,	853,	"RO",	1,	1,	0,	0},
 	{"NIROPC7"                     ,	50,	3,	853,	"RO",	1,	1,	0,	0},
-	{"RESERVED_53_63"              ,	53,	11,	853,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	853,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	854,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	854,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	56,	8,	854,	"RO",	1,	1,	0,	0},
 	{"CNT"                         ,	0,	15,	855,	"RO",	1,	1,	0,	0},
-	{"RESERVED_15_63"              ,	15,	49,	855,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	855,	"RAZ",	1,	1,	0,	0},
 	{"PTR"                         ,	0,	40,	856,	"RO",	1,	1,	0,	0},
 	{"SIZE"                        ,	40,	16,	856,	"RO",	1,	1,	0,	0},
 	{"FLAGS"                       ,	56,	8,	856,	"RO",	1,	1,	0,	0},
@@ -73464,16 +73441,16 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"Q"                           ,	17,	1,	857,	"RO",	1,	1,	0,	0},
 	{"INI"                         ,	18,	1,	857,	"RO",	1,	1,	0,	0},
 	{"EOD"                         ,	19,	1,	857,	"RO",	1,	1,	0,	0},
-	{"RESERVED_20_63"              ,	20,	44,	857,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	857,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	858,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	858,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	858,	"RAZ",	1,	1,	0,	0},
 	{"DOORBELL"                    ,	0,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_1_63"               ,	1,	63,	859,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	859,	"RAZ",	1,	1,	0,	0},
 	{"COEFFS"                      ,	0,	8,	860,	"R/W",	0,	0,	29ull,	29ull},
 	{"RESERVED_8_63"               ,	8,	56,	860,	"RAZ",	0,	0,	0ull,	0ull},
 	{"INDEX"                       ,	0,	16,	861,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	16,	16,	861,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	1,	1,	0,	0},
 	{"MEM"                         ,	0,	1,	862,	"RO",	0,	0,	0ull,	0ull},
 	{"RRC"                         ,	1,	1,	862,	"RO",	0,	0,	0ull,	0ull},
 	{"RESERVED_2_63"               ,	2,	62,	862,	"RAZ",	1,	1,	0,	0},
@@ -73511,11 +73488,11 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"PENDING"                     ,	17,	1,	868,	"RO",	0,	1,	0ull,	0},
 	{"RESERVED_18_63"              ,	18,	46,	868,	"RAZ",	1,	1,	0,	0},
 	{"INTERVAL"                    ,	0,	22,	869,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	869,	"RAZ",	1,	1,	0,	0},
 	{"COUNT"                       ,	24,	22,	869,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_46_46"              ,	46,	1,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	869,	"RAZ",	1,	1,	0,	0},
 	{"ENA"                         ,	47,	1,	869,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_48_63"              ,	48,	16,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	869,	"RAZ",	1,	1,	0,	0},
 	{"BSIZE"                       ,	0,	20,	870,	"RO",	1,	0,	0,	0ull},
 	{"BASE"                        ,	20,	31,	870,	"RO",	1,	0,	0,	0ull},
 	{"BUCKET"                      ,	51,	13,	870,	"RO",	1,	0,	0,	0ull},
@@ -73523,32 +73500,32 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"RESERVED_7_7"                ,	7,	1,	871,	"RAZ",	1,	0,	0,	0ull},
 	{"CSIZE"                       ,	8,	13,	871,	"RO",	1,	0,	0,	0ull},
 	{"CPOOL"                       ,	21,	3,	871,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_24_63"              ,	24,	40,	871,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	871,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	872,	"R/W",	0,	0,	0ull,	0ull},
 	{"NUM_BUCKETS"                 ,	4,	20,	872,	"R/W",	0,	0,	0ull,	0ull},
 	{"FIRST_BUCKET"                ,	24,	31,	872,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_55_63"              ,	55,	9,	872,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	872,	"RAZ",	1,	1,	0,	0},
 	{"RING"                        ,	0,	4,	873,	"R/W",	0,	0,	0ull,	0ull},
 	{"INTERVAL"                    ,	4,	22,	873,	"R/W",	0,	0,	0ull,	0ull},
 	{"WORDS_PER_CHUNK"             ,	26,	13,	873,	"R/W",	0,	0,	0ull,	0ull},
 	{"POOL"                        ,	39,	3,	873,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE"                      ,	42,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_43_63"              ,	43,	21,	873,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	873,	"RAZ",	1,	1,	0,	0},
 	{"CTL"                         ,	0,	1,	874,	"RO",	1,	0,	0,	0ull},
 	{"NCB"                         ,	1,	1,	874,	"RO",	1,	0,	0,	0ull},
 	{"STA"                         ,	2,	2,	874,	"RO",	1,	0,	0,	0ull},
-	{"RESERVED_4_63"               ,	4,	60,	874,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	874,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	875,	"R/W1C",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	875,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	875,	"RAZ",	1,	1,	0,	0},
 	{"ENABLE_TIMERS"               ,	0,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
 	{"ENABLE_DWB"                  ,	1,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
 	{"RESET"                       ,	2,	1,	876,	"RAZ",	0,	0,	0ull,	0ull},
-	{"RESERVED_3_63"               ,	3,	61,	876,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	876,	"RAZ",	1,	1,	0,	0},
 	{"MASK"                        ,	0,	16,	877,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	877,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	877,	"RAZ",	1,	1,	0,	0},
 	{"INDEX"                       ,	0,	8,	878,	"R/W",	0,	0,	0ull,	0ull},
 	{"INC"                         ,	8,	8,	878,	"R/W",	0,	0,	0ull,	0ull},
-	{"RESERVED_16_63"              ,	16,	48,	878,	"RAZ",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	878,	"RAZ",	1,	1,	0,	0},
 	{"TDF0"                        ,	0,	1,	879,	"RO",	0,	0,	0ull,	0ull},
 	{"TDF1"                        ,	1,	1,	879,	"RO",	0,	0,	0ull,	0ull},
 	{"TCF"                         ,	2,	1,	879,	"RO",	0,	0,	0ull,	0ull},
@@ -73569,9 +73546,9 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"RPTR"                        ,	8,	8,	881,	"RO",	0,	0,	0ull,	0ull},
 	{"CYCLES"                      ,	16,	48,	881,	"RO",	0,	0,	0ull,	0ull},
 	{"WPTR"                        ,	0,	10,	882,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_10_11"              ,	10,	2,	882,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	882,	"RAZ",	1,	1,	0,	0},
 	{"RPTR"                        ,	12,	10,	882,	"RO",	0,	0,	0ull,	0ull},
-	{"RESERVED_22_23"              ,	22,	2,	882,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	882,	"RAZ",	1,	1,	0,	0},
 	{"CYCLES"                      ,	24,	40,	882,	"RO",	0,	0,	0ull,	0ull},
 	{"ADR"                         ,	0,	36,	883,	"R/W",	0,	1,	0ull,	0},
 	{"RESERVED_36_63"              ,	36,	28,	883,	"RAZ",	0,	0,	0ull,	0ull},
@@ -74246,6 +74223,31226 @@ static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
 	{"TXRISETUNE"                  ,	63,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
 	{NULL,0,0,0,0,0,0,0,0}
 };
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xxp1[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	124,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	125,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	126,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	127,	23,	258},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	2,	281},
+	{"cvmx_ciu_block_int"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	130,	37,	283},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	131,	2,	320},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	132,	2,	322},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	133,	2,	324},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	134,	22,	326},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	148,	22,	348},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	162,	22,	370},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	176,	33,	392},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	190,	33,	425},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	204,	33,	458},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	218,	22,	491},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	22,	513},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	230,	22,	535},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	236,	33,	557},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	242,	33,	590},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	248,	33,	623},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	254,	22,	656},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	267,	22,	678},
+	{"cvmx_ciu_int33_sum0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	273,	22,	700},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	274,	33,	722},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	275,	2,	755},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	281,	2,	757},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	287,	2,	759},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	288,	2,	761},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	289,	2,	763},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	290,	1,	765},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	296,	3,	766},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	297,	8,	769},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	298,	8,	777},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	299,	8,	785},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	300,	6,	793},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	301,	8,	799},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	302,	2,	807},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	303,	2,	809},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	304,	2,	811},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	305,	2,	813},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	306,	3,	815},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	310,	7,	818},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	316,	12,	825},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	317,	12,	837},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	318,	4,	849},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	319,	7,	853},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	320,	2,	860},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	321,	1,	862},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	322,	1,	863},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	323,	1,	864},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	324,	1,	865},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	325,	4,	866},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	326,	3,	870},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	327,	6,	873},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	328,	5,	879},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	329,	3,	884},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	330,	1,	887},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	331,	1,	888},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	332,	5,	889},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	333,	1,	894},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	334,	5,	895},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	335,	1,	900},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	336,	5,	901},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	337,	1,	906},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	338,	5,	907},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	339,	18,	912},
+	{"cvmx_dfm_char_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	340,	5,	930},
+	{"cvmx_dfm_char_mask0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	341,	2,	935},
+	{"cvmx_dfm_char_mask2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	342,	2,	937},
+	{"cvmx_dfm_comp_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	343,	11,	939},
+	{"cvmx_dfm_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	344,	17,	950},
+	{"cvmx_dfm_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	345,	18,	967},
+	{"cvmx_dfm_dll_ctl2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	346,	6,	985},
+	{"cvmx_dfm_dll_ctl3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	347,	11,	991},
+	{"cvmx_dfm_fclk_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	348,	1,	1002},
+	{"cvmx_dfm_fnt_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	349,	5,	1003},
+	{"cvmx_dfm_fnt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	350,	5,	1008},
+	{"cvmx_dfm_fnt_iena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	351,	3,	1013},
+	{"cvmx_dfm_fnt_sclk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	352,	4,	1016},
+	{"cvmx_dfm_fnt_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	353,	6,	1020},
+	{"cvmx_dfm_ifb_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	354,	1,	1026},
+	{"cvmx_dfm_modereg_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	16,	1027},
+	{"cvmx_dfm_modereg_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	25,	1043},
+	{"cvmx_dfm_ops_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	357,	1,	1068},
+	{"cvmx_dfm_phy_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	358,	9,	1069},
+	{"cvmx_dfm_reset_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	5,	1078},
+	{"cvmx_dfm_rlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	4,	1083},
+	{"cvmx_dfm_rlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	361,	1,	1087},
+	{"cvmx_dfm_rlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	362,	5,	1088},
+	{"cvmx_dfm_rodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	8,	1093},
+	{"cvmx_dfm_slot_ctl0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	365,	5,	1101},
+	{"cvmx_dfm_slot_ctl1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	366,	5,	1106},
+	{"cvmx_dfm_timing_params0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	367,	11,	1111},
+	{"cvmx_dfm_timing_params1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	368,	12,	1122},
+	{"cvmx_dfm_wlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	369,	3,	1134},
+	{"cvmx_dfm_wlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	370,	3,	1137},
+	{"cvmx_dfm_wlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	371,	5,	1140},
+	{"cvmx_dfm_wodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	373,	8,	1145},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	374,	2,	1153},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	375,	3,	1155},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	376,	3,	1158},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	384,	2,	1161},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	392,	7,	1163},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	400,	2,	1170},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	408,	1,	1172},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	416,	1,	1173},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	424,	17,	1174},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	425,	2,	1191},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	431,	3,	1193},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	437,	3,	1196},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	438,	15,	1199},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	439,	15,	1214},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	440,	4,	1229},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	441,	2,	1233},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	442,	2,	1235},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	443,	2,	1237},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	444,	2,	1239},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	445,	2,	1241},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	446,	2,	1243},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	447,	14,	1245},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	449,	2,	1259},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	451,	6,	1261},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	453,	6,	1267},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	454,	7,	1273},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	455,	3,	1280},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	462,	2,	1283},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	469,	3,	1285},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	2,	1288},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	29,	1290},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	29,	1319},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	473,	2,	1348},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	481,	2,	1350},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	489,	3,	1352},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	490,	3,	1355},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	7,	1358},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	492,	2,	1365},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	493,	2,	1367},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	494,	5,	1369},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	495,	7,	1374},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	496,	2,	1381},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	497,	8,	1383},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	498,	10,	1391},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	502,	1,	1401},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	506,	1,	1402},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	510,	1,	1403},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	514,	1,	1404},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	518,	1,	1405},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	522,	1,	1406},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	526,	2,	1407},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	530,	4,	1409},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	534,	2,	1413},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	538,	9,	1415},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	542,	13,	1424},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	546,	2,	1437},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	550,	27,	1439},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	554,	27,	1466},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	558,	2,	1493},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	562,	2,	1495},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	566,	2,	1497},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	570,	2,	1499},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	574,	2,	1501},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	578,	2,	1503},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	582,	2,	1505},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	586,	2,	1507},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	590,	2,	1509},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	594,	2,	1511},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	598,	2,	1513},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	602,	2,	1515},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	606,	4,	1517},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	610,	2,	1521},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	614,	2,	1523},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	618,	2,	1525},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	4,	1527},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	623,	4,	1531},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	624,	2,	1535},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	625,	5,	1537},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	626,	2,	1542},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	627,	2,	1544},
+	{"cvmx_gmx#_soft_bist"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	631,	3,	1546},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	632,	3,	1549},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	633,	5,	1552},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	637,	2,	1557},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	641,	2,	1559},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	642,	2,	1561},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	643,	3,	1563},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	647,	2,	1566},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	651,	2,	1568},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	655,	2,	1570},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	659,	3,	1572},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	663,	2,	1575},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	667,	2,	1577},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	671,	2,	1579},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	675,	2,	1581},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	679,	2,	1583},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	683,	2,	1585},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	687,	2,	1587},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	691,	2,	1589},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	695,	2,	1591},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	699,	2,	1593},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	703,	2,	1595},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	707,	2,	1597},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	711,	2,	1599},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	715,	2,	1601},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	719,	2,	1603},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	723,	2,	1605},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	727,	2,	1607},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	728,	2,	1609},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	729,	2,	1611},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	730,	2,	1613},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	731,	2,	1615},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	732,	3,	1617},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	733,	9,	1620},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	734,	9,	1629},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	735,	2,	1638},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	736,	2,	1640},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	737,	6,	1642},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	738,	2,	1648},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	739,	2,	1650},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	740,	2,	1652},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	741,	9,	1654},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	742,	3,	1663},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	743,	10,	1666},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	759,	2,	1676},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	763,	3,	1678},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	765,	2,	1681},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	766,	2,	1683},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	767,	2,	1685},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	768,	2,	1687},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	769,	24,	1689},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	8,	1713},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	771,	3,	1721},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	3,	1724},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	773,	3,	1727},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	774,	5,	1730},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	775,	5,	1735},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	776,	1,	1740},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	777,	1,	1741},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	778,	7,	1742},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	779,	7,	1749},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	780,	3,	1756},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	781,	3,	1759},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	782,	3,	1762},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	783,	5,	1765},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	784,	5,	1770},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	785,	1,	1775},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	786,	1,	1776},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	787,	3,	1777},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	3,	1780},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	789,	3,	1783},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	790,	3,	1786},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	791,	4,	1789},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	792,	2,	1793},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	793,	2,	1795},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	794,	2,	1797},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	795,	19,	1799},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	796,	2,	1818},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	797,	1,	1820},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	798,	16,	1821},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	799,	13,	1837},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	800,	13,	1850},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	801,	2,	1863},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	802,	2,	1865},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	803,	2,	1867},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	804,	3,	1869},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	812,	3,	1872},
+	{"cvmx_ipd_port#_bp_page_cnt3" ,	CVMX_CSR_DB_TYPE_NCB,	64,	816,	3,	1875},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	820,	2,	1878},
+	{"cvmx_ipd_port_bp_counters3_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	824,	2,	1880},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	828,	2,	1882},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	836,	2,	1884},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	964,	1,	1886},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	967,	1,	1887},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	970,	6,	1888},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	971,	5,	1894},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	972,	6,	1899},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	973,	7,	1905},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	974,	2,	1912},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	982,	2,	1914},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	983,	3,	1916},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	984,	2,	1919},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	985,	5,	1921},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	993,	3,	1926},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	994,	4,	1929},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	995,	3,	1933},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	996,	2,	1936},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	997,	2,	1938},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	4,	1940},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	999,	3,	1944},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1000,	5,	1947},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1001,	5,	1952},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1002,	12,	1957},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	5,	1969},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	4,	1974},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1005,	3,	1978},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	1,	1981},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2798,	11,	1982},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2799,	4,	1993},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4335,	9,	1997},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4336,	9,	2006},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4337,	6,	2015},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4338,	5,	2021},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4339,	7,	2026},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4340,	9,	2033},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4341,	1,	2042},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4342,	1,	2043},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4343,	4,	2044},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4344,	2,	2048},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4350,	5,	2050},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4351,	1,	2055},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4352,	1,	2056},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4353,	8,	2057},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4354,	8,	2065},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4355,	8,	2073},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4356,	1,	2081},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4357,	1,	2082},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4358,	1,	2083},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4359,	1,	2084},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4360,	5,	2085},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4361,	9,	2090},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	4362,	1,	2099},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4363,	2,	2100},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	4364,	2,	2102},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4365,	4,	2104},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4366,	2,	2108},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4372,	6,	2110},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4373,	3,	2116},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5397,	2,	2119},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5398,	2,	2121},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5404,	1,	2123},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5405,	4,	2124},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5406,	1,	2128},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5407,	5,	2129},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5408,	1,	2134},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5409,	2,	2135},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5410,	1,	2137},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5411,	2,	2138},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5412,	12,	2140},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5413,	11,	2152},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5414,	17,	2163},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5415,	20,	2180},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5416,	1,	2200},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5417,	11,	2201},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5418,	16,	2212},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5420,	5,	2228},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5421,	6,	2233},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5422,	11,	2239},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5423,	4,	2250},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5424,	5,	2254},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5425,	6,	2259},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5426,	1,	2265},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	5427,	4,	2266},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5428,	4,	2270},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5429,	16,	2274},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5430,	25,	2290},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	5431,	10,	2315},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5432,	1,	2325},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5433,	9,	2326},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5434,	5,	2335},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5435,	4,	2340},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5436,	1,	2344},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5437,	11,	2345},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5441,	8,	2356},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5442,	5,	2364},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5443,	5,	2369},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5444,	5,	2374},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5445,	11,	2379},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5446,	12,	2390},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5447,	3,	2402},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5448,	2,	2405},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5449,	3,	2407},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5450,	3,	2410},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5451,	11,	2413},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5455,	8,	2424},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5456,	2,	2432},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5457,	3,	2434},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5458,	10,	2437},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5460,	3,	2447},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5462,	3,	2450},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5464,	15,	2453},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5466,	3,	2468},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5467,	3,	2471},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5468,	3,	2474},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5469,	5,	2477},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5471,	1,	2482},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5472,	9,	2483},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5473,	13,	2492},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5481,	13,	2505},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5489,	6,	2518},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5490,	1,	2524},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5492,	2,	2525},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5493,	2,	2527},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5494,	12,	2529},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5495,	18,	2541},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5496,	4,	2559},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5497,	1,	2563},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5498,	7,	2564},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5499,	3,	2571},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5500,	8,	2574},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5501,	7,	2582},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5502,	6,	2589},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5503,	5,	2595},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5504,	4,	2600},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5505,	2,	2604},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5506,	4,	2606},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5507,	2,	2610},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5508,	2,	2612},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5509,	3,	2614},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5510,	10,	2617},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5511,	2,	2627},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5512,	2,	2629},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	5513,	10,	2631},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5514,	2,	2641},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5515,	1,	2643},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5516,	2,	2644},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5517,	1,	2646},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	5518,	1,	2647},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5519,	9,	2648},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5520,	4,	2657},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5521,	9,	2661},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5523,	3,	2670},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5524,	6,	2673},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5525,	6,	2679},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5526,	13,	2685},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5528,	12,	2698},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5530,	3,	2710},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5532,	3,	2713},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5534,	2,	2716},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5536,	2,	2718},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5538,	2,	2720},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5540,	7,	2722},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5542,	2,	2729},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5544,	7,	2731},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5546,	4,	2738},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5548,	8,	2742},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5550,	9,	2750},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5552,	7,	2759},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5554,	9,	2766},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5556,	2,	2775},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5558,	2,	2777},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5560,	4,	2779},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5562,	2,	2783},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5564,	2,	2785},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5566,	2,	2787},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5568,	4,	2789},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5570,	2,	2793},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5572,	2,	2795},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5574,	2,	2797},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5576,	2,	2799},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5578,	2,	2801},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5580,	2,	2803},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5582,	6,	2805},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5584,	7,	2811},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5586,	9,	2818},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5588,	9,	2827},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5590,	2,	2836},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5592,	3,	2838},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5594,	4,	2841},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5596,	4,	2845},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5598,	9,	2849},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5600,	2,	2858},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5602,	2,	2860},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5604,	4,	2862},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5606,	4,	2866},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5608,	4,	2870},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5610,	6,	2874},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5612,	1,	2880},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5614,	4,	2881},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5615,	1,	2885},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5616,	2,	2886},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5617,	3,	2888},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5618,	8,	2891},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5619,	8,	2899},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5620,	12,	2907},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5621,	8,	2919},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5622,	2,	2927},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5624,	24,	2929},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5626,	4,	2953},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5628,	5,	2957},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5630,	5,	2962},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5632,	2,	2967},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5634,	1,	2969},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5636,	1,	2970},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5638,	5,	2971},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5640,	2,	2976},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5642,	1,	2978},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5644,	1,	2979},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5646,	4,	2980},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5648,	2,	2984},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5650,	2,	2986},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5652,	1,	2988},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5654,	1,	2989},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5656,	2,	2990},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5658,	3,	2992},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5660,	2,	2995},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5662,	2,	2997},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5664,	4,	2999},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5666,	10,	3003},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5668,	12,	3013},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5670,	7,	3025},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5672,	2,	3032},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5674,	1,	3034},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5676,	2,	3035},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5678,	7,	3037},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5680,	11,	3044},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5682,	19,	3055},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5684,	11,	3074},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5686,	17,	3085},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5688,	12,	3102},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5690,	22,	3114},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5692,	3,	3136},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5694,	3,	3139},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5696,	1,	3142},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5698,	11,	3143},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5700,	1,	3154},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5702,	1,	3155},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5704,	3,	3156},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5706,	14,	3159},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5708,	14,	3173},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5710,	14,	3187},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5712,	9,	3201},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5714,	9,	3210},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5716,	6,	3219},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5718,	1,	3225},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5720,	1,	3226},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5722,	1,	3227},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5724,	1,	3228},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5726,	2,	3229},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5728,	1,	3231},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5730,	6,	3232},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5732,	6,	3238},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5734,	13,	3244},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5736,	5,	3257},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5738,	8,	3262},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5740,	19,	3270},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5742,	3,	3289},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5744,	1,	3292},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5746,	1,	3293},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5748,	3,	3294},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5750,	3,	3297},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5752,	3,	3300},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5754,	4,	3303},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5756,	4,	3307},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5758,	4,	3311},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5760,	7,	3315},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5762,	5,	3322},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5764,	5,	3327},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5766,	4,	3332},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5768,	4,	3336},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5770,	4,	3340},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5772,	7,	3344},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5774,	1,	3351},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5776,	1,	3352},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5778,	2,	3353},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5780,	24,	3355},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5782,	4,	3379},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5784,	5,	3383},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5786,	1,	3388},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5788,	1,	3389},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5790,	4,	3390},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5792,	17,	3394},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5794,	4,	3411},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5796,	6,	3415},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5798,	1,	3421},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5800,	1,	3422},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5802,	2,	3423},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5804,	2,	3425},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5806,	1,	3427},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5808,	15,	3428},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5810,	10,	3443},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5812,	12,	3453},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5814,	7,	3465},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5816,	2,	3472},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5818,	1,	3474},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5820,	2,	3475},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5822,	7,	3477},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5824,	11,	3484},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5826,	19,	3495},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5828,	11,	3514},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5830,	20,	3525},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5832,	12,	3545},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5834,	22,	3557},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5836,	8,	3579},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5838,	4,	3587},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5840,	3,	3591},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5842,	3,	3594},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5844,	1,	3597},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5846,	11,	3598},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5848,	1,	3609},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5850,	1,	3610},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5852,	3,	3611},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5854,	14,	3614},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5856,	14,	3628},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5858,	14,	3642},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5860,	9,	3656},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5862,	9,	3665},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5864,	6,	3674},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5866,	1,	3680},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5868,	1,	3681},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5870,	1,	3682},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5872,	1,	3683},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5874,	4,	3684},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5876,	9,	3688},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5878,	2,	3697},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5880,	2,	3699},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5882,	1,	3701},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5884,	6,	3702},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5886,	6,	3708},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5888,	13,	3714},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5890,	5,	3727},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5892,	8,	3732},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5894,	19,	3740},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5896,	3,	3759},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5898,	1,	3762},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5900,	1,	3763},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5902,	3,	3764},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5904,	3,	3767},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5906,	3,	3770},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5908,	4,	3773},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5910,	4,	3777},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5912,	4,	3781},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5914,	7,	3785},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5916,	5,	3792},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5918,	5,	3797},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5920,	4,	3802},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5922,	4,	3806},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5924,	4,	3810},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5926,	7,	3814},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5928,	1,	3821},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5930,	1,	3822},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5932,	9,	3823},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5936,	6,	3832},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5940,	9,	3838},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5944,	6,	3847},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5948,	14,	3853},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5952,	14,	3867},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5956,	2,	3881},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5960,	4,	3883},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5964,	8,	3887},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5968,	13,	3895},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5972,	17,	3908},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5976,	7,	3925},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5980,	3,	3932},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5984,	8,	3935},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5988,	7,	3943},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5992,	4,	3950},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5996,	5,	3954},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6000,	8,	3959},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6001,	2,	3967},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6002,	5,	3969},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6003,	10,	3974},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6004,	2,	3984},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6005,	8,	3986},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6006,	8,	3994},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6007,	6,	4002},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6008,	5,	4008},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6009,	5,	4013},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6010,	3,	4018},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6011,	6,	4021},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6012,	9,	4027},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6013,	5,	4036},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6014,	10,	4041},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6015,	5,	4051},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6047,	5,	4056},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6049,	9,	4061},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6051,	11,	4070},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6053,	2,	4081},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6055,	2,	4083},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6057,	2,	4085},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6059,	18,	4087},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6061,	32,	4105},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6063,	32,	4137},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6065,	5,	4169},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6067,	15,	4174},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6069,	15,	4189},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6071,	15,	4204},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6073,	2,	4219},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6075,	2,	4221},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6077,	2,	4223},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6079,	2,	4225},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6087,	2,	4227},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6095,	8,	4229},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6097,	5,	4237},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6098,	2,	4242},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6099,	2,	4244},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6100,	4,	4246},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6104,	16,	4250},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6105,	16,	4266},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6106,	3,	4282},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6107,	8,	4285},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6108,	23,	4293},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6109,	6,	4316},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6110,	14,	4322},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6111,	14,	4336},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6112,	2,	4350},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6113,	28,	4352},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6129,	25,	4380},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6145,	2,	4405},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6209,	4,	4407},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6217,	9,	4411},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6225,	2,	4420},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6226,	2,	4422},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6227,	2,	4424},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6239,	2,	4426},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6251,	2,	4428},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6263,	2,	4430},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6275,	2,	4432},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6287,	2,	4434},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6299,	2,	4436},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6311,	2,	4438},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6323,	2,	4440},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6335,	2,	4442},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6347,	2,	4444},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6348,	2,	4446},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6364,	2,	4448},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6380,	2,	4450},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6396,	2,	4452},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6460,	2,	4454},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6461,	3,	4456},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6462,	3,	4459},
+	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6463,	2,	4462},
+	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6467,	2,	4464},
+	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6471,	2,	4466},
+	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6475,	2,	4468},
+	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6479,	2,	4470},
+	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6483,	2,	4472},
+	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6487,	2,	4474},
+	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6491,	2,	4476},
+	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6495,	2,	4478},
+	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6499,	2,	4480},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6503,	2,	4482},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6504,	2,	4484},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6505,	4,	4486},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6506,	5,	4490},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6507,	4,	4495},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6508,	8,	4499},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6509,	4,	4507},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6510,	5,	4511},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6511,	1,	4516},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6512,	5,	4517},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6513,	1,	4522},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6514,	13,	4523},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6515,	6,	4536},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6516,	13,	4542},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6517,	6,	4555},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6518,	9,	4561},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6519,	4,	4570},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6520,	7,	4574},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6521,	5,	4581},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	5,	4586},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	4,	4591},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	9,	4595},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6525,	5,	4604},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	16,	4609},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	4,	4625},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6528,	1,	4629},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6529,	1,	4630},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	1,	4631},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	1,	4632},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6532,	13,	4633},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6533,	2,	4646},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	4,	4648},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	5,	4652},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	3,	4657},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	4,	4660},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	2,	4664},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	3,	4666},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	3,	4669},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	2,	4672},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6542,	10,	4674},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6543,	2,	4684},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6544,	13,	4686},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6545,	3,	4699},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6546,	2,	4702},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6554,	2,	4704},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6555,	2,	4706},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6556,	2,	4708},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6557,	2,	4710},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6565,	2,	4712},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6566,	2,	4714},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6567,	2,	4716},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6568,	10,	4718},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6574,	5,	4728},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6582,	10,	4733},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6590,	2,	4743},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6591,	2,	4745},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6592,	2,	4747},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6600,	3,	4749},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6601,	6,	4752},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6617,	5,	4758},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6618,	7,	4763},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6634,	2,	4770},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6650,	1,	4772},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6651,	1,	4773},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6652,	1,	4774},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6653,	5,	4775},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6654,	5,	4780},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6655,	4,	4785},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6656,	10,	4789},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6657,	1,	4799},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6658,	3,	4800},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6659,	7,	4803},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6660,	2,	4810},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6661,	1,	4812},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6662,	1,	4813},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6663,	1,	4814},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6664,	18,	4815},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6665,	3,	4833},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6666,	2,	4836},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6667,	3,	4838},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6668,	7,	4841},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6669,	2,	4848},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6670,	2,	4850},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6671,	2,	4852},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6672,	3,	4854},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6673,	3,	4857},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6674,	9,	4860},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6675,	1,	4869},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6676,	1,	4870},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6677,	25,	4871},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6678,	16,	4896},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6680,	4,	4912},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6681,	5,	4916},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6682,	3,	4921},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6683,	3,	4924},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6684,	2,	4927},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6686,	2,	4929},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6688,	2,	4931},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6690,	35,	4933},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6691,	37,	4968},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6693,	37,	5005},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6694,	1,	5042},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6695,	1,	5043},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6696,	7,	5044},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6697,	3,	5051},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6698,	9,	5054},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6714,	1,	5063},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6715,	1,	5064},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6716,	1,	5065},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6717,	1,	5066},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6718,	1,	5067},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6719,	1,	5068},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6720,	1,	5069},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6721,	1,	5070},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6722,	3,	5071},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6723,	1,	5074},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6724,	1,	5075},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6725,	1,	5076},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6726,	1,	5077},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6727,	1,	5078},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6728,	1,	5079},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6729,	1,	5080},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6730,	1,	5081},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	3,	5082},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	2,	5085},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6733,	3,	5087},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6734,	3,	5090},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6735,	3,	5093},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6736,	3,	5096},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6768,	2,	5099},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6800,	2,	5101},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6832,	2,	5103},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6864,	5,	5105},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6896,	21,	5110},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6928,	3,	5131},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6960,	2,	5134},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6992,	2,	5136},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7024,	2,	5138},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7056,	2,	5140},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7057,	2,	5142},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7058,	3,	5144},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7059,	1,	5147},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7060,	2,	5148},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7061,	2,	5150},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7062,	2,	5152},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7063,	2,	5154},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7064,	2,	5156},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7096,	2,	5158},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7097,	1,	5160},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7098,	10,	5161},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7099,	2,	5171},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7100,	1,	5173},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7101,	2,	5174},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7102,	3,	5176},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7103,	2,	5179},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7104,	2,	5181},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7105,	2,	5183},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7106,	2,	5185},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7107,	1,	5187},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7108,	2,	5188},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7109,	1,	5190},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7110,	2,	5191},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7111,	2,	5193},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7112,	2,	5195},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7113,	2,	5197},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7114,	4,	5199},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7116,	1,	5203},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7117,	1,	5204},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7118,	4,	5205},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7119,	8,	5209},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7120,	5,	5217},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7121,	4,	5222},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7122,	1,	5226},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7123,	4,	5227},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7124,	1,	5231},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7125,	2,	5232},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7126,	2,	5234},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7127,	10,	5236},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7129,	6,	5246},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7131,	2,	5252},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7133,	4,	5254},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7135,	4,	5258},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7137,	4,	5262},
+	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7138,	4,	5266},
+	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7140,	3,	5270},
+	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7142,	3,	5273},
+	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7144,	5,	5276},
+	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7146,	18,	5281},
+	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7148,	14,	5299},
+	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7150,	14,	5313},
+	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7154,	24,	5327},
+	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7218,	24,	5351},
+	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7266,	13,	5375},
+	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7268,	23,	5388},
+	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7270,	9,	5411},
+	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7272,	1,	5420},
+	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7274,	11,	5421},
+	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7276,	5,	5432},
+	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7278,	23,	5437},
+	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7280,	9,	5460},
+	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7282,	6,	5469},
+	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7284,	3,	5475},
+	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7286,	2,	5478},
+	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7288,	8,	5480},
+	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7290,	10,	5488},
+	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7294,	16,	5498},
+	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7298,	16,	5514},
+	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7302,	4,	5530},
+	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7306,	17,	5534},
+	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7310,	9,	5551},
+	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7312,	3,	5560},
+	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7314,	9,	5563},
+	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7316,	11,	5572},
+	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7348,	2,	5583},
+	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7350,	3,	5585},
+	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7352,	6,	5588},
+	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7354,	6,	5594},
+	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7356,	10,	5600},
+	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7358,	11,	5610},
+	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7360,	12,	5621},
+	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7362,	5,	5633},
+	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7364,	2,	5638},
+	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7366,	2,	5640},
+	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7368,	7,	5642},
+	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7400,	2,	5649},
+	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7402,	1,	5651},
+	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7404,	6,	5652},
+	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7406,	2,	5658},
+	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7408,	2,	5660},
+	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7410,	26,	5662},
+	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7412,	4,	5688},
+	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7414,	14,	5692},
+	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7416,	5,	5706},
+	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7418,	14,	5711},
+	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7420,	3,	5725},
+	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7422,	2,	5728},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7424,	1,	5730},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7426,	3,	5731},
+	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7428,	9,	5734},
+	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7430,	4,	5743},
+	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7432,	4,	5747},
+	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7434,	12,	5751},
+	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7436,	12,	5763},
+	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7438,	1,	5775},
+	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7440,	1,	5776},
+	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7442,	1,	5777},
+	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7444,	1,	5778},
+	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7446,	2,	5779},
+	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7448,	7,	5781},
+	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7450,	1,	5788},
+	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7452,	9,	5789},
+	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7454,	5,	5798},
+	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7456,	2,	5803},
+	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7458,	2,	5805},
+	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7460,	1,	5807},
+	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7462,	5,	5808},
+	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7464,	2,	5813},
+	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7466,	1,	5815},
+	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7468,	5,	5816},
+	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7470,	15,	5821},
+	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7478,	2,	5836},
+	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7480,	2,	5838},
+	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7482,	2,	5840},
+	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7484,	4,	5842},
+	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7486,	2,	5846},
+	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7488,	5,	5848},
+	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7490,	7,	5853},
+	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7492,	11,	5860},
+	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7494,	2,	5871},
+	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7496,	18,	5873},
+	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7498,	16,	5891},
+	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7500,	20,	5907},
+	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7502,	4,	5927},
+	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7504,	2,	5931},
+	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7506,	2,	5933},
+	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7508,	2,	5935},
+	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7510,	3,	5937},
+	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7512,	3,	5940},
+	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7514,	3,	5943},
+	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7516,	2,	5946},
+	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7518,	26,	5948},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7520,	6,	5974},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7521,	3,	5980},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7522,	5,	5983},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7523,	4,	5988},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7524,	6,	5992},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7525,	4,	5998},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7526,	2,	6002},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7527,	4,	6004},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7528,	2,	6008},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7529,	3,	6010},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7530,	2,	6013},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7531,	13,	6015},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7532,	3,	6028},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7533,	5,	6031},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7534,	2,	6036},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7535,	2,	6038},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7536,	57,	6040},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7537,	20,	6097},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7538,	7,	6117},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7539,	5,	6124},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7540,	1,	6129},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7541,	2,	6130},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7542,	2,	6132},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7543,	57,	6134},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7544,	20,	6191},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7545,	7,	6211},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7546,	2,	6218},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7547,	2,	6220},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7548,	57,	6222},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7549,	20,	6279},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7550,	7,	6299},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7551,	2,	6306},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7552,	2,	6308},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7553,	1,	6310},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7554,	2,	6311},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7555,	3,	6313},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7556,	7,	6316},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7557,	10,	6323},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7558,	3,	6333},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7559,	5,	6336},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7560,	7,	6341},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7561,	2,	6348},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7562,	1,	6350},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7563,	2,	6351},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7564,	19,	6353},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7566,	13,	6372},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7567,	7,	6385},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7568,	12,	6392},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7569,	2,	6404},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7570,	2,	6406},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7571,	7,	6408},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7572,	10,	6415},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7573,	2,	6425},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7574,	2,	6427},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7575,	2,	6429},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7576,	4,	6431},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7577,	2,	6435},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7578,	3,	6437},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7579,	2,	6440},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7580,	10,	6442},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7581,	10,	6452},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7582,	10,	6462},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7583,	2,	6472},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7584,	2,	6474},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7585,	2,	6476},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7586,	2,	6478},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7587,	8,	6480},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7588,	2,	6488},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7589,	15,	6490},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7591,	8,	6505},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7592,	2,	6513},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7593,	1,	6515},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7594,	7,	6516},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7595,	21,	6523},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7596,	12,	6544},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7597,	2,	6556},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7598,	3,	6558},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7599,	2,	6561},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7600,	9,	6563},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7601,	9,	6572},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7602,	11,	6581},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7603,	3,	6592},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7604,	2,	6595},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7605,	11,	6597},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7606,	20,	6608},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7608,	3,	6628},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7609,	5,	6631},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7610,	3,	6636},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7611,	6,	6639},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7612,	2,	6645},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7613,	2,	6647},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7614,	2,	6649},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7615,	2,	6651},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xxp1[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_RX_INBND"        ,	   0x11800e0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_CLK"             ,	   0x11800e0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"AGL_PRT1_CTL"                ,	   0x11800e0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_BLOCK_INT"               ,	   0x10700000007c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT33_EN0"               ,	   0x1070000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT33_EN0_W1C"           ,	   0x1070000002410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT33_EN0_W1S"           ,	   0x1070000006410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT33_EN1"               ,	   0x1070000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT33_EN1_W1C"           ,	   0x1070000002418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT33_EN1_W1S"           ,	   0x1070000006418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT33_SUM0"              ,	   0x1070000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	115},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	120},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"DFM_CHAR_CTL"                ,	   0x11800d4000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"DFM_CHAR_MASK0"              ,	   0x11800d4000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"DFM_CHAR_MASK2"              ,	   0x11800d4000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"DFM_COMP_CTL2"               ,	   0x11800d40001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"DFM_CONFIG"                  ,	   0x11800d4000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"DFM_CONTROL"                 ,	   0x11800d4000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"DFM_DLL_CTL2"                ,	   0x11800d40001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"DFM_DLL_CTL3"                ,	   0x11800d4000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"DFM_FCLK_CNT"                ,	   0x11800d40001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"DFM_FNT_BIST"                ,	   0x11800d40007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"DFM_FNT_CTL"                 ,	   0x11800d4000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"DFM_FNT_IENA"                ,	   0x11800d4000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"DFM_FNT_SCLK"                ,	   0x11800d4000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"DFM_FNT_STAT"                ,	   0x11800d4000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"DFM_IFB_CNT"                 ,	   0x11800d40001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"DFM_MODEREG_PARAMS0"         ,	   0x11800d40001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"DFM_MODEREG_PARAMS1"         ,	   0x11800d4000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"DFM_OPS_CNT"                 ,	   0x11800d40001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"DFM_PHY_CTL"                 ,	   0x11800d4000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"DFM_RESET_CTL"               ,	   0x11800d4000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"DFM_RLEVEL_CTL"              ,	   0x11800d40002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"DFM_RLEVEL_DBG"              ,	   0x11800d40002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"DFM_RLEVEL_RANK0"            ,	   0x11800d4000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"DFM_RLEVEL_RANK1"            ,	   0x11800d4000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"DFM_RODT_MASK"               ,	   0x11800d4000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"DFM_SLOT_CTL0"               ,	   0x11800d40001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"DFM_SLOT_CTL1"               ,	   0x11800d4000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"DFM_TIMING_PARAMS0"          ,	   0x11800d4000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"DFM_TIMING_PARAMS1"          ,	   0x11800d40001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"DFM_WLEVEL_CTL"              ,	   0x11800d4000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"DFM_WLEVEL_DBG"              ,	   0x11800d4000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"DFM_WLEVEL_RANK0"            ,	   0x11800d40002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"DFM_WLEVEL_RANK1"            ,	   0x11800d40002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"DFM_WODT_MASK"               ,	   0x11800d40001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_SOFT_BIST"              ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_PORT40_BP_PAGE_CNT3"     ,	   0x14f00000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PORT41_BP_PAGE_CNT3"     ,	   0x14f00000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PORT42_BP_PAGE_CNT3"     ,	   0x14f00000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PORT43_BP_PAGE_CNT3"     ,	   0x14f00000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PORT_BP_COUNTERS3_PAIR40",	   0x14f00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT_BP_COUNTERS3_PAIR41",	   0x14f00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT_BP_COUNTERS3_PAIR42",	   0x14f00000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT_BP_COUNTERS3_PAIR43",	   0x14f00000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1024"            ,	   0x1180080942000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1025"            ,	   0x1180080942008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1026"            ,	   0x1180080942010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1027"            ,	   0x1180080942018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1028"            ,	   0x1180080942020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1029"            ,	   0x1180080942028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1030"            ,	   0x1180080942030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1031"            ,	   0x1180080942038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1032"            ,	   0x1180080942040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1033"            ,	   0x1180080942048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1034"            ,	   0x1180080942050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1035"            ,	   0x1180080942058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1036"            ,	   0x1180080942060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1037"            ,	   0x1180080942068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1038"            ,	   0x1180080942070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1039"            ,	   0x1180080942078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1040"            ,	   0x1180080942080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1041"            ,	   0x1180080942088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1042"            ,	   0x1180080942090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1043"            ,	   0x1180080942098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1044"            ,	   0x11800809420a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1045"            ,	   0x11800809420a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1046"            ,	   0x11800809420b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1047"            ,	   0x11800809420b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1048"            ,	   0x11800809420c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1049"            ,	   0x11800809420c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1050"            ,	   0x11800809420d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1051"            ,	   0x11800809420d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1052"            ,	   0x11800809420e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1053"            ,	   0x11800809420e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1054"            ,	   0x11800809420f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1055"            ,	   0x11800809420f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1056"            ,	   0x1180080942100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1057"            ,	   0x1180080942108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1058"            ,	   0x1180080942110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1059"            ,	   0x1180080942118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1060"            ,	   0x1180080942120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1061"            ,	   0x1180080942128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1062"            ,	   0x1180080942130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1063"            ,	   0x1180080942138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1064"            ,	   0x1180080942140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1065"            ,	   0x1180080942148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1066"            ,	   0x1180080942150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1067"            ,	   0x1180080942158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1068"            ,	   0x1180080942160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1069"            ,	   0x1180080942168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1070"            ,	   0x1180080942170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1071"            ,	   0x1180080942178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1072"            ,	   0x1180080942180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1073"            ,	   0x1180080942188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1074"            ,	   0x1180080942190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1075"            ,	   0x1180080942198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1076"            ,	   0x11800809421a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1077"            ,	   0x11800809421a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1078"            ,	   0x11800809421b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1079"            ,	   0x11800809421b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1080"            ,	   0x11800809421c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1081"            ,	   0x11800809421c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1082"            ,	   0x11800809421d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1083"            ,	   0x11800809421d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1084"            ,	   0x11800809421e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1085"            ,	   0x11800809421e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1086"            ,	   0x11800809421f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1087"            ,	   0x11800809421f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1088"            ,	   0x1180080942200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1089"            ,	   0x1180080942208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1090"            ,	   0x1180080942210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1091"            ,	   0x1180080942218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1092"            ,	   0x1180080942220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1093"            ,	   0x1180080942228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1094"            ,	   0x1180080942230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1095"            ,	   0x1180080942238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1096"            ,	   0x1180080942240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1097"            ,	   0x1180080942248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1098"            ,	   0x1180080942250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1099"            ,	   0x1180080942258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1100"            ,	   0x1180080942260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1101"            ,	   0x1180080942268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1102"            ,	   0x1180080942270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1103"            ,	   0x1180080942278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1104"            ,	   0x1180080942280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1105"            ,	   0x1180080942288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1106"            ,	   0x1180080942290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1107"            ,	   0x1180080942298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1108"            ,	   0x11800809422a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1109"            ,	   0x11800809422a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1110"            ,	   0x11800809422b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1111"            ,	   0x11800809422b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1112"            ,	   0x11800809422c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1113"            ,	   0x11800809422c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1114"            ,	   0x11800809422d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1115"            ,	   0x11800809422d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1116"            ,	   0x11800809422e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1117"            ,	   0x11800809422e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1118"            ,	   0x11800809422f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1119"            ,	   0x11800809422f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1120"            ,	   0x1180080942300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1121"            ,	   0x1180080942308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1122"            ,	   0x1180080942310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1123"            ,	   0x1180080942318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1124"            ,	   0x1180080942320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1125"            ,	   0x1180080942328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1126"            ,	   0x1180080942330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1127"            ,	   0x1180080942338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1128"            ,	   0x1180080942340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1129"            ,	   0x1180080942348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1130"            ,	   0x1180080942350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1131"            ,	   0x1180080942358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1132"            ,	   0x1180080942360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1133"            ,	   0x1180080942368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1134"            ,	   0x1180080942370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1135"            ,	   0x1180080942378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1136"            ,	   0x1180080942380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1137"            ,	   0x1180080942388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1138"            ,	   0x1180080942390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1139"            ,	   0x1180080942398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1140"            ,	   0x11800809423a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1141"            ,	   0x11800809423a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1142"            ,	   0x11800809423b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1143"            ,	   0x11800809423b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1144"            ,	   0x11800809423c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1145"            ,	   0x11800809423c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1146"            ,	   0x11800809423d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1147"            ,	   0x11800809423d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1148"            ,	   0x11800809423e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1149"            ,	   0x11800809423e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1150"            ,	   0x11800809423f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1151"            ,	   0x11800809423f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1152"            ,	   0x1180080942400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1153"            ,	   0x1180080942408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1154"            ,	   0x1180080942410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1155"            ,	   0x1180080942418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1156"            ,	   0x1180080942420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1157"            ,	   0x1180080942428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1158"            ,	   0x1180080942430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1159"            ,	   0x1180080942438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1160"            ,	   0x1180080942440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1161"            ,	   0x1180080942448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1162"            ,	   0x1180080942450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1163"            ,	   0x1180080942458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1164"            ,	   0x1180080942460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1165"            ,	   0x1180080942468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1166"            ,	   0x1180080942470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1167"            ,	   0x1180080942478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1168"            ,	   0x1180080942480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1169"            ,	   0x1180080942488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1170"            ,	   0x1180080942490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1171"            ,	   0x1180080942498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1172"            ,	   0x11800809424a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1173"            ,	   0x11800809424a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1174"            ,	   0x11800809424b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1175"            ,	   0x11800809424b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1176"            ,	   0x11800809424c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1177"            ,	   0x11800809424c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1178"            ,	   0x11800809424d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1179"            ,	   0x11800809424d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1180"            ,	   0x11800809424e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1181"            ,	   0x11800809424e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1182"            ,	   0x11800809424f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1183"            ,	   0x11800809424f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1184"            ,	   0x1180080942500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1185"            ,	   0x1180080942508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1186"            ,	   0x1180080942510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1187"            ,	   0x1180080942518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1188"            ,	   0x1180080942520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1189"            ,	   0x1180080942528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1190"            ,	   0x1180080942530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1191"            ,	   0x1180080942538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1192"            ,	   0x1180080942540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1193"            ,	   0x1180080942548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1194"            ,	   0x1180080942550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1195"            ,	   0x1180080942558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1196"            ,	   0x1180080942560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1197"            ,	   0x1180080942568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1198"            ,	   0x1180080942570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1199"            ,	   0x1180080942578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1200"            ,	   0x1180080942580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1201"            ,	   0x1180080942588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1202"            ,	   0x1180080942590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1203"            ,	   0x1180080942598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1204"            ,	   0x11800809425a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1205"            ,	   0x11800809425a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1206"            ,	   0x11800809425b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1207"            ,	   0x11800809425b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1208"            ,	   0x11800809425c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1209"            ,	   0x11800809425c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1210"            ,	   0x11800809425d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1211"            ,	   0x11800809425d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1212"            ,	   0x11800809425e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1213"            ,	   0x11800809425e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1214"            ,	   0x11800809425f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1215"            ,	   0x11800809425f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1216"            ,	   0x1180080942600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1217"            ,	   0x1180080942608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1218"            ,	   0x1180080942610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1219"            ,	   0x1180080942618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1220"            ,	   0x1180080942620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1221"            ,	   0x1180080942628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1222"            ,	   0x1180080942630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1223"            ,	   0x1180080942638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1224"            ,	   0x1180080942640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1225"            ,	   0x1180080942648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1226"            ,	   0x1180080942650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1227"            ,	   0x1180080942658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1228"            ,	   0x1180080942660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1229"            ,	   0x1180080942668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1230"            ,	   0x1180080942670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1231"            ,	   0x1180080942678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1232"            ,	   0x1180080942680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1233"            ,	   0x1180080942688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1234"            ,	   0x1180080942690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1235"            ,	   0x1180080942698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1236"            ,	   0x11800809426a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1237"            ,	   0x11800809426a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1238"            ,	   0x11800809426b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1239"            ,	   0x11800809426b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1240"            ,	   0x11800809426c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1241"            ,	   0x11800809426c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1242"            ,	   0x11800809426d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1243"            ,	   0x11800809426d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1244"            ,	   0x11800809426e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1245"            ,	   0x11800809426e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1246"            ,	   0x11800809426f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1247"            ,	   0x11800809426f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1248"            ,	   0x1180080942700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1249"            ,	   0x1180080942708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1250"            ,	   0x1180080942710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1251"            ,	   0x1180080942718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1252"            ,	   0x1180080942720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1253"            ,	   0x1180080942728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1254"            ,	   0x1180080942730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1255"            ,	   0x1180080942738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1256"            ,	   0x1180080942740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1257"            ,	   0x1180080942748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1258"            ,	   0x1180080942750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1259"            ,	   0x1180080942758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1260"            ,	   0x1180080942760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1261"            ,	   0x1180080942768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1262"            ,	   0x1180080942770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1263"            ,	   0x1180080942778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1264"            ,	   0x1180080942780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1265"            ,	   0x1180080942788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1266"            ,	   0x1180080942790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1267"            ,	   0x1180080942798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1268"            ,	   0x11800809427a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1269"            ,	   0x11800809427a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1270"            ,	   0x11800809427b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1271"            ,	   0x11800809427b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1272"            ,	   0x11800809427c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1273"            ,	   0x11800809427c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1274"            ,	   0x11800809427d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1275"            ,	   0x11800809427d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1276"            ,	   0x11800809427e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1277"            ,	   0x11800809427e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1278"            ,	   0x11800809427f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1279"            ,	   0x11800809427f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1280"            ,	   0x1180080942800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1281"            ,	   0x1180080942808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1282"            ,	   0x1180080942810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1283"            ,	   0x1180080942818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1284"            ,	   0x1180080942820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1285"            ,	   0x1180080942828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1286"            ,	   0x1180080942830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1287"            ,	   0x1180080942838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1288"            ,	   0x1180080942840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1289"            ,	   0x1180080942848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1290"            ,	   0x1180080942850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1291"            ,	   0x1180080942858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1292"            ,	   0x1180080942860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1293"            ,	   0x1180080942868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1294"            ,	   0x1180080942870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1295"            ,	   0x1180080942878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1296"            ,	   0x1180080942880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1297"            ,	   0x1180080942888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1298"            ,	   0x1180080942890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1299"            ,	   0x1180080942898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1300"            ,	   0x11800809428a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1301"            ,	   0x11800809428a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1302"            ,	   0x11800809428b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1303"            ,	   0x11800809428b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1304"            ,	   0x11800809428c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1305"            ,	   0x11800809428c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1306"            ,	   0x11800809428d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1307"            ,	   0x11800809428d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1308"            ,	   0x11800809428e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1309"            ,	   0x11800809428e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1310"            ,	   0x11800809428f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1311"            ,	   0x11800809428f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1312"            ,	   0x1180080942900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1313"            ,	   0x1180080942908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1314"            ,	   0x1180080942910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1315"            ,	   0x1180080942918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1316"            ,	   0x1180080942920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1317"            ,	   0x1180080942928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1318"            ,	   0x1180080942930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1319"            ,	   0x1180080942938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1320"            ,	   0x1180080942940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1321"            ,	   0x1180080942948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1322"            ,	   0x1180080942950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1323"            ,	   0x1180080942958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1324"            ,	   0x1180080942960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1325"            ,	   0x1180080942968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1326"            ,	   0x1180080942970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1327"            ,	   0x1180080942978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1328"            ,	   0x1180080942980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1329"            ,	   0x1180080942988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1330"            ,	   0x1180080942990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1331"            ,	   0x1180080942998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1332"            ,	   0x11800809429a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1333"            ,	   0x11800809429a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1334"            ,	   0x11800809429b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1335"            ,	   0x11800809429b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1336"            ,	   0x11800809429c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1337"            ,	   0x11800809429c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1338"            ,	   0x11800809429d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1339"            ,	   0x11800809429d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1340"            ,	   0x11800809429e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1341"            ,	   0x11800809429e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1342"            ,	   0x11800809429f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1343"            ,	   0x11800809429f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1344"            ,	   0x1180080942a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1345"            ,	   0x1180080942a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1346"            ,	   0x1180080942a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1347"            ,	   0x1180080942a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1348"            ,	   0x1180080942a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1349"            ,	   0x1180080942a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1350"            ,	   0x1180080942a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1351"            ,	   0x1180080942a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1352"            ,	   0x1180080942a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1353"            ,	   0x1180080942a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1354"            ,	   0x1180080942a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1355"            ,	   0x1180080942a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1356"            ,	   0x1180080942a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1357"            ,	   0x1180080942a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1358"            ,	   0x1180080942a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1359"            ,	   0x1180080942a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1360"            ,	   0x1180080942a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1361"            ,	   0x1180080942a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1362"            ,	   0x1180080942a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1363"            ,	   0x1180080942a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1364"            ,	   0x1180080942aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1365"            ,	   0x1180080942aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1366"            ,	   0x1180080942ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1367"            ,	   0x1180080942ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1368"            ,	   0x1180080942ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1369"            ,	   0x1180080942ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1370"            ,	   0x1180080942ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1371"            ,	   0x1180080942ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1372"            ,	   0x1180080942ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1373"            ,	   0x1180080942ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1374"            ,	   0x1180080942af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1375"            ,	   0x1180080942af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1376"            ,	   0x1180080942b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1377"            ,	   0x1180080942b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1378"            ,	   0x1180080942b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1379"            ,	   0x1180080942b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1380"            ,	   0x1180080942b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1381"            ,	   0x1180080942b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1382"            ,	   0x1180080942b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1383"            ,	   0x1180080942b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1384"            ,	   0x1180080942b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1385"            ,	   0x1180080942b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1386"            ,	   0x1180080942b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1387"            ,	   0x1180080942b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1388"            ,	   0x1180080942b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1389"            ,	   0x1180080942b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1390"            ,	   0x1180080942b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1391"            ,	   0x1180080942b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1392"            ,	   0x1180080942b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1393"            ,	   0x1180080942b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1394"            ,	   0x1180080942b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1395"            ,	   0x1180080942b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1396"            ,	   0x1180080942ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1397"            ,	   0x1180080942ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1398"            ,	   0x1180080942bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1399"            ,	   0x1180080942bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1400"            ,	   0x1180080942bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1401"            ,	   0x1180080942bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1402"            ,	   0x1180080942bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1403"            ,	   0x1180080942bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1404"            ,	   0x1180080942be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1405"            ,	   0x1180080942be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1406"            ,	   0x1180080942bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1407"            ,	   0x1180080942bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1408"            ,	   0x1180080942c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1409"            ,	   0x1180080942c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1410"            ,	   0x1180080942c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1411"            ,	   0x1180080942c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1412"            ,	   0x1180080942c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1413"            ,	   0x1180080942c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1414"            ,	   0x1180080942c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1415"            ,	   0x1180080942c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1416"            ,	   0x1180080942c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1417"            ,	   0x1180080942c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1418"            ,	   0x1180080942c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1419"            ,	   0x1180080942c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1420"            ,	   0x1180080942c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1421"            ,	   0x1180080942c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1422"            ,	   0x1180080942c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1423"            ,	   0x1180080942c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1424"            ,	   0x1180080942c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1425"            ,	   0x1180080942c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1426"            ,	   0x1180080942c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1427"            ,	   0x1180080942c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1428"            ,	   0x1180080942ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1429"            ,	   0x1180080942ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1430"            ,	   0x1180080942cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1431"            ,	   0x1180080942cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1432"            ,	   0x1180080942cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1433"            ,	   0x1180080942cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1434"            ,	   0x1180080942cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1435"            ,	   0x1180080942cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1436"            ,	   0x1180080942ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1437"            ,	   0x1180080942ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1438"            ,	   0x1180080942cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1439"            ,	   0x1180080942cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1440"            ,	   0x1180080942d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1441"            ,	   0x1180080942d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1442"            ,	   0x1180080942d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1443"            ,	   0x1180080942d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1444"            ,	   0x1180080942d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1445"            ,	   0x1180080942d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1446"            ,	   0x1180080942d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1447"            ,	   0x1180080942d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1448"            ,	   0x1180080942d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1449"            ,	   0x1180080942d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1450"            ,	   0x1180080942d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1451"            ,	   0x1180080942d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1452"            ,	   0x1180080942d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1453"            ,	   0x1180080942d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1454"            ,	   0x1180080942d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1455"            ,	   0x1180080942d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1456"            ,	   0x1180080942d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1457"            ,	   0x1180080942d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1458"            ,	   0x1180080942d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1459"            ,	   0x1180080942d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1460"            ,	   0x1180080942da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1461"            ,	   0x1180080942da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1462"            ,	   0x1180080942db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1463"            ,	   0x1180080942db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1464"            ,	   0x1180080942dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1465"            ,	   0x1180080942dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1466"            ,	   0x1180080942dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1467"            ,	   0x1180080942dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1468"            ,	   0x1180080942de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1469"            ,	   0x1180080942de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1470"            ,	   0x1180080942df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1471"            ,	   0x1180080942df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1472"            ,	   0x1180080942e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1473"            ,	   0x1180080942e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1474"            ,	   0x1180080942e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1475"            ,	   0x1180080942e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1476"            ,	   0x1180080942e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1477"            ,	   0x1180080942e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1478"            ,	   0x1180080942e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1479"            ,	   0x1180080942e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1480"            ,	   0x1180080942e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1481"            ,	   0x1180080942e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1482"            ,	   0x1180080942e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1483"            ,	   0x1180080942e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1484"            ,	   0x1180080942e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1485"            ,	   0x1180080942e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1486"            ,	   0x1180080942e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1487"            ,	   0x1180080942e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1488"            ,	   0x1180080942e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1489"            ,	   0x1180080942e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1490"            ,	   0x1180080942e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1491"            ,	   0x1180080942e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1492"            ,	   0x1180080942ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1493"            ,	   0x1180080942ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1494"            ,	   0x1180080942eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1495"            ,	   0x1180080942eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1496"            ,	   0x1180080942ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1497"            ,	   0x1180080942ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1498"            ,	   0x1180080942ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1499"            ,	   0x1180080942ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1500"            ,	   0x1180080942ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1501"            ,	   0x1180080942ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1502"            ,	   0x1180080942ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1503"            ,	   0x1180080942ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1504"            ,	   0x1180080942f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1505"            ,	   0x1180080942f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1506"            ,	   0x1180080942f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1507"            ,	   0x1180080942f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1508"            ,	   0x1180080942f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1509"            ,	   0x1180080942f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1510"            ,	   0x1180080942f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1511"            ,	   0x1180080942f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1512"            ,	   0x1180080942f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1513"            ,	   0x1180080942f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1514"            ,	   0x1180080942f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1515"            ,	   0x1180080942f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1516"            ,	   0x1180080942f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1517"            ,	   0x1180080942f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1518"            ,	   0x1180080942f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1519"            ,	   0x1180080942f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1520"            ,	   0x1180080942f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1521"            ,	   0x1180080942f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1522"            ,	   0x1180080942f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1523"            ,	   0x1180080942f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1524"            ,	   0x1180080942fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1525"            ,	   0x1180080942fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1526"            ,	   0x1180080942fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1527"            ,	   0x1180080942fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1528"            ,	   0x1180080942fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1529"            ,	   0x1180080942fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1530"            ,	   0x1180080942fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1531"            ,	   0x1180080942fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1532"            ,	   0x1180080942fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1533"            ,	   0x1180080942fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1534"            ,	   0x1180080942ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP1535"            ,	   0x1180080942ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1024"             ,	   0x1180080e02000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1025"             ,	   0x1180080e02008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1026"             ,	   0x1180080e02010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1027"             ,	   0x1180080e02018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1028"             ,	   0x1180080e02020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1029"             ,	   0x1180080e02028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1030"             ,	   0x1180080e02030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1031"             ,	   0x1180080e02038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1032"             ,	   0x1180080e02040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1033"             ,	   0x1180080e02048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1034"             ,	   0x1180080e02050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1035"             ,	   0x1180080e02058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1036"             ,	   0x1180080e02060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1037"             ,	   0x1180080e02068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1038"             ,	   0x1180080e02070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1039"             ,	   0x1180080e02078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1040"             ,	   0x1180080e02080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1041"             ,	   0x1180080e02088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1042"             ,	   0x1180080e02090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1043"             ,	   0x1180080e02098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1044"             ,	   0x1180080e020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1045"             ,	   0x1180080e020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1046"             ,	   0x1180080e020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1047"             ,	   0x1180080e020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1048"             ,	   0x1180080e020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1049"             ,	   0x1180080e020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1050"             ,	   0x1180080e020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1051"             ,	   0x1180080e020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1052"             ,	   0x1180080e020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1053"             ,	   0x1180080e020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1054"             ,	   0x1180080e020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1055"             ,	   0x1180080e020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1056"             ,	   0x1180080e02100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1057"             ,	   0x1180080e02108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1058"             ,	   0x1180080e02110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1059"             ,	   0x1180080e02118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1060"             ,	   0x1180080e02120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1061"             ,	   0x1180080e02128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1062"             ,	   0x1180080e02130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1063"             ,	   0x1180080e02138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1064"             ,	   0x1180080e02140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1065"             ,	   0x1180080e02148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1066"             ,	   0x1180080e02150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1067"             ,	   0x1180080e02158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1068"             ,	   0x1180080e02160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1069"             ,	   0x1180080e02168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1070"             ,	   0x1180080e02170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1071"             ,	   0x1180080e02178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1072"             ,	   0x1180080e02180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1073"             ,	   0x1180080e02188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1074"             ,	   0x1180080e02190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1075"             ,	   0x1180080e02198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1076"             ,	   0x1180080e021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1077"             ,	   0x1180080e021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1078"             ,	   0x1180080e021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1079"             ,	   0x1180080e021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1080"             ,	   0x1180080e021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1081"             ,	   0x1180080e021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1082"             ,	   0x1180080e021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1083"             ,	   0x1180080e021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1084"             ,	   0x1180080e021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1085"             ,	   0x1180080e021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1086"             ,	   0x1180080e021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1087"             ,	   0x1180080e021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1088"             ,	   0x1180080e02200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1089"             ,	   0x1180080e02208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1090"             ,	   0x1180080e02210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1091"             ,	   0x1180080e02218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1092"             ,	   0x1180080e02220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1093"             ,	   0x1180080e02228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1094"             ,	   0x1180080e02230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1095"             ,	   0x1180080e02238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1096"             ,	   0x1180080e02240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1097"             ,	   0x1180080e02248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1098"             ,	   0x1180080e02250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1099"             ,	   0x1180080e02258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1100"             ,	   0x1180080e02260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1101"             ,	   0x1180080e02268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1102"             ,	   0x1180080e02270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1103"             ,	   0x1180080e02278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1104"             ,	   0x1180080e02280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1105"             ,	   0x1180080e02288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1106"             ,	   0x1180080e02290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1107"             ,	   0x1180080e02298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1108"             ,	   0x1180080e022a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1109"             ,	   0x1180080e022a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1110"             ,	   0x1180080e022b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1111"             ,	   0x1180080e022b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1112"             ,	   0x1180080e022c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1113"             ,	   0x1180080e022c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1114"             ,	   0x1180080e022d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1115"             ,	   0x1180080e022d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1116"             ,	   0x1180080e022e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1117"             ,	   0x1180080e022e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1118"             ,	   0x1180080e022f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1119"             ,	   0x1180080e022f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1120"             ,	   0x1180080e02300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1121"             ,	   0x1180080e02308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1122"             ,	   0x1180080e02310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1123"             ,	   0x1180080e02318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1124"             ,	   0x1180080e02320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1125"             ,	   0x1180080e02328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1126"             ,	   0x1180080e02330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1127"             ,	   0x1180080e02338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1128"             ,	   0x1180080e02340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1129"             ,	   0x1180080e02348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1130"             ,	   0x1180080e02350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1131"             ,	   0x1180080e02358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1132"             ,	   0x1180080e02360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1133"             ,	   0x1180080e02368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1134"             ,	   0x1180080e02370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1135"             ,	   0x1180080e02378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1136"             ,	   0x1180080e02380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1137"             ,	   0x1180080e02388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1138"             ,	   0x1180080e02390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1139"             ,	   0x1180080e02398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1140"             ,	   0x1180080e023a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1141"             ,	   0x1180080e023a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1142"             ,	   0x1180080e023b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1143"             ,	   0x1180080e023b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1144"             ,	   0x1180080e023c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1145"             ,	   0x1180080e023c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1146"             ,	   0x1180080e023d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1147"             ,	   0x1180080e023d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1148"             ,	   0x1180080e023e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1149"             ,	   0x1180080e023e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1150"             ,	   0x1180080e023f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1151"             ,	   0x1180080e023f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1152"             ,	   0x1180080e02400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1153"             ,	   0x1180080e02408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1154"             ,	   0x1180080e02410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1155"             ,	   0x1180080e02418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1156"             ,	   0x1180080e02420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1157"             ,	   0x1180080e02428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1158"             ,	   0x1180080e02430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1159"             ,	   0x1180080e02438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1160"             ,	   0x1180080e02440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1161"             ,	   0x1180080e02448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1162"             ,	   0x1180080e02450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1163"             ,	   0x1180080e02458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1164"             ,	   0x1180080e02460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1165"             ,	   0x1180080e02468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1166"             ,	   0x1180080e02470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1167"             ,	   0x1180080e02478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1168"             ,	   0x1180080e02480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1169"             ,	   0x1180080e02488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1170"             ,	   0x1180080e02490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1171"             ,	   0x1180080e02498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1172"             ,	   0x1180080e024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1173"             ,	   0x1180080e024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1174"             ,	   0x1180080e024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1175"             ,	   0x1180080e024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1176"             ,	   0x1180080e024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1177"             ,	   0x1180080e024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1178"             ,	   0x1180080e024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1179"             ,	   0x1180080e024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1180"             ,	   0x1180080e024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1181"             ,	   0x1180080e024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1182"             ,	   0x1180080e024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1183"             ,	   0x1180080e024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1184"             ,	   0x1180080e02500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1185"             ,	   0x1180080e02508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1186"             ,	   0x1180080e02510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1187"             ,	   0x1180080e02518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1188"             ,	   0x1180080e02520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1189"             ,	   0x1180080e02528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1190"             ,	   0x1180080e02530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1191"             ,	   0x1180080e02538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1192"             ,	   0x1180080e02540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1193"             ,	   0x1180080e02548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1194"             ,	   0x1180080e02550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1195"             ,	   0x1180080e02558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1196"             ,	   0x1180080e02560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1197"             ,	   0x1180080e02568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1198"             ,	   0x1180080e02570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1199"             ,	   0x1180080e02578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1200"             ,	   0x1180080e02580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1201"             ,	   0x1180080e02588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1202"             ,	   0x1180080e02590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1203"             ,	   0x1180080e02598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1204"             ,	   0x1180080e025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1205"             ,	   0x1180080e025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1206"             ,	   0x1180080e025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1207"             ,	   0x1180080e025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1208"             ,	   0x1180080e025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1209"             ,	   0x1180080e025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1210"             ,	   0x1180080e025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1211"             ,	   0x1180080e025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1212"             ,	   0x1180080e025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1213"             ,	   0x1180080e025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1214"             ,	   0x1180080e025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1215"             ,	   0x1180080e025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1216"             ,	   0x1180080e02600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1217"             ,	   0x1180080e02608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1218"             ,	   0x1180080e02610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1219"             ,	   0x1180080e02618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1220"             ,	   0x1180080e02620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1221"             ,	   0x1180080e02628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1222"             ,	   0x1180080e02630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1223"             ,	   0x1180080e02638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1224"             ,	   0x1180080e02640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1225"             ,	   0x1180080e02648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1226"             ,	   0x1180080e02650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1227"             ,	   0x1180080e02658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1228"             ,	   0x1180080e02660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1229"             ,	   0x1180080e02668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1230"             ,	   0x1180080e02670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1231"             ,	   0x1180080e02678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1232"             ,	   0x1180080e02680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1233"             ,	   0x1180080e02688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1234"             ,	   0x1180080e02690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1235"             ,	   0x1180080e02698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1236"             ,	   0x1180080e026a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1237"             ,	   0x1180080e026a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1238"             ,	   0x1180080e026b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1239"             ,	   0x1180080e026b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1240"             ,	   0x1180080e026c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1241"             ,	   0x1180080e026c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1242"             ,	   0x1180080e026d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1243"             ,	   0x1180080e026d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1244"             ,	   0x1180080e026e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1245"             ,	   0x1180080e026e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1246"             ,	   0x1180080e026f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1247"             ,	   0x1180080e026f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1248"             ,	   0x1180080e02700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1249"             ,	   0x1180080e02708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1250"             ,	   0x1180080e02710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1251"             ,	   0x1180080e02718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1252"             ,	   0x1180080e02720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1253"             ,	   0x1180080e02728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1254"             ,	   0x1180080e02730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1255"             ,	   0x1180080e02738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1256"             ,	   0x1180080e02740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1257"             ,	   0x1180080e02748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1258"             ,	   0x1180080e02750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1259"             ,	   0x1180080e02758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1260"             ,	   0x1180080e02760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1261"             ,	   0x1180080e02768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1262"             ,	   0x1180080e02770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1263"             ,	   0x1180080e02778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1264"             ,	   0x1180080e02780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1265"             ,	   0x1180080e02788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1266"             ,	   0x1180080e02790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1267"             ,	   0x1180080e02798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1268"             ,	   0x1180080e027a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1269"             ,	   0x1180080e027a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1270"             ,	   0x1180080e027b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1271"             ,	   0x1180080e027b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1272"             ,	   0x1180080e027c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1273"             ,	   0x1180080e027c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1274"             ,	   0x1180080e027d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1275"             ,	   0x1180080e027d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1276"             ,	   0x1180080e027e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1277"             ,	   0x1180080e027e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1278"             ,	   0x1180080e027f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1279"             ,	   0x1180080e027f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1280"             ,	   0x1180080e02800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1281"             ,	   0x1180080e02808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1282"             ,	   0x1180080e02810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1283"             ,	   0x1180080e02818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1284"             ,	   0x1180080e02820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1285"             ,	   0x1180080e02828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1286"             ,	   0x1180080e02830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1287"             ,	   0x1180080e02838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1288"             ,	   0x1180080e02840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1289"             ,	   0x1180080e02848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1290"             ,	   0x1180080e02850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1291"             ,	   0x1180080e02858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1292"             ,	   0x1180080e02860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1293"             ,	   0x1180080e02868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1294"             ,	   0x1180080e02870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1295"             ,	   0x1180080e02878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1296"             ,	   0x1180080e02880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1297"             ,	   0x1180080e02888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1298"             ,	   0x1180080e02890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1299"             ,	   0x1180080e02898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1300"             ,	   0x1180080e028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1301"             ,	   0x1180080e028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1302"             ,	   0x1180080e028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1303"             ,	   0x1180080e028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1304"             ,	   0x1180080e028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1305"             ,	   0x1180080e028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1306"             ,	   0x1180080e028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1307"             ,	   0x1180080e028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1308"             ,	   0x1180080e028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1309"             ,	   0x1180080e028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1310"             ,	   0x1180080e028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1311"             ,	   0x1180080e028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1312"             ,	   0x1180080e02900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1313"             ,	   0x1180080e02908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1314"             ,	   0x1180080e02910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1315"             ,	   0x1180080e02918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1316"             ,	   0x1180080e02920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1317"             ,	   0x1180080e02928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1318"             ,	   0x1180080e02930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1319"             ,	   0x1180080e02938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1320"             ,	   0x1180080e02940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1321"             ,	   0x1180080e02948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1322"             ,	   0x1180080e02950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1323"             ,	   0x1180080e02958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1324"             ,	   0x1180080e02960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1325"             ,	   0x1180080e02968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1326"             ,	   0x1180080e02970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1327"             ,	   0x1180080e02978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1328"             ,	   0x1180080e02980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1329"             ,	   0x1180080e02988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1330"             ,	   0x1180080e02990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1331"             ,	   0x1180080e02998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1332"             ,	   0x1180080e029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1333"             ,	   0x1180080e029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1334"             ,	   0x1180080e029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1335"             ,	   0x1180080e029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1336"             ,	   0x1180080e029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1337"             ,	   0x1180080e029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1338"             ,	   0x1180080e029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1339"             ,	   0x1180080e029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1340"             ,	   0x1180080e029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1341"             ,	   0x1180080e029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1342"             ,	   0x1180080e029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1343"             ,	   0x1180080e029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1344"             ,	   0x1180080e02a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1345"             ,	   0x1180080e02a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1346"             ,	   0x1180080e02a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1347"             ,	   0x1180080e02a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1348"             ,	   0x1180080e02a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1349"             ,	   0x1180080e02a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1350"             ,	   0x1180080e02a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1351"             ,	   0x1180080e02a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1352"             ,	   0x1180080e02a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1353"             ,	   0x1180080e02a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1354"             ,	   0x1180080e02a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1355"             ,	   0x1180080e02a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1356"             ,	   0x1180080e02a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1357"             ,	   0x1180080e02a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1358"             ,	   0x1180080e02a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1359"             ,	   0x1180080e02a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1360"             ,	   0x1180080e02a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1361"             ,	   0x1180080e02a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1362"             ,	   0x1180080e02a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1363"             ,	   0x1180080e02a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1364"             ,	   0x1180080e02aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1365"             ,	   0x1180080e02aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1366"             ,	   0x1180080e02ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1367"             ,	   0x1180080e02ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1368"             ,	   0x1180080e02ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1369"             ,	   0x1180080e02ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1370"             ,	   0x1180080e02ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1371"             ,	   0x1180080e02ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1372"             ,	   0x1180080e02ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1373"             ,	   0x1180080e02ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1374"             ,	   0x1180080e02af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1375"             ,	   0x1180080e02af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1376"             ,	   0x1180080e02b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1377"             ,	   0x1180080e02b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1378"             ,	   0x1180080e02b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1379"             ,	   0x1180080e02b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1380"             ,	   0x1180080e02b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1381"             ,	   0x1180080e02b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1382"             ,	   0x1180080e02b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1383"             ,	   0x1180080e02b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1384"             ,	   0x1180080e02b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1385"             ,	   0x1180080e02b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1386"             ,	   0x1180080e02b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1387"             ,	   0x1180080e02b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1388"             ,	   0x1180080e02b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1389"             ,	   0x1180080e02b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1390"             ,	   0x1180080e02b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1391"             ,	   0x1180080e02b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1392"             ,	   0x1180080e02b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1393"             ,	   0x1180080e02b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1394"             ,	   0x1180080e02b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1395"             ,	   0x1180080e02b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1396"             ,	   0x1180080e02ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1397"             ,	   0x1180080e02ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1398"             ,	   0x1180080e02bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1399"             ,	   0x1180080e02bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1400"             ,	   0x1180080e02bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1401"             ,	   0x1180080e02bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1402"             ,	   0x1180080e02bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1403"             ,	   0x1180080e02bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1404"             ,	   0x1180080e02be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1405"             ,	   0x1180080e02be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1406"             ,	   0x1180080e02bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1407"             ,	   0x1180080e02bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1408"             ,	   0x1180080e02c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1409"             ,	   0x1180080e02c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1410"             ,	   0x1180080e02c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1411"             ,	   0x1180080e02c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1412"             ,	   0x1180080e02c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1413"             ,	   0x1180080e02c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1414"             ,	   0x1180080e02c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1415"             ,	   0x1180080e02c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1416"             ,	   0x1180080e02c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1417"             ,	   0x1180080e02c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1418"             ,	   0x1180080e02c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1419"             ,	   0x1180080e02c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1420"             ,	   0x1180080e02c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1421"             ,	   0x1180080e02c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1422"             ,	   0x1180080e02c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1423"             ,	   0x1180080e02c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1424"             ,	   0x1180080e02c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1425"             ,	   0x1180080e02c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1426"             ,	   0x1180080e02c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1427"             ,	   0x1180080e02c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1428"             ,	   0x1180080e02ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1429"             ,	   0x1180080e02ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1430"             ,	   0x1180080e02cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1431"             ,	   0x1180080e02cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1432"             ,	   0x1180080e02cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1433"             ,	   0x1180080e02cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1434"             ,	   0x1180080e02cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1435"             ,	   0x1180080e02cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1436"             ,	   0x1180080e02ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1437"             ,	   0x1180080e02ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1438"             ,	   0x1180080e02cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1439"             ,	   0x1180080e02cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1440"             ,	   0x1180080e02d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1441"             ,	   0x1180080e02d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1442"             ,	   0x1180080e02d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1443"             ,	   0x1180080e02d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1444"             ,	   0x1180080e02d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1445"             ,	   0x1180080e02d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1446"             ,	   0x1180080e02d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1447"             ,	   0x1180080e02d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1448"             ,	   0x1180080e02d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1449"             ,	   0x1180080e02d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1450"             ,	   0x1180080e02d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1451"             ,	   0x1180080e02d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1452"             ,	   0x1180080e02d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1453"             ,	   0x1180080e02d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1454"             ,	   0x1180080e02d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1455"             ,	   0x1180080e02d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1456"             ,	   0x1180080e02d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1457"             ,	   0x1180080e02d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1458"             ,	   0x1180080e02d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1459"             ,	   0x1180080e02d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1460"             ,	   0x1180080e02da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1461"             ,	   0x1180080e02da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1462"             ,	   0x1180080e02db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1463"             ,	   0x1180080e02db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1464"             ,	   0x1180080e02dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1465"             ,	   0x1180080e02dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1466"             ,	   0x1180080e02dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1467"             ,	   0x1180080e02dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1468"             ,	   0x1180080e02de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1469"             ,	   0x1180080e02de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1470"             ,	   0x1180080e02df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1471"             ,	   0x1180080e02df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1472"             ,	   0x1180080e02e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1473"             ,	   0x1180080e02e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1474"             ,	   0x1180080e02e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1475"             ,	   0x1180080e02e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1476"             ,	   0x1180080e02e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1477"             ,	   0x1180080e02e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1478"             ,	   0x1180080e02e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1479"             ,	   0x1180080e02e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1480"             ,	   0x1180080e02e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1481"             ,	   0x1180080e02e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1482"             ,	   0x1180080e02e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1483"             ,	   0x1180080e02e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1484"             ,	   0x1180080e02e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1485"             ,	   0x1180080e02e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1486"             ,	   0x1180080e02e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1487"             ,	   0x1180080e02e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1488"             ,	   0x1180080e02e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1489"             ,	   0x1180080e02e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1490"             ,	   0x1180080e02e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1491"             ,	   0x1180080e02e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1492"             ,	   0x1180080e02ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1493"             ,	   0x1180080e02ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1494"             ,	   0x1180080e02eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1495"             ,	   0x1180080e02eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1496"             ,	   0x1180080e02ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1497"             ,	   0x1180080e02ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1498"             ,	   0x1180080e02ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1499"             ,	   0x1180080e02ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1500"             ,	   0x1180080e02ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1501"             ,	   0x1180080e02ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1502"             ,	   0x1180080e02ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1503"             ,	   0x1180080e02ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1504"             ,	   0x1180080e02f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1505"             ,	   0x1180080e02f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1506"             ,	   0x1180080e02f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1507"             ,	   0x1180080e02f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1508"             ,	   0x1180080e02f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1509"             ,	   0x1180080e02f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1510"             ,	   0x1180080e02f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1511"             ,	   0x1180080e02f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1512"             ,	   0x1180080e02f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1513"             ,	   0x1180080e02f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1514"             ,	   0x1180080e02f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1515"             ,	   0x1180080e02f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1516"             ,	   0x1180080e02f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1517"             ,	   0x1180080e02f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1518"             ,	   0x1180080e02f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1519"             ,	   0x1180080e02f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1520"             ,	   0x1180080e02f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1521"             ,	   0x1180080e02f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1522"             ,	   0x1180080e02f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1523"             ,	   0x1180080e02f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1524"             ,	   0x1180080e02fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1525"             ,	   0x1180080e02fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1526"             ,	   0x1180080e02fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1527"             ,	   0x1180080e02fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1528"             ,	   0x1180080e02fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1529"             ,	   0x1180080e02fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1530"             ,	   0x1180080e02fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1531"             ,	   0x1180080e02fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1532"             ,	   0x1180080e02fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1533"             ,	   0x1180080e02fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1534"             ,	   0x1180080e02ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_DUT_MAP1535"             ,	   0x1180080e02ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_PP4"                 ,	   0x1180080880020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_PP5"                 ,	   0x1180080880028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VIRTID_PP4"              ,	   0x11800808c0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VIRTID_PP5"              ,	   0x11800808c0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM82"               ,	   0x1180080900290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM83"               ,	   0x1180080900298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM84"               ,	   0x11800809002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM85"               ,	   0x11800809002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM86"               ,	   0x11800809002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM87"               ,	   0x11800809002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM88"               ,	   0x11800809002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM89"               ,	   0x11800809002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM90"               ,	   0x11800809002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM91"               ,	   0x11800809002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM92"               ,	   0x11800809002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM93"               ,	   0x11800809002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM94"               ,	   0x11800809002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM95"               ,	   0x11800809002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM96"               ,	   0x1180080900300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM97"               ,	   0x1180080900308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM98"               ,	   0x1180080900310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM99"               ,	   0x1180080900318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM100"              ,	   0x1180080900320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM101"              ,	   0x1180080900328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM102"              ,	   0x1180080900330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM103"              ,	   0x1180080900338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM104"              ,	   0x1180080900340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
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+	{"L2C_VRT_MEM106"              ,	   0x1180080900350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM107"              ,	   0x1180080900358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM108"              ,	   0x1180080900360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM109"              ,	   0x1180080900368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM110"              ,	   0x1180080900370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM111"              ,	   0x1180080900378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
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+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_WPAR_PP4"                ,	   0x1180080840020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_WPAR_PP5"                ,	   0x1180080840028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	522},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	522},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	523},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	523},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	525},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	525},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	527},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	527},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	530},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	530},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	531},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	531},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	532},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	532},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	533},
+	{"MIX1_TSCTL"                  ,	   0x1070000100868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	533},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	534},
+	{"MIX1_TSTAMP"                 ,	   0x1070000100860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	534},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	535},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	536},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	537},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	538},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	539},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	540},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	541},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PEM0_P2P_BAR000_END"         ,	   0x11800c0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM0_P2P_BAR001_END"         ,	   0x11800c0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM0_P2P_BAR002_END"         ,	   0x11800c0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM0_P2P_BAR003_END"         ,	   0x11800c0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM1_P2P_BAR000_END"         ,	   0x11800c1000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM1_P2P_BAR001_END"         ,	   0x11800c1000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM1_P2P_BAR002_END"         ,	   0x11800c1000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM1_P2P_BAR003_END"         ,	   0x11800c1000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM0_P2P_BAR000_START"       ,	   0x11800c0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM0_P2P_BAR001_START"       ,	   0x11800c0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM0_P2P_BAR002_START"       ,	   0x11800c0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM0_P2P_BAR003_START"       ,	   0x11800c0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM1_P2P_BAR000_START"       ,	   0x11800c1000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM1_P2P_BAR001_START"       ,	   0x11800c1000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM1_P2P_BAR002_START"       ,	   0x11800c1000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM1_P2P_BAR003_START"       ,	   0x11800c1000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG40"               ,	   0x11800a0000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG41"               ,	   0x11800a0000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG42"               ,	   0x11800a0000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_CFG43"               ,	   0x11800a0000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG40"               ,	   0x11800a0000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG41"               ,	   0x11800a0000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG42"               ,	   0x11800a0000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_PRT_TAG43"               ,	   0x11800a0000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	839},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	840},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	841},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	842},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	843},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	844},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	887},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	888},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	888},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	889},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	890},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	891},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	892},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	893},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	893},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	894},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	895},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	895},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	896},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	898},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	911},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	917},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	969},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	970},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	971},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	972},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	973},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	975},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	976},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	977},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	978},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	979},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	980},
+	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	981},
+	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	982},
+	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	983},
+	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	984},
+	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1019},
+	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1019},
+	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1020},
+	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1020},
+	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1021},
+	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1022},
+	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1022},
+	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1023},
+	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1023},
+	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1024},
+	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1024},
+	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
+	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1025},
+	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
+	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1026},
+	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1027},
+	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
+	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1028},
+	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
+	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1029},
+	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
+	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1030},
+	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
+	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1031},
+	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
+	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1032},
+	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
+	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1033},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1034},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1035},
+	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
+	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1036},
+	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1079},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1080},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1081},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1082},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1083},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1084},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1085},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1086},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1087},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1088},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1089},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1090},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1091},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1092},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1093},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1094},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1095},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1096},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1097},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1098},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1099},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1100},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1101},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1102},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1103},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1110},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1111},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1112},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1113},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1114},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1115},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1116},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1117},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1118},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1119},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1120},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1121},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1122},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1123},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1123},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1124},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1125},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1126},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1127},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1128},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1129},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1130},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1131},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1132},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1133},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1134},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1135},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1136},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1137},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1138},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1139},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1140},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1141},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1151},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1152},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1153},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1154},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1155},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1156},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1157},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1158},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1159},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1160},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1161},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1162},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1163},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1163},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1164},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1165},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1166},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1167},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1168},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1169},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1170},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1171},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	5,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	72,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	3,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IPD"                         ,	9,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	16,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PIP"                         ,	20,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"ASXPCS0"                     ,	22,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PEM0"                        ,	25,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	26,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	28,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	30,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"SRIO0"                       ,	32,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	33,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	73,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	40,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	41,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	42,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	73,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	6,	74,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	74,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	6,	75,	"RO",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	75,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	76,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	78,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	79,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	80,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	81,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	82,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	83,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	84,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	85,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	86,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	87,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	88,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	89,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	91,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	92,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	92,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	92,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	92,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	92,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	92,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	32,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	93,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	94,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	94,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	6,	95,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	95,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	96,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	6,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	97,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	98,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	99,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	5,	99,	"R/W",	0,	0,	31ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	99,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	100,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	100,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	100,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	4,	100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	100,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	100,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	101,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	4,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	101,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	102,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	4,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	102,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	3,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	103,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	2,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	103,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	103,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	104,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	104,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	3,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_60"              ,	43,	18,	104,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	104,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	104,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	104,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	105,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	105,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	106,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	106,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	107,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	107,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	108,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	108,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	109,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	110,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	1,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	1,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	1,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MWB"                         ,	28,	1,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	113,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	113,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	114,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	114,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	114,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	114,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	114,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	115,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	116,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	117,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	118,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	119,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	120,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	120,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	120,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	120,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	121,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	121,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	121,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	122,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	122,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	122,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	122,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	122,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	122,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	123,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	123,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	123,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	124,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	125,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	126,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	127,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	127,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	127,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	128,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	129,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	129,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	129,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	129,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	130,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	131,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	131,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	131,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	131,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	131,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	132,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	133,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	133,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	133,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	134,	"RAZ",	1,	1,	0,	0},
+	{"PRBS"                        ,	0,	32,	135,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	135,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	135,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	135,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	135,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	136,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	136,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	137,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	137,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	138,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	138,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	138,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	138,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	138,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	138,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	138,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	138,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	138,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	138,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	138,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	139,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW_LSB"                     ,	2,	3,	139,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	139,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	139,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	139,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	139,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	139,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	139,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	139,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	139,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_55_63"              ,	55,	9,	139,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWCNT"                       ,	1,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	3,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	140,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	140,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_FCLKDIS"                ,	17,	1,	140,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	140,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	140,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	141,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	141,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	142,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	142,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_SETTING"               ,	20,	8,	142,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	142,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	142,	"RAZ",	1,	1,	0,	0},
+	{"FCLKCNT"                     ,	0,	64,	143,	"RO",	0,	0,	0ull,	0ull},
+	{"MWB"                         ,	0,	1,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"RPB"                         ,	1,	1,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"MFF"                         ,	2,	1,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQ"                         ,	3,	1,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	144,	"RAZ",	1,	1,	0,	0},
+	{"DFR_ENA"                     ,	0,	1,	145,	"R/W",	0,	0,	0ull,	1ull},
+	{"RECC_ENA"                    ,	1,	1,	145,	"R/W",	0,	0,	0ull,	1ull},
+	{"WECC_ENA"                    ,	2,	1,	145,	"R/W",	0,	0,	0ull,	1ull},
+	{"SBE_ENA"                     ,	3,	1,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	145,	"RAZ",	1,	1,	0,	0},
+	{"SBE_INTENA"                  ,	0,	1,	146,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBE_INTENA"                  ,	1,	1,	146,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	146,	"RAZ",	1,	1,	0,	0},
+	{"SCLKDIS"                     ,	0,	1,	147,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST_START"                  ,	1,	1,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	2,	1,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	147,	"RAZ",	1,	1,	0,	0},
+	{"SBE_ERR"                     ,	0,	1,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE_ERR"                     ,	1,	1,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	148,	"RAZ",	1,	1,	0,	0},
+	{"FADR"                        ,	4,	28,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	32,	10,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	148,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"CWL"                         ,	0,	3,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	150,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	150,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	150,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	150,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	150,	"R/W",	0,	0,	1ull,	1ull},
+	{"PPD"                         ,	24,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	150,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	151,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	152,	"RO",	0,	0,	0ull,	0ull},
+	{"TS_STAGGER"                  ,	0,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	153,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	153,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	153,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	153,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	154,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	155,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	155,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	155,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	155,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	156,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	157,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_53"              ,	12,	42,	157,	"R/W",	1,	1,	0,	0},
+	{"STATUS"                      ,	54,	2,	157,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	157,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D0_R1"                  ,	8,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R0"                  ,	16,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R1"                  ,	24,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R0"                  ,	32,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	159,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	159,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	159,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	159,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	159,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	160,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	160,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	160,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	160,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	160,	"RAZ",	1,	1,	0,	0},
+	{"TCKEON"                      ,	0,	10,	161,	"R/W",	0,	0,	329ull,	0ull},
+	{"TZQCS"                       ,	10,	4,	161,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	161,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	161,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	161,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	161,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	161,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	161,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	161,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	161,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_46_63"              ,	46,	18,	161,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	162,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	162,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	162,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	162,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRFC"                        ,	17,	5,	162,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	162,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	162,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	162,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	162,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	162,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	162,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_46_63"              ,	46,	18,	162,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	163,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	163,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	163,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	164,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	165,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	165,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_44"              ,	10,	35,	165,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	45,	2,	165,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	165,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R0"                  ,	32,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	40,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	48,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	56,	8,	166,	"R/W",	0,	0,	255ull,	255ull},
+	{"BIST"                        ,	0,	37,	167,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	167,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	168,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLK"                         ,	1,	1,	168,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	168,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	169,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	170,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	170,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	171,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	171,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	171,	"RAZ",	1,	1,	0,	0},
+	{"IDLE"                        ,	40,	1,	171,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	171,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	171,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	171,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	172,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	172,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	173,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	174,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	175,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	175,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	175,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	175,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	175,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	175,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	175,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	175,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	175,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	175,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	175,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	175,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	175,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	175,	"R/W",	0,	1,	0ull,	0},
+	{"COMMIT_MODE"                 ,	58,	1,	175,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_59_63"              ,	59,	5,	175,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	176,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	176,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	177,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	4,	177,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	177,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	178,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	178,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	178,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	179,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	179,	"R/W",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	180,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	180,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	180,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	181,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	181,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	181,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	181,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	182,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	183,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	183,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	184,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	184,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	185,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	185,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	186,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	186,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	187,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	187,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	188,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	188,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	188,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_15"              ,	14,	2,	188,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	188,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	1,	188,	"RO",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	188,	"RAZ",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	188,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	189,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	189,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	190,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	190,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	190,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	190,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	190,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	190,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	191,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	192,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	193,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	193,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	193,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	194,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	194,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	195,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	195,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	195,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	196,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	196,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	197,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	198,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	199,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	200,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	200,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	201,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	201,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	201,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	202,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	202,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	202,	"RO",	0,	0,	0ull,	7ull},
+	{"RESERVED_0_1"                ,	0,	2,	203,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	203,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	203,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	203,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	203,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	203,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	203,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	204,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	205,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	205,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	206,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	206,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	206,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	207,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	207,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	1,	207,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	207,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	207,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	207,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	208,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	208,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	209,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	209,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	209,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	209,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	210,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	210,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	210,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	210,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	210,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	210,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	210,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	210,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	210,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	210,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	211,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	212,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	213,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	214,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	215,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	216,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	217,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	217,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	218,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	218,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	218,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	219,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	219,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	220,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	220,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	220,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	221,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	221,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	221,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	221,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	222,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	222,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	223,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	223,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	223,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	223,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	223,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	224,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	224,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	224,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	224,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	224,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	224,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	224,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	225,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	225,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	226,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	226,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	227,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	228,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	228,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	229,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	229,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	230,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	230,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	231,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	231,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	232,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	233,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	233,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	234,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	235,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	235,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	236,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	236,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	237,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	237,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	238,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	238,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	239,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	239,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	240,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	240,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	241,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	241,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	241,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	242,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	242,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	243,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	243,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	244,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	244,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	244,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	244,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	244,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	245,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	246,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	246,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	0,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"START_BIST"                  ,	1,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	247,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	248,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	249,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	249,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	249,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	249,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	249,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	250,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	250,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	251,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	251,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	252,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	252,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	253,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	253,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	253,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	254,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	254,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	255,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	255,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	256,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	256,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	257,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	257,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	257,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	258,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	258,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	259,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	260,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	260,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	261,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	261,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	262,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	262,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	263,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	263,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	264,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	264,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	265,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	265,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	266,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	266,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	272,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	273,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	273,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	274,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	275,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	275,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	276,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	276,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	277,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	277,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	278,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	278,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	279,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	279,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	279,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	280,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	281,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	282,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	282,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	283,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	283,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	284,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	284,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	284,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	284,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	284,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	284,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	285,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	285,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	286,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	286,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	287,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	287,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	288,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	288,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	288,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	288,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	288,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	289,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	289,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	290,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	291,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	291,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	292,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	293,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	293,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	294,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	295,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	296,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	296,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	18,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	19,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	20,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	21,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	22,	1,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	297,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	298,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	298,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	298,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	298,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	299,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	299,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	299,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	300,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	300,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	300,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	301,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	301,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	301,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	302,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	302,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	302,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	302,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	303,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	303,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	303,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	303,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	303,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	304,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	305,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	306,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	307,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	308,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	308,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	308,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	309,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	310,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	311,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	311,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	311,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	311,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	312,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	312,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	312,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	312,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	312,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	313,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	314,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	315,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	315,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	315,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	316,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	316,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	316,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	317,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	318,	"RO",	0,	1,	0ull,	0},
+	{"VPORT"                       ,	6,	6,	318,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	318,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	319,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	319,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	319,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	320,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	321,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	322,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	322,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	323,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	44,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	324,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	326,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	327,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	328,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	328,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	329,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	330,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	330,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	331,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	331,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	332,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	333,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	334,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	334,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	334,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	335,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	335,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	336,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	336,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	337,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	337,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	338,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	338,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	339,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	341,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	341,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	341,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	341,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	341,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	341,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	342,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	342,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	342,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	342,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_44_63"              ,	44,	20,	342,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	343,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	344,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	344,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	344,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	344,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	344,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	344,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	345,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	345,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	346,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	346,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	347,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	8,	348,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	348,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	349,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	349,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	349,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	349,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	350,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	350,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	350,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	351,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	351,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	351,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	352,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	352,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	352,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	353,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	353,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	354,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	354,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	355,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	356,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	357,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	358,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	1,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	359,	"RAZ",	1,	1,	0,	0},
+	{"VRTFL"                       ,	4,	1,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	359,	"RAZ",	1,	1,	0,	0},
+	{"DUTRESFL"                    ,	8,	1,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	359,	"RAZ",	1,	1,	0,	0},
+	{"IOCDATFL"                    ,	12,	1,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	359,	"RAZ",	1,	1,	0,	0},
+	{"IOCCMDFL"                    ,	16,	1,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	359,	"RAZ",	1,	1,	0,	0},
+	{"DUTFL"                       ,	32,	6,	359,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	359,	"RAZ",	1,	1,	0,	0},
+	{"VBFFL"                       ,	0,	4,	360,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	360,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	360,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	360,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	360,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	361,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	361,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	361,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	361,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	362,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	362,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	362,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	363,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	364,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	364,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	364,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	365,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	365,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	366,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	366,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	17,	366,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	366,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	366,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	366,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	366,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	366,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	366,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	367,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	14,	367,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	367,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	367,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	367,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	368,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	368,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	369,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	369,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	4,	369,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_57"              ,	52,	6,	369,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	369,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	370,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_15"               ,	6,	10,	371,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	371,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	371,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	372,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	373,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	2,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	374,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	2,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	374,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	2,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	375,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	376,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	376,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	377,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	378,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	379,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	379,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	379,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	379,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	380,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	380,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	380,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	380,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	380,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	380,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	380,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	380,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	381,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	381,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	382,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	383,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	384,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	385,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	386,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	386,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	386,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	386,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	386,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	387,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	387,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	387,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	387,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	389,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	6,	390,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	390,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	391,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	391,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	392,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	393,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	393,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	393,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	393,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	393,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	394,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	395,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	396,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	397,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	398,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	398,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	398,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	399,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	400,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	400,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	400,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	400,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	400,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	401,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	402,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	402,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	403,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	404,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	404,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	405,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	405,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	405,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	405,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	405,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	405,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	405,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	405,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	405,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	405,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	405,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	405,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	406,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	406,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	406,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	406,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	406,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	406,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	406,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	406,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	406,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	406,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	406,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	407,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	407,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	407,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	407,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	407,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	407,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	407,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	407,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	407,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	407,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	407,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	407,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	407,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	407,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	407,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	407,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_55_63"              ,	55,	9,	407,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	408,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	408,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	408,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	408,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	408,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	408,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	408,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	408,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT"                     ,	0,	64,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"CLKF"                        ,	0,	7,	410,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	410,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	410,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	410,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	410,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	410,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	412,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	412,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	412,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	412,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	413,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	413,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	414,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	414,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	414,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	414,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	414,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	415,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	415,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	415,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	416,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	416,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	417,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	418,	"RO",	0,	0,	0ull,	0ull},
+	{"NXM_WR_ERR"                  ,	0,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	419,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	420,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	420,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	420,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	420,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	421,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	421,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	421,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	421,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	421,	"R/W",	0,	0,	1ull,	1ull},
+	{"PPD"                         ,	24,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	421,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	422,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	423,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"TS_STAGGER"                  ,	0,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	425,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	425,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	425,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	426,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	427,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	427,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	427,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	427,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	428,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	429,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	429,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	429,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	430,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	430,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	430,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	430,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	431,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	431,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	431,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	431,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	431,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	432,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	432,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	432,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	432,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	432,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	433,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	433,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	433,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	433,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	433,	"RAZ",	1,	1,	0,	0},
+	{"TCKEON"                      ,	0,	10,	434,	"R/W",	0,	0,	329ull,	0ull},
+	{"TZQCS"                       ,	10,	4,	434,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	434,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	434,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	434,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	434,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	434,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	434,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	434,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	434,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_46_63"              ,	46,	18,	434,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	435,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	435,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	435,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	435,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	435,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	435,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	435,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	435,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	435,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	435,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	435,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_46_63"              ,	46,	18,	435,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	436,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	436,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	436,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	437,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	437,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	438,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	438,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	439,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	439,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	440,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	440,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	440,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	441,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	441,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	441,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	441,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	441,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	441,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	441,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	441,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	9,	442,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	442,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	443,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	443,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	443,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	444,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	444,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	445,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	445,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	445,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	446,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	446,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	446,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	447,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	447,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	447,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	447,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	447,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	447,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	447,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	447,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	448,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	448,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	449,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	450,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	450,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	450,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	451,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	451,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	451,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	451,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	451,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	452,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	453,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	453,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	453,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	453,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	453,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	453,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	453,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	453,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	453,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	454,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	454,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	454,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	454,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	454,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	454,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	454,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	456,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	456,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	456,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	456,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	456,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	457,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	458,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	458,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	459,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	459,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	6,	460,	"RO",	1,	1,	0,	0},
+	{"RESERVED_6_15"               ,	6,	10,	460,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	460,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	460,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	460,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	460,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	460,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	460,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	460,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	460,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	460,	"RO",	1,	1,	0,	0},
+	{"RESERVED_35_63"              ,	35,	29,	460,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	461,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	461,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	461,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	461,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	461,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	461,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	461,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	461,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	461,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	461,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	461,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	461,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	461,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	461,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	461,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	461,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	461,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	461,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	462,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	462,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	462,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	462,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	463,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	464,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	464,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	464,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	464,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	464,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	464,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	464,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	465,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	466,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	466,	"R/W",	0,	1,	20000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	466,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	466,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	466,	"RO",	0,	0,	1ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	466,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	467,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	467,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	467,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	467,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	468,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	468,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	468,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	468,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	468,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	468,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	469,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	470,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	470,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	471,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	472,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	472,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	472,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	472,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	473,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	473,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	474,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	474,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	475,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	475,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	475,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	476,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	476,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	476,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	476,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	477,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	477,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	478,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	479,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	482,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	483,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	484,	"R/W",	0,	0,	0ull,	0ull},
+	{"RBOOT_PIN"                   ,	0,	1,	485,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	485,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	485,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	485,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	485,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	485,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	485,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	485,	"RO",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	485,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_CLR_BIST"               ,	0,	1,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_5"                ,	2,	4,	486,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	6,	58,	486,	"RO",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	487,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	487,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	487,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	487,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	487,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	487,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	487,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	487,	"RAZ",	1,	1,	0,	0},
+	{"WARM_RST_DLY"                ,	0,	16,	488,	"R/W",	0,	1,	2047ull,	0},
+	{"SOFT_RST_DLY"                ,	16,	16,	488,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	489,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	489,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	490,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	490,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	491,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	491,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	491,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	491,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	491,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	491,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	491,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	491,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	491,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	492,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	492,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	492,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	492,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	492,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	492,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	492,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	492,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	493,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	493,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	494,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	494,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	494,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	495,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	495,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	496,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	496,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	497,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	498,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	498,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	498,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	498,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	498,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	498,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	498,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	499,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	500,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	500,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	501,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	501,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	501,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	501,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	502,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	502,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	502,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	503,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	503,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	503,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	503,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	503,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	503,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	503,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	503,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	503,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	504,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	505,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	505,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	505,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	505,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	505,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	505,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	505,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	505,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	505,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	506,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	506,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	507,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	507,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	508,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	508,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	508,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	508,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	509,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	509,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	510,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	511,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	512,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	512,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	512,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	512,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	513,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	513,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	514,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	515,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	515,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	516,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	516,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	517,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	517,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	518,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	518,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	519,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	519,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	519,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	519,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	519,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	519,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	521,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	521,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	521,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	522,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	523,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	524,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	525,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	525,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	525,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	526,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	526,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	526,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	526,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	527,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	528,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	529,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	530,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	530,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	530,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	530,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	531,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	531,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	531,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	531,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	532,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	532,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	533,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	533,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	533,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	533,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	3,	535,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	535,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	535,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	535,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	536,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	537,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	537,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	538,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	538,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	538,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	539,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	539,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	540,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	540,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	541,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	541,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	541,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	541,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	541,	"R/W",	0,	0,	3ull,	3ull},
+	{"MB_DIS"                      ,	27,	1,	541,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	541,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	542,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	542,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	542,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	542,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	542,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	542,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	542,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	542,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	543,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	543,	"RO/WRSL",	0,	0,	144ull,	144ull},
+	{"ISAE"                        ,	0,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	544,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	544,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	544,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	544,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	545,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	545,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	545,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	545,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	546,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	547,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	547,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	547,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	547,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	548,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	548,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	550,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	551,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	551,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	551,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	551,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	551,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	552,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	552,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	554,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	555,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	555,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	555,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	555,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	556,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	556,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	557,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	558,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	560,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	560,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	561,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	562,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	562,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	563,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	563,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	564,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	564,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	565,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	565,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	565,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	565,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	565,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	566,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	566,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	566,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	566,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	567,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	567,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	567,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	567,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	567,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	568,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	570,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	571,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	571,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	571,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	571,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	571,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	571,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	572,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	572,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	572,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	572,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	572,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	572,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	572,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	572,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	573,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	573,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	573,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	573,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	574,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"MLW"                         ,	4,	6,	574,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	574,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	574,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	574,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	574,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	575,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	575,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	575,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	575,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	575,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	575,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	575,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	576,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	577,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	577,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	578,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	578,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	579,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	580,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	581,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	581,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	581,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	582,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	583,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	584,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	584,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	584,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	585,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	585,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	585,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	586,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	586,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	586,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	586,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	587,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	587,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	587,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	587,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	588,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	588,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	588,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	589,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	589,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	589,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	589,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	590,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	590,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	590,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	595,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	595,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	596,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	597,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	597,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	597,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	597,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	598,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	598,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	598,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	598,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	598,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	599,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	599,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	599,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	599,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	599,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	599,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	599,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	600,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	601,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	601,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	601,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	601,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	601,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	601,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	602,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	602,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	602,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	603,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	606,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	607,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	608,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	609,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	610,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	612,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	612,	"RO/WRSL",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	612,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	612,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	612,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	612,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	612,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	613,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	613,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	613,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	613,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	613,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	614,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	614,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	614,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	614,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	614,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	615,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	615,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	615,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	615,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	616,	"RO/WRSL",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	616,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	616,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	616,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	617,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	617,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	617,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	617,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	618,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	618,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	618,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	621,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	621,	"R/W",	0,	0,	144ull,	144ull},
+	{"ISAE"                        ,	0,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	622,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	622,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	622,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	622,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	622,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	623,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	623,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	624,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	625,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	626,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	628,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	628,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	628,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	628,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	628,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	628,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	629,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	629,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	630,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	630,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	630,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	630,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	634,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	634,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	635,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	636,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	636,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	636,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	637,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	637,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	637,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	637,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	637,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	638,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	638,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	638,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	638,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	639,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	639,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	639,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	639,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	640,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	642,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	643,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	643,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	643,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	643,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	644,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	644,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	644,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	644,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	644,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	645,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	645,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	645,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	645,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	645,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	645,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	645,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	646,	"R/W",	0,	0,	2ull,	2ull},
+	{"MLW"                         ,	4,	6,	646,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	646,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	646,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	646,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	646,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	646,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	646,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	647,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	647,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	647,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	647,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	647,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	647,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	647,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	647,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	647,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	649,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	649,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	649,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	649,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	649,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	649,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	650,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	650,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	651,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	651,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	651,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	651,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	652,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	652,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	653,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	654,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	655,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	655,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	655,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	656,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	657,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	658,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	658,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	659,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	659,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	659,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	660,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	660,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	660,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	661,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	661,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	661,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	661,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	661,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	661,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	661,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	661,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	662,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	662,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	662,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	663,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	663,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	663,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	663,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	664,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	664,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	664,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	664,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	669,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	670,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	671,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	671,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	672,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	672,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	673,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	674,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	674,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	674,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	674,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	675,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	675,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	675,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	675,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	675,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	676,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	676,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	676,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	676,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	676,	"R/W",	0,	0,	15ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	676,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	676,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	677,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	678,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	678,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	678,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	678,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	678,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	678,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	679,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	679,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	679,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	680,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	680,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	683,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	684,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	685,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	686,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	686,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	687,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	687,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	687,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	687,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	688,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	688,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	688,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	688,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	689,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	689,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	689,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	689,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	689,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	689,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	689,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	690,	"R/W",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	690,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	690,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	690,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	690,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	691,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	691,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	691,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	691,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	691,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	692,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	692,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	692,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	692,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	693,	"R/W",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	693,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	693,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	693,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	694,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	694,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	694,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	694,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	695,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	695,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	695,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	698,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	698,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	698,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	698,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	698,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	698,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	698,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	698,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	698,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	699,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	699,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	699,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	699,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	699,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	699,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	700,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	700,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	700,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	700,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	700,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	700,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	700,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	700,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	700,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	701,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	701,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	701,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	701,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	701,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	701,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	702,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	702,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	703,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	704,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	704,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	705,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	705,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	706,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	706,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	706,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	707,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	707,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	707,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	707,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	707,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	707,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	707,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	708,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	708,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	708,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	708,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	708,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	708,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	708,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	709,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	710,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	711,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	711,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	711,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	711,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	711,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	711,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	711,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	712,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	712,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	712,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	712,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	712,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	712,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	712,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	713,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	713,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	713,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	714,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	715,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	715,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	715,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	715,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	715,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	715,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	715,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	715,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	716,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	717,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	717,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	717,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	717,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	717,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	718,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	718,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	718,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	718,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	718,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	718,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	718,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	718,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	719,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	719,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	720,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	720,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	720,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	721,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	721,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	722,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	722,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	723,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	723,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	723,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	723,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	724,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	724,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	724,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	724,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	724,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	725,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	725,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	726,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	726,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	726,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	726,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	726,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	727,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	727,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	727,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	727,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	727,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	727,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	727,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	728,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	729,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	729,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	729,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	729,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	729,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	730,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	730,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	730,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	730,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	731,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	731,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	731,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	731,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	732,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	733,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	734,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	734,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	735,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	735,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	736,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	737,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	737,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	737,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	737,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	737,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	737,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	737,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	738,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	739,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	740,	"RO",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	741,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	741,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	742,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	742,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	743,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	743,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	743,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	744,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	745,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	746,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	746,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	747,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	747,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	748,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	748,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"SLI_P"                       ,	0,	8,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	749,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_P"                       ,	24,	8,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_NP"                      ,	32,	8,	749,	"R/W",	0,	0,	16ull,	16ull},
+	{"PEM_CPL"                     ,	40,	8,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	749,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	749,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	750,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	750,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	750,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	750,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	750,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	751,	"RAZ",	1,	1,	0,	0},
+	{"CLKEN"                       ,	0,	1,	752,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	752,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	753,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	756,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	756,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	756,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	757,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	757,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	757,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	757,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	758,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	758,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	758,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	758,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	758,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	758,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	758,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	759,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	759,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	759,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	759,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	760,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	761,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	761,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	762,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	763,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	763,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	763,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	763,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	763,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	763,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	763,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	763,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	764,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	765,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	766,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	766,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	767,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	767,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	767,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	767,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	767,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	768,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	769,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	769,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	770,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	770,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	771,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	771,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	772,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	772,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	773,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	773,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	774,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	774,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	775,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	775,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	776,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	776,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	777,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	777,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	779,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	780,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	780,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	781,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	781,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	782,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	782,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	783,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	783,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	784,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	785,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	785,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	786,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	786,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	787,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	787,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	787,	"RO",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	788,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	788,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	789,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	789,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	790,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	790,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	791,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	791,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	792,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	792,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	793,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	793,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	794,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	795,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	795,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	797,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	32,	798,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	799,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	799,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	800,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	800,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	800,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	800,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	801,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	801,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	801,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	801,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	802,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	802,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	802,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	802,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	803,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	803,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	803,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	803,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	804,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	804,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	804,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	804,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	805,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	805,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	805,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	805,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	805,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	806,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	807,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	807,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	807,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	807,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	807,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	808,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	809,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	809,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	809,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	809,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	809,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	809,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	809,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	809,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	810,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	810,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	810,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	810,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	810,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	810,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	811,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	811,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	811,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	811,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	811,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	811,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	811,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	811,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	812,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	812,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	812,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	812,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	812,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	812,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	813,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	813,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	813,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	813,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	814,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	814,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	814,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	814,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	815,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	815,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	815,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	815,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	815,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	815,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	815,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	816,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	816,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	816,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	816,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	816,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	817,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	817,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	817,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	817,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	817,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	818,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	818,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	818,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	818,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	819,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	819,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	819,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	819,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	819,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	819,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	819,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	819,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	819,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	820,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	820,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	820,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	820,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	820,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	821,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	821,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	821,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	821,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	822,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	823,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	825,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	826,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	827,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_48_63"              ,	48,	16,	827,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	12,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	828,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	829,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	830,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	830,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	831,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	831,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	832,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	833,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	834,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	834,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	835,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	836,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	836,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	837,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	6,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	837,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	838,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	838,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	839,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	839,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	839,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	839,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	839,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	839,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	839,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	839,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	839,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	839,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	839,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	840,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	840,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	841,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	841,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	842,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	842,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	843,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	843,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	844,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	844,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	845,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	845,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	11,	846,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	846,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	847,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	847,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	848,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	848,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	849,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	849,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	849,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	850,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	850,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	850,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	850,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	850,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	10,	851,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	851,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	10,	851,	"R/W",	0,	1,	1023ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	851,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	11,	851,	"RO",	0,	1,	1011ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	851,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	11,	851,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	851,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	11,	851,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	851,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	852,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	852,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	853,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	853,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	854,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	854,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	855,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	855,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	855,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	11,	856,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	856,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	11,	856,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	856,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	856,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	856,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	857,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	857,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	857,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	857,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	857,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	10,	858,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	858,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	10,	858,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	858,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	858,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	858,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	858,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	859,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	859,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	860,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	861,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	862,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	863,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	863,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	863,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	863,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	863,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	864,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	864,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	864,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	864,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	864,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	865,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	865,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	865,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	866,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	866,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	866,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	866,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	866,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	866,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	866,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	866,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	866,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	866,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	867,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	868,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	868,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	868,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	869,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	869,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	869,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	869,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	869,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	869,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	869,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	870,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	870,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	871,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	872,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	873,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	874,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	874,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	874,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	874,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	874,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	874,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	874,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	874,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	874,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	874,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	874,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	874,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	874,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	874,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	874,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	874,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	874,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	874,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	875,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	875,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	875,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	876,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	876,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	877,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	877,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	877,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	878,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	878,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	878,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	878,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	878,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	878,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	878,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	879,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	879,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	880,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	881,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	881,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	882,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	883,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	883,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	884,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	884,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	885,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	886,	"WO",	0,	0,	0ull,	0ull},
+	{"NCB_CMD"                     ,	0,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	887,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	887,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	887,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	887,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	888,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	888,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	888,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	888,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	888,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	888,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	888,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	888,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	888,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	888,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	888,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	889,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	889,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	889,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	889,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	890,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	890,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	890,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	890,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	890,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	891,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	891,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	891,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	892,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	892,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	893,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	893,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	894,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	894,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	895,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	896,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	898,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	898,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	898,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	898,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	898,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	899,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	900,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	901,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	901,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	901,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_48_63"              ,	48,	16,	901,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	902,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	902,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	903,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	903,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	903,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	903,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	903,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	903,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	903,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	904,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	905,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	906,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	907,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	908,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	911,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	912,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	912,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	912,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	914,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	916,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	917,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	919,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	920,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	921,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	921,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	921,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	922,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	922,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	923,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	923,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	923,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	924,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	924,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	924,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	925,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	925,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	925,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	926,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	927,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	928,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	928,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	929,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	930,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	930,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	930,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	930,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	930,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	931,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	931,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	931,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	931,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	931,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	932,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	932,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	932,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	933,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	933,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	934,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	934,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	935,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	935,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	936,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	936,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	937,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	937,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	938,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	938,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	938,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	939,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	940,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	940,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	941,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	942,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	942,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	943,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	943,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	944,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	944,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	945,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	945,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	946,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	947,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	947,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	947,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	947,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	947,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	948,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	948,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	949,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	950,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	950,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	951,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	951,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	951,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	952,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	952,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	953,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	953,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	954,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	954,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	955,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	955,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	956,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	957,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	957,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	958,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	959,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	959,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	960,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	960,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	961,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	961,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	962,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	962,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	963,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	963,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	964,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	965,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	966,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	966,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	966,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	966,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	967,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	967,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	967,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	967,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	967,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	967,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	967,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	967,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	968,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	968,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	968,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	968,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	968,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	969,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	969,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	969,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	969,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	970,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	971,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	971,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	971,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	971,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	972,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	973,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	973,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	974,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	974,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	975,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	975,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	975,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	975,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	975,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	975,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	975,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	976,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	976,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	976,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	976,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	976,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	976,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	977,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	977,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	978,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	978,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	978,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	978,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	979,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	979,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	979,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	979,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	980,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	980,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	980,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	980,	"RAZ",	1,	1,	0,	0},
+	{"DENY_BAR0"                   ,	0,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR1"                   ,	1,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR2"                   ,	2,	1,	981,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	981,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	982,	"R/W",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	982,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	982,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	983,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_REV"                    ,	16,	16,	983,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	983,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	984,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	984,	"RAZ",	1,	1,	0,	0},
+	{"OMSG"                        ,	0,	7,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"IMSG"                        ,	7,	5,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF"                       ,	12,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"TXBUF"                       ,	14,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"OSPF"                        ,	16,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"ISPF"                        ,	17,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB"                        ,	18,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_23"              ,	20,	4,	985,	"RAZ",	1,	1,	0,	0},
+	{"OPTRS"                       ,	24,	4,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"OBULK"                       ,	28,	4,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"RTN"                         ,	32,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"OFREE"                       ,	34,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"ITAG"                        ,	35,	1,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"OTAG"                        ,	36,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"BELL"                        ,	38,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"CRAM"                        ,	40,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"MRAM"                        ,	42,	2,	985,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	985,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	986,	"R/W",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	4,	4,	986,	"R/W",	0,	1,	0ull,	0},
+	{"LTTR"                        ,	8,	4,	986,	"R/W",	0,	1,	0ull,	0},
+	{"PRT_SEL"                     ,	12,	3,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	986,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	16,	2,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	18,	1,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	19,	2,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	21,	1,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	986,	"RAZ",	1,	1,	0,	0},
+	{"RSP_THR"                     ,	24,	6,	986,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	986,	"RAZ",	1,	1,	0,	0},
+	{"TO_MODE"                     ,	31,	1,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	986,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	0,	32,	987,	"R/W",	0,	1,	0ull,	0},
+	{"TT"                          ,	32,	2,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RS"                          ,	34,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_41"              ,	35,	7,	987,	"RAZ",	1,	1,	0,	0},
+	{"NTAG"                        ,	42,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	43,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	44,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	45,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	987,	"RAZ",	1,	1,	0,	0},
+	{"SL"                          ,	48,	7,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	987,	"RAZ",	1,	1,	0,	0},
+	{"PM"                          ,	56,	2,	987,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_62"              ,	58,	5,	987,	"RAZ",	1,	1,	0,	0},
+	{"R"                           ,	63,	1,	987,	"R/W",	0,	1,	0ull,	0},
+	{"GRP0"                        ,	0,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS0"                        ,	4,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP1"                        ,	8,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1"                        ,	12,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP2"                        ,	16,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2"                        ,	20,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP3"                        ,	24,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3"                        ,	28,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_31_31"              ,	31,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP4"                        ,	32,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4"                        ,	36,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_39"              ,	39,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP5"                        ,	40,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5"                        ,	44,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP6"                        ,	48,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6"                        ,	52,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"GRP7"                        ,	56,	4,	988,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7"                        ,	60,	3,	988,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_63_63"              ,	63,	1,	988,	"RAZ",	1,	1,	0,	0},
+	{"SID0"                        ,	0,	16,	989,	"RO",	0,	1,	0ull,	0},
+	{"LTTR0"                       ,	16,	2,	989,	"RO",	0,	1,	0ull,	0},
+	{"MBOX0"                       ,	18,	2,	989,	"RO",	0,	1,	0ull,	0},
+	{"SEG0"                        ,	20,	4,	989,	"RO",	0,	1,	0ull,	0},
+	{"DIS0"                        ,	24,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TT0"                         ,	25,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_26"              ,	26,	1,	989,	"RAZ",	1,	1,	0,	0},
+	{"PRT0"                        ,	27,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TOC0"                        ,	28,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TOE0"                        ,	29,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"ERR0"                        ,	30,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"VAL0"                        ,	31,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"SID1"                        ,	32,	16,	989,	"RO",	0,	1,	0ull,	0},
+	{"LTTR1"                       ,	48,	2,	989,	"RO",	0,	1,	0ull,	0},
+	{"MBOX1"                       ,	50,	2,	989,	"RO",	0,	1,	0ull,	0},
+	{"SEG1"                        ,	52,	4,	989,	"RO",	0,	1,	0ull,	0},
+	{"DIS1"                        ,	56,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TT1"                         ,	57,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_58"              ,	58,	1,	989,	"RAZ",	1,	1,	0,	0},
+	{"PRT1"                        ,	59,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TOC1"                        ,	60,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"TOE1"                        ,	61,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"ERR1"                        ,	62,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"VAL1"                        ,	63,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"MAX_P0"                      ,	0,	6,	990,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	990,	"RAZ",	1,	1,	0,	0},
+	{"MAX_P1"                      ,	8,	6,	990,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	990,	"RAZ",	1,	1,	0,	0},
+	{"BUF_THR"                     ,	16,	4,	990,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	990,	"RAZ",	1,	1,	0,	0},
+	{"SP_VPORT"                    ,	31,	1,	990,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_S0"                      ,	32,	6,	990,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	990,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S1"                      ,	40,	6,	990,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	990,	"RAZ",	1,	1,	0,	0},
+	{"MAX_TOT"                     ,	48,	6,	990,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	990,	"RAZ",	1,	1,	0,	0},
+	{"TXBELL"                      ,	0,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"BELL_ERR"                    ,	1,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBELL"                      ,	2,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAINT_OP"                    ,	3,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR_ERR"                     ,	4,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"DENY_WR"                     ,	5,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLI_ERR"                     ,	6,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"WR_DONE"                     ,	7,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"MCE_RX"                      ,	9,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_TX"                     ,	10,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_RX"                     ,	11,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"LOG_ERB"                     ,	12,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"PHY_ERB"                     ,	13,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_DWN"                    ,	14,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_UP"                     ,	15,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG0"                       ,	16,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG1"                       ,	17,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG_ERR"                    ,	18,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO_ERR"                     ,	19,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"RTRY_ERR"                    ,	20,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"F_ERROR"                     ,	21,	1,	991,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	991,	"RAZ",	1,	1,	0,	0},
+	{"BE1"                         ,	0,	8,	992,	"RO",	0,	1,	0ull,	0},
+	{"BE0"                         ,	8,	8,	992,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_28"              ,	16,	13,	992,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	29,	3,	992,	"RO",	0,	1,	0ull,	0},
+	{"LENGTH"                      ,	32,	10,	992,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	992,	"RO",	1,	1,	0,	0},
+	{"TAG"                         ,	48,	8,	992,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	992,	"RO",	0,	1,	0ull,	0},
+	{"CMD"                         ,	60,	4,	992,	"RO",	0,	1,	0ull,	0},
+	{"INFO1"                       ,	0,	64,	993,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"LNS"                         ,	1,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"RSRVD"                       ,	2,	30,	994,	"RO",	0,	1,	0ull,	0},
+	{"LETTER"                      ,	32,	2,	994,	"RO",	0,	1,	0ull,	0},
+	{"MBOX"                        ,	34,	2,	994,	"RO",	0,	1,	0ull,	0},
+	{"XMBOX"                       ,	36,	4,	994,	"RO",	0,	1,	0ull,	0},
+	{"DID"                         ,	40,	16,	994,	"RO",	0,	1,	0ull,	0},
+	{"SSIZE"                       ,	56,	4,	994,	"RO",	0,	1,	0ull,	0},
+	{"SIS"                         ,	60,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	61,	1,	994,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	994,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_7"                ,	0,	8,	995,	"RAZ",	1,	1,	0,	0},
+	{"OTHER"                       ,	8,	48,	995,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	995,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	60,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	995,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BELL_ERR"                    ,	1,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBELL"                      ,	2,	1,	996,	"RO",	0,	0,	0ull,	0ull},
+	{"MAINT_OP"                    ,	3,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR_ERR"                     ,	4,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DENY_WR"                     ,	5,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI_ERR"                     ,	6,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WR_DONE"                     ,	7,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_RX"                      ,	9,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_TX"                     ,	10,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_RX"                     ,	11,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOG_ERB"                     ,	12,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_ERB"                     ,	13,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_DWN"                    ,	14,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_UP"                     ,	15,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG0"                       ,	16,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG1"                       ,	17,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG_ERR"                    ,	18,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_ERR"                     ,	19,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTRY_ERR"                    ,	20,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"F_ERROR"                     ,	21,	1,	996,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	996,	"RAZ",	1,	1,	0,	0},
+	{"RX_POL"                      ,	0,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_POL"                      ,	4,	4,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_WIDTH"                    ,	8,	2,	997,	"R/W",	0,	0,	2ull,	2ull},
+	{"TX_FLOW"                     ,	10,	1,	997,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	997,	"RAZ",	1,	1,	0,	0},
+	{"A50"                         ,	12,	1,	997,	"R/W",	0,	0,	1ull,	1ull},
+	{"A66"                         ,	13,	1,	997,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	997,	"RAZ",	1,	1,	0,	0},
+	{"OPS"                         ,	32,	32,	997,	"R/W",	0,	0,	64756ull,	64756ull},
+	{"ADDR"                        ,	0,	24,	998,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	24,	1,	998,	"R/W",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	25,	1,	998,	"RO",	0,	1,	0ull,	0},
+	{"FAIL"                        ,	26,	1,	998,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	998,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	32,	32,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DATA"                     ,	0,	32,	999,	"RO",	0,	1,	0ull,	0},
+	{"VALID"                       ,	32,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	999,	"RAZ",	1,	1,	0,	0},
+	{"MCE"                         ,	0,	1,	1000,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1000,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1001,	"RAZ",	1,	1,	0,	0},
+	{"W_RO"                        ,	8,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RR_RO"                       ,	9,	1,	1001,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1001,	"RAZ",	1,	1,	0,	0},
+	{"LTTR_MP"                     ,	0,	4,	1002,	"R/W",	0,	1,	15ull,	0},
+	{"LTTR_SP"                     ,	4,	4,	1002,	"R/W",	0,	1,	15ull,	0},
+	{"IDM_DID"                     ,	8,	1,	1002,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_SIS"                     ,	9,	1,	1002,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_TT"                      ,	10,	1,	1002,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_11_14"              ,	11,	4,	1002,	"RAZ",	1,	1,	0,	0},
+	{"RTRY_EN"                     ,	15,	1,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"RTRY_THR"                    ,	16,	16,	1002,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_62"              ,	32,	31,	1002,	"RAZ",	1,	1,	0,	0},
+	{"TESTMODE"                    ,	63,	1,	1002,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_PSD"                     ,	0,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1003,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1003,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_NMP"                     ,	1,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_4"                ,	4,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX_NMP"                    ,	5,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1004,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID_NMP"                      ,	9,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1004,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1004,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	2,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_30"               ,	2,	29,	1005,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	31,	1,	1005,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1005,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"XMBOX_SP"                    ,	15,	1,	1006,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1006,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1007,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"DEST_ID"                     ,	4,	1,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1007,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	8,	8,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	16,	16,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1007,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1007,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1008,	"RO",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	32,	8,	1008,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1008,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1009,	"RO",	0,	1,	128ull,	0},
+	{"N_POST"                      ,	8,	5,	1009,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1009,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1009,	"RO",	0,	1,	128ull,	0},
+	{"MBOX"                        ,	24,	4,	1009,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_28_39"              ,	28,	12,	1009,	"RAZ",	1,	1,	0,	0},
+	{"RTN_PR1"                     ,	40,	8,	1009,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR2"                     ,	48,	8,	1009,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR3"                     ,	56,	8,	1009,	"RO",	0,	1,	0ull,	0},
+	{"IAOW_SEL"                    ,	0,	2,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	1010,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	4,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	5,	1,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1010,	"RAZ",	1,	1,	0,	0},
+	{"RD_PRIOR"                    ,	8,	2,	1010,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_PRIOR"                    ,	10,	2,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_OP"                       ,	12,	3,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1010,	"RAZ",	1,	1,	0,	0},
+	{"WR_OP"                       ,	16,	3,	1010,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1010,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1011,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1011,	"RAZ",	1,	1,	0,	0},
+	{"SRIO"                        ,	0,	1,	1012,	"RO",	1,	1,	0,	0},
+	{"ACCESS"                      ,	1,	1,	1012,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	1012,	"RAZ",	1,	1,	0,	0},
+	{"ITAG"                        ,	0,	5,	1013,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1013,	"RAZ",	1,	1,	0,	0},
+	{"OTAG"                        ,	8,	5,	1013,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1013,	"RAZ",	1,	1,	0,	0},
+	{"O_CLR"                       ,	16,	1,	1013,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1013,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1014,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_POST"                      ,	8,	5,	1014,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_13_15"              ,	13,	3,	1014,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1014,	"R/W",	0,	0,	128ull,	128ull},
+	{"MBOX"                        ,	24,	4,	1014,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_28_63"              ,	28,	36,	1014,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1015,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1015,	"RAZ",	1,	1,	0,	0},
+	{"PENDING"                     ,	8,	1,	1015,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1015,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1015,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1016,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	5,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"ERROR"                       ,	6,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	7,	1,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1016,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1016,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1016,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH0"                      ,	0,	4,	1017,	"R/W",	0,	0,	6ull,	3ull},
+	{"RESERVED_4_7"                ,	4,	4,	1017,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH1"                      ,	8,	4,	1017,	"R/W",	0,	0,	4ull,	2ull},
+	{"RESERVED_12_15"              ,	12,	4,	1017,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH2"                      ,	16,	4,	1017,	"R/W",	0,	0,	2ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1017,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH0"                     ,	32,	5,	1017,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_37_39"              ,	37,	3,	1017,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH1"                     ,	40,	5,	1017,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_45_47"              ,	45,	3,	1017,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH2"                     ,	48,	5,	1017,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_53_63"              ,	53,	11,	1017,	"RAZ",	1,	1,	0,	0},
+	{"S2M_PR0"                     ,	0,	8,	1018,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR1"                     ,	8,	8,	1018,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR2"                     ,	16,	8,	1018,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR3"                     ,	24,	8,	1018,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1018,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1019,	"RO",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1019,	"RO",	0,	0,	0ull,	0ull},
+	{"EXT_FPTR"                    ,	0,	16,	1020,	"RO",	0,	0,	256ull,	256ull},
+	{"ASSY_REV"                    ,	16,	16,	1020,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_2"                ,	1,	2,	1021,	"RAZ",	1,	1,	0,	0},
+	{"NCA"                         ,	3,	1,	1021,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	4,	2,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1021,	"RAZ",	1,	1,	0,	0},
+	{"LA"                          ,	8,	22,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1021,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	0,	1,	1022,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1022,	"RAZ",	1,	1,	0,	0},
+	{"COMP_TAG"                    ,	0,	32,	1023,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEMORY"                      ,	0,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
+	{"DOORBELL"                    ,	1,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG0"                       ,	2,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG1"                       ,	3,	1,	1024,	"R/W",	0,	0,	0ull,	1ull},
+	{"HALT"                        ,	4,	1,	1024,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	1024,	"RAZ",	1,	1,	0,	0},
+	{"VENDOR"                      ,	0,	16,	1025,	"RO",	0,	0,	140ull,	140ull},
+	{"DEVICE"                      ,	16,	16,	1025,	"RO",	0,	1,	144ull,	0},
+	{"REVISION"                    ,	0,	8,	1026,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_31"               ,	8,	24,	1026,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1027,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1027,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1027,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	0,	1,	1028,	"R/W0C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_23"               ,	1,	23,	1028,	"RAZ",	1,	1,	0,	0},
+	{"ERR_TYPE"                    ,	24,	5,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"INF_TYPE"                    ,	29,	3,	1028,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_TOUT"                    ,	0,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_16"               ,	6,	11,	1029,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	17,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RATE_CNT"                    ,	0,	8,	1030,	"R/W",	0,	1,	0ull,	0},
+	{"PK_RATE"                     ,	8,	8,	1030,	"R/W",	0,	1,	0ull,	0},
+	{"RATE_LIM"                    ,	16,	2,	1030,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	1030,	"RAZ",	1,	1,	0,	0},
+	{"ERR_BIAS"                    ,	24,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
+	{"LNK_TOUT"                    ,	0,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_16"               ,	6,	11,	1031,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	17,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1032,	"RAZ",	1,	1,	0,	0},
+	{"DGRAD_TH"                    ,	16,	8,	1032,	"R/W",	0,	0,	255ull,	128ull},
+	{"FAIL_TH"                     ,	24,	8,	1032,	"R/W",	0,	0,	255ull,	255ull},
+	{"EF_ID"                       ,	0,	16,	1033,	"RO",	0,	0,	7ull,	7ull},
+	{"EF_PTR"                      ,	16,	16,	1033,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	32,	1034,	"R/W",	0,	0,	0ull,	0ull},
+	{"XADDR"                       ,	0,	2,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1035,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	29,	1035,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPT_IDX"                    ,	0,	5,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDPTR"                       ,	6,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"TT"                          ,	7,	1,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	8,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	12,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRA"                       ,	16,	8,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTYPE"                       ,	24,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"FTYPE"                       ,	28,	4,	1036,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_14"               ,	0,	15,	1037,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	15,	1,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID8"                         ,	16,	8,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID16"                        ,	24,	8,	1037,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID8"                     ,	0,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID16"                    ,	8,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID8"                     ,	16,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID16"                    ,	24,	8,	1038,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1040,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1042,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1043,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1044,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOSTID"                      ,	0,	16,	1045,	"R/W",	0,	0,	65535ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1045,	"RAZ",	1,	1,	0,	0},
+	{"RX_SYNC"                     ,	0,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_SYNC"                     ,	1,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FLOW"                     ,	2,	1,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_19"               ,	3,	17,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_WM2"                      ,	20,	4,	1046,	"R/W",	0,	0,	2ull,	1ull},
+	{"TX_WM1"                      ,	24,	4,	1046,	"R/W",	0,	0,	3ull,	2ull},
+	{"TX_WM0"                      ,	28,	4,	1046,	"R/W",	0,	0,	4ull,	3ull},
+	{"PD_CTRL"                     ,	0,	32,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"LN0_DIS"                     ,	0,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN0_RX"                      ,	1,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_DIS"                     ,	4,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_RX"                      ,	5,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_DIS"                     ,	8,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_RX"                      ,	9,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_DIS"                     ,	12,	1,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_RX"                      ,	13,	3,	1048,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1048,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_26"               ,	0,	27,	1049,	"RAZ",	1,	1,	0,	0},
+	{"LOOPBACK"                    ,	27,	2,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_RESET"                    ,	30,	1,	1049,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_RESET"                    ,	31,	1,	1049,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_SM"                     ,	0,	10,	1050,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_31"              ,	10,	22,	1050,	"RAZ",	1,	1,	0,	0},
+	{"OVERWRT"                     ,	0,	1,	1051,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1051,	"RAZ",	1,	1,	0,	0},
+	{"PKT_DATA"                    ,	0,	32,	1052,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1053,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1053,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1053,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1053,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1053,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1054,	"RAZ",	1,	1,	0,	0},
+	{"OCTETS"                      ,	16,	16,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_DATA"                    ,	0,	32,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1056,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1056,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1056,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1056,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1056,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUSN"                     ,	0,	3,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS1"                     ,	3,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_5"                ,	4,	2,	1057,	"RAZ",	1,	1,	0,	0},
+	{"XTRAIN"                      ,	6,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"XSYNC"                       ,	7,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"DEC_ERR"                     ,	8,	4,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TRAIN"                    ,	12,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SYNC"                     ,	13,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ADAPT"                    ,	14,	1,	1057,	"RO",	0,	0,	1ull,	1ull},
+	{"RX_INV"                      ,	15,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TYPE"                     ,	16,	2,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_MODE"                     ,	18,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_TYPE"                     ,	19,	1,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"LANE"                        ,	20,	4,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	24,	8,	1057,	"RO",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	0,	31,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1058,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_20"               ,	0,	21,	1059,	"R/W",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	21,	11,	1059,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_13"               ,	3,	11,	1061,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	14,	18,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"BARSIZE"                     ,	3,	3,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_19"               ,	6,	14,	1063,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	20,	12,	1063,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAX"                         ,	3,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"ESX"                         ,	4,	2,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1064,	"RAZ",	1,	1,	0,	0},
+	{"ADDR48"                      ,	9,	7,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1065,	"RO",	0,	0,	7ull,	7ull},
+	{"EX_FEAT"                     ,	3,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
+	{"LG_TRAN"                     ,	4,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
+	{"CRF"                         ,	5,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	6,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	1065,	"RAZ",	1,	1,	0,	0},
+	{"MULT_PRT"                    ,	27,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
+	{"SWITCHF"                     ,	28,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
+	{"PROC"                        ,	29,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
+	{"MEMORY"                      ,	30,	1,	1065,	"RO",	0,	0,	1ull,	1ull},
+	{"BRIDGE"                      ,	31,	1,	1065,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1066,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_31"               ,	3,	29,	1066,	"RAZ",	1,	1,	0,	0},
+	{"PT_TYPE"                     ,	0,	1,	1067,	"RO",	0,	0,	1ull,	1ull},
+	{"PRT_LOCK"                    ,	1,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"DROP_PKT"                    ,	2,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"STP_PORT"                    ,	3,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	4,	8,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_STAT"                     ,	12,	2,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_WIDTH"                    ,	14,	2,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	1067,	"RAZ",	1,	1,	0,	0},
+	{"ENUMB"                       ,	17,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_18"              ,	18,	1,	1067,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	19,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_ERR"                     ,	20,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"I_ENABLE"                    ,	21,	1,	1067,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ENABLE"                    ,	22,	1,	1067,	"R/W",	0,	0,	0ull,	1ull},
+	{"DISABLE"                     ,	23,	1,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"OV_WIDTH"                    ,	24,	3,	1067,	"R/W",	0,	0,	0ull,	0ull},
+	{"IT_WIDTH"                    ,	27,	3,	1067,	"RO",	0,	1,	0ull,	0},
+	{"PT_WIDTH"                    ,	30,	2,	1067,	"RO",	0,	0,	2ull,	2ull},
+	{"EMPH_EN"                     ,	0,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EMPH"                     ,	1,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB_625G"                    ,	16,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUP_625G"                    ,	17,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
+	{"ENB_500G"                    ,	18,	1,	1068,	"R/W",	1,	1,	0,	0},
+	{"SUB_500G"                    ,	19,	1,	1068,	"RO",	1,	1,	0,	0},
+	{"ENB_312G"                    ,	20,	1,	1068,	"R/W",	1,	1,	0,	0},
+	{"SUP_312G"                    ,	21,	1,	1068,	"RO",	1,	1,	0,	0},
+	{"ENB_250G"                    ,	22,	1,	1068,	"R/W",	1,	1,	0,	0},
+	{"SUP_250G"                    ,	23,	1,	1068,	"RO",	1,	1,	0,	0},
+	{"ENB_125G"                    ,	24,	1,	1068,	"R/W",	1,	1,	0,	0},
+	{"SUP_125G"                    ,	25,	1,	1068,	"RO",	1,	1,	0,	0},
+	{"BAUD_ENB"                    ,	26,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAUD_SUP"                    ,	27,	1,	1068,	"RO",	0,	0,	0ull,	0ull},
+	{"SEL_BAUD"                    ,	28,	4,	1068,	"RO",	0,	1,	0ull,	0},
+	{"PT_UINIT"                    ,	0,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"PT_OK"                       ,	1,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"PT_ERROR"                    ,	2,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1069,	"RAZ",	1,	1,	0,	0},
+	{"PT_WRITE"                    ,	4,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1069,	"RAZ",	1,	1,	0,	0},
+	{"I_SM_ERR"                    ,	8,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"I_ERROR"                     ,	9,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I_SM_RET"                    ,	10,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1069,	"RAZ",	1,	1,	0,	0},
+	{"O_SM_ERR"                    ,	16,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"O_ERROR"                     ,	17,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_SM_RET"                    ,	18,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RTRIED"                    ,	19,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RETRY"                     ,	20,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1069,	"RAZ",	1,	1,	0,	0},
+	{"O_DGRAD"                     ,	24,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_FAIL"                      ,	25,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKT_DROP"                    ,	26,	1,	1069,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	1069,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_28"               ,	0,	29,	1070,	"RAZ",	1,	1,	0,	0},
+	{"DISCOVER"                    ,	29,	1,	1070,	"R/W",	0,	0,	0ull,	1ull},
+	{"MENABLE"                     ,	30,	1,	1070,	"R/W",	1,	0,	0,	1ull},
+	{"HOST"                        ,	31,	1,	1070,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1071,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1071,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"EF_ID"                       ,	0,	16,	1072,	"RO",	0,	0,	1ull,	0ull},
+	{"EF_PTR"                      ,	16,	16,	1072,	"RO",	0,	0,	4096ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1073,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1073,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"ID16"                        ,	0,	16,	1074,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1074,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1074,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE16"                    ,	0,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE8"                     ,	1,	1,	1075,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	1075,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	0,	16,	1076,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1076,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1076,	"RAZ",	1,	1,	0,	0},
+	{"EF_ID"                       ,	0,	16,	1077,	"RO",	0,	0,	13ull,	13ull},
+	{"EF_PTR"                      ,	16,	16,	1077,	"RO",	0,	0,	8192ull,	0ull},
+	{"RESERVED_0_1"                ,	0,	2,	1078,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1078,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1078,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1078,	"RO",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	0,	22,	1079,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1079,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1079,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1079,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1079,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1079,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1080,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1080,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1080,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1081,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1081,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1081,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1081,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1081,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1082,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1083,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1084,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1084,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1084,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1084,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1085,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1085,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1086,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1086,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1086,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1087,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1088,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1089,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1090,	"R/W",	0,	0,	0ull,	0ull},
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+	{"POW"                         ,	12,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
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+	{"RAD"                         ,	14,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1096,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1096,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1096,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1096,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
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+	{"DWB"                         ,	19,	1,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1097,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
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+	{"MCD0_TRG"                    ,	2,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1098,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1098,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	1099,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1100,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1100,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1101,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1102,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1102,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"STT"                         ,	17,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"WBIL2I"                      ,	24,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1102,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"LCKL2"                       ,	31,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBST8"                      ,	36,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBST64"                     ,	39,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"CLR8"                        ,	44,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"CLR32"                       ,	46,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"INCR8"                       ,	48,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"INCR32"                      ,	50,	1,	1102,	"R/W",	0,	0,	0ull,	1ull},
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+	{"MIO"                         ,	0,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1103,	"R/W",	0,	0,	0ull,	3ull},
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+	{"ILLEGAL2"                    ,	11,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
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+	{"USB0"                        ,	13,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1103,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1103,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1103,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1103,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1104,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_20_63"              ,	20,	44,	1104,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1105,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1105,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1106,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAA32"                       ,	58,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAA64"                       ,	59,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1107,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1108,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1108,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1108,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1108,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1108,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1110,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1110,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1111,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1112,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1113,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1113,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1114,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1114,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1114,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1115,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1115,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1115,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1115,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1115,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1116,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1116,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1116,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1118,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1119,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1121,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1122,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1122,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1123,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1123,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1123,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1123,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1124,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1124,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1124,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1125,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1125,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1126,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1126,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1126,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1126,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1127,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1127,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1128,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1129,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1129,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1130,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1130,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1131,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1132,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1133,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1133,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1134,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1134,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1134,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1135,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1135,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1136,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1136,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1136,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1137,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1138,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1138,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1139,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1140,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1141,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1142,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1143,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1144,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1144,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1145,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1145,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1145,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1145,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1145,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1145,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1145,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1146,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1147,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1147,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1147,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1148,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1148,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1148,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1148,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1148,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1148,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1151,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1152,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1152,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1152,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1152,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1152,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1152,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1152,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1153,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1153,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1153,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1153,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1154,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1154,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1155,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1155,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1156,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1156,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1157,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1158,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1158,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1159,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1159,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1159,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1159,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1159,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1160,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1160,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1161,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1161,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1162,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1162,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1163,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1163,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1163,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1163,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXRISETUNE"                  ,	26,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1163,	"R/W",	0,	0,	5ull,	5ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1163,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1163,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1163,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1164,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	39,	1164,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1164,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1165,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1166,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1166,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1167,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1167,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1167,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1167,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1167,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	1167,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1168,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1169,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1169,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1170,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1171,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1171,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	13,	16},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	11,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	14,	54},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	68},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	70},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	72},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	21,	74},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	21,	95},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	116},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	118},
+	{"cvmx_agl_gmx_rx#_rx_inbnd"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	4,	120},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	130},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	132},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	134},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	136},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	138},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	140},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	142},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	144},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	148},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	150},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	152},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	154},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	158},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	162},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	164},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	167},
+	{"cvmx_agl_gmx_tx#_clk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	2,	172},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	3,	174},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	177},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	179},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	181},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	183},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	185},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	193},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	195},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	197},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	199},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	201},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	203},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	205},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	207},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	209},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	211},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	2,	213},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	2,	215},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	3,	217},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	12,	220},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	12,	232},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	2,	244},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	246},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	124,	6,	248},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	125,	2,	254},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	126,	2,	256},
+	{"cvmx_agl_prt#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	127,	23,	258},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	2,	281},
+	{"cvmx_ciu_block_int"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	130,	37,	283},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	131,	2,	320},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	132,	2,	322},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	133,	2,	324},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	134,	22,	326},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	148,	22,	348},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	162,	22,	370},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	176,	33,	392},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	190,	33,	425},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	204,	33,	458},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	218,	22,	491},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	22,	513},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	230,	22,	535},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	236,	33,	557},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	242,	33,	590},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	248,	33,	623},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	254,	22,	656},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	267,	22,	678},
+	{"cvmx_ciu_int33_sum0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	273,	22,	700},
+	{"cvmx_ciu_int_dbg_sel"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	274,	6,	722},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	275,	33,	728},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	276,	2,	761},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	282,	2,	763},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	288,	2,	765},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	289,	2,	767},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	290,	2,	769},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	291,	1,	771},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	297,	3,	772},
+	{"cvmx_ciu_qlm0"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	298,	13,	775},
+	{"cvmx_ciu_qlm1"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	299,	13,	788},
+	{"cvmx_ciu_qlm2"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	300,	8,	801},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	301,	6,	809},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	302,	8,	815},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	303,	2,	823},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	304,	2,	825},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	305,	2,	827},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	306,	2,	829},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	307,	3,	831},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	311,	7,	834},
+	{"cvmx_dfa_bist0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	317,	12,	841},
+	{"cvmx_dfa_bist1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	318,	12,	853},
+	{"cvmx_dfa_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	319,	5,	865},
+	{"cvmx_dfa_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	320,	7,	870},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	321,	2,	877},
+	{"cvmx_dfa_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	322,	1,	879},
+	{"cvmx_dfa_debug1"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	323,	1,	880},
+	{"cvmx_dfa_debug2"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	324,	1,	881},
+	{"cvmx_dfa_debug3"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	325,	1,	882},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	326,	4,	883},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	327,	3,	887},
+	{"cvmx_dfa_dtcfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	328,	6,	890},
+	{"cvmx_dfa_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	329,	5,	896},
+	{"cvmx_dfa_intmsk"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	330,	3,	901},
+	{"cvmx_dfa_memhidat"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	331,	1,	904},
+	{"cvmx_dfa_pfc0_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	332,	1,	905},
+	{"cvmx_dfa_pfc0_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	333,	5,	906},
+	{"cvmx_dfa_pfc1_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	334,	1,	911},
+	{"cvmx_dfa_pfc1_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	335,	5,	912},
+	{"cvmx_dfa_pfc2_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	336,	1,	917},
+	{"cvmx_dfa_pfc2_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	337,	5,	918},
+	{"cvmx_dfa_pfc3_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	338,	1,	923},
+	{"cvmx_dfa_pfc3_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	339,	5,	924},
+	{"cvmx_dfa_pfc_gctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	340,	18,	929},
+	{"cvmx_dfm_char_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	341,	5,	947},
+	{"cvmx_dfm_char_mask0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	342,	2,	952},
+	{"cvmx_dfm_char_mask2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	343,	2,	954},
+	{"cvmx_dfm_char_mask4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	344,	12,	956},
+	{"cvmx_dfm_comp_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	345,	11,	968},
+	{"cvmx_dfm_config"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	346,	21,	979},
+	{"cvmx_dfm_control"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	347,	20,	1000},
+	{"cvmx_dfm_dll_ctl2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	348,	6,	1020},
+	{"cvmx_dfm_dll_ctl3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	349,	11,	1026},
+	{"cvmx_dfm_fclk_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	350,	1,	1037},
+	{"cvmx_dfm_fnt_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	351,	6,	1038},
+	{"cvmx_dfm_fnt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	352,	5,	1044},
+	{"cvmx_dfm_fnt_iena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	353,	3,	1049},
+	{"cvmx_dfm_fnt_sclk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	354,	4,	1052},
+	{"cvmx_dfm_fnt_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	6,	1056},
+	{"cvmx_dfm_ifb_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	1,	1062},
+	{"cvmx_dfm_modereg_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	357,	16,	1063},
+	{"cvmx_dfm_modereg_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	358,	25,	1079},
+	{"cvmx_dfm_ops_cnt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	1,	1104},
+	{"cvmx_dfm_phy_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	10,	1105},
+	{"cvmx_dfm_reset_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	361,	5,	1115},
+	{"cvmx_dfm_rlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	362,	10,	1120},
+	{"cvmx_dfm_rlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	363,	1,	1130},
+	{"cvmx_dfm_rlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	5,	1131},
+	{"cvmx_dfm_rodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	366,	8,	1136},
+	{"cvmx_dfm_slot_ctl0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	367,	5,	1144},
+	{"cvmx_dfm_slot_ctl1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	368,	5,	1149},
+	{"cvmx_dfm_timing_params0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	369,	12,	1154},
+	{"cvmx_dfm_timing_params1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	370,	13,	1166},
+	{"cvmx_dfm_wlevel_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	371,	6,	1179},
+	{"cvmx_dfm_wlevel_dbg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	372,	3,	1185},
+	{"cvmx_dfm_wlevel_rank#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	373,	5,	1188},
+	{"cvmx_dfm_wodt_mask"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	375,	8,	1193},
+	{"cvmx_dpi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	376,	2,	1201},
+	{"cvmx_dpi_ctl"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	377,	3,	1203},
+	{"cvmx_dpi_dma#_counts"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	378,	3,	1206},
+	{"cvmx_dpi_dma#_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	386,	2,	1209},
+	{"cvmx_dpi_dma#_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	394,	7,	1211},
+	{"cvmx_dpi_dma#_naddr"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	402,	2,	1218},
+	{"cvmx_dpi_dma#_reqbnk0"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	410,	1,	1220},
+	{"cvmx_dpi_dma#_reqbnk1"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	418,	1,	1221},
+	{"cvmx_dpi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	426,	19,	1222},
+	{"cvmx_dpi_dma_eng#_en"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	427,	2,	1241},
+	{"cvmx_dpi_eng#_buf"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	433,	3,	1243},
+	{"cvmx_dpi_info_reg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	439,	5,	1246},
+	{"cvmx_dpi_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	440,	15,	1251},
+	{"cvmx_dpi_int_reg"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	441,	15,	1266},
+	{"cvmx_dpi_pint_info"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	442,	4,	1281},
+	{"cvmx_dpi_pkt_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	443,	2,	1285},
+	{"cvmx_dpi_req_err_rsp"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	444,	2,	1287},
+	{"cvmx_dpi_req_err_rsp_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	445,	2,	1289},
+	{"cvmx_dpi_req_err_rst"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	446,	2,	1291},
+	{"cvmx_dpi_req_err_rst_en"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	447,	2,	1293},
+	{"cvmx_dpi_req_gbl_en"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	448,	2,	1295},
+	{"cvmx_dpi_sli_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	449,	14,	1297},
+	{"cvmx_dpi_sli_prt#_err"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	451,	2,	1311},
+	{"cvmx_dpi_sli_prt#_err_info"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	453,	6,	1313},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	455,	6,	1319},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	10,	1325},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	457,	3,	1335},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	2,	1338},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	3,	1340},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	2,	1343},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	473,	45,	1345},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	474,	45,	1390},
+	{"cvmx_fpa_packet_threshold"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	475,	2,	1435},
+	{"cvmx_fpa_pool#_threshold"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	476,	2,	1437},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	484,	2,	1439},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	492,	2,	1441},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	500,	3,	1443},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	501,	3,	1446},
+	{"cvmx_fpa_wqe_threshold"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	502,	2,	1449},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	7,	1451},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	504,	2,	1458},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	505,	2,	1460},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	506,	5,	1462},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	7,	1467},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	508,	2,	1474},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	509,	8,	1476},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	510,	10,	1484},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	514,	1,	1494},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	518,	1,	1495},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	522,	1,	1496},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	526,	1,	1497},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	530,	1,	1498},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	534,	1,	1499},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	538,	2,	1500},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	542,	4,	1502},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	546,	2,	1506},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	550,	9,	1508},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	554,	13,	1517},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	558,	2,	1530},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	562,	27,	1532},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	566,	27,	1559},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	570,	2,	1586},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	574,	2,	1588},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	578,	2,	1590},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	582,	2,	1592},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	586,	2,	1594},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	590,	2,	1596},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	594,	2,	1598},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	598,	2,	1600},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	602,	2,	1602},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	606,	2,	1604},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	610,	2,	1606},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	614,	2,	1608},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	618,	4,	1610},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	2,	1614},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	626,	2,	1616},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	630,	2,	1618},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	634,	4,	1620},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	635,	4,	1624},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	636,	2,	1628},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	637,	5,	1630},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	638,	2,	1635},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	639,	2,	1637},
+	{"cvmx_gmx#_soft_bist"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	643,	3,	1639},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	644,	3,	1642},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	645,	5,	1645},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	649,	2,	1650},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	653,	2,	1652},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	654,	2,	1654},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	655,	3,	1656},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	659,	2,	1659},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	663,	2,	1661},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	667,	2,	1663},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	671,	3,	1665},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	675,	2,	1668},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	679,	2,	1670},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	683,	2,	1672},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	687,	2,	1674},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	691,	2,	1676},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	695,	2,	1678},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	699,	2,	1680},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	703,	2,	1682},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	707,	2,	1684},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	711,	2,	1686},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	715,	2,	1688},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	719,	2,	1690},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	723,	2,	1692},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	727,	2,	1694},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	731,	2,	1696},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	735,	2,	1698},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	739,	2,	1700},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	740,	2,	1702},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	741,	2,	1704},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	742,	2,	1706},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	743,	2,	1708},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	744,	3,	1710},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	745,	9,	1713},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	746,	9,	1722},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	747,	2,	1731},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	748,	2,	1733},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	749,	6,	1735},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	2,	1741},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	2,	1743},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	752,	2,	1745},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	753,	9,	1747},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	754,	3,	1756},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	755,	10,	1759},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	771,	2,	1769},
+	{"cvmx_gpio_clk_qlm#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	775,	3,	1771},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	777,	2,	1774},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	778,	2,	1776},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	779,	2,	1778},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	780,	2,	1780},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	781,	24,	1782},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	782,	8,	1806},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	783,	3,	1814},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	784,	3,	1817},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	785,	3,	1820},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	786,	5,	1823},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	787,	5,	1828},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	1,	1833},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	789,	1,	1834},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	790,	7,	1835},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	791,	7,	1842},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	792,	3,	1849},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	793,	3,	1852},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	3,	1855},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	5,	1858},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	796,	5,	1863},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	797,	1,	1868},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	798,	1,	1869},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	799,	3,	1870},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	800,	3,	1873},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	801,	3,	1876},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	3,	1879},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	4,	1882},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	804,	2,	1886},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	805,	2,	1888},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	806,	2,	1890},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	807,	19,	1892},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	808,	2,	1911},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	809,	1,	1913},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	810,	18,	1914},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	811,	13,	1932},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	812,	13,	1945},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	813,	2,	1958},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	814,	2,	1960},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	815,	2,	1962},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	816,	3,	1964},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	824,	3,	1967},
+	{"cvmx_ipd_port#_bp_page_cnt3" ,	CVMX_CSR_DB_TYPE_NCB,	64,	828,	3,	1970},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	832,	2,	1973},
+	{"cvmx_ipd_port_bp_counters3_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	836,	2,	1975},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	840,	2,	1977},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	848,	2,	1979},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	976,	1,	1981},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	979,	1,	1982},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	982,	6,	1983},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	983,	5,	1989},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	984,	6,	1994},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	985,	7,	2000},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	986,	2,	2007},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	994,	2,	2009},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	995,	3,	2011},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	996,	2,	2014},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	997,	5,	2016},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1005,	3,	2021},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1006,	4,	2024},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1007,	3,	2028},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1008,	2,	2031},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1009,	2,	2033},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1010,	4,	2035},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1011,	3,	2039},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1012,	5,	2042},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1013,	5,	2047},
+	{"cvmx_l2c_big_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	4,	2052},
+	{"cvmx_l2c_bst"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1015,	12,	2056},
+	{"cvmx_l2c_bst_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1016,	5,	2068},
+	{"cvmx_l2c_bst_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1017,	5,	2073},
+	{"cvmx_l2c_bst_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	3,	2078},
+	{"cvmx_l2c_cop0_map#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	1,	2081},
+	{"cvmx_l2c_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2811,	14,	2082},
+	{"cvmx_l2c_dut_map#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2812,	4,	2096},
+	{"cvmx_l2c_err_tdt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4348,	9,	2100},
+	{"cvmx_l2c_err_ttg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4349,	9,	2109},
+	{"cvmx_l2c_err_vbf#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4350,	6,	2118},
+	{"cvmx_l2c_err_xmc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4351,	5,	2124},
+	{"cvmx_l2c_int_ena"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4352,	9,	2129},
+	{"cvmx_l2c_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4353,	11,	2138},
+	{"cvmx_l2c_ioc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4354,	1,	2149},
+	{"cvmx_l2c_ior#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4355,	1,	2150},
+	{"cvmx_l2c_qos_iob#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4356,	4,	2151},
+	{"cvmx_l2c_qos_pp#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4357,	2,	2155},
+	{"cvmx_l2c_qos_wgt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4363,	5,	2157},
+	{"cvmx_l2c_rsc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4364,	1,	2162},
+	{"cvmx_l2c_rsd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4365,	1,	2163},
+	{"cvmx_l2c_tad#_ecc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4366,	8,	2164},
+	{"cvmx_l2c_tad#_ecc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4367,	8,	2172},
+	{"cvmx_l2c_tad#_ien"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4368,	10,	2180},
+	{"cvmx_l2c_tad#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4369,	10,	2190},
+	{"cvmx_l2c_tad#_pfc0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4370,	1,	2200},
+	{"cvmx_l2c_tad#_pfc1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4371,	1,	2201},
+	{"cvmx_l2c_tad#_pfc2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4372,	1,	2202},
+	{"cvmx_l2c_tad#_pfc3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4373,	1,	2203},
+	{"cvmx_l2c_tad#_prf"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4374,	5,	2204},
+	{"cvmx_l2c_tad#_tag"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4375,	9,	2209},
+	{"cvmx_l2c_ver_id"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	4376,	1,	2218},
+	{"cvmx_l2c_ver_iob"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4377,	2,	2219},
+	{"cvmx_l2c_ver_msc"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4378,	3,	2221},
+	{"cvmx_l2c_ver_pp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	4379,	2,	2224},
+	{"cvmx_l2c_virtid_iob#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	4380,	4,	2226},
+	{"cvmx_l2c_virtid_pp#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	4381,	2,	2230},
+	{"cvmx_l2c_vrt_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	4387,	6,	2232},
+	{"cvmx_l2c_vrt_mem#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	4388,	3,	2238},
+	{"cvmx_l2c_wpar_iob#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5412,	2,	2241},
+	{"cvmx_l2c_wpar_pp#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5413,	2,	2243},
+	{"cvmx_l2c_xmc#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5419,	1,	2245},
+	{"cvmx_l2c_xmc_cmd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5420,	4,	2246},
+	{"cvmx_l2c_xmd#_pfc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5421,	1,	2250},
+	{"cvmx_lmc#_char_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5422,	5,	2251},
+	{"cvmx_lmc#_char_mask0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5423,	1,	2256},
+	{"cvmx_lmc#_char_mask1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5424,	2,	2257},
+	{"cvmx_lmc#_char_mask2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5425,	1,	2259},
+	{"cvmx_lmc#_char_mask3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5426,	2,	2260},
+	{"cvmx_lmc#_char_mask4"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5427,	12,	2262},
+	{"cvmx_lmc#_comp_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5428,	11,	2274},
+	{"cvmx_lmc#_config"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5429,	21,	2285},
+	{"cvmx_lmc#_control"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5430,	20,	2306},
+	{"cvmx_lmc#_dclk_cnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5431,	1,	2326},
+	{"cvmx_lmc#_ddr_pll_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5432,	11,	2327},
+	{"cvmx_lmc#_dimm#_params"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5433,	16,	2338},
+	{"cvmx_lmc#_dimm_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5435,	5,	2354},
+	{"cvmx_lmc#_dll_ctl2"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5436,	6,	2359},
+	{"cvmx_lmc#_dll_ctl3"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5437,	11,	2365},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5438,	4,	2376},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5439,	5,	2380},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	5440,	6,	2385},
+	{"cvmx_lmc#_ifb_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5441,	1,	2391},
+	{"cvmx_lmc#_int"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	5442,	4,	2392},
+	{"cvmx_lmc#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5443,	4,	2396},
+	{"cvmx_lmc#_modereg_params0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5444,	16,	2400},
+	{"cvmx_lmc#_modereg_params1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5445,	25,	2416},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	5446,	10,	2441},
+	{"cvmx_lmc#_ops_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5447,	1,	2451},
+	{"cvmx_lmc#_phy_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5448,	10,	2452},
+	{"cvmx_lmc#_reset_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5449,	5,	2462},
+	{"cvmx_lmc#_rlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5450,	10,	2467},
+	{"cvmx_lmc#_rlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5451,	1,	2477},
+	{"cvmx_lmc#_rlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5452,	11,	2478},
+	{"cvmx_lmc#_rodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5456,	8,	2489},
+	{"cvmx_lmc#_slot_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5457,	5,	2497},
+	{"cvmx_lmc#_slot_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5458,	5,	2502},
+	{"cvmx_lmc#_slot_ctl2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5459,	5,	2507},
+	{"cvmx_lmc#_timing_params0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5460,	12,	2512},
+	{"cvmx_lmc#_timing_params1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5461,	13,	2524},
+	{"cvmx_lmc#_tro_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5462,	3,	2537},
+	{"cvmx_lmc#_tro_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5463,	2,	2540},
+	{"cvmx_lmc#_wlevel_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5464,	6,	2542},
+	{"cvmx_lmc#_wlevel_dbg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5465,	3,	2548},
+	{"cvmx_lmc#_wlevel_rank#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5466,	11,	2551},
+	{"cvmx_lmc#_wodt_mask"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5470,	8,	2562},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5471,	2,	2570},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5472,	3,	2572},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5473,	10,	2575},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5475,	3,	2585},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5477,	3,	2588},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5479,	15,	2591},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5481,	3,	2606},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5482,	3,	2609},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5483,	3,	2612},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5484,	5,	2615},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5486,	1,	2620},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5487,	9,	2621},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5488,	13,	2630},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5496,	13,	2643},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5504,	6,	2656},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5505,	1,	2662},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5507,	2,	2663},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5508,	2,	2665},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5509,	12,	2667},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5510,	18,	2679},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5511,	4,	2697},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5512,	1,	2701},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5513,	7,	2702},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5514,	3,	2709},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5515,	8,	2712},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5516,	7,	2720},
+	{"cvmx_mio_fus_read_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5517,	6,	2727},
+	{"cvmx_mio_fus_repair_res0"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5518,	5,	2733},
+	{"cvmx_mio_fus_repair_res1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5519,	4,	2738},
+	{"cvmx_mio_fus_repair_res2"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5520,	2,	2742},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5521,	4,	2744},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	5522,	2,	2748},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5523,	2,	2750},
+	{"cvmx_mio_gpio_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5524,	3,	2752},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5525,	10,	2755},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	5526,	2,	2765},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5527,	2,	2767},
+	{"cvmx_mio_ptp_clock_cfg"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	5528,	10,	2769},
+	{"cvmx_mio_ptp_clock_comp"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	5529,	2,	2779},
+	{"cvmx_mio_ptp_clock_hi"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5530,	1,	2781},
+	{"cvmx_mio_ptp_clock_lo"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	5531,	2,	2782},
+	{"cvmx_mio_ptp_evt_cnt"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	5532,	1,	2784},
+	{"cvmx_mio_ptp_timestamp"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	5533,	1,	2785},
+	{"cvmx_mio_rst_boot"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5534,	9,	2786},
+	{"cvmx_mio_rst_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5535,	5,	2795},
+	{"cvmx_mio_rst_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5536,	10,	2800},
+	{"cvmx_mio_rst_delay"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5538,	3,	2810},
+	{"cvmx_mio_rst_int"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	5539,	6,	2813},
+	{"cvmx_mio_rst_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5540,	6,	2819},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	5541,	13,	2825},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5543,	12,	2838},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5545,	3,	2850},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5547,	3,	2853},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5549,	2,	2856},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5551,	2,	2858},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5553,	2,	2860},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5555,	7,	2862},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5557,	2,	2869},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5559,	7,	2871},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5561,	4,	2878},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5563,	8,	2882},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5565,	9,	2890},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5567,	7,	2899},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5569,	9,	2906},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5571,	2,	2915},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5573,	2,	2917},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5575,	4,	2919},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5577,	2,	2923},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5579,	2,	2925},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5581,	2,	2927},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5583,	4,	2929},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5585,	2,	2933},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	5587,	2,	2935},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5589,	2,	2937},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5591,	2,	2939},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5593,	2,	2941},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5595,	2,	2943},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5597,	6,	2945},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	5599,	7,	2951},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5601,	9,	2958},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5603,	9,	2967},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5605,	2,	2976},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5607,	3,	2978},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5609,	4,	2981},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5611,	4,	2985},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5613,	9,	2989},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5615,	2,	2998},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5617,	2,	3000},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5619,	4,	3002},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5621,	4,	3006},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5623,	4,	3010},
+	{"cvmx_mix#_tsctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5625,	6,	3014},
+	{"cvmx_mix#_tstamp"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5627,	1,	3020},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	5629,	4,	3021},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5630,	1,	3025},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5631,	2,	3026},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	5632,	3,	3028},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	5633,	8,	3031},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5634,	8,	3039},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	5635,	12,	3047},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	5636,	8,	3059},
+	{"cvmx_pcieep#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5637,	2,	3067},
+	{"cvmx_pcieep#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5639,	24,	3069},
+	{"cvmx_pcieep#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5641,	4,	3093},
+	{"cvmx_pcieep#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5643,	5,	3097},
+	{"cvmx_pcieep#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5645,	5,	3102},
+	{"cvmx_pcieep#_cfg004_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5647,	2,	3107},
+	{"cvmx_pcieep#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5649,	1,	3109},
+	{"cvmx_pcieep#_cfg005_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5651,	1,	3110},
+	{"cvmx_pcieep#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5653,	5,	3111},
+	{"cvmx_pcieep#_cfg006_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5655,	2,	3116},
+	{"cvmx_pcieep#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5657,	1,	3118},
+	{"cvmx_pcieep#_cfg007_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5659,	1,	3119},
+	{"cvmx_pcieep#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5661,	4,	3120},
+	{"cvmx_pcieep#_cfg008_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5663,	2,	3124},
+	{"cvmx_pcieep#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5665,	2,	3126},
+	{"cvmx_pcieep#_cfg009_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5667,	1,	3128},
+	{"cvmx_pcieep#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5669,	1,	3129},
+	{"cvmx_pcieep#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5671,	2,	3130},
+	{"cvmx_pcieep#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5673,	3,	3132},
+	{"cvmx_pcieep#_cfg012_mask"    ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5675,	2,	3135},
+	{"cvmx_pcieep#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5677,	2,	3137},
+	{"cvmx_pcieep#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5679,	4,	3139},
+	{"cvmx_pcieep#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5681,	10,	3143},
+	{"cvmx_pcieep#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5683,	12,	3153},
+	{"cvmx_pcieep#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5685,	7,	3165},
+	{"cvmx_pcieep#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5687,	2,	3172},
+	{"cvmx_pcieep#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5689,	1,	3174},
+	{"cvmx_pcieep#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5691,	2,	3175},
+	{"cvmx_pcieep#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5693,	7,	3177},
+	{"cvmx_pcieep#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5695,	11,	3184},
+	{"cvmx_pcieep#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5697,	19,	3195},
+	{"cvmx_pcieep#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5699,	11,	3214},
+	{"cvmx_pcieep#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5701,	17,	3225},
+	{"cvmx_pcieep#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5703,	12,	3242},
+	{"cvmx_pcieep#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5705,	22,	3254},
+	{"cvmx_pcieep#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5707,	3,	3276},
+	{"cvmx_pcieep#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5709,	3,	3279},
+	{"cvmx_pcieep#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5711,	1,	3282},
+	{"cvmx_pcieep#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5713,	11,	3283},
+	{"cvmx_pcieep#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5715,	1,	3294},
+	{"cvmx_pcieep#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5717,	1,	3295},
+	{"cvmx_pcieep#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5719,	3,	3296},
+	{"cvmx_pcieep#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5721,	14,	3299},
+	{"cvmx_pcieep#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5723,	14,	3313},
+	{"cvmx_pcieep#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5725,	14,	3327},
+	{"cvmx_pcieep#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5727,	9,	3341},
+	{"cvmx_pcieep#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5729,	9,	3350},
+	{"cvmx_pcieep#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5731,	6,	3359},
+	{"cvmx_pcieep#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5733,	1,	3365},
+	{"cvmx_pcieep#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5735,	1,	3366},
+	{"cvmx_pcieep#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5737,	1,	3367},
+	{"cvmx_pcieep#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5739,	1,	3368},
+	{"cvmx_pcieep#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5741,	2,	3369},
+	{"cvmx_pcieep#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5743,	1,	3371},
+	{"cvmx_pcieep#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5745,	6,	3372},
+	{"cvmx_pcieep#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5747,	6,	3378},
+	{"cvmx_pcieep#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5749,	13,	3384},
+	{"cvmx_pcieep#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5751,	5,	3397},
+	{"cvmx_pcieep#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5753,	8,	3402},
+	{"cvmx_pcieep#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5755,	19,	3410},
+	{"cvmx_pcieep#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5757,	3,	3429},
+	{"cvmx_pcieep#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5759,	1,	3432},
+	{"cvmx_pcieep#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5761,	1,	3433},
+	{"cvmx_pcieep#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5763,	3,	3434},
+	{"cvmx_pcieep#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5765,	3,	3437},
+	{"cvmx_pcieep#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5767,	3,	3440},
+	{"cvmx_pcieep#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5769,	4,	3443},
+	{"cvmx_pcieep#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5771,	4,	3447},
+	{"cvmx_pcieep#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5773,	4,	3451},
+	{"cvmx_pcieep#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5775,	7,	3455},
+	{"cvmx_pcieep#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5777,	5,	3462},
+	{"cvmx_pcieep#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5779,	5,	3467},
+	{"cvmx_pcieep#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5781,	4,	3472},
+	{"cvmx_pcieep#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5783,	4,	3476},
+	{"cvmx_pcieep#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5785,	4,	3480},
+	{"cvmx_pcieep#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5787,	7,	3484},
+	{"cvmx_pcieep#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5789,	1,	3491},
+	{"cvmx_pcieep#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	5791,	1,	3492},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5793,	2,	3493},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5795,	24,	3495},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5797,	4,	3519},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5799,	5,	3523},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5801,	1,	3528},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5803,	1,	3529},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5805,	4,	3530},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5807,	17,	3534},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5809,	4,	3551},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5811,	6,	3555},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5813,	1,	3561},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5815,	1,	3562},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5817,	2,	3563},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5819,	2,	3565},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5821,	1,	3567},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5823,	15,	3568},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5825,	10,	3583},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5827,	12,	3593},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5829,	7,	3605},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5831,	2,	3612},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5833,	1,	3614},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5835,	2,	3615},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5837,	7,	3617},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5839,	11,	3624},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5841,	19,	3635},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5843,	11,	3654},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5845,	20,	3665},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5847,	12,	3685},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5849,	22,	3697},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5851,	8,	3719},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5853,	4,	3727},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5855,	3,	3731},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5857,	3,	3734},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5859,	1,	3737},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5861,	11,	3738},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5863,	1,	3749},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5865,	1,	3750},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5867,	3,	3751},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5869,	14,	3754},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5871,	14,	3768},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5873,	14,	3782},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5875,	9,	3796},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5877,	9,	3805},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5879,	6,	3814},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5881,	1,	3820},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5883,	1,	3821},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5885,	1,	3822},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5887,	1,	3823},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5889,	4,	3824},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5891,	9,	3828},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5893,	2,	3837},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5895,	2,	3839},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5897,	1,	3841},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5899,	6,	3842},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5901,	6,	3848},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5903,	13,	3854},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5905,	5,	3867},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5907,	8,	3872},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5909,	19,	3880},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5911,	3,	3899},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5913,	1,	3902},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5915,	1,	3903},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5917,	3,	3904},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5919,	3,	3907},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5921,	3,	3910},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5923,	4,	3913},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5925,	4,	3917},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5927,	4,	3921},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5929,	7,	3925},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5931,	5,	3932},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5933,	5,	3937},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5935,	4,	3942},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5937,	4,	3946},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5939,	4,	3950},
+	{"cvmx_pcierc#_cfg515"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5941,	7,	3954},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5943,	1,	3961},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	5945,	1,	3962},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5947,	9,	3963},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5951,	6,	3972},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5955,	9,	3978},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5959,	6,	3987},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5963,	14,	3993},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5967,	14,	4007},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	5971,	2,	4021},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5975,	4,	4023},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	5979,	8,	4027},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5983,	13,	4035},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5987,	17,	4048},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	5991,	7,	4065},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	5995,	3,	4072},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5999,	8,	4075},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6003,	7,	4083},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6007,	4,	4090},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6011,	5,	4094},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6015,	8,	4099},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6016,	2,	4107},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6017,	5,	4109},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6018,	10,	4114},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6019,	2,	4124},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6020,	8,	4126},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6021,	8,	4134},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6022,	6,	4142},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6023,	5,	4148},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6024,	5,	4153},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6025,	3,	4158},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6026,	6,	4161},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6027,	9,	4167},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	6028,	5,	4176},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	6029,	10,	4181},
+	{"cvmx_pem#_bar1_index#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6030,	5,	4191},
+	{"cvmx_pem#_bar_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6062,	5,	4196},
+	{"cvmx_pem#_bist_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6064,	9,	4201},
+	{"cvmx_pem#_bist_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6066,	11,	4210},
+	{"cvmx_pem#_cfg_rd"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6068,	2,	4221},
+	{"cvmx_pem#_cfg_wr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6070,	2,	4223},
+	{"cvmx_pem#_cpl_lut_valid"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6072,	2,	4225},
+	{"cvmx_pem#_ctl_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6074,	18,	4227},
+	{"cvmx_pem#_dbg_info"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6076,	32,	4245},
+	{"cvmx_pem#_dbg_info_en"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6078,	32,	4277},
+	{"cvmx_pem#_diag_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6080,	5,	4309},
+	{"cvmx_pem#_int_enb"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6082,	15,	4314},
+	{"cvmx_pem#_int_enb_int"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6084,	15,	4329},
+	{"cvmx_pem#_int_sum"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6086,	15,	4344},
+	{"cvmx_pem#_p2n_bar0_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6088,	2,	4359},
+	{"cvmx_pem#_p2n_bar1_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6090,	2,	4361},
+	{"cvmx_pem#_p2n_bar2_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6092,	2,	4363},
+	{"cvmx_pem#_p2p_bar#_end"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6094,	2,	4365},
+	{"cvmx_pem#_p2p_bar#_start"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6102,	2,	4367},
+	{"cvmx_pem#_tlp_credits"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6110,	8,	4369},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6112,	5,	4377},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6113,	2,	4382},
+	{"cvmx_pip_clken"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	6114,	2,	4384},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6115,	4,	4386},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6119,	16,	4390},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6120,	16,	4406},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6121,	3,	4422},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6122,	8,	4425},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6123,	23,	4433},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6124,	6,	4456},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	6125,	14,	4462},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6126,	14,	4476},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6127,	2,	4490},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6128,	28,	4492},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6144,	25,	4520},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6160,	2,	4545},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6224,	4,	4547},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6232,	9,	4551},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6240,	2,	4560},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6241,	2,	4562},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6242,	2,	4564},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6254,	2,	4566},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6266,	2,	4568},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6278,	2,	4570},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6290,	2,	4572},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6302,	2,	4574},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6314,	2,	4576},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6326,	2,	4578},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6338,	2,	4580},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6350,	2,	4582},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6362,	2,	4584},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6363,	2,	4586},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6379,	2,	4588},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6395,	2,	4590},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6411,	2,	4592},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	6475,	2,	4594},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6476,	3,	4596},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6477,	3,	4599},
+	{"cvmx_pip_xstat0_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6478,	2,	4602},
+	{"cvmx_pip_xstat1_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6482,	2,	4604},
+	{"cvmx_pip_xstat2_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6486,	2,	4606},
+	{"cvmx_pip_xstat3_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6490,	2,	4608},
+	{"cvmx_pip_xstat4_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6494,	2,	4610},
+	{"cvmx_pip_xstat5_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6498,	2,	4612},
+	{"cvmx_pip_xstat6_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6502,	2,	4614},
+	{"cvmx_pip_xstat7_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6506,	2,	4616},
+	{"cvmx_pip_xstat8_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6510,	2,	4618},
+	{"cvmx_pip_xstat9_prt#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6514,	2,	4620},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6518,	2,	4622},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6519,	2,	4624},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6520,	4,	4626},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6521,	5,	4630},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6522,	4,	4635},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6523,	8,	4639},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6524,	4,	4647},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6525,	5,	4651},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6526,	1,	4656},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6527,	5,	4657},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6528,	1,	4662},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6529,	13,	4663},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6530,	6,	4676},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6531,	13,	4682},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6532,	6,	4695},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6533,	9,	4701},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6534,	4,	4710},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6535,	7,	4714},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6536,	5,	4721},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6537,	5,	4726},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6538,	4,	4731},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6539,	9,	4735},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6540,	5,	4744},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6541,	16,	4749},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6542,	4,	4765},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6543,	1,	4769},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6544,	1,	4770},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6545,	1,	4771},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6546,	1,	4772},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	6547,	13,	4773},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6548,	2,	4786},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6549,	4,	4788},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6550,	5,	4792},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	6551,	3,	4797},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6552,	4,	4800},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6553,	2,	4804},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6554,	3,	4806},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6555,	3,	4809},
+	{"cvmx_pko_reg_timestamp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	6556,	2,	4812},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6557,	10,	4814},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6558,	2,	4824},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6559,	13,	4826},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6560,	3,	4839},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6561,	2,	4842},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6569,	2,	4844},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6570,	2,	4846},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6571,	2,	4848},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6572,	2,	4850},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	6580,	2,	4852},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6581,	2,	4854},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	6582,	2,	4856},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6583,	10,	4858},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6589,	5,	4868},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	6597,	10,	4873},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	6605,	2,	4883},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6606,	2,	4885},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6607,	2,	4887},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6615,	3,	4889},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6616,	6,	4892},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	6632,	5,	4898},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	6633,	7,	4903},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	6649,	2,	4910},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6665,	1,	4912},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6666,	1,	4913},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6667,	1,	4914},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	6668,	5,	4915},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6669,	5,	4920},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6670,	4,	4925},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6671,	10,	4929},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6672,	1,	4939},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6673,	3,	4940},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6674,	7,	4943},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6675,	2,	4950},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6676,	1,	4952},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6677,	1,	4953},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6678,	1,	4954},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6679,	18,	4955},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6680,	3,	4973},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6681,	2,	4976},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6682,	3,	4978},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6683,	7,	4981},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	6684,	2,	4988},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6685,	2,	4990},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	6686,	2,	4992},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6687,	3,	4994},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6688,	3,	4997},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6689,	9,	5000},
+	{"cvmx_rnm_eer_dbg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6690,	1,	5009},
+	{"cvmx_rnm_eer_key"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	6691,	1,	5010},
+	{"cvmx_rnm_serial_num"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	6692,	1,	5011},
+	{"cvmx_sli_bist_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6693,	25,	5012},
+	{"cvmx_sli_ctl_port#"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6694,	16,	5037},
+	{"cvmx_sli_ctl_status"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6696,	4,	5053},
+	{"cvmx_sli_data_out_cnt"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6697,	5,	5057},
+	{"cvmx_sli_dbg_data"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6698,	3,	5062},
+	{"cvmx_sli_dbg_select"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6699,	3,	5065},
+	{"cvmx_sli_dma#_cnt"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6700,	2,	5068},
+	{"cvmx_sli_dma#_int_level"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6702,	2,	5070},
+	{"cvmx_sli_dma#_tim"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6704,	2,	5072},
+	{"cvmx_sli_int_enb_ciu"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6706,	35,	5074},
+	{"cvmx_sli_int_enb_port#"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6707,	37,	5109},
+	{"cvmx_sli_int_sum"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6709,	37,	5146},
+	{"cvmx_sli_last_win_rdata0"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6710,	1,	5183},
+	{"cvmx_sli_last_win_rdata1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6711,	1,	5184},
+	{"cvmx_sli_mac_credit_cnt"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6712,	13,	5185},
+	{"cvmx_sli_mac_number"         ,	CVMX_CSR_DB_TYPE_PEXP,	64,	6713,	2,	5198},
+	{"cvmx_sli_mem_access_ctl"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6714,	3,	5200},
+	{"cvmx_sli_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6715,	9,	5203},
+	{"cvmx_sli_msi_enb0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6731,	1,	5212},
+	{"cvmx_sli_msi_enb1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6732,	1,	5213},
+	{"cvmx_sli_msi_enb2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6733,	1,	5214},
+	{"cvmx_sli_msi_enb3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6734,	1,	5215},
+	{"cvmx_sli_msi_rcv0"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6735,	1,	5216},
+	{"cvmx_sli_msi_rcv1"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6736,	1,	5217},
+	{"cvmx_sli_msi_rcv2"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6737,	1,	5218},
+	{"cvmx_sli_msi_rcv3"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6738,	1,	5219},
+	{"cvmx_sli_msi_rd_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6739,	3,	5220},
+	{"cvmx_sli_msi_w1c_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6740,	1,	5223},
+	{"cvmx_sli_msi_w1c_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6741,	1,	5224},
+	{"cvmx_sli_msi_w1c_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6742,	1,	5225},
+	{"cvmx_sli_msi_w1c_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6743,	1,	5226},
+	{"cvmx_sli_msi_w1s_enb0"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6744,	1,	5227},
+	{"cvmx_sli_msi_w1s_enb1"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6745,	1,	5228},
+	{"cvmx_sli_msi_w1s_enb2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6746,	1,	5229},
+	{"cvmx_sli_msi_w1s_enb3"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6747,	1,	5230},
+	{"cvmx_sli_msi_wr_map"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6748,	3,	5231},
+	{"cvmx_sli_pcie_msi_rcv"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6749,	2,	5234},
+	{"cvmx_sli_pcie_msi_rcv_b1"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6750,	3,	5236},
+	{"cvmx_sli_pcie_msi_rcv_b2"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6751,	3,	5239},
+	{"cvmx_sli_pcie_msi_rcv_b3"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6752,	3,	5242},
+	{"cvmx_sli_pkt#_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6753,	3,	5245},
+	{"cvmx_sli_pkt#_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6785,	2,	5248},
+	{"cvmx_sli_pkt#_instr_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6817,	2,	5250},
+	{"cvmx_sli_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6849,	2,	5252},
+	{"cvmx_sli_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6881,	5,	5254},
+	{"cvmx_sli_pkt#_instr_header"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6913,	21,	5259},
+	{"cvmx_sli_pkt#_out_size"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6945,	3,	5280},
+	{"cvmx_sli_pkt#_slist_baddr"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	6977,	2,	5283},
+	{"cvmx_sli_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7009,	2,	5285},
+	{"cvmx_sli_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7041,	2,	5287},
+	{"cvmx_sli_pkt_cnt_int"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7073,	2,	5289},
+	{"cvmx_sli_pkt_cnt_int_enb"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7074,	2,	5291},
+	{"cvmx_sli_pkt_ctl"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7075,	3,	5293},
+	{"cvmx_sli_pkt_data_out_es"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7076,	1,	5296},
+	{"cvmx_sli_pkt_data_out_ns"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7077,	2,	5297},
+	{"cvmx_sli_pkt_data_out_ror"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7078,	2,	5299},
+	{"cvmx_sli_pkt_dpaddr"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7079,	2,	5301},
+	{"cvmx_sli_pkt_in_bp"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7080,	2,	5303},
+	{"cvmx_sli_pkt_in_done#_cnts"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7081,	2,	5305},
+	{"cvmx_sli_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7113,	2,	5307},
+	{"cvmx_sli_pkt_in_pcie_port"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7114,	1,	5309},
+	{"cvmx_sli_pkt_input_control"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7115,	10,	5310},
+	{"cvmx_sli_pkt_instr_enb"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7116,	2,	5320},
+	{"cvmx_sli_pkt_instr_rd_size"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7117,	1,	5322},
+	{"cvmx_sli_pkt_instr_size"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7118,	2,	5323},
+	{"cvmx_sli_pkt_int_levels"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7119,	3,	5325},
+	{"cvmx_sli_pkt_iptr"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7120,	2,	5328},
+	{"cvmx_sli_pkt_out_bmode"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7121,	2,	5330},
+	{"cvmx_sli_pkt_out_enb"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7122,	2,	5332},
+	{"cvmx_sli_pkt_output_wmark"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7123,	2,	5334},
+	{"cvmx_sli_pkt_pcie_port"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7124,	1,	5336},
+	{"cvmx_sli_pkt_port_in_rst"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7125,	2,	5337},
+	{"cvmx_sli_pkt_slist_es"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7126,	1,	5339},
+	{"cvmx_sli_pkt_slist_ns"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7127,	2,	5340},
+	{"cvmx_sli_pkt_slist_ror"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7128,	2,	5342},
+	{"cvmx_sli_pkt_time_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7129,	2,	5344},
+	{"cvmx_sli_pkt_time_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7130,	2,	5346},
+	{"cvmx_sli_s2m_port#_ctl"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7131,	4,	5348},
+	{"cvmx_sli_scratch_1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7133,	1,	5352},
+	{"cvmx_sli_scratch_2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7134,	1,	5353},
+	{"cvmx_sli_state1"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7135,	4,	5354},
+	{"cvmx_sli_state2"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7136,	8,	5358},
+	{"cvmx_sli_state3"             ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7137,	5,	5366},
+	{"cvmx_sli_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7138,	4,	5371},
+	{"cvmx_sli_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7139,	1,	5375},
+	{"cvmx_sli_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7140,	4,	5376},
+	{"cvmx_sli_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7141,	1,	5380},
+	{"cvmx_sli_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PEXP,	64,	7142,	2,	5381},
+	{"cvmx_sli_window_ctl"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	7143,	2,	5383},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7144,	10,	5385},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	7146,	6,	5395},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7148,	2,	5401},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7150,	4,	5403},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7152,	4,	5407},
+	{"cvmx_smi_drv_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7154,	4,	5411},
+	{"cvmx_srio#_acc_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7155,	4,	5415},
+	{"cvmx_srio#_asmbly_id"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7157,	3,	5419},
+	{"cvmx_srio#_asmbly_info"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7159,	3,	5422},
+	{"cvmx_srio#_bell_resp_ctrl"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7161,	5,	5425},
+	{"cvmx_srio#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7163,	19,	5430},
+	{"cvmx_srio#_imsg_ctrl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7165,	14,	5449},
+	{"cvmx_srio#_imsg_inst_hdr#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7167,	14,	5463},
+	{"cvmx_srio#_imsg_qos_grp#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7171,	24,	5477},
+	{"cvmx_srio#_imsg_status#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7235,	24,	5501},
+	{"cvmx_srio#_imsg_vport_thr"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7283,	13,	5525},
+	{"cvmx_srio#_int2_enable"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7285,	2,	5538},
+	{"cvmx_srio#_int2_reg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7287,	4,	5540},
+	{"cvmx_srio#_int_enable"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7289,	27,	5544},
+	{"cvmx_srio#_int_info0"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7291,	9,	5571},
+	{"cvmx_srio#_int_info1"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7293,	1,	5580},
+	{"cvmx_srio#_int_info2"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7295,	11,	5581},
+	{"cvmx_srio#_int_info3"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7297,	5,	5592},
+	{"cvmx_srio#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7299,	29,	5597},
+	{"cvmx_srio#_ip_feature"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7301,	9,	5626},
+	{"cvmx_srio#_mac_buffers"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7303,	10,	5635},
+	{"cvmx_srio#_maint_op"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7305,	6,	5645},
+	{"cvmx_srio#_maint_rd_data"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7307,	3,	5651},
+	{"cvmx_srio#_mce_tx_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7309,	2,	5654},
+	{"cvmx_srio#_mem_op_ctrl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7311,	8,	5656},
+	{"cvmx_srio#_omsg_ctrl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7313,	11,	5664},
+	{"cvmx_srio#_omsg_done_counts#",	CVMX_CSR_DB_TYPE_RSL,	64,	7317,	3,	5675},
+	{"cvmx_srio#_omsg_fmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7321,	16,	5678},
+	{"cvmx_srio#_omsg_nmp_mr#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7325,	16,	5694},
+	{"cvmx_srio#_omsg_port#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7329,	4,	5710},
+	{"cvmx_srio#_omsg_silo_thr"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7333,	2,	5714},
+	{"cvmx_srio#_omsg_sp_mr#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7335,	17,	5716},
+	{"cvmx_srio#_prio#_in_use"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7339,	3,	5733},
+	{"cvmx_srio#_rx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7347,	9,	5736},
+	{"cvmx_srio#_rx_bell_seq"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7349,	3,	5745},
+	{"cvmx_srio#_rx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7351,	9,	5748},
+	{"cvmx_srio#_s2m_type#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7353,	11,	5757},
+	{"cvmx_srio#_seq"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7385,	2,	5768},
+	{"cvmx_srio#_status_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7387,	3,	5770},
+	{"cvmx_srio#_tag_ctrl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7389,	6,	5773},
+	{"cvmx_srio#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7391,	6,	5779},
+	{"cvmx_srio#_tx_bell"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7393,	10,	5785},
+	{"cvmx_srio#_tx_bell_info"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	7395,	11,	5795},
+	{"cvmx_srio#_tx_ctrl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7397,	12,	5806},
+	{"cvmx_srio#_tx_emphasis"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7399,	2,	5818},
+	{"cvmx_srio#_tx_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7401,	5,	5820},
+	{"cvmx_srio#_wr_done_counts"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7403,	3,	5825},
+	{"cvmx_sriomaint#_asmbly_id"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7405,	2,	5828},
+	{"cvmx_sriomaint#_asmbly_info" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7407,	2,	5830},
+	{"cvmx_sriomaint#_bar1_idx#"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7409,	7,	5832},
+	{"cvmx_sriomaint#_bell_status" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7441,	2,	5839},
+	{"cvmx_sriomaint#_comp_tag"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7443,	1,	5841},
+	{"cvmx_sriomaint#_core_enables",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7445,	6,	5842},
+	{"cvmx_sriomaint#_dev_id"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7447,	2,	5848},
+	{"cvmx_sriomaint#_dev_rev"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7449,	2,	5850},
+	{"cvmx_sriomaint#_dst_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7451,	26,	5852},
+	{"cvmx_sriomaint#_erb_attr_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7453,	5,	5878},
+	{"cvmx_sriomaint#_erb_err_det" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7455,	17,	5883},
+	{"cvmx_sriomaint#_erb_err_rate",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7457,	5,	5900},
+	{"cvmx_sriomaint#_erb_err_rate_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7459,	17,	5905},
+	{"cvmx_sriomaint#_erb_err_rate_thr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7461,	3,	5922},
+	{"cvmx_sriomaint#_erb_hdr"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7463,	2,	5925},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_h",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7465,	1,	5927},
+	{"cvmx_sriomaint#_erb_lt_addr_capt_l",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7467,	3,	5928},
+	{"cvmx_sriomaint#_erb_lt_ctrl_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7469,	9,	5931},
+	{"cvmx_sriomaint#_erb_lt_dev_id",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7471,	4,	5940},
+	{"cvmx_sriomaint#_erb_lt_dev_id_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7473,	4,	5944},
+	{"cvmx_sriomaint#_erb_lt_err_det",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7475,	12,	5948},
+	{"cvmx_sriomaint#_erb_lt_err_en",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7477,	12,	5960},
+	{"cvmx_sriomaint#_erb_pack_capt_1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7479,	1,	5972},
+	{"cvmx_sriomaint#_erb_pack_capt_2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7481,	1,	5973},
+	{"cvmx_sriomaint#_erb_pack_capt_3",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7483,	1,	5974},
+	{"cvmx_sriomaint#_erb_pack_sym_capt",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7485,	1,	5975},
+	{"cvmx_sriomaint#_hb_dev_id_lock",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7487,	2,	5976},
+	{"cvmx_sriomaint#_ir_buffer_config",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7489,	7,	5978},
+	{"cvmx_sriomaint#_ir_buffer_config2",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7491,	8,	5985},
+	{"cvmx_sriomaint#_ir_pd_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7493,	1,	5993},
+	{"cvmx_sriomaint#_ir_pd_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7495,	9,	5994},
+	{"cvmx_sriomaint#_ir_pi_phy_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7497,	5,	6003},
+	{"cvmx_sriomaint#_ir_pi_phy_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7499,	4,	6008},
+	{"cvmx_sriomaint#_ir_sp_rx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7501,	2,	6012},
+	{"cvmx_sriomaint#_ir_sp_rx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7503,	1,	6014},
+	{"cvmx_sriomaint#_ir_sp_rx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7505,	5,	6015},
+	{"cvmx_sriomaint#_ir_sp_tx_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7507,	2,	6020},
+	{"cvmx_sriomaint#_ir_sp_tx_data",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7509,	1,	6022},
+	{"cvmx_sriomaint#_ir_sp_tx_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7511,	5,	6023},
+	{"cvmx_sriomaint#_lane_#_status_0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7513,	15,	6028},
+	{"cvmx_sriomaint#_lcs_ba0"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7521,	2,	6043},
+	{"cvmx_sriomaint#_lcs_ba1"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7523,	2,	6045},
+	{"cvmx_sriomaint#_m2s_bar0_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7525,	2,	6047},
+	{"cvmx_sriomaint#_m2s_bar0_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7527,	4,	6049},
+	{"cvmx_sriomaint#_m2s_bar1_start0",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7529,	2,	6053},
+	{"cvmx_sriomaint#_m2s_bar1_start1",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7531,	5,	6055},
+	{"cvmx_sriomaint#_m2s_bar2_start",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7533,	7,	6060},
+	{"cvmx_sriomaint#_mac_ctrl"    ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7535,	5,	6067},
+	{"cvmx_sriomaint#_pe_feat"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7537,	11,	6072},
+	{"cvmx_sriomaint#_pe_llc"      ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7539,	2,	6083},
+	{"cvmx_sriomaint#_port_0_ctl"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7541,	18,	6085},
+	{"cvmx_sriomaint#_port_0_ctl2" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7543,	16,	6103},
+	{"cvmx_sriomaint#_port_0_err_stat",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7545,	20,	6119},
+	{"cvmx_sriomaint#_port_0_link_req",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7547,	2,	6139},
+	{"cvmx_sriomaint#_port_0_link_resp",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7549,	4,	6141},
+	{"cvmx_sriomaint#_port_0_local_ackid",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7551,	6,	6145},
+	{"cvmx_sriomaint#_port_gen_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7553,	4,	6151},
+	{"cvmx_sriomaint#_port_lt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7555,	2,	6155},
+	{"cvmx_sriomaint#_port_mbh0"   ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7557,	2,	6157},
+	{"cvmx_sriomaint#_port_rt_ctl" ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7559,	2,	6159},
+	{"cvmx_sriomaint#_port_ttl_ctl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7561,	2,	6161},
+	{"cvmx_sriomaint#_pri_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7563,	3,	6163},
+	{"cvmx_sriomaint#_sec_dev_ctrl",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7565,	3,	6166},
+	{"cvmx_sriomaint#_sec_dev_id"  ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7567,	3,	6169},
+	{"cvmx_sriomaint#_serial_lane_hdr",	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7569,	2,	6172},
+	{"cvmx_sriomaint#_src_ops"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7571,	26,	6174},
+	{"cvmx_sriomaint#_tx_drop"     ,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	7573,	3,	6200},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7575,	6,	6203},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7576,	3,	6209},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7577,	5,	6212},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7578,	4,	6217},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7579,	6,	6221},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7580,	4,	6227},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7581,	2,	6231},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7582,	4,	6233},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7583,	2,	6237},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7584,	3,	6239},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7585,	2,	6242},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	7586,	14,	6244},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7587,	3,	6258},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7588,	5,	6261},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7589,	2,	6266},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	7590,	2,	6268},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7591,	57,	6270},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7592,	20,	6327},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7593,	7,	6347},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7594,	5,	6354},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7595,	1,	6359},
+	{"cvmx_tra_read_dat_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	7596,	2,	6360},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7597,	2,	6362},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7598,	2,	6364},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7599,	57,	6366},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7600,	20,	6423},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7601,	7,	6443},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7602,	2,	6450},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7603,	2,	6452},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7604,	57,	6454},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7605,	20,	6511},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7606,	7,	6531},
+	{"cvmx_uahc#_ehci_asynclistaddr",	CVMX_CSR_DB_TYPE_NCB,	32,	7607,	2,	6538},
+	{"cvmx_uahc#_ehci_configflag"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7608,	2,	6540},
+	{"cvmx_uahc#_ehci_ctrldssegment",	CVMX_CSR_DB_TYPE_NCB,	32,	7609,	1,	6542},
+	{"cvmx_uahc#_ehci_frindex"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7610,	2,	6543},
+	{"cvmx_uahc#_ehci_hccapbase"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7611,	3,	6545},
+	{"cvmx_uahc#_ehci_hccparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7612,	7,	6548},
+	{"cvmx_uahc#_ehci_hcsparams"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7613,	10,	6555},
+	{"cvmx_uahc#_ehci_insnreg00"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7614,	3,	6565},
+	{"cvmx_uahc#_ehci_insnreg03"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7615,	5,	6568},
+	{"cvmx_uahc#_ehci_insnreg04"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7616,	7,	6573},
+	{"cvmx_uahc#_ehci_insnreg06"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7617,	2,	6580},
+	{"cvmx_uahc#_ehci_insnreg07"   ,	CVMX_CSR_DB_TYPE_NCB,	32,	7618,	1,	6582},
+	{"cvmx_uahc#_ehci_periodiclistbase",	CVMX_CSR_DB_TYPE_NCB,	32,	7619,	2,	6583},
+	{"cvmx_uahc#_ehci_portsc#"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7620,	19,	6585},
+	{"cvmx_uahc#_ehci_usbcmd"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7622,	13,	6604},
+	{"cvmx_uahc#_ehci_usbintr"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7623,	7,	6617},
+	{"cvmx_uahc#_ehci_usbsts"      ,	CVMX_CSR_DB_TYPE_NCB,	32,	7624,	12,	6624},
+	{"cvmx_uahc#_ohci0_hcbulkcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7625,	2,	6636},
+	{"cvmx_uahc#_ohci0_hcbulkheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7626,	2,	6638},
+	{"cvmx_uahc#_ohci0_hccommandstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7627,	7,	6640},
+	{"cvmx_uahc#_ohci0_hccontrol"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7628,	10,	6647},
+	{"cvmx_uahc#_ohci0_hccontrolcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7629,	2,	6657},
+	{"cvmx_uahc#_ohci0_hccontrolheaded",	CVMX_CSR_DB_TYPE_NCB,	32,	7630,	2,	6659},
+	{"cvmx_uahc#_ohci0_hcdonehead" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7631,	2,	6661},
+	{"cvmx_uahc#_ohci0_hcfminterval",	CVMX_CSR_DB_TYPE_NCB,	32,	7632,	4,	6663},
+	{"cvmx_uahc#_ohci0_hcfmnumber" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7633,	2,	6667},
+	{"cvmx_uahc#_ohci0_hcfmremaining",	CVMX_CSR_DB_TYPE_NCB,	32,	7634,	3,	6669},
+	{"cvmx_uahc#_ohci0_hchcca"     ,	CVMX_CSR_DB_TYPE_NCB,	32,	7635,	2,	6672},
+	{"cvmx_uahc#_ohci0_hcinterruptdisable",	CVMX_CSR_DB_TYPE_NCB,	32,	7636,	10,	6674},
+	{"cvmx_uahc#_ohci0_hcinterruptenable",	CVMX_CSR_DB_TYPE_NCB,	32,	7637,	10,	6684},
+	{"cvmx_uahc#_ohci0_hcinterruptstatus",	CVMX_CSR_DB_TYPE_NCB,	32,	7638,	10,	6694},
+	{"cvmx_uahc#_ohci0_hclsthreshold",	CVMX_CSR_DB_TYPE_NCB,	32,	7639,	2,	6704},
+	{"cvmx_uahc#_ohci0_hcperiodcurrented",	CVMX_CSR_DB_TYPE_NCB,	32,	7640,	2,	6706},
+	{"cvmx_uahc#_ohci0_hcperiodicstart",	CVMX_CSR_DB_TYPE_NCB,	32,	7641,	2,	6708},
+	{"cvmx_uahc#_ohci0_hcrevision" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7642,	2,	6710},
+	{"cvmx_uahc#_ohci0_hcrhdescriptora",	CVMX_CSR_DB_TYPE_NCB,	32,	7643,	8,	6712},
+	{"cvmx_uahc#_ohci0_hcrhdescriptorb",	CVMX_CSR_DB_TYPE_NCB,	32,	7644,	2,	6720},
+	{"cvmx_uahc#_ohci0_hcrhportstatus#",	CVMX_CSR_DB_TYPE_NCB,	32,	7645,	15,	6722},
+	{"cvmx_uahc#_ohci0_hcrhstatus" ,	CVMX_CSR_DB_TYPE_NCB,	32,	7647,	8,	6737},
+	{"cvmx_uahc#_ohci0_insnreg06"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7648,	2,	6745},
+	{"cvmx_uahc#_ohci0_insnreg07"  ,	CVMX_CSR_DB_TYPE_NCB,	32,	7649,	1,	6747},
+	{"cvmx_uctl#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7650,	7,	6748},
+	{"cvmx_uctl#_clk_rst_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	7651,	21,	6755},
+	{"cvmx_uctl#_ehci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7652,	12,	6776},
+	{"cvmx_uctl#_ehci_fla"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7653,	2,	6788},
+	{"cvmx_uctl#_erto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7654,	3,	6790},
+	{"cvmx_uctl#_if_ena"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7655,	2,	6793},
+	{"cvmx_uctl#_int_ena"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7656,	9,	6795},
+	{"cvmx_uctl#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7657,	9,	6804},
+	{"cvmx_uctl#_ohci_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7658,	11,	6813},
+	{"cvmx_uctl#_orto_ctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	7659,	3,	6824},
+	{"cvmx_uctl#_ppaf_wm"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7660,	2,	6827},
+	{"cvmx_uctl#_uphy_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	7661,	11,	6829},
+	{"cvmx_uctl#_uphy_port#_ctl_status",	CVMX_CSR_DB_TYPE_RSL,	64,	7662,	20,	6840},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	7664,	3,	6860},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7665,	5,	6863},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	7666,	3,	6868},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	7667,	6,	6871},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	7668,	2,	6877},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	7669,	2,	6879},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7670,	2,	6881},
+	{"cvmx_zip_throttle"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	7671,	2,	6883},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800e0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800e0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800e0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800e0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800e0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800e0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800e0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800e0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800e0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800e0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800e0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800e0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800e00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800e00009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800e00001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800e00009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800e0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800e0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800e0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800e0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800e0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800e0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800e0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800e0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800e0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800e0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800e0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800e0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800e0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800e0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800e0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800e0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800e0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800e0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800e0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800e0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800e0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800e0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800e0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800e0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_RX_INBND"        ,	   0x11800e0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_RX_INBND"        ,	   0x11800e0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800e0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800e0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800e0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800e0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800e0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800e0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800e00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800e00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800e00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800e00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800e0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800e0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800e00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800e00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800e0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800e0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800e00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800e00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800e00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800e00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800e0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800e0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800e0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800e0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800e0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800e0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800e0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800e0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800e00004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800e00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_SMAC0"               ,	   0x11800e0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC1"               ,	   0x11800e0000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800e0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800e0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800e0000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_CLK"             ,	   0x11800e0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_CLK"             ,	   0x11800e0000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800e0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800e0000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800e0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800e0000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800e0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800e0000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800e0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800e0000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800e0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800e0000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800e0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800e0000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800e0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800e0000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800e0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800e0000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800e0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800e0000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800e0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800e0000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800e0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800e0000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800e00002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800e0000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800e00002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800e0000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800e00002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800e0000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800e00002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800e0000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800e00002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800e0000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800e00002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800e0000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800e0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800e0000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800e0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800e0000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800e00004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800e0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800e0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800e0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800e0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800e0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800e00004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800e00004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800e00004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800e00004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"AGL_PRT0_CTL"                ,	   0x11800e0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"AGL_PRT1_CTL"                ,	   0x11800e0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_BLOCK_INT"               ,	   0x10700000007c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN0"               ,	   0x10700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN0"               ,	   0x10700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT33_EN0"               ,	   0x1070000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT33_EN0_W1C"           ,	   0x1070000002410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT33_EN0_W1S"           ,	   0x1070000006410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_EN1"               ,	   0x10700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_EN1"               ,	   0x10700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT33_EN1"               ,	   0x1070000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT33_EN1_W1C"           ,	   0x1070000002418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT33_EN1_W1S"           ,	   0x1070000006418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006c80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006c90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006ca0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006cb0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006cc0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006cd0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006c88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006c98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006ca8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006cb8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006cc8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006cd8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000c00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000c08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000c10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000c18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000c20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000c28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_INT33_SUM0"              ,	   0x1070000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_INT_DBG_SEL"             ,	   0x10700000007d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_POKE4"                ,	   0x10700000005a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_POKE5"                ,	   0x10700000005a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_QLM0"                    ,	   0x1070000000780ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_QLM1"                    ,	   0x1070000000788ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_QLM2"                    ,	   0x1070000000790ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	106},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	107},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	108},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	109},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	110},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	111},
+	{"DFA_BIST0"                   ,	   0x11800370007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"DFA_BIST1"                   ,	   0x11800370007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"DFA_CONFIG"                  ,	   0x1180037000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"DFA_CONTROL"                 ,	   0x1180037000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	116},
+	{"DFA_DEBUG0"                  ,	   0x1180037000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"DFA_DEBUG1"                  ,	   0x1180037000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"DFA_DEBUG2"                  ,	   0x1180037000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"DFA_DEBUG3"                  ,	   0x1180037000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"DFA_DTCFADR"                 ,	   0x1180037000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"DFA_ERROR"                   ,	   0x1180037000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"DFA_INTMSK"                  ,	   0x1180037000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"DFA_MEMHIDAT"                ,	   0x1370700000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"DFA_PFC0_CNT"                ,	   0x1180037000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"DFA_PFC0_CTL"                ,	   0x1180037000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"DFA_PFC1_CNT"                ,	   0x11800370000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"DFA_PFC1_CTL"                ,	   0x1180037000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"DFA_PFC2_CNT"                ,	   0x11800370000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"DFA_PFC2_CTL"                ,	   0x11800370000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"DFA_PFC3_CNT"                ,	   0x11800370000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"DFA_PFC3_CTL"                ,	   0x11800370000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"DFA_PFC_GCTL"                ,	   0x1180037000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"DFM_CHAR_CTL"                ,	   0x11800d4000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"DFM_CHAR_MASK0"              ,	   0x11800d4000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"DFM_CHAR_MASK2"              ,	   0x11800d4000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"DFM_CHAR_MASK4"              ,	   0x11800d4000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"DFM_COMP_CTL2"               ,	   0x11800d40001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"DFM_CONFIG"                  ,	   0x11800d4000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"DFM_CONTROL"                 ,	   0x11800d4000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"DFM_DLL_CTL2"                ,	   0x11800d40001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"DFM_DLL_CTL3"                ,	   0x11800d4000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"DFM_FCLK_CNT"                ,	   0x11800d40001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"DFM_FNT_BIST"                ,	   0x11800d40007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"DFM_FNT_CTL"                 ,	   0x11800d4000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"DFM_FNT_IENA"                ,	   0x11800d4000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"DFM_FNT_SCLK"                ,	   0x11800d4000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"DFM_FNT_STAT"                ,	   0x11800d4000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"DFM_IFB_CNT"                 ,	   0x11800d40001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"DFM_MODEREG_PARAMS0"         ,	   0x11800d40001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"DFM_MODEREG_PARAMS1"         ,	   0x11800d4000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"DFM_OPS_CNT"                 ,	   0x11800d40001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"DFM_PHY_CTL"                 ,	   0x11800d4000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"DFM_RESET_CTL"               ,	   0x11800d4000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"DFM_RLEVEL_CTL"              ,	   0x11800d40002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"DFM_RLEVEL_DBG"              ,	   0x11800d40002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"DFM_RLEVEL_RANK0"            ,	   0x11800d4000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"DFM_RLEVEL_RANK1"            ,	   0x11800d4000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"DFM_RODT_MASK"               ,	   0x11800d4000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"DFM_SLOT_CTL0"               ,	   0x11800d40001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"DFM_SLOT_CTL1"               ,	   0x11800d4000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"DFM_TIMING_PARAMS0"          ,	   0x11800d4000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"DFM_TIMING_PARAMS1"          ,	   0x11800d40001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"DFM_WLEVEL_CTL"              ,	   0x11800d4000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"DFM_WLEVEL_DBG"              ,	   0x11800d4000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"DFM_WLEVEL_RANK0"            ,	   0x11800d40002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"DFM_WLEVEL_RANK1"            ,	   0x11800d40002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"DFM_WODT_MASK"               ,	   0x11800d40001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"DPI_BIST_STATUS"             ,	   0x1df0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"DPI_CTL"                     ,	   0x1df0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"DPI_DMA0_COUNTS"             ,	   0x1df0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA1_COUNTS"             ,	   0x1df0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA2_COUNTS"             ,	   0x1df0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA3_COUNTS"             ,	   0x1df0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA4_COUNTS"             ,	   0x1df0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA5_COUNTS"             ,	   0x1df0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA6_COUNTS"             ,	   0x1df0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA7_COUNTS"             ,	   0x1df0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"DPI_DMA0_DBELL"              ,	   0x1df0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA1_DBELL"              ,	   0x1df0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA2_DBELL"              ,	   0x1df0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA3_DBELL"              ,	   0x1df0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA4_DBELL"              ,	   0x1df0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA5_DBELL"              ,	   0x1df0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA6_DBELL"              ,	   0x1df0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA7_DBELL"              ,	   0x1df0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"DPI_DMA0_IBUFF_SADDR"        ,	   0x1df0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA1_IBUFF_SADDR"        ,	   0x1df0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA2_IBUFF_SADDR"        ,	   0x1df0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA3_IBUFF_SADDR"        ,	   0x1df0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA4_IBUFF_SADDR"        ,	   0x1df00000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA5_IBUFF_SADDR"        ,	   0x1df00000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA6_IBUFF_SADDR"        ,	   0x1df00000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA7_IBUFF_SADDR"        ,	   0x1df00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"DPI_DMA0_NADDR"              ,	   0x1df0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA1_NADDR"              ,	   0x1df0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA2_NADDR"              ,	   0x1df0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA3_NADDR"              ,	   0x1df0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA4_NADDR"              ,	   0x1df00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA5_NADDR"              ,	   0x1df00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA6_NADDR"              ,	   0x1df00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA7_NADDR"              ,	   0x1df00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"DPI_DMA0_REQBNK0"            ,	   0x1df0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA1_REQBNK0"            ,	   0x1df0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA2_REQBNK0"            ,	   0x1df0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA3_REQBNK0"            ,	   0x1df0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA4_REQBNK0"            ,	   0x1df0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA5_REQBNK0"            ,	   0x1df0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA6_REQBNK0"            ,	   0x1df0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA7_REQBNK0"            ,	   0x1df0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"DPI_DMA0_REQBNK1"            ,	   0x1df0000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA1_REQBNK1"            ,	   0x1df0000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA2_REQBNK1"            ,	   0x1df0000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA3_REQBNK1"            ,	   0x1df0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA4_REQBNK1"            ,	   0x1df00000004a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA5_REQBNK1"            ,	   0x1df00000004a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA6_REQBNK1"            ,	   0x1df00000004b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA7_REQBNK1"            ,	   0x1df00000004b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"DPI_DMA_CONTROL"             ,	   0x1df0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"DPI_DMA_ENG0_EN"             ,	   0x1df0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_DMA_ENG1_EN"             ,	   0x1df0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_DMA_ENG2_EN"             ,	   0x1df0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_DMA_ENG3_EN"             ,	   0x1df0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_DMA_ENG4_EN"             ,	   0x1df00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_DMA_ENG5_EN"             ,	   0x1df00000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"DPI_ENG0_BUF"                ,	   0x1df0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_ENG1_BUF"                ,	   0x1df0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_ENG2_BUF"                ,	   0x1df0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_ENG3_BUF"                ,	   0x1df0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_ENG4_BUF"                ,	   0x1df00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_ENG5_BUF"                ,	   0x1df00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"DPI_INFO_REG"                ,	   0x1df0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"DPI_INT_EN"                  ,	   0x1df0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"DPI_INT_REG"                 ,	   0x1df0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"DPI_PINT_INFO"               ,	   0x1df0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"DPI_PKT_ERR_RSP"             ,	   0x1df0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"DPI_REQ_ERR_RSP"             ,	   0x1df0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"DPI_REQ_ERR_RSP_EN"          ,	   0x1df0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"DPI_REQ_ERR_RST"             ,	   0x1df0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"DPI_REQ_ERR_RST_EN"          ,	   0x1df0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"DPI_REQ_GBL_EN"              ,	   0x1df0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"DPI_SLI_PRT0_CFG"            ,	   0x1df0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"DPI_SLI_PRT1_CFG"            ,	   0x1df0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"DPI_SLI_PRT0_ERR"            ,	   0x1df0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"DPI_SLI_PRT1_ERR"            ,	   0x1df0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"DPI_SLI_PRT0_ERR_INFO"       ,	   0x1df0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"DPI_SLI_PRT1_ERR_INFO"       ,	   0x1df0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"FPA_PACKET_THRESHOLD"        ,	   0x1180028000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"FPA_POOL0_THRESHOLD"         ,	   0x1180028000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL1_THRESHOLD"         ,	   0x1180028000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL2_THRESHOLD"         ,	   0x1180028000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL3_THRESHOLD"         ,	   0x1180028000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL4_THRESHOLD"         ,	   0x1180028000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL5_THRESHOLD"         ,	   0x1180028000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL6_THRESHOLD"         ,	   0x1180028000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_POOL7_THRESHOLD"         ,	   0x1180028000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"FPA_WQE_THRESHOLD"           ,	   0x1180028000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"GMX0_INF_MODE"               ,	   0x11800080007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_SMAC001"                ,	   0x1180008000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_SMAC003"                ,	   0x1180008001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"GMX0_SOFT_BIST"              ,	   0x11800080007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"GMX0_TX_BP"                  ,	   0x11800080004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"GPIO_CLK_QLM0"               ,	   0x10700000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"GPIO_CLK_QLM1"               ,	   0x10700000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"IOB_BIST_STATUS"             ,	   0x11800f00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"IOB_CTL_STATUS"              ,	   0x11800f0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800f0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800f0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800f0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800f0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800f0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800f0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800f0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"IOB_INT_ENB"                 ,	   0x11800f0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"IOB_INT_SUM"                 ,	   0x11800f0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800f0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800f0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800f0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800f0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800f00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800f0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800f00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800f0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800f0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800f0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"IOB_PKT_ERR"                 ,	   0x11800f0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800f00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14f0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14f0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"IPD_BIST_STATUS"             ,	   0x14f00000007f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14f0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"IPD_CLK_COUNT"               ,	   0x14f0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"IPD_CTL_STATUS"              ,	   0x14f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"IPD_INT_ENB"                 ,	   0x14f0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"IPD_INT_SUM"                 ,	   0x14f0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14f0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14f0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14f0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14f0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14f0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14f0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14f0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14f0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14f0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14f0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14f0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14f0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"IPD_PORT40_BP_PAGE_CNT3"     ,	   0x14f00000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT41_BP_PAGE_CNT3"     ,	   0x14f00000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT42_BP_PAGE_CNT3"     ,	   0x14f00000003e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT43_BP_PAGE_CNT3"     ,	   0x14f00000003e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14f0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14f0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14f0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14f00000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"IPD_PORT_BP_COUNTERS3_PAIR40",	   0x14f00000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS3_PAIR41",	   0x14f00000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS3_PAIR42",	   0x14f00000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS3_PAIR43",	   0x14f00000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14f00000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14f00000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14f00000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14f00000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14f00000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14f00000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14f00000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14f00000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14f0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14f0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14f0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14f00000008a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14f00000008a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14f00000008b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14f00000008b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14f00000008c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14f00000008c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14f00000008d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14f00000008d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14f00000008e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14f00000008e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14f00000008f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14f00000008f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14f0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14f0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14f0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14f0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14f0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14f0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14f0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14f0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14f0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14f0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14f0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14f0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14f0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14f0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14f0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14f0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14f0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14f0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14f0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14f0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14f00000010a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14f00000010a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14f00000010b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14f00000010b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14f00000010c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14f00000010c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14f00000010d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14f00000010d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14f00000010e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14f00000010e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14f00000010f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14f00000010f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14f0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14f0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14f0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14f0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14f0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14f0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14f0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14f0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14f0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14f0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14f0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14f0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14f0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14f0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14f0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14f0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14f0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14f0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14f0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14f0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14f00000011a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14f00000011a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14f00000011b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14f00000011b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14f00000011c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14f00000011c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14f00000011d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14f00000011d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14f00000011e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14f00000011e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14f00000011f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14f00000011f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14f0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14f0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14f0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14f0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14f0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14f0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14f0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14f0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14f0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14f0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14f0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14f0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14f0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14f0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14f0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14f0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14f0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_320_CNT"        ,	   0x14f0000001288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_321_CNT"        ,	   0x14f0000001290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_322_CNT"        ,	   0x14f0000001298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_323_CNT"        ,	   0x14f00000012a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_324_CNT"        ,	   0x14f00000012a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_325_CNT"        ,	   0x14f00000012b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_326_CNT"        ,	   0x14f00000012b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_327_CNT"        ,	   0x14f00000012c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_328_CNT"        ,	   0x14f00000012c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_329_CNT"        ,	   0x14f00000012d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_330_CNT"        ,	   0x14f00000012d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_331_CNT"        ,	   0x14f00000012e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_332_CNT"        ,	   0x14f00000012e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_333_CNT"        ,	   0x14f00000012f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_334_CNT"        ,	   0x14f00000012f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_335_CNT"        ,	   0x14f0000001300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_336_CNT"        ,	   0x14f0000001308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_337_CNT"        ,	   0x14f0000001310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_338_CNT"        ,	   0x14f0000001318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_339_CNT"        ,	   0x14f0000001320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_340_CNT"        ,	   0x14f0000001328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_341_CNT"        ,	   0x14f0000001330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_342_CNT"        ,	   0x14f0000001338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_343_CNT"        ,	   0x14f0000001340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_344_CNT"        ,	   0x14f0000001348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_345_CNT"        ,	   0x14f0000001350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_346_CNT"        ,	   0x14f0000001358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_347_CNT"        ,	   0x14f0000001360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_348_CNT"        ,	   0x14f0000001368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_349_CNT"        ,	   0x14f0000001370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_350_CNT"        ,	   0x14f0000001378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_351_CNT"        ,	   0x14f0000001380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14f0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14f0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT5"           ,	   0x14f0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14f0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14f0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PORT_QOS_INT_ENB5"       ,	   0x14f0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14f0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14f0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"IPD_PTR_COUNT"               ,	   0x14f0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14f0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14f0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14f0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14f0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14f0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14f0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14f00000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14f00000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14f00000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14f0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14f00000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14f00000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14f00000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14f00000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14f00000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14f00000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14f0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14f0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14f0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14f0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14f0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14f0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14f0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14f0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"L2C_BIG_CTL"                 ,	   0x1180080800030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"L2C_BST"                     ,	   0x11800808007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"L2C_BST_MEM0"                ,	   0x1180080c007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"L2C_BST_TDT0"                ,	   0x1180080a007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"L2C_BST_TTG0"                ,	   0x1180080a007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"L2C_COP0_MAP0"               ,	   0x1180080940000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1"               ,	   0x1180080940008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP2"               ,	   0x1180080940010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP3"               ,	   0x1180080940018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP4"               ,	   0x1180080940020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP5"               ,	   0x1180080940028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP6"               ,	   0x1180080940030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP7"               ,	   0x1180080940038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP8"               ,	   0x1180080940040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP9"               ,	   0x1180080940048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP10"              ,	   0x1180080940050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP11"              ,	   0x1180080940058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP12"              ,	   0x1180080940060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP13"              ,	   0x1180080940068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP14"              ,	   0x1180080940070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP15"              ,	   0x1180080940078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16"              ,	   0x1180080940080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP17"              ,	   0x1180080940088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP18"              ,	   0x1180080940090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP19"              ,	   0x1180080940098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP20"              ,	   0x11800809400a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP21"              ,	   0x11800809400a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP22"              ,	   0x11800809400b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP23"              ,	   0x11800809400b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP24"              ,	   0x11800809400c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP25"              ,	   0x11800809400c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP26"              ,	   0x11800809400d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP27"              ,	   0x11800809400d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP28"              ,	   0x11800809400e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP29"              ,	   0x11800809400e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP30"              ,	   0x11800809400f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP31"              ,	   0x11800809400f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP32"              ,	   0x1180080940100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP33"              ,	   0x1180080940108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP34"              ,	   0x1180080940110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP35"              ,	   0x1180080940118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP36"              ,	   0x1180080940120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP37"              ,	   0x1180080940128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP38"              ,	   0x1180080940130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP39"              ,	   0x1180080940138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP40"              ,	   0x1180080940140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP41"              ,	   0x1180080940148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP42"              ,	   0x1180080940150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP43"              ,	   0x1180080940158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP44"              ,	   0x1180080940160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP45"              ,	   0x1180080940168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP46"              ,	   0x1180080940170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP47"              ,	   0x1180080940178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP48"              ,	   0x1180080940180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP49"              ,	   0x1180080940188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP50"              ,	   0x1180080940190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP51"              ,	   0x1180080940198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP52"              ,	   0x11800809401a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP53"              ,	   0x11800809401a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP54"              ,	   0x11800809401b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP55"              ,	   0x11800809401b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP56"              ,	   0x11800809401c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP57"              ,	   0x11800809401c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP58"              ,	   0x11800809401d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP59"              ,	   0x11800809401d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP60"              ,	   0x11800809401e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP61"              ,	   0x11800809401e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP62"              ,	   0x11800809401f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP63"              ,	   0x11800809401f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP64"              ,	   0x1180080940200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP65"              ,	   0x1180080940208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP66"              ,	   0x1180080940210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP67"              ,	   0x1180080940218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP68"              ,	   0x1180080940220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP69"              ,	   0x1180080940228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP70"              ,	   0x1180080940230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP71"              ,	   0x1180080940238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP72"              ,	   0x1180080940240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP73"              ,	   0x1180080940248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP74"              ,	   0x1180080940250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP75"              ,	   0x1180080940258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP76"              ,	   0x1180080940260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP77"              ,	   0x1180080940268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP78"              ,	   0x1180080940270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP79"              ,	   0x1180080940278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP80"              ,	   0x1180080940280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP81"              ,	   0x1180080940288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP82"              ,	   0x1180080940290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP83"              ,	   0x1180080940298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP84"              ,	   0x11800809402a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP85"              ,	   0x11800809402a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP86"              ,	   0x11800809402b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP87"              ,	   0x11800809402b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP88"              ,	   0x11800809402c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP89"              ,	   0x11800809402c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP90"              ,	   0x11800809402d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP91"              ,	   0x11800809402d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP92"              ,	   0x11800809402e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP93"              ,	   0x11800809402e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP94"              ,	   0x11800809402f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP95"              ,	   0x11800809402f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP96"              ,	   0x1180080940300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP97"              ,	   0x1180080940308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP98"              ,	   0x1180080940310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP99"              ,	   0x1180080940318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP100"             ,	   0x1180080940320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP101"             ,	   0x1180080940328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP102"             ,	   0x1180080940330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP103"             ,	   0x1180080940338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP104"             ,	   0x1180080940340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP105"             ,	   0x1180080940348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP106"             ,	   0x1180080940350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP107"             ,	   0x1180080940358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP108"             ,	   0x1180080940360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP109"             ,	   0x1180080940368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP110"             ,	   0x1180080940370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP111"             ,	   0x1180080940378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP112"             ,	   0x1180080940380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP113"             ,	   0x1180080940388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP114"             ,	   0x1180080940390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP115"             ,	   0x1180080940398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP116"             ,	   0x11800809403a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP117"             ,	   0x11800809403a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP118"             ,	   0x11800809403b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP119"             ,	   0x11800809403b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP120"             ,	   0x11800809403c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP121"             ,	   0x11800809403c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP122"             ,	   0x11800809403d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP123"             ,	   0x11800809403d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP124"             ,	   0x11800809403e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP125"             ,	   0x11800809403e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP126"             ,	   0x11800809403f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP127"             ,	   0x11800809403f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP128"             ,	   0x1180080940400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP129"             ,	   0x1180080940408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP130"             ,	   0x1180080940410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP131"             ,	   0x1180080940418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP132"             ,	   0x1180080940420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP133"             ,	   0x1180080940428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP134"             ,	   0x1180080940430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP135"             ,	   0x1180080940438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP136"             ,	   0x1180080940440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP137"             ,	   0x1180080940448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP138"             ,	   0x1180080940450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP139"             ,	   0x1180080940458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP140"             ,	   0x1180080940460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP141"             ,	   0x1180080940468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP142"             ,	   0x1180080940470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP143"             ,	   0x1180080940478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP144"             ,	   0x1180080940480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP145"             ,	   0x1180080940488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP146"             ,	   0x1180080940490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP147"             ,	   0x1180080940498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP148"             ,	   0x11800809404a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP149"             ,	   0x11800809404a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP150"             ,	   0x11800809404b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP151"             ,	   0x11800809404b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP152"             ,	   0x11800809404c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP153"             ,	   0x11800809404c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP154"             ,	   0x11800809404d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP155"             ,	   0x11800809404d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP156"             ,	   0x11800809404e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP157"             ,	   0x11800809404e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP158"             ,	   0x11800809404f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP159"             ,	   0x11800809404f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP160"             ,	   0x1180080940500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP161"             ,	   0x1180080940508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP162"             ,	   0x1180080940510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP163"             ,	   0x1180080940518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP164"             ,	   0x1180080940520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP165"             ,	   0x1180080940528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP166"             ,	   0x1180080940530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP167"             ,	   0x1180080940538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP168"             ,	   0x1180080940540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP169"             ,	   0x1180080940548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP170"             ,	   0x1180080940550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP171"             ,	   0x1180080940558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP172"             ,	   0x1180080940560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP173"             ,	   0x1180080940568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP174"             ,	   0x1180080940570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP175"             ,	   0x1180080940578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP176"             ,	   0x1180080940580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP177"             ,	   0x1180080940588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP178"             ,	   0x1180080940590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP179"             ,	   0x1180080940598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP180"             ,	   0x11800809405a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP181"             ,	   0x11800809405a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP182"             ,	   0x11800809405b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP183"             ,	   0x11800809405b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP184"             ,	   0x11800809405c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP185"             ,	   0x11800809405c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP186"             ,	   0x11800809405d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP187"             ,	   0x11800809405d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP188"             ,	   0x11800809405e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP189"             ,	   0x11800809405e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP190"             ,	   0x11800809405f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP191"             ,	   0x11800809405f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP192"             ,	   0x1180080940600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP193"             ,	   0x1180080940608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP194"             ,	   0x1180080940610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP195"             ,	   0x1180080940618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP196"             ,	   0x1180080940620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP197"             ,	   0x1180080940628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP198"             ,	   0x1180080940630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP199"             ,	   0x1180080940638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP200"             ,	   0x1180080940640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP201"             ,	   0x1180080940648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP202"             ,	   0x1180080940650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP203"             ,	   0x1180080940658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP204"             ,	   0x1180080940660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP205"             ,	   0x1180080940668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP206"             ,	   0x1180080940670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP207"             ,	   0x1180080940678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP208"             ,	   0x1180080940680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP209"             ,	   0x1180080940688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP210"             ,	   0x1180080940690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP211"             ,	   0x1180080940698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP212"             ,	   0x11800809406a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP213"             ,	   0x11800809406a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP214"             ,	   0x11800809406b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP215"             ,	   0x11800809406b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP216"             ,	   0x11800809406c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP217"             ,	   0x11800809406c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP218"             ,	   0x11800809406d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP219"             ,	   0x11800809406d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP220"             ,	   0x11800809406e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP221"             ,	   0x11800809406e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP222"             ,	   0x11800809406f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP223"             ,	   0x11800809406f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP224"             ,	   0x1180080940700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP225"             ,	   0x1180080940708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP226"             ,	   0x1180080940710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP227"             ,	   0x1180080940718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP228"             ,	   0x1180080940720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP229"             ,	   0x1180080940728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP230"             ,	   0x1180080940730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP231"             ,	   0x1180080940738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP232"             ,	   0x1180080940740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP233"             ,	   0x1180080940748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP234"             ,	   0x1180080940750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP235"             ,	   0x1180080940758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP236"             ,	   0x1180080940760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP237"             ,	   0x1180080940768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP238"             ,	   0x1180080940770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP239"             ,	   0x1180080940778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP240"             ,	   0x1180080940780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP241"             ,	   0x1180080940788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP242"             ,	   0x1180080940790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP243"             ,	   0x1180080940798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP244"             ,	   0x11800809407a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP245"             ,	   0x11800809407a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP246"             ,	   0x11800809407b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP247"             ,	   0x11800809407b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP248"             ,	   0x11800809407c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP249"             ,	   0x11800809407c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP250"             ,	   0x11800809407d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP251"             ,	   0x11800809407d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP252"             ,	   0x11800809407e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP253"             ,	   0x11800809407e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP254"             ,	   0x11800809407f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP255"             ,	   0x11800809407f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP256"             ,	   0x1180080940800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP257"             ,	   0x1180080940808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP258"             ,	   0x1180080940810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP259"             ,	   0x1180080940818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP260"             ,	   0x1180080940820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP261"             ,	   0x1180080940828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP262"             ,	   0x1180080940830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP263"             ,	   0x1180080940838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP264"             ,	   0x1180080940840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP265"             ,	   0x1180080940848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP266"             ,	   0x1180080940850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP267"             ,	   0x1180080940858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP268"             ,	   0x1180080940860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP269"             ,	   0x1180080940868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP270"             ,	   0x1180080940870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP271"             ,	   0x1180080940878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP272"             ,	   0x1180080940880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP273"             ,	   0x1180080940888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP274"             ,	   0x1180080940890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP275"             ,	   0x1180080940898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP276"             ,	   0x11800809408a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP277"             ,	   0x11800809408a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP278"             ,	   0x11800809408b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP279"             ,	   0x11800809408b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP280"             ,	   0x11800809408c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP281"             ,	   0x11800809408c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP282"             ,	   0x11800809408d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP283"             ,	   0x11800809408d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP284"             ,	   0x11800809408e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP285"             ,	   0x11800809408e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP286"             ,	   0x11800809408f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP287"             ,	   0x11800809408f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP288"             ,	   0x1180080940900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP289"             ,	   0x1180080940908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP290"             ,	   0x1180080940910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP291"             ,	   0x1180080940918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP292"             ,	   0x1180080940920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP293"             ,	   0x1180080940928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP294"             ,	   0x1180080940930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP295"             ,	   0x1180080940938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP296"             ,	   0x1180080940940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP297"             ,	   0x1180080940948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP298"             ,	   0x1180080940950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP299"             ,	   0x1180080940958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP300"             ,	   0x1180080940960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP301"             ,	   0x1180080940968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP302"             ,	   0x1180080940970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP303"             ,	   0x1180080940978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP304"             ,	   0x1180080940980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP305"             ,	   0x1180080940988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP306"             ,	   0x1180080940990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP307"             ,	   0x1180080940998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP308"             ,	   0x11800809409a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP309"             ,	   0x11800809409a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP310"             ,	   0x11800809409b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP311"             ,	   0x11800809409b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP312"             ,	   0x11800809409c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP313"             ,	   0x11800809409c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP314"             ,	   0x11800809409d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP315"             ,	   0x11800809409d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP316"             ,	   0x11800809409e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP317"             ,	   0x11800809409e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP318"             ,	   0x11800809409f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP319"             ,	   0x11800809409f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP320"             ,	   0x1180080940a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP321"             ,	   0x1180080940a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP322"             ,	   0x1180080940a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP323"             ,	   0x1180080940a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP324"             ,	   0x1180080940a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP325"             ,	   0x1180080940a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP326"             ,	   0x1180080940a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP327"             ,	   0x1180080940a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP328"             ,	   0x1180080940a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP329"             ,	   0x1180080940a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP330"             ,	   0x1180080940a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP331"             ,	   0x1180080940a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP332"             ,	   0x1180080940a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP333"             ,	   0x1180080940a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP334"             ,	   0x1180080940a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP335"             ,	   0x1180080940a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP336"             ,	   0x1180080940a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP337"             ,	   0x1180080940a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP338"             ,	   0x1180080940a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP339"             ,	   0x1180080940a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP340"             ,	   0x1180080940aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP341"             ,	   0x1180080940aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP342"             ,	   0x1180080940ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP343"             ,	   0x1180080940ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP344"             ,	   0x1180080940ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP345"             ,	   0x1180080940ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP346"             ,	   0x1180080940ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP347"             ,	   0x1180080940ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP348"             ,	   0x1180080940ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP349"             ,	   0x1180080940ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP350"             ,	   0x1180080940af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP351"             ,	   0x1180080940af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP352"             ,	   0x1180080940b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP353"             ,	   0x1180080940b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP354"             ,	   0x1180080940b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP355"             ,	   0x1180080940b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP356"             ,	   0x1180080940b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP357"             ,	   0x1180080940b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP358"             ,	   0x1180080940b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP359"             ,	   0x1180080940b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP360"             ,	   0x1180080940b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP361"             ,	   0x1180080940b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP362"             ,	   0x1180080940b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP363"             ,	   0x1180080940b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP364"             ,	   0x1180080940b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP365"             ,	   0x1180080940b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP366"             ,	   0x1180080940b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP367"             ,	   0x1180080940b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP368"             ,	   0x1180080940b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP369"             ,	   0x1180080940b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP370"             ,	   0x1180080940b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP371"             ,	   0x1180080940b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP372"             ,	   0x1180080940ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP373"             ,	   0x1180080940ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP374"             ,	   0x1180080940bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP375"             ,	   0x1180080940bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP376"             ,	   0x1180080940bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP377"             ,	   0x1180080940bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP378"             ,	   0x1180080940bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP379"             ,	   0x1180080940bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP380"             ,	   0x1180080940be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP381"             ,	   0x1180080940be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP382"             ,	   0x1180080940bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP383"             ,	   0x1180080940bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP384"             ,	   0x1180080940c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP385"             ,	   0x1180080940c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP386"             ,	   0x1180080940c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP387"             ,	   0x1180080940c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP388"             ,	   0x1180080940c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP389"             ,	   0x1180080940c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP390"             ,	   0x1180080940c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP391"             ,	   0x1180080940c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP392"             ,	   0x1180080940c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP393"             ,	   0x1180080940c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP394"             ,	   0x1180080940c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP395"             ,	   0x1180080940c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP396"             ,	   0x1180080940c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP397"             ,	   0x1180080940c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP398"             ,	   0x1180080940c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP399"             ,	   0x1180080940c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP400"             ,	   0x1180080940c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP401"             ,	   0x1180080940c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP402"             ,	   0x1180080940c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP403"             ,	   0x1180080940c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP404"             ,	   0x1180080940ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP405"             ,	   0x1180080940ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP406"             ,	   0x1180080940cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP407"             ,	   0x1180080940cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP408"             ,	   0x1180080940cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP409"             ,	   0x1180080940cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP410"             ,	   0x1180080940cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP411"             ,	   0x1180080940cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP412"             ,	   0x1180080940ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP413"             ,	   0x1180080940ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP414"             ,	   0x1180080940cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP415"             ,	   0x1180080940cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP416"             ,	   0x1180080940d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP417"             ,	   0x1180080940d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP418"             ,	   0x1180080940d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP419"             ,	   0x1180080940d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP420"             ,	   0x1180080940d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP421"             ,	   0x1180080940d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP422"             ,	   0x1180080940d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP423"             ,	   0x1180080940d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP424"             ,	   0x1180080940d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP425"             ,	   0x1180080940d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP426"             ,	   0x1180080940d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP427"             ,	   0x1180080940d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP428"             ,	   0x1180080940d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP429"             ,	   0x1180080940d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP430"             ,	   0x1180080940d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP431"             ,	   0x1180080940d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP432"             ,	   0x1180080940d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP433"             ,	   0x1180080940d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP434"             ,	   0x1180080940d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP435"             ,	   0x1180080940d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP436"             ,	   0x1180080940da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP437"             ,	   0x1180080940da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP438"             ,	   0x1180080940db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP439"             ,	   0x1180080940db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP440"             ,	   0x1180080940dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP441"             ,	   0x1180080940dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP442"             ,	   0x1180080940dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP443"             ,	   0x1180080940dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP444"             ,	   0x1180080940de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP445"             ,	   0x1180080940de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP446"             ,	   0x1180080940df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP447"             ,	   0x1180080940df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP448"             ,	   0x1180080940e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP449"             ,	   0x1180080940e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP450"             ,	   0x1180080940e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP451"             ,	   0x1180080940e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP452"             ,	   0x1180080940e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP453"             ,	   0x1180080940e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP454"             ,	   0x1180080940e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP455"             ,	   0x1180080940e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP456"             ,	   0x1180080940e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP457"             ,	   0x1180080940e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP458"             ,	   0x1180080940e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP459"             ,	   0x1180080940e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP460"             ,	   0x1180080940e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP461"             ,	   0x1180080940e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP462"             ,	   0x1180080940e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP463"             ,	   0x1180080940e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP464"             ,	   0x1180080940e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP465"             ,	   0x1180080940e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP466"             ,	   0x1180080940e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP467"             ,	   0x1180080940e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP468"             ,	   0x1180080940ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP469"             ,	   0x1180080940ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP470"             ,	   0x1180080940eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP471"             ,	   0x1180080940eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP472"             ,	   0x1180080940ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP473"             ,	   0x1180080940ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP474"             ,	   0x1180080940ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP475"             ,	   0x1180080940ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP476"             ,	   0x1180080940ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP477"             ,	   0x1180080940ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP478"             ,	   0x1180080940ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP479"             ,	   0x1180080940ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP480"             ,	   0x1180080940f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP481"             ,	   0x1180080940f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP482"             ,	   0x1180080940f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP483"             ,	   0x1180080940f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP484"             ,	   0x1180080940f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP485"             ,	   0x1180080940f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP486"             ,	   0x1180080940f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP487"             ,	   0x1180080940f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP488"             ,	   0x1180080940f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP489"             ,	   0x1180080940f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP490"             ,	   0x1180080940f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP491"             ,	   0x1180080940f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP492"             ,	   0x1180080940f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP493"             ,	   0x1180080940f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP494"             ,	   0x1180080940f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP495"             ,	   0x1180080940f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP496"             ,	   0x1180080940f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP497"             ,	   0x1180080940f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP498"             ,	   0x1180080940f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP499"             ,	   0x1180080940f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP500"             ,	   0x1180080940fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP501"             ,	   0x1180080940fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP502"             ,	   0x1180080940fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP503"             ,	   0x1180080940fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP504"             ,	   0x1180080940fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP505"             ,	   0x1180080940fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP506"             ,	   0x1180080940fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP507"             ,	   0x1180080940fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP508"             ,	   0x1180080940fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP509"             ,	   0x1180080940fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP510"             ,	   0x1180080940ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP511"             ,	   0x1180080940ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP512"             ,	   0x1180080941000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP513"             ,	   0x1180080941008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP514"             ,	   0x1180080941010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP515"             ,	   0x1180080941018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP516"             ,	   0x1180080941020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP517"             ,	   0x1180080941028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP518"             ,	   0x1180080941030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP519"             ,	   0x1180080941038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP520"             ,	   0x1180080941040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP521"             ,	   0x1180080941048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP522"             ,	   0x1180080941050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP523"             ,	   0x1180080941058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP524"             ,	   0x1180080941060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP525"             ,	   0x1180080941068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP526"             ,	   0x1180080941070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP527"             ,	   0x1180080941078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP528"             ,	   0x1180080941080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP529"             ,	   0x1180080941088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP530"             ,	   0x1180080941090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP531"             ,	   0x1180080941098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP532"             ,	   0x11800809410a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP533"             ,	   0x11800809410a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP534"             ,	   0x11800809410b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP535"             ,	   0x11800809410b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP536"             ,	   0x11800809410c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP537"             ,	   0x11800809410c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP538"             ,	   0x11800809410d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP539"             ,	   0x11800809410d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP540"             ,	   0x11800809410e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP541"             ,	   0x11800809410e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP542"             ,	   0x11800809410f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP543"             ,	   0x11800809410f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP544"             ,	   0x1180080941100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP545"             ,	   0x1180080941108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP546"             ,	   0x1180080941110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP547"             ,	   0x1180080941118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP548"             ,	   0x1180080941120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP549"             ,	   0x1180080941128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP550"             ,	   0x1180080941130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP551"             ,	   0x1180080941138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP552"             ,	   0x1180080941140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP553"             ,	   0x1180080941148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP554"             ,	   0x1180080941150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP555"             ,	   0x1180080941158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP556"             ,	   0x1180080941160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP557"             ,	   0x1180080941168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP558"             ,	   0x1180080941170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP559"             ,	   0x1180080941178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP560"             ,	   0x1180080941180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP561"             ,	   0x1180080941188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP562"             ,	   0x1180080941190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP563"             ,	   0x1180080941198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP564"             ,	   0x11800809411a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP565"             ,	   0x11800809411a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP566"             ,	   0x11800809411b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP567"             ,	   0x11800809411b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP568"             ,	   0x11800809411c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP569"             ,	   0x11800809411c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP570"             ,	   0x11800809411d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP571"             ,	   0x11800809411d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP572"             ,	   0x11800809411e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP573"             ,	   0x11800809411e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP574"             ,	   0x11800809411f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP575"             ,	   0x11800809411f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP576"             ,	   0x1180080941200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP577"             ,	   0x1180080941208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP578"             ,	   0x1180080941210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP579"             ,	   0x1180080941218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP580"             ,	   0x1180080941220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP581"             ,	   0x1180080941228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP582"             ,	   0x1180080941230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP583"             ,	   0x1180080941238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP584"             ,	   0x1180080941240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP585"             ,	   0x1180080941248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP586"             ,	   0x1180080941250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP587"             ,	   0x1180080941258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP588"             ,	   0x1180080941260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP589"             ,	   0x1180080941268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP590"             ,	   0x1180080941270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP591"             ,	   0x1180080941278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP592"             ,	   0x1180080941280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP593"             ,	   0x1180080941288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP594"             ,	   0x1180080941290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP595"             ,	   0x1180080941298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP596"             ,	   0x11800809412a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP597"             ,	   0x11800809412a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP598"             ,	   0x11800809412b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP599"             ,	   0x11800809412b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP600"             ,	   0x11800809412c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP601"             ,	   0x11800809412c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP602"             ,	   0x11800809412d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP603"             ,	   0x11800809412d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP604"             ,	   0x11800809412e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP605"             ,	   0x11800809412e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP606"             ,	   0x11800809412f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP607"             ,	   0x11800809412f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP608"             ,	   0x1180080941300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP609"             ,	   0x1180080941308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP610"             ,	   0x1180080941310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP611"             ,	   0x1180080941318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP612"             ,	   0x1180080941320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP613"             ,	   0x1180080941328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP614"             ,	   0x1180080941330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP615"             ,	   0x1180080941338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP616"             ,	   0x1180080941340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP617"             ,	   0x1180080941348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP618"             ,	   0x1180080941350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP619"             ,	   0x1180080941358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP620"             ,	   0x1180080941360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP621"             ,	   0x1180080941368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP622"             ,	   0x1180080941370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP623"             ,	   0x1180080941378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP624"             ,	   0x1180080941380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP625"             ,	   0x1180080941388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP626"             ,	   0x1180080941390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP627"             ,	   0x1180080941398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP628"             ,	   0x11800809413a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP629"             ,	   0x11800809413a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP630"             ,	   0x11800809413b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP631"             ,	   0x11800809413b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP632"             ,	   0x11800809413c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP633"             ,	   0x11800809413c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP634"             ,	   0x11800809413d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP635"             ,	   0x11800809413d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP636"             ,	   0x11800809413e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP637"             ,	   0x11800809413e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP638"             ,	   0x11800809413f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP639"             ,	   0x11800809413f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP640"             ,	   0x1180080941400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP641"             ,	   0x1180080941408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP642"             ,	   0x1180080941410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP643"             ,	   0x1180080941418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP644"             ,	   0x1180080941420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP645"             ,	   0x1180080941428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP646"             ,	   0x1180080941430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP647"             ,	   0x1180080941438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP648"             ,	   0x1180080941440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP649"             ,	   0x1180080941448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP650"             ,	   0x1180080941450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP651"             ,	   0x1180080941458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP652"             ,	   0x1180080941460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP653"             ,	   0x1180080941468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP654"             ,	   0x1180080941470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP655"             ,	   0x1180080941478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP656"             ,	   0x1180080941480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP657"             ,	   0x1180080941488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP658"             ,	   0x1180080941490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP659"             ,	   0x1180080941498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP660"             ,	   0x11800809414a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP661"             ,	   0x11800809414a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP662"             ,	   0x11800809414b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP663"             ,	   0x11800809414b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP664"             ,	   0x11800809414c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP665"             ,	   0x11800809414c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP666"             ,	   0x11800809414d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP667"             ,	   0x11800809414d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP668"             ,	   0x11800809414e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP669"             ,	   0x11800809414e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP670"             ,	   0x11800809414f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP671"             ,	   0x11800809414f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP672"             ,	   0x1180080941500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP673"             ,	   0x1180080941508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP674"             ,	   0x1180080941510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP675"             ,	   0x1180080941518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP676"             ,	   0x1180080941520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP677"             ,	   0x1180080941528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP678"             ,	   0x1180080941530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP679"             ,	   0x1180080941538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP680"             ,	   0x1180080941540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP681"             ,	   0x1180080941548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP682"             ,	   0x1180080941550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP683"             ,	   0x1180080941558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP684"             ,	   0x1180080941560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP685"             ,	   0x1180080941568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP686"             ,	   0x1180080941570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP687"             ,	   0x1180080941578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP688"             ,	   0x1180080941580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP689"             ,	   0x1180080941588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP690"             ,	   0x1180080941590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP691"             ,	   0x1180080941598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP692"             ,	   0x11800809415a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP693"             ,	   0x11800809415a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP694"             ,	   0x11800809415b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP695"             ,	   0x11800809415b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP696"             ,	   0x11800809415c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP697"             ,	   0x11800809415c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP698"             ,	   0x11800809415d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP699"             ,	   0x11800809415d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP700"             ,	   0x11800809415e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP701"             ,	   0x11800809415e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP702"             ,	   0x11800809415f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP703"             ,	   0x11800809415f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP704"             ,	   0x1180080941600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP705"             ,	   0x1180080941608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP706"             ,	   0x1180080941610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP707"             ,	   0x1180080941618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP708"             ,	   0x1180080941620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP709"             ,	   0x1180080941628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP710"             ,	   0x1180080941630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP711"             ,	   0x1180080941638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP712"             ,	   0x1180080941640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP713"             ,	   0x1180080941648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP714"             ,	   0x1180080941650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP715"             ,	   0x1180080941658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP716"             ,	   0x1180080941660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP717"             ,	   0x1180080941668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP718"             ,	   0x1180080941670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP719"             ,	   0x1180080941678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP720"             ,	   0x1180080941680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP721"             ,	   0x1180080941688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP722"             ,	   0x1180080941690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP723"             ,	   0x1180080941698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP724"             ,	   0x11800809416a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP725"             ,	   0x11800809416a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP726"             ,	   0x11800809416b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP727"             ,	   0x11800809416b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP728"             ,	   0x11800809416c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP729"             ,	   0x11800809416c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP730"             ,	   0x11800809416d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP731"             ,	   0x11800809416d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP732"             ,	   0x11800809416e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP733"             ,	   0x11800809416e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP734"             ,	   0x11800809416f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP735"             ,	   0x11800809416f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP736"             ,	   0x1180080941700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP737"             ,	   0x1180080941708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP738"             ,	   0x1180080941710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP739"             ,	   0x1180080941718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP740"             ,	   0x1180080941720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP741"             ,	   0x1180080941728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP742"             ,	   0x1180080941730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP743"             ,	   0x1180080941738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP744"             ,	   0x1180080941740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP745"             ,	   0x1180080941748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP746"             ,	   0x1180080941750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP747"             ,	   0x1180080941758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP748"             ,	   0x1180080941760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP749"             ,	   0x1180080941768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP750"             ,	   0x1180080941770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP751"             ,	   0x1180080941778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP752"             ,	   0x1180080941780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP753"             ,	   0x1180080941788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP754"             ,	   0x1180080941790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP755"             ,	   0x1180080941798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP756"             ,	   0x11800809417a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP757"             ,	   0x11800809417a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP758"             ,	   0x11800809417b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP759"             ,	   0x11800809417b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP760"             ,	   0x11800809417c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP761"             ,	   0x11800809417c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP762"             ,	   0x11800809417d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP763"             ,	   0x11800809417d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP764"             ,	   0x11800809417e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP765"             ,	   0x11800809417e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP766"             ,	   0x11800809417f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP767"             ,	   0x11800809417f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP768"             ,	   0x1180080941800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP769"             ,	   0x1180080941808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP770"             ,	   0x1180080941810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP771"             ,	   0x1180080941818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP772"             ,	   0x1180080941820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP773"             ,	   0x1180080941828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP774"             ,	   0x1180080941830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP775"             ,	   0x1180080941838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP776"             ,	   0x1180080941840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP777"             ,	   0x1180080941848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP778"             ,	   0x1180080941850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP779"             ,	   0x1180080941858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP780"             ,	   0x1180080941860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP781"             ,	   0x1180080941868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP782"             ,	   0x1180080941870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP783"             ,	   0x1180080941878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP784"             ,	   0x1180080941880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP785"             ,	   0x1180080941888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP786"             ,	   0x1180080941890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP787"             ,	   0x1180080941898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP788"             ,	   0x11800809418a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP789"             ,	   0x11800809418a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP790"             ,	   0x11800809418b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP791"             ,	   0x11800809418b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP792"             ,	   0x11800809418c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP793"             ,	   0x11800809418c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP794"             ,	   0x11800809418d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP795"             ,	   0x11800809418d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP796"             ,	   0x11800809418e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP797"             ,	   0x11800809418e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP798"             ,	   0x11800809418f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP799"             ,	   0x11800809418f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP800"             ,	   0x1180080941900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP801"             ,	   0x1180080941908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP802"             ,	   0x1180080941910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP803"             ,	   0x1180080941918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP804"             ,	   0x1180080941920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP805"             ,	   0x1180080941928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP806"             ,	   0x1180080941930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP807"             ,	   0x1180080941938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP808"             ,	   0x1180080941940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP809"             ,	   0x1180080941948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP810"             ,	   0x1180080941950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP811"             ,	   0x1180080941958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP812"             ,	   0x1180080941960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP813"             ,	   0x1180080941968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP814"             ,	   0x1180080941970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP815"             ,	   0x1180080941978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP816"             ,	   0x1180080941980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP817"             ,	   0x1180080941988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP818"             ,	   0x1180080941990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP819"             ,	   0x1180080941998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP820"             ,	   0x11800809419a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP821"             ,	   0x11800809419a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP822"             ,	   0x11800809419b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP823"             ,	   0x11800809419b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP824"             ,	   0x11800809419c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP825"             ,	   0x11800809419c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP826"             ,	   0x11800809419d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP827"             ,	   0x11800809419d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP828"             ,	   0x11800809419e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP829"             ,	   0x11800809419e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP830"             ,	   0x11800809419f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP831"             ,	   0x11800809419f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP832"             ,	   0x1180080941a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP833"             ,	   0x1180080941a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP834"             ,	   0x1180080941a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP835"             ,	   0x1180080941a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP836"             ,	   0x1180080941a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP837"             ,	   0x1180080941a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP838"             ,	   0x1180080941a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP839"             ,	   0x1180080941a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP840"             ,	   0x1180080941a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP841"             ,	   0x1180080941a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP842"             ,	   0x1180080941a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP843"             ,	   0x1180080941a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP844"             ,	   0x1180080941a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP845"             ,	   0x1180080941a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP846"             ,	   0x1180080941a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP847"             ,	   0x1180080941a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP848"             ,	   0x1180080941a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP849"             ,	   0x1180080941a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP850"             ,	   0x1180080941a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP851"             ,	   0x1180080941a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP852"             ,	   0x1180080941aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP853"             ,	   0x1180080941aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP854"             ,	   0x1180080941ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP855"             ,	   0x1180080941ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP856"             ,	   0x1180080941ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP857"             ,	   0x1180080941ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP858"             ,	   0x1180080941ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP859"             ,	   0x1180080941ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP860"             ,	   0x1180080941ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP861"             ,	   0x1180080941ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP862"             ,	   0x1180080941af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP863"             ,	   0x1180080941af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP864"             ,	   0x1180080941b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP865"             ,	   0x1180080941b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP866"             ,	   0x1180080941b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP867"             ,	   0x1180080941b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP868"             ,	   0x1180080941b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP869"             ,	   0x1180080941b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP870"             ,	   0x1180080941b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP871"             ,	   0x1180080941b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP872"             ,	   0x1180080941b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP873"             ,	   0x1180080941b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP874"             ,	   0x1180080941b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP875"             ,	   0x1180080941b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP876"             ,	   0x1180080941b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP877"             ,	   0x1180080941b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP878"             ,	   0x1180080941b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP879"             ,	   0x1180080941b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP880"             ,	   0x1180080941b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP881"             ,	   0x1180080941b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP882"             ,	   0x1180080941b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP883"             ,	   0x1180080941b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP884"             ,	   0x1180080941ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP885"             ,	   0x1180080941ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP886"             ,	   0x1180080941bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP887"             ,	   0x1180080941bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP888"             ,	   0x1180080941bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP889"             ,	   0x1180080941bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP890"             ,	   0x1180080941bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP891"             ,	   0x1180080941bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP892"             ,	   0x1180080941be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP893"             ,	   0x1180080941be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP894"             ,	   0x1180080941bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP895"             ,	   0x1180080941bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP896"             ,	   0x1180080941c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP897"             ,	   0x1180080941c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP898"             ,	   0x1180080941c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP899"             ,	   0x1180080941c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP900"             ,	   0x1180080941c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP901"             ,	   0x1180080941c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP902"             ,	   0x1180080941c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP903"             ,	   0x1180080941c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP904"             ,	   0x1180080941c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP905"             ,	   0x1180080941c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP906"             ,	   0x1180080941c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP907"             ,	   0x1180080941c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP908"             ,	   0x1180080941c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP909"             ,	   0x1180080941c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP910"             ,	   0x1180080941c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP911"             ,	   0x1180080941c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP912"             ,	   0x1180080941c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP913"             ,	   0x1180080941c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP914"             ,	   0x1180080941c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP915"             ,	   0x1180080941c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP916"             ,	   0x1180080941ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP917"             ,	   0x1180080941ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP918"             ,	   0x1180080941cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP919"             ,	   0x1180080941cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP920"             ,	   0x1180080941cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP921"             ,	   0x1180080941cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP922"             ,	   0x1180080941cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP923"             ,	   0x1180080941cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP924"             ,	   0x1180080941ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP925"             ,	   0x1180080941ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP926"             ,	   0x1180080941cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP927"             ,	   0x1180080941cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP928"             ,	   0x1180080941d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP929"             ,	   0x1180080941d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP930"             ,	   0x1180080941d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP931"             ,	   0x1180080941d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP932"             ,	   0x1180080941d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP933"             ,	   0x1180080941d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP934"             ,	   0x1180080941d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP935"             ,	   0x1180080941d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP936"             ,	   0x1180080941d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP937"             ,	   0x1180080941d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP938"             ,	   0x1180080941d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP939"             ,	   0x1180080941d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP940"             ,	   0x1180080941d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP941"             ,	   0x1180080941d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP942"             ,	   0x1180080941d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP943"             ,	   0x1180080941d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP944"             ,	   0x1180080941d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP945"             ,	   0x1180080941d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP946"             ,	   0x1180080941d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP947"             ,	   0x1180080941d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP948"             ,	   0x1180080941da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP949"             ,	   0x1180080941da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP950"             ,	   0x1180080941db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP951"             ,	   0x1180080941db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP952"             ,	   0x1180080941dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP953"             ,	   0x1180080941dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP954"             ,	   0x1180080941dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP955"             ,	   0x1180080941dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP956"             ,	   0x1180080941de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP957"             ,	   0x1180080941de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP958"             ,	   0x1180080941df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP959"             ,	   0x1180080941df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP960"             ,	   0x1180080941e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP961"             ,	   0x1180080941e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP962"             ,	   0x1180080941e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP963"             ,	   0x1180080941e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP964"             ,	   0x1180080941e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP965"             ,	   0x1180080941e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP966"             ,	   0x1180080941e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP967"             ,	   0x1180080941e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP968"             ,	   0x1180080941e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP969"             ,	   0x1180080941e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP970"             ,	   0x1180080941e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP971"             ,	   0x1180080941e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP972"             ,	   0x1180080941e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP973"             ,	   0x1180080941e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP974"             ,	   0x1180080941e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP975"             ,	   0x1180080941e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP976"             ,	   0x1180080941e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP977"             ,	   0x1180080941e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP978"             ,	   0x1180080941e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP979"             ,	   0x1180080941e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP980"             ,	   0x1180080941ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP981"             ,	   0x1180080941ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP982"             ,	   0x1180080941eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP983"             ,	   0x1180080941eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP984"             ,	   0x1180080941ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP985"             ,	   0x1180080941ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP986"             ,	   0x1180080941ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP987"             ,	   0x1180080941ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP988"             ,	   0x1180080941ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP989"             ,	   0x1180080941ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP990"             ,	   0x1180080941ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP991"             ,	   0x1180080941ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP992"             ,	   0x1180080941f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP993"             ,	   0x1180080941f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP994"             ,	   0x1180080941f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP995"             ,	   0x1180080941f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP996"             ,	   0x1180080941f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP997"             ,	   0x1180080941f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP998"             ,	   0x1180080941f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP999"             ,	   0x1180080941f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1000"            ,	   0x1180080941f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1001"            ,	   0x1180080941f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1002"            ,	   0x1180080941f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1003"            ,	   0x1180080941f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1004"            ,	   0x1180080941f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1005"            ,	   0x1180080941f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1006"            ,	   0x1180080941f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1007"            ,	   0x1180080941f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1008"            ,	   0x1180080941f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1009"            ,	   0x1180080941f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1010"            ,	   0x1180080941f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1011"            ,	   0x1180080941f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1012"            ,	   0x1180080941fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1013"            ,	   0x1180080941fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1014"            ,	   0x1180080941fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1015"            ,	   0x1180080941fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1016"            ,	   0x1180080941fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1017"            ,	   0x1180080941fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1018"            ,	   0x1180080941fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1019"            ,	   0x1180080941fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1020"            ,	   0x1180080941fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1021"            ,	   0x1180080941fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1022"            ,	   0x1180080941ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1023"            ,	   0x1180080941ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1024"            ,	   0x1180080942000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1025"            ,	   0x1180080942008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1026"            ,	   0x1180080942010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1027"            ,	   0x1180080942018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1028"            ,	   0x1180080942020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1029"            ,	   0x1180080942028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1030"            ,	   0x1180080942030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1031"            ,	   0x1180080942038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1032"            ,	   0x1180080942040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1033"            ,	   0x1180080942048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1034"            ,	   0x1180080942050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1035"            ,	   0x1180080942058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1036"            ,	   0x1180080942060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1037"            ,	   0x1180080942068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1038"            ,	   0x1180080942070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1039"            ,	   0x1180080942078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1040"            ,	   0x1180080942080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1041"            ,	   0x1180080942088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1042"            ,	   0x1180080942090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1043"            ,	   0x1180080942098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1044"            ,	   0x11800809420a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1045"            ,	   0x11800809420a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1046"            ,	   0x11800809420b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1047"            ,	   0x11800809420b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1048"            ,	   0x11800809420c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1049"            ,	   0x11800809420c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1050"            ,	   0x11800809420d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1051"            ,	   0x11800809420d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1052"            ,	   0x11800809420e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1053"            ,	   0x11800809420e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1054"            ,	   0x11800809420f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1055"            ,	   0x11800809420f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1056"            ,	   0x1180080942100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1057"            ,	   0x1180080942108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1058"            ,	   0x1180080942110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1059"            ,	   0x1180080942118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1060"            ,	   0x1180080942120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1061"            ,	   0x1180080942128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1062"            ,	   0x1180080942130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1063"            ,	   0x1180080942138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1064"            ,	   0x1180080942140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1065"            ,	   0x1180080942148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1066"            ,	   0x1180080942150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1067"            ,	   0x1180080942158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1068"            ,	   0x1180080942160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1069"            ,	   0x1180080942168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1070"            ,	   0x1180080942170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1071"            ,	   0x1180080942178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1072"            ,	   0x1180080942180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1073"            ,	   0x1180080942188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1074"            ,	   0x1180080942190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1075"            ,	   0x1180080942198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1076"            ,	   0x11800809421a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1077"            ,	   0x11800809421a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1078"            ,	   0x11800809421b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1079"            ,	   0x11800809421b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1080"            ,	   0x11800809421c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1081"            ,	   0x11800809421c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1082"            ,	   0x11800809421d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1083"            ,	   0x11800809421d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1084"            ,	   0x11800809421e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1085"            ,	   0x11800809421e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1086"            ,	   0x11800809421f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1087"            ,	   0x11800809421f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1088"            ,	   0x1180080942200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1089"            ,	   0x1180080942208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1090"            ,	   0x1180080942210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1091"            ,	   0x1180080942218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1092"            ,	   0x1180080942220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1093"            ,	   0x1180080942228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1094"            ,	   0x1180080942230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1095"            ,	   0x1180080942238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1096"            ,	   0x1180080942240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1097"            ,	   0x1180080942248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1098"            ,	   0x1180080942250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1099"            ,	   0x1180080942258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1100"            ,	   0x1180080942260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1101"            ,	   0x1180080942268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1102"            ,	   0x1180080942270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1103"            ,	   0x1180080942278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1104"            ,	   0x1180080942280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1105"            ,	   0x1180080942288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1106"            ,	   0x1180080942290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1107"            ,	   0x1180080942298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1108"            ,	   0x11800809422a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1109"            ,	   0x11800809422a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1110"            ,	   0x11800809422b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1111"            ,	   0x11800809422b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1112"            ,	   0x11800809422c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1113"            ,	   0x11800809422c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1114"            ,	   0x11800809422d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1115"            ,	   0x11800809422d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1116"            ,	   0x11800809422e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1117"            ,	   0x11800809422e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1118"            ,	   0x11800809422f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1119"            ,	   0x11800809422f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1120"            ,	   0x1180080942300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1121"            ,	   0x1180080942308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1122"            ,	   0x1180080942310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1123"            ,	   0x1180080942318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1124"            ,	   0x1180080942320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1125"            ,	   0x1180080942328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1126"            ,	   0x1180080942330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1127"            ,	   0x1180080942338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1128"            ,	   0x1180080942340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1129"            ,	   0x1180080942348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1130"            ,	   0x1180080942350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1131"            ,	   0x1180080942358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1132"            ,	   0x1180080942360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1133"            ,	   0x1180080942368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1134"            ,	   0x1180080942370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1135"            ,	   0x1180080942378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1136"            ,	   0x1180080942380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1137"            ,	   0x1180080942388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1138"            ,	   0x1180080942390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1139"            ,	   0x1180080942398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1140"            ,	   0x11800809423a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1141"            ,	   0x11800809423a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1142"            ,	   0x11800809423b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1143"            ,	   0x11800809423b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1144"            ,	   0x11800809423c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1145"            ,	   0x11800809423c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1146"            ,	   0x11800809423d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1147"            ,	   0x11800809423d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1148"            ,	   0x11800809423e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1149"            ,	   0x11800809423e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1150"            ,	   0x11800809423f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1151"            ,	   0x11800809423f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1152"            ,	   0x1180080942400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1153"            ,	   0x1180080942408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1154"            ,	   0x1180080942410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1155"            ,	   0x1180080942418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1156"            ,	   0x1180080942420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1157"            ,	   0x1180080942428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1158"            ,	   0x1180080942430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1159"            ,	   0x1180080942438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1160"            ,	   0x1180080942440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1161"            ,	   0x1180080942448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1162"            ,	   0x1180080942450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1163"            ,	   0x1180080942458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1164"            ,	   0x1180080942460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1165"            ,	   0x1180080942468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1166"            ,	   0x1180080942470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1167"            ,	   0x1180080942478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1168"            ,	   0x1180080942480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1169"            ,	   0x1180080942488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1170"            ,	   0x1180080942490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1171"            ,	   0x1180080942498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1172"            ,	   0x11800809424a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1173"            ,	   0x11800809424a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1174"            ,	   0x11800809424b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1175"            ,	   0x11800809424b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1176"            ,	   0x11800809424c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1177"            ,	   0x11800809424c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1178"            ,	   0x11800809424d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1179"            ,	   0x11800809424d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1180"            ,	   0x11800809424e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1181"            ,	   0x11800809424e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1182"            ,	   0x11800809424f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1183"            ,	   0x11800809424f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1184"            ,	   0x1180080942500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1185"            ,	   0x1180080942508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1186"            ,	   0x1180080942510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1187"            ,	   0x1180080942518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1188"            ,	   0x1180080942520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1189"            ,	   0x1180080942528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1190"            ,	   0x1180080942530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1191"            ,	   0x1180080942538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1192"            ,	   0x1180080942540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1193"            ,	   0x1180080942548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1194"            ,	   0x1180080942550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1195"            ,	   0x1180080942558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1196"            ,	   0x1180080942560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1197"            ,	   0x1180080942568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1198"            ,	   0x1180080942570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1199"            ,	   0x1180080942578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1200"            ,	   0x1180080942580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1201"            ,	   0x1180080942588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1202"            ,	   0x1180080942590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1203"            ,	   0x1180080942598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1204"            ,	   0x11800809425a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1205"            ,	   0x11800809425a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1206"            ,	   0x11800809425b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1207"            ,	   0x11800809425b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1208"            ,	   0x11800809425c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1209"            ,	   0x11800809425c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1210"            ,	   0x11800809425d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1211"            ,	   0x11800809425d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1212"            ,	   0x11800809425e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1213"            ,	   0x11800809425e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1214"            ,	   0x11800809425f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1215"            ,	   0x11800809425f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1216"            ,	   0x1180080942600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1217"            ,	   0x1180080942608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1218"            ,	   0x1180080942610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1219"            ,	   0x1180080942618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1220"            ,	   0x1180080942620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1221"            ,	   0x1180080942628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1222"            ,	   0x1180080942630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1223"            ,	   0x1180080942638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1224"            ,	   0x1180080942640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1225"            ,	   0x1180080942648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1226"            ,	   0x1180080942650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1227"            ,	   0x1180080942658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1228"            ,	   0x1180080942660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1229"            ,	   0x1180080942668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1230"            ,	   0x1180080942670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1231"            ,	   0x1180080942678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1232"            ,	   0x1180080942680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1233"            ,	   0x1180080942688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1234"            ,	   0x1180080942690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1235"            ,	   0x1180080942698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1236"            ,	   0x11800809426a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1237"            ,	   0x11800809426a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1238"            ,	   0x11800809426b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1239"            ,	   0x11800809426b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1240"            ,	   0x11800809426c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1241"            ,	   0x11800809426c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1242"            ,	   0x11800809426d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1243"            ,	   0x11800809426d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1244"            ,	   0x11800809426e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1245"            ,	   0x11800809426e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1246"            ,	   0x11800809426f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1247"            ,	   0x11800809426f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1248"            ,	   0x1180080942700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1249"            ,	   0x1180080942708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1250"            ,	   0x1180080942710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1251"            ,	   0x1180080942718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1252"            ,	   0x1180080942720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1253"            ,	   0x1180080942728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1254"            ,	   0x1180080942730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1255"            ,	   0x1180080942738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1256"            ,	   0x1180080942740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1257"            ,	   0x1180080942748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1258"            ,	   0x1180080942750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1259"            ,	   0x1180080942758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1260"            ,	   0x1180080942760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1261"            ,	   0x1180080942768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1262"            ,	   0x1180080942770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1263"            ,	   0x1180080942778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1264"            ,	   0x1180080942780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1265"            ,	   0x1180080942788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1266"            ,	   0x1180080942790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1267"            ,	   0x1180080942798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1268"            ,	   0x11800809427a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1269"            ,	   0x11800809427a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1270"            ,	   0x11800809427b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1271"            ,	   0x11800809427b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1272"            ,	   0x11800809427c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1273"            ,	   0x11800809427c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1274"            ,	   0x11800809427d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1275"            ,	   0x11800809427d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1276"            ,	   0x11800809427e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1277"            ,	   0x11800809427e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1278"            ,	   0x11800809427f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1279"            ,	   0x11800809427f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1280"            ,	   0x1180080942800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1281"            ,	   0x1180080942808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1282"            ,	   0x1180080942810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1283"            ,	   0x1180080942818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1284"            ,	   0x1180080942820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1285"            ,	   0x1180080942828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1286"            ,	   0x1180080942830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1287"            ,	   0x1180080942838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1288"            ,	   0x1180080942840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1289"            ,	   0x1180080942848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1290"            ,	   0x1180080942850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1291"            ,	   0x1180080942858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1292"            ,	   0x1180080942860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1293"            ,	   0x1180080942868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1294"            ,	   0x1180080942870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1295"            ,	   0x1180080942878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1296"            ,	   0x1180080942880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1297"            ,	   0x1180080942888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1298"            ,	   0x1180080942890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1299"            ,	   0x1180080942898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1300"            ,	   0x11800809428a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1301"            ,	   0x11800809428a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1302"            ,	   0x11800809428b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1303"            ,	   0x11800809428b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1304"            ,	   0x11800809428c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1305"            ,	   0x11800809428c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1306"            ,	   0x11800809428d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1307"            ,	   0x11800809428d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1308"            ,	   0x11800809428e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1309"            ,	   0x11800809428e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1310"            ,	   0x11800809428f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1311"            ,	   0x11800809428f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1312"            ,	   0x1180080942900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1313"            ,	   0x1180080942908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1314"            ,	   0x1180080942910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1315"            ,	   0x1180080942918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1316"            ,	   0x1180080942920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1317"            ,	   0x1180080942928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1318"            ,	   0x1180080942930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1319"            ,	   0x1180080942938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1320"            ,	   0x1180080942940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1321"            ,	   0x1180080942948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1322"            ,	   0x1180080942950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1323"            ,	   0x1180080942958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1324"            ,	   0x1180080942960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1325"            ,	   0x1180080942968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1326"            ,	   0x1180080942970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1327"            ,	   0x1180080942978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1328"            ,	   0x1180080942980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1329"            ,	   0x1180080942988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1330"            ,	   0x1180080942990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1331"            ,	   0x1180080942998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1332"            ,	   0x11800809429a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1333"            ,	   0x11800809429a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1334"            ,	   0x11800809429b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1335"            ,	   0x11800809429b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1336"            ,	   0x11800809429c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1337"            ,	   0x11800809429c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1338"            ,	   0x11800809429d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1339"            ,	   0x11800809429d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1340"            ,	   0x11800809429e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1341"            ,	   0x11800809429e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1342"            ,	   0x11800809429f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1343"            ,	   0x11800809429f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1344"            ,	   0x1180080942a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1345"            ,	   0x1180080942a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1346"            ,	   0x1180080942a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1347"            ,	   0x1180080942a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1348"            ,	   0x1180080942a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1349"            ,	   0x1180080942a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1350"            ,	   0x1180080942a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1351"            ,	   0x1180080942a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1352"            ,	   0x1180080942a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1353"            ,	   0x1180080942a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1354"            ,	   0x1180080942a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1355"            ,	   0x1180080942a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1356"            ,	   0x1180080942a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1357"            ,	   0x1180080942a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1358"            ,	   0x1180080942a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1359"            ,	   0x1180080942a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1360"            ,	   0x1180080942a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1361"            ,	   0x1180080942a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1362"            ,	   0x1180080942a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1363"            ,	   0x1180080942a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1364"            ,	   0x1180080942aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1365"            ,	   0x1180080942aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1366"            ,	   0x1180080942ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1367"            ,	   0x1180080942ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1368"            ,	   0x1180080942ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1369"            ,	   0x1180080942ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1370"            ,	   0x1180080942ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1371"            ,	   0x1180080942ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1372"            ,	   0x1180080942ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1373"            ,	   0x1180080942ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1374"            ,	   0x1180080942af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1375"            ,	   0x1180080942af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1376"            ,	   0x1180080942b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1377"            ,	   0x1180080942b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1378"            ,	   0x1180080942b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1379"            ,	   0x1180080942b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1380"            ,	   0x1180080942b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1381"            ,	   0x1180080942b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1382"            ,	   0x1180080942b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1383"            ,	   0x1180080942b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1384"            ,	   0x1180080942b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1385"            ,	   0x1180080942b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1386"            ,	   0x1180080942b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1387"            ,	   0x1180080942b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1388"            ,	   0x1180080942b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1389"            ,	   0x1180080942b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1390"            ,	   0x1180080942b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1391"            ,	   0x1180080942b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1392"            ,	   0x1180080942b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1393"            ,	   0x1180080942b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1394"            ,	   0x1180080942b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1395"            ,	   0x1180080942b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1396"            ,	   0x1180080942ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1397"            ,	   0x1180080942ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1398"            ,	   0x1180080942bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1399"            ,	   0x1180080942bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1400"            ,	   0x1180080942bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1401"            ,	   0x1180080942bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1402"            ,	   0x1180080942bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1403"            ,	   0x1180080942bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1404"            ,	   0x1180080942be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1405"            ,	   0x1180080942be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1406"            ,	   0x1180080942bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1407"            ,	   0x1180080942bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1408"            ,	   0x1180080942c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1409"            ,	   0x1180080942c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1410"            ,	   0x1180080942c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1411"            ,	   0x1180080942c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1412"            ,	   0x1180080942c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1413"            ,	   0x1180080942c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1414"            ,	   0x1180080942c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1415"            ,	   0x1180080942c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1416"            ,	   0x1180080942c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1417"            ,	   0x1180080942c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1418"            ,	   0x1180080942c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1419"            ,	   0x1180080942c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1420"            ,	   0x1180080942c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1421"            ,	   0x1180080942c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1422"            ,	   0x1180080942c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1423"            ,	   0x1180080942c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1424"            ,	   0x1180080942c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1425"            ,	   0x1180080942c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1426"            ,	   0x1180080942c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1427"            ,	   0x1180080942c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1428"            ,	   0x1180080942ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1429"            ,	   0x1180080942ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1430"            ,	   0x1180080942cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1431"            ,	   0x1180080942cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1432"            ,	   0x1180080942cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1433"            ,	   0x1180080942cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1434"            ,	   0x1180080942cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1435"            ,	   0x1180080942cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1436"            ,	   0x1180080942ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1437"            ,	   0x1180080942ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1438"            ,	   0x1180080942cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1439"            ,	   0x1180080942cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1440"            ,	   0x1180080942d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1441"            ,	   0x1180080942d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1442"            ,	   0x1180080942d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1443"            ,	   0x1180080942d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1444"            ,	   0x1180080942d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1445"            ,	   0x1180080942d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1446"            ,	   0x1180080942d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1447"            ,	   0x1180080942d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1448"            ,	   0x1180080942d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1449"            ,	   0x1180080942d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1450"            ,	   0x1180080942d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1451"            ,	   0x1180080942d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1452"            ,	   0x1180080942d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1453"            ,	   0x1180080942d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1454"            ,	   0x1180080942d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1455"            ,	   0x1180080942d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1456"            ,	   0x1180080942d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1457"            ,	   0x1180080942d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1458"            ,	   0x1180080942d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1459"            ,	   0x1180080942d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1460"            ,	   0x1180080942da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1461"            ,	   0x1180080942da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1462"            ,	   0x1180080942db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1463"            ,	   0x1180080942db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1464"            ,	   0x1180080942dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1465"            ,	   0x1180080942dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1466"            ,	   0x1180080942dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1467"            ,	   0x1180080942dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1468"            ,	   0x1180080942de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1469"            ,	   0x1180080942de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1470"            ,	   0x1180080942df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1471"            ,	   0x1180080942df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1472"            ,	   0x1180080942e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1473"            ,	   0x1180080942e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1474"            ,	   0x1180080942e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1475"            ,	   0x1180080942e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1476"            ,	   0x1180080942e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1477"            ,	   0x1180080942e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1478"            ,	   0x1180080942e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1479"            ,	   0x1180080942e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1480"            ,	   0x1180080942e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1481"            ,	   0x1180080942e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1482"            ,	   0x1180080942e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1483"            ,	   0x1180080942e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1484"            ,	   0x1180080942e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1485"            ,	   0x1180080942e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1486"            ,	   0x1180080942e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1487"            ,	   0x1180080942e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1488"            ,	   0x1180080942e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1489"            ,	   0x1180080942e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1490"            ,	   0x1180080942e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1491"            ,	   0x1180080942e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1492"            ,	   0x1180080942ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1493"            ,	   0x1180080942ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1494"            ,	   0x1180080942eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1495"            ,	   0x1180080942eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1496"            ,	   0x1180080942ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1497"            ,	   0x1180080942ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1498"            ,	   0x1180080942ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1499"            ,	   0x1180080942ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1500"            ,	   0x1180080942ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1501"            ,	   0x1180080942ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1502"            ,	   0x1180080942ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1503"            ,	   0x1180080942ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1504"            ,	   0x1180080942f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1505"            ,	   0x1180080942f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1506"            ,	   0x1180080942f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1507"            ,	   0x1180080942f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1508"            ,	   0x1180080942f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1509"            ,	   0x1180080942f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1510"            ,	   0x1180080942f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1511"            ,	   0x1180080942f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1512"            ,	   0x1180080942f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1513"            ,	   0x1180080942f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1514"            ,	   0x1180080942f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1515"            ,	   0x1180080942f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1516"            ,	   0x1180080942f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1517"            ,	   0x1180080942f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1518"            ,	   0x1180080942f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1519"            ,	   0x1180080942f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1520"            ,	   0x1180080942f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1521"            ,	   0x1180080942f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1522"            ,	   0x1180080942f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1523"            ,	   0x1180080942f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1524"            ,	   0x1180080942fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1525"            ,	   0x1180080942fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1526"            ,	   0x1180080942fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1527"            ,	   0x1180080942fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1528"            ,	   0x1180080942fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1529"            ,	   0x1180080942fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1530"            ,	   0x1180080942fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1531"            ,	   0x1180080942fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1532"            ,	   0x1180080942fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1533"            ,	   0x1180080942fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1534"            ,	   0x1180080942ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP1535"            ,	   0x1180080942ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16128"           ,	   0x118008095f800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16129"           ,	   0x118008095f808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16130"           ,	   0x118008095f810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16131"           ,	   0x118008095f818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16132"           ,	   0x118008095f820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16133"           ,	   0x118008095f828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16134"           ,	   0x118008095f830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16135"           ,	   0x118008095f838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16136"           ,	   0x118008095f840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16137"           ,	   0x118008095f848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16138"           ,	   0x118008095f850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16139"           ,	   0x118008095f858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16140"           ,	   0x118008095f860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16141"           ,	   0x118008095f868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16142"           ,	   0x118008095f870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16143"           ,	   0x118008095f878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16144"           ,	   0x118008095f880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16145"           ,	   0x118008095f888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16146"           ,	   0x118008095f890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16147"           ,	   0x118008095f898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16148"           ,	   0x118008095f8a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16149"           ,	   0x118008095f8a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16150"           ,	   0x118008095f8b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16151"           ,	   0x118008095f8b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16152"           ,	   0x118008095f8c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16153"           ,	   0x118008095f8c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16154"           ,	   0x118008095f8d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16155"           ,	   0x118008095f8d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16156"           ,	   0x118008095f8e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16157"           ,	   0x118008095f8e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16158"           ,	   0x118008095f8f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16159"           ,	   0x118008095f8f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16160"           ,	   0x118008095f900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16161"           ,	   0x118008095f908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16162"           ,	   0x118008095f910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16163"           ,	   0x118008095f918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16164"           ,	   0x118008095f920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16165"           ,	   0x118008095f928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16166"           ,	   0x118008095f930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16167"           ,	   0x118008095f938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16168"           ,	   0x118008095f940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16169"           ,	   0x118008095f948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16170"           ,	   0x118008095f950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16171"           ,	   0x118008095f958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16172"           ,	   0x118008095f960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16173"           ,	   0x118008095f968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16174"           ,	   0x118008095f970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16175"           ,	   0x118008095f978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16176"           ,	   0x118008095f980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16177"           ,	   0x118008095f988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16178"           ,	   0x118008095f990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16179"           ,	   0x118008095f998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16180"           ,	   0x118008095f9a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16181"           ,	   0x118008095f9a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16182"           ,	   0x118008095f9b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16183"           ,	   0x118008095f9b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16184"           ,	   0x118008095f9c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16185"           ,	   0x118008095f9c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16186"           ,	   0x118008095f9d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16187"           ,	   0x118008095f9d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16188"           ,	   0x118008095f9e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16189"           ,	   0x118008095f9e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16190"           ,	   0x118008095f9f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16191"           ,	   0x118008095f9f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16192"           ,	   0x118008095fa00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16193"           ,	   0x118008095fa08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16194"           ,	   0x118008095fa10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16195"           ,	   0x118008095fa18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16196"           ,	   0x118008095fa20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16197"           ,	   0x118008095fa28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16198"           ,	   0x118008095fa30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16199"           ,	   0x118008095fa38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16200"           ,	   0x118008095fa40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16201"           ,	   0x118008095fa48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16202"           ,	   0x118008095fa50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16203"           ,	   0x118008095fa58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16204"           ,	   0x118008095fa60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16205"           ,	   0x118008095fa68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16206"           ,	   0x118008095fa70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16207"           ,	   0x118008095fa78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16208"           ,	   0x118008095fa80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16209"           ,	   0x118008095fa88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16210"           ,	   0x118008095fa90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16211"           ,	   0x118008095fa98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16212"           ,	   0x118008095faa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16213"           ,	   0x118008095faa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16214"           ,	   0x118008095fab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16215"           ,	   0x118008095fab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16216"           ,	   0x118008095fac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16217"           ,	   0x118008095fac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16218"           ,	   0x118008095fad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16219"           ,	   0x118008095fad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16220"           ,	   0x118008095fae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16221"           ,	   0x118008095fae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16222"           ,	   0x118008095faf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16223"           ,	   0x118008095faf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16224"           ,	   0x118008095fb00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16225"           ,	   0x118008095fb08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16226"           ,	   0x118008095fb10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16227"           ,	   0x118008095fb18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16228"           ,	   0x118008095fb20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16229"           ,	   0x118008095fb28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16230"           ,	   0x118008095fb30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16231"           ,	   0x118008095fb38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16232"           ,	   0x118008095fb40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16233"           ,	   0x118008095fb48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16234"           ,	   0x118008095fb50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16235"           ,	   0x118008095fb58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16236"           ,	   0x118008095fb60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16237"           ,	   0x118008095fb68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16238"           ,	   0x118008095fb70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16239"           ,	   0x118008095fb78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16240"           ,	   0x118008095fb80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16241"           ,	   0x118008095fb88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16242"           ,	   0x118008095fb90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16243"           ,	   0x118008095fb98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16244"           ,	   0x118008095fba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16245"           ,	   0x118008095fba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16246"           ,	   0x118008095fbb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16247"           ,	   0x118008095fbb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16248"           ,	   0x118008095fbc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16249"           ,	   0x118008095fbc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16250"           ,	   0x118008095fbd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16251"           ,	   0x118008095fbd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16252"           ,	   0x118008095fbe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16253"           ,	   0x118008095fbe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16254"           ,	   0x118008095fbf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16255"           ,	   0x118008095fbf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16256"           ,	   0x118008095fc00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16257"           ,	   0x118008095fc08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16258"           ,	   0x118008095fc10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16259"           ,	   0x118008095fc18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16260"           ,	   0x118008095fc20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16261"           ,	   0x118008095fc28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16262"           ,	   0x118008095fc30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16263"           ,	   0x118008095fc38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16264"           ,	   0x118008095fc40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16265"           ,	   0x118008095fc48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16266"           ,	   0x118008095fc50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16267"           ,	   0x118008095fc58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16268"           ,	   0x118008095fc60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16269"           ,	   0x118008095fc68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16270"           ,	   0x118008095fc70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16271"           ,	   0x118008095fc78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16272"           ,	   0x118008095fc80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16273"           ,	   0x118008095fc88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16274"           ,	   0x118008095fc90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16275"           ,	   0x118008095fc98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16276"           ,	   0x118008095fca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16277"           ,	   0x118008095fca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16278"           ,	   0x118008095fcb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16279"           ,	   0x118008095fcb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16280"           ,	   0x118008095fcc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16281"           ,	   0x118008095fcc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16282"           ,	   0x118008095fcd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16283"           ,	   0x118008095fcd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16284"           ,	   0x118008095fce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16285"           ,	   0x118008095fce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16286"           ,	   0x118008095fcf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16287"           ,	   0x118008095fcf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16288"           ,	   0x118008095fd00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16289"           ,	   0x118008095fd08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16290"           ,	   0x118008095fd10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16291"           ,	   0x118008095fd18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16292"           ,	   0x118008095fd20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16293"           ,	   0x118008095fd28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16294"           ,	   0x118008095fd30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16295"           ,	   0x118008095fd38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16296"           ,	   0x118008095fd40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16297"           ,	   0x118008095fd48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16298"           ,	   0x118008095fd50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16299"           ,	   0x118008095fd58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16300"           ,	   0x118008095fd60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16301"           ,	   0x118008095fd68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16302"           ,	   0x118008095fd70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16303"           ,	   0x118008095fd78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16304"           ,	   0x118008095fd80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16305"           ,	   0x118008095fd88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16306"           ,	   0x118008095fd90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16307"           ,	   0x118008095fd98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16308"           ,	   0x118008095fda0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16309"           ,	   0x118008095fda8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16310"           ,	   0x118008095fdb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16311"           ,	   0x118008095fdb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16312"           ,	   0x118008095fdc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16313"           ,	   0x118008095fdc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16314"           ,	   0x118008095fdd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16315"           ,	   0x118008095fdd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16316"           ,	   0x118008095fde0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16317"           ,	   0x118008095fde8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16318"           ,	   0x118008095fdf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16319"           ,	   0x118008095fdf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16320"           ,	   0x118008095fe00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16321"           ,	   0x118008095fe08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16322"           ,	   0x118008095fe10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16323"           ,	   0x118008095fe18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16324"           ,	   0x118008095fe20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16325"           ,	   0x118008095fe28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16326"           ,	   0x118008095fe30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16327"           ,	   0x118008095fe38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16328"           ,	   0x118008095fe40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16329"           ,	   0x118008095fe48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16330"           ,	   0x118008095fe50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16331"           ,	   0x118008095fe58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16332"           ,	   0x118008095fe60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16333"           ,	   0x118008095fe68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16334"           ,	   0x118008095fe70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16335"           ,	   0x118008095fe78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16336"           ,	   0x118008095fe80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16337"           ,	   0x118008095fe88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16338"           ,	   0x118008095fe90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16339"           ,	   0x118008095fe98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16340"           ,	   0x118008095fea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16341"           ,	   0x118008095fea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16342"           ,	   0x118008095feb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16343"           ,	   0x118008095feb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16344"           ,	   0x118008095fec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16345"           ,	   0x118008095fec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16346"           ,	   0x118008095fed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16347"           ,	   0x118008095fed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16348"           ,	   0x118008095fee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16349"           ,	   0x118008095fee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16350"           ,	   0x118008095fef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16351"           ,	   0x118008095fef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16352"           ,	   0x118008095ff00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16353"           ,	   0x118008095ff08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16354"           ,	   0x118008095ff10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16355"           ,	   0x118008095ff18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16356"           ,	   0x118008095ff20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16357"           ,	   0x118008095ff28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16358"           ,	   0x118008095ff30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16359"           ,	   0x118008095ff38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16360"           ,	   0x118008095ff40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16361"           ,	   0x118008095ff48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16362"           ,	   0x118008095ff50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16363"           ,	   0x118008095ff58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16364"           ,	   0x118008095ff60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16365"           ,	   0x118008095ff68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16366"           ,	   0x118008095ff70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16367"           ,	   0x118008095ff78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16368"           ,	   0x118008095ff80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16369"           ,	   0x118008095ff88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16370"           ,	   0x118008095ff90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16371"           ,	   0x118008095ff98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16372"           ,	   0x118008095ffa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16373"           ,	   0x118008095ffa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16374"           ,	   0x118008095ffb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16375"           ,	   0x118008095ffb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16376"           ,	   0x118008095ffc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16377"           ,	   0x118008095ffc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16378"           ,	   0x118008095ffd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16379"           ,	   0x118008095ffd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16380"           ,	   0x118008095ffe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16381"           ,	   0x118008095ffe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16382"           ,	   0x118008095fff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_COP0_MAP16383"           ,	   0x118008095fff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"L2C_CTL"                     ,	   0x1180080800000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"L2C_DUT_MAP0"                ,	   0x1180080e00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1"                ,	   0x1180080e00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP2"                ,	   0x1180080e00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP3"                ,	   0x1180080e00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP4"                ,	   0x1180080e00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP5"                ,	   0x1180080e00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP6"                ,	   0x1180080e00030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP7"                ,	   0x1180080e00038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP8"                ,	   0x1180080e00040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP9"                ,	   0x1180080e00048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP10"               ,	   0x1180080e00050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP11"               ,	   0x1180080e00058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP12"               ,	   0x1180080e00060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP13"               ,	   0x1180080e00068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP14"               ,	   0x1180080e00070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP15"               ,	   0x1180080e00078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP16"               ,	   0x1180080e00080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP17"               ,	   0x1180080e00088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP18"               ,	   0x1180080e00090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP19"               ,	   0x1180080e00098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP20"               ,	   0x1180080e000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP21"               ,	   0x1180080e000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP22"               ,	   0x1180080e000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP23"               ,	   0x1180080e000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP24"               ,	   0x1180080e000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP25"               ,	   0x1180080e000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP26"               ,	   0x1180080e000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP27"               ,	   0x1180080e000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP28"               ,	   0x1180080e000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP29"               ,	   0x1180080e000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP30"               ,	   0x1180080e000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP31"               ,	   0x1180080e000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP32"               ,	   0x1180080e00100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP33"               ,	   0x1180080e00108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP34"               ,	   0x1180080e00110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP35"               ,	   0x1180080e00118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP36"               ,	   0x1180080e00120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP37"               ,	   0x1180080e00128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP38"               ,	   0x1180080e00130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP39"               ,	   0x1180080e00138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP40"               ,	   0x1180080e00140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP41"               ,	   0x1180080e00148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP42"               ,	   0x1180080e00150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP43"               ,	   0x1180080e00158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP44"               ,	   0x1180080e00160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP45"               ,	   0x1180080e00168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP46"               ,	   0x1180080e00170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP47"               ,	   0x1180080e00178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP48"               ,	   0x1180080e00180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP49"               ,	   0x1180080e00188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP50"               ,	   0x1180080e00190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP51"               ,	   0x1180080e00198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP52"               ,	   0x1180080e001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP53"               ,	   0x1180080e001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP54"               ,	   0x1180080e001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP55"               ,	   0x1180080e001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP56"               ,	   0x1180080e001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP57"               ,	   0x1180080e001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP58"               ,	   0x1180080e001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP59"               ,	   0x1180080e001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP60"               ,	   0x1180080e001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP61"               ,	   0x1180080e001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP62"               ,	   0x1180080e001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP63"               ,	   0x1180080e001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP64"               ,	   0x1180080e00200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP65"               ,	   0x1180080e00208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP66"               ,	   0x1180080e00210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP67"               ,	   0x1180080e00218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP68"               ,	   0x1180080e00220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP69"               ,	   0x1180080e00228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP70"               ,	   0x1180080e00230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP71"               ,	   0x1180080e00238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP72"               ,	   0x1180080e00240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP73"               ,	   0x1180080e00248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP74"               ,	   0x1180080e00250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP75"               ,	   0x1180080e00258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP76"               ,	   0x1180080e00260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP77"               ,	   0x1180080e00268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP78"               ,	   0x1180080e00270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP79"               ,	   0x1180080e00278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP80"               ,	   0x1180080e00280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP81"               ,	   0x1180080e00288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP82"               ,	   0x1180080e00290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP83"               ,	   0x1180080e00298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP84"               ,	   0x1180080e002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP85"               ,	   0x1180080e002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP86"               ,	   0x1180080e002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP87"               ,	   0x1180080e002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP88"               ,	   0x1180080e002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP89"               ,	   0x1180080e002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP90"               ,	   0x1180080e002d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP91"               ,	   0x1180080e002d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP92"               ,	   0x1180080e002e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP93"               ,	   0x1180080e002e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP94"               ,	   0x1180080e002f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP95"               ,	   0x1180080e002f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP96"               ,	   0x1180080e00300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP97"               ,	   0x1180080e00308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP98"               ,	   0x1180080e00310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP99"               ,	   0x1180080e00318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP100"              ,	   0x1180080e00320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP101"              ,	   0x1180080e00328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP102"              ,	   0x1180080e00330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP103"              ,	   0x1180080e00338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP104"              ,	   0x1180080e00340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP105"              ,	   0x1180080e00348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP106"              ,	   0x1180080e00350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP107"              ,	   0x1180080e00358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP108"              ,	   0x1180080e00360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP109"              ,	   0x1180080e00368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP110"              ,	   0x1180080e00370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP111"              ,	   0x1180080e00378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP112"              ,	   0x1180080e00380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP113"              ,	   0x1180080e00388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP114"              ,	   0x1180080e00390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP115"              ,	   0x1180080e00398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP116"              ,	   0x1180080e003a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP117"              ,	   0x1180080e003a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP118"              ,	   0x1180080e003b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP119"              ,	   0x1180080e003b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP120"              ,	   0x1180080e003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP121"              ,	   0x1180080e003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP122"              ,	   0x1180080e003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP123"              ,	   0x1180080e003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP124"              ,	   0x1180080e003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP125"              ,	   0x1180080e003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP126"              ,	   0x1180080e003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP127"              ,	   0x1180080e003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP128"              ,	   0x1180080e00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP129"              ,	   0x1180080e00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP130"              ,	   0x1180080e00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP131"              ,	   0x1180080e00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP132"              ,	   0x1180080e00420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP133"              ,	   0x1180080e00428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP134"              ,	   0x1180080e00430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP135"              ,	   0x1180080e00438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP136"              ,	   0x1180080e00440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP137"              ,	   0x1180080e00448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP138"              ,	   0x1180080e00450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP139"              ,	   0x1180080e00458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP140"              ,	   0x1180080e00460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP141"              ,	   0x1180080e00468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP142"              ,	   0x1180080e00470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP143"              ,	   0x1180080e00478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP144"              ,	   0x1180080e00480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP145"              ,	   0x1180080e00488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP146"              ,	   0x1180080e00490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP147"              ,	   0x1180080e00498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP148"              ,	   0x1180080e004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP149"              ,	   0x1180080e004a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP150"              ,	   0x1180080e004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP151"              ,	   0x1180080e004b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP152"              ,	   0x1180080e004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP153"              ,	   0x1180080e004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP154"              ,	   0x1180080e004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP155"              ,	   0x1180080e004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP156"              ,	   0x1180080e004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP157"              ,	   0x1180080e004e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP158"              ,	   0x1180080e004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP159"              ,	   0x1180080e004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP160"              ,	   0x1180080e00500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP161"              ,	   0x1180080e00508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP162"              ,	   0x1180080e00510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP163"              ,	   0x1180080e00518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP164"              ,	   0x1180080e00520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP165"              ,	   0x1180080e00528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP166"              ,	   0x1180080e00530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP167"              ,	   0x1180080e00538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP168"              ,	   0x1180080e00540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP169"              ,	   0x1180080e00548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP170"              ,	   0x1180080e00550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP171"              ,	   0x1180080e00558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP172"              ,	   0x1180080e00560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP173"              ,	   0x1180080e00568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP174"              ,	   0x1180080e00570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP175"              ,	   0x1180080e00578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP176"              ,	   0x1180080e00580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP177"              ,	   0x1180080e00588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP178"              ,	   0x1180080e00590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP179"              ,	   0x1180080e00598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP180"              ,	   0x1180080e005a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP181"              ,	   0x1180080e005a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP182"              ,	   0x1180080e005b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP183"              ,	   0x1180080e005b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP184"              ,	   0x1180080e005c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP185"              ,	   0x1180080e005c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP186"              ,	   0x1180080e005d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP187"              ,	   0x1180080e005d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP188"              ,	   0x1180080e005e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP189"              ,	   0x1180080e005e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP190"              ,	   0x1180080e005f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP191"              ,	   0x1180080e005f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP192"              ,	   0x1180080e00600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP193"              ,	   0x1180080e00608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP194"              ,	   0x1180080e00610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP195"              ,	   0x1180080e00618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP196"              ,	   0x1180080e00620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP197"              ,	   0x1180080e00628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP198"              ,	   0x1180080e00630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP199"              ,	   0x1180080e00638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP200"              ,	   0x1180080e00640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP201"              ,	   0x1180080e00648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP202"              ,	   0x1180080e00650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP203"              ,	   0x1180080e00658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP204"              ,	   0x1180080e00660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP205"              ,	   0x1180080e00668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP206"              ,	   0x1180080e00670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP207"              ,	   0x1180080e00678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP208"              ,	   0x1180080e00680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP209"              ,	   0x1180080e00688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP210"              ,	   0x1180080e00690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP211"              ,	   0x1180080e00698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP212"              ,	   0x1180080e006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP213"              ,	   0x1180080e006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP214"              ,	   0x1180080e006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP215"              ,	   0x1180080e006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP216"              ,	   0x1180080e006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP217"              ,	   0x1180080e006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP218"              ,	   0x1180080e006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP219"              ,	   0x1180080e006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP220"              ,	   0x1180080e006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP221"              ,	   0x1180080e006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP222"              ,	   0x1180080e006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP223"              ,	   0x1180080e006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP224"              ,	   0x1180080e00700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP225"              ,	   0x1180080e00708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP226"              ,	   0x1180080e00710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP227"              ,	   0x1180080e00718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP228"              ,	   0x1180080e00720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP229"              ,	   0x1180080e00728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP230"              ,	   0x1180080e00730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP231"              ,	   0x1180080e00738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP232"              ,	   0x1180080e00740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP233"              ,	   0x1180080e00748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP234"              ,	   0x1180080e00750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP235"              ,	   0x1180080e00758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP236"              ,	   0x1180080e00760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP237"              ,	   0x1180080e00768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP238"              ,	   0x1180080e00770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP239"              ,	   0x1180080e00778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP240"              ,	   0x1180080e00780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP241"              ,	   0x1180080e00788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP242"              ,	   0x1180080e00790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP243"              ,	   0x1180080e00798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP244"              ,	   0x1180080e007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP245"              ,	   0x1180080e007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP246"              ,	   0x1180080e007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP247"              ,	   0x1180080e007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP248"              ,	   0x1180080e007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP249"              ,	   0x1180080e007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP250"              ,	   0x1180080e007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP251"              ,	   0x1180080e007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP252"              ,	   0x1180080e007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP253"              ,	   0x1180080e007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP254"              ,	   0x1180080e007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP255"              ,	   0x1180080e007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP256"              ,	   0x1180080e00800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP257"              ,	   0x1180080e00808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP258"              ,	   0x1180080e00810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP259"              ,	   0x1180080e00818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP260"              ,	   0x1180080e00820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP261"              ,	   0x1180080e00828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP262"              ,	   0x1180080e00830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP263"              ,	   0x1180080e00838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP264"              ,	   0x1180080e00840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP265"              ,	   0x1180080e00848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP266"              ,	   0x1180080e00850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP267"              ,	   0x1180080e00858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP268"              ,	   0x1180080e00860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP269"              ,	   0x1180080e00868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP270"              ,	   0x1180080e00870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP271"              ,	   0x1180080e00878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP272"              ,	   0x1180080e00880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP273"              ,	   0x1180080e00888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP274"              ,	   0x1180080e00890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP275"              ,	   0x1180080e00898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP276"              ,	   0x1180080e008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP277"              ,	   0x1180080e008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP278"              ,	   0x1180080e008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP279"              ,	   0x1180080e008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP280"              ,	   0x1180080e008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP281"              ,	   0x1180080e008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP282"              ,	   0x1180080e008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP283"              ,	   0x1180080e008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP284"              ,	   0x1180080e008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP285"              ,	   0x1180080e008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP286"              ,	   0x1180080e008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP287"              ,	   0x1180080e008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP288"              ,	   0x1180080e00900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP289"              ,	   0x1180080e00908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP290"              ,	   0x1180080e00910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP291"              ,	   0x1180080e00918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP292"              ,	   0x1180080e00920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP293"              ,	   0x1180080e00928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP294"              ,	   0x1180080e00930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP295"              ,	   0x1180080e00938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP296"              ,	   0x1180080e00940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP297"              ,	   0x1180080e00948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP298"              ,	   0x1180080e00950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP299"              ,	   0x1180080e00958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP300"              ,	   0x1180080e00960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP301"              ,	   0x1180080e00968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP302"              ,	   0x1180080e00970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP303"              ,	   0x1180080e00978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP304"              ,	   0x1180080e00980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP305"              ,	   0x1180080e00988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP306"              ,	   0x1180080e00990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP307"              ,	   0x1180080e00998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP308"              ,	   0x1180080e009a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP309"              ,	   0x1180080e009a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP310"              ,	   0x1180080e009b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP311"              ,	   0x1180080e009b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP312"              ,	   0x1180080e009c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP313"              ,	   0x1180080e009c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP314"              ,	   0x1180080e009d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP315"              ,	   0x1180080e009d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP316"              ,	   0x1180080e009e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP317"              ,	   0x1180080e009e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP318"              ,	   0x1180080e009f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP319"              ,	   0x1180080e009f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP320"              ,	   0x1180080e00a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP321"              ,	   0x1180080e00a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP322"              ,	   0x1180080e00a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP323"              ,	   0x1180080e00a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP324"              ,	   0x1180080e00a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP325"              ,	   0x1180080e00a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP326"              ,	   0x1180080e00a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP327"              ,	   0x1180080e00a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP328"              ,	   0x1180080e00a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP329"              ,	   0x1180080e00a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP330"              ,	   0x1180080e00a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP331"              ,	   0x1180080e00a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP332"              ,	   0x1180080e00a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP333"              ,	   0x1180080e00a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP334"              ,	   0x1180080e00a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP335"              ,	   0x1180080e00a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP336"              ,	   0x1180080e00a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP337"              ,	   0x1180080e00a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP338"              ,	   0x1180080e00a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP339"              ,	   0x1180080e00a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP340"              ,	   0x1180080e00aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP341"              ,	   0x1180080e00aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP342"              ,	   0x1180080e00ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP343"              ,	   0x1180080e00ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP344"              ,	   0x1180080e00ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP345"              ,	   0x1180080e00ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP346"              ,	   0x1180080e00ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP347"              ,	   0x1180080e00ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP348"              ,	   0x1180080e00ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP349"              ,	   0x1180080e00ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP350"              ,	   0x1180080e00af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP351"              ,	   0x1180080e00af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP352"              ,	   0x1180080e00b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP353"              ,	   0x1180080e00b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP354"              ,	   0x1180080e00b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP355"              ,	   0x1180080e00b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP356"              ,	   0x1180080e00b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP357"              ,	   0x1180080e00b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP358"              ,	   0x1180080e00b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP359"              ,	   0x1180080e00b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP360"              ,	   0x1180080e00b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP361"              ,	   0x1180080e00b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP362"              ,	   0x1180080e00b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP363"              ,	   0x1180080e00b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP364"              ,	   0x1180080e00b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP365"              ,	   0x1180080e00b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP366"              ,	   0x1180080e00b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP367"              ,	   0x1180080e00b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP368"              ,	   0x1180080e00b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP369"              ,	   0x1180080e00b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP370"              ,	   0x1180080e00b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP371"              ,	   0x1180080e00b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP372"              ,	   0x1180080e00ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP373"              ,	   0x1180080e00ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP374"              ,	   0x1180080e00bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP375"              ,	   0x1180080e00bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP376"              ,	   0x1180080e00bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP377"              ,	   0x1180080e00bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP378"              ,	   0x1180080e00bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP379"              ,	   0x1180080e00bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP380"              ,	   0x1180080e00be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP381"              ,	   0x1180080e00be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP382"              ,	   0x1180080e00bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP383"              ,	   0x1180080e00bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP384"              ,	   0x1180080e00c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP385"              ,	   0x1180080e00c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP386"              ,	   0x1180080e00c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP387"              ,	   0x1180080e00c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP388"              ,	   0x1180080e00c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP389"              ,	   0x1180080e00c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP390"              ,	   0x1180080e00c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP391"              ,	   0x1180080e00c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP392"              ,	   0x1180080e00c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP393"              ,	   0x1180080e00c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP394"              ,	   0x1180080e00c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP395"              ,	   0x1180080e00c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP396"              ,	   0x1180080e00c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP397"              ,	   0x1180080e00c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP398"              ,	   0x1180080e00c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP399"              ,	   0x1180080e00c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP400"              ,	   0x1180080e00c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP401"              ,	   0x1180080e00c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP402"              ,	   0x1180080e00c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP403"              ,	   0x1180080e00c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP404"              ,	   0x1180080e00ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP405"              ,	   0x1180080e00ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP406"              ,	   0x1180080e00cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP407"              ,	   0x1180080e00cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP408"              ,	   0x1180080e00cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP409"              ,	   0x1180080e00cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP410"              ,	   0x1180080e00cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP411"              ,	   0x1180080e00cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP412"              ,	   0x1180080e00ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP413"              ,	   0x1180080e00ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP414"              ,	   0x1180080e00cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP415"              ,	   0x1180080e00cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP416"              ,	   0x1180080e00d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP417"              ,	   0x1180080e00d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP418"              ,	   0x1180080e00d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP419"              ,	   0x1180080e00d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP420"              ,	   0x1180080e00d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP421"              ,	   0x1180080e00d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP422"              ,	   0x1180080e00d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP423"              ,	   0x1180080e00d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP424"              ,	   0x1180080e00d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP425"              ,	   0x1180080e00d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP426"              ,	   0x1180080e00d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP427"              ,	   0x1180080e00d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP428"              ,	   0x1180080e00d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP429"              ,	   0x1180080e00d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP430"              ,	   0x1180080e00d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP431"              ,	   0x1180080e00d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP432"              ,	   0x1180080e00d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP433"              ,	   0x1180080e00d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP434"              ,	   0x1180080e00d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP435"              ,	   0x1180080e00d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP436"              ,	   0x1180080e00da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP437"              ,	   0x1180080e00da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP438"              ,	   0x1180080e00db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP439"              ,	   0x1180080e00db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP440"              ,	   0x1180080e00dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP441"              ,	   0x1180080e00dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP442"              ,	   0x1180080e00dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP443"              ,	   0x1180080e00dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP444"              ,	   0x1180080e00de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP445"              ,	   0x1180080e00de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP446"              ,	   0x1180080e00df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP447"              ,	   0x1180080e00df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP448"              ,	   0x1180080e00e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP449"              ,	   0x1180080e00e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP450"              ,	   0x1180080e00e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP451"              ,	   0x1180080e00e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP452"              ,	   0x1180080e00e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP453"              ,	   0x1180080e00e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP454"              ,	   0x1180080e00e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP455"              ,	   0x1180080e00e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP456"              ,	   0x1180080e00e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP457"              ,	   0x1180080e00e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP458"              ,	   0x1180080e00e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP459"              ,	   0x1180080e00e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP460"              ,	   0x1180080e00e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP461"              ,	   0x1180080e00e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP462"              ,	   0x1180080e00e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP463"              ,	   0x1180080e00e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP464"              ,	   0x1180080e00e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP465"              ,	   0x1180080e00e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP466"              ,	   0x1180080e00e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP467"              ,	   0x1180080e00e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP468"              ,	   0x1180080e00ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP469"              ,	   0x1180080e00ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP470"              ,	   0x1180080e00eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP471"              ,	   0x1180080e00eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP472"              ,	   0x1180080e00ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP473"              ,	   0x1180080e00ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP474"              ,	   0x1180080e00ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP475"              ,	   0x1180080e00ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP476"              ,	   0x1180080e00ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP477"              ,	   0x1180080e00ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP478"              ,	   0x1180080e00ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP479"              ,	   0x1180080e00ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP480"              ,	   0x1180080e00f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP481"              ,	   0x1180080e00f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP482"              ,	   0x1180080e00f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP483"              ,	   0x1180080e00f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP484"              ,	   0x1180080e00f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP485"              ,	   0x1180080e00f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP486"              ,	   0x1180080e00f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP487"              ,	   0x1180080e00f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP488"              ,	   0x1180080e00f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP489"              ,	   0x1180080e00f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP490"              ,	   0x1180080e00f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP491"              ,	   0x1180080e00f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP492"              ,	   0x1180080e00f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP493"              ,	   0x1180080e00f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP494"              ,	   0x1180080e00f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP495"              ,	   0x1180080e00f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP496"              ,	   0x1180080e00f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP497"              ,	   0x1180080e00f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP498"              ,	   0x1180080e00f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP499"              ,	   0x1180080e00f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP500"              ,	   0x1180080e00fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP501"              ,	   0x1180080e00fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP502"              ,	   0x1180080e00fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP503"              ,	   0x1180080e00fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP504"              ,	   0x1180080e00fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP505"              ,	   0x1180080e00fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP506"              ,	   0x1180080e00fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP507"              ,	   0x1180080e00fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP508"              ,	   0x1180080e00fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP509"              ,	   0x1180080e00fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP510"              ,	   0x1180080e00ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP511"              ,	   0x1180080e00ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP512"              ,	   0x1180080e01000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP513"              ,	   0x1180080e01008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP514"              ,	   0x1180080e01010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP515"              ,	   0x1180080e01018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP516"              ,	   0x1180080e01020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP517"              ,	   0x1180080e01028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP518"              ,	   0x1180080e01030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP519"              ,	   0x1180080e01038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP520"              ,	   0x1180080e01040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP521"              ,	   0x1180080e01048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP522"              ,	   0x1180080e01050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP523"              ,	   0x1180080e01058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP524"              ,	   0x1180080e01060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP525"              ,	   0x1180080e01068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP526"              ,	   0x1180080e01070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP527"              ,	   0x1180080e01078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP528"              ,	   0x1180080e01080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP529"              ,	   0x1180080e01088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP530"              ,	   0x1180080e01090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP531"              ,	   0x1180080e01098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP532"              ,	   0x1180080e010a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP533"              ,	   0x1180080e010a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP534"              ,	   0x1180080e010b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP535"              ,	   0x1180080e010b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP536"              ,	   0x1180080e010c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP537"              ,	   0x1180080e010c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP538"              ,	   0x1180080e010d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP539"              ,	   0x1180080e010d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP540"              ,	   0x1180080e010e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP541"              ,	   0x1180080e010e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP542"              ,	   0x1180080e010f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP543"              ,	   0x1180080e010f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP544"              ,	   0x1180080e01100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP545"              ,	   0x1180080e01108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP546"              ,	   0x1180080e01110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP547"              ,	   0x1180080e01118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP548"              ,	   0x1180080e01120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP549"              ,	   0x1180080e01128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP550"              ,	   0x1180080e01130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP551"              ,	   0x1180080e01138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP552"              ,	   0x1180080e01140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP553"              ,	   0x1180080e01148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP554"              ,	   0x1180080e01150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP555"              ,	   0x1180080e01158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP556"              ,	   0x1180080e01160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP557"              ,	   0x1180080e01168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP558"              ,	   0x1180080e01170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP559"              ,	   0x1180080e01178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP560"              ,	   0x1180080e01180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP561"              ,	   0x1180080e01188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP562"              ,	   0x1180080e01190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP563"              ,	   0x1180080e01198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP564"              ,	   0x1180080e011a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP565"              ,	   0x1180080e011a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP566"              ,	   0x1180080e011b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP567"              ,	   0x1180080e011b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP568"              ,	   0x1180080e011c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP569"              ,	   0x1180080e011c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP570"              ,	   0x1180080e011d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP571"              ,	   0x1180080e011d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP572"              ,	   0x1180080e011e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP573"              ,	   0x1180080e011e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP574"              ,	   0x1180080e011f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP575"              ,	   0x1180080e011f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP576"              ,	   0x1180080e01200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP577"              ,	   0x1180080e01208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP578"              ,	   0x1180080e01210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP579"              ,	   0x1180080e01218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP580"              ,	   0x1180080e01220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP581"              ,	   0x1180080e01228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP582"              ,	   0x1180080e01230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP583"              ,	   0x1180080e01238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP584"              ,	   0x1180080e01240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP585"              ,	   0x1180080e01248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP586"              ,	   0x1180080e01250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP587"              ,	   0x1180080e01258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP588"              ,	   0x1180080e01260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP589"              ,	   0x1180080e01268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP590"              ,	   0x1180080e01270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP591"              ,	   0x1180080e01278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP592"              ,	   0x1180080e01280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP593"              ,	   0x1180080e01288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP594"              ,	   0x1180080e01290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP595"              ,	   0x1180080e01298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP596"              ,	   0x1180080e012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP597"              ,	   0x1180080e012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP598"              ,	   0x1180080e012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP599"              ,	   0x1180080e012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP600"              ,	   0x1180080e012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP601"              ,	   0x1180080e012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP602"              ,	   0x1180080e012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP603"              ,	   0x1180080e012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP604"              ,	   0x1180080e012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP605"              ,	   0x1180080e012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP606"              ,	   0x1180080e012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP607"              ,	   0x1180080e012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP608"              ,	   0x1180080e01300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP609"              ,	   0x1180080e01308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP610"              ,	   0x1180080e01310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP611"              ,	   0x1180080e01318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP612"              ,	   0x1180080e01320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP613"              ,	   0x1180080e01328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP614"              ,	   0x1180080e01330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP615"              ,	   0x1180080e01338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP616"              ,	   0x1180080e01340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP617"              ,	   0x1180080e01348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP618"              ,	   0x1180080e01350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP619"              ,	   0x1180080e01358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP620"              ,	   0x1180080e01360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP621"              ,	   0x1180080e01368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP622"              ,	   0x1180080e01370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP623"              ,	   0x1180080e01378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP624"              ,	   0x1180080e01380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP625"              ,	   0x1180080e01388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP626"              ,	   0x1180080e01390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP627"              ,	   0x1180080e01398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP628"              ,	   0x1180080e013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP629"              ,	   0x1180080e013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP630"              ,	   0x1180080e013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP631"              ,	   0x1180080e013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP632"              ,	   0x1180080e013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP633"              ,	   0x1180080e013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP634"              ,	   0x1180080e013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP635"              ,	   0x1180080e013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP636"              ,	   0x1180080e013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP637"              ,	   0x1180080e013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP638"              ,	   0x1180080e013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP639"              ,	   0x1180080e013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP640"              ,	   0x1180080e01400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP641"              ,	   0x1180080e01408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP642"              ,	   0x1180080e01410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP643"              ,	   0x1180080e01418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP644"              ,	   0x1180080e01420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP645"              ,	   0x1180080e01428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP646"              ,	   0x1180080e01430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP647"              ,	   0x1180080e01438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP648"              ,	   0x1180080e01440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP649"              ,	   0x1180080e01448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP650"              ,	   0x1180080e01450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP651"              ,	   0x1180080e01458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP652"              ,	   0x1180080e01460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP653"              ,	   0x1180080e01468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP654"              ,	   0x1180080e01470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP655"              ,	   0x1180080e01478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP656"              ,	   0x1180080e01480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP657"              ,	   0x1180080e01488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP658"              ,	   0x1180080e01490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP659"              ,	   0x1180080e01498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP660"              ,	   0x1180080e014a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP661"              ,	   0x1180080e014a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP662"              ,	   0x1180080e014b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP663"              ,	   0x1180080e014b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP664"              ,	   0x1180080e014c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP665"              ,	   0x1180080e014c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP666"              ,	   0x1180080e014d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP667"              ,	   0x1180080e014d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP668"              ,	   0x1180080e014e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP669"              ,	   0x1180080e014e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP670"              ,	   0x1180080e014f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP671"              ,	   0x1180080e014f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP672"              ,	   0x1180080e01500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP673"              ,	   0x1180080e01508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP674"              ,	   0x1180080e01510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP675"              ,	   0x1180080e01518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP676"              ,	   0x1180080e01520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP677"              ,	   0x1180080e01528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP678"              ,	   0x1180080e01530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP679"              ,	   0x1180080e01538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP680"              ,	   0x1180080e01540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP681"              ,	   0x1180080e01548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP682"              ,	   0x1180080e01550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP683"              ,	   0x1180080e01558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP684"              ,	   0x1180080e01560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP685"              ,	   0x1180080e01568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP686"              ,	   0x1180080e01570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP687"              ,	   0x1180080e01578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP688"              ,	   0x1180080e01580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP689"              ,	   0x1180080e01588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP690"              ,	   0x1180080e01590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP691"              ,	   0x1180080e01598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP692"              ,	   0x1180080e015a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP693"              ,	   0x1180080e015a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP694"              ,	   0x1180080e015b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP695"              ,	   0x1180080e015b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP696"              ,	   0x1180080e015c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP697"              ,	   0x1180080e015c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP698"              ,	   0x1180080e015d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP699"              ,	   0x1180080e015d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP700"              ,	   0x1180080e015e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP701"              ,	   0x1180080e015e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP702"              ,	   0x1180080e015f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP703"              ,	   0x1180080e015f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP704"              ,	   0x1180080e01600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP705"              ,	   0x1180080e01608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP706"              ,	   0x1180080e01610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP707"              ,	   0x1180080e01618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP708"              ,	   0x1180080e01620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP709"              ,	   0x1180080e01628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP710"              ,	   0x1180080e01630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP711"              ,	   0x1180080e01638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP712"              ,	   0x1180080e01640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP713"              ,	   0x1180080e01648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP714"              ,	   0x1180080e01650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP715"              ,	   0x1180080e01658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP716"              ,	   0x1180080e01660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP717"              ,	   0x1180080e01668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP718"              ,	   0x1180080e01670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP719"              ,	   0x1180080e01678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP720"              ,	   0x1180080e01680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP721"              ,	   0x1180080e01688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP722"              ,	   0x1180080e01690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP723"              ,	   0x1180080e01698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP724"              ,	   0x1180080e016a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP725"              ,	   0x1180080e016a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP726"              ,	   0x1180080e016b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP727"              ,	   0x1180080e016b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP728"              ,	   0x1180080e016c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP729"              ,	   0x1180080e016c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP730"              ,	   0x1180080e016d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP731"              ,	   0x1180080e016d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP732"              ,	   0x1180080e016e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP733"              ,	   0x1180080e016e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP734"              ,	   0x1180080e016f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP735"              ,	   0x1180080e016f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP736"              ,	   0x1180080e01700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP737"              ,	   0x1180080e01708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP738"              ,	   0x1180080e01710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP739"              ,	   0x1180080e01718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP740"              ,	   0x1180080e01720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP741"              ,	   0x1180080e01728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP742"              ,	   0x1180080e01730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP743"              ,	   0x1180080e01738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP744"              ,	   0x1180080e01740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP745"              ,	   0x1180080e01748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP746"              ,	   0x1180080e01750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP747"              ,	   0x1180080e01758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP748"              ,	   0x1180080e01760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP749"              ,	   0x1180080e01768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP750"              ,	   0x1180080e01770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP751"              ,	   0x1180080e01778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP752"              ,	   0x1180080e01780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP753"              ,	   0x1180080e01788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP754"              ,	   0x1180080e01790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP755"              ,	   0x1180080e01798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP756"              ,	   0x1180080e017a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP757"              ,	   0x1180080e017a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP758"              ,	   0x1180080e017b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP759"              ,	   0x1180080e017b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP760"              ,	   0x1180080e017c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP761"              ,	   0x1180080e017c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP762"              ,	   0x1180080e017d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP763"              ,	   0x1180080e017d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP764"              ,	   0x1180080e017e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP765"              ,	   0x1180080e017e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP766"              ,	   0x1180080e017f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP767"              ,	   0x1180080e017f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP768"              ,	   0x1180080e01800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP769"              ,	   0x1180080e01808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP770"              ,	   0x1180080e01810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP771"              ,	   0x1180080e01818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP772"              ,	   0x1180080e01820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP773"              ,	   0x1180080e01828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP774"              ,	   0x1180080e01830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP775"              ,	   0x1180080e01838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP776"              ,	   0x1180080e01840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP777"              ,	   0x1180080e01848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP778"              ,	   0x1180080e01850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP779"              ,	   0x1180080e01858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP780"              ,	   0x1180080e01860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP781"              ,	   0x1180080e01868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP782"              ,	   0x1180080e01870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP783"              ,	   0x1180080e01878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP784"              ,	   0x1180080e01880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP785"              ,	   0x1180080e01888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP786"              ,	   0x1180080e01890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP787"              ,	   0x1180080e01898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP788"              ,	   0x1180080e018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP789"              ,	   0x1180080e018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP790"              ,	   0x1180080e018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP791"              ,	   0x1180080e018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP792"              ,	   0x1180080e018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP793"              ,	   0x1180080e018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP794"              ,	   0x1180080e018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP795"              ,	   0x1180080e018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP796"              ,	   0x1180080e018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP797"              ,	   0x1180080e018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP798"              ,	   0x1180080e018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP799"              ,	   0x1180080e018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP800"              ,	   0x1180080e01900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP801"              ,	   0x1180080e01908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP802"              ,	   0x1180080e01910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP803"              ,	   0x1180080e01918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP804"              ,	   0x1180080e01920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP805"              ,	   0x1180080e01928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP806"              ,	   0x1180080e01930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP807"              ,	   0x1180080e01938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP808"              ,	   0x1180080e01940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP809"              ,	   0x1180080e01948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP810"              ,	   0x1180080e01950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP811"              ,	   0x1180080e01958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP812"              ,	   0x1180080e01960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP813"              ,	   0x1180080e01968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP814"              ,	   0x1180080e01970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP815"              ,	   0x1180080e01978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP816"              ,	   0x1180080e01980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP817"              ,	   0x1180080e01988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP818"              ,	   0x1180080e01990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP819"              ,	   0x1180080e01998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP820"              ,	   0x1180080e019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP821"              ,	   0x1180080e019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP822"              ,	   0x1180080e019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP823"              ,	   0x1180080e019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP824"              ,	   0x1180080e019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP825"              ,	   0x1180080e019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP826"              ,	   0x1180080e019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP827"              ,	   0x1180080e019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP828"              ,	   0x1180080e019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP829"              ,	   0x1180080e019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP830"              ,	   0x1180080e019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP831"              ,	   0x1180080e019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP832"              ,	   0x1180080e01a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP833"              ,	   0x1180080e01a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP834"              ,	   0x1180080e01a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP835"              ,	   0x1180080e01a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP836"              ,	   0x1180080e01a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP837"              ,	   0x1180080e01a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP838"              ,	   0x1180080e01a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP839"              ,	   0x1180080e01a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP840"              ,	   0x1180080e01a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP841"              ,	   0x1180080e01a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP842"              ,	   0x1180080e01a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP843"              ,	   0x1180080e01a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP844"              ,	   0x1180080e01a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP845"              ,	   0x1180080e01a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP846"              ,	   0x1180080e01a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP847"              ,	   0x1180080e01a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP848"              ,	   0x1180080e01a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP849"              ,	   0x1180080e01a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP850"              ,	   0x1180080e01a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP851"              ,	   0x1180080e01a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP852"              ,	   0x1180080e01aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP853"              ,	   0x1180080e01aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP854"              ,	   0x1180080e01ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP855"              ,	   0x1180080e01ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP856"              ,	   0x1180080e01ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP857"              ,	   0x1180080e01ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP858"              ,	   0x1180080e01ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP859"              ,	   0x1180080e01ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP860"              ,	   0x1180080e01ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP861"              ,	   0x1180080e01ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP862"              ,	   0x1180080e01af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP863"              ,	   0x1180080e01af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP864"              ,	   0x1180080e01b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP865"              ,	   0x1180080e01b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP866"              ,	   0x1180080e01b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP867"              ,	   0x1180080e01b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP868"              ,	   0x1180080e01b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP869"              ,	   0x1180080e01b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP870"              ,	   0x1180080e01b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP871"              ,	   0x1180080e01b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP872"              ,	   0x1180080e01b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP873"              ,	   0x1180080e01b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP874"              ,	   0x1180080e01b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP875"              ,	   0x1180080e01b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP876"              ,	   0x1180080e01b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP877"              ,	   0x1180080e01b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP878"              ,	   0x1180080e01b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP879"              ,	   0x1180080e01b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP880"              ,	   0x1180080e01b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP881"              ,	   0x1180080e01b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP882"              ,	   0x1180080e01b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP883"              ,	   0x1180080e01b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP884"              ,	   0x1180080e01ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP885"              ,	   0x1180080e01ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP886"              ,	   0x1180080e01bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP887"              ,	   0x1180080e01bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP888"              ,	   0x1180080e01bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP889"              ,	   0x1180080e01bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP890"              ,	   0x1180080e01bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP891"              ,	   0x1180080e01bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP892"              ,	   0x1180080e01be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP893"              ,	   0x1180080e01be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP894"              ,	   0x1180080e01bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP895"              ,	   0x1180080e01bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP896"              ,	   0x1180080e01c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP897"              ,	   0x1180080e01c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP898"              ,	   0x1180080e01c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP899"              ,	   0x1180080e01c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP900"              ,	   0x1180080e01c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP901"              ,	   0x1180080e01c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP902"              ,	   0x1180080e01c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP903"              ,	   0x1180080e01c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP904"              ,	   0x1180080e01c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP905"              ,	   0x1180080e01c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP906"              ,	   0x1180080e01c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP907"              ,	   0x1180080e01c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP908"              ,	   0x1180080e01c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP909"              ,	   0x1180080e01c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP910"              ,	   0x1180080e01c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP911"              ,	   0x1180080e01c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP912"              ,	   0x1180080e01c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP913"              ,	   0x1180080e01c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP914"              ,	   0x1180080e01c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP915"              ,	   0x1180080e01c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP916"              ,	   0x1180080e01ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP917"              ,	   0x1180080e01ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP918"              ,	   0x1180080e01cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP919"              ,	   0x1180080e01cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP920"              ,	   0x1180080e01cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP921"              ,	   0x1180080e01cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP922"              ,	   0x1180080e01cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP923"              ,	   0x1180080e01cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP924"              ,	   0x1180080e01ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP925"              ,	   0x1180080e01ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP926"              ,	   0x1180080e01cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP927"              ,	   0x1180080e01cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP928"              ,	   0x1180080e01d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP929"              ,	   0x1180080e01d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP930"              ,	   0x1180080e01d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP931"              ,	   0x1180080e01d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP932"              ,	   0x1180080e01d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP933"              ,	   0x1180080e01d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP934"              ,	   0x1180080e01d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP935"              ,	   0x1180080e01d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP936"              ,	   0x1180080e01d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP937"              ,	   0x1180080e01d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP938"              ,	   0x1180080e01d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP939"              ,	   0x1180080e01d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP940"              ,	   0x1180080e01d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP941"              ,	   0x1180080e01d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP942"              ,	   0x1180080e01d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP943"              ,	   0x1180080e01d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP944"              ,	   0x1180080e01d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP945"              ,	   0x1180080e01d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP946"              ,	   0x1180080e01d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP947"              ,	   0x1180080e01d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP948"              ,	   0x1180080e01da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP949"              ,	   0x1180080e01da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP950"              ,	   0x1180080e01db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP951"              ,	   0x1180080e01db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP952"              ,	   0x1180080e01dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP953"              ,	   0x1180080e01dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP954"              ,	   0x1180080e01dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP955"              ,	   0x1180080e01dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP956"              ,	   0x1180080e01de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP957"              ,	   0x1180080e01de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP958"              ,	   0x1180080e01df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP959"              ,	   0x1180080e01df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP960"              ,	   0x1180080e01e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP961"              ,	   0x1180080e01e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP962"              ,	   0x1180080e01e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP963"              ,	   0x1180080e01e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP964"              ,	   0x1180080e01e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP965"              ,	   0x1180080e01e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP966"              ,	   0x1180080e01e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP967"              ,	   0x1180080e01e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP968"              ,	   0x1180080e01e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP969"              ,	   0x1180080e01e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP970"              ,	   0x1180080e01e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP971"              ,	   0x1180080e01e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP972"              ,	   0x1180080e01e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP973"              ,	   0x1180080e01e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP974"              ,	   0x1180080e01e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP975"              ,	   0x1180080e01e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP976"              ,	   0x1180080e01e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP977"              ,	   0x1180080e01e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP978"              ,	   0x1180080e01e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP979"              ,	   0x1180080e01e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP980"              ,	   0x1180080e01ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP981"              ,	   0x1180080e01ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP982"              ,	   0x1180080e01eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP983"              ,	   0x1180080e01eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP984"              ,	   0x1180080e01ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP985"              ,	   0x1180080e01ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP986"              ,	   0x1180080e01ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP987"              ,	   0x1180080e01ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP988"              ,	   0x1180080e01ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP989"              ,	   0x1180080e01ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP990"              ,	   0x1180080e01ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP991"              ,	   0x1180080e01ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP992"              ,	   0x1180080e01f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP993"              ,	   0x1180080e01f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP994"              ,	   0x1180080e01f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP995"              ,	   0x1180080e01f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP996"              ,	   0x1180080e01f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP997"              ,	   0x1180080e01f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP998"              ,	   0x1180080e01f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP999"              ,	   0x1180080e01f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1000"             ,	   0x1180080e01f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1001"             ,	   0x1180080e01f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1002"             ,	   0x1180080e01f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1003"             ,	   0x1180080e01f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1004"             ,	   0x1180080e01f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1005"             ,	   0x1180080e01f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1006"             ,	   0x1180080e01f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1007"             ,	   0x1180080e01f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1008"             ,	   0x1180080e01f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1009"             ,	   0x1180080e01f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1010"             ,	   0x1180080e01f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1011"             ,	   0x1180080e01f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1012"             ,	   0x1180080e01fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1013"             ,	   0x1180080e01fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1014"             ,	   0x1180080e01fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1015"             ,	   0x1180080e01fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1016"             ,	   0x1180080e01fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1017"             ,	   0x1180080e01fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1018"             ,	   0x1180080e01fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1019"             ,	   0x1180080e01fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1020"             ,	   0x1180080e01fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1021"             ,	   0x1180080e01fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1022"             ,	   0x1180080e01ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1023"             ,	   0x1180080e01ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1024"             ,	   0x1180080e02000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1025"             ,	   0x1180080e02008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1026"             ,	   0x1180080e02010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1027"             ,	   0x1180080e02018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1028"             ,	   0x1180080e02020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1029"             ,	   0x1180080e02028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1030"             ,	   0x1180080e02030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1031"             ,	   0x1180080e02038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1032"             ,	   0x1180080e02040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1033"             ,	   0x1180080e02048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1034"             ,	   0x1180080e02050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1035"             ,	   0x1180080e02058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1036"             ,	   0x1180080e02060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1037"             ,	   0x1180080e02068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1038"             ,	   0x1180080e02070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1039"             ,	   0x1180080e02078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1040"             ,	   0x1180080e02080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1041"             ,	   0x1180080e02088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1042"             ,	   0x1180080e02090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1043"             ,	   0x1180080e02098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1044"             ,	   0x1180080e020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1045"             ,	   0x1180080e020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1046"             ,	   0x1180080e020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1047"             ,	   0x1180080e020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1048"             ,	   0x1180080e020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1049"             ,	   0x1180080e020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1050"             ,	   0x1180080e020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1051"             ,	   0x1180080e020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1052"             ,	   0x1180080e020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1053"             ,	   0x1180080e020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1054"             ,	   0x1180080e020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1055"             ,	   0x1180080e020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1056"             ,	   0x1180080e02100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1057"             ,	   0x1180080e02108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1058"             ,	   0x1180080e02110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1059"             ,	   0x1180080e02118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1060"             ,	   0x1180080e02120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1061"             ,	   0x1180080e02128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1062"             ,	   0x1180080e02130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1063"             ,	   0x1180080e02138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1064"             ,	   0x1180080e02140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1065"             ,	   0x1180080e02148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1066"             ,	   0x1180080e02150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1067"             ,	   0x1180080e02158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1068"             ,	   0x1180080e02160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1069"             ,	   0x1180080e02168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1070"             ,	   0x1180080e02170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1071"             ,	   0x1180080e02178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1072"             ,	   0x1180080e02180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1073"             ,	   0x1180080e02188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1074"             ,	   0x1180080e02190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1075"             ,	   0x1180080e02198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1076"             ,	   0x1180080e021a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1077"             ,	   0x1180080e021a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1078"             ,	   0x1180080e021b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1079"             ,	   0x1180080e021b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1080"             ,	   0x1180080e021c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1081"             ,	   0x1180080e021c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1082"             ,	   0x1180080e021d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1083"             ,	   0x1180080e021d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1084"             ,	   0x1180080e021e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1085"             ,	   0x1180080e021e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1086"             ,	   0x1180080e021f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1087"             ,	   0x1180080e021f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1088"             ,	   0x1180080e02200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1089"             ,	   0x1180080e02208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1090"             ,	   0x1180080e02210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1091"             ,	   0x1180080e02218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1092"             ,	   0x1180080e02220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1093"             ,	   0x1180080e02228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1094"             ,	   0x1180080e02230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1095"             ,	   0x1180080e02238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1096"             ,	   0x1180080e02240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1097"             ,	   0x1180080e02248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1098"             ,	   0x1180080e02250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1099"             ,	   0x1180080e02258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1100"             ,	   0x1180080e02260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1101"             ,	   0x1180080e02268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1102"             ,	   0x1180080e02270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1103"             ,	   0x1180080e02278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1104"             ,	   0x1180080e02280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1105"             ,	   0x1180080e02288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1106"             ,	   0x1180080e02290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1107"             ,	   0x1180080e02298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1108"             ,	   0x1180080e022a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1109"             ,	   0x1180080e022a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1110"             ,	   0x1180080e022b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1111"             ,	   0x1180080e022b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1112"             ,	   0x1180080e022c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1113"             ,	   0x1180080e022c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1114"             ,	   0x1180080e022d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1115"             ,	   0x1180080e022d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1116"             ,	   0x1180080e022e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1117"             ,	   0x1180080e022e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1118"             ,	   0x1180080e022f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1119"             ,	   0x1180080e022f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1120"             ,	   0x1180080e02300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1121"             ,	   0x1180080e02308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1122"             ,	   0x1180080e02310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1123"             ,	   0x1180080e02318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1124"             ,	   0x1180080e02320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1125"             ,	   0x1180080e02328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1126"             ,	   0x1180080e02330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1127"             ,	   0x1180080e02338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1128"             ,	   0x1180080e02340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1129"             ,	   0x1180080e02348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1130"             ,	   0x1180080e02350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1131"             ,	   0x1180080e02358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1132"             ,	   0x1180080e02360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1133"             ,	   0x1180080e02368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1134"             ,	   0x1180080e02370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1135"             ,	   0x1180080e02378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1136"             ,	   0x1180080e02380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1137"             ,	   0x1180080e02388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1138"             ,	   0x1180080e02390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1139"             ,	   0x1180080e02398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1140"             ,	   0x1180080e023a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1141"             ,	   0x1180080e023a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1142"             ,	   0x1180080e023b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1143"             ,	   0x1180080e023b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1144"             ,	   0x1180080e023c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1145"             ,	   0x1180080e023c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1146"             ,	   0x1180080e023d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1147"             ,	   0x1180080e023d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1148"             ,	   0x1180080e023e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1149"             ,	   0x1180080e023e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1150"             ,	   0x1180080e023f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1151"             ,	   0x1180080e023f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1152"             ,	   0x1180080e02400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1153"             ,	   0x1180080e02408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1154"             ,	   0x1180080e02410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1155"             ,	   0x1180080e02418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1156"             ,	   0x1180080e02420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1157"             ,	   0x1180080e02428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1158"             ,	   0x1180080e02430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1159"             ,	   0x1180080e02438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1160"             ,	   0x1180080e02440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1161"             ,	   0x1180080e02448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1162"             ,	   0x1180080e02450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1163"             ,	   0x1180080e02458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1164"             ,	   0x1180080e02460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1165"             ,	   0x1180080e02468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1166"             ,	   0x1180080e02470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1167"             ,	   0x1180080e02478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1168"             ,	   0x1180080e02480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1169"             ,	   0x1180080e02488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1170"             ,	   0x1180080e02490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1171"             ,	   0x1180080e02498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1172"             ,	   0x1180080e024a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1173"             ,	   0x1180080e024a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1174"             ,	   0x1180080e024b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1175"             ,	   0x1180080e024b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1176"             ,	   0x1180080e024c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1177"             ,	   0x1180080e024c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1178"             ,	   0x1180080e024d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1179"             ,	   0x1180080e024d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1180"             ,	   0x1180080e024e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1181"             ,	   0x1180080e024e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1182"             ,	   0x1180080e024f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1183"             ,	   0x1180080e024f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1184"             ,	   0x1180080e02500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1185"             ,	   0x1180080e02508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1186"             ,	   0x1180080e02510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1187"             ,	   0x1180080e02518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1188"             ,	   0x1180080e02520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1189"             ,	   0x1180080e02528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1190"             ,	   0x1180080e02530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1191"             ,	   0x1180080e02538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1192"             ,	   0x1180080e02540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1193"             ,	   0x1180080e02548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1194"             ,	   0x1180080e02550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1195"             ,	   0x1180080e02558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1196"             ,	   0x1180080e02560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1197"             ,	   0x1180080e02568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1198"             ,	   0x1180080e02570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1199"             ,	   0x1180080e02578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1200"             ,	   0x1180080e02580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1201"             ,	   0x1180080e02588ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1202"             ,	   0x1180080e02590ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1203"             ,	   0x1180080e02598ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1204"             ,	   0x1180080e025a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1205"             ,	   0x1180080e025a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1206"             ,	   0x1180080e025b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1207"             ,	   0x1180080e025b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1208"             ,	   0x1180080e025c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1209"             ,	   0x1180080e025c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1210"             ,	   0x1180080e025d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1211"             ,	   0x1180080e025d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1212"             ,	   0x1180080e025e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1213"             ,	   0x1180080e025e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1214"             ,	   0x1180080e025f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1215"             ,	   0x1180080e025f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1216"             ,	   0x1180080e02600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1217"             ,	   0x1180080e02608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1218"             ,	   0x1180080e02610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1219"             ,	   0x1180080e02618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1220"             ,	   0x1180080e02620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1221"             ,	   0x1180080e02628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1222"             ,	   0x1180080e02630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1223"             ,	   0x1180080e02638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1224"             ,	   0x1180080e02640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1225"             ,	   0x1180080e02648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1226"             ,	   0x1180080e02650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1227"             ,	   0x1180080e02658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1228"             ,	   0x1180080e02660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1229"             ,	   0x1180080e02668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1230"             ,	   0x1180080e02670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1231"             ,	   0x1180080e02678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1232"             ,	   0x1180080e02680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1233"             ,	   0x1180080e02688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1234"             ,	   0x1180080e02690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1235"             ,	   0x1180080e02698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1236"             ,	   0x1180080e026a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1237"             ,	   0x1180080e026a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1238"             ,	   0x1180080e026b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1239"             ,	   0x1180080e026b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1240"             ,	   0x1180080e026c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1241"             ,	   0x1180080e026c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1242"             ,	   0x1180080e026d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1243"             ,	   0x1180080e026d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1244"             ,	   0x1180080e026e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1245"             ,	   0x1180080e026e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1246"             ,	   0x1180080e026f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1247"             ,	   0x1180080e026f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1248"             ,	   0x1180080e02700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1249"             ,	   0x1180080e02708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1250"             ,	   0x1180080e02710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1251"             ,	   0x1180080e02718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1252"             ,	   0x1180080e02720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1253"             ,	   0x1180080e02728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1254"             ,	   0x1180080e02730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1255"             ,	   0x1180080e02738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1256"             ,	   0x1180080e02740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1257"             ,	   0x1180080e02748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1258"             ,	   0x1180080e02750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1259"             ,	   0x1180080e02758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1260"             ,	   0x1180080e02760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1261"             ,	   0x1180080e02768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1262"             ,	   0x1180080e02770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1263"             ,	   0x1180080e02778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1264"             ,	   0x1180080e02780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1265"             ,	   0x1180080e02788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1266"             ,	   0x1180080e02790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1267"             ,	   0x1180080e02798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1268"             ,	   0x1180080e027a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1269"             ,	   0x1180080e027a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1270"             ,	   0x1180080e027b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1271"             ,	   0x1180080e027b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1272"             ,	   0x1180080e027c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1273"             ,	   0x1180080e027c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1274"             ,	   0x1180080e027d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1275"             ,	   0x1180080e027d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1276"             ,	   0x1180080e027e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1277"             ,	   0x1180080e027e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1278"             ,	   0x1180080e027f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1279"             ,	   0x1180080e027f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1280"             ,	   0x1180080e02800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1281"             ,	   0x1180080e02808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1282"             ,	   0x1180080e02810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1283"             ,	   0x1180080e02818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1284"             ,	   0x1180080e02820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1285"             ,	   0x1180080e02828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1286"             ,	   0x1180080e02830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1287"             ,	   0x1180080e02838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1288"             ,	   0x1180080e02840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1289"             ,	   0x1180080e02848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1290"             ,	   0x1180080e02850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1291"             ,	   0x1180080e02858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1292"             ,	   0x1180080e02860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1293"             ,	   0x1180080e02868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1294"             ,	   0x1180080e02870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1295"             ,	   0x1180080e02878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1296"             ,	   0x1180080e02880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1297"             ,	   0x1180080e02888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1298"             ,	   0x1180080e02890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1299"             ,	   0x1180080e02898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1300"             ,	   0x1180080e028a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1301"             ,	   0x1180080e028a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1302"             ,	   0x1180080e028b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1303"             ,	   0x1180080e028b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1304"             ,	   0x1180080e028c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1305"             ,	   0x1180080e028c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1306"             ,	   0x1180080e028d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1307"             ,	   0x1180080e028d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1308"             ,	   0x1180080e028e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1309"             ,	   0x1180080e028e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1310"             ,	   0x1180080e028f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1311"             ,	   0x1180080e028f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1312"             ,	   0x1180080e02900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1313"             ,	   0x1180080e02908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1314"             ,	   0x1180080e02910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1315"             ,	   0x1180080e02918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1316"             ,	   0x1180080e02920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1317"             ,	   0x1180080e02928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1318"             ,	   0x1180080e02930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1319"             ,	   0x1180080e02938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1320"             ,	   0x1180080e02940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1321"             ,	   0x1180080e02948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1322"             ,	   0x1180080e02950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1323"             ,	   0x1180080e02958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1324"             ,	   0x1180080e02960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1325"             ,	   0x1180080e02968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1326"             ,	   0x1180080e02970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1327"             ,	   0x1180080e02978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1328"             ,	   0x1180080e02980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1329"             ,	   0x1180080e02988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1330"             ,	   0x1180080e02990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1331"             ,	   0x1180080e02998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1332"             ,	   0x1180080e029a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1333"             ,	   0x1180080e029a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1334"             ,	   0x1180080e029b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1335"             ,	   0x1180080e029b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1336"             ,	   0x1180080e029c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1337"             ,	   0x1180080e029c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1338"             ,	   0x1180080e029d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1339"             ,	   0x1180080e029d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1340"             ,	   0x1180080e029e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1341"             ,	   0x1180080e029e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1342"             ,	   0x1180080e029f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1343"             ,	   0x1180080e029f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1344"             ,	   0x1180080e02a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1345"             ,	   0x1180080e02a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1346"             ,	   0x1180080e02a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1347"             ,	   0x1180080e02a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1348"             ,	   0x1180080e02a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1349"             ,	   0x1180080e02a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1350"             ,	   0x1180080e02a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1351"             ,	   0x1180080e02a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1352"             ,	   0x1180080e02a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1353"             ,	   0x1180080e02a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1354"             ,	   0x1180080e02a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1355"             ,	   0x1180080e02a58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1356"             ,	   0x1180080e02a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1357"             ,	   0x1180080e02a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1358"             ,	   0x1180080e02a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1359"             ,	   0x1180080e02a78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1360"             ,	   0x1180080e02a80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1361"             ,	   0x1180080e02a88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1362"             ,	   0x1180080e02a90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1363"             ,	   0x1180080e02a98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1364"             ,	   0x1180080e02aa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1365"             ,	   0x1180080e02aa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1366"             ,	   0x1180080e02ab0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1367"             ,	   0x1180080e02ab8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1368"             ,	   0x1180080e02ac0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1369"             ,	   0x1180080e02ac8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1370"             ,	   0x1180080e02ad0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1371"             ,	   0x1180080e02ad8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1372"             ,	   0x1180080e02ae0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1373"             ,	   0x1180080e02ae8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1374"             ,	   0x1180080e02af0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1375"             ,	   0x1180080e02af8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1376"             ,	   0x1180080e02b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1377"             ,	   0x1180080e02b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1378"             ,	   0x1180080e02b10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1379"             ,	   0x1180080e02b18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1380"             ,	   0x1180080e02b20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1381"             ,	   0x1180080e02b28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1382"             ,	   0x1180080e02b30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1383"             ,	   0x1180080e02b38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1384"             ,	   0x1180080e02b40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1385"             ,	   0x1180080e02b48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1386"             ,	   0x1180080e02b50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1387"             ,	   0x1180080e02b58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1388"             ,	   0x1180080e02b60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1389"             ,	   0x1180080e02b68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1390"             ,	   0x1180080e02b70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1391"             ,	   0x1180080e02b78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1392"             ,	   0x1180080e02b80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1393"             ,	   0x1180080e02b88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1394"             ,	   0x1180080e02b90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1395"             ,	   0x1180080e02b98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1396"             ,	   0x1180080e02ba0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1397"             ,	   0x1180080e02ba8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1398"             ,	   0x1180080e02bb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1399"             ,	   0x1180080e02bb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1400"             ,	   0x1180080e02bc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1401"             ,	   0x1180080e02bc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1402"             ,	   0x1180080e02bd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1403"             ,	   0x1180080e02bd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1404"             ,	   0x1180080e02be0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1405"             ,	   0x1180080e02be8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1406"             ,	   0x1180080e02bf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1407"             ,	   0x1180080e02bf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1408"             ,	   0x1180080e02c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1409"             ,	   0x1180080e02c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1410"             ,	   0x1180080e02c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1411"             ,	   0x1180080e02c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1412"             ,	   0x1180080e02c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1413"             ,	   0x1180080e02c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1414"             ,	   0x1180080e02c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1415"             ,	   0x1180080e02c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1416"             ,	   0x1180080e02c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1417"             ,	   0x1180080e02c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1418"             ,	   0x1180080e02c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1419"             ,	   0x1180080e02c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1420"             ,	   0x1180080e02c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1421"             ,	   0x1180080e02c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1422"             ,	   0x1180080e02c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1423"             ,	   0x1180080e02c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1424"             ,	   0x1180080e02c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1425"             ,	   0x1180080e02c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1426"             ,	   0x1180080e02c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1427"             ,	   0x1180080e02c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1428"             ,	   0x1180080e02ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1429"             ,	   0x1180080e02ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1430"             ,	   0x1180080e02cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1431"             ,	   0x1180080e02cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1432"             ,	   0x1180080e02cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1433"             ,	   0x1180080e02cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1434"             ,	   0x1180080e02cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1435"             ,	   0x1180080e02cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1436"             ,	   0x1180080e02ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1437"             ,	   0x1180080e02ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1438"             ,	   0x1180080e02cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1439"             ,	   0x1180080e02cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1440"             ,	   0x1180080e02d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1441"             ,	   0x1180080e02d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1442"             ,	   0x1180080e02d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1443"             ,	   0x1180080e02d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1444"             ,	   0x1180080e02d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1445"             ,	   0x1180080e02d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1446"             ,	   0x1180080e02d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1447"             ,	   0x1180080e02d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1448"             ,	   0x1180080e02d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1449"             ,	   0x1180080e02d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1450"             ,	   0x1180080e02d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1451"             ,	   0x1180080e02d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1452"             ,	   0x1180080e02d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1453"             ,	   0x1180080e02d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1454"             ,	   0x1180080e02d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1455"             ,	   0x1180080e02d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1456"             ,	   0x1180080e02d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1457"             ,	   0x1180080e02d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1458"             ,	   0x1180080e02d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1459"             ,	   0x1180080e02d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1460"             ,	   0x1180080e02da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1461"             ,	   0x1180080e02da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1462"             ,	   0x1180080e02db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1463"             ,	   0x1180080e02db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1464"             ,	   0x1180080e02dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1465"             ,	   0x1180080e02dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1466"             ,	   0x1180080e02dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1467"             ,	   0x1180080e02dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1468"             ,	   0x1180080e02de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1469"             ,	   0x1180080e02de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1470"             ,	   0x1180080e02df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1471"             ,	   0x1180080e02df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1472"             ,	   0x1180080e02e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1473"             ,	   0x1180080e02e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1474"             ,	   0x1180080e02e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1475"             ,	   0x1180080e02e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1476"             ,	   0x1180080e02e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1477"             ,	   0x1180080e02e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1478"             ,	   0x1180080e02e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1479"             ,	   0x1180080e02e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1480"             ,	   0x1180080e02e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1481"             ,	   0x1180080e02e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1482"             ,	   0x1180080e02e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1483"             ,	   0x1180080e02e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1484"             ,	   0x1180080e02e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1485"             ,	   0x1180080e02e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1486"             ,	   0x1180080e02e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1487"             ,	   0x1180080e02e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1488"             ,	   0x1180080e02e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1489"             ,	   0x1180080e02e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1490"             ,	   0x1180080e02e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1491"             ,	   0x1180080e02e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1492"             ,	   0x1180080e02ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1493"             ,	   0x1180080e02ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1494"             ,	   0x1180080e02eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1495"             ,	   0x1180080e02eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1496"             ,	   0x1180080e02ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1497"             ,	   0x1180080e02ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1498"             ,	   0x1180080e02ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1499"             ,	   0x1180080e02ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1500"             ,	   0x1180080e02ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1501"             ,	   0x1180080e02ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1502"             ,	   0x1180080e02ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1503"             ,	   0x1180080e02ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1504"             ,	   0x1180080e02f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1505"             ,	   0x1180080e02f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1506"             ,	   0x1180080e02f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1507"             ,	   0x1180080e02f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1508"             ,	   0x1180080e02f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1509"             ,	   0x1180080e02f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1510"             ,	   0x1180080e02f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1511"             ,	   0x1180080e02f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1512"             ,	   0x1180080e02f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1513"             ,	   0x1180080e02f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1514"             ,	   0x1180080e02f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1515"             ,	   0x1180080e02f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1516"             ,	   0x1180080e02f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1517"             ,	   0x1180080e02f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1518"             ,	   0x1180080e02f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1519"             ,	   0x1180080e02f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1520"             ,	   0x1180080e02f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1521"             ,	   0x1180080e02f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1522"             ,	   0x1180080e02f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1523"             ,	   0x1180080e02f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1524"             ,	   0x1180080e02fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1525"             ,	   0x1180080e02fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1526"             ,	   0x1180080e02fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1527"             ,	   0x1180080e02fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1528"             ,	   0x1180080e02fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1529"             ,	   0x1180080e02fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1530"             ,	   0x1180080e02fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1531"             ,	   0x1180080e02fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1532"             ,	   0x1180080e02fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1533"             ,	   0x1180080e02fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1534"             ,	   0x1180080e02ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_DUT_MAP1535"             ,	   0x1180080e02ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"L2C_ERR_TDT0"                ,	   0x1180080a007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"L2C_ERR_TTG0"                ,	   0x1180080a007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"L2C_ERR_VBF0"                ,	   0x1180080c007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"L2C_ERR_XMC"                 ,	   0x11800808007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"L2C_INT_ENA"                 ,	   0x1180080800020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"L2C_INT_REG"                 ,	   0x1180080800018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"L2C_IOC0_PFC"                ,	   0x1180080800420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"L2C_IOR0_PFC"                ,	   0x1180080800428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"L2C_QOS_IOB0"                ,	   0x1180080880200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"L2C_QOS_PP0"                 ,	   0x1180080880000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP1"                 ,	   0x1180080880008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP2"                 ,	   0x1180080880010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP3"                 ,	   0x1180080880018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP4"                 ,	   0x1180080880020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_PP5"                 ,	   0x1180080880028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"L2C_QOS_WGT"                 ,	   0x1180080800008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"L2C_RSC0_PFC"                ,	   0x1180080800410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"L2C_RSD0_PFC"                ,	   0x1180080800418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"L2C_TAD0_ECC0"               ,	   0x1180080a00018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"L2C_TAD0_ECC1"               ,	   0x1180080a00020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"L2C_TAD0_IEN"                ,	   0x1180080a00000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"L2C_TAD0_INT"                ,	   0x1180080a00028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"L2C_TAD0_PFC0"               ,	   0x1180080a00400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"L2C_TAD0_PFC1"               ,	   0x1180080a00408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"L2C_TAD0_PFC2"               ,	   0x1180080a00410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"L2C_TAD0_PFC3"               ,	   0x1180080a00418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"L2C_TAD0_PRF"                ,	   0x1180080a00008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"L2C_TAD0_TAG"                ,	   0x1180080a00010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"L2C_VER_ID"                  ,	   0x11800808007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"L2C_VER_IOB"                 ,	   0x11800808007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"L2C_VER_MSC"                 ,	   0x11800808007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"L2C_VER_PP"                  ,	   0x11800808007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"L2C_VIRTID_IOB0"             ,	   0x11800808c0200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"L2C_VIRTID_PP0"              ,	   0x11800808c0000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP1"              ,	   0x11800808c0008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP2"              ,	   0x11800808c0010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP3"              ,	   0x11800808c0018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP4"              ,	   0x11800808c0020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VIRTID_PP5"              ,	   0x11800808c0028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"L2C_VRT_CTL"                 ,	   0x1180080800010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"L2C_VRT_MEM0"                ,	   0x1180080900000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1"                ,	   0x1180080900008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM2"                ,	   0x1180080900010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM3"                ,	   0x1180080900018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM4"                ,	   0x1180080900020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM5"                ,	   0x1180080900028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM6"                ,	   0x1180080900030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM7"                ,	   0x1180080900038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM8"                ,	   0x1180080900040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM9"                ,	   0x1180080900048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM10"               ,	   0x1180080900050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM11"               ,	   0x1180080900058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM12"               ,	   0x1180080900060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM13"               ,	   0x1180080900068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM14"               ,	   0x1180080900070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM15"               ,	   0x1180080900078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM16"               ,	   0x1180080900080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM17"               ,	   0x1180080900088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM18"               ,	   0x1180080900090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM19"               ,	   0x1180080900098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM20"               ,	   0x11800809000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM21"               ,	   0x11800809000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM22"               ,	   0x11800809000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM23"               ,	   0x11800809000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM24"               ,	   0x11800809000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM25"               ,	   0x11800809000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM26"               ,	   0x11800809000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM27"               ,	   0x11800809000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM28"               ,	   0x11800809000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM29"               ,	   0x11800809000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM30"               ,	   0x11800809000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM31"               ,	   0x11800809000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM32"               ,	   0x1180080900100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM33"               ,	   0x1180080900108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM34"               ,	   0x1180080900110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM35"               ,	   0x1180080900118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM36"               ,	   0x1180080900120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM37"               ,	   0x1180080900128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM38"               ,	   0x1180080900130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM39"               ,	   0x1180080900138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM40"               ,	   0x1180080900140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM41"               ,	   0x1180080900148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM42"               ,	   0x1180080900150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM43"               ,	   0x1180080900158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM44"               ,	   0x1180080900160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM45"               ,	   0x1180080900168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM46"               ,	   0x1180080900170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM47"               ,	   0x1180080900178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM48"               ,	   0x1180080900180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM49"               ,	   0x1180080900188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM50"               ,	   0x1180080900190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM51"               ,	   0x1180080900198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM52"               ,	   0x11800809001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM53"               ,	   0x11800809001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM54"               ,	   0x11800809001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM55"               ,	   0x11800809001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM56"               ,	   0x11800809001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM57"               ,	   0x11800809001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM58"               ,	   0x11800809001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM59"               ,	   0x11800809001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM60"               ,	   0x11800809001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM61"               ,	   0x11800809001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM62"               ,	   0x11800809001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM63"               ,	   0x11800809001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM64"               ,	   0x1180080900200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM65"               ,	   0x1180080900208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM66"               ,	   0x1180080900210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM67"               ,	   0x1180080900218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM68"               ,	   0x1180080900220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM69"               ,	   0x1180080900228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM70"               ,	   0x1180080900230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM71"               ,	   0x1180080900238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM72"               ,	   0x1180080900240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM73"               ,	   0x1180080900248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM74"               ,	   0x1180080900250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM75"               ,	   0x1180080900258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM76"               ,	   0x1180080900260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM77"               ,	   0x1180080900268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM78"               ,	   0x1180080900270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM79"               ,	   0x1180080900278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM80"               ,	   0x1180080900280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM81"               ,	   0x1180080900288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
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+	{"L2C_VRT_MEM910"              ,	   0x1180080901c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM911"              ,	   0x1180080901c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM912"              ,	   0x1180080901c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM913"              ,	   0x1180080901c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM914"              ,	   0x1180080901c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM915"              ,	   0x1180080901c98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM916"              ,	   0x1180080901ca0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM917"              ,	   0x1180080901ca8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM918"              ,	   0x1180080901cb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM919"              ,	   0x1180080901cb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM920"              ,	   0x1180080901cc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM921"              ,	   0x1180080901cc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM922"              ,	   0x1180080901cd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM923"              ,	   0x1180080901cd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM924"              ,	   0x1180080901ce0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM925"              ,	   0x1180080901ce8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM926"              ,	   0x1180080901cf0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM927"              ,	   0x1180080901cf8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM928"              ,	   0x1180080901d00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM929"              ,	   0x1180080901d08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM930"              ,	   0x1180080901d10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM931"              ,	   0x1180080901d18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM932"              ,	   0x1180080901d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM933"              ,	   0x1180080901d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM934"              ,	   0x1180080901d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM935"              ,	   0x1180080901d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM936"              ,	   0x1180080901d40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM937"              ,	   0x1180080901d48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM938"              ,	   0x1180080901d50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM939"              ,	   0x1180080901d58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM940"              ,	   0x1180080901d60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM941"              ,	   0x1180080901d68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM942"              ,	   0x1180080901d70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM943"              ,	   0x1180080901d78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM944"              ,	   0x1180080901d80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM945"              ,	   0x1180080901d88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM946"              ,	   0x1180080901d90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM947"              ,	   0x1180080901d98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM948"              ,	   0x1180080901da0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM949"              ,	   0x1180080901da8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM950"              ,	   0x1180080901db0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM951"              ,	   0x1180080901db8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM952"              ,	   0x1180080901dc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM953"              ,	   0x1180080901dc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM954"              ,	   0x1180080901dd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM955"              ,	   0x1180080901dd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM956"              ,	   0x1180080901de0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM957"              ,	   0x1180080901de8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM958"              ,	   0x1180080901df0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM959"              ,	   0x1180080901df8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM960"              ,	   0x1180080901e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM961"              ,	   0x1180080901e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM962"              ,	   0x1180080901e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM963"              ,	   0x1180080901e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM964"              ,	   0x1180080901e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM965"              ,	   0x1180080901e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM966"              ,	   0x1180080901e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM967"              ,	   0x1180080901e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM968"              ,	   0x1180080901e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM969"              ,	   0x1180080901e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM970"              ,	   0x1180080901e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM971"              ,	   0x1180080901e58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM972"              ,	   0x1180080901e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM973"              ,	   0x1180080901e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM974"              ,	   0x1180080901e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM975"              ,	   0x1180080901e78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM976"              ,	   0x1180080901e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM977"              ,	   0x1180080901e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM978"              ,	   0x1180080901e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM979"              ,	   0x1180080901e98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM980"              ,	   0x1180080901ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM981"              ,	   0x1180080901ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM982"              ,	   0x1180080901eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM983"              ,	   0x1180080901eb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM984"              ,	   0x1180080901ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM985"              ,	   0x1180080901ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM986"              ,	   0x1180080901ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM987"              ,	   0x1180080901ed8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM988"              ,	   0x1180080901ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM989"              ,	   0x1180080901ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM990"              ,	   0x1180080901ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM991"              ,	   0x1180080901ef8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM992"              ,	   0x1180080901f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM993"              ,	   0x1180080901f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM994"              ,	   0x1180080901f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM995"              ,	   0x1180080901f18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM996"              ,	   0x1180080901f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM997"              ,	   0x1180080901f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM998"              ,	   0x1180080901f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM999"              ,	   0x1180080901f38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1000"             ,	   0x1180080901f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1001"             ,	   0x1180080901f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1002"             ,	   0x1180080901f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1003"             ,	   0x1180080901f58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1004"             ,	   0x1180080901f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1005"             ,	   0x1180080901f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1006"             ,	   0x1180080901f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1007"             ,	   0x1180080901f78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1008"             ,	   0x1180080901f80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1009"             ,	   0x1180080901f88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1010"             ,	   0x1180080901f90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1011"             ,	   0x1180080901f98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1012"             ,	   0x1180080901fa0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1013"             ,	   0x1180080901fa8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1014"             ,	   0x1180080901fb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1015"             ,	   0x1180080901fb8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1016"             ,	   0x1180080901fc0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1017"             ,	   0x1180080901fc8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1018"             ,	   0x1180080901fd0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1019"             ,	   0x1180080901fd8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1020"             ,	   0x1180080901fe0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1021"             ,	   0x1180080901fe8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1022"             ,	   0x1180080901ff0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_VRT_MEM1023"             ,	   0x1180080901ff8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"L2C_WPAR_IOB0"               ,	   0x1180080840200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"L2C_WPAR_PP0"                ,	   0x1180080840000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP1"                ,	   0x1180080840008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP2"                ,	   0x1180080840010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP3"                ,	   0x1180080840018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP4"                ,	   0x1180080840020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_WPAR_PP5"                ,	   0x1180080840028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"L2C_XMC0_PFC"                ,	   0x1180080800400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"L2C_XMC_CMD"                 ,	   0x1180080800028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"L2C_XMD0_PFC"                ,	   0x1180080800408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"LMC0_CHAR_CTL"               ,	   0x1180088000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"LMC0_CHAR_MASK0"             ,	   0x1180088000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"LMC0_CHAR_MASK1"             ,	   0x1180088000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"LMC0_CHAR_MASK2"             ,	   0x1180088000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"LMC0_CHAR_MASK3"             ,	   0x1180088000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"LMC0_CHAR_MASK4"             ,	   0x1180088000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"LMC0_COMP_CTL2"              ,	   0x11800880001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"LMC0_CONFIG"                 ,	   0x1180088000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"LMC0_CONTROL"                ,	   0x1180088000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"LMC0_DCLK_CNT"               ,	   0x11800880001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"LMC0_DDR_PLL_CTL"            ,	   0x1180088000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"LMC0_DIMM000_PARAMS"         ,	   0x1180088000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"LMC0_DIMM001_PARAMS"         ,	   0x1180088000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"LMC0_DIMM_CTL"               ,	   0x1180088000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"LMC0_DLL_CTL2"               ,	   0x11800880001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"LMC0_DLL_CTL3"               ,	   0x1180088000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"LMC0_IFB_CNT"                ,	   0x11800880001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"LMC0_INT"                    ,	   0x11800880001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"LMC0_INT_EN"                 ,	   0x11800880001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"LMC0_MODEREG_PARAMS0"        ,	   0x11800880001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"LMC0_MODEREG_PARAMS1"        ,	   0x1180088000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"LMC0_NXM"                    ,	   0x11800880000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"LMC0_OPS_CNT"                ,	   0x11800880001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"LMC0_PHY_CTL"                ,	   0x1180088000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"LMC0_RESET_CTL"              ,	   0x1180088000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"LMC0_RLEVEL_CTL"             ,	   0x11800880002a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"LMC0_RLEVEL_DBG"             ,	   0x11800880002a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"LMC0_RLEVEL_RANK000"         ,	   0x1180088000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK001"         ,	   0x1180088000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK002"         ,	   0x1180088000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RLEVEL_RANK003"         ,	   0x1180088000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"LMC0_RODT_MASK"              ,	   0x1180088000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"LMC0_SLOT_CTL0"              ,	   0x11800880001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"LMC0_SLOT_CTL1"              ,	   0x1180088000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"LMC0_SLOT_CTL2"              ,	   0x1180088000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"LMC0_TIMING_PARAMS0"         ,	   0x1180088000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"LMC0_TIMING_PARAMS1"         ,	   0x11800880001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"LMC0_TRO_CTL"                ,	   0x1180088000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"LMC0_TRO_STAT"               ,	   0x1180088000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"LMC0_WLEVEL_CTL"             ,	   0x1180088000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"LMC0_WLEVEL_DBG"             ,	   0x1180088000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"LMC0_WLEVEL_RANK000"         ,	   0x11800880002b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_WLEVEL_RANK001"         ,	   0x11800880002b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_WLEVEL_RANK002"         ,	   0x11800880002c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_WLEVEL_RANK003"         ,	   0x11800880002c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"LMC0_WODT_MASK"              ,	   0x11800880001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"MIO_BOOT_INT"                ,	   0x11800000000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"MIO_BOOT_THR"                ,	   0x11800000000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"MIO_FUS_READ_TIMES"          ,	   0x1180000001570ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"MIO_FUS_REPAIR_RES0"         ,	   0x1180000001558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"MIO_FUS_REPAIR_RES1"         ,	   0x1180000001560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"MIO_FUS_REPAIR_RES2"         ,	   0x1180000001568ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"MIO_GPIO_COMP"               ,	   0x11800000000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"MIO_PTP_CLOCK_CFG"           ,	   0x1070000000f00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"MIO_PTP_CLOCK_COMP"          ,	   0x1070000000f18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"MIO_PTP_CLOCK_HI"            ,	   0x1070000000f10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"MIO_PTP_CLOCK_LO"            ,	   0x1070000000f08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"MIO_PTP_EVT_CNT"             ,	   0x1070000000f28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	491},
+	{"MIO_PTP_TIMESTAMP"           ,	   0x1070000000f20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"MIO_RST_BOOT"                ,	   0x1180000001600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"MIO_RST_CFG"                 ,	   0x1180000001610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"MIO_RST_CTL0"                ,	   0x1180000001618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_RST_CTL1"                ,	   0x1180000001620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"MIO_RST_DELAY"               ,	   0x1180000001608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"MIO_RST_INT"                 ,	   0x1180000001628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"MIO_RST_INT_EN"              ,	   0x1180000001630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_UART1_DLH"               ,	   0x1180000000c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_UART1_DLL"               ,	   0x1180000000c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_UART1_FAR"               ,	   0x1180000000d20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_UART1_FCR"               ,	   0x1180000000c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"MIO_UART0_HTX"               ,	   0x1180000000b08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"MIO_UART1_HTX"               ,	   0x1180000000f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"MIO_UART1_IER"               ,	   0x1180000000c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"MIO_UART1_IIR"               ,	   0x1180000000c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"MIO_UART1_LCR"               ,	   0x1180000000c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"MIO_UART1_LSR"               ,	   0x1180000000c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"MIO_UART1_MCR"               ,	   0x1180000000c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"MIO_UART1_MSR"               ,	   0x1180000000c30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"MIO_UART1_RBR"               ,	   0x1180000000c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"MIO_UART0_RFL"               ,	   0x1180000000a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"MIO_UART1_RFL"               ,	   0x1180000000e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"MIO_UART1_RFW"               ,	   0x1180000000d30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"MIO_UART1_SCR"               ,	   0x1180000000c38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"MIO_UART0_SFE"               ,	   0x1180000000a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"MIO_UART1_SFE"               ,	   0x1180000000e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"MIO_UART0_SRR"               ,	   0x1180000000a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"MIO_UART1_SRR"               ,	   0x1180000000e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"MIO_UART0_SRT"               ,	   0x1180000000a38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_UART1_SRT"               ,	   0x1180000000e38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000a18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000e18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"MIO_UART0_STT"               ,	   0x1180000000b00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"MIO_UART1_STT"               ,	   0x1180000000f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"MIO_UART0_TFL"               ,	   0x1180000000a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"MIO_UART1_TFL"               ,	   0x1180000000e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"MIO_UART1_TFR"               ,	   0x1180000000d28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"MIO_UART1_THR"               ,	   0x1180000000c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"MIO_UART1_USR"               ,	   0x1180000000d38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	530},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	530},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	531},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	531},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	532},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	532},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	533},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	533},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	534},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	534},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	535},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	535},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	536},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	536},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	537},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	537},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	538},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	538},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	539},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	539},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	540},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	540},
+	{"MIX0_TSCTL"                  ,	   0x1070000100068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	541},
+	{"MIX1_TSCTL"                  ,	   0x1070000100868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	541},
+	{"MIX0_TSTAMP"                 ,	   0x1070000100060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
+	{"MIX1_TSTAMP"                 ,	   0x1070000100860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	543},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	544},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	545},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	546},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	547},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	548},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	549},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	550},
+	{"PCIEEP0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP0_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP1_CFG004_MASK"         ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP0_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP1_CFG005_MASK"         ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP0_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP1_CFG006_MASK"         ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP0_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP1_CFG007_MASK"         ,	        0x8000001cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP0_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP1_CFG008_MASK"         ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP0_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP1_CFG009_MASK"         ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP0_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP1_CFG012_MASK"         ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIEEP0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	618},
+	{"PCIEEP0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	619},
+	{"PCIEEP0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	620},
+	{"PCIEEP0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	621},
+	{"PCIEEP0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	622},
+	{"PCIEEP0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	623},
+	{"PCIEEP0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	624},
+	{"PCIEEP0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	625},
+	{"PCIEEP0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	626},
+	{"PCIEEP0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	627},
+	{"PCIEEP0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIEEP1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	628},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC0_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC1_CFG003"              ,	               0xcull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC0_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC1_CFG007"              ,	              0x1cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC1_CFG011"              ,	              0x2cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC1_CFG015"              ,	              0x3cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC0_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC1_CFG023"              ,	              0x5cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG031"              ,	              0x7cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG035"              ,	              0x8cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG039"              ,	              0x9cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC1_CFG040"              ,	              0xa0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC0_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG041"              ,	              0xa4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC1_CFG042"              ,	              0xa8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC1_CFG067"              ,	             0x10cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC1_CFG071"              ,	             0x11cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC1_CFG075"              ,	             0x12cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC0_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG451"              ,	             0x70cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC0_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG455"              ,	             0x71cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG459"              ,	             0x72cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC0_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC1_CFG463"              ,	             0x73cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	694},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	695},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	696},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	697},
+	{"PCIERC0_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC1_CFG467"              ,	             0x74cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	698},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	699},
+	{"PCIERC0_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC1_CFG490"              ,	             0x7a8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	700},
+	{"PCIERC0_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC1_CFG491"              ,	             0x7acull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	701},
+	{"PCIERC0_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC1_CFG492"              ,	             0x7b0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	702},
+	{"PCIERC0_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC1_CFG515"              ,	             0x80cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	703},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	704},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	705},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800b0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800b0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800b0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800b0001c10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800b0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800b0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800b0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800b0001c28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800b0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800b0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800b0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800b0001c18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800b0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800b0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800b0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800b0001c20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800b0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800b0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800b0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800b0001c88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_INT000_REG"             ,	   0x11800b0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_INT001_REG"             ,	   0x11800b0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_INT002_REG"             ,	   0x11800b0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_INT003_REG"             ,	   0x11800b0001c80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800b0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800b0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800b0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800b0001c40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800b0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800b0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800b0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800b0001c90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800b0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800b0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800b0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800b0001c78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800b0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800b0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800b0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800b0001c00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800b0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800b0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800b0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800b0001c08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800b0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800b0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800b0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800b0001c58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800b0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800b0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800b0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800b0001c50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800b0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800b0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800b0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800b0001c68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800b0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800b0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800b0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800b0001c70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800b0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800b0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800b0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800b0001c60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800b0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800b0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800b0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800b0001c48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800b0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800b0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800b0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800b0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800b0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800b0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PCSX0_INT_REG"               ,	   0x11800b0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800b0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800b0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800b0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800b0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800b0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800b0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800b0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800b0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PEM0_BAR1_INDEX000"          ,	   0x11800c00000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX001"          ,	   0x11800c00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX002"          ,	   0x11800c00000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX003"          ,	   0x11800c00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX004"          ,	   0x11800c00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX005"          ,	   0x11800c00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX006"          ,	   0x11800c00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX007"          ,	   0x11800c00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX008"          ,	   0x11800c00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX009"          ,	   0x11800c00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX010"          ,	   0x11800c00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX011"          ,	   0x11800c0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX012"          ,	   0x11800c0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX013"          ,	   0x11800c0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX014"          ,	   0x11800c0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR1_INDEX015"          ,	   0x11800c0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX000"          ,	   0x11800c10000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX001"          ,	   0x11800c10000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX002"          ,	   0x11800c10000b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX003"          ,	   0x11800c10000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX004"          ,	   0x11800c10000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX005"          ,	   0x11800c10000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX006"          ,	   0x11800c10000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX007"          ,	   0x11800c10000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX008"          ,	   0x11800c10000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX009"          ,	   0x11800c10000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX010"          ,	   0x11800c10000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX011"          ,	   0x11800c1000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX012"          ,	   0x11800c1000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX013"          ,	   0x11800c1000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX014"          ,	   0x11800c1000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM1_BAR1_INDEX015"          ,	   0x11800c1000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PEM0_BAR_CTL"                ,	   0x11800c0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PEM1_BAR_CTL"                ,	   0x11800c1000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PEM0_BIST_STATUS"            ,	   0x11800c0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PEM1_BIST_STATUS"            ,	   0x11800c1000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PEM0_BIST_STATUS2"           ,	   0x11800c0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PEM1_BIST_STATUS2"           ,	   0x11800c1000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PEM0_CFG_RD"                 ,	   0x11800c0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PEM1_CFG_RD"                 ,	   0x11800c1000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PEM0_CFG_WR"                 ,	   0x11800c0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PEM1_CFG_WR"                 ,	   0x11800c1000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PEM0_CPL_LUT_VALID"          ,	   0x11800c0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PEM1_CPL_LUT_VALID"          ,	   0x11800c1000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PEM0_CTL_STATUS"             ,	   0x11800c0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PEM1_CTL_STATUS"             ,	   0x11800c1000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PEM0_DBG_INFO"               ,	   0x11800c0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PEM1_DBG_INFO"               ,	   0x11800c1000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PEM0_DBG_INFO_EN"            ,	   0x11800c00000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM1_DBG_INFO_EN"            ,	   0x11800c10000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PEM0_DIAG_STATUS"            ,	   0x11800c0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM1_DIAG_STATUS"            ,	   0x11800c1000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PEM0_INT_ENB"                ,	   0x11800c0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PEM1_INT_ENB"                ,	   0x11800c1000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PEM0_INT_ENB_INT"            ,	   0x11800c0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PEM1_INT_ENB_INT"            ,	   0x11800c1000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PEM0_INT_SUM"                ,	   0x11800c0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PEM1_INT_SUM"                ,	   0x11800c1000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PEM0_P2N_BAR0_START"         ,	   0x11800c0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PEM1_P2N_BAR0_START"         ,	   0x11800c1000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PEM0_P2N_BAR1_START"         ,	   0x11800c0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PEM1_P2N_BAR1_START"         ,	   0x11800c1000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PEM0_P2N_BAR2_START"         ,	   0x11800c0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PEM1_P2N_BAR2_START"         ,	   0x11800c1000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PEM0_P2P_BAR000_END"         ,	   0x11800c0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM0_P2P_BAR001_END"         ,	   0x11800c0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM0_P2P_BAR002_END"         ,	   0x11800c0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM0_P2P_BAR003_END"         ,	   0x11800c0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM1_P2P_BAR000_END"         ,	   0x11800c1000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM1_P2P_BAR001_END"         ,	   0x11800c1000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM1_P2P_BAR002_END"         ,	   0x11800c1000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM1_P2P_BAR003_END"         ,	   0x11800c1000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PEM0_P2P_BAR000_START"       ,	   0x11800c0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM0_P2P_BAR001_START"       ,	   0x11800c0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM0_P2P_BAR002_START"       ,	   0x11800c0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM0_P2P_BAR003_START"       ,	   0x11800c0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM1_P2P_BAR000_START"       ,	   0x11800c1000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM1_P2P_BAR001_START"       ,	   0x11800c1000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM1_P2P_BAR002_START"       ,	   0x11800c1000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM1_P2P_BAR003_START"       ,	   0x11800c1000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PEM0_TLP_CREDITS"            ,	   0x11800c0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PEM1_TLP_CREDITS"            ,	   0x11800c1000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_BCK_PRS"                 ,	   0x11800a0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_BIST_STATUS"             ,	   0x11800a0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_CLKEN"                   ,	   0x11800a0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800a0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800a0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800a0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800a0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800a0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800a0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800a0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_GBL_CFG"                 ,	   0x11800a0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_GBL_CTL"                 ,	   0x11800a0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800a00001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_INT_EN"                  ,	   0x11800a0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_INT_REG"                 ,	   0x11800a0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_IP_OFFSET"               ,	   0x11800a0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_PRT_CFG0"                ,	   0x11800a0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG1"                ,	   0x11800a0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG2"                ,	   0x11800a0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG3"                ,	   0x11800a0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG32"               ,	   0x11800a0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG33"               ,	   0x11800a0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG34"               ,	   0x11800a0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG35"               ,	   0x11800a0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG36"               ,	   0x11800a0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG37"               ,	   0x11800a0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG38"               ,	   0x11800a0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG39"               ,	   0x11800a0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG40"               ,	   0x11800a0000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG41"               ,	   0x11800a0000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG42"               ,	   0x11800a0000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_CFG43"               ,	   0x11800a0000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_PRT_TAG0"                ,	   0x11800a0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG1"                ,	   0x11800a0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG2"                ,	   0x11800a0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG3"                ,	   0x11800a0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG32"               ,	   0x11800a0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG33"               ,	   0x11800a0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG34"               ,	   0x11800a0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG35"               ,	   0x11800a0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG36"               ,	   0x11800a0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG37"               ,	   0x11800a0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG38"               ,	   0x11800a0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG39"               ,	   0x11800a0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG40"               ,	   0x11800a0000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG41"               ,	   0x11800a0000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG42"               ,	   0x11800a0000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_PRT_TAG43"               ,	   0x11800a0000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_QOS_DIFF0"               ,	   0x11800a0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF1"               ,	   0x11800a0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF2"               ,	   0x11800a0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF3"               ,	   0x11800a0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF4"               ,	   0x11800a0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF5"               ,	   0x11800a0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF6"               ,	   0x11800a0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF7"               ,	   0x11800a0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF8"               ,	   0x11800a0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF9"               ,	   0x11800a0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF10"              ,	   0x11800a0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF11"              ,	   0x11800a0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF12"              ,	   0x11800a0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF13"              ,	   0x11800a0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF14"              ,	   0x11800a0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF15"              ,	   0x11800a0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF16"              ,	   0x11800a0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF17"              ,	   0x11800a0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF18"              ,	   0x11800a0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF19"              ,	   0x11800a0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF20"              ,	   0x11800a00006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF21"              ,	   0x11800a00006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF22"              ,	   0x11800a00006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF23"              ,	   0x11800a00006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF24"              ,	   0x11800a00006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF25"              ,	   0x11800a00006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF26"              ,	   0x11800a00006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF27"              ,	   0x11800a00006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF28"              ,	   0x11800a00006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF29"              ,	   0x11800a00006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF30"              ,	   0x11800a00006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF31"              ,	   0x11800a00006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF32"              ,	   0x11800a0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF33"              ,	   0x11800a0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF34"              ,	   0x11800a0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF35"              ,	   0x11800a0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF36"              ,	   0x11800a0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF37"              ,	   0x11800a0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF38"              ,	   0x11800a0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF39"              ,	   0x11800a0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF40"              ,	   0x11800a0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF41"              ,	   0x11800a0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF42"              ,	   0x11800a0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF43"              ,	   0x11800a0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF44"              ,	   0x11800a0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF45"              ,	   0x11800a0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF46"              ,	   0x11800a0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF47"              ,	   0x11800a0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF48"              ,	   0x11800a0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF49"              ,	   0x11800a0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF50"              ,	   0x11800a0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF51"              ,	   0x11800a0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF52"              ,	   0x11800a00007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF53"              ,	   0x11800a00007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF54"              ,	   0x11800a00007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF55"              ,	   0x11800a00007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF56"              ,	   0x11800a00007c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF57"              ,	   0x11800a00007c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF58"              ,	   0x11800a00007d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF59"              ,	   0x11800a00007d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF60"              ,	   0x11800a00007e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF61"              ,	   0x11800a00007e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF62"              ,	   0x11800a00007f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_DIFF63"              ,	   0x11800a00007f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_QOS_VLAN0"               ,	   0x11800a00000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN1"               ,	   0x11800a00000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN2"               ,	   0x11800a00000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN3"               ,	   0x11800a00000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN4"               ,	   0x11800a00000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN5"               ,	   0x11800a00000e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN6"               ,	   0x11800a00000f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_VLAN7"               ,	   0x11800a00000f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_QOS_WATCH0"              ,	   0x11800a0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH1"              ,	   0x11800a0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH2"              ,	   0x11800a0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH3"              ,	   0x11800a0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH4"              ,	   0x11800a0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH5"              ,	   0x11800a0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH6"              ,	   0x11800a0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_QOS_WATCH7"              ,	   0x11800a0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_RAW_WORD"                ,	   0x11800a00000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_SFT_RST"                 ,	   0x11800a0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PIP_STAT0_PRT0"              ,	   0x11800a0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT1"              ,	   0x11800a0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT2"              ,	   0x11800a00008a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT3"              ,	   0x11800a00008f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT32"             ,	   0x11800a0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT33"             ,	   0x11800a0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT34"             ,	   0x11800a00012a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT35"             ,	   0x11800a00012f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT36"             ,	   0x11800a0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT37"             ,	   0x11800a0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT38"             ,	   0x11800a00013e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT0_PRT39"             ,	   0x11800a0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PIP_STAT1_PRT0"              ,	   0x11800a0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT1"              ,	   0x11800a0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT2"              ,	   0x11800a00008a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT3"              ,	   0x11800a00008f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT32"             ,	   0x11800a0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT33"             ,	   0x11800a0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT34"             ,	   0x11800a00012a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT35"             ,	   0x11800a00012f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT36"             ,	   0x11800a0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT37"             ,	   0x11800a0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT38"             ,	   0x11800a00013e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT1_PRT39"             ,	   0x11800a0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PIP_STAT2_PRT0"              ,	   0x11800a0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT1"              ,	   0x11800a0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT2"              ,	   0x11800a00008b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT3"              ,	   0x11800a0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT32"             ,	   0x11800a0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT33"             ,	   0x11800a0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT34"             ,	   0x11800a00012b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT35"             ,	   0x11800a0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT36"             ,	   0x11800a0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT37"             ,	   0x11800a00013a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT38"             ,	   0x11800a00013f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT2_PRT39"             ,	   0x11800a0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PIP_STAT3_PRT0"              ,	   0x11800a0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT1"              ,	   0x11800a0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT2"              ,	   0x11800a00008b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT3"              ,	   0x11800a0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT32"             ,	   0x11800a0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT33"             ,	   0x11800a0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT34"             ,	   0x11800a00012b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT35"             ,	   0x11800a0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT36"             ,	   0x11800a0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT37"             ,	   0x11800a00013a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT38"             ,	   0x11800a00013f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT3_PRT39"             ,	   0x11800a0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PIP_STAT4_PRT0"              ,	   0x11800a0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT1"              ,	   0x11800a0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT2"              ,	   0x11800a00008c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT3"              ,	   0x11800a0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT32"             ,	   0x11800a0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT33"             ,	   0x11800a0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT34"             ,	   0x11800a00012c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT35"             ,	   0x11800a0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT36"             ,	   0x11800a0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT37"             ,	   0x11800a00013b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT38"             ,	   0x11800a0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT4_PRT39"             ,	   0x11800a0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PIP_STAT5_PRT0"              ,	   0x11800a0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT1"              ,	   0x11800a0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT2"              ,	   0x11800a00008c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT3"              ,	   0x11800a0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT32"             ,	   0x11800a0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT33"             ,	   0x11800a0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT34"             ,	   0x11800a00012c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT35"             ,	   0x11800a0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT36"             ,	   0x11800a0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT37"             ,	   0x11800a00013b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT38"             ,	   0x11800a0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT5_PRT39"             ,	   0x11800a0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PIP_STAT6_PRT0"              ,	   0x11800a0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT1"              ,	   0x11800a0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT2"              ,	   0x11800a00008d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT3"              ,	   0x11800a0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT32"             ,	   0x11800a0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT33"             ,	   0x11800a0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT34"             ,	   0x11800a00012d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT35"             ,	   0x11800a0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT36"             ,	   0x11800a0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT37"             ,	   0x11800a00013c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT38"             ,	   0x11800a0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT6_PRT39"             ,	   0x11800a0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PIP_STAT7_PRT0"              ,	   0x11800a0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT1"              ,	   0x11800a0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT2"              ,	   0x11800a00008d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT3"              ,	   0x11800a0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT32"             ,	   0x11800a0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT33"             ,	   0x11800a0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT34"             ,	   0x11800a00012d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT35"             ,	   0x11800a0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT36"             ,	   0x11800a0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT37"             ,	   0x11800a00013c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT38"             ,	   0x11800a0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT7_PRT39"             ,	   0x11800a0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PIP_STAT8_PRT0"              ,	   0x11800a0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT1"              ,	   0x11800a0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT2"              ,	   0x11800a00008e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT3"              ,	   0x11800a0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT32"             ,	   0x11800a0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT33"             ,	   0x11800a0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT34"             ,	   0x11800a00012e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT35"             ,	   0x11800a0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT36"             ,	   0x11800a0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT37"             ,	   0x11800a00013d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT38"             ,	   0x11800a0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT8_PRT39"             ,	   0x11800a0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PIP_STAT9_PRT0"              ,	   0x11800a0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT1"              ,	   0x11800a0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT2"              ,	   0x11800a00008e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT3"              ,	   0x11800a0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT32"             ,	   0x11800a0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT33"             ,	   0x11800a0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT34"             ,	   0x11800a00012e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT35"             ,	   0x11800a0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT36"             ,	   0x11800a0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT37"             ,	   0x11800a00013d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT38"             ,	   0x11800a0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT9_PRT39"             ,	   0x11800a0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PIP_STAT_CTL"                ,	   0x11800a0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800a0001a10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800a0001a30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800a0001a50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800a0001a70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800a0001e10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800a0001e30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800a0001e50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800a0001e70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800a0001e90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800a0001eb0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800a0001ed0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800a0001ef0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS40"         ,	   0x11800a0001f10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS41"         ,	   0x11800a0001f30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS42"         ,	   0x11800a0001f50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_ERRS43"         ,	   0x11800a0001f70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800a0001a08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800a0001a28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800a0001a48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800a0001a68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800a0001e08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800a0001e28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800a0001e48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800a0001e68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800a0001e88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800a0001ea8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800a0001ec8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800a0001ee8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS40"         ,	   0x11800a0001f08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS41"         ,	   0x11800a0001f28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS42"         ,	   0x11800a0001f48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_OCTS43"         ,	   0x11800a0001f68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800a0001a00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800a0001a20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800a0001a40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800a0001a60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800a0001e00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800a0001e20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800a0001e40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800a0001e60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800a0001e80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800a0001ea0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800a0001ec0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800a0001ee0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS40"         ,	   0x11800a0001f00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS41"         ,	   0x11800a0001f20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS42"         ,	   0x11800a0001f40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_STAT_INB_PKTS43"         ,	   0x11800a0001f60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PIP_TAG_INC0"                ,	   0x11800a0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC1"                ,	   0x11800a0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC2"                ,	   0x11800a0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC3"                ,	   0x11800a0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC4"                ,	   0x11800a0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC5"                ,	   0x11800a0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC6"                ,	   0x11800a0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC7"                ,	   0x11800a0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC8"                ,	   0x11800a0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC9"                ,	   0x11800a0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC10"               ,	   0x11800a0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC11"               ,	   0x11800a0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC12"               ,	   0x11800a0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC13"               ,	   0x11800a0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC14"               ,	   0x11800a0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC15"               ,	   0x11800a0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC16"               ,	   0x11800a0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC17"               ,	   0x11800a0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC18"               ,	   0x11800a0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC19"               ,	   0x11800a0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC20"               ,	   0x11800a00018a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC21"               ,	   0x11800a00018a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC22"               ,	   0x11800a00018b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC23"               ,	   0x11800a00018b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC24"               ,	   0x11800a00018c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC25"               ,	   0x11800a00018c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC26"               ,	   0x11800a00018d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC27"               ,	   0x11800a00018d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC28"               ,	   0x11800a00018e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC29"               ,	   0x11800a00018e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC30"               ,	   0x11800a00018f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC31"               ,	   0x11800a00018f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC32"               ,	   0x11800a0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC33"               ,	   0x11800a0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC34"               ,	   0x11800a0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC35"               ,	   0x11800a0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC36"               ,	   0x11800a0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC37"               ,	   0x11800a0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC38"               ,	   0x11800a0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC39"               ,	   0x11800a0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC40"               ,	   0x11800a0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC41"               ,	   0x11800a0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC42"               ,	   0x11800a0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC43"               ,	   0x11800a0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC44"               ,	   0x11800a0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC45"               ,	   0x11800a0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC46"               ,	   0x11800a0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC47"               ,	   0x11800a0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC48"               ,	   0x11800a0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC49"               ,	   0x11800a0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC50"               ,	   0x11800a0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC51"               ,	   0x11800a0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC52"               ,	   0x11800a00019a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC53"               ,	   0x11800a00019a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC54"               ,	   0x11800a00019b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC55"               ,	   0x11800a00019b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC56"               ,	   0x11800a00019c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC57"               ,	   0x11800a00019c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC58"               ,	   0x11800a00019d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC59"               ,	   0x11800a00019d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC60"               ,	   0x11800a00019e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC61"               ,	   0x11800a00019e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC62"               ,	   0x11800a00019f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_INC63"               ,	   0x11800a00019f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PIP_TAG_MASK"                ,	   0x11800a0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PIP_TAG_SECRET"              ,	   0x11800a0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PIP_TODO_ENTRY"              ,	   0x11800a0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PIP_XSTAT0_PRT40"            ,	   0x11800a0002000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT0_PRT41"            ,	   0x11800a0002050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT0_PRT42"            ,	   0x11800a00020a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT0_PRT43"            ,	   0x11800a00020f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PIP_XSTAT1_PRT40"            ,	   0x11800a0002008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT1_PRT41"            ,	   0x11800a0002058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT1_PRT42"            ,	   0x11800a00020a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT1_PRT43"            ,	   0x11800a00020f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PIP_XSTAT2_PRT40"            ,	   0x11800a0002010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT2_PRT41"            ,	   0x11800a0002060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT2_PRT42"            ,	   0x11800a00020b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT2_PRT43"            ,	   0x11800a0002100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PIP_XSTAT3_PRT40"            ,	   0x11800a0002018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT3_PRT41"            ,	   0x11800a0002068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT3_PRT42"            ,	   0x11800a00020b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT3_PRT43"            ,	   0x11800a0002108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PIP_XSTAT4_PRT40"            ,	   0x11800a0002020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT4_PRT41"            ,	   0x11800a0002070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT4_PRT42"            ,	   0x11800a00020c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT4_PRT43"            ,	   0x11800a0002110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PIP_XSTAT5_PRT40"            ,	   0x11800a0002028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT5_PRT41"            ,	   0x11800a0002078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT5_PRT42"            ,	   0x11800a00020c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT5_PRT43"            ,	   0x11800a0002118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PIP_XSTAT6_PRT40"            ,	   0x11800a0002030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT6_PRT41"            ,	   0x11800a0002080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT6_PRT42"            ,	   0x11800a00020d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT6_PRT43"            ,	   0x11800a0002120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PIP_XSTAT7_PRT40"            ,	   0x11800a0002038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT7_PRT41"            ,	   0x11800a0002088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT7_PRT42"            ,	   0x11800a00020d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT7_PRT43"            ,	   0x11800a0002128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PIP_XSTAT8_PRT40"            ,	   0x11800a0002040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT8_PRT41"            ,	   0x11800a0002090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT8_PRT42"            ,	   0x11800a00020e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT8_PRT43"            ,	   0x11800a0002130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PIP_XSTAT9_PRT40"            ,	   0x11800a0002048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT9_PRT41"            ,	   0x11800a0002098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT9_PRT42"            ,	   0x11800a00020e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PIP_XSTAT9_PRT43"            ,	   0x11800a0002138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"PKO_REG_TIMESTAMP"           ,	   0x1180050000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"POW_BIST_STAT"               ,	   0x16700000003f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	845},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	846},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	847},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	848},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	849},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	850},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	851},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	852},
+	{"POW_IQ_THR0"                 ,	   0x16700000003a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR1"                 ,	   0x16700000003a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR2"                 ,	   0x16700000003b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR3"                 ,	   0x16700000003b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR4"                 ,	   0x16700000003c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR5"                 ,	   0x16700000003c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR6"                 ,	   0x16700000003d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_IQ_THR7"                 ,	   0x16700000003d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	853},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	854},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	855},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	856},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	857},
+	{"POW_QOS_RND0"                ,	   0x16700000001c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND1"                ,	   0x16700000001c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND2"                ,	   0x16700000001d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND3"                ,	   0x16700000001d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND4"                ,	   0x16700000001e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND5"                ,	   0x16700000001e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND6"                ,	   0x16700000001f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_RND7"                ,	   0x16700000001f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	858},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR4"                ,	   0x16700000001a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR5"                ,	   0x16700000001a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR6"                ,	   0x16700000001b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_QOS_THR7"                ,	   0x16700000001b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	859},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	860},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	861},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	862},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	863},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	864},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	865},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	866},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC4"                  ,	   0x16700000002a0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC5"                  ,	   0x16700000002a8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC6"                  ,	   0x16700000002b0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC7"                  ,	   0x16700000002b8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC8"                  ,	   0x16700000002c0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC9"                  ,	   0x16700000002c8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC10"                 ,	   0x16700000002d0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC11"                 ,	   0x16700000002d8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC12"                 ,	   0x16700000002e0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC13"                 ,	   0x16700000002e8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC14"                 ,	   0x16700000002f0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"POW_WS_PC15"                 ,	   0x16700000002f8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	867},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"RNM_EER_DBG"                 ,	   0x1180040000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"RNM_EER_KEY"                 ,	   0x1180040000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"RNM_SERIAL_NUM"              ,	   0x1180040000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"SLI_BIST_STATUS"             ,	   0x11f0000010580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	896},
+	{"SLI_CTL_PORT0"               ,	   0x11f0000010050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
+	{"SLI_CTL_PORT1"               ,	   0x11f0000010060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	897},
+	{"SLI_CTL_STATUS"              ,	   0x11f0000010570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	898},
+	{"SLI_DATA_OUT_CNT"            ,	   0x11f00000105f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	899},
+	{"SLI_DBG_DATA"                ,	   0x11f0000010310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	900},
+	{"SLI_DBG_SELECT"              ,	   0x11f0000010300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	901},
+	{"SLI_DMA0_CNT"                ,	   0x11f0000010400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
+	{"SLI_DMA1_CNT"                ,	   0x11f0000010410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	902},
+	{"SLI_DMA0_INT_LEVEL"          ,	   0x11f00000103e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_DMA1_INT_LEVEL"          ,	   0x11f00000103f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	903},
+	{"SLI_DMA0_TIM"                ,	   0x11f0000010420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
+	{"SLI_DMA1_TIM"                ,	   0x11f0000010430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	904},
+	{"SLI_INT_ENB_CIU"             ,	   0x11f0000013cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905},
+	{"SLI_INT_ENB_PORT0"           ,	   0x11f0000010340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
+	{"SLI_INT_ENB_PORT1"           ,	   0x11f0000010350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906},
+	{"SLI_INT_SUM"                 ,	   0x11f0000010330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907},
+	{"SLI_LAST_WIN_RDATA0"         ,	   0x11f0000010600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908},
+	{"SLI_LAST_WIN_RDATA1"         ,	   0x11f0000010610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909},
+	{"SLI_MAC_CREDIT_CNT"          ,	   0x11f0000013d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910},
+	{"SLI_MAC_NUMBER"              ,	            0x3e00ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	911},
+	{"SLI_MEM_ACCESS_CTL"          ,	   0x11f00000102f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912},
+	{"SLI_MEM_ACCESS_SUBID12"      ,	   0x11f00000100e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID13"      ,	   0x11f00000100f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID14"      ,	   0x11f0000010100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID15"      ,	   0x11f0000010110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID16"      ,	   0x11f0000010120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID17"      ,	   0x11f0000010130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID18"      ,	   0x11f0000010140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID19"      ,	   0x11f0000010150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID20"      ,	   0x11f0000010160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID21"      ,	   0x11f0000010170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID22"      ,	   0x11f0000010180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID23"      ,	   0x11f0000010190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID24"      ,	   0x11f00000101a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID25"      ,	   0x11f00000101b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID26"      ,	   0x11f00000101c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MEM_ACCESS_SUBID27"      ,	   0x11f00000101d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913},
+	{"SLI_MSI_ENB0"                ,	   0x11f0000013c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	914},
+	{"SLI_MSI_ENB1"                ,	   0x11f0000013c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	915},
+	{"SLI_MSI_ENB2"                ,	   0x11f0000013c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	916},
+	{"SLI_MSI_ENB3"                ,	   0x11f0000013c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	917},
+	{"SLI_MSI_RCV0"                ,	   0x11f0000013c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	918},
+	{"SLI_MSI_RCV1"                ,	   0x11f0000013c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	919},
+	{"SLI_MSI_RCV2"                ,	   0x11f0000013c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	920},
+	{"SLI_MSI_RCV3"                ,	   0x11f0000013c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921},
+	{"SLI_MSI_RD_MAP"              ,	   0x11f0000013ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	922},
+	{"SLI_MSI_W1C_ENB0"            ,	   0x11f0000013cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	923},
+	{"SLI_MSI_W1C_ENB1"            ,	   0x11f0000013d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	924},
+	{"SLI_MSI_W1C_ENB2"            ,	   0x11f0000013d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925},
+	{"SLI_MSI_W1C_ENB3"            ,	   0x11f0000013d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	926},
+	{"SLI_MSI_W1S_ENB0"            ,	   0x11f0000013d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	927},
+	{"SLI_MSI_W1S_ENB1"            ,	   0x11f0000013d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	928},
+	{"SLI_MSI_W1S_ENB2"            ,	   0x11f0000013d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929},
+	{"SLI_MSI_W1S_ENB3"            ,	   0x11f0000013d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930},
+	{"SLI_MSI_WR_MAP"              ,	   0x11f0000013c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931},
+	{"SLI_PCIE_MSI_RCV"            ,	   0x11f0000013cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932},
+	{"SLI_PCIE_MSI_RCV_B1"         ,	   0x11f0000010650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933},
+	{"SLI_PCIE_MSI_RCV_B2"         ,	   0x11f0000010660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934},
+	{"SLI_PCIE_MSI_RCV_B3"         ,	   0x11f0000010670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935},
+	{"SLI_PKT0_CNTS"               ,	   0x11f0000012400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT1_CNTS"               ,	   0x11f0000012410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT2_CNTS"               ,	   0x11f0000012420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT3_CNTS"               ,	   0x11f0000012430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT4_CNTS"               ,	   0x11f0000012440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT5_CNTS"               ,	   0x11f0000012450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT6_CNTS"               ,	   0x11f0000012460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT7_CNTS"               ,	   0x11f0000012470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT8_CNTS"               ,	   0x11f0000012480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT9_CNTS"               ,	   0x11f0000012490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT10_CNTS"              ,	   0x11f00000124a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT11_CNTS"              ,	   0x11f00000124b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT12_CNTS"              ,	   0x11f00000124c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT13_CNTS"              ,	   0x11f00000124d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT14_CNTS"              ,	   0x11f00000124e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT15_CNTS"              ,	   0x11f00000124f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT16_CNTS"              ,	   0x11f0000012500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT17_CNTS"              ,	   0x11f0000012510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT18_CNTS"              ,	   0x11f0000012520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT19_CNTS"              ,	   0x11f0000012530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT20_CNTS"              ,	   0x11f0000012540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT21_CNTS"              ,	   0x11f0000012550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT22_CNTS"              ,	   0x11f0000012560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT23_CNTS"              ,	   0x11f0000012570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT24_CNTS"              ,	   0x11f0000012580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT25_CNTS"              ,	   0x11f0000012590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT26_CNTS"              ,	   0x11f00000125a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT27_CNTS"              ,	   0x11f00000125b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT28_CNTS"              ,	   0x11f00000125c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT29_CNTS"              ,	   0x11f00000125d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT30_CNTS"              ,	   0x11f00000125e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT31_CNTS"              ,	   0x11f00000125f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936},
+	{"SLI_PKT0_IN_BP"              ,	   0x11f0000013800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT1_IN_BP"              ,	   0x11f0000013810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT2_IN_BP"              ,	   0x11f0000013820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT3_IN_BP"              ,	   0x11f0000013830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT4_IN_BP"              ,	   0x11f0000013840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT5_IN_BP"              ,	   0x11f0000013850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT6_IN_BP"              ,	   0x11f0000013860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT7_IN_BP"              ,	   0x11f0000013870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT8_IN_BP"              ,	   0x11f0000013880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT9_IN_BP"              ,	   0x11f0000013890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT10_IN_BP"             ,	   0x11f00000138a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT11_IN_BP"             ,	   0x11f00000138b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT12_IN_BP"             ,	   0x11f00000138c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT13_IN_BP"             ,	   0x11f00000138d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT14_IN_BP"             ,	   0x11f00000138e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT15_IN_BP"             ,	   0x11f00000138f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT16_IN_BP"             ,	   0x11f0000013900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT17_IN_BP"             ,	   0x11f0000013910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT18_IN_BP"             ,	   0x11f0000013920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT19_IN_BP"             ,	   0x11f0000013930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT20_IN_BP"             ,	   0x11f0000013940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT21_IN_BP"             ,	   0x11f0000013950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT22_IN_BP"             ,	   0x11f0000013960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT23_IN_BP"             ,	   0x11f0000013970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT24_IN_BP"             ,	   0x11f0000013980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT25_IN_BP"             ,	   0x11f0000013990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT26_IN_BP"             ,	   0x11f00000139a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT27_IN_BP"             ,	   0x11f00000139b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT28_IN_BP"             ,	   0x11f00000139c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT29_IN_BP"             ,	   0x11f00000139d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT30_IN_BP"             ,	   0x11f00000139e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT31_IN_BP"             ,	   0x11f00000139f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937},
+	{"SLI_PKT0_INSTR_BADDR"        ,	   0x11f0000012800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT1_INSTR_BADDR"        ,	   0x11f0000012810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT2_INSTR_BADDR"        ,	   0x11f0000012820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT3_INSTR_BADDR"        ,	   0x11f0000012830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT4_INSTR_BADDR"        ,	   0x11f0000012840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT5_INSTR_BADDR"        ,	   0x11f0000012850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT6_INSTR_BADDR"        ,	   0x11f0000012860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT7_INSTR_BADDR"        ,	   0x11f0000012870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT8_INSTR_BADDR"        ,	   0x11f0000012880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT9_INSTR_BADDR"        ,	   0x11f0000012890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT10_INSTR_BADDR"       ,	   0x11f00000128a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT11_INSTR_BADDR"       ,	   0x11f00000128b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT12_INSTR_BADDR"       ,	   0x11f00000128c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT13_INSTR_BADDR"       ,	   0x11f00000128d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT14_INSTR_BADDR"       ,	   0x11f00000128e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT15_INSTR_BADDR"       ,	   0x11f00000128f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT16_INSTR_BADDR"       ,	   0x11f0000012900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT17_INSTR_BADDR"       ,	   0x11f0000012910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT18_INSTR_BADDR"       ,	   0x11f0000012920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT19_INSTR_BADDR"       ,	   0x11f0000012930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT20_INSTR_BADDR"       ,	   0x11f0000012940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT21_INSTR_BADDR"       ,	   0x11f0000012950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT22_INSTR_BADDR"       ,	   0x11f0000012960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT23_INSTR_BADDR"       ,	   0x11f0000012970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT24_INSTR_BADDR"       ,	   0x11f0000012980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT25_INSTR_BADDR"       ,	   0x11f0000012990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT26_INSTR_BADDR"       ,	   0x11f00000129a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT27_INSTR_BADDR"       ,	   0x11f00000129b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT28_INSTR_BADDR"       ,	   0x11f00000129c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT29_INSTR_BADDR"       ,	   0x11f00000129d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT30_INSTR_BADDR"       ,	   0x11f00000129e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT31_INSTR_BADDR"       ,	   0x11f00000129f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938},
+	{"SLI_PKT0_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT1_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT2_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT3_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT4_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT5_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT6_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT7_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT8_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT9_INSTR_BAOFF_DBELL"  ,	   0x11f0000012c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT10_INSTR_BAOFF_DBELL" ,	   0x11f0000012ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT11_INSTR_BAOFF_DBELL" ,	   0x11f0000012cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT12_INSTR_BAOFF_DBELL" ,	   0x11f0000012cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT13_INSTR_BAOFF_DBELL" ,	   0x11f0000012cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT14_INSTR_BAOFF_DBELL" ,	   0x11f0000012ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT15_INSTR_BAOFF_DBELL" ,	   0x11f0000012cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT16_INSTR_BAOFF_DBELL" ,	   0x11f0000012d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT17_INSTR_BAOFF_DBELL" ,	   0x11f0000012d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT18_INSTR_BAOFF_DBELL" ,	   0x11f0000012d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT19_INSTR_BAOFF_DBELL" ,	   0x11f0000012d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT20_INSTR_BAOFF_DBELL" ,	   0x11f0000012d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT21_INSTR_BAOFF_DBELL" ,	   0x11f0000012d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT22_INSTR_BAOFF_DBELL" ,	   0x11f0000012d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT23_INSTR_BAOFF_DBELL" ,	   0x11f0000012d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT24_INSTR_BAOFF_DBELL" ,	   0x11f0000012d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT25_INSTR_BAOFF_DBELL" ,	   0x11f0000012d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT26_INSTR_BAOFF_DBELL" ,	   0x11f0000012da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT27_INSTR_BAOFF_DBELL" ,	   0x11f0000012db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT28_INSTR_BAOFF_DBELL" ,	   0x11f0000012dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT29_INSTR_BAOFF_DBELL" ,	   0x11f0000012dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT30_INSTR_BAOFF_DBELL" ,	   0x11f0000012de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT31_INSTR_BAOFF_DBELL" ,	   0x11f0000012df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939},
+	{"SLI_PKT0_INSTR_FIFO_RSIZE"   ,	   0x11f0000013000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT1_INSTR_FIFO_RSIZE"   ,	   0x11f0000013010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT2_INSTR_FIFO_RSIZE"   ,	   0x11f0000013020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT3_INSTR_FIFO_RSIZE"   ,	   0x11f0000013030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT4_INSTR_FIFO_RSIZE"   ,	   0x11f0000013040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT5_INSTR_FIFO_RSIZE"   ,	   0x11f0000013050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT6_INSTR_FIFO_RSIZE"   ,	   0x11f0000013060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT7_INSTR_FIFO_RSIZE"   ,	   0x11f0000013070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT8_INSTR_FIFO_RSIZE"   ,	   0x11f0000013080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT9_INSTR_FIFO_RSIZE"   ,	   0x11f0000013090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT10_INSTR_FIFO_RSIZE"  ,	   0x11f00000130a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT11_INSTR_FIFO_RSIZE"  ,	   0x11f00000130b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT12_INSTR_FIFO_RSIZE"  ,	   0x11f00000130c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT13_INSTR_FIFO_RSIZE"  ,	   0x11f00000130d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT14_INSTR_FIFO_RSIZE"  ,	   0x11f00000130e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT15_INSTR_FIFO_RSIZE"  ,	   0x11f00000130f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT16_INSTR_FIFO_RSIZE"  ,	   0x11f0000013100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT17_INSTR_FIFO_RSIZE"  ,	   0x11f0000013110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT18_INSTR_FIFO_RSIZE"  ,	   0x11f0000013120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT19_INSTR_FIFO_RSIZE"  ,	   0x11f0000013130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT20_INSTR_FIFO_RSIZE"  ,	   0x11f0000013140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT21_INSTR_FIFO_RSIZE"  ,	   0x11f0000013150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT22_INSTR_FIFO_RSIZE"  ,	   0x11f0000013160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT23_INSTR_FIFO_RSIZE"  ,	   0x11f0000013170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT24_INSTR_FIFO_RSIZE"  ,	   0x11f0000013180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT25_INSTR_FIFO_RSIZE"  ,	   0x11f0000013190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT26_INSTR_FIFO_RSIZE"  ,	   0x11f00000131a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT27_INSTR_FIFO_RSIZE"  ,	   0x11f00000131b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT28_INSTR_FIFO_RSIZE"  ,	   0x11f00000131c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT29_INSTR_FIFO_RSIZE"  ,	   0x11f00000131d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT30_INSTR_FIFO_RSIZE"  ,	   0x11f00000131e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT31_INSTR_FIFO_RSIZE"  ,	   0x11f00000131f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940},
+	{"SLI_PKT0_INSTR_HEADER"       ,	   0x11f0000013400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT1_INSTR_HEADER"       ,	   0x11f0000013410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT2_INSTR_HEADER"       ,	   0x11f0000013420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT3_INSTR_HEADER"       ,	   0x11f0000013430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT4_INSTR_HEADER"       ,	   0x11f0000013440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT5_INSTR_HEADER"       ,	   0x11f0000013450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT6_INSTR_HEADER"       ,	   0x11f0000013460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT7_INSTR_HEADER"       ,	   0x11f0000013470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT8_INSTR_HEADER"       ,	   0x11f0000013480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT9_INSTR_HEADER"       ,	   0x11f0000013490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT10_INSTR_HEADER"      ,	   0x11f00000134a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT11_INSTR_HEADER"      ,	   0x11f00000134b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT12_INSTR_HEADER"      ,	   0x11f00000134c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT13_INSTR_HEADER"      ,	   0x11f00000134d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT14_INSTR_HEADER"      ,	   0x11f00000134e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT15_INSTR_HEADER"      ,	   0x11f00000134f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT16_INSTR_HEADER"      ,	   0x11f0000013500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT17_INSTR_HEADER"      ,	   0x11f0000013510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT18_INSTR_HEADER"      ,	   0x11f0000013520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT19_INSTR_HEADER"      ,	   0x11f0000013530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT20_INSTR_HEADER"      ,	   0x11f0000013540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT21_INSTR_HEADER"      ,	   0x11f0000013550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT22_INSTR_HEADER"      ,	   0x11f0000013560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT23_INSTR_HEADER"      ,	   0x11f0000013570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT24_INSTR_HEADER"      ,	   0x11f0000013580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT25_INSTR_HEADER"      ,	   0x11f0000013590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT26_INSTR_HEADER"      ,	   0x11f00000135a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT27_INSTR_HEADER"      ,	   0x11f00000135b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT28_INSTR_HEADER"      ,	   0x11f00000135c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT29_INSTR_HEADER"      ,	   0x11f00000135d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT30_INSTR_HEADER"      ,	   0x11f00000135e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT31_INSTR_HEADER"      ,	   0x11f00000135f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941},
+	{"SLI_PKT0_OUT_SIZE"           ,	   0x11f0000010c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT1_OUT_SIZE"           ,	   0x11f0000010c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT2_OUT_SIZE"           ,	   0x11f0000010c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT3_OUT_SIZE"           ,	   0x11f0000010c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT4_OUT_SIZE"           ,	   0x11f0000010c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT5_OUT_SIZE"           ,	   0x11f0000010c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT6_OUT_SIZE"           ,	   0x11f0000010c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT7_OUT_SIZE"           ,	   0x11f0000010c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT8_OUT_SIZE"           ,	   0x11f0000010c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT9_OUT_SIZE"           ,	   0x11f0000010c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT10_OUT_SIZE"          ,	   0x11f0000010ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT11_OUT_SIZE"          ,	   0x11f0000010cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT12_OUT_SIZE"          ,	   0x11f0000010cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT13_OUT_SIZE"          ,	   0x11f0000010cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT14_OUT_SIZE"          ,	   0x11f0000010ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT15_OUT_SIZE"          ,	   0x11f0000010cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT16_OUT_SIZE"          ,	   0x11f0000010d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT17_OUT_SIZE"          ,	   0x11f0000010d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT18_OUT_SIZE"          ,	   0x11f0000010d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT19_OUT_SIZE"          ,	   0x11f0000010d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT20_OUT_SIZE"          ,	   0x11f0000010d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT21_OUT_SIZE"          ,	   0x11f0000010d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT22_OUT_SIZE"          ,	   0x11f0000010d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT23_OUT_SIZE"          ,	   0x11f0000010d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT24_OUT_SIZE"          ,	   0x11f0000010d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT25_OUT_SIZE"          ,	   0x11f0000010d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT26_OUT_SIZE"          ,	   0x11f0000010da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT27_OUT_SIZE"          ,	   0x11f0000010db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT28_OUT_SIZE"          ,	   0x11f0000010dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT29_OUT_SIZE"          ,	   0x11f0000010dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT30_OUT_SIZE"          ,	   0x11f0000010de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT31_OUT_SIZE"          ,	   0x11f0000010df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942},
+	{"SLI_PKT0_SLIST_BADDR"        ,	   0x11f0000011400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT1_SLIST_BADDR"        ,	   0x11f0000011410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT2_SLIST_BADDR"        ,	   0x11f0000011420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT3_SLIST_BADDR"        ,	   0x11f0000011430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT4_SLIST_BADDR"        ,	   0x11f0000011440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT5_SLIST_BADDR"        ,	   0x11f0000011450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT6_SLIST_BADDR"        ,	   0x11f0000011460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT7_SLIST_BADDR"        ,	   0x11f0000011470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT8_SLIST_BADDR"        ,	   0x11f0000011480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT9_SLIST_BADDR"        ,	   0x11f0000011490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT10_SLIST_BADDR"       ,	   0x11f00000114a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT11_SLIST_BADDR"       ,	   0x11f00000114b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT12_SLIST_BADDR"       ,	   0x11f00000114c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT13_SLIST_BADDR"       ,	   0x11f00000114d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT14_SLIST_BADDR"       ,	   0x11f00000114e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT15_SLIST_BADDR"       ,	   0x11f00000114f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT16_SLIST_BADDR"       ,	   0x11f0000011500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT17_SLIST_BADDR"       ,	   0x11f0000011510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT18_SLIST_BADDR"       ,	   0x11f0000011520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT19_SLIST_BADDR"       ,	   0x11f0000011530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT20_SLIST_BADDR"       ,	   0x11f0000011540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT21_SLIST_BADDR"       ,	   0x11f0000011550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT22_SLIST_BADDR"       ,	   0x11f0000011560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT23_SLIST_BADDR"       ,	   0x11f0000011570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT24_SLIST_BADDR"       ,	   0x11f0000011580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT25_SLIST_BADDR"       ,	   0x11f0000011590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT26_SLIST_BADDR"       ,	   0x11f00000115a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT27_SLIST_BADDR"       ,	   0x11f00000115b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT28_SLIST_BADDR"       ,	   0x11f00000115c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT29_SLIST_BADDR"       ,	   0x11f00000115d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT30_SLIST_BADDR"       ,	   0x11f00000115e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT31_SLIST_BADDR"       ,	   0x11f00000115f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943},
+	{"SLI_PKT0_SLIST_BAOFF_DBELL"  ,	   0x11f0000011800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT1_SLIST_BAOFF_DBELL"  ,	   0x11f0000011810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT2_SLIST_BAOFF_DBELL"  ,	   0x11f0000011820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT3_SLIST_BAOFF_DBELL"  ,	   0x11f0000011830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT4_SLIST_BAOFF_DBELL"  ,	   0x11f0000011840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT5_SLIST_BAOFF_DBELL"  ,	   0x11f0000011850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT6_SLIST_BAOFF_DBELL"  ,	   0x11f0000011860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT7_SLIST_BAOFF_DBELL"  ,	   0x11f0000011870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT8_SLIST_BAOFF_DBELL"  ,	   0x11f0000011880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT9_SLIST_BAOFF_DBELL"  ,	   0x11f0000011890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT10_SLIST_BAOFF_DBELL" ,	   0x11f00000118a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT11_SLIST_BAOFF_DBELL" ,	   0x11f00000118b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT12_SLIST_BAOFF_DBELL" ,	   0x11f00000118c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT13_SLIST_BAOFF_DBELL" ,	   0x11f00000118d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT14_SLIST_BAOFF_DBELL" ,	   0x11f00000118e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT15_SLIST_BAOFF_DBELL" ,	   0x11f00000118f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT16_SLIST_BAOFF_DBELL" ,	   0x11f0000011900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT17_SLIST_BAOFF_DBELL" ,	   0x11f0000011910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT18_SLIST_BAOFF_DBELL" ,	   0x11f0000011920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT19_SLIST_BAOFF_DBELL" ,	   0x11f0000011930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT20_SLIST_BAOFF_DBELL" ,	   0x11f0000011940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT21_SLIST_BAOFF_DBELL" ,	   0x11f0000011950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT22_SLIST_BAOFF_DBELL" ,	   0x11f0000011960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT23_SLIST_BAOFF_DBELL" ,	   0x11f0000011970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT24_SLIST_BAOFF_DBELL" ,	   0x11f0000011980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT25_SLIST_BAOFF_DBELL" ,	   0x11f0000011990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT26_SLIST_BAOFF_DBELL" ,	   0x11f00000119a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT27_SLIST_BAOFF_DBELL" ,	   0x11f00000119b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT28_SLIST_BAOFF_DBELL" ,	   0x11f00000119c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT29_SLIST_BAOFF_DBELL" ,	   0x11f00000119d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT30_SLIST_BAOFF_DBELL" ,	   0x11f00000119e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT31_SLIST_BAOFF_DBELL" ,	   0x11f00000119f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944},
+	{"SLI_PKT0_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT1_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT2_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT3_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT4_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT5_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT6_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT7_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT8_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT9_SLIST_FIFO_RSIZE"   ,	   0x11f0000011c90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT10_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ca0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT11_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cb0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT12_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT13_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT14_SLIST_FIFO_RSIZE"  ,	   0x11f0000011ce0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT15_SLIST_FIFO_RSIZE"  ,	   0x11f0000011cf0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT16_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT17_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT18_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT19_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT20_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT21_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT22_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT23_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT24_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT25_SLIST_FIFO_RSIZE"  ,	   0x11f0000011d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT26_SLIST_FIFO_RSIZE"  ,	   0x11f0000011da0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT27_SLIST_FIFO_RSIZE"  ,	   0x11f0000011db0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT28_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dc0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT29_SLIST_FIFO_RSIZE"  ,	   0x11f0000011dd0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT30_SLIST_FIFO_RSIZE"  ,	   0x11f0000011de0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT31_SLIST_FIFO_RSIZE"  ,	   0x11f0000011df0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945},
+	{"SLI_PKT_CNT_INT"             ,	   0x11f0000011130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946},
+	{"SLI_PKT_CNT_INT_ENB"         ,	   0x11f0000011150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947},
+	{"SLI_PKT_CTL"                 ,	   0x11f0000011220ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	948},
+	{"SLI_PKT_DATA_OUT_ES"         ,	   0x11f00000110b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	949},
+	{"SLI_PKT_DATA_OUT_NS"         ,	   0x11f00000110a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	950},
+	{"SLI_PKT_DATA_OUT_ROR"        ,	   0x11f0000011090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	951},
+	{"SLI_PKT_DPADDR"              ,	   0x11f0000011080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	952},
+	{"SLI_PKT_IN_BP"               ,	   0x11f0000011210ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	953},
+	{"SLI_PKT_IN_DONE0_CNTS"       ,	   0x11f0000012000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE1_CNTS"       ,	   0x11f0000012010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE2_CNTS"       ,	   0x11f0000012020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE3_CNTS"       ,	   0x11f0000012030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE4_CNTS"       ,	   0x11f0000012040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE5_CNTS"       ,	   0x11f0000012050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE6_CNTS"       ,	   0x11f0000012060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE7_CNTS"       ,	   0x11f0000012070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE8_CNTS"       ,	   0x11f0000012080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE9_CNTS"       ,	   0x11f0000012090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE10_CNTS"      ,	   0x11f00000120a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE11_CNTS"      ,	   0x11f00000120b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE12_CNTS"      ,	   0x11f00000120c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE13_CNTS"      ,	   0x11f00000120d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE14_CNTS"      ,	   0x11f00000120e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE15_CNTS"      ,	   0x11f00000120f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE16_CNTS"      ,	   0x11f0000012100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE17_CNTS"      ,	   0x11f0000012110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE18_CNTS"      ,	   0x11f0000012120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE19_CNTS"      ,	   0x11f0000012130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE20_CNTS"      ,	   0x11f0000012140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE21_CNTS"      ,	   0x11f0000012150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE22_CNTS"      ,	   0x11f0000012160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE23_CNTS"      ,	   0x11f0000012170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE24_CNTS"      ,	   0x11f0000012180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE25_CNTS"      ,	   0x11f0000012190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE26_CNTS"      ,	   0x11f00000121a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE27_CNTS"      ,	   0x11f00000121b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE28_CNTS"      ,	   0x11f00000121c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE29_CNTS"      ,	   0x11f00000121d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE30_CNTS"      ,	   0x11f00000121e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_DONE31_CNTS"      ,	   0x11f00000121f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	954},
+	{"SLI_PKT_IN_INSTR_COUNTS"     ,	   0x11f0000011200ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	955},
+	{"SLI_PKT_IN_PCIE_PORT"        ,	   0x11f00000111b0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	956},
+	{"SLI_PKT_INPUT_CONTROL"       ,	   0x11f0000011170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	957},
+	{"SLI_PKT_INSTR_ENB"           ,	   0x11f0000011000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	958},
+	{"SLI_PKT_INSTR_RD_SIZE"       ,	   0x11f00000111a0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	959},
+	{"SLI_PKT_INSTR_SIZE"          ,	   0x11f0000011020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	960},
+	{"SLI_PKT_INT_LEVELS"          ,	   0x11f0000011120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	961},
+	{"SLI_PKT_IPTR"                ,	   0x11f0000011070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	962},
+	{"SLI_PKT_OUT_BMODE"           ,	   0x11f00000110d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963},
+	{"SLI_PKT_OUT_ENB"             ,	   0x11f0000011010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964},
+	{"SLI_PKT_OUTPUT_WMARK"        ,	   0x11f0000011180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965},
+	{"SLI_PKT_PCIE_PORT"           ,	   0x11f00000110e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966},
+	{"SLI_PKT_PORT_IN_RST"         ,	   0x11f00000111f0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967},
+	{"SLI_PKT_SLIST_ES"            ,	   0x11f0000011050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968},
+	{"SLI_PKT_SLIST_NS"            ,	   0x11f0000011040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969},
+	{"SLI_PKT_SLIST_ROR"           ,	   0x11f0000011030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970},
+	{"SLI_PKT_TIME_INT"            ,	   0x11f0000011140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971},
+	{"SLI_PKT_TIME_INT_ENB"        ,	   0x11f0000011160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972},
+	{"SLI_S2M_PORT0_CTL"           ,	   0x11f0000013d80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_S2M_PORT1_CTL"           ,	   0x11f0000013d90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973},
+	{"SLI_SCRATCH_1"               ,	   0x11f00000103c0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974},
+	{"SLI_SCRATCH_2"               ,	   0x11f00000103d0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	975},
+	{"SLI_STATE1"                  ,	   0x11f0000010620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976},
+	{"SLI_STATE2"                  ,	   0x11f0000010630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977},
+	{"SLI_STATE3"                  ,	   0x11f0000010640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978},
+	{"SLI_WIN_RD_ADDR"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	979},
+	{"SLI_WIN_RD_DATA"             ,	              0x40ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	980},
+	{"SLI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	981},
+	{"SLI_WIN_WR_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	982},
+	{"SLI_WIN_WR_MASK"             ,	              0x30ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	983},
+	{"SLI_WINDOW_CTL"              ,	   0x11f00000102e0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	984},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	985},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	986},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	987},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	988},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	989},
+	{"SMI_DRV_CTL"                 ,	   0x1180000001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	990},
+	{"SRIO0_ACC_CTRL"              ,	   0x11800c8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO1_ACC_CTRL"              ,	   0x11800c9000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	991},
+	{"SRIO0_ASMBLY_ID"             ,	   0x11800c8000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO1_ASMBLY_ID"             ,	   0x11800c9000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	992},
+	{"SRIO0_ASMBLY_INFO"           ,	   0x11800c8000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO1_ASMBLY_INFO"           ,	   0x11800c9000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	993},
+	{"SRIO0_BELL_RESP_CTRL"        ,	   0x11800c8000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO1_BELL_RESP_CTRL"        ,	   0x11800c9000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	994},
+	{"SRIO0_BIST_STATUS"           ,	   0x11800c8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO1_BIST_STATUS"           ,	   0x11800c9000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	995},
+	{"SRIO0_IMSG_CTRL"             ,	   0x11800c8000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO1_IMSG_CTRL"             ,	   0x11800c9000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	996},
+	{"SRIO0_IMSG_INST_HDR000"      ,	   0x11800c8000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO0_IMSG_INST_HDR001"      ,	   0x11800c8000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO1_IMSG_INST_HDR000"      ,	   0x11800c9000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO1_IMSG_INST_HDR001"      ,	   0x11800c9000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	997},
+	{"SRIO0_IMSG_QOS_GRP000"       ,	   0x11800c8000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP001"       ,	   0x11800c8000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP002"       ,	   0x11800c8000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP003"       ,	   0x11800c8000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP004"       ,	   0x11800c8000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP005"       ,	   0x11800c8000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP006"       ,	   0x11800c8000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP007"       ,	   0x11800c8000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP008"       ,	   0x11800c8000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP009"       ,	   0x11800c8000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP010"       ,	   0x11800c8000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP011"       ,	   0x11800c8000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP012"       ,	   0x11800c8000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP013"       ,	   0x11800c8000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP014"       ,	   0x11800c8000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP015"       ,	   0x11800c8000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP016"       ,	   0x11800c8000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP017"       ,	   0x11800c8000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP018"       ,	   0x11800c8000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP019"       ,	   0x11800c8000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP020"       ,	   0x11800c80006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP021"       ,	   0x11800c80006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP022"       ,	   0x11800c80006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP023"       ,	   0x11800c80006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP024"       ,	   0x11800c80006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP025"       ,	   0x11800c80006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP026"       ,	   0x11800c80006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP027"       ,	   0x11800c80006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP028"       ,	   0x11800c80006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP029"       ,	   0x11800c80006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP030"       ,	   0x11800c80006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_QOS_GRP031"       ,	   0x11800c80006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP000"       ,	   0x11800c9000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP001"       ,	   0x11800c9000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP002"       ,	   0x11800c9000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP003"       ,	   0x11800c9000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP004"       ,	   0x11800c9000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP005"       ,	   0x11800c9000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP006"       ,	   0x11800c9000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP007"       ,	   0x11800c9000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP008"       ,	   0x11800c9000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP009"       ,	   0x11800c9000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP010"       ,	   0x11800c9000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP011"       ,	   0x11800c9000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP012"       ,	   0x11800c9000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP013"       ,	   0x11800c9000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP014"       ,	   0x11800c9000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP015"       ,	   0x11800c9000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP016"       ,	   0x11800c9000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP017"       ,	   0x11800c9000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP018"       ,	   0x11800c9000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP019"       ,	   0x11800c9000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP020"       ,	   0x11800c90006a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP021"       ,	   0x11800c90006a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP022"       ,	   0x11800c90006b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP023"       ,	   0x11800c90006b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP024"       ,	   0x11800c90006c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP025"       ,	   0x11800c90006c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP026"       ,	   0x11800c90006d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP027"       ,	   0x11800c90006d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP028"       ,	   0x11800c90006e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP029"       ,	   0x11800c90006e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP030"       ,	   0x11800c90006f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO1_IMSG_QOS_GRP031"       ,	   0x11800c90006f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	998},
+	{"SRIO0_IMSG_STATUS000"        ,	   0x11800c8000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS001"        ,	   0x11800c8000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS002"        ,	   0x11800c8000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS003"        ,	   0x11800c8000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS004"        ,	   0x11800c8000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS005"        ,	   0x11800c8000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS006"        ,	   0x11800c8000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS007"        ,	   0x11800c8000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS008"        ,	   0x11800c8000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS009"        ,	   0x11800c8000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS010"        ,	   0x11800c8000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS011"        ,	   0x11800c8000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS012"        ,	   0x11800c8000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS013"        ,	   0x11800c8000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS014"        ,	   0x11800c8000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS015"        ,	   0x11800c8000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS016"        ,	   0x11800c8000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS017"        ,	   0x11800c8000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS018"        ,	   0x11800c8000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS019"        ,	   0x11800c8000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS020"        ,	   0x11800c80007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS021"        ,	   0x11800c80007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS022"        ,	   0x11800c80007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_STATUS023"        ,	   0x11800c80007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS000"        ,	   0x11800c9000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS001"        ,	   0x11800c9000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS002"        ,	   0x11800c9000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS003"        ,	   0x11800c9000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS004"        ,	   0x11800c9000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS005"        ,	   0x11800c9000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS006"        ,	   0x11800c9000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS007"        ,	   0x11800c9000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS008"        ,	   0x11800c9000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS009"        ,	   0x11800c9000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS010"        ,	   0x11800c9000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS011"        ,	   0x11800c9000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS012"        ,	   0x11800c9000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS013"        ,	   0x11800c9000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS014"        ,	   0x11800c9000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS015"        ,	   0x11800c9000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS016"        ,	   0x11800c9000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS017"        ,	   0x11800c9000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS018"        ,	   0x11800c9000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS019"        ,	   0x11800c9000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS020"        ,	   0x11800c90007a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS021"        ,	   0x11800c90007a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS022"        ,	   0x11800c90007b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO1_IMSG_STATUS023"        ,	   0x11800c90007b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	999},
+	{"SRIO0_IMSG_VPORT_THR"        ,	   0x11800c8000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO1_IMSG_VPORT_THR"        ,	   0x11800c9000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1000},
+	{"SRIO0_INT2_ENABLE"           ,	   0x11800c80003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO1_INT2_ENABLE"           ,	   0x11800c90003e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1001},
+	{"SRIO0_INT2_REG"              ,	   0x11800c80003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO1_INT2_REG"              ,	   0x11800c90003e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1002},
+	{"SRIO0_INT_ENABLE"            ,	   0x11800c8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO1_INT_ENABLE"            ,	   0x11800c9000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1003},
+	{"SRIO0_INT_INFO0"             ,	   0x11800c8000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO1_INT_INFO0"             ,	   0x11800c9000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1004},
+	{"SRIO0_INT_INFO1"             ,	   0x11800c8000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO1_INT_INFO1"             ,	   0x11800c9000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1005},
+	{"SRIO0_INT_INFO2"             ,	   0x11800c8000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO1_INT_INFO2"             ,	   0x11800c9000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1006},
+	{"SRIO0_INT_INFO3"             ,	   0x11800c8000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO1_INT_INFO3"             ,	   0x11800c9000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1007},
+	{"SRIO0_INT_REG"               ,	   0x11800c8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO1_INT_REG"               ,	   0x11800c9000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1008},
+	{"SRIO0_IP_FEATURE"            ,	   0x11800c80003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO1_IP_FEATURE"            ,	   0x11800c90003f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1009},
+	{"SRIO0_MAC_BUFFERS"           ,	   0x11800c8000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO1_MAC_BUFFERS"           ,	   0x11800c9000390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1010},
+	{"SRIO0_MAINT_OP"              ,	   0x11800c8000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO1_MAINT_OP"              ,	   0x11800c9000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1011},
+	{"SRIO0_MAINT_RD_DATA"         ,	   0x11800c8000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO1_MAINT_RD_DATA"         ,	   0x11800c9000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1012},
+	{"SRIO0_MCE_TX_CTL"            ,	   0x11800c8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO1_MCE_TX_CTL"            ,	   0x11800c9000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1013},
+	{"SRIO0_MEM_OP_CTRL"           ,	   0x11800c8000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO1_MEM_OP_CTRL"           ,	   0x11800c9000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1014},
+	{"SRIO0_OMSG_CTRL000"          ,	   0x11800c8000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO0_OMSG_CTRL001"          ,	   0x11800c80004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO1_OMSG_CTRL000"          ,	   0x11800c9000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO1_OMSG_CTRL001"          ,	   0x11800c90004c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1015},
+	{"SRIO0_OMSG_DONE_COUNTS000"   ,	   0x11800c80004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_OMSG_DONE_COUNTS001"   ,	   0x11800c80004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_OMSG_DONE_COUNTS000"   ,	   0x11800c90004b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO1_OMSG_DONE_COUNTS001"   ,	   0x11800c90004f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1016},
+	{"SRIO0_OMSG_FMP_MR000"        ,	   0x11800c8000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO0_OMSG_FMP_MR001"        ,	   0x11800c80004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO1_OMSG_FMP_MR000"        ,	   0x11800c9000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO1_OMSG_FMP_MR001"        ,	   0x11800c90004d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1017},
+	{"SRIO0_OMSG_NMP_MR000"        ,	   0x11800c80004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO0_OMSG_NMP_MR001"        ,	   0x11800c80004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO1_OMSG_NMP_MR000"        ,	   0x11800c90004a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO1_OMSG_NMP_MR001"        ,	   0x11800c90004e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1018},
+	{"SRIO0_OMSG_PORT000"          ,	   0x11800c8000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO0_OMSG_PORT001"          ,	   0x11800c80004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO1_OMSG_PORT000"          ,	   0x11800c9000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO1_OMSG_PORT001"          ,	   0x11800c90004c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1019},
+	{"SRIO0_OMSG_SILO_THR"         ,	   0x11800c80004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO1_OMSG_SILO_THR"         ,	   0x11800c90004f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1020},
+	{"SRIO0_OMSG_SP_MR000"         ,	   0x11800c8000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO0_OMSG_SP_MR001"         ,	   0x11800c80004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO1_OMSG_SP_MR000"         ,	   0x11800c9000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO1_OMSG_SP_MR001"         ,	   0x11800c90004d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1021},
+	{"SRIO0_PRIO000_IN_USE"        ,	   0x11800c80003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_PRIO001_IN_USE"        ,	   0x11800c80003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_PRIO002_IN_USE"        ,	   0x11800c80003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_PRIO003_IN_USE"        ,	   0x11800c80003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_PRIO000_IN_USE"        ,	   0x11800c90003c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_PRIO001_IN_USE"        ,	   0x11800c90003c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_PRIO002_IN_USE"        ,	   0x11800c90003d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO1_PRIO003_IN_USE"        ,	   0x11800c90003d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1022},
+	{"SRIO0_RX_BELL"               ,	   0x11800c8000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO1_RX_BELL"               ,	   0x11800c9000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1023},
+	{"SRIO0_RX_BELL_SEQ"           ,	   0x11800c8000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO1_RX_BELL_SEQ"           ,	   0x11800c9000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1024},
+	{"SRIO0_RX_STATUS"             ,	   0x11800c8000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO1_RX_STATUS"             ,	   0x11800c9000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1025},
+	{"SRIO0_S2M_TYPE000"           ,	   0x11800c8000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE001"           ,	   0x11800c8000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE002"           ,	   0x11800c8000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE003"           ,	   0x11800c8000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE004"           ,	   0x11800c80001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE005"           ,	   0x11800c80001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE006"           ,	   0x11800c80001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE007"           ,	   0x11800c80001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE008"           ,	   0x11800c80001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE009"           ,	   0x11800c80001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE010"           ,	   0x11800c80001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE011"           ,	   0x11800c80001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE012"           ,	   0x11800c80001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE013"           ,	   0x11800c80001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE014"           ,	   0x11800c80001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_S2M_TYPE015"           ,	   0x11800c80001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE000"           ,	   0x11800c9000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE001"           ,	   0x11800c9000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE002"           ,	   0x11800c9000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE003"           ,	   0x11800c9000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE004"           ,	   0x11800c90001a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE005"           ,	   0x11800c90001a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE006"           ,	   0x11800c90001b0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE007"           ,	   0x11800c90001b8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE008"           ,	   0x11800c90001c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE009"           ,	   0x11800c90001c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE010"           ,	   0x11800c90001d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE011"           ,	   0x11800c90001d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE012"           ,	   0x11800c90001e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE013"           ,	   0x11800c90001e8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE014"           ,	   0x11800c90001f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO1_S2M_TYPE015"           ,	   0x11800c90001f8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1026},
+	{"SRIO0_SEQ"                   ,	   0x11800c8000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO1_SEQ"                   ,	   0x11800c9000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1027},
+	{"SRIO0_STATUS_REG"            ,	   0x11800c8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO1_STATUS_REG"            ,	   0x11800c9000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1028},
+	{"SRIO0_TAG_CTRL"              ,	   0x11800c8000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"SRIO1_TAG_CTRL"              ,	   0x11800c9000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1029},
+	{"SRIO0_TLP_CREDITS"           ,	   0x11800c8000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"SRIO1_TLP_CREDITS"           ,	   0x11800c9000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1030},
+	{"SRIO0_TX_BELL"               ,	   0x11800c8000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"SRIO1_TX_BELL"               ,	   0x11800c9000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1031},
+	{"SRIO0_TX_BELL_INFO"          ,	   0x11800c8000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO1_TX_BELL_INFO"          ,	   0x11800c9000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1032},
+	{"SRIO0_TX_CTRL"               ,	   0x11800c8000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"SRIO1_TX_CTRL"               ,	   0x11800c9000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1033},
+	{"SRIO0_TX_EMPHASIS"           ,	   0x11800c80003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"SRIO1_TX_EMPHASIS"           ,	   0x11800c90003f0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1034},
+	{"SRIO0_TX_STATUS"             ,	   0x11800c8000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"SRIO1_TX_STATUS"             ,	   0x11800c9000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1035},
+	{"SRIO0_WR_DONE_COUNTS"        ,	   0x11800c8000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"SRIO1_WR_DONE_COUNTS"        ,	   0x11800c9000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1036},
+	{"SRIOMAINT0_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT1_ASMBLY_ID"        ,	               0x8ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1037},
+	{"SRIOMAINT0_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT1_ASMBLY_INFO"      ,	               0xcull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1038},
+	{"SRIOMAINT0_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX000"      ,	          0x200010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX001"      ,	          0x200014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX002"      ,	          0x200018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX003"      ,	          0x20001cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX004"      ,	          0x200020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX005"      ,	          0x200024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX006"      ,	          0x200028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX007"      ,	          0x20002cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX008"      ,	          0x200030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX009"      ,	          0x200034ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX010"      ,	          0x200038ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX011"      ,	          0x20003cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX012"      ,	          0x200040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX013"      ,	          0x200044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX014"      ,	          0x200048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT1_BAR1_IDX015"      ,	          0x20004cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1039},
+	{"SRIOMAINT0_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT1_BELL_STATUS"      ,	          0x200080ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1040},
+	{"SRIOMAINT0_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT1_COMP_TAG"         ,	              0x6cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1041},
+	{"SRIOMAINT0_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT1_CORE_ENABLES"     ,	          0x200070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1042},
+	{"SRIOMAINT0_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT1_DEV_ID"           ,	               0x0ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1043},
+	{"SRIOMAINT0_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT1_DEV_REV"          ,	               0x4ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1044},
+	{"SRIOMAINT0_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT1_DST_OPS"          ,	              0x1cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1045},
+	{"SRIOMAINT0_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT1_ERB_ATTR_CAPT"    ,	            0x2048ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1046},
+	{"SRIOMAINT0_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT1_ERB_ERR_DET"      ,	            0x2040ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1047},
+	{"SRIOMAINT0_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT1_ERB_ERR_RATE"     ,	            0x2068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1048},
+	{"SRIOMAINT0_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT1_ERB_ERR_RATE_EN"  ,	            0x2044ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1049},
+	{"SRIOMAINT0_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT1_ERB_ERR_RATE_THR" ,	            0x206cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1050},
+	{"SRIOMAINT0_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT1_ERB_HDR"          ,	            0x2000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1051},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_H",	            0x2010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1052},
+	{"SRIOMAINT0_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT1_ERB_LT_ADDR_CAPT_L",	            0x2014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1053},
+	{"SRIOMAINT0_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT1_ERB_LT_CTRL_CAPT" ,	            0x201cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1054},
+	{"SRIOMAINT0_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT1_ERB_LT_DEV_ID"    ,	            0x2028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1055},
+	{"SRIOMAINT0_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT1_ERB_LT_DEV_ID_CAPT",	            0x2018ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1056},
+	{"SRIOMAINT0_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT1_ERB_LT_ERR_DET"   ,	            0x2008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1057},
+	{"SRIOMAINT0_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT1_ERB_LT_ERR_EN"    ,	            0x200cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1058},
+	{"SRIOMAINT0_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT1_ERB_PACK_CAPT_1"  ,	            0x2050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1059},
+	{"SRIOMAINT0_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT1_ERB_PACK_CAPT_2"  ,	            0x2054ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1060},
+	{"SRIOMAINT0_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT1_ERB_PACK_CAPT_3"  ,	            0x2058ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1061},
+	{"SRIOMAINT0_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT1_ERB_PACK_SYM_CAPT",	            0x204cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1062},
+	{"SRIOMAINT0_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT1_HB_DEV_ID_LOCK"   ,	              0x68ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1063},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG" ,	          0x102000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1064},
+	{"SRIOMAINT0_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT1_IR_BUFFER_CONFIG2",	          0x102004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1065},
+	{"SRIOMAINT0_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT1_IR_PD_PHY_CTRL"   ,	          0x107028ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1066},
+	{"SRIOMAINT0_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT1_IR_PD_PHY_STAT"   ,	          0x10702cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1067},
+	{"SRIOMAINT0_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT1_IR_PI_PHY_CTRL"   ,	          0x107020ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1068},
+	{"SRIOMAINT0_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT1_IR_PI_PHY_STAT"   ,	          0x107024ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1069},
+	{"SRIOMAINT0_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT1_IR_SP_RX_CTRL"    ,	          0x10700cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1070},
+	{"SRIOMAINT0_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT1_IR_SP_RX_DATA"    ,	          0x107014ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1071},
+	{"SRIOMAINT0_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT1_IR_SP_RX_STAT"    ,	          0x107010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1072},
+	{"SRIOMAINT0_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT1_IR_SP_TX_CTRL"    ,	          0x107000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1073},
+	{"SRIOMAINT0_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT1_IR_SP_TX_DATA"    ,	          0x107008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1074},
+	{"SRIOMAINT0_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT1_IR_SP_TX_STAT"    ,	          0x107004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1075},
+	{"SRIOMAINT0_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_LANE_000_STATUS_0",	            0x1010ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_LANE_001_STATUS_0",	            0x1030ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_LANE_002_STATUS_0",	            0x1050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT1_LANE_003_STATUS_0",	            0x1070ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1076},
+	{"SRIOMAINT0_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT1_LCS_BA0"          ,	              0x58ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1077},
+	{"SRIOMAINT0_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT1_LCS_BA1"          ,	              0x5cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1078},
+	{"SRIOMAINT0_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT1_M2S_BAR0_START0"  ,	          0x200000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1079},
+	{"SRIOMAINT0_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT1_M2S_BAR0_START1"  ,	          0x200004ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1080},
+	{"SRIOMAINT0_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT1_M2S_BAR1_START0"  ,	          0x200008ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1081},
+	{"SRIOMAINT0_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT1_M2S_BAR1_START1"  ,	          0x20000cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1082},
+	{"SRIOMAINT0_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT1_M2S_BAR2_START"   ,	          0x200050ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1083},
+	{"SRIOMAINT0_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"SRIOMAINT1_MAC_CTRL"         ,	          0x200068ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1084},
+	{"SRIOMAINT0_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
+	{"SRIOMAINT1_PE_FEAT"          ,	              0x10ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1085},
+	{"SRIOMAINT0_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
+	{"SRIOMAINT1_PE_LLC"           ,	              0x4cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1086},
+	{"SRIOMAINT0_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
+	{"SRIOMAINT1_PORT_0_CTL"       ,	             0x15cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1087},
+	{"SRIOMAINT0_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
+	{"SRIOMAINT1_PORT_0_CTL2"      ,	             0x154ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1088},
+	{"SRIOMAINT0_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
+	{"SRIOMAINT1_PORT_0_ERR_STAT"  ,	             0x158ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1089},
+	{"SRIOMAINT0_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
+	{"SRIOMAINT1_PORT_0_LINK_REQ"  ,	             0x140ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1090},
+	{"SRIOMAINT0_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
+	{"SRIOMAINT1_PORT_0_LINK_RESP" ,	             0x144ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1091},
+	{"SRIOMAINT0_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
+	{"SRIOMAINT1_PORT_0_LOCAL_ACKID",	             0x148ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1092},
+	{"SRIOMAINT0_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
+	{"SRIOMAINT1_PORT_GEN_CTL"     ,	             0x13cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1093},
+	{"SRIOMAINT0_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
+	{"SRIOMAINT1_PORT_LT_CTL"      ,	             0x120ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1094},
+	{"SRIOMAINT0_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
+	{"SRIOMAINT1_PORT_MBH0"        ,	             0x100ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1095},
+	{"SRIOMAINT0_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
+	{"SRIOMAINT1_PORT_RT_CTL"      ,	             0x124ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1096},
+	{"SRIOMAINT0_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
+	{"SRIOMAINT1_PORT_TTL_CTL"     ,	             0x12cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1097},
+	{"SRIOMAINT0_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
+	{"SRIOMAINT1_PRI_DEV_ID"       ,	              0x60ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1098},
+	{"SRIOMAINT0_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
+	{"SRIOMAINT1_SEC_DEV_CTRL"     ,	          0x200064ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1099},
+	{"SRIOMAINT0_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
+	{"SRIOMAINT1_SEC_DEV_ID"       ,	          0x200060ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1100},
+	{"SRIOMAINT0_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
+	{"SRIOMAINT1_SERIAL_LANE_HDR"  ,	            0x1000ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1101},
+	{"SRIOMAINT0_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT1_SRC_OPS"          ,	              0x18ull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1102},
+	{"SRIOMAINT0_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"SRIOMAINT1_TX_DROP"          ,	          0x20006cull,	CVMX_CSR_DB_TYPE_SRIOMAINT,	32,	1103},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1104},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1105},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1106},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1107},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1108},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1109},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1110},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1111},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1112},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1113},
+	{"TRA_BIST_STATUS"             ,	   0x11800a8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1114},
+	{"TRA_CTL"                     ,	   0x11800a8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1115},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800a8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1116},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800a8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1117},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800a8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1118},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800a8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1119},
+	{"TRA_FILT_CMD"                ,	   0x11800a8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1120},
+	{"TRA_FILT_DID"                ,	   0x11800a8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1121},
+	{"TRA_FILT_SID"                ,	   0x11800a8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1122},
+	{"TRA_INT_STATUS"              ,	   0x11800a8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1123},
+	{"TRA_READ_DAT"                ,	   0x11800a8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1124},
+	{"TRA_READ_DAT_HI"             ,	   0x11800a8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1125},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800a8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1126},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800a80000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1127},
+	{"TRA_TRIG0_CMD"               ,	   0x11800a8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1128},
+	{"TRA_TRIG0_DID"               ,	   0x11800a8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1129},
+	{"TRA_TRIG0_SID"               ,	   0x11800a8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1130},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800a80000d8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1131},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800a80000e0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1132},
+	{"TRA_TRIG1_CMD"               ,	   0x11800a80000c0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1133},
+	{"TRA_TRIG1_DID"               ,	   0x11800a80000d0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1134},
+	{"TRA_TRIG1_SID"               ,	   0x11800a80000c8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1135},
+	{"UAHC0_EHCI_ASYNCLISTADDR"    ,	   0x16f0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1136},
+	{"UAHC0_EHCI_CONFIGFLAG"       ,	   0x16f0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1137},
+	{"UAHC0_EHCI_CTRLDSSEGMENT"    ,	   0x16f0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1138},
+	{"UAHC0_EHCI_FRINDEX"          ,	   0x16f000000001cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1139},
+	{"UAHC0_EHCI_HCCAPBASE"        ,	   0x16f0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1140},
+	{"UAHC0_EHCI_HCCPARAMS"        ,	   0x16f0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1141},
+	{"UAHC0_EHCI_HCSPARAMS"        ,	   0x16f0000000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1142},
+	{"UAHC0_EHCI_INSNREG00"        ,	   0x16f0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1143},
+	{"UAHC0_EHCI_INSNREG03"        ,	   0x16f000000009cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1144},
+	{"UAHC0_EHCI_INSNREG04"        ,	   0x16f00000000a0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1145},
+	{"UAHC0_EHCI_INSNREG06"        ,	   0x16f00000000e8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1146},
+	{"UAHC0_EHCI_INSNREG07"        ,	   0x16f00000000ecull,	CVMX_CSR_DB_TYPE_NCB,	32,	1147},
+	{"UAHC0_EHCI_PERIODICLISTBASE" ,	   0x16f0000000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1148},
+	{"UAHC0_EHCI_PORTSC001"        ,	   0x16f0000000054ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
+	{"UAHC0_EHCI_PORTSC002"        ,	   0x16f0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1149},
+	{"UAHC0_EHCI_USBCMD"           ,	   0x16f0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1150},
+	{"UAHC0_EHCI_USBINTR"          ,	   0x16f0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1151},
+	{"UAHC0_EHCI_USBSTS"           ,	   0x16f0000000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1152},
+	{"UAHC0_OHCI0_HCBULKCURRENTED" ,	   0x16f000000042cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1153},
+	{"UAHC0_OHCI0_HCBULKHEADED"    ,	   0x16f0000000428ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1154},
+	{"UAHC0_OHCI0_HCCOMMANDSTATUS" ,	   0x16f0000000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1155},
+	{"UAHC0_OHCI0_HCCONTROL"       ,	   0x16f0000000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1156},
+	{"UAHC0_OHCI0_HCCONTROLCURRENTED",	   0x16f0000000424ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1157},
+	{"UAHC0_OHCI0_HCCONTROLHEADED" ,	   0x16f0000000420ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1158},
+	{"UAHC0_OHCI0_HCDONEHEAD"      ,	   0x16f0000000430ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1159},
+	{"UAHC0_OHCI0_HCFMINTERVAL"    ,	   0x16f0000000434ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1160},
+	{"UAHC0_OHCI0_HCFMNUMBER"      ,	   0x16f000000043cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1161},
+	{"UAHC0_OHCI0_HCFMREMAINING"   ,	   0x16f0000000438ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1162},
+	{"UAHC0_OHCI0_HCHCCA"          ,	   0x16f0000000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1163},
+	{"UAHC0_OHCI0_HCINTERRUPTDISABLE",	   0x16f0000000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1164},
+	{"UAHC0_OHCI0_HCINTERRUPTENABLE",	   0x16f0000000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1165},
+	{"UAHC0_OHCI0_HCINTERRUPTSTATUS",	   0x16f000000040cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1166},
+	{"UAHC0_OHCI0_HCLSTHRESHOLD"   ,	   0x16f0000000444ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1167},
+	{"UAHC0_OHCI0_HCPERIODCURRENTED",	   0x16f000000041cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1168},
+	{"UAHC0_OHCI0_HCPERIODICSTART" ,	   0x16f0000000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1169},
+	{"UAHC0_OHCI0_HCREVISION"      ,	   0x16f0000000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1170},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORA" ,	   0x16f0000000448ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1171},
+	{"UAHC0_OHCI0_HCRHDESCRIPTORB" ,	   0x16f000000044cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1172},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS001",	   0x16f0000000454ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
+	{"UAHC0_OHCI0_HCRHPORTSTATUS002",	   0x16f0000000458ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1173},
+	{"UAHC0_OHCI0_HCRHSTATUS"      ,	   0x16f0000000450ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1174},
+	{"UAHC0_OHCI0_INSNREG06"       ,	   0x16f0000000498ull,	CVMX_CSR_DB_TYPE_NCB,	32,	1175},
+	{"UAHC0_OHCI0_INSNREG07"       ,	   0x16f000000049cull,	CVMX_CSR_DB_TYPE_NCB,	32,	1176},
+	{"UCTL0_BIST_STATUS"           ,	   0x118006f0000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1177},
+	{"UCTL0_CLK_RST_CTL"           ,	   0x118006f000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1178},
+	{"UCTL0_EHCI_CTL"              ,	   0x118006f000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1179},
+	{"UCTL0_EHCI_FLA"              ,	   0x118006f0000a8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1180},
+	{"UCTL0_ERTO_CTL"              ,	   0x118006f000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1181},
+	{"UCTL0_IF_ENA"                ,	   0x118006f000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1182},
+	{"UCTL0_INT_ENA"               ,	   0x118006f000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1183},
+	{"UCTL0_INT_REG"               ,	   0x118006f000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1184},
+	{"UCTL0_OHCI_CTL"              ,	   0x118006f000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1185},
+	{"UCTL0_ORTO_CTL"              ,	   0x118006f000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1186},
+	{"UCTL0_PPAF_WM"               ,	   0x118006f000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1187},
+	{"UCTL0_UPHY_CTL_STATUS"       ,	   0x118006f000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1188},
+	{"UCTL0_UPHY_PORT000_CTL_STATUS",	   0x118006f000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
+	{"UCTL0_UPHY_PORT001_CTL_STATUS",	   0x118006f000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1189},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1190},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1191},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1192},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000a0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1193},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1194},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1195},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1196},
+	{"ZIP_THROTTLE"                ,	   0x1180038000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1197},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_25"              ,	24,	2,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	2,	"R/W",	0,	1,	1ull,	0},
+	{"RX_EN"                       ,	4,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"BURST"                       ,	6,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	2,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	2,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	2,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	3,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	4,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	9,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	10,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	10,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	10,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	11,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	12,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	13,	"RO",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	13,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	13,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	13,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	13,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	14,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	14,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	15,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	15,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	16,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	17,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	18,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	19,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	19,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	20,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	20,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	21,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	21,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	23,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	32,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	32,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	33,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	35,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	36,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	36,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	37,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	37,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	37,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	38,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	38,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	39,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	39,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	40,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	40,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"PTP_LOST"                    ,	20,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRST"                      ,	1,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"ENABLE"                      ,	2,	1,	71,	"R/W",	0,	0,	1ull,	1ull},
+	{"COMP"                        ,	3,	1,	71,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLLRST"                      ,	4,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_SET"                   ,	8,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_14"              ,	13,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKTX_BYP"                   ,	15,	1,	71,	"R/W",	0,	1,	1ull,	0},
+	{"CLKRX_SET"                   ,	16,	5,	71,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_22"              ,	21,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CLKRX_BYP"                   ,	23,	1,	71,	"R/W",	0,	1,	0ull,	0},
+	{"CLK_SET"                     ,	24,	5,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_NCTL"                    ,	32,	6,	71,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_PCTL"                    ,	40,	6,	71,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_NCTL"                    ,	48,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_54_55"              ,	54,	2,	71,	"RAZ",	1,	1,	0,	0},
+	{"CMP_PCTL"                    ,	56,	6,	71,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	71,	"RAZ",	1,	1,	0,	0},
+	{"DRV_BYP"                     ,	63,	1,	71,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST"                        ,	0,	5,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	72,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"SLI"                         ,	3,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IPD"                         ,	9,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"L2C"                         ,	16,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PIP"                         ,	20,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"ASXPCS0"                     ,	22,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	73,	"RAZ",	1,	1,	0,	0},
+	{"PEM0"                        ,	25,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	26,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	28,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"IOB"                         ,	30,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	73,	"RAZ",	1,	1,	0,	0},
+	{"SRIO0"                       ,	32,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	33,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_39"              ,	34,	6,	73,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	40,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	41,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	42,	1,	73,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	73,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	6,	74,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	74,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	6,	75,	"RO",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	75,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	76,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	78,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	79,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	79,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	80,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	80,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	81,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	81,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	82,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	82,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	83,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	84,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	84,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	85,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	85,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	86,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	86,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	87,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	6,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	88,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	46,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"DFM"                         ,	56,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RST"                         ,	63,	1,	88,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	89,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	89,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	89,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	90,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	90,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	91,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	91,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	91,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	91,	"RO",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	3,	92,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_7"                ,	3,	5,	92,	"RAZ",	1,	1,	0,	0},
+	{"IRQ"                         ,	8,	2,	92,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	92,	"RAZ",	1,	1,	0,	0},
+	{"SEL"                         ,	16,	3,	92,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	92,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	6,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_17"               ,	6,	12,	93,	"RAZ",	1,	1,	0,	0},
+	{"MII1"                        ,	18,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	20,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	21,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	22,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	23,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	24,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	25,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	26,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	27,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	28,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	29,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	30,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	31,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	32,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	33,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"SLI"                         ,	34,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"DPI"                         ,	35,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"AGX0"                        ,	36,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_45"              ,	37,	9,	93,	"RAZ",	1,	1,	0,	0},
+	{"AGL"                         ,	46,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"PTP"                         ,	47,	1,	93,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PEM0"                        ,	48,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"PEM1"                        ,	49,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO0"                       ,	50,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"SRIO1"                       ,	51,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	52,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_55"              ,	53,	3,	93,	"RAZ",	1,	1,	0,	0},
+	{"DFM"                         ,	56,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_62"              ,	57,	6,	93,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	63,	1,	93,	"RO",	0,	0,	0ull,	0ull},
+	{"BITS"                        ,	0,	32,	94,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	94,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	95,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	95,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	6,	96,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	96,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	97,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	6,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	98,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	99,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	100,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	5,	100,	"R/W",	0,	0,	31ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	100,	"RAZ",	1,	1,	0,	0},
+	{"LANE_EN"                     ,	0,	4,	101,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	101,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	101,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	101,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	101,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	101,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	101,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	102,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	102,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_39"              ,	32,	8,	102,	"RAZ",	1,	1,	0,	0},
+	{"G2MARGIN"                    ,	40,	5,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	102,	"RAZ",	1,	1,	0,	0},
+	{"G2DEEMPH"                    ,	48,	5,	102,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	102,	"RAZ",	1,	1,	0,	0},
+	{"G2BYPASS"                    ,	63,	1,	102,	"R/W",	0,	1,	0ull,	0},
+	{"LANE_EN"                     ,	0,	4,	103,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	103,	"RAZ",	1,	1,	0,	0},
+	{"TXMARGIN"                    ,	8,	5,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	103,	"RAZ",	1,	1,	0,	0},
+	{"TXDEEMPH"                    ,	16,	5,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_30"              ,	21,	10,	103,	"RAZ",	1,	1,	0,	0},
+	{"TXBYPASS"                    ,	31,	1,	103,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	103,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	3,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	104,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	2,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	104,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	104,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	105,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	105,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	105,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	3,	105,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_60"              ,	43,	18,	105,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	105,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	105,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	105,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	106,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	106,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	107,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	107,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	108,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	108,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	109,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	109,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	110,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	111,	"RAZ",	1,	1,	0,	0},
+	{"PDB"                         ,	0,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	4,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTX"                         ,	8,	2,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX"                         ,	16,	2,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFB"                         ,	24,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_27"              ,	25,	3,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MWB"                         ,	28,	1,	112,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	112,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	0,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"GIB"                         ,	1,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"GIF"                         ,	2,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"NCD"                         ,	3,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"GUTP"                        ,	4,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GUTV"                        ,	8,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	9,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM1"                        ,	10,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM2"                        ,	11,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RAM3"                        ,	12,	1,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	0,	1,	114,	"R/W",	0,	0,	1ull,	0ull},
+	{"CLDTECRIP"                   ,	1,	3,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLMSKCRIP"                   ,	4,	4,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"REPL_ENA"                    ,	8,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	114,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	115,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	115,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	115,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_4"                ,	3,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"SBDLCK"                      ,	5,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	115,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	116,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	117,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	118,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	119,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	120,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	121,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	121,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	121,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	121,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	122,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	35,	122,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	122,	"RAZ",	1,	1,	0,	0},
+	{"RAM1FADR"                    ,	0,	14,	123,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	123,	"RAZ",	1,	1,	0,	0},
+	{"RAM2FADR"                    ,	16,	9,	123,	"RO",	1,	1,	0,	0},
+	{"RESERVED_25_31"              ,	25,	7,	123,	"RAZ",	1,	1,	0,	0},
+	{"RAM3FADR"                    ,	32,	12,	123,	"RO",	1,	1,	0,	0},
+	{"RESERVED_44_63"              ,	44,	20,	123,	"RAZ",	1,	1,	0,	0},
+	{"DBLOVF"                      ,	0,	1,	124,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC0PERR"                     ,	1,	3,	124,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	124,	"RAZ",	1,	1,	0,	0},
+	{"CNDRD"                       ,	16,	1,	124,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	124,	"RAZ",	1,	1,	0,	0},
+	{"DBLINA"                      ,	0,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC0PENA"                     ,	1,	3,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	125,	"RAZ",	1,	1,	0,	0},
+	{"HIDAT"                       ,	0,	64,	126,	"R/W",	1,	1,	0,	0},
+	{"PFCNT0"                      ,	0,	64,	127,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	128,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	128,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	128,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT1"                      ,	0,	64,	129,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	130,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	130,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	130,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT2"                      ,	0,	64,	131,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	132,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	132,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	132,	"RAZ",	1,	1,	0,	0},
+	{"PFCNT3"                      ,	0,	64,	133,	"R/W",	0,	1,	0ull,	0},
+	{"CLNUM"                       ,	0,	2,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLDTE"                       ,	2,	4,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	134,	"RAZ",	1,	1,	0,	0},
+	{"EVSEL"                       ,	8,	6,	134,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_14_63"              ,	14,	50,	134,	"RAZ",	1,	1,	0,	0},
+	{"CNT0ENA"                     ,	0,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	1,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	2,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	3,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0WCLR"                    ,	4,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1WCLR"                    ,	5,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2WCLR"                    ,	6,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3WCLR"                    ,	7,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RCLR"                    ,	8,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RCLR"                    ,	9,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RCLR"                    ,	10,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RCLR"                    ,	11,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNODE"                       ,	12,	3,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENODE"                       ,	15,	3,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"EDNODE"                      ,	18,	2,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMODE"                       ,	20,	1,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGID"                        ,	21,	8,	135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	135,	"RAZ",	1,	1,	0,	0},
+	{"PRBS"                        ,	0,	32,	136,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	136,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	136,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	136,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	136,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	137,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	137,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	138,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	138,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	139,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	139,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	139,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	139,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	139,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	139,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	139,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	139,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	139,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	139,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	139,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	139,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	140,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	140,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	140,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	140,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	140,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	140,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	140,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	140,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	140,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	140,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	140,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	141,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW_LSB"                     ,	2,	3,	141,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	141,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	141,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	141,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	141,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	141,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	141,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	141,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWCNT"                       ,	1,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	3,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	142,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	142,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_FCLKDIS"                ,	17,	1,	142,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	142,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	142,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	143,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	143,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	144,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	144,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_SETTING"               ,	20,	8,	144,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	144,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	144,	"RAZ",	1,	1,	0,	0},
+	{"FCLKCNT"                     ,	0,	64,	145,	"RO",	0,	0,	0ull,	0ull},
+	{"MWB"                         ,	0,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"RPB"                         ,	1,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"MFF"                         ,	2,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQ"                         ,	3,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"CAB"                         ,	4,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	146,	"RAZ",	1,	1,	0,	0},
+	{"DFR_ENA"                     ,	0,	1,	147,	"R/W",	0,	0,	0ull,	1ull},
+	{"RECC_ENA"                    ,	1,	1,	147,	"R/W",	0,	0,	0ull,	1ull},
+	{"WECC_ENA"                    ,	2,	1,	147,	"R/W",	0,	0,	0ull,	1ull},
+	{"SBE_ENA"                     ,	3,	1,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	147,	"RAZ",	1,	1,	0,	0},
+	{"SBE_INTENA"                  ,	0,	1,	148,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBE_INTENA"                  ,	1,	1,	148,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	148,	"RAZ",	1,	1,	0,	0},
+	{"SCLKDIS"                     ,	0,	1,	149,	"R/W",	0,	0,	1ull,	0ull},
+	{"BIST_START"                  ,	1,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	2,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	149,	"RAZ",	1,	1,	0,	0},
+	{"SBE_ERR"                     ,	0,	1,	150,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE_ERR"                     ,	1,	1,	150,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	150,	"RAZ",	1,	1,	0,	0},
+	{"FADR"                        ,	4,	28,	150,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	32,	10,	150,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	150,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	151,	"RO",	0,	0,	0ull,	0ull},
+	{"CWL"                         ,	0,	3,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	152,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	152,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	152,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	152,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"PPD"                         ,	24,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	152,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	153,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	153,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	154,	"RO",	0,	0,	0ull,	0ull},
+	{"TS_STAGGER"                  ,	0,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	155,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	155,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	155,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	156,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	157,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	157,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	157,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	157,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	157,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	158,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	159,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_53"              ,	12,	42,	159,	"R/W",	1,	1,	0,	0},
+	{"STATUS"                      ,	54,	2,	159,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	159,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D0_R1"                  ,	8,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R0"                  ,	16,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D1_R1"                  ,	24,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R0"                  ,	32,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	161,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	161,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	161,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	161,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	161,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	162,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	162,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	162,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	162,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	162,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	163,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	163,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	163,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	163,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	163,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	163,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	163,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	163,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	163,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	163,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	163,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	164,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	164,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	164,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	164,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRFC"                        ,	17,	5,	164,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	164,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	164,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	164,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	164,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	164,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	164,	"R/W",	0,	0,	10ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	164,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	165,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	165,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	165,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	165,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	165,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	166,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	167,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	167,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_44"              ,	10,	35,	167,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	45,	2,	167,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	167,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R0"                  ,	32,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	40,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	48,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	56,	8,	168,	"R/W",	0,	0,	255ull,	255ull},
+	{"BIST"                        ,	0,	37,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	169,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	170,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLK"                         ,	1,	1,	170,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	170,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	171,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	172,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	172,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	173,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	173,	"RAZ",	1,	1,	0,	0},
+	{"IDLE"                        ,	40,	1,	173,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_41_47"              ,	41,	7,	173,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	48,	14,	173,	"R/W",	0,	1,	64ull,	0},
+	{"RESERVED_62_63"              ,	62,	2,	173,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	174,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	174,	"RAZ",	1,	1,	0,	0},
+	{"STATE"                       ,	0,	64,	175,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	0,	64,	176,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_13"               ,	0,	14,	177,	"RAZ",	1,	1,	0,	0},
+	{"O_MODE"                      ,	14,	1,	177,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	177,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	177,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	177,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	177,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	177,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	177,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	177,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_47"              ,	34,	14,	177,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ENB"                     ,	48,	6,	177,	"R/W",	0,	0,	0ull,	63ull},
+	{"RESERVED_54_55"              ,	54,	2,	177,	"RAZ",	1,	1,	0,	0},
+	{"PKT_EN"                      ,	56,	1,	177,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_HP"                      ,	57,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"COMMIT_MODE"                 ,	58,	1,	177,	"R/W",	0,	0,	0ull,	1ull},
+	{"FFP_DIS"                     ,	59,	1,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_EN1"                     ,	60,	1,	177,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_61_63"              ,	61,	3,	177,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	178,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	178,	"RAZ",	1,	1,	0,	0},
+	{"BLKS"                        ,	0,	4,	179,	"R/W",	0,	1,	2ull,	0},
+	{"BASE"                        ,	4,	4,	179,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	179,	"RAZ",	1,	1,	0,	0},
+	{"RSL"                         ,	0,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB"                         ,	1,	1,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	180,	"RAZ",	1,	1,	0,	0},
+	{"FFP"                         ,	4,	4,	180,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	180,	"RAZ",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMADBO"                      ,	8,	8,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	181,	"R/W",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	181,	"R/W",	1,	1,	0,	0},
+	{"NDERR"                       ,	0,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFOVR"                       ,	1,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	182,	"RAZ",	1,	1,	0,	0},
+	{"DMADBO"                      ,	8,	8,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADADR"                  ,	16,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADLEN"                  ,	17,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_OVRFLW"                  ,	18,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_UNDFLW"                  ,	19,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_ANULL"                   ,	20,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_INULL"                   ,	21,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REQ_BADFIL"                  ,	22,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	182,	"RAZ",	1,	1,	0,	0},
+	{"SPRT0_RST"                   ,	24,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_RST"                   ,	25,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_63"              ,	26,	38,	182,	"RAZ",	1,	1,	0,	0},
+	{"SINFO"                       ,	0,	6,	183,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	183,	"RAZ",	1,	1,	0,	0},
+	{"IINFO"                       ,	8,	6,	183,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	183,	"RAZ",	1,	1,	0,	0},
+	{"PKTERR"                      ,	0,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	184,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	185,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	185,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	186,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	186,	"RAZ",	1,	1,	0,	0},
+	{"QERR"                        ,	0,	8,	187,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	187,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	188,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	188,	"RAZ",	1,	1,	0,	0},
+	{"QEN"                         ,	0,	8,	189,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_8_63"               ,	8,	56,	189,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	2,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	190,	"RAZ",	1,	1,	0,	0},
+	{"MRRS_LIM"                    ,	3,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPS"                         ,	4,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	190,	"RAZ",	1,	1,	0,	0},
+	{"MPS_LIM"                     ,	7,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOLR"                        ,	8,	6,	190,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_14_15"              ,	14,	2,	190,	"RAZ",	1,	1,	0,	0},
+	{"RD_MODE"                     ,	16,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	190,	"RAZ",	1,	1,	0,	0},
+	{"QLM_CFG"                     ,	20,	1,	190,	"RO",	1,	1,	0,	0},
+	{"RESERVED_21_23"              ,	21,	3,	190,	"RAZ",	1,	1,	0,	0},
+	{"HALT"                        ,	24,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	190,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	191,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	191,	"RO",	0,	1,	0ull,	0},
+	{"REQQ"                        ,	0,	3,	192,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	192,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	4,	1,	192,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	192,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	8,	1,	192,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	192,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	193,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ_OFF"                     ,	18,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RET_OFF"                     ,	19,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE_EN"                     ,	20,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	194,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	195,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	195,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	195,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	196,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	196,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	197,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	197,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	197,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	198,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	198,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	199,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL0TH"                     ,	28,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL1TH"                     ,	29,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL2TH"                     ,	30,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL3TH"                     ,	31,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL4TH"                     ,	32,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL5TH"                     ,	33,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL6TH"                     ,	34,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POOL7TH"                     ,	35,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE0"                       ,	36,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE1"                       ,	37,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE2"                       ,	38,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE3"                       ,	39,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE4"                       ,	40,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE5"                       ,	41,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE6"                       ,	42,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FREE7"                       ,	43,	1,	200,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	200,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	32,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	201,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	29,	202,	"R/W",	0,	0,	536870911ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	202,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	203,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	204,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	204,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	205,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	205,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	205,	"RO",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	206,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	206,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	206,	"RO",	0,	0,	0ull,	7ull},
+	{"THRESH"                      ,	0,	32,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	208,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	208,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	208,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	25,	209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	209,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	210,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	211,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	211,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	211,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	211,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	211,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	212,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	212,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	212,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	1,	212,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	212,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	4,	212,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	212,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	213,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	213,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	214,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	214,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	214,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	214,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	215,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	215,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	215,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	215,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	215,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	215,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	215,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	215,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	215,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	215,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	216,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	217,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	218,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	219,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	220,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	221,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	222,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	222,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	223,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	223,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	223,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	224,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	224,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	225,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	225,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	225,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	225,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	226,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	226,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	226,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	226,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	226,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	226,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	226,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	226,	"RAZ",	1,	1,	0,	0},
+	{"PTP_MODE"                    ,	12,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	226,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	227,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	227,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	228,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	228,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	228,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	228,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	228,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	229,	"R/W1C",	0,	1,	0ull,	0},
+	{"CAREXT"                      ,	1,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	229,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	229,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	229,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	229,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	229,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	230,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	230,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	231,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	231,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	232,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	233,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	233,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	234,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	234,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	235,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	235,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	236,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	236,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	237,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	237,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	238,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	238,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	239,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	239,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	240,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	240,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	241,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	241,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	242,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	242,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	243,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	243,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	244,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	244,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	245,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	245,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	246,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	246,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	246,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	247,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	247,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	248,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	248,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	249,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	249,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	249,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	249,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	249,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	250,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	251,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	251,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	0,	1,	252,	"R/W",	0,	1,	0ull,	0},
+	{"START_BIST"                  ,	1,	1,	252,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	252,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	253,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	253,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	254,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	254,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	254,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	254,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	254,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	255,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	255,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	256,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	256,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	257,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	257,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	258,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	258,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	258,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	259,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	259,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	260,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	260,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	261,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	261,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	262,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	262,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	262,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	263,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	263,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	264,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	264,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	265,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	265,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	266,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	266,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	267,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	268,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	269,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	269,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	270,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	271,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	272,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	272,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	273,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	273,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	274,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	274,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	275,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	275,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	276,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	276,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	277,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	278,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	278,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	279,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	280,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	280,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	281,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	281,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	282,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	282,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	283,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	283,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	284,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	284,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	284,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	285,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTP_LOST"                    ,	20,	4,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	286,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	287,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	287,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	288,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	288,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	289,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	289,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	290,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	290,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	291,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	291,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	292,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	292,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	293,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	293,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	293,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	293,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	294,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	294,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCE_SEL"                   ,	15,	2,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	295,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	296,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	296,	"RAZ",	1,	1,	0,	0},
+	{"LANE_SEL"                    ,	0,	2,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIV"                         ,	2,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	297,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	298,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	298,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	299,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	299,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	300,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	301,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	301,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IOCFIF"                      ,	18,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RSDFIF"                      ,	19,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IORFIF"                      ,	20,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"XMCFIF"                      ,	21,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"XMDFIF"                      ,	22,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	302,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	303,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	303,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"XMC_PER"                     ,	6,	4,	303,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	303,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	304,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	305,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	305,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	305,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	306,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	307,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	307,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	307,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	307,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	307,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	308,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	308,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	308,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	308,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	308,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	309,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	310,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	311,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	312,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	312,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	313,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	314,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	315,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	315,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	315,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	316,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	316,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	316,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	317,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	317,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	317,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	318,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	319,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	320,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	321,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	322,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	322,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	322,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	323,	"RO",	0,	1,	0ull,	0},
+	{"VPORT"                       ,	6,	6,	323,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	323,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	324,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	324,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	324,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	324,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	325,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	326,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	327,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	328,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	44,	329,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	329,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	331,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKEN"                       ,	15,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RST_DONE"                    ,	16,	1,	331,	"RO",	0,	0,	1ull,	0ull},
+	{"USE_SOP"                     ,	17,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	331,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	332,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	333,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	334,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	334,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	335,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	335,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	336,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	336,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	337,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	338,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	339,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	340,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	340,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	341,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	342,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	342,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	343,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	343,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	345,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	346,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	346,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	346,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	346,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	346,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	347,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	347,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	347,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_44_63"              ,	44,	20,	347,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	348,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	349,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	349,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	349,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	349,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	349,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	349,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	350,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	350,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	351,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	352,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	352,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	352,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	8,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	353,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	354,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	354,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	354,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	354,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	354,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	355,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	355,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	355,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	356,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	356,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	356,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	356,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	357,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	357,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	357,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	358,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	358,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	359,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	359,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	360,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	361,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	362,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	363,	"RAZ",	1,	1,	0,	0},
+	{"DISABLE"                     ,	0,	1,	364,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	364,	"RAZ",	1,	1,	0,	0},
+	{"MAXDRAM"                     ,	4,	4,	364,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_8_63"               ,	8,	56,	364,	"RAZ",	1,	1,	0,	0},
+	{"TDFFL"                       ,	0,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"VRTFL"                       ,	4,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"DUTRESFL"                    ,	8,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"IOCDATFL"                    ,	12,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	365,	"RAZ",	1,	1,	0,	0},
+	{"IOCCMDFL"                    ,	16,	1,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	365,	"RAZ",	1,	1,	0,	0},
+	{"DUTFL"                       ,	32,	6,	365,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	365,	"RAZ",	1,	1,	0,	0},
+	{"VBFFL"                       ,	0,	4,	366,	"RO",	1,	0,	0,	0ull},
+	{"RDFFL"                       ,	4,	1,	366,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_61"               ,	5,	57,	366,	"RAZ",	1,	1,	0,	0},
+	{"CLEAR_BIST"                  ,	62,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	63,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFL"                       ,	0,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"FBFFL"                       ,	8,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"SBFFL"                       ,	16,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"FBFRSPFL"                    ,	24,	8,	367,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	367,	"RAZ",	1,	1,	0,	0},
+	{"TAGFL"                       ,	0,	16,	368,	"RO",	1,	0,	0,	0ull},
+	{"LRUFL"                       ,	16,	1,	368,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	368,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	369,	"R/W",	1,	1,	0,	0},
+	{"DISIDXALIAS"                 ,	0,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISECC"                      ,	1,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"VAB_THRESH"                  ,	2,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"EF_CNT"                      ,	6,	7,	370,	"R/W",	0,	0,	0ull,	4ull},
+	{"EF_ENA"                      ,	13,	1,	370,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMC_ARB_MODE"                ,	14,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSP_ARB_MODE"                ,	15,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXLFB"                      ,	16,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXVAB"                      ,	20,	4,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCCLK"                     ,	24,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFDBE"                     ,	25,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2DFSBE"                     ,	26,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISSTGL2I"                   ,	27,	1,	370,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	370,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	0,	1,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_9"                ,	1,	9,	371,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	10,	28,	371,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	371,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	372,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	4,	17,	372,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	372,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	10,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	373,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_6"                ,	2,	5,	373,	"RAZ",	1,	1,	0,	0},
+	{"WAYIDX"                      ,	7,	14,	373,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_21_49"              ,	21,	29,	373,	"RAZ",	1,	1,	0,	0},
+	{"SYN"                         ,	50,	6,	373,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_60"              ,	56,	5,	373,	"RAZ",	1,	1,	0,	0},
+	{"NOWAY"                       ,	61,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE"                         ,	62,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	63,	1,	373,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TYPE"                        ,	0,	2,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_49"               ,	2,	48,	374,	"RAZ",	1,	1,	0,	0},
+	{"VSYN"                        ,	50,	10,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"VSBE"                        ,	60,	1,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"VDBE"                        ,	61,	1,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	374,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	38,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_47"              ,	38,	10,	375,	"RAZ",	1,	1,	0,	0},
+	{"SID"                         ,	48,	4,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_57"              ,	52,	6,	375,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	58,	6,	375,	"RO",	0,	1,	0ull,	0},
+	{"HOLERD"                      ,	0,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"HOLEWR"                      ,	1,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTWR"                       ,	2,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTIDRNG"                    ,	3,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTADRNG"                    ,	4,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"VRTPE"                       ,	5,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGWR"                       ,	6,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"BIGRD"                       ,	7,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	376,	"RAZ",	1,	1,	0,	0},
+	{"HOLERD"                      ,	0,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HOLEWR"                      ,	1,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTWR"                       ,	2,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTIDRNG"                    ,	3,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTADRNG"                    ,	4,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"VRTPE"                       ,	5,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGWR"                       ,	6,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BIGRD"                       ,	7,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	377,	"RAZ",	1,	1,	0,	0},
+	{"TAD0"                        ,	16,	1,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	377,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	378,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	379,	"R/W",	0,	1,	0ull,	0},
+	{"LVL"                         ,	0,	2,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	380,	"RAZ",	1,	1,	0,	0},
+	{"DWBLVL"                      ,	4,	2,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	380,	"RAZ",	1,	1,	0,	0},
+	{"LVL"                         ,	0,	2,	381,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	381,	"RAZ",	1,	1,	0,	0},
+	{"WGT0"                        ,	0,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT1"                        ,	8,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT2"                        ,	16,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"WGT3"                        ,	24,	8,	382,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	382,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	383,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	384,	"R/W",	0,	1,	0ull,	0},
+	{"OW0ECC"                      ,	0,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW1ECC"                      ,	16,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW2ECC"                      ,	32,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW3ECC"                      ,	48,	10,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"OW4ECC"                      ,	0,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW5ECC"                      ,	16,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_31"              ,	26,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW6ECC"                      ,	32,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"OW7ECC"                      ,	48,	10,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	386,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"WRDISLMC"                    ,	8,	1,	387,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	387,	"RAZ",	1,	1,	0,	0},
+	{"L2DSBE"                      ,	0,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"L2DDBE"                      ,	1,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGSBE"                      ,	2,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"TAGDBE"                      ,	3,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFSBE"                      ,	4,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"VBFDBE"                      ,	5,	1,	388,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"NOWAY"                       ,	6,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDDISLMC"                    ,	7,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WRDISLMC"                    ,	8,	1,	388,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	388,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	389,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	390,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	391,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	64,	392,	"R/W",	0,	1,	0ull,	0},
+	{"CNT0SEL"                     ,	0,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT1SEL"                     ,	8,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT2SEL"                     ,	16,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"CNT3SEL"                     ,	24,	8,	393,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	393,	"RAZ",	1,	1,	0,	0},
+	{"LOCK"                        ,	0,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIRTY"                       ,	1,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	2,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE"                         ,	3,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_16"               ,	4,	13,	394,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	17,	19,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	394,	"RAZ",	1,	1,	0,	0},
+	{"ECC"                         ,	40,	6,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_63"              ,	46,	18,	394,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	395,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MASK"                        ,	0,	1,	396,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	396,	"RAZ",	1,	1,	0,	0},
+	{"DWB"                         ,	0,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	1,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	397,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	6,	398,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	398,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	399,	"RAZ",	1,	1,	0,	0},
+	{"DWBID"                       ,	8,	6,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	399,	"RAZ",	1,	1,	0,	0},
+	{"ID"                          ,	0,	6,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	400,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	401,	"R/W",	0,	0,	0ull,	1ull},
+	{"NUMID"                       ,	1,	3,	401,	"R/W",	0,	0,	5ull,	5ull},
+	{"MEMSZ"                       ,	4,	3,	401,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_7_7"                ,	7,	1,	401,	"RAZ",	1,	1,	0,	0},
+	{"OOBERR"                      ,	8,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	401,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	32,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	32,	4,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	402,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	403,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	404,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	64,	405,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	38,	406,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_38_56"              ,	38,	19,	406,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	57,	6,	406,	"R/W",	1,	1,	0,	0},
+	{"INUSE"                       ,	63,	1,	406,	"RO",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	0,	64,	407,	"R/W",	0,	1,	0ull,	0},
+	{"PRBS"                        ,	0,	32,	408,	"R/W",	1,	1,	0,	0},
+	{"PROG"                        ,	32,	8,	408,	"R/W",	1,	1,	0,	0},
+	{"SEL"                         ,	40,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"EN"                          ,	41,	1,	408,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	408,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	409,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	410,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	410,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	411,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	8,	412,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	412,	"R/W",	1,	1,	0,	0},
+	{"CKE_MASK"                    ,	0,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"CS0_N_MASK"                  ,	2,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"CS1_N_MASK"                  ,	4,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"ODT0_MASK"                   ,	6,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"ODT1_MASK"                   ,	8,	2,	413,	"R/W",	1,	1,	0,	0},
+	{"RAS_N_MASK"                  ,	10,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"CAS_N_MASK"                  ,	11,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"WE_N_MASK"                   ,	12,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"BA_MASK"                     ,	13,	3,	413,	"R/W",	1,	1,	0,	0},
+	{"A_MASK"                      ,	16,	16,	413,	"R/W",	1,	1,	0,	0},
+	{"RESET_N_MASK"                ,	32,	1,	413,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_33_63"              ,	33,	31,	413,	"R/W",	1,	1,	0,	0},
+	{"DQX_CTL"                     ,	0,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"CK_CTL"                      ,	4,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"CMD_CTL"                     ,	8,	4,	414,	"R/W",	0,	1,	4ull,	0},
+	{"RODT_CTL"                    ,	12,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"NTUNE"                       ,	16,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"PTUNE"                       ,	20,	4,	414,	"R/W",	0,	1,	0ull,	0},
+	{"BYP"                         ,	24,	1,	414,	"R/W",	0,	1,	0ull,	0},
+	{"M180"                        ,	25,	1,	414,	"R/W",	0,	1,	0ull,	0},
+	{"DDR__NTUNE"                  ,	26,	4,	414,	"RO",	1,	1,	0,	0},
+	{"DDR__PTUNE"                  ,	30,	4,	414,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	414,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	415,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	415,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	415,	"R/W",	0,	1,	5ull,	0},
+	{"IDLEPOWER"                   ,	9,	3,	415,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	12,	4,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	16,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESET"                       ,	17,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"REF_ZQCS_INT"                ,	18,	19,	415,	"R/W",	1,	1,	0,	0},
+	{"SEQUENCE"                    ,	37,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"EARLY_DQX"                   ,	40,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"SREF_WITH_DLL"               ,	41,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RANK_ENA"                    ,	42,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RANKMASK"                    ,	43,	4,	415,	"R/W",	0,	1,	0ull,	0},
+	{"MIRRMASK"                    ,	47,	4,	415,	"R/W",	0,	1,	0ull,	0},
+	{"INIT_STATUS"                 ,	51,	4,	415,	"R/W1",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R0"          ,	55,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D0_R1"          ,	56,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R0"          ,	57,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"EARLY_UNLOAD_D1_R1"          ,	58,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	415,	"RAZ",	1,	1,	0,	0},
+	{"RDIMM_ENA"                   ,	0,	1,	416,	"R/W",	0,	1,	0ull,	0},
+	{"BWCNT"                       ,	1,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	2,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"POCAS"                       ,	3,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH2"                      ,	4,	2,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"THROTTLE_RD"                 ,	6,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"THROTTLE_WR"                 ,	7,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_RD"                  ,	8,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_WR"                  ,	9,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"ELEV_PRIO_DIS"               ,	10,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXM_WRITE_EN"                ,	11,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	12,	4,	416,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	16,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"AUTO_DCLKDIS"                ,	17,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_ZQCS_DIS"                ,	18,	1,	416,	"R/W",	0,	0,	1ull,	0ull},
+	{"EXT_ZQCS_DIS"                ,	19,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	20,	2,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"WODT_BPRCH"                  ,	22,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_BPRCH"                  ,	23,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	416,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT"                     ,	0,	64,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"CLKF"                        ,	0,	7,	418,	"R/W",	0,	1,	48ull,	0},
+	{"RESET_N"                     ,	7,	1,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPB"                         ,	8,	3,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"CPS"                         ,	11,	3,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIFFAMP"                     ,	14,	4,	418,	"R/W",	0,	0,	0ull,	1ull},
+	{"DDR_PS_EN"                   ,	18,	3,	418,	"R/W",	0,	1,	2ull,	0},
+	{"DDR_DIV_RESET"               ,	21,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
+	{"DFM_PS_EN"                   ,	22,	3,	418,	"R/W",	0,	1,	2ull,	0},
+	{"DFM_DIV_RESET"               ,	25,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
+	{"JTG_TEST_MODE"               ,	26,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	418,	"RAZ",	1,	1,	0,	0},
+	{"RC0"                         ,	0,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC1"                         ,	4,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC2"                         ,	8,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC3"                         ,	12,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC4"                         ,	16,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC5"                         ,	20,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC6"                         ,	24,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC7"                         ,	28,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC8"                         ,	32,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC9"                         ,	36,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC10"                        ,	40,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC11"                        ,	44,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC12"                        ,	48,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC13"                        ,	52,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC14"                        ,	56,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RC15"                        ,	60,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIMM0_WMASK"                 ,	0,	16,	420,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"DIMM1_WMASK"                 ,	16,	16,	420,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"TCWS"                        ,	32,	13,	420,	"R/W",	0,	0,	1248ull,	1248ull},
+	{"PARITY"                      ,	45,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	420,	"RAZ",	1,	1,	0,	0},
+	{"BYP_SETTING"                 ,	0,	8,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYP_SEL"                     ,	8,	4,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"QUAD_DLL_ENA"                ,	12,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	13,	1,	421,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLL_BRINGUP"                 ,	14,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	421,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	6,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"BYTE_SEL"                    ,	6,	4,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE_SEL"                    ,	10,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOAD_OFFSET"                 ,	12,	1,	422,	"WR0",	0,	0,	0ull,	0ull},
+	{"OFFSET_ENA"                  ,	13,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYTE_SEL"              ,	14,	4,	422,	"R/W",	0,	0,	1ull,	1ull},
+	{"DLL_MODE"                    ,	18,	1,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINE_TUNE_MODE"              ,	19,	1,	422,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL90_SETTING"               ,	20,	8,	422,	"RO",	1,	1,	0,	0},
+	{"DLL_FAST"                    ,	28,	1,	422,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	422,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	423,	"RAZ",	1,	1,	0,	0},
+	{"ROW_LSB"                     ,	16,	3,	423,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_19_63"              ,	19,	45,	423,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	424,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	14,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	14,	16,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	30,	3,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	33,	1,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	34,	2,	425,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	425,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT"                      ,	0,	64,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"NXM_WR_ERR"                  ,	0,	1,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SEC_ERR"                     ,	1,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	5,	4,	427,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	427,	"RAZ",	1,	1,	0,	0},
+	{"INTR_NXM_WR_ENA"             ,	0,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_SEC_ENA"                ,	1,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	2,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	428,	"RAZ",	1,	1,	0,	0},
+	{"CWL"                         ,	0,	3,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPRLOC"                      ,	3,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPR"                         ,	5,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL"                         ,	6,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"AL"                          ,	7,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"WLEV"                        ,	9,	1,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"TDQS"                        ,	10,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOFF"                        ,	11,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"BL"                          ,	12,	2,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	14,	4,	429,	"R/W",	0,	0,	2ull,	2ull},
+	{"RBT"                         ,	18,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"TM"                          ,	19,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLR"                        ,	20,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRP"                         ,	21,	3,	429,	"R/W",	0,	0,	1ull,	1ull},
+	{"PPD"                         ,	24,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	429,	"RAZ",	1,	1,	0,	0},
+	{"PASR_00"                     ,	0,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_00"                      ,	3,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_00"                      ,	4,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_00"                   ,	5,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_00"                      ,	7,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_00"                  ,	9,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_01"                     ,	12,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_01"                      ,	15,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_01"                      ,	16,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_01"                   ,	17,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_01"                      ,	19,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_01"                  ,	21,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_10"                     ,	24,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_10"                      ,	27,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_10"                      ,	28,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_10"                   ,	29,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_10"                      ,	31,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_10"                  ,	33,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"PASR_11"                     ,	36,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASR_11"                      ,	39,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRT_11"                      ,	40,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_WR_11"                   ,	41,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC_11"                      ,	43,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTT_NOM_11"                  ,	45,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	430,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R0"               ,	8,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D0_R1"               ,	12,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R0"               ,	16,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D1_R1"               ,	20,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R0"               ,	24,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D2_R1"               ,	28,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R0"               ,	32,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"MEM_MSB_D3_R1"               ,	36,	4,	431,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	431,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT"                      ,	0,	64,	432,	"RO",	0,	0,	0ull,	0ull},
+	{"TS_STAGGER"                  ,	0,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK_POS"                ,	1,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LOOPBACK"                    ,	2,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT0"                  ,	3,	4,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE0"                    ,	7,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_DLYOUT1"                  ,	8,	4,	433,	"R/W",	0,	1,	0ull,	0},
+	{"CK_TUNE1"                    ,	12,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"LV_MODE"                     ,	13,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RX_ALWAYS_ON"                ,	14,	1,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	433,	"RAZ",	1,	1,	0,	0},
+	{"DDR3RST"                     ,	0,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PWARM"                   ,	1,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSOFT"                   ,	2,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR3PSV"                     ,	3,	1,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	434,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	435,	"R/W",	0,	1,	0ull,	0},
+	{"OFFSET"                      ,	4,	4,	435,	"R/W",	0,	0,	2ull,	2ull},
+	{"OFFSET_EN"                   ,	8,	1,	435,	"R/W",	0,	0,	1ull,	1ull},
+	{"OR_DIS"                      ,	9,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	10,	8,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_0"              ,	18,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_1"              ,	19,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_2"              ,	20,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"DELAY_UNLOAD_3"              ,	21,	1,	435,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	435,	"RAZ",	1,	1,	0,	0},
+	{"BITMASK"                     ,	0,	64,	436,	"RO",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	6,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	12,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	18,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	24,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	30,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	36,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	42,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	48,	6,	437,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	54,	2,	437,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	437,	"RAZ",	1,	1,	0,	0},
+	{"RODT_D0_R0"                  ,	0,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D0_R1"                  ,	8,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R0"                  ,	16,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D1_R1"                  ,	24,	8,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RODT_D2_R0"                  ,	32,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D2_R1"                  ,	40,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R0"                  ,	48,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RODT_D3_R1"                  ,	56,	8,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_INIT"                    ,	0,	6,	439,	"R/W",	0,	1,	1ull,	0},
+	{"R2W_INIT"                    ,	6,	6,	439,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_INIT"                    ,	12,	6,	439,	"R/W",	0,	1,	9ull,	0},
+	{"W2W_INIT"                    ,	18,	6,	439,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	439,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XRANK_INIT"              ,	0,	6,	440,	"R/W",	0,	1,	3ull,	0},
+	{"R2W_XRANK_INIT"              ,	6,	6,	440,	"R/W",	0,	1,	6ull,	0},
+	{"W2R_XRANK_INIT"              ,	12,	6,	440,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XRANK_INIT"              ,	18,	6,	440,	"R/W",	0,	1,	5ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	440,	"RAZ",	1,	1,	0,	0},
+	{"R2R_XDIMM_INIT"              ,	0,	6,	441,	"R/W",	0,	1,	4ull,	0},
+	{"R2W_XDIMM_INIT"              ,	6,	6,	441,	"R/W",	0,	1,	7ull,	0},
+	{"W2R_XDIMM_INIT"              ,	12,	6,	441,	"R/W",	0,	1,	4ull,	0},
+	{"W2W_XDIMM_INIT"              ,	18,	6,	441,	"R/W",	0,	1,	6ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	441,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_9"                ,	0,	10,	442,	"RAZ",	1,	1,	0,	0},
+	{"TZQCS"                       ,	10,	4,	442,	"R/W",	0,	0,	4ull,	4ull},
+	{"TCKE"                        ,	14,	4,	442,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPR"                        ,	18,	4,	442,	"R/W",	0,	0,	5ull,	5ull},
+	{"TMRD"                        ,	22,	4,	442,	"R/W",	0,	0,	4ull,	4ull},
+	{"TMOD"                        ,	26,	4,	442,	"R/W",	0,	0,	12ull,	12ull},
+	{"TDLLK"                       ,	30,	4,	442,	"R/W",	0,	0,	2ull,	2ull},
+	{"TZQINIT"                     ,	34,	4,	442,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	38,	4,	442,	"R/W",	0,	0,	6ull,	6ull},
+	{"TCKSRE"                      ,	42,	4,	442,	"R/W",	0,	0,	5ull,	5ull},
+	{"TRP_EXT"                     ,	46,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	442,	"RAZ",	1,	1,	0,	0},
+	{"TMPRR"                       ,	0,	4,	443,	"R/W",	0,	0,	1ull,	1ull},
+	{"TRAS"                        ,	4,	5,	443,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	9,	4,	443,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	13,	4,	443,	"R/W",	0,	0,	2ull,	3ull},
+	{"TRFC"                        ,	17,	5,	443,	"R/W",	0,	0,	6ull,	7ull},
+	{"TRRD"                        ,	22,	3,	443,	"R/W",	0,	0,	2ull,	2ull},
+	{"TXP"                         ,	25,	3,	443,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWLMRD"                      ,	28,	4,	443,	"R/W",	0,	0,	10ull,	10ull},
+	{"TWLDQSEN"                    ,	32,	4,	443,	"R/W",	0,	0,	7ull,	7ull},
+	{"TFAW"                        ,	36,	5,	443,	"R/W",	0,	0,	0ull,	9ull},
+	{"TXPDLL"                      ,	41,	5,	443,	"R/W",	0,	0,	10ull,	10ull},
+	{"TRAS_EXT"                    ,	46,	1,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	443,	"RAZ",	1,	1,	0,	0},
+	{"TRESET"                      ,	0,	1,	444,	"R/W",	0,	1,	1ull,	0},
+	{"RCLK_CNT"                    ,	1,	32,	444,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	444,	"RAZ",	1,	1,	0,	0},
+	{"RING_CNT"                    ,	0,	32,	445,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	445,	"RAZ",	1,	1,	0,	0},
+	{"LANEMASK"                    ,	0,	9,	446,	"R/W",	0,	1,	0ull,	0},
+	{"SSET"                        ,	9,	1,	446,	"R/W",	0,	1,	0ull,	0},
+	{"OR_DIS"                      ,	10,	1,	446,	"R/W",	0,	1,	0ull,	0},
+	{"BITMASK"                     ,	11,	8,	446,	"R/W",	0,	1,	0ull,	0},
+	{"RTT_NOM"                     ,	19,	3,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	446,	"RAZ",	1,	1,	0,	0},
+	{"BYTE"                        ,	0,	4,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	4,	8,	447,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	447,	"RAZ",	1,	1,	0,	0},
+	{"BYTE0"                       ,	0,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	5,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	10,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	15,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	20,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	25,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	30,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	35,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	40,	5,	448,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	45,	2,	448,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_63"              ,	47,	17,	448,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	449,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D0_R1"                  ,	8,	8,	449,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R0"                  ,	16,	8,	449,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D1_R1"                  ,	24,	8,	449,	"R/W",	0,	1,	255ull,	0},
+	{"WODT_D2_R0"                  ,	32,	8,	449,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D2_R1"                  ,	40,	8,	449,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R0"                  ,	48,	8,	449,	"R/W",	0,	0,	255ull,	0ull},
+	{"WODT_D3_R1"                  ,	56,	8,	449,	"R/W",	0,	0,	255ull,	0ull},
+	{"STAT"                        ,	0,	9,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	450,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	451,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	6,	6,	451,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	451,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	452,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	452,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	452,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	452,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	453,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	453,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	453,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	454,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	455,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	455,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	455,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	456,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	456,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	456,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	457,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	457,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	457,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	458,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	458,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	458,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	459,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	459,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	459,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	459,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	459,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	460,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	461,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	461,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	461,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	461,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	461,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	461,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	461,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	461,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	461,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	462,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	462,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	462,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	462,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	462,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	462,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	462,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	463,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	463,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	463,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	463,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	464,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	464,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	464,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	464,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	464,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	464,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	465,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	466,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	467,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	467,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	6,	468,	"RO",	1,	1,	0,	0},
+	{"RESERVED_6_15"               ,	6,	10,	468,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	468,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_25"              ,	24,	2,	468,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	468,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	468,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	468,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_31"              ,	29,	3,	468,	"RO",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	468,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	468,	"RO",	1,	1,	0,	0},
+	{"DORM_CRYPTO"                 ,	34,	1,	468,	"RO",	1,	1,	0,	0},
+	{"RESERVED_35_63"              ,	35,	29,	468,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	469,	"RAZ",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	469,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	469,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	469,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	469,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	469,	"RO",	1,	1,	0,	0},
+	{"ZIP_INFO"                    ,	29,	2,	469,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_31"              ,	31,	1,	469,	"RAZ",	1,	1,	0,	0},
+	{"L2C_CRIP"                    ,	32,	3,	469,	"RO",	1,	1,	0,	0},
+	{"PLL_HALF_DIS"                ,	35,	1,	469,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_MAN"                ,	36,	1,	469,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK_RSV"                ,	37,	1,	469,	"RO",	1,	1,	0,	0},
+	{"EMA"                         ,	38,	2,	469,	"RO",	1,	1,	0,	0},
+	{"RESERVED_40_40"              ,	40,	1,	469,	"RAZ",	1,	1,	0,	0},
+	{"DFA_INFO_CLM"                ,	41,	4,	469,	"RO",	1,	1,	0,	0},
+	{"DFA_INFO_DTE"                ,	45,	3,	469,	"RO",	1,	1,	0,	0},
+	{"PLL_CTL"                     ,	48,	10,	469,	"RO",	1,	1,	0,	0},
+	{"RESERVED_58_63"              ,	58,	6,	469,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	470,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_3_3"                ,	3,	1,	470,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	470,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_7_63"               ,	7,	57,	470,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	471,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	472,	"RAZ",	0,	1,	0ull,	0},
+	{"PNR_COUT_SEL"                ,	2,	2,	472,	"R/W",	0,	1,	0ull,	0},
+	{"PNR_COUT_RST"                ,	4,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_SEL"                  ,	5,	2,	472,	"R/W",	0,	1,	0ull,	0},
+	{"C_COUT_RST"                  ,	7,	1,	472,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	472,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	473,	"R/W",	1,	1,	0,	0},
+	{"SOFT"                        ,	1,	1,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	473,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	6,	474,	"R/W",	0,	1,	1ull,	0},
+	{"SCLK_HI"                     ,	6,	15,	474,	"R/W",	0,	1,	5000ull,	0},
+	{"SCLK_LO"                     ,	21,	4,	474,	"R/W",	0,	1,	1ull,	0},
+	{"OUT"                         ,	25,	7,	474,	"R/W",	0,	1,	1ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	474,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC_PIN"                    ,	33,	1,	474,	"RO",	0,	0,	0ull,	0ull},
+	{"VGATE_PIN"                   ,	34,	1,	474,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	474,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	475,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	475,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	475,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	475,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	475,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	475,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	10,	476,	"R/W",	0,	1,	999ull,	0},
+	{"SDH"                         ,	10,	4,	476,	"R/W",	0,	1,	0ull,	0},
+	{"PRH"                         ,	14,	4,	476,	"R/W",	0,	1,	6ull,	0},
+	{"FSH"                         ,	18,	4,	476,	"R/W",	0,	1,	15ull,	0},
+	{"SCH"                         ,	22,	4,	476,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	476,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	18,	477,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	18,	18,	477,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	36,	18,	477,	"RO",	0,	0,	0ull,	0ull},
+	{"TOO_MANY"                    ,	54,	1,	477,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	477,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR3"                     ,	0,	18,	478,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR4"                     ,	18,	18,	478,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR5"                     ,	36,	18,	478,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	478,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR6"                     ,	0,	18,	479,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	479,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	480,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR1"                     ,	14,	14,	480,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR2"                     ,	28,	14,	480,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_42_63"              ,	42,	22,	480,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	481,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	481,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	4,	482,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	482,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	483,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	6,	6,	483,	"R/W",	0,	1,	19ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	483,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	484,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	484,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	484,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	485,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	485,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	486,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	486,	"RAZ",	1,	1,	0,	0},
+	{"PTP_EN"                      ,	0,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_EN"                  ,	1,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_CLK_IN"                  ,	2,	6,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EN"                    ,	8,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_EDGE"                  ,	9,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSTMP_IN"                    ,	10,	6,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EN"                    ,	16,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_EDGE"                  ,	17,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"EVCNT_IN"                    ,	18,	6,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	487,	"RAZ",	1,	1,	0,	0},
+	{"FRNANOSEC"                   ,	0,	32,	488,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	32,	32,	488,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	489,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRNANOSEC"                   ,	0,	32,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	490,	"RAZ",	1,	1,	0,	0},
+	{"CNTR"                        ,	0,	64,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"NANOSEC"                     ,	0,	64,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"RBOOT_PIN"                   ,	0,	1,	493,	"RO",	1,	1,	0,	0},
+	{"RBOOT"                       ,	1,	1,	493,	"R/W",	1,	1,	0,	0},
+	{"LBOOT"                       ,	2,	10,	493,	"R/W1C",	1,	1,	0,	0},
+	{"QLM0_SPD"                    ,	12,	4,	493,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	16,	4,	493,	"RO",	1,	1,	0,	0},
+	{"QLM2_SPD"                    ,	20,	4,	493,	"RO",	1,	1,	0,	0},
+	{"PNR_MUL"                     ,	24,	6,	493,	"RO",	1,	1,	0,	0},
+	{"C_MUL"                       ,	30,	6,	493,	"RO",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	493,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_CLR_BIST"               ,	0,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"WARM_CLR_BIST"               ,	1,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNTL_CLR_BIST"               ,	2,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_5"                ,	3,	3,	494,	"RAZ",	1,	1,	0,	0},
+	{"BIST_DELAY"                  ,	6,	58,	494,	"RO",	1,	1,	0,	0},
+	{"RST_VAL"                     ,	0,	1,	495,	"RO",	1,	1,	0,	0},
+	{"RST_CHIP"                    ,	1,	1,	495,	"R/W",	0,	1,	0ull,	0},
+	{"RST_RCV"                     ,	2,	1,	495,	"R/W",	1,	1,	0,	0},
+	{"RST_DRV"                     ,	3,	1,	495,	"R/W",	1,	1,	0,	0},
+	{"PRTMODE"                     ,	4,	2,	495,	"R/W",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	6,	1,	495,	"RO",	1,	1,	0,	0},
+	{"RST_LINK"                    ,	7,	1,	495,	"R/W",	1,	1,	0,	0},
+	{"RST_DONE"                    ,	8,	1,	495,	"RO",	1,	1,	0,	0},
+	{"PRST_LINK"                   ,	9,	1,	495,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	495,	"RAZ",	1,	1,	0,	0},
+	{"WARM_RST_DLY"                ,	0,	16,	496,	"R/W",	0,	1,	2047ull,	0},
+	{"SOFT_RST_DLY"                ,	16,	16,	496,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	496,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	497,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	497,	"RAZ",	1,	1,	0,	0},
+	{"RST_LINK0"                   ,	0,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"RST_LINK1"                   ,	1,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_7"                ,	2,	6,	498,	"RAZ",	1,	1,	0,	0},
+	{"PERST0"                      ,	8,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"PERST1"                      ,	9,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	498,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	499,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	499,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	499,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	499,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	499,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	499,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	499,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	499,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	500,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	500,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	500,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	500,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	500,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	500,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	501,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	501,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	501,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	502,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	502,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	502,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	503,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	504,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	505,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	505,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	506,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	506,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	506,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	506,	"RAZ",	1,	1,	0,	0},
+	{"TXTRIG"                      ,	4,	2,	506,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	506,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	506,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	507,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	507,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"PTIME"                       ,	7,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	508,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	509,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	509,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	509,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	509,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	510,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	510,	"RAZ",	1,	1,	0,	0},
+	{"BRK"                         ,	6,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	510,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	511,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	511,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	511,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	511,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	511,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	511,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	511,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	511,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	511,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	512,	"RAZ",	1,	1,	0,	0},
+	{"DCTS"                        ,	0,	1,	513,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	513,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	513,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	513,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	513,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	513,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	513,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	513,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	513,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	514,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	514,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	515,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	515,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	516,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	516,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	516,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	516,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	517,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	518,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	519,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	520,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	520,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	520,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	520,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	521,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	521,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	522,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	523,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	524,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	524,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	525,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	525,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	526,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	526,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	527,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	527,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	527,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	527,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	527,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	527,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"MRGDAT"                      ,	4,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"OPFDAT"                      ,	5,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	528,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	529,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	529,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"TS_THRESH"                   ,	8,	4,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	529,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSENA"                       ,	7,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	530,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	531,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	532,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	533,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	37,	533,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	40,	20,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	533,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	534,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	534,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	534,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	534,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TS"                          ,	7,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	535,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	536,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	537,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	538,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	37,	538,	"R/W",	0,	1,	0ull,	0},
+	{"OSIZE"                       ,	40,	20,	538,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	538,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	539,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	539,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	539,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	539,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	540,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	540,	"RAZ",	1,	1,	0,	0},
+	{"TSCNT"                       ,	0,	5,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	541,	"RAZ",	1,	1,	0,	0},
+	{"TSTOT"                       ,	8,	5,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	541,	"RAZ",	1,	1,	0,	0},
+	{"TSAVL"                       ,	16,	5,	541,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_21_63"              ,	21,	43,	541,	"RAZ",	1,	1,	0,	0},
+	{"TSTAMP"                      ,	0,	64,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	3,	543,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	543,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	543,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	543,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	544,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	545,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	545,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	546,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	546,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	546,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	547,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	547,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	548,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	549,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	549,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	549,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	549,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	549,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	549,	"R/W",	0,	0,	3ull,	3ull},
+	{"MB_DIS"                      ,	27,	1,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	549,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	550,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	550,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	550,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	550,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	550,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	550,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	550,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	550,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	551,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	551,	"RO/WRSL",	0,	0,	144ull,	144ull},
+	{"ISAE"                        ,	0,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	552,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	552,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	552,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	552,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	553,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	553,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	553,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	553,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	554,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	555,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	555,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	555,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	555,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	556,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	556,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	558,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	559,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	559,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	559,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	560,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	560,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	562,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	563,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	563,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	563,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	564,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	564,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_8"                ,	0,	9,	565,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	9,	23,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	566,	"WORSL",	0,	0,	511ull,	511ull},
+	{"CISP"                        ,	0,	32,	567,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	568,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	568,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	569,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	570,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	570,	"WORSL",	0,	0,	32767ull,	32767ull},
+	{"CP"                          ,	0,	8,	571,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	571,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	572,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	572,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	573,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	573,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	573,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	573,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	573,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	573,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	573,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	573,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	574,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	574,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	574,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	575,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	575,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	575,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	575,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	575,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	576,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	578,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	579,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	579,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	579,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	579,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	579,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	579,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	580,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	580,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	580,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	580,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	580,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	580,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	580,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	580,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	580,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	580,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	580,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	581,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	581,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	581,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	581,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	581,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	581,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	582,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"MLW"                         ,	4,	6,	582,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"ASLPMS"                      ,	10,	2,	582,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	582,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	582,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	582,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	582,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	582,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	582,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	582,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	582,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	583,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	583,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	583,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	583,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	583,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	583,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	583,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	584,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	585,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	585,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	586,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	586,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	586,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	587,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	588,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	589,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	589,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	589,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	590,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	591,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	592,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	592,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	593,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	593,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	593,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	593,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	594,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	594,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	594,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	595,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	595,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	595,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	595,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	596,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	596,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	596,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	597,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	597,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	597,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	597,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	598,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	598,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	598,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	598,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	599,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	600,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	603,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	603,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	604,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	605,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	605,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	605,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	606,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	606,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	606,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	606,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	606,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	607,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	607,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	607,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	607,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	607,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	607,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	607,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	608,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	609,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	609,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	609,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	609,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	609,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	609,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	610,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	610,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	610,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	611,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	611,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	611,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	614,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	615,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	615,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	615,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	616,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	617,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	618,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	620,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	620,	"RO/WRSL",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	620,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	620,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	620,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	620,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	620,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	621,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	621,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	621,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	621,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	621,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	622,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	622,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	622,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	622,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	622,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	623,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	623,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	623,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	623,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	624,	"RO/WRSL",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	624,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	624,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	624,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	625,	"RO/WRSL",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	625,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	625,	"RO/WRSL",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	625,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	626,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	626,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	626,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	629,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	629,	"R/W",	0,	0,	144ull,	144ull},
+	{"ISAE"                        ,	0,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	630,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	630,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	630,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	630,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	631,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	631,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	631,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	632,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	632,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	632,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	633,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	634,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	636,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	636,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	636,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	636,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	636,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	636,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	636,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	637,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	637,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	638,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	638,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	638,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	638,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	642,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	642,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	643,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	644,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	644,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	644,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	645,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	645,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	645,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	645,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	646,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	646,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	646,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	647,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	647,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	647,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	647,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	648,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	649,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	650,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	651,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	651,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	651,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	651,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	652,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	652,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	652,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	652,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	652,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	653,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	653,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	653,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	653,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	653,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	653,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	654,	"R/W",	0,	0,	2ull,	2ull},
+	{"MLW"                         ,	4,	6,	654,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	654,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	654,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	654,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	654,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	654,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	654,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	654,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	654,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	655,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	655,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	655,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	655,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	655,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	655,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	655,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	655,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	657,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	657,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	657,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	657,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	657,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	657,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	658,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	658,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	658,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	659,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	660,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	660,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	660,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	661,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	662,	"RAZ",	1,	1,	0,	0},
+	{"TLS"                         ,	0,	4,	663,	"R/W",	1,	0,	0,	2ull},
+	{"EC"                          ,	4,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"HASD"                        ,	5,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDE"                         ,	6,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"TM"                          ,	7,	3,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMC"                         ,	10,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSOS"                        ,	11,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDE"                         ,	12,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	663,	"RAZ",	1,	1,	0,	0},
+	{"CDL"                         ,	16,	1,	663,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	663,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	664,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	665,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	666,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	666,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	667,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	667,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	667,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	668,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	668,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	668,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	669,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	669,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	669,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	669,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	670,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	670,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	670,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	670,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	671,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	671,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	671,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	671,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	672,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	672,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	672,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	672,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	673,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	674,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	675,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	676,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	677,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	678,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	678,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	679,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	679,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	680,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	680,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	681,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	682,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	682,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	682,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	682,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	683,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	683,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	683,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	683,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	683,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	684,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	684,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	684,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	684,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	684,	"R/W",	0,	0,	15ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	684,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	684,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	685,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	686,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	686,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	686,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	686,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	686,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	686,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	687,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	687,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	687,	"R/W",	0,	0,	1ull,	1ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	688,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	691,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	692,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	693,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	693,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	693,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	694,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	695,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	697,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	697,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	697,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	697,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	697,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	697,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	697,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	698,	"R/W",	0,	0,	32ull,	32ull},
+	{"HEADER_CREDITS"              ,	12,	8,	698,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	698,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	698,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	698,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	699,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	699,	"R/W",	0,	0,	96ull,	96ull},
+	{"RESERVED_20_20"              ,	20,	1,	699,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	699,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	699,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	700,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	700,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	700,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	700,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	701,	"R/W",	0,	0,	136ull,	136ull},
+	{"RESERVED_14_15"              ,	14,	2,	701,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	701,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	701,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	702,	"R/W",	0,	0,	392ull,	392ull},
+	{"RESERVED_14_15"              ,	14,	2,	702,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	702,	"R/W",	0,	0,	102ull,	102ull},
+	{"RESERVED_26_31"              ,	26,	6,	702,	"RAZ",	1,	1,	0,	0},
+	{"N_FTS"                       ,	0,	8,	703,	"R/W",	0,	0,	128ull,	128ull},
+	{"LE"                          ,	8,	9,	703,	"R/W",	0,	0,	8ull,	8ull},
+	{"DSC"                         ,	17,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"CPYTS"                       ,	18,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTCRB"                       ,	19,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"S_D_E"                       ,	20,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	703,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	706,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	706,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	706,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	706,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	706,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	706,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	706,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	707,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	708,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	708,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	708,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	708,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	709,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	709,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	710,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	12,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	710,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	12,	1,	711,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	711,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	712,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	712,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	713,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	713,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	713,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	714,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	714,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	714,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	715,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	715,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	715,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	715,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	715,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	715,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	715,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	716,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	716,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	716,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	716,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	716,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	716,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	716,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	716,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	717,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	718,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	718,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	719,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	719,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	719,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	719,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	719,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	719,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	719,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	719,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	720,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	720,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	720,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	720,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	720,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	720,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	720,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	721,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	721,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	721,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	721,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	722,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	722,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	723,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	723,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	723,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	723,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	723,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	723,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	723,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	723,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	724,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	724,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	725,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	725,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	725,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	725,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	725,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	726,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	726,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	726,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	726,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	726,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	726,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	726,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	726,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	726,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	727,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	727,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	728,	"R/W",	0,	0,	0ull,	1ull},
+	{"DBG_SYNC_EN"                 ,	6,	1,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	728,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBG_SYNC"                    ,	6,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	729,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	730,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	730,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	731,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	731,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	731,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	731,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	732,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	732,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	732,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	732,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	732,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	733,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	733,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	734,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	734,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	734,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	734,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	734,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	734,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	735,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	735,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	735,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	735,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	735,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	735,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	735,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	736,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	737,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	737,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	737,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	737,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	737,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	738,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	738,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	16,	738,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	738,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	739,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	739,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR1_SIZ"                    ,	4,	3,	739,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_63"               ,	7,	57,	739,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	3,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	4,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	5,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	6,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	7,	1,	740,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	740,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	6,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	7,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	8,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	9,	1,	741,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	741,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	742,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	742,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	743,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	743,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	744,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	744,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"FAST_LM"                     ,	2,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	745,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	745,	"R/W",	0,	0,	0ull,	32ull},
+	{"RESERVED_32_33"              ,	32,	2,	745,	"RAZ",	1,	1,	0,	0},
+	{"PBUS"                        ,	34,	8,	745,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	42,	5,	745,	"RO",	1,	1,	0,	0},
+	{"AUTO_SD"                     ,	47,	1,	745,	"RO",	1,	1,	0,	0},
+	{"RESERVED_48_63"              ,	48,	16,	745,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	746,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	746,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	747,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	748,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	748,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	748,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	748,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	748,	"RO",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	749,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	749,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"SE"                          ,	1,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEI"                        ,	2,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"PMEM"                        ,	3,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B1"                       ,	4,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_B2"                       ,	5,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UP_BX"                       ,	6,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B1"                       ,	7,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_B2"                       ,	8,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"UN_BX"                       ,	9,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"EXC"                         ,	10,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDLK"                        ,	11,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_ER"                      ,	12,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS_DR"                      ,	13,	1,	750,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_14_63"              ,	14,	50,	750,	"RAZ",	1,	1,	0,	0},
+	{"AERI"                        ,	0,	1,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"SE"                          ,	1,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PMEI"                        ,	2,	1,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEM"                        ,	3,	1,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"UP_B1"                       ,	4,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_B2"                       ,	5,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UP_BX"                       ,	6,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B1"                       ,	7,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_B2"                       ,	8,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UN_BX"                       ,	9,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EXC"                         ,	10,	1,	751,	"RO",	0,	0,	0ull,	0ull},
+	{"RDLK"                        ,	11,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_ER"                      ,	12,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS_DR"                      ,	13,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	751,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	752,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	752,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	753,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_40"               ,	0,	41,	754,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	41,	23,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	755,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	755,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	756,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	756,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"SLI_P"                       ,	0,	8,	757,	"R/W",	0,	0,	128ull,	128ull},
+	{"SLI_NP"                      ,	8,	8,	757,	"R/W",	0,	0,	16ull,	16ull},
+	{"SLI_CPL"                     ,	16,	8,	757,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_P"                       ,	24,	8,	757,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEM_NP"                      ,	32,	8,	757,	"R/W",	0,	0,	16ull,	16ull},
+	{"PEM_CPL"                     ,	40,	8,	757,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	757,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	757,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	758,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	758,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	758,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	758,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	758,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	759,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	759,	"RAZ",	1,	1,	0,	0},
+	{"CLKEN"                       ,	0,	1,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	760,	"RAZ",	0,	1,	0ull,	0},
+	{"DPRT"                        ,	0,	16,	761,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	761,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	761,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	761,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	763,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	764,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	764,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	764,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	765,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	765,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	765,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	765,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	765,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	766,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	766,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	766,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	766,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	766,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	766,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"IHMSK_DIS"                   ,	27,	1,	766,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	766,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	767,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	767,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	767,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	767,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	767,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	767,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	768,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	768,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	769,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	769,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	770,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	770,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	771,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	771,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	771,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	771,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	771,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	771,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	771,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	771,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	771,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	772,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	772,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	773,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	773,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	774,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	774,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	775,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	775,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	775,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	775,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	776,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	777,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	777,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	778,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	779,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	779,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	780,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	781,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	781,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	782,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	782,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	783,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	783,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	784,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	784,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	785,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	785,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	786,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	786,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	787,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	787,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	788,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	788,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	789,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	789,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	790,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	790,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	791,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	791,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	792,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	793,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	793,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	794,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	794,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	794,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	795,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	795,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	795,	"RO",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	796,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	797,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	797,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	798,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	799,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	800,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	801,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	801,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	802,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	802,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	803,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	803,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	804,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	804,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	805,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	805,	"R/W",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	0,	32,	806,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	806,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	807,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	807,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	808,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	808,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	808,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	808,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	809,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	809,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	809,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	809,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	809,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	810,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	810,	"RAZ",	1,	1,	0,	0},
+	{"PTRS1"                       ,	32,	17,	810,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	810,	"RAZ",	1,	1,	0,	0},
+	{"MOD"                         ,	0,	3,	811,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	811,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	811,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	811,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	811,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	812,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	812,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	812,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	812,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	813,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	813,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	813,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	813,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	813,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	814,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	815,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	815,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	815,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	815,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	815,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	816,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	817,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	817,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	817,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	817,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	817,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	817,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	817,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	817,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	817,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	818,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	818,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	818,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR_3"                     ,	54,	1,	818,	"RO",	1,	0,	0,	0ull},
+	{"PTP"                         ,	55,	1,	818,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	818,	"RAZ",	1,	1,	0,	0},
+	{"QID_BASE"                    ,	0,	8,	819,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	819,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	819,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	819,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	819,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	819,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	819,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	819,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	819,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	820,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	820,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	820,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	820,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	820,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	820,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	821,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	821,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	8,	20,	821,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	821,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	821,	"RAZ",	1,	1,	0,	0},
+	{"PTRS3"                       ,	0,	17,	822,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	822,	"RAZ",	1,	1,	0,	0},
+	{"PTRS0"                       ,	32,	17,	822,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	822,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	823,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	823,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	823,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	823,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	823,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	823,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	823,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	824,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	824,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	824,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	824,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	824,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	825,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	825,	"RAZ",	1,	1,	0,	0},
+	{"RATE_PKT"                    ,	8,	24,	825,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	825,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	825,	"RAZ",	1,	1,	0,	0},
+	{"PID"                         ,	0,	6,	826,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	826,	"RAZ",	1,	1,	0,	0},
+	{"RATE_LIM"                    ,	8,	24,	826,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	826,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE"                       ,	0,	7,	827,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	827,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	827,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	827,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	827,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	827,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	827,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	827,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	827,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	828,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	828,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	828,	"RAZ",	1,	1,	0,	0},
+	{"QOS_MASK"                    ,	53,	8,	828,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	828,	"RAZ",	1,	1,	0,	0},
+	{"DAT_PTR"                     ,	0,	4,	829,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	829,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	829,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	829,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	829,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	829,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	13,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	830,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	831,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE10"                    ,	40,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE11"                    ,	44,	4,	835,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_48_63"              ,	48,	16,	835,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	12,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	836,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	837,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	837,	"RAZ",	1,	1,	0,	0},
+	{"ENA_PKO"                     ,	0,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	838,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	838,	"RAZ",	1,	1,	0,	0},
+	{"MODE0"                       ,	0,	3,	839,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	839,	"RAZ",	1,	1,	0,	0},
+	{"PARITY"                      ,	0,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	840,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	841,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	841,	"RAZ",	1,	1,	0,	0},
+	{"QID7"                        ,	0,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	842,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	842,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	843,	"RAZ",	1,	1,	0,	0},
+	{"WQE_WORD"                    ,	0,	4,	844,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_4_63"               ,	4,	60,	844,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	1,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	2,	1,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	3,	1,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	4,	4,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR"                         ,	8,	3,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	11,	1,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	845,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	6,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	845,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	846,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	846,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	847,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	847,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	847,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	847,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	847,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	847,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	847,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	847,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	847,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	847,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	847,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	848,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	848,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	848,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	849,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	849,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	850,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	850,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	851,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	851,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	852,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	852,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	853,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	853,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	11,	854,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	854,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	855,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	855,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	856,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	856,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	857,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	857,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	857,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	858,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	858,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	858,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	858,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	858,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	10,	859,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	859,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	10,	859,	"R/W",	0,	1,	1023ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	859,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	11,	859,	"RO",	0,	1,	1011ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	859,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	11,	859,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	859,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	11,	859,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_59_63"              ,	59,	5,	859,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	860,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	860,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	861,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	862,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	862,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	863,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	863,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	863,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	11,	864,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	864,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	11,	864,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	864,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	864,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	864,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	865,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	865,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	865,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	865,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	865,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	10,	866,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	866,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	10,	866,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	866,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	866,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	866,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	866,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	867,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	867,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	868,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	869,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	870,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	871,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	871,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	871,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	871,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	871,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	872,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	872,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	872,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	872,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	872,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	873,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	873,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	873,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	874,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	874,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	874,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	874,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	874,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	874,	"RO",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	874,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	874,	"RO",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	874,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	874,	"RO",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	875,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	876,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	876,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	876,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	877,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	877,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	877,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	877,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	877,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	877,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	877,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	15,	878,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	878,	"RAZ",	1,	1,	0,	0},
+	{"OWORDP"                      ,	0,	64,	879,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	880,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	881,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	882,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	882,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	882,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	882,	"RAZ",	1,	1,	0,	0},
+	{"FPACREDS"                    ,	12,	2,	882,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	882,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	882,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	882,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	882,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	882,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	882,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	882,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	882,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	882,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	882,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	882,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	882,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	882,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	883,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	883,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	883,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	884,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	884,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	885,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	885,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	885,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	886,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	886,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	886,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	886,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	886,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	886,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	886,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	887,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	887,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	888,	"RAZ",	1,	1,	0,	0},
+	{"COEFFS"                      ,	0,	8,	889,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	889,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	890,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	891,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"EER_VAL"                     ,	9,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"EER_LCK"                     ,	10,	1,	892,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	892,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	893,	"RO",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	64,	894,	"WO",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	895,	"RO",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_0"                      ,	2,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI0_1"                      ,	3,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_0"                      ,	4,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"DSI1_1"                      ,	5,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	896,	"RAZ",	1,	1,	0,	0},
+	{"P2N1_P1"                     ,	9,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_24"              ,	19,	6,	896,	"RAZ",	1,	1,	0,	0},
+	{"CPL_P1"                      ,	25,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	896,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	896,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_4"                ,	1,	4,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTLP_RO"                     ,	5,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	897,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	897,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	897,	"R/W",	0,	0,	3ull,	3ull},
+	{"WAITL_COM"                   ,	16,	1,	897,	"R/W",	0,	1,	0ull,	0},
+	{"DIS_PORT"                    ,	17,	1,	897,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTA"                        ,	18,	1,	897,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	19,	1,	897,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	20,	1,	897,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	21,	1,	897,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_63"              ,	22,	42,	897,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	898,	"RO",	1,	1,	0,	0},
+	{"P0_NTAGS"                    ,	8,	6,	898,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	14,	6,	898,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_63"              ,	20,	44,	898,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	899,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	899,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	899,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	899,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	899,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	900,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	900,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	900,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	32,	901,	"R/W",	0,	1,	0ull,	0},
+	{"ADBG_SEL"                    ,	32,	1,	901,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	901,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	902,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	902,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	903,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	903,	"R/W",	0,	1,	0ull,	0},
+	{"TIM"                         ,	0,	32,	904,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	904,	"RAZ",	1,	1,	0,	0},
+	{"RML_TO"                      ,	0,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	905,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	905,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	4,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	5,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UP_WI"                    ,	9,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_B0"                    ,	10,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M0_UN_WI"                    ,	11,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_B0"                    ,	12,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UP_WI"                    ,	13,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_B0"                    ,	14,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"M1_UN_WI"                    ,	15,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT0"                    ,	16,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO_INT1"                    ,	17,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC0_INT"                    ,	18,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC1_INT"                    ,	19,	1,	906,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAFI"                       ,	32,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	48,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_PAD"                     ,	60,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML_TO"                      ,	0,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	4,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	5,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_B0"                    ,	8,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UP_WI"                    ,	9,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_B0"                    ,	10,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M0_UN_WI"                    ,	11,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_B0"                    ,	12,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UP_WI"                    ,	13,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_B0"                    ,	14,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"M1_UN_WI"                    ,	15,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MIO_INT0"                    ,	16,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"MIO_INT1"                    ,	17,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC0_INT"                    ,	18,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"MAC1_INT"                    ,	19,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	907,	"RAZ",	1,	1,	0,	0},
+	{"DMAFI"                       ,	32,	2,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT"                        ,	34,	2,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME"                       ,	36,	2,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_47"              ,	38,	10,	907,	"RAZ",	1,	1,	0,	0},
+	{"PIDBOF"                      ,	48,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	49,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	50,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	51,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	52,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	53,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	54,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	55,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT0_ERR"                   ,	56,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SPRT1_ERR"                   ,	57,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_59"              ,	58,	2,	907,	"RAZ",	1,	1,	0,	0},
+	{"ILL_PAD"                     ,	60,	1,	907,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	907,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	908,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	909,	"RO",	0,	1,	0ull,	0},
+	{"P0_PCNT"                     ,	0,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	910,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	910,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	910,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_P_D"                      ,	48,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_N_D"                      ,	49,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"P0_C_D"                      ,	50,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_P_D"                      ,	51,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_N_D"                      ,	52,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"P1_C_D"                      ,	53,	1,	910,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_54_63"              ,	54,	10,	910,	"RAZ",	1,	1,	0,	0},
+	{"NUM"                         ,	0,	8,	911,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	911,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	912,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	912,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	912,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	913,	"R/W",	0,	1,	0ull,	0},
+	{"RTYPE"                       ,	30,	2,	913,	"R/W",	0,	1,	0ull,	0},
+	{"WTYPE"                       ,	32,	2,	913,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	913,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	913,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	3,	913,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	42,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	913,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	914,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	915,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	916,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	917,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	918,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	919,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	920,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	921,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	922,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	922,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	922,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	924,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	931,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	931,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	931,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	932,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	932,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	933,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	933,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	933,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	934,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	934,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	934,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	935,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	935,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	935,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	936,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	936,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	937,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	937,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	938,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	938,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	939,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	940,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	940,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	940,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	940,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	940,	"RO",	0,	1,	16ull,	0},
+	{"NTAG"                        ,	0,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	1,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	2,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	3,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	941,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	941,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RNTAG"                       ,	22,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RNTT"                        ,	23,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RNGRP"                       ,	24,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RNQOS"                       ,	25,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_27"              ,	26,	2,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	941,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	941,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	941,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	942,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	942,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	942,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	943,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	943,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	944,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	945,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	945,	"RO",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	946,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	946,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	947,	"RAZ",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	0,	4,	948,	"R/W",	0,	0,	15ull,	15ull},
+	{"RING_EN"                     ,	4,	1,	948,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	948,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	949,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	950,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	950,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	951,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	951,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	952,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	952,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	953,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	953,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	954,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	954,	"RO",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	955,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	955,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	956,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	957,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	957,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	957,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	957,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	957,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	957,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	957,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	957,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	957,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	957,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	958,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	958,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	959,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	960,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	960,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	961,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	961,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	961,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	962,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	962,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	963,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	963,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	964,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	964,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	965,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	965,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	966,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	967,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	967,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	968,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	969,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	969,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	970,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	970,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	971,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	971,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	972,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	972,	"RAZ",	1,	1,	0,	0},
+	{"MRRS"                        ,	0,	3,	973,	"R/W",	0,	0,	2ull,	2ull},
+	{"BAR0_D"                      ,	3,	1,	973,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIND_D"                      ,	4,	1,	973,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	973,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	974,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	975,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	976,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	976,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	976,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	976,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	977,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	977,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	977,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	977,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	977,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	977,	"RAZ",	1,	1,	0,	0},
+	{"NNP1"                        ,	48,	8,	977,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	977,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	978,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	978,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	978,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	978,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	978,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	979,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	979,	"R/W",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	979,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	979,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	980,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	981,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	981,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	981,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	981,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	982,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	983,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	983,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	984,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	984,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	985,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	985,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	985,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	985,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	985,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	985,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	985,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	986,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	986,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	986,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	986,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	987,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	987,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	988,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	988,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	988,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	988,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	989,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	989,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	989,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	6,	990,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_6_7"                ,	6,	2,	990,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	6,	990,	"R/W",	0,	0,	19ull,	19ull},
+	{"RESERVED_14_63"              ,	14,	50,	990,	"RAZ",	1,	1,	0,	0},
+	{"DENY_BAR0"                   ,	0,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR1"                   ,	1,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"DENY_BAR2"                   ,	2,	1,	991,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	991,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	992,	"R/W",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	992,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	992,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	993,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_REV"                    ,	16,	16,	993,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	993,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	994,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	994,	"RAZ",	1,	1,	0,	0},
+	{"OMSG"                        ,	0,	7,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"IMSG"                        ,	7,	5,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF"                       ,	12,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"TXBUF"                       ,	14,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"OSPF"                        ,	16,	1,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"ISPF"                        ,	17,	1,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"OARB"                        ,	18,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"RXBUF2"                      ,	20,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	995,	"RAZ",	1,	1,	0,	0},
+	{"OPTRS"                       ,	24,	4,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"OBULK"                       ,	28,	4,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"RTN"                         ,	32,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"OFREE"                       ,	34,	1,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"ITAG"                        ,	35,	1,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"OTAG"                        ,	36,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"BELL"                        ,	38,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"CRAM"                        ,	40,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"MRAM"                        ,	42,	2,	995,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	995,	"RAZ",	1,	1,	0,	0},
+	{"MBOX"                        ,	0,	4,	996,	"R/W",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	4,	4,	996,	"R/W",	0,	1,	0ull,	0},
+	{"LTTR"                        ,	8,	4,	996,	"R/W",	0,	1,	0ull,	0},
+	{"PRT_SEL"                     ,	12,	3,	996,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	996,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	16,	2,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	18,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	19,	2,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	21,	1,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	996,	"RAZ",	1,	1,	0,	0},
+	{"RSP_THR"                     ,	24,	6,	996,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	996,	"RAZ",	1,	1,	0,	0},
+	{"TO_MODE"                     ,	31,	1,	996,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	996,	"RAZ",	1,	1,	0,	0},
+	{"TAG"                         ,	0,	32,	997,	"R/W",	0,	1,	0ull,	0},
+	{"TT"                          ,	32,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RS"                          ,	34,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_41"              ,	35,	7,	997,	"RAZ",	1,	1,	0,	0},
+	{"NTAG"                        ,	42,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NTT"                         ,	43,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NGRP"                        ,	44,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"NQOS"                        ,	45,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	997,	"RAZ",	1,	1,	0,	0},
+	{"SL"                          ,	48,	7,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	997,	"RAZ",	1,	1,	0,	0},
+	{"PM"                          ,	56,	2,	997,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_62"              ,	58,	5,	997,	"RAZ",	1,	1,	0,	0},
+	{"R"                           ,	63,	1,	997,	"R/W",	0,	1,	0ull,	0},
+	{"GRP0"                        ,	0,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS0"                        ,	4,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP1"                        ,	8,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1"                        ,	12,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_15"              ,	15,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP2"                        ,	16,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2"                        ,	20,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP3"                        ,	24,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3"                        ,	28,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_31_31"              ,	31,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP4"                        ,	32,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4"                        ,	36,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_39_39"              ,	39,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP5"                        ,	40,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5"                        ,	44,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_47_47"              ,	47,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP6"                        ,	48,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6"                        ,	52,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_55_55"              ,	55,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"GRP7"                        ,	56,	4,	998,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7"                        ,	60,	3,	998,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_63_63"              ,	63,	1,	998,	"RAZ",	1,	1,	0,	0},
+	{"SID0"                        ,	0,	16,	999,	"RO",	0,	1,	0ull,	0},
+	{"LTTR0"                       ,	16,	2,	999,	"RO",	0,	1,	0ull,	0},
+	{"MBOX0"                       ,	18,	2,	999,	"RO",	0,	1,	0ull,	0},
+	{"SEG0"                        ,	20,	4,	999,	"RO",	0,	1,	0ull,	0},
+	{"DIS0"                        ,	24,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TT0"                         ,	25,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_26_26"              ,	26,	1,	999,	"RAZ",	1,	1,	0,	0},
+	{"PRT0"                        ,	27,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TOC0"                        ,	28,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TOE0"                        ,	29,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"ERR0"                        ,	30,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"VAL0"                        ,	31,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"SID1"                        ,	32,	16,	999,	"RO",	0,	1,	0ull,	0},
+	{"LTTR1"                       ,	48,	2,	999,	"RO",	0,	1,	0ull,	0},
+	{"MBOX1"                       ,	50,	2,	999,	"RO",	0,	1,	0ull,	0},
+	{"SEG1"                        ,	52,	4,	999,	"RO",	0,	1,	0ull,	0},
+	{"DIS1"                        ,	56,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TT1"                         ,	57,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_58"              ,	58,	1,	999,	"RAZ",	1,	1,	0,	0},
+	{"PRT1"                        ,	59,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TOC1"                        ,	60,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"TOE1"                        ,	61,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"ERR1"                        ,	62,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"VAL1"                        ,	63,	1,	999,	"RO",	0,	1,	0ull,	0},
+	{"MAX_P0"                      ,	0,	6,	1000,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1000,	"RAZ",	1,	1,	0,	0},
+	{"MAX_P1"                      ,	8,	6,	1000,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1000,	"RAZ",	1,	1,	0,	0},
+	{"BUF_THR"                     ,	16,	4,	1000,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_30"              ,	20,	11,	1000,	"RAZ",	1,	1,	0,	0},
+	{"SP_VPORT"                    ,	31,	1,	1000,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAX_S0"                      ,	32,	6,	1000,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_38_39"              ,	38,	2,	1000,	"RAZ",	1,	1,	0,	0},
+	{"MAX_S1"                      ,	40,	6,	1000,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	1000,	"RAZ",	1,	1,	0,	0},
+	{"MAX_TOT"                     ,	48,	6,	1000,	"R/W",	0,	1,	48ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	1000,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1001,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1001,	"RAZ",	1,	1,	0,	0},
+	{"PKO_RST"                     ,	0,	1,	1002,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_30"               ,	1,	30,	1002,	"RAZ",	1,	1,	0,	0},
+	{"INT_SUM"                     ,	31,	1,	1002,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1002,	"RAZ",	1,	1,	0,	0},
+	{"TXBELL"                      ,	0,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"BELL_ERR"                    ,	1,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBELL"                      ,	2,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAINT_OP"                    ,	3,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR_ERR"                     ,	4,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"DENY_WR"                     ,	5,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLI_ERR"                     ,	6,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"WR_DONE"                     ,	7,	1,	1003,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"MCE_RX"                      ,	9,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_TX"                     ,	10,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"SOFT_RX"                     ,	11,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"LOG_ERB"                     ,	12,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"PHY_ERB"                     ,	13,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_DWN"                    ,	14,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"LINK_UP"                     ,	15,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG0"                       ,	16,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG1"                       ,	17,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"OMSG_ERR"                    ,	18,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO_ERR"                     ,	19,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"RTRY_ERR"                    ,	20,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"F_ERROR"                     ,	21,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAC_BUF"                     ,	22,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"DEGRADE"                     ,	23,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAIL"                        ,	24,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"TTL_TOUT"                    ,	25,	1,	1003,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_26_63"              ,	26,	38,	1003,	"RAZ",	1,	1,	0,	0},
+	{"BE1"                         ,	0,	8,	1004,	"RO",	0,	1,	0ull,	0},
+	{"BE0"                         ,	8,	8,	1004,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_28"              ,	16,	13,	1004,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	29,	3,	1004,	"RO",	0,	1,	0ull,	0},
+	{"LENGTH"                      ,	32,	10,	1004,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_42_47"              ,	42,	6,	1004,	"RO",	1,	1,	0,	0},
+	{"TAG"                         ,	48,	8,	1004,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1004,	"RO",	0,	1,	0ull,	0},
+	{"CMD"                         ,	60,	4,	1004,	"RO",	0,	1,	0ull,	0},
+	{"INFO1"                       ,	0,	64,	1005,	"RO",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	1,	1006,	"RO",	0,	1,	0ull,	0},
+	{"LNS"                         ,	1,	1,	1006,	"RO",	0,	1,	0ull,	0},
+	{"RSRVD"                       ,	2,	30,	1006,	"RO",	0,	1,	0ull,	0},
+	{"LETTER"                      ,	32,	2,	1006,	"RO",	0,	1,	0ull,	0},
+	{"MBOX"                        ,	34,	2,	1006,	"RO",	0,	1,	0ull,	0},
+	{"XMBOX"                       ,	36,	4,	1006,	"RO",	0,	1,	0ull,	0},
+	{"DID"                         ,	40,	16,	1006,	"RO",	0,	1,	0ull,	0},
+	{"SSIZE"                       ,	56,	4,	1006,	"RO",	0,	1,	0ull,	0},
+	{"SIS"                         ,	60,	1,	1006,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	61,	1,	1006,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1006,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1007,	"RAZ",	1,	1,	0,	0},
+	{"OTHER"                       ,	8,	48,	1007,	"RO",	0,	1,	0ull,	0},
+	{"TYPE"                        ,	56,	4,	1007,	"RO",	0,	1,	0ull,	0},
+	{"TT"                          ,	60,	2,	1007,	"RO",	0,	1,	0ull,	0},
+	{"PRIO"                        ,	62,	2,	1007,	"RO",	0,	1,	0ull,	0},
+	{"TXBELL"                      ,	0,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BELL_ERR"                    ,	1,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBELL"                      ,	2,	1,	1008,	"RO",	0,	0,	0ull,	0ull},
+	{"MAINT_OP"                    ,	3,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR_ERR"                     ,	4,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DENY_WR"                     ,	5,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SLI_ERR"                     ,	6,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WR_DONE"                     ,	7,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_TX"                      ,	8,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCE_RX"                      ,	9,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_TX"                     ,	10,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SOFT_RX"                     ,	11,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOG_ERB"                     ,	12,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_ERB"                     ,	13,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_DWN"                    ,	14,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LINK_UP"                     ,	15,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG0"                       ,	16,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG1"                       ,	17,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OMSG_ERR"                    ,	18,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKO_ERR"                     ,	19,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTRY_ERR"                    ,	20,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"F_ERROR"                     ,	21,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAC_BUF"                     ,	22,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEGRAD"                      ,	23,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FAIL"                        ,	24,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TTL_TOUT"                    ,	25,	1,	1008,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	1008,	"RAZ",	1,	1,	0,	0},
+	{"INT2_SUM"                    ,	31,	1,	1008,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1008,	"RAZ",	1,	1,	0,	0},
+	{"RX_POL"                      ,	0,	4,	1009,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_POL"                      ,	4,	4,	1009,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_WIDTH"                    ,	8,	2,	1009,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_FLOW"                     ,	10,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_11_11"              ,	11,	1,	1009,	"RAZ",	1,	1,	0,	0},
+	{"A50"                         ,	12,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
+	{"A66"                         ,	13,	1,	1009,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	1009,	"RAZ",	1,	1,	0,	0},
+	{"OPS"                         ,	32,	32,	1009,	"R/W",	0,	0,	64756ull,	64756ull},
+	{"RX_STAT"                     ,	0,	8,	1010,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_INUSE"                    ,	8,	4,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	1010,	"RAZ",	1,	1,	0,	0},
+	{"RX_ENB"                      ,	16,	8,	1010,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_24_31"              ,	24,	8,	1010,	"RAZ",	1,	1,	0,	0},
+	{"TX_STAT"                     ,	32,	8,	1010,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_INUSE"                    ,	40,	4,	1010,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_47"              ,	44,	4,	1010,	"RAZ",	1,	1,	0,	0},
+	{"TX_ENB"                      ,	48,	8,	1010,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_56_63"              ,	56,	8,	1010,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	24,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	24,	1,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	25,	1,	1011,	"RO",	0,	1,	0ull,	0},
+	{"FAIL"                        ,	26,	1,	1011,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_27_31"              ,	27,	5,	1011,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	32,	32,	1011,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DATA"                     ,	0,	32,	1012,	"RO",	0,	1,	0ull,	0},
+	{"VALID"                       ,	32,	1,	1012,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_33_63"              ,	33,	31,	1012,	"RAZ",	1,	1,	0,	0},
+	{"MCE"                         ,	0,	1,	1013,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1013,	"RAZ",	1,	1,	0,	0},
+	{"RP0_PID"                     ,	0,	2,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_PID"                     ,	2,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP0_SID"                     ,	3,	2,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RP1_SID"                     ,	5,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1014,	"RAZ",	1,	1,	0,	0},
+	{"W_RO"                        ,	8,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RR_RO"                       ,	9,	1,	1014,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1014,	"RAZ",	1,	1,	0,	0},
+	{"LTTR_MP"                     ,	0,	4,	1015,	"R/W",	0,	1,	15ull,	0},
+	{"LTTR_SP"                     ,	4,	4,	1015,	"R/W",	0,	1,	15ull,	0},
+	{"IDM_DID"                     ,	8,	1,	1015,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_SIS"                     ,	9,	1,	1015,	"R/W",	0,	1,	1ull,	0},
+	{"IDM_TT"                      ,	10,	1,	1015,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_11_14"              ,	11,	4,	1015,	"RAZ",	1,	1,	0,	0},
+	{"RTRY_EN"                     ,	15,	1,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"RTRY_THR"                    ,	16,	16,	1015,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_MAX"                    ,	32,	5,	1015,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_62"              ,	37,	26,	1015,	"RAZ",	1,	1,	0,	0},
+	{"TESTMODE"                    ,	63,	1,	1015,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOOD"                        ,	0,	16,	1016,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1016,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1016,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1017,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1017,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALL_NMP"                     ,	1,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_4"                ,	4,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX_NMP"                    ,	5,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1018,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID_NMP"                      ,	9,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1018,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_15_63"              ,	15,	49,	1018,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	2,	1019,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_30"               ,	2,	29,	1019,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	31,	1,	1019,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1019,	"RAZ",	1,	1,	0,	0},
+	{"TOT_SILO"                    ,	0,	5,	1020,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	1020,	"RAZ",	1,	1,	0,	0},
+	{"ALL_PSD"                     ,	0,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_NMP"                     ,	1,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_FMP"                     ,	2,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ALL_SP"                      ,	3,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_PSD"                    ,	4,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_NMP"                    ,	5,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_FMP"                    ,	6,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"MBOX_SP"                     ,	7,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ID_PSD"                      ,	8,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ID_NMP"                      ,	9,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ID_FMP"                      ,	10,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"ID_SP"                       ,	11,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_NMP"                    ,	12,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_FMP"                    ,	13,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"CTLR_SP"                     ,	14,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"XMBOX_SP"                    ,	15,	1,	1021,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	1021,	"RAZ",	1,	1,	0,	0},
+	{"START_CNT"                   ,	0,	16,	1022,	"RO",	0,	1,	0ull,	0},
+	{"END_CNT"                     ,	16,	16,	1022,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1022,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1023,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"DEST_ID"                     ,	4,	1,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1023,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	8,	8,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	16,	16,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1023,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1023,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1024,	"RO",	0,	1,	0ull,	0},
+	{"COUNT"                       ,	32,	8,	1024,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	1024,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1025,	"RO",	0,	1,	128ull,	0},
+	{"N_POST"                      ,	8,	5,	1025,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1025,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1025,	"RO",	0,	1,	128ull,	0},
+	{"MBOX"                        ,	24,	4,	1025,	"RO",	0,	1,	8ull,	0},
+	{"RESERVED_28_39"              ,	28,	12,	1025,	"RAZ",	1,	1,	0,	0},
+	{"RTN_PR1"                     ,	40,	8,	1025,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR2"                     ,	48,	8,	1025,	"RO",	0,	1,	0ull,	0},
+	{"RTN_PR3"                     ,	56,	8,	1025,	"RO",	0,	1,	0ull,	0},
+	{"IAOW_SEL"                    ,	0,	2,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	1026,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	4,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	5,	1,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	1026,	"RAZ",	1,	1,	0,	0},
+	{"RD_PRIOR"                    ,	8,	2,	1026,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_PRIOR"                    ,	10,	2,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_OP"                       ,	12,	3,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	1026,	"RAZ",	1,	1,	0,	0},
+	{"WR_OP"                       ,	16,	3,	1026,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1026,	"RAZ",	1,	1,	0,	0},
+	{"SEQ"                         ,	0,	32,	1027,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1027,	"RAZ",	1,	1,	0,	0},
+	{"SRIO"                        ,	0,	1,	1028,	"RO",	1,	1,	0,	0},
+	{"ACCESS"                      ,	1,	1,	1028,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	1028,	"RAZ",	1,	1,	0,	0},
+	{"ITAG"                        ,	0,	5,	1029,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1029,	"RAZ",	1,	1,	0,	0},
+	{"OTAG"                        ,	8,	5,	1029,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	1029,	"RAZ",	1,	1,	0,	0},
+	{"O_CLR"                       ,	16,	1,	1029,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1029,	"RAZ",	1,	1,	0,	0},
+	{"POST"                        ,	0,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_POST"                      ,	8,	5,	1030,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_13_15"              ,	13,	3,	1030,	"RAZ",	1,	1,	0,	0},
+	{"COMP"                        ,	16,	8,	1030,	"R/W",	0,	0,	128ull,	128ull},
+	{"MBOX"                        ,	24,	4,	1030,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_28_63"              ,	28,	36,	1030,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1031,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1031,	"RAZ",	1,	1,	0,	0},
+	{"PENDING"                     ,	8,	1,	1031,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	1031,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1031,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1031,	"RAZ",	1,	1,	0,	0},
+	{"PRIORITY"                    ,	0,	2,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1032,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	3,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"SRC_ID"                      ,	4,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	5,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"ERROR"                       ,	6,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	7,	1,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1032,	"RAZ",	1,	1,	0,	0},
+	{"DEST_ID"                     ,	16,	16,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	32,	16,	1032,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1032,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH0"                      ,	0,	4,	1033,	"R/W",	0,	0,	6ull,	3ull},
+	{"RESERVED_4_7"                ,	4,	4,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH1"                      ,	8,	4,	1033,	"R/W",	0,	0,	4ull,	2ull},
+	{"RESERVED_12_15"              ,	12,	4,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TX_TH2"                      ,	16,	4,	1033,	"R/W",	0,	0,	2ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH0"                     ,	32,	5,	1033,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_37_39"              ,	37,	3,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH1"                     ,	40,	5,	1033,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_45_47"              ,	45,	3,	1033,	"RAZ",	1,	1,	0,	0},
+	{"TAG_TH2"                     ,	48,	5,	1033,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_53_63"              ,	53,	11,	1033,	"RAZ",	1,	1,	0,	0},
+	{"EMPH"                        ,	0,	4,	1034,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1034,	"RAZ",	1,	1,	0,	0},
+	{"S2M_PR0"                     ,	0,	8,	1035,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR1"                     ,	8,	8,	1035,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR2"                     ,	16,	8,	1035,	"RO",	0,	1,	0ull,	0},
+	{"S2M_PR3"                     ,	24,	8,	1035,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1035,	"RAZ",	1,	1,	0,	0},
+	{"GOOD"                        ,	0,	16,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"BAD"                         ,	16,	16,	1036,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	1036,	"RAZ",	1,	1,	0,	0},
+	{"ASSY_VEN"                    ,	0,	16,	1037,	"RO",	0,	0,	140ull,	0ull},
+	{"ASSY_ID"                     ,	16,	16,	1037,	"RO",	0,	0,	0ull,	0ull},
+	{"EXT_FPTR"                    ,	0,	16,	1038,	"RO",	0,	0,	256ull,	256ull},
+	{"ASSY_REV"                    ,	16,	16,	1038,	"RO",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_2"                ,	1,	2,	1039,	"RAZ",	1,	1,	0,	0},
+	{"NCA"                         ,	3,	1,	1039,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	4,	2,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1039,	"RAZ",	1,	1,	0,	0},
+	{"LA"                          ,	8,	22,	1039,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1039,	"RAZ",	1,	1,	0,	0},
+	{"FULL"                        ,	0,	1,	1040,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1040,	"RAZ",	1,	1,	0,	0},
+	{"COMP_TAG"                    ,	0,	32,	1041,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEMORY"                      ,	0,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
+	{"DOORBELL"                    ,	1,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG0"                       ,	2,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
+	{"IMSG1"                       ,	3,	1,	1042,	"R/W",	0,	0,	0ull,	1ull},
+	{"HALT"                        ,	4,	1,	1042,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	1042,	"RAZ",	1,	1,	0,	0},
+	{"VENDOR"                      ,	0,	16,	1043,	"RO",	0,	0,	140ull,	140ull},
+	{"DEVICE"                      ,	16,	16,	1043,	"RO",	0,	1,	144ull,	0},
+	{"REVISION"                    ,	0,	8,	1044,	"RO",	1,	1,	0,	0},
+	{"RESERVED_8_31"               ,	8,	24,	1044,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	1045,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1045,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1045,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1045,	"RO",	0,	0,	0ull,	0ull},
+	{"VALID"                       ,	0,	1,	1046,	"R/W0C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	1046,	"RAZ",	1,	1,	0,	0},
+	{"ERR_INFO"                    ,	4,	20,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_TYPE"                    ,	24,	5,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"INF_TYPE"                    ,	29,	3,	1046,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_TOUT"                    ,	0,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1047,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1047,	"R/W",	0,	0,	0ull,	0ull},
+	{"RATE_CNT"                    ,	0,	8,	1048,	"R/W",	0,	1,	0ull,	0},
+	{"PK_RATE"                     ,	8,	8,	1048,	"R/W",	0,	1,	0ull,	0},
+	{"RATE_LIM"                    ,	16,	2,	1048,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_23"              ,	18,	6,	1048,	"RAZ",	1,	1,	0,	0},
+	{"ERR_BIAS"                    ,	24,	8,	1048,	"R/W",	0,	0,	128ull,	128ull},
+	{"LNK_TOUT"                    ,	0,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ACK"                     ,	1,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEL_ERR"                     ,	2,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_TOGGLE"                    ,	3,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"PROTERR"                     ,	4,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_ACK"                     ,	5,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_14"               ,	6,	9,	1049,	"RAZ",	1,	1,	0,	0},
+	{"INV_DATA"                    ,	15,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_CHAR"                    ,	16,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	17,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CRC"                     ,	18,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUT_ACK"                     ,	19,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"NACK"                        ,	20,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_ID"                      ,	21,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTL_CRC"                     ,	22,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_30"              ,	23,	8,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMP_ERR"                     ,	31,	1,	1049,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1050,	"RAZ",	1,	1,	0,	0},
+	{"DGRAD_TH"                    ,	16,	8,	1050,	"R/W",	0,	0,	255ull,	128ull},
+	{"FAIL_TH"                     ,	24,	8,	1050,	"R/W",	0,	0,	255ull,	255ull},
+	{"EF_ID"                       ,	0,	16,	1051,	"RO",	0,	0,	7ull,	7ull},
+	{"EF_PTR"                      ,	16,	16,	1051,	"RO",	0,	0,	0ull,	0ull},
+	{"ADDR"                        ,	0,	32,	1052,	"R/W",	0,	0,	0ull,	0ull},
+	{"XADDR"                       ,	0,	2,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	1053,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	29,	1053,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPT_IDX"                    ,	0,	5,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDPTR"                       ,	6,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"TT"                          ,	7,	1,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	8,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATUS"                      ,	12,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRA"                       ,	16,	8,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"TTYPE"                       ,	24,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"FTYPE"                       ,	28,	4,	1054,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_14"               ,	0,	15,	1055,	"RAZ",	1,	1,	0,	0},
+	{"TT"                          ,	15,	1,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID8"                         ,	16,	8,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"ID16"                        ,	24,	8,	1055,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID8"                     ,	0,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRC_ID16"                    ,	8,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID8"                     ,	16,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST_ID16"                    ,	24,	8,	1056,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1057,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESP_SZ"                     ,	0,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_21"               ,	1,	21,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_TRAN"                    ,	22,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNS_RESP"                    ,	23,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_TOUT"                    ,	24,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_TOUT"                    ,	25,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TGT"                     ,	26,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILL_TRAN"                    ,	27,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_FMT"                     ,	28,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSM_ERR"                     ,	29,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_ERR"                     ,	30,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO_ERR"                      ,	31,	1,	1058,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1059,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1060,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1061,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAPTURE"                     ,	0,	32,	1062,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOSTID"                      ,	0,	16,	1063,	"R/W",	0,	0,	65535ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1063,	"RAZ",	1,	1,	0,	0},
+	{"RX_SYNC"                     ,	0,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_SYNC"                     ,	1,	1,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_FLOW"                     ,	2,	1,	1064,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_19"               ,	3,	17,	1064,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_WM2"                      ,	20,	4,	1064,	"R/W",	0,	1,	2ull,	0},
+	{"TX_WM1"                      ,	24,	4,	1064,	"R/W",	0,	1,	3ull,	0},
+	{"TX_WM0"                      ,	28,	4,	1064,	"R/W",	0,	1,	4ull,	0},
+	{"RX_WM0"                      ,	0,	4,	1065,	"R/W",	0,	0,	4ull,	4ull},
+	{"RX_WM1"                      ,	4,	4,	1065,	"R/W",	0,	0,	3ull,	3ull},
+	{"RX_WM2"                      ,	8,	4,	1065,	"R/W",	0,	0,	2ull,	2ull},
+	{"RX_WM3"                      ,	12,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_WM0"                      ,	16,	4,	1065,	"R/W",	0,	0,	4ull,	4ull},
+	{"TX_WM1"                      ,	20,	4,	1065,	"R/W",	0,	0,	3ull,	3ull},
+	{"TX_WM2"                      ,	24,	4,	1065,	"R/W",	0,	0,	2ull,	2ull},
+	{"TX_WM3"                      ,	28,	4,	1065,	"R/W",	0,	0,	1ull,	1ull},
+	{"PD_CTRL"                     ,	0,	32,	1066,	"R/W",	0,	0,	0ull,	0ull},
+	{"LN0_DIS"                     ,	0,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN0_RX"                      ,	1,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_DIS"                     ,	4,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN1_RX"                      ,	5,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_DIS"                     ,	8,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN2_RX"                      ,	9,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_DIS"                     ,	12,	1,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"LN3_RX"                      ,	13,	3,	1067,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1067,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_26"               ,	0,	27,	1068,	"RAZ",	1,	1,	0,	0},
+	{"LOOPBACK"                    ,	27,	2,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	1068,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_RESET"                    ,	30,	1,	1068,	"R/W",	0,	0,	1ull,	1ull},
+	{"TX_RESET"                    ,	31,	1,	1068,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_SM"                     ,	0,	10,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_RDY"                      ,	10,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_RDY"                      ,	11,	1,	1069,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	1069,	"RAZ",	1,	1,	0,	0},
+	{"OVERWRT"                     ,	0,	1,	1070,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_31"               ,	1,	31,	1070,	"RAZ",	1,	1,	0,	0},
+	{"PKT_DATA"                    ,	0,	32,	1071,	"RO",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1072,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1072,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	5,	7,	1072,	"RO",	0,	1,	0ull,	0},
+	{"BUFFERS"                     ,	12,	4,	1072,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1072,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_15"               ,	0,	16,	1073,	"RAZ",	1,	1,	0,	0},
+	{"OCTETS"                      ,	16,	16,	1073,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_DATA"                    ,	0,	32,	1074,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIFO_ST"                     ,	0,	4,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"FULL"                        ,	4,	1,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_11"               ,	5,	7,	1075,	"RAZ",	1,	1,	0,	0},
+	{"BUFFERS"                     ,	12,	4,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"OCTETS"                      ,	16,	16,	1075,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUSN"                     ,	0,	3,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"STATUS1"                     ,	3,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_5"                ,	4,	2,	1076,	"RAZ",	1,	1,	0,	0},
+	{"XTRAIN"                      ,	6,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"XSYNC"                       ,	7,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"DEC_ERR"                     ,	8,	4,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TRAIN"                    ,	12,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_SYNC"                     ,	13,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ADAPT"                    ,	14,	1,	1076,	"RO",	0,	0,	1ull,	1ull},
+	{"RX_INV"                      ,	15,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_TYPE"                     ,	16,	2,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_MODE"                     ,	18,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_TYPE"                     ,	19,	1,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"LANE"                        ,	20,	4,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	24,	8,	1076,	"RO",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	0,	31,	1077,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1077,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_20"               ,	0,	21,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"LCSBA"                       ,	21,	11,	1078,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1079,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_13"               ,	3,	11,	1080,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	14,	18,	1080,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR48"                      ,	0,	16,	1081,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1081,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"BARSIZE"                     ,	3,	4,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_19"               ,	7,	13,	1082,	"RAZ",	1,	1,	0,	0},
+	{"ADDR32"                      ,	20,	12,	1082,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	0,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR66"                      ,	1,	2,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAX"                         ,	3,	1,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ESX"                         ,	4,	2,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_8"                ,	6,	3,	1083,	"RAZ",	1,	1,	0,	0},
+	{"ADDR48"                      ,	9,	7,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR64"                      ,	16,	16,	1083,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_RTRY"                    ,	0,	16,	1084,	"R/W",	0,	1,	0ull,	0},
+	{"TYPE_MRG"                    ,	16,	1,	1084,	"R/W",	0,	0,	1ull,	1ull},
+	{"EOP_MRG"                     ,	17,	1,	1084,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_SPF"                      ,	18,	1,	1084,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	1084,	"RAZ",	1,	1,	0,	0},
+	{"EX_ADDR"                     ,	0,	3,	1085,	"RO",	0,	0,	7ull,	7ull},
+	{"EX_FEAT"                     ,	3,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
+	{"LG_TRAN"                     ,	4,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
+	{"CRF"                         ,	5,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	6,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	1085,	"RAZ",	1,	1,	0,	0},
+	{"MULT_PRT"                    ,	27,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"SWITCHF"                     ,	28,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"PROC"                        ,	29,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
+	{"MEMORY"                      ,	30,	1,	1085,	"RO",	0,	0,	1ull,	1ull},
+	{"BRIDGE"                      ,	31,	1,	1085,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_ADDR"                     ,	0,	3,	1086,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_31"               ,	3,	29,	1086,	"RAZ",	1,	1,	0,	0},
+	{"PT_TYPE"                     ,	0,	1,	1087,	"RO",	0,	0,	1ull,	1ull},
+	{"PRT_LOCK"                    ,	1,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"DROP_PKT"                    ,	2,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"STP_PORT"                    ,	3,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUPPRESS"                    ,	4,	8,	1087,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_STAT"                     ,	12,	2,	1087,	"RO",	0,	0,	0ull,	0ull},
+	{"EX_WIDTH"                    ,	14,	2,	1087,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	1087,	"RAZ",	1,	1,	0,	0},
+	{"ENUMB"                       ,	17,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_18"              ,	18,	1,	1087,	"RAZ",	1,	1,	0,	0},
+	{"MCAST"                       ,	19,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIS_ERR"                     ,	20,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"I_ENABLE"                    ,	21,	1,	1087,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ENABLE"                    ,	22,	1,	1087,	"R/W",	0,	0,	0ull,	1ull},
+	{"DISABLE"                     ,	23,	1,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"OV_WIDTH"                    ,	24,	3,	1087,	"R/W",	0,	0,	0ull,	0ull},
+	{"IT_WIDTH"                    ,	27,	3,	1087,	"RO",	0,	1,	0ull,	0},
+	{"PT_WIDTH"                    ,	30,	2,	1087,	"RO",	0,	0,	3ull,	3ull},
+	{"EMPH_EN"                     ,	0,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EMPH"                     ,	1,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB_625G"                    ,	16,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUP_625G"                    ,	17,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"ENB_500G"                    ,	18,	1,	1088,	"R/W",	1,	1,	0,	0},
+	{"SUB_500G"                    ,	19,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"ENB_312G"                    ,	20,	1,	1088,	"R/W",	1,	1,	0,	0},
+	{"SUP_312G"                    ,	21,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"ENB_250G"                    ,	22,	1,	1088,	"R/W",	1,	1,	0,	0},
+	{"SUP_250G"                    ,	23,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"ENB_125G"                    ,	24,	1,	1088,	"R/W",	1,	1,	0,	0},
+	{"SUP_125G"                    ,	25,	1,	1088,	"RO",	1,	1,	0,	0},
+	{"BAUD_ENB"                    ,	26,	1,	1088,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAUD_SUP"                    ,	27,	1,	1088,	"RO",	0,	0,	0ull,	0ull},
+	{"SEL_BAUD"                    ,	28,	4,	1088,	"RO",	0,	1,	0ull,	0},
+	{"PT_UINIT"                    ,	0,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"PT_OK"                       ,	1,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"PT_ERROR"                    ,	2,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1089,	"RAZ",	1,	1,	0,	0},
+	{"PT_WRITE"                    ,	4,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	1089,	"RAZ",	1,	1,	0,	0},
+	{"I_SM_ERR"                    ,	8,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"I_ERROR"                     ,	9,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I_SM_RET"                    ,	10,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	1089,	"RAZ",	1,	1,	0,	0},
+	{"O_SM_ERR"                    ,	16,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"O_ERROR"                     ,	17,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_SM_RET"                    ,	18,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RTRIED"                    ,	19,	1,	1089,	"RO",	0,	0,	0ull,	0ull},
+	{"O_RETRY"                     ,	20,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	1089,	"RAZ",	1,	1,	0,	0},
+	{"O_DGRAD"                     ,	24,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"O_FAIL"                      ,	25,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PKT_DROP"                    ,	26,	1,	1089,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	1089,	"RAZ",	1,	1,	0,	0},
+	{"CMD"                         ,	0,	3,	1090,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_31"               ,	3,	29,	1090,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	5,	1091,	"RO",	0,	1,	0ull,	0},
+	{"ACKID"                       ,	5,	6,	1091,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_11_30"              ,	11,	20,	1091,	"RAZ",	1,	1,	0,	0},
+	{"VALID"                       ,	31,	1,	1091,	"RO",	0,	1,	0ull,	0},
+	{"O_ACKID"                     ,	0,	6,	1092,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	1092,	"RAZ",	1,	1,	0,	0},
+	{"E_ACKID"                     ,	8,	6,	1092,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_23"              ,	14,	10,	1092,	"RAZ",	1,	1,	0,	0},
+	{"I_ACKID"                     ,	24,	6,	1092,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	1092,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_28"               ,	0,	29,	1093,	"RAZ",	1,	1,	0,	0},
+	{"DISCOVER"                    ,	29,	1,	1093,	"R/W",	0,	0,	0ull,	1ull},
+	{"MENABLE"                     ,	30,	1,	1093,	"R/W",	1,	0,	0,	1ull},
+	{"HOST"                        ,	31,	1,	1093,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1094,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1094,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"EF_ID"                       ,	0,	16,	1095,	"RO",	0,	0,	1ull,	0ull},
+	{"EF_PTR"                      ,	16,	16,	1095,	"RO",	0,	0,	4096ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1096,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1096,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1097,	"RAZ",	1,	1,	0,	0},
+	{"TIMEOUT"                     ,	8,	24,	1097,	"R/W",	0,	0,	16777215ull,	0ull},
+	{"ID16"                        ,	0,	16,	1098,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1098,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1098,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE16"                    ,	0,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE8"                     ,	1,	1,	1099,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	1099,	"RAZ",	1,	1,	0,	0},
+	{"ID16"                        ,	0,	16,	1100,	"R/W",	0,	0,	65535ull,	0ull},
+	{"ID8"                         ,	16,	8,	1100,	"R/W",	0,	0,	255ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1100,	"RAZ",	1,	1,	0,	0},
+	{"EF_ID"                       ,	0,	16,	1101,	"RO",	0,	0,	13ull,	13ull},
+	{"EF_PTR"                      ,	16,	16,	1101,	"RO",	0,	0,	8192ull,	0ull},
+	{"RESERVED_0_1"                ,	0,	2,	1102,	"RAZ",	1,	1,	0,	0},
+	{"PORT_WR"                     ,	2,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SWP"                    ,	3,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"ATOM_CLR"                    ,	4,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_SET"                    ,	5,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_DEC"                    ,	6,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"ATOM_INC"                    ,	7,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"TESTSWAP"                    ,	8,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"COMPSWAP"                    ,	9,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	10,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"MSG"                         ,	11,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE_R"                     ,	12,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"SWRITE"                      ,	13,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"WRITE"                       ,	14,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"READ"                        ,	15,	1,	1102,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_21"              ,	16,	6,	1102,	"RAZ",	1,	1,	0,	0},
+	{"TLB_INVS"                    ,	22,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"TLB_INV"                     ,	23,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"I_INVALD"                    ,	24,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"IO_READ"                     ,	25,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"D_FLUSH"                     ,	26,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"CASTOUT"                     ,	27,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"D_INVALD"                    ,	28,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"RD_OWN"                      ,	29,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"I_READ"                      ,	30,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"GSM_READ"                    ,	31,	1,	1102,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP_CNT"                    ,	0,	16,	1103,	"RO",	0,	1,	0ull,	0},
+	{"DROP"                        ,	16,	1,	1103,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	1103,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	1104,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1104,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	24,	22,	1104,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	1104,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	47,	1,	1104,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	1104,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	20,	1105,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	1105,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	1105,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	1106,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	1106,	"RO",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	1106,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	1106,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	1106,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	1107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	1107,	"RAZ",	1,	1,	0,	0},
+	{"RING"                        ,	0,	4,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	1108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1108,	"RAZ",	1,	1,	0,	0},
+	{"CTL"                         ,	0,	1,	1109,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	1109,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	1109,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	1109,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1110,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1110,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE_TIMERS"               ,	0,	1,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	1111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	1111,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	1111,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	1112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1112,	"RAZ",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	1113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	1113,	"RAZ",	1,	1,	0,	0},
+	{"TDF"                         ,	0,	1,	1114,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKALWAYS"                   ,	15,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDAT_MD"                     ,	16,	1,	1115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	1116,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	1117,	"RAZ",	1,	1,	0,	0},
+	{"RPTR"                        ,	12,	10,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	1117,	"RAZ",	1,	1,	0,	0},
+	{"CYCLES"                      ,	24,	40,	1117,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1118,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1118,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1119,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1120,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1120,	"R/W",	0,	0,	0ull,	0ull},
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+	{"FAA64"                       ,	59,	1,	1120,	"R/W",	0,	0,	0ull,	1ull},
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+	{"USB0"                        ,	13,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1121,	"R/W",	0,	0,	0ull,	4095ull},
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+	{"ILLEGAL4"                    ,	28,	2,	1121,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1121,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1121,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1122,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_20_63"              ,	20,	44,	1122,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
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+	{"MCD0_TRG"                    ,	2,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	1123,	"R/W1C",	0,	0,	0ull,	0ull},
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+	{"DATA"                        ,	0,	64,	1124,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	5,	1125,	"RO",	0,	0,	0ull,	0ull},
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+	{"ADR"                         ,	0,	38,	1126,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1126,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1127,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
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+	{"CLR8"                        ,	44,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
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+	{"FAA64"                       ,	59,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1128,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1128,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1129,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1129,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1129,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1129,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1129,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1130,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	1131,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	38,	1132,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	1132,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NOP"                         ,	0,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	1,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	2,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	3,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RPL2"                        ,	4,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"DWB"                         ,	5,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_7"                ,	6,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"LDD"                         ,	8,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	9,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_14"              ,	10,	5,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	15,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	16,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	17,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	18,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	19,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STFIL1"                      ,	20,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STTIL1"                      ,	21,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS32"                       ,	22,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"FAS64"                       ,	23,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2I"                      ,	24,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"LTGL2I"                      ,	25,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"STGL2I"                      ,	26,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"INVL2"                       ,	28,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBIL2"                       ,	29,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"WBL2"                        ,	30,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKL2"                       ,	31,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	32,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	33,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	34,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	35,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST8"                      ,	36,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST16"                     ,	37,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST32"                     ,	38,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST64"                     ,	39,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET8"                        ,	40,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET16"                       ,	41,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET32"                       ,	42,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"SET64"                       ,	43,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR8"                        ,	44,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR16"                       ,	45,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR32"                       ,	46,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"CLR64"                       ,	47,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR8"                       ,	48,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR16"                      ,	49,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR32"                      ,	50,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"INCR64"                      ,	51,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR8"                       ,	52,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR16"                      ,	53,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR32"                      ,	54,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"DECR64"                      ,	55,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_56_57"              ,	56,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
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+	{"FAA64"                       ,	59,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_60_61"              ,	60,	2,	1133,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAA32"                       ,	62,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA64"                       ,	63,	1,	1133,	"R/W",	0,	0,	0ull,	1ull},
+	{"MIO"                         ,	0,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	1134,	"R/W",	0,	0,	0ull,	3ull},
+	{"SLI"                         ,	3,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPD"                         ,	9,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKO"                         ,	10,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	11,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"POW"                         ,	12,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"USB0"                        ,	13,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RAD"                         ,	14,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	15,	12,	1134,	"R/W",	0,	0,	0ull,	4095ull},
+	{"DPI"                         ,	27,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL4"                    ,	28,	2,	1134,	"R/W",	0,	0,	0ull,	3ull},
+	{"FAU"                         ,	30,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL5"                    ,	31,	1,	1134,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	1134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	8,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1135,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	1136,	"R/W",	0,	1,	0ull,	0},
+	{"LPL"                         ,	5,	27,	1136,	"R/W",	0,	1,	0ull,	0},
+	{"CF"                          ,	0,	1,	1137,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_31"               ,	1,	31,	1137,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTRLDSSEG"                   ,	0,	32,	1138,	"R/W",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1139,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_31"              ,	14,	18,	1139,	"RO",	0,	0,	0ull,	0ull},
+	{"CAPLENGTH"                   ,	0,	8,	1140,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_15"               ,	8,	8,	1140,	"RO",	0,	0,	0ull,	0ull},
+	{"HCIVERSION"                  ,	16,	16,	1140,	"RO",	0,	0,	256ull,	256ull},
+	{"AC64"                        ,	0,	1,	1141,	"RO",	0,	0,	1ull,	1ull},
+	{"PFLF"                        ,	1,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPC"                        ,	2,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"IST"                         ,	4,	4,	1141,	"RO",	0,	0,	2ull,	2ull},
+	{"EECP"                        ,	8,	8,	1141,	"RO",	0,	0,	160ull,	160ull},
+	{"RESERVED_16_31"              ,	16,	16,	1141,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PORTS"                     ,	0,	4,	1142,	"RO",	0,	0,	2ull,	2ull},
+	{"PPC"                         ,	4,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"PRR"                         ,	7,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"N_PCC"                       ,	8,	4,	1142,	"RO",	0,	0,	2ull,	2ull},
+	{"N_CC"                        ,	12,	4,	1142,	"RO",	0,	0,	1ull,	1ull},
+	{"P_INDICATOR"                 ,	16,	1,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"DPN"                         ,	20,	4,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_31"              ,	24,	8,	1142,	"RO",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	0,	1,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"MFMC"                        ,	1,	13,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	1143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_0"                ,	0,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"TA_OFF"                      ,	1,	8,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXTX_TADAO"                  ,	10,	3,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_31"              ,	13,	19,	1144,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_RW"                      ,	0,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCP_FW"                      ,	1,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"PESD"                        ,	2,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	1145,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NAKRF_DIS"                   ,	4,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTO_DIS"                    ,	5,	1,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_31"               ,	6,	26,	1145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_30"               ,	0,	31,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1146,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1147,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	1148,	"R/W",	0,	1,	0ull,	0},
+	{"BADDR"                       ,	12,	20,	1148,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	1,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PED"                         ,	2,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"PEDC"                        ,	3,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OCA"                         ,	4,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
+	{"OCC"                         ,	5,	1,	1149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FPR"                         ,	6,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPD"                         ,	7,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRST"                        ,	8,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	1149,	"RO",	0,	0,	0ull,	0ull},
+	{"LSTS"                        ,	10,	2,	1149,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	12,	1,	1149,	"RO",	0,	0,	1ull,	1ull},
+	{"PO"                          ,	13,	1,	1149,	"R/W",	0,	0,	1ull,	0ull},
+	{"PIC"                         ,	14,	2,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTC"                         ,	16,	4,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKCNNT_E"                    ,	20,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKDSCNNT_E"                  ,	21,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKOC_E"                      ,	22,	1,	1149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	1149,	"RO",	0,	0,	0ull,	0ull},
+	{"RS"                          ,	0,	1,	1150,	"R/W",	0,	0,	0ull,	1ull},
+	{"HCRESET"                     ,	1,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"FLS"                         ,	2,	2,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"PS_EN"                       ,	4,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"AS_EN"                       ,	5,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"IAA_DB"                      ,	6,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"LHCR"                        ,	7,	1,	1150,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASPMC"                       ,	8,	2,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"ASPM_EN"                     ,	11,	1,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"ITC"                         ,	16,	8,	1150,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_24_31"              ,	24,	8,	1150,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT_EN"                   ,	0,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"USBERRINT_EN"                ,	1,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"PCI_EN"                      ,	2,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"FLRO_EN"                     ,	3,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"HSERR_EN"                    ,	4,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"IOAA_EN"                     ,	5,	1,	1151,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	1151,	"RO",	0,	0,	0ull,	0ull},
+	{"USBINT"                      ,	0,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBERRINT"                   ,	1,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCD"                         ,	2,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLRO"                        ,	3,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSYSERR"                     ,	4,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOAA"                        ,	5,	1,	1152,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHTD"                       ,	12,	1,	1152,	"RO",	0,	0,	1ull,	0ull},
+	{"RECLM"                       ,	13,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"PSS"                         ,	14,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"ASS"                         ,	15,	1,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	1152,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1153,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCED"                        ,	4,	28,	1153,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1154,	"R/W",	0,	0,	0ull,	0ull},
+	{"BHED"                        ,	4,	28,	1154,	"R/W",	0,	1,	0ull,	0},
+	{"HCR"                         ,	0,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLF"                         ,	1,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLF"                         ,	2,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCR"                         ,	3,	1,	1155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"SOC"                         ,	16,	2,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	1155,	"RO",	0,	0,	0ull,	0ull},
+	{"CBSR"                        ,	0,	2,	1156,	"R/W",	0,	1,	0ull,	0},
+	{"PLE"                         ,	2,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"IE"                          ,	3,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	4,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLE"                         ,	5,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCFS"                        ,	6,	2,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"IR"                          ,	8,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWC"                         ,	9,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RWE"                         ,	10,	1,	1156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	1156,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1157,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCED"                        ,	4,	28,	1157,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHED"                        ,	4,	28,	1158,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_3"                ,	0,	4,	1159,	"RO",	0,	0,	0ull,	0ull},
+	{"DH"                          ,	4,	28,	1159,	"RO",	0,	1,	0ull,	0},
+	{"FI"                          ,	0,	14,	1160,	"R/W",	0,	1,	11999ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	1160,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSMPS"                       ,	16,	15,	1160,	"R/W",	0,	1,	0ull,	0},
+	{"FIT"                         ,	31,	1,	1160,	"R/W",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	0,	16,	1161,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	1161,	"RO",	0,	0,	0ull,	0ull},
+	{"FR"                          ,	0,	14,	1162,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_30"              ,	14,	17,	1162,	"RO",	0,	0,	0ull,	0ull},
+	{"FRT"                         ,	31,	1,	1162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_7"                ,	0,	8,	1163,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCCA"                        ,	8,	24,	1163,	"R/W",	0,	1,	0ull,	0},
+	{"SO"                          ,	0,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1164,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1164,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1165,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"MIE"                         ,	31,	1,	1165,	"R/W",	0,	0,	0ull,	0ull},
+	{"SO"                          ,	0,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WDH"                         ,	1,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SF"                          ,	2,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RD"                          ,	3,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UE"                          ,	4,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FNO"                         ,	5,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RHSC"                        ,	6,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_29"               ,	7,	23,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"OC"                          ,	30,	1,	1166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	1166,	"RO",	0,	0,	0ull,	0ull},
+	{"LST"                         ,	0,	12,	1167,	"R/W",	0,	1,	1576ull,	0},
+	{"RESERVED_12_31"              ,	12,	20,	1167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	1168,	"RO",	0,	0,	0ull,	0ull},
+	{"PCED"                        ,	4,	28,	1168,	"RO",	0,	1,	0ull,	0},
+	{"PS"                          ,	0,	14,	1169,	"R/W",	0,	0,	0ull,	15975ull},
+	{"RESERVED_14_31"              ,	14,	18,	1169,	"R/W",	0,	0,	0ull,	0ull},
+	{"REV"                         ,	0,	8,	1170,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_8_31"               ,	8,	24,	1170,	"RO",	0,	0,	0ull,	0ull},
+	{"NDP"                         ,	0,	8,	1171,	"RO",	0,	0,	2ull,	2ull},
+	{"NPS"                         ,	8,	1,	1171,	"R/W",	0,	0,	0ull,	0ull},
+	{"PSM"                         ,	9,	1,	1171,	"R/W",	0,	0,	1ull,	1ull},
+	{"DT"                          ,	10,	1,	1171,	"RO",	0,	0,	0ull,	0ull},
+	{"OCPM"                        ,	11,	1,	1171,	"R/W",	1,	1,	0,	0},
+	{"NOCP"                        ,	12,	1,	1171,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_23"              ,	13,	11,	1171,	"RO",	0,	0,	0ull,	0ull},
+	{"POTPGT"                      ,	24,	8,	1171,	"R/W",	0,	0,	1ull,	1ull},
+	{"DR"                          ,	0,	16,	1172,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPCM"                        ,	16,	16,	1172,	"R/W",	0,	1,	0ull,	0},
+	{"CCS"                         ,	0,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PES"                         ,	1,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PSS"                         ,	2,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"POCI"                        ,	3,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PRS"                         ,	4,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPS"                         ,	8,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"LSDA"                        ,	9,	1,	1173,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_15"              ,	10,	6,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSC"                         ,	16,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PESC"                        ,	17,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PSSC"                        ,	18,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"OCIC"                        ,	19,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"PRSC"                        ,	20,	1,	1173,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_31"              ,	21,	11,	1173,	"R/W",	0,	0,	0ull,	0ull},
+	{"LPS"                         ,	0,	1,	1174,	"R/W",	0,	0,	0ull,	0ull},
+	{"OCI"                         ,	1,	1,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_14"               ,	2,	13,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"DRWE"                        ,	15,	1,	1174,	"R/W",	0,	1,	0ull,	0},
+	{"LPSC"                        ,	16,	1,	1174,	"R/W",	0,	1,	0ull,	0},
+	{"CCIC"                        ,	17,	1,	1174,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_18_30"              ,	18,	13,	1174,	"RO",	0,	0,	0ull,	0ull},
+	{"CRWE"                        ,	31,	1,	1174,	"WO",	1,	1,	0,	0},
+	{"RESERVED_0_30"               ,	0,	31,	1175,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	31,	1,	1175,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERR_ADDR"                    ,	0,	32,	1176,	"RO",	0,	0,	0ull,	0ull},
+	{"PPAF_BIS"                    ,	0,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"WRBM_BIS"                    ,	1,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"ORBM_BIS"                    ,	2,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBM_BIS"                    ,	3,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"DESC_BIS"                    ,	4,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_BIS"                    ,	5,	1,	1177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	1177,	"RO",	1,	1,	0,	0},
+	{"HRST"                        ,	0,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_PRST"                      ,	1,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_POR"                       ,	2,	1,	1178,	"R/W",	0,	0,	1ull,	0ull},
+	{"P_COM_ON"                    ,	3,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	1178,	"R/W",	0,	1,	0ull,	0},
+	{"P_REFCLK_DIV"                ,	5,	2,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_REFCLK_SEL"                ,	7,	2,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"H_DIV"                       ,	9,	4,	1178,	"R/W",	0,	0,	6ull,	6ull},
+	{"O_CLKDIV_EN"                 ,	13,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_EN"                 ,	14,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_RST"                ,	15,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"H_CLKDIV_BYP"                ,	16,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"O_CLKDIV_RST"                ,	17,	1,	1178,	"R/W",	0,	0,	0ull,	1ull},
+	{"APP_START_CLK"               ,	18,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_SUSP_LGCY"              ,	19,	1,	1178,	"R/W",	0,	0,	1ull,	1ull},
+	{"OHCI_SM"                     ,	20,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"OHCI_CLKCKTRST"              ,	21,	1,	1178,	"R/W",	0,	0,	1ull,	1ull},
+	{"EHCI_SM"                     ,	22,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"START_BIST"                  ,	23,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLEAR_BIST"                  ,	24,	1,	1178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	1178,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1179,	"R/W",	0,	1,	0ull,	0},
+	{"EHCI_64B_ADDR_EN"            ,	8,	1,	1179,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_REG_A2"                  ,	9,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1179,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1179,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"DESC_RBM"                    ,	19,	1,	1179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	1179,	"RAZ",	1,	1,	0,	0},
+	{"FLA"                         ,	0,	6,	1180,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_6_63"               ,	6,	58,	1180,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	1181,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	5,	27,	1181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1181,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	1182,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	1182,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1183,	"RAZ",	1,	1,	0,	0},
+	{"PP_PSH_F"                    ,	0,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ER_PSH_F"                    ,	1,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OR_PSH_F"                    ,	2,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CF_PSH_F"                    ,	3,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_PSH_F"                    ,	4,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WB_POP_E"                    ,	5,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OC_OVF_E"                    ,	6,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EC_OVF_E"                    ,	7,	1,	1184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	1184,	"RAZ",	1,	1,	0,	0},
+	{"L2C_ADDR_MSB"                ,	0,	8,	1185,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_8"                ,	8,	1,	1185,	"RAZ",	1,	1,	0,	0},
+	{"INV_REG_A2"                  ,	9,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DESC_EMOD"               ,	10,	2,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BUFF_EMOD"               ,	12,	2,	1185,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2C_STT"                     ,	14,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_0PAG"                    ,	15,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_BC"                      ,	16,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_DC"                      ,	17,	1,	1185,	"R/W",	0,	0,	1ull,	1ull},
+	{"REG_NB"                      ,	18,	1,	1185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	1185,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	1186,	"RAZ",	1,	1,	0,	0},
+	{"TO_VAL"                      ,	8,	24,	1186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	1186,	"RAZ",	1,	1,	0,	0},
+	{"WM"                          ,	0,	5,	1187,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_5_63"               ,	5,	59,	1187,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_EN"                     ,	1,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"UPHY_BIST"                   ,	2,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_EN"                    ,	3,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	4,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	5,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	6,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	7,	1,	1188,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ERR"                    ,	8,	1,	1188,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	9,	1,	1188,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1188,	"RAZ",	1,	1,	0,	0},
+	{"TDATA_IN"                    ,	0,	8,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	8,	4,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	12,	1,	1189,	"R/W",	0,	0,	1ull,	0ull},
+	{"TCLK"                        ,	13,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_EN"                     ,	14,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPDISTUNE"                 ,	15,	3,	1189,	"R/W",	0,	0,	4ull,	4ull},
+	{"SQRXTUNE"                    ,	18,	3,	1189,	"R/W",	0,	0,	4ull,	4ull},
+	{"TXFSLSTUNE"                  ,	21,	4,	1189,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXPREEMPHASISTUNE"           ,	25,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXRISETUNE"                  ,	26,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXVREFTUNE"                  ,	27,	4,	1189,	"R/W",	0,	0,	5ull,	5ull},
+	{"TXHSVXTUNE"                  ,	31,	2,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	33,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"VBUSVLDEXT"                  ,	34,	1,	1189,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPPULLDOWN"                  ,	35,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
+	{"DMPULLDOWN"                  ,	36,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFEN"               ,	37,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
+	{"TXBISTSTUFFENH"              ,	38,	1,	1189,	"R/W",	0,	0,	1ull,	1ull},
+	{"TDATA_OUT"                   ,	39,	4,	1189,	"RO",	1,	1,	0,	0},
+	{"RESERVED_43_63"              ,	43,	21,	1189,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	1190,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	39,	1190,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	1190,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	33,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	1191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	1191,	"RAZ",	1,	1,	0,	0},
+	{"RESET"                       ,	0,	1,	1192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	1192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	1192,	"RAZ",	1,	1,	0,	0},
+	{"DISABLED"                    ,	0,	1,	1193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	1193,	"RAZ",	1,	1,	0,	0},
+	{"CTXSIZE"                     ,	8,	12,	1193,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	1193,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	1193,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	1193,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	1194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	1194,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1195,	"RAZ",	1,	1,	0,	0},
+	{"DOORBELL"                    ,	0,	1,	1196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	1196,	"RAZ",	1,	1,	0,	0},
+	{"MAX_INFL"                    ,	0,	4,	1197,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	1197,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
 
 
 const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
@@ -74260,6 +105457,8 @@ const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
 	cvmx_csr_db_cn50xx,
 	cvmx_csr_db_cn52xxp1,
 	cvmx_csr_db_cn52xx,
+	cvmx_csr_db_cn63xxp1,
+	cvmx_csr_db_cn63xx,
 	NULL
 };
 const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
@@ -74274,6 +105473,8 @@ const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
 	cvmx_csr_db_addresses_cn50xx,
 	cvmx_csr_db_addresses_cn52xxp1,
 	cvmx_csr_db_addresses_cn52xx,
+	cvmx_csr_db_addresses_cn63xxp1,
+	cvmx_csr_db_addresses_cn63xx,
 	NULL
 };
 const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
@@ -74288,5 +105489,7 @@ const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
 	cvmx_csr_db_fields_cn50xx,
 	cvmx_csr_db_fields_cn52xxp1,
 	cvmx_csr_db_fields_cn52xx,
+	cvmx_csr_db_fields_cn63xxp1,
+	cvmx_csr_db_fields_cn63xx,
 	NULL
 };
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.h b/sys/contrib/octeon-sdk/cvmx-csr-db.h
index a3b0239..b5e12df 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-db.h
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 #ifndef __CVMX_CSR_DB_H__
 #define __CVMX_CSR_DB_H__
 
@@ -48,10 +50,12 @@
  * Interface for the Octeon CSR database.
  *
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49507 $<hr>
  *
  */
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 #include "cvmx-platform.h"
+#endif
 
 #ifdef  __cplusplus
 extern "C" {
@@ -66,7 +70,8 @@ typedef enum {
    CVMX_CSR_DB_TYPE_PEXP,            /**< PCIe BAR 0 address only */
    CVMX_CSR_DB_TYPE_PEXP_NCB,        /**< NCB-direct and PCIe BAR0 address */
    CVMX_CSR_DB_TYPE_PCICONFIGEP,     /**< PCIe config address (EP mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
-   CVMX_CSR_DB_TYPE_PCICONFIGRC      /**< PCICONFIGRC - PCIe config address (RC mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
+   CVMX_CSR_DB_TYPE_PCICONFIGRC,     /**< PCICONFIGRC - PCIe config address (RC mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
+   CVMX_CSR_DB_TYPE_SRIOMAINT        /**< SRIOMAINT - SRIO maintenance registers */
 } CVMX_CSR_DB_TYPE_FIELD;
 
 /**
@@ -164,6 +169,16 @@ extern const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const cha
 extern void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value);
 
 /**
+ * Decode a CSR value into named bitfields. The model can either
+ * be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param name       CSR name to decode
+ * @param value      Value to decode
+ */
+extern void cvmx_csr_db_decode_by_name(int identifier, const char *name, uint64_t value);
+
+/**
  * Print a list of csrs begimning with a prefix. The
  * model can either be specified as a processor id or PCI id.
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-enums.h b/sys/contrib/octeon-sdk/cvmx-csr-enums.h
index f6f19a2..4813625 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-enums.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-enums.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,11 +42,12 @@
 
 
 
+
 /**
  * @file
  * Definitions for enumerations used with Octeon CSRs.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 #ifndef __CVMX_CSR_ENUMS_H__
@@ -53,7 +55,7 @@
 
 typedef enum {
    CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
-   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All bloccks into  L2 */
+   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All blocks into L2 */
    CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
    CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
 } cvmx_ipd_mode_t;
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h b/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
index 24d6386..4354209 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  *
@@ -44,73948 +46,66 @@
  *
  * This file is auto generated. Do not edit.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 #ifndef __CVMX_CSR_TYPEDEFS_H__
 #define __CVMX_CSR_TYPEDEFS_H__
-
-
-/**
- * cvmx_agl_gmx_bad_reg
- *
- * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong
- *
- *
- * Notes:
- * OUT_OVR[0], OVRFLW, TXPOP, TXPSH    will be reset when MIX0_CTL[RESET] is set to 1.
- * OUT_OVR[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.
- * LOSTSTAT, STATOVR, STATOVR will bee reset when both MIX0/1_CTL[RESET] are set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_bad_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t txpsh1                  : 1;       /**< TX FIFO overflow (MII1) */
-        uint64_t txpop1                  : 1;       /**< TX FIFO underflow (MII1) */
-        uint64_t ovrflw1                 : 1;       /**< RX FIFO overflow (MII1) */
-        uint64_t txpsh                   : 1;       /**< TX FIFO overflow */
-        uint64_t txpop                   : 1;       /**< TX FIFO underflow */
-        uint64_t ovrflw                  : 1;       /**< RX FIFO overflow */
-        uint64_t reserved_27_31          : 5;
-        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
-        uint64_t reserved_23_25          : 3;
-        uint64_t loststat                : 1;       /**< TX Statistics data was over-written
-                                                         TX Stats are corrupted */
-        uint64_t reserved_4_21           : 18;
-        uint64_t out_ovr                 : 2;       /**< Outbound data FIFO overflow */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t out_ovr                 : 2;
-        uint64_t reserved_4_21           : 18;
-        uint64_t loststat                : 1;
-        uint64_t reserved_23_25          : 3;
-        uint64_t statovr                 : 1;
-        uint64_t reserved_27_31          : 5;
-        uint64_t ovrflw                  : 1;
-        uint64_t txpop                   : 1;
-        uint64_t txpsh                   : 1;
-        uint64_t ovrflw1                 : 1;
-        uint64_t txpop1                  : 1;
-        uint64_t txpsh1                  : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_agl_gmx_bad_reg_s        cn52xx;
-    struct cvmx_agl_gmx_bad_reg_s        cn52xxp1;
-    struct cvmx_agl_gmx_bad_reg_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_35_63          : 29;
-        uint64_t txpsh                   : 1;       /**< TX FIFO overflow */
-        uint64_t txpop                   : 1;       /**< TX FIFO underflow */
-        uint64_t ovrflw                  : 1;       /**< RX FIFO overflow */
-        uint64_t reserved_27_31          : 5;
-        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
-        uint64_t reserved_23_25          : 3;
-        uint64_t loststat                : 1;       /**< TX Statistics data was over-written
-                                                         TX Stats are corrupted */
-        uint64_t reserved_3_21           : 19;
-        uint64_t out_ovr                 : 1;       /**< Outbound data FIFO overflow */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t out_ovr                 : 1;
-        uint64_t reserved_3_21           : 19;
-        uint64_t loststat                : 1;
-        uint64_t reserved_23_25          : 3;
-        uint64_t statovr                 : 1;
-        uint64_t reserved_27_31          : 5;
-        uint64_t ovrflw                  : 1;
-        uint64_t txpop                   : 1;
-        uint64_t txpsh                   : 1;
-        uint64_t reserved_35_63          : 29;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_bad_reg_cn56xx   cn56xxp1;
-} cvmx_agl_gmx_bad_reg_t;
-
-
-/**
- * cvmx_agl_gmx_bist
- *
- * AGL_GMX_BIST = GMX BIST Results
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_bist_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t status                  : 10;      /**< BIST Results.
-                                                          HW sets a bit in BIST for for memory that fails
-                                                         - 0: gmx#.inb.drf64x78m1_bist
-                                                         - 1: gmx#.outb.fif.drf64x71m1_bist
-                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
-                                                         - 3: 0
-                                                         - 4: 0
-                                                         - 5: 0
-                                                         - 6: gmx#.csr.drf20x80m1_bist
-                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
-                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
-                                                         - 9: 0 */
-#else
-        uint64_t status                  : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_agl_gmx_bist_s           cn52xx;
-    struct cvmx_agl_gmx_bist_s           cn52xxp1;
-    struct cvmx_agl_gmx_bist_s           cn56xx;
-    struct cvmx_agl_gmx_bist_s           cn56xxp1;
-} cvmx_agl_gmx_bist_t;
-
-
-/**
- * cvmx_agl_gmx_drv_ctl
- *
- * AGL_GMX_DRV_CTL = GMX Drive Control
- *
- *
- * Notes:
- * NCTL, PCTL, BYP_EN    will be reset when MIX0_CTL[RESET] is set to 1.
- * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_drv_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t byp_en1                 : 1;       /**< Compensation Controller Bypass Enable (MII1) */
-        uint64_t reserved_45_47          : 3;
-        uint64_t pctl1                   : 5;       /**< AGL PCTL (MII1) */
-        uint64_t reserved_37_39          : 3;
-        uint64_t nctl1                   : 5;       /**< AGL NCTL (MII1) */
-        uint64_t reserved_17_31          : 15;
-        uint64_t byp_en                  : 1;       /**< Compensation Controller Bypass Enable */
-        uint64_t reserved_13_15          : 3;
-        uint64_t pctl                    : 5;       /**< AGL PCTL */
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 5;       /**< AGL NCTL */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t byp_en                  : 1;
-        uint64_t reserved_17_31          : 15;
-        uint64_t nctl1                   : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t pctl1                   : 5;
-        uint64_t reserved_45_47          : 3;
-        uint64_t byp_en1                 : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_agl_gmx_drv_ctl_s        cn52xx;
-    struct cvmx_agl_gmx_drv_ctl_s        cn52xxp1;
-    struct cvmx_agl_gmx_drv_ctl_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t byp_en                  : 1;       /**< Compensation Controller Bypass Enable */
-        uint64_t reserved_13_15          : 3;
-        uint64_t pctl                    : 5;       /**< AGL PCTL */
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 5;       /**< AGL NCTL */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t byp_en                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_drv_ctl_cn56xx   cn56xxp1;
-} cvmx_agl_gmx_drv_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_inf_mode
- *
- * AGL_GMX_INF_MODE = Interface Mode
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_inf_mode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t en                      : 1;       /**< Interface Enable */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_agl_gmx_inf_mode_s       cn52xx;
-    struct cvmx_agl_gmx_inf_mode_s       cn52xxp1;
-    struct cvmx_agl_gmx_inf_mode_s       cn56xx;
-    struct cvmx_agl_gmx_inf_mode_s       cn56xxp1;
-} cvmx_agl_gmx_inf_mode_t;
-
-
-/**
- * cvmx_agl_gmx_prt#_cfg
- *
- * AGL_GMX_PRT_CFG = Port description
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_prtx_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t tx_en                   : 1;       /**< Port enable.  Must be set for Octane to send
-                                                         RMGII traffic.   When this bit clear on a given
-                                                         port, then all MII cycles will appear as
-                                                         inter-frame cycles. */
-        uint64_t rx_en                   : 1;       /**< Port enable.  Must be set for Octane to receive
-                                                         RMGII traffic.  When this bit clear on a given
-                                                         port, then the all MII cycles will appear as
-                                                         inter-frame cycles. */
-        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
-                                                         0 = 512 bitimes (10/100Mbs operation)
-                                                         1 = Reserved */
-        uint64_t duplex                  : 1;       /**< Duplex
-                                                         0 = Half Duplex (collisions/extentions/bursts)
-                                                         1 = Full Duplex */
-        uint64_t speed                   : 1;       /**< Link Speed
-                                                         0 = 10/100Mbs operation
-                                                         1 = Reserved */
-        uint64_t en                      : 1;       /**< Link Enable
-                                                         When EN is clear, packets will not be received
-                                                         or transmitted (including PAUSE and JAM packets).
-                                                         If EN is cleared while a packet is currently
-                                                         being received or transmitted, the packet will
-                                                         be allowed to complete before the bus is idled.
-                                                         On the RX side, subsequent packets in a burst
-                                                         will be ignored. */
-#else
-        uint64_t en                      : 1;
-        uint64_t speed                   : 1;
-        uint64_t duplex                  : 1;
-        uint64_t slottime                : 1;
-        uint64_t rx_en                   : 1;
-        uint64_t tx_en                   : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_agl_gmx_prtx_cfg_s       cn52xx;
-    struct cvmx_agl_gmx_prtx_cfg_s       cn52xxp1;
-    struct cvmx_agl_gmx_prtx_cfg_s       cn56xx;
-    struct cvmx_agl_gmx_prtx_cfg_s       cn56xxp1;
-} cvmx_agl_gmx_prtx_cfg_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam0
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam0_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam1
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam1_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam2
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam2_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam3
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam3_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam4
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam4_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam5
- *
- * AGL_GMX_RX_ADR_CAM = Address Filtering Control
- *
- *
- * Notes:
- * Not reset when MIX*_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
-                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam5_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_cam_en
- *
- * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_cam_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t en                      : 8;       /**< CAM Entry Enables */
-#else
-        uint64_t en                      : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_cam_en_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_adr_ctl
- *
- * AGL_GMX_RX_ADR_CTL = Address Filtering Control
- *
- *
- * Notes:
- * * ALGORITHM
- *   Here is some pseudo code that represents the address filter behavior.
- * 
- *      @verbatim
- *      bool dmac_addr_filter(uint8 prt, uint48 dmac) [
- *        ASSERT(prt >= 0 && prt <= 3);
- *        if (is_bcst(dmac))                               // broadcast accept
- *          return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
- *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
- *          return REJECT;
- *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
- *          return ACCEPT;
- * 
- *        cam_hit = 0;
- * 
- *        for (i=0; i<8; i++) [
- *          if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
- *            continue;
- *          uint48 unswizzled_mac_adr = 0x0;
- *          for (j=5; j>=0; j--) [
- *             unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
- *          ]
- *          if (unswizzled_mac_adr == dmac) [
- *            cam_hit = 1;
- *            break;
- *          ]
- *        ]
- * 
- *        if (cam_hit)
- *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
- *        else
- *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
- *      ]
- *      @endverbatim
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_adr_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t cam_mode                : 1;       /**< Allow or deny DMAC address filter
-                                                         0 = reject the packet on DMAC address match
-                                                         1 = accept the packet on DMAC address match */
-        uint64_t mcst                    : 2;       /**< Multicast Mode
-                                                         0 = Use the Address Filter CAM
-                                                         1 = Force reject all multicast packets
-                                                         2 = Force accept all multicast packets
-                                                         3 = Reserved */
-        uint64_t bcst                    : 1;       /**< Accept All Broadcast Packets */
-#else
-        uint64_t bcst                    : 1;
-        uint64_t mcst                    : 2;
-        uint64_t cam_mode                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_adr_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_decision
- *
- * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
- *
- *
- * Notes:
- * As each byte in a packet is received by GMX, the L2 byte count is compared
- * against the AGL_GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
- * from the beginning of the L2 header (DMAC).  In normal operation, the L2
- * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any
- * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]).
- * 
- * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
- * packet and would require UDD skip length to account for them.
- * 
- *                                                 L2 Size
- * Port Mode             <=AGL_GMX_RX_DECISION bytes (default=24)  >AGL_GMX_RX_DECISION bytes (default=24)
- * 
- * MII/Full Duplex       accept packet                             apply filters
- *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
- * 
- * MII/Half Duplex       drop packet                               apply filters
- *                       packet is unconditionally dropped         accept packet based on DMAC
- * 
- * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_decision_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t cnt                     : 5;       /**< The byte count to decide when to accept or filter
-                                                         a packet. */
-#else
-        uint64_t cnt                     : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_decision_s   cn52xx;
-    struct cvmx_agl_gmx_rxx_decision_s   cn52xxp1;
-    struct cvmx_agl_gmx_rxx_decision_s   cn56xx;
-    struct cvmx_agl_gmx_rxx_decision_s   cn56xxp1;
-} cvmx_agl_gmx_rxx_decision_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_frm_chk
- *
- * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
- *
- *
- * Notes:
- * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_frm_chk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with MII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t reserved_1_1            : 1;
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_frm_chk_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_frm_chk_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_frm_chk_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_frm_chk_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_frm_chk_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_frm_ctl
- *
- * AGL_GMX_RX_FRM_CTL = Frame Control
- *
- *
- * Notes:
- * * PRE_CHK
- *   When set, the MII state expects a typical frame consisting of
- *   INTER_FRAME=>PREAMBLE(x7)=>SFD(x1)=>DAT.  The state machine watches for
- *   this exact sequence in order to recognize a valid frame and push frame
- *   data into the Octane.  There must be exactly 7 PREAMBLE cycles followed by
- *   the single SFD cycle for the frame to be accepted.
- * 
- *   When a problem does occur within the PREAMBLE seqeunce, the frame is
- *   marked as bad and not sent into the core.  The AGL_GMX_RX_INT_REG[PCTERR]
- *   interrupt is also raised.
- * 
- * * PRE_STRP
- *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
- *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
- *   core as part of the packet.
- * 
- *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
- *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
- *   are skipped when locating the start of the L2 header for DMAC and Control
- *   frame recognition.
- * 
- * * CTL_BCK/CTL_DRP
- *   These bits control how the HW handles incoming PAUSE packets.  Here are
- *   the most common modes of operation:
- *     CTL_BCK=1,CTL_DRP=1   - HW does it all
- *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
- *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
- * 
- *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
- *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
- *   would constitute an exception which should be handled by the processing
- *   cores.  PAUSE packets should not be forwarded.
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_frm_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
-                                                         regardless of the number of previous PREAMBLE
-                                                         nibbles.  In this mode, PREAMBLE can be consumed
-                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
-                                                         PRE_STRP must be set for correct operation.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
-                                                         sized pkts with padding in the client data */
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
-        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
-                                                         0 - 254 cycles of PREAMBLE followed by SFD
-                                                         PRE_FREE must be set if PRE_ALIGN is set.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped
-                                                         PRE_STRP must be set if PRE_ALIGN is set.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t pad_len                 : 1;
-        uint64_t pre_align               : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_frm_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_frm_max
- *
- * AGL_GMX_RX_FRM_MAX = Frame Max length
- *
- *
- * Notes:
- * When changing the LEN field, be sure that LEN does not exceed
- * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
- * are within the maximum length parameter to be rejected because they exceed
- * the AGL_GMX_RX_JABBER[CNT] limit.
- * 
- * Notes:
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_frm_max_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t len                     : 16;      /**< Byte count for Max-sized frame check
-                                                         Failing packets set the MAXERR interrupt and are
-                                                         optionally sent with opcode==MAXERR
-                                                         LEN <= AGL_GMX_RX_JABBER[CNT] */
-#else
-        uint64_t len                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_frm_max_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_frm_max_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_frm_max_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_frm_max_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_frm_max_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_frm_min
- *
- * AGL_GMX_RX_FRM_MIN = Frame Min length
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_frm_min_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t len                     : 16;      /**< Byte count for Min-sized frame check
-                                                         Failing packets set the MINERR interrupt and are
-                                                         optionally sent with opcode==MINERR */
-#else
-        uint64_t len                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_frm_min_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_frm_min_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_frm_min_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_frm_min_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_frm_min_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_ifg
- *
- * AGL_GMX_RX_IFG = RX Min IFG
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_ifg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ifg                     : 4;       /**< Min IFG between packets used to determine IFGERR */
-#else
-        uint64_t ifg                     : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_ifg_s        cn52xx;
-    struct cvmx_agl_gmx_rxx_ifg_s        cn52xxp1;
-    struct cvmx_agl_gmx_rxx_ifg_s        cn56xx;
-    struct cvmx_agl_gmx_rxx_ifg_s        cn56xxp1;
-} cvmx_agl_gmx_rxx_ifg_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_int_en
- *
- * AGL_GMX_RX_INT_EN = Interrupt Enable
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< MII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t reserved_1_1            : 1;
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_int_en_s     cn52xx;
-    struct cvmx_agl_gmx_rxx_int_en_s     cn52xxp1;
-    struct cvmx_agl_gmx_rxx_int_en_s     cn56xx;
-    struct cvmx_agl_gmx_rxx_int_en_s     cn56xxp1;
-} cvmx_agl_gmx_rxx_int_en_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_int_reg
- *
- * AGL_GMX_RX_INT_REG = Interrupt Register
- *
- *
- * Notes:
- * (1) exceptions will only be raised to the control processor if the
- *     corresponding bit in the AGL_GMX_RX_INT_EN register is set.
- * 
- * (2) exception conditions 10:0 can also set the rcv/opcode in the received
- *     packet's workQ entry.  The AGL_GMX_RX_FRM_CHK register provides a bit mask
- *     for configuring which conditions set the error.
- * 
- * (3) in half duplex operation, the expectation is that collisions will appear
- *     as MINERRs.
- * 
- * (4) JABBER - An RX Jabber error indicates that a packet was received which
- *              is longer than the maximum allowed packet as defined by the
- *              system.  GMX will truncate the packet at the JABBER count.
- *              Failure to do so could lead to system instabilty.
- * 
- * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
- *              AGL_GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
- *              > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
- * 
- * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN.
- * 
- * (8) ALNERR - Indicates that the packet received was not an integer number of
- *              bytes.  If FCS checking is enabled, ALNERR will only assert if
- *              the FCS is bad.  If FCS checking is disabled, ALNERR will
- *              assert in all non-integer frame cases.
- * 
- * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
- *                  is assumed by the receiver when the received
- *                  frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR
- * 
- * (A) LENERR - Length errors occur when the received packet does not match the
- *              length field.  LENERR is only checked for packets between 64
- *              and 1500 bytes.  For untagged frames, the length must exact
- *              match.  For tagged frames the length or length+4 must match.
- * 
- * (B) PCTERR - checks that the frame transtions from PREAMBLE=>SFD=>DATA.
- *              Does not check the number of PREAMBLE cycles.
- * 
- * (C) OVRERR - Not to be included in the HRM
- * 
- *              OVRERR is an architectural assertion check internal to GMX to
- *              make sure no assumption was violated.  In a correctly operating
- *              system, this interrupt can never fire.
- * 
- *              GMX has an internal arbiter which selects which of 4 ports to
- *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
- *              then each port will typically push a tick every 8 cycles - if
- *              the packet interface is going as fast as possible.  If there
- *              are four ports, they push every two cycles.  So that's the
- *              assumption.  That the inbound module will always be able to
- *              consume the tick before another is produced.  If that doesn't
- *              happen - that's when OVRERR will assert.
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< MII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with MII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t reserved_1_1            : 1;
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_int_reg_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_int_reg_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_int_reg_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_int_reg_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_int_reg_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_jabber
- *
- * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate
- *
- *
- * Notes:
- * CNT must be 8-byte aligned such that CNT[2:0] == 0
- * 
- *   The packet that will be sent to the packet input logic will have an
- *   additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and
- *   AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
- *   defined as...
- * 
- *        max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8)
- * 
- *   Be sure the CNT field value is at least as large as the
- *   AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause
- *   packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected
- *   because they exceed the CNT limit.
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_jabber_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt                     : 16;      /**< Byte count for jabber check
-                                                         Failing packets set the JABBER interrupt and are
-                                                         optionally sent with opcode==JABBER
-                                                         GMX will truncate the packet to CNT bytes
-                                                         CNT >= AGL_GMX_RX_FRM_MAX[LEN] */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_jabber_s     cn52xx;
-    struct cvmx_agl_gmx_rxx_jabber_s     cn52xxp1;
-    struct cvmx_agl_gmx_rxx_jabber_s     cn56xx;
-    struct cvmx_agl_gmx_rxx_jabber_s     cn56xxp1;
-} cvmx_agl_gmx_rxx_jabber_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_pause_drop_time
- *
- * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_pause_drop_time_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t status                  : 16;      /**< Time extracted from the dropped PAUSE packet */
-#else
-        uint64_t status                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
-    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
-    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
-} cvmx_agl_gmx_rxx_pause_drop_time_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_ctl
- *
- * AGL_GMX_RX_STATS_CTL = RX Stats Control register
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rd_clr                  : 1;       /**< RX Stats registers will clear on reads */
-#else
-        uint64_t rd_clr                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_octs
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_octs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of received good packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_octs_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_octs_ctl
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of received pause packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_octs_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_octs_dmac
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of filtered dmac packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_octs_dmac_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_octs_drp
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_octs_drp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of dropped packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_octs_drp_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_pkts
- *
- * AGL_GMX_RX_STATS_PKTS
- * 
- * Count of good received packets - packets that are not recognized as PAUSE
- * packets, dropped due the DMAC filter, dropped due FIFO full status, or
- * have any other OPCODE (FCS, Length, etc).
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_pkts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of received good packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_pkts_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_pkts_bad
- *
- * AGL_GMX_RX_STATS_PKTS_BAD
- * 
- * Count of all packets received with some error that were not dropped
- * either due to the dmac filter or lack of room in the receive FIFO.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of bad packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_pkts_bad_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_pkts_ctl
- *
- * AGL_GMX_RX_STATS_PKTS_CTL
- * 
- * Count of all packets received that were recognized as Flow Control or
- * PAUSE packets.  PAUSE packets with any kind of error are counted in
- * AGL_GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
- * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
- * increments regardless of whether the packet is dropped.  Pause packets
- * will never be counted in AGL_GMX_RX_STATS_PKTS.  Packets dropped due the dmac
- * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of received pause packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_pkts_dmac
- *
- * AGL_GMX_RX_STATS_PKTS_DMAC
- * 
- * Count of all packets received that were dropped by the dmac filter.
- * Packets that match the DMAC will be dropped and counted here regardless
- * of if they were bad packets.  These packets will never be counted in
- * AGL_GMX_RX_STATS_PKTS.
- * 
- * Some packets that were not able to satisify the DECISION_CNT may not
- * actually be dropped by Octeon, but they will be counted here as if they
- * were dropped.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of filtered dmac packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_stats_pkts_drp
- *
- * AGL_GMX_RX_STATS_PKTS_DRP
- * 
- * Count of all packets received that were dropped due to a full receive
- * FIFO.  This counts good and bad packets received - all packets dropped by
- * the FIFO.  It does not count packets dropped by the dmac or pause packet
- * filters.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of dropped packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
-    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
-    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
-} cvmx_agl_gmx_rxx_stats_pkts_drp_t;
-
-
-/**
- * cvmx_agl_gmx_rx#_udd_skp
- *
- * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
- *
- *
- * Notes:
- * (1) The skip bytes are part of the packet and will be sent down the NCB
- *     packet interface and will be handled by PKI.
- * 
- * (2) The system can determine if the UDD bytes are included in the FCS check
- *     by using the FCSSEL field - if the FCS check is enabled.
- * 
- * (3) Assume that the preamble/sfd is always at the start of the frame - even
- *     before UDD bytes.  In most cases, there will be no preamble in these
- *     cases since it will be MII to MII communication without a PHY
- *     involved.
- * 
- * (4) We can still do address filtering and control packet filtering is the
- *     user desires.
- * 
- * (5) UDD_SKP must be 0 in half-duplex operation unless
- *     AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear.  If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set,
- *     then UDD_SKP will normally be 8.
- * 
- * (6) In all cases, the UDD bytes will be sent down the packet interface as
- *     part of the packet.  The UDD bytes are never stripped from the actual
- *     packet.
- * 
- * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rxx_udd_skp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t fcssel                  : 1;       /**< Include the skip bytes in the FCS calculation
-                                                         0 = all skip bytes are included in FCS
-                                                         1 = the skip bytes are not included in FCS */
-        uint64_t reserved_7_7            : 1;
-        uint64_t len                     : 7;       /**< Amount of User-defined data before the start of
-                                                         the L2 data.  Zero means L2 comes first.
-                                                         Max value is 64. */
-#else
-        uint64_t len                     : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t fcssel                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rxx_udd_skp_s    cn52xx;
-    struct cvmx_agl_gmx_rxx_udd_skp_s    cn52xxp1;
-    struct cvmx_agl_gmx_rxx_udd_skp_s    cn56xx;
-    struct cvmx_agl_gmx_rxx_udd_skp_s    cn56xxp1;
-} cvmx_agl_gmx_rxx_udd_skp_t;
-
-
-/**
- * cvmx_agl_gmx_rx_bp_drop#
- *
- * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rx_bp_dropx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mark                    : 6;       /**< Number of 8B ticks to reserve in the RX FIFO.
-                                                         When the FIFO exceeds this count, packets will
-                                                         be dropped and not buffered.
-                                                         MARK should typically be programmed to 2.
-                                                         Failure to program correctly can lead to system
-                                                         instability. */
-#else
-        uint64_t mark                    : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rx_bp_dropx_s    cn52xx;
-    struct cvmx_agl_gmx_rx_bp_dropx_s    cn52xxp1;
-    struct cvmx_agl_gmx_rx_bp_dropx_s    cn56xx;
-    struct cvmx_agl_gmx_rx_bp_dropx_s    cn56xxp1;
-} cvmx_agl_gmx_rx_bp_dropx_t;
-
-
-/**
- * cvmx_agl_gmx_rx_bp_off#
- *
- * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rx_bp_offx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mark                    : 6;       /**< Water mark (8B ticks) to deassert backpressure */
-#else
-        uint64_t mark                    : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rx_bp_offx_s     cn52xx;
-    struct cvmx_agl_gmx_rx_bp_offx_s     cn52xxp1;
-    struct cvmx_agl_gmx_rx_bp_offx_s     cn56xx;
-    struct cvmx_agl_gmx_rx_bp_offx_s     cn56xxp1;
-} cvmx_agl_gmx_rx_bp_offx_t;
-
-
-/**
- * cvmx_agl_gmx_rx_bp_on#
- *
- * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rx_bp_onx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t mark                    : 9;       /**< Hiwater mark (8B ticks) for backpressure. */
-#else
-        uint64_t mark                    : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rx_bp_onx_s      cn52xx;
-    struct cvmx_agl_gmx_rx_bp_onx_s      cn52xxp1;
-    struct cvmx_agl_gmx_rx_bp_onx_s      cn56xx;
-    struct cvmx_agl_gmx_rx_bp_onx_s      cn56xxp1;
-} cvmx_agl_gmx_rx_bp_onx_t;
-
-
-/**
- * cvmx_agl_gmx_rx_prt_info
- *
- * AGL_GMX_RX_PRT_INFO = state information for the ports
- *
- *
- * Notes:
- * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rx_prt_info_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t drop                    : 2;       /**< Port indication that data was dropped */
-        uint64_t reserved_2_15           : 14;
-        uint64_t commit                  : 2;       /**< Port indication that SOP was accepted */
-#else
-        uint64_t commit                  : 2;
-        uint64_t reserved_2_15           : 14;
-        uint64_t drop                    : 2;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rx_prt_info_s    cn52xx;
-    struct cvmx_agl_gmx_rx_prt_info_s    cn52xxp1;
-    struct cvmx_agl_gmx_rx_prt_info_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t drop                    : 1;       /**< Port indication that data was dropped */
-        uint64_t reserved_1_15           : 15;
-        uint64_t commit                  : 1;       /**< Port indication that SOP was accepted */
-#else
-        uint64_t commit                  : 1;
-        uint64_t reserved_1_15           : 15;
-        uint64_t drop                    : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
-} cvmx_agl_gmx_rx_prt_info_t;
-
-
-/**
- * cvmx_agl_gmx_rx_tx_status
- *
- * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status
- *
- *
- * Notes:
- * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_rx_tx_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t tx                      : 2;       /**< Transmit data since last read */
-        uint64_t reserved_2_3            : 2;
-        uint64_t rx                      : 2;       /**< Receive data since last read */
-#else
-        uint64_t rx                      : 2;
-        uint64_t reserved_2_3            : 2;
-        uint64_t tx                      : 2;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_agl_gmx_rx_tx_status_s   cn52xx;
-    struct cvmx_agl_gmx_rx_tx_status_s   cn52xxp1;
-    struct cvmx_agl_gmx_rx_tx_status_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t tx                      : 1;       /**< Transmit data since last read */
-        uint64_t reserved_1_3            : 3;
-        uint64_t rx                      : 1;       /**< Receive data since last read */
-#else
-        uint64_t rx                      : 1;
-        uint64_t reserved_1_3            : 3;
-        uint64_t tx                      : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
-} cvmx_agl_gmx_rx_tx_status_t;
-
-
-/**
- * cvmx_agl_gmx_smac#
- *
- * AGL_GMX_SMAC = MII SMAC
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_smacx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t smac                    : 48;      /**< The SMAC field is used for generating and
-                                                         accepting Control Pause packets */
-#else
-        uint64_t smac                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_smacx_s          cn52xx;
-    struct cvmx_agl_gmx_smacx_s          cn52xxp1;
-    struct cvmx_agl_gmx_smacx_s          cn56xx;
-    struct cvmx_agl_gmx_smacx_s          cn56xxp1;
-} cvmx_agl_gmx_smacx_t;
-
-
-/**
- * cvmx_agl_gmx_stat_bp
- *
- * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_stat_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t bp                      : 1;       /**< Current BP state */
-        uint64_t cnt                     : 16;      /**< Number of cycles that BP has been asserted
-                                                         Saturating counter */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t bp                      : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_agl_gmx_stat_bp_s        cn52xx;
-    struct cvmx_agl_gmx_stat_bp_s        cn52xxp1;
-    struct cvmx_agl_gmx_stat_bp_s        cn56xx;
-    struct cvmx_agl_gmx_stat_bp_s        cn56xxp1;
-} cvmx_agl_gmx_stat_bp_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_append
- *
- * AGL_GMX_TX_APPEND = MII TX Append Control
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_append_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t force_fcs               : 1;       /**< Append the Ethernet FCS on each pause packet
-                                                         when FCS is clear.  Pause packets are normally
-                                                         padded to 60 bytes.  If
-                                                         AGL_GMX_TX_MIN_PKT[MIN_SIZE] exceeds 59, then
-                                                         FORCE_FCS will not be used. */
-        uint64_t fcs                     : 1;       /**< Append the Ethernet FCS on each packet */
-        uint64_t pad                     : 1;       /**< Append PAD bytes such that min sized */
-        uint64_t preamble                : 1;       /**< Prepend the Ethernet preamble on each transfer */
-#else
-        uint64_t preamble                : 1;
-        uint64_t pad                     : 1;
-        uint64_t fcs                     : 1;
-        uint64_t force_fcs               : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_append_s     cn52xx;
-    struct cvmx_agl_gmx_txx_append_s     cn52xxp1;
-    struct cvmx_agl_gmx_txx_append_s     cn56xx;
-    struct cvmx_agl_gmx_txx_append_s     cn56xxp1;
-} cvmx_agl_gmx_txx_append_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_ctl
- *
- * AGL_GMX_TX_CTL = TX Control register
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t xsdef_en                : 1;       /**< Enables the excessive deferral check for stats
-                                                         and interrupts */
-        uint64_t xscol_en                : 1;       /**< Enables the excessive collision check for stats
-                                                         and interrupts */
-#else
-        uint64_t xscol_en                : 1;
-        uint64_t xsdef_en                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_ctl_s        cn52xx;
-    struct cvmx_agl_gmx_txx_ctl_s        cn52xxp1;
-    struct cvmx_agl_gmx_txx_ctl_s        cn56xx;
-    struct cvmx_agl_gmx_txx_ctl_s        cn56xxp1;
-} cvmx_agl_gmx_txx_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_min_pkt
- *
- * AGL_GMX_TX_MIN_PKT = MII TX Min Size Packet (PAD upto min size)
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_min_pkt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t min_size                : 8;       /**< Min frame in bytes before the FCS is applied
-                                                         Padding is only appened when
-                                                         AGL_GMX_TX_APPEND[PAD] for the coresponding MII
-                                                         port is set. Packets will be padded to
-                                                         MIN_SIZE+1 The reset value will pad to 60 bytes. */
-#else
-        uint64_t min_size                : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_min_pkt_s    cn52xx;
-    struct cvmx_agl_gmx_txx_min_pkt_s    cn52xxp1;
-    struct cvmx_agl_gmx_txx_min_pkt_s    cn56xx;
-    struct cvmx_agl_gmx_txx_min_pkt_s    cn56xxp1;
-} cvmx_agl_gmx_txx_min_pkt_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_pause_pkt_interval
- *
- * AGL_GMX_TX_PAUSE_PKT_INTERVAL = MII TX Pause Packet transmission interval - how often PAUSE packets will be sent
- *
- *
- * Notes:
- * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
- * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
- * designer.  It is suggested that TIME be much greater than INTERVAL and
- * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
- * count and then when the backpressure condition is lifted, a PAUSE packet
- * with TIME==0 will be sent indicating that Octane is ready for additional
- * data.
- * 
- * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
- * suggested that TIME and INTERVAL are programmed such that they satisify the
- * following rule...
- * 
- *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
- * 
- * where largest_pkt_size is that largest packet that the system can send
- * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
- * of the PAUSE packet (normally 64B).
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_pause_pkt_interval_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t interval                : 16;      /**< Arbitrate for a pause packet every (INTERVAL*512)
-                                                         bit-times.
-                                                         Normally, 0 < INTERVAL < AGL_GMX_TX_PAUSE_PKT_TIME
-                                                         INTERVAL=0, will only send a single PAUSE packet
-                                                         for each backpressure event */
-#else
-        uint64_t interval                : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
-    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
-    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
-    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
-} cvmx_agl_gmx_txx_pause_pkt_interval_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_pause_pkt_time
- *
- * AGL_GMX_TX_PAUSE_PKT_TIME = MII TX Pause Packet pause_time field
- *
- *
- * Notes:
- * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
- * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
- * designer.  It is suggested that TIME be much greater than INTERVAL and
- * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
- * count and then when the backpressure condition is lifted, a PAUSE packet
- * with TIME==0 will be sent indicating that Octane is ready for additional
- * data.
- * 
- * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
- * suggested that TIME and INTERVAL are programmed such that they satisify the
- * following rule...
- * 
- *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
- * 
- * where largest_pkt_size is that largest packet that the system can send
- * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
- * of the PAUSE packet (normally 64B).
- * 
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_pause_pkt_time_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< The pause_time field placed is outbnd pause pkts
-                                                         pause_time is in 512 bit-times
-                                                         Normally, TIME > AGL_GMX_TX_PAUSE_PKT_INTERVAL */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
-    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
-    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
-    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
-} cvmx_agl_gmx_txx_pause_pkt_time_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_pause_togo
- *
- * AGL_GMX_TX_PAUSE_TOGO = MII TX Amount of time remaining to backpressure
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_pause_togo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
-    struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
-    struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
-    struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
-} cvmx_agl_gmx_txx_pause_togo_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_pause_zero
- *
- * AGL_GMX_TX_PAUSE_ZERO = MII TX Amount of time remaining to backpressure
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_pause_zero_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t send                    : 1;       /**< When backpressure condition clear, send PAUSE
-                                                         packet with pause_time of zero to enable the
-                                                         channel */
-#else
-        uint64_t send                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
-    struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
-    struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
-    struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
-} cvmx_agl_gmx_txx_pause_zero_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_soft_pause
- *
- * AGL_GMX_TX_SOFT_PAUSE = MII TX Software Pause
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_soft_pause_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< Back off the TX bus for (TIME*512) bit-times
-                                                         for full-duplex operation only */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
-    struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
-    struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
-    struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
-} cvmx_agl_gmx_txx_soft_pause_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat0
- *
- * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t xsdef                   : 32;      /**< Number of packets dropped (never successfully
-                                                         sent) due to excessive deferal */
-        uint64_t xscol                   : 32;      /**< Number of packets dropped (never successfully
-                                                         sent) due to excessive collision.  Defined by
-                                                         AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
-#else
-        uint64_t xscol                   : 32;
-        uint64_t xsdef                   : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat0_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat0_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat0_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat0_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat0_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat1
- *
- * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL  / AGL_GMX_TX_STATS_MCOL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t scol                    : 32;      /**< Number of packets sent with a single collision */
-        uint64_t mcol                    : 32;      /**< Number of packets sent with multiple collisions
-                                                         but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
-#else
-        uint64_t mcol                    : 32;
-        uint64_t scol                    : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat1_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat1_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat1_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat1_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat1_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat2
- *
- * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS
- *
- *
- * Notes:
- * - Octect counts are the sum of all data transmitted on the wire including
- *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
- *   counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t octs                    : 48;      /**< Number of total octets sent on the interface.
-                                                         Does not count octets from frames that were
-                                                         truncated due to collisions in halfdup mode. */
-#else
-        uint64_t octs                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat2_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat2_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat2_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat2_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat2_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat3
- *
- * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pkts                    : 32;      /**< Number of total frames sent on the interface.
-                                                         Does not count frames that were truncated due to
-                                                          collisions in halfdup mode. */
-#else
-        uint64_t pkts                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat3_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat3_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat3_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat3_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat3_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat4
- *
- * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist1                   : 32;      /**< Number of packets sent with an octet count of 64. */
-        uint64_t hist0                   : 32;      /**< Number of packets sent with an octet count
-                                                         of < 64. */
-#else
-        uint64_t hist0                   : 32;
-        uint64_t hist1                   : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat4_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat4_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat4_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat4_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat4_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat5
- *
- * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist3                   : 32;      /**< Number of packets sent with an octet count of
-                                                         128 - 255. */
-        uint64_t hist2                   : 32;      /**< Number of packets sent with an octet count of
-                                                         65 - 127. */
-#else
-        uint64_t hist2                   : 32;
-        uint64_t hist3                   : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat5_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat5_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat5_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat5_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat5_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat6
- *
- * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist5                   : 32;      /**< Number of packets sent with an octet count of
-                                                         512 - 1023. */
-        uint64_t hist4                   : 32;      /**< Number of packets sent with an octet count of
-                                                         256 - 511. */
-#else
-        uint64_t hist4                   : 32;
-        uint64_t hist5                   : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat6_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat6_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat6_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat6_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat6_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat7
- *
- * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist7                   : 32;      /**< Number of packets sent with an octet count
-                                                         of > 1518. */
-        uint64_t hist6                   : 32;      /**< Number of packets sent with an octet count of
-                                                         1024 - 1518. */
-#else
-        uint64_t hist6                   : 32;
-        uint64_t hist7                   : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat7_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat7_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat7_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat7_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat7_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat8
- *
- * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST  / AGL_GMX_TX_STATS_BCST
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
- *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
- *   as per the 802.3 frame definition.  If the system requires additional data
- *   before the L2 header, then the MCST and BCST counters may not reflect
- *   reality and should be ignored by software.
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat8_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mcst                    : 32;      /**< Number of packets sent to multicast DMAC.
-                                                         Does not include BCST packets. */
-        uint64_t bcst                    : 32;      /**< Number of packets sent to broadcast DMAC.
-                                                         Does not include MCST packets. */
-#else
-        uint64_t bcst                    : 32;
-        uint64_t mcst                    : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat8_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat8_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat8_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat8_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat8_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stat9
- *
- * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Not reset when MIX*_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stat9_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t undflw                  : 32;      /**< Number of underflow packets */
-        uint64_t ctl                     : 32;      /**< Number of Control packets (PAUSE flow control)
-                                                         generated by GMX.  It does not include control
-                                                         packets forwarded or generated by the PP's. */
-#else
-        uint64_t ctl                     : 32;
-        uint64_t undflw                  : 32;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stat9_s      cn52xx;
-    struct cvmx_agl_gmx_txx_stat9_s      cn52xxp1;
-    struct cvmx_agl_gmx_txx_stat9_s      cn56xx;
-    struct cvmx_agl_gmx_txx_stat9_s      cn56xxp1;
-} cvmx_agl_gmx_txx_stat9_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_stats_ctl
- *
- * AGL_GMX_TX_STATS_CTL = TX Stats Control register
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_stats_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rd_clr                  : 1;       /**< Stats registers will clear on reads */
-#else
-        uint64_t rd_clr                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_stats_ctl_s  cn52xx;
-    struct cvmx_agl_gmx_txx_stats_ctl_s  cn52xxp1;
-    struct cvmx_agl_gmx_txx_stats_ctl_s  cn56xx;
-    struct cvmx_agl_gmx_txx_stats_ctl_s  cn56xxp1;
-} cvmx_agl_gmx_txx_stats_ctl_t;
-
-
-/**
- * cvmx_agl_gmx_tx#_thresh
- *
- * AGL_GMX_TX_THRESH = MII TX Threshold
- *
- *
- * Notes:
- * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_txx_thresh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t cnt                     : 6;       /**< Number of 16B ticks to accumulate in the TX FIFO
-                                                         before sending on the MII interface
-                                                         This register should be large enough to prevent
-                                                         underflow on the MII interface and must never
-                                                         be set below 4.  This register cannot exceed the
-                                                         the TX FIFO depth which is 32 16B entries. */
-#else
-        uint64_t cnt                     : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_agl_gmx_txx_thresh_s     cn52xx;
-    struct cvmx_agl_gmx_txx_thresh_s     cn52xxp1;
-    struct cvmx_agl_gmx_txx_thresh_s     cn56xx;
-    struct cvmx_agl_gmx_txx_thresh_s     cn56xxp1;
-} cvmx_agl_gmx_txx_thresh_t;
-
-
-/**
- * cvmx_agl_gmx_tx_bp
- *
- * AGL_GMX_TX_BP = MII TX BackPressure Register
- *
- *
- * Notes:
- * BP[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * BP[1] will be reset when MIX1_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t bp                      : 2;       /**< Port BackPressure status
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-#else
-        uint64_t bp                      : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_bp_s          cn52xx;
-    struct cvmx_agl_gmx_tx_bp_s          cn52xxp1;
-    struct cvmx_agl_gmx_tx_bp_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t bp                      : 1;       /**< Port BackPressure status
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-#else
-        uint64_t bp                      : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_tx_bp_cn56xx     cn56xxp1;
-} cvmx_agl_gmx_tx_bp_t;
-
-
-/**
- * cvmx_agl_gmx_tx_col_attempt
- *
- * AGL_GMX_TX_COL_ATTEMPT = MII TX collision attempts before dropping frame
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_col_attempt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t limit                   : 5;       /**< Collision Attempts */
-#else
-        uint64_t limit                   : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
-    struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
-    struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
-    struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
-} cvmx_agl_gmx_tx_col_attempt_t;
-
-
-/**
- * cvmx_agl_gmx_tx_ifg
- *
- * Common
- * 
- * 
- * AGL_GMX_TX_IFG = MII TX Interframe Gap
- *
- * Notes:
- * Notes:
- * * Programming IFG1 and IFG2.
- * 
- *   For half-duplex systems that require IEEE 802.3 compatibility, IFG1 must
- *   be in the range of 1-8, IFG2 must be in the range of 4-12, and the
- *   IFG1+IFG2 sum must be 12.
- * 
- *   For full-duplex systems that require IEEE 802.3 compatibility, IFG1 must
- *   be in the range of 1-11, IFG2 must be in the range of 1-11, and the
- *   IFG1+IFG2 sum must be 12.
- * 
- *   For all other systems, IFG1 and IFG2 can be any value in the range of
- *   1-15.  Allowing for a total possible IFG sum of 2-30.
- * 
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_ifg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ifg2                    : 4;       /**< 1/3 of the interframe gap timing
-                                                         If CRS is detected during IFG2, then the
-                                                         interFrameSpacing timer is not reset and a frame
-                                                         is transmited once the timer expires. */
-        uint64_t ifg1                    : 4;       /**< 2/3 of the interframe gap timing
-                                                         If CRS is detected during IFG1, then the
-                                                         interFrameSpacing timer is reset and a frame is
-                                                         not transmited. */
-#else
-        uint64_t ifg1                    : 4;
-        uint64_t ifg2                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_ifg_s         cn52xx;
-    struct cvmx_agl_gmx_tx_ifg_s         cn52xxp1;
-    struct cvmx_agl_gmx_tx_ifg_s         cn56xx;
-    struct cvmx_agl_gmx_tx_ifg_s         cn56xxp1;
-} cvmx_agl_gmx_tx_ifg_t;
-
-
-/**
- * cvmx_agl_gmx_tx_int_en
- *
- * AGL_GMX_TX_INT_EN = Interrupt Enable
- *
- *
- * Notes:
- * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1] will be reset when MIX1_CTL[RESET] is set to 1.
- * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t late_col                : 2;       /**< TX Late Collision */
-        uint64_t reserved_14_15          : 2;
-        uint64_t xsdef                   : 2;       /**< TX Excessive deferral (MII/halfdup mode only) */
-        uint64_t reserved_10_11          : 2;
-        uint64_t xscol                   : 2;       /**< TX Excessive collisions (MII/halfdup mode only) */
-        uint64_t reserved_4_7            : 4;
-        uint64_t undflw                  : 2;       /**< TX Underflow (MII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 2;
-        uint64_t reserved_4_7            : 4;
-        uint64_t xscol                   : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t xsdef                   : 2;
-        uint64_t reserved_14_15          : 2;
-        uint64_t late_col                : 2;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_int_en_s      cn52xx;
-    struct cvmx_agl_gmx_tx_int_en_s      cn52xxp1;
-    struct cvmx_agl_gmx_tx_int_en_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t late_col                : 1;       /**< TX Late Collision */
-        uint64_t reserved_13_15          : 3;
-        uint64_t xsdef                   : 1;       /**< TX Excessive deferral (MII/halfdup mode only) */
-        uint64_t reserved_9_11           : 3;
-        uint64_t xscol                   : 1;       /**< TX Excessive collisions (MII/halfdup mode only) */
-        uint64_t reserved_3_7            : 5;
-        uint64_t undflw                  : 1;       /**< TX Underflow (MII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 1;
-        uint64_t reserved_3_7            : 5;
-        uint64_t xscol                   : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t xsdef                   : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t late_col                : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
-} cvmx_agl_gmx_tx_int_en_t;
-
-
-/**
- * cvmx_agl_gmx_tx_int_reg
- *
- * AGL_GMX_TX_INT_REG = Interrupt Register
- *
- *
- * Notes:
- * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1] will be reset when MIX1_CTL[RESET] is set to 1.
- * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t late_col                : 2;       /**< TX Late Collision */
-        uint64_t reserved_14_15          : 2;
-        uint64_t xsdef                   : 2;       /**< TX Excessive deferral (MII/halfdup mode only) */
-        uint64_t reserved_10_11          : 2;
-        uint64_t xscol                   : 2;       /**< TX Excessive collisions (MII/halfdup mode only) */
-        uint64_t reserved_4_7            : 4;
-        uint64_t undflw                  : 2;       /**< TX Underflow (MII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 2;
-        uint64_t reserved_4_7            : 4;
-        uint64_t xscol                   : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t xsdef                   : 2;
-        uint64_t reserved_14_15          : 2;
-        uint64_t late_col                : 2;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_int_reg_s     cn52xx;
-    struct cvmx_agl_gmx_tx_int_reg_s     cn52xxp1;
-    struct cvmx_agl_gmx_tx_int_reg_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t late_col                : 1;       /**< TX Late Collision */
-        uint64_t reserved_13_15          : 3;
-        uint64_t xsdef                   : 1;       /**< TX Excessive deferral (MII/halfdup mode only) */
-        uint64_t reserved_9_11           : 3;
-        uint64_t xscol                   : 1;       /**< TX Excessive collisions (MII/halfdup mode only) */
-        uint64_t reserved_3_7            : 5;
-        uint64_t undflw                  : 1;       /**< TX Underflow (MII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 1;
-        uint64_t reserved_3_7            : 5;
-        uint64_t xscol                   : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t xsdef                   : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t late_col                : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
-} cvmx_agl_gmx_tx_int_reg_t;
-
-
-/**
- * cvmx_agl_gmx_tx_jam
- *
- * AGL_GMX_TX_JAM = MII TX Jam Pattern
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_jam_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t jam                     : 8;       /**< Jam pattern */
-#else
-        uint64_t jam                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_jam_s         cn52xx;
-    struct cvmx_agl_gmx_tx_jam_s         cn52xxp1;
-    struct cvmx_agl_gmx_tx_jam_s         cn56xx;
-    struct cvmx_agl_gmx_tx_jam_s         cn56xxp1;
-} cvmx_agl_gmx_tx_jam_t;
-
-
-/**
- * cvmx_agl_gmx_tx_lfsr
- *
- * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_lfsr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t lfsr                    : 16;      /**< The current state of the LFSR used to feed random
-                                                         numbers to compute truncated binary exponential
-                                                         backoff. */
-#else
-        uint64_t lfsr                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_lfsr_s        cn52xx;
-    struct cvmx_agl_gmx_tx_lfsr_s        cn52xxp1;
-    struct cvmx_agl_gmx_tx_lfsr_s        cn56xx;
-    struct cvmx_agl_gmx_tx_lfsr_s        cn56xxp1;
-} cvmx_agl_gmx_tx_lfsr_t;
-
-
-/**
- * cvmx_agl_gmx_tx_ovr_bp
- *
- * AGL_GMX_TX_OVR_BP = MII TX Override BackPressure
- *
- *
- * Notes:
- * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.
- * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_ovr_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t en                      : 2;       /**< Per port Enable back pressure override */
-        uint64_t reserved_6_7            : 2;
-        uint64_t bp                      : 2;       /**< Port BackPressure status to use
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t reserved_2_3            : 2;
-        uint64_t ign_full                : 2;       /**< Ignore the RX FIFO full when computing BP */
-#else
-        uint64_t ign_full                : 2;
-        uint64_t reserved_2_3            : 2;
-        uint64_t bp                      : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t en                      : 2;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_ovr_bp_s      cn52xx;
-    struct cvmx_agl_gmx_tx_ovr_bp_s      cn52xxp1;
-    struct cvmx_agl_gmx_tx_ovr_bp_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t en                      : 1;       /**< Per port Enable back pressure override */
-        uint64_t reserved_5_7            : 3;
-        uint64_t bp                      : 1;       /**< Port BackPressure status to use
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t reserved_1_3            : 3;
-        uint64_t ign_full                : 1;       /**< Ignore the RX FIFO full when computing BP */
-#else
-        uint64_t ign_full                : 1;
-        uint64_t reserved_1_3            : 3;
-        uint64_t bp                      : 1;
-        uint64_t reserved_5_7            : 3;
-        uint64_t en                      : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn56xx;
-    struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
-} cvmx_agl_gmx_tx_ovr_bp_t;
-
-
-/**
- * cvmx_agl_gmx_tx_pause_pkt_dmac
- *
- * AGL_GMX_TX_PAUSE_PKT_DMAC = MII TX Pause Packet DMAC field
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t dmac                    : 48;      /**< The DMAC field placed is outbnd pause pkts */
-#else
-        uint64_t dmac                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
-    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
-    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
-    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
-} cvmx_agl_gmx_tx_pause_pkt_dmac_t;
-
-
-/**
- * cvmx_agl_gmx_tx_pause_pkt_type
- *
- * AGL_GMX_TX_PAUSE_PKT_TYPE = MII TX Pause Packet TYPE field
- *
- *
- * Notes:
- * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_agl_gmx_tx_pause_pkt_type_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t type                    : 16;      /**< The TYPE field placed is outbnd pause pkts */
-#else
-        uint64_t type                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
-    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
-    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
-    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
-} cvmx_agl_gmx_tx_pause_pkt_type_t;
-
-
-/**
- * cvmx_asx#_gmii_rx_clk_set
- *
- * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_gmii_rx_clk_set_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< Setting to place on the RXCLK (GMII receive clk)
-                                                         delay line.  The intrinsic delay can range from
-                                                         50ps to 80ps per tap. */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_gmii_rx_clk_set_s   cn30xx;
-    struct cvmx_asxx_gmii_rx_clk_set_s   cn31xx;
-    struct cvmx_asxx_gmii_rx_clk_set_s   cn50xx;
-} cvmx_asxx_gmii_rx_clk_set_t;
-
-
-/**
- * cvmx_asx#_gmii_rx_dat_set
- *
- * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_gmii_rx_dat_set_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< Setting to place on the RXD (GMII receive data)
-                                                         delay lines.  The intrinsic delay can range from
-                                                         50ps to 80ps per tap. */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_gmii_rx_dat_set_s   cn30xx;
-    struct cvmx_asxx_gmii_rx_dat_set_s   cn31xx;
-    struct cvmx_asxx_gmii_rx_dat_set_s   cn50xx;
-} cvmx_asxx_gmii_rx_dat_set_t;
-
-
-/**
- * cvmx_asx#_int_en
- *
- * ASX_INT_EN = Interrupt Enable
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t txpsh                   : 4;       /**< TX FIFO overflow on RMGII port */
-        uint64_t txpop                   : 4;       /**< TX FIFO underflow on RMGII port */
-        uint64_t ovrflw                  : 4;       /**< RX FIFO overflow on RMGII port */
-#else
-        uint64_t ovrflw                  : 4;
-        uint64_t txpop                   : 4;
-        uint64_t txpsh                   : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_asxx_int_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t txpsh                   : 3;       /**< TX FIFO overflow on RMGII port */
-        uint64_t reserved_7_7            : 1;
-        uint64_t txpop                   : 3;       /**< TX FIFO underflow on RMGII port */
-        uint64_t reserved_3_3            : 1;
-        uint64_t ovrflw                  : 3;       /**< RX FIFO overflow on RMGII port */
-#else
-        uint64_t ovrflw                  : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t txpop                   : 3;
-        uint64_t reserved_7_7            : 1;
-        uint64_t txpsh                   : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_int_en_cn30xx       cn31xx;
-    struct cvmx_asxx_int_en_s            cn38xx;
-    struct cvmx_asxx_int_en_s            cn38xxp2;
-    struct cvmx_asxx_int_en_cn30xx       cn50xx;
-    struct cvmx_asxx_int_en_s            cn58xx;
-    struct cvmx_asxx_int_en_s            cn58xxp1;
-} cvmx_asxx_int_en_t;
-
-
-/**
- * cvmx_asx#_int_reg
- *
- * ASX_INT_REG = Interrupt Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t txpsh                   : 4;       /**< TX FIFO overflow on RMGII port */
-        uint64_t txpop                   : 4;       /**< TX FIFO underflow on RMGII port */
-        uint64_t ovrflw                  : 4;       /**< RX FIFO overflow on RMGII port */
-#else
-        uint64_t ovrflw                  : 4;
-        uint64_t txpop                   : 4;
-        uint64_t txpsh                   : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_asxx_int_reg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t txpsh                   : 3;       /**< TX FIFO overflow on RMGII port */
-        uint64_t reserved_7_7            : 1;
-        uint64_t txpop                   : 3;       /**< TX FIFO underflow on RMGII port */
-        uint64_t reserved_3_3            : 1;
-        uint64_t ovrflw                  : 3;       /**< RX FIFO overflow on RMGII port */
-#else
-        uint64_t ovrflw                  : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t txpop                   : 3;
-        uint64_t reserved_7_7            : 1;
-        uint64_t txpsh                   : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_int_reg_cn30xx      cn31xx;
-    struct cvmx_asxx_int_reg_s           cn38xx;
-    struct cvmx_asxx_int_reg_s           cn38xxp2;
-    struct cvmx_asxx_int_reg_cn30xx      cn50xx;
-    struct cvmx_asxx_int_reg_s           cn58xx;
-    struct cvmx_asxx_int_reg_s           cn58xxp1;
-} cvmx_asxx_int_reg_t;
-
-
-/**
- * cvmx_asx#_mii_rx_dat_set
- *
- * ASX_MII_RX_DAT_SET = GMII Clock delay setting
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_mii_rx_dat_set_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< Setting to place on the RXD (MII receive data)
-                                                         delay lines.  The intrinsic delay can range from
-                                                         50ps to 80ps per tap. */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_mii_rx_dat_set_s    cn30xx;
-    struct cvmx_asxx_mii_rx_dat_set_s    cn50xx;
-} cvmx_asxx_mii_rx_dat_set_t;
-
-
-/**
- * cvmx_asx#_prt_loop
- *
- * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_prt_loop_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ext_loop                : 4;       /**< External Loopback Enable
-                                                         0 = No Loopback (TX FIFO is filled by RMGII)
-                                                         1 = RX FIFO drives the TX FIFO
-                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
-                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
-                                                             - core clock > 250MHZ
-                                                             - rxc must not deviate from the +-50ppm
-                                                             - if txc>rxc, idle cycle may drop over time */
-        uint64_t int_loop                : 4;       /**< Internal Loopback Enable
-                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
-                                                         1 = TX FIFO drives the RX FIFO
-                                                         Note, in internal loop-back mode, the RGMII link
-                                                         status is not used (since there is no real PHY).
-                                                         Software cannot use the inband status. */
-#else
-        uint64_t int_loop                : 4;
-        uint64_t ext_loop                : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_asxx_prt_loop_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t ext_loop                : 3;       /**< External Loopback Enable
-                                                         0 = No Loopback (TX FIFO is filled by RMGII)
-                                                         1 = RX FIFO drives the TX FIFO
-                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
-                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
-                                                             - core clock > 250MHZ
-                                                             - rxc must not deviate from the +-50ppm
-                                                             - if txc>rxc, idle cycle may drop over time */
-        uint64_t reserved_3_3            : 1;
-        uint64_t int_loop                : 3;       /**< Internal Loopback Enable
-                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
-                                                         1 = TX FIFO drives the RX FIFO
-                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
-                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
-                                                             - GMX_TX_CLK[CLK_CNT] must be 1
-                                                         Note, in internal loop-back mode, the RGMII link
-                                                         status is not used (since there is no real PHY).
-                                                         Software cannot use the inband status. */
-#else
-        uint64_t int_loop                : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t ext_loop                : 3;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_prt_loop_cn30xx     cn31xx;
-    struct cvmx_asxx_prt_loop_s          cn38xx;
-    struct cvmx_asxx_prt_loop_s          cn38xxp2;
-    struct cvmx_asxx_prt_loop_cn30xx     cn50xx;
-    struct cvmx_asxx_prt_loop_s          cn58xx;
-    struct cvmx_asxx_prt_loop_s          cn58xxp1;
-} cvmx_asxx_prt_loop_t;
-
-
-/**
- * cvmx_asx#_rld_bypass
- *
- * ASX_RLD_BYPASS
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_bypass_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t bypass                  : 1;       /**< When set, the rld_dll setting is bypassed with
-                                                         ASX_RLD_BYPASS_SETTING */
-#else
-        uint64_t bypass                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_asxx_rld_bypass_s        cn38xx;
-    struct cvmx_asxx_rld_bypass_s        cn38xxp2;
-    struct cvmx_asxx_rld_bypass_s        cn58xx;
-    struct cvmx_asxx_rld_bypass_s        cn58xxp1;
-} cvmx_asxx_rld_bypass_t;
-
-
-/**
- * cvmx_asx#_rld_bypass_setting
- *
- * ASX_RLD_BYPASS_SETTING
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_bypass_setting_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< The rld_dll setting bypass value */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rld_bypass_setting_s cn38xx;
-    struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
-    struct cvmx_asxx_rld_bypass_setting_s cn58xx;
-    struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
-} cvmx_asxx_rld_bypass_setting_t;
-
-
-/**
- * cvmx_asx#_rld_comp
- *
- * ASX_RLD_COMP
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_comp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t pctl                    : 5;       /**< PCTL Compensation Value
-                                                         These bits reflect the computed compensation
-                                                          values from the built-in compensation circuit. */
-        uint64_t nctl                    : 4;       /**< These bits reflect the computed compensation
-                                                         values from the built-in compensation circuit. */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_asxx_rld_comp_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t pctl                    : 4;       /**< These bits reflect the computed compensation
-                                                         values from the built-in compensation circuit. */
-        uint64_t nctl                    : 4;       /**< These bits reflect the computed compensation
-                                                         values from the built-in compensation circuit. */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } cn38xx;
-    struct cvmx_asxx_rld_comp_cn38xx     cn38xxp2;
-    struct cvmx_asxx_rld_comp_s          cn58xx;
-    struct cvmx_asxx_rld_comp_s          cn58xxp1;
-} cvmx_asxx_rld_comp_t;
-
-
-/**
- * cvmx_asx#_rld_data_drv
- *
- * ASX_RLD_DATA_DRV
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_data_drv_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t pctl                    : 4;       /**< These bits specify a driving strength (positive
-                                                         integer) for the RLD I/Os when the built-in
-                                                         compensation circuit is bypassed. */
-        uint64_t nctl                    : 4;       /**< These bits specify a driving strength (positive
-                                                         integer) for the RLD I/Os when the built-in
-                                                         compensation circuit is bypassed. */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_asxx_rld_data_drv_s      cn38xx;
-    struct cvmx_asxx_rld_data_drv_s      cn38xxp2;
-    struct cvmx_asxx_rld_data_drv_s      cn58xx;
-    struct cvmx_asxx_rld_data_drv_s      cn58xxp1;
-} cvmx_asxx_rld_data_drv_t;
-
-
-/**
- * cvmx_asx#_rld_fcram_mode
- *
- * ASX_RLD_FCRAM_MODE
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_fcram_mode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t mode                    : 1;       /**< Memory Mode
-                                                         - 0: RLDRAM
-                                                         - 1: FCRAM */
-#else
-        uint64_t mode                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_asxx_rld_fcram_mode_s    cn38xx;
-    struct cvmx_asxx_rld_fcram_mode_s    cn38xxp2;
-} cvmx_asxx_rld_fcram_mode_t;
-
-
-/**
- * cvmx_asx#_rld_nctl_strong
- *
- * ASX_RLD_NCTL_STRONG
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_nctl_strong_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t nctl                    : 5;       /**< Duke's drive control */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rld_nctl_strong_s   cn38xx;
-    struct cvmx_asxx_rld_nctl_strong_s   cn38xxp2;
-    struct cvmx_asxx_rld_nctl_strong_s   cn58xx;
-    struct cvmx_asxx_rld_nctl_strong_s   cn58xxp1;
-} cvmx_asxx_rld_nctl_strong_t;
-
-
-/**
- * cvmx_asx#_rld_nctl_weak
- *
- * ASX_RLD_NCTL_WEAK
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_nctl_weak_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t nctl                    : 5;       /**< UNUSED (not needed for O9N) */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rld_nctl_weak_s     cn38xx;
-    struct cvmx_asxx_rld_nctl_weak_s     cn38xxp2;
-    struct cvmx_asxx_rld_nctl_weak_s     cn58xx;
-    struct cvmx_asxx_rld_nctl_weak_s     cn58xxp1;
-} cvmx_asxx_rld_nctl_weak_t;
-
-
-/**
- * cvmx_asx#_rld_pctl_strong
- *
- * ASX_RLD_PCTL_STRONG
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_pctl_strong_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t pctl                    : 5;       /**< Duke's drive control */
-#else
-        uint64_t pctl                    : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rld_pctl_strong_s   cn38xx;
-    struct cvmx_asxx_rld_pctl_strong_s   cn38xxp2;
-    struct cvmx_asxx_rld_pctl_strong_s   cn58xx;
-    struct cvmx_asxx_rld_pctl_strong_s   cn58xxp1;
-} cvmx_asxx_rld_pctl_strong_t;
-
-
-/**
- * cvmx_asx#_rld_pctl_weak
- *
- * ASX_RLD_PCTL_WEAK
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_pctl_weak_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t pctl                    : 5;       /**< UNUSED (not needed for O9N) */
-#else
-        uint64_t pctl                    : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rld_pctl_weak_s     cn38xx;
-    struct cvmx_asxx_rld_pctl_weak_s     cn38xxp2;
-    struct cvmx_asxx_rld_pctl_weak_s     cn58xx;
-    struct cvmx_asxx_rld_pctl_weak_s     cn58xxp1;
-} cvmx_asxx_rld_pctl_weak_t;
-
-
-/**
- * cvmx_asx#_rld_setting
- *
- * ASX_RLD_SETTING
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rld_setting_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t dfaset                  : 5;       /**< RLD ClkGen DLL Setting(debug)
-                                                         ** NEW O9N ** */
-        uint64_t dfalag                  : 1;       /**< RLD ClkGen DLL Lag Error(debug)
-                                                         ** NEW O9N ** */
-        uint64_t dfalead                 : 1;       /**< RLD ClkGen DLL Lead Error(debug)
-                                                         ** NEW O9N ** */
-        uint64_t dfalock                 : 1;       /**< RLD ClkGen DLL Lock acquisition(debug)
-                                                         ** NEW O9N ** */
-        uint64_t setting                 : 5;       /**< RLDCK90 DLL Setting(debug) */
-#else
-        uint64_t setting                 : 5;
-        uint64_t dfalock                 : 1;
-        uint64_t dfalead                 : 1;
-        uint64_t dfalag                  : 1;
-        uint64_t dfaset                  : 5;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_asxx_rld_setting_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< This is the read-only true rld dll_setting. */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn38xx;
-    struct cvmx_asxx_rld_setting_cn38xx  cn38xxp2;
-    struct cvmx_asxx_rld_setting_s       cn58xx;
-    struct cvmx_asxx_rld_setting_s       cn58xxp1;
-} cvmx_asxx_rld_setting_t;
-
-
-/**
- * cvmx_asx#_rx_clk_set#
- *
- * ASX_RX_CLK_SET = RGMII Clock delay setting
- *
- *
- * Notes:
- * Setting to place on the open-loop RXC (RGMII receive clk)
- * delay line, which can delay the recieved clock. This
- * can be used if the board and/or transmitting device
- * has not otherwise delayed the clock.
- * 
- * A value of SETTING=0 disables the delay line. The delay
- * line should be disabled unless the transmitter or board
- * does not delay the clock.
- * 
- * Note that this delay line provides only a coarse control
- * over the delay. Generally, it can only reliably provide
- * a delay in the range 1.25-2.5ns, which may not be adequate
- * for some system applications.
- * 
- * The open loop delay line selects
- * from among a series of tap positions. Each incremental
- * tap position adds a delay of 50ps to 135ps per tap, depending
- * on the chip, its temperature, and the voltage.
- * To achieve from 1.25-2.5ns of delay on the recieved
- * clock, a fixed value of SETTING=24 may work.
- * For more precision, we recommend the following settings
- * based on the chip voltage:
- * 
- *    VDD           SETTING
- *  -----------------------------
- *    1.0             18
- *    1.05            19
- *    1.1             21
- *    1.15            22
- *    1.2             23
- *    1.25            24
- *    1.3             25
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_clk_setx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< Setting to place on the open-loop RXC delay line */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_rx_clk_setx_s       cn30xx;
-    struct cvmx_asxx_rx_clk_setx_s       cn31xx;
-    struct cvmx_asxx_rx_clk_setx_s       cn38xx;
-    struct cvmx_asxx_rx_clk_setx_s       cn38xxp2;
-    struct cvmx_asxx_rx_clk_setx_s       cn50xx;
-    struct cvmx_asxx_rx_clk_setx_s       cn58xx;
-    struct cvmx_asxx_rx_clk_setx_s       cn58xxp1;
-} cvmx_asxx_rx_clk_setx_t;
-
-
-/**
- * cvmx_asx#_rx_prt_en
- *
- * ASX_RX_PRT_EN = RGMII Port Enable
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_prt_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t prt_en                  : 4;       /**< Port enable.  Must be set for Octane to receive
-                                                         RMGII traffic.  When this bit clear on a given
-                                                         port, then the all RGMII cycles will appear as
-                                                         inter-frame cycles. */
-#else
-        uint64_t prt_en                  : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_asxx_rx_prt_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t prt_en                  : 3;       /**< Port enable.  Must be set for Octane to receive
-                                                         RMGII traffic.  When this bit clear on a given
-                                                         port, then the all RGMII cycles will appear as
-                                                         inter-frame cycles. */
-#else
-        uint64_t prt_en                  : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_rx_prt_en_cn30xx    cn31xx;
-    struct cvmx_asxx_rx_prt_en_s         cn38xx;
-    struct cvmx_asxx_rx_prt_en_s         cn38xxp2;
-    struct cvmx_asxx_rx_prt_en_cn30xx    cn50xx;
-    struct cvmx_asxx_rx_prt_en_s         cn58xx;
-    struct cvmx_asxx_rx_prt_en_s         cn58xxp1;
-} cvmx_asxx_rx_prt_en_t;
-
-
-/**
- * cvmx_asx#_rx_wol
- *
- * ASX_RX_WOL = RGMII RX Wake on LAN status register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_wol_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t status                  : 1;       /**< Copy of PMCSR[15] - PME_status */
-        uint64_t enable                  : 1;       /**< Copy of PMCSR[8]  - PME_enable */
-#else
-        uint64_t enable                  : 1;
-        uint64_t status                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_asxx_rx_wol_s            cn38xx;
-    struct cvmx_asxx_rx_wol_s            cn38xxp2;
-} cvmx_asxx_rx_wol_t;
-
-
-/**
- * cvmx_asx#_rx_wol_msk
- *
- * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_wol_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t msk                     : 64;      /**< Bytes to include in the CRC signature */
-#else
-        uint64_t msk                     : 64;
-#endif
-    } s;
-    struct cvmx_asxx_rx_wol_msk_s        cn38xx;
-    struct cvmx_asxx_rx_wol_msk_s        cn38xxp2;
-} cvmx_asxx_rx_wol_msk_t;
-
-
-/**
- * cvmx_asx#_rx_wol_powok
- *
- * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_wol_powok_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t powerok                 : 1;       /**< Power OK */
-#else
-        uint64_t powerok                 : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_asxx_rx_wol_powok_s      cn38xx;
-    struct cvmx_asxx_rx_wol_powok_s      cn38xxp2;
-} cvmx_asxx_rx_wol_powok_t;
-
-
-/**
- * cvmx_asx#_rx_wol_sig
- *
- * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_rx_wol_sig_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t sig                     : 32;      /**< CRC signature */
-#else
-        uint64_t sig                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_asxx_rx_wol_sig_s        cn38xx;
-    struct cvmx_asxx_rx_wol_sig_s        cn38xxp2;
-} cvmx_asxx_rx_wol_sig_t;
-
-
-/**
- * cvmx_asx#_tx_clk_set#
- *
- * ASX_TX_CLK_SET = RGMII Clock delay setting
- *
- *
- * Notes:
- * Setting to place on the open-loop TXC (RGMII transmit clk)
- * delay line, which can delay the transmited clock. This
- * can be used if the board and/or transmitting device
- * has not otherwise delayed the clock.
- * 
- * A value of SETTING=0 disables the delay line. The delay
- * line should be disabled unless the transmitter or board
- * does not delay the clock.
- * 
- * Note that this delay line provides only a coarse control
- * over the delay. Generally, it can only reliably provide
- * a delay in the range 1.25-2.5ns, which may not be adequate
- * for some system applications.
- * 
- * The open loop delay line selects
- * from among a series of tap positions. Each incremental
- * tap position adds a delay of 50ps to 135ps per tap, depending
- * on the chip, its temperature, and the voltage.
- * To achieve from 1.25-2.5ns of delay on the recieved
- * clock, a fixed value of SETTING=24 may work.
- * For more precision, we recommend the following settings
- * based on the chip voltage:
- * 
- *    VDD           SETTING
- *  -----------------------------
- *    1.0             18
- *    1.05            19
- *    1.1             21
- *    1.15            22
- *    1.2             23
- *    1.25            24
- *    1.3             25
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_tx_clk_setx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t setting                 : 5;       /**< Setting to place on the open-loop TXC delay line */
-#else
-        uint64_t setting                 : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_asxx_tx_clk_setx_s       cn30xx;
-    struct cvmx_asxx_tx_clk_setx_s       cn31xx;
-    struct cvmx_asxx_tx_clk_setx_s       cn38xx;
-    struct cvmx_asxx_tx_clk_setx_s       cn38xxp2;
-    struct cvmx_asxx_tx_clk_setx_s       cn50xx;
-    struct cvmx_asxx_tx_clk_setx_s       cn58xx;
-    struct cvmx_asxx_tx_clk_setx_s       cn58xxp1;
-} cvmx_asxx_tx_clk_setx_t;
-
-
-/**
- * cvmx_asx#_tx_comp_byp
- *
- * ASX_TX_COMP_BYP = RGMII Clock delay setting
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_tx_comp_byp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_asxx_tx_comp_byp_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t bypass                  : 1;       /**< Compensation bypass */
-        uint64_t pctl                    : 4;       /**< PCTL Compensation Value (see Duke) */
-        uint64_t nctl                    : 4;       /**< NCTL Compensation Value (see Duke) */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 4;
-        uint64_t bypass                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_tx_comp_byp_cn30xx  cn31xx;
-    struct cvmx_asxx_tx_comp_byp_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t pctl                    : 4;       /**< PCTL Compensation Value (see Duke) */
-        uint64_t nctl                    : 4;       /**< NCTL Compensation Value (see Duke) */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } cn38xx;
-    struct cvmx_asxx_tx_comp_byp_cn38xx  cn38xxp2;
-    struct cvmx_asxx_tx_comp_byp_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t bypass                  : 1;       /**< Compensation bypass */
-        uint64_t reserved_13_15          : 3;
-        uint64_t pctl                    : 5;       /**< PCTL Compensation Value (see Duke) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 5;       /**< NCTL Compensation Value (see Duke) */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t bypass                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn50xx;
-    struct cvmx_asxx_tx_comp_byp_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t pctl                    : 5;       /**< PCTL Compensation Value (see Duke) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 5;       /**< NCTL Compensation Value (see Duke) */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn58xx;
-    struct cvmx_asxx_tx_comp_byp_cn58xx  cn58xxp1;
-} cvmx_asxx_tx_comp_byp_t;
-
-
-/**
- * cvmx_asx#_tx_hi_water#
- *
- * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_tx_hi_waterx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t mark                    : 4;       /**< TX FIFO HiWatermark to stall GMX
-                                                         Value of 0 maps to 16
-                                                         Reset value changed from 10 in pass1
-                                                         Pass1 settings (assuming 125 tclk)
-                                                         - 325-375: 12
-                                                         - 375-437: 11
-                                                         - 437-550: 10
-                                                         - 550-687:  9 */
-#else
-        uint64_t mark                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_asxx_tx_hi_waterx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t mark                    : 3;       /**< TX FIFO HiWatermark to stall GMX
-                                                         Value 0 maps to 8. */
-#else
-        uint64_t mark                    : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
-    struct cvmx_asxx_tx_hi_waterx_s      cn38xx;
-    struct cvmx_asxx_tx_hi_waterx_s      cn38xxp2;
-    struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
-    struct cvmx_asxx_tx_hi_waterx_s      cn58xx;
-    struct cvmx_asxx_tx_hi_waterx_s      cn58xxp1;
-} cvmx_asxx_tx_hi_waterx_t;
-
-
-/**
- * cvmx_asx#_tx_prt_en
- *
- * ASX_TX_PRT_EN = RGMII Port Enable
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asxx_tx_prt_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t prt_en                  : 4;       /**< Port enable.  Must be set for Octane to send
-                                                         RMGII traffic.   When this bit clear on a given
-                                                         port, then all RGMII cycles will appear as
-                                                         inter-frame cycles. */
-#else
-        uint64_t prt_en                  : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_asxx_tx_prt_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t prt_en                  : 3;       /**< Port enable.  Must be set for Octane to send
-                                                         RMGII traffic.   When this bit clear on a given
-                                                         port, then all RGMII cycles will appear as
-                                                         inter-frame cycles. */
-#else
-        uint64_t prt_en                  : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_asxx_tx_prt_en_cn30xx    cn31xx;
-    struct cvmx_asxx_tx_prt_en_s         cn38xx;
-    struct cvmx_asxx_tx_prt_en_s         cn38xxp2;
-    struct cvmx_asxx_tx_prt_en_cn30xx    cn50xx;
-    struct cvmx_asxx_tx_prt_en_s         cn58xx;
-    struct cvmx_asxx_tx_prt_en_s         cn58xxp1;
-} cvmx_asxx_tx_prt_en_t;
-
-
-/**
- * cvmx_asx0_dbg_data_drv
- *
- * ASX_DBG_DATA_DRV
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asx0_dbg_data_drv_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t pctl                    : 5;       /**< These bits control the driving strength of the dbg
-                                                         interface. */
-        uint64_t nctl                    : 4;       /**< These bits control the driving strength of the dbg
-                                                         interface. */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_asx0_dbg_data_drv_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t pctl                    : 4;       /**< These bits control the driving strength of the dbg
-                                                         interface. */
-        uint64_t nctl                    : 4;       /**< These bits control the driving strength of the dbg
-                                                         interface. */
-#else
-        uint64_t nctl                    : 4;
-        uint64_t pctl                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } cn38xx;
-    struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2;
-    struct cvmx_asx0_dbg_data_drv_s      cn58xx;
-    struct cvmx_asx0_dbg_data_drv_s      cn58xxp1;
-} cvmx_asx0_dbg_data_drv_t;
-
-
-/**
- * cvmx_asx0_dbg_data_enable
- *
- * ASX_DBG_DATA_ENABLE
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_asx0_dbg_data_enable_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t en                      : 1;       /**< A 1->0 transistion, turns the dbg interface OFF. */
-#else
-        uint64_t en                      : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_asx0_dbg_data_enable_s   cn38xx;
-    struct cvmx_asx0_dbg_data_enable_s   cn38xxp2;
-    struct cvmx_asx0_dbg_data_enable_s   cn58xx;
-    struct cvmx_asx0_dbg_data_enable_s   cn58xxp1;
-} cvmx_asx0_dbg_data_enable_t;
-
-
-/**
- * cvmx_ciu_bist
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_bist_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t bist                    : 4;       /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         BIST. */
-#else
-        uint64_t bist                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_ciu_bist_s               cn30xx;
-    struct cvmx_ciu_bist_s               cn31xx;
-    struct cvmx_ciu_bist_s               cn38xx;
-    struct cvmx_ciu_bist_s               cn38xxp2;
-    struct cvmx_ciu_bist_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t bist                    : 2;       /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         BIST. */
-#else
-        uint64_t bist                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn50xx;
-    struct cvmx_ciu_bist_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t bist                    : 3;       /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         BIST. */
-#else
-        uint64_t bist                    : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_bist_cn52xx          cn52xxp1;
-    struct cvmx_ciu_bist_s               cn56xx;
-    struct cvmx_ciu_bist_s               cn56xxp1;
-    struct cvmx_ciu_bist_s               cn58xx;
-    struct cvmx_ciu_bist_s               cn58xxp1;
-} cvmx_ciu_bist_t;
-
-
-/**
- * cvmx_ciu_dint
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_dint_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dint                    : 16;      /**< Send DINT pulse to PP vector */
-#else
-        uint64_t dint                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ciu_dint_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t dint                    : 1;       /**< Send DINT pulse to PP vector */
-#else
-        uint64_t dint                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_dint_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dint                    : 2;       /**< Send DINT pulse to PP vector */
-#else
-        uint64_t dint                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_dint_s               cn38xx;
-    struct cvmx_ciu_dint_s               cn38xxp2;
-    struct cvmx_ciu_dint_cn31xx          cn50xx;
-    struct cvmx_ciu_dint_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t dint                    : 4;       /**< Send DINT pulse to PP vector */
-#else
-        uint64_t dint                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_dint_cn52xx          cn52xxp1;
-    struct cvmx_ciu_dint_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t dint                    : 12;      /**< Send DINT pulse to PP vector */
-#else
-        uint64_t dint                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_dint_cn56xx          cn56xxp1;
-    struct cvmx_ciu_dint_s               cn58xx;
-    struct cvmx_ciu_dint_s               cn58xxp1;
-} cvmx_ciu_dint_t;
-
-
-/**
- * cvmx_ciu_fuse
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_fuse_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t fuse                    : 16;      /**< Physical PP is present */
-#else
-        uint64_t fuse                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ciu_fuse_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t fuse                    : 1;       /**< Physical PP is present */
-#else
-        uint64_t fuse                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_fuse_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t fuse                    : 2;       /**< Physical PP is present */
-#else
-        uint64_t fuse                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_fuse_s               cn38xx;
-    struct cvmx_ciu_fuse_s               cn38xxp2;
-    struct cvmx_ciu_fuse_cn31xx          cn50xx;
-    struct cvmx_ciu_fuse_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t fuse                    : 4;       /**< Physical PP is present */
-#else
-        uint64_t fuse                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_fuse_cn52xx          cn52xxp1;
-    struct cvmx_ciu_fuse_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t fuse                    : 12;      /**< Physical PP is present */
-#else
-        uint64_t fuse                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_fuse_cn56xx          cn56xxp1;
-    struct cvmx_ciu_fuse_s               cn58xx;
-    struct cvmx_ciu_fuse_s               cn58xxp1;
-} cvmx_ciu_fuse_t;
-
-
-/**
- * cvmx_ciu_gstop
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_gstop_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t gstop                   : 1;       /**< GSTOP bit */
-#else
-        uint64_t gstop                   : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_ciu_gstop_s              cn30xx;
-    struct cvmx_ciu_gstop_s              cn31xx;
-    struct cvmx_ciu_gstop_s              cn38xx;
-    struct cvmx_ciu_gstop_s              cn38xxp2;
-    struct cvmx_ciu_gstop_s              cn50xx;
-    struct cvmx_ciu_gstop_s              cn52xx;
-    struct cvmx_ciu_gstop_s              cn52xxp1;
-    struct cvmx_ciu_gstop_s              cn56xx;
-    struct cvmx_ciu_gstop_s              cn56xxp1;
-    struct cvmx_ciu_gstop_s              cn58xx;
-    struct cvmx_ciu_gstop_s              cn58xxp1;
-} cvmx_ciu_gstop_t;
-
-
-/**
- * cvmx_ciu_int#_en0
- *
- * Notes:
- * CIU_INT0_EN0:  PP0 /IP2
- * CIU_INT1_EN0:  PP0 /IP3
- * ...
- * CIU_INT6_EN0:  PP3/IP2
- * CIU_INT7_EN0:  PP3/IP3
- * (hole)
- * CIU_INT32_EN0: PCI /IP
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t reserved_47_47          : 1;
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t reserved_47_47          : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_intx_en0_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_intx_en0_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn38xx;
-    struct cvmx_ciu_intx_en0_cn38xx      cn38xxp2;
-    struct cvmx_ciu_intx_en0_cn30xx      cn50xx;
-    struct cvmx_ciu_intx_en0_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en0_cn52xx      cn52xxp1;
-    struct cvmx_ciu_intx_en0_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en0_cn56xx      cn56xxp1;
-    struct cvmx_ciu_intx_en0_cn38xx      cn58xx;
-    struct cvmx_ciu_intx_en0_cn38xx      cn58xxp1;
-} cvmx_ciu_intx_en0_t;
-
-
-/**
- * cvmx_ciu_int#_en0_w1c
- *
- * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN0 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en0_w1c_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en0_w1c_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en0_w1c_s       cn56xx;
-    struct cvmx_ciu_intx_en0_w1c_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en0_w1c_t;
-
-
-/**
- * cvmx_ciu_int#_en0_w1s
- *
- * Notes:
- * Write-1-to-set version of the CIU_INTx_EN0 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en0_w1s_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en0_w1s_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en0_w1s_s       cn56xx;
-    struct cvmx_ciu_intx_en0_w1s_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en0_w1s_t;
-
-
-/**
- * cvmx_ciu_int#_en1
- *
- * Notes:
- * @verbatim
- * PPx/IP2 will be raised when...
- * 
- *    n = x*2
- *    PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
- * 
- * PPx/IP3 will be raised when...
- * 
- *    n = x*2 + 1
- *    PPx/IP3 =  |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
- * 
- * PCI/INT will be raised when...
- * 
- *    PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0])
- * @endverbatim
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en1_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t wdog                    : 1;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_intx_en1_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t wdog                    : 2;       /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_intx_en1_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_ciu_intx_en1_cn38xx      cn38xxp2;
-    struct cvmx_ciu_intx_en1_cn31xx      cn50xx;
-    struct cvmx_ciu_intx_en1_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en1_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn52xxp1;
-    struct cvmx_ciu_intx_en1_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en1_cn56xx      cn56xxp1;
-    struct cvmx_ciu_intx_en1_cn38xx      cn58xx;
-    struct cvmx_ciu_intx_en1_cn38xx      cn58xxp1;
-} cvmx_ciu_intx_en1_t;
-
-
-/**
- * cvmx_ciu_int#_en1_w1c
- *
- * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN1 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en1_w1c_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en1_w1c_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en1_w1c_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en1_w1c_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en1_w1c_t;
-
-
-/**
- * cvmx_ciu_int#_en1_w1s
- *
- * Notes:
- * Write-1-to-set version of the CIU_INTx_EN1 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en1_w1s_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en1_w1s_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en1_w1s_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en1_w1s_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en1_w1s_t;
-
-
-/**
- * cvmx_ciu_int#_en4_0
- *
- * Notes:
- * CIU_INT0_EN4_0:   PP0  /IP4
- * CIU_INT1_EN4_0:   PP1  /IP4
- * ...
- * CIU_INT11_EN4_0:  PP11 /IP4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_0_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t reserved_47_47          : 1;
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t reserved_47_47          : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn50xx;
-    struct cvmx_ciu_intx_en4_0_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_0_cn52xx    cn52xxp1;
-    struct cvmx_ciu_intx_en4_0_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en4_0_cn56xx    cn56xxp1;
-    struct cvmx_ciu_intx_en4_0_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-    struct cvmx_ciu_intx_en4_0_cn58xx    cn58xxp1;
-} cvmx_ciu_intx_en4_0_t;
-
-
-/**
- * cvmx_ciu_int#_en4_0_w1c
- *
- * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_0 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_0_w1c_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_0_w1c_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_0_w1c_s     cn56xx;
-    struct cvmx_ciu_intx_en4_0_w1c_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en4_0_w1c_t;
-
-
-/**
- * cvmx_ciu_int#_en4_0_w1s
- *
- * Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_0 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_0_w1s_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_0_w1s_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_0_w1s_s     cn56xx;
-    struct cvmx_ciu_intx_en4_0_w1s_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t reserved_44_44          : 1;
-        uint64_t pci_msi                 : 4;       /**< PCI MSI */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t reserved_44_44          : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en4_0_w1s_t;
-
-
-/**
- * cvmx_ciu_int#_en4_1
- *
- * Notes:
- * PPx/IP4 will be raised when...
- * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_1_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t wdog                    : 2;       /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn50xx;
-    struct cvmx_ciu_intx_en4_1_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_1_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn52xxp1;
-    struct cvmx_ciu_intx_en4_1_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en4_1_cn56xx    cn56xxp1;
-    struct cvmx_ciu_intx_en4_1_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn58xx;
-    struct cvmx_ciu_intx_en4_1_cn58xx    cn58xxp1;
-} cvmx_ciu_intx_en4_1_t;
-
-
-/**
- * cvmx_ciu_int#_en4_1_w1c
- *
- * Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_1 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_1_w1c_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_1_w1c_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_1_w1c_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en4_1_w1c_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en4_1_w1c_t;
-
-
-/**
- * cvmx_ciu_int#_en4_1_w1s
- *
- * Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_1 register
- * (Pass2 ONLY)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_en4_1_w1s_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_intx_en4_1_w1s_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_en4_1_w1s_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_en4_1_w1s_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn58xx;
-} cvmx_ciu_intx_en4_1_w1s_t;
-
-
-/**
- * cvmx_ciu_int#_sum0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_sum0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM0 where x=0-31.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_sum0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t reserved_47_47          : 1;
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM0 where x=0-1.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t reserved_47_47          : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_intx_sum0_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM0 where x=0-3.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_intx_sum0_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM0 where x=0-31.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn38xx;
-    struct cvmx_ciu_intx_sum0_cn38xx     cn38xxp2;
-    struct cvmx_ciu_intx_sum0_cn30xx     cn50xx;
-    struct cvmx_ciu_intx_sum0_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< SUM1&EN1 summary bit
-                                                         This read-only bit reads as a one whenever any
-                                                         CIU_INT_SUM1 bit is set and corresponding
-                                                         enable bit in CIU_INTx_EN is set, where x
-                                                         is the same as x in this CIU_INTx_SUM0.
-                                                         PPs use CIU_INTx_SUM0 where x=0-7.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3
-                                                         Note that WDOG_SUM only summarizes the SUM/EN1
-                                                         result and does not have a corresponding enable
-                                                         bit, so does not directly contribute to
-                                                         interrupts. */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         Refer to "Receiving Message-Signalled
-                                                         Interrupts" in the PCIe chapter of the spec */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
-                                                         Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the PCIe chapter of the spec */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-7
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_sum0_cn52xx     cn52xxp1;
-    struct cvmx_ciu_intx_sum0_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM0 where x=0-23.
-                                                         PCI uses the CIU_INTx_SUM0 where x=32.
-                                                         Even INTx registers report WDOG to IP2
-                                                         Odd INTx registers report WDOG to IP3 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         Refer to "Receiving Message-Signalled
-                                                         Interrupts" in the PCIe chapter of the spec */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
-                                                         Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the PCIe chapter of the spec */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-23
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_sum0_cn56xx     cn56xxp1;
-    struct cvmx_ciu_intx_sum0_cn38xx     cn58xx;
-    struct cvmx_ciu_intx_sum0_cn38xx     cn58xxp1;
-} cvmx_ciu_intx_sum0_t;
-
-
-/**
- * cvmx_ciu_int#_sum4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_intx_sum4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         These registers report WDOG to IP4 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_intx_sum4_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
-        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
-        uint64_t usb                     : 1;       /**< USB interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t reserved_47_47          : 1;
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         PPs use CIU_INTx_SUM4 where x=0-1. */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t reserved_47_47          : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t pcm                     : 1;
-        uint64_t mpi                     : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } cn50xx;
-    struct cvmx_ciu_intx_sum4_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t reserved_51_51          : 1;
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t reserved_49_49          : 1;
-        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< SUM1&EN4_1 summary bit
-                                                         This read-only bit reads as a one whenever any
-                                                         CIU_INT_SUM1 bit is set and corresponding
-                                                         enable bit in CIU_INTx_EN4_1 is set, where x
-                                                         is the same as x in this CIU_INTx_SUM4.
-                                                         PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
-                                                         Note that WDOG_SUM only summarizes the SUM/EN4_1
-                                                         result and does not have a corresponding enable
-                                                         bit, so does not directly contribute to
-                                                         interrupts. */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         Refer to "Receiving Message-Signalled
-                                                         Interrupts" in the PCIe chapter of the spec */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
-                                                         Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the PCIe chapter of the spec */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-3
-                                                         [33] is the or of <31:16>
-                                                         [32] is the or of <15:0> */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 1;
-        uint64_t reserved_49_49          : 1;
-        uint64_t ipd_drp                 : 1;
-        uint64_t reserved_51_51          : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_intx_sum4_cn52xx     cn52xxp1;
-    struct cvmx_ciu_intx_sum4_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
-        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
-        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
-        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
-        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
-        uint64_t reserved_57_58          : 2;
-        uint64_t usb                     : 1;       /**< USB Interrupt */
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         These registers report WDOG to IP4 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         Refer to "Receiving Message-Signalled
-                                                         Interrupts" in the PCIe chapter of the spec */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
-                                                         Refer to "Receiving Emulated INTA/INTB/
-                                                         INTC/INTD" in the PCIe chapter of the spec */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-11
-                                                         [33] is the or of <31:16>
-                                                         [32] is the or of <15:0> */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t usb                     : 1;
-        uint64_t reserved_57_58          : 2;
-        uint64_t twsi2                   : 1;
-        uint64_t powiq                   : 1;
-        uint64_t ipdppthr                : 1;
-        uint64_t mii                     : 1;
-        uint64_t bootdma                 : 1;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_intx_sum4_cn56xx     cn56xxp1;
-    struct cvmx_ciu_intx_sum4_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t timer                   : 4;       /**< General timer interrupts */
-        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
-                                                         KEY_ZERO will be set when the external ZERO_KEYS
-                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
-        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
-        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
-        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
-        uint64_t rml                     : 1;       /**< RML Interrupt */
-        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
-        uint64_t wdog_sum                : 1;       /**< Watchdog summary
-                                                         These registers report WDOG to IP4 */
-        uint64_t pci_msi                 : 4;       /**< PCI MSI
-                                                         [43] is the or of <63:48>
-                                                         [42] is the or of <47:32>
-                                                         [41] is the or of <31:16>
-                                                         [40] is the or of <15:0> */
-        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
-        uint64_t uart                    : 2;       /**< Two UART interrupts */
-        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
-                                                          [33] is the or of <31:16>
-                                                          [32] is the or of <15:0>
-                                                         Two PCI internal interrupts for entry 32
-                                                          CIU_PCI_INTA */
-        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
-        uint64_t workq                   : 16;      /**< 16 work queue interrupts
-                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
-#else
-        uint64_t workq                   : 16;
-        uint64_t gpio                    : 16;
-        uint64_t mbox                    : 2;
-        uint64_t uart                    : 2;
-        uint64_t pci_int                 : 4;
-        uint64_t pci_msi                 : 4;
-        uint64_t wdog_sum                : 1;
-        uint64_t twsi                    : 1;
-        uint64_t rml                     : 1;
-        uint64_t trace                   : 1;
-        uint64_t gmx_drp                 : 2;
-        uint64_t ipd_drp                 : 1;
-        uint64_t key_zero                : 1;
-        uint64_t timer                   : 4;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn58xx;
-    struct cvmx_ciu_intx_sum4_cn58xx     cn58xxp1;
-} cvmx_ciu_intx_sum4_t;
-
-
-/**
- * cvmx_ciu_int_sum1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_int_sum1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t wdog                    : 16;      /**< 16 watchdog interrupts */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_ciu_int_sum1_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t wdog                    : 1;       /**< 1 watchdog interrupt */
-#else
-        uint64_t wdog                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_int_sum1_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t wdog                    : 2;       /**< 2 watchdog interrupts */
-#else
-        uint64_t wdog                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_int_sum1_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t wdog                    : 16;      /**< 16 watchdog interrupts */
-#else
-        uint64_t wdog                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_ciu_int_sum1_cn38xx      cn38xxp2;
-    struct cvmx_ciu_int_sum1_cn31xx      cn50xx;
-    struct cvmx_ciu_int_sum1_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t nand                    : 1;       /**< NAND Flash Controller */
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< 4 watchdog interrupts */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t nand                    : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_int_sum1_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
-        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
-        uint64_t uart2                   : 1;       /**< Third UART interrupt */
-        uint64_t reserved_4_15           : 12;
-        uint64_t wdog                    : 4;       /**< 4 watchdog interrupts */
-#else
-        uint64_t wdog                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t uart2                   : 1;
-        uint64_t usb1                    : 1;
-        uint64_t mii1                    : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn52xxp1;
-    struct cvmx_ciu_int_sum1_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t wdog                    : 12;      /**< 12 watchdog interrupts */
-#else
-        uint64_t wdog                    : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_int_sum1_cn56xx      cn56xxp1;
-    struct cvmx_ciu_int_sum1_cn38xx      cn58xx;
-    struct cvmx_ciu_int_sum1_cn38xx      cn58xxp1;
-} cvmx_ciu_int_sum1_t;
-
-
-/**
- * cvmx_ciu_mbox_clr#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_mbox_clrx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bits                    : 32;      /**< On writes, clr corresponding bit in MBOX register
-                                                         on reads, return the MBOX register */
-#else
-        uint64_t bits                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_ciu_mbox_clrx_s          cn30xx;
-    struct cvmx_ciu_mbox_clrx_s          cn31xx;
-    struct cvmx_ciu_mbox_clrx_s          cn38xx;
-    struct cvmx_ciu_mbox_clrx_s          cn38xxp2;
-    struct cvmx_ciu_mbox_clrx_s          cn50xx;
-    struct cvmx_ciu_mbox_clrx_s          cn52xx;
-    struct cvmx_ciu_mbox_clrx_s          cn52xxp1;
-    struct cvmx_ciu_mbox_clrx_s          cn56xx;
-    struct cvmx_ciu_mbox_clrx_s          cn56xxp1;
-    struct cvmx_ciu_mbox_clrx_s          cn58xx;
-    struct cvmx_ciu_mbox_clrx_s          cn58xxp1;
-} cvmx_ciu_mbox_clrx_t;
-
-
-/**
- * cvmx_ciu_mbox_set#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_mbox_setx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bits                    : 32;      /**< On writes, set corresponding bit in MBOX register
-                                                         on reads, return the MBOX register */
-#else
-        uint64_t bits                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_ciu_mbox_setx_s          cn30xx;
-    struct cvmx_ciu_mbox_setx_s          cn31xx;
-    struct cvmx_ciu_mbox_setx_s          cn38xx;
-    struct cvmx_ciu_mbox_setx_s          cn38xxp2;
-    struct cvmx_ciu_mbox_setx_s          cn50xx;
-    struct cvmx_ciu_mbox_setx_s          cn52xx;
-    struct cvmx_ciu_mbox_setx_s          cn52xxp1;
-    struct cvmx_ciu_mbox_setx_s          cn56xx;
-    struct cvmx_ciu_mbox_setx_s          cn56xxp1;
-    struct cvmx_ciu_mbox_setx_s          cn58xx;
-    struct cvmx_ciu_mbox_setx_s          cn58xxp1;
-} cvmx_ciu_mbox_setx_t;
-
-
-/**
- * cvmx_ciu_nmi
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_nmi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t nmi                     : 16;      /**< Send NMI pulse to PP vector */
-#else
-        uint64_t nmi                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ciu_nmi_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t nmi                     : 1;       /**< Send NMI pulse to PP vector */
-#else
-        uint64_t nmi                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_nmi_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t nmi                     : 2;       /**< Send NMI pulse to PP vector */
-#else
-        uint64_t nmi                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_nmi_s                cn38xx;
-    struct cvmx_ciu_nmi_s                cn38xxp2;
-    struct cvmx_ciu_nmi_cn31xx           cn50xx;
-    struct cvmx_ciu_nmi_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t nmi                     : 4;       /**< Send NMI pulse to PP vector */
-#else
-        uint64_t nmi                     : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_nmi_cn52xx           cn52xxp1;
-    struct cvmx_ciu_nmi_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t nmi                     : 12;      /**< Send NMI pulse to PP vector */
-#else
-        uint64_t nmi                     : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_nmi_cn56xx           cn56xxp1;
-    struct cvmx_ciu_nmi_s                cn58xx;
-    struct cvmx_ciu_nmi_s                cn58xxp1;
-} cvmx_ciu_nmi_t;
-
-
-/**
- * cvmx_ciu_pci_inta
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_pci_inta_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t intr                    : 2;       /**< PCI interrupt
-                                                         These bits are observed in CIU_INT32_SUM0<33:32> */
-#else
-        uint64_t intr                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_ciu_pci_inta_s           cn30xx;
-    struct cvmx_ciu_pci_inta_s           cn31xx;
-    struct cvmx_ciu_pci_inta_s           cn38xx;
-    struct cvmx_ciu_pci_inta_s           cn38xxp2;
-    struct cvmx_ciu_pci_inta_s           cn50xx;
-    struct cvmx_ciu_pci_inta_s           cn52xx;
-    struct cvmx_ciu_pci_inta_s           cn52xxp1;
-    struct cvmx_ciu_pci_inta_s           cn56xx;
-    struct cvmx_ciu_pci_inta_s           cn56xxp1;
-    struct cvmx_ciu_pci_inta_s           cn58xx;
-    struct cvmx_ciu_pci_inta_s           cn58xxp1;
-} cvmx_ciu_pci_inta_t;
-
-
-/**
- * cvmx_ciu_pp_dbg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_pp_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ppdbg                   : 16;      /**< Debug[DM] value for each PP
-                                                         whether the PP's are in debug mode or not */
-#else
-        uint64_t ppdbg                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ciu_pp_dbg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t ppdbg                   : 1;       /**< Debug[DM] value for each PP
-                                                         whether the PP's are in debug mode or not */
-#else
-        uint64_t ppdbg                   : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_pp_dbg_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t ppdbg                   : 2;       /**< Debug[DM] value for each PP
-                                                         whether the PP's are in debug mode or not */
-#else
-        uint64_t ppdbg                   : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_pp_dbg_s             cn38xx;
-    struct cvmx_ciu_pp_dbg_s             cn38xxp2;
-    struct cvmx_ciu_pp_dbg_cn31xx        cn50xx;
-    struct cvmx_ciu_pp_dbg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ppdbg                   : 4;       /**< Debug[DM] value for each PP
-                                                         whether the PP's are in debug mode or not */
-#else
-        uint64_t ppdbg                   : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_pp_dbg_cn52xx        cn52xxp1;
-    struct cvmx_ciu_pp_dbg_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t ppdbg                   : 12;      /**< Debug[DM] value for each PP
-                                                         whether the PP's are in debug mode or not */
-#else
-        uint64_t ppdbg                   : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_pp_dbg_cn56xx        cn56xxp1;
-    struct cvmx_ciu_pp_dbg_s             cn58xx;
-    struct cvmx_ciu_pp_dbg_s             cn58xxp1;
-} cvmx_ciu_pp_dbg_t;
-
-
-/**
- * cvmx_ciu_pp_poke#
- *
- * Notes:
- * Any write to a CIU_PP_POKE register clears any pending interrupt generated
- * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set
- * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8).
- * 
- * Reads to this register will return the associated CIU_WDOG register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_pp_pokex_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t poke                    : 64;      /**< Reserved */
-#else
-        uint64_t poke                    : 64;
-#endif
-    } s;
-    struct cvmx_ciu_pp_pokex_s           cn30xx;
-    struct cvmx_ciu_pp_pokex_s           cn31xx;
-    struct cvmx_ciu_pp_pokex_s           cn38xx;
-    struct cvmx_ciu_pp_pokex_s           cn38xxp2;
-    struct cvmx_ciu_pp_pokex_s           cn50xx;
-    struct cvmx_ciu_pp_pokex_s           cn52xx;
-    struct cvmx_ciu_pp_pokex_s           cn52xxp1;
-    struct cvmx_ciu_pp_pokex_s           cn56xx;
-    struct cvmx_ciu_pp_pokex_s           cn56xxp1;
-    struct cvmx_ciu_pp_pokex_s           cn58xx;
-    struct cvmx_ciu_pp_pokex_s           cn58xxp1;
-} cvmx_ciu_pp_pokex_t;
-
-
-/**
- * cvmx_ciu_pp_rst
- *
- * Contains the reset control for each PP.  Value of '1' will hold a PP in reset, '0' will release.
- * Resets to 0xffff when PCI boot is enabled, 0xfffe otherwise.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_pp_rst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t rst                     : 15;      /**< PP Rst for PP's 15-1 */
-        uint64_t rst0                    : 1;       /**< PP Rst for PP0
-                                                         depends on standalone mode */
-#else
-        uint64_t rst0                    : 1;
-        uint64_t rst                     : 15;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ciu_pp_rst_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rst0                    : 1;       /**< PP Rst for PP0
-                                                         depends on standalone mode */
-#else
-        uint64_t rst0                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn30xx;
-    struct cvmx_ciu_pp_rst_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t rst                     : 1;       /**< PP Rst for PP1 */
-        uint64_t rst0                    : 1;       /**< PP Rst for PP0
-                                                         depends on standalone mode */
-#else
-        uint64_t rst0                    : 1;
-        uint64_t rst                     : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_ciu_pp_rst_s             cn38xx;
-    struct cvmx_ciu_pp_rst_s             cn38xxp2;
-    struct cvmx_ciu_pp_rst_cn31xx        cn50xx;
-    struct cvmx_ciu_pp_rst_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t rst                     : 3;       /**< PP Rst for PP's 11-1 */
-        uint64_t rst0                    : 1;       /**< PP Rst for PP0
-                                                         depends on standalone mode */
-#else
-        uint64_t rst0                    : 1;
-        uint64_t rst                     : 3;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_pp_rst_cn52xx        cn52xxp1;
-    struct cvmx_ciu_pp_rst_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t rst                     : 11;      /**< PP Rst for PP's 11-1 */
-        uint64_t rst0                    : 1;       /**< PP Rst for PP0
-                                                         depends on standalone mode */
-#else
-        uint64_t rst0                    : 1;
-        uint64_t rst                     : 11;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xx;
-    struct cvmx_ciu_pp_rst_cn56xx        cn56xxp1;
-    struct cvmx_ciu_pp_rst_s             cn58xx;
-    struct cvmx_ciu_pp_rst_s             cn58xxp1;
-} cvmx_ciu_pp_rst_t;
-
-
-/**
- * cvmx_ciu_qlm_dcok
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_qlm_dcok_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t qlm_dcok                : 4;       /**< Re-assert dcok for each QLM. The value in this
-                                                         field is "anded" with the pll_dcok pin and then
-                                                         sent to each QLM (0..3). */
-#else
-        uint64_t qlm_dcok                : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_ciu_qlm_dcok_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t qlm_dcok                : 2;       /**< Re-assert dcok for each QLM. The value in this
-                                                         field is "anded" with the pll_dcok pin and then
-                                                         sent to each QLM (0..3). */
-#else
-        uint64_t qlm_dcok                : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_qlm_dcok_cn52xx      cn52xxp1;
-    struct cvmx_ciu_qlm_dcok_s           cn56xx;
-    struct cvmx_ciu_qlm_dcok_s           cn56xxp1;
-} cvmx_ciu_qlm_dcok_t;
-
-
-/**
- * cvmx_ciu_qlm_jtgc
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_qlm_jtgc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t clk_div                 : 3;       /**< Clock divider for QLM JTAG operations.  eclk is
-                                                         divided by 2^(CLK_DIV + 2) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t mux_sel                 : 2;       /**< Selects which QLM JTAG shift out is shifted into
-                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
-        uint64_t bypass                  : 4;       /**< Selects which QLM JTAG shift chains are bypassed
-                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
-                                                         bit per QLM) */
-#else
-        uint64_t bypass                  : 4;
-        uint64_t mux_sel                 : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t clk_div                 : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_ciu_qlm_jtgc_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t clk_div                 : 3;       /**< Clock divider for QLM JTAG operations.  eclk is
-                                                         divided by 2^(CLK_DIV + 2) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t mux_sel                 : 1;       /**< Selects which QLM JTAG shift out is shifted into
-                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
-        uint64_t reserved_2_3            : 2;
-        uint64_t bypass                  : 2;       /**< Selects which QLM JTAG shift chains are bypassed
-                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
-                                                         bit per QLM) */
-#else
-        uint64_t bypass                  : 2;
-        uint64_t reserved_2_3            : 2;
-        uint64_t mux_sel                 : 1;
-        uint64_t reserved_5_7            : 3;
-        uint64_t clk_div                 : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_qlm_jtgc_cn52xx      cn52xxp1;
-    struct cvmx_ciu_qlm_jtgc_s           cn56xx;
-    struct cvmx_ciu_qlm_jtgc_s           cn56xxp1;
-} cvmx_ciu_qlm_jtgc_t;
-
-
-/**
- * cvmx_ciu_qlm_jtgd
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_qlm_jtgd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
-                                                         op completes) */
-        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
-                                                         op completes) */
-        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
-                                                         op completes) */
-        uint64_t reserved_44_60          : 17;
-        uint64_t select                  : 4;       /**< Selects which QLM JTAG shift chains the JTAG
-                                                         operations are performed on */
-        uint64_t reserved_37_39          : 3;
-        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
-        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
-#else
-        uint64_t shft_reg                : 32;
-        uint64_t shft_cnt                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t select                  : 4;
-        uint64_t reserved_44_60          : 17;
-        uint64_t update                  : 1;
-        uint64_t shift                   : 1;
-        uint64_t capture                 : 1;
-#endif
-    } s;
-    struct cvmx_ciu_qlm_jtgd_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
-                                                         op completes) */
-        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
-                                                         op completes) */
-        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
-                                                         op completes) */
-        uint64_t reserved_42_60          : 19;
-        uint64_t select                  : 2;       /**< Selects which QLM JTAG shift chains the JTAG
-                                                         operations are performed on */
-        uint64_t reserved_37_39          : 3;
-        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
-        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
-#else
-        uint64_t shft_reg                : 32;
-        uint64_t shft_cnt                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t select                  : 2;
-        uint64_t reserved_42_60          : 19;
-        uint64_t update                  : 1;
-        uint64_t shift                   : 1;
-        uint64_t capture                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_qlm_jtgd_cn52xx      cn52xxp1;
-    struct cvmx_ciu_qlm_jtgd_s           cn56xx;
-    struct cvmx_ciu_qlm_jtgd_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
-                                                         op completes) */
-        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
-                                                         op completes) */
-        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
-                                                         op completes) */
-        uint64_t reserved_37_60          : 24;
-        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
-        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
-#else
-        uint64_t shft_reg                : 32;
-        uint64_t shft_cnt                : 5;
-        uint64_t reserved_37_60          : 24;
-        uint64_t update                  : 1;
-        uint64_t shift                   : 1;
-        uint64_t capture                 : 1;
-#endif
-    } cn56xxp1;
-} cvmx_ciu_qlm_jtgd_t;
-
-
-/**
- * cvmx_ciu_soft_bist
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_soft_bist_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t soft_bist               : 1;       /**< Run BIST on soft reset. */
-#else
-        uint64_t soft_bist               : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_ciu_soft_bist_s          cn30xx;
-    struct cvmx_ciu_soft_bist_s          cn31xx;
-    struct cvmx_ciu_soft_bist_s          cn38xx;
-    struct cvmx_ciu_soft_bist_s          cn38xxp2;
-    struct cvmx_ciu_soft_bist_s          cn50xx;
-    struct cvmx_ciu_soft_bist_s          cn52xx;
-    struct cvmx_ciu_soft_bist_s          cn52xxp1;
-    struct cvmx_ciu_soft_bist_s          cn56xx;
-    struct cvmx_ciu_soft_bist_s          cn56xxp1;
-    struct cvmx_ciu_soft_bist_s          cn58xx;
-    struct cvmx_ciu_soft_bist_s          cn58xxp1;
-} cvmx_ciu_soft_bist_t;
-
-
-/**
- * cvmx_ciu_soft_prst
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_soft_prst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t host64                  : 1;       /**< PCX Host Mode Device Capability (0=32b/1=64b) */
-        uint64_t npi                     : 1;       /**< When PCI soft reset is asserted, also reset the
-                                                         NPI and PNI logic */
-        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
-                                                         configured as a HOST. When OCTEON is a PCI host
-                                                         (i.e. when PCI_HOST_MODE = 1), This controls
-                                                         PCI_RST_L. Refer to section 10.11.1. */
-#else
-        uint64_t soft_prst               : 1;
-        uint64_t npi                     : 1;
-        uint64_t host64                  : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_ciu_soft_prst_s          cn30xx;
-    struct cvmx_ciu_soft_prst_s          cn31xx;
-    struct cvmx_ciu_soft_prst_s          cn38xx;
-    struct cvmx_ciu_soft_prst_s          cn38xxp2;
-    struct cvmx_ciu_soft_prst_s          cn50xx;
-    struct cvmx_ciu_soft_prst_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
-                                                         configured as a HOST. When OCTEON is a PCI host
-                                                         (i.e. when PCI_HOST_MODE = 1), This controls
-                                                         PCI_RST_L. Refer to section 10.11.1. */
-#else
-        uint64_t soft_prst               : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn52xx;
-    struct cvmx_ciu_soft_prst_cn52xx     cn52xxp1;
-    struct cvmx_ciu_soft_prst_cn52xx     cn56xx;
-    struct cvmx_ciu_soft_prst_cn52xx     cn56xxp1;
-    struct cvmx_ciu_soft_prst_s          cn58xx;
-    struct cvmx_ciu_soft_prst_s          cn58xxp1;
-} cvmx_ciu_soft_prst_t;
-
-
-/**
- * cvmx_ciu_soft_prst1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_soft_prst1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
-                                                         configured as a HOST. When OCTEON is a PCI host
-                                                         (i.e. when PCI_HOST_MODE = 1), This controls
-                                                         PCI_RST_L. Refer to section 10.11.1. */
-#else
-        uint64_t soft_prst               : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_ciu_soft_prst1_s         cn52xx;
-    struct cvmx_ciu_soft_prst1_s         cn52xxp1;
-    struct cvmx_ciu_soft_prst1_s         cn56xx;
-    struct cvmx_ciu_soft_prst1_s         cn56xxp1;
-} cvmx_ciu_soft_prst1_t;
-
-
-/**
- * cvmx_ciu_soft_rst
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_soft_rst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t soft_rst                : 1;       /**< Resets Octeon
-                                                         When soft reseting Octeon from a remote PCI host,
-                                                         always read CIU_SOFT_RST (and wait for result)
-                                                         before writing SOFT_RST to '1'. */
-#else
-        uint64_t soft_rst                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_ciu_soft_rst_s           cn30xx;
-    struct cvmx_ciu_soft_rst_s           cn31xx;
-    struct cvmx_ciu_soft_rst_s           cn38xx;
-    struct cvmx_ciu_soft_rst_s           cn38xxp2;
-    struct cvmx_ciu_soft_rst_s           cn50xx;
-    struct cvmx_ciu_soft_rst_s           cn52xx;
-    struct cvmx_ciu_soft_rst_s           cn52xxp1;
-    struct cvmx_ciu_soft_rst_s           cn56xx;
-    struct cvmx_ciu_soft_rst_s           cn56xxp1;
-    struct cvmx_ciu_soft_rst_s           cn58xx;
-    struct cvmx_ciu_soft_rst_s           cn58xxp1;
-} cvmx_ciu_soft_rst_t;
-
-
-/**
- * cvmx_ciu_tim#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_timx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t one_shot                : 1;       /**< One-shot mode */
-        uint64_t len                     : 36;      /**< Timeout length in core clock cycles
-                                                         Periodic interrupts will occur every LEN+1 core
-                                                         clock cycles when ONE_SHOT==0
-                                                         Timer disabled when LEN==0 */
-#else
-        uint64_t len                     : 36;
-        uint64_t one_shot                : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } s;
-    struct cvmx_ciu_timx_s               cn30xx;
-    struct cvmx_ciu_timx_s               cn31xx;
-    struct cvmx_ciu_timx_s               cn38xx;
-    struct cvmx_ciu_timx_s               cn38xxp2;
-    struct cvmx_ciu_timx_s               cn50xx;
-    struct cvmx_ciu_timx_s               cn52xx;
-    struct cvmx_ciu_timx_s               cn52xxp1;
-    struct cvmx_ciu_timx_s               cn56xx;
-    struct cvmx_ciu_timx_s               cn56xxp1;
-    struct cvmx_ciu_timx_s               cn58xx;
-    struct cvmx_ciu_timx_s               cn58xxp1;
-} cvmx_ciu_timx_t;
-
-
-/**
- * cvmx_ciu_wdog#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ciu_wdogx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_46_63          : 18;
-        uint64_t gstopen                 : 1;       /**< GSTOPEN */
-        uint64_t dstop                   : 1;       /**< DSTOP */
-        uint64_t cnt                     : 24;      /**< Number of 256-cycle intervals until next watchdog
-                                                         expiration.  Cleared on write to associated
-                                                         CIU_PP_POKE register. */
-        uint64_t len                     : 16;      /**< Watchdog time expiration length
-                                                         The 16 bits of LEN represent the most significant
-                                                         bits of a 24 bit decrementer that decrements
-                                                         every 256 cycles.
-                                                         LEN must be set > 0 */
-        uint64_t state                   : 2;       /**< Watchdog state
-                                                         number of watchdog time expirations since last
-                                                         PP poke.  Cleared on write to associated
-                                                         CIU_PP_POKE register. */
-        uint64_t mode                    : 2;       /**< Watchdog mode
-                                                         0 = Off
-                                                         1 = Interrupt Only
-                                                         2 = Interrupt + NMI
-                                                         3 = Interrupt + NMI + Soft-Reset */
-#else
-        uint64_t mode                    : 2;
-        uint64_t state                   : 2;
-        uint64_t len                     : 16;
-        uint64_t cnt                     : 24;
-        uint64_t dstop                   : 1;
-        uint64_t gstopen                 : 1;
-        uint64_t reserved_46_63          : 18;
-#endif
-    } s;
-    struct cvmx_ciu_wdogx_s              cn30xx;
-    struct cvmx_ciu_wdogx_s              cn31xx;
-    struct cvmx_ciu_wdogx_s              cn38xx;
-    struct cvmx_ciu_wdogx_s              cn38xxp2;
-    struct cvmx_ciu_wdogx_s              cn50xx;
-    struct cvmx_ciu_wdogx_s              cn52xx;
-    struct cvmx_ciu_wdogx_s              cn52xxp1;
-    struct cvmx_ciu_wdogx_s              cn56xx;
-    struct cvmx_ciu_wdogx_s              cn56xxp1;
-    struct cvmx_ciu_wdogx_s              cn58xx;
-    struct cvmx_ciu_wdogx_s              cn58xxp1;
-} cvmx_ciu_wdogx_t;
-
-
-/**
- * cvmx_dbg_data
- *
- * DBG_DATA = Debug Data Register
- * 
- * Value returned on the debug-data lines from the RSLs
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dbg_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_dbg_data_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t pll_mul                 : 3;       /**< pll_mul pins sampled at DCOK assertion */
-        uint64_t reserved_23_27          : 5;
-        uint64_t c_mul                   : 5;       /**< Core PLL multiplier sampled at DCOK assertion */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t reserved_23_27          : 5;
-        uint64_t pll_mul                 : 3;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn30xx;
-    struct cvmx_dbg_data_cn30xx          cn31xx;
-    struct cvmx_dbg_data_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t d_mul                   : 4;       /**< D_MUL pins sampled on DCOK assertion */
-        uint64_t dclk_mul2               : 1;       /**< Should always be set for fast DDR-II operation */
-        uint64_t cclk_div2               : 1;       /**< Should always be clear for fast core clock */
-        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t cclk_div2               : 1;
-        uint64_t dclk_mul2               : 1;
-        uint64_t d_mul                   : 4;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn38xx;
-    struct cvmx_dbg_data_cn38xx          cn38xxp2;
-    struct cvmx_dbg_data_cn30xx          cn50xx;
-    struct cvmx_dbg_data_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t rem                     : 6;       /**< Remaining debug_select pins sampled at DCOK */
-        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t rem                     : 6;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn58xx;
-    struct cvmx_dbg_data_cn58xx          cn58xxp1;
-} cvmx_dbg_data_t;
-
-
-/**
- * cvmx_dfa_bst0
- *
- * DFA_BST0 = DFA Bist Status
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_bst0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rdf                     : 16;      /**< Bist Results for RDF[3:0] RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t pdf                     : 16;      /**< Bist Results for PDF[3:0] RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t pdf                     : 16;
-        uint64_t rdf                     : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_dfa_bst0_s               cn31xx;
-    struct cvmx_dfa_bst0_s               cn38xx;
-    struct cvmx_dfa_bst0_s               cn38xxp2;
-    struct cvmx_dfa_bst0_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t rdf                     : 4;       /**< Bist Results for RDF[3:0] RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_4_15           : 12;
-        uint64_t pdf                     : 4;       /**< Bist Results for PDF[3:0] RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t pdf                     : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t rdf                     : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn58xx;
-    struct cvmx_dfa_bst0_cn58xx          cn58xxp1;
-} cvmx_dfa_bst0_t;
-
-
-/**
- * cvmx_dfa_bst1
- *
- * DFA_BST1 = DFA Bist Status
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_bst1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t drf                     : 1;       /**< Bist Results for DRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p0_bwb                  : 1;       /**< Bist Results for P0_BWB RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p1_bwb                  : 1;       /**< Bist Results for P1_BWB RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p0_brf                  : 8;       /**< Bist Results for P0_BRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p1_brf                  : 8;       /**< Bist Results for P1_BRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t p1_brf                  : 8;
-        uint64_t p0_brf                  : 8;
-        uint64_t p1_bwb                  : 1;
-        uint64_t p0_bwb                  : 1;
-        uint64_t crf                     : 1;
-        uint64_t drf                     : 1;
-        uint64_t gfu                     : 1;
-        uint64_t ifu                     : 1;
-        uint64_t crq                     : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_dfa_bst1_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t drf                     : 1;       /**< Bist Results for DRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_0_17           : 18;
-#else
-        uint64_t reserved_0_17           : 18;
-        uint64_t crf                     : 1;
-        uint64_t drf                     : 1;
-        uint64_t gfu                     : 1;
-        uint64_t ifu                     : 1;
-        uint64_t crq                     : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } cn31xx;
-    struct cvmx_dfa_bst1_s               cn38xx;
-    struct cvmx_dfa_bst1_s               cn38xxp2;
-    struct cvmx_dfa_bst1_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_19_19          : 1;
-        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p0_bwb                  : 1;       /**< Bist Results for P0_BWB RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p1_bwb                  : 1;       /**< Bist Results for P1_BWB RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p0_brf                  : 8;       /**< Bist Results for P0_BRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t p1_brf                  : 8;       /**< Bist Results for P1_BRF RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t p1_brf                  : 8;
-        uint64_t p0_brf                  : 8;
-        uint64_t p1_bwb                  : 1;
-        uint64_t p0_bwb                  : 1;
-        uint64_t crf                     : 1;
-        uint64_t reserved_19_19          : 1;
-        uint64_t gfu                     : 1;
-        uint64_t ifu                     : 1;
-        uint64_t crq                     : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } cn58xx;
-    struct cvmx_dfa_bst1_cn58xx          cn58xxp1;
-} cvmx_dfa_bst1_t;
-
-
-/**
- * cvmx_dfa_cfg
- *
- * Specify the RSL base addresses for the block
- * 
- *                  DFA_CFG = DFA Configuration
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t nrpl_ena                : 1;       /**< When set, allows the per-node replication feature to be
-                                                         enabled.
-                                                         In 36-bit mode: The IWORD0[31:30]=SNREPL field AND
-                                                         bits [21:20] of the Next Node ptr are used in generating
-                                                         the next node address (see OCTEON HRM - DFA Chapter for
-                                                         psuedo-code of DTE next node address generation).
-                                                         NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode),
-                                                         (regardless of IWORD0[NRPLEN]), the Resultant Word1+
-                                                         [[47:44],[23:20]] = Next Node's [27:20] bits. This allows
-                                                         SW to use the RESERVED bits of the final node for SW
-                                                         caching. Also, if required, SW will use [22:21]=Node
-                                                         Replication to re-start the same graph walk(if graph
-                                                         walk prematurely terminated (ie: DATA_GONE).
-                                                         In 18-bit mode: The IWORD0[31:30]=SNREPL field AND
-                                                         bit [16:14] of the Next Node ptr are used in generating
-                                                         the next node address (see OCTEON HRM - DFA Chapter for
-                                                         psuedo-code of DTE next node address generation).
-                                                         If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [
-                                                            If next node ptr[16] is set [
-                                                              next node ptr[15:14] indicates the next node repl
-                                                              next node ptr[13:0]  indicates the position of the
-                                                                 node relative to the first normal node (i.e.
-                                                                 IWORD3[Msize] must be added to get the final node)
-                                                            ]
-                                                            else If next node ptr[16] is not set [
-                                                              next node ptr[15:0] indicates the next node id
-                                                              next node repl = 0
-                                                            ]
-                                                         ]
-                                                         NOTE: For 18b node replication, MAX node space=64KB(2^16)
-                                                         is used in detecting terminal node space(see HRM for full
-                                                         description).
-                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
-                                                         aware of the "per-node" replication. */
-        uint64_t nxor_ena                : 1;       /**< When set, allows the DTE Instruction IWORD0[NXOREN]
-                                                         to be used to enable/disable the per-node address 'scramble'
-                                                         of the LLM address to lessen the effects of bank conflicts.
-                                                         If IWORD0[NXOREN] is also set, then:
-                                                         In 36-bit mode: The node_Id[7:0] 8-bit value is XORed
-                                                         against the LLM address addr[9:2].
-                                                         In 18-bit mode: The node_id[6:0] 7-bit value is XORed
-                                                         against the LLM address addr[8:2]. (note: we don't address
-                                                         scramble outside the mode's node space).
-                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
-                                                         aware of the "per-node" address scramble.
-                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
-                                                         read/write operations. */
-        uint64_t gxor_ena                : 1;       /**< When set, the DTE Instruction IWORD0[GXOR]
-                                                         field is used to 'scramble' the LLM address
-                                                         to lessen the effects of bank conflicts.
-                                                         In 36-bit mode: The GXOR[7:0] 8-bit value is XORed
-                                                         against the LLM address addr[9:2].
-                                                         In 18-bit mode: GXOR[6:0] 7-bit value is XORed against
-                                                         the LLM address addr[8:2]. (note: we don't address
-                                                         scramble outside the mode's node space)
-                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
-                                                         aware of the "per-graph" address scramble.
-                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
-                                                         read/write operations. */
-        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
-                                                         Selects the arbitration mode used to select DFA
-                                                         requests issued from either CP2 or the DTE (NCB-CSR
-                                                         or DFA HW engine).
-                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
-                                                            - 1: Round-Robin
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-#else
-        uint64_t sarb                    : 1;
-        uint64_t gxor_ena                : 1;
-        uint64_t nxor_ena                : 1;
-        uint64_t nrpl_ena                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_dfa_cfg_s                cn38xx;
-    struct cvmx_dfa_cfg_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
-                                                         Selects the arbitration mode used to select DFA
-                                                         requests issued from either CP2 or the DTE (NCB-CSR
-                                                         or DFA HW engine).
-                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
-                                                            - 1: Round-Robin
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-#else
-        uint64_t sarb                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn38xxp2;
-    struct cvmx_dfa_cfg_s                cn58xx;
-    struct cvmx_dfa_cfg_s                cn58xxp1;
-} cvmx_dfa_cfg_t;
-
-
-/**
- * cvmx_dfa_dbell
- *
- * DFA_DBELL = DFA Doorbell Register
- * 
- * Description:
- *  NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00.
- *        To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00.
- * 
- *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect.
- *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t dbell                   : 20;      /**< Represents the cumulative total of pending
-                                                         DFA instructions which SW has previously written
-                                                         into the DFA Instruction FIFO (DIF) in main memory.
-                                                         Each DFA instruction contains a fixed size 32B
-                                                         instruction word which is executed by the DFA HW.
-                                                         The DBL register can hold up to 1M-1 (2^20-1)
-                                                         pending DFA instruction requests.
-                                                         During a read (by SW), the 'most recent' contents
-                                                         of the DFA_DBELL register are returned at the time
-                                                         the NCB-INB bus is driven.
-                                                         NOTE: Since DFA HW updates this register, its
-                                                         contents are unpredictable in SW. */
-#else
-        uint64_t dbell                   : 20;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_dfa_dbell_s              cn31xx;
-    struct cvmx_dfa_dbell_s              cn38xx;
-    struct cvmx_dfa_dbell_s              cn38xxp2;
-    struct cvmx_dfa_dbell_s              cn58xx;
-    struct cvmx_dfa_dbell_s              cn58xxp1;
-} cvmx_dfa_dbell_t;
-
-
-/**
- * cvmx_dfa_ddr2_addr
- *
- * DFA_DDR2_ADDR = DFA DDR2  fclk-domain Memory Address Config Register
- * 
- * 
- * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK
- *              etc.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t rdimm_ena               : 1;       /**< If there is a need to insert a register chip on the
-                                                         system (the equivalent of a registered DIMM) to
-                                                         provide better setup for the command and control bits
-                                                         turn this mode on.
-                                                             RDIMM_ENA
-                                                                0           Registered Mode OFF
-                                                                1           Registered Mode ON */
-        uint64_t num_rnks                : 2;       /**< NUM_RNKS is programmed based on how many ranks there
-                                                         are in the system. This needs to be programmed correctly
-                                                         regardless of whether we are in RNK_LO mode or not.
-                                                            NUM_RNKS     \# of Ranks
-                                                              0              1
-                                                              1              2
-                                                              2              4
-                                                              3              RESERVED */
-        uint64_t rnk_lo                  : 1;       /**< When this mode is turned on, consecutive addresses
-                                                         outside the bank boundary
-                                                         are programmed to go to different ranks in order to
-                                                         minimize bank conflicts. It is useful in 4-bank DDR2
-                                                         parts based memory to extend out the \#physical banks
-                                                         available and minimize bank conflicts.
-                                                         On 8 bank ddr2 parts, this mode is not very useful
-                                                         because this mode does come with
-                                                         a penalty which is that every successive reads that
-                                                         cross rank boundary will need a 1 cycle bubble
-                                                         inserted to prevent bus turnaround conflicts.
-                                                            RNK_LO
-                                                             0      - OFF
-                                                             1      - ON */
-        uint64_t num_colrows             : 3;       /**< NUM_COLROWS    is used to set the MSB of the ROW_ADDR
-                                                         and the LSB of RANK address when not in RNK_LO mode.
-                                                         Calculate the sum of \#COL and \#ROW and program the
-                                                         controller appropriately
-                                                            RANK_LSB        \#COLs + \#ROWs
-                                                            ------------------------------
-                                                             - 000:                   22
-                                                             - 001:                   23
-                                                             - 010:                   24
-                                                             - 011:                   25
-                                                            - 100-111:             RESERVED */
-        uint64_t num_cols                : 2;       /**< The Long word address that the controller receives
-                                                         needs to be converted to Row, Col, Rank and Bank
-                                                         addresses depending on the memory part's micro arch.
-                                                         NUM_COL tells the controller how many colum bits
-                                                         there are and the controller uses this info to map
-                                                         the LSB of the row address
-                                                             - 00: num_cols = 9
-                                                             - 01: num_cols = 10
-                                                             - 10: num_cols = 11
-                                                             - 11: RESERVED */
-#else
-        uint64_t num_cols                : 2;
-        uint64_t num_colrows             : 3;
-        uint64_t rnk_lo                  : 1;
-        uint64_t num_rnks                : 2;
-        uint64_t rdimm_ena               : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_addr_s          cn31xx;
-} cvmx_dfa_ddr2_addr_t;
-
-
-/**
- * cvmx_dfa_ddr2_bus
- *
- * DFA_DDR2_BUS = DFA DDR Bus Activity Counter
- * 
- * 
- * Description: This counter counts \# cycles that the memory bus is doing a read/write/command
- *              Useful to benchmark the bus utilization as a ratio of
- *              \#Cycles of Data Transfer/\#Cycles since init or
- *              \#Cycles of Data Transfer/\#Cycles that memory controller is active
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_bus_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_47_63          : 17;
-        uint64_t bus_cnt                 : 47;      /**< Counter counts the \# cycles of Data transfer */
-#else
-        uint64_t bus_cnt                 : 47;
-        uint64_t reserved_47_63          : 17;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_bus_s           cn31xx;
-} cvmx_dfa_ddr2_bus_t;
-
-
-/**
- * cvmx_dfa_ddr2_cfg
- *
- * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_41_63          : 23;
-        uint64_t trfc                    : 5;       /**< Establishes tRFC(from DDR2 data sheets) in \# of
-                                                         4 fclk intervals.
-                                                         General Equation:
-                                                         TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))]
-                                                         Example:
-                                                            tRFC(data-sheet-ns) = 127.5ns
-                                                            Operational Frequency: 533MHz DDR rate
-                                                                [fclk=266MHz(3.75ns)]
-                                                         Then:
-                                                            TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)]
-                                                                      = 9 */
-        uint64_t mrs_pgm                 : 1;       /**< When clear, the HW initialization sequence fixes
-                                                         some of the *MRS register bit definitions.
-                                                            EMRS:
-                                                              A[14:13] = 0 RESERVED
-                                                              A[12] = 0    Output Buffers Enabled (FIXED)
-                                                              A[11] = 0    RDQS Disabled (FIXED)
-                                                              A[10] = 0    DQSn Enabled (FIXED)
-                                                              A[9:7] = 0   OCD Not supported (FIXED)
-                                                              A[6] = 0     RTT Disabled (FIXED)
-                                                              A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1)
-                                                                            Additive LATENCY (Programmable)
-                                                              A[2]=0       RTT Disabled (FIXED)
-                                                              A[1]=DFA_DDR2_TMG[DIC] (Programmable)
-                                                              A[0] = 0     DLL Enabled (FIXED)
-                                                            MRS:
-                                                              A[14:13] = 0 RESERVED
-                                                              A[12] = 0    Fast Active Power Down Mode (FIXED)
-                                                              A[11:9] = DFA_DDR2_TMG[TWR](Programmable)
-                                                              A[8] = 1     DLL Reset (FIXED)
-                                                              A[7] = 0     Test Mode (FIXED)
-                                                              A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable)
-                                                              A[3] = 0     Burst Type(must be 0:Sequential) (FIXED)
-                                                              A[2:0] = 2   Burst Length=4 (must be 0:Sequential) (FIXED)
-                                                         When set, the HW initialization sequence sources
-                                                         the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are
-                                                         driven onto the DFA_A[] pins. (this allows the MRS/EMRS
-                                                         fields to be completely programmable - however care
-                                                         must be taken by software).
-                                                         This mode is useful for customers who wish to:
-                                                            1) override the FIXED definitions(above), or
-                                                            2) Use a "clamshell mode" of operation where the
-                                                               address bits(per rank) are swizzled on the
-                                                               board to reduce stub lengths for optimal
-                                                               frequency operation.
-                                                         Use this in combination with DFA_DDR2_CFG[RNK_MSK]
-                                                         to specify the INIT sequence for each of the 4
-                                                         supported ranks. */
-        uint64_t fpip                    : 3;       /**< Early Fill Programmable Pipe [\#fclks]
-                                                         This field dictates the \#fclks prior to the arrival
-                                                         of fill data(in fclk domain), to start the 'early' fill
-                                                         command pipe (in the eclk domain) so as to minimize the
-                                                         overall fill latency.
-                                                         The programmable early fill command signal is synchronized
-                                                         into the eclk domain, where it is used to pull data out of
-                                                         asynchronous RAM as fast as possible.
-                                                         NOTE: A value of FPIP=0 is the 'safest' setting and will
-                                                         result in the early fill command pipe starting in the
-                                                         same cycle as the fill data.
-                                                         General Equation: (for FPIP)
-                                                             FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)]
-                                                         where:
-                                                           EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)]
-                                                         Example: FCLK=200MHz/ECLK=600MHz
-                                                            FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)]
-                                                            FPIP <= 3 */
-        uint64_t reserved_29_31          : 3;
-        uint64_t ref_int                 : 13;      /**< Refresh Interval (represented in \#of fclk
-                                                         increments).
-                                                         Each refresh interval will generate a single
-                                                         auto-refresh command sequence which implicitly targets
-                                                         all banks within the device:
-                                                         Example: For fclk=200MHz(5ns)/400MHz(DDR):
-                                                           trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet]
-                                                           REF_INT = ROUND_DOWN[(trefint/fclk)]
-                                                                   = ROUND_DOWN[(3900ns/5ns)]
-                                                                   = 780 fclks (0x30c)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t reserved_14_15          : 2;
-        uint64_t tskw                    : 2;       /**< Board Skew (represented in \#fclks)
-                                                         Represents additional board skew of DQ/DQS.
-                                                             - 00: board-skew = 0 fclk
-                                                             - 01: board-skew = 1 fclk
-                                                             - 10: board-skew = 2 fclk
-                                                             - 11: board-skew = 3 fclk
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t rnk_msk                 : 4;       /**< Controls the CS_N[3:0] during a) a HW Initialization
-                                                         sequence (triggered by DFA_DDR2_CFG[INIT]) or
-                                                         b) during a normal refresh sequence. If
-                                                         the RNK_MSK[x]=1, the corresponding CS_N[x] is driven.
-                                                         NOTE: This is required for DRAM used in a
-                                                         clamshell configuration, since the address lines
-                                                         carry Mode Register write data that is unique
-                                                         per rank(or clam). In a clamshell configuration,
-                                                         the N3K DFA_A[x] pin may be tied into Clam#0's A[x]
-                                                         and also into Clam#1's 'mirrored' address bit A[y]
-                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
-                                                         To support clamshell designs, SW must initiate
-                                                         separate HW init sequences each unique rank address
-                                                         mapping. Before each HW init sequence is triggered,
-                                                         SW must preload the DFA_DDR2_MRS/EMRS registers with
-                                                         the data that will be driven onto the A[14:0] wires
-                                                         during the EMRS/MRS mode register write(s).
-                                                         NOTE: After the final HW initialization sequence has
-                                                         been triggered, SW must wait 64K eclks before writing
-                                                         the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0]
-                                                         is driven during refresh sequences in normal operation.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t silo_qc                 : 1;       /**< Enables Quarter Cycle move of the Rd sampling window */
-        uint64_t silo_hc                 : 1;       /**< A combination of SILO_HC, SILO_QC and TSKW
-                                                         specifies the positioning of the sampling strobe
-                                                         when receiving read data back from DDR2. This is
-                                                         done to offset any board trace induced delay on
-                                                         the DQ and DQS which inherently makes these
-                                                         asynchronous with respect to the internal clk of
-                                                         controller. TSKW moves this sampling window by
-                                                         integer cycles. SILO_QC and HC move this quarter
-                                                         and half a cycle respectively. */
-        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#fclks): On reads, determines how many
-                                                         additional fclks to wait (on top of CASLAT+1) before
-                                                         pulling data out of the padring silos used for time
-                                                         domain boundary crossing.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t bprch                   : 1;       /**< Tristate Enable (back porch) (\#fclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable back porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t fprch                   : 1;       /**< Tristate Enable (front porch) (\#fclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable front porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t init                    : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for the LLM Memory Port is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Enable memory port
-                                                               a) PRTENA=1
-                                                           2) Wait 200us (to ensure a stable clock
-                                                              to the DDR2) - as per DDR2 spec.
-                                                           3) Write a '1' to the INIT which
-                                                              will initiate a hardware initialization
-                                                              sequence.
-                                                         NOTE: After writing a '1', SW must wait 64K eclk
-                                                         cycles to ensure the HW init sequence has completed
-                                                         before writing to ANY of the DFA_DDR2* registers.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t prtena                  : 1;       /**< Enable DFA Memory
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for DFA-LLM memory port. */
-#else
-        uint64_t prtena                  : 1;
-        uint64_t init                    : 1;
-        uint64_t fprch                   : 1;
-        uint64_t bprch                   : 1;
-        uint64_t sil_lat                 : 2;
-        uint64_t silo_hc                 : 1;
-        uint64_t silo_qc                 : 1;
-        uint64_t rnk_msk                 : 4;
-        uint64_t tskw                    : 2;
-        uint64_t reserved_14_15          : 2;
-        uint64_t ref_int                 : 13;
-        uint64_t reserved_29_31          : 3;
-        uint64_t fpip                    : 3;
-        uint64_t mrs_pgm                 : 1;
-        uint64_t trfc                    : 5;
-        uint64_t reserved_41_63          : 23;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_cfg_s           cn31xx;
-} cvmx_dfa_ddr2_cfg_t;
-
-
-/**
- * cvmx_dfa_ddr2_comp
- *
- * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration
- * 
- * 
- * Description: The following are registers to program the DDR2 PLL and DLL
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_comp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dfa__pctl               : 4;       /**< DFA DDR pctl from compensation circuit
-                                                         Internal DBG only */
-        uint64_t dfa__nctl               : 4;       /**< DFA DDR nctl from compensation circuit
-                                                         Internal DBG only */
-        uint64_t reserved_9_55           : 47;
-        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t comp_bypass             : 1;       /**< Compensation Bypass */
-#else
-        uint64_t comp_bypass             : 1;
-        uint64_t nctl_csr                : 4;
-        uint64_t pctl_csr                : 4;
-        uint64_t reserved_9_55           : 47;
-        uint64_t dfa__nctl               : 4;
-        uint64_t dfa__pctl               : 4;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_comp_s          cn31xx;
-} cvmx_dfa_ddr2_comp_t;
-
-
-/**
- * cvmx_dfa_ddr2_emrs
- *
- * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0]
- * Description: This register contains the data driven onto the Address[14:0] lines during  DDR INIT
- * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
- * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
- * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
- * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
- *
- * Notes:
- * For DDR-II please consult your device's data sheet for further details:
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_emrs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t emrs1_ocd               : 15;      /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)"
-                                                         step \#12a "EMRS OCD Default Command" A[9:7]=111
-                                                         of DDR2 HW initialization sequence.
-                                                         (See JEDEC DDR2 specification (JESD79-2):
-                                                         Power Up and initialization sequence).
-                                                            A[14:13] = 0, RESERVED
-                                                            A[12] = 0, Output Buffers Enabled
-                                                            A[11] = 0, RDQS Disabled (we do not support RDQS)
-                                                            A[10] = 0, DQSn Enabled
-                                                            A[9:7] = 7, OCD Calibration Mode Default
-                                                            A[6] = 0, ODT Disabled
-                                                            A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
-                                                            A[2]=0    Termination Res RTT (ODT off Default)
-                                                            [A6,A2] = 0 -> ODT Disabled
-                                                                      1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
-                                                            A[1]=0  Normal Output Driver Imp mode
-                                                                    (1 - weak ie., 60% of normal drive strength)
-                                                            A[0] = 0 DLL Enabled */
-        uint64_t reserved_15_15          : 1;
-        uint64_t emrs1                   : 15;      /**< Memory Address[14:0] during:
-                                                           a) Step \#7 "EMRS1 to enable DLL (A[0]=0)"
-                                                           b) Step \#12b "EMRS OCD Calibration Mode Exit"
-                                                         steps of DDR2 HW initialization sequence.
-                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up and
-                                                         initialization sequence).
-                                                           A[14:13] = 0, RESERVED
-                                                           A[12] = 0, Output Buffers Enabled
-                                                           A[11] = 0, RDQS Disabled (we do not support RDQS)
-                                                           A[10] = 0, DQSn Enabled
-                                                           A[9:7] = 0, OCD Calibration Mode exit/maintain
-                                                           A[6] = 0, ODT Disabled
-                                                           A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
-                                                           A[2]=0    Termination Res RTT (ODT off Default)
-                                                           [A6,A2] = 0 -> ODT Disabled
-                                                                     1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
-                                                           A[1]=0  Normal Output Driver Imp mode
-                                                                   (1 - weak ie., 60% of normal drive strength)
-                                                           A[0] = 0 DLL Enabled */
-#else
-        uint64_t emrs1                   : 15;
-        uint64_t reserved_15_15          : 1;
-        uint64_t emrs1_ocd               : 15;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_emrs_s          cn31xx;
-} cvmx_dfa_ddr2_emrs_t;
-
-
-/**
- * cvmx_dfa_ddr2_fcnt
- *
- * DFA_DDR2_FCNT = DFA FCLK Counter
- * 
- * 
- * Description: This FCLK cycle counter gets going after memory has been initialized
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_fcnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_47_63          : 17;
-        uint64_t fcyc_cnt                : 47;      /**< Counter counts FCLK cycles or \# cycles that the memory
-                                                         controller has requests queued up depending on FCNT_MODE
-                                                         If FCNT_MODE = 0, this counter counts the \# FCLK cycles
-                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
-                                                         controller is active with memory requests. */
-#else
-        uint64_t fcyc_cnt                : 47;
-        uint64_t reserved_47_63          : 17;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_fcnt_s          cn31xx;
-} cvmx_dfa_ddr2_fcnt_t;
-
-
-/**
- * cvmx_dfa_ddr2_mrs
- *
- * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0]
- * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT
- * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
- * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
- * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
- * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
- *
- * Notes:
- * For DDR-II please consult your device's data sheet for further details:
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_mrs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t mrs                     : 15;      /**< Memory Address[14:0] during "MRS without resetting
-                                                         DLL A[8]=0" step of HW initialization sequence.
-                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
-                                                         and initialization sequence - Step \#11).
-                                                           A[14:13] = 0, RESERVED
-                                                           A[12] = 0, Fast Active Power Down Mode
-                                                           A[11:9] = DFA_DDR2_TMG[TWR]
-                                                           A[8] = 0, for DLL Reset
-                                                           A[7] =0  Test Mode (must be 0 for normal operation)
-                                                           A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4)
-                                                           A[3]=0    Burst Type(must be 0:Sequential)
-                                                           A[2:0]=2  Burst Length=4(default) */
-        uint64_t reserved_15_15          : 1;
-        uint64_t mrs_dll                 : 15;      /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1"
-                                                         step of HW initialization sequence.
-                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
-                                                         and initialization sequence - Step \#8).
-                                                           A[14:13] = 0, RESERVED
-                                                           A[12] = 0, Fast Active Power Down Mode
-                                                           A[11:9] = DFA_DDR2_TMG[TWR]
-                                                           A[8] = 1, for DLL Reset
-                                                           A[7] = 0  Test Mode (must be 0 for normal operation)
-                                                           A[6:4]=DFA_DDR2_TMG[CASLAT]    CAS LATENCY (default 4)
-                                                           A[3] = 0    Burst Type(must be 0:Sequential)
-                                                           A[2:0] = 2  Burst Length=4(default) */
-#else
-        uint64_t mrs_dll                 : 15;
-        uint64_t reserved_15_15          : 1;
-        uint64_t mrs                     : 15;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_mrs_s           cn31xx;
-} cvmx_dfa_ddr2_mrs_t;
-
-
-/**
- * cvmx_dfa_ddr2_opt
- *
- * DFA_DDR2_OPT = DFA DDR2 Optimization Registers
- * 
- * 
- * Description: The following are registers to tweak certain parameters to boost performance
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_opt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t max_read_batch          : 5;       /**< Maximum number of consecutive read to service before
-                                                         allowing write to interrupt. */
-        uint64_t max_write_batch         : 5;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-#else
-        uint64_t max_write_batch         : 5;
-        uint64_t max_read_batch          : 5;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_opt_s           cn31xx;
-} cvmx_dfa_ddr2_opt_t;
-
-
-/**
- * cvmx_dfa_ddr2_pll
- *
- * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration
- * 
- * 
- * Description: The following are registers to program the DDR2 PLL and DLL
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_pll_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pll_setting             : 17;      /**< Internal Debug Use Only */
-        uint64_t reserved_32_46          : 15;
-        uint64_t setting90               : 5;       /**< Contains the setting of DDR DLL; Internal DBG only */
-        uint64_t reserved_21_26          : 6;
-        uint64_t dll_setting             : 5;       /**< Contains the open loop setting value for the DDR90 delay
-                                                         line. */
-        uint64_t dll_byp                 : 1;       /**< DLL Bypass. When set, the DDR90 DLL is bypassed and
-                                                         the DLL behaves in Open Loop giving a fixed delay
-                                                         set by DLL_SETTING */
-        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
-                                                         erst deassertion will reset the DDR 90 DLL. Allow
-                                                         200 micro seconds for Lock before DDR Init. */
-        uint64_t bw_ctl                  : 4;       /**< Internal Use Only - for Debug */
-        uint64_t bw_upd                  : 1;       /**< Internal Use Only - for Debug */
-        uint64_t pll_div2                : 1;       /**< PLL Output is further divided by 2. Useful for slow
-                                                         fclk frequencies where the PLL may be out of range. */
-        uint64_t reserved_7_7            : 1;
-        uint64_t pll_ratio               : 5;       /**< Bits <6:2> sets the clk multiplication ratio
-                                                         If the fclk frequency desired is less than 260MHz
-                                                         (lower end saturation point of the pll), write 2x
-                                                         the ratio desired in this register and set PLL_DIV2 */
-        uint64_t pll_bypass              : 1;       /**< PLL Bypass. Uses the ref_clk without multiplication. */
-        uint64_t pll_init                : 1;       /**< Need a 0 to 1 pulse on this CSR to get the DFA
-                                                         Clk Generator Started. Write this register before
-                                                         starting anything. Allow 200 uS for PLL Lock before
-                                                         doing anything. */
-#else
-        uint64_t pll_init                : 1;
-        uint64_t pll_bypass              : 1;
-        uint64_t pll_ratio               : 5;
-        uint64_t reserved_7_7            : 1;
-        uint64_t pll_div2                : 1;
-        uint64_t bw_upd                  : 1;
-        uint64_t bw_ctl                  : 4;
-        uint64_t qdll_ena                : 1;
-        uint64_t dll_byp                 : 1;
-        uint64_t dll_setting             : 5;
-        uint64_t reserved_21_26          : 6;
-        uint64_t setting90               : 5;
-        uint64_t reserved_32_46          : 15;
-        uint64_t pll_setting             : 17;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_pll_s           cn31xx;
-} cvmx_dfa_ddr2_pll_t;
-
-
-/**
- * cvmx_dfa_ddr2_tmg
- *
- * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register
- * 
- * 
- * Description: The following are registers to program the DDR2 memory timing parameters.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ddr2_tmg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_47_63          : 17;
-        uint64_t fcnt_mode               : 1;       /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles
-                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
-                                                         controller is active with memory requests. */
-        uint64_t cnt_clr                 : 1;       /**< Clears the FCLK Cyc & Bus Util counter */
-        uint64_t cavmipo                 : 1;       /**< RESERVED */
-        uint64_t ctr_rst                 : 1;       /**< Reset oneshot pulse for refresh counter & Perf counters
-                                                         SW should first write this field to a one to clear
-                                                         & then write to a zero for normal operation */
-        uint64_t odt_rtt                 : 2;       /**< DDR2 Termination Resistor Setting
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                              00 = ODT Disabled
-                                                              01 = 75 ohm Termination
-                                                              10 = 150 ohm Termination
-                                                              11 = 50 ohm Termination */
-        uint64_t dqsn_ena                : 1;       /**< For DDR-II Mode, DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                              0 - DQSN Enable
-                                                              1 - DQSN Disable */
-        uint64_t dic                     : 1;       /**< Drive Strength Control:
-                                                         For DDR-I/II Mode, DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization. (see DDR-I data sheet EMRS
-                                                         description)
-                                                              0 = Normal
-                                                              1 = Reduced */
-        uint64_t r2r_slot                : 1;       /**< A 1 on this register will force the controller to
-                                                         slot a bubble between every reads */
-        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
-                                                         Four Access Window time. Relevant only in
-                                                         8-bank parts.
-                                                              TFAW = 5'b0 for DDR2-4bank
-                                                              TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
-        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
-                                                         Last Wr Data to Rd Command time.
-                                                         (Represented in fclk cycles)
-                                                         TYP=15ns
-                                                              - 0000: RESERVED
-                                                              - 0001: 1
-                                                              - ...
-                                                              - 0111: 7
-                                                              - 1000-1111: RESERVED */
-        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech
-                                                         This is not a direct encoding of the value. Its
-                                                         programmed as below per DDR2 spec. The decimal number
-                                                         on the right is RNDUP(tWR(ns) / clkFreq)
-                                                         TYP=15ns
-                                                              - 000: RESERVED
-                                                              - 001: 2
-                                                              - 010: 3
-                                                              - 011: 4
-                                                              - 100: 5
-                                                              - 101: 6
-                                                              - 110-111: RESERVED */
-        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
-                                                         (Represented in fclk cycles)
-                                                         TYP=15ns
-                                                              - 0000: RESERVED
-                                                              - 0001: 1
-                                                              - ...
-                                                              - 0111: 7
-                                                              - 1000-1111: RESERVED
-                                                         When using parts with 8 banks (DFA_CFG->MAX_BNK
-                                                         is 1), load tRP cycles + 1 into this register. */
-        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
-                                                         (Represented in fclk cycles)
-                                                         TYP=45ns
-                                                              - 00000-0001: RESERVED
-                                                              - 00010: 2
-                                                              - ...
-                                                              - 10100: 20
-                                                              - 10101-11111: RESERVED */
-        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
-                                                         banks. (Represented in fclk cycles)
-                                                         For DDR2, TYP=7.5ns
-                                                             - 000: RESERVED
-                                                             - 001: 1 tCYC
-                                                             - 010: 2 tCYC
-                                                             - 011: 3 tCYC
-                                                             - 100: 4 tCYC
-                                                             - 101: 5 tCYC
-                                                             - 110-111: RESERVED */
-        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
-                                                         (Represented in fclk cycles)
-                                                         TYP=15ns
-                                                              - 0000: RESERVED
-                                                              - 0001: 2 (2 is the smallest value allowed)
-                                                              - 0002: 2
-                                                              - ...
-                                                              - 0111: 7
-                                                              - 1110-1111: RESERVED */
-        uint64_t addlat                  : 3;       /**< When in Posted CAS mode ADDLAT needs to be programmed
-                                                         to tRCD-1
-                                                               ADDLAT         \#additional latency cycles
-                                                                000              0
-                                                                001              1 (tRCD = 2 fclk's)
-                                                                010              2 (tRCD = 3 fclk's)
-                                                                011              3 (tRCD = 4 fclk's)
-                                                                100              4 (tRCD = 5 fclk's)
-                                                                101              5 (tRCD = 6 fclk's)
-                                                                110              6 (tRCD = 7 fclk's)
-                                                                111              7 (tRCD = 8 fclk's) */
-        uint64_t pocas                   : 1;       /**< Posted CAS mode. When 1, we use DDR2's Posted CAS
-                                                         feature. When using this mode, ADDLAT needs to be
-                                                         programmed as well */
-        uint64_t caslat                  : 3;       /**< CAS Latency in \# fclk Cycles
-                                                         CASLAT           \#  CAS latency cycles
-                                                          000 - 010           RESERVED
-                                                          011                    3
-                                                          100                    4
-                                                          101                    5
-                                                          110                    6
-                                                          111                    7 */
-        uint64_t tmrd                    : 2;       /**< tMRD Cycles
-                                                         (Represented in fclk tCYC)
-                                                         For DDR2, its TYP 2*tCYC)
-                                                             - 000: RESERVED
-                                                             - 001: 1
-                                                             - 010: 2
-                                                             - 011: 3 */
-        uint64_t ddr2t                   : 1;       /**< When 2T mode is turned on, command signals are
-                                                         setup a cycle ahead of when the CS is enabled
-                                                         and kept for a total of 2 cycles. This mode is
-                                                         enabled in higher speeds when there is difficulty
-                                                         meeting setup. Performance could
-                                                         be negatively affected in 2T mode */
-#else
-        uint64_t ddr2t                   : 1;
-        uint64_t tmrd                    : 2;
-        uint64_t caslat                  : 3;
-        uint64_t pocas                   : 1;
-        uint64_t addlat                  : 3;
-        uint64_t trcd                    : 4;
-        uint64_t trrd                    : 3;
-        uint64_t tras                    : 5;
-        uint64_t trp                     : 4;
-        uint64_t twr                     : 3;
-        uint64_t twtr                    : 4;
-        uint64_t tfaw                    : 5;
-        uint64_t r2r_slot                : 1;
-        uint64_t dic                     : 1;
-        uint64_t dqsn_ena                : 1;
-        uint64_t odt_rtt                 : 2;
-        uint64_t ctr_rst                 : 1;
-        uint64_t cavmipo                 : 1;
-        uint64_t cnt_clr                 : 1;
-        uint64_t fcnt_mode               : 1;
-        uint64_t reserved_47_63          : 17;
-#endif
-    } s;
-    struct cvmx_dfa_ddr2_tmg_s           cn31xx;
-} cvmx_dfa_ddr2_tmg_t;
-
-
-/**
- * cvmx_dfa_difctl
- *
- * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register
- * 
- * Description:
- *  NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b11.
- *        To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b11.
- * 
- *  NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could
- *  cause the DFA and FPA HW to become unpredictable.
- * 
- *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect.
- *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_difctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t dwbcnt                  : 8;       /**< Represents the \# of cache lines in the instruction
-                                                         buffer that may be dirty and should not be
-                                                         written-back to memory when the instruction
-                                                         chunk is returned to the Free Page list.
-                                                         NOTE: Typically SW will want to mark all DFA
-                                                         Instruction memory returned to the Free Page list
-                                                         as DWB (Don't WriteBack), therefore SW should
-                                                         seed this register as:
-                                                           DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */
-        uint64_t pool                    : 3;       /**< Represents the 3bit buffer pool-id  used by DFA HW
-                                                         when the DFA instruction chunk is recycled back
-                                                         to the Free Page List maintained by the FPA HW
-                                                         (once the DFA instruction has been issued). */
-        uint64_t size                    : 9;       /**< Represents the \# of 32B instructions contained
-                                                         within each DFA instruction chunk. At Power-on,
-                                                         SW will seed the SIZE register with a fixed
-                                                         chunk-size. (Must be at least 3)
-                                                         DFA HW uses this field to determine the size
-                                                         of each DFA instruction chunk, in order to:
-                                                            a) determine when to read the next DFA
-                                                               instruction chunk pointer which is
-                                                               written by SW at the end of the current
-                                                               DFA instruction chunk (see DFA description
-                                                               of next chunk buffer Ptr for format).
-                                                            b) determine when a DFA instruction chunk
-                                                               can be returned to the Free Page List
-                                                               maintained by the FPA HW. */
-#else
-        uint64_t size                    : 9;
-        uint64_t pool                    : 3;
-        uint64_t dwbcnt                  : 8;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_dfa_difctl_s             cn31xx;
-    struct cvmx_dfa_difctl_s             cn38xx;
-    struct cvmx_dfa_difctl_s             cn38xxp2;
-    struct cvmx_dfa_difctl_s             cn58xx;
-    struct cvmx_dfa_difctl_s             cn58xxp1;
-} cvmx_dfa_difctl_t;
-
-
-/**
- * cvmx_dfa_difrdptr
- *
- * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register
- * 
- * Description:
- *  NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01.
- *        To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01.
- * 
- *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect.
- *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_difrdptr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t rdptr                   : 31;      /**< Represents the 32B-aligned address of the current
-                                                         instruction in the DFA Instruction FIFO in main
-                                                         memory. The RDPTR must be seeded by software at
-                                                         boot time, and is then maintained thereafter
-                                                         by DFA HW.
-                                                         During the seed write (by SW), RDPTR[6:5]=0,
-                                                         since DFA instruction chunks must be 128B aligned.
-                                                         During a read (by SW), the 'most recent' contents
-                                                         of the RDPTR register are returned at the time
-                                                         the NCB-INB bus is driven.
-                                                         NOTE: Since DFA HW updates this register, its
-                                                         contents are unpredictable in SW (unless
-                                                         its guaranteed that no new DoorBell register
-                                                         writes have occurred and the DoorBell register is
-                                                         read as zero). */
-        uint64_t reserved_0_4            : 5;
-#else
-        uint64_t reserved_0_4            : 5;
-        uint64_t rdptr                   : 31;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_dfa_difrdptr_s           cn31xx;
-    struct cvmx_dfa_difrdptr_s           cn38xx;
-    struct cvmx_dfa_difrdptr_s           cn38xxp2;
-    struct cvmx_dfa_difrdptr_s           cn58xx;
-    struct cvmx_dfa_difrdptr_s           cn58xxp1;
-} cvmx_dfa_difrdptr_t;
-
-
-/**
- * cvmx_dfa_eclkcfg
- *
- * Specify the RSL base addresses for the block
- * 
- *                  DFA_ECLKCFG = DFA eclk-domain Configuration Registers
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_eclkcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t sbdnum                  : 3;       /**< SBD Debug Entry#
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         Selects which one of 8 DFA Scoreboard entries is
-                                                         latched into the DFA_SBD_DBG[0-3] registers. */
-        uint64_t reserved_15_15          : 1;
-        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         When written with a '1', the DFA Scoreboard Debug
-                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
-                                                         This allows SW to lock down the contents of the entire
-                                                         SBD for a single instant in time. All subsequent reads
-                                                         of the DFA scoreboard registers will return the data
-                                                         from that instant in time. */
-        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
-                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
-                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
-                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
-                                                         Selects the arbitration mode used to select DFA requests
-                                                         issued from either CP2 or the DTE (NCB-CSR or DFA HW engine).
-                                                          - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
-                                                          - 1: Round-Robin
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t reserved_3_7            : 5;
-        uint64_t dteclkdis               : 1;       /**< DFA DTE Clock Disable
-                                                         When SET, the DFA clocks for DTE(thread engine)
-                                                         operation are disabled.
-                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
-                                                         the DFA via the NCB Bus. All DFA Operations must be
-                                                         issued solely through the CP2 interface. */
-        uint64_t maxbnk                  : 1;       /**< Maximum Banks per-device (used by the address mapper
-                                                         when extracting address bits for the memory bank#.
-                                                                 - 0: 4 banks/device
-                                                                 - 1: 8 banks/device */
-        uint64_t dfa_frstn               : 1;       /**< Hold this 0 until the DFA DDR PLL and DLL lock
-                                                         and then write a 1. A 1 on this register deasserts
-                                                         the internal frst_n. Refer to DFA_DDR2_PLL registers for more
-                                                         startup information.
-                                                         Startup sequence if DFA interface needs to be ON:
-                                                          After valid power up,
-                                                          Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS
-                                                          to the appropriate values
-                                                          Wait a few cycles
-                                                          Write a 1 DFA_DDR2_PLL -> PLL_INIT
-                                                          Wait 100 microseconds
-                                                          Write a 1 to DFA_DDR2_PLL -> QDLL_ENA
-                                                          Wait 10 microseconds
-                                                          Write a 1 to this register DFA_FRSTN to pull DFA out of
-                                                          reset
-                                                          Now the DFA block is ready to be initialized (follow the
-                                                          DDR init sequence). */
-#else
-        uint64_t dfa_frstn               : 1;
-        uint64_t maxbnk                  : 1;
-        uint64_t dteclkdis               : 1;
-        uint64_t reserved_3_7            : 5;
-        uint64_t sarb                    : 1;
-        uint64_t imode                   : 1;
-        uint64_t qmode                   : 1;
-        uint64_t pmode                   : 1;
-        uint64_t dtmode                  : 1;
-        uint64_t dcmode                  : 1;
-        uint64_t sbdlck                  : 1;
-        uint64_t reserved_15_15          : 1;
-        uint64_t sbdnum                  : 3;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_dfa_eclkcfg_s            cn31xx;
-} cvmx_dfa_eclkcfg_t;
-
-
-/**
- * cvmx_dfa_err
- *
- * DFA_ERR = DFA ERROR Register
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_33_63          : 31;
-        uint64_t dblina                  : 1;       /**< Doorbell Overflow Interrupt Enable bit.
-                                                         When set, doorbell overflow conditions are reported. */
-        uint64_t dblovf                  : 1;       /**< Doorbell Overflow detected - Status bit
-                                                         When set, the 20b accumulated doorbell register
-                                                         had overflowed (SW wrote too many doorbell requests).
-                                                         If the DBLINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         NOTE: Detection of a Doorbell Register overflow
-                                                         is a catastrophic error which may leave the DFA
-                                                         HW in an unrecoverable state. */
-        uint64_t cp2pina                 : 1;       /**< CP2 LW Mode Parity Error Interrupt Enable bit.
-                                                         When set, all PP-generated LW Mode read
-                                                         transactions which encounter a parity error (across
-                                                         the 36b of data) are reported. */
-        uint64_t cp2perr                 : 1;       /**< PP-CP2 Parity Error Detected - Status bit
-                                                         When set, a parity error had been detected for a
-                                                         PP-generated LW Mode read transaction.
-                                                         If the CP2PINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         See also: DFA_MEMFADR CSR which contains more data
-                                                         about the memory address/control to help isolate
-                                                         the failure. */
-        uint64_t cp2parena               : 1;       /**< CP2 LW Mode Parity Error Enable
-                                                         When set, all PP-generated LW Mode read
-                                                         transactions which encounter a parity error (across
-                                                         the 36b of data) are reported.
-                                                         NOTE: This signal must only be written to a different
-                                                         value when there are no PP-CP2 transactions
-                                                         (preferrably during power-on software initialization). */
-        uint64_t dtepina                 : 1;       /**< DTE Parity Error Interrupt Enable bit
-                                                         (for 18b SIMPLE mode ONLY).
-                                                         When set, all DTE-generated 18b SIMPLE Mode read
-                                                         transactions which encounter a parity error (across
-                                                         the 17b of data) are reported. */
-        uint64_t dteperr                 : 1;       /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY)
-                                                         When set, all DTE-generated 18b SIMPLE Mode read
-                                                         transactions which encounter a parity error (across
-                                                         the 17b of data) are reported. */
-        uint64_t dteparena               : 1;       /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY)
-                                                         When set, all DTE-generated 18b SIMPLE Mode read
-                                                         transactions which encounter a parity error (across
-                                                         the 17b of data) are reported.
-                                                         NOTE: This signal must only be written to a different
-                                                         value when there are no DFA thread engines active
-                                                         (preferrably during power-on). */
-        uint64_t dtesyn                  : 7;       /**< DTE 29b ECC Failing 6bit Syndrome
-                                                         When DTESBE or DTEDBE are set, this field contains
-                                                         the failing 7b ECC syndrome. */
-        uint64_t dtedbina                : 1;       /**< DTE 29b Double Bit Error Interrupt Enable bit
-                                                         When set, an interrupt is posted for any DTE-generated
-                                                         36b SIMPLE Mode read which encounters a double bit
-                                                         error. */
-        uint64_t dtesbina                : 1;       /**< DTE 29b Single Bit Error Interrupt Enable bit
-                                                         When set, an interrupt is posted for any DTE-generated
-                                                         36b SIMPLE Mode read which encounters a single bit
-                                                         error (which is also corrected). */
-        uint64_t dtedbe                  : 1;       /**< DTE 29b Double Bit Error Detected - Status bit
-                                                         When set, a double bit error had been detected
-                                                         for a DTE-generated 36b SIMPLE Mode read transaction.
-                                                         The DTESYN contains the failing syndrome.
-                                                         If the DTEDBINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         See also: DFA_MEMFADR CSR which contains more data
-                                                         about the memory address/control to help isolate
-                                                         the failure.
-                                                         NOTE: DTE-generated 18b SIMPLE Mode Read transactions
-                                                         do not participate in ECC check/correct). */
-        uint64_t dtesbe                  : 1;       /**< DTE 29b Single Bit Error Corrected - Status bit
-                                                         When set, a single bit error had been detected and
-                                                         corrected for a DTE-generated 36b SIMPLE Mode read
-                                                         transaction.
-                                                         If the DTEDBE=0, then the DTESYN contains the
-                                                         failing syndrome (used during correction).
-                                                         NOTE: DTE-generated 18b SIMPLE Mode Read
-                                                         transactions do not participate in ECC check/correct).
-                                                         If the DTESBINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         See also: DFA_MEMFADR CSR which contains more data
-                                                         about the memory address/control to help isolate
-                                                         the failure. */
-        uint64_t dteeccena               : 1;       /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY)
-                                                         When set, 29b ECC is enabled on all DTE-generated
-                                                         36b SIMPLE Mode read transactions.
-                                                         NOTE: This signal must only be written to a different
-                                                         value when there are no DFA thread engines active
-                                                         (preferrably during power-on software initialization). */
-        uint64_t cp2syn                  : 8;       /**< PP-CP2 QW ECC Failing 8bit Syndrome
-                                                         When CP2SBE or CP2DBE are set, this field contains
-                                                         the failing ECC 8b syndrome.
-                                                         Refer to CP2ECCENA. */
-        uint64_t cp2dbina                : 1;       /**< PP-CP2 Double Bit Error Interrupt Enable bit
-                                                         When set, an interrupt is posted for any PP-generated
-                                                         QW Mode read which encounters a double bit error.
-                                                         Refer to CP2DBE. */
-        uint64_t cp2sbina                : 1;       /**< PP-CP2 Single Bit Error Interrupt Enable bit
-                                                         When set, an interrupt is posted for any PP-generated
-                                                         QW Mode read which encounters a single bit error
-                                                         (which is also corrected).
-                                                         Refer to CP2SBE. */
-        uint64_t cp2dbe                  : 1;       /**< PP-CP2 Double Bit Error Detected - Status bit
-                                                         When set, a double bit error had been detected
-                                                         for a PP-generated QW Mode read transaction.
-                                                         The CP2SYN contains the failing syndrome.
-                                                          NOTE: PP-generated LW Mode Read transactions
-                                                         do not participate in ECC check/correct).
-                                                         Refer to CP2ECCENA.
-                                                         If the CP2DBINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         See also: DFA_MEMFADR CSR which contains more data
-                                                         about the memory address/control to help isolate
-                                                         the failure. */
-        uint64_t cp2sbe                  : 1;       /**< PP-CP2 Single Bit Error Corrected - Status bit
-                                                         When set, a single bit error had been detected and
-                                                         corrected for a PP-generated QW Mode read
-                                                         transaction.
-                                                         If the CP2DBE=0, then the CP2SYN contains the
-                                                         failing syndrome (used during correction).
-                                                         Refer to CP2ECCENA.
-                                                         If the CP2SBINA had previously been enabled(set),
-                                                         an interrupt will be posted. Software can clear
-                                                         the interrupt by writing a 1 to this register bit.
-                                                         See also: DFA_MEMFADR CSR which contains more data
-                                                         about the memory address/control to help isolate
-                                                         the failure.
-                                                         NOTE: PP-generated LW Mode Read transactions
-                                                         do not participate in ECC check/correct). */
-        uint64_t cp2eccena               : 1;       /**< PP-CP2 QW ECC Enable (for QW Mode transactions)
-                                                         When set, 8bit QW ECC is enabled on all PP-generated
-                                                         QW Mode read transactions, CP2SBE and
-                                                         CP2DBE may be set, and CP2SYN may be filled.
-                                                         NOTE: This signal must only be written to a different
-                                                         value when there are no PP-CP2 transactions
-                                                         (preferrably during power-on software initialization).
-                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
-                                                         by a processor core). LW refers to a 36-bit load/store. */
-#else
-        uint64_t cp2eccena               : 1;
-        uint64_t cp2sbe                  : 1;
-        uint64_t cp2dbe                  : 1;
-        uint64_t cp2sbina                : 1;
-        uint64_t cp2dbina                : 1;
-        uint64_t cp2syn                  : 8;
-        uint64_t dteeccena               : 1;
-        uint64_t dtesbe                  : 1;
-        uint64_t dtedbe                  : 1;
-        uint64_t dtesbina                : 1;
-        uint64_t dtedbina                : 1;
-        uint64_t dtesyn                  : 7;
-        uint64_t dteparena               : 1;
-        uint64_t dteperr                 : 1;
-        uint64_t dtepina                 : 1;
-        uint64_t cp2parena               : 1;
-        uint64_t cp2perr                 : 1;
-        uint64_t cp2pina                 : 1;
-        uint64_t dblovf                  : 1;
-        uint64_t dblina                  : 1;
-        uint64_t reserved_33_63          : 31;
-#endif
-    } s;
-    struct cvmx_dfa_err_s                cn31xx;
-    struct cvmx_dfa_err_s                cn38xx;
-    struct cvmx_dfa_err_s                cn38xxp2;
-    struct cvmx_dfa_err_s                cn58xx;
-    struct cvmx_dfa_err_s                cn58xxp1;
-} cvmx_dfa_err_t;
-
-
-/**
- * cvmx_dfa_memcfg0
- *
- * DFA_MEMCFG0 = DFA Memory Configuration
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memcfg0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rldqck90_rst            : 1;       /**< RLDCK90 and RLDQK90 DLL SW Reset
-                                                         When written with a '1' the RLDCK90 and RLDQK90 DLL are
-                                                         in soft-reset. */
-        uint64_t rldck_rst               : 1;       /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset
-                                                         When written with a '1' the RLDCK zero delay DLL is in
-                                                         soft-reset. */
-        uint64_t clkdiv                  : 2;       /**< RLDCLK Divisor Select
-                                                           - 0: RLDx_CK_H/L = Core Clock /2
-                                                           - 1: RESERVED (must not be used)
-                                                           - 2: RLDx_CK_H/L = Core Clock /3
-                                                           - 3: RLDx_CK_H/L = Core Clock /4
-                                                         The DFA LLM interface(s) are tied to the core clock
-                                                         frequency through this programmable clock divisor.
-                                                         Examples:
-                                                            Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV
-                                                           -----------------+--------------------+--------
-                                                                 800        |    400/(800-DDR)   |  /2
-                                                                1000        |    333/(666-DDR)   |  /3
-                                                                 800        |    200/(400-DDR)   |  /4
-                                                         NOTE: This value MUST BE programmed BEFORE doing a
-                                                         Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits).
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t lpp_ena                 : 1;       /**< PP Linear Port Addressing Mode Enable
-                                                         When enabled, PP-core LLM accesses to the lower-512MB
-                                                         LLM address space are sent to the single DFA port
-                                                         which is enabled. NOTE: If LPP_ENA=1, only
-                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
-                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
-                                                         PP-core LLM accesses to the upper-512MB LLM address
-                                                         space are sent to the other 'disabled' DFA port.
-                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
-                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
-                                                         ENA_P1 CAN NEVER BOTH be set).
-                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
-                                                         disabled port, such that each port can be sequentially
-                                                         addressed (ie: disable LW address interleaving).
-                                                         Enabling this bit allows BOTH PORTs to be active and
-                                                         sequentially addressable. The single port that is
-                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
-                                                         space, and the other 'disabled' port will respond to the
-                                                         high-512MB LLM address space.
-                                                         Example usage:
-                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
-                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
-                                                         USAGE NOTE:
-                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
-                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
-                                                         sequence WILL NOT occur for the disabled port.
-                                                         If LPP_ENA=1 and SW does initialize the disabled port
-                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
-                                                         the HW init sequence WILL occur to the disabled port. */
-        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
-                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
-                                                         b) during a normal refresh sequence. If
-                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
-                                                         NOTE: This is required for DRAM used in a
-                                                         clamshell configuration, since the address lines
-                                                         carry Mode Register write data that is unique
-                                                         per bunk(or clam). In a clamshell configuration,
-                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
-                                                         and also into Clam#1's 'mirrored' address bit A[y]
-                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
-                                                         To support clamshell designs, SW must initiate
-                                                         two separate HW init sequences for the two bunks
-                                                         (or clams) . Before each HW init sequence is triggered,
-                                                         SW must preload the DFA_MEMRLD[22:0] with the data
-                                                         that will be driven onto the A[22:0] wires during
-                                                         an MRS mode register write.
-                                                         NOTE: After the final HW initialization sequence has
-                                                         been triggered, SW must wait 64K eclks before writing
-                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
-                                                         driven during refresh sequences in normal operation.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#0 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
-                                                              RLDRAM operation.
-                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
-                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
-                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
-                                                              the SAME TIME. This step puts all three DLLs in
-                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
-                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
-                                                              This step takes the RLDCK DLL out of soft-reset so
-                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
-                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
-                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
-                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
-                                                              of soft-reset.
-                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
-                                                           7) Enable memory port(s):  ENA_P0=1/ENA_P1=1
-                                                           8) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           - - - - - Hardware Initialization Sequence - - - - -
-                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
-                                                              intended to be initialized.
-                                                          10) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence to that'specific' port.
-                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
-                                                              [to ensure the HW init sequence has completed
-                                                              before writing to ANY of the DFA_MEM* registers]
-                                                           - - - - - Hardware Initialization Sequence - - - - -
-                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
-                                                              refreshes to BOTH bunks.
-                                                         NOTE: In some cases (where the address wires are routed
-                                                         differently between the front and back 'bunks'),
-                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
-                                                         control the Hardware initialization sequence for a
-                                                         'specific bunk'. In these cases, SW would setup the
-                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#1 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
-                                                              RLDRAM operation.
-                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
-                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
-                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
-                                                              the SAME TIME. This step puts all three DLLs in
-                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
-                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
-                                                              This step takes the RLDCK DLL out of soft-reset so
-                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
-                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
-                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
-                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
-                                                              of soft-reset.
-                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
-                                                           7) Enable memory port(s) ENA_P0=1/ENA_P1=1
-                                                           8) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           - - - - - Hardware Initialization Sequence - - - - -
-                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
-                                                              intended to be initialized.
-                                                          10) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence to that'specific' port.
-                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
-                                                              [to ensure the HW init sequence has completed
-                                                              before writing to ANY of the DFA_MEM* registers]
-                                                           - - - - - Hardware Initialization Sequence - - - - -
-                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
-                                                              refreshes to BOTH bunks.
-                                                         NOTE: In some cases (where the address wires are routed
-                                                         differently between the front and back 'bunks'),
-                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
-                                                         control the Hardware initialization sequence for a
-                                                         'specific bunk'. In these cases, SW would setup the
-                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
-                                                         if back to back reads are issued to different physical
-                                                         bunks. This is to avoid DQ data bus collisions when
-                                                         references cross between physical bunks.
-                                                         [NOTE: the physical bunk address boundary is determined
-                                                         by the PBUNK bit].
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
-                                                         Specifies which address bit within the Longword
-                                                         Memory address MA[23:0] is used to determine the
-                                                         chip selects.
-                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
-                                                         RLD_CS1_N corresponds to physical bunk \#1].
-                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
-                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
-                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
-                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
-                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
-                                                           - 101-111: CS0_N = 0 /CS1_N = 1
-                                                         Example(s):
-                                                         To build out a 128MB DFA memory, 4x 32Mx9
-                                                         parts could be used to fill out TWO physical
-                                                         bunks (clamshell configuration). Each (of the
-                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
-                                                         Each RLDRAM device also contains 8 internal banks,
-                                                         therefore the memory Address is 16M/8banks = 2M
-                                                         addresses/bunk (2^21). In this case, MA[21] would
-                                                         select the physical bunk.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         be used to determine the Chip Select(s). */
-        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
-                                                         NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */
-        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable back porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable front porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from write to read. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II(BL2): (TBL=1)
-                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
-                                                         on W->R transitions is not pronounced. */
-        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from read to write. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II(BL2): (TBL=1)
-                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
-                                                         on R->W transitions is not pronounced. */
-        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
-                                                         additional dclks to wait (on top of tRL+1) before
-                                                         pulling data out of the padring silos used for time
-                                                         domain boundary crossing.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t mtype                   : 1;       /**< FCRAM-II Memory Type
-                                                         *** O9N UNSUPPORTED *** */
-        uint64_t reserved_2_2            : 1;
-        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#0.
-                                                         NOTE: a customer is at
-                                                         liberty to enable either Port#0 or Port#1 or both.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#1.
-                                                         NOTE: a customer is at
-                                                         liberty to enable either Port#0 or Port#1 or both.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-#else
-        uint64_t ena_p1                  : 1;
-        uint64_t ena_p0                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t mtype                   : 1;
-        uint64_t sil_lat                 : 2;
-        uint64_t rw_dly                  : 4;
-        uint64_t wr_dly                  : 4;
-        uint64_t fprch                   : 2;
-        uint64_t bprch                   : 2;
-        uint64_t blen                    : 1;
-        uint64_t pbunk                   : 3;
-        uint64_t r2r_pbunk               : 1;
-        uint64_t init_p1                 : 1;
-        uint64_t init_p0                 : 1;
-        uint64_t bunk_init               : 2;
-        uint64_t lpp_ena                 : 1;
-        uint64_t clkdiv                  : 2;
-        uint64_t rldck_rst               : 1;
-        uint64_t rldqck90_rst            : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_dfa_memcfg0_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lpp_ena                 : 1;       /**< PP Linear Port Addressing Mode Enable
-                                                         When enabled, PP-core LLM accesses to the lower-512MB
-                                                         LLM address space are sent to the single DFA port
-                                                         which is enabled. NOTE: If LPP_ENA=1, only
-                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
-                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
-                                                         PP-core LLM accesses to the upper-512MB LLM address
-                                                         space are sent to the other 'disabled' DFA port.
-                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
-                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
-                                                         ENA_P1 CAN NEVER BOTH be set).
-                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
-                                                         disabled port, such that each port can be sequentially
-                                                         addressed (ie: disable LW address interleaving).
-                                                         Enabling this bit allows BOTH PORTs to be active and
-                                                         sequentially addressable. The single port that is
-                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
-                                                         space, and the other 'disabled' port will respond to the
-                                                         high-512MB LLM address space.
-                                                         Example usage:
-                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
-                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
-                                                         USAGE NOTE:
-                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
-                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
-                                                         sequence WILL NOT occur for the disabled port.
-                                                         If LPP_ENA=1 and SW does initialize the disabled port
-                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
-                                                         the HW init sequence WILL occur to the disabled port. */
-        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
-                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
-                                                         b) during a normal refresh sequence. If
-                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
-                                                         NOTE: This is required for DRAM used in a
-                                                         clamshell configuration, since the address lines
-                                                         carry Mode Register write data that is unique
-                                                         per bunk(or clam). In a clamshell configuration,
-                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
-                                                         and also into Clam#1's 'mirrored' address bit A[y]
-                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
-                                                         To support clamshell designs, SW must initiate
-                                                         two separate HW init sequences for the two bunks
-                                                         (or clams) . Before each HW init sequence is triggered,
-                                                         SW must preload the DFA_MEMRLD[22:0] with the data
-                                                         that will be driven onto the A[22:0] wires during
-                                                         an MRS mode register write.
-                                                         NOTE: After the final HW initialization sequence has
-                                                         been triggered, SW must wait 64K eclks before writing
-                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
-                                                         driven during refresh sequences in normal operation.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
-                                                         initialized independently. In other words, a HW init
-                                                         must be done for Bunk#0, and then another HW init
-                                                         must be done for Bunk#1 at power-on. */
-        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#0 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Enable memory port(s):
-                                                               a) ENA_P1=1 (single port in pass 1) OR
-                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
-                                                           2) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           3) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence.
-                                                         NOTE: After writing a '1', SW must wait 64K eclk
-                                                         cycles to ensure the HW init sequence has completed
-                                                         before writing to ANY of the DFA_MEM* registers.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#1 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Enable memory port(s):
-                                                               a) ENA_P1=1 (single port in pass 1) OR
-                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
-                                                           2) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           3) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence.
-                                                         NOTE: After writing a '1', SW must wait 64K eclk
-                                                         cycles to ensure the HW init sequence has completed
-                                                         before writing to ANY of the DFA_MEM* registers.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
-                                                         if back to back reads are issued to different physical
-                                                         bunks. This is to avoid DQ data bus collisions when
-                                                         references cross between physical bunks.
-                                                         [NOTE: the physical bunk address boundary is determined
-                                                         by the PBUNK bit].
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
-                                                         ZERO(for optimal performance). However, if electrically,
-                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
-                                                         should be set (but at a cost to performance (1/2 BW). */
-        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
-                                                         Specifies which address bit within the Longword
-                                                         Memory address MA[23:0] is used to determine the
-                                                         chip selects.
-                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
-                                                         RLD_CS1_N corresponds to physical bunk \#1].
-                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
-                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
-                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
-                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
-                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
-                                                           - 101-111: CS0_N = 0 /CS1_N = 1
-                                                         Example(s):
-                                                         To build out a 128MB DFA memory, 4x 32Mx9
-                                                         parts could be used to fill out TWO physical
-                                                         bunks (clamshell configuration). Each (of the
-                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
-                                                         Each RLDRAM device also contains 8 internal banks,
-                                                         therefore the memory Address is 16M/8banks = 2M
-                                                         addresses/bunk (2^21). In this case, MA[21] would
-                                                         select the physical bunk.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         be used to determine the Chip Select(s).
-                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
-                                                         "Redundant Bunk" scheme is employed to provide the
-                                                         highest overall performance (1 Req/ MCLK cycle).
-                                                         In this mode, it's imperative that SW set the PBUNK
-                                                         field +1 'above' the highest address bit. (such that
-                                                         the PBUNK extracted from the address will always be
-                                                         zero). In this mode, the CS_N[1:0] pins are driven
-                                                         to each redundant bunk based on a TDM scheme:
-                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
-        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
-                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
-                                                         decomposed into 2 separate BL2(LW) requests to the
-                                                         Low-Latency memory.
-                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
-                                                         treated as 1 BL4(QW) request to the low latency memory.
-                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
-                                                         by a processor core). LW refers to a 36-bit load/store.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization before the DFA LLM
-                                                         (low latency memory) is used.
-                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
-                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
-                                                         multi-bunk(clam) board design.
-                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
-                                                         SW SHOULD use CP2 QW read/write requests (for
-                                                         optimal low-latency bus performance).
-                                                         [LW length read/write requests(in BL4 mode) use 50%
-                                                         of the available bus bandwidth]
-                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
-                                                         be used with FCRAM-II devices which support BL2 mode
-                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
-                                                         transfers).
-                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
-                                                         write requests (FCRAM-II+ device specification has removed
-                                                         the variable write mask function from the devices).
-                                                         As such, if this mode is used, SW must be careful to
-                                                         issue only PP-CP2 QW write requests. */
-        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable back porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable front porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from write to read. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II(BL2): (TBL=1)
-                                                         For FCRAM-II (BL4): (TBL=2)
-                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
-                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
-                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
-                                                            grepl>=2x, writes require redundant bunk writes
-                                                            which require an additional 2 cycles before slotting
-                                                            the next read.
-                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
-                                                         on W->R transitions is not pronounced. */
-        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from read to write. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
-                                                         For FCRAM-II (BL4): (TBL=2)
-                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
-                                                         on R->W transitions is not pronounced. */
-        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
-                                                         additional dclks to wait (on top of tRL+1) before
-                                                         pulling data out of the padring silos used for time
-                                                         domain boundary crossing.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t mtype                   : 1;       /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
-                                                         NOTE: N3K-P1 only supports RLDRAM-II
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
-                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
-                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
-                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
-                                                         in a clamshell configuration such that clam0 is
-                                                         addressed independently of clam1, and DQ is shared
-                                                         for optimal performance. As such it's imperative that
-                                                         the QS are conditionally received (and are NOT
-                                                         free-running), as the N3K receive data capture silos
-                                                         OR the clam0/1 QS strobes.
-                                                         NOTE: If this bit is SET, the ASX0/1
-                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
-                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
-        uint64_t reserved_2_2            : 1;
-        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#0.
-                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
-                                                         Port#1 MUST ALSO be enabled.
-                                                         NOTE: For N3K-P2, single port mode, a customer is at
-                                                         liberty to enable either Port#0 or Port#1.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#1.
-                                                         NOTE: For N3K-P1, If the customer wishes to use a
-                                                         single port, s/he must enable Port#1 (and not Port#0).
-                                                         NOTE: For N3K-P2, single port mode, a customer is at
-                                                         liberty to enable either Port#0 or Port#1.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-#else
-        uint64_t ena_p1                  : 1;
-        uint64_t ena_p0                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t mtype                   : 1;
-        uint64_t sil_lat                 : 2;
-        uint64_t rw_dly                  : 4;
-        uint64_t wr_dly                  : 4;
-        uint64_t fprch                   : 2;
-        uint64_t bprch                   : 2;
-        uint64_t blen                    : 1;
-        uint64_t pbunk                   : 3;
-        uint64_t r2r_pbunk               : 1;
-        uint64_t init_p1                 : 1;
-        uint64_t init_p0                 : 1;
-        uint64_t bunk_init               : 2;
-        uint64_t lpp_ena                 : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn38xx;
-    struct cvmx_dfa_memcfg0_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
-                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
-                                                         b) during a normal refresh sequence. If
-                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
-                                                         NOTE: This is required for DRAM used in a
-                                                         clamshell configuration, since the address lines
-                                                         carry Mode Register write data that is unique
-                                                         per bunk(or clam). In a clamshell configuration,
-                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
-                                                         and also into Clam#1's 'mirrored' address bit A[y]
-                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
-                                                         To support clamshell designs, SW must initiate
-                                                         two separate HW init sequences for the two bunks
-                                                         (or clams) . Before each HW init sequence is triggered,
-                                                         SW must preload the DFA_MEMRLD[22:0] with the data
-                                                         that will be driven onto the A[22:0] wires during
-                                                         an MRS mode register write.
-                                                         NOTE: After the final HW initialization sequence has
-                                                         been triggered, SW must wait 64K eclks before writing
-                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
-                                                         driven during refresh sequences in normal operation.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
-                                                         initialized independently. In other words, a HW init
-                                                         must be done for Bunk#0, and then another HW init
-                                                         must be done for Bunk#1 at power-on. */
-        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#0 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Enable memory port(s):
-                                                               a) ENA_P1=1 (single port in pass 1) OR
-                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
-                                                           2) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           3) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence.
-                                                         NOTE: After writing a '1', SW must wait 64K eclk
-                                                         cycles to ensure the HW init sequence has completed
-                                                         before writing to ANY of the DFA_MEM* registers.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
-                                                         the HW init sequence(s) for Memory Port \#1 is
-                                                         initiated.
-                                                         NOTE: To initialize memory, SW must:
-                                                           1) Enable memory port(s):
-                                                               a) ENA_P1=1 (single port in pass 1) OR
-                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
-                                                           2) Wait 100us (to ensure a stable clock
-                                                              to the RLDRAMs) - as per RLDRAM spec.
-                                                           3) Write a '1' to the corresponding INIT_Px which
-                                                              will initiate a hardware initialization
-                                                              sequence.
-                                                         NOTE: After writing a '1', SW must wait 64K eclk
-                                                         cycles to ensure the HW init sequence has completed
-                                                         before writing to ANY of the DFA_MEM* registers.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
-                                                         if back to back reads are issued to different physical
-                                                         bunks. This is to avoid DQ data bus collisions when
-                                                         references cross between physical bunks.
-                                                         [NOTE: the physical bunk address boundary is determined
-                                                         by the PBUNK bit].
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
-                                                         ZERO(for optimal performance). However, if electrically,
-                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
-                                                         should be set (but at a cost to performance (1/2 BW). */
-        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
-                                                         Specifies which address bit within the Longword
-                                                         Memory address MA[23:0] is used to determine the
-                                                         chip selects.
-                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
-                                                         RLD_CS1_N corresponds to physical bunk \#1].
-                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
-                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
-                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
-                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
-                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
-                                                           - 101-111: CS0_N = 0 /CS1_N = 1
-                                                         Example(s):
-                                                         To build out a 128MB DFA memory, 4x 32Mx9
-                                                         parts could be used to fill out TWO physical
-                                                         bunks (clamshell configuration). Each (of the
-                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
-                                                         Each RLDRAM device also contains 8 internal banks,
-                                                         therefore the memory Address is 16M/8banks = 2M
-                                                         addresses/bunk (2^21). In this case, MA[21] would
-                                                         select the physical bunk.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         be used to determine the Chip Select(s).
-                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
-                                                         "Redundant Bunk" scheme is employed to provide the
-                                                         highest overall performance (1 Req/ MCLK cycle).
-                                                         In this mode, it's imperative that SW set the PBUNK
-                                                         field +1 'above' the highest address bit. (such that
-                                                         the PBUNK extracted from the address will always be
-                                                         zero). In this mode, the CS_N[1:0] pins are driven
-                                                         to each redundant bunk based on a TDM scheme:
-                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
-        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
-                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
-                                                         decomposed into 2 separate BL2(LW) requests to the
-                                                         Low-Latency memory.
-                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
-                                                         treated as 1 BL4(QW) request to the low latency memory.
-                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
-                                                         by a processor core). LW refers to a 36-bit load/store.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization before the DFA LLM
-                                                         (low latency memory) is used.
-                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
-                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
-                                                         multi-bunk(clam) board design.
-                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
-                                                         SW SHOULD use CP2 QW read/write requests (for
-                                                         optimal low-latency bus performance).
-                                                         [LW length read/write requests(in BL4 mode) use 50%
-                                                         of the available bus bandwidth]
-                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
-                                                         be used with FCRAM-II devices which support BL2 mode
-                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
-                                                         transfers).
-                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
-                                                         write requests (FCRAM-II+ device specification has removed
-                                                         the variable write mask function from the devices).
-                                                         As such, if this mode is used, SW must be careful to
-                                                         issue only PP-CP2 QW write requests. */
-        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable back porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
-                                                         On reads, allows user to control the shape of the
-                                                         tristate disable front porch for the DQ data bus.
-                                                         This parameter is also very dependent on the
-                                                         RW_DLY and WR_DLY parameters and care must be
-                                                         taken when programming these parameters to avoid
-                                                         data bus contention. Valid range [0..2]
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from write to read. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II(BL2): (TBL=1)
-                                                         For FCRAM-II (BL4): (TBL=2)
-                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
-                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
-                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
-                                                            grepl>=2x, writes require redundant bunk writes
-                                                            which require an additional 2 cycles before slotting
-                                                            the next read.
-                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
-                                                         on W->R transitions is not pronounced. */
-        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
-                                                         Determines \#mclk cycles to insert when controller
-                                                         switches from read to write. This allows programmer
-                                                         to control the data bus contention.
-                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
-                                                         For FCRAM-II (BL4): (TBL=2)
-                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: For aggressive(performance optimal) designs,
-                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
-                                                         on R->W transitions is not pronounced. */
-        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
-                                                         additional dclks to wait (on top of tRL+1) before
-                                                         pulling data out of the padring silos used for time
-                                                         domain boundary crossing.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t mtype                   : 1;       /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
-                                                         NOTE: N3K-P1 only supports RLDRAM-II
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
-                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
-                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
-                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
-                                                         in a clamshell configuration such that clam0 is
-                                                         addressed independently of clam1, and DQ is shared
-                                                         for optimal performance. As such it's imperative that
-                                                         the QS are conditionally received (and are NOT
-                                                         free-running), as the N3K receive data capture silos
-                                                         OR the clam0/1 QS strobes.
-                                                         NOTE: If this bit is SET, the ASX0/1
-                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
-                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
-        uint64_t reserved_2_2            : 1;
-        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#0.
-                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
-                                                         Port#1 MUST ALSO be enabled.
-                                                         NOTE: For N3K-P2, single port mode, a customer is at
-                                                         liberty to enable either Port#0 or Port#1.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
-                                                         RLD0_* pins. */
-        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
-                                                         When enabled, this bit lets N3K be the default
-                                                         driver for memory port \#1.
-                                                         NOTE: For N3K-P1, If the customer wishes to use a
-                                                         single port, s/he must enable Port#1 (and not Port#0).
-                                                         NOTE: For N3K-P2, single port mode, a customer is at
-                                                         liberty to enable either Port#0 or Port#1.
-                                                         NOTE: Once a port has been disabled, it MUST NEVER
-                                                         be re-enabled. [the only way to enable a port is
-                                                         through a chip reset].
-                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
-                                                         RLD1_* pins. */
-#else
-        uint64_t ena_p1                  : 1;
-        uint64_t ena_p0                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t mtype                   : 1;
-        uint64_t sil_lat                 : 2;
-        uint64_t rw_dly                  : 4;
-        uint64_t wr_dly                  : 4;
-        uint64_t fprch                   : 2;
-        uint64_t bprch                   : 2;
-        uint64_t blen                    : 1;
-        uint64_t pbunk                   : 3;
-        uint64_t r2r_pbunk               : 1;
-        uint64_t init_p1                 : 1;
-        uint64_t init_p0                 : 1;
-        uint64_t bunk_init               : 2;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn38xxp2;
-    struct cvmx_dfa_memcfg0_s            cn58xx;
-    struct cvmx_dfa_memcfg0_s            cn58xxp1;
-} cvmx_dfa_memcfg0_t;
-
-
-/**
- * cvmx_dfa_memcfg1
- *
- * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memcfg1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ref_intlo               : 9;       /**< Burst Refresh Interval[8:0] (\#dclks)
-                                                         For finer refresh interval granularity control.
-                                                         This field provides an additional level of granularity
-                                                         for the refresh interval. It specifies the additional
-                                                         \#dclks [0...511] to be added to the REF_INT[3:0] field.
-                                                         For RLDRAM-II: For dclk(400MHz=2.5ns):
-                                                         Example: 64K AREF cycles required within tREF=32ms
-                                                             trefint = tREF(ms)/(64K cycles/8banks)
-                                                                         = 32ms/8K = 3.9us = 3900ns
-                                                             REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512]
-                                                                          = ROUND_DOWN[(3900/2.5)/512]
-                                                                          = 3
-                                                             REF_INTLO[8:0] = MOD[(trefint/dclk)/512]
-                                                                            = MOD[(3900/2.5)/512]
-                                                                            = 24
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t aref_ena                : 1;       /**< Auto Refresh Cycle Enable
-                                                         INTERNAL USE ONLY:
-                                                         NOTE: This mode bit is ONLY intended to be used by
-                                                         low-level power-on initialization routines in the
-                                                         event that the hardware initialization routine
-                                                         does not work. It allows SW to create AREF
-                                                         commands on the RLDRAM bus directly.
-                                                         When this bit is set, ALL RLDRAM writes (issued by
-                                                         a PP through the NCB or CP2) are converted to AREF
-                                                         commands on the RLDRAM bus. The write-address is
-                                                         presented on the A[20:0]/BA[2:0] pins (for which
-                                                         the RLDRAM only interprets BA[2:0]).
-                                                         When this bit is set, only writes are allowed
-                                                         and MUST use grepl=0 (1x).
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
-                                                         (SW can set one or the other, but never both!)
-                                                         NOTE: AREF commands generated using this method target
-                                                         the 'addressed' bunk. */
-        uint64_t mrs_ena                 : 1;       /**< Mode Register Set Cycle Enable
-                                                         INTERNAL USE ONLY:
-                                                         NOTE: This mode bit is ONLY intended to be used by
-                                                         low-level power-on initialization routines in the
-                                                         event that the hardware initialization routine
-                                                         does not work. It allows SW to create MRS
-                                                         commands on the RLDRAM bus directly.
-                                                         When this bit is set, ALL RLDRAM writes (issued by
-                                                         a PP through the NCB or CP2) are converted to MRS
-                                                         commands on the RLDRAM bus. The write-address is
-                                                         presented on the A[20:0]/BA[2:0] pins (for which
-                                                         the RLDRAM only interprets A[17:0]).
-                                                         When this bit is set, only writes are allowed
-                                                         and MUST use grepl=0 (1x).
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization.
-                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
-                                                         (SW can set one or the other, but never both!)
-                                                         NOTE: MRS commands generated using this method target
-                                                         the 'addressed' bunk. */
-        uint64_t tmrsc                   : 3;       /**< Mode Register Set Cycle Time (represented in \#mclks)
-                                                              - 000-001: RESERVED
-                                                              - 010: tMRSC = 2 mclks
-                                                              - 011: tMRSC = 3 mclks
-                                                              - ...
-                                                              - 111: tMRSC = 7 mclks
-                                                         NOTE: The device tMRSC parameter is a function of CL
-                                                         (which during HW initialization is not known. Its
-                                                         recommended to load tMRSC(MAX) value to avoid timing
-                                                         violations.
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t trc                     : 4;       /**< Row Cycle Time (represented in \#mclks)
-                                                         see also: DFA_MEMRLD[RLCFG] field which must
-                                                         correspond with tRL/tWL parameter(s).
-                                                              - 0000-0010: RESERVED
-                                                              - 0011: tRC = 3 mclks
-                                                              - 0100: tRC = 4 mclks
-                                                              - 0101: tRC = 5 mclks
-                                                              - 0110: tRC = 6 mclks
-                                                              - 0111: tRC = 7 mclks
-                                                              - 1000: tRC = 8 mclks
-                                                              - 1001: tRC = 9 mclks
-                                                              - 1010-1111: RESERVED
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t twl                     : 4;       /**< Write Latency (represented in \#mclks)
-                                                         see also: DFA_MEMRLD[RLCFG] field which must
-                                                         correspond with tRL/tWL parameter(s).
-                                                              - 0000-0001: RESERVED
-                                                              - 0010: Write Latency (WL=2.0 mclk)
-                                                              - 0011: Write Latency (WL=3.0 mclks)
-                                                              - 0100: Write Latency (WL=4.0 mclks)
-                                                              - 0101: Write Latency (WL=5.0 mclks)
-                                                              - 0110: Write Latency (WL=6.0 mclks)
-                                                              - 0111: Write Latency (WL=7.0 mclks)
-                                                              - 1000: Write Latency (WL=8.0 mclks)
-                                                              - 1001: Write Latency (WL=9.0 mclks)
-                                                              - 1010: Write Latency (WL=10.0 mclks)
-                                                              - 1011-1111: RESERVED
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t trl                     : 4;       /**< Read Latency (represented in \#mclks)
-                                                         see also: DFA_MEMRLD[RLCFG] field which must
-                                                         correspond with tRL/tWL parameter(s).
-                                                              - 0000-0010: RESERVED
-                                                              - 0011: Read Latency = 3 mclks
-                                                              - 0100: Read Latency = 4 mclks
-                                                              - 0101: Read Latency = 5 mclks
-                                                              - 0110: Read Latency = 6 mclks
-                                                              - 0111: Read Latency = 7 mclks
-                                                              - 1000: Read Latency = 8 mclks
-                                                              - 1001: Read Latency = 9 mclks
-                                                              - 1010: Read Latency = 10 mclks
-                                                              - 1011-1111: RESERVED
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t reserved_6_7            : 2;
-        uint64_t tskw                    : 2;       /**< Board Skew (represented in \#dclks)
-                                                         Represents additional board skew of DQ/DQS.
-                                                             - 00: board-skew = 0 dclk
-                                                             - 01: board-skew = 1 dclk
-                                                             - 10: board-skew = 2 dclk
-                                                             - 11: board-skew = 3 dclk
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t ref_int                 : 4;       /**< Refresh Interval (represented in \#of 512 dclk
-                                                         increments).
-                                                              - 0000: RESERVED
-                                                              - 0001: 1 * 512  = 512 dclks
-                                                              - ...
-                                                              - 1111: 15 * 512 = 7680 dclks
-                                                         NOTE: For finer level of granularity, refer to
-                                                         REF_INTLO[8:0] field.
-                                                         For RLDRAM-II, each refresh interval will
-                                                         generate a burst of 8 AREF commands, one to each of
-                                                         8 explicit banks (referenced using the RLD_BA[2:0]
-                                                         pins.
-                                                         Example: For mclk=200MHz/dclk(400MHz=2.5ns):
-                                                           64K AREF cycles required within tREF=32ms
-                                                             trefint = tREF(ms)/(64K cycles/8banks)
-                                                                     = 32ms/8K = 3.9us = 3900ns
-                                                             REF_INT = ROUND_DOWN[(trefint/dclk)/512]
-                                                                     = ROUND_DOWN[(3900/2.5)/512]
-                                                                     = 3
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-#else
-        uint64_t ref_int                 : 4;
-        uint64_t tskw                    : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t trl                     : 4;
-        uint64_t twl                     : 4;
-        uint64_t trc                     : 4;
-        uint64_t tmrsc                   : 3;
-        uint64_t mrs_ena                 : 1;
-        uint64_t aref_ena                : 1;
-        uint64_t ref_intlo               : 9;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_dfa_memcfg1_s            cn38xx;
-    struct cvmx_dfa_memcfg1_s            cn38xxp2;
-    struct cvmx_dfa_memcfg1_s            cn58xx;
-    struct cvmx_dfa_memcfg1_s            cn58xxp1;
-} cvmx_dfa_memcfg1_t;
-
-
-/**
- * cvmx_dfa_memcfg2
- *
- * DFA_MEMCFG2 = DFA Memory Config Register \#2
- * *** NOTE: Pass2 Addition
- * 
- * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memcfg2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t dteclkdis               : 1;       /**< DFA DTE Clock Disable
-                                                         When SET, the DFA clocks for DTE(thread engine)
-                                                         operation are disabled.
-                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
-                                                         the DFA via the NCB Bus. All DFA Operations must be
-                                                         issued solely through the CP2 interface.
-                                                         *** NOTE: PASS2 Addition
-                                                         NOTE: When DTECLKDIS=1, if CP2 Errors are encountered
-                                                         (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR
-                                                         does not reflect the failing address/ctl information. */
-        uint64_t silrst                  : 1;       /**< LLM-PHY Silo Reset
-                                                         When a '1' is written (when the previous
-                                                         value was a '0') causes the the LLM-PHY Silo read/write
-                                                         pointers to be reset.
-                                                         NOTE: SW MUST WAIT 400 dclks after the LAST HW Init
-                                                         sequence was launched (ie: INIT_START 0->1 CSR write),
-                                                         before the SILRST can be triggered (0->1). */
-        uint64_t trfc                    : 5;       /**< FCRAM-II Refresh Interval
-                                                         *** O9N UNSUPPORTED *** */
-        uint64_t refshort                : 1;       /**< FCRAM Short Refresh Mode
-                                                         *** O9N UNSUPPORTED *** */
-        uint64_t ua_start                : 2;       /**< FCRAM-II Upper Addres Start
-                                                         *** O9N UNSUPPORTED *** */
-        uint64_t maxbnk                  : 1;       /**< Maximum Banks per-device (used by the address mapper
-                                                         when extracting address bits for the memory bank#.
-                                                           - 0: 4 banks/device
-                                                           - 1: 8 banks/device
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t fcram2p                 : 1;       /**< FCRAM-II+ Mode Enable
-                                                         *** O9N UNSUPPORTED *** */
-#else
-        uint64_t fcram2p                 : 1;
-        uint64_t maxbnk                  : 1;
-        uint64_t ua_start                : 2;
-        uint64_t refshort                : 1;
-        uint64_t trfc                    : 5;
-        uint64_t silrst                  : 1;
-        uint64_t dteclkdis               : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_dfa_memcfg2_s            cn38xx;
-    struct cvmx_dfa_memcfg2_s            cn38xxp2;
-    struct cvmx_dfa_memcfg2_s            cn58xx;
-    struct cvmx_dfa_memcfg2_s            cn58xxp1;
-} cvmx_dfa_memcfg2_t;
-
-
-/**
- * cvmx_dfa_memfadr
- *
- * DFA_MEMFADR = RLDRAM Failing Address/Control Register
- * 
- * Description: DFA Memory Failing Address/Control Error Capture information
- * This register contains useful information to help in isolating an RLDRAM memory failure.
- * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is
- * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt
- * via the FSRC field.
- * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memfadr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t maddr                   : 24;      /**< Memory Address */
-#else
-        uint64_t maddr                   : 24;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_dfa_memfadr_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t fdst                    : 9;       /**< Fill-Destination
-                                                            FSRC[1:0]    | FDST[8:0]
-                                                            -------------+-------------------------------------
-                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
-                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
-                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
-                                                           where:
-                                                               DTE: DFA Thread Engine ID#
-                                                               PP: Packet Processor ID#
-                                                               FID: Fill-ID# (unique per PP)
-                                                               WIDX:  16b SIMPLE Mode (index)
-                                                               DMODE: (0=16b SIMPLE/1=32b SIMPLE)
-                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
-                                                               INDEX: (0=Low LW/1=High LW)
-                                                         NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated
-                                                         by a processor core). LW refers to a 32-bit load/store. */
-        uint64_t fsrc                    : 2;       /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
-        uint64_t pnum                    : 1;       /**< Memory Port
-                                                         NOTE: For O2P, this bit will always return zero. */
-        uint64_t bnum                    : 3;       /**< Memory Bank
-                                                         When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0].
-                                                         (RANK[1] can be inferred from MADDR[24:0]) */
-        uint64_t maddr                   : 25;      /**< Memory Address */
-#else
-        uint64_t maddr                   : 25;
-        uint64_t bnum                    : 3;
-        uint64_t pnum                    : 1;
-        uint64_t fsrc                    : 2;
-        uint64_t fdst                    : 9;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } cn31xx;
-    struct cvmx_dfa_memfadr_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t fdst                    : 9;       /**< Fill-Destination
-                                                            FSRC[1:0]    | FDST[8:0]
-                                                            -------------+-------------------------------------
-                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
-                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
-                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
-                                                           where:
-                                                               DTE: DFA Thread Engine ID#
-                                                               PP: Packet Processor ID#
-                                                               FID: Fill-ID# (unique per PP)
-                                                               WIDX:  18b SIMPLE Mode (index)
-                                                               DMODE: (0=18b SIMPLE/1=36b SIMPLE)
-                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
-                                                               INDEX: (0=Low LW/1=High LW)
-                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
-                                                         by a processor core). LW refers to a 36-bit load/store. */
-        uint64_t fsrc                    : 2;       /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
-        uint64_t pnum                    : 1;       /**< Memory Port
-                                                         NOTE: the port id's are reversed
-                                                            PNUM==0 => port#1
-                                                            PNUM==1 => port#0 */
-        uint64_t bnum                    : 3;       /**< Memory Bank */
-        uint64_t maddr                   : 24;      /**< Memory Address */
-#else
-        uint64_t maddr                   : 24;
-        uint64_t bnum                    : 3;
-        uint64_t pnum                    : 1;
-        uint64_t fsrc                    : 2;
-        uint64_t fdst                    : 9;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } cn38xx;
-    struct cvmx_dfa_memfadr_cn38xx       cn38xxp2;
-    struct cvmx_dfa_memfadr_cn38xx       cn58xx;
-    struct cvmx_dfa_memfadr_cn38xx       cn58xxp1;
-} cvmx_dfa_memfadr_t;
-
-
-/**
- * cvmx_dfa_memfcr
- *
- * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0]
- * *** O9N UNSUPPORTED ***
- *
- * Notes:
- * For FCRAM-II please consult your device's data sheet for further details:
- * MRS Definition:
- *    A[13:8]=0   RESERVED
- *    A[7]=0      TEST MODE     (N3K requires test mode 0:"disabled")
- *    A[6:4]      CAS LATENCY   (fully programmable - SW must ensure that the value programmed
- *                               into DFA_MEM_CFG0[TRL] corresponds with this value).
- *    A[3]=0      BURST TYPE    (N3K requires 0:"Sequential" Burst Type)
- *    A[2:0]      BURST LENGTH  Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4)
- * 
- *                                  In BL2 mode(for highest performance), only 1/2 the phsyical
- *                                  memory is unique (ie: each bunk stores the same information).
- *                                  In BL4 mode(highest capacity), all of the physical memory
- *                                  is unique (ie: each bunk is uniquely addressable).
- * EMRS Definition:
- *    A[13:12]    REFRESH MODE  (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes)
- * 
- *                              (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT]
- *                              is also reflected in the Refresh Mode encoding).
- *    A[11:7]=0   RESERVED
- *    A[6:5]=2    STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture
- *                              silos rely on a conditional QS strobe)
- *    A[4:3]      DIC(QS)       QS Drive Strength: fully programmable (consult your FCRAM-II data sheet)
- *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
- *    A[2:1]      DIC(DQ)       DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet)
- *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
- *    A[0]        DLL           DLL Enable: Programmable [0:DLL Enable/1: DLL Disable]
- * 
- * EMRS2 Definition: (for FCRAM-II+)
- *    A[13:11]=0                RESERVED
- *    A[10:8]     ODTDS         On Die Termination (DS+/-)
- *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
- *    A[7:6]=0    MBW           Multi-Bank Write: (N3K requires use of 0:"single bank" mode only)
- *    A[5:3]      ODTin         On Die Termination (input pin)
- *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
- *    A[2:0]      ODTDQ         On Die Termination (DQ)
- *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memfcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_47_63          : 17;
-        uint64_t emrs2                   : 15;      /**< Memory Address[14:0] during EMRS2(for FCRAM-II+)
-                                                         *** O9N UNSUPPORTED *** */
-        uint64_t reserved_31_31          : 1;
-        uint64_t emrs                    : 15;      /**< Memory Address[14:0] during EMRS
-                                                         *** O9N UNSUPPORTED ***
-                                                           A[0]=1: DLL Enabled) */
-        uint64_t reserved_15_15          : 1;
-        uint64_t mrs                     : 15;      /**< FCRAM Memory Address[14:0] during MRS
-                                                         *** O9N UNSUPPORTED ***
-                                                           A[6:4]=4  CAS LATENCY=4(default)
-                                                           A[3]=0    Burst Type(must be 0:Sequential)
-                                                           A[2:0]=2  Burst Length=4(default) */
-#else
-        uint64_t mrs                     : 15;
-        uint64_t reserved_15_15          : 1;
-        uint64_t emrs                    : 15;
-        uint64_t reserved_31_31          : 1;
-        uint64_t emrs2                   : 15;
-        uint64_t reserved_47_63          : 17;
-#endif
-    } s;
-    struct cvmx_dfa_memfcr_s             cn38xx;
-    struct cvmx_dfa_memfcr_s             cn38xxp2;
-    struct cvmx_dfa_memfcr_s             cn58xx;
-    struct cvmx_dfa_memfcr_s             cn58xxp1;
-} cvmx_dfa_memfcr_t;
-
-
-/**
- * cvmx_dfa_memrld
- *
- * DFA_MEMRLD = DFA RLDRAM MRS Register Values
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_memrld_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t mrsdat                  : 23;      /**< This field represents the data driven onto the
-                                                         A[22:0] address lines during MRS(Mode Register Set)
-                                                         commands (during a HW init sequence). This field
-                                                         corresponds with the Mode Register Bit Map from
-                                                         your RLDRAM-II device specific data sheet.
-                                                            A[17:10]: RESERVED
-                                                            A[9]:     ODT (on die termination)
-                                                            A[8]:     Impedance Matching
-                                                            A[7]:     DLL Reset
-                                                            A[6]:     UNUSED
-                                                            A[5]:     Address Mux  (for N3K: MUST BE ZERO)
-                                                            A[4:3]:   Burst Length (for N3K: MUST BE ZERO)
-                                                            A[2:0]:   Configuration (see data sheet for
-                                                                      specific RLDRAM-II device).
-                                                               - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5]
-                                                               - 010:     CFG=2 [tRC=6/tRL=6/tWL=7]
-                                                               - 011:     CFG=3 [tRC=8/tRL=8/tWL=9]
-                                                               - 100-111: RESERVED
-                                                          NOTE: For additional density, the RLDRAM-II parts
-                                                          can be 'clamshelled' (ie: two devices mounted on
-                                                          different sides of the PCB board), since the BGA
-                                                          pinout supports 'mirroring'.
-                                                          To support a clamshell design, SW must preload
-                                                          the MRSDAT[22:0] with the proper A[22:0] pin mapping
-                                                          which is dependent on the 'selected' bunk/clam
-                                                          (see also: DFA_MEMCFG0[BUNK_INIT] field).
-                                                          NOTE: Care MUST BE TAKEN NOT to write to this register
-                                                          within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1).
-                                                          NOTE: This should only be written to a different value
-                                                          during power-on SW initialization. */
-#else
-        uint64_t mrsdat                  : 23;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_dfa_memrld_s             cn38xx;
-    struct cvmx_dfa_memrld_s             cn38xxp2;
-    struct cvmx_dfa_memrld_s             cn58xx;
-    struct cvmx_dfa_memrld_s             cn58xxp1;
-} cvmx_dfa_memrld_t;
-
-
-/**
- * cvmx_dfa_ncbctl
- *
- * DFA_NCBCTL = DFA NCB CTL Register
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_ncbctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t sbdnum                  : 5;       /**< SBD Debug Entry#
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         Selects which one of 32 DFA Scoreboard entries is
-                                                         latched into the DFA_SBD_DBG[0-3] registers. */
-        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         When written with a '1', the DFA Scoreboard Debug
-                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
-                                                         This allows SW to lock down the contents of the entire
-                                                         SBD for a single instant in time. All subsequent reads
-                                                         of the DFA scoreboard registers will return the data
-                                                         from that instant in time. */
-        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
-                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
-                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
-                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-#else
-        uint64_t imode                   : 1;
-        uint64_t qmode                   : 1;
-        uint64_t pmode                   : 1;
-        uint64_t dtmode                  : 1;
-        uint64_t dcmode                  : 1;
-        uint64_t sbdlck                  : 1;
-        uint64_t sbdnum                  : 5;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_dfa_ncbctl_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t sbdnum                  : 4;       /**< SBD Debug Entry#
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         Selects which one of 16 DFA Scoreboard entries is
-                                                         latched into the DFA_SBD_DBG[0-3] registers. */
-        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
-                                                         For internal use only. (DFA Scoreboard debug)
-                                                         When written with a '1', the DFA Scoreboard Debug
-                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
-                                                         This allows SW to lock down the contents of the entire
-                                                         SBD for a single instant in time. All subsequent reads
-                                                         of the DFA scoreboard registers will return the data
-                                                         from that instant in time. */
-        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
-                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
-                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
-                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
-                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
-                                                         NOTE: This should only be written to a different value
-                                                         during power-on SW initialization. */
-#else
-        uint64_t imode                   : 1;
-        uint64_t qmode                   : 1;
-        uint64_t pmode                   : 1;
-        uint64_t dtmode                  : 1;
-        uint64_t dcmode                  : 1;
-        uint64_t sbdlck                  : 1;
-        uint64_t sbdnum                  : 4;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn38xx;
-    struct cvmx_dfa_ncbctl_cn38xx        cn38xxp2;
-    struct cvmx_dfa_ncbctl_s             cn58xx;
-    struct cvmx_dfa_ncbctl_s             cn58xxp1;
-} cvmx_dfa_ncbctl_t;
-
-
-/**
- * cvmx_dfa_rodt_comp_ctl
- *
- * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination")
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_rodt_comp_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t enable                  : 1;       /**< Read On Die Termination Enable
-                                                         (0=disable, 1=enable) */
-        uint64_t reserved_12_15          : 4;
-        uint64_t nctl                    : 4;       /**< Compensation control bits */
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;       /**< Compensation control bits */
-#else
-        uint64_t pctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 4;
-        uint64_t reserved_12_15          : 4;
-        uint64_t enable                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_dfa_rodt_comp_ctl_s      cn58xx;
-    struct cvmx_dfa_rodt_comp_ctl_s      cn58xxp1;
-} cvmx_dfa_rodt_comp_ctl_t;
-
-
-/**
- * cvmx_dfa_sbd_dbg0
- *
- * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register
- * 
- * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
- * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
- * CSR read.
- * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
- * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
- * instruction.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_sbd_dbg0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t sbd0                    : 64;      /**< DFA ScoreBoard \#0 Data
-                                                         For internal use only! (DFA Scoreboard Debug)
-                                                         [63:40] rptr[26:3]: Result Base Pointer
-                                                         [39:24] rwcnt[15:0] Cumulative Result Write Counter
-                                                         [23]    lastgrdrsp: Last Gather-Rd Response
-                                                         [22]    wtgrdrsp: Waiting Gather-Rd Response
-                                                         [21]    wtgrdreq: Waiting for Gather-Rd Issue
-                                                         [20]    glvld: GLPTR/GLCNT Valid
-                                                         [19]    cmpmark: Completion Marked Node Detected
-                                                         [18:17] cmpcode[1:0]: Completion Code
-                                                                       [0=PDGONE/1=PERR/2=RFULL/3=TERM]
-                                                         [16]    cmpdet: Completion Detected
-                                                         [15]    wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp
-                                                         [14]    wtlastwrcmtrsp: Waiting for LAST RESULT
-                                                                       RWrCmtRsp
-                                                         [13]    hdrwrreq: Waiting for HDR RWrReq
-                                                         [12]    wtrwrreq: Waiting for RWrReq
-                                                         [11]    wtwqwrreq: Waiting for WQWrReq issue
-                                                         [10]    lastprdrspeot: Last Packet-Rd Response
-                                                         [9]     lastprdrsp: Last Packet-Rd Response
-                                                         [8]     wtprdrsp:  Waiting for PRdRsp EOT
-                                                         [7]     wtprdreq: Waiting for PRdReq Issue
-                                                         [6]     lastpdvld: PDPTR/PDLEN Valid
-                                                         [5]     pdvld: Packet Data Valid
-                                                         [4]     wqvld: WQVLD
-                                                         [3]     wqdone: WorkQueue Done condition
-                                                                       a) WQWrReq issued(for WQPTR<>0) OR
-                                                                       b) HDR RWrCmtRsp completed)
-                                                         [2]     rwstf: Resultant write STF/P Mode
-                                                         [1]     pdldt: Packet-Data LDT mode
-                                                         [0]     gmode: Gather-Mode */
-#else
-        uint64_t sbd0                    : 64;
-#endif
-    } s;
-    struct cvmx_dfa_sbd_dbg0_s           cn31xx;
-    struct cvmx_dfa_sbd_dbg0_s           cn38xx;
-    struct cvmx_dfa_sbd_dbg0_s           cn38xxp2;
-    struct cvmx_dfa_sbd_dbg0_s           cn58xx;
-    struct cvmx_dfa_sbd_dbg0_s           cn58xxp1;
-} cvmx_dfa_sbd_dbg0_t;
-
-
-/**
- * cvmx_dfa_sbd_dbg1
- *
- * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register
- * 
- * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
- * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
- * CSR read.
- * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
- * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
- * instruction.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_sbd_dbg1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t sbd1                    : 64;      /**< DFA ScoreBoard \#1 Data
-                                                         For internal use only! (DFA Scoreboard Debug)
-                                                         [63:61] wqptr[35:33]: Work Queue Pointer
-                                                         [60:52] rptr[35:27]: Result Base Pointer
-                                                         [51:16] pdptr[35:0]: Packet Data Pointer
-                                                         [15:0]  pdcnt[15:0]: Packet Data Counter */
-#else
-        uint64_t sbd1                    : 64;
-#endif
-    } s;
-    struct cvmx_dfa_sbd_dbg1_s           cn31xx;
-    struct cvmx_dfa_sbd_dbg1_s           cn38xx;
-    struct cvmx_dfa_sbd_dbg1_s           cn38xxp2;
-    struct cvmx_dfa_sbd_dbg1_s           cn58xx;
-    struct cvmx_dfa_sbd_dbg1_s           cn58xxp1;
-} cvmx_dfa_sbd_dbg1_t;
-
-
-/**
- * cvmx_dfa_sbd_dbg2
- *
- * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register
- * 
- * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
- * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
- * CSR read.
- * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
- * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
- * instruction.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_sbd_dbg2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t sbd2                    : 64;      /**< DFA ScoreBoard \#2 Data
-                                                         [63:49] wqptr[17:3]: Work Queue Pointer
-                                                         [48:16] rwptr[35:3]: Result Write Pointer
-                                                         [15:0]  prwcnt[15:0]: Pending Result Write Counter */
-#else
-        uint64_t sbd2                    : 64;
-#endif
-    } s;
-    struct cvmx_dfa_sbd_dbg2_s           cn31xx;
-    struct cvmx_dfa_sbd_dbg2_s           cn38xx;
-    struct cvmx_dfa_sbd_dbg2_s           cn38xxp2;
-    struct cvmx_dfa_sbd_dbg2_s           cn58xx;
-    struct cvmx_dfa_sbd_dbg2_s           cn58xxp1;
-} cvmx_dfa_sbd_dbg2_t;
-
-
-/**
- * cvmx_dfa_sbd_dbg3
- *
- * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register
- * 
- * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
- * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
- * CSR read.
- * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
- * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
- * instruction.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_dfa_sbd_dbg3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t sbd3                    : 64;      /**< DFA ScoreBoard \#3 Data
-                                                         [63:49] wqptr[32:18]: Work Queue Pointer
-                                                         [48:16] glptr[35:3]: Gather List Pointer
-                                                         [15:0]  glcnt[15:0]: Gather List Counter */
-#else
-        uint64_t sbd3                    : 64;
-#endif
-    } s;
-    struct cvmx_dfa_sbd_dbg3_s           cn31xx;
-    struct cvmx_dfa_sbd_dbg3_s           cn38xx;
-    struct cvmx_dfa_sbd_dbg3_s           cn38xxp2;
-    struct cvmx_dfa_sbd_dbg3_s           cn58xx;
-    struct cvmx_dfa_sbd_dbg3_s           cn58xxp1;
-} cvmx_dfa_sbd_dbg3_t;
-
-
-/**
- * cvmx_fpa_bist_status
- *
- * FPA_BIST_STATUS = BIST Status of FPA Memories
- * 
- * The result of the BIST run on the FPA memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t frd                     : 1;       /**< fpa_frd  memory bist status. */
-        uint64_t fpf0                    : 1;       /**< fpa_fpf0 memory bist status. */
-        uint64_t fpf1                    : 1;       /**< fpa_fpf1 memory bist status. */
-        uint64_t ffr                     : 1;       /**< fpa_ffr  memory bist status. */
-        uint64_t fdr                     : 1;       /**< fpa_fdr  memory bist status. */
-#else
-        uint64_t fdr                     : 1;
-        uint64_t ffr                     : 1;
-        uint64_t fpf1                    : 1;
-        uint64_t fpf0                    : 1;
-        uint64_t frd                     : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_fpa_bist_status_s        cn30xx;
-    struct cvmx_fpa_bist_status_s        cn31xx;
-    struct cvmx_fpa_bist_status_s        cn38xx;
-    struct cvmx_fpa_bist_status_s        cn38xxp2;
-    struct cvmx_fpa_bist_status_s        cn50xx;
-    struct cvmx_fpa_bist_status_s        cn52xx;
-    struct cvmx_fpa_bist_status_s        cn52xxp1;
-    struct cvmx_fpa_bist_status_s        cn56xx;
-    struct cvmx_fpa_bist_status_s        cn56xxp1;
-    struct cvmx_fpa_bist_status_s        cn58xx;
-    struct cvmx_fpa_bist_status_s        cn58xxp1;
-} cvmx_fpa_bist_status_t;
-
-
-/**
- * cvmx_fpa_ctl_status
- *
- * FPA_CTL_STATUS = FPA's Control/Status Register
- * 
- * The FPA's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t reset                   : 1;       /**< When set causes a reset of the FPA with the
-                                                         exception of the RSL. */
-        uint64_t use_ldt                 : 1;       /**< When clear '0' the FPA will use LDT to load
-                                                         pointers from the L2C. */
-        uint64_t use_stt                 : 1;       /**< When clear '0' the FPA will use STT to store
-                                                         pointers to the L2C. */
-        uint64_t enb                     : 1;       /**< Must be set to 1 AFTER writing all config registers
-                                                         and 10 cycles have past. If any of the config
-                                                         register are written after writing this bit the
-                                                         FPA may begin to operate incorrectly. */
-        uint64_t mem1_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
-                                                         respective to bit 6:0 of this field, for FPF
-                                                         FIFO 1. */
-        uint64_t mem0_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
-                                                         respective to bit 6:0 of this field, for FPF
-                                                         FIFO 0. */
-#else
-        uint64_t mem0_err                : 7;
-        uint64_t mem1_err                : 7;
-        uint64_t enb                     : 1;
-        uint64_t use_stt                 : 1;
-        uint64_t use_ldt                 : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_fpa_ctl_status_s         cn30xx;
-    struct cvmx_fpa_ctl_status_s         cn31xx;
-    struct cvmx_fpa_ctl_status_s         cn38xx;
-    struct cvmx_fpa_ctl_status_s         cn38xxp2;
-    struct cvmx_fpa_ctl_status_s         cn50xx;
-    struct cvmx_fpa_ctl_status_s         cn52xx;
-    struct cvmx_fpa_ctl_status_s         cn52xxp1;
-    struct cvmx_fpa_ctl_status_s         cn56xx;
-    struct cvmx_fpa_ctl_status_s         cn56xxp1;
-    struct cvmx_fpa_ctl_status_s         cn58xx;
-    struct cvmx_fpa_ctl_status_s         cn58xxp1;
-} cvmx_fpa_ctl_status_t;
-
-
-/**
- * cvmx_fpa_fpf#_marks
- *
- * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks
- * 
- * The high and low watermark register that determines when we write and read free pages from L2C
- * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 diffrence. Recommend value
- * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_fpfx_marks_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_22_63          : 42;
-        uint64_t fpf_wr                  : 11;      /**< When the number of free-page-pointers in a
-                                                          queue exceeds this value the FPA will write
-                                                          32-page-pointers of that queue to DRAM.
-                                                         The MAX value for this field should be
-                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
-        uint64_t fpf_rd                  : 11;      /**< When the number of free-page-pointers in a
-                                                          queue drops below this value amd there are
-                                                          free-page-pointers in DRAM, the FPA will
-                                                          read one page (32 pointers) from DRAM.
-                                                         This maximum value for this field should be
-                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
-                                                         for this would be 16. */
-#else
-        uint64_t fpf_rd                  : 11;
-        uint64_t fpf_wr                  : 11;
-        uint64_t reserved_22_63          : 42;
-#endif
-    } s;
-    struct cvmx_fpa_fpfx_marks_s         cn38xx;
-    struct cvmx_fpa_fpfx_marks_s         cn38xxp2;
-    struct cvmx_fpa_fpfx_marks_s         cn56xx;
-    struct cvmx_fpa_fpfx_marks_s         cn56xxp1;
-    struct cvmx_fpa_fpfx_marks_s         cn58xx;
-    struct cvmx_fpa_fpfx_marks_s         cn58xxp1;
-} cvmx_fpa_fpfx_marks_t;
-
-
-/**
- * cvmx_fpa_fpf#_size
- *
- * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size
- * 
- * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
- * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
- * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_fpfx_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t fpf_siz                 : 11;      /**< The number of entries assigned in the FPA FIFO
-                                                         (used to hold page-pointers) for this Queue.
-                                                         The value of this register must divisable by 2,
-                                                         and the FPA will ignore bit [0] of this register.
-                                                         The total of the FPF_SIZ field of the 8 (0-7)
-                                                         FPA_FPF#_SIZE registers must not exceed 2048.
-                                                         After writing this field the FPA will need 10
-                                                         core clock cycles to be ready for operation. The
-                                                         assignment of location in the FPA FIFO must
-                                                         start with Queue 0, then 1, 2, etc.
-                                                         The number of useable entries will be FPF_SIZ-2. */
-#else
-        uint64_t fpf_siz                 : 11;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_fpa_fpfx_size_s          cn38xx;
-    struct cvmx_fpa_fpfx_size_s          cn38xxp2;
-    struct cvmx_fpa_fpfx_size_s          cn56xx;
-    struct cvmx_fpa_fpfx_size_s          cn56xxp1;
-    struct cvmx_fpa_fpfx_size_s          cn58xx;
-    struct cvmx_fpa_fpfx_size_s          cn58xxp1;
-} cvmx_fpa_fpfx_size_t;
-
-
-/**
- * cvmx_fpa_fpf0_marks
- *
- * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks
- * 
- * The high and low watermark register that determines when we write and read free pages from L2C
- * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 diffrence. Recommend value
- * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_fpf0_marks_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t fpf_wr                  : 12;      /**< When the number of free-page-pointers in a
-                                                          queue exceeds this value the FPA will write
-                                                          32-page-pointers of that queue to DRAM.
-                                                         The MAX value for this field should be
-                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
-        uint64_t fpf_rd                  : 12;      /**< When the number of free-page-pointers in a
-                                                         queue drops below this value amd there are
-                                                         free-page-pointers in DRAM, the FPA will
-                                                         read one page (32 pointers) from DRAM.
-                                                         This maximum value for this field should be
-                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
-                                                         for this would be 16. */
-#else
-        uint64_t fpf_rd                  : 12;
-        uint64_t fpf_wr                  : 12;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_fpa_fpf0_marks_s         cn38xx;
-    struct cvmx_fpa_fpf0_marks_s         cn38xxp2;
-    struct cvmx_fpa_fpf0_marks_s         cn56xx;
-    struct cvmx_fpa_fpf0_marks_s         cn56xxp1;
-    struct cvmx_fpa_fpf0_marks_s         cn58xx;
-    struct cvmx_fpa_fpf0_marks_s         cn58xxp1;
-} cvmx_fpa_fpf0_marks_t;
-
-
-/**
- * cvmx_fpa_fpf0_size
- *
- * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size
- * 
- * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
- * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
- * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_fpf0_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t fpf_siz                 : 12;      /**< The number of entries assigned in the FPA FIFO
-                                                         (used to hold page-pointers) for this Queue.
-                                                         The value of this register must divisable by 2,
-                                                         and the FPA will ignore bit [0] of this register.
-                                                         The total of the FPF_SIZ field of the 8 (0-7)
-                                                         FPA_FPF#_SIZE registers must not exceed 2048.
-                                                         After writing this field the FPA will need 10
-                                                         core clock cycles to be ready for operation. The
-                                                         assignment of location in the FPA FIFO must
-                                                         start with Queue 0, then 1, 2, etc.
-                                                         The number of useable entries will be FPF_SIZ-2. */
-#else
-        uint64_t fpf_siz                 : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_fpa_fpf0_size_s          cn38xx;
-    struct cvmx_fpa_fpf0_size_s          cn38xxp2;
-    struct cvmx_fpa_fpf0_size_s          cn56xx;
-    struct cvmx_fpa_fpf0_size_s          cn56xxp1;
-    struct cvmx_fpa_fpf0_size_s          cn58xx;
-    struct cvmx_fpa_fpf0_size_s          cn58xxp1;
-} cvmx_fpa_fpf0_size_t;
-
-
-/**
- * cvmx_fpa_int_enb
- *
- * FPA_INT_ENB = FPA's Interrupt Enable
- * 
- * The FPA's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t q7_perr                 : 1;       /**< When set (1) and bit 27 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q7_coff                 : 1;       /**< When set (1) and bit 26 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q7_und                  : 1;       /**< When set (1) and bit 25 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q6_perr                 : 1;       /**< When set (1) and bit 24 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q6_coff                 : 1;       /**< When set (1) and bit 23 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q6_und                  : 1;       /**< When set (1) and bit 22 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q5_perr                 : 1;       /**< When set (1) and bit 21 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q5_coff                 : 1;       /**< When set (1) and bit 20 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q5_und                  : 1;       /**< When set (1) and bit 19 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q4_perr                 : 1;       /**< When set (1) and bit 18 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q4_coff                 : 1;       /**< When set (1) and bit 17 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q4_und                  : 1;       /**< When set (1) and bit 16 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q3_perr                 : 1;       /**< When set (1) and bit 15 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q3_coff                 : 1;       /**< When set (1) and bit 14 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q3_und                  : 1;       /**< When set (1) and bit 13 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q2_perr                 : 1;       /**< When set (1) and bit 12 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q2_coff                 : 1;       /**< When set (1) and bit 11 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q2_und                  : 1;       /**< When set (1) and bit 10 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q1_perr                 : 1;       /**< When set (1) and bit 9 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q1_coff                 : 1;       /**< When set (1) and bit 8 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q1_und                  : 1;       /**< When set (1) and bit 7 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q0_perr                 : 1;       /**< When set (1) and bit 6 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q0_coff                 : 1;       /**< When set (1) and bit 5 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t q0_und                  : 1;       /**< When set (1) and bit 4 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t fed1_dbe                : 1;       /**< When set (1) and bit 3 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t fed1_sbe                : 1;       /**< When set (1) and bit 2 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t fed0_dbe                : 1;       /**< When set (1) and bit 1 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-        uint64_t fed0_sbe                : 1;       /**< When set (1) and bit 0 of the FPA_INT_SUM
-                                                         register is asserted the FPA will assert an
-                                                         interrupt. */
-#else
-        uint64_t fed0_sbe                : 1;
-        uint64_t fed0_dbe                : 1;
-        uint64_t fed1_sbe                : 1;
-        uint64_t fed1_dbe                : 1;
-        uint64_t q0_und                  : 1;
-        uint64_t q0_coff                 : 1;
-        uint64_t q0_perr                 : 1;
-        uint64_t q1_und                  : 1;
-        uint64_t q1_coff                 : 1;
-        uint64_t q1_perr                 : 1;
-        uint64_t q2_und                  : 1;
-        uint64_t q2_coff                 : 1;
-        uint64_t q2_perr                 : 1;
-        uint64_t q3_und                  : 1;
-        uint64_t q3_coff                 : 1;
-        uint64_t q3_perr                 : 1;
-        uint64_t q4_und                  : 1;
-        uint64_t q4_coff                 : 1;
-        uint64_t q4_perr                 : 1;
-        uint64_t q5_und                  : 1;
-        uint64_t q5_coff                 : 1;
-        uint64_t q5_perr                 : 1;
-        uint64_t q6_und                  : 1;
-        uint64_t q6_coff                 : 1;
-        uint64_t q6_perr                 : 1;
-        uint64_t q7_und                  : 1;
-        uint64_t q7_coff                 : 1;
-        uint64_t q7_perr                 : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_fpa_int_enb_s            cn30xx;
-    struct cvmx_fpa_int_enb_s            cn31xx;
-    struct cvmx_fpa_int_enb_s            cn38xx;
-    struct cvmx_fpa_int_enb_s            cn38xxp2;
-    struct cvmx_fpa_int_enb_s            cn50xx;
-    struct cvmx_fpa_int_enb_s            cn52xx;
-    struct cvmx_fpa_int_enb_s            cn52xxp1;
-    struct cvmx_fpa_int_enb_s            cn56xx;
-    struct cvmx_fpa_int_enb_s            cn56xxp1;
-    struct cvmx_fpa_int_enb_s            cn58xx;
-    struct cvmx_fpa_int_enb_s            cn58xxp1;
-} cvmx_fpa_int_enb_t;
-
-
-/**
- * cvmx_fpa_int_sum
- *
- * FPA_INT_SUM = FPA's Interrupt Summary Register
- * 
- * Contains the diffrent interrupt summary bits of the FPA.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t q7_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q7_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q7_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q6_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q6_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q6_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q5_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q5_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q5_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q4_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q4_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q4_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q3_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q3_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q3_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q2_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q2_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than than pointers
-                                                         present in the FPA. */
-        uint64_t q2_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q1_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q1_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than pointers
-                                                         present in the FPA. */
-        uint64_t q1_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t q0_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
-                                                         the L2C does not have the FPA owner ship bit set. */
-        uint64_t q0_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
-                                                         the count available is greater than pointers
-                                                         present in the FPA. */
-        uint64_t q0_und                  : 1;       /**< Set when a Queue0 page count available goes
-                                                         negative. */
-        uint64_t fed1_dbe                : 1;       /**< Set when a Double Bit Error is detected in FPF1. */
-        uint64_t fed1_sbe                : 1;       /**< Set when a Single Bit Error is detected in FPF1. */
-        uint64_t fed0_dbe                : 1;       /**< Set when a Double Bit Error is detected in FPF0. */
-        uint64_t fed0_sbe                : 1;       /**< Set when a Single Bit Error is detected in FPF0. */
-#else
-        uint64_t fed0_sbe                : 1;
-        uint64_t fed0_dbe                : 1;
-        uint64_t fed1_sbe                : 1;
-        uint64_t fed1_dbe                : 1;
-        uint64_t q0_und                  : 1;
-        uint64_t q0_coff                 : 1;
-        uint64_t q0_perr                 : 1;
-        uint64_t q1_und                  : 1;
-        uint64_t q1_coff                 : 1;
-        uint64_t q1_perr                 : 1;
-        uint64_t q2_und                  : 1;
-        uint64_t q2_coff                 : 1;
-        uint64_t q2_perr                 : 1;
-        uint64_t q3_und                  : 1;
-        uint64_t q3_coff                 : 1;
-        uint64_t q3_perr                 : 1;
-        uint64_t q4_und                  : 1;
-        uint64_t q4_coff                 : 1;
-        uint64_t q4_perr                 : 1;
-        uint64_t q5_und                  : 1;
-        uint64_t q5_coff                 : 1;
-        uint64_t q5_perr                 : 1;
-        uint64_t q6_und                  : 1;
-        uint64_t q6_coff                 : 1;
-        uint64_t q6_perr                 : 1;
-        uint64_t q7_und                  : 1;
-        uint64_t q7_coff                 : 1;
-        uint64_t q7_perr                 : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_fpa_int_sum_s            cn30xx;
-    struct cvmx_fpa_int_sum_s            cn31xx;
-    struct cvmx_fpa_int_sum_s            cn38xx;
-    struct cvmx_fpa_int_sum_s            cn38xxp2;
-    struct cvmx_fpa_int_sum_s            cn50xx;
-    struct cvmx_fpa_int_sum_s            cn52xx;
-    struct cvmx_fpa_int_sum_s            cn52xxp1;
-    struct cvmx_fpa_int_sum_s            cn56xx;
-    struct cvmx_fpa_int_sum_s            cn56xxp1;
-    struct cvmx_fpa_int_sum_s            cn58xx;
-    struct cvmx_fpa_int_sum_s            cn58xxp1;
-} cvmx_fpa_int_sum_t;
-
-
-/**
- * cvmx_fpa_que#_available
- *
- * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register
- * 
- * The number of page pointers that are available in the FPA and local DRAM.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_quex_available_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t que_siz                 : 29;      /**< The number of free pages available in this Queue. */
-#else
-        uint64_t que_siz                 : 29;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_fpa_quex_available_s     cn30xx;
-    struct cvmx_fpa_quex_available_s     cn31xx;
-    struct cvmx_fpa_quex_available_s     cn38xx;
-    struct cvmx_fpa_quex_available_s     cn38xxp2;
-    struct cvmx_fpa_quex_available_s     cn50xx;
-    struct cvmx_fpa_quex_available_s     cn52xx;
-    struct cvmx_fpa_quex_available_s     cn52xxp1;
-    struct cvmx_fpa_quex_available_s     cn56xx;
-    struct cvmx_fpa_quex_available_s     cn56xxp1;
-    struct cvmx_fpa_quex_available_s     cn58xx;
-    struct cvmx_fpa_quex_available_s     cn58xxp1;
-} cvmx_fpa_quex_available_t;
-
-
-/**
- * cvmx_fpa_que#_page_index
- *
- * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index
- * 
- * The present index page for queue 0 of the FPA.
- * This numbr reflests the number of pages of pointers that have been written to memory
- * for this queue.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_quex_page_index_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_25_63          : 39;
-        uint64_t pg_num                  : 25;      /**< Page number. */
-#else
-        uint64_t pg_num                  : 25;
-        uint64_t reserved_25_63          : 39;
-#endif
-    } s;
-    struct cvmx_fpa_quex_page_index_s    cn30xx;
-    struct cvmx_fpa_quex_page_index_s    cn31xx;
-    struct cvmx_fpa_quex_page_index_s    cn38xx;
-    struct cvmx_fpa_quex_page_index_s    cn38xxp2;
-    struct cvmx_fpa_quex_page_index_s    cn50xx;
-    struct cvmx_fpa_quex_page_index_s    cn52xx;
-    struct cvmx_fpa_quex_page_index_s    cn52xxp1;
-    struct cvmx_fpa_quex_page_index_s    cn56xx;
-    struct cvmx_fpa_quex_page_index_s    cn56xxp1;
-    struct cvmx_fpa_quex_page_index_s    cn58xx;
-    struct cvmx_fpa_quex_page_index_s    cn58xxp1;
-} cvmx_fpa_quex_page_index_t;
-
-
-/**
- * cvmx_fpa_que_act
- *
- * FPA_QUE_ACT = FPA's Queue# Actual Page Index
- * 
- * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C.
- * This is latched on the first error and will not latch again unitl all errors are cleared.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_que_act_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t act_que                 : 3;       /**< FPA-queue-number read from memory. */
-        uint64_t act_indx                : 26;      /**< Page number read from memory. */
-#else
-        uint64_t act_indx                : 26;
-        uint64_t act_que                 : 3;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_fpa_que_act_s            cn30xx;
-    struct cvmx_fpa_que_act_s            cn31xx;
-    struct cvmx_fpa_que_act_s            cn38xx;
-    struct cvmx_fpa_que_act_s            cn38xxp2;
-    struct cvmx_fpa_que_act_s            cn50xx;
-    struct cvmx_fpa_que_act_s            cn52xx;
-    struct cvmx_fpa_que_act_s            cn52xxp1;
-    struct cvmx_fpa_que_act_s            cn56xx;
-    struct cvmx_fpa_que_act_s            cn56xxp1;
-    struct cvmx_fpa_que_act_s            cn58xx;
-    struct cvmx_fpa_que_act_s            cn58xxp1;
-} cvmx_fpa_que_act_t;
-
-
-/**
- * cvmx_fpa_que_exp
- *
- * FPA_QUE_EXP = FPA's Queue# Expected Page Index
- * 
- * When a INT_SUM[PERR#] occurs this will be latched with the expected value.
- * This is latched on the first error and will not latch again unitl all errors are cleared.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_que_exp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t exp_que                 : 3;       /**< Expected fpa-queue-number read from memory. */
-        uint64_t exp_indx                : 26;      /**< Expected page number read from memory. */
-#else
-        uint64_t exp_indx                : 26;
-        uint64_t exp_que                 : 3;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_fpa_que_exp_s            cn30xx;
-    struct cvmx_fpa_que_exp_s            cn31xx;
-    struct cvmx_fpa_que_exp_s            cn38xx;
-    struct cvmx_fpa_que_exp_s            cn38xxp2;
-    struct cvmx_fpa_que_exp_s            cn50xx;
-    struct cvmx_fpa_que_exp_s            cn52xx;
-    struct cvmx_fpa_que_exp_s            cn52xxp1;
-    struct cvmx_fpa_que_exp_s            cn56xx;
-    struct cvmx_fpa_que_exp_s            cn56xxp1;
-    struct cvmx_fpa_que_exp_s            cn58xx;
-    struct cvmx_fpa_que_exp_s            cn58xxp1;
-} cvmx_fpa_que_exp_t;
-
-
-/**
- * cvmx_fpa_wart_ctl
- *
- * FPA_WART_CTL = FPA's WART Control
- * 
- * Control and status for the WART block.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_wart_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ctl                     : 16;      /**< Control information. */
-#else
-        uint64_t ctl                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_fpa_wart_ctl_s           cn30xx;
-    struct cvmx_fpa_wart_ctl_s           cn31xx;
-    struct cvmx_fpa_wart_ctl_s           cn38xx;
-    struct cvmx_fpa_wart_ctl_s           cn38xxp2;
-    struct cvmx_fpa_wart_ctl_s           cn50xx;
-    struct cvmx_fpa_wart_ctl_s           cn52xx;
-    struct cvmx_fpa_wart_ctl_s           cn52xxp1;
-    struct cvmx_fpa_wart_ctl_s           cn56xx;
-    struct cvmx_fpa_wart_ctl_s           cn56xxp1;
-    struct cvmx_fpa_wart_ctl_s           cn58xx;
-    struct cvmx_fpa_wart_ctl_s           cn58xxp1;
-} cvmx_fpa_wart_ctl_t;
-
-
-/**
- * cvmx_fpa_wart_status
- *
- * FPA_WART_STATUS = FPA's WART Status
- * 
- * Control and status for the WART block.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_fpa_wart_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t status                  : 32;      /**< Status information. */
-#else
-        uint64_t status                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_fpa_wart_status_s        cn30xx;
-    struct cvmx_fpa_wart_status_s        cn31xx;
-    struct cvmx_fpa_wart_status_s        cn38xx;
-    struct cvmx_fpa_wart_status_s        cn38xxp2;
-    struct cvmx_fpa_wart_status_s        cn50xx;
-    struct cvmx_fpa_wart_status_s        cn52xx;
-    struct cvmx_fpa_wart_status_s        cn52xxp1;
-    struct cvmx_fpa_wart_status_s        cn56xx;
-    struct cvmx_fpa_wart_status_s        cn56xxp1;
-    struct cvmx_fpa_wart_status_s        cn58xx;
-    struct cvmx_fpa_wart_status_s        cn58xxp1;
-} cvmx_fpa_wart_status_t;
-
-
-/**
- * cvmx_gmx#_bad_reg
- *
- * GMX_BAD_REG = A collection of things that have gone very, very wrong
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_bad_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
-        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
-        uint64_t loststat                : 4;       /**< TX Statistics data was over-written (per RGM port)
-                                                         TX Stats are corrupted */
-        uint64_t reserved_18_21          : 4;
-        uint64_t out_ovr                 : 16;      /**< Outbound data FIFO overflow (per port) */
-        uint64_t ncb_ovr                 : 1;       /**< Outbound NCB FIFO Overflow */
-        uint64_t out_col                 : 1;       /**< Outbound collision occured between PKO and NCB */
-#else
-        uint64_t out_col                 : 1;
-        uint64_t ncb_ovr                 : 1;
-        uint64_t out_ovr                 : 16;
-        uint64_t reserved_18_21          : 4;
-        uint64_t loststat                : 4;
-        uint64_t statovr                 : 1;
-        uint64_t inb_nxa                 : 4;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_gmxx_bad_reg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
-        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
-        uint64_t reserved_25_25          : 1;
-        uint64_t loststat                : 3;       /**< TX Statistics data was over-written (per RGM port)
-                                                         TX Stats are corrupted */
-        uint64_t reserved_5_21           : 17;
-        uint64_t out_ovr                 : 3;       /**< Outbound data FIFO overflow (per port) */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t out_ovr                 : 3;
-        uint64_t reserved_5_21           : 17;
-        uint64_t loststat                : 3;
-        uint64_t reserved_25_25          : 1;
-        uint64_t statovr                 : 1;
-        uint64_t inb_nxa                 : 4;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_bad_reg_cn30xx      cn31xx;
-    struct cvmx_gmxx_bad_reg_s           cn38xx;
-    struct cvmx_gmxx_bad_reg_s           cn38xxp2;
-    struct cvmx_gmxx_bad_reg_cn30xx      cn50xx;
-    struct cvmx_gmxx_bad_reg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
-        uint64_t statovr                 : 1;       /**< TX Statistics overflow
-                                                         The common FIFO to SGMII and XAUI had an overflow
-                                                         TX Stats are corrupted */
-        uint64_t loststat                : 4;       /**< TX Statistics data was over-written
-                                                         In SGMII, one bit per port
-                                                         In XAUI, only port0 is used
-                                                         TX Stats are corrupted */
-        uint64_t reserved_6_21           : 16;
-        uint64_t out_ovr                 : 4;       /**< Outbound data FIFO overflow (per port) */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t out_ovr                 : 4;
-        uint64_t reserved_6_21           : 16;
-        uint64_t loststat                : 4;
-        uint64_t statovr                 : 1;
-        uint64_t inb_nxa                 : 4;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_bad_reg_cn52xx      cn52xxp1;
-    struct cvmx_gmxx_bad_reg_cn52xx      cn56xx;
-    struct cvmx_gmxx_bad_reg_cn52xx      cn56xxp1;
-    struct cvmx_gmxx_bad_reg_s           cn58xx;
-    struct cvmx_gmxx_bad_reg_s           cn58xxp1;
-} cvmx_gmxx_bad_reg_t;
-
-
-/**
- * cvmx_gmx#_bist
- *
- * GMX_BIST = GMX BIST Results
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_bist_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t status                  : 17;      /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         - 0: gmx#.inb.fif_bnk0
-                                                         - 1: gmx#.inb.fif_bnk1
-                                                         - 2: gmx#.inb.fif_bnk2
-                                                         - 3: gmx#.inb.fif_bnk3
-                                                         - 4: gmx#.outb.fif.fif_bnk0
-                                                         - 5: gmx#.outb.fif.fif_bnk1
-                                                         - 6: gmx#.outb.fif.fif_bnk2
-                                                         - 7: gmx#.outb.fif.fif_bnk3
-                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
-                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
-                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
-                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
-                                                         - 12: gmx#.csr.drf20x80m1_bist
-                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
-                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
-                                                         - 15: gmx#.outb.ncb.drf16x76m1_bist
-                                                         - 16: gmx#.outb.fif.srf32x16m2_bist */
-#else
-        uint64_t status                  : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_gmxx_bist_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t status                  : 10;      /**< BIST Results.
-                                                          HW sets a bit in BIST for for memory that fails
-                                                         - 0: gmx#.inb.dpr512x78m4_bist
-                                                         - 1: gmx#.outb.fif.dpr512x71m4_bist
-                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
-                                                         - 3: gmx#.csr.gmi1.srf8x64m1_bist
-                                                         - 4: gmx#.csr.gmi2.srf8x64m1_bist
-                                                         - 5: 0
-                                                         - 6: gmx#.csr.drf20x80m1_bist
-                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
-                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
-                                                         - 9: 0 */
-#else
-        uint64_t status                  : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_bist_cn30xx         cn31xx;
-    struct cvmx_gmxx_bist_cn30xx         cn38xx;
-    struct cvmx_gmxx_bist_cn30xx         cn38xxp2;
-    struct cvmx_gmxx_bist_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t status                  : 12;      /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails */
-#else
-        uint64_t status                  : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn50xx;
-    struct cvmx_gmxx_bist_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t status                  : 16;      /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         - 0: gmx#.inb.fif_bnk0
-                                                         - 1: gmx#.inb.fif_bnk1
-                                                         - 2: gmx#.inb.fif_bnk2
-                                                         - 3: gmx#.inb.fif_bnk3
-                                                         - 4: gmx#.outb.fif.fif_bnk0
-                                                         - 5: gmx#.outb.fif.fif_bnk1
-                                                         - 6: gmx#.outb.fif.fif_bnk2
-                                                         - 7: gmx#.outb.fif.fif_bnk3
-                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
-                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
-                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
-                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
-                                                         - 12: gmx#.csr.drf20x80m1_bist
-                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
-                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
-                                                         - 15: xgmii.tx.drf16x38m1_async_bist */
-#else
-        uint64_t status                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_bist_cn52xx         cn52xxp1;
-    struct cvmx_gmxx_bist_cn52xx         cn56xx;
-    struct cvmx_gmxx_bist_cn52xx         cn56xxp1;
-    struct cvmx_gmxx_bist_s              cn58xx;
-    struct cvmx_gmxx_bist_s              cn58xxp1;
-} cvmx_gmxx_bist_t;
-
-
-/**
- * cvmx_gmx#_clk_en
- *
- * DO NOT DOCUMENT THIS REGISTER - IT IS NOT OFFICIAL
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_clk_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t clk_en                  : 1;       /**< Force the clock enables on */
-#else
-        uint64_t clk_en                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_clk_en_s            cn52xx;
-    struct cvmx_gmxx_clk_en_s            cn52xxp1;
-    struct cvmx_gmxx_clk_en_s            cn56xx;
-    struct cvmx_gmxx_clk_en_s            cn56xxp1;
-} cvmx_gmxx_clk_en_t;
-
-
-/**
- * cvmx_gmx#_hg2_control
- *
- * Notes:
- * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However
- * setting just the TX or RX bit will result in only the HG2 message transmit or the receive
- * capability.
- * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received
- * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages
- * are disabled.
- * 
- * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN
- * are set.
- * 
- * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN
- * are set.
- * 
- * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
- * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when
- * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1
- * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
- * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_hg2_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t hg2tx_en                : 1;       /**< Enable Transmission of HG2 phys and logl messages
-                                                         When set, also disables HW auto-generated (802.3
-                                                         and CBFC) pause frames. (OCTEON cannot generate
-                                                         proper 802.3 or CBFC pause frames in HiGig2 mode.) */
-        uint64_t hg2rx_en                : 1;       /**< Enable extraction and processing of HG2 message
-                                                         packet from RX flow. Physical logical pause info
-                                                         is used to pause physical link, back pressure PKO
-                                                         HG2RX_EN must be set when HiGig2 messages are
-                                                         present in the receive stream. */
-        uint64_t phys_en                 : 1;       /**< 1 bit physical link pause enable for recevied
-                                                         HiGig2 physical pause message */
-        uint64_t logl_en                 : 16;      /**< 16 bit xof enables for recevied HiGig2 messages
-                                                         or CBFC packets */
-#else
-        uint64_t logl_en                 : 16;
-        uint64_t phys_en                 : 1;
-        uint64_t hg2rx_en                : 1;
-        uint64_t hg2tx_en                : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_gmxx_hg2_control_s       cn52xx;
-    struct cvmx_gmxx_hg2_control_s       cn52xxp1;
-    struct cvmx_gmxx_hg2_control_s       cn56xx;
-} cvmx_gmxx_hg2_control_t;
-
-
-/**
- * cvmx_gmx#_inf_mode
- *
- * GMX_INF_MODE = Interface Mode
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_inf_mode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t speed                   : 2;       /**< Interface Speed
-                                                         - 0: 1.250GHz
-                                                         - 1: 2.500GHz
-                                                         - 2: 3.125GHz
-                                                         - 3: 3.750GHz */
-        uint64_t reserved_6_7            : 2;
-        uint64_t mode                    : 2;       /**< Interface Electrical Operating Mode
-                                                         - 0: Disabled (PCIe)
-                                                         - 1: XAUI (IEEE 802.3-2005)
-                                                         - 2: SGMII (v1.8)
-                                                         - 3: PICMG3.1 */
-        uint64_t reserved_3_3            : 1;
-        uint64_t p0mii                   : 1;       /**< Port 0 Interface Mode
-                                                         - 0: Port 0 is RGMII
-                                                         - 1: Port 0 is MII */
-        uint64_t en                      : 1;       /**< Interface Enable */
-        uint64_t type                    : 1;       /**< Interface Mode
-                                                         - 0: RGMII Mode
-                                                         - 1: Spi4 Mode */
-#else
-        uint64_t type                    : 1;
-        uint64_t en                      : 1;
-        uint64_t p0mii                   : 1;
-        uint64_t reserved_3_3            : 1;
-        uint64_t mode                    : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t speed                   : 2;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_gmxx_inf_mode_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t p0mii                   : 1;       /**< Port 0 Interface Mode
-                                                         - 0: Port 0 is RGMII
-                                                         - 1: Port 0 is MII */
-        uint64_t en                      : 1;       /**< Interface Enable
-                                                         Must be set to enable the packet interface.
-                                                         Should be enabled before any other requests to
-                                                         GMX including enabling port back pressure with
-                                                         IPD_CTL_STATUS[PBP_EN] */
-        uint64_t type                    : 1;       /**< Port 1/2 Interface Mode
-                                                         - 0: Ports 1 and 2 are RGMII
-                                                         - 1: Port  1 is GMII/MII, Port 2 is unused
-                                                             GMII/MII is selected by GMX_PRT1_CFG[SPEED] */
-#else
-        uint64_t type                    : 1;
-        uint64_t en                      : 1;
-        uint64_t p0mii                   : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_inf_mode_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t en                      : 1;       /**< Interface Enable
-                                                         Must be set to enable the packet interface.
-                                                         Should be enabled before any other requests to
-                                                         GMX including enabling port back pressure with
-                                                         IPD_CTL_STATUS[PBP_EN] */
-        uint64_t type                    : 1;       /**< Interface Mode
-                                                         - 0: All three ports are RGMII ports
-                                                         - 1: prt0 is RGMII, prt1 is GMII, and prt2 is unused */
-#else
-        uint64_t type                    : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn31xx;
-    struct cvmx_gmxx_inf_mode_cn31xx     cn38xx;
-    struct cvmx_gmxx_inf_mode_cn31xx     cn38xxp2;
-    struct cvmx_gmxx_inf_mode_cn30xx     cn50xx;
-    struct cvmx_gmxx_inf_mode_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t speed                   : 2;       /**< Interface Speed
-                                                         - 0: 1.250GHz
-                                                         - 1: 2.500GHz
-                                                         - 2: 3.125GHz
-                                                         - 3: 3.750GHz */
-        uint64_t reserved_6_7            : 2;
-        uint64_t mode                    : 2;       /**< Interface Electrical Operating Mode
-                                                         - 0: Disabled (PCIe)
-                                                         - 1: XAUI (IEEE 802.3-2005)
-                                                         - 2: SGMII (v1.8)
-                                                         - 3: PICMG3.1 */
-        uint64_t reserved_2_3            : 2;
-        uint64_t en                      : 1;       /**< Interface Enable
-                                                         Must be set to enable the packet interface.
-                                                         Should be enabled before any other requests to
-                                                         GMX including enabling port back pressure with
-                                                         IPD_CTL_STATUS[PBP_EN] */
-        uint64_t type                    : 1;       /**< Interface Protocol Type
-                                                         - 0: SGMII/1000Base-X
-                                                         - 1: XAUI */
-#else
-        uint64_t type                    : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t mode                    : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t speed                   : 2;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_inf_mode_cn52xx     cn52xxp1;
-    struct cvmx_gmxx_inf_mode_cn52xx     cn56xx;
-    struct cvmx_gmxx_inf_mode_cn52xx     cn56xxp1;
-    struct cvmx_gmxx_inf_mode_cn31xx     cn58xx;
-    struct cvmx_gmxx_inf_mode_cn31xx     cn58xxp1;
-} cvmx_gmxx_inf_mode_t;
-
-
-/**
- * cvmx_gmx#_nxa_adr
- *
- * GMX_NXA_ADR = NXA Port Address
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_nxa_adr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t prt                     : 6;       /**< Logged address for NXA exceptions
-                                                         The logged address will be from the first
-                                                         exception that caused the problem.  NCB has
-                                                         higher priority than PKO and will win. */
-#else
-        uint64_t prt                     : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_gmxx_nxa_adr_s           cn30xx;
-    struct cvmx_gmxx_nxa_adr_s           cn31xx;
-    struct cvmx_gmxx_nxa_adr_s           cn38xx;
-    struct cvmx_gmxx_nxa_adr_s           cn38xxp2;
-    struct cvmx_gmxx_nxa_adr_s           cn50xx;
-    struct cvmx_gmxx_nxa_adr_s           cn52xx;
-    struct cvmx_gmxx_nxa_adr_s           cn52xxp1;
-    struct cvmx_gmxx_nxa_adr_s           cn56xx;
-    struct cvmx_gmxx_nxa_adr_s           cn56xxp1;
-    struct cvmx_gmxx_nxa_adr_s           cn58xx;
-    struct cvmx_gmxx_nxa_adr_s           cn58xxp1;
-} cvmx_gmxx_nxa_adr_t;
-
-
-/**
- * cvmx_gmx#_prt#_cbfc_ctl
- *
- * ** HG2 message CSRs end
- *
- *
- * Notes:
- * XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_prtx_cbfc_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t phys_en                 : 16;      /**< Determines which ports will have physical
-                                                         backpressure pause packets.
-                                                         The value pplaced in the Class Enable Vector
-                                                         field of the CBFC pause packet will be
-                                                         PHYS_EN | LOGL_EN */
-        uint64_t logl_en                 : 16;      /**< Determines which ports will have logical
-                                                         backpressure pause packets.
-                                                         The value pplaced in the Class Enable Vector
-                                                         field of the CBFC pause packet will be
-                                                         PHYS_EN | LOGL_EN */
-        uint64_t phys_bp                 : 16;      /**< When RX_EN is set and the HW is backpressuring any
-                                                         ports (from either CBFC pause packets or the
-                                                         GMX_TX_OVR_BP[TX_PRT_BP] register) and all ports
-                                                         indiciated by PHYS_BP are backpressured, simulate
-                                                         physical backpressure by defering all packets on
-                                                         the transmitter. */
-        uint64_t reserved_4_15           : 12;
-        uint64_t bck_en                  : 1;       /**< Forward CBFC Pause information to BP block */
-        uint64_t drp_en                  : 1;       /**< Drop Control CBFC Pause Frames */
-        uint64_t tx_en                   : 1;       /**< When set, allow for CBFC Pause Packets
-                                                         Must be clear in HiGig2 mode i.e. when
-                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                         GMX_RX_UDD_SKP[SKIP]=16. */
-        uint64_t rx_en                   : 1;       /**< When set, allow for CBFC Pause Packets
-                                                         Must be clear in HiGig2 mode i.e. when
-                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                         GMX_RX_UDD_SKP[SKIP]=16. */
-#else
-        uint64_t rx_en                   : 1;
-        uint64_t tx_en                   : 1;
-        uint64_t drp_en                  : 1;
-        uint64_t bck_en                  : 1;
-        uint64_t reserved_4_15           : 12;
-        uint64_t phys_bp                 : 16;
-        uint64_t logl_en                 : 16;
-        uint64_t phys_en                 : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_prtx_cbfc_ctl_s     cn52xx;
-    struct cvmx_gmxx_prtx_cbfc_ctl_s     cn56xx;
-} cvmx_gmxx_prtx_cbfc_ctl_t;
-
-
-/**
- * cvmx_gmx#_prt#_cfg
- *
- * GMX_PRT_CFG = Port description
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_prtx_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t tx_idle                 : 1;       /**< TX Machine is idle */
-        uint64_t rx_idle                 : 1;       /**< RX Machine is idle */
-        uint64_t reserved_9_11           : 3;
-        uint64_t speed_msb               : 1;       /**< Link Speed MSB [SPEED_MSB:SPEED]
-                                                         10 = 10Mbs operation
-                                                         00 = 100Mbs operation
-                                                         01 = 1000Mbs operation
-                                                         11 = Reserved
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_4_7            : 4;
-        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
-                                                         0 = 512 bitimes (10/100Mbs operation)
-                                                         1 = 4096 bitimes (1000Mbs operation) */
-        uint64_t duplex                  : 1;       /**< Duplex
-                                                         0 = Half Duplex (collisions/extentions/bursts)
-                                                         1 = Full Duplex */
-        uint64_t speed                   : 1;       /**< Link Speed
-                                                         0 = 10/100Mbs operation
-                                                             (GMX_TX_CLK[CLK_CNT] > 1)
-                                                         1 = 1000Mbs operation */
-        uint64_t en                      : 1;       /**< Link Enable
-                                                         When EN is clear, packets will not be received
-                                                         or transmitted (including PAUSE and JAM packets).
-                                                         If EN is cleared while a packet is currently
-                                                         being received or transmitted, the packet will
-                                                         be allowed to complete before the bus is idled.
-                                                         On the RX side, subsequent packets in a burst
-                                                         will be ignored. */
-#else
-        uint64_t en                      : 1;
-        uint64_t speed                   : 1;
-        uint64_t duplex                  : 1;
-        uint64_t slottime                : 1;
-        uint64_t reserved_4_7            : 4;
-        uint64_t speed_msb               : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t rx_idle                 : 1;
-        uint64_t tx_idle                 : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_gmxx_prtx_cfg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
-                                                         0 = 512 bitimes (10/100Mbs operation)
-                                                         1 = 4096 bitimes (1000Mbs operation) */
-        uint64_t duplex                  : 1;       /**< Duplex
-                                                         0 = Half Duplex (collisions/extentions/bursts)
-                                                         1 = Full Duplex */
-        uint64_t speed                   : 1;       /**< Link Speed
-                                                         0 = 10/100Mbs operation
-                                                             (in RGMII mode, GMX_TX_CLK[CLK_CNT] >  1)
-                                                             (in MII   mode, GMX_TX_CLK[CLK_CNT] == 1)
-                                                         1 = 1000Mbs operation */
-        uint64_t en                      : 1;       /**< Link Enable
-                                                         When EN is clear, packets will not be received
-                                                         or transmitted (including PAUSE and JAM packets).
-                                                         If EN is cleared while a packet is currently
-                                                         being received or transmitted, the packet will
-                                                         be allowed to complete before the bus is idled.
-                                                         On the RX side, subsequent packets in a burst
-                                                         will be ignored. */
-#else
-        uint64_t en                      : 1;
-        uint64_t speed                   : 1;
-        uint64_t duplex                  : 1;
-        uint64_t slottime                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn31xx;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn38xx;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn38xxp2;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn50xx;
-    struct cvmx_gmxx_prtx_cfg_s          cn52xx;
-    struct cvmx_gmxx_prtx_cfg_s          cn52xxp1;
-    struct cvmx_gmxx_prtx_cfg_s          cn56xx;
-    struct cvmx_gmxx_prtx_cfg_s          cn56xxp1;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn58xx;
-    struct cvmx_gmxx_prtx_cfg_cn30xx     cn58xxp1;
-} cvmx_gmxx_prtx_cfg_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam0
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam0_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam0_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam1
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam1_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam1_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam2
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam2_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam2_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam3
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam3_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam3_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam4
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam4_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam4_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam5
- *
- * GMX_RX_ADR_CAM = Address Filtering Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t adr                     : 64;      /**< The DMAC address to match on
-                                                         Each entry contributes 8bits to one of 8 matchers
-                                                         Write transactions to GMX_RX_ADR_CAM will not
-                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
-                                                         The CAM matches against unicst or multicst DMAC
-                                                         addresses. */
-#else
-        uint64_t adr                     : 64;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam5_s      cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam5_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_cam_en
- *
- * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_cam_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t en                      : 8;       /**< CAM Entry Enables */
-#else
-        uint64_t en                      : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn30xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn31xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn38xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn50xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn52xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn56xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn58xx;
-    struct cvmx_gmxx_rxx_adr_cam_en_s    cn58xxp1;
-} cvmx_gmxx_rxx_adr_cam_en_t;
-
-
-/**
- * cvmx_gmx#_rx#_adr_ctl
- *
- * GMX_RX_ADR_CTL = Address Filtering Control
- *
- *
- * Notes:
- * * ALGORITHM
- * Here is some pseudo code that represents the address filter behavior.
- * 
- *    @verbatim
- *    bool dmac_addr_filter(uint8 prt, uint48 dmac) [
- *      ASSERT(prt >= 0 && prt <= 3);
- *      if (is_bcst(dmac))                               // broadcast accept
- *        return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
- *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
- *        return REJECT;
- *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
- *        return ACCEPT;
- * 
- *      cam_hit = 0;
- * 
- *      for (i=0; i<8; i++) [
- *        if (GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
- *          continue;
- *        uint48 unswizzled_mac_adr = 0x0;
- *        for (j=5; j>=0; j--) [
- *           unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
- *        ]
- *        if (unswizzled_mac_adr == dmac) [
- *          cam_hit = 1;
- *          break;
- *        ]
- *      ]
- * 
- *      if (cam_hit)
- *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
- *      else
- *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
- *    ]
- *    @endverbatim
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_adr_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t cam_mode                : 1;       /**< Allow or deny DMAC address filter
-                                                         0 = reject the packet on DMAC address match
-                                                         1 = accept the packet on DMAC address match */
-        uint64_t mcst                    : 2;       /**< Multicast Mode
-                                                         0 = Use the Address Filter CAM
-                                                         1 = Force reject all multicast packets
-                                                         2 = Force accept all multicast packets
-                                                         3 = Reserved */
-        uint64_t bcst                    : 1;       /**< Accept All Broadcast Packets */
-#else
-        uint64_t bcst                    : 1;
-        uint64_t mcst                    : 2;
-        uint64_t cam_mode                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn30xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn31xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn38xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn38xxp2;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn50xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn52xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn52xxp1;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn56xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn56xxp1;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn58xx;
-    struct cvmx_gmxx_rxx_adr_ctl_s       cn58xxp1;
-} cvmx_gmxx_rxx_adr_ctl_t;
-
-
-/**
- * cvmx_gmx#_rx#_decision
- *
- * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
- *
- *
- * Notes:
- * As each byte in a packet is received by GMX, the L2 byte count is compared
- * against the GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
- * from the beginning of the L2 header (DMAC).  In normal operation, the L2
- * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any
- * optional UDD skip data (GMX_RX_UDD_SKP[LEN]).
- * 
- * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
- * packet and would require UDD skip length to account for them.
- * 
- *                                                 L2 Size
- * Port Mode             <GMX_RX_DECISION bytes (default=24)       >=GMX_RX_DECISION bytes (default=24)
- * 
- * Full Duplex           accept packet                             apply filters
- *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
- * 
- * Half Duplex           drop packet                               apply filters
- *                       packet is unconditionally dropped         accept packet based on DMAC
- * 
- * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_decision_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t cnt                     : 5;       /**< The byte count to decide when to accept or filter
-                                                         a packet. */
-#else
-        uint64_t cnt                     : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_decision_s      cn30xx;
-    struct cvmx_gmxx_rxx_decision_s      cn31xx;
-    struct cvmx_gmxx_rxx_decision_s      cn38xx;
-    struct cvmx_gmxx_rxx_decision_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_decision_s      cn50xx;
-    struct cvmx_gmxx_rxx_decision_s      cn52xx;
-    struct cvmx_gmxx_rxx_decision_s      cn52xxp1;
-    struct cvmx_gmxx_rxx_decision_s      cn56xx;
-    struct cvmx_gmxx_rxx_decision_s      cn56xxp1;
-    struct cvmx_gmxx_rxx_decision_s      cn58xx;
-    struct cvmx_gmxx_rxx_decision_s      cn58xxp1;
-} cvmx_gmxx_rxx_decision_t;
-
-
-/**
- * cvmx_gmx#_rx#_frm_chk
- *
- * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
- *
- *
- * Notes:
- * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
- * 
- * In XAUI mode prt0 is used for checking.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_frm_chk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn30xx;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn31xx;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn38xx;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn38xxp2;
-    struct cvmx_gmxx_rxx_frm_chk_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t reserved_6_6            : 1;
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t reserved_6_6            : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn50xx;
-    struct cvmx_gmxx_rxx_frm_chk_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
-        uint64_t reserved_5_6            : 2;
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< Carrier extend error
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn52xxp1;
-    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn56xx;
-    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn56xxp1;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn58xx;
-    struct cvmx_gmxx_rxx_frm_chk_s       cn58xxp1;
-} cvmx_gmxx_rxx_frm_chk_t;
-
-
-/**
- * cvmx_gmx#_rx#_frm_ctl
- *
- * GMX_RX_FRM_CTL = Frame Control
- *
- *
- * Notes:
- * * PRE_CHK
- *   When set, the RX state expects a typical frame consisting of
- *   INTER_FRAME=>PREAMBLE(x7)=>SFD(x1)=>DAT.  The state machine watches for
- *   this exact sequence in order to recognize a valid frame and push frame
- *   data into the Octane.  There must be exactly 7 PREAMBLE cycles followed by
- *   the single SFD cycle for the frame to be accepted.
- * 
- *   When a problem does occur within the PREAMBLE seqeunce, the frame is
- *   marked as bad and not sent into the core.  The GMX_RX_INT_REG[PCTERR]
- *   interrupt is also raised.
- * 
- * * PRE_STRP
- *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
- *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
- *   core as part of the packet.
- * 
- *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
- *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
- *   are skipped when locating the start of the L2 header for DMAC and Control
- *   frame recognition.
- * 
- * * CTL_BCK/CTL_DRP
- *   These bits control how the HW handles incoming PAUSE packets.  Here are
- *   the most common modes of operation:
- *     CTL_BCK=1,CTL_DRP=1   - HW does it all
- *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
- *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
- * 
- *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
- *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
- *   would constitute an exception which should be handled by the processing
- *   cores.  PAUSE packets should not be forwarded.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_frm_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t null_dis                : 1;       /**< When set, do not modify the MOD bits on NULL ticks
-                                                         due to PARITAL packets
-                                                         In spi4 mode, all ports use prt0 for checking. */
-        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
-                                                         regardless of the number of previous PREAMBLE
-                                                         nibbles.  In this mode, PREAMBLE can be consumed
-                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
-                                                         PRE_STRP must be set for correct operation.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
-                                                         sized pkts with padding in the client data
-                                                         (PASS3 Only) */
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts
-                                                         (PASS2 only) */
-        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
-                                                         0 - 254 cycles of PREAMBLE followed by SFD */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t pad_len                 : 1;
-        uint64_t pre_align               : 1;
-        uint64_t null_dis                : 1;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_frm_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
-                                                         sized pkts with padding in the client data */
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
-        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
-                                                         0-7 cycles of PREAMBLE followed by SFD (pass 1.0)
-                                                         0-254 cycles of PREAMBLE followed by SFD (else) */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t pad_len                 : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
-        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
-                                                         0 - 7 cycles of PREAMBLE followed by SFD (pass1.0)
-                                                         0 - 254 cycles of PREAMBLE followed by SFD (else) */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } cn31xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn30xx  cn38xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn31xx  cn38xxp2;
-    struct cvmx_gmxx_rxx_frm_ctl_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t null_dis                : 1;       /**< When set, do not modify the MOD bits on NULL ticks
-                                                         due to PARITAL packets */
-        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
-                                                         regardless of the number of previous PREAMBLE
-                                                         nibbles.  In this mode, PREAMBLE can be consumed
-                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
-                                                         PRE_STRP must be set for correct operation.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t reserved_7_8            : 2;
-        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
-                                                         0-254 cycles of PREAMBLE followed by SFD */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t reserved_7_8            : 2;
-        uint64_t pre_align               : 1;
-        uint64_t null_dis                : 1;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn50xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn52xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn52xxp1;
-    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn56xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
-                                                         regardless of the number of previous PREAMBLE
-                                                         nibbles.  In this mode, PRE_STRP should be set to
-                                                         account for the variable nature of the PREAMBLE.
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features.
-                                                         (SGMII at 10/100Mbs only) */
-        uint64_t reserved_7_8            : 2;
-        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
-                                                         0 - 254 cycles of PREAMBLE followed by SFD
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features.
-                                                         (SGMII/1000Base-X only) */
-        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
-        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
-                                                         Multicast address */
-        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
-        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
-        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
-                                                         0=PREAMBLE+SFD is sent to core as part of frame
-                                                         1=PREAMBLE+SFD is dropped
-                                                         PRE_CHK must be set to enable this and all
-                                                         PREAMBLE features. */
-        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
-                                                         to begin every frame.  GMX checks that the
-                                                         PREAMBLE is sent correctly.
-                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK
-                                                         must be zero. */
-#else
-        uint64_t pre_chk                 : 1;
-        uint64_t pre_strp                : 1;
-        uint64_t ctl_drp                 : 1;
-        uint64_t ctl_bck                 : 1;
-        uint64_t ctl_mcst                : 1;
-        uint64_t ctl_smac                : 1;
-        uint64_t pre_free                : 1;
-        uint64_t reserved_7_8            : 2;
-        uint64_t pre_align               : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn56xxp1;
-    struct cvmx_gmxx_rxx_frm_ctl_s       cn58xx;
-    struct cvmx_gmxx_rxx_frm_ctl_cn30xx  cn58xxp1;
-} cvmx_gmxx_rxx_frm_ctl_t;
-
-
-/**
- * cvmx_gmx#_rx#_frm_max
- *
- * GMX_RX_FRM_MAX = Frame Max length
- *
- *
- * Notes:
- * In spi4 mode, all spi4 ports use prt0 for checking.
- * 
- * When changing the LEN field, be sure that LEN does not exceed
- * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
- * are within the maximum length parameter to be rejected because they exceed
- * the GMX_RX_JABBER[CNT] limit.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_frm_max_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t len                     : 16;      /**< Byte count for Max-sized frame check
-                                                         Failing packets set the MAXERR interrupt and are
-                                                         optionally sent with opcode==MAXERR
-                                                         LEN =< GMX_RX_JABBER[CNT] */
-#else
-        uint64_t len                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_frm_max_s       cn30xx;
-    struct cvmx_gmxx_rxx_frm_max_s       cn31xx;
-    struct cvmx_gmxx_rxx_frm_max_s       cn38xx;
-    struct cvmx_gmxx_rxx_frm_max_s       cn38xxp2;
-    struct cvmx_gmxx_rxx_frm_max_s       cn58xx;
-    struct cvmx_gmxx_rxx_frm_max_s       cn58xxp1;
-} cvmx_gmxx_rxx_frm_max_t;
-
-
-/**
- * cvmx_gmx#_rx#_frm_min
- *
- * GMX_RX_FRM_MIN = Frame Min length
- *
- *
- * Notes:
- * In spi4 mode, all spi4 ports use prt0 for checking.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_frm_min_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t len                     : 16;      /**< Byte count for Min-sized frame check
-                                                         Failing packets set the MINERR interrupt and are
-                                                         optionally sent with opcode==MINERR */
-#else
-        uint64_t len                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_frm_min_s       cn30xx;
-    struct cvmx_gmxx_rxx_frm_min_s       cn31xx;
-    struct cvmx_gmxx_rxx_frm_min_s       cn38xx;
-    struct cvmx_gmxx_rxx_frm_min_s       cn38xxp2;
-    struct cvmx_gmxx_rxx_frm_min_s       cn58xx;
-    struct cvmx_gmxx_rxx_frm_min_s       cn58xxp1;
-} cvmx_gmxx_rxx_frm_min_t;
-
-
-/**
- * cvmx_gmx#_rx#_ifg
- *
- * GMX_RX_IFG = RX Min IFG
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_ifg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ifg                     : 4;       /**< Min IFG between packets used to determine IFGERR
-                                                         1000Mbs, IFG==0.096us or 12 clks
-                                                         100Mbs,  IFG==0.96us or 24 clks
-                                                         10Mbs,   IFG==9.6us or 24 clks
-                                                         In order to simplify the programming model,
-                                                         IFG is doubled internally when
-                                                         GMX_PRT_CFG[SPEED]==0. */
-#else
-        uint64_t ifg                     : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_ifg_s           cn30xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn31xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn38xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn38xxp2;
-    struct cvmx_gmxx_rxx_ifg_s           cn50xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn52xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn52xxp1;
-    struct cvmx_gmxx_rxx_ifg_s           cn56xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn56xxp1;
-    struct cvmx_gmxx_rxx_ifg_s           cn58xx;
-    struct cvmx_gmxx_rxx_ifg_s           cn58xxp1;
-} cvmx_gmxx_rxx_ifg_t;
-
-
-/**
- * cvmx_gmx#_rx#_int_en
- *
- * GMX_RX_INT_EN = Interrupt Enable
- *
- *
- * Notes:
- * In XAUI mode prt0 is used for checking.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t hg2cc                   : 1;       /**< HiGig2 CRC8 or Control char error interrupt enable */
-        uint64_t hg2fld                  : 1;       /**< HiGig2 Bad field error interrupt enable */
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t hg2fld                  : 1;
-        uint64_t hg2cc                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_int_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_rxx_int_en_cn30xx   cn31xx;
-    struct cvmx_gmxx_rxx_int_en_cn30xx   cn38xx;
-    struct cvmx_gmxx_rxx_int_en_cn30xx   cn38xxp2;
-    struct cvmx_gmxx_rxx_int_en_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t reserved_6_6            : 1;
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t reserved_6_6            : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn50xx;
-    struct cvmx_gmxx_rxx_int_en_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t hg2cc                   : 1;       /**< HiGig2 CRC8 or Control char error interrupt enable */
-        uint64_t hg2fld                  : 1;       /**< HiGig2 Bad field error interrupt enable */
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         (SGMII/1000Base-X only) */
-        uint64_t coldet                  : 1;       /**< Collision Detection
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
-                                                         (SGMII/1000Base-X only) */
-        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
-        uint64_t reserved_5_6            : 2;
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< Carrier extend error
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t hg2fld                  : 1;
-        uint64_t hg2cc                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_rxx_int_en_cn52xx   cn52xxp1;
-    struct cvmx_gmxx_rxx_int_en_cn52xx   cn56xx;
-    struct cvmx_gmxx_rxx_int_en_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         (SGMII/1000Base-X only) */
-        uint64_t coldet                  : 1;       /**< Collision Detection
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
-                                                         (SGMII/1000Base-X only) */
-        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
-        uint64_t reserved_5_6            : 2;
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< Carrier extend error
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn56xxp1;
-    struct cvmx_gmxx_rxx_int_en_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn58xx;
-    struct cvmx_gmxx_rxx_int_en_cn58xx   cn58xxp1;
-} cvmx_gmxx_rxx_int_en_t;
-
-
-/**
- * cvmx_gmx#_rx#_int_reg
- *
- * GMX_RX_INT_REG = Interrupt Register
- *
- *
- * Notes:
- * (1) exceptions will only be raised to the control processor if the
- *     corresponding bit in the GMX_RX_INT_EN register is set.
- * 
- * (2) exception conditions 10:0 can also set the rcv/opcode in the received
- *     packet's workQ entry.  The GMX_RX_FRM_CHK register provides a bit mask
- *     for configuring which conditions set the error.
- * 
- * (3) in half duplex operation, the expectation is that collisions will appear
- *     as either MINERR o r CAREXT errors.
- * 
- * (4) JABBER - An RX Jabber error indicates that a packet was received which
- *              is longer than the maximum allowed packet as defined by the
- *              system.  GMX will truncate the packet at the JABBER count.
- *              Failure to do so could lead to system instabilty.
- * 
- * (5) NIBERR - This error is illegal at 1000Mbs speeds
- *              (GMX_RX_PRT_CFG[SPEED]==0) and will never assert.
- * 
- * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
- *              GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
- *              > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
- * 
- * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < GMX_RX_FRM_MIN.
- * 
- * (8) ALNERR - Indicates that the packet received was not an integer number of
- *              bytes.  If FCS checking is enabled, ALNERR will only assert if
- *              the FCS is bad.  If FCS checking is disabled, ALNERR will
- *              assert in all non-integer frame cases.
- * 
- * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
- *                  is assumed by the receiver when the slottime
- *                  (GMX_PRT_CFG[SLOTTIME]) is not satisfied.  In 10/100 mode,
- *                  this will result in a frame < SLOTTIME.  In 1000 mode, it
- *                  could result either in frame < SLOTTIME or a carrier extend
- *                  error with the SLOTTIME.  These conditions are visible by...
- * 
- *                  . transfer ended before slottime - COLDET
- *                  . carrier extend error           - CAREXT
- * 
- * (A) LENERR - Length errors occur when the received packet does not match the
- *              length field.  LENERR is only checked for packets between 64
- *              and 1500 bytes.  For untagged frames, the length must exact
- *              match.  For tagged frames the length or length+4 must match.
- * 
- * (B) PCTERR - checks that the frame transtions from PREAMBLE=>SFD=>DATA.
- *              Does not check the number of PREAMBLE cycles.
- * 
- * (C) OVRERR - Not to be included in the HRM
- * 
- *              OVRERR is an architectural assertion check internal to GMX to
- *              make sure no assumption was violated.  In a correctly operating
- *              system, this interrupt can never fire.
- * 
- *              GMX has an internal arbiter which selects which of 4 ports to
- *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
- *              then each port will typically push a tick every 8 cycles - if
- *              the packet interface is going as fast as possible.  If there
- *              are four ports, they push every two cycles.  So that's the
- *              assumption.  That the inbound module will always be able to
- *              consume the tick before another is produced.  If that doesn't
- *              happen - that's when OVRERR will assert.
- * 
- * (D) In XAUI mode prt0 is used for interrupt logging.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t hg2cc                   : 1;       /**< HiGig2 received message CRC or Control char  error
-                                                         Set when either CRC8 error detected or when
-                                                         a Control Character is found in the message
-                                                         bytes after the K.SOM
-                                                         NOTE: HG2CC has higher priority than HG2FLD
-                                                               i.e. a HiGig2 message that results in HG2CC
-                                                               getting set, will never set HG2FLD. */
-        uint64_t hg2fld                  : 1;       /**< HiGig2 received message field error, as below
-                                                         1) MSG_TYPE field not 6'b00_0000
-                                                            i.e. it is not a FLOW CONTROL message, which
-                                                            is the only defined type for HiGig2
-                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
-                                                            which is the only defined type for HiGig2
-                                                         3) FC_OBJECT field is neither 4'b0000 for
-                                                            Physical Link nor 4'b0010 for Logical Link.
-                                                            Those are the only two defined types in HiGig2 */
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t hg2fld                  : 1;
-        uint64_t hg2cc                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_int_reg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn31xx;
-    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn38xx;
-    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn38xxp2;
-    struct cvmx_gmxx_rxx_int_reg_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t reserved_6_6            : 1;
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t reserved_6_6            : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn50xx;
-    struct cvmx_gmxx_rxx_int_reg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t hg2cc                   : 1;       /**< HiGig2 received message CRC or Control char  error
-                                                         Set when either CRC8 error detected or when
-                                                         a Control Character is found in the message
-                                                         bytes after the K.SOM
-                                                         NOTE: HG2CC has higher priority than HG2FLD
-                                                               i.e. a HiGig2 message that results in HG2CC
-                                                               getting set, will never set HG2FLD. */
-        uint64_t hg2fld                  : 1;       /**< HiGig2 received message field error, as below
-                                                         1) MSG_TYPE field not 6'b00_0000
-                                                            i.e. it is not a FLOW CONTROL message, which
-                                                            is the only defined type for HiGig2
-                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
-                                                            which is the only defined type for HiGig2
-                                                         3) FC_OBJECT field is neither 4'b0000 for
-                                                            Physical Link nor 4'b0010 for Logical Link.
-                                                            Those are the only two defined types in HiGig2 */
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure
-                                                         (SGMII/1000Base-X only) */
-        uint64_t coldet                  : 1;       /**< Collision Detection
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
-                                                         (SGMII/1000Base-X only) */
-        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol
-                                                         In XAUI mode, the column of data that was bad
-                                                         will be logged in GMX_RX_XAUI_BAD_COL */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
-        uint64_t reserved_5_6            : 2;
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< Carrier extend error
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t hg2fld                  : 1;
-        uint64_t hg2cc                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_rxx_int_reg_cn52xx  cn52xxp1;
-    struct cvmx_gmxx_rxx_int_reg_cn52xx  cn56xx;
-    struct cvmx_gmxx_rxx_int_reg_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t undat                   : 1;       /**< Unexpected Data
-                                                         (XAUI Mode only) */
-        uint64_t uneop                   : 1;       /**< Unexpected EOP
-                                                         (XAUI Mode only) */
-        uint64_t unsop                   : 1;       /**< Unexpected SOP
-                                                         (XAUI Mode only) */
-        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
-                                                         than /T/.  The error propagation control
-                                                         character /E/ will be included as part of the
-                                                         frame and does not cause a frame termination.
-                                                         (XAUI Mode only) */
-        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
-                                                         (XAUI Mode only) */
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t reserved_16_18          : 3;
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure
-                                                         (SGMII/1000Base-X only) */
-        uint64_t coldet                  : 1;       /**< Collision Detection
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
-                                                         (SGMII/1000Base-X only) */
-        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol
-                                                         In XAUI mode, the column of data that was bad
-                                                         will be logged in GMX_RX_XAUI_BAD_COL */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_9_9            : 1;
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
-        uint64_t reserved_5_6            : 2;
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t reserved_2_2            : 1;
-        uint64_t carext                  : 1;       /**< Carrier extend error
-                                                         (SGMII/1000Base-X only) */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t carext                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t pause_drp               : 1;
-        uint64_t loc_fault               : 1;
-        uint64_t rem_fault               : 1;
-        uint64_t bad_seq                 : 1;
-        uint64_t bad_term                : 1;
-        uint64_t unsop                   : 1;
-        uint64_t uneop                   : 1;
-        uint64_t undat                   : 1;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn56xxp1;
-    struct cvmx_gmxx_rxx_int_reg_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
-        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
-        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
-        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
-        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
-                                                         Does not necessarily indicate a failure */
-        uint64_t coldet                  : 1;       /**< Collision Detection */
-        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
-        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
-        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
-        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
-                                                         This interrupt should never assert */
-        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
-        uint64_t skperr                  : 1;       /**< Skipper error */
-        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
-        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
-        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-#else
-        uint64_t minerr                  : 1;
-        uint64_t carext                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t jabber                  : 1;
-        uint64_t fcserr                  : 1;
-        uint64_t alnerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t rcverr                  : 1;
-        uint64_t skperr                  : 1;
-        uint64_t niberr                  : 1;
-        uint64_t ovrerr                  : 1;
-        uint64_t pcterr                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t falerr                  : 1;
-        uint64_t coldet                  : 1;
-        uint64_t ifgerr                  : 1;
-        uint64_t phy_link                : 1;
-        uint64_t phy_spd                 : 1;
-        uint64_t phy_dupx                : 1;
-        uint64_t pause_drp               : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn58xx;
-    struct cvmx_gmxx_rxx_int_reg_cn58xx  cn58xxp1;
-} cvmx_gmxx_rxx_int_reg_t;
-
-
-/**
- * cvmx_gmx#_rx#_jabber
- *
- * GMX_RX_JABBER = The max size packet after which GMX will truncate
- *
- *
- * Notes:
- * CNT must be 8-byte aligned such that CNT[2:0] == 0
- * 
- * The packet that will be sent to the packet input logic will have an
- * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and
- * GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
- * defined as...
- * 
- *      max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8)
- * 
- * In XAUI mode prt0 is used for checking.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_jabber_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt                     : 16;      /**< Byte count for jabber check
-                                                         Failing packets set the JABBER interrupt and are
-                                                         optionally sent with opcode==JABBER
-                                                         GMX will truncate the packet to CNT bytes
-                                                         CNT >= GMX_RX_FRM_MAX[LEN] */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_jabber_s        cn30xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn31xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn38xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn38xxp2;
-    struct cvmx_gmxx_rxx_jabber_s        cn50xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn52xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn52xxp1;
-    struct cvmx_gmxx_rxx_jabber_s        cn56xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn56xxp1;
-    struct cvmx_gmxx_rxx_jabber_s        cn58xx;
-    struct cvmx_gmxx_rxx_jabber_s        cn58xxp1;
-} cvmx_gmxx_rxx_jabber_t;
-
-
-/**
- * cvmx_gmx#_rx#_pause_drop_time
- *
- * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_pause_drop_time_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t status                  : 16;      /**< Time extracted from the dropped PAUSE packet */
-#else
-        uint64_t status                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
-    struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
-} cvmx_gmxx_rxx_pause_drop_time_t;
-
-
-/**
- * cvmx_gmx#_rx#_rx_inbnd
- *
- * GMX_RX_INBND = RGMII InBand Link Status
- *
- *
- * Notes:
- * These fields are only valid if the attached PHY is operating in RGMII mode
- * and supports the optional in-band status (see section 3.4.1 of the RGMII
- * specification, version 1.3 for more information).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_rx_inbnd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t duplex                  : 1;       /**< RGMII Inbound LinkDuplex
-                                                         0=half-duplex
-                                                         1=full-duplex */
-        uint64_t speed                   : 2;       /**< RGMII Inbound LinkSpeed
-                                                         00=2.5MHz
-                                                         01=25MHz
-                                                         10=125MHz
-                                                         11=Reserved */
-        uint64_t status                  : 1;       /**< RGMII Inbound LinkStatus
-                                                         0=down
-                                                         1=up */
-#else
-        uint64_t status                  : 1;
-        uint64_t speed                   : 2;
-        uint64_t duplex                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn30xx;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn31xx;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn38xx;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn38xxp2;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn50xx;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn58xx;
-    struct cvmx_gmxx_rxx_rx_inbnd_s      cn58xxp1;
-} cvmx_gmxx_rxx_rx_inbnd_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_ctl
- *
- * GMX_RX_STATS_CTL = RX Stats Control register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rd_clr                  : 1;       /**< RX Stats registers will clear on reads */
-#else
-        uint64_t rd_clr                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn30xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn31xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn38xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn50xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn52xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn56xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn58xx;
-    struct cvmx_gmxx_rxx_stats_ctl_s     cn58xxp1;
-} cvmx_gmxx_rxx_stats_ctl_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_octs
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_octs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of received good packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn30xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn31xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn38xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn50xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn52xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn56xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn58xx;
-    struct cvmx_gmxx_rxx_stats_octs_s    cn58xxp1;
-} cvmx_gmxx_rxx_stats_octs_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_octs_ctl
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of received pause packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_octs_ctl_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_octs_dmac
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of filtered dmac packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_octs_dmac_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_octs_drp
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t cnt                     : 48;      /**< Octet count of dropped packets */
-#else
-        uint64_t cnt                     : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_octs_drp_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_pkts
- *
- * GMX_RX_STATS_PKTS
- * 
- * Count of good received packets - packets that are not recognized as PAUSE
- * packets, dropped due the DMAC filter, dropped due FIFO full status, or
- * have any other OPCODE (FCS, Length, etc).
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_pkts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of received good packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn30xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn31xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn38xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn50xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn52xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn56xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn58xx;
-    struct cvmx_gmxx_rxx_stats_pkts_s    cn58xxp1;
-} cvmx_gmxx_rxx_stats_pkts_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_pkts_bad
- *
- * GMX_RX_STATS_PKTS_BAD
- * 
- * Count of all packets received with some error that were not dropped
- * either due to the dmac filter or lack of room in the receive FIFO.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of bad packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_pkts_bad_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_pkts_ctl
- *
- * GMX_RX_STATS_PKTS_CTL
- * 
- * Count of all packets received that were recognized as Flow Control or
- * PAUSE packets.  PAUSE packets with any kind of error are counted in
- * GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
- * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
- * increments regardless of whether the packet is dropped.  Pause packets
- * will never be counted in GMX_RX_STATS_PKTS.  Packets dropped due the dmac
- * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of received pause packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_pkts_ctl_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_pkts_dmac
- *
- * GMX_RX_STATS_PKTS_DMAC
- * 
- * Count of all packets received that were dropped by the dmac filter.
- * Packets that match the DMAC will be dropped and counted here regardless
- * of if they were bad packets.  These packets will never be counted in
- * GMX_RX_STATS_PKTS.
- * 
- * Some packets that were not able to satisify the DECISION_CNT may not
- * actually be dropped by Octeon, but they will be counted here as if they
- * were dropped.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of filtered dmac packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_pkts_dmac_t;
-
-
-/**
- * cvmx_gmx#_rx#_stats_pkts_drp
- *
- * GMX_RX_STATS_PKTS_DRP
- * 
- * Count of all packets received that were dropped due to a full receive
- * FIFO.  This counts good and bad packets received - all packets dropped by
- * the FIFO.  It does not count packets dropped by the dmac or pause packet
- * filters.
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Count of dropped packets */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
-    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
-} cvmx_gmxx_rxx_stats_pkts_drp_t;
-
-
-/**
- * cvmx_gmx#_rx#_udd_skp
- *
- * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
- *
- *
- * Notes:
- * (1) The skip bytes are part of the packet and will be sent down the NCB
- *     packet interface and will be handled by PKI.
- * 
- * (2) The system can determine if the UDD bytes are included in the FCS check
- *     by using the FCSSEL field - if the FCS check is enabled.
- * 
- * (3) Assume that the preamble/sfd is always at the start of the frame - even
- *     before UDD bytes.  In most cases, there will be no preamble in these
- *     cases since it will be packet interface in direct communication to
- *     another packet interface (MAC to MAC) without a PHY involved.
- * 
- * (4) We can still do address filtering and control packet filtering is the
- *     user desires.
- * 
- * (5) UDD_SKP must be 0 in half-duplex operation unless
- *     GMX_RX_FRM_CTL[PRE_CHK] is clear.  If GMX_RX_FRM_CTL[PRE_CHK] is clear,
- *     then UDD_SKP will normally be 8.
- * 
- * (6) In all cases, the UDD bytes will be sent down the packet interface as
- *     part of the packet.  The UDD bytes are never stripped from the actual
- *     packet.
- * 
- * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rxx_udd_skp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t fcssel                  : 1;       /**< Include the skip bytes in the FCS calculation
-                                                         0 = all skip bytes are included in FCS
-                                                         1 = the skip bytes are not included in FCS */
-        uint64_t reserved_7_7            : 1;
-        uint64_t len                     : 7;       /**< Amount of User-defined data before the start of
-                                                         the L2 data.  Zero means L2 comes first.
-                                                         Max value is 64. */
-#else
-        uint64_t len                     : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t fcssel                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn30xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn31xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn38xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn38xxp2;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn50xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn52xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn52xxp1;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn56xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn56xxp1;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn58xx;
-    struct cvmx_gmxx_rxx_udd_skp_s       cn58xxp1;
-} cvmx_gmxx_rxx_udd_skp_t;
-
-
-/**
- * cvmx_gmx#_rx_bp_drop#
- *
- * GMX_RX_BP_DROP = FIFO mark for packet drop
- *
- *
- * Notes:
- * The actual watermark is dynamic with respect to the GMX_RX_PRTS
- * register.  The GMX_RX_PRTS controls the depth of the port's
- * FIFO so as ports are added or removed, the drop point may change.
- * 
- * In XAUI mode prt0 is used for checking.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_bp_dropx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mark                    : 6;       /**< Number of 8B ticks to reserve in the RX FIFO.
-                                                         When the FIFO exceeds this count, packets will
-                                                         be dropped and not buffered.
-                                                         MARK should typically be programmed to ports+1.
-                                                         Failure to program correctly can lead to system
-                                                         instability.
-                                                         Reset value for RGMII mode = 2
-                                                         Reset value for Spi4 mode  = 17 */
-#else
-        uint64_t mark                    : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn30xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn31xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn38xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn38xxp2;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn50xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn52xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn52xxp1;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn56xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn56xxp1;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn58xx;
-    struct cvmx_gmxx_rx_bp_dropx_s       cn58xxp1;
-} cvmx_gmxx_rx_bp_dropx_t;
-
-
-/**
- * cvmx_gmx#_rx_bp_off#
- *
- * GMX_RX_BP_OFF = Lowater mark for packet drop
- *
- *
- * Notes:
- * In XAUI mode, prt0 is used for checking.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_bp_offx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mark                    : 6;       /**< Water mark (8B ticks) to deassert backpressure */
-#else
-        uint64_t mark                    : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_bp_offx_s        cn30xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn31xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn38xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn38xxp2;
-    struct cvmx_gmxx_rx_bp_offx_s        cn50xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn52xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn52xxp1;
-    struct cvmx_gmxx_rx_bp_offx_s        cn56xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn56xxp1;
-    struct cvmx_gmxx_rx_bp_offx_s        cn58xx;
-    struct cvmx_gmxx_rx_bp_offx_s        cn58xxp1;
-} cvmx_gmxx_rx_bp_offx_t;
-
-
-/**
- * cvmx_gmx#_rx_bp_on#
- *
- * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
- *
- *
- * Notes:
- * In XAUI mode, prt0 is used for checking.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_bp_onx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t mark                    : 9;       /**< Hiwater mark (8B ticks) for backpressure.
-                                                         In RGMII mode, the backpressure is given per
-                                                         port.  In Spi4 mode, the backpressure is for the
-                                                         entire interface.  GMX_RX_BP_ON must satisfy
-                                                         BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP)
-                                                         The reset value is half the FIFO.
-                                                         Reset value RGMII mode = 0x40  (512bytes)
-                                                         Reset value Spi4 mode  = 0x100 (2048bytes)
-                                                         A value of zero will immediately assert back
-                                                         pressure. */
-#else
-        uint64_t mark                    : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_bp_onx_s         cn30xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn31xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn38xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn38xxp2;
-    struct cvmx_gmxx_rx_bp_onx_s         cn50xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn52xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn52xxp1;
-    struct cvmx_gmxx_rx_bp_onx_s         cn56xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn56xxp1;
-    struct cvmx_gmxx_rx_bp_onx_s         cn58xx;
-    struct cvmx_gmxx_rx_bp_onx_s         cn58xxp1;
-} cvmx_gmxx_rx_bp_onx_t;
-
-
-/**
- * cvmx_gmx#_rx_hg2_status
- *
- * ** HG2 message CSRs
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_hg2_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t phtim2go                : 16;      /**< Physical time to go for removal of physical link
-                                                         pause. Initial value from received HiGig2 msg pkt
-                                                         Non-zero only when physical back pressure active */
-        uint64_t xof                     : 16;      /**< 16 bit xof back pressure vector from HiGig2 msg pkt
-                                                         or from CBFC packets.
-                                                         Non-zero only when logical back pressure is active
-                                                         All bits will be 0 when LGTIM2GO=0 */
-        uint64_t lgtim2go                : 16;      /**< Logical packet flow back pressure time remaining
-                                                         Initial value set from xof time field of HiGig2
-                                                         message packet received or a function of the
-                                                         enabled and current timers for CBFC packets.
-                                                         Non-zero only when logical back pressure is active */
-#else
-        uint64_t lgtim2go                : 16;
-        uint64_t xof                     : 16;
-        uint64_t phtim2go                : 16;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_hg2_status_s     cn52xx;
-    struct cvmx_gmxx_rx_hg2_status_s     cn52xxp1;
-    struct cvmx_gmxx_rx_hg2_status_s     cn56xx;
-} cvmx_gmxx_rx_hg2_status_t;
-
-
-/**
- * cvmx_gmx#_rx_pass_en
- *
- * GMX_RX_PASS_EN = Packet pass through mode enable
- * 
- * When both Octane ports are running in Spi4 mode, packets can be directly
- * passed from one SPX interface to the other without being processed by the
- * core or PP's.  The register has one bit for each port to enable the pass
- * through feature.
- *
- * Notes:
- * (1) Can only be used in dual Spi4 configs
- * 
- * (2) The mapped pass through output port cannot be the destination port for
- *     any Octane core traffic.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_pass_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t en                      : 16;      /**< Which ports to configure in pass through mode */
-#else
-        uint64_t en                      : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_pass_en_s        cn38xx;
-    struct cvmx_gmxx_rx_pass_en_s        cn38xxp2;
-    struct cvmx_gmxx_rx_pass_en_s        cn58xx;
-    struct cvmx_gmxx_rx_pass_en_s        cn58xxp1;
-} cvmx_gmxx_rx_pass_en_t;
-
-
-/**
- * cvmx_gmx#_rx_pass_map#
- *
- * GMX_RX_PASS_MAP = Packet pass through port map
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_pass_mapx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t dprt                    : 4;       /**< Destination port to map Spi pass through traffic */
-#else
-        uint64_t dprt                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_pass_mapx_s      cn38xx;
-    struct cvmx_gmxx_rx_pass_mapx_s      cn38xxp2;
-    struct cvmx_gmxx_rx_pass_mapx_s      cn58xx;
-    struct cvmx_gmxx_rx_pass_mapx_s      cn58xxp1;
-} cvmx_gmxx_rx_pass_mapx_t;
-
-
-/**
- * cvmx_gmx#_rx_prt_info
- *
- * GMX_RX_PRT_INFO = Report the RX status for port
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_prt_info_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t drop                    : 16;      /**< Per port indication that data was dropped
-                                                         (PASS3 only) */
-        uint64_t commit                  : 16;      /**< Per port indication that SOP was accepted
-                                                         (PASS3 only) */
-#else
-        uint64_t commit                  : 16;
-        uint64_t drop                    : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_prt_info_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t drop                    : 3;       /**< Per port indication that data was dropped */
-        uint64_t reserved_3_15           : 13;
-        uint64_t commit                  : 3;       /**< Per port indication that SOP was accepted */
-#else
-        uint64_t commit                  : 3;
-        uint64_t reserved_3_15           : 13;
-        uint64_t drop                    : 3;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_rx_prt_info_cn30xx  cn31xx;
-    struct cvmx_gmxx_rx_prt_info_s       cn38xx;
-    struct cvmx_gmxx_rx_prt_info_cn30xx  cn50xx;
-    struct cvmx_gmxx_rx_prt_info_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t drop                    : 4;       /**< Per port indication that data was dropped */
-        uint64_t reserved_4_15           : 12;
-        uint64_t commit                  : 4;       /**< Per port indication that SOP was accepted */
-#else
-        uint64_t commit                  : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t drop                    : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_rx_prt_info_cn52xx  cn52xxp1;
-    struct cvmx_gmxx_rx_prt_info_cn52xx  cn56xx;
-    struct cvmx_gmxx_rx_prt_info_cn52xx  cn56xxp1;
-    struct cvmx_gmxx_rx_prt_info_s       cn58xx;
-    struct cvmx_gmxx_rx_prt_info_s       cn58xxp1;
-} cvmx_gmxx_rx_prt_info_t;
-
-
-/**
- * cvmx_gmx#_rx_prts
- *
- * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into
- *
- *
- * Notes:
- * GMX_RX_PRTS is unused in XAUI mode since the RX buffer is always unified.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_prts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t prts                    : 3;       /**< In RGMII mode, the RX buffer can be carved into
-                                                         several logical buffers depending on the number
-                                                         or implemented ports.
-                                                         0 or 1 port  = 512ticks / 4096bytes
-                                                         2 ports      = 256ticks / 2048bytes
-                                                         3 or 4 ports = 128ticks / 1024bytes */
-#else
-        uint64_t prts                    : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_prts_s           cn30xx;
-    struct cvmx_gmxx_rx_prts_s           cn31xx;
-    struct cvmx_gmxx_rx_prts_s           cn38xx;
-    struct cvmx_gmxx_rx_prts_s           cn38xxp2;
-    struct cvmx_gmxx_rx_prts_s           cn50xx;
-    struct cvmx_gmxx_rx_prts_s           cn52xx;
-    struct cvmx_gmxx_rx_prts_s           cn52xxp1;
-    struct cvmx_gmxx_rx_prts_s           cn56xx;
-    struct cvmx_gmxx_rx_prts_s           cn56xxp1;
-    struct cvmx_gmxx_rx_prts_s           cn58xx;
-    struct cvmx_gmxx_rx_prts_s           cn58xxp1;
-} cvmx_gmxx_rx_prts_t;
-
-
-/**
- * cvmx_gmx#_rx_tx_status
- *
- * GMX_RX_TX_STATUS = GMX RX/TX Status
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_tx_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t tx                      : 3;       /**< Transmit data since last read */
-        uint64_t reserved_3_3            : 1;
-        uint64_t rx                      : 3;       /**< Receive data since last read */
-#else
-        uint64_t rx                      : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t tx                      : 3;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_tx_status_s      cn30xx;
-    struct cvmx_gmxx_rx_tx_status_s      cn31xx;
-    struct cvmx_gmxx_rx_tx_status_s      cn50xx;
-} cvmx_gmxx_rx_tx_status_t;
-
-
-/**
- * cvmx_gmx#_rx_xaui_bad_col
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_xaui_bad_col_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t val                     : 1;       /**< Set when GMX_RX_INT_REG[PCTERR] is set.
-                                                         (XAUI mode only) */
-        uint64_t state                   : 3;       /**< When GMX_RX_INT_REG[PCTERR] is set, STATE will
-                                                         conatin the receive state at the time of the
-                                                         error.
-                                                         (XAUI mode only) */
-        uint64_t lane_rxc                : 4;       /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXC will
-                                                         conatin the XAUI column at the time of the error.
-                                                         (XAUI mode only) */
-        uint64_t lane_rxd                : 32;      /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXD will
-                                                         conatin the XAUI column at the time of the error.
-                                                         (XAUI mode only) */
-#else
-        uint64_t lane_rxd                : 32;
-        uint64_t lane_rxc                : 4;
-        uint64_t state                   : 3;
-        uint64_t val                     : 1;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_xaui_bad_col_s   cn52xx;
-    struct cvmx_gmxx_rx_xaui_bad_col_s   cn52xxp1;
-    struct cvmx_gmxx_rx_xaui_bad_col_s   cn56xx;
-    struct cvmx_gmxx_rx_xaui_bad_col_s   cn56xxp1;
-} cvmx_gmxx_rx_xaui_bad_col_t;
-
-
-/**
- * cvmx_gmx#_rx_xaui_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_rx_xaui_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t status                  : 2;       /**< Link Status
-                                                         0=Link OK
-                                                         1=Local Fault
-                                                         2=Remote Fault
-                                                         3=Reserved
-                                                         (XAUI mode only) */
-#else
-        uint64_t status                  : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_gmxx_rx_xaui_ctl_s       cn52xx;
-    struct cvmx_gmxx_rx_xaui_ctl_s       cn52xxp1;
-    struct cvmx_gmxx_rx_xaui_ctl_s       cn56xx;
-    struct cvmx_gmxx_rx_xaui_ctl_s       cn56xxp1;
-} cvmx_gmxx_rx_xaui_ctl_t;
-
-
-/**
- * cvmx_gmx#_smac#
- *
- * GMX_SMAC = Packet SMAC
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_smacx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t smac                    : 48;      /**< The SMAC field is used for generating and
-                                                         accepting Control Pause packets */
-#else
-        uint64_t smac                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_smacx_s             cn30xx;
-    struct cvmx_gmxx_smacx_s             cn31xx;
-    struct cvmx_gmxx_smacx_s             cn38xx;
-    struct cvmx_gmxx_smacx_s             cn38xxp2;
-    struct cvmx_gmxx_smacx_s             cn50xx;
-    struct cvmx_gmxx_smacx_s             cn52xx;
-    struct cvmx_gmxx_smacx_s             cn52xxp1;
-    struct cvmx_gmxx_smacx_s             cn56xx;
-    struct cvmx_gmxx_smacx_s             cn56xxp1;
-    struct cvmx_gmxx_smacx_s             cn58xx;
-    struct cvmx_gmxx_smacx_s             cn58xxp1;
-} cvmx_gmxx_smacx_t;
-
-
-/**
- * cvmx_gmx#_stat_bp
- *
- * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_stat_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t bp                      : 1;       /**< Current BP state */
-        uint64_t cnt                     : 16;      /**< Number of cycles that BP has been asserted
-                                                         Saturating counter */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t bp                      : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_gmxx_stat_bp_s           cn30xx;
-    struct cvmx_gmxx_stat_bp_s           cn31xx;
-    struct cvmx_gmxx_stat_bp_s           cn38xx;
-    struct cvmx_gmxx_stat_bp_s           cn38xxp2;
-    struct cvmx_gmxx_stat_bp_s           cn50xx;
-    struct cvmx_gmxx_stat_bp_s           cn52xx;
-    struct cvmx_gmxx_stat_bp_s           cn52xxp1;
-    struct cvmx_gmxx_stat_bp_s           cn56xx;
-    struct cvmx_gmxx_stat_bp_s           cn56xxp1;
-    struct cvmx_gmxx_stat_bp_s           cn58xx;
-    struct cvmx_gmxx_stat_bp_s           cn58xxp1;
-} cvmx_gmxx_stat_bp_t;
-
-
-/**
- * cvmx_gmx#_tx#_append
- *
- * GMX_TX_APPEND = Packet TX Append Control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_append_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t force_fcs               : 1;       /**< Append the Ethernet FCS on each pause packet
-                                                         When FCS is clear
-                                                         This implies that FCS==0 and PAD==0
-                                                         (PASS2 only) */
-        uint64_t fcs                     : 1;       /**< Append the Ethernet FCS on each packet */
-        uint64_t pad                     : 1;       /**< Append PAD bytes such that min sized */
-        uint64_t preamble                : 1;       /**< Prepend the Ethernet preamble on each transfer */
-#else
-        uint64_t preamble                : 1;
-        uint64_t pad                     : 1;
-        uint64_t fcs                     : 1;
-        uint64_t force_fcs               : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_append_s        cn30xx;
-    struct cvmx_gmxx_txx_append_s        cn31xx;
-    struct cvmx_gmxx_txx_append_s        cn38xx;
-    struct cvmx_gmxx_txx_append_s        cn38xxp2;
-    struct cvmx_gmxx_txx_append_s        cn50xx;
-    struct cvmx_gmxx_txx_append_s        cn52xx;
-    struct cvmx_gmxx_txx_append_s        cn52xxp1;
-    struct cvmx_gmxx_txx_append_s        cn56xx;
-    struct cvmx_gmxx_txx_append_s        cn56xxp1;
-    struct cvmx_gmxx_txx_append_s        cn58xx;
-    struct cvmx_gmxx_txx_append_s        cn58xxp1;
-} cvmx_gmxx_txx_append_t;
-
-
-/**
- * cvmx_gmx#_tx#_burst
- *
- * GMX_TX_BURST = Packet TX Burst Counter
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_burst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t burst                   : 16;      /**< Burst (refer to 802.3 to set correctly)
-                                                         10/100Mbs: 0x0
-                                                         1000Mbs:   0x2000 */
-#else
-        uint64_t burst                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_burst_s         cn30xx;
-    struct cvmx_gmxx_txx_burst_s         cn31xx;
-    struct cvmx_gmxx_txx_burst_s         cn38xx;
-    struct cvmx_gmxx_txx_burst_s         cn38xxp2;
-    struct cvmx_gmxx_txx_burst_s         cn50xx;
-    struct cvmx_gmxx_txx_burst_s         cn52xx;
-    struct cvmx_gmxx_txx_burst_s         cn52xxp1;
-    struct cvmx_gmxx_txx_burst_s         cn56xx;
-    struct cvmx_gmxx_txx_burst_s         cn56xxp1;
-    struct cvmx_gmxx_txx_burst_s         cn58xx;
-    struct cvmx_gmxx_txx_burst_s         cn58xxp1;
-} cvmx_gmxx_txx_burst_t;
-
-
-/**
- * cvmx_gmx#_tx#_cbfc_xoff
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_cbfc_xoff_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t xoff                    : 16;      /**< Which ports to backpressure
-                                                         Do not write in HiGig2 mode i.e. when
-                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                         GMX_RX_UDD_SKP[SKIP]=16. */
-#else
-        uint64_t xoff                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_cbfc_xoff_s     cn52xx;
-    struct cvmx_gmxx_txx_cbfc_xoff_s     cn56xx;
-} cvmx_gmxx_txx_cbfc_xoff_t;
-
-
-/**
- * cvmx_gmx#_tx#_cbfc_xon
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_cbfc_xon_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t xon                     : 16;      /**< Which ports to stop backpressure
-                                                         Do not write in HiGig2 mode i.e. when
-                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                         GMX_RX_UDD_SKP[SKIP]=16. */
-#else
-        uint64_t xon                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_cbfc_xon_s      cn52xx;
-    struct cvmx_gmxx_txx_cbfc_xon_s      cn56xx;
-} cvmx_gmxx_txx_cbfc_xon_t;
-
-
-/**
- * cvmx_gmx#_tx#_clk
- *
- * Per Port
- * 
- * 
- * GMX_TX_CLK = RGMII TX Clock Generation Register
- *
- * Notes:
- * Programming Restrictions:
- *  (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1.
- *  (2) In MII mode, CLK_CNT == 1
- *  (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock.
- * 
- * RGMII Example:
- *  Given a 125MHz PLL reference clock...
- *   CLK_CNT ==  1 ==> 125.0MHz TXC clock period (8ns* 1)
- *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)
- *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_clk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t clk_cnt                 : 6;       /**< Controls the RGMII TXC frequency
-                                                         When PLL is used, TXC(phase) =
-                                                          spi4_tx_pll_ref_clk(period)/2*CLK_CNT
-                                                         When PLL bypass is used, TXC(phase) =
-                                                          spi4_tx_pll_ref_clk(period)*2*CLK_CNT
-                                                         NOTE: CLK_CNT==0 will not generate any clock
-                                                         if CLK_CNT > 1 if GMX_PRT_CFG[SPEED]==0 */
-#else
-        uint64_t clk_cnt                 : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_clk_s           cn30xx;
-    struct cvmx_gmxx_txx_clk_s           cn31xx;
-    struct cvmx_gmxx_txx_clk_s           cn38xx;
-    struct cvmx_gmxx_txx_clk_s           cn38xxp2;
-    struct cvmx_gmxx_txx_clk_s           cn50xx;
-    struct cvmx_gmxx_txx_clk_s           cn58xx;
-    struct cvmx_gmxx_txx_clk_s           cn58xxp1;
-} cvmx_gmxx_txx_clk_t;
-
-
-/**
- * cvmx_gmx#_tx#_ctl
- *
- * GMX_TX_CTL = TX Control register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t xsdef_en                : 1;       /**< Enables the excessive deferral check for stats
-                                                         and interrupts
-                                                         (PASS2 only) */
-        uint64_t xscol_en                : 1;       /**< Enables the excessive collision check for stats
-                                                         and interrupts
-                                                         (PASS2 only) */
-#else
-        uint64_t xscol_en                : 1;
-        uint64_t xsdef_en                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_ctl_s           cn30xx;
-    struct cvmx_gmxx_txx_ctl_s           cn31xx;
-    struct cvmx_gmxx_txx_ctl_s           cn38xx;
-    struct cvmx_gmxx_txx_ctl_s           cn38xxp2;
-    struct cvmx_gmxx_txx_ctl_s           cn50xx;
-    struct cvmx_gmxx_txx_ctl_s           cn52xx;
-    struct cvmx_gmxx_txx_ctl_s           cn52xxp1;
-    struct cvmx_gmxx_txx_ctl_s           cn56xx;
-    struct cvmx_gmxx_txx_ctl_s           cn56xxp1;
-    struct cvmx_gmxx_txx_ctl_s           cn58xx;
-    struct cvmx_gmxx_txx_ctl_s           cn58xxp1;
-} cvmx_gmxx_txx_ctl_t;
-
-
-/**
- * cvmx_gmx#_tx#_min_pkt
- *
- * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_min_pkt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t min_size                : 8;       /**< Min frame in bytes before the FCS is applied
-                                                         Padding is only appened when GMX_TX_APPEND[PAD]
-                                                         for the coresponding RGMII port is set. */
-#else
-        uint64_t min_size                : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_min_pkt_s       cn30xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn31xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn38xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn38xxp2;
-    struct cvmx_gmxx_txx_min_pkt_s       cn50xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn52xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn52xxp1;
-    struct cvmx_gmxx_txx_min_pkt_s       cn56xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn56xxp1;
-    struct cvmx_gmxx_txx_min_pkt_s       cn58xx;
-    struct cvmx_gmxx_txx_min_pkt_s       cn58xxp1;
-} cvmx_gmxx_txx_min_pkt_t;
-
-
-/**
- * cvmx_gmx#_tx#_pause_pkt_interval
- *
- * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent
- *
- *
- * Notes:
- * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
- * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
- * designer.  It is suggested that TIME be much greater than INTERVAL and
- * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
- * count and then when the backpressure condition is lifted, a PAUSE packet
- * with TIME==0 will be sent indicating that Octane is ready for additional
- * data.
- * 
- * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
- * suggested that TIME and INTERVAL are programmed such that they satisify the
- * following rule...
- * 
- *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
- * 
- * where largest_pkt_size is that largest packet that the system can send
- * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
- * of the PAUSE packet (normally 64B).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t interval                : 16;      /**< Arbitrate for a pause packet every (INTERVAL*512)
-                                                         bit-times.
-                                                         Normally, 0 < INTERVAL < GMX_TX_PAUSE_PKT_TIME
-                                                         INTERVAL=0, will only send a single PAUSE packet
-                                                         for each backpressure event */
-#else
-        uint64_t interval                : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
-    struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
-} cvmx_gmxx_txx_pause_pkt_interval_t;
-
-
-/**
- * cvmx_gmx#_tx#_pause_pkt_time
- *
- * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field
- *
- *
- * Notes:
- * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
- * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
- * designer.  It is suggested that TIME be much greater than INTERVAL and
- * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
- * count and then when the backpressure condition is lifted, a PAUSE packet
- * with TIME==0 will be sent indicating that Octane is ready for additional
- * data.
- * 
- * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
- * suggested that TIME and INTERVAL are programmed such that they satisify the
- * following rule...
- * 
- *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
- * 
- * where largest_pkt_size is that largest packet that the system can send
- * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
- * of the PAUSE packet (normally 64B).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_pause_pkt_time_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< The pause_time field placed is outbnd pause pkts
-                                                         pause_time is in 512 bit-times
-                                                         Normally, TIME > GMX_TX_PAUSE_PKT_INTERVAL */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
-    struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
-} cvmx_gmxx_txx_pause_pkt_time_t;
-
-
-/**
- * cvmx_gmx#_tx#_pause_togo
- *
- * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_pause_togo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t msg_time                : 16;      /**< Amount of time remaining to backpressure
-                                                         From the higig2 physical message pause timer
-                                                         (only valid on port0) */
-        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
-#else
-        uint64_t time                    : 16;
-        uint64_t msg_time                : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
-    struct cvmx_gmxx_txx_pause_togo_s    cn52xx;
-    struct cvmx_gmxx_txx_pause_togo_s    cn52xxp1;
-    struct cvmx_gmxx_txx_pause_togo_s    cn56xx;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
-    struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
-} cvmx_gmxx_txx_pause_togo_t;
-
-
-/**
- * cvmx_gmx#_tx#_pause_zero
- *
- * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_pause_zero_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t send                    : 1;       /**< When backpressure condition clear, send PAUSE
-                                                         packet with pause_time of zero to enable the
-                                                         channel */
-#else
-        uint64_t send                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_pause_zero_s    cn30xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn31xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn38xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn38xxp2;
-    struct cvmx_gmxx_txx_pause_zero_s    cn50xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn52xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn52xxp1;
-    struct cvmx_gmxx_txx_pause_zero_s    cn56xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn56xxp1;
-    struct cvmx_gmxx_txx_pause_zero_s    cn58xx;
-    struct cvmx_gmxx_txx_pause_zero_s    cn58xxp1;
-} cvmx_gmxx_txx_pause_zero_t;
-
-
-/**
- * cvmx_gmx#_tx#_sgmii_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_sgmii_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t align                   : 1;       /**< Align the transmission to even cycles
-                                                         0 = Data can be sent on any cycle
-                                                             Possible to for the TX PCS machine to drop
-                                                             first byte of preamble
-                                                         1 = Data will only be sent on even cycles
-                                                             There will be no loss of data
-                                                         (SGMII/1000Base-X only) */
-#else
-        uint64_t align                   : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_sgmii_ctl_s     cn52xx;
-    struct cvmx_gmxx_txx_sgmii_ctl_s     cn52xxp1;
-    struct cvmx_gmxx_txx_sgmii_ctl_s     cn56xx;
-    struct cvmx_gmxx_txx_sgmii_ctl_s     cn56xxp1;
-} cvmx_gmxx_txx_sgmii_ctl_t;
-
-
-/**
- * cvmx_gmx#_tx#_slot
- *
- * GMX_TX_SLOT = Packet TX Slottime Counter
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_slot_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t slot                    : 10;      /**< Slottime (refer to 802.3 to set correctly)
-                                                         10/100Mbs: 0x40
-                                                         1000Mbs:   0x200 */
-#else
-        uint64_t slot                    : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_slot_s          cn30xx;
-    struct cvmx_gmxx_txx_slot_s          cn31xx;
-    struct cvmx_gmxx_txx_slot_s          cn38xx;
-    struct cvmx_gmxx_txx_slot_s          cn38xxp2;
-    struct cvmx_gmxx_txx_slot_s          cn50xx;
-    struct cvmx_gmxx_txx_slot_s          cn52xx;
-    struct cvmx_gmxx_txx_slot_s          cn52xxp1;
-    struct cvmx_gmxx_txx_slot_s          cn56xx;
-    struct cvmx_gmxx_txx_slot_s          cn56xxp1;
-    struct cvmx_gmxx_txx_slot_s          cn58xx;
-    struct cvmx_gmxx_txx_slot_s          cn58xxp1;
-} cvmx_gmxx_txx_slot_t;
-
-
-/**
- * cvmx_gmx#_tx#_soft_pause
- *
- * GMX_TX_SOFT_PAUSE = Packet TX Software Pause
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_soft_pause_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t time                    : 16;      /**< Back off the TX bus for (TIME*512) bit-times */
-#else
-        uint64_t time                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_soft_pause_s    cn30xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn31xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn38xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn38xxp2;
-    struct cvmx_gmxx_txx_soft_pause_s    cn50xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn52xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn52xxp1;
-    struct cvmx_gmxx_txx_soft_pause_s    cn56xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn56xxp1;
-    struct cvmx_gmxx_txx_soft_pause_s    cn58xx;
-    struct cvmx_gmxx_txx_soft_pause_s    cn58xxp1;
-} cvmx_gmxx_txx_soft_pause_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat0
- *
- * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t xsdef                   : 32;      /**< Number of packets dropped (never successfully
-                                                         sent) due to excessive deferal */
-        uint64_t xscol                   : 32;      /**< Number of packets dropped (never successfully
-                                                         sent) due to excessive collision.  Defined by
-                                                         GMX_TX_COL_ATTEMPT[LIMIT]. */
-#else
-        uint64_t xscol                   : 32;
-        uint64_t xsdef                   : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat0_s         cn30xx;
-    struct cvmx_gmxx_txx_stat0_s         cn31xx;
-    struct cvmx_gmxx_txx_stat0_s         cn38xx;
-    struct cvmx_gmxx_txx_stat0_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat0_s         cn50xx;
-    struct cvmx_gmxx_txx_stat0_s         cn52xx;
-    struct cvmx_gmxx_txx_stat0_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat0_s         cn56xx;
-    struct cvmx_gmxx_txx_stat0_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat0_s         cn58xx;
-    struct cvmx_gmxx_txx_stat0_s         cn58xxp1;
-} cvmx_gmxx_txx_stat0_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat1
- *
- * GMX_TX_STAT1 = GMX_TX_STATS_SCOL  / GMX_TX_STATS_MCOL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t scol                    : 32;      /**< Number of packets sent with a single collision */
-        uint64_t mcol                    : 32;      /**< Number of packets sent with multiple collisions
-                                                         but < GMX_TX_COL_ATTEMPT[LIMIT]. */
-#else
-        uint64_t mcol                    : 32;
-        uint64_t scol                    : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat1_s         cn30xx;
-    struct cvmx_gmxx_txx_stat1_s         cn31xx;
-    struct cvmx_gmxx_txx_stat1_s         cn38xx;
-    struct cvmx_gmxx_txx_stat1_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat1_s         cn50xx;
-    struct cvmx_gmxx_txx_stat1_s         cn52xx;
-    struct cvmx_gmxx_txx_stat1_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat1_s         cn56xx;
-    struct cvmx_gmxx_txx_stat1_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat1_s         cn58xx;
-    struct cvmx_gmxx_txx_stat1_s         cn58xxp1;
-} cvmx_gmxx_txx_stat1_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat2
- *
- * GMX_TX_STAT2 = GMX_TX_STATS_OCTS
- *
- *
- * Notes:
- * - Octect counts are the sum of all data transmitted on the wire including
- *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
- *   counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t octs                    : 48;      /**< Number of total octets sent on the interface.
-                                                         Does not count octets from frames that were
-                                                         truncated due to collisions in halfdup mode. */
-#else
-        uint64_t octs                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat2_s         cn30xx;
-    struct cvmx_gmxx_txx_stat2_s         cn31xx;
-    struct cvmx_gmxx_txx_stat2_s         cn38xx;
-    struct cvmx_gmxx_txx_stat2_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat2_s         cn50xx;
-    struct cvmx_gmxx_txx_stat2_s         cn52xx;
-    struct cvmx_gmxx_txx_stat2_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat2_s         cn56xx;
-    struct cvmx_gmxx_txx_stat2_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat2_s         cn58xx;
-    struct cvmx_gmxx_txx_stat2_s         cn58xxp1;
-} cvmx_gmxx_txx_stat2_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat3
- *
- * GMX_TX_STAT3 = GMX_TX_STATS_PKTS
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pkts                    : 32;      /**< Number of total frames sent on the interface.
-                                                         Does not count frames that were truncated due to
-                                                          collisions in halfdup mode. */
-#else
-        uint64_t pkts                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat3_s         cn30xx;
-    struct cvmx_gmxx_txx_stat3_s         cn31xx;
-    struct cvmx_gmxx_txx_stat3_s         cn38xx;
-    struct cvmx_gmxx_txx_stat3_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat3_s         cn50xx;
-    struct cvmx_gmxx_txx_stat3_s         cn52xx;
-    struct cvmx_gmxx_txx_stat3_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat3_s         cn56xx;
-    struct cvmx_gmxx_txx_stat3_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat3_s         cn58xx;
-    struct cvmx_gmxx_txx_stat3_s         cn58xxp1;
-} cvmx_gmxx_txx_stat3_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat4
- *
- * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist1                   : 32;      /**< Number of packets sent with an octet count of 64. */
-        uint64_t hist0                   : 32;      /**< Number of packets sent with an octet count
-                                                         of < 64. */
-#else
-        uint64_t hist0                   : 32;
-        uint64_t hist1                   : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat4_s         cn30xx;
-    struct cvmx_gmxx_txx_stat4_s         cn31xx;
-    struct cvmx_gmxx_txx_stat4_s         cn38xx;
-    struct cvmx_gmxx_txx_stat4_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat4_s         cn50xx;
-    struct cvmx_gmxx_txx_stat4_s         cn52xx;
-    struct cvmx_gmxx_txx_stat4_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat4_s         cn56xx;
-    struct cvmx_gmxx_txx_stat4_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat4_s         cn58xx;
-    struct cvmx_gmxx_txx_stat4_s         cn58xxp1;
-} cvmx_gmxx_txx_stat4_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat5
- *
- * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist3                   : 32;      /**< Number of packets sent with an octet count of
-                                                         128 - 255. */
-        uint64_t hist2                   : 32;      /**< Number of packets sent with an octet count of
-                                                         65 - 127. */
-#else
-        uint64_t hist2                   : 32;
-        uint64_t hist3                   : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat5_s         cn30xx;
-    struct cvmx_gmxx_txx_stat5_s         cn31xx;
-    struct cvmx_gmxx_txx_stat5_s         cn38xx;
-    struct cvmx_gmxx_txx_stat5_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat5_s         cn50xx;
-    struct cvmx_gmxx_txx_stat5_s         cn52xx;
-    struct cvmx_gmxx_txx_stat5_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat5_s         cn56xx;
-    struct cvmx_gmxx_txx_stat5_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat5_s         cn58xx;
-    struct cvmx_gmxx_txx_stat5_s         cn58xxp1;
-} cvmx_gmxx_txx_stat5_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat6
- *
- * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist5                   : 32;      /**< Number of packets sent with an octet count of
-                                                         512 - 1023. */
-        uint64_t hist4                   : 32;      /**< Number of packets sent with an octet count of
-                                                         256 - 511. */
-#else
-        uint64_t hist4                   : 32;
-        uint64_t hist5                   : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat6_s         cn30xx;
-    struct cvmx_gmxx_txx_stat6_s         cn31xx;
-    struct cvmx_gmxx_txx_stat6_s         cn38xx;
-    struct cvmx_gmxx_txx_stat6_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat6_s         cn50xx;
-    struct cvmx_gmxx_txx_stat6_s         cn52xx;
-    struct cvmx_gmxx_txx_stat6_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat6_s         cn56xx;
-    struct cvmx_gmxx_txx_stat6_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat6_s         cn58xx;
-    struct cvmx_gmxx_txx_stat6_s         cn58xxp1;
-} cvmx_gmxx_txx_stat6_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat7
- *
- * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518)
- *
- *
- * Notes:
- * - Packet length is the sum of all data transmitted on the wire for the given
- *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
- *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t hist7                   : 32;      /**< Number of packets sent with an octet count
-                                                         of > 1518. */
-        uint64_t hist6                   : 32;      /**< Number of packets sent with an octet count of
-                                                         1024 - 1518. */
-#else
-        uint64_t hist6                   : 32;
-        uint64_t hist7                   : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat7_s         cn30xx;
-    struct cvmx_gmxx_txx_stat7_s         cn31xx;
-    struct cvmx_gmxx_txx_stat7_s         cn38xx;
-    struct cvmx_gmxx_txx_stat7_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat7_s         cn50xx;
-    struct cvmx_gmxx_txx_stat7_s         cn52xx;
-    struct cvmx_gmxx_txx_stat7_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat7_s         cn56xx;
-    struct cvmx_gmxx_txx_stat7_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat7_s         cn58xx;
-    struct cvmx_gmxx_txx_stat7_s         cn58xxp1;
-} cvmx_gmxx_txx_stat7_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat8
- *
- * GMX_TX_STAT8 = GMX_TX_STATS_MCST  / GMX_TX_STATS_BCST
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
- *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
- *   as per the 802.3 frame definition.  If the system requires additional data
- *   before the L2 header, then the MCST and BCST counters may not reflect
- *   reality and should be ignored by software.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat8_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mcst                    : 32;      /**< Number of packets sent to multicast DMAC.
-                                                         Does not include BCST packets. */
-        uint64_t bcst                    : 32;      /**< Number of packets sent to broadcast DMAC.
-                                                         Does not include MCST packets. */
-#else
-        uint64_t bcst                    : 32;
-        uint64_t mcst                    : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat8_s         cn30xx;
-    struct cvmx_gmxx_txx_stat8_s         cn31xx;
-    struct cvmx_gmxx_txx_stat8_s         cn38xx;
-    struct cvmx_gmxx_txx_stat8_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat8_s         cn50xx;
-    struct cvmx_gmxx_txx_stat8_s         cn52xx;
-    struct cvmx_gmxx_txx_stat8_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat8_s         cn56xx;
-    struct cvmx_gmxx_txx_stat8_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat8_s         cn58xx;
-    struct cvmx_gmxx_txx_stat8_s         cn58xxp1;
-} cvmx_gmxx_txx_stat8_t;
-
-
-/**
- * cvmx_gmx#_tx#_stat9
- *
- * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL
- *
- *
- * Notes:
- * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
- * - Counters will wrap
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stat9_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t undflw                  : 32;      /**< Number of underflow packets */
-        uint64_t ctl                     : 32;      /**< Number of Control packets (PAUSE flow control)
-                                                         generated by GMX.  It does not include control
-                                                         packets forwarded or generated by the PP's. */
-#else
-        uint64_t ctl                     : 32;
-        uint64_t undflw                  : 32;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stat9_s         cn30xx;
-    struct cvmx_gmxx_txx_stat9_s         cn31xx;
-    struct cvmx_gmxx_txx_stat9_s         cn38xx;
-    struct cvmx_gmxx_txx_stat9_s         cn38xxp2;
-    struct cvmx_gmxx_txx_stat9_s         cn50xx;
-    struct cvmx_gmxx_txx_stat9_s         cn52xx;
-    struct cvmx_gmxx_txx_stat9_s         cn52xxp1;
-    struct cvmx_gmxx_txx_stat9_s         cn56xx;
-    struct cvmx_gmxx_txx_stat9_s         cn56xxp1;
-    struct cvmx_gmxx_txx_stat9_s         cn58xx;
-    struct cvmx_gmxx_txx_stat9_s         cn58xxp1;
-} cvmx_gmxx_txx_stat9_t;
-
-
-/**
- * cvmx_gmx#_tx#_stats_ctl
- *
- * GMX_TX_STATS_CTL = TX Stats Control register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_stats_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rd_clr                  : 1;       /**< Stats registers will clear on reads */
-#else
-        uint64_t rd_clr                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn30xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn31xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn38xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn38xxp2;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn50xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn52xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn52xxp1;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn56xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn56xxp1;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn58xx;
-    struct cvmx_gmxx_txx_stats_ctl_s     cn58xxp1;
-} cvmx_gmxx_txx_stats_ctl_t;
-
-
-/**
- * cvmx_gmx#_tx#_thresh
- *
- * Per Port
- * 
- * 
- * GMX_TX_THRESH = Packet TX Threshold
- *
- * Notes:
- * In XAUI mode, prt0 is used for checking.  Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x80.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_txx_thresh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t cnt                     : 9;       /**< Number of 16B ticks to accumulate in the TX FIFO
-                                                         before sending on the RGMII interface
-                                                         This register should be large enough to prevent
-                                                         underflow on the RGMII interface and must never
-                                                         be set to zero.  This register cannot exceed the
-                                                         the TX FIFO depth which is...
-                                                          GMX_TX_PRTS==0,1:  CNT MAX = 0x100
-                                                          GMX_TX_PRTS==2  :  CNT MAX = 0x080
-                                                          GMX_TX_PRTS==3,4:  CNT MAX = 0x040 */
-#else
-        uint64_t cnt                     : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_gmxx_txx_thresh_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t cnt                     : 7;       /**< Number of 16B ticks to accumulate in the TX FIFO
-                                                         before sending on the RGMII interface
-                                                         This register should be large enough to prevent
-                                                         underflow on the RGMII interface and must never
-                                                         be set below 4.  This register cannot exceed the
-                                                         the TX FIFO depth which is 64 16B entries. */
-#else
-        uint64_t cnt                     : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_txx_thresh_cn30xx   cn31xx;
-    struct cvmx_gmxx_txx_thresh_s        cn38xx;
-    struct cvmx_gmxx_txx_thresh_s        cn38xxp2;
-    struct cvmx_gmxx_txx_thresh_cn30xx   cn50xx;
-    struct cvmx_gmxx_txx_thresh_s        cn52xx;
-    struct cvmx_gmxx_txx_thresh_s        cn52xxp1;
-    struct cvmx_gmxx_txx_thresh_s        cn56xx;
-    struct cvmx_gmxx_txx_thresh_s        cn56xxp1;
-    struct cvmx_gmxx_txx_thresh_s        cn58xx;
-    struct cvmx_gmxx_txx_thresh_s        cn58xxp1;
-} cvmx_gmxx_txx_thresh_t;
-
-
-/**
- * cvmx_gmx#_tx_bp
- *
- * GMX_TX_BP = Packet Interface TX BackPressure Register
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of BP is used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t bp                      : 4;       /**< Per port BackPressure status
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-#else
-        uint64_t bp                      : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_bp_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t bp                      : 3;       /**< Per port BackPressure status
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-#else
-        uint64_t bp                      : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_tx_bp_cn30xx        cn31xx;
-    struct cvmx_gmxx_tx_bp_s             cn38xx;
-    struct cvmx_gmxx_tx_bp_s             cn38xxp2;
-    struct cvmx_gmxx_tx_bp_cn30xx        cn50xx;
-    struct cvmx_gmxx_tx_bp_s             cn52xx;
-    struct cvmx_gmxx_tx_bp_s             cn52xxp1;
-    struct cvmx_gmxx_tx_bp_s             cn56xx;
-    struct cvmx_gmxx_tx_bp_s             cn56xxp1;
-    struct cvmx_gmxx_tx_bp_s             cn58xx;
-    struct cvmx_gmxx_tx_bp_s             cn58xxp1;
-} cvmx_gmxx_tx_bp_t;
-
-
-/**
- * cvmx_gmx#_tx_clk_msk#
- *
- * GMX_TX_CLK_MSK = GMX Clock Select
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_clk_mskx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t msk                     : 1;       /**< Write this bit to a 1 when switching clks */
-#else
-        uint64_t msk                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_clk_mskx_s       cn30xx;
-    struct cvmx_gmxx_tx_clk_mskx_s       cn50xx;
-} cvmx_gmxx_tx_clk_mskx_t;
-
-
-/**
- * cvmx_gmx#_tx_col_attempt
- *
- * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_col_attempt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t limit                   : 5;       /**< Collision Attempts */
-#else
-        uint64_t limit                   : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_col_attempt_s    cn30xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn31xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn38xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn38xxp2;
-    struct cvmx_gmxx_tx_col_attempt_s    cn50xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn52xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn52xxp1;
-    struct cvmx_gmxx_tx_col_attempt_s    cn56xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn56xxp1;
-    struct cvmx_gmxx_tx_col_attempt_s    cn58xx;
-    struct cvmx_gmxx_tx_col_attempt_s    cn58xxp1;
-} cvmx_gmxx_tx_col_attempt_t;
-
-
-/**
- * cvmx_gmx#_tx_corrupt
- *
- * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set
- *
- *
- * Notes:
- * Packets sent from PKO with the ERR wire asserted will be corrupted by
- * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0).
- * 
- * Corruption means that GMX will send a bad FCS value.  If GMX_TX_APPEND[FCS]
- * is clear then no FCS is sent and the GMX cannot corrupt it.  The corrupt FCS
- * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
- * propagation code in XAUI mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_corrupt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t corrupt                 : 4;       /**< Per port error propagation
-                                                         0=Never corrupt packets
-                                                         1=Corrupt packets with ERR */
-#else
-        uint64_t corrupt                 : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_corrupt_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t corrupt                 : 3;       /**< Per port error propagation
-                                                         0=Never corrupt packets
-                                                         1=Corrupt packets with ERR */
-#else
-        uint64_t corrupt                 : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_tx_corrupt_cn30xx   cn31xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn38xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn38xxp2;
-    struct cvmx_gmxx_tx_corrupt_cn30xx   cn50xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn52xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn52xxp1;
-    struct cvmx_gmxx_tx_corrupt_s        cn56xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn56xxp1;
-    struct cvmx_gmxx_tx_corrupt_s        cn58xx;
-    struct cvmx_gmxx_tx_corrupt_s        cn58xxp1;
-} cvmx_gmxx_tx_corrupt_t;
-
-
-/**
- * cvmx_gmx#_tx_hg2_reg1
- *
- * Notes:
- * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
- * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of
- * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
- * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
- * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_hg2_reg1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t tx_xof                  : 16;      /**< TX HiGig2 message for logical link pause when any
-                                                         bit value changes
-                                                          Only write in HiGig2 mode i.e. when
-                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                          GMX_RX_UDD_SKP[SKIP]=16. */
-#else
-        uint64_t tx_xof                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_hg2_reg1_s       cn52xx;
-    struct cvmx_gmxx_tx_hg2_reg1_s       cn52xxp1;
-    struct cvmx_gmxx_tx_hg2_reg1_s       cn56xx;
-} cvmx_gmxx_tx_hg2_reg1_t;
-
-
-/**
- * cvmx_gmx#_tx_hg2_reg2
- *
- * Notes:
- * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
- * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address  of
- * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
- * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
- * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_hg2_reg2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t tx_xon                  : 16;      /**< TX HiGig2 message for logical link pause when any
-                                                         bit value changes
-                                                          Only write in HiGig2 mode i.e. when
-                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
-                                                          GMX_RX_UDD_SKP[SKIP]=16. */
-#else
-        uint64_t tx_xon                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_hg2_reg2_s       cn52xx;
-    struct cvmx_gmxx_tx_hg2_reg2_s       cn52xxp1;
-    struct cvmx_gmxx_tx_hg2_reg2_s       cn56xx;
-} cvmx_gmxx_tx_hg2_reg2_t;
-
-
-/**
- * cvmx_gmx#_tx_ifg
- *
- * GMX_TX_IFG = Packet TX Interframe Gap
- *
- *
- * Notes:
- * * Programming IFG1 and IFG2.
- * 
- * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3
- * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range
- * of 4-12, and the IFG1+IFG2 sum must be 12.
- * 
- * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3
- * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range
- * of 1-11, and the IFG1+IFG2 sum must be 12.
- * 
- * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the
- * IFG1+IFG2 sum must be 12.  IFG1[1:0] and IFG2[1:0] must be zero.
- * 
- * For all other systems, IFG1 and IFG2 can be any value in the range of
- * 1-15.  Allowing for a total possible IFG sum of 2-30.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_ifg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ifg2                    : 4;       /**< 1/3 of the interframe gap timing (in IFG2*8 bits)
-                                                         If CRS is detected during IFG2, then the
-                                                         interFrameSpacing timer is not reset and a frame
-                                                         is transmited once the timer expires. */
-        uint64_t ifg1                    : 4;       /**< 2/3 of the interframe gap timing (in IFG1*8 bits)
-                                                         If CRS is detected during IFG1, then the
-                                                         interFrameSpacing timer is reset and a frame is
-                                                         not transmited. */
-#else
-        uint64_t ifg1                    : 4;
-        uint64_t ifg2                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_ifg_s            cn30xx;
-    struct cvmx_gmxx_tx_ifg_s            cn31xx;
-    struct cvmx_gmxx_tx_ifg_s            cn38xx;
-    struct cvmx_gmxx_tx_ifg_s            cn38xxp2;
-    struct cvmx_gmxx_tx_ifg_s            cn50xx;
-    struct cvmx_gmxx_tx_ifg_s            cn52xx;
-    struct cvmx_gmxx_tx_ifg_s            cn52xxp1;
-    struct cvmx_gmxx_tx_ifg_s            cn56xx;
-    struct cvmx_gmxx_tx_ifg_s            cn56xxp1;
-    struct cvmx_gmxx_tx_ifg_s            cn58xx;
-    struct cvmx_gmxx_tx_ifg_s            cn58xxp1;
-} cvmx_gmxx_tx_ifg_t;
-
-
-/**
- * cvmx_gmx#_tx_int_en
- *
- * GMX_TX_INT_EN = Interrupt Enable
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t late_col                : 4;       /**< TX Late Collision
-                                                         (PASS3 only) */
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
-        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t ncb_nxa                 : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t late_col                : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_int_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t late_col                : 3;       /**< TX Late Collision */
-        uint64_t reserved_15_15          : 1;
-        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
-        uint64_t reserved_11_11          : 1;
-        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 3;
-        uint64_t reserved_5_7            : 3;
-        uint64_t xscol                   : 3;
-        uint64_t reserved_11_11          : 1;
-        uint64_t xsdef                   : 3;
-        uint64_t reserved_15_15          : 1;
-        uint64_t late_col                : 3;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_tx_int_en_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
-        uint64_t reserved_11_11          : 1;
-        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 3;
-        uint64_t reserved_5_7            : 3;
-        uint64_t xscol                   : 3;
-        uint64_t reserved_11_11          : 1;
-        uint64_t xsdef                   : 3;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } cn31xx;
-    struct cvmx_gmxx_tx_int_en_s         cn38xx;
-    struct cvmx_gmxx_tx_int_en_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
-        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t ncb_nxa                 : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xxp2;
-    struct cvmx_gmxx_tx_int_en_cn30xx    cn50xx;
-    struct cvmx_gmxx_tx_int_en_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t late_col                : 4;       /**< TX Late Collision
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t late_col                : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_tx_int_en_cn52xx    cn52xxp1;
-    struct cvmx_gmxx_tx_int_en_cn52xx    cn56xx;
-    struct cvmx_gmxx_tx_int_en_cn52xx    cn56xxp1;
-    struct cvmx_gmxx_tx_int_en_s         cn58xx;
-    struct cvmx_gmxx_tx_int_en_s         cn58xxp1;
-} cvmx_gmxx_tx_int_en_t;
-
-
-/**
- * cvmx_gmx#_tx_int_reg
- *
- * GMX_TX_INT_REG = Interrupt Register
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t late_col                : 4;       /**< TX Late Collision
-                                                         (PASS3 only) */
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
-        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t ncb_nxa                 : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t late_col                : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_int_reg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t late_col                : 3;       /**< TX Late Collision */
-        uint64_t reserved_15_15          : 1;
-        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
-        uint64_t reserved_11_11          : 1;
-        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 3;
-        uint64_t reserved_5_7            : 3;
-        uint64_t xscol                   : 3;
-        uint64_t reserved_11_11          : 1;
-        uint64_t xsdef                   : 3;
-        uint64_t reserved_15_15          : 1;
-        uint64_t late_col                : 3;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_tx_int_reg_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
-        uint64_t reserved_11_11          : 1;
-        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
-        uint64_t reserved_5_7            : 3;
-        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 3;
-        uint64_t reserved_5_7            : 3;
-        uint64_t xscol                   : 3;
-        uint64_t reserved_11_11          : 1;
-        uint64_t xsdef                   : 3;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } cn31xx;
-    struct cvmx_gmxx_tx_int_reg_s        cn38xx;
-    struct cvmx_gmxx_tx_int_reg_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
-                                                         (PASS2 only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
-        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t ncb_nxa                 : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xxp2;
-    struct cvmx_gmxx_tx_int_reg_cn30xx   cn50xx;
-    struct cvmx_gmxx_tx_int_reg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t late_col                : 4;       /**< TX Late Collision
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t xsdef                   : 4;       /**< TX Excessive deferral
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t xscol                   : 4;       /**< TX Excessive collisions
-                                                         (SGMII/1000Base-X half-duplex only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t undflw                  : 4;       /**< TX Underflow */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
-#else
-        uint64_t pko_nxa                 : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t undflw                  : 4;
-        uint64_t reserved_6_7            : 2;
-        uint64_t xscol                   : 4;
-        uint64_t xsdef                   : 4;
-        uint64_t late_col                : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_gmxx_tx_int_reg_cn52xx   cn52xxp1;
-    struct cvmx_gmxx_tx_int_reg_cn52xx   cn56xx;
-    struct cvmx_gmxx_tx_int_reg_cn52xx   cn56xxp1;
-    struct cvmx_gmxx_tx_int_reg_s        cn58xx;
-    struct cvmx_gmxx_tx_int_reg_s        cn58xxp1;
-} cvmx_gmxx_tx_int_reg_t;
-
-
-/**
- * cvmx_gmx#_tx_jam
- *
- * GMX_TX_JAM = Packet TX Jam Pattern
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_jam_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t jam                     : 8;       /**< Jam pattern */
-#else
-        uint64_t jam                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_jam_s            cn30xx;
-    struct cvmx_gmxx_tx_jam_s            cn31xx;
-    struct cvmx_gmxx_tx_jam_s            cn38xx;
-    struct cvmx_gmxx_tx_jam_s            cn38xxp2;
-    struct cvmx_gmxx_tx_jam_s            cn50xx;
-    struct cvmx_gmxx_tx_jam_s            cn52xx;
-    struct cvmx_gmxx_tx_jam_s            cn52xxp1;
-    struct cvmx_gmxx_tx_jam_s            cn56xx;
-    struct cvmx_gmxx_tx_jam_s            cn56xxp1;
-    struct cvmx_gmxx_tx_jam_s            cn58xx;
-    struct cvmx_gmxx_tx_jam_s            cn58xxp1;
-} cvmx_gmxx_tx_jam_t;
-
-
-/**
- * cvmx_gmx#_tx_lfsr
- *
- * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_lfsr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t lfsr                    : 16;      /**< The current state of the LFSR used to feed random
-                                                         numbers to compute truncated binary exponential
-                                                         backoff. */
-#else
-        uint64_t lfsr                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_lfsr_s           cn30xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn31xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn38xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn38xxp2;
-    struct cvmx_gmxx_tx_lfsr_s           cn50xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn52xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn52xxp1;
-    struct cvmx_gmxx_tx_lfsr_s           cn56xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn56xxp1;
-    struct cvmx_gmxx_tx_lfsr_s           cn58xx;
-    struct cvmx_gmxx_tx_lfsr_s           cn58xxp1;
-} cvmx_gmxx_tx_lfsr_t;
-
-
-/**
- * cvmx_gmx#_tx_ovr_bp
- *
- * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure
- *
- *
- * Notes:
- * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used.
- * 
- * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
- * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol
- * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by
- * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure
- * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
- * protocol.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_ovr_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t tx_prt_bp               : 16;      /**< Per port BP sent to PKO
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t reserved_12_31          : 20;
-        uint64_t en                      : 4;       /**< Per port Enable back pressure override */
-        uint64_t bp                      : 4;       /**< Per port BackPressure status to use
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t ign_full                : 4;       /**< Ignore the RX FIFO full when computing BP */
-#else
-        uint64_t ign_full                : 4;
-        uint64_t bp                      : 4;
-        uint64_t en                      : 4;
-        uint64_t reserved_12_31          : 20;
-        uint64_t tx_prt_bp               : 16;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_ovr_bp_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t en                      : 3;       /**< Per port Enable back pressure override */
-        uint64_t reserved_7_7            : 1;
-        uint64_t bp                      : 3;       /**< Per port BackPressure status to use
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t reserved_3_3            : 1;
-        uint64_t ign_full                : 3;       /**< Ignore the RX FIFO full when computing BP */
-#else
-        uint64_t ign_full                : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t bp                      : 3;
-        uint64_t reserved_7_7            : 1;
-        uint64_t en                      : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn30xx;
-    struct cvmx_gmxx_tx_ovr_bp_cn30xx    cn31xx;
-    struct cvmx_gmxx_tx_ovr_bp_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t en                      : 4;       /**< Per port Enable back pressure override */
-        uint64_t bp                      : 4;       /**< Per port BackPressure status to use
-                                                         0=Port is available
-                                                         1=Port should be back pressured */
-        uint64_t ign_full                : 4;       /**< Ignore the RX FIFO full when computing BP */
-#else
-        uint64_t ign_full                : 4;
-        uint64_t bp                      : 4;
-        uint64_t en                      : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn38xx;
-    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn38xxp2;
-    struct cvmx_gmxx_tx_ovr_bp_cn30xx    cn50xx;
-    struct cvmx_gmxx_tx_ovr_bp_s         cn52xx;
-    struct cvmx_gmxx_tx_ovr_bp_s         cn52xxp1;
-    struct cvmx_gmxx_tx_ovr_bp_s         cn56xx;
-    struct cvmx_gmxx_tx_ovr_bp_s         cn56xxp1;
-    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn58xx;
-    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn58xxp1;
-} cvmx_gmxx_tx_ovr_bp_t;
-
-
-/**
- * cvmx_gmx#_tx_pause_pkt_dmac
- *
- * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t dmac                    : 48;      /**< The DMAC field placed is outbnd pause pkts */
-#else
-        uint64_t dmac                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
-    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
-} cvmx_gmxx_tx_pause_pkt_dmac_t;
-
-
-/**
- * cvmx_gmx#_tx_pause_pkt_type
- *
- * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_pause_pkt_type_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t type                    : 16;      /**< The TYPE field placed is outbnd pause pkts */
-#else
-        uint64_t type                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
-    struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
-} cvmx_gmxx_tx_pause_pkt_type_t;
-
-
-/**
- * cvmx_gmx#_tx_prts
- *
- * Common
- * 
- * 
- * GMX_TX_PRTS = TX Ports
- *
- * Notes:
- * * The value programmed for PRTS is the number of the highest architected
- * port number on the interface, plus 1.  For example, if port 2 is the
- * highest architected port, then the programmed value should be 3 since
- * there are 3 ports in the system - 0, 1, and 2.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_prts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t prts                    : 5;       /**< Number of ports allowed on the interface */
-#else
-        uint64_t prts                    : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_prts_s           cn30xx;
-    struct cvmx_gmxx_tx_prts_s           cn31xx;
-    struct cvmx_gmxx_tx_prts_s           cn38xx;
-    struct cvmx_gmxx_tx_prts_s           cn38xxp2;
-    struct cvmx_gmxx_tx_prts_s           cn50xx;
-    struct cvmx_gmxx_tx_prts_s           cn52xx;
-    struct cvmx_gmxx_tx_prts_s           cn52xxp1;
-    struct cvmx_gmxx_tx_prts_s           cn56xx;
-    struct cvmx_gmxx_tx_prts_s           cn56xxp1;
-    struct cvmx_gmxx_tx_prts_s           cn58xx;
-    struct cvmx_gmxx_tx_prts_s           cn58xxp1;
-} cvmx_gmxx_tx_prts_t;
-
-
-/**
- * cvmx_gmx#_tx_spi_ctl
- *
- * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_spi_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t tpa_clr                 : 1;       /**< TPA Clear Mode
-                                                         Clear credit counter when satisifed status */
-        uint64_t cont_pkt                : 1;       /**< Contiguous Packet Mode
-                                                         Finish one packet before switching to another
-                                                         Cannot be set in Spi4 pass-through mode */
-#else
-        uint64_t cont_pkt                : 1;
-        uint64_t tpa_clr                 : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_spi_ctl_s        cn38xx;
-    struct cvmx_gmxx_tx_spi_ctl_s        cn38xxp2;
-    struct cvmx_gmxx_tx_spi_ctl_s        cn58xx;
-    struct cvmx_gmxx_tx_spi_ctl_s        cn58xxp1;
-} cvmx_gmxx_tx_spi_ctl_t;
-
-
-/**
- * cvmx_gmx#_tx_spi_drain
- *
- * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_spi_drain_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t drain                   : 16;      /**< Per port drain control
-                                                         0=Normal operation
-                                                         1=GMX TX will be popped, but no valid data will
-                                                           be sent to SPX.  Credits are correctly returned
-                                                           to PKO.  STX_IGN_CAL should be set to ignore
-                                                           TPA and not stall due to back-pressure.
-                                                         (PASS3 only) */
-#else
-        uint64_t drain                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_spi_drain_s      cn38xx;
-    struct cvmx_gmxx_tx_spi_drain_s      cn58xx;
-    struct cvmx_gmxx_tx_spi_drain_s      cn58xxp1;
-} cvmx_gmxx_tx_spi_drain_t;
-
-
-/**
- * cvmx_gmx#_tx_spi_max
- *
- * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_spi_max_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t slice                   : 7;       /**< Number of 16B blocks to transmit in a burst before
-                                                         switching to the next port. SLICE does not always
-                                                         limit the burst length transmitted by OCTEON.
-                                                         Depending on the traffic pattern and
-                                                         GMX_TX_SPI_ROUND programming, the next port could
-                                                         be the same as the current port. In this case,
-                                                         OCTEON may merge multiple sub-SLICE bursts into
-                                                         one contiguous burst that is longer than SLICE
-                                                         (as long as the burst does not cross a packet
-                                                         boundary).
-                                                         SLICE must be programmed to be >=
-                                                           GMX_TX_SPI_THRESH[THRESH]
-                                                         If SLICE==0, then the transmitter will tend to
-                                                         send the complete packet. The port will only
-                                                         switch if credits are exhausted or PKO cannot
-                                                         keep up.
-                                                         (90nm ONLY) */
-        uint64_t max2                    : 8;       /**< MAX2 (per Spi4.2 spec) */
-        uint64_t max1                    : 8;       /**< MAX1 (per Spi4.2 spec)
-                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
-#else
-        uint64_t max1                    : 8;
-        uint64_t max2                    : 8;
-        uint64_t slice                   : 7;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_spi_max_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t max2                    : 8;       /**< MAX2 (per Spi4.2 spec) */
-        uint64_t max1                    : 8;       /**< MAX1 (per Spi4.2 spec)
-                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
-#else
-        uint64_t max1                    : 8;
-        uint64_t max2                    : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_gmxx_tx_spi_max_cn38xx   cn38xxp2;
-    struct cvmx_gmxx_tx_spi_max_s        cn58xx;
-    struct cvmx_gmxx_tx_spi_max_s        cn58xxp1;
-} cvmx_gmxx_tx_spi_max_t;
-
-
-/**
- * cvmx_gmx#_tx_spi_round#
- *
- * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_spi_roundx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t round                   : 16;      /**< Which Spi ports participate in each arbitration
-                                                          round.  Each bit corresponds to a spi port
-                                                         - 0: this port will arb in this round
-                                                         - 1: this port will not arb in this round
-                                                          (90nm ONLY) */
-#else
-        uint64_t round                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_spi_roundx_s     cn58xx;
-    struct cvmx_gmxx_tx_spi_roundx_s     cn58xxp1;
-} cvmx_gmxx_tx_spi_roundx_t;
-
-
-/**
- * cvmx_gmx#_tx_spi_thresh
- *
- * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold
- *
- *
- * Notes:
- * Note: zero will map to 0x20
- * 
- * This will normally creates Spi4 traffic bursts at least THRESH in length.
- * If dclk > eclk, then this rule may not always hold and Octeon may split
- * transfers into smaller bursts - some of which could be as short as 16B.
- * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
- * not a multiple of 16B.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_spi_thresh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t thresh                  : 6;       /**< Transmit threshold in 16B blocks - cannot be zero
-                                                         THRESH <= TX_FIFO size   (in non-passthrough mode)
-                                                         THRESH <= TX_FIFO size-2 (in passthrough mode)
-                                                         THRESH <= GMX_TX_SPI_MAX[MAX1]
-                                                         THRESH <= GMX_TX_SPI_MAX[MAX2], if not then is it
-                                                          possible for Octeon to send a Spi4 data burst of
-                                                          MAX2 <= burst <= THRESH 16B ticks
-                                                         GMX_TX_SPI_MAX[SLICE] must be programmed to be >=
-                                                           THRESH */
-#else
-        uint64_t thresh                  : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_spi_thresh_s     cn38xx;
-    struct cvmx_gmxx_tx_spi_thresh_s     cn38xxp2;
-    struct cvmx_gmxx_tx_spi_thresh_s     cn58xx;
-    struct cvmx_gmxx_tx_spi_thresh_s     cn58xxp1;
-} cvmx_gmxx_tx_spi_thresh_t;
-
-
-/**
- * cvmx_gmx#_tx_xaui_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_tx_xaui_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t hg_pause_hgi            : 2;       /**< HGI Field for HW generated HiGig pause packets
-                                                         (XAUI mode only) */
-        uint64_t hg_en                   : 1;       /**< Enable HiGig Mode
-                                                         When HG_EN is set, the following must be set:
-                                                          GMX_RX_FRM_CTL[PRE_CHK] == 0
-                                                          GMX_RX_UDD_SKP[FCSSEL] == 0
-                                                          GMX_RX_UDD_SKP[SKIP] == 12 or 16
-                                                          GMX_TX_APPEND[PREAMBLE] == 0
-                                                           (depending on the HiGig header size)
-                                                         (XAUI mode only) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t ls_byp                  : 1;       /**< Bypass the link status as determined by the XGMII
-                                                         receiver and set the link status of the
-                                                         transmitter to LS.
-                                                         (XAUI mode only) */
-        uint64_t ls                      : 2;       /**< Link Status
-                                                         0 = Link Ok
-                                                             Link runs normally. RS passes MAC data to PCS
-                                                         1 = Local Fault
-                                                             RS layer sends continuous remote fault
-                                                              sequences.
-                                                         2 = Remote Fault
-                                                             RS layer sends continuous idles sequences
-                                                         (XAUI mode only) */
-        uint64_t reserved_2_3            : 2;
-        uint64_t uni_en                  : 1;       /**< Enable Unidirectional Mode (IEEE Clause 66)
-                                                         (XAUI mode only) */
-        uint64_t dic_en                  : 1;       /**< Enable the deficit idle counter for IFG averaging
-                                                         (XAUI mode only) */
-#else
-        uint64_t dic_en                  : 1;
-        uint64_t uni_en                  : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t ls                      : 2;
-        uint64_t ls_byp                  : 1;
-        uint64_t reserved_7_7            : 1;
-        uint64_t hg_en                   : 1;
-        uint64_t hg_pause_hgi            : 2;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_gmxx_tx_xaui_ctl_s       cn52xx;
-    struct cvmx_gmxx_tx_xaui_ctl_s       cn52xxp1;
-    struct cvmx_gmxx_tx_xaui_ctl_s       cn56xx;
-    struct cvmx_gmxx_tx_xaui_ctl_s       cn56xxp1;
-} cvmx_gmxx_tx_xaui_ctl_t;
-
-
-/**
- * cvmx_gmx#_xaui_ext_loopback
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gmxx_xaui_ext_loopback_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t en                      : 1;       /**< Loopback enable
-                                                         Puts the packet interface in external loopback
-                                                         mode on the XAUI bus in which the RX lines are
-                                                         reflected on the TX lines.
-                                                         (XAUI mode only) */
-        uint64_t thresh                  : 4;       /**< Threshhold on the TX FIFO
-                                                         SW must only write the typical value.  Any other
-                                                         value will cause loopback mode not to function
-                                                         correctly.
-                                                         (XAUI mode only) */
-#else
-        uint64_t thresh                  : 4;
-        uint64_t en                      : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
-    struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
-    struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
-    struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
-} cvmx_gmxx_xaui_ext_loopback_t;
-
-
-/**
- * cvmx_gpio_bit_cfg#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_bit_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t clk_gen                 : 1;       /**< When TX_OE is set, GPIO pin becomes a clock */
-        uint64_t clk_sel                 : 2;       /**< Selects which of the 4 GPIO clock generators */
-        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
-        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
-        uint64_t int_type                : 1;       /**< Type of interrupt
-                                                         0 = level (default)
-                                                         1 = rising edge */
-        uint64_t int_en                  : 1;       /**< Bit mask to indicate which bits to raise interrupt */
-        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
-        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
-#else
-        uint64_t tx_oe                   : 1;
-        uint64_t rx_xor                  : 1;
-        uint64_t int_en                  : 1;
-        uint64_t int_type                : 1;
-        uint64_t fil_cnt                 : 4;
-        uint64_t fil_sel                 : 4;
-        uint64_t clk_sel                 : 2;
-        uint64_t clk_gen                 : 1;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_gpio_bit_cfgx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
-        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
-        uint64_t int_type                : 1;       /**< Type of interrupt
-                                                         0 = level (default)
-                                                         1 = rising edge */
-        uint64_t int_en                  : 1;       /**< Bit mask to indicate which bits to raise interrupt */
-        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
-        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
-#else
-        uint64_t tx_oe                   : 1;
-        uint64_t rx_xor                  : 1;
-        uint64_t int_en                  : 1;
-        uint64_t int_type                : 1;
-        uint64_t fil_cnt                 : 4;
-        uint64_t fil_sel                 : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn30xx;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn31xx;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn38xx;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn38xxp2;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn50xx;
-    struct cvmx_gpio_bit_cfgx_s          cn52xx;
-    struct cvmx_gpio_bit_cfgx_s          cn52xxp1;
-    struct cvmx_gpio_bit_cfgx_s          cn56xx;
-    struct cvmx_gpio_bit_cfgx_s          cn56xxp1;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn58xx;
-    struct cvmx_gpio_bit_cfgx_cn30xx     cn58xxp1;
-} cvmx_gpio_bit_cfgx_t;
-
-
-/**
- * cvmx_gpio_boot_ena
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_boot_ena_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t boot_ena                : 4;       /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t boot_ena                : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_gpio_boot_ena_s          cn30xx;
-    struct cvmx_gpio_boot_ena_s          cn31xx;
-    struct cvmx_gpio_boot_ena_s          cn50xx;
-} cvmx_gpio_boot_ena_t;
-
-
-/**
- * cvmx_gpio_clk_gen#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_clk_genx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t n                       : 32;      /**< Determines the frequency of the GPIO clk generator
-                                                         NOTE: Fgpio_clk = Feclk * N / 2^32
-                                                               N = (Fgpio_clk / Feclk) * 2^32
-                                                         NOTE: writing N == 0 stops the clock generator
-                                                         N  should be <= 2^31-1. */
-#else
-        uint64_t n                       : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_gpio_clk_genx_s          cn52xx;
-    struct cvmx_gpio_clk_genx_s          cn52xxp1;
-    struct cvmx_gpio_clk_genx_s          cn56xx;
-    struct cvmx_gpio_clk_genx_s          cn56xxp1;
-} cvmx_gpio_clk_genx_t;
-
-
-/**
- * cvmx_gpio_dbg_ena
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_dbg_ena_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t dbg_ena                 : 21;      /**< Enable the debug port to be driven on the gpio */
-#else
-        uint64_t dbg_ena                 : 21;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } s;
-    struct cvmx_gpio_dbg_ena_s           cn30xx;
-    struct cvmx_gpio_dbg_ena_s           cn31xx;
-    struct cvmx_gpio_dbg_ena_s           cn50xx;
-} cvmx_gpio_dbg_ena_t;
-
-
-/**
- * cvmx_gpio_int_clr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_int_clr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t type                    : 16;      /**< Clear the interrupt rising edge detector */
-#else
-        uint64_t type                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_gpio_int_clr_s           cn30xx;
-    struct cvmx_gpio_int_clr_s           cn31xx;
-    struct cvmx_gpio_int_clr_s           cn38xx;
-    struct cvmx_gpio_int_clr_s           cn38xxp2;
-    struct cvmx_gpio_int_clr_s           cn50xx;
-    struct cvmx_gpio_int_clr_s           cn52xx;
-    struct cvmx_gpio_int_clr_s           cn52xxp1;
-    struct cvmx_gpio_int_clr_s           cn56xx;
-    struct cvmx_gpio_int_clr_s           cn56xxp1;
-    struct cvmx_gpio_int_clr_s           cn58xx;
-    struct cvmx_gpio_int_clr_s           cn58xxp1;
-} cvmx_gpio_int_clr_t;
-
-
-/**
- * cvmx_gpio_rx_dat
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_rx_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t dat                     : 24;      /**< GPIO Read Data */
-#else
-        uint64_t dat                     : 24;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_gpio_rx_dat_s            cn30xx;
-    struct cvmx_gpio_rx_dat_s            cn31xx;
-    struct cvmx_gpio_rx_dat_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dat                     : 16;      /**< GPIO Read Data */
-#else
-        uint64_t dat                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_gpio_rx_dat_cn38xx       cn38xxp2;
-    struct cvmx_gpio_rx_dat_s            cn50xx;
-    struct cvmx_gpio_rx_dat_cn38xx       cn52xx;
-    struct cvmx_gpio_rx_dat_cn38xx       cn52xxp1;
-    struct cvmx_gpio_rx_dat_cn38xx       cn56xx;
-    struct cvmx_gpio_rx_dat_cn38xx       cn56xxp1;
-    struct cvmx_gpio_rx_dat_cn38xx       cn58xx;
-    struct cvmx_gpio_rx_dat_cn38xx       cn58xxp1;
-} cvmx_gpio_rx_dat_t;
-
-
-/**
- * cvmx_gpio_tx_clr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_tx_clr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t clr                     : 24;      /**< Bit mask to indicate which bits to drive to '0'. */
-#else
-        uint64_t clr                     : 24;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_gpio_tx_clr_s            cn30xx;
-    struct cvmx_gpio_tx_clr_s            cn31xx;
-    struct cvmx_gpio_tx_clr_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t clr                     : 16;      /**< Bit mask to indicate which bits to drive to '0'. */
-#else
-        uint64_t clr                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_gpio_tx_clr_cn38xx       cn38xxp2;
-    struct cvmx_gpio_tx_clr_s            cn50xx;
-    struct cvmx_gpio_tx_clr_cn38xx       cn52xx;
-    struct cvmx_gpio_tx_clr_cn38xx       cn52xxp1;
-    struct cvmx_gpio_tx_clr_cn38xx       cn56xx;
-    struct cvmx_gpio_tx_clr_cn38xx       cn56xxp1;
-    struct cvmx_gpio_tx_clr_cn38xx       cn58xx;
-    struct cvmx_gpio_tx_clr_cn38xx       cn58xxp1;
-} cvmx_gpio_tx_clr_t;
-
-
-/**
- * cvmx_gpio_tx_set
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_tx_set_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t set                     : 24;      /**< Bit mask to indicate which bits to drive to '1'. */
-#else
-        uint64_t set                     : 24;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_gpio_tx_set_s            cn30xx;
-    struct cvmx_gpio_tx_set_s            cn31xx;
-    struct cvmx_gpio_tx_set_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t set                     : 16;      /**< Bit mask to indicate which bits to drive to '1'. */
-#else
-        uint64_t set                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_gpio_tx_set_cn38xx       cn38xxp2;
-    struct cvmx_gpio_tx_set_s            cn50xx;
-    struct cvmx_gpio_tx_set_cn38xx       cn52xx;
-    struct cvmx_gpio_tx_set_cn38xx       cn52xxp1;
-    struct cvmx_gpio_tx_set_cn38xx       cn56xx;
-    struct cvmx_gpio_tx_set_cn38xx       cn56xxp1;
-    struct cvmx_gpio_tx_set_cn38xx       cn58xx;
-    struct cvmx_gpio_tx_set_cn38xx       cn58xxp1;
-} cvmx_gpio_tx_set_t;
-
-
-/**
- * cvmx_gpio_xbit_cfg#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_gpio_xbit_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
-        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
-        uint64_t reserved_2_3            : 2;
-        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
-        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
-#else
-        uint64_t tx_oe                   : 1;
-        uint64_t rx_xor                  : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t fil_cnt                 : 4;
-        uint64_t fil_sel                 : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_gpio_xbit_cfgx_s         cn30xx;
-    struct cvmx_gpio_xbit_cfgx_s         cn31xx;
-    struct cvmx_gpio_xbit_cfgx_s         cn50xx;
-} cvmx_gpio_xbit_cfgx_t;
-
-
-/**
- * cvmx_iob_bist_status
- *
- * IOB_BIST_STATUS = BIST Status of IOB Memories
- * 
- * The result of the BIST run on the IOB memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t icnrcb                  : 1;       /**< icnr_cb_reg_fifo_bist_status */
-        uint64_t icr0                    : 1;       /**< icr_bist_req_fifo0_status */
-        uint64_t icr1                    : 1;       /**< icr_bist_req_fifo1_status */
-        uint64_t icnr1                   : 1;       /**< icnr_reg_mem1_bist_status */
-        uint64_t icnr0                   : 1;       /**< icnr_reg_mem0_bist_status */
-        uint64_t ibdr0                   : 1;       /**< ibdr_bist_req_fifo0_status */
-        uint64_t ibdr1                   : 1;       /**< ibdr_bist_req_fifo1_status */
-        uint64_t ibr0                    : 1;       /**< ibr_bist_rsp_fifo0_status */
-        uint64_t ibr1                    : 1;       /**< ibr_bist_rsp_fifo1_status */
-        uint64_t icnrt                   : 1;       /**< icnr_tag_cb_reg_fifo_bist_status */
-        uint64_t ibrq0                   : 1;       /**< ibrq_bist_req_fifo0_status */
-        uint64_t ibrq1                   : 1;       /**< ibrq_bist_req_fifo1_status */
-        uint64_t icrn0                   : 1;       /**< icr_ncb_bist_mem0_status */
-        uint64_t icrn1                   : 1;       /**< icr_ncb_bist_mem1_status */
-        uint64_t icrp0                   : 1;       /**< icr_pko_bist_mem0_status */
-        uint64_t icrp1                   : 1;       /**< icr_pko_bist_mem1_status */
-        uint64_t ibd                     : 1;       /**< ibd_bist_mem0_status */
-        uint64_t icd                     : 1;       /**< icd_ncb_fifo_bist_status */
-#else
-        uint64_t icd                     : 1;
-        uint64_t ibd                     : 1;
-        uint64_t icrp1                   : 1;
-        uint64_t icrp0                   : 1;
-        uint64_t icrn1                   : 1;
-        uint64_t icrn0                   : 1;
-        uint64_t ibrq1                   : 1;
-        uint64_t ibrq0                   : 1;
-        uint64_t icnrt                   : 1;
-        uint64_t ibr1                    : 1;
-        uint64_t ibr0                    : 1;
-        uint64_t ibdr1                   : 1;
-        uint64_t ibdr0                   : 1;
-        uint64_t icnr0                   : 1;
-        uint64_t icnr1                   : 1;
-        uint64_t icr1                    : 1;
-        uint64_t icr0                    : 1;
-        uint64_t icnrcb                  : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_iob_bist_status_s        cn30xx;
-    struct cvmx_iob_bist_status_s        cn31xx;
-    struct cvmx_iob_bist_status_s        cn38xx;
-    struct cvmx_iob_bist_status_s        cn38xxp2;
-    struct cvmx_iob_bist_status_s        cn50xx;
-    struct cvmx_iob_bist_status_s        cn52xx;
-    struct cvmx_iob_bist_status_s        cn52xxp1;
-    struct cvmx_iob_bist_status_s        cn56xx;
-    struct cvmx_iob_bist_status_s        cn56xxp1;
-    struct cvmx_iob_bist_status_s        cn58xx;
-    struct cvmx_iob_bist_status_s        cn58xxp1;
-} cvmx_iob_bist_status_t;
-
-
-/**
- * cvmx_iob_ctl_status
- *
- * IOB Control Status = IOB Control and Status Register
- * 
- * Provides control for IOB functions.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t rr_mode                 : 1;       /**< When set to '1' will enable Round-Robin mode of next
-                                                         transaction that could arbitrate for the XMB. */
-        uint64_t outb_mat                : 1;       /**< Was a match on the outbound bus to the inb pattern
-                                                         matchers. PASS2 FIELD. */
-        uint64_t inb_mat                 : 1;       /**< Was a match on the inbound bus to the inb pattern
-                                                         matchers. PASS2 FIELD. */
-        uint64_t pko_enb                 : 1;       /**< Toggles the endian style of the FAU for the PKO.
-                                                         '0' is for big-endian and '1' is for little-endian. */
-        uint64_t dwb_enb                 : 1;       /**< Enables the DWB function of the IOB. */
-        uint64_t fau_end                 : 1;       /**< Toggles the endian style of the FAU. '0' is for
-                                                         big-endian and '1' is for little-endian. */
-#else
-        uint64_t fau_end                 : 1;
-        uint64_t dwb_enb                 : 1;
-        uint64_t pko_enb                 : 1;
-        uint64_t inb_mat                 : 1;
-        uint64_t outb_mat                : 1;
-        uint64_t rr_mode                 : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_iob_ctl_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t outb_mat                : 1;       /**< Was a match on the outbound bus to the inb pattern
-                                                         matchers. */
-        uint64_t inb_mat                 : 1;       /**< Was a match on the inbound bus to the inb pattern
-                                                         matchers. */
-        uint64_t pko_enb                 : 1;       /**< Toggles the endian style of the FAU for the PKO.
-                                                         '0' is for big-endian and '1' is for little-endian. */
-        uint64_t dwb_enb                 : 1;       /**< Enables the DWB function of the IOB. */
-        uint64_t fau_end                 : 1;       /**< Toggles the endian style of the FAU. '0' is for
-                                                         big-endian and '1' is for little-endian. */
-#else
-        uint64_t fau_end                 : 1;
-        uint64_t dwb_enb                 : 1;
-        uint64_t pko_enb                 : 1;
-        uint64_t inb_mat                 : 1;
-        uint64_t outb_mat                : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn30xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn31xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn38xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn38xxp2;
-    struct cvmx_iob_ctl_status_cn30xx    cn50xx;
-    struct cvmx_iob_ctl_status_s         cn52xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn52xxp1;
-    struct cvmx_iob_ctl_status_cn30xx    cn56xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn56xxp1;
-    struct cvmx_iob_ctl_status_cn30xx    cn58xx;
-    struct cvmx_iob_ctl_status_cn30xx    cn58xxp1;
-} cvmx_iob_ctl_status_t;
-
-
-/**
- * cvmx_iob_dwb_pri_cnt
- *
- * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_dwb_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to CMB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_dwb_pri_cnt_s        cn38xx;
-    struct cvmx_iob_dwb_pri_cnt_s        cn38xxp2;
-    struct cvmx_iob_dwb_pri_cnt_s        cn52xx;
-    struct cvmx_iob_dwb_pri_cnt_s        cn52xxp1;
-    struct cvmx_iob_dwb_pri_cnt_s        cn56xx;
-    struct cvmx_iob_dwb_pri_cnt_s        cn56xxp1;
-    struct cvmx_iob_dwb_pri_cnt_s        cn58xx;
-    struct cvmx_iob_dwb_pri_cnt_s        cn58xxp1;
-} cvmx_iob_dwb_pri_cnt_t;
-
-
-/**
- * cvmx_iob_fau_timeout
- *
- * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout
- * 
- * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
- * for Queue 0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_fau_timeout_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t tout_enb                : 1;       /**< The enable for the FAU timeout feature.
-                                                         '1' will enable the timeout, '0' will disable. */
-        uint64_t tout_val                : 12;      /**< When a tag request arrives from the PP a timer is
-                                                         started associate with that PP. The timer which
-                                                         increments every 256 eclks is compared to TOUT_VAL.
-                                                         When the two are equal the IOB will flag the tag
-                                                         request to complete as a time-out tag operation.
-                                                         The 256 count timer used to increment the PP
-                                                         associated timer is always running so the first
-                                                         increment of the PP associated timer may occur any
-                                                         where within the first 256 eclks.  Note that '0'
-                                                         is an illegal value. */
-#else
-        uint64_t tout_val                : 12;
-        uint64_t tout_enb                : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_iob_fau_timeout_s        cn30xx;
-    struct cvmx_iob_fau_timeout_s        cn31xx;
-    struct cvmx_iob_fau_timeout_s        cn38xx;
-    struct cvmx_iob_fau_timeout_s        cn38xxp2;
-    struct cvmx_iob_fau_timeout_s        cn50xx;
-    struct cvmx_iob_fau_timeout_s        cn52xx;
-    struct cvmx_iob_fau_timeout_s        cn52xxp1;
-    struct cvmx_iob_fau_timeout_s        cn56xx;
-    struct cvmx_iob_fau_timeout_s        cn56xxp1;
-    struct cvmx_iob_fau_timeout_s        cn58xx;
-    struct cvmx_iob_fau_timeout_s        cn58xxp1;
-} cvmx_iob_fau_timeout_t;
-
-
-/**
- * cvmx_iob_i2c_pri_cnt
- *
- * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_i2c_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to CMB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_i2c_pri_cnt_s        cn38xx;
-    struct cvmx_iob_i2c_pri_cnt_s        cn38xxp2;
-    struct cvmx_iob_i2c_pri_cnt_s        cn52xx;
-    struct cvmx_iob_i2c_pri_cnt_s        cn52xxp1;
-    struct cvmx_iob_i2c_pri_cnt_s        cn56xx;
-    struct cvmx_iob_i2c_pri_cnt_s        cn56xxp1;
-    struct cvmx_iob_i2c_pri_cnt_s        cn58xx;
-    struct cvmx_iob_i2c_pri_cnt_s        cn58xxp1;
-} cvmx_iob_i2c_pri_cnt_t;
-
-
-/**
- * cvmx_iob_inb_control_match
- *
- * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match
- * 
- * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_inb_control_match_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t mask                    : 8;       /**< Pattern to match on the inbound NCB. */
-        uint64_t opc                     : 4;       /**< Pattern to match on the inbound NCB. */
-        uint64_t dst                     : 9;       /**< Pattern to match on the inbound NCB. */
-        uint64_t src                     : 8;       /**< Pattern to match on the inbound NCB. */
-#else
-        uint64_t src                     : 8;
-        uint64_t dst                     : 9;
-        uint64_t opc                     : 4;
-        uint64_t mask                    : 8;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_iob_inb_control_match_s  cn30xx;
-    struct cvmx_iob_inb_control_match_s  cn31xx;
-    struct cvmx_iob_inb_control_match_s  cn38xx;
-    struct cvmx_iob_inb_control_match_s  cn38xxp2;
-    struct cvmx_iob_inb_control_match_s  cn50xx;
-    struct cvmx_iob_inb_control_match_s  cn52xx;
-    struct cvmx_iob_inb_control_match_s  cn52xxp1;
-    struct cvmx_iob_inb_control_match_s  cn56xx;
-    struct cvmx_iob_inb_control_match_s  cn56xxp1;
-    struct cvmx_iob_inb_control_match_s  cn58xx;
-    struct cvmx_iob_inb_control_match_s  cn58xxp1;
-} cvmx_iob_inb_control_match_t;
-
-
-/**
- * cvmx_iob_inb_control_match_enb
- *
- * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable
- * 
- * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_inb_control_match_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t mask                    : 8;       /**< Pattern to match on the inbound NCB. */
-        uint64_t opc                     : 4;       /**< Pattern to match on the inbound NCB. */
-        uint64_t dst                     : 9;       /**< Pattern to match on the inbound NCB. */
-        uint64_t src                     : 8;       /**< Pattern to match on the inbound NCB. */
-#else
-        uint64_t src                     : 8;
-        uint64_t dst                     : 9;
-        uint64_t opc                     : 4;
-        uint64_t mask                    : 8;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_iob_inb_control_match_enb_s cn30xx;
-    struct cvmx_iob_inb_control_match_enb_s cn31xx;
-    struct cvmx_iob_inb_control_match_enb_s cn38xx;
-    struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
-    struct cvmx_iob_inb_control_match_enb_s cn50xx;
-    struct cvmx_iob_inb_control_match_enb_s cn52xx;
-    struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
-    struct cvmx_iob_inb_control_match_enb_s cn56xx;
-    struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
-    struct cvmx_iob_inb_control_match_enb_s cn58xx;
-    struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
-} cvmx_iob_inb_control_match_enb_t;
-
-
-/**
- * cvmx_iob_inb_data_match
- *
- * IOB_INB_DATA_MATCH = IOB Inbound Data Match
- * 
- * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_inb_data_match_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Pattern to match on the inbound NCB. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_iob_inb_data_match_s     cn30xx;
-    struct cvmx_iob_inb_data_match_s     cn31xx;
-    struct cvmx_iob_inb_data_match_s     cn38xx;
-    struct cvmx_iob_inb_data_match_s     cn38xxp2;
-    struct cvmx_iob_inb_data_match_s     cn50xx;
-    struct cvmx_iob_inb_data_match_s     cn52xx;
-    struct cvmx_iob_inb_data_match_s     cn52xxp1;
-    struct cvmx_iob_inb_data_match_s     cn56xx;
-    struct cvmx_iob_inb_data_match_s     cn56xxp1;
-    struct cvmx_iob_inb_data_match_s     cn58xx;
-    struct cvmx_iob_inb_data_match_s     cn58xxp1;
-} cvmx_iob_inb_data_match_t;
-
-
-/**
- * cvmx_iob_inb_data_match_enb
- *
- * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable
- * 
- * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_inb_data_match_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Bit to enable match of. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_iob_inb_data_match_enb_s cn30xx;
-    struct cvmx_iob_inb_data_match_enb_s cn31xx;
-    struct cvmx_iob_inb_data_match_enb_s cn38xx;
-    struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
-    struct cvmx_iob_inb_data_match_enb_s cn50xx;
-    struct cvmx_iob_inb_data_match_enb_s cn52xx;
-    struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
-    struct cvmx_iob_inb_data_match_enb_s cn56xx;
-    struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
-    struct cvmx_iob_inb_data_match_enb_s cn58xx;
-    struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
-} cvmx_iob_inb_data_match_enb_t;
-
-
-/**
- * cvmx_iob_int_enb
- *
- * IOB_INT_ENB = IOB's Interrupt Enable
- * 
- * The IOB's interrupt enable register. This is a PASS-2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t p_dat                   : 1;       /**< When set (1) and bit 5 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t np_dat                  : 1;       /**< When set (1) and bit 4 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t p_eop                   : 1;       /**< When set (1) and bit 3 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t p_sop                   : 1;       /**< When set (1) and bit 2 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t np_eop                  : 1;       /**< When set (1) and bit 1 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t np_sop                  : 1;       /**< When set (1) and bit 0 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-#else
-        uint64_t np_sop                  : 1;
-        uint64_t np_eop                  : 1;
-        uint64_t p_sop                   : 1;
-        uint64_t p_eop                   : 1;
-        uint64_t np_dat                  : 1;
-        uint64_t p_dat                   : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_iob_int_enb_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t p_eop                   : 1;       /**< When set (1) and bit 3 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t p_sop                   : 1;       /**< When set (1) and bit 2 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t np_eop                  : 1;       /**< When set (1) and bit 1 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-        uint64_t np_sop                  : 1;       /**< When set (1) and bit 0 of the IOB_INT_SUM
-                                                         register is asserted the IOB will assert an
-                                                         interrupt. */
-#else
-        uint64_t np_sop                  : 1;
-        uint64_t np_eop                  : 1;
-        uint64_t p_sop                   : 1;
-        uint64_t p_eop                   : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_iob_int_enb_cn30xx       cn31xx;
-    struct cvmx_iob_int_enb_cn30xx       cn38xx;
-    struct cvmx_iob_int_enb_cn30xx       cn38xxp2;
-    struct cvmx_iob_int_enb_s            cn50xx;
-    struct cvmx_iob_int_enb_s            cn52xx;
-    struct cvmx_iob_int_enb_s            cn52xxp1;
-    struct cvmx_iob_int_enb_s            cn56xx;
-    struct cvmx_iob_int_enb_s            cn56xxp1;
-    struct cvmx_iob_int_enb_s            cn58xx;
-    struct cvmx_iob_int_enb_s            cn58xxp1;
-} cvmx_iob_int_enb_t;
-
-
-/**
- * cvmx_iob_int_sum
- *
- * IOB_INT_SUM = IOB's Interrupt Summary Register
- * 
- * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t p_dat                   : 1;       /**< Set when a data arrives before a SOP for the same
-                                                         port for a passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t np_dat                  : 1;       /**< Set when a data arrives before a SOP for the same
-                                                         port for a non-passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t p_eop                   : 1;       /**< Set when a EOP is followed by an EOP for the same
-                                                         port for a passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t p_sop                   : 1;       /**< Set when a SOP is followed by an SOP for the same
-                                                         port for a passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t np_eop                  : 1;       /**< Set when a EOP is followed by an EOP for the same
-                                                         port for a non-passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t np_sop                  : 1;       /**< Set when a SOP is followed by an SOP for the same
-                                                         port for a non-passthrough packet.
-                                                         The first detected error associated with bits [5:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-#else
-        uint64_t np_sop                  : 1;
-        uint64_t np_eop                  : 1;
-        uint64_t p_sop                   : 1;
-        uint64_t p_eop                   : 1;
-        uint64_t np_dat                  : 1;
-        uint64_t p_dat                   : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_iob_int_sum_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t p_eop                   : 1;       /**< Set when a EOP is followed by an EOP for the same
-                                                         port for a passthrough packet.
-                                                         The first detected error associated with bits [3:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t p_sop                   : 1;       /**< Set when a SOP is followed by an SOP for the same
-                                                         port for a passthrough packet.
-                                                         The first detected error associated with bits [3:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t np_eop                  : 1;       /**< Set when a EOP is followed by an EOP for the same
-                                                         port for a non-passthrough packet.
-                                                         The first detected error associated with bits [3:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-        uint64_t np_sop                  : 1;       /**< Set when a SOP is followed by an SOP for the same
-                                                         port for a non-passthrough packet.
-                                                         The first detected error associated with bits [3:0]
-                                                         of this register will only be set here. A new bit
-                                                         can be set when the previous reported bit is cleared. */
-#else
-        uint64_t np_sop                  : 1;
-        uint64_t np_eop                  : 1;
-        uint64_t p_sop                   : 1;
-        uint64_t p_eop                   : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_iob_int_sum_cn30xx       cn31xx;
-    struct cvmx_iob_int_sum_cn30xx       cn38xx;
-    struct cvmx_iob_int_sum_cn30xx       cn38xxp2;
-    struct cvmx_iob_int_sum_s            cn50xx;
-    struct cvmx_iob_int_sum_s            cn52xx;
-    struct cvmx_iob_int_sum_s            cn52xxp1;
-    struct cvmx_iob_int_sum_s            cn56xx;
-    struct cvmx_iob_int_sum_s            cn56xxp1;
-    struct cvmx_iob_int_sum_s            cn58xx;
-    struct cvmx_iob_int_sum_s            cn58xxp1;
-} cvmx_iob_int_sum_t;
-
-
-/**
- * cvmx_iob_n2c_l2c_pri_cnt
- *
- * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to CMB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn38xx;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn38xxp2;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn52xx;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn52xxp1;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn56xx;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn56xxp1;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn58xx;
-    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn58xxp1;
-} cvmx_iob_n2c_l2c_pri_cnt_t;
-
-
-/**
- * cvmx_iob_n2c_rsp_pri_cnt
- *
- * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to CMB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn38xx;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn38xxp2;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn52xx;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn52xxp1;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn56xx;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn56xxp1;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn58xx;
-    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn58xxp1;
-} cvmx_iob_n2c_rsp_pri_cnt_t;
-
-
-/**
- * cvmx_iob_outb_com_pri_cnt
- *
- * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_com_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to NCB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn38xx;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn38xxp2;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn52xx;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn52xxp1;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn56xx;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn56xxp1;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn58xx;
-    struct cvmx_iob_outb_com_pri_cnt_s   cn58xxp1;
-} cvmx_iob_outb_com_pri_cnt_t;
-
-
-/**
- * cvmx_iob_outb_control_match
- *
- * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match
- * 
- * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_control_match_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_26_63          : 38;
-        uint64_t mask                    : 8;       /**< Pattern to match on the outbound NCB. */
-        uint64_t eot                     : 1;       /**< Pattern to match on the outbound NCB. */
-        uint64_t dst                     : 8;       /**< Pattern to match on the outbound NCB. */
-        uint64_t src                     : 9;       /**< Pattern to match on the outbound NCB. */
-#else
-        uint64_t src                     : 9;
-        uint64_t dst                     : 8;
-        uint64_t eot                     : 1;
-        uint64_t mask                    : 8;
-        uint64_t reserved_26_63          : 38;
-#endif
-    } s;
-    struct cvmx_iob_outb_control_match_s cn30xx;
-    struct cvmx_iob_outb_control_match_s cn31xx;
-    struct cvmx_iob_outb_control_match_s cn38xx;
-    struct cvmx_iob_outb_control_match_s cn38xxp2;
-    struct cvmx_iob_outb_control_match_s cn50xx;
-    struct cvmx_iob_outb_control_match_s cn52xx;
-    struct cvmx_iob_outb_control_match_s cn52xxp1;
-    struct cvmx_iob_outb_control_match_s cn56xx;
-    struct cvmx_iob_outb_control_match_s cn56xxp1;
-    struct cvmx_iob_outb_control_match_s cn58xx;
-    struct cvmx_iob_outb_control_match_s cn58xxp1;
-} cvmx_iob_outb_control_match_t;
-
-
-/**
- * cvmx_iob_outb_control_match_enb
- *
- * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable
- * 
- * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_control_match_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_26_63          : 38;
-        uint64_t mask                    : 8;       /**< Pattern to match on the outbound NCB. */
-        uint64_t eot                     : 1;       /**< Pattern to match on the outbound NCB. */
-        uint64_t dst                     : 8;       /**< Pattern to match on the outbound NCB. */
-        uint64_t src                     : 9;       /**< Pattern to match on the outbound NCB. */
-#else
-        uint64_t src                     : 9;
-        uint64_t dst                     : 8;
-        uint64_t eot                     : 1;
-        uint64_t mask                    : 8;
-        uint64_t reserved_26_63          : 38;
-#endif
-    } s;
-    struct cvmx_iob_outb_control_match_enb_s cn30xx;
-    struct cvmx_iob_outb_control_match_enb_s cn31xx;
-    struct cvmx_iob_outb_control_match_enb_s cn38xx;
-    struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
-    struct cvmx_iob_outb_control_match_enb_s cn50xx;
-    struct cvmx_iob_outb_control_match_enb_s cn52xx;
-    struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
-    struct cvmx_iob_outb_control_match_enb_s cn56xx;
-    struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
-    struct cvmx_iob_outb_control_match_enb_s cn58xx;
-    struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
-} cvmx_iob_outb_control_match_enb_t;
-
-
-/**
- * cvmx_iob_outb_data_match
- *
- * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match
- * 
- * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_data_match_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Pattern to match on the outbound NCB. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_iob_outb_data_match_s    cn30xx;
-    struct cvmx_iob_outb_data_match_s    cn31xx;
-    struct cvmx_iob_outb_data_match_s    cn38xx;
-    struct cvmx_iob_outb_data_match_s    cn38xxp2;
-    struct cvmx_iob_outb_data_match_s    cn50xx;
-    struct cvmx_iob_outb_data_match_s    cn52xx;
-    struct cvmx_iob_outb_data_match_s    cn52xxp1;
-    struct cvmx_iob_outb_data_match_s    cn56xx;
-    struct cvmx_iob_outb_data_match_s    cn56xxp1;
-    struct cvmx_iob_outb_data_match_s    cn58xx;
-    struct cvmx_iob_outb_data_match_s    cn58xxp1;
-} cvmx_iob_outb_data_match_t;
-
-
-/**
- * cvmx_iob_outb_data_match_enb
- *
- * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable
- * 
- * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_data_match_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Bit to enable match of. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_iob_outb_data_match_enb_s cn30xx;
-    struct cvmx_iob_outb_data_match_enb_s cn31xx;
-    struct cvmx_iob_outb_data_match_enb_s cn38xx;
-    struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
-    struct cvmx_iob_outb_data_match_enb_s cn50xx;
-    struct cvmx_iob_outb_data_match_enb_s cn52xx;
-    struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
-    struct cvmx_iob_outb_data_match_enb_s cn56xx;
-    struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
-    struct cvmx_iob_outb_data_match_enb_s cn58xx;
-    struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
-} cvmx_iob_outb_data_match_enb_t;
-
-
-/**
- * cvmx_iob_outb_fpa_pri_cnt
- *
- * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_fpa_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to NCB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn38xx;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn38xxp2;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn52xx;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn52xxp1;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn56xx;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn56xxp1;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn58xx;
-    struct cvmx_iob_outb_fpa_pri_cnt_s   cn58xxp1;
-} cvmx_iob_outb_fpa_pri_cnt_t;
-
-
-/**
- * cvmx_iob_outb_req_pri_cnt
- *
- * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_outb_req_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to NCB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn38xx;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn38xxp2;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn52xx;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn52xxp1;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn56xx;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn56xxp1;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn58xx;
-    struct cvmx_iob_outb_req_pri_cnt_s   cn58xxp1;
-} cvmx_iob_outb_req_pri_cnt_t;
-
-
-/**
- * cvmx_iob_p2c_req_pri_cnt
- *
- * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value
- * 
- * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_p2c_req_pri_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
-                                                         when CNT_VAL is reached. */
-        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
-                                                         the priority for access to CMB. */
-#else
-        uint64_t cnt_val                 : 15;
-        uint64_t cnt_enb                 : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn38xx;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn38xxp2;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn52xx;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn52xxp1;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn56xx;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn56xxp1;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn58xx;
-    struct cvmx_iob_p2c_req_pri_cnt_s    cn58xxp1;
-} cvmx_iob_p2c_req_pri_cnt_t;
-
-
-/**
- * cvmx_iob_pkt_err
- *
- * IOB_PKT_ERR = IOB Packet Error Register
- * 
- * Provides status about the failing packet recevie error. This is a PASS-2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_pkt_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t port                    : 6;       /**< When IOB_INT_SUM[3:0] bit is set, this field
-                                                         latches the failing port associate with the
-                                                         IOB_INT_SUM[3:0] bit set. */
-#else
-        uint64_t port                    : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_iob_pkt_err_s            cn30xx;
-    struct cvmx_iob_pkt_err_s            cn31xx;
-    struct cvmx_iob_pkt_err_s            cn38xx;
-    struct cvmx_iob_pkt_err_s            cn38xxp2;
-    struct cvmx_iob_pkt_err_s            cn50xx;
-    struct cvmx_iob_pkt_err_s            cn52xx;
-    struct cvmx_iob_pkt_err_s            cn52xxp1;
-    struct cvmx_iob_pkt_err_s            cn56xx;
-    struct cvmx_iob_pkt_err_s            cn56xxp1;
-    struct cvmx_iob_pkt_err_s            cn58xx;
-    struct cvmx_iob_pkt_err_s            cn58xxp1;
-} cvmx_iob_pkt_err_t;
-
-
-/**
- * cvmx_iob_to_cmb_credits
- *
- * IOB_TO_CMB_CREDITS = IOB To CMB Credits
- * 
- * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_iob_to_cmb_credits_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t pko_rd                  : 3;       /**< Number of PKO reads that can be out to L2C where
-                                                         0 == 8-credits. */
-        uint64_t ncb_rd                  : 3;       /**< Number of NCB reads that can be out to L2C where
-                                                         0 == 8-credits. */
-        uint64_t ncb_wr                  : 3;       /**< Number of NCB/PKI writes that can be out to L2C
-                                                         where 0 == 8-credits. */
-#else
-        uint64_t ncb_wr                  : 3;
-        uint64_t ncb_rd                  : 3;
-        uint64_t pko_rd                  : 3;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_iob_to_cmb_credits_s     cn52xx;
-} cvmx_iob_to_cmb_credits_t;
-
-
-/**
- * cvmx_ipd_1st_mbuff_skip
- *
- * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size
- * 
- * The number of words that the IPD will skip when writing the first MBUFF.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_1st_mbuff_skip_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t skip_sz                 : 6;       /**< The number of 8-byte words from the top of the
-                                                         1st MBUFF that the IPD will store the next-pointer.
-                                                         Legal values are 0 to 32, where the MAX value
-                                                         is also limited to:
-                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18. */
-#else
-        uint64_t skip_sz                 : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn30xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn31xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn38xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn38xxp2;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn50xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn52xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn52xxp1;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn56xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn56xxp1;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn58xx;
-    struct cvmx_ipd_1st_mbuff_skip_s     cn58xxp1;
-} cvmx_ipd_1st_mbuff_skip_t;
-
-
-/**
- * cvmx_ipd_1st_next_ptr_back
- *
- * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values
- * 
- * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_1st_next_ptr_back_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t back                    : 4;       /**< Used to find head of buffer from the nxt-hdr-ptr. */
-#else
-        uint64_t back                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn30xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn31xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn38xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn38xxp2;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn50xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn52xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn52xxp1;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn56xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn56xxp1;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn58xx;
-    struct cvmx_ipd_1st_next_ptr_back_s  cn58xxp1;
-} cvmx_ipd_1st_next_ptr_back_t;
-
-
-/**
- * cvmx_ipd_2nd_next_ptr_back
- *
- * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value
- * 
- * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_2nd_next_ptr_back_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t back                    : 4;       /**< Used to find head of buffer from the nxt-hdr-ptr. */
-#else
-        uint64_t back                    : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn30xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn31xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn38xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn38xxp2;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn50xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn52xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn52xxp1;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn56xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn56xxp1;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn58xx;
-    struct cvmx_ipd_2nd_next_ptr_back_s  cn58xxp1;
-} cvmx_ipd_2nd_next_ptr_back_t;
-
-
-/**
- * cvmx_ipd_bist_status
- *
- * IPD_BIST_STATUS = IPD BIST STATUS
- * 
- * BIST Status for IPD's Memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t csr_mem                 : 1;       /**< CSR Register Memory Bist Status. */
-        uint64_t csr_ncmd                : 1;       /**< CSR NCB Commands Memory Bist Status. */
-        uint64_t pwq_wqed                : 1;       /**< PWQ PIP WQE DONE Memory Bist Status. */
-        uint64_t pwq_wp1                 : 1;       /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
-        uint64_t pwq_pow                 : 1;       /**< PWQ POW MEM Memory Bist Status. */
-        uint64_t ipq_pbe1                : 1;       /**< IPQ PBE1 Memory Bist Status. */
-        uint64_t ipq_pbe0                : 1;       /**< IPQ PBE0 Memory Bist Status. */
-        uint64_t pbm3                    : 1;       /**< PBM3 Memory Bist Status. */
-        uint64_t pbm2                    : 1;       /**< PBM2 Memory Bist Status. */
-        uint64_t pbm1                    : 1;       /**< PBM1 Memory Bist Status. */
-        uint64_t pbm0                    : 1;       /**< PBM0 Memory Bist Status. */
-        uint64_t pbm_word                : 1;       /**< PBM_WORD Memory Bist Status. */
-        uint64_t pwq1                    : 1;       /**< PWQ1 Memory Bist Status. */
-        uint64_t pwq0                    : 1;       /**< PWQ0 Memory Bist Status. */
-        uint64_t prc_off                 : 1;       /**< PRC_OFF Memory Bist Status. */
-        uint64_t ipd_old                 : 1;       /**< IPD_OLD Memory Bist Status. */
-        uint64_t ipd_new                 : 1;       /**< IPD_NEW Memory Bist Status. */
-        uint64_t pwp                     : 1;       /**< PWP Memory Bist Status. */
-#else
-        uint64_t pwp                     : 1;
-        uint64_t ipd_new                 : 1;
-        uint64_t ipd_old                 : 1;
-        uint64_t prc_off                 : 1;
-        uint64_t pwq0                    : 1;
-        uint64_t pwq1                    : 1;
-        uint64_t pbm_word                : 1;
-        uint64_t pbm0                    : 1;
-        uint64_t pbm1                    : 1;
-        uint64_t pbm2                    : 1;
-        uint64_t pbm3                    : 1;
-        uint64_t ipq_pbe0                : 1;
-        uint64_t ipq_pbe1                : 1;
-        uint64_t pwq_pow                 : 1;
-        uint64_t pwq_wp1                 : 1;
-        uint64_t pwq_wqed                : 1;
-        uint64_t csr_ncmd                : 1;
-        uint64_t csr_mem                 : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_ipd_bist_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t pwq_wqed                : 1;       /**< PWQ PIP WQE DONE Memory Bist Status. */
-        uint64_t pwq_wp1                 : 1;       /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
-        uint64_t pwq_pow                 : 1;       /**< PWQ POW MEM Memory Bist Status. */
-        uint64_t ipq_pbe1                : 1;       /**< IPQ PBE1 Memory Bist Status. */
-        uint64_t ipq_pbe0                : 1;       /**< IPQ PBE0 Memory Bist Status. */
-        uint64_t pbm3                    : 1;       /**< PBM3 Memory Bist Status. */
-        uint64_t pbm2                    : 1;       /**< PBM2 Memory Bist Status. */
-        uint64_t pbm1                    : 1;       /**< PBM1 Memory Bist Status. */
-        uint64_t pbm0                    : 1;       /**< PBM0 Memory Bist Status. */
-        uint64_t pbm_word                : 1;       /**< PBM_WORD Memory Bist Status. */
-        uint64_t pwq1                    : 1;       /**< PWQ1 Memory Bist Status. */
-        uint64_t pwq0                    : 1;       /**< PWQ0 Memory Bist Status. */
-        uint64_t prc_off                 : 1;       /**< PRC_OFF Memory Bist Status. */
-        uint64_t ipd_old                 : 1;       /**< IPD_OLD Memory Bist Status. */
-        uint64_t ipd_new                 : 1;       /**< IPD_NEW Memory Bist Status. */
-        uint64_t pwp                     : 1;       /**< PWP Memory Bist Status. */
-#else
-        uint64_t pwp                     : 1;
-        uint64_t ipd_new                 : 1;
-        uint64_t ipd_old                 : 1;
-        uint64_t prc_off                 : 1;
-        uint64_t pwq0                    : 1;
-        uint64_t pwq1                    : 1;
-        uint64_t pbm_word                : 1;
-        uint64_t pbm0                    : 1;
-        uint64_t pbm1                    : 1;
-        uint64_t pbm2                    : 1;
-        uint64_t pbm3                    : 1;
-        uint64_t ipq_pbe0                : 1;
-        uint64_t ipq_pbe1                : 1;
-        uint64_t pwq_pow                 : 1;
-        uint64_t pwq_wp1                 : 1;
-        uint64_t pwq_wqed                : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_bist_status_cn30xx   cn31xx;
-    struct cvmx_ipd_bist_status_cn30xx   cn38xx;
-    struct cvmx_ipd_bist_status_cn30xx   cn38xxp2;
-    struct cvmx_ipd_bist_status_cn30xx   cn50xx;
-    struct cvmx_ipd_bist_status_s        cn52xx;
-    struct cvmx_ipd_bist_status_s        cn52xxp1;
-    struct cvmx_ipd_bist_status_s        cn56xx;
-    struct cvmx_ipd_bist_status_s        cn56xxp1;
-    struct cvmx_ipd_bist_status_cn30xx   cn58xx;
-    struct cvmx_ipd_bist_status_cn30xx   cn58xxp1;
-} cvmx_ipd_bist_status_t;
-
-
-/**
- * cvmx_ipd_bp_prt_red_end
- *
- * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable
- * 
- * When IPD applies backpressure to a PORT and the corresponding bit in this register is set,
- * the RED Unit will drop packets for that port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_bp_prt_red_end_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t prt_enb                 : 40;      /**< The port corresponding to the bit position in this
-                                                         field, will allow RED to drop back when port level
-                                                         backpressure is applied to the port. The applying
-                                                         of port-level backpressure for this RED dropping
-                                                         does not take into consideration the value of
-                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
-#else
-        uint64_t prt_enb                 : 40;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t prt_enb                 : 36;      /**< The port corresponding to the bit position in this
-                                                         field, will allow RED to drop back when port level
-                                                         backpressure is applied to the port. The applying
-                                                         of port-level backpressure for this RED dropping
-                                                         does not take into consideration the value of
-                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
-#else
-        uint64_t prt_enb                 : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
-    struct cvmx_ipd_bp_prt_red_end_s     cn52xx;
-    struct cvmx_ipd_bp_prt_red_end_s     cn52xxp1;
-    struct cvmx_ipd_bp_prt_red_end_s     cn56xx;
-    struct cvmx_ipd_bp_prt_red_end_s     cn56xxp1;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
-    struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
-} cvmx_ipd_bp_prt_red_end_t;
-
-
-/**
- * cvmx_ipd_clk_count
- *
- * IPD_CLK_COUNT = IPD Clock Count
- * 
- * Counts the number of core clocks periods since the de-asserition of reset.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_clk_count_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t clk_cnt                 : 64;      /**< This counter will be zeroed when reset is applied
-                                                         and will increment every rising edgge of the
-                                                         core-clock. PASS2 FIELD. */
-#else
-        uint64_t clk_cnt                 : 64;
-#endif
-    } s;
-    struct cvmx_ipd_clk_count_s          cn30xx;
-    struct cvmx_ipd_clk_count_s          cn31xx;
-    struct cvmx_ipd_clk_count_s          cn38xx;
-    struct cvmx_ipd_clk_count_s          cn38xxp2;
-    struct cvmx_ipd_clk_count_s          cn50xx;
-    struct cvmx_ipd_clk_count_s          cn52xx;
-    struct cvmx_ipd_clk_count_s          cn52xxp1;
-    struct cvmx_ipd_clk_count_s          cn56xx;
-    struct cvmx_ipd_clk_count_s          cn56xxp1;
-    struct cvmx_ipd_clk_count_s          cn58xx;
-    struct cvmx_ipd_clk_count_s          cn58xxp1;
-} cvmx_ipd_clk_count_t;
-
-
-/**
- * cvmx_ipd_ctl_status
- *
- * IPD_CTL_STATUS = IPS'd Control Status Register
- * 
- * The number of words in a MBUFF used for packet data store.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t no_wptr                 : 1;       /**< When set '1' the WQE pointers will not be used and
-                                                         the WQE will be located at the front of the packet. */
-        uint64_t pq_apkt                 : 1;       /**< When set IPD_PORT_QOS_X_CNT WILL be incremented
-                                                         by one for every work queue entry that is sent to
-                                                         POW. */
-        uint64_t pq_nabuf                : 1;       /**< When set IPD_PORT_QOS_X_CNT WILL NOT be
-                                                         incremented when IPD allocates a buffer for a
-                                                         packet. */
-        uint64_t ipd_full                : 1;       /**< When clear '0' the IPD acts normaly.
-                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
-                                                         the IOB-arbiter, telling it to not give grants to
-                                                         NCB devices sending packet data. */
-        uint64_t pkt_off                 : 1;       /**< When clear '0' the IPD working normaly,
-                                                         buffering the received packet data. When set '1'
-                                                         the IPD will not buffer the received packet data. */
-        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
-                                                         data-length field in the header written wo the
-                                                         POW and the top of a MBUFF.
-                                                         OCTEAN PASS2 generates a length that includes the
-                                                         length of the data + 8 for the header-field. By
-                                                         setting this bit the 8 for the instr-field will
-                                                         not be included in the length field of the header.
-                                                         NOTE: IPD is compliant with the spec when this
-                                                         field is '1'. */
-        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
-                                                         RSL. */
-        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL be incremented by one for every work
-                                                         queue entry that is sent to POW.
-                                                         PASS-2 Field. */
-        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL NOT be incremented when IPD allocates a
-                                                         buffer for a packet on the port.
-                                                         PASS-2 Field. */
-        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
-        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
-        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
-                                                         the sending of port level backpressure to the
-                                                         Octane input-ports. Once enabled the sending of
-                                                         port-level-backpressure can not be disabled by
-                                                         changing the value of this bit. */
-        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
-                                                         is written through to memory.
-                                                         1 ==> All packet data (and next buffer pointers) is
-                                                         written into the cache.
-                                                         2 ==> The first aligned cache block holding the
-                                                         packet data (and initial next buffer pointer) is
-                                                         written to the L2 cache, all remaining cache blocks
-                                                         are not written to the L2 cache.
-                                                         3 ==> The first two aligned cache blocks holding
-                                                         the packet data (and initial next buffer pointer)
-                                                         are written to the L2 cache, all remaining cache
-                                                         blocks are not written to the L2 cache. */
-        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD.
-                                                         When clear '0', the IPD will appear to the
-                                                         IOB-arbiter to be applying backpressure, this
-                                                         causes the IOB-Arbiter to not send grants to NCB
-                                                         devices requesting to send packet data to the IPD. */
-#else
-        uint64_t ipd_en                  : 1;
-        cvmx_ipd_mode_t opc_mode         : 2;
-        uint64_t pbp_en                  : 1;
-        uint64_t wqe_lend                : 1;
-        uint64_t pkt_lend                : 1;
-        uint64_t naddbuf                 : 1;
-        uint64_t addpkt                  : 1;
-        uint64_t reset                   : 1;
-        uint64_t len_m8                  : 1;
-        uint64_t pkt_off                 : 1;
-        uint64_t ipd_full                : 1;
-        uint64_t pq_nabuf                : 1;
-        uint64_t pq_apkt                 : 1;
-        uint64_t no_wptr                 : 1;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_ipd_ctl_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
-                                                         data-length field in the header written wo the
-                                                         POW and the top of a MBUFF.
-                                                         OCTEAN generates a length that includes the
-                                                         length of the data + 8 for the header-field. By
-                                                         setting this bit the 8 for the instr-field will
-                                                         not be included in the length field of the header.
-                                                         NOTE: IPD is compliant with the spec when this
-                                                         field is '1'. */
-        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
-                                                         RSL. */
-        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL be incremented by one for every work
-                                                         queue entry that is sent to POW. */
-        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL NOT be incremented when IPD allocates a
-                                                         buffer for a packet on the port. */
-        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
-        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
-        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
-                                                         the sending of port level backpressure to the
-                                                         Octane input-ports. Once enabled the sending of
-                                                         port-level-backpressure can not be disabled by
-                                                         changing the value of this bit.
-                                                         GMXX_INF_MODE[EN] must be set to '1' for each
-                                                         packet interface which requires port back pressure
-                                                         prior to setting PBP_EN to '1'. */
-        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
-                                                         is written through to memory.
-                                                         1 ==> All packet data (and next buffer pointers) is
-                                                         written into the cache.
-                                                         2 ==> The first aligned cache block holding the
-                                                         packet data (and initial next buffer pointer) is
-                                                         written to the L2 cache, all remaining cache blocks
-                                                         are not written to the L2 cache.
-                                                         3 ==> The first two aligned cache blocks holding
-                                                         the packet data (and initial next buffer pointer)
-                                                         are written to the L2 cache, all remaining cache
-                                                         blocks are not written to the L2 cache. */
-        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD. */
-#else
-        uint64_t ipd_en                  : 1;
-        cvmx_ipd_mode_t opc_mode         : 2;
-        uint64_t pbp_en                  : 1;
-        uint64_t wqe_lend                : 1;
-        uint64_t pkt_lend                : 1;
-        uint64_t naddbuf                 : 1;
-        uint64_t addpkt                  : 1;
-        uint64_t reset                   : 1;
-        uint64_t len_m8                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_ctl_status_cn30xx    cn31xx;
-    struct cvmx_ipd_ctl_status_cn30xx    cn38xx;
-    struct cvmx_ipd_ctl_status_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
-                                                         RSL. */
-        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL be incremented by one for every work
-                                                         queue entry that is sent to POW.
-                                                         PASS-2 Field. */
-        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL NOT be incremented when IPD allocates a
-                                                         buffer for a packet on the port.
-                                                         PASS-2 Field. */
-        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
-        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
-        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
-                                                         the sending of port level backpressure to the
-                                                         Octane input-ports. Once enabled the sending of
-                                                         port-level-backpressure can not be disabled by
-                                                         changing the value of this bit. */
-        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
-                                                         is written through to memory.
-                                                         1 ==> All packet data (and next buffer pointers) is
-                                                         written into the cache.
-                                                         2 ==> The first aligned cache block holding the
-                                                         packet data (and initial next buffer pointer) is
-                                                         written to the L2 cache, all remaining cache blocks
-                                                         are not written to the L2 cache.
-                                                         3 ==> The first two aligned cache blocks holding
-                                                         the packet data (and initial next buffer pointer)
-                                                         are written to the L2 cache, all remaining cache
-                                                         blocks are not written to the L2 cache. */
-        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD. */
-#else
-        uint64_t ipd_en                  : 1;
-        cvmx_ipd_mode_t opc_mode         : 2;
-        uint64_t pbp_en                  : 1;
-        uint64_t wqe_lend                : 1;
-        uint64_t pkt_lend                : 1;
-        uint64_t naddbuf                 : 1;
-        uint64_t addpkt                  : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn38xxp2;
-    struct cvmx_ipd_ctl_status_s         cn50xx;
-    struct cvmx_ipd_ctl_status_s         cn52xx;
-    struct cvmx_ipd_ctl_status_s         cn52xxp1;
-    struct cvmx_ipd_ctl_status_s         cn56xx;
-    struct cvmx_ipd_ctl_status_s         cn56xxp1;
-    struct cvmx_ipd_ctl_status_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t ipd_full                : 1;       /**< When clear '0' the IPD acts normaly.
-                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
-                                                         the IOB-arbiter, telling it to not give grants to
-                                                         NCB devices sending packet data. */
-        uint64_t pkt_off                 : 1;       /**< When clear '0' the IPD working normaly,
-                                                         buffering the received packet data. When set '1'
-                                                         the IPD will not buffer the received packet data. */
-        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
-                                                         data-length field in the header written wo the
-                                                         POW and the top of a MBUFF.
-                                                         OCTEAN PASS2 generates a length that includes the
-                                                         length of the data + 8 for the header-field. By
-                                                         setting this bit the 8 for the instr-field will
-                                                         not be included in the length field of the header.
-                                                         NOTE: IPD is compliant with the spec when this
-                                                         field is '1'. */
-        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
-                                                         RSL. */
-        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL be incremented by one for every work
-                                                         queue entry that is sent to POW.
-                                                         PASS-2 Field. */
-        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
-                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
-                                                         WILL NOT be incremented when IPD allocates a
-                                                         buffer for a packet on the port.
-                                                         PASS-2 Field. */
-        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
-        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
-        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
-                                                         the sending of port level backpressure to the
-                                                         Octane input-ports. Once enabled the sending of
-                                                         port-level-backpressure can not be disabled by
-                                                         changing the value of this bit. */
-        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
-                                                         is written through to memory.
-                                                         1 ==> All packet data (and next buffer pointers) is
-                                                         written into the cache.
-                                                         2 ==> The first aligned cache block holding the
-                                                         packet data (and initial next buffer pointer) is
-                                                         written to the L2 cache, all remaining cache blocks
-                                                         are not written to the L2 cache.
-                                                         3 ==> The first two aligned cache blocks holding
-                                                         the packet data (and initial next buffer pointer)
-                                                         are written to the L2 cache, all remaining cache
-                                                         blocks are not written to the L2 cache. */
-        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD.
-                                                         When clear '0', the IPD will appear to the
-                                                         IOB-arbiter to be applying backpressure, this
-                                                         causes the IOB-Arbiter to not send grants to NCB
-                                                         devices requesting to send packet data to the IPD. */
-#else
-        uint64_t ipd_en                  : 1;
-        cvmx_ipd_mode_t opc_mode         : 2;
-        uint64_t pbp_en                  : 1;
-        uint64_t wqe_lend                : 1;
-        uint64_t pkt_lend                : 1;
-        uint64_t naddbuf                 : 1;
-        uint64_t addpkt                  : 1;
-        uint64_t reset                   : 1;
-        uint64_t len_m8                  : 1;
-        uint64_t pkt_off                 : 1;
-        uint64_t ipd_full                : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn58xx;
-    struct cvmx_ipd_ctl_status_cn58xx    cn58xxp1;
-} cvmx_ipd_ctl_status_t;
-
-
-/**
- * cvmx_ipd_int_enb
- *
- * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register
- * 
- * Used to enable the various interrupting conditions of IPD
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t pq_sub                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set. */
-        uint64_t pq_add                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set. */
-        uint64_t bc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t d_coll                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t c_coll                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t cc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t dc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
-                                                         has an illegal value. */
-        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t dc_ovr                  : 1;
-        uint64_t cc_ovr                  : 1;
-        uint64_t c_coll                  : 1;
-        uint64_t d_coll                  : 1;
-        uint64_t bc_ovr                  : 1;
-        uint64_t pq_add                  : 1;
-        uint64_t pq_sub                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_ipd_int_enb_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
-                                                         has an illegal value. */
-        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_int_enb_cn30xx       cn31xx;
-    struct cvmx_ipd_int_enb_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t bc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t d_coll                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t c_coll                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t cc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t dc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
-                                                         corresponding bit in the IPD_INT_SUM is set.
-                                                         This is a PASS-3 Field. */
-        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
-                                                         has an illegal value. */
-        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t dc_ovr                  : 1;
-        uint64_t cc_ovr                  : 1;
-        uint64_t c_coll                  : 1;
-        uint64_t d_coll                  : 1;
-        uint64_t bc_ovr                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn38xx;
-    struct cvmx_ipd_int_enb_cn30xx       cn38xxp2;
-    struct cvmx_ipd_int_enb_cn38xx       cn50xx;
-    struct cvmx_ipd_int_enb_s            cn52xx;
-    struct cvmx_ipd_int_enb_s            cn52xxp1;
-    struct cvmx_ipd_int_enb_s            cn56xx;
-    struct cvmx_ipd_int_enb_s            cn56xxp1;
-    struct cvmx_ipd_int_enb_cn38xx       cn58xx;
-    struct cvmx_ipd_int_enb_cn38xx       cn58xxp1;
-} cvmx_ipd_int_enb_t;
-
-
-/**
- * cvmx_ipd_int_sum
- *
- * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register
- * 
- * Set when an interrupt condition occurs, write '1' to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t pq_sub                  : 1;       /**< Set when a port-qos does an sub to the count
-                                                         that causes the counter to wrap. */
-        uint64_t pq_add                  : 1;       /**< Set when a port-qos does an add to the count
-                                                         that causes the counter to wrap. */
-        uint64_t bc_ovr                  : 1;       /**< Set when the byte-count to send to IOB overflows.
-                                                         This is a PASS-3 Field. */
-        uint64_t d_coll                  : 1;       /**< Set when the packet/WQE data to be sent to IOB
-                                                         collides.
-                                                         This is a PASS-3 Field. */
-        uint64_t c_coll                  : 1;       /**< Set when the packet/WQE commands to be sent to IOB
-                                                         collides.
-                                                         This is a PASS-3 Field. */
-        uint64_t cc_ovr                  : 1;       /**< Set when the command credits to the IOB overflow.
-                                                         This is a PASS-3 Field. */
-        uint64_t dc_ovr                  : 1;       /**< Set when the data credits to the IOB overflow.
-                                                         This is a PASS-3 Field. */
-        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
-                                                         supplied illegal value. */
-        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t dc_ovr                  : 1;
-        uint64_t cc_ovr                  : 1;
-        uint64_t c_coll                  : 1;
-        uint64_t d_coll                  : 1;
-        uint64_t bc_ovr                  : 1;
-        uint64_t pq_add                  : 1;
-        uint64_t pq_sub                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_ipd_int_sum_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
-                                                         supplied illegal value. */
-        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_int_sum_cn30xx       cn31xx;
-    struct cvmx_ipd_int_sum_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t bc_ovr                  : 1;       /**< Set when the byte-count to send to IOB overflows.
-                                                         This is a PASS-3 Field. */
-        uint64_t d_coll                  : 1;       /**< Set when the packet/WQE data to be sent to IOB
-                                                         collides.
-                                                         This is a PASS-3 Field. */
-        uint64_t c_coll                  : 1;       /**< Set when the packet/WQE commands to be sent to IOB
-                                                         collides.
-                                                         This is a PASS-3 Field. */
-        uint64_t cc_ovr                  : 1;       /**< Set when the command credits to the IOB overflow.
-                                                         This is a PASS-3 Field. */
-        uint64_t dc_ovr                  : 1;       /**< Set when the data credits to the IOB overflow.
-                                                         This is a PASS-3 Field. */
-        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
-                                                         supplied illegal value. */
-        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
-                                                         [127:96] of the PBM memory. */
-        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
-                                                         [95:64] of the PBM memory. */
-        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
-                                                         [63:32] of the PBM memory. */
-        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
-                                                         [31:0] of the PBM memory. */
-#else
-        uint64_t prc_par0                : 1;
-        uint64_t prc_par1                : 1;
-        uint64_t prc_par2                : 1;
-        uint64_t prc_par3                : 1;
-        uint64_t bp_sub                  : 1;
-        uint64_t dc_ovr                  : 1;
-        uint64_t cc_ovr                  : 1;
-        uint64_t c_coll                  : 1;
-        uint64_t d_coll                  : 1;
-        uint64_t bc_ovr                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn38xx;
-    struct cvmx_ipd_int_sum_cn30xx       cn38xxp2;
-    struct cvmx_ipd_int_sum_cn38xx       cn50xx;
-    struct cvmx_ipd_int_sum_s            cn52xx;
-    struct cvmx_ipd_int_sum_s            cn52xxp1;
-    struct cvmx_ipd_int_sum_s            cn56xx;
-    struct cvmx_ipd_int_sum_s            cn56xxp1;
-    struct cvmx_ipd_int_sum_cn38xx       cn58xx;
-    struct cvmx_ipd_int_sum_cn38xx       cn58xxp1;
-} cvmx_ipd_int_sum_t;
-
-
-/**
- * cvmx_ipd_not_1st_mbuff_skip
- *
- * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size
- * 
- * The number of words that the IPD will skip when writing any MBUFF that is not the first.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_not_1st_mbuff_skip_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t skip_sz                 : 6;       /**< The number of 8-byte words from the top of any
-                                                         MBUFF, that is not the 1st MBUFF, that the IPD
-                                                         will write the next-pointer.
-                                                         Legal values are 0 to 32, where the MAX value
-                                                         is also limited to:
-                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */
-#else
-        uint64_t skip_sz                 : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
-    struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
-} cvmx_ipd_not_1st_mbuff_skip_t;
-
-
-/**
- * cvmx_ipd_packet_mbuff_size
- *
- * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words
- * 
- * The number of words in a MBUFF used for packet data store.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_packet_mbuff_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t mb_size                 : 12;      /**< The number of 8-byte words in a MBUF.
-                                                         This must be a number in the range of 32 to
-                                                         2048.
-                                                         This is also the size of the FPA's
-                                                         Queue-0 Free-Page. */
-#else
-        uint64_t mb_size                 : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_ipd_packet_mbuff_size_s  cn30xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn31xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn38xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn38xxp2;
-    struct cvmx_ipd_packet_mbuff_size_s  cn50xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn52xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn52xxp1;
-    struct cvmx_ipd_packet_mbuff_size_s  cn56xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn56xxp1;
-    struct cvmx_ipd_packet_mbuff_size_s  cn58xx;
-    struct cvmx_ipd_packet_mbuff_size_s  cn58xxp1;
-} cvmx_ipd_packet_mbuff_size_t;
-
-
-/**
- * cvmx_ipd_pkt_ptr_valid
- *
- * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid
- * 
- * The value of the packet-pointer fetched and in the valid register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_pkt_ptr_valid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t ptr                     : 29;      /**< Pointer value. */
-#else
-        uint64_t ptr                     : 29;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn30xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn31xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn38xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn50xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn52xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn52xxp1;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn56xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn56xxp1;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn58xx;
-    struct cvmx_ipd_pkt_ptr_valid_s      cn58xxp1;
-} cvmx_ipd_pkt_ptr_valid_t;
-
-
-/**
- * cvmx_ipd_port#_bp_page_cnt
- *
- * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count
- * 
- * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_portx_bp_page_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t bp_enb                  : 1;       /**< When set '1' BP will be applied, if '0' BP will
-                                                         not be applied to port. */
-        uint64_t page_cnt                : 17;      /**< The number of page pointers assigned to
-                                                         the port, that when exceeded will cause
-                                                         back-pressure to be applied to the port.
-                                                         This value is in 256 page-pointer increments,
-                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
-#else
-        uint64_t page_cnt                : 17;
-        uint64_t bp_enb                  : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn30xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn31xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn38xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn38xxp2;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn50xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn52xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn52xxp1;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn56xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn56xxp1;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn58xx;
-    struct cvmx_ipd_portx_bp_page_cnt_s  cn58xxp1;
-} cvmx_ipd_portx_bp_page_cnt_t;
-
-
-/**
- * cvmx_ipd_port#_bp_page_cnt2
- *
- * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count
- * 
- * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_portx_bp_page_cnt2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t bp_enb                  : 1;       /**< When set '1' BP will be applied, if '0' BP will
-                                                         not be applied to port. */
-        uint64_t page_cnt                : 17;      /**< The number of page pointers assigned to
-                                                         the port, that when exceeded will cause
-                                                         back-pressure to be applied to the port.
-                                                         This value is in 256 page-pointer increments,
-                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
-#else
-        uint64_t page_cnt                : 17;
-        uint64_t bp_enb                  : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
-    struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
-    struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
-    struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
-} cvmx_ipd_portx_bp_page_cnt2_t;
-
-
-/**
- * cvmx_ipd_port_bp_counters2_pair#
- *
- * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_port_bp_counters2_pairx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_25_63          : 39;
-        uint64_t cnt_val                 : 25;      /**< Number of MBUFs being used by data on this port. */
-#else
-        uint64_t cnt_val                 : 25;
-        uint64_t reserved_25_63          : 39;
-#endif
-    } s;
-    struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
-    struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
-    struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
-    struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
-} cvmx_ipd_port_bp_counters2_pairx_t;
-
-
-/**
- * cvmx_ipd_port_bp_counters_pair#
- *
- * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_port_bp_counters_pairx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_25_63          : 39;
-        uint64_t cnt_val                 : 25;      /**< Number of MBUFs being used by data on this port. */
-#else
-        uint64_t cnt_val                 : 25;
-        uint64_t reserved_25_63          : 39;
-#endif
-    } s;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
-    struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
-} cvmx_ipd_port_bp_counters_pairx_t;
-
-
-/**
- * cvmx_ipd_port_qos_#_cnt
- *
- * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count
- * 
- * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0
- * QOS 0-7 respectively followed by port 1 at (8-15), etc
- * Ports 0-3, 36-39
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_port_qos_x_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t wmark                   : 32;      /**< When the field CNT after being modified is equal to
-                                                         or crosses this value (i.e. value was greater than
-                                                         then becomes less then, or value was less than and
-                                                         becomes greater than) the cooresponding bit in
-                                                         IPD_PORT_QOS_INTX is set. */
-        uint64_t cnt                     : 32;      /**< The packet related count that is incremented as
-                                                         specified by IPD_SUB_PORT_QOS_CNT. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t wmark                   : 32;
-#endif
-    } s;
-    struct cvmx_ipd_port_qos_x_cnt_s     cn52xx;
-    struct cvmx_ipd_port_qos_x_cnt_s     cn52xxp1;
-    struct cvmx_ipd_port_qos_x_cnt_s     cn56xx;
-    struct cvmx_ipd_port_qos_x_cnt_s     cn56xxp1;
-} cvmx_ipd_port_qos_x_cnt_t;
-
-
-/**
- * cvmx_ipd_port_qos_int#
- *
- * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt
- * 
- * See the description for IPD_PORT_QOS_X_CNT
- * 
- * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63
- * Only ports used are: P0-3, and P32-39. Therefore only IPD_PORT_QOS_INT0[31:0] and IPD_PORT_QOS_INT4[63:0] exist.
- * Unused registers and register fields are reserved.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_port_qos_intx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t intr                    : 64;      /**< Interrupt bits. */
-#else
-        uint64_t intr                    : 64;
-#endif
-    } s;
-    struct cvmx_ipd_port_qos_intx_s      cn52xx;
-    struct cvmx_ipd_port_qos_intx_s      cn52xxp1;
-    struct cvmx_ipd_port_qos_intx_s      cn56xx;
-    struct cvmx_ipd_port_qos_intx_s      cn56xxp1;
-} cvmx_ipd_port_qos_intx_t;
-
-
-/**
- * cvmx_ipd_port_qos_int_enb#
- *
- * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable
- * 
- * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_port_qos_int_enbx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t enb                     : 64;      /**< Enable bits. */
-#else
-        uint64_t enb                     : 64;
-#endif
-    } s;
-    struct cvmx_ipd_port_qos_int_enbx_s  cn52xx;
-    struct cvmx_ipd_port_qos_int_enbx_s  cn52xxp1;
-    struct cvmx_ipd_port_qos_int_enbx_s  cn56xx;
-    struct cvmx_ipd_port_qos_int_enbx_s  cn56xxp1;
-} cvmx_ipd_port_qos_int_enbx_t;
-
-
-/**
- * cvmx_ipd_prc_hold_ptr_fifo_ctl
- *
- * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control
- * 
- * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t max_pkt                 : 3;       /**< Maximum number of Packet-Pointers that COULD be
-                                                         in the FIFO. */
-        uint64_t praddr                  : 3;       /**< Present Packet-Pointer read address. */
-        uint64_t ptr                     : 29;      /**< The output of the prc-holding-fifo. */
-        uint64_t cena                    : 1;       /**< Active low Chip Enable that controls the
-                                                         MUX-select that steers [RADDR] to the fifo.
-                                                         *WARNING - Setting this field to '0' will allow
-                                                         reading of the memories thorugh the PTR field,
-                                                         but will cause unpredictable operation of the IPD
-                                                         under normal operation. */
-        uint64_t raddr                   : 3;       /**< Sets the address to read from in the holding.
-                                                         fifo in the PRC. This FIFO holds Packet-Pointers
-                                                         to be used for packet data storage. */
-#else
-        uint64_t raddr                   : 3;
-        uint64_t cena                    : 1;
-        uint64_t ptr                     : 29;
-        uint64_t praddr                  : 3;
-        uint64_t max_pkt                 : 3;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } s;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
-    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
-} cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
-
-
-/**
- * cvmx_ipd_prc_port_ptr_fifo_ctl
- *
- * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control
- * 
- * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t max_pkt                 : 7;       /**< Maximum number of Packet-Pointers that are in
-                                                         in the FIFO. */
-        uint64_t ptr                     : 29;      /**< The output of the prc-port-ptr-fifo. */
-        uint64_t cena                    : 1;       /**< Active low Chip Enable to the read port of the
-                                                         pwp_fifo. This bit also controls the MUX-select
-                                                         that steers [RADDR] to the pwp_fifo.
-                                                         *WARNING - Setting this field to '0' will allow
-                                                         reading of the memories thorugh the PTR field,
-                                                         but will cause unpredictable operation of the IPD
-                                                         under normal operation. */
-        uint64_t raddr                   : 7;       /**< Sets the address to read from in the port
-                                                         fifo in the PRC. This FIFO holds Packet-Pointers
-                                                         to be used for packet data storage. */
-#else
-        uint64_t raddr                   : 7;
-        uint64_t cena                    : 1;
-        uint64_t ptr                     : 29;
-        uint64_t max_pkt                 : 7;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
-    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
-} cvmx_ipd_prc_port_ptr_fifo_ctl_t;
-
-
-/**
- * cvmx_ipd_ptr_count
- *
- * IPD_PTR_COUNT = IPD Page Pointer Count
- * 
- * Shows the number of WQE and Packet Page Pointers stored in the IPD.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_ptr_count_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t pktv_cnt                : 1;       /**< PKT Ptr Valid. PASS2 Field */
-        uint64_t wqev_cnt                : 1;       /**< WQE Ptr Valid. This value is '1' when a WQE
-                                                         is being for use by the IPD. The value of this
-                                                         field shoould be added to tha value of the
-                                                         WQE_PCNT field, of this register, for a total
-                                                         count of the WQE Page Pointers being held by IPD.
-                                                         PASS2 Field. */
-        uint64_t pfif_cnt                : 3;       /**< See PKT_PCNT. */
-        uint64_t pkt_pcnt                : 7;       /**< This value plus PFIF_CNT plus 36 is the number
-                                                         of PKT Page Pointers in IPD. */
-        uint64_t wqe_pcnt                : 7;       /**< Number of page pointers for WQE storage that are
-                                                         buffered in the IPD. The total count is the value
-                                                         of this buffer plus the field [WQEV_CNT]. For
-                                                         PASS-1 (which does not have the WQEV_CNT field)
-                                                         when the value of this register is '0' there still
-                                                         may be 1 pointer being help by IPD. */
-#else
-        uint64_t wqe_pcnt                : 7;
-        uint64_t pkt_pcnt                : 7;
-        uint64_t pfif_cnt                : 3;
-        uint64_t wqev_cnt                : 1;
-        uint64_t pktv_cnt                : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_ipd_ptr_count_s          cn30xx;
-    struct cvmx_ipd_ptr_count_s          cn31xx;
-    struct cvmx_ipd_ptr_count_s          cn38xx;
-    struct cvmx_ipd_ptr_count_s          cn38xxp2;
-    struct cvmx_ipd_ptr_count_s          cn50xx;
-    struct cvmx_ipd_ptr_count_s          cn52xx;
-    struct cvmx_ipd_ptr_count_s          cn52xxp1;
-    struct cvmx_ipd_ptr_count_s          cn56xx;
-    struct cvmx_ipd_ptr_count_s          cn56xxp1;
-    struct cvmx_ipd_ptr_count_s          cn58xx;
-    struct cvmx_ipd_ptr_count_s          cn58xxp1;
-} cvmx_ipd_ptr_count_t;
-
-
-/**
- * cvmx_ipd_pwp_ptr_fifo_ctl
- *
- * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control
- * 
- * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_61_63          : 3;
-        uint64_t max_cnts                : 7;       /**< Maximum number of Packet-Pointers or WQE-Pointers
-                                                         that COULD be in the FIFO. */
-        uint64_t wraddr                  : 8;       /**< Present FIFO WQE Read address. */
-        uint64_t praddr                  : 8;       /**< Present FIFO Packet Read address. */
-        uint64_t ptr                     : 29;      /**< The output of the pwp_fifo. */
-        uint64_t cena                    : 1;       /**< Active low Chip Enable to the read port of the
-                                                         pwp_fifo. This bit also controls the MUX-select
-                                                         that steers [RADDR] to the pwp_fifo.
-                                                         *WARNING - Setting this field to '0' will allow
-                                                         reading of the memories thorugh the PTR field,
-                                                         but will cause unpredictable operation of the IPD
-                                                         under normal operation. */
-        uint64_t raddr                   : 8;       /**< Sets the address to read from in the pwp_fifo.
-                                                         Addresses 0 through 7 contain Packet-Pointers and
-                                                         addresses 8 through 15 contain WQE-Pointers. */
-#else
-        uint64_t raddr                   : 8;
-        uint64_t cena                    : 1;
-        uint64_t ptr                     : 29;
-        uint64_t praddr                  : 8;
-        uint64_t wraddr                  : 8;
-        uint64_t max_cnts                : 7;
-        uint64_t reserved_61_63          : 3;
-#endif
-    } s;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn30xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn31xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn38xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn50xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn52xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn52xxp1;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn56xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn56xxp1;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn58xx;
-    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn58xxp1;
-} cvmx_ipd_pwp_ptr_fifo_ctl_t;
-
-
-/**
- * cvmx_ipd_qos#_red_marks
- *
- * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low
- * 
- * Set the pass-drop marks for qos level.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_qosx_red_marks_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t drop                    : 32;      /**< Packets will be dropped when the average value of
-                                                         IPD_QUE0_FREE_PAGE_CNT is equal to or less than
-                                                         this value. */
-        uint64_t pass                    : 32;      /**< Packets will be passed when the average value of
-                                                         IPD_QUE0_FREE_PAGE_CNT is larger than this value. */
-#else
-        uint64_t pass                    : 32;
-        uint64_t drop                    : 32;
-#endif
-    } s;
-    struct cvmx_ipd_qosx_red_marks_s     cn30xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn31xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn38xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn38xxp2;
-    struct cvmx_ipd_qosx_red_marks_s     cn50xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn52xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn52xxp1;
-    struct cvmx_ipd_qosx_red_marks_s     cn56xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn56xxp1;
-    struct cvmx_ipd_qosx_red_marks_s     cn58xx;
-    struct cvmx_ipd_qosx_red_marks_s     cn58xxp1;
-} cvmx_ipd_qosx_red_marks_t;
-
-
-/**
- * cvmx_ipd_que0_free_page_cnt
- *
- * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count
- * 
- * Number of Free-Page Pointer that are available for use in the FPA for Queue-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_que0_free_page_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t q0_pcnt                 : 32;      /**< Number of Queue-0 Page Pointers Available. */
-#else
-        uint64_t q0_pcnt                 : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
-    struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
-    struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
-    struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
-    struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
-} cvmx_ipd_que0_free_page_cnt_t;
-
-
-/**
- * cvmx_ipd_red_port_enable
- *
- * IPD_RED_PORT_ENABLE = IPD RED Port Enable
- * 
- * Set the pass-drop marks for qos level.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_red_port_enable_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t prb_dly                 : 14;      /**< Number (core clocks periods + 68) * 8 to wait
-                                                         before caluclating the new packet drop
-                                                         probability for each QOS level. */
-        uint64_t avg_dly                 : 14;      /**< Number (core clocks periods + 10) * 8 to wait
-                                                         before caluclating the moving average for wach
-                                                         QOS level.
-                                                         Larger AVG_DLY values cause the moving averages
-                                                         of ALL QOS levels to track changes in the actual
-                                                         free space more slowly. Smaller NEW_CON (and
-                                                         larger AVG_CON) values can have a similar effect,
-                                                         but only affect an individual QOS level, rather
-                                                         than all. */
-        uint64_t prt_enb                 : 36;      /**< The bit position will enable the corresponding
-                                                         Ports ability to have packets dropped by RED
-                                                         probability. */
-#else
-        uint64_t prt_enb                 : 36;
-        uint64_t avg_dly                 : 14;
-        uint64_t prb_dly                 : 14;
-#endif
-    } s;
-    struct cvmx_ipd_red_port_enable_s    cn30xx;
-    struct cvmx_ipd_red_port_enable_s    cn31xx;
-    struct cvmx_ipd_red_port_enable_s    cn38xx;
-    struct cvmx_ipd_red_port_enable_s    cn38xxp2;
-    struct cvmx_ipd_red_port_enable_s    cn50xx;
-    struct cvmx_ipd_red_port_enable_s    cn52xx;
-    struct cvmx_ipd_red_port_enable_s    cn52xxp1;
-    struct cvmx_ipd_red_port_enable_s    cn56xx;
-    struct cvmx_ipd_red_port_enable_s    cn56xxp1;
-    struct cvmx_ipd_red_port_enable_s    cn58xx;
-    struct cvmx_ipd_red_port_enable_s    cn58xxp1;
-} cvmx_ipd_red_port_enable_t;
-
-
-/**
- * cvmx_ipd_red_port_enable2
- *
- * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2
- * 
- * Set the pass-drop marks for qos level.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_red_port_enable2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t prt_enb                 : 4;       /**< Bits 3-0 cooresponds to ports 39-36. These bits
-                                                         have the same meaning as the PRT_ENB field of
-                                                         IPD_RED_PORT_ENABLE. */
-#else
-        uint64_t prt_enb                 : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_ipd_red_port_enable2_s   cn52xx;
-    struct cvmx_ipd_red_port_enable2_s   cn52xxp1;
-    struct cvmx_ipd_red_port_enable2_s   cn56xx;
-    struct cvmx_ipd_red_port_enable2_s   cn56xxp1;
-} cvmx_ipd_red_port_enable2_t;
-
-
-/**
- * cvmx_ipd_red_que#_param
- *
- * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters
- * 
- * Value control the Passing and Dropping of packets by the red engine for QOS Level-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_red_quex_param_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t use_pcnt                : 1;       /**< When set '1' red will use the actual Packet-Page
-                                                         Count in place of the Average for RED calculations. */
-        uint64_t new_con                 : 8;       /**< This value is used control how much of the present
-                                                         Actual Queue Size is used to calculate the new
-                                                         Average Queue Size. The value is a number from 0
-                                                         256, which represents NEW_CON/256 of the Actual
-                                                         Queue Size that will be used in the calculation.
-                                                         The number in this field plus the value of
-                                                         AVG_CON must be equal to 256.
-                                                         Larger AVG_DLY values cause the moving averages
-                                                         of ALL QOS levels to track changes in the actual
-                                                         free space more slowly. Smaller NEW_CON (and
-                                                         larger AVG_CON) values can have a similar effect,
-                                                         but only affect an individual QOS level, rather
-                                                         than all. */
-        uint64_t avg_con                 : 8;       /**< This value is used control how much of the present
-                                                         Average Queue Size is used to calculate the new
-                                                         Average Queue Size. The value is a number from 0
-                                                         256, which represents AVG_CON/256 of the Average
-                                                         Queue Size that will be used in the calculation.
-                                                         The number in this field plus the value of
-                                                         NEW_CON must be equal to 256.
-                                                         Larger AVG_DLY values cause the moving averages
-                                                         of ALL QOS levels to track changes in the actual
-                                                         free space more slowly. Smaller NEW_CON (and
-                                                         larger AVG_CON) values can have a similar effect,
-                                                         but only affect an individual QOS level, rather
-                                                         than all. */
-        uint64_t prb_con                 : 32;      /**< Used in computing the probability of a packet being
-                                                         passed or drop by the WRED engine. The field is
-                                                         calculated to be (255 * 2^24)/(PASS-DROP). Where
-                                                         PASS and DROP are the field from the
-                                                         IPD_QOS0_RED_MARKS CSR. */
-#else
-        uint64_t prb_con                 : 32;
-        uint64_t avg_con                 : 8;
-        uint64_t new_con                 : 8;
-        uint64_t use_pcnt                : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_ipd_red_quex_param_s     cn30xx;
-    struct cvmx_ipd_red_quex_param_s     cn31xx;
-    struct cvmx_ipd_red_quex_param_s     cn38xx;
-    struct cvmx_ipd_red_quex_param_s     cn38xxp2;
-    struct cvmx_ipd_red_quex_param_s     cn50xx;
-    struct cvmx_ipd_red_quex_param_s     cn52xx;
-    struct cvmx_ipd_red_quex_param_s     cn52xxp1;
-    struct cvmx_ipd_red_quex_param_s     cn56xx;
-    struct cvmx_ipd_red_quex_param_s     cn56xxp1;
-    struct cvmx_ipd_red_quex_param_s     cn58xx;
-    struct cvmx_ipd_red_quex_param_s     cn58xxp1;
-} cvmx_ipd_red_quex_param_t;
-
-
-/**
- * cvmx_ipd_sub_port_bp_page_cnt
- *
- * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count
- * 
- * Will add the value to the indicated port count register, the number of pages supplied. The value added should
- * be the 2's complement of the vallue that needs to be subtracted. Users would add 2's compliment values to the
- * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level
- * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the
- * value in the IPD_PORTX_BP_PAGE_CNT.
- * 
- * This register can't be written from the PCI via a window write.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t port                    : 6;       /**< The port to add the PAGE_CNT field to. */
-        uint64_t page_cnt                : 25;      /**< The number of page pointers to add to
-                                                         the port counter pointed to by the
-                                                         PORT Field. */
-#else
-        uint64_t page_cnt                : 25;
-        uint64_t port                    : 6;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
-    struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
-} cvmx_ipd_sub_port_bp_page_cnt_t;
-
-
-/**
- * cvmx_ipd_sub_port_fcs
- *
- * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register
- * 
- * When set '1' the port corresponding to the but set will subtract 4 bytes from the end of
- * the packet.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_sub_port_fcs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t port_bit2               : 4;       /**< When set '1', the port corresponding to the bit
-                                                         position set, will subtract the FCS for packets
-                                                         on that port. */
-        uint64_t reserved_32_35          : 4;
-        uint64_t port_bit                : 32;      /**< When set '1', the port corresponding to the bit
-                                                         position set, will subtract the FCS for packets
-                                                         on that port. */
-#else
-        uint64_t port_bit                : 32;
-        uint64_t reserved_32_35          : 4;
-        uint64_t port_bit2               : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_ipd_sub_port_fcs_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t port_bit                : 3;       /**< When set '1', the port corresponding to the bit
-                                                         position set, will subtract the FCS for packets
-                                                         on that port. */
-#else
-        uint64_t port_bit                : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_ipd_sub_port_fcs_cn30xx  cn31xx;
-    struct cvmx_ipd_sub_port_fcs_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t port_bit                : 32;      /**< When set '1', the port corresponding to the bit
-                                                         position set, will subtract the FCS for packets
-                                                         on that port. */
-#else
-        uint64_t port_bit                : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_ipd_sub_port_fcs_cn38xx  cn38xxp2;
-    struct cvmx_ipd_sub_port_fcs_cn30xx  cn50xx;
-    struct cvmx_ipd_sub_port_fcs_s       cn52xx;
-    struct cvmx_ipd_sub_port_fcs_s       cn52xxp1;
-    struct cvmx_ipd_sub_port_fcs_s       cn56xx;
-    struct cvmx_ipd_sub_port_fcs_s       cn56xxp1;
-    struct cvmx_ipd_sub_port_fcs_cn38xx  cn58xx;
-    struct cvmx_ipd_sub_port_fcs_cn38xx  cn58xxp1;
-} cvmx_ipd_sub_port_fcs_t;
-
-
-/**
- * cvmx_ipd_sub_port_qos_cnt
- *
- * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count
- * 
- * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be
- * be the 2's complement of the value that needs to be subtracted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_sub_port_qos_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_41_63          : 23;
-        uint64_t port_qos                : 9;       /**< The port to add the CNT field to. */
-        uint64_t cnt                     : 32;      /**< The value to be added to the register selected
-                                                         in the PORT_QOS field. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t port_qos                : 9;
-        uint64_t reserved_41_63          : 23;
-#endif
-    } s;
-    struct cvmx_ipd_sub_port_qos_cnt_s   cn52xx;
-    struct cvmx_ipd_sub_port_qos_cnt_s   cn52xxp1;
-    struct cvmx_ipd_sub_port_qos_cnt_s   cn56xx;
-    struct cvmx_ipd_sub_port_qos_cnt_s   cn56xxp1;
-} cvmx_ipd_sub_port_qos_cnt_t;
-
-
-/**
- * cvmx_ipd_wqe_fpa_queue
- *
- * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size
- * 
- * Which FPA Queue (0-7) to fetch page-pointers from for WQE's
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_wqe_fpa_queue_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t wqe_pool                : 3;       /**< Which FPA Queue to fetch page-pointers
-                                                         from for WQE's. */
-#else
-        uint64_t wqe_pool                : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn30xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn31xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn38xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn38xxp2;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn50xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn52xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn52xxp1;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn56xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn56xxp1;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn58xx;
-    struct cvmx_ipd_wqe_fpa_queue_s      cn58xxp1;
-} cvmx_ipd_wqe_fpa_queue_t;
-
-
-/**
- * cvmx_ipd_wqe_ptr_valid
- *
- * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid
- * 
- * The value of the WQE-pointer fetched and in the valid register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ipd_wqe_ptr_valid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t ptr                     : 29;      /**< Pointer value. */
-#else
-        uint64_t ptr                     : 29;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn30xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn31xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn38xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn50xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn52xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn52xxp1;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn56xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn56xxp1;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn58xx;
-    struct cvmx_ipd_wqe_ptr_valid_s      cn58xxp1;
-} cvmx_ipd_wqe_ptr_valid_t;
-
-
-/**
- * cvmx_key_bist_reg
- *
- * KEY_BIST_REG = KEY's BIST Status Register
- * 
- * The KEY's BIST status for memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_key_bist_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t rrc                     : 1;       /**< RRC bist status. */
-        uint64_t mem1                    : 1;       /**< MEM - 1 bist status. */
-        uint64_t mem0                    : 1;       /**< MEM - 0 bist status. */
-#else
-        uint64_t mem0                    : 1;
-        uint64_t mem1                    : 1;
-        uint64_t rrc                     : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_key_bist_reg_s           cn38xx;
-    struct cvmx_key_bist_reg_s           cn38xxp2;
-    struct cvmx_key_bist_reg_s           cn56xx;
-    struct cvmx_key_bist_reg_s           cn56xxp1;
-    struct cvmx_key_bist_reg_s           cn58xx;
-    struct cvmx_key_bist_reg_s           cn58xxp1;
-} cvmx_key_bist_reg_t;
-
-
-/**
- * cvmx_key_ctl_status
- *
- * KEY_CTL_STATUS = KEY's Control/Status Register
- * 
- * The KEY's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_key_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t mem1_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
-                                                         respective to bit 13:7 of this field, for FPF
-                                                         FIFO 1. */
-        uint64_t mem0_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
-                                                         respective to bit 6:0 of this field, for FPF
-                                                         FIFO 0. */
-#else
-        uint64_t mem0_err                : 7;
-        uint64_t mem1_err                : 7;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_key_ctl_status_s         cn38xx;
-    struct cvmx_key_ctl_status_s         cn38xxp2;
-    struct cvmx_key_ctl_status_s         cn56xx;
-    struct cvmx_key_ctl_status_s         cn56xxp1;
-    struct cvmx_key_ctl_status_s         cn58xx;
-    struct cvmx_key_ctl_status_s         cn58xxp1;
-} cvmx_key_ctl_status_t;
-
-
-/**
- * cvmx_key_int_enb
- *
- * KEY_INT_ENB = KEY's Interrupt Enable
- * 
- * The KEY's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_key_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ked1_dbe                : 1;       /**< When set (1) and bit 3 of the KEY_INT_SUM
-                                                         register is asserted the KEY will assert an
-                                                         interrupt. */
-        uint64_t ked1_sbe                : 1;       /**< When set (1) and bit 2 of the KEY_INT_SUM
-                                                         register is asserted the KEY will assert an
-                                                         interrupt. */
-        uint64_t ked0_dbe                : 1;       /**< When set (1) and bit 1 of the KEY_INT_SUM
-                                                         register is asserted the KEY will assert an
-                                                         interrupt. */
-        uint64_t ked0_sbe                : 1;       /**< When set (1) and bit 0 of the KEY_INT_SUM
-                                                         register is asserted the KEY will assert an
-                                                         interrupt. */
-#else
-        uint64_t ked0_sbe                : 1;
-        uint64_t ked0_dbe                : 1;
-        uint64_t ked1_sbe                : 1;
-        uint64_t ked1_dbe                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_key_int_enb_s            cn38xx;
-    struct cvmx_key_int_enb_s            cn38xxp2;
-    struct cvmx_key_int_enb_s            cn56xx;
-    struct cvmx_key_int_enb_s            cn56xxp1;
-    struct cvmx_key_int_enb_s            cn58xx;
-    struct cvmx_key_int_enb_s            cn58xxp1;
-} cvmx_key_int_enb_t;
-
-
-/**
- * cvmx_key_int_sum
- *
- * KEY_INT_SUM = KEY's Interrupt Summary Register
- * 
- * Contains the diffrent interrupt summary bits of the KEY.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_key_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ked1_dbe                : 1;
-        uint64_t ked1_sbe                : 1;
-        uint64_t ked0_dbe                : 1;
-        uint64_t ked0_sbe                : 1;
-#else
-        uint64_t ked0_sbe                : 1;
-        uint64_t ked0_dbe                : 1;
-        uint64_t ked1_sbe                : 1;
-        uint64_t ked1_dbe                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_key_int_sum_s            cn38xx;
-    struct cvmx_key_int_sum_s            cn38xxp2;
-    struct cvmx_key_int_sum_s            cn56xx;
-    struct cvmx_key_int_sum_s            cn56xxp1;
-    struct cvmx_key_int_sum_s            cn58xx;
-    struct cvmx_key_int_sum_s            cn58xxp1;
-} cvmx_key_int_sum_t;
-
-
-/**
- * cvmx_l2c_bst0
- *
- * L2C_BST0 = L2C BIST 0 CTL/STAT
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_bst0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t dtbnk                   : 1;       /**< DuTag Bank#
-                                                         When DT=1(BAD), this field provides additional information
-                                                         about which DuTag Bank (0/1) failed.
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t dtcnt                   : 13;      /**< DuTag BiST Counter (used to help isolate the failure)
-                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
-                                                         [11:10]: j (Pattern# 1 of 4)
-                                                         [9:4]:   k (DT Index 1 of 64)
-                                                         [3:0]:   l (DT# 1 of 16 DTs) */
-        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t wlb_dat                 : 4;
-        uint64_t stin_msk                : 1;
-        uint64_t dt                      : 1;
-        uint64_t dtcnt                   : 13;
-        uint64_t wlb_msk                 : 4;
-        uint64_t dtbnk                   : 1;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_l2c_bst0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_15_18          : 4;
-        uint64_t dtcnt                   : 9;       /**< DuTag BiST Counter (used to help isolate the failure)
-                                                         [8]:   i (0=FORWARD/1=REVERSE pass)
-                                                         [7:6]: j (Pattern# 1 of 4)
-                                                         [5:0]: k (DT Index 1 of 64) */
-        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_4_4            : 1;
-        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t wlb_dat                 : 4;
-        uint64_t reserved_4_4            : 1;
-        uint64_t dt                      : 1;
-        uint64_t dtcnt                   : 9;
-        uint64_t reserved_15_18          : 4;
-        uint64_t wlb_msk                 : 4;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_bst0_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_16_18          : 3;
-        uint64_t dtcnt                   : 10;      /**< DuTag BiST Counter (used to help isolate the failure)
-                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
-                                                         [8:7]: j (Pattern# 1 of 4)
-                                                         [6:1]: k (DT Index 1 of 64)
-                                                         [0]:   l (DT# 1 of 2 DTs) */
-        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t wlb_dat                 : 4;
-        uint64_t stin_msk                : 1;
-        uint64_t dt                      : 1;
-        uint64_t dtcnt                   : 10;
-        uint64_t reserved_16_18          : 3;
-        uint64_t wlb_msk                 : 4;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_bst0_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t dtcnt                   : 13;      /**< DuTag BiST Counter (used to help isolate the failure)
-                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
-                                                         [11:10]: j (Pattern# 1 of 4)
-                                                         [9:4]:   k (DT Index 1 of 64)
-                                                         [3:0]:   l (DT# 1 of 16 DTs) */
-        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t wlb_dat                 : 4;
-        uint64_t stin_msk                : 1;
-        uint64_t dt                      : 1;
-        uint64_t dtcnt                   : 13;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn38xx;
-    struct cvmx_l2c_bst0_cn38xx          cn38xxp2;
-    struct cvmx_l2c_bst0_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t dtbnk                   : 1;       /**< DuTag Bank#
-                                                         When DT=1(BAD), this field provides additional information
-                                                         about which DuTag Bank (0/1) failed. */
-        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_16_18          : 3;
-        uint64_t dtcnt                   : 10;      /**< DuTag BiST Counter (used to help isolate the failure)
-                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
-                                                         [8:7]: j (Pattern# 1 of 4)
-                                                         [6:1]: k (DT Index 1 of 64)
-                                                         [0]:   l (DT# 1 of 2 DTs) */
-        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t wlb_dat                 : 4;
-        uint64_t stin_msk                : 1;
-        uint64_t dt                      : 1;
-        uint64_t dtcnt                   : 10;
-        uint64_t reserved_16_18          : 3;
-        uint64_t wlb_msk                 : 4;
-        uint64_t dtbnk                   : 1;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_bst0_cn50xx          cn52xx;
-    struct cvmx_l2c_bst0_cn50xx          cn52xxp1;
-    struct cvmx_l2c_bst0_s               cn56xx;
-    struct cvmx_l2c_bst0_s               cn56xxp1;
-    struct cvmx_l2c_bst0_s               cn58xx;
-    struct cvmx_l2c_bst0_s               cn58xxp1;
-} cvmx_l2c_bst0_t;
-
-
-/**
- * cvmx_l2c_bst1
- *
- * L2C_BST1 = L2C BIST 1 CTL/STAT
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_bst1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t l2t                     : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_l2c_bst1_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t lrf                     : 2;       /**< Bist Results for LRF RAMs (PLC+ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_5_8            : 4;
-        uint64_t l2t                     : 5;       /**< Bist Results for L2T (USE+4SET RAMs)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t l2t                     : 5;
-        uint64_t reserved_5_8            : 4;
-        uint64_t vab_vwcf                : 1;
-        uint64_t lrf                     : 2;
-        uint64_t vwdf                    : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_bst1_cn30xx          cn31xx;
-    struct cvmx_l2c_bst1_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t lrf                     : 2;       /**< Bist Results for LRF RAMs (PLC+ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t l2t                     : 9;
-        uint64_t vab_vwcf                : 1;
-        uint64_t lrf                     : 2;
-        uint64_t vwdf                    : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_l2c_bst1_cn38xx          cn38xxp2;
-    struct cvmx_l2c_bst1_cn38xx          cn50xx;
-    struct cvmx_l2c_bst1_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t plc2                    : 1;       /**< Bist Results for PLC2 RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t plc1                    : 1;       /**< Bist Results for PLC1 RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t plc0                    : 1;       /**< Bist Results for PLC0 RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_11_11          : 1;
-        uint64_t ilc                     : 1;       /**< Bist Results for ILC RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t l2t                     : 9;
-        uint64_t vab_vwcf                : 1;
-        uint64_t ilc                     : 1;
-        uint64_t reserved_11_11          : 1;
-        uint64_t vwdf                    : 4;
-        uint64_t plc0                    : 1;
-        uint64_t plc1                    : 1;
-        uint64_t plc2                    : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } cn52xx;
-    struct cvmx_l2c_bst1_cn52xx          cn52xxp1;
-    struct cvmx_l2c_bst1_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t plc2                    : 1;       /**< Bist Results for LRF RAMs (ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t plc1                    : 1;       /**< Bist Results for LRF RAMs (ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t plc0                    : 1;       /**< Bist Results for LRF RAMs (ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ilc                     : 1;       /**< Bist Results for LRF RAMs (ILC)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vwdf1                   : 4;       /**< Bist Results for VWDF1 RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vwdf0                   : 4;       /**< Bist Results for VWDF0 RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t vab_vwcf1               : 1;       /**< Bist Results for VAB VWCF1_MEM */
-        uint64_t reserved_10_10          : 1;
-        uint64_t vab_vwcf0               : 1;       /**< Bist Results for VAB VWCF0_MEM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t l2t                     : 9;
-        uint64_t vab_vwcf0               : 1;
-        uint64_t reserved_10_10          : 1;
-        uint64_t vab_vwcf1               : 1;
-        uint64_t vwdf0                   : 4;
-        uint64_t vwdf1                   : 4;
-        uint64_t ilc                     : 1;
-        uint64_t plc0                    : 1;
-        uint64_t plc1                    : 1;
-        uint64_t plc2                    : 1;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } cn56xx;
-    struct cvmx_l2c_bst1_cn56xx          cn56xxp1;
-    struct cvmx_l2c_bst1_cn38xx          cn58xx;
-    struct cvmx_l2c_bst1_cn38xx          cn58xxp1;
-} cvmx_l2c_bst1_t;
-
-
-/**
- * cvmx_l2c_bst2
- *
- * L2C_BST2 = L2C BIST 2 CTL/STAT
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_bst2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_4_11           : 8;
-        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
-                                                         - 1: BAD */
-        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
-                                                         - 1: BAD */
-        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t xrddat                  : 1;
-        uint64_t xrdmsk                  : 1;
-        uint64_t picbst                  : 1;
-        uint64_t ipcbst                  : 1;
-        uint64_t reserved_4_11           : 8;
-        uint64_t mrb                     : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_l2c_bst2_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t rmdf                    : 4;       /**< Bist Results for RMDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_4_7            : 4;
-        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t reserved_2_2            : 1;
-        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t xrddat                  : 1;
-        uint64_t xrdmsk                  : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t ipcbst                  : 1;
-        uint64_t reserved_4_7            : 4;
-        uint64_t rmdf                    : 4;
-        uint64_t mrb                     : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_bst2_cn30xx          cn31xx;
-    struct cvmx_l2c_bst2_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t rmdf                    : 4;       /**< Bist Results for RMDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t rhdf                    : 4;       /**< Bist Results for RHDF RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
-                                                         - 1: BAD */
-        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
-                                                         - 1: BAD */
-        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t xrddat                  : 1;
-        uint64_t xrdmsk                  : 1;
-        uint64_t picbst                  : 1;
-        uint64_t ipcbst                  : 1;
-        uint64_t rhdf                    : 4;
-        uint64_t rmdf                    : 4;
-        uint64_t mrb                     : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_l2c_bst2_cn38xx          cn38xxp2;
-    struct cvmx_l2c_bst2_cn30xx          cn50xx;
-    struct cvmx_l2c_bst2_cn30xx          cn52xx;
-    struct cvmx_l2c_bst2_cn30xx          cn52xxp1;
-    struct cvmx_l2c_bst2_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t rmdb                    : 4;       /**< Bist Results for RMDB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t rhdb                    : 4;       /**< Bist Results for RHDB RAMs
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
-                                                         - 1: BAD */
-        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
-                                                         - 1: BAD */
-        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t xrddat                  : 1;
-        uint64_t xrdmsk                  : 1;
-        uint64_t picbst                  : 1;
-        uint64_t ipcbst                  : 1;
-        uint64_t rhdb                    : 4;
-        uint64_t rmdb                    : 4;
-        uint64_t mrb                     : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn56xx;
-    struct cvmx_l2c_bst2_cn56xx          cn56xxp1;
-    struct cvmx_l2c_bst2_cn56xx          cn58xx;
-    struct cvmx_l2c_bst2_cn56xx          cn58xxp1;
-} cvmx_l2c_bst2_t;
-
-
-/**
- * cvmx_l2c_cfg
- *
- * Specify the RSL base addresses for the block
- * 
- *                  L2C_CFG = L2C Configuration
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
-                                                         Indicates when the L2C HW Bist sequence(short or long) is
-                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
-                                                         *** NOTE: O9N PASS2 Addition */
-        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
-                                                         When the previous state was '0' and SW writes a '1',
-                                                         the long bist sequence (enhanced 13N March) is performed.
-                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
-                                                         that the long bist sequence is running. When BSTRUN-=0,
-                                                         the state of the L2D_BST[0-3] registers contain information
-                                                         which reflects the status of the recent long bist sequence.
-                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
-                                                         (ie: when BSTRUN=1 never write LBIST=0).
-                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
-                                                         Fuse is blown.
-                                                         *** NOTE: O9N PASS2 Addition */
-        uint64_t xor_bank                : 1;       /**< L2C XOR Bank Bit
-                                                         When both LMC's are enabled(DPRES1=1/DPRES0=1), this
-                                                         bit determines how addresses are assigned to
-                                                         LMC port(s).
-                                                            XOR_BANK|  LMC#
-                                                          ----------+---------------------------------
-                                                              0     |   byte address[7]
-                                                              1     |   byte address[7] XOR byte address[12]
-                                                         Example: If both LMC ports are enabled (DPRES1=1/DPRES0=1)
-                                                         and XOR_BANK=1, then addr[7] XOR addr[12] is used to determine
-                                                         which LMC Port# a reference is directed to.
-                                                         *** NOTE: O56 PASS1 Addition */
-        uint64_t dpres1                  : 1;       /**< DDR1 Present/LMC1 Enable
-                                                         When DPRES1 is set, LMC#1 is enabled(DDR1 pins at
-                                                         the BOTTOM of the chip are active).
-                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
-                                                         see XOR_BANK bit to determine how a reference is
-                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
-                                                         the address sent to the targeted LMC port is the
-                                                         address shifted right by one).
-                                                         NOTE: For power-savings, the DPRES1 is also used to
-                                                         disable DDR1/LMC1 clocks.
-                                                         SW Constraint: When dual LMC is enabled
-                                                         (L2C_CFG[DPRES0/1]=1), the LMCx_DDR2_CTL[DDR_EOF]
-                                                         must be increased by +1 to account for an additional
-                                                         cycle of uncertainty.
-                                                         *** NOTE: O56 PASS1 Addition */
-        uint64_t dpres0                  : 1;       /**< DDR0 Present/LMC0 Enable
-                                                         When DPRES0 is set, LMC#0 is enabled(DDR0 pins at
-                                                         the BOTTOM of the chip are active).
-                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
-                                                         see XOR_BANK bit to determine how a reference is
-                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
-                                                         the address sent to the targeted LMC port is the
-                                                         address shifted right by one).
-                                                         NOTE: For power-savings, the DPRES0 is also used to
-                                                         disable DDR0/LMC0 clocks.
-                                                         SW Constraint: When dual LMC is enabled
-                                                         (L2C_CFG[DPRES0/1]=1), the LMCx_DDR2_CTL[DDR_EOF]
-                                                         must be increased by +1 to account for an additional
-                                                         cycle of uncertainty.
-                                                         *** NOTE: O56 PASS1 Addition */
-        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
-                                                         When set, the L2C dual-fill performance feature is
-                                                         disabled.
-                                                         NOTE: This bit is only intended to evaluate the
-                                                         effectiveness of the dual-fill feature. For OPTIMAL
-                                                         performance, this bit should ALWAYS be zero.
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When FPEN is enabled and the LFB is empty, the
-                                                         forward progress counter (FPCNT) is initialized to:
-                                                            FPCNT[24:0] = 2^(9+FPEXP)
-                                                         When the LFB is non-empty the FPCNT is decremented
-                                                         (every eclk interval). If the FPCNT reaches zero,
-                                                         the LFB no longer accepts new requests until either
-                                                            a) all of the current LFB entries have completed
-                                                               (to ensure forward progress).
-                                                            b) FPEMPTY=0 and another forward progress count
-                                                               interval timeout expires.
-                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
-                                                         (For eclk=500MHz(2ns), this would be ~4us). */
-        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL all current LFB
-                                                         entries have completed.
-                                                         When clear, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL either
-                                                           a) all current LFB entries have completed.
-                                                           b) another forward progress interval expires
-                                                         NOTE: We may want to FREEZE/HANG the system when
-                                                         we encounter an LFB entry cannot complete, and there
-                                                         may be times when we want to allow further LFB-NQs
-                                                         to be permitted to help in further analyzing the
-                                                         source */
-        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, enables the Forward Progress Counter to
-                                                         prevent new LFB entries from enqueueing until ALL
-                                                         current LFB entries have completed. */
-        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
-                                                         When set, the L2 Tag/Data Store will alias the 11-bit
-                                                         index with the low order 11-bits of the tag.
-                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
-                                                         NOTE: This bit must only be modified at boot time,
-                                                         when it can be guaranteed that no blocks have been
-                                                         loaded into the L2 Cache.
-                                                         The index aliasing is a performance enhancement feature
-                                                         which reduces the L2 cache thrashing experienced for
-                                                         regular stride references.
-                                                         NOTE: The index alias is stored in the LFB and VAB, and
-                                                         its effects are reversed for memory references (Victims,
-                                                         STT-Misses and Read-Misses) */
-        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
-                                                         become less than or equal to the MWF_CRD, the L2C will
-                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
-                                                         writes (victims) higher priority. */
-        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
-                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
-                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
-                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
-                                                             STRSC(ST RSP no invalidate)] */
-        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB->PP requests are higher priority than
-                                                             PP->IOB requests
-                                                         - 1: Round Robin -
-                                                             I/O requests from PP and IOB are serviced in
-                                                             round robin */
-        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB memory requests are higher priority than PP
-                                                             memory requests.
-                                                         - 1: Round Robin -
-                                                             Memory requests from PP and IOB are serviced in
-                                                             round robin. */
-#else
-        uint64_t lrf_arb_mode            : 1;
-        uint64_t rfb_arb_mode            : 1;
-        uint64_t rsp_arb_mode            : 1;
-        uint64_t mwf_crd                 : 4;
-        uint64_t idxalias                : 1;
-        uint64_t fpen                    : 1;
-        uint64_t fpempty                 : 1;
-        uint64_t fpexp                   : 4;
-        uint64_t dfill_dis               : 1;
-        uint64_t dpres0                  : 1;
-        uint64_t dpres1                  : 1;
-        uint64_t xor_bank                : 1;
-        uint64_t lbist                   : 1;
-        uint64_t bstrun                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_l2c_cfg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When FPEN is enabled and the LFB is empty, the
-                                                         forward progress counter (FPCNT) is initialized to:
-                                                            FPCNT[24:0] = 2^(9+FPEXP)
-                                                         When the LFB is non-empty the FPCNT is decremented
-                                                         (every eclk interval). If the FPCNT reaches zero,
-                                                         the LFB no longer accepts new requests until either
-                                                            a) all of the current LFB entries have completed
-                                                               (to ensure forward progress).
-                                                            b) FPEMPTY=0 and another forward progress count
-                                                               interval timeout expires.
-                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
-                                                         (For eclk=500MHz(2ns), this would be ~4us). */
-        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL all current LFB
-                                                         entries have completed.
-                                                         When clear, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL either
-                                                           a) all current LFB entries have completed.
-                                                           b) another forward progress interval expires
-                                                         NOTE: We may want to FREEZE/HANG the system when
-                                                         we encounter an LFB entry cannot complete, and there
-                                                         may be times when we want to allow further LFB-NQs
-                                                         to be permitted to help in further analyzing the
-                                                         source */
-        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, enables the Forward Progress Counter to
-                                                         prevent new LFB entries from enqueueing until ALL
-                                                         current LFB entries have completed. */
-        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
-                                                         When set, the L2 Tag/Data Store will alias the 8-bit
-                                                         index with the low order 8-bits of the tag.
-                                                            index[14:7] =  (tag[22:15] ^ index[14:7])
-                                                         NOTE: This bit must only be modified at boot time,
-                                                         when it can be guaranteed that no blocks have been
-                                                         loaded into the L2 Cache.
-                                                         The index aliasing is a performance enhancement feature
-                                                         which reduces the L2 cache thrashing experienced for
-                                                         regular stride references.
-                                                         NOTE: The index alias is stored in the LFB and VAB, and
-                                                         its effects are reversed for memory references (Victims,
-                                                         STT-Misses and Read-Misses) */
-        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
-                                                         become less than or equal to the MWF_CRD, the L2C will
-                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
-                                                         writes (victims) higher priority. */
-        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
-                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
-                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
-                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
-                                                             STRSC(ST RSP no invalidate)] */
-        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB->PP requests are higher priority than
-                                                             PP->IOB requests
-                                                         - 1: Round Robin -
-                                                             I/O requests from PP and IOB are serviced in
-                                                             round robin */
-        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB memory requests are higher priority than PP
-                                                             memory requests.
-                                                         - 1: Round Robin -
-                                                             Memory requests from PP and IOB are serviced in
-                                                             round robin. */
-#else
-        uint64_t lrf_arb_mode            : 1;
-        uint64_t rfb_arb_mode            : 1;
-        uint64_t rsp_arb_mode            : 1;
-        uint64_t mwf_crd                 : 4;
-        uint64_t idxalias                : 1;
-        uint64_t fpen                    : 1;
-        uint64_t fpempty                 : 1;
-        uint64_t fpexp                   : 4;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_cfg_cn30xx           cn31xx;
-    struct cvmx_l2c_cfg_cn30xx           cn38xx;
-    struct cvmx_l2c_cfg_cn30xx           cn38xxp2;
-    struct cvmx_l2c_cfg_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
-                                                         Indicates when the L2C HW Bist sequence(short or long) is
-                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
-                                                         *** NOTE: O56 PASS1 Addition */
-        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
-                                                         When the previous state was '0' and SW writes a '1',
-                                                         the long bist sequence (enhanced 13N March) is performed.
-                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
-                                                         that the long bist sequence is running. When BSTRUN-=0,
-                                                         the state of the L2D_BST[0-3] registers contain information
-                                                         which reflects the status of the recent long bist sequence.
-                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
-                                                         (ie: when BSTRUN=1 never write LBIST=0). */
-        uint64_t reserved_14_17          : 4;
-        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When FPEN is enabled and the LFB is empty, the
-                                                         forward progress counter (FPCNT) is initialized to:
-                                                            FPCNT[24:0] = 2^(9+FPEXP)
-                                                         When the LFB is non-empty the FPCNT is decremented
-                                                         (every eclk interval). If the FPCNT reaches zero,
-                                                         the LFB no longer accepts new requests until either
-                                                            a) all of the current LFB entries have completed
-                                                               (to ensure forward progress).
-                                                            b) FPEMPTY=0 and another forward progress count
-                                                               interval timeout expires.
-                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
-                                                         (For eclk=500MHz(2ns), this would be ~4us). */
-        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL all current LFB
-                                                         entries have completed.
-                                                         When clear, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL either
-                                                           a) all current LFB entries have completed.
-                                                           b) another forward progress interval expires
-                                                         NOTE: We may want to FREEZE/HANG the system when
-                                                         we encounter an LFB entry cannot complete, and there
-                                                         may be times when we want to allow further LFB-NQs
-                                                         to be permitted to help in further analyzing the
-                                                         source */
-        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, enables the Forward Progress Counter to
-                                                         prevent new LFB entries from enqueueing until ALL
-                                                         current LFB entries have completed. */
-        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
-                                                         When set, the L2 Tag/Data Store will alias the 7-bit
-                                                         index with the low order 7-bits of the tag.
-                                                            index[13:7] =  (tag[20:14] ^ index[13:7])
-                                                         NOTE: This bit must only be modified at boot time,
-                                                         when it can be guaranteed that no blocks have been
-                                                         loaded into the L2 Cache.
-                                                         The index aliasing is a performance enhancement feature
-                                                         which reduces the L2 cache thrashing experienced for
-                                                         regular stride references.
-                                                         NOTE: The index alias is stored in the LFB and VAB, and
-                                                         its effects are reversed for memory references (Victims,
-                                                         STT-Misses and Read-Misses) */
-        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
-                                                         become less than or equal to the MWF_CRD, the L2C will
-                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
-                                                         writes (victims) higher priority. */
-        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
-                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
-                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
-                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
-                                                             STRSC(ST RSP no invalidate)] */
-        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB->PP requests are higher priority than
-                                                             PP->IOB requests
-                                                         - 1: Round Robin -
-                                                             I/O requests from PP and IOB are serviced in
-                                                             round robin */
-        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB memory requests are higher priority than PP
-                                                             memory requests.
-                                                         - 1: Round Robin -
-                                                             Memory requests from PP and IOB are serviced in
-                                                             round robin. */
-#else
-        uint64_t lrf_arb_mode            : 1;
-        uint64_t rfb_arb_mode            : 1;
-        uint64_t rsp_arb_mode            : 1;
-        uint64_t mwf_crd                 : 4;
-        uint64_t idxalias                : 1;
-        uint64_t fpen                    : 1;
-        uint64_t fpempty                 : 1;
-        uint64_t fpexp                   : 4;
-        uint64_t reserved_14_17          : 4;
-        uint64_t lbist                   : 1;
-        uint64_t bstrun                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_cfg_cn50xx           cn52xx;
-    struct cvmx_l2c_cfg_cn50xx           cn52xxp1;
-    struct cvmx_l2c_cfg_s                cn56xx;
-    struct cvmx_l2c_cfg_s                cn56xxp1;
-    struct cvmx_l2c_cfg_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
-                                                         Indicates when the L2C HW Bist sequence(short or long) is
-                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
-                                                         *** NOTE: O9N PASS2 Addition */
-        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
-                                                         When the previous state was '0' and SW writes a '1',
-                                                         the long bist sequence (enhanced 13N March) is performed.
-                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
-                                                         that the long bist sequence is running. When BSTRUN-=0,
-                                                         the state of the L2D_BST[0-3] registers contain information
-                                                         which reflects the status of the recent long bist sequence.
-                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
-                                                         (ie: when BSTRUN=1 never write LBIST=0).
-                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
-                                                         Fuse is blown.
-                                                         *** NOTE: O9N PASS2 Addition */
-        uint64_t reserved_15_17          : 3;
-        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
-                                                         When set, the L2C dual-fill performance feature is
-                                                         disabled.
-                                                         NOTE: This bit is only intended to evaluate the
-                                                         effectiveness of the dual-fill feature. For OPTIMAL
-                                                         performance, this bit should ALWAYS be zero.
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When FPEN is enabled and the LFB is empty, the
-                                                         forward progress counter (FPCNT) is initialized to:
-                                                            FPCNT[24:0] = 2^(9+FPEXP)
-                                                         When the LFB is non-empty the FPCNT is decremented
-                                                         (every eclk interval). If the FPCNT reaches zero,
-                                                         the LFB no longer accepts new requests until either
-                                                            a) all of the current LFB entries have completed
-                                                               (to ensure forward progress).
-                                                            b) FPEMPTY=0 and another forward progress count
-                                                               interval timeout expires.
-                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
-                                                         (For eclk=500MHz(2ns), this would be ~4us). */
-        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL all current LFB
-                                                         entries have completed.
-                                                         When clear, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL either
-                                                           a) all current LFB entries have completed.
-                                                           b) another forward progress interval expires
-                                                         NOTE: We may want to FREEZE/HANG the system when
-                                                         we encounter an LFB entry cannot complete, and there
-                                                         may be times when we want to allow further LFB-NQs
-                                                         to be permitted to help in further analyzing the
-                                                         source */
-        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, enables the Forward Progress Counter to
-                                                         prevent new LFB entries from enqueueing until ALL
-                                                         current LFB entries have completed. */
-        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
-                                                         When set, the L2 Tag/Data Store will alias the 11-bit
-                                                         index with the low order 11-bits of the tag.
-                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
-                                                         NOTE: This bit must only be modified at boot time,
-                                                         when it can be guaranteed that no blocks have been
-                                                         loaded into the L2 Cache.
-                                                         The index aliasing is a performance enhancement feature
-                                                         which reduces the L2 cache thrashing experienced for
-                                                         regular stride references.
-                                                         NOTE: The index alias is stored in the LFB and VAB, and
-                                                         its effects are reversed for memory references (Victims,
-                                                         STT-Misses and Read-Misses) */
-        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
-                                                         become less than or equal to the MWF_CRD, the L2C will
-                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
-                                                         writes (victims) higher priority. */
-        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
-                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
-                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
-                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
-                                                             STRSC(ST RSP no invalidate)] */
-        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB->PP requests are higher priority than
-                                                             PP->IOB requests
-                                                         - 1: Round Robin -
-                                                             I/O requests from PP and IOB are serviced in
-                                                             round robin */
-        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB memory requests are higher priority than PP
-                                                             memory requests.
-                                                         - 1: Round Robin -
-                                                             Memory requests from PP and IOB are serviced in
-                                                             round robin. */
-#else
-        uint64_t lrf_arb_mode            : 1;
-        uint64_t rfb_arb_mode            : 1;
-        uint64_t rsp_arb_mode            : 1;
-        uint64_t mwf_crd                 : 4;
-        uint64_t idxalias                : 1;
-        uint64_t fpen                    : 1;
-        uint64_t fpempty                 : 1;
-        uint64_t fpexp                   : 4;
-        uint64_t dfill_dis               : 1;
-        uint64_t reserved_15_17          : 3;
-        uint64_t lbist                   : 1;
-        uint64_t bstrun                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn58xx;
-    struct cvmx_l2c_cfg_cn58xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
-                                                         When set, the L2C dual-fill performance feature is
-                                                         disabled.
-                                                         NOTE: This bit is only intended to evaluate the
-                                                         effectiveness of the dual-fill feature. For OPTIMAL
-                                                         performance, this bit should ALWAYS be zero.
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When FPEN is enabled and the LFB is empty, the
-                                                         forward progress counter (FPCNT) is initialized to:
-                                                            FPCNT[24:0] = 2^(9+FPEXP)
-                                                         When the LFB is non-empty the FPCNT is decremented
-                                                         (every eclk interval). If the FPCNT reaches zero,
-                                                         the LFB no longer accepts new requests until either
-                                                            a) all of the current LFB entries have completed
-                                                               (to ensure forward progress).
-                                                            b) FPEMPTY=0 and another forward progress count
-                                                               interval timeout expires.
-                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
-                                                         (For eclk=500MHz(2ns), this would be ~4us). */
-        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL all current LFB
-                                                         entries have completed.
-                                                         When clear, if the forward progress counter expires,
-                                                         all new LFB-NQs are stopped UNTIL either
-                                                           a) all current LFB entries have completed.
-                                                           b) another forward progress interval expires
-                                                         NOTE: We may want to FREEZE/HANG the system when
-                                                         we encounter an LFB entry cannot complete, and there
-                                                         may be times when we want to allow further LFB-NQs
-                                                         to be permitted to help in further analyzing the
-                                                         source */
-        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
-                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
-                                                         When set, enables the Forward Progress Counter to
-                                                         prevent new LFB entries from enqueueing until ALL
-                                                         current LFB entries have completed. */
-        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
-                                                         When set, the L2 Tag/Data Store will alias the 11-bit
-                                                         index with the low order 11-bits of the tag.
-                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
-                                                         NOTE: This bit must only be modified at boot time,
-                                                         when it can be guaranteed that no blocks have been
-                                                         loaded into the L2 Cache.
-                                                         The index aliasing is a performance enhancement feature
-                                                         which reduces the L2 cache thrashing experienced for
-                                                         regular stride references.
-                                                         NOTE: The index alias is stored in the LFB and VAB, and
-                                                         its effects are reversed for memory references (Victims,
-                                                         STT-Misses and Read-Misses) */
-        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
-                                                         become less than or equal to the MWF_CRD, the L2C will
-                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
-                                                         writes (victims) higher priority. */
-        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
-                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
-                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
-                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
-                                                             STRSC(ST RSP no invalidate)] */
-        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB->PP requests are higher priority than
-                                                             PP->IOB requests
-                                                         - 1: Round Robin -
-                                                             I/O requests from PP and IOB are serviced in
-                                                             round robin */
-        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
-                                                         - 0: Fixed Priority -
-                                                             IOB memory requests are higher priority than PP
-                                                             memory requests.
-                                                         - 1: Round Robin -
-                                                             Memory requests from PP and IOB are serviced in
-                                                             round robin. */
-#else
-        uint64_t lrf_arb_mode            : 1;
-        uint64_t rfb_arb_mode            : 1;
-        uint64_t rsp_arb_mode            : 1;
-        uint64_t mwf_crd                 : 4;
-        uint64_t idxalias                : 1;
-        uint64_t fpen                    : 1;
-        uint64_t fpempty                 : 1;
-        uint64_t fpexp                   : 4;
-        uint64_t dfill_dis               : 1;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } cn58xxp1;
-} cvmx_l2c_cfg_t;
-
-
-/**
- * cvmx_l2c_dbg
- *
- * L2C_DBG = L2C DEBUG Register
- * 
- * Description: L2C Tag/Data Store Debug Register
- *
- * Notes:
- * (1) When using the L2T, L2D or FINV Debug probe feature, the LDD command WILL NOT update the DuTags.
- * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one set)
- * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
- *     dirty data to memory to maintain coherency.
- * (4) L2 Cache Lock Down feature MUST BE disabled (L2C_LCKBASE[LCK_ENA]=0) if ANY of the L2C debug
- *     features (L2T, L2D, FINV) are enabled.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t lfb_enum                : 4;       /**< Specifies the LFB Entry# which is to be captured. */
-        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
-                                                         the LFB specified by LFB_ENUM[3:0] are captured
-                                                         into the L2C_LFB(0/1/2) registers.
-                                                         NOTE: Some fields of the LFB entry are unpredictable
-                                                         and dependent on usage. This is only intended to be
-                                                         used for HW debug. */
-        uint64_t ppnum                   : 4;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines which one-of-16
-                                                         PPs is selected as the diagnostic PP. */
-        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines 1-of-n targeted
-                                                         sets to act upon.
-                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
-                                                         unusable set (see UMSK* registers and Cripple mode
-                                                         fuses). */
-        uint64_t finv                    : 1;       /**< Flush-Invalidate.
-                                                         When flush-invalidate is enable (FINV=1), all STF
-                                                         (L1 store-miss) commands generated from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
-                                                         (L2C_DBG[SET]) at the index specified in the STF
-                                                         address[17:7]. If a dirty block is detected (D=1), it is
-                                                         written back to memory. The contents of the invalid
-                                                         L2 Cache line is also 'scrubbed' with the STF write data.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
-                                                         STF address[17:7] refers to the 'aliased' address.
-                                                         NOTE: An STF command with write data=ZEROES can be
-                                                         generated by SW using the Prefetch instruction with
-                                                         Hint=30d "prepare for Store", followed by a SYNCW.
-                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
-                                                         of its mask bits clear (indicates zero-fill data).
-                                                         A flush-invalidate will 'force-hit' the L2 cache at
-                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
-                                                         If the cache block is dirty, it is also written back
-                                                         to memory. The DuTag state is probed/updated as normal
-                                                         for an STF request.
-                                                         TYPICAL APPLICATIONS:
-                                                            1) L2 Tag/Data ECC SW Recovery
-                                                            2) Cache Unlocking
-                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
-                                                         a flush-invalidate operation will explicitly UNLOCK
-                                                         (L=0) the set/index specified.
-                                                         NOTE: The diagnostic PP cores can generate STF
-                                                         commands to the L2 Cache whenever all 128 bytes in a
-                                                         block are written. SW must take this into consideration
-                                                         to avoid 'errant' Flush-Invalidates. */
-        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
-                                                         returned directly from the L2 Data Store
-                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
-                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
-                                                         field. The selected set# is determined by the
-                                                         L2C_DBG[SET] field, and the index is determined
-                                                         from the address[17:7] associated with the LDD
-                                                         command.
-                                                         This 'force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state. */
-        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:18]]
-                                                         is returned on the data bus starting at +32(and +96) bytes
-                                                         offset from the beginning of cacheline when an LDD
-                                                         (L1 load-miss) command is issued from a PP determined by
-                                                         the L2C_DBG[PPNUM] field.
-                                                         The selected L2 set# is determined by the L2C_DBG[SET]
-                                                         field, and the L2 index is determined from the
-                                                         phys_addr[17:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: The diagnostic PP should issue a d-stream load
-                                                         to an aligned cacheline+0x20(+0x60) in order to have the
-                                                         return VDLUTAG information (in OW2/OW6) written directly
-                                                         into the proper PP register. The diagnostic PP should also
-                                                         flush it's local L1 cache after use(to ensure data
-                                                         coherency).
-                                                         NOTE: The position of the VDLUTAG data in the destination
-                                                         register is dependent on the endian mode(big/little).
-                                                         NOTE: N3K-Pass2 modification. (This bit's functionality
-                                                         has changed since Pass1-in the following way).
-                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
-                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
-                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
-                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
-                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
-#else
-        uint64_t l2t                     : 1;
-        uint64_t l2d                     : 1;
-        uint64_t finv                    : 1;
-        uint64_t set                     : 3;
-        uint64_t ppnum                   : 4;
-        uint64_t lfb_dmp                 : 1;
-        uint64_t lfb_enum                : 4;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_l2c_dbg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t lfb_enum                : 2;       /**< Specifies the LFB Entry# which is to be captured. */
-        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
-                                                         the LFB specified by LFB_ENUM are captured
-                                                         into the L2C_LFB(0/1/2) registers.
-                                                         NOTE: Some fields of the LFB entry are unpredictable
-                                                         and dependent on usage. This is only intended to be
-                                                         used for HW debug. */
-        uint64_t reserved_7_9            : 3;
-        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines which
-                                                         PP is selected as the diagnostic PP.
-                                                         NOTE: For O1P single core PPNUM=0 (MBZ) */
-        uint64_t reserved_5_5            : 1;
-        uint64_t set                     : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines 1-of-n targeted
-                                                         sets to act upon.
-                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
-                                                         unusable set (see UMSK* registers and Cripple mode
-                                                         fuses). */
-        uint64_t finv                    : 1;       /**< Flush-Invalidate.
-                                                         When flush-invalidate is enable (FINV=1), all STF
-                                                         (L1 store-miss) commands generated from the PP will invalidate
-                                                         the specified set(L2C_DBG[SET]) at the index specified
-                                                         in the STF address[14:7]. If a dirty block is detected(D=1),
-                                                         it is written back to memory. The contents of the invalid
-                                                         L2 Cache line is also 'scrubbed' with the STF write data.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
-                                                         STF address[14:7] refers to the 'aliased' address.
-                                                         NOTE: An STF command with write data=ZEROES can be
-                                                         generated by SW using the Prefetch instruction with
-                                                         Hint=30d "prepare for Store", followed by a SYNCW.
-                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
-                                                         of its mask bits clear (indicates zero-fill data).
-                                                         A flush-invalidate will 'force-hit' the L2 cache at
-                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
-                                                         If the cache block is dirty, it is also written back
-                                                         to memory. The DuTag state is probed/updated as normal
-                                                         for an STF request.
-                                                         TYPICAL APPLICATIONS:
-                                                            1) L2 Tag/Data ECC SW Recovery
-                                                            2) Cache Unlocking
-                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
-                                                         a flush-invalidate operation will explicitly UNLOCK
-                                                         (L=0) the set/index specified.
-                                                         NOTE: The PP can generate STF(L1 store-miss)
-                                                         commands to the L2 Cache whenever all 128 bytes in a
-                                                         block are written. SW must take this into consideration
-                                                         to avoid 'errant' Flush-Invalidates. */
-        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
-                                                         returned directly from the L2 Data Store
-                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
-                                                         command is issued from the PP.
-                                                         The selected set# is determined by the
-                                                         L2C_DBG[SET] field, and the index is determined
-                                                         from the address[14:7] associated with the LDD
-                                                         command.
-                                                         This 'force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state. */
-        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:15]]
-                                                         is returned on the data bus starting at +32(and +96) bytes
-                                                         offset from the beginning of cacheline when an LDD
-                                                         (L1 load-miss) command is issued from the PP.
-                                                         The selected L2 set# is determined by the L2C_DBG[SET]
-                                                         field, and the L2 index is determined from the
-                                                         phys_addr[14:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: The diagnostic PP should issue a d-stream load
-                                                         to an aligned cacheline+0x20(+0x60) in order to have the
-                                                         return VDLUTAG information (in OW2/OW6) written directly
-                                                         into the proper PP register. The diagnostic PP should also
-                                                         flush it's local L1 cache after use(to ensure data
-                                                         coherency).
-                                                         NOTE: The position of the VDLUTAG data in the destination
-                                                         register is dependent on the endian mode(big/little).
-                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
-                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
-                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
-                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
-                                                         LDD(L1 load-miss) is detected. */
-#else
-        uint64_t l2t                     : 1;
-        uint64_t l2d                     : 1;
-        uint64_t finv                    : 1;
-        uint64_t set                     : 2;
-        uint64_t reserved_5_5            : 1;
-        uint64_t ppnum                   : 1;
-        uint64_t reserved_7_9            : 3;
-        uint64_t lfb_dmp                 : 1;
-        uint64_t lfb_enum                : 2;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_dbg_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
-        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
-                                                         the LFB specified by LFB_ENUM are captured
-                                                         into the L2C_LFB(0/1/2) registers.
-                                                         NOTE: Some fields of the LFB entry are unpredictable
-                                                         and dependent on usage. This is only intended to be
-                                                         used for HW debug. */
-        uint64_t reserved_7_9            : 3;
-        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines which
-                                                         PP is selected as the diagnostic PP. */
-        uint64_t reserved_5_5            : 1;
-        uint64_t set                     : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines 1-of-n targeted
-                                                         sets to act upon.
-                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
-                                                         unusable set (see UMSK* registers and Cripple mode
-                                                         fuses). */
-        uint64_t finv                    : 1;       /**< Flush-Invalidate.
-                                                         When flush-invalidate is enable (FINV=1), all STF
-                                                         (L1 store-miss) commands generated from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
-                                                         (L2C_DBG[SET]) at the index specified in the STF
-                                                         address[15:7]. If a dirty block is detected (D=1), it is
-                                                         written back to memory. The contents of the invalid
-                                                         L2 Cache line is also 'scrubbed' with the STF write data.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
-                                                         STF address[15:7] refers to the 'aliased' address.
-                                                         NOTE: An STF command with write data=ZEROES can be
-                                                         generated by SW using the Prefetch instruction with
-                                                         Hint=30d "prepare for Store", followed by a SYNCW.
-                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
-                                                         of its mask bits clear (indicates zero-fill data).
-                                                         A flush-invalidate will 'force-hit' the L2 cache at
-                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
-                                                         If the cache block is dirty, it is also written back
-                                                         to memory. The DuTag state is probed/updated as normal
-                                                         for an STF request.
-                                                         TYPICAL APPLICATIONS:
-                                                            1) L2 Tag/Data ECC SW Recovery
-                                                            2) Cache Unlocking
-                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
-                                                         a flush-invalidate operation will explicitly UNLOCK
-                                                         (L=0) the set/index specified.
-                                                         NOTE: The diagnostic PP cores can generate STF(L1 store-miss)
-                                                         commands to the L2 Cache whenever all 128 bytes in a
-                                                         block are written. SW must take this into consideration
-                                                         to avoid 'errant' Flush-Invalidates. */
-        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
-                                                         returned directly from the L2 Data Store
-                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
-                                                         command is issued from a PP determined by the
-                                                         L2C_DBG[PPNUM] field. The selected set# is determined
-                                                         by the L2C_DBG[SET] field, and the index is determined
-                                                         from the address[15:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state. */
-        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
-                                                         is returned on the data bus starting at +32(and +96) bytes
-                                                         offset from the beginning of cacheline when an LDD
-                                                         (L1 load-miss) command is issued from a PP determined by
-                                                         the L2C_DBG[PPNUM] field.
-                                                         The selected L2 set# is determined by the L2C_DBG[SET]
-                                                         field, and the L2 index is determined from the
-                                                         phys_addr[15:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: The diagnostic PP should issue a d-stream load
-                                                         to an aligned cacheline+0x20(+0x60) in order to have the
-                                                         return VDLUTAG information (in OW2/OW6) written directly
-                                                         into the proper PP register. The diagnostic PP should also
-                                                         flush it's local L1 cache after use(to ensure data
-                                                         coherency).
-                                                         NOTE: The position of the VDLUTAG data in the destination
-                                                         register is dependent on the endian mode(big/little).
-                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
-                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
-                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
-                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
-                                                         LDD(L1 load-miss) is detected from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]). */
-#else
-        uint64_t l2t                     : 1;
-        uint64_t l2d                     : 1;
-        uint64_t finv                    : 1;
-        uint64_t set                     : 2;
-        uint64_t reserved_5_5            : 1;
-        uint64_t ppnum                   : 1;
-        uint64_t reserved_7_9            : 3;
-        uint64_t lfb_dmp                 : 1;
-        uint64_t lfb_enum                : 3;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_dbg_s                cn38xx;
-    struct cvmx_l2c_dbg_s                cn38xxp2;
-    struct cvmx_l2c_dbg_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
-        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
-                                                         the LFB specified by LFB_ENUM[2:0] are captured
-                                                         into the L2C_LFB(0/1/2) registers.
-                                                         NOTE: Some fields of the LFB entry are unpredictable
-                                                         and dependent on usage. This is only intended to be
-                                                         used for HW debug. */
-        uint64_t reserved_7_9            : 3;
-        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines which 1-of-2
-                                                         PPs is selected as the diagnostic PP. */
-        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines 1-of-n targeted
-                                                         sets to act upon.
-                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
-                                                         unusable set (see UMSK* registers and Cripple mode
-                                                         fuses). */
-        uint64_t finv                    : 1;       /**< Flush-Invalidate.
-                                                         When flush-invalidate is enable (FINV=1), all STF
-                                                         (L1 store-miss) commands generated from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
-                                                         (L2C_DBG[SET]) at the index specified in the STF
-                                                         address[13:7]. If a dirty block is detected (D=1), it is
-                                                         written back to memory. The contents of the invalid
-                                                         L2 Cache line is also 'scrubbed' with the STF write data.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
-                                                         STF address[13:7] refers to the 'aliased' address.
-                                                         NOTE: An STF command with write data=ZEROES can be
-                                                         generated by SW using the Prefetch instruction with
-                                                         Hint=30d "prepare for Store", followed by a SYNCW.
-                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
-                                                         of its mask bits clear (indicates zero-fill data).
-                                                         A flush-invalidate will 'force-hit' the L2 cache at
-                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
-                                                         If the cache block is dirty, it is also written back
-                                                         to memory. The DuTag state is probed/updated as normal
-                                                         for an STF request.
-                                                         TYPICAL APPLICATIONS:
-                                                            1) L2 Tag/Data ECC SW Recovery
-                                                            2) Cache Unlocking
-                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
-                                                         a flush-invalidate operation will explicitly UNLOCK
-                                                         (L=0) the set/index specified.
-                                                         NOTE: The diagnostic PP cores can generate STF
-                                                         commands to the L2 Cache whenever all 128 bytes in a
-                                                         block are written. SW must take this into consideration
-                                                         to avoid 'errant' Flush-Invalidates. */
-        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
-                                                         returned directly from the L2 Data Store
-                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
-                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
-                                                         field. The selected set# is determined by the
-                                                         L2C_DBG[SET] field, and the index is determined
-                                                         from the address[13:7] associated with the LDD
-                                                         command.
-                                                         This 'force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state. */
-        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:14]]
-                                                         is returned on the data bus starting at +32(and +96) bytes
-                                                         offset from the beginning of cacheline when an LDD
-                                                         (L1 load-miss) command is issued from a PP determined by
-                                                         the L2C_DBG[PPNUM] field.
-                                                         The selected L2 set# is determined by the L2C_DBG[SET]
-                                                         field, and the L2 index is determined from the
-                                                         phys_addr[13:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: The diagnostic PP should issue a d-stream load
-                                                         to an aligned cacheline+0x20(+0x60) in order to have the
-                                                         return VDLUTAG information (in OW2/OW6) written directly
-                                                         into the proper PP register. The diagnostic PP should also
-                                                         flush it's local L1 cache after use(to ensure data
-                                                         coherency).
-                                                         NOTE: The position of the VDLUTAG data in the destination
-                                                         register is dependent on the endian mode(big/little).
-                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
-                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
-                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
-                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
-                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
-#else
-        uint64_t l2t                     : 1;
-        uint64_t l2d                     : 1;
-        uint64_t finv                    : 1;
-        uint64_t set                     : 3;
-        uint64_t ppnum                   : 1;
-        uint64_t reserved_7_9            : 3;
-        uint64_t lfb_dmp                 : 1;
-        uint64_t lfb_enum                : 3;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_dbg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
-        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
-                                                         the LFB specified by LFB_ENUM[2:0] are captured
-                                                         into the L2C_LFB(0/1/2) registers.
-                                                         NOTE: Some fields of the LFB entry are unpredictable
-                                                         and dependent on usage. This is only intended to be
-                                                         used for HW debug. */
-        uint64_t reserved_8_9            : 2;
-        uint64_t ppnum                   : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines which 1-of-4
-                                                         PPs is selected as the diagnostic PP. */
-        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
-                                                         is enabled, this field determines 1-of-n targeted
-                                                         sets to act upon.
-                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
-                                                         unusable set (see UMSK* registers and Cripple mode
-                                                         fuses). */
-        uint64_t finv                    : 1;       /**< Flush-Invalidate.
-                                                         When flush-invalidate is enable (FINV=1), all STF
-                                                         (L1 store-miss) commands generated from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
-                                                         (L2C_DBG[SET]) at the index specified in the STF
-                                                         address[15:7]. If a dirty block is detected (D=1), it is
-                                                         written back to memory. The contents of the invalid
-                                                         L2 Cache line is also 'scrubbed' with the STF write data.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
-                                                         STF address[15:7] refers to the 'aliased' address.
-                                                         NOTE: An STF command with write data=ZEROES can be
-                                                         generated by SW using the Prefetch instruction with
-                                                         Hint=30d "prepare for Store", followed by a SYNCW.
-                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
-                                                         of its mask bits clear (indicates zero-fill data).
-                                                         A flush-invalidate will 'force-hit' the L2 cache at
-                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
-                                                         If the cache block is dirty, it is also written back
-                                                         to memory. The DuTag state is probed/updated as normal
-                                                         for an STF request.
-                                                         TYPICAL APPLICATIONS:
-                                                            1) L2 Tag/Data ECC SW Recovery
-                                                            2) Cache Unlocking
-                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
-                                                         a flush-invalidate operation will explicitly UNLOCK
-                                                         (L=0) the set/index specified.
-                                                         NOTE: The diagnostic PP cores can generate STF
-                                                         commands to the L2 Cache whenever all 128 bytes in a
-                                                         block are written. SW must take this into consideration
-                                                         to avoid 'errant' Flush-Invalidates. */
-        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
-                                                         returned directly from the L2 Data Store
-                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
-                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
-                                                         field. The selected set# is determined by the
-                                                         L2C_DBG[SET] field, and the index is determined
-                                                         from the address[15:7] associated with the LDD
-                                                         command.
-                                                         This 'force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state. */
-        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
-                                                         is returned on the data bus starting at +32(and +96) bytes
-                                                         offset from the beginning of cacheline when an LDD
-                                                         (L1 load-miss) command is issued from a PP determined by
-                                                         the L2C_DBG[PPNUM] field.
-                                                         The selected L2 set# is determined by the L2C_DBG[SET]
-                                                         field, and the L2 index is determined from the
-                                                         phys_addr[15:7] associated with the LDD command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: The diagnostic PP should issue a d-stream load
-                                                         to an aligned cacheline+0x20(+0x60) in order to have the
-                                                         return VDLUTAG information (in OW2/OW6) written directly
-                                                         into the proper PP register. The diagnostic PP should also
-                                                         flush it's local L1 cache after use(to ensure data
-                                                         coherency).
-                                                         NOTE: The position of the VDLUTAG data in the destination
-                                                         register is dependent on the endian mode(big/little).
-                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
-                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
-                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
-                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
-                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
-#else
-        uint64_t l2t                     : 1;
-        uint64_t l2d                     : 1;
-        uint64_t finv                    : 1;
-        uint64_t set                     : 3;
-        uint64_t ppnum                   : 2;
-        uint64_t reserved_8_9            : 2;
-        uint64_t lfb_dmp                 : 1;
-        uint64_t lfb_enum                : 3;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn52xx;
-    struct cvmx_l2c_dbg_cn52xx           cn52xxp1;
-    struct cvmx_l2c_dbg_s                cn56xx;
-    struct cvmx_l2c_dbg_s                cn56xxp1;
-    struct cvmx_l2c_dbg_s                cn58xx;
-    struct cvmx_l2c_dbg_s                cn58xxp1;
-} cvmx_l2c_dbg_t;
-
-
-/**
- * cvmx_l2c_dut
- *
- * L2C_DUT = L2C DUTAG Register
- * 
- * Description: L2C Duplicate Tag State Register
- *
- * Notes:
- * (1) When using the L2T, L2D or FINV Debug probe feature, an LDD command issued by the diagnostic PP
- *     WILL NOT update the DuTags.
- * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one enabled at a time).
- * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
- *     dirty data to memory to maintain coherency. (A side effect of FINV is that an LDD L2 fill is
- *     launched which fills data into the L2 DS).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_dut_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dtena                   : 1;       /**< DuTag Diagnostic read enable.
-                                                         When L2C_DUT[DTENA]=1, all LDD(L1 load-miss)
-                                                         commands issued from the diagnostic PP
-                                                         (L2C_DBG[PPNUM]) will capture the DuTag state (V|L1TAG)
-                                                         of the PP#(specified in the LDD address[29:26] into
-                                                         the L2C_DUT CSR register. This allows the diagPP to
-                                                         read ALL DuTags (from any PP).
-                                                         The DuTag Set# to capture is extracted from the LDD
-                                                         address[25:20]. The diagnostic PP would issue the
-                                                         LDD then read the L2C_DUT register (one at a time).
-                                                         This LDD 'L2 force-hit' will NOT alter the current L2
-                                                         Tag State OR the DuTag state.
-                                                         NOTE: For O9N the DuTag SIZE has doubled (to 16KB)
-                                                         where each DuTag is organized as 2x 64-way entries.
-                                                         The LDD address[7] determines which 1(of-2) internal
-                                                         64-ways to select.
-                                                         The fill data is returned directly from the L2 Data
-                                                         Store(regardless of hit/miss) when an LDD command
-                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
-                                                         field. The selected L2 Set# is determined by the
-                                                         L2C_DBG[SET] field, and the index is determined
-                                                         from the address[17:7] associated with the LDD
-                                                         command.
-                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
-                                                         state OR the DuTag state.
-                                                         NOTE: In order for the DiagPP to generate an LDD command
-                                                         to the L2C, it must first force an L1 Dcache flush. */
-        uint64_t reserved_30_30          : 1;
-        uint64_t dt_vld                  : 1;       /**< Duplicate L1 Tag Valid bit latched in for previous
-                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
-        uint64_t dt_tag                  : 29;      /**< Duplicate L1 Tag[35:7] latched in for previous
-                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
-#else
-        uint64_t dt_tag                  : 29;
-        uint64_t dt_vld                  : 1;
-        uint64_t reserved_30_30          : 1;
-        uint64_t dtena                   : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_dut_s                cn30xx;
-    struct cvmx_l2c_dut_s                cn31xx;
-    struct cvmx_l2c_dut_s                cn38xx;
-    struct cvmx_l2c_dut_s                cn38xxp2;
-    struct cvmx_l2c_dut_s                cn50xx;
-    struct cvmx_l2c_dut_s                cn52xx;
-    struct cvmx_l2c_dut_s                cn52xxp1;
-    struct cvmx_l2c_dut_s                cn56xx;
-    struct cvmx_l2c_dut_s                cn56xxp1;
-    struct cvmx_l2c_dut_s                cn58xx;
-    struct cvmx_l2c_dut_s                cn58xxp1;
-} cvmx_l2c_dut_t;
-
-
-/**
- * cvmx_l2c_grpwrr0
- *
- * L2C_GRPWRR0 = L2C PP Weighted Round \#0 Register
- * 
- * Description: Defines Weighted rounds(32) for Group PLC0,PLC1
- *
- * Notes:
- * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
- * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_grpwrr0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t plc1rmsk                : 32;      /**< PLC1 Group#1 Weighted Round Mask
-                                                         Each bit represents 1 of 32 rounds
-                                                         for Group \#1's participation. When a 'round' bit is
-                                                         set, Group#1 is 'masked' and DOES NOT participate.
-                                                         When a 'round' bit is clear, Group#1 WILL
-                                                         participate in the arbitration for this round. */
-        uint64_t plc0rmsk                : 32;      /**< PLC Group#0 Weighted Round Mask
-                                                         Each bit represents 1 of 32 rounds
-                                                         for Group \#0's participation. When a 'round' bit is
-                                                         set, Group#0 is 'masked' and DOES NOT participate.
-                                                         When a 'round' bit is clear, Group#0 WILL
-                                                         participate in the arbitration for this round. */
-#else
-        uint64_t plc0rmsk                : 32;
-        uint64_t plc1rmsk                : 32;
-#endif
-    } s;
-    struct cvmx_l2c_grpwrr0_s            cn52xx;
-    struct cvmx_l2c_grpwrr0_s            cn52xxp1;
-    struct cvmx_l2c_grpwrr0_s            cn56xx;
-    struct cvmx_l2c_grpwrr0_s            cn56xxp1;
-} cvmx_l2c_grpwrr0_t;
-
-
-/**
- * cvmx_l2c_grpwrr1
- *
- * L2C_GRPWRR1 = L2C PP Weighted Round \#1 Register
- * 
- * Description: Defines Weighted Rounds(32) for Group PLC2,ILC
- *
- * Notes:
- * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
- * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_grpwrr1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t ilcrmsk                 : 32;      /**< ILC (IOB) Weighted Round Mask
-                                                         Each bit represents 1 of 32 rounds
-                                                         for IOB participation. When a 'round' bit is
-                                                         set, IOB is 'masked' and DOES NOT participate.
-                                                         When a 'round' bit is clear, IOB WILL
-                                                         participate in the arbitration for this round. */
-        uint64_t plc2rmsk                : 32;      /**< PLC Group#2 Weighted Round Mask
-                                                         Each bit represents 1 of 32 rounds
-                                                         for Group \#2's participation. When a 'round' bit is
-                                                         set, Group#2 is 'masked' and DOES NOT participate.
-                                                         When a 'round' bit is clear, Group#2 WILL
-                                                         participate in the arbitration for this round. */
-#else
-        uint64_t plc2rmsk                : 32;
-        uint64_t ilcrmsk                 : 32;
-#endif
-    } s;
-    struct cvmx_l2c_grpwrr1_s            cn52xx;
-    struct cvmx_l2c_grpwrr1_s            cn52xxp1;
-    struct cvmx_l2c_grpwrr1_s            cn56xx;
-    struct cvmx_l2c_grpwrr1_s            cn56xxp1;
-} cvmx_l2c_grpwrr1_t;
-
-
-/**
- * cvmx_l2c_int_en
- *
- * L2C_INT_EN = L2C Global Interrupt Enable Register
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t lck2ena                 : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
-                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA2] */
-        uint64_t lckena                  : 1;       /**< L2 Tag Lock Error Interrupt Enable bit
-                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA] */
-        uint64_t l2ddeden                : 1;       /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
-                                                         When set, allows interrupts to be reported on double bit
-                                                         (uncorrectable) errors from the L2 Data Arrays.
-                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_INTENA] */
-        uint64_t l2dsecen                : 1;       /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
-                                                         When set, allows interrupts to be reported on single bit
-                                                         (correctable) errors from the L2 Data Arrays.
-                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_INTENA] */
-        uint64_t l2tdeden                : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_INTENA] */
-        uint64_t l2tsecen                : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays.
-                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_INTENA] */
-        uint64_t oob3en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#3 */
-        uint64_t oob2en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#2 */
-        uint64_t oob1en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#1 */
-#else
-        uint64_t oob1en                  : 1;
-        uint64_t oob2en                  : 1;
-        uint64_t oob3en                  : 1;
-        uint64_t l2tsecen                : 1;
-        uint64_t l2tdeden                : 1;
-        uint64_t l2dsecen                : 1;
-        uint64_t l2ddeden                : 1;
-        uint64_t lckena                  : 1;
-        uint64_t lck2ena                 : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_l2c_int_en_s             cn52xx;
-    struct cvmx_l2c_int_en_s             cn52xxp1;
-    struct cvmx_l2c_int_en_s             cn56xx;
-    struct cvmx_l2c_int_en_s             cn56xxp1;
-} cvmx_l2c_int_en_t;
-
-
-/**
- * cvmx_l2c_int_stat
- *
- * L2C_INT_STAT = L2C Global Interrupt Status Register
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_int_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t lck2                    : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked.
-                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR2] */
-        uint64_t lck                     : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs).
-                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR] */
-        uint64_t l2dded                  : 1;       /**< L2D Double Error detected (DED)
-                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_ERR] */
-        uint64_t l2dsec                  : 1;       /**< L2D Single Error corrected (SEC)
-                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR] */
-        uint64_t l2tded                  : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled).
-                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_ERR] */
-        uint64_t l2tsec                  : 1;       /**< L2T Single Bit Error corrected (SEC) status
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled).
-                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR] */
-        uint64_t oob3                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#3 */
-        uint64_t oob2                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#2 */
-        uint64_t oob1                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#1 */
-#else
-        uint64_t oob1                    : 1;
-        uint64_t oob2                    : 1;
-        uint64_t oob3                    : 1;
-        uint64_t l2tsec                  : 1;
-        uint64_t l2tded                  : 1;
-        uint64_t l2dsec                  : 1;
-        uint64_t l2dded                  : 1;
-        uint64_t lck                     : 1;
-        uint64_t lck2                    : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_l2c_int_stat_s           cn52xx;
-    struct cvmx_l2c_int_stat_s           cn52xxp1;
-    struct cvmx_l2c_int_stat_s           cn56xx;
-    struct cvmx_l2c_int_stat_s           cn56xxp1;
-} cvmx_l2c_int_stat_t;
-
-
-/**
- * cvmx_l2c_lckbase
- *
- * L2C_LCKBASE = L2C LockDown Base Register
- * 
- * Description: L2C LockDown Base Register
- *
- * Notes:
- * (1) SW RESTRICTION \#1: SW must manage the L2 Data Store lockdown space such that at least 1
- *     set per cache line remains in the 'unlocked' (normal) state to allow general caching operations.
- *     If SW violates this restriction, a status bit is set (LCK_ERR) and an interrupt is posted.
- *     [this limits the total lockdown space to 7/8ths of the total L2 data store = 896KB]
- * (2) IOB initiated LDI commands are ignored (only PP initiated LDI/LDD commands are considered
- *     for lockdown).
- * (3) To 'unlock' a locked cache line, SW can use the FLUSH-INVAL CSR mechanism (see L2C_DBG[FINV]).
- * (4) LCK_ENA MUST only be activated when debug modes are disabled (L2C_DBG[L2T], L2C_DBG[L2D], L2C_DBG[FINV]).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lckbase_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t lck_base                : 27;      /**< Base Memory block address[33:7]. Specifies the
-                                                         starting address of the lockdown region. */
-        uint64_t reserved_1_3            : 3;
-        uint64_t lck_ena                 : 1;       /**< L2 Cache Lock Enable
-                                                         When the LCK_ENA=1, all LDI(I-stream Load) or
-                                                         LDD(L1 load-miss) commands issued from the
-                                                         diagnostic PP (specified by the L2C_DBG[PPNUM]),
-                                                         which fall within a predefined lockdown address
-                                                         range (specified by: [lck_base:lck_base+lck_offset])
-                                                         are LOCKED in the L2 cache. The LOCKED state is
-                                                         denoted using an explicit L2 Tag bit (L=1).
-                                                         If the LOCK request L2-Hits (on ANY SET), then data is
-                                                         returned from the L2 and the hit set is updated to the
-                                                         LOCKED state. NOTE: If the Hit Set# is outside the
-                                                         available sets for a given PP (see UMSK'x'), the
-                                                         the LOCK bit is still SET. If the programmer's intent
-                                                         is to explicitly LOCK addresses into 'available' sets,
-                                                         care must be taken to flush-invalidate the cache first
-                                                         (to avoid such situations). Not following this procedure
-                                                         can lead to LCKERR2 interrupts.
-                                                         If the LOCK request L2-Misses, a replacment set is
-                                                         chosen(from the available sets (UMSK'x').
-                                                         If the replacement set contains a dirty-victim it is
-                                                         written back to memory. Memory read data is then written
-                                                         into the replacement set, and the replacment SET is
-                                                         updated to the LOCKED state(L=1).
-                                                         NOTE: SETs that contain LOCKED addresses are
-                                                         excluded from the replacement set selection algorithm.
-                                                         NOTE: The LDD command will allocate the DuTag as normal.
-                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the address is 'aliased' first
-                                                         before being checked against the lockdown address
-                                                         range. To ensure an 'aliased' address is properly locked,
-                                                         it is recommmended that SW preload the 'aliased' locked adddress
-                                                         into the L2C_LCKBASE[LCK_BASE] register (while keeping
-                                                         L2C_LCKOFF[LCK_OFFSET]=0).
-                                                         NOTE: The OCTEON(N3) implementation only supports 16GB(MAX) of
-                                                         physical memory. Therefore, only byte address[33:0] are used
-                                                         (ie: address[35:34] are ignored). */
-#else
-        uint64_t lck_ena                 : 1;
-        uint64_t reserved_1_3            : 3;
-        uint64_t lck_base                : 27;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_l2c_lckbase_s            cn30xx;
-    struct cvmx_l2c_lckbase_s            cn31xx;
-    struct cvmx_l2c_lckbase_s            cn38xx;
-    struct cvmx_l2c_lckbase_s            cn38xxp2;
-    struct cvmx_l2c_lckbase_s            cn50xx;
-    struct cvmx_l2c_lckbase_s            cn52xx;
-    struct cvmx_l2c_lckbase_s            cn52xxp1;
-    struct cvmx_l2c_lckbase_s            cn56xx;
-    struct cvmx_l2c_lckbase_s            cn56xxp1;
-    struct cvmx_l2c_lckbase_s            cn58xx;
-    struct cvmx_l2c_lckbase_s            cn58xxp1;
-} cvmx_l2c_lckbase_t;
-
-
-/**
- * cvmx_l2c_lckoff
- *
- * L2C_LCKOFF = L2C LockDown OFFSET Register
- * 
- * Description: L2C LockDown OFFSET Register
- *
- * Notes:
- * (1) The generation of the end lockdown block address will 'wrap'.
- * (2) The minimum granularity for lockdown is 1 cache line (= 128B block)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lckoff_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t lck_offset              : 10;      /**< LockDown block Offset. Used in determining
-                                                         the ending block address of the lockdown
-                                                         region:
-                                                         End Lockdown block Address[33:7] =
-                                                         LCK_BASE[33:7]+LCK_OFFSET[9:0] */
-#else
-        uint64_t lck_offset              : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_l2c_lckoff_s             cn30xx;
-    struct cvmx_l2c_lckoff_s             cn31xx;
-    struct cvmx_l2c_lckoff_s             cn38xx;
-    struct cvmx_l2c_lckoff_s             cn38xxp2;
-    struct cvmx_l2c_lckoff_s             cn50xx;
-    struct cvmx_l2c_lckoff_s             cn52xx;
-    struct cvmx_l2c_lckoff_s             cn52xxp1;
-    struct cvmx_l2c_lckoff_s             cn56xx;
-    struct cvmx_l2c_lckoff_s             cn56xxp1;
-    struct cvmx_l2c_lckoff_s             cn58xx;
-    struct cvmx_l2c_lckoff_s             cn58xxp1;
-} cvmx_l2c_lckoff_t;
-
-
-/**
- * cvmx_l2c_lfb0
- *
- * L2C_LFB0 = L2C LFB DEBUG 0 Register
- * 
- * Description: L2C LFB Contents (Status Bits)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lfb0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
-        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
-        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
-        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
-        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
-        uint64_t inxt                    : 4;       /**< Next LFB Pointer(invalid if ITL=1) */
-        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
-        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
-        uint64_t set                     : 3;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
-        uint64_t vabnum                  : 4;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
-        uint64_t sid                     : 9;       /**< LFB Source ID */
-        uint64_t cmd                     : 4;       /**< LFB Command */
-        uint64_t vld                     : 1;       /**< LFB Valid */
-#else
-        uint64_t vld                     : 1;
-        uint64_t cmd                     : 4;
-        uint64_t sid                     : 9;
-        uint64_t vabnum                  : 4;
-        uint64_t set                     : 3;
-        uint64_t ihd                     : 1;
-        uint64_t itl                     : 1;
-        uint64_t inxt                    : 4;
-        uint64_t vam                     : 1;
-        uint64_t stcfl                   : 1;
-        uint64_t stinv                   : 1;
-        uint64_t stpnd                   : 1;
-        uint64_t stcpnd                  : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_lfb0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
-        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
-        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
-        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
-        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
-        uint64_t reserved_25_26          : 2;
-        uint64_t inxt                    : 2;       /**< Next LFB Pointer(invalid if ITL=1) */
-        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
-        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
-        uint64_t reserved_20_20          : 1;
-        uint64_t set                     : 2;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
-        uint64_t reserved_16_17          : 2;
-        uint64_t vabnum                  : 2;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
-        uint64_t sid                     : 9;       /**< LFB Source ID */
-        uint64_t cmd                     : 4;       /**< LFB Command */
-        uint64_t vld                     : 1;       /**< LFB Valid */
-#else
-        uint64_t vld                     : 1;
-        uint64_t cmd                     : 4;
-        uint64_t sid                     : 9;
-        uint64_t vabnum                  : 2;
-        uint64_t reserved_16_17          : 2;
-        uint64_t set                     : 2;
-        uint64_t reserved_20_20          : 1;
-        uint64_t ihd                     : 1;
-        uint64_t itl                     : 1;
-        uint64_t inxt                    : 2;
-        uint64_t reserved_25_26          : 2;
-        uint64_t vam                     : 1;
-        uint64_t stcfl                   : 1;
-        uint64_t stinv                   : 1;
-        uint64_t stpnd                   : 1;
-        uint64_t stcpnd                  : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_lfb0_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
-        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
-        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
-        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
-        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
-        uint64_t reserved_26_26          : 1;
-        uint64_t inxt                    : 3;       /**< Next LFB Pointer(invalid if ITL=1) */
-        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
-        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
-        uint64_t reserved_20_20          : 1;
-        uint64_t set                     : 2;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
-        uint64_t reserved_17_17          : 1;
-        uint64_t vabnum                  : 3;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
-        uint64_t sid                     : 9;       /**< LFB Source ID */
-        uint64_t cmd                     : 4;       /**< LFB Command */
-        uint64_t vld                     : 1;       /**< LFB Valid */
-#else
-        uint64_t vld                     : 1;
-        uint64_t cmd                     : 4;
-        uint64_t sid                     : 9;
-        uint64_t vabnum                  : 3;
-        uint64_t reserved_17_17          : 1;
-        uint64_t set                     : 2;
-        uint64_t reserved_20_20          : 1;
-        uint64_t ihd                     : 1;
-        uint64_t itl                     : 1;
-        uint64_t inxt                    : 3;
-        uint64_t reserved_26_26          : 1;
-        uint64_t vam                     : 1;
-        uint64_t stcfl                   : 1;
-        uint64_t stinv                   : 1;
-        uint64_t stpnd                   : 1;
-        uint64_t stcpnd                  : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_lfb0_s               cn38xx;
-    struct cvmx_l2c_lfb0_s               cn38xxp2;
-    struct cvmx_l2c_lfb0_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
-        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
-        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
-        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
-        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
-        uint64_t reserved_26_26          : 1;
-        uint64_t inxt                    : 3;       /**< Next LFB Pointer(invalid if ITL=1) */
-        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
-        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
-        uint64_t set                     : 3;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
-        uint64_t reserved_17_17          : 1;
-        uint64_t vabnum                  : 3;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
-        uint64_t sid                     : 9;       /**< LFB Source ID */
-        uint64_t cmd                     : 4;       /**< LFB Command */
-        uint64_t vld                     : 1;       /**< LFB Valid */
-#else
-        uint64_t vld                     : 1;
-        uint64_t cmd                     : 4;
-        uint64_t sid                     : 9;
-        uint64_t vabnum                  : 3;
-        uint64_t reserved_17_17          : 1;
-        uint64_t set                     : 3;
-        uint64_t ihd                     : 1;
-        uint64_t itl                     : 1;
-        uint64_t inxt                    : 3;
-        uint64_t reserved_26_26          : 1;
-        uint64_t vam                     : 1;
-        uint64_t stcfl                   : 1;
-        uint64_t stinv                   : 1;
-        uint64_t stpnd                   : 1;
-        uint64_t stcpnd                  : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_lfb0_cn50xx          cn52xx;
-    struct cvmx_l2c_lfb0_cn50xx          cn52xxp1;
-    struct cvmx_l2c_lfb0_s               cn56xx;
-    struct cvmx_l2c_lfb0_s               cn56xxp1;
-    struct cvmx_l2c_lfb0_s               cn58xx;
-    struct cvmx_l2c_lfb0_s               cn58xxp1;
-} cvmx_l2c_lfb0_t;
-
-
-/**
- * cvmx_l2c_lfb1
- *
- * L2C_LFB1 = L2C LFB DEBUG 1 Register
- * 
- * Description: L2C LFB Contents (Wait Bits)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lfb1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t dsgoing                 : 1;       /**< LFB DS Going (in flight) */
-        uint64_t bid                     : 2;       /**< LFB DS Bid# */
-        uint64_t wtrsp                   : 1;       /**< LFB Waiting for RSC Response [FILL,STRSP] completion */
-        uint64_t wtdw                    : 1;       /**< LFB Waiting for DS-WR completion */
-        uint64_t wtdq                    : 1;       /**< LFB Waiting for LFB-DQ */
-        uint64_t wtwhp                   : 1;       /**< LFB Waiting for Write-Hit Partial L2 DS-WR completion */
-        uint64_t wtwhf                   : 1;       /**< LFB Waiting for Write-Hit Full L2 DS-WR completion */
-        uint64_t wtwrm                   : 1;       /**< LFB Waiting for Write-Miss L2 DS-WR completion */
-        uint64_t wtstm                   : 1;       /**< LFB Waiting for Write-Miss L2 DS-WR completion */
-        uint64_t wtrda                   : 1;       /**< LFB Waiting for Read-Miss L2 DS-WR completion */
-        uint64_t wtstdt                  : 1;       /**< LFB Waiting for all ST write Data to arrive on XMD bus */
-        uint64_t wtstrsp                 : 1;       /**< LFB Waiting for ST RSC/RSD to be issued on RSP
-                                                         (with invalidates) */
-        uint64_t wtstrsc                 : 1;       /**< LFB Waiting for ST RSC-Only to be issued on RSP
-                                                         (no-invalidates) */
-        uint64_t wtvtm                   : 1;       /**< LFB Waiting for Victim Read L2 DS-RD completion */
-        uint64_t wtmfl                   : 1;       /**< LFB Waiting for Memory Fill completion to MRB */
-        uint64_t prbrty                  : 1;       /**< Probe-Retry Detected - waiting for probe completion */
-        uint64_t wtprb                   : 1;       /**< LFB Waiting for Probe */
-        uint64_t vld                     : 1;       /**< LFB Valid */
-#else
-        uint64_t vld                     : 1;
-        uint64_t wtprb                   : 1;
-        uint64_t prbrty                  : 1;
-        uint64_t wtmfl                   : 1;
-        uint64_t wtvtm                   : 1;
-        uint64_t wtstrsc                 : 1;
-        uint64_t wtstrsp                 : 1;
-        uint64_t wtstdt                  : 1;
-        uint64_t wtrda                   : 1;
-        uint64_t wtstm                   : 1;
-        uint64_t wtwrm                   : 1;
-        uint64_t wtwhf                   : 1;
-        uint64_t wtwhp                   : 1;
-        uint64_t wtdq                    : 1;
-        uint64_t wtdw                    : 1;
-        uint64_t wtrsp                   : 1;
-        uint64_t bid                     : 2;
-        uint64_t dsgoing                 : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_l2c_lfb1_s               cn30xx;
-    struct cvmx_l2c_lfb1_s               cn31xx;
-    struct cvmx_l2c_lfb1_s               cn38xx;
-    struct cvmx_l2c_lfb1_s               cn38xxp2;
-    struct cvmx_l2c_lfb1_s               cn50xx;
-    struct cvmx_l2c_lfb1_s               cn52xx;
-    struct cvmx_l2c_lfb1_s               cn52xxp1;
-    struct cvmx_l2c_lfb1_s               cn56xx;
-    struct cvmx_l2c_lfb1_s               cn56xxp1;
-    struct cvmx_l2c_lfb1_s               cn58xx;
-    struct cvmx_l2c_lfb1_s               cn58xxp1;
-} cvmx_l2c_lfb1_t;
-
-
-/**
- * cvmx_l2c_lfb2
- *
- * L2C_LFB2 = L2C LFB DEBUG 2 Register
- * 
- * Description: L2C LFB Contents Tag/Index
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lfb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_l2c_lfb2_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t lfb_tag                 : 19;      /**< LFB TAG[33:15] */
-        uint64_t lfb_idx                 : 8;       /**< LFB IDX[14:7] */
-#else
-        uint64_t lfb_idx                 : 8;
-        uint64_t lfb_tag                 : 19;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_lfb2_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t lfb_tag                 : 17;      /**< LFB TAG[33:16] */
-        uint64_t lfb_idx                 : 10;      /**< LFB IDX[15:7] */
-#else
-        uint64_t lfb_idx                 : 10;
-        uint64_t lfb_tag                 : 17;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_lfb2_cn31xx          cn38xx;
-    struct cvmx_l2c_lfb2_cn31xx          cn38xxp2;
-    struct cvmx_l2c_lfb2_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t lfb_tag                 : 20;      /**< LFB TAG[33:14] */
-        uint64_t lfb_idx                 : 7;       /**< LFB IDX[13:7] */
-#else
-        uint64_t lfb_idx                 : 7;
-        uint64_t lfb_tag                 : 20;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_lfb2_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t lfb_tag                 : 18;      /**< LFB TAG[33:16] */
-        uint64_t lfb_idx                 : 9;       /**< LFB IDX[15:7] */
-#else
-        uint64_t lfb_idx                 : 9;
-        uint64_t lfb_tag                 : 18;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn52xx;
-    struct cvmx_l2c_lfb2_cn52xx          cn52xxp1;
-    struct cvmx_l2c_lfb2_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t lfb_tag                 : 16;      /**< LFB TAG[33:18] */
-        uint64_t lfb_idx                 : 11;      /**< LFB IDX[17:7] */
-#else
-        uint64_t lfb_idx                 : 11;
-        uint64_t lfb_tag                 : 16;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn56xx;
-    struct cvmx_l2c_lfb2_cn56xx          cn56xxp1;
-    struct cvmx_l2c_lfb2_cn56xx          cn58xx;
-    struct cvmx_l2c_lfb2_cn56xx          cn58xxp1;
-} cvmx_l2c_lfb2_t;
-
-
-/**
- * cvmx_l2c_lfb3
- *
- * L2C_LFB3 = L2C LFB DEBUG 3 Register
- * 
- * Description: LFB High Water Mark Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_lfb3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
-                                                         When clear, all STP/C(store partials) will take 2 cycles
-                                                         to complete (power-on default).
-                                                         When set, all STP/C(store partials) will take 4 cycles
-                                                         to complete.
-                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t lfb_hwm                 : 4;       /**< LFB High Water Mark
-                                                         Determines \#of LFB Entries in use before backpressure
-                                                         is asserted.
-                                                            HWM=0:   1 LFB Entry available
-                                                                       - ...
-                                                            HWM=15: 16 LFB Entries available
-                                                         *** NOTE: PASS2 Addition */
-#else
-        uint64_t lfb_hwm                 : 4;
-        uint64_t stpartdis               : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_l2c_lfb3_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
-                                                         When clear, all STP/C(store partials) will take 2 cycles
-                                                         to complete (power-on default).
-                                                         When set, all STP/C(store partials) will take 4 cycles
-                                                         to complete.
-                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
-        uint64_t reserved_2_3            : 2;
-        uint64_t lfb_hwm                 : 2;       /**< LFB High Water Mark
-                                                         Determines \#of LFB Entries in use before backpressure
-                                                         is asserted.
-                                                            HWM=0:   1 LFB Entry available
-                                                                       - ...
-                                                            HWM=3:   4 LFB Entries available */
-#else
-        uint64_t lfb_hwm                 : 2;
-        uint64_t reserved_2_3            : 2;
-        uint64_t stpartdis               : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_lfb3_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
-                                                         When clear, all STP/C(store partials) will take 2 cycles
-                                                         to complete (power-on default).
-                                                         When set, all STP/C(store partials) will take 4 cycles
-                                                         to complete.
-                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
-        uint64_t reserved_3_3            : 1;
-        uint64_t lfb_hwm                 : 3;       /**< LFB High Water Mark
-                                                         Determines \#of LFB Entries in use before backpressure
-                                                         is asserted.
-                                                            HWM=0:   1 LFB Entry available
-                                                                       - ...
-                                                            HWM=7:   8 LFB Entries available */
-#else
-        uint64_t lfb_hwm                 : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t stpartdis               : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_lfb3_s               cn38xx;
-    struct cvmx_l2c_lfb3_s               cn38xxp2;
-    struct cvmx_l2c_lfb3_cn31xx          cn50xx;
-    struct cvmx_l2c_lfb3_cn31xx          cn52xx;
-    struct cvmx_l2c_lfb3_cn31xx          cn52xxp1;
-    struct cvmx_l2c_lfb3_s               cn56xx;
-    struct cvmx_l2c_lfb3_s               cn56xxp1;
-    struct cvmx_l2c_lfb3_s               cn58xx;
-    struct cvmx_l2c_lfb3_s               cn58xxp1;
-} cvmx_l2c_lfb3_t;
-
-
-/**
- * cvmx_l2c_oob
- *
- * L2C_OOB = L2C Out of Bounds Global Enables
- * 
- * Description: Defines DMA "Out of Bounds" global enables.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_oob_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dwbena                  : 1;       /**< DMA Out of Bounds Range Checker for DMA DWB
-                                                         commands (Don't WriteBack).
-                                                         When enabled, any DMA DWB commands which hit 1-of-3
-                                                         out of bounds regions will be logged into
-                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
-                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
-                                                         is enabled, an interrupt will also be reported. */
-        uint64_t stena                   : 1;       /**< DMA Out of Bounds Range Checker for DMA store
-                                                         commands (STF/P/T).
-                                                         When enabled, any DMA store commands (STF/P/T) which
-                                                         hit 1-of-3 out of bounds regions will be logged into
-                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
-                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
-                                                         is enabled, an interrupt will also be reported. */
-#else
-        uint64_t stena                   : 1;
-        uint64_t dwbena                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_l2c_oob_s                cn52xx;
-    struct cvmx_l2c_oob_s                cn52xxp1;
-    struct cvmx_l2c_oob_s                cn56xx;
-    struct cvmx_l2c_oob_s                cn56xxp1;
-} cvmx_l2c_oob_t;
-
-
-/**
- * cvmx_l2c_oob1
- *
- * L2C_OOB1 = L2C Out of Bounds Range Checker
- * 
- * Description: Defines DMA "Out of Bounds" region \#1. If a DMA initiated write transaction generates an address
- * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_oob1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
-                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
-                                                         DMA cacheline address.
-                                                         (addr[33:7] = full cacheline address captured)
-                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB1]
-                                                         is cleared. */
-        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
-                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
-                                                         type of DMA command.
-                                                          - 0: ST* (STF/P/T)
-                                                          - 1: DWB (Don't WriteBack)
-                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB1]
-                                                         is cleared. */
-        uint64_t reserved_34_35          : 2;
-        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
-                                                         (1MB granularity) */
-        uint64_t reserved_14_19          : 6;
-        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
-                                                         (1MB granularity)
-                                                         Example: 0: 0MB / 1: 1MB
-                                                         The range check is for:
-                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
-                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
-                                                         the 34bit ending bounds address. */
-#else
-        uint64_t size                    : 14;
-        uint64_t reserved_14_19          : 6;
-        uint64_t sadr                    : 14;
-        uint64_t reserved_34_35          : 2;
-        uint64_t fsrc                    : 1;
-        uint64_t fadr                    : 27;
-#endif
-    } s;
-    struct cvmx_l2c_oob1_s               cn52xx;
-    struct cvmx_l2c_oob1_s               cn52xxp1;
-    struct cvmx_l2c_oob1_s               cn56xx;
-    struct cvmx_l2c_oob1_s               cn56xxp1;
-} cvmx_l2c_oob1_t;
-
-
-/**
- * cvmx_l2c_oob2
- *
- * L2C_OOB2 = L2C Out of Bounds Range Checker
- * 
- * Description: Defines DMA "Out of Bounds" region \#2. If a DMA initiated write transaction generates an address
- * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_oob2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
-                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
-                                                         DMA cacheline address.
-                                                         (addr[33:7] = full cacheline address captured)
-                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB2]
-                                                         is cleared. */
-        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
-                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
-                                                         type of DMA command.
-                                                          - 0: ST* (STF/P/T)
-                                                          - 1: DWB (Don't WriteBack)
-                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB2]
-                                                         is cleared. */
-        uint64_t reserved_34_35          : 2;
-        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
-                                                         (1MB granularity) */
-        uint64_t reserved_14_19          : 6;
-        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
-                                                         (1MB granularity)
-                                                         Example: 0: 0MB / 1: 1MB
-                                                         The range check is for:
-                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
-                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
-                                                         the 34bit ending bounds address. */
-#else
-        uint64_t size                    : 14;
-        uint64_t reserved_14_19          : 6;
-        uint64_t sadr                    : 14;
-        uint64_t reserved_34_35          : 2;
-        uint64_t fsrc                    : 1;
-        uint64_t fadr                    : 27;
-#endif
-    } s;
-    struct cvmx_l2c_oob2_s               cn52xx;
-    struct cvmx_l2c_oob2_s               cn52xxp1;
-    struct cvmx_l2c_oob2_s               cn56xx;
-    struct cvmx_l2c_oob2_s               cn56xxp1;
-} cvmx_l2c_oob2_t;
-
-
-/**
- * cvmx_l2c_oob3
- *
- * L2C_OOB3 = L2C Out of Bounds Range Checker
- * 
- * Description: Defines DMA "Out of Bounds" region \#3. If a DMA initiated write transaction generates an address
- * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_oob3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
-                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
-                                                         DMA cacheline address.
-                                                         (addr[33:7] = full cacheline address captured)
-                                                         NOTE: FADR is locked down until L2C_INT_STAT[00B3]
-                                                         is cleared. */
-        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
-                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
-                                                         type of DMA command.
-                                                          - 0: ST* (STF/P/T)
-                                                          - 1: DWB (Don't WriteBack)
-                                                         NOTE: FSRC is locked down until L2C_INT_STAT[00B3]
-                                                         is cleared. */
-        uint64_t reserved_34_35          : 2;
-        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
-                                                         (1MB granularity) */
-        uint64_t reserved_14_19          : 6;
-        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
-                                                         (1MB granularity)
-                                                         Example: 0: 0MB / 1: 1MB
-                                                         The range check is for:
-                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
-                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
-                                                         the 34bit ending bounds address. */
-#else
-        uint64_t size                    : 14;
-        uint64_t reserved_14_19          : 6;
-        uint64_t sadr                    : 14;
-        uint64_t reserved_34_35          : 2;
-        uint64_t fsrc                    : 1;
-        uint64_t fadr                    : 27;
-#endif
-    } s;
-    struct cvmx_l2c_oob3_s               cn52xx;
-    struct cvmx_l2c_oob3_s               cn52xxp1;
-    struct cvmx_l2c_oob3_s               cn56xx;
-    struct cvmx_l2c_oob3_s               cn56xxp1;
-} cvmx_l2c_oob3_t;
-
-
-/**
- * cvmx_l2c_pfc#
- *
- * L2C_PFC0 = L2 Performance Counter \#0
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_pfcx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t pfcnt0                  : 36;      /**< Performance Counter \#0 */
-#else
-        uint64_t pfcnt0                  : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_l2c_pfcx_s               cn30xx;
-    struct cvmx_l2c_pfcx_s               cn31xx;
-    struct cvmx_l2c_pfcx_s               cn38xx;
-    struct cvmx_l2c_pfcx_s               cn38xxp2;
-    struct cvmx_l2c_pfcx_s               cn50xx;
-    struct cvmx_l2c_pfcx_s               cn52xx;
-    struct cvmx_l2c_pfcx_s               cn52xxp1;
-    struct cvmx_l2c_pfcx_s               cn56xx;
-    struct cvmx_l2c_pfcx_s               cn56xxp1;
-    struct cvmx_l2c_pfcx_s               cn58xx;
-    struct cvmx_l2c_pfcx_s               cn58xxp1;
-} cvmx_l2c_pfcx_t;
-
-
-/**
- * cvmx_l2c_pfctl
- *
- * L2C_PFCTL = L2 Performance Counter Control Register
- * 
- * Description: Controls the actions of the 4 Performance Counters
- *
- * Notes:
- * - There are four 36b performance counter registers which can simultaneously count events.
- * Each Counter's event is programmably selected via the corresponding CNTxSEL field:
- *       CNTxSEL[5:0]    Event
- *    -----------------+-----------------------
- *             0       | Cycles
- *             1       | L2 Instruction Miss
- *             2       | L2 Instruction Hit
- *             3       | L2 Data Miss
- *             4       | L2 Data Hit
- *             5       | L2 Miss (I/D)
- *             6       | L2 Hit (I/D)
- *             7       | L2 Victim Buffer Hit (Retry Probe)
- *             8       | LFB-NQ Index Conflict
- *             9       | L2 Tag Probe (issued - could be VB-Retried)
- *            10       | L2 Tag Update (completed - note: some CMD types do not update)
- *            11       | L2 Tag Probe Completed (beyond VB-RTY window)
- *            12       | L2 Tag Dirty Victim
- *            13       | L2 Data Store NOP
- *            14       | L2 Data Store READ
- *            15       | L2 Data Store WRITE
- *            16       | Memory Fill Data valid (1 strobe/32B)
- *            17       | Memory Write Request
- *            18       | Memory Read Request
- *            19       | Memory Write Data valid (1 strobe/32B)
- *            20       | XMC NOP (XMC Bus Idle)
- *            21       | XMC LDT (Load-Through Request)
- *            22       | XMC LDI (L2 Load I-Stream Request)
- *            23       | XMC LDD (L2 Load D-stream Request)
- *            24       | XMC STF (L2 Store Full cacheline Request)
- *            25       | XMC STT (L2 Store Through Request)
- *            26       | XMC STP (L2 Store Partial Request)
- *            27       | XMC STC (L2 Store Conditional Request)
- *            28       | XMC DWB (L2 Don't WriteBack Request)
- *            29       | XMC PL2 (L2 Prefetch Request)
- *            30       | XMC PSL1 (L1 Prefetch Request)
- *            31       | XMC IOBLD
- *            32       | XMC IOBST
- *            33       | XMC IOBDMA
- *            34       | XMC IOBRSP
- *            35       | XMD Bus valid (all)
- *            36       | XMD Bus valid (DST=L2C) Memory Data
- *            37       | XMD Bus valid (DST=IOB) REFL Data
- *            38       | XMD Bus valid (DST=PP) IOBRSP Data
- *            39       | RSC NOP
- *            40       | RSC STDN
- *            41       | RSC FILL
- *            42       | RSC REFL
- *            43       | RSC STIN
- *            44       | RSC SCIN
- *            45       | RSC SCFL
- *            46       | RSC SCDN
- *            47       | RSD Data Valid
- *            48       | RSD Data Valid (FILL)
- *            49       | RSD Data Valid (STRSP)
- *            50       | RSD Data Valid (REFL)
- *            51       | LRF-REQ (LFB-NQ)
- *            52       | DT RD-ALLOC (LDD/PSL1 Commands)
- *            53       | DT WR-INVAL (ST* Commands)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_pfctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t cnt3rdclr               : 1;       /**< Performance Counter 3 Read Clear
-                                                         When set, all CSR reads of the L2C_PFC3
-                                                         register will auto-clear the counter. This allows
-                                                         SW to maintain 'cumulative' counters in SW.
-                                                         NOTE: If the CSR read occurs in the same cycle as
-                                                         the 'event' to be counted, the counter will
-                                                         properly reflect the event.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t cnt2rdclr               : 1;       /**< Performance Counter 2 Read Clear
-                                                         When set, all CSR reads of the L2C_PFC2
-                                                         register will auto-clear the counter. This allows
-                                                         SW to maintain 'cumulative' counters in SW.
-                                                         NOTE: If the CSR read occurs in the same cycle as
-                                                         the 'event' to be counted, the counter will
-                                                         properly reflect the event.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t cnt1rdclr               : 1;       /**< Performance Counter 1 Read Clear
-                                                         When set, all CSR reads of the L2C_PFC1
-                                                         register will auto-clear the counter. This allows
-                                                         SW to maintain 'cumulative' counters in SW.
-                                                         NOTE: If the CSR read occurs in the same cycle as
-                                                         the 'event' to be counted, the counter will
-                                                         properly reflect the event.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t cnt0rdclr               : 1;       /**< Performance Counter 0 Read Clear
-                                                         When set, all CSR reads of the L2C_PFC0
-                                                         register will 'auto-clear' the counter. This allows
-                                                         SW to maintain accurate 'cumulative' counters.
-                                                         NOTE: If the CSR read occurs in the same cycle as
-                                                         the 'event' to be counted, the counter will
-                                                         properly reflect the event.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t cnt3ena                 : 1;       /**< Performance Counter 3 Enable
-                                                         When this bit is set, the performance counter
-                                                         is enabled. */
-        uint64_t cnt3clr                 : 1;       /**< Performance Counter 3 Clear
-                                                         When the CSR write occurs, if this bit is set,
-                                                         the performance counter is cleared. Otherwise,
-                                                         it will resume counting from its current value. */
-        uint64_t cnt3sel                 : 6;       /**< Performance Counter 3 Event Selector
-                                                         (see list of selectable events to count in NOTES) */
-        uint64_t cnt2ena                 : 1;       /**< Performance Counter 2 Enable
-                                                         When this bit is set, the performance counter
-                                                         is enabled. */
-        uint64_t cnt2clr                 : 1;       /**< Performance Counter 2 Clear
-                                                         When the CSR write occurs, if this bit is set,
-                                                         the performance counter is cleared. Otherwise,
-                                                         it will resume counting from its current value. */
-        uint64_t cnt2sel                 : 6;       /**< Performance Counter 2 Event Selector
-                                                         (see list of selectable events to count in NOTES) */
-        uint64_t cnt1ena                 : 1;       /**< Performance Counter 1 Enable
-                                                         When this bit is set, the performance counter
-                                                         is enabled. */
-        uint64_t cnt1clr                 : 1;       /**< Performance Counter 1 Clear
-                                                         When the CSR write occurs, if this bit is set,
-                                                         the performance counter is cleared. Otherwise,
-                                                         it will resume counting from its current value. */
-        uint64_t cnt1sel                 : 6;       /**< Performance Counter 1 Event Selector
-                                                         (see list of selectable events to count in NOTES) */
-        uint64_t cnt0ena                 : 1;       /**< Performance Counter 0 Enable
-                                                         When this bit is set, the performance counter
-                                                         is enabled. */
-        uint64_t cnt0clr                 : 1;       /**< Performance Counter 0 Clear
-                                                         When the CSR write occurs, if this bit is set,
-                                                         the performance counter is cleared. Otherwise,
-                                                         it will resume counting from its current value. */
-        uint64_t cnt0sel                 : 6;       /**< Performance Counter 0 Event Selector
-                                                         (see list of selectable events to count in NOTES) */
-#else
-        uint64_t cnt0sel                 : 6;
-        uint64_t cnt0clr                 : 1;
-        uint64_t cnt0ena                 : 1;
-        uint64_t cnt1sel                 : 6;
-        uint64_t cnt1clr                 : 1;
-        uint64_t cnt1ena                 : 1;
-        uint64_t cnt2sel                 : 6;
-        uint64_t cnt2clr                 : 1;
-        uint64_t cnt2ena                 : 1;
-        uint64_t cnt3sel                 : 6;
-        uint64_t cnt3clr                 : 1;
-        uint64_t cnt3ena                 : 1;
-        uint64_t cnt0rdclr               : 1;
-        uint64_t cnt1rdclr               : 1;
-        uint64_t cnt2rdclr               : 1;
-        uint64_t cnt3rdclr               : 1;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_l2c_pfctl_s              cn30xx;
-    struct cvmx_l2c_pfctl_s              cn31xx;
-    struct cvmx_l2c_pfctl_s              cn38xx;
-    struct cvmx_l2c_pfctl_s              cn38xxp2;
-    struct cvmx_l2c_pfctl_s              cn50xx;
-    struct cvmx_l2c_pfctl_s              cn52xx;
-    struct cvmx_l2c_pfctl_s              cn52xxp1;
-    struct cvmx_l2c_pfctl_s              cn56xx;
-    struct cvmx_l2c_pfctl_s              cn56xxp1;
-    struct cvmx_l2c_pfctl_s              cn58xx;
-    struct cvmx_l2c_pfctl_s              cn58xxp1;
-} cvmx_l2c_pfctl_t;
-
-
-/**
- * cvmx_l2c_ppgrp
- *
- * L2C_PPGRP = L2C PP Group Number
- * 
- * Description: Defines the PP(Packet Processor) PLC Group \# (0,1,2)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_ppgrp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t pp11grp                 : 2;       /**< PP11 PLC Group# (0,1,2) */
-        uint64_t pp10grp                 : 2;       /**< PP10 PLC Group# (0,1,2) */
-        uint64_t pp9grp                  : 2;       /**< PP9 PLC Group# (0,1,2) */
-        uint64_t pp8grp                  : 2;       /**< PP8 PLC Group# (0,1,2) */
-        uint64_t pp7grp                  : 2;       /**< PP7 PLC Group# (0,1,2) */
-        uint64_t pp6grp                  : 2;       /**< PP6 PLC Group# (0,1,2) */
-        uint64_t pp5grp                  : 2;       /**< PP5 PLC Group# (0,1,2) */
-        uint64_t pp4grp                  : 2;       /**< PP4 PLC Group# (0,1,2) */
-        uint64_t pp3grp                  : 2;       /**< PP3 PLC Group# (0,1,2) */
-        uint64_t pp2grp                  : 2;       /**< PP2 PLC Group# (0,1,2) */
-        uint64_t pp1grp                  : 2;       /**< PP1 PLC Group# (0,1,2) */
-        uint64_t pp0grp                  : 2;       /**< PP0 PLC Group# (0,1,2) */
-#else
-        uint64_t pp0grp                  : 2;
-        uint64_t pp1grp                  : 2;
-        uint64_t pp2grp                  : 2;
-        uint64_t pp3grp                  : 2;
-        uint64_t pp4grp                  : 2;
-        uint64_t pp5grp                  : 2;
-        uint64_t pp6grp                  : 2;
-        uint64_t pp7grp                  : 2;
-        uint64_t pp8grp                  : 2;
-        uint64_t pp9grp                  : 2;
-        uint64_t pp10grp                 : 2;
-        uint64_t pp11grp                 : 2;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_l2c_ppgrp_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t pp3grp                  : 2;       /**< PP3 PLC Group# (0,1,2) */
-        uint64_t pp2grp                  : 2;       /**< PP2 PLC Group# (0,1,2) */
-        uint64_t pp1grp                  : 2;       /**< PP1 PLC Group# (0,1,2) */
-        uint64_t pp0grp                  : 2;       /**< PP0 PLC Group# (0,1,2) */
-#else
-        uint64_t pp0grp                  : 2;
-        uint64_t pp1grp                  : 2;
-        uint64_t pp2grp                  : 2;
-        uint64_t pp3grp                  : 2;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } cn52xx;
-    struct cvmx_l2c_ppgrp_cn52xx         cn52xxp1;
-    struct cvmx_l2c_ppgrp_s              cn56xx;
-    struct cvmx_l2c_ppgrp_s              cn56xxp1;
-} cvmx_l2c_ppgrp_t;
-
-
-/**
- * cvmx_l2c_spar0
- *
- * L2C_SPAR0 = L2 Set Partitioning Register (PP0-3)
- * 
- * Description: L2 Set Partitioning Register
- *
- * Notes:
- * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
- *   set for replacement.
- * - There MUST ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
- * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
- *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_spar0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t umsk3                   : 8;       /**< PP[3] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk2                   : 8;       /**< PP[2] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk1                   : 8;       /**< PP[1] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk0                   : 8;       /**< PP[0] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk0                   : 8;
-        uint64_t umsk1                   : 8;
-        uint64_t umsk2                   : 8;
-        uint64_t umsk3                   : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_spar0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t umsk0                   : 4;       /**< PP[0] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk0                   : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_spar0_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t umsk1                   : 4;       /**< PP[1] L2 'DO NOT USE' set partition mask */
-        uint64_t reserved_4_7            : 4;
-        uint64_t umsk0                   : 4;       /**< PP[0] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk0                   : 4;
-        uint64_t reserved_4_7            : 4;
-        uint64_t umsk1                   : 4;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn31xx;
-    struct cvmx_l2c_spar0_s              cn38xx;
-    struct cvmx_l2c_spar0_s              cn38xxp2;
-    struct cvmx_l2c_spar0_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t umsk1                   : 8;       /**< PP[1] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk0                   : 8;       /**< PP[0] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk0                   : 8;
-        uint64_t umsk1                   : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn50xx;
-    struct cvmx_l2c_spar0_s              cn52xx;
-    struct cvmx_l2c_spar0_s              cn52xxp1;
-    struct cvmx_l2c_spar0_s              cn56xx;
-    struct cvmx_l2c_spar0_s              cn56xxp1;
-    struct cvmx_l2c_spar0_s              cn58xx;
-    struct cvmx_l2c_spar0_s              cn58xxp1;
-} cvmx_l2c_spar0_t;
-
-
-/**
- * cvmx_l2c_spar1
- *
- * L2C_SPAR1 = L2 Set Partitioning Register (PP4-7)
- * 
- * Description: L2 Set Partitioning Register
- *
- * Notes:
- * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
- *   set for replacement.
- * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
- * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
- *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_spar1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t umsk7                   : 8;       /**< PP[7] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk6                   : 8;       /**< PP[6] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk5                   : 8;       /**< PP[5] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk4                   : 8;       /**< PP[4] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk4                   : 8;
-        uint64_t umsk5                   : 8;
-        uint64_t umsk6                   : 8;
-        uint64_t umsk7                   : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_spar1_s              cn38xx;
-    struct cvmx_l2c_spar1_s              cn38xxp2;
-    struct cvmx_l2c_spar1_s              cn56xx;
-    struct cvmx_l2c_spar1_s              cn56xxp1;
-    struct cvmx_l2c_spar1_s              cn58xx;
-    struct cvmx_l2c_spar1_s              cn58xxp1;
-} cvmx_l2c_spar1_t;
-
-
-/**
- * cvmx_l2c_spar2
- *
- * L2C_SPAR2 = L2 Set Partitioning Register (PP8-11)
- * 
- * Description: L2 Set Partitioning Register
- *
- * Notes:
- * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
- *   set for replacement.
- * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
- * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
- *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_spar2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t umsk11                  : 8;       /**< PP[11] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk10                  : 8;       /**< PP[10] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk9                   : 8;       /**< PP[9] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk8                   : 8;       /**< PP[8] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk8                   : 8;
-        uint64_t umsk9                   : 8;
-        uint64_t umsk10                  : 8;
-        uint64_t umsk11                  : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_spar2_s              cn38xx;
-    struct cvmx_l2c_spar2_s              cn38xxp2;
-    struct cvmx_l2c_spar2_s              cn56xx;
-    struct cvmx_l2c_spar2_s              cn56xxp1;
-    struct cvmx_l2c_spar2_s              cn58xx;
-    struct cvmx_l2c_spar2_s              cn58xxp1;
-} cvmx_l2c_spar2_t;
-
-
-/**
- * cvmx_l2c_spar3
- *
- * L2C_SPAR3 = L2 Set Partitioning Register (PP12-15)
- * 
- * Description: L2 Set Partitioning Register
- *
- * Notes:
- * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
- *   set for replacement.
- * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
- * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
- *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_spar3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t umsk15                  : 8;       /**< PP[15] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk14                  : 8;       /**< PP[14] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk13                  : 8;       /**< PP[13] L2 'DO NOT USE' set partition mask */
-        uint64_t umsk12                  : 8;       /**< PP[12] L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umsk12                  : 8;
-        uint64_t umsk13                  : 8;
-        uint64_t umsk14                  : 8;
-        uint64_t umsk15                  : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_l2c_spar3_s              cn38xx;
-    struct cvmx_l2c_spar3_s              cn38xxp2;
-    struct cvmx_l2c_spar3_s              cn58xx;
-    struct cvmx_l2c_spar3_s              cn58xxp1;
-} cvmx_l2c_spar3_t;
-
-
-/**
- * cvmx_l2c_spar4
- *
- * L2C_SPAR4 = L2 Set Partitioning Register (IOB)
- * 
- * Description: L2 Set Partitioning Register
- *
- * Notes:
- * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
- *   set for replacement.
- * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
- * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
- *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2c_spar4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t umskiob                 : 8;       /**< IOB L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umskiob                 : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_l2c_spar4_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t umskiob                 : 4;       /**< IOB L2 'DO NOT USE' set partition mask */
-#else
-        uint64_t umskiob                 : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_l2c_spar4_cn30xx         cn31xx;
-    struct cvmx_l2c_spar4_s              cn38xx;
-    struct cvmx_l2c_spar4_s              cn38xxp2;
-    struct cvmx_l2c_spar4_s              cn50xx;
-    struct cvmx_l2c_spar4_s              cn52xx;
-    struct cvmx_l2c_spar4_s              cn52xxp1;
-    struct cvmx_l2c_spar4_s              cn56xx;
-    struct cvmx_l2c_spar4_s              cn56xxp1;
-    struct cvmx_l2c_spar4_s              cn58xx;
-    struct cvmx_l2c_spar4_s              cn58xxp1;
-} cvmx_l2c_spar4_t;
-
-
-/**
- * cvmx_l2d_bst0
- *
- * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_bst0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_35_63          : 29;
-        uint64_t ftl                     : 1;       /**< L2C Data Store Fatal Defect(across all QUADs)
-                                                         2 or more columns were detected bad across all
-                                                         QUADs[0-3]. Please refer to individual quad failures
-                                                         for bad column = 0x7e to determine which QUAD was in
-                                                         error. */
-        uint64_t q0stat                  : 34;      /**< Bist Results for QUAD0
-                                                         Failure \#1 Status
-                                                           [16:14] bad bank
-                                                           [13:7] bad high column
-                                                           [6:0] bad low column
-                                                         Failure \#2 Status
-                                                           [33:31] bad bank
-                                                           [30:24] bad high column
-                                                           [23:17] bad low column
-                                                         NOTES: For bad high/low column reporting:
-                                                            0x7f:   No failure
-                                                            0x7e:   Fatal Defect: 2 or more bad columns
-                                                            0-0x45: Bad column
-                                                         NOTE: If there are less than 2 failures then the
-                                                            bad bank will be 0x7. */
-#else
-        uint64_t q0stat                  : 34;
-        uint64_t ftl                     : 1;
-        uint64_t reserved_35_63          : 29;
-#endif
-    } s;
-    struct cvmx_l2d_bst0_s               cn30xx;
-    struct cvmx_l2d_bst0_s               cn31xx;
-    struct cvmx_l2d_bst0_s               cn38xx;
-    struct cvmx_l2d_bst0_s               cn38xxp2;
-    struct cvmx_l2d_bst0_s               cn50xx;
-    struct cvmx_l2d_bst0_s               cn52xx;
-    struct cvmx_l2d_bst0_s               cn52xxp1;
-    struct cvmx_l2d_bst0_s               cn56xx;
-    struct cvmx_l2d_bst0_s               cn56xxp1;
-    struct cvmx_l2d_bst0_s               cn58xx;
-    struct cvmx_l2d_bst0_s               cn58xxp1;
-} cvmx_l2d_bst0_t;
-
-
-/**
- * cvmx_l2d_bst1
- *
- * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_bst1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q1stat                  : 34;      /**< Bist Results for QUAD1
-                                                         Failure \#1 Status
-                                                            [16:14] bad bank
-                                                            [13:7] bad high column
-                                                            [6:0] bad low column
-                                                          Failure \#2 Status
-                                                            [33:31] bad bank
-                                                            [30:24] bad high column
-                                                            [23:17] bad low column
-                                                          NOTES: For bad high/low column reporting:
-                                                             0x7f:   No failure
-                                                             0x7e:   Fatal Defect: 2 or more bad columns
-                                                             0-0x45: Bad column
-                                                          NOTE: If there are less than 2 failures then the
-                                                             bad bank will be 0x7. */
-#else
-        uint64_t q1stat                  : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_bst1_s               cn30xx;
-    struct cvmx_l2d_bst1_s               cn31xx;
-    struct cvmx_l2d_bst1_s               cn38xx;
-    struct cvmx_l2d_bst1_s               cn38xxp2;
-    struct cvmx_l2d_bst1_s               cn50xx;
-    struct cvmx_l2d_bst1_s               cn52xx;
-    struct cvmx_l2d_bst1_s               cn52xxp1;
-    struct cvmx_l2d_bst1_s               cn56xx;
-    struct cvmx_l2d_bst1_s               cn56xxp1;
-    struct cvmx_l2d_bst1_s               cn58xx;
-    struct cvmx_l2d_bst1_s               cn58xxp1;
-} cvmx_l2d_bst1_t;
-
-
-/**
- * cvmx_l2d_bst2
- *
- * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_bst2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q2stat                  : 34;      /**< Bist Results for QUAD2
-                                                         Failure \#1 Status
-                                                            [16:14] bad bank
-                                                            [13:7] bad high column
-                                                            [6:0] bad low column
-                                                          Failure \#2 Status
-                                                            [33:31] bad bank
-                                                            [30:24] bad high column
-                                                            [23:17] bad low column
-                                                          NOTES: For bad high/low column reporting:
-                                                             0x7f:   No failure
-                                                             0x7e:   Fatal Defect: 2 or more bad columns
-                                                             0-0x45: Bad column
-                                                          NOTE: If there are less than 2 failures then the
-                                                             bad bank will be 0x7. */
-#else
-        uint64_t q2stat                  : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_bst2_s               cn30xx;
-    struct cvmx_l2d_bst2_s               cn31xx;
-    struct cvmx_l2d_bst2_s               cn38xx;
-    struct cvmx_l2d_bst2_s               cn38xxp2;
-    struct cvmx_l2d_bst2_s               cn50xx;
-    struct cvmx_l2d_bst2_s               cn52xx;
-    struct cvmx_l2d_bst2_s               cn52xxp1;
-    struct cvmx_l2d_bst2_s               cn56xx;
-    struct cvmx_l2d_bst2_s               cn56xxp1;
-    struct cvmx_l2d_bst2_s               cn58xx;
-    struct cvmx_l2d_bst2_s               cn58xxp1;
-} cvmx_l2d_bst2_t;
-
-
-/**
- * cvmx_l2d_bst3
- *
- * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_bst3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q3stat                  : 34;      /**< Bist Results for QUAD3
-                                                         Failure \#1 Status
-                                                            [16:14] bad bank
-                                                            [13:7] bad high column
-                                                            [6:0] bad low column
-                                                          Failure \#2 Status
-                                                            [33:31] bad bank
-                                                            [30:24] bad high column
-                                                            [23:17] bad low column
-                                                          NOTES: For bad high/low column reporting:
-                                                             0x7f:   No failure
-                                                             0x7e:   Fatal Defect: 2 or more bad columns
-                                                             0-0x45: Bad column
-                                                          NOTE: If there are less than 2 failures then the
-                                                             bad bank will be 0x7. */
-#else
-        uint64_t q3stat                  : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_bst3_s               cn30xx;
-    struct cvmx_l2d_bst3_s               cn31xx;
-    struct cvmx_l2d_bst3_s               cn38xx;
-    struct cvmx_l2d_bst3_s               cn38xxp2;
-    struct cvmx_l2d_bst3_s               cn50xx;
-    struct cvmx_l2d_bst3_s               cn52xx;
-    struct cvmx_l2d_bst3_s               cn52xxp1;
-    struct cvmx_l2d_bst3_s               cn56xx;
-    struct cvmx_l2d_bst3_s               cn56xxp1;
-    struct cvmx_l2d_bst3_s               cn58xx;
-    struct cvmx_l2d_bst3_s               cn58xxp1;
-} cvmx_l2d_bst3_t;
-
-
-/**
- * cvmx_l2d_err
- *
- * L2D_ERR = L2 Data Errors
- * 
- * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t bmhclsel                : 1;       /**< L2 Bit Map Half CacheLine ECC Selector
-                                                          *** NOTE: PASS2 Addition
-                                                          When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
-                                                          which half cacheline to conditionally latch into
-                                                          the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
-                                                          is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
-                                                         - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
-                                                             be conditionally latched into the L2D_FSYN0/1 CSRs.
-                                                         - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
-                                                             be conditionally latched into
-                                                             the L2D_FSYN0/1 CSRs. */
-        uint64_t ded_err                 : 1;       /**< L2D Double Error detected (DED) */
-        uint64_t sec_err                 : 1;       /**< L2D Single Error corrected (SEC) */
-        uint64_t ded_intena              : 1;       /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
-                                                         When set, allows interrupts to be reported on double bit
-                                                         (uncorrectable) errors from the L2 Data Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
-                                                         When set, allows interrupts to be reported on single bit
-                                                         (correctable) errors from the L2 Data Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Data ECC Enable
-                                                         When set, enables 10-bit SEC/DED codeword for 128bit L2
-                                                         Data Arrays. */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t bmhclsel                : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_l2d_err_s                cn30xx;
-    struct cvmx_l2d_err_s                cn31xx;
-    struct cvmx_l2d_err_s                cn38xx;
-    struct cvmx_l2d_err_s                cn38xxp2;
-    struct cvmx_l2d_err_s                cn50xx;
-    struct cvmx_l2d_err_s                cn52xx;
-    struct cvmx_l2d_err_s                cn52xxp1;
-    struct cvmx_l2d_err_s                cn56xx;
-    struct cvmx_l2d_err_s                cn56xxp1;
-    struct cvmx_l2d_err_s                cn58xx;
-    struct cvmx_l2d_err_s                cn58xxp1;
-} cvmx_l2d_err_t;
-
-
-/**
- * cvmx_l2d_fadr
- *
- * L2D_FADR = L2 Failing Address
- * 
- * Description: L2 Data ECC SEC/DED Failing Address
- *
- * Notes:
- * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
- * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fadr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t fadru                   : 1;       /**< Failing L2 Data Store Upper Index bit(MSB) */
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t fset                    : 3;       /**< Failing SET# */
-        uint64_t fadr                    : 11;      /**< Failing L2 Data Store Lower Index bits
-                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
-                                                            [FADRU, FADR[10:1]]: cacheline index[17:7]
-                                                            FADR[0]: 1/2 cacheline index
-                                                         NOTE: FADR[1] is used to select between upper/lower 1MB
-                                                         physical L2 Data Store banks. */
-#else
-        uint64_t fadr                    : 11;
-        uint64_t fset                    : 3;
-        uint64_t fowmsk                  : 4;
-        uint64_t fadru                   : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_l2d_fadr_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t reserved_13_13          : 1;
-        uint64_t fset                    : 2;       /**< Failing SET# */
-        uint64_t reserved_9_10           : 2;
-        uint64_t fadr                    : 9;       /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
-#else
-        uint64_t fadr                    : 9;
-        uint64_t reserved_9_10           : 2;
-        uint64_t fset                    : 2;
-        uint64_t reserved_13_13          : 1;
-        uint64_t fowmsk                  : 4;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn30xx;
-    struct cvmx_l2d_fadr_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t reserved_13_13          : 1;
-        uint64_t fset                    : 2;       /**< Failing SET# */
-        uint64_t reserved_10_10          : 1;
-        uint64_t fadr                    : 10;      /**< Failing L2 Data Store Index
-                                                         (1 of 1024 = half cacheline indices) */
-#else
-        uint64_t fadr                    : 10;
-        uint64_t reserved_10_10          : 1;
-        uint64_t fset                    : 2;
-        uint64_t reserved_13_13          : 1;
-        uint64_t fowmsk                  : 4;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn31xx;
-    struct cvmx_l2d_fadr_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t fset                    : 3;       /**< Failing SET# */
-        uint64_t fadr                    : 11;      /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
-#else
-        uint64_t fadr                    : 11;
-        uint64_t fset                    : 3;
-        uint64_t fowmsk                  : 4;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn38xx;
-    struct cvmx_l2d_fadr_cn38xx          cn38xxp2;
-    struct cvmx_l2d_fadr_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t fset                    : 3;       /**< Failing SET# */
-        uint64_t reserved_8_10           : 3;
-        uint64_t fadr                    : 8;       /**< Failing L2 Data Store Lower Index bits
-                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
-                                                            FADR[7:1]: cacheline index[13:7]
-                                                            FADR[0]: 1/2 cacheline index */
-#else
-        uint64_t fadr                    : 8;
-        uint64_t reserved_8_10           : 3;
-        uint64_t fset                    : 3;
-        uint64_t fowmsk                  : 4;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn50xx;
-    struct cvmx_l2d_fadr_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
-                                                         error) */
-        uint64_t fset                    : 3;       /**< Failing SET# */
-        uint64_t reserved_10_10          : 1;
-        uint64_t fadr                    : 10;      /**< Failing L2 Data Store Lower Index bits
-                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
-                                                            FADR[9:1]: cacheline index[15:7]
-                                                            FADR[0]: 1/2 cacheline index */
-#else
-        uint64_t fadr                    : 10;
-        uint64_t reserved_10_10          : 1;
-        uint64_t fset                    : 3;
-        uint64_t fowmsk                  : 4;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn52xx;
-    struct cvmx_l2d_fadr_cn52xx          cn52xxp1;
-    struct cvmx_l2d_fadr_s               cn56xx;
-    struct cvmx_l2d_fadr_s               cn56xxp1;
-    struct cvmx_l2d_fadr_s               cn58xx;
-    struct cvmx_l2d_fadr_s               cn58xxp1;
-} cvmx_l2d_fadr_t;
-
-
-/**
- * cvmx_l2d_fsyn0
- *
- * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
- * 
- * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
- *
- * Notes:
- * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
- * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fsyn0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t fsyn_ow1                : 10;      /**< Failing L2 Data Store SYNDROME OW[1,5]
-                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
-                                                         or L2D_ERR[DED_ERR] are set, this field represents
-                                                         the failing OWECC syndrome for the half cacheline
-                                                         indexed by L2D_FADR[FADR].
-                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
-                                                         OW lane(1of4) detected the error.
-                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
-                                                         command from the diagnostic PP will conditionally latch
-                                                         the raw OWECC for the selected half cacheline.
-                                                         (see: L2D_ERR[BMHCLSEL] */
-        uint64_t fsyn_ow0                : 10;      /**< Failing L2 Data Store SYNDROME OW[0,4]
-                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
-                                                         or L2D_ERR[DED_ERR] are set, this field represents
-                                                         the failing OWECC syndrome for the half cacheline
-                                                         indexed by L2D_FADR[FADR].
-                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
-                                                         OW lane(1of4) detected the error.
-                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
-                                                         (L1 load-miss) from the diagnostic PP will conditionally
-                                                         latch the raw OWECC for the selected half cacheline.
-                                                         (see: L2D_ERR[BMHCLSEL] */
-#else
-        uint64_t fsyn_ow0                : 10;
-        uint64_t fsyn_ow1                : 10;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_l2d_fsyn0_s              cn30xx;
-    struct cvmx_l2d_fsyn0_s              cn31xx;
-    struct cvmx_l2d_fsyn0_s              cn38xx;
-    struct cvmx_l2d_fsyn0_s              cn38xxp2;
-    struct cvmx_l2d_fsyn0_s              cn50xx;
-    struct cvmx_l2d_fsyn0_s              cn52xx;
-    struct cvmx_l2d_fsyn0_s              cn52xxp1;
-    struct cvmx_l2d_fsyn0_s              cn56xx;
-    struct cvmx_l2d_fsyn0_s              cn56xxp1;
-    struct cvmx_l2d_fsyn0_s              cn58xx;
-    struct cvmx_l2d_fsyn0_s              cn58xxp1;
-} cvmx_l2d_fsyn0_t;
-
-
-/**
- * cvmx_l2d_fsyn1
- *
- * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
- * 
- * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
- *
- * Notes:
- * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
- * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fsyn1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t fsyn_ow3                : 10;      /**< Failing L2 Data Store SYNDROME OW[3,7] */
-        uint64_t fsyn_ow2                : 10;      /**< Failing L2 Data Store SYNDROME OW[2,5] */
-#else
-        uint64_t fsyn_ow2                : 10;
-        uint64_t fsyn_ow3                : 10;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_l2d_fsyn1_s              cn30xx;
-    struct cvmx_l2d_fsyn1_s              cn31xx;
-    struct cvmx_l2d_fsyn1_s              cn38xx;
-    struct cvmx_l2d_fsyn1_s              cn38xxp2;
-    struct cvmx_l2d_fsyn1_s              cn50xx;
-    struct cvmx_l2d_fsyn1_s              cn52xx;
-    struct cvmx_l2d_fsyn1_s              cn52xxp1;
-    struct cvmx_l2d_fsyn1_s              cn56xx;
-    struct cvmx_l2d_fsyn1_s              cn56xxp1;
-    struct cvmx_l2d_fsyn1_s              cn58xx;
-    struct cvmx_l2d_fsyn1_s              cn58xxp1;
-} cvmx_l2d_fsyn1_t;
-
-
-/**
- * cvmx_l2d_fus0
- *
- * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fus0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q0fus                   : 34;      /**< Fuse Register for QUAD0
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuse are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q0fus                   : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_fus0_s               cn30xx;
-    struct cvmx_l2d_fus0_s               cn31xx;
-    struct cvmx_l2d_fus0_s               cn38xx;
-    struct cvmx_l2d_fus0_s               cn38xxp2;
-    struct cvmx_l2d_fus0_s               cn50xx;
-    struct cvmx_l2d_fus0_s               cn52xx;
-    struct cvmx_l2d_fus0_s               cn52xxp1;
-    struct cvmx_l2d_fus0_s               cn56xx;
-    struct cvmx_l2d_fus0_s               cn56xxp1;
-    struct cvmx_l2d_fus0_s               cn58xx;
-    struct cvmx_l2d_fus0_s               cn58xxp1;
-} cvmx_l2d_fus0_t;
-
-
-/**
- * cvmx_l2d_fus1
- *
- * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fus1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q1fus                   : 34;      /**< Fuse Register for QUAD1
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuse are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q1fus                   : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_fus1_s               cn30xx;
-    struct cvmx_l2d_fus1_s               cn31xx;
-    struct cvmx_l2d_fus1_s               cn38xx;
-    struct cvmx_l2d_fus1_s               cn38xxp2;
-    struct cvmx_l2d_fus1_s               cn50xx;
-    struct cvmx_l2d_fus1_s               cn52xx;
-    struct cvmx_l2d_fus1_s               cn52xxp1;
-    struct cvmx_l2d_fus1_s               cn56xx;
-    struct cvmx_l2d_fus1_s               cn56xxp1;
-    struct cvmx_l2d_fus1_s               cn58xx;
-    struct cvmx_l2d_fus1_s               cn58xxp1;
-} cvmx_l2d_fus1_t;
-
-
-/**
- * cvmx_l2d_fus2
- *
- * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fus2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t q2fus                   : 34;      /**< Fuse Register for QUAD2
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuse are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q2fus                   : 34;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_l2d_fus2_s               cn30xx;
-    struct cvmx_l2d_fus2_s               cn31xx;
-    struct cvmx_l2d_fus2_s               cn38xx;
-    struct cvmx_l2d_fus2_s               cn38xxp2;
-    struct cvmx_l2d_fus2_s               cn50xx;
-    struct cvmx_l2d_fus2_s               cn52xx;
-    struct cvmx_l2d_fus2_s               cn52xxp1;
-    struct cvmx_l2d_fus2_s               cn56xx;
-    struct cvmx_l2d_fus2_s               cn56xxp1;
-    struct cvmx_l2d_fus2_s               cn58xx;
-    struct cvmx_l2d_fus2_s               cn58xxp1;
-} cvmx_l2d_fus2_t;
-
-
-/**
- * cvmx_l2d_fus3
- *
- * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2d_fus3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
-                                                         These bits are used to 'observe' the EMA[1:0] inputs
-                                                         for the L2 Data Store RAMs which are controlled by
-                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
-                                                         From poweron (dc_ok), the EMA_CTL are driven from
-                                                         FUSE[141:140]. However after the 1st CSR write to the
-                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
-                                                         from the MIO_FUSE_EMA[EMA] register permanently
-                                                         (until dc_ok).
-                                                         NOTE: O9N Addition */
-        uint64_t reserved_34_36          : 3;
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t reserved_34_36          : 3;
-        uint64_t ema_ctl                 : 3;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_l2d_fus3_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_35_63          : 29;
-        uint64_t crip_64k                : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:15] UNUSED
-                                                             [14]    bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:32] UNUSED
-                                                             [31]    bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_64k                : 1;
-        uint64_t reserved_35_63          : 29;
-#endif
-    } cn30xx;
-    struct cvmx_l2d_fus3_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_35_63          : 29;
-        uint64_t crip_128k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:15] UNUSED
-                                                             [14]    bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:32] UNUSED
-                                                             [31]    bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_128k               : 1;
-        uint64_t reserved_35_63          : 29;
-#endif
-    } cn31xx;
-    struct cvmx_l2d_fus3_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t crip_256k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_512k               : 1;
-        uint64_t crip_256k               : 1;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } cn38xx;
-    struct cvmx_l2d_fus3_cn38xx          cn38xxp2;
-    struct cvmx_l2d_fus3_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
-                                                         These bits are used to 'observe' the EMA[2:0] inputs
-                                                         for the L2 Data Store RAMs which are controlled by
-                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
-                                                         From poweron (dc_ok), the EMA_CTL are driven from
-                                                         FUSE[141:140]. However after the 1st CSR write to the
-                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
-                                                         from the MIO_FUSE_EMA[EMA] register permanently
-                                                         (until dc_ok). */
-        uint64_t reserved_36_36          : 1;
-        uint64_t crip_32k                : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t crip_64k                : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_64k                : 1;
-        uint64_t crip_32k                : 1;
-        uint64_t reserved_36_36          : 1;
-        uint64_t ema_ctl                 : 3;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } cn50xx;
-    struct cvmx_l2d_fus3_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
-                                                         These bits are used to 'observe' the EMA[2:0] inputs
-                                                         for the L2 Data Store RAMs which are controlled by
-                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
-                                                         From poweron (dc_ok), the EMA_CTL are driven from
-                                                         FUSE[141:140]. However after the 1st CSR write to the
-                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
-                                                         from the MIO_FUSE_EMA[EMA] register permanently
-                                                         (until dc_ok). */
-        uint64_t reserved_36_36          : 1;
-        uint64_t crip_128k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t crip_256k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1. */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_256k               : 1;
-        uint64_t crip_128k               : 1;
-        uint64_t reserved_36_36          : 1;
-        uint64_t ema_ctl                 : 3;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } cn52xx;
-    struct cvmx_l2d_fus3_cn52xx          cn52xxp1;
-    struct cvmx_l2d_fus3_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
-                                                         These bits are used to 'observe' the EMA[2:0] inputs
-                                                         for the L2 Data Store RAMs which are controlled by
-                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
-                                                         From poweron (dc_ok), the EMA_CTL are driven from
-                                                         FUSE[141:140]. However after the 1st CSR write to the
-                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
-                                                         from the MIO_FUSE_EMA[EMA] register permanently
-                                                         (until dc_ok).
-                                                         NOTE: O9N Addition */
-        uint64_t reserved_36_36          : 1;
-        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t crip_1024k              : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_1024k              : 1;
-        uint64_t crip_512k               : 1;
-        uint64_t reserved_36_36          : 1;
-        uint64_t ema_ctl                 : 3;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } cn56xx;
-    struct cvmx_l2d_fus3_cn56xx          cn56xxp1;
-    struct cvmx_l2d_fus3_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t ema_ctl                 : 2;       /**< L2 Data Store EMA Control
-                                                         These bits are used to 'observe' the EMA[1:0] inputs
-                                                         for the L2 Data Store RAMs which are controlled by
-                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
-                                                         From poweron (dc_ok), the EMA_CTL are driven from
-                                                         FUSE[141:140]. However after the 1st CSR write to the
-                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
-                                                         from the MIO_FUSE_EMA[EMA] register permanently
-                                                         (until dc_ok).
-                                                         NOTE: O9N Addition */
-        uint64_t reserved_36_36          : 1;
-        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t crip_1024k              : 1;       /**< This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         If the FUSE is not-blown, then this bit should read
-                                                         as 0. If the FUSE is blown, then this bit should read
-                                                         as 1.
-                                                         *** NOTE: Pass2 Addition */
-        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
-                                                         This is purely for debug and not needed in the general
-                                                         manufacturing flow.
-                                                         Note that the fuses are complementary (Assigning a
-                                                         fuse to 1 will read as a zero). This means the case
-                                                         where no fuses are blown result in these csr's showing
-                                                         all ones.
-                                                          Failure \#1 Fuse Mapping
-                                                             [16:14] bad bank
-                                                             [13:7] bad high column
-                                                             [6:0] bad low column
-                                                           Failure \#2 Fuse Mapping
-                                                             [33:31] bad bank
-                                                             [30:24] bad high column
-                                                             [23:17] bad low column */
-#else
-        uint64_t q3fus                   : 34;
-        uint64_t crip_1024k              : 1;
-        uint64_t crip_512k               : 1;
-        uint64_t reserved_36_36          : 1;
-        uint64_t ema_ctl                 : 2;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } cn58xx;
-    struct cvmx_l2d_fus3_cn58xx          cn58xxp1;
-} cvmx_l2d_fus3_t;
-
-
-/**
- * cvmx_l2t_err
- *
- * L2T_ERR = L2 Tag Errors
- * 
- * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_l2t_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t fadru                   : 1;       /**< Failing L2 Tag Upper Address Bit (Index[10])
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADRU contains the upper(MSB bit) cacheline index
-                                                         into the L2 Tag Store. */
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t fadr                    : 10;      /**< Failing L2 Tag Address (10-bit Index)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the lower 10bit cacheline index
-                                                         into the L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 19-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:18]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 10;
-        uint64_t fset                    : 3;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t fadru                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_l2t_err_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked. */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is
-                                                         completed successfully, however the address is NOT
-                                                         locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t reserved_23_23          : 1;
-        uint64_t fset                    : 2;       /**< Failing L2 Tag Hit Set# (1-of-4)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t reserved_19_20          : 2;
-        uint64_t fadr                    : 8;       /**< Failing L2 Tag Store Index (8-bit)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the 8bit cacheline index into the
-                                                         L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 22-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:15]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 8;
-        uint64_t reserved_19_20          : 2;
-        uint64_t fset                    : 2;
-        uint64_t reserved_23_23          : 1;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn30xx;
-    struct cvmx_l2t_err_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked. */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t reserved_23_23          : 1;
-        uint64_t fset                    : 2;       /**< Failing L2 Tag Hit Set# (1-of-4)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t reserved_20_20          : 1;
-        uint64_t fadr                    : 9;       /**< Failing L2 Tag Address (9-bit Index)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the 9-bit cacheline index into the
-                                                         L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 9;
-        uint64_t reserved_20_20          : 1;
-        uint64_t fset                    : 2;
-        uint64_t reserved_23_23          : 1;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn31xx;
-    struct cvmx_l2t_err_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked.
-                                                         *** NOTE: PASS2 Addition */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t fadr                    : 10;      /**< Failing L2 Tag Address (10-bit Index)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the 10bit cacheline index into the
-                                                         L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 20-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:17]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 10;
-        uint64_t fset                    : 3;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn38xx;
-    struct cvmx_l2t_err_cn38xx           cn38xxp2;
-    struct cvmx_l2t_err_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked. */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t reserved_18_20          : 3;
-        uint64_t fadr                    : 7;       /**< Failing L2 Tag Address (7-bit Index)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the lower 7bit cacheline index
-                                                         into the L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 23-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:14]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 7;
-        uint64_t reserved_18_20          : 3;
-        uint64_t fset                    : 3;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn50xx;
-    struct cvmx_l2t_err_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
-        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
-                                                         could not find an available/unlocked set (for
-                                                         replacement).
-                                                         Most likely, this is a result of SW mixing SET
-                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
-                                                         another PP to LOCKDOWN all SETs available to PP#n,
-                                                         then a Rd/Wr Miss from PP#n will be unable
-                                                         to determine a 'valid' replacement set (since LOCKED
-                                                         addresses should NEVER be replaced).
-                                                         If such an event occurs, the HW will select the smallest
-                                                         available SET(specified by UMSK'x)' as the replacement
-                                                         set, and the address is unlocked. */
-        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
-        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
-                                                         the INDEX (which is ignored by HW - but reported to SW).
-                                                         The LDD(L1 load-miss) for the LOCK operation is completed
-                                                         successfully, however the address is NOT locked.
-                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
-                                                         into account. For example, if diagnostic PPx has
-                                                         UMSKx defined to only use SETs [1:0], and SET1 had
-                                                         been previously LOCKED, then an attempt to LOCK the
-                                                         last available SET0 would result in a LCKERR. (This
-                                                         is to ensure that at least 1 SET at each INDEX is
-                                                         not LOCKED for general use by other PPs). */
-        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
-                                                         (FSYN != 0), the FSET specifies the failing hit-set.
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
-                                                         is specified by the L2C_DBG[SET]. */
-        uint64_t reserved_20_20          : 1;
-        uint64_t fadr                    : 9;       /**< Failing L2 Tag Address (9-bit Index)
-                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the FADR contains the lower 9bit cacheline index
-                                                         into the L2 Tag Store. */
-        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
-                                                         the contents of this register contain the 6-bit
-                                                         syndrome for the hit set only.
-                                                         If (FSYN = 0), the SBE or DBE reported was for one of
-                                                         the "non-hit" sets at the failing index(FADR).
-                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
-                                                         is specified by the L2C_DBG[SET].
-                                                         If (FSYN != 0), the SBE or DBE reported was for the
-                                                         hit set at the failing index(FADR) and failing
-                                                         set(FSET).
-                                                         SW NOTE: To determine which "non-hit" set was in error,
-                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
-                                                         read the other sets at the failing index(FADR). When
-                                                         (FSYN !=0), then the FSET contains the failing hit-set.
-                                                         NOTE: A DED Error will always overwrite a SEC Error
-                                                         SYNDROME and FADR). */
-        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for double bit errors(DBEs).
-                                                         This bit is set if ANY of the 8 sets contains a DBE.
-                                                         DBEs also generated an interrupt(if enabled). */
-        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
-                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
-                                                         given index) are checked for single bit errors(SBEs).
-                                                         This bit is set if ANY of the 8 sets contains an SBE.
-                                                         SBEs are auto corrected in HW and generate an
-                                                         interrupt(if enabled). */
-        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on double bit (uncorrectable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
-                                                         Enable bit. When set, allows interrupts to be
-                                                         reported on single bit (correctable) errors from
-                                                         the L2 Tag Arrays. */
-        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
-                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
-                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
-#else
-        uint64_t ecc_ena                 : 1;
-        uint64_t sec_intena              : 1;
-        uint64_t ded_intena              : 1;
-        uint64_t sec_err                 : 1;
-        uint64_t ded_err                 : 1;
-        uint64_t fsyn                    : 6;
-        uint64_t fadr                    : 9;
-        uint64_t reserved_20_20          : 1;
-        uint64_t fset                    : 3;
-        uint64_t lckerr                  : 1;
-        uint64_t lck_intena              : 1;
-        uint64_t lckerr2                 : 1;
-        uint64_t lck_intena2             : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn52xx;
-    struct cvmx_l2t_err_cn52xx           cn52xxp1;
-    struct cvmx_l2t_err_s                cn56xx;
-    struct cvmx_l2t_err_s                cn56xxp1;
-    struct cvmx_l2t_err_s                cn58xx;
-    struct cvmx_l2t_err_s                cn58xxp1;
-} cvmx_l2t_err_t;
-
-
-/**
- * cvmx_led_blink
- *
- * LED_BLINK = LED Blink Rate (in led_clks)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_blink_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rate                    : 8;       /**< LED Blink rate in led_latch clks
-                                                         RATE must be > 0 */
-#else
-        uint64_t rate                    : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_led_blink_s              cn38xx;
-    struct cvmx_led_blink_s              cn38xxp2;
-    struct cvmx_led_blink_s              cn56xx;
-    struct cvmx_led_blink_s              cn56xxp1;
-    struct cvmx_led_blink_s              cn58xx;
-    struct cvmx_led_blink_s              cn58xxp1;
-} cvmx_led_blink_t;
-
-
-/**
- * cvmx_led_clk_phase
- *
- * LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
- *
- *
- * Notes:
- * Example:
- * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
- * led_clk phase is 64 eclks, or 128ns.  The led_clk period is 2*phase,
- * or 256ns which is 3.9MHz.  The default value of 4, yields an led_clk
- * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_clk_phase_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t phase                   : 7;       /**< Number of 64 eclks in order to create the led_clk */
-#else
-        uint64_t phase                   : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_led_clk_phase_s          cn38xx;
-    struct cvmx_led_clk_phase_s          cn38xxp2;
-    struct cvmx_led_clk_phase_s          cn56xx;
-    struct cvmx_led_clk_phase_s          cn56xxp1;
-    struct cvmx_led_clk_phase_s          cn58xx;
-    struct cvmx_led_clk_phase_s          cn58xxp1;
-} cvmx_led_clk_phase_t;
-
-
-/**
- * cvmx_led_cylon
- *
- * LED_CYLON = LED CYLON Effect (should remain undocumented)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_cylon_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t rate                    : 16;      /**< LED Cylon Effect when RATE!=0
-                                                         Changes at RATE*LATCH period */
-#else
-        uint64_t rate                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_led_cylon_s              cn38xx;
-    struct cvmx_led_cylon_s              cn38xxp2;
-    struct cvmx_led_cylon_s              cn56xx;
-    struct cvmx_led_cylon_s              cn56xxp1;
-    struct cvmx_led_cylon_s              cn58xx;
-    struct cvmx_led_cylon_s              cn58xxp1;
-} cvmx_led_cylon_t;
-
-
-/**
- * cvmx_led_dbg
- *
- * LED_DBG = LED Debug Port information
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t dbg_en                  : 1;       /**< Add Debug Port Data to the LED shift chain
-                                                         Debug Data is shifted out LSB to MSB */
-#else
-        uint64_t dbg_en                  : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_led_dbg_s                cn38xx;
-    struct cvmx_led_dbg_s                cn38xxp2;
-    struct cvmx_led_dbg_s                cn56xx;
-    struct cvmx_led_dbg_s                cn56xxp1;
-    struct cvmx_led_dbg_s                cn58xx;
-    struct cvmx_led_dbg_s                cn58xxp1;
-} cvmx_led_dbg_t;
-
-
-/**
- * cvmx_led_en
- *
- * LED_EN = LED Interface Enable
- *
- *
- * Notes:
- * The LED interface is comprised of a shift chain with a parallel latch.  LED
- * data is shifted out on each fallingg edge of led_clk and then captured by
- * led_lat.
- * 
- * The LED shift chain is comprised of the following...
- * 
- *      32  - UDD header
- *      6x8 - per port status
- *      17  - debug port
- *      32  - UDD trailer
- * 
- * for a total of 129 bits.
- * 
- * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
- * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
- * ... LED_UDD_DAT0[LED_UDD_CNT0].
- * 
- * The per port status is also variable.  Systems can control which ports send
- * data (LED_PRT) as well as the status content (LED_PRT_FMT and
- * LED_PRT_STATUS*).  When multiple ports are enabled, they come out in lowest
- * port to highest port (prt0, prt1, ...).
- * 
- * The debug port data can also be added to the LED chain (LED_DBG).  When
- * enabled, the debug data shifts out LSB to MSB.
- * 
- * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
- * and LED_UDD_DAT1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t en                      : 1;       /**< Enable the LED interface shift-chain */
-#else
-        uint64_t en                      : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_led_en_s                 cn38xx;
-    struct cvmx_led_en_s                 cn38xxp2;
-    struct cvmx_led_en_s                 cn56xx;
-    struct cvmx_led_en_s                 cn56xxp1;
-    struct cvmx_led_en_s                 cn58xx;
-    struct cvmx_led_en_s                 cn58xxp1;
-} cvmx_led_en_t;
-
-
-/**
- * cvmx_led_polarity
- *
- * LED_POLARITY = LED Polarity
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_polarity_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t polarity                : 1;       /**< LED active polarity
-                                                         0 = active HIGH LED
-                                                         1 = active LOW LED (invert led_dat) */
-#else
-        uint64_t polarity                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_led_polarity_s           cn38xx;
-    struct cvmx_led_polarity_s           cn38xxp2;
-    struct cvmx_led_polarity_s           cn56xx;
-    struct cvmx_led_polarity_s           cn56xxp1;
-    struct cvmx_led_polarity_s           cn58xx;
-    struct cvmx_led_polarity_s           cn58xxp1;
-} cvmx_led_polarity_t;
-
-
-/**
- * cvmx_led_prt
- *
- * LED_PRT = LED Port status information
- *
- *
- * Notes:
- * Note:
- * the PRT vector enables information of the 8 RGMII ports connected to
- * Octane.  It does not reflect the actual programmed PHY addresses.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_prt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t prt_en                  : 8;       /**< Which ports are enabled to display status
-                                                         PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
-                                                         PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
-                                                         Only applies when interface is in RGMII mode
-                                                         The status format is defined by LED_PRT_FMT */
-#else
-        uint64_t prt_en                  : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_led_prt_s                cn38xx;
-    struct cvmx_led_prt_s                cn38xxp2;
-    struct cvmx_led_prt_s                cn56xx;
-    struct cvmx_led_prt_s                cn56xxp1;
-    struct cvmx_led_prt_s                cn58xx;
-    struct cvmx_led_prt_s                cn58xxp1;
-} cvmx_led_prt_t;
-
-
-/**
- * cvmx_led_prt_fmt
- *
- * LED_PRT_FMT = LED Port Status Infomation Format
- *
- *
- * Notes:
- * TX: RGMII TX block is sending packet data or extends on the port
- * RX: RGMII RX block has received non-idle cycle
- * 
- * For short transfers, LEDs will remain on for at least one blink cycle
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_prt_fmt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t format                  : 4;       /**< Port Status Information for each enabled port in
-                                                         LED_PRT.  The formats are below
-                                                         0x0: [ LED_PRT_STATUS[0]            ]
-                                                         0x1: [ LED_PRT_STATUS[1:0]          ]
-                                                         0x2: [ LED_PRT_STATUS[3:0]          ]
-                                                         0x3: [ LED_PRT_STATUS[5:0]          ]
-                                                         0x4: [ (RX|TX), LED_PRT_STATUS[0]   ]
-                                                         0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
-                                                         0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
-                                                         0x8: [ Tx, Rx, LED_PRT_STATUS[0]    ]
-                                                         0x9: [ Tx, Rx, LED_PRT_STATUS[1:0]  ]
-                                                         0xa: [ Tx, Rx, LED_PRT_STATUS[3:0]  ] */
-#else
-        uint64_t format                  : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_led_prt_fmt_s            cn38xx;
-    struct cvmx_led_prt_fmt_s            cn38xxp2;
-    struct cvmx_led_prt_fmt_s            cn56xx;
-    struct cvmx_led_prt_fmt_s            cn56xxp1;
-    struct cvmx_led_prt_fmt_s            cn58xx;
-    struct cvmx_led_prt_fmt_s            cn58xxp1;
-} cvmx_led_prt_fmt_t;
-
-
-/**
- * cvmx_led_prt_status#
- *
- * LED_PRT_STATUS = LED Port Status information
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_prt_statusx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t status                  : 6;       /**< Bits that software can set to be added to the
-                                                         LED shift chain - depending on LED_PRT_FMT
-                                                         LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
-                                                          on interface0
-                                                         LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
-                                                          on interface1
-                                                         Only applies when interface is in RGMII mode */
-#else
-        uint64_t status                  : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_led_prt_statusx_s        cn38xx;
-    struct cvmx_led_prt_statusx_s        cn38xxp2;
-    struct cvmx_led_prt_statusx_s        cn56xx;
-    struct cvmx_led_prt_statusx_s        cn56xxp1;
-    struct cvmx_led_prt_statusx_s        cn58xx;
-    struct cvmx_led_prt_statusx_s        cn58xxp1;
-} cvmx_led_prt_statusx_t;
-
-
-/**
- * cvmx_led_udd_cnt#
- *
- * LED_UDD_CNT = LED UDD Counts
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_udd_cntx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t cnt                     : 6;       /**< Number of bits of user-defined data to include in
-                                                         the LED shift chain.  Legal values: 0-32. */
-#else
-        uint64_t cnt                     : 6;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_led_udd_cntx_s           cn38xx;
-    struct cvmx_led_udd_cntx_s           cn38xxp2;
-    struct cvmx_led_udd_cntx_s           cn56xx;
-    struct cvmx_led_udd_cntx_s           cn56xxp1;
-    struct cvmx_led_udd_cntx_s           cn58xx;
-    struct cvmx_led_udd_cntx_s           cn58xxp1;
-} cvmx_led_udd_cntx_t;
-
-
-/**
- * cvmx_led_udd_dat#
- *
- * LED_UDD_DAT = User defined data (header or trailer)
- *
- *
- * Notes:
- * Bits come out LSB to MSB on the shift chain.  If LED_UDD_CNT is set to 4
- * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
- * LED_UDD_DAT[3].
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_udd_datx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dat                     : 32;      /**< Header or trailer UDD data to be displayed on
-                                                         the LED shift chain.  Number of bits to include
-                                                         is controled by LED_UDD_CNT */
-#else
-        uint64_t dat                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_led_udd_datx_s           cn38xx;
-    struct cvmx_led_udd_datx_s           cn38xxp2;
-    struct cvmx_led_udd_datx_s           cn56xx;
-    struct cvmx_led_udd_datx_s           cn56xxp1;
-    struct cvmx_led_udd_datx_s           cn58xx;
-    struct cvmx_led_udd_datx_s           cn58xxp1;
-} cvmx_led_udd_datx_t;
-
-
-/**
- * cvmx_led_udd_dat_clr#
- *
- * LED_UDD_DAT_CLR = User defined data (header or trailer)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_udd_dat_clrx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t clr                     : 32;      /**< Bitwise clear for the Header or trailer UDD data to
-                                                         be displayed on the LED shift chain. */
-#else
-        uint64_t clr                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_led_udd_dat_clrx_s       cn38xx;
-    struct cvmx_led_udd_dat_clrx_s       cn38xxp2;
-    struct cvmx_led_udd_dat_clrx_s       cn56xx;
-    struct cvmx_led_udd_dat_clrx_s       cn56xxp1;
-    struct cvmx_led_udd_dat_clrx_s       cn58xx;
-    struct cvmx_led_udd_dat_clrx_s       cn58xxp1;
-} cvmx_led_udd_dat_clrx_t;
-
-
-/**
- * cvmx_led_udd_dat_set#
- *
- * LED_UDD_DAT_SET = User defined data (header or trailer)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_led_udd_dat_setx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t set                     : 32;      /**< Bitwise set for the Header or trailer UDD data to
-                                                         be displayed on the LED shift chain. */
-#else
-        uint64_t set                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_led_udd_dat_setx_s       cn38xx;
-    struct cvmx_led_udd_dat_setx_s       cn38xxp2;
-    struct cvmx_led_udd_dat_setx_s       cn56xx;
-    struct cvmx_led_udd_dat_setx_s       cn56xxp1;
-    struct cvmx_led_udd_dat_setx_s       cn58xx;
-    struct cvmx_led_udd_dat_setx_s       cn58xxp1;
-} cvmx_led_udd_dat_setx_t;
-
-
-/**
- * cvmx_lmc#_bist_ctl
- *
- * Notes:
- * This controls BiST only for the memories that operate on DCLK.  The normal, chip-wide BiST flow
- * controls BiST for the memories that operate on ECLK.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_bist_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t start                   : 1;       /**< A 0->1 transition causes BiST to run. */
-#else
-        uint64_t start                   : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_lmcx_bist_ctl_s          cn50xx;
-    struct cvmx_lmcx_bist_ctl_s          cn52xx;
-    struct cvmx_lmcx_bist_ctl_s          cn52xxp1;
-    struct cvmx_lmcx_bist_ctl_s          cn56xx;
-    struct cvmx_lmcx_bist_ctl_s          cn56xxp1;
-} cvmx_lmcx_bist_ctl_t;
-
-
-/**
- * cvmx_lmc#_bist_result
- *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_bist_result_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t csrd2e                  : 1;       /**< BiST result of CSRD2E memory (0=pass, !0=fail) */
-        uint64_t csre2d                  : 1;       /**< BiST result of CSRE2D memory (0=pass, !0=fail) */
-        uint64_t mwf                     : 1;       /**< BiST result of MWF memories (0=pass, !0=fail) */
-        uint64_t mwd                     : 3;       /**< BiST result of MWD memories (0=pass, !0=fail) */
-        uint64_t mwc                     : 1;       /**< BiST result of MWC memories (0=pass, !0=fail) */
-        uint64_t mrf                     : 1;       /**< BiST result of MRF memories (0=pass, !0=fail) */
-        uint64_t mrd                     : 3;       /**< BiST result of MRD memories (0=pass, !0=fail) */
-#else
-        uint64_t mrd                     : 3;
-        uint64_t mrf                     : 1;
-        uint64_t mwc                     : 1;
-        uint64_t mwd                     : 3;
-        uint64_t mwf                     : 1;
-        uint64_t csre2d                  : 1;
-        uint64_t csrd2e                  : 1;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_lmcx_bist_result_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t mwf                     : 1;       /**< BiST result of MWF memories (0=pass, !0=fail) */
-        uint64_t mwd                     : 3;       /**< BiST result of MWD memories (0=pass, !0=fail) */
-        uint64_t mwc                     : 1;       /**< BiST result of MWC memories (0=pass, !0=fail) */
-        uint64_t mrf                     : 1;       /**< BiST result of MRF memories (0=pass, !0=fail) */
-        uint64_t mrd                     : 3;       /**< BiST result of MRD memories (0=pass, !0=fail) */
-#else
-        uint64_t mrd                     : 3;
-        uint64_t mrf                     : 1;
-        uint64_t mwc                     : 1;
-        uint64_t mwd                     : 3;
-        uint64_t mwf                     : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn50xx;
-    struct cvmx_lmcx_bist_result_s       cn52xx;
-    struct cvmx_lmcx_bist_result_s       cn52xxp1;
-    struct cvmx_lmcx_bist_result_s       cn56xx;
-    struct cvmx_lmcx_bist_result_s       cn56xxp1;
-} cvmx_lmcx_bist_result_t;
-
-
-/**
- * cvmx_lmc#_comp_ctl
- *
- * LMC_COMP_CTL = LMC Compensation control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_comp_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t nctl_clk                : 4;       /**< Compensation control bits */
-        uint64_t nctl_cmd                : 4;       /**< Compensation control bits */
-        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
-        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t pctl_clk                : 4;       /**< Compensation control bits */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t pctl_clk                : 4;
-        uint64_t pctl_csr                : 4;
-        uint64_t nctl_dat                : 4;
-        uint64_t nctl_cmd                : 4;
-        uint64_t nctl_clk                : 4;
-        uint64_t nctl_csr                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_comp_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t nctl_clk                : 4;       /**< Compensation control bits */
-        uint64_t nctl_cmd                : 4;       /**< Compensation control bits */
-        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
-        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t pctl_clk                : 4;       /**< Compensation control bits */
-        uint64_t pctl_cmd                : 4;       /**< Compensation control bits */
-        uint64_t pctl_dat                : 4;       /**< Compensation control bits */
-#else
-        uint64_t pctl_dat                : 4;
-        uint64_t pctl_cmd                : 4;
-        uint64_t pctl_clk                : 4;
-        uint64_t pctl_csr                : 4;
-        uint64_t nctl_dat                : 4;
-        uint64_t nctl_cmd                : 4;
-        uint64_t nctl_clk                : 4;
-        uint64_t nctl_csr                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_lmcx_comp_ctl_cn30xx     cn31xx;
-    struct cvmx_lmcx_comp_ctl_cn30xx     cn38xx;
-    struct cvmx_lmcx_comp_ctl_cn30xx     cn38xxp2;
-    struct cvmx_lmcx_comp_ctl_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t reserved_20_27          : 8;
-        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
-        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t reserved_5_11           : 7;
-        uint64_t pctl_dat                : 5;       /**< Compensation control bits */
-#else
-        uint64_t pctl_dat                : 5;
-        uint64_t reserved_5_11           : 7;
-        uint64_t pctl_csr                : 4;
-        uint64_t nctl_dat                : 4;
-        uint64_t reserved_20_27          : 8;
-        uint64_t nctl_csr                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn50xx;
-    struct cvmx_lmcx_comp_ctl_cn50xx     cn52xx;
-    struct cvmx_lmcx_comp_ctl_cn50xx     cn52xxp1;
-    struct cvmx_lmcx_comp_ctl_cn50xx     cn56xx;
-    struct cvmx_lmcx_comp_ctl_cn50xx     cn56xxp1;
-    struct cvmx_lmcx_comp_ctl_cn50xx     cn58xx;
-    struct cvmx_lmcx_comp_ctl_cn58xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t reserved_20_27          : 8;
-        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
-        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
-        uint64_t reserved_4_11           : 8;
-        uint64_t pctl_dat                : 4;       /**< Compensation control bits */
-#else
-        uint64_t pctl_dat                : 4;
-        uint64_t reserved_4_11           : 8;
-        uint64_t pctl_csr                : 4;
-        uint64_t nctl_dat                : 4;
-        uint64_t reserved_20_27          : 8;
-        uint64_t nctl_csr                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn58xxp1;
-} cvmx_lmcx_comp_ctl_t;
-
-
-/**
- * cvmx_lmc#_ctl
- *
- * LMC_CTL = LMC Control
- * This register is an assortment of various control fields needed by the memory controller
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t pll_div2                : 1;       /**< PLL Div2. */
-        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
-        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
-        uint64_t reserved_10_11          : 2;
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks */
-        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
-                                                         A non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the 4/8 ODT
-                                                         pins (64/128b mode) based on what the masks
-                                                         (LMC_WODT_CTL) are programmed to.
-                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
-                                                         for READS. LMC_RODT_CTL needs to be programmed based
-                                                         on the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization.
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t reserved_10_11          : 2;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t pll_bypass              : 1;
-        uint64_t pll_div2                : 1;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
-                                                         when compared to pass1 */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t pll_div2                : 1;       /**< PLL Div2. */
-        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
-        uint64_t inorder_mrf             : 1;       /**< Always set to zero */
-        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
-                                                         Dclk domain is (DRESET || ECLK_RESET). */
-        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
-                                                         Set to 1 if we use only 32 DQ pins
-                                                         0 for 16b DQ mode. */
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks */
-        uint64_t qs_dic                  : 2;       /**< QS Drive Strength Control (DDR1):
-                                                         & DDR2 Termination Resistor Setting
-                                                         When in DDR2, a non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the 8 ODT
-                                                         pins based on what the masks (LMC_WODT_CTL1 & 2)
-                                                         are programmed to. LMC_DDR2_CTL->ODT_ENA
-                                                         enables Octeon to drive ODT pins for READS.
-                                                         LMC_RODT_CTL needs to be programmed based on
-                                                         the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         For DDR-I/II Mode, DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization. (see DDR-I data sheet EMRS
-                                                         description)
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t mode32b                 : 1;
-        uint64_t dreset                  : 1;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t pll_bypass              : 1;
-        uint64_t pll_div2                : 1;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_lmcx_ctl_cn30xx          cn31xx;
-    struct cvmx_lmcx_ctl_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
-                                                         when compared to pass1
-                                                         NOTE - This bit has NO effect in PASS1 */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t reserved_16_17          : 2;
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< When set, forces LMC_MWF (writes) into strict, in-order
-                                                         mode.  When clear, writes may be serviced out of order
-                                                         (optimized to keep multiple banks active).
-                                                         This bit is ONLY to be set at power-on and
-                                                         should not be set for normal use.
-                                                         NOTE: For PASS1, set as follows:
-                                                             DDR-I -> 1
-                                                             DDR-II -> 0
-                                                         For Pass2, this bit is RA0, write ignore (this feature
-                                                         is permanently disabled) */
-        uint64_t inorder_mrf             : 1;       /**< When set, forces LMC_MRF (reads) into strict, in-order
-                                                         mode.  When clear, reads may be serviced out of order
-                                                         (optimized to keep multiple banks active).
-                                                         This bit is ONLY to be set at power-on and
-                                                         should not be set for normal use.
-                                                         NOTE: For PASS1, set as follows:
-                                                             DDR-I -> 1
-                                                             DDR-II -> 0
-                                                         For Pass2, this bit should be written ZERO for
-                                                         DDR I & II */
-        uint64_t set_zero                : 1;       /**< Reserved. Always Set this Bit to Zero */
-        uint64_t mode128b                : 1;       /**< 128b data Path Mode
-                                                         Set to 1 if we use all 128 DQ pins
-                                                         0 for 64b DQ mode. */
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks */
-        uint64_t qs_dic                  : 2;       /**< QS Drive Strength Control (DDR1):
-                                                         & DDR2 Termination Resistor Setting
-                                                         When in DDR2, a non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the 4/8 ODT
-                                                         pins (64/128b mode) based on what the masks
-                                                         (LMC_WODT_CTL) are programmed to.
-                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
-                                                         for READS. LMC_RODT_CTL needs to be programmed based
-                                                         on the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         For DDR-I/II Mode, DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization. (see DDR-I data sheet EMRS
-                                                         description)
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t mode128b                : 1;
-        uint64_t set_zero                : 1;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t reserved_16_17          : 2;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_lmcx_ctl_cn38xx          cn38xxp2;
-    struct cvmx_lmcx_ctl_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t reserved_17_17          : 1;
-        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
-        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
-        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
-                                                         Dclk domain is (DRESET || ECLK_RESET). */
-        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
-                                                         Set to 1 if we use 32 DQ pins
-                                                         0 for 16b DQ mode. */
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks */
-        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
-                                                         When in DDR2, a non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the ODT
-                                                         pins based on what the masks
-                                                         (LMC_WODT_CTL) are programmed to.
-                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
-                                                         for READS. LMC_RODT_CTL needs to be programmed based
-                                                         on the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization.
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t mode32b                 : 1;
-        uint64_t dreset                  : 1;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t pll_bypass              : 1;
-        uint64_t reserved_17_17          : 1;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn50xx;
-    struct cvmx_lmcx_ctl_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< Always clear to zero */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t reserved_16_17          : 2;
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
-        uint64_t inorder_mrf             : 1;       /**< Always set to zero */
-        uint64_t dreset                  : 1;       /**< MBZ
-                                                         THIS IS OBSOLETE.  Use LMC_DLL_CTL[DRESET] instead. */
-        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
-                                                         Set to 1 if we use only 32 DQ pins
-                                                         0 for 64b DQ mode. */
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1.
-                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks
-                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
-        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
-                                                         When in DDR2, a non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the 4/8 ODT
-                                                         pins (64/128b mode) based on what the masks
-                                                         (LMC_WODT_CTL0 & 1) are programmed to.
-                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
-                                                         for READS. LMC_RODT_CTL needs to be programmed based
-                                                         on the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization.
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t mode32b                 : 1;
-        uint64_t dreset                  : 1;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t reserved_16_17          : 2;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn52xx;
-    struct cvmx_lmcx_ctl_cn52xx          cn52xxp1;
-    struct cvmx_lmcx_ctl_cn52xx          cn56xx;
-    struct cvmx_lmcx_ctl_cn52xx          cn56xxp1;
-    struct cvmx_lmcx_ctl_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pulldns. */
-        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
-                                                         The encoded value on this will adjust the drive strength
-                                                         of the DDR DQ pullup. */
-        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
-        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
-                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
-                                                         else
-                                                           bank[n:0]=address[n+7:7]
-                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
-        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
-                                                         allowing reads to interrupt. */
-        uint64_t reserved_16_17          : 2;
-        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
-                                                         of JEDEC Registered DIMMs which require Write
-                                                         data to be registered in the controller. */
-        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
-                                                         will slot an additional 1 cycle data bus bubble to
-                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
-                                                         in case the "built-in" DIMM and RANK crossing logic
-                                                         which should auto-detect and perfectly slot
-                                                         read-to-reads to the same DIMM/RANK. */
-        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
-        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
-        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
-                                                         Dclk domain is (DRESET || ECLK_RESET). */
-        uint64_t mode128b                : 1;       /**< 128b data Path Mode
-                                                         Set to 1 if we use all 128 DQ pins
-                                                         0 for 64b DQ mode. */
-        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
-                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
-                                                         This bit should typically be set. */
-        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
-                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
-                                                         cycle. This should be set to one whenever both SILO_HC
-                                                         and SILO_QC are set. */
-        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
-                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
-                                                         data out of the pad silos.
-                                                             - 00: illegal
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: illegal
-                                                         This should always be set to 1. */
-        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
-                                                         DELAY on DQ (used in the controller to determine the
-                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
-                                                         the largest of the per byte Board delay
-                                                             - 00: 0 dclk
-                                                             - 01: 1 dclks
-                                                             - 10: 2 dclks
-                                                             - 11: 3 dclks */
-        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
-                                                         A non Zero value in this register
-                                                         enables the On Die Termination (ODT) in DDR parts.
-                                                         These two bits are loaded into the RTT
-                                                         portion of the EMRS register bits A6 & A2. If DDR2's
-                                                         termination (for the memory's DQ/DQS/DM pads) is not
-                                                         desired, set it to 00. If it is, chose between
-                                                         01 for 75 ohm and 10 for 150 ohm termination.
-                                                             00 = ODT Disabled
-                                                             01 = 75 ohm Termination
-                                                             10 = 150 ohm Termination
-                                                             11 = 50 ohm Termination
-                                                         Octeon, on writes, by default, drives the 4/8 ODT
-                                                         pins (64/128b mode) based on what the masks
-                                                         (LMC_WODT_CTL) are programmed to.
-                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
-                                                         for READS. LMC_RODT_CTL needs to be programmed based
-                                                         on the system's needs for ODT. */
-        uint64_t dic                     : 2;       /**< Drive Strength Control:
-                                                         DIC[0] is
-                                                         loaded into the Extended Mode Register (EMRS) A1 bit
-                                                         during initialization.
-                                                             0 = Normal
-                                                             1 = Reduced
-                                                         DIC[1] is used to load into EMRS
-                                                         bit 10 - DQSN Enable/Disable field. By default, we
-                                                         program the DDR's to drive the DQSN also. Set it to
-                                                         1 if DQSN should be Hi-Z.
-                                                             0 - DQSN Enable
-                                                             1 - DQSN Disable */
-#else
-        uint64_t dic                     : 2;
-        uint64_t qs_dic                  : 2;
-        uint64_t tskw                    : 2;
-        uint64_t sil_lat                 : 2;
-        uint64_t bprch                   : 1;
-        uint64_t fprch2                  : 1;
-        uint64_t mode128b                : 1;
-        uint64_t dreset                  : 1;
-        uint64_t inorder_mrf             : 1;
-        uint64_t inorder_mwf             : 1;
-        uint64_t r2r_slot                : 1;
-        uint64_t rdimm_ena               : 1;
-        uint64_t reserved_16_17          : 2;
-        uint64_t max_write_batch         : 4;
-        uint64_t xor_bank                : 1;
-        uint64_t slow_scf                : 1;
-        uint64_t ddr__pctl               : 4;
-        uint64_t ddr__nctl               : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn58xx;
-    struct cvmx_lmcx_ctl_cn58xx          cn58xxp1;
-} cvmx_lmcx_ctl_t;
-
-
-/**
- * cvmx_lmc#_ctl1
- *
- * LMC_CTL1 = LMC Control1
- * This register is an assortment of various control fields needed by the memory controller
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ctl1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t ecc_adr                 : 1;       /**< Include memory reference address in the ECC calculation
-                                                         0=disabled, 1=enabled */
-        uint64_t forcewrite              : 4;       /**< Force the oldest outstanding write to complete after
-                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
-        uint64_t idlepower               : 3;       /**< Enter power-down mode after the memory controller has
-                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
-        uint64_t sequence                : 3;       /**< Instruction sequence that is run after a 0->1 transition
-                                                         on LMC_MEM_CFG0[INIT_START].
-                                                         0=DDR2 power-up/init, 1=read-leveling
-                                                         2=self-refresh entry, 3=self-refresh exit,
-                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
-        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
-        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
-                                                         0=disable, 1=enable
-                                                         If the memory part does not support DCC, then this bit
-                                                         must be set to 0. */
-        uint64_t reserved_2_7            : 6;
-        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
-                                                         In 32b mode, this setting has no effect and the data
-                                                         layout DQ[35:0] is the following:
-                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
-                                                         In 16b mode, the DQ[35:0] layouts are the following:
-                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
-                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
-                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
-                                                         where E means ecc, D means data, and 0 means unused
-                                                         (ignored on reads and written as 0 on writes) */
-#else
-        uint64_t data_layout             : 2;
-        uint64_t reserved_2_7            : 6;
-        uint64_t dcc_enable              : 1;
-        uint64_t sil_mode                : 1;
-        uint64_t sequence                : 3;
-        uint64_t idlepower               : 3;
-        uint64_t forcewrite              : 4;
-        uint64_t ecc_adr                 : 1;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } s;
-    struct cvmx_lmcx_ctl1_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
-                                                         In 32b mode, this setting has no effect and the data
-                                                         layout DQ[35:0] is the following:
-                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
-                                                         In 16b mode, the DQ[35:0] layouts are the following:
-                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
-                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
-                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
-                                                         where E means ecc, D means data, and 0 means unused
-                                                         (ignored on reads and written as 0 on writes) */
-#else
-        uint64_t data_layout             : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn30xx;
-    struct cvmx_lmcx_ctl1_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
-        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
-                                                         0=disable, 1=enable
-                                                         If the memory part does not support DCC, then this bit
-                                                         must be set to 0. */
-        uint64_t reserved_2_7            : 6;
-        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
-                                                         In 32b mode, this setting has no effect and the data
-                                                         layout DQ[35:0] is the following:
-                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
-                                                         In 16b mode, the DQ[35:0] layouts are the following:
-                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
-                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
-                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
-                                                         where E means ecc, D means data, and 0 means unused
-                                                         (ignored on reads and written as 0 on writes) */
-#else
-        uint64_t data_layout             : 2;
-        uint64_t reserved_2_7            : 6;
-        uint64_t dcc_enable              : 1;
-        uint64_t sil_mode                : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn50xx;
-    struct cvmx_lmcx_ctl1_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t ecc_adr                 : 1;       /**< Include memory reference address in the ECC calculation
-                                                         0=disabled, 1=enabled */
-        uint64_t forcewrite              : 4;       /**< Force the oldest outstanding write to complete after
-                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
-        uint64_t idlepower               : 3;       /**< Enter power-down mode after the memory controller has
-                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
-        uint64_t sequence                : 3;       /**< Instruction sequence that is run after a 0->1 transition
-                                                         on LMC_MEM_CFG0[INIT_START].
-                                                         0=DDR2 power-up/init, 1=read-leveling
-                                                         2=self-refresh entry, 3=self-refresh exit,
-                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
-        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
-        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
-                                                         0=disable, 1=enable
-                                                         If the memory part does not support DCC, then this bit
-                                                         must be set to 0. */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t dcc_enable              : 1;
-        uint64_t sil_mode                : 1;
-        uint64_t sequence                : 3;
-        uint64_t idlepower               : 3;
-        uint64_t forcewrite              : 4;
-        uint64_t ecc_adr                 : 1;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } cn52xx;
-    struct cvmx_lmcx_ctl1_cn52xx         cn52xxp1;
-    struct cvmx_lmcx_ctl1_cn52xx         cn56xx;
-    struct cvmx_lmcx_ctl1_cn52xx         cn56xxp1;
-    struct cvmx_lmcx_ctl1_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
-        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
-                                                         0=disable, 1=enable
-                                                         If the memory part does not support DCC, then this bit
-                                                         must be set to 0. */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t dcc_enable              : 1;
-        uint64_t sil_mode                : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn58xx;
-    struct cvmx_lmcx_ctl1_cn58xx         cn58xxp1;
-} cvmx_lmcx_ctl1_t;
-
-
-/**
- * cvmx_lmc#_dclk_cnt_hi
- *
- * LMC_DCLK_CNT_HI  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_dclk_cnt_hi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dclkcnt_hi              : 32;      /**< Performance Counter that counts dclks
-                                                         Upper 32-bits of a 64-bit counter. */
-#else
-        uint64_t dclkcnt_hi              : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn30xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn31xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn38xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn38xxp2;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn50xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn52xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn52xxp1;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn56xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn56xxp1;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn58xx;
-    struct cvmx_lmcx_dclk_cnt_hi_s       cn58xxp1;
-} cvmx_lmcx_dclk_cnt_hi_t;
-
-
-/**
- * cvmx_lmc#_dclk_cnt_lo
- *
- * LMC_DCLK_CNT_LO  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_dclk_cnt_lo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dclkcnt_lo              : 32;      /**< Performance Counter that counts dclks
-                                                         Lower 32-bits of a 64-bit counter. */
-#else
-        uint64_t dclkcnt_lo              : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn30xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn31xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn38xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn38xxp2;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn50xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn52xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn52xxp1;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn56xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn56xxp1;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn58xx;
-    struct cvmx_lmcx_dclk_cnt_lo_s       cn58xxp1;
-} cvmx_lmcx_dclk_cnt_lo_t;
-
-
-/**
- * cvmx_lmc#_dclk_ctl
- *
- * LMC_DCLK_CTL = LMC DCLK generation control
- *
- *
- * Notes:
- * This CSR is only relevant for LMC1. LMC0_DCLK_CTL is not used.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_dclk_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t off90_ena               : 1;       /**< 0=use global DCLK (i.e. the PLL) directly for LMC1
-                                                         1=use the 90 degree DCLK DLL to offset LMC1 DCLK */
-        uint64_t dclk90_byp              : 1;       /**< 0=90 degree DCLK DLL uses sampled delay from LMC0
-                                                         1=90 degree DCLK DLL uses DCLK90_VLU
-                                                         See DCLK90_VLU. */
-        uint64_t dclk90_ld               : 1;       /**< The 90 degree DCLK DLL samples the delay setting
-                                                         from LMC0's DLL when this field transitions 0->1 */
-        uint64_t dclk90_vlu              : 5;       /**< Manual open-loop delay setting.
-                                                         The LMC1 90 degree DCLK DLL uses DCLK90_VLU rather
-                                                         than the delay setting sampled from LMC0 when
-                                                         DCLK90_BYP=1. */
-#else
-        uint64_t dclk90_vlu              : 5;
-        uint64_t dclk90_ld               : 1;
-        uint64_t dclk90_byp              : 1;
-        uint64_t off90_ena               : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_lmcx_dclk_ctl_s          cn56xx;
-    struct cvmx_lmcx_dclk_ctl_s          cn56xxp1;
-} cvmx_lmcx_dclk_ctl_t;
-
-
-/**
- * cvmx_lmc#_ddr2_ctl
- *
- * LMC_DDR2_CTL = LMC DDR2 & DLL Control Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ddr2_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bank8                   : 1;       /**< For 8 bank DDR2 parts
-                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
-                                                         wide).
-                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
-                                                         wide). */
-        uint64_t burst8                  : 1;       /**< 8-burst mode.
-                                                         1 - DDR data transfer happens in burst of 8
-                                                         0 - DDR data transfer happens in burst of 4
-                                                         BURST8 should be set when DDR2T is set
-                                                         to minimize the command bandwidth loss. */
-        uint64_t addlat                  : 3;       /**< Additional Latency for posted CAS
-                                                         When Posted CAS is on, this configures the additional
-                                                         latency. This should be set to
-                                                                1 .. LMC_MEM_CFG1[TRCD]-2
-                                                         (Note the implication that posted CAS should not
-                                                         be used when tRCD is two.) */
-        uint64_t pocas                   : 1;       /**< Enable the Posted CAS feature of DDR2. */
-        uint64_t bwcnt                   : 1;       /**< Bus utilization counter Clear.
-                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
-                                                         LMC_DCLK_CNT_* registers. SW should first write this
-                                                         field to a one, then write this field to a zero to
-                                                         clear the CSR's. */
-        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
-                                                         This is not a direct encoding of the value. Its
-                                                         programmed as below per DDR2 spec. The decimal number
-                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
-                                                          TYP=15ns
-                                                             - 000: RESERVED
-                                                             - 001: 2
-                                                             - 010: 3
-                                                             - 011: 4
-                                                             - 100: 5
-                                                             - 101: 6
-                                                             - 110: 7
-                                                             - 111: 8 */
-        uint64_t silo_hc                 : 1;       /**< Delays the read sample window by a Half Cycle. */
-        uint64_t ddr_eof                 : 4;       /**< Early Fill Counter Init.
-                                                         L2 needs to know a few cycle before a fill completes so
-                                                         it can get its Control pipe started (for better overall
-                                                         performance). This counter contains  an init value which
-                                                         is a function of Eclk/Dclk ratio to account for the
-                                                         asynchronous boundary between L2 cache and the DRAM
-                                                         controller. This init value will
-                                                         determine when to safely let the L2 know that a fill
-                                                         termination is coming up.
-                                                         Set DDR_EOF according to the following rule:
-                                                         eclkFreq/dclkFreq = dclkPeriod/eclkPeriod = RATIO
-                                                                RATIO < 6/6  -> illegal
-                                                         6/6 <= RATIO < 6/5  -> DDR_EOF=3
-                                                         6/5 <= RATIO < 6/4  -> DDR_EOF=3
-                                                         6/4 <= RATIO < 6/3  -> DDR_EOF=2
-                                                         6/3 <= RATIO < 6/2  -> DDR_EOF=1
-                                                         6/2 <= RATIO < 6/1  -> DDR_EOF=0
-                                                         6/1 <= RATIO        -> DDR_EOF=0 */
-        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
-                                                         Four Access Window time. Relevant only in DDR2 AND in
-                                                         8-bank parts.
-                                                             tFAW = 5'b0 in DDR2-4bank
-                                                             tFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1
-                                                                      in DDR2-8bank */
-        uint64_t crip_mode               : 1;       /**< Cripple Mode - When set, the LMC allows only
-                                                         1 inflight transaction (.vs. 8 in normal mode).
-                                                         This bit is ONLY to be set at power-on and
-                                                         should not be set for normal use. */
-        uint64_t ddr2t                   : 1;       /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
-                                                         address. This mode helps relieve setup time pressure
-                                                         on the Address and command bus which nominally have
-                                                         a very large fanout. Please refer to Micron's tech
-                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
-                                                         for Two Dimm Unbuffered Systems" for physical details.
-                                                         BURST8 should be set when DDR2T is set to minimize
-                                                         add/cmd loss. */
-        uint64_t odt_ena                 : 1;       /**< Enable Obsolete ODT on Reads
-                                                         Obsolete Read ODT wiggles DDR_ODT_* pins on reads.
-                                                         Should normally be cleared to zero.
-                                                         When this is on, the following fields must also be
-                                                         programmed:
-                                                             LMC_CTL->QS_DIC - programs the termination value
-                                                             LMC_RODT_CTL - programs the ODT I/O mask for Reads */
-        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
-                                                         DCLK init sequence will reset the DDR 90 DLL. Should
-                                                         happen at startup before any activity in DDR.
-                                                         DRESET should be asserted before and for 10 usec
-                                                         following the 0->1 transition on QDLL_ENA. */
-        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
-                                                         line. */
-        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
-                                                         bypassed and the setting is defined by DLL90_VLU */
-        uint64_t rdqs                    : 1;       /**< DDR2 RDQS mode. When set, configures memory subsystem to
-                                                         use unidirectional DQS pins. RDQS/DM - Rcv & DQS - Xmit */
-        uint64_t ddr2                    : 1;       /**< Should be set */
-#else
-        uint64_t ddr2                    : 1;
-        uint64_t rdqs                    : 1;
-        uint64_t dll90_byp               : 1;
-        uint64_t dll90_vlu               : 5;
-        uint64_t qdll_ena                : 1;
-        uint64_t odt_ena                 : 1;
-        uint64_t ddr2t                   : 1;
-        uint64_t crip_mode               : 1;
-        uint64_t tfaw                    : 5;
-        uint64_t ddr_eof                 : 4;
-        uint64_t silo_hc                 : 1;
-        uint64_t twr                     : 3;
-        uint64_t bwcnt                   : 1;
-        uint64_t pocas                   : 1;
-        uint64_t addlat                  : 3;
-        uint64_t burst8                  : 1;
-        uint64_t bank8                   : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ddr2_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bank8                   : 1;       /**< For 8 bank DDR2 parts
-                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
-                                                         wide).
-                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
-                                                         wide). */
-        uint64_t burst8                  : 1;       /**< 8-burst mode.
-                                                         1 - DDR data transfer happens in burst of 8
-                                                         0 - DDR data transfer happens in burst of 4
-                                                         BURST8 should be set when DDR2T is set to minimize
-                                                         add/cmd bandwidth loss. */
-        uint64_t addlat                  : 3;       /**< Additional Latency for posted CAS
-                                                         When Posted CAS is on, this configures the additional
-                                                         latency. This should be set to
-                                                                1 .. LMC_MEM_CFG1[TRCD]-2
-                                                         (Note the implication that posted CAS should not
-                                                         be used when tRCD is two.) */
-        uint64_t pocas                   : 1;       /**< Enable the Posted CAS feature of DDR2. */
-        uint64_t bwcnt                   : 1;       /**< Bus utilization counter Clear.
-                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
-                                                         LMC_DCLK_CNT_* registers. SW should first write this
-                                                         field to a one, then write this field to a zero to
-                                                         clear the CSR's. */
-        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
-                                                         This is not a direct encoding of the value. Its
-                                                         programmed as below per DDR2 spec. The decimal number
-                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
-                                                          TYP=15ns
-                                                             - 000: RESERVED
-                                                             - 001: 2
-                                                             - 010: 3
-                                                             - 011: 4
-                                                             - 100: 5
-                                                             - 101: 6
-                                                             - 110-111: RESERVED */
-        uint64_t silo_hc                 : 1;       /**< Delays the read sample window by a Half Cycle. */
-        uint64_t ddr_eof                 : 4;       /**< Early Fill Counter Init.
-                                                         L2 needs to know a few cycle before a fill completes so
-                                                         it can get its Control pipe started (for better overall
-                                                         performance). This counter contains  an init value which
-                                                         is a function of Eclk/Dclk ratio to account for the
-                                                         asynchronous boundary between L2 cache and the DRAM
-                                                         controller. This init value will
-                                                         determine when to safely let the L2 know that a fill
-                                                         termination is coming up.
-                                                         DDR_EOF = RNDUP (DCLK period/Eclk Period). If the ratio
-                                                         is above 3, set DDR_EOF to 3.
-                                                             DCLK/ECLK period         DDR_EOF
-                                                                Less than 1            1
-                                                                Less than 2            2
-                                                                More than 2            3 */
-        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
-                                                         Four Access Window time. Relevant only in
-                                                         8-bank parts.
-                                                             TFAW = 5'b0 for DDR2-4bank
-                                                             TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
-        uint64_t crip_mode               : 1;       /**< Cripple Mode - When set, the LMC allows only
-                                                         1 inflight transaction (.vs. 8 in normal mode).
-                                                         This bit is ONLY to be set at power-on and
-                                                         should not be set for normal use. */
-        uint64_t ddr2t                   : 1;       /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
-                                                         address. This mode helps relieve setup time pressure
-                                                         on the Address and command bus which nominally have
-                                                         a very large fanout. Please refer to Micron's tech
-                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
-                                                         for Two Dimm Unbuffered Systems" for physical details.
-                                                         BURST8 should be used when DDR2T is set to minimize
-                                                         add/cmd bandwidth loss. */
-        uint64_t odt_ena                 : 1;       /**< Enable ODT for DDR2 on Reads
-                                                         When this is on, the following fields must also be
-                                                         programmed:
-                                                             LMC_CTL->QS_DIC - programs the termination value
-                                                             LMC_RODT_CTL - programs the ODT I/O mask for writes
-                                                         Program as 0 for DDR1 mode and ODT needs to be off
-                                                         on Octeon Reads */
-        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
-                                                         erst deassertion will reset the DDR 90 DLL. Should
-                                                         happen at startup before any activity in DDR. */
-        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
-                                                         line. */
-        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
-                                                         bypassed and the setting is defined by DLL90_VLU */
-        uint64_t reserved_1_1            : 1;
-        uint64_t ddr2                    : 1;       /**< DDR2 Enable: When set, configures memory subsystem for
-                                                         DDR-II SDRAMs. */
-#else
-        uint64_t ddr2                    : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t dll90_byp               : 1;
-        uint64_t dll90_vlu               : 5;
-        uint64_t qdll_ena                : 1;
-        uint64_t odt_ena                 : 1;
-        uint64_t ddr2t                   : 1;
-        uint64_t crip_mode               : 1;
-        uint64_t tfaw                    : 5;
-        uint64_t ddr_eof                 : 4;
-        uint64_t silo_hc                 : 1;
-        uint64_t twr                     : 3;
-        uint64_t bwcnt                   : 1;
-        uint64_t pocas                   : 1;
-        uint64_t addlat                  : 3;
-        uint64_t burst8                  : 1;
-        uint64_t bank8                   : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_lmcx_ddr2_ctl_cn30xx     cn31xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn38xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn38xxp2;
-    struct cvmx_lmcx_ddr2_ctl_s          cn50xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn52xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn52xxp1;
-    struct cvmx_lmcx_ddr2_ctl_s          cn56xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn56xxp1;
-    struct cvmx_lmcx_ddr2_ctl_s          cn58xx;
-    struct cvmx_lmcx_ddr2_ctl_s          cn58xxp1;
-} cvmx_lmcx_ddr2_ctl_t;
-
-
-/**
- * cvmx_lmc#_delay_cfg
- *
- * LMC_DELAY_CFG = Open-loop delay line settings
- *
- *
- * Notes:
- * The DQ bits add OUTGOING delay only to dq, dqs_[p,n], cb, cbs_[p,n], dqm.  Delay is approximately
- * 50-80ps per setting depending on process/voltage.  There is no need to add incoming delay since by
- * default all strobe bits are delayed internally by 90 degrees (as was always the case in previous
- * passes and past chips.
- * 
- * The CMD add delay to all command bits DDR_RAS, DDR_CAS, DDR_A<15:0>, DDR_BA<2:0>, DDR_n_CS<1:0>_L,
- * DDR_WE, DDR_CKE and DDR_ODT_<7:0>. Again, delay is 50-80ps per tap.
- * 
- * The CLK bits add delay to all clock signals DDR_CK_<5:0>_P and DDR_CK_<5:0>_N.  Again, delay is
- * 50-80ps per tap.
- * 
- * The usage scenario is the following: There is too much delay on command signals and setup on command
- * is not met. The user can then delay the clock until setup is met.
- * 
- * At the same time though, dq/dqs should be delayed because there is also a DDR spec tying dqs with
- * clock. If clock is too much delayed with respect to dqs, writes will start to fail.
- * 
- * This scheme should eliminate the board need of adding routing delay to clock signals to make high
- * frequencies work.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_delay_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t dq                      : 5;       /**< Setting for DQ  delay line */
-        uint64_t cmd                     : 5;       /**< Setting for CMD delay line */
-        uint64_t clk                     : 5;       /**< Setting for CLK delay line */
-#else
-        uint64_t clk                     : 5;
-        uint64_t cmd                     : 5;
-        uint64_t dq                      : 5;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_lmcx_delay_cfg_s         cn30xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t dq                      : 4;       /**< Setting for DQ  delay line */
-        uint64_t reserved_9_9            : 1;
-        uint64_t cmd                     : 4;       /**< Setting for CMD delay line */
-        uint64_t reserved_4_4            : 1;
-        uint64_t clk                     : 4;       /**< Setting for CLK delay line */
-#else
-        uint64_t clk                     : 4;
-        uint64_t reserved_4_4            : 1;
-        uint64_t cmd                     : 4;
-        uint64_t reserved_9_9            : 1;
-        uint64_t dq                      : 4;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn38xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn50xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn52xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn52xxp1;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn56xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn56xxp1;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn58xx;
-    struct cvmx_lmcx_delay_cfg_cn38xx    cn58xxp1;
-} cvmx_lmcx_delay_cfg_t;
-
-
-/**
- * cvmx_lmc#_dll_ctl
- *
- * LMC_DLL_CTL = LMC DLL control and DCLK reset
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_dll_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
-                                                         Dclk domain is (DRESET || ECLK_RESET). */
-        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
-                                                         bypassed and the setting is defined by DLL90_VLU */
-        uint64_t dll90_ena               : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
-                                                         DCLK init sequence resets the DDR 90 DLL. Should
-                                                         happen at startup before any activity in DDR. QDLL_ENA
-                                                         must not transition 1->0 outside of a DRESET sequence
-                                                         (i.e. it must remain 1 until the next DRESET).
-                                                         DRESET should be asserted before and for 10 usec
-                                                         following the 0->1 transition on QDLL_ENA. */
-        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
-                                                         line. */
-#else
-        uint64_t dll90_vlu               : 5;
-        uint64_t dll90_ena               : 1;
-        uint64_t dll90_byp               : 1;
-        uint64_t dreset                  : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_lmcx_dll_ctl_s           cn52xx;
-    struct cvmx_lmcx_dll_ctl_s           cn52xxp1;
-    struct cvmx_lmcx_dll_ctl_s           cn56xx;
-    struct cvmx_lmcx_dll_ctl_s           cn56xxp1;
-} cvmx_lmcx_dll_ctl_t;
-
-
-/**
- * cvmx_lmc#_dual_memcfg
- *
- * LMC_DUAL_MEMCFG = LMC Dual Memory Configuration Register
- * 
- * This register controls certain parameters of Dual Memory Configuration
- *
- * Notes:
- * This register enables the design to have two, separate memory configurations, selected dynamically
- * by the reference address.  Note however, that both configurations share LMC_CTL[MODE128b],
- * LMC_CTL[XOR_BANK], LMC_MEM_CFG0[PBANK_LSB], LMC_MEM_CFG0[BUNK_ENA], and all timing parameters.
- * In this description, "config0" refers to the normal memory configuration that is defined by the
- * LMC_MEM_CFG0[ROW_LSB] andLMC_DDR2_CTL[BANK8] parameters and "config1" refers to the dual (or second)
- * memory configuration that is defined by this register.
- * 
- * Memory config0 must be programmed for the part with the most strict timing requirements.  If a mix of
- * 4 bank and 8 bank parts is used, then config0 must be used for the 8 bank part (because the timing
- * requirements of tFAW and tRP are more strict for 8 bank parts than they are for 4 bank parts).
- * 
- * Enable mask to chip select mapping is shown below:
- *   CS_MASK[7] -> DDR_3_CS_<1>
- *   CS_MASK[6] -> DDR_3_CS_<0>
- * 
- *   CS_MASK[5] -> DDR_2_CS_<1>
- *   CS_MASK[4] -> DDR_2_CS_<0>
- * 
- *   CS_MASK[3] -> DDR_1_CS_<1>
- *   CS_MASK[2] -> DDR_1_CS_<0>
- * 
- *   CS_MASK[1] -> DDR_0_CS_<1>
- *   CS_MASK[0] -> DDR_0_CS_<0>
- * 
- * the DIMMS are arranged in one of the following arrangements:
- *   LMC_CTL[MODE128b] == 1                                    LMC_CTL[MODE128b] == 0
- * 
- *   DIMM3_RANK1  | DIMM1_RANK1  highest address               DIMM3_RANK1  highest addres
- *   DIMM3_RANK0  | DIMM1_RANK0                                DIMM3_RANK0
- * 
- *   DIMM2_RANK1  | DIMM0_RANK1                                DIMM2_RANK1
- *   DIMM2_RANK0  | DIMM0_RANK0  lowest address                DIMM2_RANK0
- * 
- *   data[127:64] | data_[63:0]                                DIMM1_RANK1
- *                                                             DIMM1_RANK0
- * 
- *                                                             DIMM0_RANK1
- *                                                             DIMM0_RANK0  lowest address
- * 
- *                                                             data_[63:0]
- * 
- *  DIMM n uses the pair of chip selects DDR_n_CS_<1:0>.  When LMC_CTL[BUNK_ENA] == 1, each
- *  chip select in the pair asserts independently.  When LMC_CTL[BUNK_ENA] == 0, both chip
- *  selects in the pair assert together.
- * 
- *  Programming restrictions for CS_MASK:
- *    when LMC_CTL[BUNK_ENA] == 0, CS_MASK[2n + 1] = CS_MASK[2n], where 0 <= n <= 3
- *    when LMC_CTL[MODE128b] == 1, CS_MASK[ n + 4] = CS_MASK[ n], where 0 <= n <= 3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_dual_memcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t bank8                   : 1;       /**< See LMC_DDR2_CTL[BANK8] */
-        uint64_t row_lsb                 : 3;       /**< See LMC_MEM_CFG0[ROW_LSB] */
-        uint64_t reserved_8_15           : 8;
-        uint64_t cs_mask                 : 8;       /**< Chip select mask.
-                                                         This mask corresponds to the 8 chip selects for a memory
-                                                         configuration.  Each reference address will assert one of
-                                                         the chip selects.  If that chip select has its
-                                                         corresponding CS_MASK bit set, then the "config1"
-                                                         parameters are used, otherwise the "config0" parameters
-                                                         are used.  See additional notes below. */
-#else
-        uint64_t cs_mask                 : 8;
-        uint64_t reserved_8_15           : 8;
-        uint64_t row_lsb                 : 3;
-        uint64_t bank8                   : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_lmcx_dual_memcfg_s       cn50xx;
-    struct cvmx_lmcx_dual_memcfg_s       cn52xx;
-    struct cvmx_lmcx_dual_memcfg_s       cn52xxp1;
-    struct cvmx_lmcx_dual_memcfg_s       cn56xx;
-    struct cvmx_lmcx_dual_memcfg_s       cn56xxp1;
-    struct cvmx_lmcx_dual_memcfg_s       cn58xx;
-    struct cvmx_lmcx_dual_memcfg_s       cn58xxp1;
-} cvmx_lmcx_dual_memcfg_t;
-
-
-/**
- * cvmx_lmc#_ecc_synd
- *
- * LMC_ECC_SYND = MRD ECC Syndromes
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ecc_synd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t mrdsyn3                 : 8;       /**< MRD ECC Syndrome Quad3
-                                                         128b mode -  corresponds to DQ[127:64], Phase1
-                                                         64b mode  -  corresponds to DQ[127:64], Phase1, cycle1 */
-        uint64_t mrdsyn2                 : 8;       /**< MRD ECC Syndrome Quad2
-                                                         128b mode -  corresponds to DQ[63:0], Phase1
-                                                         64b mode  -  corresponds to DQ[63:0], Phase1, cycle0 */
-        uint64_t mrdsyn1                 : 8;       /**< MRD ECC Syndrome Quad1
-                                                         128b mode -  corresponds to DQ[127:64], Phase0
-                                                         64b mode  -  corresponds to DQ[127:64], Phase0, cycle1 */
-        uint64_t mrdsyn0                 : 8;       /**< MRD ECC Syndrome Quad0
-                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
-                                                         SYND0 corresponds to DQ[63:0], Phase0
-                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
-                                                         SYND0 corresponds to DQ[63:0], Phase0, cycle0 */
-#else
-        uint64_t mrdsyn0                 : 8;
-        uint64_t mrdsyn1                 : 8;
-        uint64_t mrdsyn2                 : 8;
-        uint64_t mrdsyn3                 : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ecc_synd_s          cn30xx;
-    struct cvmx_lmcx_ecc_synd_s          cn31xx;
-    struct cvmx_lmcx_ecc_synd_s          cn38xx;
-    struct cvmx_lmcx_ecc_synd_s          cn38xxp2;
-    struct cvmx_lmcx_ecc_synd_s          cn50xx;
-    struct cvmx_lmcx_ecc_synd_s          cn52xx;
-    struct cvmx_lmcx_ecc_synd_s          cn52xxp1;
-    struct cvmx_lmcx_ecc_synd_s          cn56xx;
-    struct cvmx_lmcx_ecc_synd_s          cn56xxp1;
-    struct cvmx_lmcx_ecc_synd_s          cn58xx;
-    struct cvmx_lmcx_ecc_synd_s          cn58xxp1;
-} cvmx_lmcx_ecc_synd_t;
-
-
-/**
- * cvmx_lmc#_fadr
- *
- * LMC_FADR = LMC Failing Address Register (SEC/DED)
- * 
- * This register only captures the first transaction with ecc errors. A DBE error can
- * over-write this register with its failing addresses. If you write
- * LMC_MEM_CFG0->SEC_ERR/DED_ERR then it will clear the error bits and capture the
- * next failing address.
- * The phy mapping is a function of the num Col bits & \# row bits
- * 
- * If failing dimm is 2 that means the error is in the higher bits dimm.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_fadr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t fdimm                   : 2;       /**< Failing DIMM# */
-        uint64_t fbunk                   : 1;       /**< Failing Rank */
-        uint64_t fbank                   : 3;       /**< Failing Bank[2:0] */
-        uint64_t frow                    : 14;      /**< Failing Row Address[13:0] */
-        uint64_t fcol                    : 12;      /**< Failing Column Start Address[11:0]
-                                                         Represents the Failing read's starting column address
-                                                         (and not the exact column address in which the SEC/DED
-                                                         was detected) */
-#else
-        uint64_t fcol                    : 12;
-        uint64_t frow                    : 14;
-        uint64_t fbank                   : 3;
-        uint64_t fbunk                   : 1;
-        uint64_t fdimm                   : 2;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_fadr_s              cn30xx;
-    struct cvmx_lmcx_fadr_s              cn31xx;
-    struct cvmx_lmcx_fadr_s              cn38xx;
-    struct cvmx_lmcx_fadr_s              cn38xxp2;
-    struct cvmx_lmcx_fadr_s              cn50xx;
-    struct cvmx_lmcx_fadr_s              cn52xx;
-    struct cvmx_lmcx_fadr_s              cn52xxp1;
-    struct cvmx_lmcx_fadr_s              cn56xx;
-    struct cvmx_lmcx_fadr_s              cn56xxp1;
-    struct cvmx_lmcx_fadr_s              cn58xx;
-    struct cvmx_lmcx_fadr_s              cn58xxp1;
-} cvmx_lmcx_fadr_t;
-
-
-/**
- * cvmx_lmc#_ifb_cnt_hi
- *
- * LMC_IFB_CNT_HI  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ifb_cnt_hi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ifbcnt_hi               : 32;      /**< Performance Counter to measure Bus Utilization
-                                                         Upper 32-bits of 64-bit counter that increments every
-                                                         cycle there is something in the in-flight buffer. */
-#else
-        uint64_t ifbcnt_hi               : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn30xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn31xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn38xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn38xxp2;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn50xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn52xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn52xxp1;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn56xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn56xxp1;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn58xx;
-    struct cvmx_lmcx_ifb_cnt_hi_s        cn58xxp1;
-} cvmx_lmcx_ifb_cnt_hi_t;
-
-
-/**
- * cvmx_lmc#_ifb_cnt_lo
- *
- * LMC_IFB_CNT_LO  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ifb_cnt_lo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ifbcnt_lo               : 32;      /**< Performance Counter
-                                                         Low 32-bits of 64-bit counter that increments every
-                                                         cycle there is something in the in-flight buffer. */
-#else
-        uint64_t ifbcnt_lo               : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn30xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn31xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn38xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn38xxp2;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn50xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn52xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn52xxp1;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn56xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn56xxp1;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn58xx;
-    struct cvmx_lmcx_ifb_cnt_lo_s        cn58xxp1;
-} cvmx_lmcx_ifb_cnt_lo_t;
-
-
-/**
- * cvmx_lmc#_mem_cfg0
- *
- * Specify the RSL base addresses for the block
- * 
- *                  LMC_MEM_CFG0 = LMC Memory Configuration Register0
- * 
- * This register controls certain parameters of  Memory Configuration
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_mem_cfg0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t reset                   : 1;       /**< Reset oneshot pulse for refresh counter,
-                                                         and LMC_OPS_CNT_*, LMC_IFB_CNT_*, and LMC_DCLK_CNT_*
-                                                         CSR's. SW should write this to a one, then re-write
-                                                         it to a zero to cause the reset. */
-        uint64_t silo_qc                 : 1;       /**< Adds a Quarter Cycle granularity to generate
-                                                         dqs pulse generation for silo.
-                                                         Combination of Silo_HC and Silo_QC gives the
-                                                         ability to position the read enable with quarter
-                                                         cycle resolution. This is applied on all the bytes
-                                                         uniformly. */
-        uint64_t bunk_ena                : 1;       /**< Bunk Enable aka RANK ena (for use with dual-rank DIMMs)
-                                                         For dual-rank DIMMs, the bunk_ena bit will enable
-                                                         the drive of the CS_N[1:0] pins based on the
-                                                         (pbank_lsb-1) address bit.
-                                                         Write 0 for SINGLE ranked DIMM's. */
-        uint64_t ded_err                 : 4;       /**< Double Error detected (DED) of Rd Data
-                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
-                                                         [25] corresponds to DQ[63:0], Phase0
-                                                         [26] corresponds to DQ[127:64], Phase0
-                                                         [27] corresponds to DQ[63:0], Phase1
-                                                         [28] corresponds to DQ[127:64], Phase1
-                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
-                                                         [25] corresponds to DQ[63:0], Phase0, cycle0
-                                                         [26] corresponds to DQ[63:0], Phase0, cycle1
-                                                         [27] corresponds to DQ[63:0], Phase1, cycle0
-                                                         [28] corresponds to DQ[63:0], Phase1, cycle1
-                                                         Write of 1 will clear the corresponding error bit */
-        uint64_t sec_err                 : 4;       /**< Single Error (corrected) of Rd Data
-                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
-                                                         [21] corresponds to DQ[63:0], Phase0
-                                                         [22] corresponds to DQ[127:64], Phase0
-                                                         [23] corresponds to DQ[63:0], Phase1
-                                                         [24] corresponds to DQ[127:64], Phase1
-                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
-                                                         [21] corresponds to DQ[63:0], Phase0, cycle0
-                                                         [22] corresponds to DQ[63:0], Phase0, cycle1
-                                                         [23] corresponds to DQ[63:0], Phase1, cycle0
-                                                         [24] corresponds to DQ[63:0], Phase1, cycle1
-                                                         Write of 1 will clear the corresponding error bit */
-        uint64_t intr_ded_ena            : 1;       /**< ECC Double Error Detect(DED) Interrupt Enable bit
-                                                         When set, the memory controller raises a processor
-                                                         interrupt on detecting an uncorrectable Dbl Bit ECC
-                                                         error. */
-        uint64_t intr_sec_ena            : 1;       /**< ECC Single Error Correct(SEC) Interrupt Enable bit
-                                                         When set, the memory controller raises a processor
-                                                         interrupt on detecting a correctable Single Bit ECC
-                                                         error. */
-        uint64_t tcl                     : 4;       /**< This register is not used */
-        uint64_t ref_int                 : 6;       /**< Refresh interval represented in \#of 512 dclk increments.
-                                                         Program this to RND-DN(tREFI/clkPeriod/512)
-                                                            - 000000: RESERVED
-                                                            - 000001: 1 * 512  = 512 dclks
-                                                             - ...
-                                                            - 111111: 63 * 512 = 32256 dclks */
-        uint64_t pbank_lsb               : 4;       /**< Physical Bank address select
-                                                                                 Reverting to the explanation for ROW_LSB,
-                                                                                 PBank_LSB would be Row_LSB bit + \#rowbits
-                                                                                 + \#rankbits
-                                                                                 In the 512MB DIMM Example, assuming no rank bits:
-                                                                                 pbank_lsb=mem_addr[15+13] for 64 b mode
-                                                                                          =mem_addr[16+13] for 128b mode
-                                                                                 Hence the parameter
-                                                         0000:pbank[1:0] = mem_adr[28:27]    / rank = mem_adr[26] (if bunk_ena)
-                                                         0001:pbank[1:0] = mem_adr[29:28]    / rank = mem_adr[27]      "
-                                                         0010:pbank[1:0] = mem_adr[30:29]    / rank = mem_adr[28]      "
-                                                         0011:pbank[1:0] = mem_adr[31:30]    / rank = mem_adr[29]      "
-                                                         0100:pbank[1:0] = mem_adr[32:31]    / rank = mem_adr[30]      "
-                                                         0101:pbank[1:0] = mem_adr[33:32]    / rank = mem_adr[31]      "
-                                                         0110:pbank[1:0] =[1'b0,mem_adr[33]] / rank = mem_adr[32]      "
-                                                         0111:pbank[1:0] =[2'b0]             / rank = mem_adr[33]      "
-                                                         1000-1111: RESERVED */
-        uint64_t row_lsb                 : 3;       /**< Encoding used to determine which memory address
-                                                         bit position represents the low order DDR ROW address.
-                                                         The processor's memory address[33:7] needs to be
-                                                         translated to DRAM addresses (bnk,row,col,rank and dimm)
-                                                         and that is a function of the following:
-                                                         1. \# Banks (4 or 8) - spec'd by BANK8
-                                                         2. Datapath Width(64 or 128) - MODE128b
-                                                         3. \# Ranks in a DIMM - spec'd by BUNK_ENA
-                                                         4. \# DIMM's in the system
-                                                         5. \# Column Bits of the memory part - spec'd indirectly
-                                                         by this register.
-                                                         6. \# Row Bits of the memory part - spec'd indirectly
-                                                         by the register below (PBANK_LSB).
-                                                         Illustration: For Micron's MT18HTF6472A,512MB DDR2
-                                                         Unbuffered DIMM which uses 256Mb parts (8M x 8 x 4),
-                                                         \# Banks = 4 -> 2 bits of BA
-                                                         \# Columns = 1K -> 10 bits of Col
-                                                         \# Rows = 8K -> 13 bits of Row
-                                                         Assuming that the total Data width is 128, this is how
-                                                         we arrive at row_lsb:
-                                                         Col Address starts from mem_addr[4] for 128b (16Bytes)
-                                                         dq width or from mem_addr[3] for 64b (8Bytes) dq width
-                                                         \# col + \# bank = 12. Hence row_lsb is mem_adr[15] for
-                                                         64bmode or mem_adr[16] for 128b mode. Hence row_lsb
-                                                         parameter should be set to 001 (64b) or 010 (128b).
-                                                              - 000: row_lsb = mem_adr[14]
-                                                              - 001: row_lsb = mem_adr[15]
-                                                              - 010: row_lsb = mem_adr[16]
-                                                              - 011: row_lsb = mem_adr[17]
-                                                              - 100: row_lsb = mem_adr[18]
-                                                              - 101-111:row_lsb = RESERVED */
-        uint64_t ecc_ena                 : 1;       /**< ECC Enable: When set will enable the 8b ECC
-                                                         check/correct logic. Should be 1 when used with DIMMs
-                                                         with ECC. 0, otherwise.
-                                                         When this mode is turned on, DQ[71:64] and DQ[143:137]
-                                                         on writes, will contain the ECC code generated for
-                                                         the lower 64 and upper 64 bits of data which will
-                                                         written in the memory and then later on reads, used
-                                                         to check for Single bit error (which will be auto-
-                                                         corrected) and Double Bit error (which will be
-                                                         reported). When not turned on, DQ[71:64] and DQ[143:137]
-                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
-                                                         LMC_FADR, and LMC_ECC_SYND registers
-                                                         for diagnostics information when there is an error. */
-        uint64_t init_start              : 1;       /**< A 0->1 transition starts the DDR memory initialization
-                                                         sequence. */
-#else
-        uint64_t init_start              : 1;
-        uint64_t ecc_ena                 : 1;
-        uint64_t row_lsb                 : 3;
-        uint64_t pbank_lsb               : 4;
-        uint64_t ref_int                 : 6;
-        uint64_t tcl                     : 4;
-        uint64_t intr_sec_ena            : 1;
-        uint64_t intr_ded_ena            : 1;
-        uint64_t sec_err                 : 4;
-        uint64_t ded_err                 : 4;
-        uint64_t bunk_ena                : 1;
-        uint64_t silo_qc                 : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_mem_cfg0_s          cn30xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn31xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn38xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn38xxp2;
-    struct cvmx_lmcx_mem_cfg0_s          cn50xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn52xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn52xxp1;
-    struct cvmx_lmcx_mem_cfg0_s          cn56xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn56xxp1;
-    struct cvmx_lmcx_mem_cfg0_s          cn58xx;
-    struct cvmx_lmcx_mem_cfg0_s          cn58xxp1;
-} cvmx_lmcx_mem_cfg0_t;
-
-
-/**
- * cvmx_lmc#_mem_cfg1
- *
- * LMC_MEM_CFG1 = LMC Memory Configuration Register1
- * 
- * This register controls the External Memory Configuration Timing Parameters. Please refer to the
- * appropriate DDR part spec from your memory vendor for the various values in this CSR.
- * The details of each of these timing parameters can be found in the JEDEC spec or the vendor
- * spec of the memory parts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_mem_cfg1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t comp_bypass             : 1;       /**< Compensation bypass. */
-        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
-                                                         banks. (Represented in tCYC cycles == 1dclks)
-                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
-                                                         For DDR2, TYP=7.5ns
-                                                            - 000: RESERVED
-                                                            - 001: 1 tCYC
-                                                            - 010: 2 tCYC
-                                                            - 011: 3 tCYC
-                                                            - 100: 4 tCYC
-                                                            - 101: 5 tCYC
-                                                            - 110: 6 tCYC
-                                                            - 111: 7 tCYC */
-        uint64_t caslat                  : 3;       /**< CAS Latency Encoding which is loaded into each DDR
-                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
-                                                         (Represented in tCYC cycles == 1 dclks)
-                                                            000 RESERVED
-                                                            001 RESERVED
-                                                            010 2.0 tCYC
-                                                            011 3.0 tCYC
-                                                            100 4.0 tCYC
-                                                            101 5.0 tCYC
-                                                            110 6.0 tCYC
-                                                            111 RESERVED
-                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
-                                                         account for 1/4 cycle granularity in board/etch delays. */
-        uint64_t tmrd                    : 3;       /**< tMRD Cycles
-                                                         (Represented in dclk tCYC)
-                                                         For DDR2, its TYP 2*tCYC)
-                                                             - 000: RESERVED
-                                                             - 001: 1
-                                                             - 010: 2
-                                                             - 011: 3
-                                                             - 100: 4
-                                                             - 101-111: RESERVED */
-        uint64_t trfc                    : 5;       /**< 1/4 tRFC Cycles = RNDUP[tRFC(ns)/4*tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclks)
-                                                         For 2Gb, DDR2-667 parts, typ=195ns
-                                                         (TRFC = 195/3/4 = 5'd17 = 0x11)
-                                                             - 00000-00001: RESERVED
-                                                             - 00010: 8
-                                                             - 00011: 12
-                                                             - 00100: 16
-                                                             - ...
-                                                             - 11110: 120
-                                                             - 11111: 124 */
-        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclk)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 1
-                                                             - ...
-                                                             - 1001: 9
-                                                             - 1010-1111: RESERVED
-                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
-                                                         is 1), load tRP cycles + 1 into this register. */
-        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
-                                                         Last Wr Data to Rd Command time.
-                                                         (Represented in tCYC cycles == 1dclks)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 1
-                                                             - ...
-                                                             - 0111: 7
-                                                             - 1000-1111: RESERVED */
-        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclk)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 2 (2 is the smallest value allowed)
-                                                             - 0002: 2
-                                                             - ...
-                                                             - 1001: 9
-                                                             - 1010-1111: RESERVED
-                                                         In 2T mode, make this register TRCD-1, not going
-                                                         below 2. */
-        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1 dclk)
-                                                             - 00000-0001: RESERVED
-                                                             - 00010: 2
-                                                             - ...
-                                                             - 11111: 31 */
-#else
-        uint64_t tras                    : 5;
-        uint64_t trcd                    : 4;
-        uint64_t twtr                    : 4;
-        uint64_t trp                     : 4;
-        uint64_t trfc                    : 5;
-        uint64_t tmrd                    : 3;
-        uint64_t caslat                  : 3;
-        uint64_t trrd                    : 3;
-        uint64_t comp_bypass             : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_mem_cfg1_s          cn30xx;
-    struct cvmx_lmcx_mem_cfg1_s          cn31xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
-                                                         banks. (Represented in tCYC cycles == 1dclks)
-                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
-                                                         For DDR2, TYP=7.5ns
-                                                            - 000: RESERVED
-                                                            - 001: 1 tCYC
-                                                            - 010: 2 tCYC
-                                                            - 011: 3 tCYC
-                                                            - 100: 4 tCYC
-                                                            - 101: 5 tCYC
-                                                            - 110-111: RESERVED */
-        uint64_t caslat                  : 3;       /**< CAS Latency Encoding which is loaded into each DDR
-                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
-                                                         (Represented in tCYC cycles == 1 dclks)
-                                                            000 RESERVED
-                                                            001 RESERVED
-                                                            010 2.0 tCYC
-                                                            011 3.0 tCYC
-                                                            100 4.0 tCYC
-                                                            101 5.0 tCYC
-                                                            110 6.0 tCYC (DDR2)
-                                                                2.5 tCYC (DDR1)
-                                                            111 RESERVED
-                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
-                                                         account for 1/4 cycle granularity in board/etch delays. */
-        uint64_t tmrd                    : 3;       /**< tMRD Cycles
-                                                         (Represented in dclk tCYC)
-                                                         For DDR2, its TYP 2*tCYC)
-                                                             - 000: RESERVED
-                                                             - 001: 1
-                                                             - 010: 2
-                                                             - 011: 3
-                                                             - 100: 4
-                                                             - 101-111: RESERVED */
-        uint64_t trfc                    : 5;       /**< 1/4 tRFC Cycles = RNDUP[tRFC(ns)/4*tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclks)
-                                                         For DDR-I, the following encodings are used
-                                                         TYP=70ns (133MHz - 3; 333MHz - 6)
-                                                         For 2Gb, DDR2-667 parts, typ=195ns
-                                                         (TRFC = 195/3/4 = 5'd17 = 0x11)
-                                                             - 00000-00001: RESERVED
-                                                             - 00010: 8
-                                                             - 00011: 12
-                                                             - 00100: 16
-                                                             - ...
-                                                             - 11110: 120
-                                                             - 11111: 124 */
-        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclk)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 1
-                                                             - ...
-                                                             - 0111: 7
-                                                             - 1000-1111: RESERVED
-                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
-                                                         is 1), load tRP cycles + 1 into this register. */
-        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
-                                                         Last Wr Data to Rd Command time.
-                                                         (Represented in tCYC cycles == 1dclks)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 1
-                                                             - ...
-                                                             - 0111: 7
-                                                             - 1000-1111: RESERVED */
-        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1dclk)
-                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
-                                                             - 0000: RESERVED
-                                                             - 0001: 2 (2 is the smallest value allowed)
-                                                             - 0002: 2
-                                                             - ...
-                                                             - 0111: 7
-                                                             - 1110-1111: RESERVED
-                                                         In 2T mode, make this register TRCD-1, not going
-                                                         below 2. */
-        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
-                                                         (Represented in tCYC cycles == 1 dclk)
-                                                         For DDR-I mode:
-                                                         TYP=45ns (66MHz=3,167MHz=8,400MHz=18
-                                                             - 00000-0001: RESERVED
-                                                             - 00010: 2
-                                                             - ...
-                                                             - 10100: 20
-                                                             - 10101-11111: RESERVED */
-#else
-        uint64_t tras                    : 5;
-        uint64_t trcd                    : 4;
-        uint64_t twtr                    : 4;
-        uint64_t trp                     : 4;
-        uint64_t trfc                    : 5;
-        uint64_t tmrd                    : 3;
-        uint64_t caslat                  : 3;
-        uint64_t trrd                    : 3;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn38xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn38xxp2;
-    struct cvmx_lmcx_mem_cfg1_s          cn50xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn52xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn52xxp1;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn56xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn56xxp1;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn58xx;
-    struct cvmx_lmcx_mem_cfg1_cn38xx     cn58xxp1;
-} cvmx_lmcx_mem_cfg1_t;
-
-
-/**
- * cvmx_lmc#_nxm
- *
- * LMC_NXM = LMC non-existent memory
- *
- *
- * Notes:
- * This CSR was introduced in pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_nxm_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t cs_mask                 : 8;       /**< Chip select mask.
-                                                         This mask corresponds to the 8 chip selects for a memory
-                                                         configuration.  If LMC_MEM_CFG0[BUNK_ENA]==0 then this
-                                                         mask must be set in pairs because each reference address
-                                                         will assert a pair of chip selects.  If the chip
-                                                         select(s) have a corresponding CS_MASK bit set, then the
-                                                         reference is to non-existent memory.  LMC will alias the
-                                                         reference to use the lowest, legal chip select(s) in
-                                                         that case. */
-#else
-        uint64_t cs_mask                 : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_lmcx_nxm_s               cn52xx;
-    struct cvmx_lmcx_nxm_s               cn56xx;
-    struct cvmx_lmcx_nxm_s               cn58xx;
-} cvmx_lmcx_nxm_t;
-
-
-/**
- * cvmx_lmc#_ops_cnt_hi
- *
- * LMC_OPS_CNT_HI  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ops_cnt_hi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t opscnt_hi               : 32;      /**< Performance Counter to measure Bus Utilization
-                                                         Upper 32-bits of 64-bit counter
-                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
-#else
-        uint64_t opscnt_hi               : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn30xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn31xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn38xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn38xxp2;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn50xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn52xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn52xxp1;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn56xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn56xxp1;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn58xx;
-    struct cvmx_lmcx_ops_cnt_hi_s        cn58xxp1;
-} cvmx_lmcx_ops_cnt_hi_t;
-
-
-/**
- * cvmx_lmc#_ops_cnt_lo
- *
- * LMC_OPS_CNT_LO  = Performance Counters
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_ops_cnt_lo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t opscnt_lo               : 32;      /**< Performance Counter
-                                                         Low 32-bits of 64-bit counter
-                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
-#else
-        uint64_t opscnt_lo               : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn30xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn31xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn38xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn38xxp2;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn50xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn52xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn52xxp1;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn56xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn56xxp1;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn58xx;
-    struct cvmx_lmcx_ops_cnt_lo_s        cn58xxp1;
-} cvmx_lmcx_ops_cnt_lo_t;
-
-
-/**
- * cvmx_lmc#_pll_bwctl
- *
- * LMC_PLL_BWCTL  = DDR PLL Bandwidth Control Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_pll_bwctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t bwupd                   : 1;       /**< Load this Bandwidth Register value into the PLL */
-        uint64_t bwctl                   : 4;       /**< Bandwidth Control Register for DDR PLL */
-#else
-        uint64_t bwctl                   : 4;
-        uint64_t bwupd                   : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_lmcx_pll_bwctl_s         cn30xx;
-    struct cvmx_lmcx_pll_bwctl_s         cn31xx;
-    struct cvmx_lmcx_pll_bwctl_s         cn38xx;
-    struct cvmx_lmcx_pll_bwctl_s         cn38xxp2;
-} cvmx_lmcx_pll_bwctl_t;
-
-
-/**
- * cvmx_lmc#_pll_ctl
- *
- * LMC_PLL_CTL = LMC pll control
- *
- *
- * Notes:
- * This CSR is only relevant for LMC0. LMC1_PLL_CTL is not used.
- * 
- * Exactly one of EN2, EN4, EN6, EN8, EN12, EN16 must be set.
- * 
- * The resultant DDR_CK frequency is the DDR2_REF_CLK
- * frequency multiplied by:
- * 
- *     (CLKF + 1) / ((CLKR + 1) * EN(2,4,6,8,12,16))
- * 
- * The PLL frequency, which is:
- * 
- *     (DDR2_REF_CLK freq) * ((CLKF + 1) / (CLKR + 1))
- * 
- * must reside between 1.2 and 2.5 GHz. A faster PLL frequency is desirable if there is a choice.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_pll_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_30_63          : 34;
-        uint64_t bypass                  : 1;       /**< PLL Bypass */
-        uint64_t fasten_n                : 1;       /**< Should be set, especially when CLKF > ~80 */
-        uint64_t div_reset               : 1;       /**< Analog pll divider reset
-                                                         De-assert at least 500*(CLKR+1) reference clock
-                                                         cycles following RESET_N de-assertion. */
-        uint64_t reset_n                 : 1;       /**< Analog pll reset
-                                                         De-assert at least 5 usec after CLKF, CLKR,
-                                                         and EN* are set up. */
-        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
-                                                         CLKF must be <= 128 */
-        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
-        uint64_t reserved_6_7            : 2;
-        uint64_t en16                    : 1;       /**< Divide output by 16 */
-        uint64_t en12                    : 1;       /**< Divide output by 12 */
-        uint64_t en8                     : 1;       /**< Divide output by 8 */
-        uint64_t en6                     : 1;       /**< Divide output by 6 */
-        uint64_t en4                     : 1;       /**< Divide output by 4 */
-        uint64_t en2                     : 1;       /**< Divide output by 2 */
-#else
-        uint64_t en2                     : 1;
-        uint64_t en4                     : 1;
-        uint64_t en6                     : 1;
-        uint64_t en8                     : 1;
-        uint64_t en12                    : 1;
-        uint64_t en16                    : 1;
-        uint64_t reserved_6_7            : 2;
-        uint64_t clkr                    : 6;
-        uint64_t clkf                    : 12;
-        uint64_t reset_n                 : 1;
-        uint64_t div_reset               : 1;
-        uint64_t fasten_n                : 1;
-        uint64_t bypass                  : 1;
-        uint64_t reserved_30_63          : 34;
-#endif
-    } s;
-    struct cvmx_lmcx_pll_ctl_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t fasten_n                : 1;       /**< Should be set, especially when CLKF > ~80 */
-        uint64_t div_reset               : 1;       /**< Analog pll divider reset
-                                                         De-assert at least 500*(CLKR+1) reference clock
-                                                         cycles following RESET_N de-assertion. */
-        uint64_t reset_n                 : 1;       /**< Analog pll reset
-                                                         De-assert at least 5 usec after CLKF, CLKR,
-                                                         and EN* are set up. */
-        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
-                                                         CLKF must be <= 256 */
-        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
-        uint64_t reserved_6_7            : 2;
-        uint64_t en16                    : 1;       /**< Divide output by 16 */
-        uint64_t en12                    : 1;       /**< Divide output by 12 */
-        uint64_t en8                     : 1;       /**< Divide output by 8 */
-        uint64_t en6                     : 1;       /**< Divide output by 6 */
-        uint64_t en4                     : 1;       /**< Divide output by 4 */
-        uint64_t en2                     : 1;       /**< Divide output by 2 */
-#else
-        uint64_t en2                     : 1;
-        uint64_t en4                     : 1;
-        uint64_t en6                     : 1;
-        uint64_t en8                     : 1;
-        uint64_t en12                    : 1;
-        uint64_t en16                    : 1;
-        uint64_t reserved_6_7            : 2;
-        uint64_t clkr                    : 6;
-        uint64_t clkf                    : 12;
-        uint64_t reset_n                 : 1;
-        uint64_t div_reset               : 1;
-        uint64_t fasten_n                : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn50xx;
-    struct cvmx_lmcx_pll_ctl_s           cn52xx;
-    struct cvmx_lmcx_pll_ctl_s           cn52xxp1;
-    struct cvmx_lmcx_pll_ctl_cn50xx      cn56xx;
-    struct cvmx_lmcx_pll_ctl_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t div_reset               : 1;       /**< Analog pll divider reset
-                                                         De-assert at least 500*(CLKR+1) reference clock
-                                                         cycles following RESET_N de-assertion. */
-        uint64_t reset_n                 : 1;       /**< Analog pll reset
-                                                         De-assert at least 5 usec after CLKF, CLKR,
-                                                         and EN* are set up. */
-        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
-                                                         CLKF must be <= 128 */
-        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
-        uint64_t reserved_6_7            : 2;
-        uint64_t en16                    : 1;       /**< Divide output by 16 */
-        uint64_t en12                    : 1;       /**< Divide output by 12 */
-        uint64_t en8                     : 1;       /**< Divide output by 8 */
-        uint64_t en6                     : 1;       /**< Divide output by 6 */
-        uint64_t en4                     : 1;       /**< Divide output by 4 */
-        uint64_t en2                     : 1;       /**< Divide output by 2 */
-#else
-        uint64_t en2                     : 1;
-        uint64_t en4                     : 1;
-        uint64_t en6                     : 1;
-        uint64_t en8                     : 1;
-        uint64_t en12                    : 1;
-        uint64_t en16                    : 1;
-        uint64_t reserved_6_7            : 2;
-        uint64_t clkr                    : 6;
-        uint64_t clkf                    : 12;
-        uint64_t reset_n                 : 1;
-        uint64_t div_reset               : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn56xxp1;
-    struct cvmx_lmcx_pll_ctl_cn56xxp1    cn58xx;
-    struct cvmx_lmcx_pll_ctl_cn56xxp1    cn58xxp1;
-} cvmx_lmcx_pll_ctl_t;
-
-
-/**
- * cvmx_lmc#_pll_status
- *
- * LMC_PLL_STATUS = LMC pll status
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_pll_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ddr__nctl               : 5;       /**< DDR nctl from compensation circuit */
-        uint64_t ddr__pctl               : 5;       /**< DDR pctl from compensation circuit */
-        uint64_t reserved_2_21           : 20;
-        uint64_t rfslip                  : 1;       /**< Reference clock slip */
-        uint64_t fbslip                  : 1;       /**< Feedback clock slip */
-#else
-        uint64_t fbslip                  : 1;
-        uint64_t rfslip                  : 1;
-        uint64_t reserved_2_21           : 20;
-        uint64_t ddr__pctl               : 5;
-        uint64_t ddr__nctl               : 5;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_pll_status_s        cn50xx;
-    struct cvmx_lmcx_pll_status_s        cn52xx;
-    struct cvmx_lmcx_pll_status_s        cn52xxp1;
-    struct cvmx_lmcx_pll_status_s        cn56xx;
-    struct cvmx_lmcx_pll_status_s        cn56xxp1;
-    struct cvmx_lmcx_pll_status_s        cn58xx;
-    struct cvmx_lmcx_pll_status_cn58xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t rfslip                  : 1;       /**< Reference clock slip */
-        uint64_t fbslip                  : 1;       /**< Feedback clock slip */
-#else
-        uint64_t fbslip                  : 1;
-        uint64_t rfslip                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn58xxp1;
-} cvmx_lmcx_pll_status_t;
-
-
-/**
- * cvmx_lmc#_read_level_ctl
- *
- * Notes:
- * The HW writes and reads the cache block selected by ROW, COL, BNK and the rank as part of a read-leveling sequence for a rank.
- * A cache block write is 16 72-bit words. PATTERN selects the write value. For the first 8
- * words, the write value is the bit PATTERN<i> duplicated into a 72-bit vector. The write value of
- * the last 8 words is the inverse of the write value of the first 8 words.
- * See LMC*_READ_LEVEL_RANK*.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_read_level_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t rankmask                : 4;       /**< Selects ranks to be leveled
-                                                         to read-level rank i, set RANKMASK<i> */
-        uint64_t pattern                 : 8;       /**< All DQ driven to PATTERN[burst], 0 <= burst <= 7
-                                                         All DQ driven to ~PATTERN[burst-8], 8 <= burst <= 15 */
-        uint64_t row                     : 16;      /**< Row    address used to write/read data pattern */
-        uint64_t col                     : 12;      /**< Column address used to write/read data pattern */
-        uint64_t reserved_3_3            : 1;
-        uint64_t bnk                     : 3;       /**< Bank   address used to write/read data pattern */
-#else
-        uint64_t bnk                     : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t col                     : 12;
-        uint64_t row                     : 16;
-        uint64_t pattern                 : 8;
-        uint64_t rankmask                : 4;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_lmcx_read_level_ctl_s    cn52xx;
-    struct cvmx_lmcx_read_level_ctl_s    cn52xxp1;
-    struct cvmx_lmcx_read_level_ctl_s    cn56xx;
-    struct cvmx_lmcx_read_level_ctl_s    cn56xxp1;
-} cvmx_lmcx_read_level_ctl_t;
-
-
-/**
- * cvmx_lmc#_read_level_dbg
- *
- * Notes:
- * A given read of LMC*_READ_LEVEL_DBG returns the read-leveling pass/fail results for all possible
- * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled.
- * LMC*_READ_LEVEL_DBG[BYTE] selects the particular byte.
- * To get these pass/fail results for another different rank, you must run the hardware read-leveling
- * again. For example, it is possible to get the BITMASK results for every byte of every rank
- * if you run read-leveling separately for each rank, probing LMC*_READ_LEVEL_DBG between each
- * read-leveling.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_read_level_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bitmask                 : 16;      /**< Bitmask generated during deskew settings sweep
-                                                         BITMASK[n]=0 means deskew setting n failed
-                                                         BITMASK[n]=1 means deskew setting n passed
-                                                         for 0 <= n <= 15 */
-        uint64_t reserved_4_15           : 12;
-        uint64_t byte                    : 4;       /**< 0 <= BYTE <= 8 */
-#else
-        uint64_t byte                    : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t bitmask                 : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_read_level_dbg_s    cn52xx;
-    struct cvmx_lmcx_read_level_dbg_s    cn52xxp1;
-    struct cvmx_lmcx_read_level_dbg_s    cn56xx;
-    struct cvmx_lmcx_read_level_dbg_s    cn56xxp1;
-} cvmx_lmcx_read_level_dbg_t;
-
-
-/**
- * cvmx_lmc#_read_level_rank#
- *
- * Notes:
- * This is four CSRs per LMC, one per each rank.
- * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.)
- * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
- * Deskew setting is measured in units of 1/4 DCLK, so the above BYTE* values can range over 4 DCLKs.
- * SW initiates a HW read-leveling sequence by programming LMC*_READ_LEVEL_CTL and writing INIT_START=1 with SEQUENCE=1.
- * See LMC*_READ_LEVEL_CTL.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_read_level_rankx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t status                  : 2;       /**< Indicates status of the read-levelling and where
-                                                         the BYTE* programmings in <35:0> came from:
-                                                         0 = BYTE* values are their reset value
-                                                         1 = BYTE* values were set via a CSR write to this register
-                                                         2 = read-leveling sequence currently in progress (BYTE* values are unpredictable)
-                                                         3 = BYTE* values came from a complete read-leveling sequence */
-        uint64_t byte8                   : 4;       /**< Deskew setting */
-        uint64_t byte7                   : 4;       /**< Deskew setting */
-        uint64_t byte6                   : 4;       /**< Deskew setting */
-        uint64_t byte5                   : 4;       /**< Deskew setting */
-        uint64_t byte4                   : 4;       /**< Deskew setting */
-        uint64_t byte3                   : 4;       /**< Deskew setting */
-        uint64_t byte2                   : 4;       /**< Deskew setting */
-        uint64_t byte1                   : 4;       /**< Deskew setting */
-        uint64_t byte0                   : 4;       /**< Deskew setting */
-#else
-        uint64_t byte0                   : 4;
-        uint64_t byte1                   : 4;
-        uint64_t byte2                   : 4;
-        uint64_t byte3                   : 4;
-        uint64_t byte4                   : 4;
-        uint64_t byte5                   : 4;
-        uint64_t byte6                   : 4;
-        uint64_t byte7                   : 4;
-        uint64_t byte8                   : 4;
-        uint64_t status                  : 2;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_lmcx_read_level_rankx_s  cn52xx;
-    struct cvmx_lmcx_read_level_rankx_s  cn52xxp1;
-    struct cvmx_lmcx_read_level_rankx_s  cn56xx;
-    struct cvmx_lmcx_read_level_rankx_s  cn56xxp1;
-} cvmx_lmcx_read_level_rankx_t;
-
-
-/**
- * cvmx_lmc#_rodt_comp_ctl
- *
- * LMC_RODT_COMP_CTL = LMC Compensation control
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_rodt_comp_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t enable                  : 1;       /**< 0=not enabled, 1=enable */
-        uint64_t reserved_12_15          : 4;
-        uint64_t nctl                    : 4;       /**< Compensation control bits */
-        uint64_t reserved_5_7            : 3;
-        uint64_t pctl                    : 5;       /**< Compensation control bits */
-#else
-        uint64_t pctl                    : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t nctl                    : 4;
-        uint64_t reserved_12_15          : 4;
-        uint64_t enable                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn50xx;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn52xx;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn52xxp1;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn56xx;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn56xxp1;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn58xx;
-    struct cvmx_lmcx_rodt_comp_ctl_s     cn58xxp1;
-} cvmx_lmcx_rodt_comp_ctl_t;
-
-
-/**
- * cvmx_lmc#_rodt_ctl
- *
- * LMC_RODT_CTL = Obsolete LMC Read OnDieTermination control
- * See the description in LMC_WODT_CTL1. On Reads, Octeon only supports turning on ODT's in
- * the lower 2 DIMM's with the masks as below.
- *
- * Notes:
- * When a given RANK in position N is selected, the RODT _HI and _LO masks for that position are used.
- * Mask[3:0] is used for RODT control of the RANKs in positions 3, 2, 1, and 0, respectively.
- * In  64b mode, DIMMs are assumed to be ordered in the following order:
- *  position 3: [unused        , DIMM1_RANK1_LO]
- *  position 2: [unused        , DIMM1_RANK0_LO]
- *  position 1: [unused        , DIMM0_RANK1_LO]
- *  position 0: [unused        , DIMM0_RANK0_LO]
- * In 128b mode, DIMMs are assumed to be ordered in the following order:
- *  position 3: [DIMM3_RANK1_HI, DIMM1_RANK1_LO]
- *  position 2: [DIMM3_RANK0_HI, DIMM1_RANK0_LO]
- *  position 1: [DIMM2_RANK1_HI, DIMM0_RANK1_LO]
- *  position 0: [DIMM2_RANK0_HI, DIMM0_RANK0_LO]
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_rodt_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rodt_hi3                : 4;       /**< Read ODT mask for position 3, data[127:64] */
-        uint64_t rodt_hi2                : 4;       /**< Read ODT mask for position 2, data[127:64] */
-        uint64_t rodt_hi1                : 4;       /**< Read ODT mask for position 1, data[127:64] */
-        uint64_t rodt_hi0                : 4;       /**< Read ODT mask for position 0, data[127:64] */
-        uint64_t rodt_lo3                : 4;       /**< Read ODT mask for position 3, data[ 63: 0] */
-        uint64_t rodt_lo2                : 4;       /**< Read ODT mask for position 2, data[ 63: 0] */
-        uint64_t rodt_lo1                : 4;       /**< Read ODT mask for position 1, data[ 63: 0] */
-        uint64_t rodt_lo0                : 4;       /**< Read ODT mask for position 0, data[ 63: 0] */
-#else
-        uint64_t rodt_lo0                : 4;
-        uint64_t rodt_lo1                : 4;
-        uint64_t rodt_lo2                : 4;
-        uint64_t rodt_lo3                : 4;
-        uint64_t rodt_hi0                : 4;
-        uint64_t rodt_hi1                : 4;
-        uint64_t rodt_hi2                : 4;
-        uint64_t rodt_hi3                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_rodt_ctl_s          cn30xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn31xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn38xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn38xxp2;
-    struct cvmx_lmcx_rodt_ctl_s          cn50xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn52xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn52xxp1;
-    struct cvmx_lmcx_rodt_ctl_s          cn56xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn56xxp1;
-    struct cvmx_lmcx_rodt_ctl_s          cn58xx;
-    struct cvmx_lmcx_rodt_ctl_s          cn58xxp1;
-} cvmx_lmcx_rodt_ctl_t;
-
-
-/**
- * cvmx_lmc#_wodt_ctl0
- *
- * LMC_WODT_CTL0 = LMC Write OnDieTermination control
- * See the description in LMC_WODT_CTL1.
- *
- * Notes:
- * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.  See LMC_WODT_CTL1.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_wodt_ctl0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wodt_d1_r1              : 8;       /**< Write ODT mask DIMM1, RANK1 */
-        uint64_t wodt_d1_r0              : 8;       /**< Write ODT mask DIMM1, RANK0 */
-        uint64_t wodt_d0_r1              : 8;       /**< Write ODT mask DIMM0, RANK1 */
-        uint64_t wodt_d0_r0              : 8;       /**< Write ODT mask DIMM0, RANK0 */
-#else
-        uint64_t wodt_d0_r0              : 8;
-        uint64_t wodt_d0_r1              : 8;
-        uint64_t wodt_d1_r0              : 8;
-        uint64_t wodt_d1_r1              : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn31xx;
-    struct cvmx_lmcx_wodt_ctl0_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wodt_hi3                : 4;       /**< Write ODT mask for position 3, data[127:64] */
-        uint64_t wodt_hi2                : 4;       /**< Write ODT mask for position 2, data[127:64] */
-        uint64_t wodt_hi1                : 4;       /**< Write ODT mask for position 1, data[127:64] */
-        uint64_t wodt_hi0                : 4;       /**< Write ODT mask for position 0, data[127:64] */
-        uint64_t wodt_lo3                : 4;       /**< Write ODT mask for position 3, data[ 63: 0] */
-        uint64_t wodt_lo2                : 4;       /**< Write ODT mask for position 2, data[ 63: 0] */
-        uint64_t wodt_lo1                : 4;       /**< Write ODT mask for position 1, data[ 63: 0] */
-        uint64_t wodt_lo0                : 4;       /**< Write ODT mask for position 0, data[ 63: 0] */
-#else
-        uint64_t wodt_lo0                : 4;
-        uint64_t wodt_lo1                : 4;
-        uint64_t wodt_lo2                : 4;
-        uint64_t wodt_lo3                : 4;
-        uint64_t wodt_hi0                : 4;
-        uint64_t wodt_hi1                : 4;
-        uint64_t wodt_hi2                : 4;
-        uint64_t wodt_hi3                : 4;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn38xxp2;
-    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn50xx;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn52xx;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn52xxp1;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn56xx;
-    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn56xxp1;
-    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn58xx;
-    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn58xxp1;
-} cvmx_lmcx_wodt_ctl0_t;
-
-
-/**
- * cvmx_lmc#_wodt_ctl1
- *
- * LMC_WODT_CTL1 = LMC Write OnDieTermination control
- * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations
- * (667MHz and faster), especially on a multi-rank system. DDR2 DQ/DM/DQS I/O's have built in
- * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
- * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
- * in that DIMM. System designers may prefer different combinations of ODT ON's for read and write
- * into different ranks. Octeon supports full programmability by way of the mask register below.
- * Each Rank position has its own 8-bit programmable field.
- * When the controller does a write to that rank, it sets the 8 ODT pins to the MASK pins below.
- * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines
- * with the resistor on Dimm0/Rank1. The mask WODT_D0_R0 would then be [00000010].
- * If ODT feature is not desired, the DDR parts can be programmed to not look at these pins by
- * writing 0 in QS_DIC. Octeon drives the appropriate mask values on the ODT pins by default.
- * If this feature is not required, write 0 in this register.
- *
- * Notes:
- * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.
- * When a given RANK is selected, the WODT mask for that RANK is used.  The resulting WODT mask is
- * driven to the DIMMs in the following manner:
- *            BUNK_ENA=1     BUNK_ENA=0
- * Mask[7] -> DIMM3, RANK1    DIMM3
- * Mask[6] -> DIMM3, RANK0
- * Mask[5] -> DIMM2, RANK1    DIMM2
- * Mask[4] -> DIMM2, RANK0
- * Mask[3] -> DIMM1, RANK1    DIMM1
- * Mask[2] -> DIMM1, RANK0
- * Mask[1] -> DIMM0, RANK1    DIMM0
- * Mask[0] -> DIMM0, RANK0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_lmcx_wodt_ctl1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wodt_d3_r1              : 8;       /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked */
-        uint64_t wodt_d3_r0              : 8;       /**< Write ODT mask DIMM3, RANK0 */
-        uint64_t wodt_d2_r1              : 8;       /**< Write ODT mask DIMM2, RANK1/DIMM2 in SingleRanked */
-        uint64_t wodt_d2_r0              : 8;       /**< Write ODT mask DIMM2, RANK0 */
-#else
-        uint64_t wodt_d2_r0              : 8;
-        uint64_t wodt_d2_r1              : 8;
-        uint64_t wodt_d3_r0              : 8;
-        uint64_t wodt_d3_r1              : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_lmcx_wodt_ctl1_s         cn30xx;
-    struct cvmx_lmcx_wodt_ctl1_s         cn31xx;
-    struct cvmx_lmcx_wodt_ctl1_s         cn52xx;
-    struct cvmx_lmcx_wodt_ctl1_s         cn52xxp1;
-    struct cvmx_lmcx_wodt_ctl1_s         cn56xx;
-    struct cvmx_lmcx_wodt_ctl1_s         cn56xxp1;
-} cvmx_lmcx_wodt_ctl1_t;
-
-
-/**
- * cvmx_mio_boot_bist_stat
- *
- * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register
- * 
- * Contains the BIST status for the MIO boot memories.  '0' = pass, '1' = fail.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_bist_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_boot_bist_stat_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ncbo_1                  : 1;       /**< NCB output FIFO 1 BIST status */
-        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO 0 BIST status */
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t ncbo_0                  : 1;
-        uint64_t ncbo_1                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
-    struct cvmx_mio_boot_bist_stat_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t ncbo_0                  : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn38xx;
-    struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
-    struct cvmx_mio_boot_bist_stat_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t pcm_1                   : 1;       /**< PCM memory 1 BIST status */
-        uint64_t pcm_0                   : 1;       /**< PCM memory 0 BIST status */
-        uint64_t ncbo_1                  : 1;       /**< NCB output FIFO 1 BIST status */
-        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO 0 BIST status */
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t ncbo_0                  : 1;
-        uint64_t ncbo_1                  : 1;
-        uint64_t pcm_0                   : 1;
-        uint64_t pcm_1                   : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } cn50xx;
-    struct cvmx_mio_boot_bist_stat_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t ndf                     : 2;       /**< NAND flash BIST status */
-        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
-        uint64_t dma                     : 1;       /**< DMA memory BIST status */
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t dma                     : 1;
-        uint64_t ncbo_0                  : 1;
-        uint64_t ndf                     : 2;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } cn52xx;
-    struct cvmx_mio_boot_bist_stat_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
-        uint64_t dma                     : 1;       /**< DMA memory BIST status */
-        uint64_t loc                     : 1;       /**< Local memory BIST status */
-        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
-#else
-        uint64_t ncbi                    : 1;
-        uint64_t loc                     : 1;
-        uint64_t dma                     : 1;
-        uint64_t ncbo_0                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn52xxp1;
-    struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
-    struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
-    struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
-    struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
-} cvmx_mio_boot_bist_stat_t;
-
-
-/**
- * cvmx_mio_boot_comp
- *
- * MIO_BOOT_COMP = MIO Boot Compensation Register
- * 
- * Reset value is as follows:
- * 
- * no pullups,               PCTL=0x1f, NCTL=0x1f
- * pullup on boot_ad[9],     PCTL=0x1b, NCTL=0x1b (20 ohm termination)
- * pullup on boot_ad[10],    PCTL=0x07, NCTL=0x08 (50 ohm termination)
- * pullups on boot_ad[10:9], PCTL=0x06, NCTL=0x04 (60 ohm termination)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_comp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pctl                    : 5;       /**< Boot bus PCTL */
-        uint64_t nctl                    : 5;       /**< Boot bus NCTL */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_mio_boot_comp_s          cn50xx;
-    struct cvmx_mio_boot_comp_s          cn52xx;
-    struct cvmx_mio_boot_comp_s          cn52xxp1;
-    struct cvmx_mio_boot_comp_s          cn56xx;
-    struct cvmx_mio_boot_comp_s          cn56xxp1;
-} cvmx_mio_boot_comp_t;
-
-
-/**
- * cvmx_mio_boot_dma_cfg#
- *
- * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines)
- * 
- * SIZE is specified in number of bus transfers, where one transfer is equal to the following number
- * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]:
- * 
- * WIDTH     DDR      Transfer Size (bytes)
- * ----------------------------------------
- *   0        0               2
- *   0        1               4
- *   1        0               4
- *   1        1               8
- * 
- * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_dma_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t en                      : 1;       /**< DMA Engine X enable */
-        uint64_t rw                      : 1;       /**< DMA Engine X R/W bit (0 = read, 1 = write) */
-        uint64_t clr                     : 1;       /**< DMA Engine X clear EN on device terminated burst */
-        uint64_t reserved_60_60          : 1;
-        uint64_t swap32                  : 1;       /**< DMA Engine X 32 bit swap */
-        uint64_t swap16                  : 1;       /**< DMA Engine X 16 bit swap */
-        uint64_t swap8                   : 1;       /**< DMA Engine X 8 bit swap */
-        uint64_t endian                  : 1;       /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */
-        uint64_t size                    : 20;      /**< DMA Engine X size */
-        uint64_t adr                     : 36;      /**< DMA Engine X address */
-#else
-        uint64_t adr                     : 36;
-        uint64_t size                    : 20;
-        uint64_t endian                  : 1;
-        uint64_t swap8                   : 1;
-        uint64_t swap16                  : 1;
-        uint64_t swap32                  : 1;
-        uint64_t reserved_60_60          : 1;
-        uint64_t clr                     : 1;
-        uint64_t rw                      : 1;
-        uint64_t en                      : 1;
-#endif
-    } s;
-    struct cvmx_mio_boot_dma_cfgx_s      cn52xx;
-    struct cvmx_mio_boot_dma_cfgx_s      cn52xxp1;
-    struct cvmx_mio_boot_dma_cfgx_s      cn56xx;
-    struct cvmx_mio_boot_dma_cfgx_s      cn56xxp1;
-} cvmx_mio_boot_dma_cfgx_t;
-
-
-/**
- * cvmx_mio_boot_dma_int#
- *
- * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_dma_intx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dmarq                   : 1;       /**< DMA Engine X DMARQ asserted interrupt */
-        uint64_t done                    : 1;       /**< DMA Engine X request completion interrupt */
-#else
-        uint64_t done                    : 1;
-        uint64_t dmarq                   : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_boot_dma_intx_s      cn52xx;
-    struct cvmx_mio_boot_dma_intx_s      cn52xxp1;
-    struct cvmx_mio_boot_dma_intx_s      cn56xx;
-    struct cvmx_mio_boot_dma_intx_s      cn56xxp1;
-} cvmx_mio_boot_dma_intx_t;
-
-
-/**
- * cvmx_mio_boot_dma_int_en#
- *
- * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_dma_int_enx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dmarq                   : 1;       /**< DMA Engine X DMARQ asserted interrupt enable */
-        uint64_t done                    : 1;       /**< DMA Engine X request completion interrupt enable */
-#else
-        uint64_t done                    : 1;
-        uint64_t dmarq                   : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_boot_dma_int_enx_s   cn52xx;
-    struct cvmx_mio_boot_dma_int_enx_s   cn52xxp1;
-    struct cvmx_mio_boot_dma_int_enx_s   cn56xx;
-    struct cvmx_mio_boot_dma_int_enx_s   cn56xxp1;
-} cvmx_mio_boot_dma_int_enx_t;
-
-
-/**
- * cvmx_mio_boot_dma_tim#
- *
- * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines)
- * 
- * DMACK_PI inverts the assertion level of boot_dmack[n].  The default polarity of boot_dmack[1:0] is
- * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high
- * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity).
- * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default
- * polarity on engine n.  To interface with CF cards in True IDE Mode, either a pullup should be placed
- * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set.
- * 
- * DMARQ_PI inverts the assertion level of boot_dmarq[n].  The default polarity of boot_dmarq[1:0] is
- * active high, thus setting the polarity inversion bits changes the polarity to active low.  To
- * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear.
- * 
- * TIM_MULT specifies the timing multiplier for an engine.  The timing multiplier applies to all timing
- * parameters, except for DMARQ and RD_DLY, which simply count eclks.  TIM_MULT is encoded as follows:
- * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x.
- * 
- * RD_DLY specifies the read sample delay in eclk cycles for an engine.  For reads, the data bus is
- * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode).
- * This parameter can delay that sampling edge by up to 7 eclks.  Note: the number of eclk cycles
- * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY.
- * 
- * If DDR is set, then WE_N must be less than WE_A.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_dma_timx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dmack_pi                : 1;       /**< DMA Engine X DMA ack polarity inversion */
-        uint64_t dmarq_pi                : 1;       /**< DMA Engine X DMA request polarity inversion */
-        uint64_t tim_mult                : 2;       /**< DMA Engine X timing multiplier */
-        uint64_t rd_dly                  : 3;       /**< DMA Engine X read sample delay */
-        uint64_t ddr                     : 1;       /**< DMA Engine X DDR mode */
-        uint64_t width                   : 1;       /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */
-        uint64_t reserved_48_54          : 7;
-        uint64_t pause                   : 6;       /**< DMA Engine X pause count */
-        uint64_t dmack_h                 : 6;       /**< DMA Engine X DMA ack hold count */
-        uint64_t we_n                    : 6;       /**< DMA Engine X write enable negated count */
-        uint64_t we_a                    : 6;       /**< DMA Engine X write enable asserted count */
-        uint64_t oe_n                    : 6;       /**< DMA Engine X output enable negated count */
-        uint64_t oe_a                    : 6;       /**< DMA Engine X output enable asserted count */
-        uint64_t dmack_s                 : 6;       /**< DMA Engine X DMA ack setup count */
-        uint64_t dmarq                   : 6;       /**< DMA Engine X DMA request count (must be non-zero) */
-#else
-        uint64_t dmarq                   : 6;
-        uint64_t dmack_s                 : 6;
-        uint64_t oe_a                    : 6;
-        uint64_t oe_n                    : 6;
-        uint64_t we_a                    : 6;
-        uint64_t we_n                    : 6;
-        uint64_t dmack_h                 : 6;
-        uint64_t pause                   : 6;
-        uint64_t reserved_48_54          : 7;
-        uint64_t width                   : 1;
-        uint64_t ddr                     : 1;
-        uint64_t rd_dly                  : 3;
-        uint64_t tim_mult                : 2;
-        uint64_t dmarq_pi                : 1;
-        uint64_t dmack_pi                : 1;
-#endif
-    } s;
-    struct cvmx_mio_boot_dma_timx_s      cn52xx;
-    struct cvmx_mio_boot_dma_timx_s      cn52xxp1;
-    struct cvmx_mio_boot_dma_timx_s      cn56xx;
-    struct cvmx_mio_boot_dma_timx_s      cn56xxp1;
-} cvmx_mio_boot_dma_timx_t;
-
-
-/**
- * cvmx_mio_boot_err
- *
- * MIO_BOOT_ERR = MIO Boot Error Register
- * 
- * Contains the address decode error and wait mode error bits.  Address decode error is set when a
- * boot bus access does not hit in any of the 8 remote regions or 2 local regions.  Wait mode error is
- * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t wait_err                : 1;       /**< Wait mode error */
-        uint64_t adr_err                 : 1;       /**< Address decode error */
-#else
-        uint64_t adr_err                 : 1;
-        uint64_t wait_err                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_boot_err_s           cn30xx;
-    struct cvmx_mio_boot_err_s           cn31xx;
-    struct cvmx_mio_boot_err_s           cn38xx;
-    struct cvmx_mio_boot_err_s           cn38xxp2;
-    struct cvmx_mio_boot_err_s           cn50xx;
-    struct cvmx_mio_boot_err_s           cn52xx;
-    struct cvmx_mio_boot_err_s           cn52xxp1;
-    struct cvmx_mio_boot_err_s           cn56xx;
-    struct cvmx_mio_boot_err_s           cn56xxp1;
-    struct cvmx_mio_boot_err_s           cn58xx;
-    struct cvmx_mio_boot_err_s           cn58xxp1;
-} cvmx_mio_boot_err_t;
-
-
-/**
- * cvmx_mio_boot_int
- *
- * MIO_BOOT_INT = MIO Boot Interrupt Register
- * 
- * Contains the interrupt enable bits for address decode error and wait mode error.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t wait_int                : 1;       /**< Wait mode error interrupt enable */
-        uint64_t adr_int                 : 1;       /**< Address decode error interrupt enable */
-#else
-        uint64_t adr_int                 : 1;
-        uint64_t wait_int                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_boot_int_s           cn30xx;
-    struct cvmx_mio_boot_int_s           cn31xx;
-    struct cvmx_mio_boot_int_s           cn38xx;
-    struct cvmx_mio_boot_int_s           cn38xxp2;
-    struct cvmx_mio_boot_int_s           cn50xx;
-    struct cvmx_mio_boot_int_s           cn52xx;
-    struct cvmx_mio_boot_int_s           cn52xxp1;
-    struct cvmx_mio_boot_int_s           cn56xx;
-    struct cvmx_mio_boot_int_s           cn56xxp1;
-    struct cvmx_mio_boot_int_s           cn58xx;
-    struct cvmx_mio_boot_int_s           cn58xxp1;
-} cvmx_mio_boot_int_t;
-
-
-/**
- * cvmx_mio_boot_loc_adr
- *
- * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Address Register
- * 
- * Specifies the address for reading or writing the local memory.  This address will post-increment
- * following an access to the MIO Boot Local Memory Data Register (MIO_BOOT_LOC_DAT).
- * 
- * Local memory region 0 exists from addresses 0x00 - 0x78.
- * Local memory region 1 exists from addresses 0x80 - 0xf8.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_loc_adr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t adr                     : 5;       /**< Local memory address */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t adr                     : 5;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_boot_loc_adr_s       cn30xx;
-    struct cvmx_mio_boot_loc_adr_s       cn31xx;
-    struct cvmx_mio_boot_loc_adr_s       cn38xx;
-    struct cvmx_mio_boot_loc_adr_s       cn38xxp2;
-    struct cvmx_mio_boot_loc_adr_s       cn50xx;
-    struct cvmx_mio_boot_loc_adr_s       cn52xx;
-    struct cvmx_mio_boot_loc_adr_s       cn52xxp1;
-    struct cvmx_mio_boot_loc_adr_s       cn56xx;
-    struct cvmx_mio_boot_loc_adr_s       cn56xxp1;
-    struct cvmx_mio_boot_loc_adr_s       cn58xx;
-    struct cvmx_mio_boot_loc_adr_s       cn58xxp1;
-} cvmx_mio_boot_loc_adr_t;
-
-
-/**
- * cvmx_mio_boot_loc_cfg#
- *
- * MIO_BOOT_LOC_CFG = MIO Boot Local Region Config Register (1 per region * 2 regions)
- * 
- * Contains local region enable and local region base address parameters.  Each local region is 128
- * bytes organized as 16 entries x 8 bytes.
- * 
- * Base address specifies address bits [31:7] of the region.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_loc_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t en                      : 1;       /**< Local region X enable */
-        uint64_t reserved_28_30          : 3;
-        uint64_t base                    : 25;      /**< Local region X base address */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t base                    : 25;
-        uint64_t reserved_28_30          : 3;
-        uint64_t en                      : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_mio_boot_loc_cfgx_s      cn30xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn31xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn38xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn38xxp2;
-    struct cvmx_mio_boot_loc_cfgx_s      cn50xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn52xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn52xxp1;
-    struct cvmx_mio_boot_loc_cfgx_s      cn56xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn56xxp1;
-    struct cvmx_mio_boot_loc_cfgx_s      cn58xx;
-    struct cvmx_mio_boot_loc_cfgx_s      cn58xxp1;
-} cvmx_mio_boot_loc_cfgx_t;
-
-
-/**
- * cvmx_mio_boot_loc_dat
- *
- * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Data Register
- * 
- * This is a pseudo-register that will read/write the local memory at the address specified by the MIO
- * Boot Local Address Register (MIO_BOOT_LOC_ADR) when accessed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_loc_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Local memory data */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_mio_boot_loc_dat_s       cn30xx;
-    struct cvmx_mio_boot_loc_dat_s       cn31xx;
-    struct cvmx_mio_boot_loc_dat_s       cn38xx;
-    struct cvmx_mio_boot_loc_dat_s       cn38xxp2;
-    struct cvmx_mio_boot_loc_dat_s       cn50xx;
-    struct cvmx_mio_boot_loc_dat_s       cn52xx;
-    struct cvmx_mio_boot_loc_dat_s       cn52xxp1;
-    struct cvmx_mio_boot_loc_dat_s       cn56xx;
-    struct cvmx_mio_boot_loc_dat_s       cn56xxp1;
-    struct cvmx_mio_boot_loc_dat_s       cn58xx;
-    struct cvmx_mio_boot_loc_dat_s       cn58xxp1;
-} cvmx_mio_boot_loc_dat_t;
-
-
-/**
- * cvmx_mio_boot_pin_defs
- *
- * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_pin_defs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
-        uint64_t width                   : 1;       /**< Region 0 default bus width */
-        uint64_t dmack_p2                : 1;       /**< boot_dmack[2] default polarity */
-        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
-        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
-        uint64_t term                    : 2;       /**< Selects default driver termination */
-        uint64_t nand                    : 1;       /**< Region 0 is NAND flash */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t nand                    : 1;
-        uint64_t term                    : 2;
-        uint64_t dmack_p0                : 1;
-        uint64_t dmack_p1                : 1;
-        uint64_t dmack_p2                : 1;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_mio_boot_pin_defs_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
-        uint64_t width                   : 1;       /**< Region 0 default bus width */
-        uint64_t reserved_13_13          : 1;
-        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
-        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
-        uint64_t term                    : 2;       /**< Selects default driver termination */
-        uint64_t nand                    : 1;       /**< Region 0 is NAND flash */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t nand                    : 1;
-        uint64_t term                    : 2;
-        uint64_t dmack_p0                : 1;
-        uint64_t dmack_p1                : 1;
-        uint64_t reserved_13_13          : 1;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn52xx;
-    struct cvmx_mio_boot_pin_defs_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
-        uint64_t width                   : 1;       /**< Region 0 default bus width */
-        uint64_t dmack_p2                : 1;       /**< boot_dmack[2] default polarity */
-        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
-        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
-        uint64_t term                    : 2;       /**< Selects default driver termination */
-        uint64_t reserved_0_8            : 9;
-#else
-        uint64_t reserved_0_8            : 9;
-        uint64_t term                    : 2;
-        uint64_t dmack_p0                : 1;
-        uint64_t dmack_p1                : 1;
-        uint64_t dmack_p2                : 1;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn56xx;
-} cvmx_mio_boot_pin_defs_t;
-
-
-/**
- * cvmx_mio_boot_reg_cfg#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_reg_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t dmack                   : 2;       /**< Region X DMACK */
-        uint64_t tim_mult                : 2;       /**< Region X timing multiplier */
-        uint64_t rd_dly                  : 3;       /**< Region X read sample delay */
-        uint64_t sam                     : 1;       /**< Region X SAM mode */
-        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
-        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
-        uint64_t en                      : 1;       /**< Region X enable */
-        uint64_t orbit                   : 1;       /**< Region X or bit */
-        uint64_t ale                     : 1;       /**< Region X ALE mode */
-        uint64_t width                   : 1;       /**< Region X bus width */
-        uint64_t size                    : 12;      /**< Region X size */
-        uint64_t base                    : 16;      /**< Region X base address */
-#else
-        uint64_t base                    : 16;
-        uint64_t size                    : 12;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t orbit                   : 1;
-        uint64_t en                      : 1;
-        uint64_t oe_ext                  : 2;
-        uint64_t we_ext                  : 2;
-        uint64_t sam                     : 1;
-        uint64_t rd_dly                  : 3;
-        uint64_t tim_mult                : 2;
-        uint64_t dmack                   : 2;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_mio_boot_reg_cfgx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t sam                     : 1;       /**< Region X SAM mode */
-        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
-        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
-        uint64_t en                      : 1;       /**< Region X enable */
-        uint64_t orbit                   : 1;       /**< Region X or bit */
-        uint64_t ale                     : 1;       /**< Region X ALE mode */
-        uint64_t width                   : 1;       /**< Region X bus width */
-        uint64_t size                    : 12;      /**< Region X size */
-        uint64_t base                    : 16;      /**< Region X base address */
-#else
-        uint64_t base                    : 16;
-        uint64_t size                    : 12;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t orbit                   : 1;
-        uint64_t en                      : 1;
-        uint64_t oe_ext                  : 2;
-        uint64_t we_ext                  : 2;
-        uint64_t sam                     : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } cn30xx;
-    struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
-    struct cvmx_mio_boot_reg_cfgx_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t en                      : 1;       /**< Region X enable */
-        uint64_t orbit                   : 1;       /**< Region X or bit */
-        uint64_t reserved_28_29          : 2;
-        uint64_t size                    : 12;      /**< Region X size */
-        uint64_t base                    : 16;      /**< Region X base address */
-#else
-        uint64_t base                    : 16;
-        uint64_t size                    : 12;
-        uint64_t reserved_28_29          : 2;
-        uint64_t orbit                   : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
-    struct cvmx_mio_boot_reg_cfgx_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_42_63          : 22;
-        uint64_t tim_mult                : 2;       /**< Region X timing multiplier */
-        uint64_t rd_dly                  : 3;       /**< Region X read sample delay */
-        uint64_t sam                     : 1;       /**< Region X SAM mode */
-        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
-        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
-        uint64_t en                      : 1;       /**< Region X enable */
-        uint64_t orbit                   : 1;       /**< Region X or bit */
-        uint64_t ale                     : 1;       /**< Region X ALE mode */
-        uint64_t width                   : 1;       /**< Region X bus width */
-        uint64_t size                    : 12;      /**< Region X size */
-        uint64_t base                    : 16;      /**< Region X base address */
-#else
-        uint64_t base                    : 16;
-        uint64_t size                    : 12;
-        uint64_t width                   : 1;
-        uint64_t ale                     : 1;
-        uint64_t orbit                   : 1;
-        uint64_t en                      : 1;
-        uint64_t oe_ext                  : 2;
-        uint64_t we_ext                  : 2;
-        uint64_t sam                     : 1;
-        uint64_t rd_dly                  : 3;
-        uint64_t tim_mult                : 2;
-        uint64_t reserved_42_63          : 22;
-#endif
-    } cn50xx;
-    struct cvmx_mio_boot_reg_cfgx_s      cn52xx;
-    struct cvmx_mio_boot_reg_cfgx_s      cn52xxp1;
-    struct cvmx_mio_boot_reg_cfgx_s      cn56xx;
-    struct cvmx_mio_boot_reg_cfgx_s      cn56xxp1;
-    struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
-    struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
-} cvmx_mio_boot_reg_cfgx_t;
-
-
-/**
- * cvmx_mio_boot_reg_tim#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_reg_timx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pagem                   : 1;       /**< Region X page mode */
-        uint64_t waitm                   : 1;       /**< Region X wait mode */
-        uint64_t pages                   : 2;       /**< Region X page size */
-        uint64_t ale                     : 6;       /**< Region X ALE count */
-        uint64_t page                    : 6;       /**< Region X page count */
-        uint64_t wait                    : 6;       /**< Region X wait count */
-        uint64_t pause                   : 6;       /**< Region X pause count */
-        uint64_t wr_hld                  : 6;       /**< Region X write hold count */
-        uint64_t rd_hld                  : 6;       /**< Region X read hold count */
-        uint64_t we                      : 6;       /**< Region X write enable count */
-        uint64_t oe                      : 6;       /**< Region X output enable count */
-        uint64_t ce                      : 6;       /**< Region X chip enable count */
-        uint64_t adr                     : 6;       /**< Region X address count */
-#else
-        uint64_t adr                     : 6;
-        uint64_t ce                      : 6;
-        uint64_t oe                      : 6;
-        uint64_t we                      : 6;
-        uint64_t rd_hld                  : 6;
-        uint64_t wr_hld                  : 6;
-        uint64_t pause                   : 6;
-        uint64_t wait                    : 6;
-        uint64_t page                    : 6;
-        uint64_t ale                     : 6;
-        uint64_t pages                   : 2;
-        uint64_t waitm                   : 1;
-        uint64_t pagem                   : 1;
-#endif
-    } s;
-    struct cvmx_mio_boot_reg_timx_s      cn30xx;
-    struct cvmx_mio_boot_reg_timx_s      cn31xx;
-    struct cvmx_mio_boot_reg_timx_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pagem                   : 1;       /**< Region X page mode */
-        uint64_t waitm                   : 1;       /**< Region X wait mode */
-        uint64_t pages                   : 2;       /**< Region X page size (NOT IN PASS 1) */
-        uint64_t reserved_54_59          : 6;
-        uint64_t page                    : 6;       /**< Region X page count */
-        uint64_t wait                    : 6;       /**< Region X wait count */
-        uint64_t pause                   : 6;       /**< Region X pause count */
-        uint64_t wr_hld                  : 6;       /**< Region X write hold count */
-        uint64_t rd_hld                  : 6;       /**< Region X read hold count */
-        uint64_t we                      : 6;       /**< Region X write enable count */
-        uint64_t oe                      : 6;       /**< Region X output enable count */
-        uint64_t ce                      : 6;       /**< Region X chip enable count */
-        uint64_t adr                     : 6;       /**< Region X address count */
-#else
-        uint64_t adr                     : 6;
-        uint64_t ce                      : 6;
-        uint64_t oe                      : 6;
-        uint64_t we                      : 6;
-        uint64_t rd_hld                  : 6;
-        uint64_t wr_hld                  : 6;
-        uint64_t pause                   : 6;
-        uint64_t wait                    : 6;
-        uint64_t page                    : 6;
-        uint64_t reserved_54_59          : 6;
-        uint64_t pages                   : 2;
-        uint64_t waitm                   : 1;
-        uint64_t pagem                   : 1;
-#endif
-    } cn38xx;
-    struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
-    struct cvmx_mio_boot_reg_timx_s      cn50xx;
-    struct cvmx_mio_boot_reg_timx_s      cn52xx;
-    struct cvmx_mio_boot_reg_timx_s      cn52xxp1;
-    struct cvmx_mio_boot_reg_timx_s      cn56xx;
-    struct cvmx_mio_boot_reg_timx_s      cn56xxp1;
-    struct cvmx_mio_boot_reg_timx_s      cn58xx;
-    struct cvmx_mio_boot_reg_timx_s      cn58xxp1;
-} cvmx_mio_boot_reg_timx_t;
-
-
-/**
- * cvmx_mio_boot_thr
- *
- * MIO_BOOT_THR = MIO Boot Threshold Register
- * 
- * Contains MIO Boot threshold values:
- * 
- * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for
- *           customer use).
- * 
- * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA
- *           accesses have completed.  If set to zero, only perform a DMA access when non-DMA
- *           accesses are not pending.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_boot_thr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_22_63          : 42;
-        uint64_t dma_thr                 : 6;       /**< DMA threshold */
-        uint64_t reserved_14_15          : 2;
-        uint64_t fif_cnt                 : 6;       /**< Current NCB FIFO count */
-        uint64_t reserved_6_7            : 2;
-        uint64_t fif_thr                 : 6;       /**< NCB busy threshold */
-#else
-        uint64_t fif_thr                 : 6;
-        uint64_t reserved_6_7            : 2;
-        uint64_t fif_cnt                 : 6;
-        uint64_t reserved_14_15          : 2;
-        uint64_t dma_thr                 : 6;
-        uint64_t reserved_22_63          : 42;
-#endif
-    } s;
-    struct cvmx_mio_boot_thr_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t fif_cnt                 : 6;       /**< Current NCB FIFO count */
-        uint64_t reserved_6_7            : 2;
-        uint64_t fif_thr                 : 6;       /**< NCB busy threshold */
-#else
-        uint64_t fif_thr                 : 6;
-        uint64_t reserved_6_7            : 2;
-        uint64_t fif_cnt                 : 6;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn30xx;
-    struct cvmx_mio_boot_thr_cn30xx      cn31xx;
-    struct cvmx_mio_boot_thr_cn30xx      cn38xx;
-    struct cvmx_mio_boot_thr_cn30xx      cn38xxp2;
-    struct cvmx_mio_boot_thr_cn30xx      cn50xx;
-    struct cvmx_mio_boot_thr_s           cn52xx;
-    struct cvmx_mio_boot_thr_s           cn52xxp1;
-    struct cvmx_mio_boot_thr_s           cn56xx;
-    struct cvmx_mio_boot_thr_s           cn56xxp1;
-    struct cvmx_mio_boot_thr_cn30xx      cn58xx;
-    struct cvmx_mio_boot_thr_cn30xx      cn58xxp1;
-} cvmx_mio_boot_thr_t;
-
-
-/**
- * cvmx_mio_fus_bnk_dat#
- *
- * Notes:
- * The intial state of MIO_FUS_BNK_DAT* is as if bank1 was just read i.e. DAT* = fus[511:256]
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_bnk_datx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dat                     : 64;      /**< Efuse bank store
-                                                         For reads, the DAT gets the fus bank last read
-                                                         For write, the DAT determines which fuses to blow */
-#else
-        uint64_t dat                     : 64;
-#endif
-    } s;
-    struct cvmx_mio_fus_bnk_datx_s       cn50xx;
-    struct cvmx_mio_fus_bnk_datx_s       cn52xx;
-    struct cvmx_mio_fus_bnk_datx_s       cn52xxp1;
-    struct cvmx_mio_fus_bnk_datx_s       cn56xx;
-    struct cvmx_mio_fus_bnk_datx_s       cn56xxp1;
-    struct cvmx_mio_fus_bnk_datx_s       cn58xx;
-    struct cvmx_mio_fus_bnk_datx_s       cn58xxp1;
-} cvmx_mio_fus_bnk_datx_t;
-
-
-/**
- * cvmx_mio_fus_dat0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_dat0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t man_info                : 32;      /**< Fuse information - manufacturing info [31:0] */
-#else
-        uint64_t man_info                : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_mio_fus_dat0_s           cn30xx;
-    struct cvmx_mio_fus_dat0_s           cn31xx;
-    struct cvmx_mio_fus_dat0_s           cn38xx;
-    struct cvmx_mio_fus_dat0_s           cn38xxp2;
-    struct cvmx_mio_fus_dat0_s           cn50xx;
-    struct cvmx_mio_fus_dat0_s           cn52xx;
-    struct cvmx_mio_fus_dat0_s           cn52xxp1;
-    struct cvmx_mio_fus_dat0_s           cn56xx;
-    struct cvmx_mio_fus_dat0_s           cn56xxp1;
-    struct cvmx_mio_fus_dat0_s           cn58xx;
-    struct cvmx_mio_fus_dat0_s           cn58xxp1;
-} cvmx_mio_fus_dat0_t;
-
-
-/**
- * cvmx_mio_fus_dat1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_dat1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t man_info                : 32;      /**< Fuse information - manufacturing info [63:32] */
-#else
-        uint64_t man_info                : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_mio_fus_dat1_s           cn30xx;
-    struct cvmx_mio_fus_dat1_s           cn31xx;
-    struct cvmx_mio_fus_dat1_s           cn38xx;
-    struct cvmx_mio_fus_dat1_s           cn38xxp2;
-    struct cvmx_mio_fus_dat1_s           cn50xx;
-    struct cvmx_mio_fus_dat1_s           cn52xx;
-    struct cvmx_mio_fus_dat1_s           cn52xxp1;
-    struct cvmx_mio_fus_dat1_s           cn56xx;
-    struct cvmx_mio_fus_dat1_s           cn56xxp1;
-    struct cvmx_mio_fus_dat1_s           cn58xx;
-    struct cvmx_mio_fus_dat1_s           cn58xxp1;
-} cvmx_mio_fus_dat1_t;
-
-
-/**
- * cvmx_mio_fus_dat2
- *
- * Notes:
- * CHIP_ID is consumed in several places within Octeon.
- * 
- *    * Core COP0 ProcessorIdentification[Revision]
- *    * Core EJTAG DeviceIdentification[Version]
- *    * PCI_CFG02[RID]
- *    * JTAG controller
- * 
- * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses.
- * Modification to the efuses will not change what the JTAG controller reports
- * for CHIP_ID.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_dat2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
-        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
-        uint64_t reserved_30_31          : 2;
-        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t reserved_0_15           : 16;
-#else
-        uint64_t reserved_0_15           : 16;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t nokasu                  : 1;
-        uint64_t reserved_30_31          : 2;
-        uint64_t raid_en                 : 1;
-        uint64_t fus318                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_mio_fus_dat2_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t pll_off                 : 4;       /**< Fuse information - core pll offset
-                                                         Used to compute the base offset for the core pll.
-                                                         the offset will be (PLL_OFF ^ 8)
-                                                         Note, these fuses can only be set from laser fuse */
-        uint64_t reserved_1_11           : 11;
-        uint64_t pp_dis                  : 1;       /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 1;
-        uint64_t reserved_1_11           : 11;
-        uint64_t pll_off                 : 4;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn30xx;
-    struct cvmx_mio_fus_dat2_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t pll_off                 : 4;       /**< Fuse information - core pll offset
-                                                         Used to compute the base offset for the core pll.
-                                                         the offset will be (PLL_OFF ^ 8)
-                                                         Note, these fuses can only be set from laser fuse */
-        uint64_t reserved_2_11           : 10;
-        uint64_t pp_dis                  : 2;       /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 2;
-        uint64_t reserved_2_11           : 10;
-        uint64_t pll_off                 : 4;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn31xx;
-    struct cvmx_mio_fus_dat2_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2)
-                                                         (PASS2 Only) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable
-                                                         (PASS2 Only) */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable
-                                                         (PASS2 Only) */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t pp_dis                  : 16;      /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 16;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn38xx;
-    struct cvmx_mio_fus_dat2_cn38xx      cn38xxp2;
-    struct cvmx_mio_fus_dat2_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
-        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled
-                                                         (5020 does not have RAID co-processor) */
-        uint64_t reserved_30_31          : 2;
-        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2)
-                                                         (5020 does not have DFA co-processor) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t reserved_2_15           : 14;
-        uint64_t pp_dis                  : 2;       /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 2;
-        uint64_t reserved_2_15           : 14;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t nokasu                  : 1;
-        uint64_t reserved_30_31          : 2;
-        uint64_t raid_en                 : 1;
-        uint64_t fus318                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn50xx;
-    struct cvmx_mio_fus_dat2_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
-        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
-        uint64_t reserved_30_31          : 2;
-        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t reserved_4_15           : 12;
-        uint64_t pp_dis                  : 4;       /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 4;
-        uint64_t reserved_4_15           : 12;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t nokasu                  : 1;
-        uint64_t reserved_30_31          : 2;
-        uint64_t raid_en                 : 1;
-        uint64_t fus318                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn52xx;
-    struct cvmx_mio_fus_dat2_cn52xx      cn52xxp1;
-    struct cvmx_mio_fus_dat2_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
-        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
-        uint64_t reserved_30_31          : 2;
-        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t reserved_12_15          : 4;
-        uint64_t pp_dis                  : 12;      /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 12;
-        uint64_t reserved_12_15          : 4;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t nokasu                  : 1;
-        uint64_t reserved_30_31          : 2;
-        uint64_t raid_en                 : 1;
-        uint64_t fus318                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn56xx;
-    struct cvmx_mio_fus_dat2_cn56xx      cn56xxp1;
-    struct cvmx_mio_fus_dat2_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_30_63          : 34;
-        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
-        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
-        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
-        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
-        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
-        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
-        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
-        uint64_t pp_dis                  : 16;      /**< Fuse information - PP_DISABLES */
-#else
-        uint64_t pp_dis                  : 16;
-        uint64_t chip_id                 : 8;
-        uint64_t bist_dis                : 1;
-        uint64_t rst_sht                 : 1;
-        uint64_t nocrypto                : 1;
-        uint64_t nomul                   : 1;
-        uint64_t nodfa_cp2               : 1;
-        uint64_t nokasu                  : 1;
-        uint64_t reserved_30_63          : 34;
-#endif
-    } cn58xx;
-    struct cvmx_mio_fus_dat2_cn58xx      cn58xxp1;
-} cvmx_mio_fus_dat2_t;
-
-
-/**
- * cvmx_mio_fus_dat3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_dat3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pll_div4                : 1;       /**< Fuse information - PLL DIV4 mode
-                                                         (laser fuse only) */
-        uint64_t zip_crip                : 2;       /**< Fuse information - Zip Cripple */
-        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1') */
-        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown */
-        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
-                                                         This bit only has side effects when blown in
-                                                         the laser fuses.  It is ignore if only set in
-                                                         efuse store. */
-        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable */
-        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE) */
-        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
-#else
-        uint64_t icache                  : 24;
-        uint64_t nodfa_dte               : 1;
-        uint64_t nozip                   : 1;
-        uint64_t efus_ign                : 1;
-        uint64_t efus_lck                : 1;
-        uint64_t bar2_en                 : 1;
-        uint64_t zip_crip                : 2;
-        uint64_t pll_div4                : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_mio_fus_dat3_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pll_div4                : 1;       /**< Fuse information - PLL DIV4 mode
-                                                         (laser fuse only) */
-        uint64_t reserved_29_30          : 2;
-        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1') */
-        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown */
-        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
-                                                         This bit only has side effects when blown in
-                                                         the laser fuses.  It is ignore if only set in
-                                                         efuse store. */
-        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable */
-        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE) */
-        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
-#else
-        uint64_t icache                  : 24;
-        uint64_t nodfa_dte               : 1;
-        uint64_t nozip                   : 1;
-        uint64_t efus_ign                : 1;
-        uint64_t efus_lck                : 1;
-        uint64_t bar2_en                 : 1;
-        uint64_t reserved_29_30          : 2;
-        uint64_t pll_div4                : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_mio_fus_dat3_s           cn31xx;
-    struct cvmx_mio_fus_dat3_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t zip_crip                : 2;       /**< Fuse information - Zip Cripple
-                                                         (PASS3 Only) */
-        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1')
-                                                         (PASS2 Only) */
-        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown
-                                                         (PASS2 Only) */
-        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
-                                                         This bit only has side effects when blown in
-                                                         the laser fuses.  It is ignore if only set in
-                                                         efuse store.
-                                                         (PASS2 Only) */
-        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable
-                                                         (PASS2 Only) */
-        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE)
-                                                         (PASS2 Only) */
-        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
-#else
-        uint64_t icache                  : 24;
-        uint64_t nodfa_dte               : 1;
-        uint64_t nozip                   : 1;
-        uint64_t efus_ign                : 1;
-        uint64_t efus_lck                : 1;
-        uint64_t bar2_en                 : 1;
-        uint64_t zip_crip                : 2;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn38xx;
-    struct cvmx_mio_fus_dat3_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1')
-                                                         (PASS2 Only) */
-        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown
-                                                         (PASS2 Only) */
-        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
-                                                         This bit only has side effects when blown in
-                                                         the laser fuses.  It is ignore if only set in
-                                                         efuse store.
-                                                         (PASS2 Only) */
-        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable
-                                                         (PASS2 Only) */
-        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE)
-                                                         (PASS2 Only) */
-        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
-#else
-        uint64_t icache                  : 24;
-        uint64_t nodfa_dte               : 1;
-        uint64_t nozip                   : 1;
-        uint64_t efus_ign                : 1;
-        uint64_t efus_lck                : 1;
-        uint64_t bar2_en                 : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn38xxp2;
-    struct cvmx_mio_fus_dat3_cn38xx      cn50xx;
-    struct cvmx_mio_fus_dat3_cn38xx      cn52xx;
-    struct cvmx_mio_fus_dat3_cn38xx      cn52xxp1;
-    struct cvmx_mio_fus_dat3_cn38xx      cn56xx;
-    struct cvmx_mio_fus_dat3_cn38xx      cn56xxp1;
-    struct cvmx_mio_fus_dat3_cn38xx      cn58xx;
-    struct cvmx_mio_fus_dat3_cn38xx      cn58xxp1;
-} cvmx_mio_fus_dat3_t;
-
-
-/**
- * cvmx_mio_fus_ema
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_ema_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t eff_ema                 : 3;       /**< Effective EMA value */
-        uint64_t reserved_3_3            : 1;
-        uint64_t ema                     : 3;       /**< EMA Settings */
-#else
-        uint64_t ema                     : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t eff_ema                 : 3;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mio_fus_ema_s            cn50xx;
-    struct cvmx_mio_fus_ema_s            cn52xx;
-    struct cvmx_mio_fus_ema_s            cn52xxp1;
-    struct cvmx_mio_fus_ema_s            cn56xx;
-    struct cvmx_mio_fus_ema_s            cn56xxp1;
-    struct cvmx_mio_fus_ema_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t ema                     : 2;       /**< EMA Settings */
-#else
-        uint64_t ema                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn58xx;
-    struct cvmx_mio_fus_ema_cn58xx       cn58xxp1;
-} cvmx_mio_fus_ema_t;
-
-
-/**
- * cvmx_mio_fus_pdf
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_pdf_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pdf                     : 64;      /**< Fuse information - Product Definition Field */
-#else
-        uint64_t pdf                     : 64;
-#endif
-    } s;
-    struct cvmx_mio_fus_pdf_s            cn50xx;
-    struct cvmx_mio_fus_pdf_s            cn52xx;
-    struct cvmx_mio_fus_pdf_s            cn52xxp1;
-    struct cvmx_mio_fus_pdf_s            cn56xx;
-    struct cvmx_mio_fus_pdf_s            cn56xxp1;
-    struct cvmx_mio_fus_pdf_s            cn58xx;
-} cvmx_mio_fus_pdf_t;
-
-
-/**
- * cvmx_mio_fus_pll
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_pll_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t rfslip                  : 1;       /**< PLL reference clock slip */
-        uint64_t fbslip                  : 1;       /**< PLL feedback clock slip */
-#else
-        uint64_t fbslip                  : 1;
-        uint64_t rfslip                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_fus_pll_s            cn50xx;
-    struct cvmx_mio_fus_pll_s            cn52xx;
-    struct cvmx_mio_fus_pll_s            cn52xxp1;
-    struct cvmx_mio_fus_pll_s            cn56xx;
-    struct cvmx_mio_fus_pll_s            cn56xxp1;
-    struct cvmx_mio_fus_pll_s            cn58xx;
-    struct cvmx_mio_fus_pll_s            cn58xxp1;
-} cvmx_mio_fus_pll_t;
-
-
-/**
- * cvmx_mio_fus_prog
- *
- * Notes:
- * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be
- * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which
- * fuses to blow.  Once ADDR, and DAT are setup, SW can write to
- * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG.  Once PROG is
- * clear, the bank write is complete.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_prog_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t prog                    : 1;       /**< Blow the fuse bank
-                                                         SW will set PROG, and then the HW will clear
-                                                         when the PROG bank is complete */
-#else
-        uint64_t prog                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_fus_prog_s           cn30xx;
-    struct cvmx_mio_fus_prog_s           cn31xx;
-    struct cvmx_mio_fus_prog_s           cn38xx;
-    struct cvmx_mio_fus_prog_s           cn38xxp2;
-    struct cvmx_mio_fus_prog_s           cn50xx;
-    struct cvmx_mio_fus_prog_s           cn52xx;
-    struct cvmx_mio_fus_prog_s           cn52xxp1;
-    struct cvmx_mio_fus_prog_s           cn56xx;
-    struct cvmx_mio_fus_prog_s           cn56xxp1;
-    struct cvmx_mio_fus_prog_s           cn58xx;
-    struct cvmx_mio_fus_prog_s           cn58xxp1;
-} cvmx_mio_fus_prog_t;
-
-
-/**
- * cvmx_mio_fus_prog_times
- *
- * Notes:
- * All values must be > 0 for correct electrical operation.
- * 
- * The reset values are a conservative version for a 50MHz ref_clk.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_prog_times_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_33_63          : 31;
-        uint64_t prog_pin                : 1;       /**< efuse program pin */
-        uint64_t out                     : 8;       /**< efuse timing param (ref_clks to delay 10ns) */
-        uint64_t sclk_lo                 : 4;       /**< efuse timing param (ref_clks to delay 5ns) */
-        uint64_t sclk_hi                 : 12;      /**< efuse timing param (ref_clks to delay 1000ns) */
-        uint64_t setup                   : 8;       /**< efuse timing param (ref_clks to delay 10ns) */
-#else
-        uint64_t setup                   : 8;
-        uint64_t sclk_hi                 : 12;
-        uint64_t sclk_lo                 : 4;
-        uint64_t out                     : 8;
-        uint64_t prog_pin                : 1;
-        uint64_t reserved_33_63          : 31;
-#endif
-    } s;
-    struct cvmx_mio_fus_prog_times_s     cn50xx;
-    struct cvmx_mio_fus_prog_times_s     cn52xx;
-    struct cvmx_mio_fus_prog_times_s     cn52xxp1;
-    struct cvmx_mio_fus_prog_times_s     cn56xx;
-    struct cvmx_mio_fus_prog_times_s     cn56xxp1;
-    struct cvmx_mio_fus_prog_times_s     cn58xx;
-    struct cvmx_mio_fus_prog_times_s     cn58xxp1;
-} cvmx_mio_fus_prog_times_t;
-
-
-/**
- * cvmx_mio_fus_rcmd
- *
- * Notes:
- * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of
- * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND].  When PEND is
- * clear, then MIO_FUS_RCMD[DAT] is valid.  In addition, if the efuse read went
- * to the efuse banks (e.g. ADDR > (320/8) || EFUSE is set) SW can read
- * MIO_FUS_BNK_DATX which contains all 256 fuses in the bank associated in
- * ADDR.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_rcmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t dat                     : 8;       /**< 8bits of fuse data */
-        uint64_t reserved_13_15          : 3;
-        uint64_t pend                    : 1;       /**< SW sets this bit on a write to start FUSE read
-                                                         operation.  HW clears when read is complete and
-                                                         the DAT is valid */
-        uint64_t reserved_9_11           : 3;
-        uint64_t efuse                   : 1;       /**< When set, return data from the efuse storage
-                                                         rather than the local storage for the 320 HW fuses */
-        uint64_t addr                    : 8;       /**< The byte address of the fuse to read */
-#else
-        uint64_t addr                    : 8;
-        uint64_t efuse                   : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t pend                    : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t dat                     : 8;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_mio_fus_rcmd_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t dat                     : 8;       /**< 8bits of fuse data */
-        uint64_t reserved_13_15          : 3;
-        uint64_t pend                    : 1;       /**< SW sets this bit on a write to start FUSE read
-                                                         operation.  HW clears when read is complete and
-                                                         the DAT is valid */
-        uint64_t reserved_9_11           : 3;
-        uint64_t efuse                   : 1;       /**< When set, return data from the efuse storage
-                                                         rather than the local storage for the 320 HW fuses */
-        uint64_t reserved_7_7            : 1;
-        uint64_t addr                    : 7;       /**< The byte address of the fuse to read */
-#else
-        uint64_t addr                    : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t efuse                   : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t pend                    : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t dat                     : 8;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } cn30xx;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn31xx;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn38xx;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn38xxp2;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn50xx;
-    struct cvmx_mio_fus_rcmd_s           cn52xx;
-    struct cvmx_mio_fus_rcmd_s           cn52xxp1;
-    struct cvmx_mio_fus_rcmd_s           cn56xx;
-    struct cvmx_mio_fus_rcmd_s           cn56xxp1;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn58xx;
-    struct cvmx_mio_fus_rcmd_cn30xx      cn58xxp1;
-} cvmx_mio_fus_rcmd_t;
-
-
-/**
- * cvmx_mio_fus_spr_repair_res
- *
- * Notes:
- * Pass3 Only
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_spr_repair_res_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_42_63          : 22;
-        uint64_t repair2                 : 14;      /**< SPR BISR Results */
-        uint64_t repair1                 : 14;      /**< SPR BISR Results */
-        uint64_t repair0                 : 14;      /**< SPR BISR Results */
-#else
-        uint64_t repair0                 : 14;
-        uint64_t repair1                 : 14;
-        uint64_t repair2                 : 14;
-        uint64_t reserved_42_63          : 22;
-#endif
-    } s;
-    struct cvmx_mio_fus_spr_repair_res_s cn30xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn31xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn38xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn50xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn52xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
-    struct cvmx_mio_fus_spr_repair_res_s cn56xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
-    struct cvmx_mio_fus_spr_repair_res_s cn58xx;
-    struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
-} cvmx_mio_fus_spr_repair_res_t;
-
-
-/**
- * cvmx_mio_fus_spr_repair_sum
- *
- * Notes:
- * Pass3 Only
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_spr_repair_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t too_many                : 1;       /**< Too Many Defects - cannot repair - bad part */
-#else
-        uint64_t too_many                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
-    struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
-    struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
-    struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
-} cvmx_mio_fus_spr_repair_sum_t;
-
-
-/**
- * cvmx_mio_fus_unlock
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_unlock_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t key                     : 24;      /**< When set to the typical value, allows SW to
-                                                         program the efuses */
-#else
-        uint64_t key                     : 24;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_mio_fus_unlock_s         cn30xx;
-    struct cvmx_mio_fus_unlock_s         cn31xx;
-} cvmx_mio_fus_unlock_t;
-
-
-/**
- * cvmx_mio_fus_wadr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_fus_wadr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t addr                    : 10;      /**< Which of the four banks of 256 fuses to blow */
-#else
-        uint64_t addr                    : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_mio_fus_wadr_s           cn30xx;
-    struct cvmx_mio_fus_wadr_s           cn31xx;
-    struct cvmx_mio_fus_wadr_s           cn38xx;
-    struct cvmx_mio_fus_wadr_s           cn38xxp2;
-    struct cvmx_mio_fus_wadr_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t addr                    : 2;       /**< Which of the four banks of 256 fuses to blow */
-#else
-        uint64_t addr                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn50xx;
-    struct cvmx_mio_fus_wadr_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t addr                    : 3;       /**< Which of the four banks of 256 fuses to blow */
-#else
-        uint64_t addr                    : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn52xx;
-    struct cvmx_mio_fus_wadr_cn52xx      cn52xxp1;
-    struct cvmx_mio_fus_wadr_cn52xx      cn56xx;
-    struct cvmx_mio_fus_wadr_cn52xx      cn56xxp1;
-    struct cvmx_mio_fus_wadr_cn50xx      cn58xx;
-    struct cvmx_mio_fus_wadr_cn50xx      cn58xxp1;
-} cvmx_mio_fus_wadr_t;
-
-
-/**
- * cvmx_mio_ndf_dma_cfg
- *
- * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register
- * 
- * SIZE is specified in number of 64 bit transfers (encoded in -1 notation).
- * 
- * ADR must be 64 bit aligned.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_ndf_dma_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t en                      : 1;       /**< DMA Engine enable */
-        uint64_t rw                      : 1;       /**< DMA Engine R/W bit (0 = read, 1 = write) */
-        uint64_t clr                     : 1;       /**< DMA Engine clear EN on device terminated burst */
-        uint64_t reserved_60_60          : 1;
-        uint64_t swap32                  : 1;       /**< DMA Engine 32 bit swap */
-        uint64_t swap16                  : 1;       /**< DMA Engine 16 bit swap */
-        uint64_t swap8                   : 1;       /**< DMA Engine 8 bit swap */
-        uint64_t endian                  : 1;       /**< DMA Engine NCB endian mode (0 = big, 1 = little) */
-        uint64_t size                    : 20;      /**< DMA Engine size */
-        uint64_t adr                     : 36;      /**< DMA Engine address */
-#else
-        uint64_t adr                     : 36;
-        uint64_t size                    : 20;
-        uint64_t endian                  : 1;
-        uint64_t swap8                   : 1;
-        uint64_t swap16                  : 1;
-        uint64_t swap32                  : 1;
-        uint64_t reserved_60_60          : 1;
-        uint64_t clr                     : 1;
-        uint64_t rw                      : 1;
-        uint64_t en                      : 1;
-#endif
-    } s;
-    struct cvmx_mio_ndf_dma_cfg_s        cn52xx;
-} cvmx_mio_ndf_dma_cfg_t;
-
-
-/**
- * cvmx_mio_ndf_dma_int
- *
- * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_ndf_dma_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t done                    : 1;       /**< DMA Engine request completion interrupt */
-#else
-        uint64_t done                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_ndf_dma_int_s        cn52xx;
-} cvmx_mio_ndf_dma_int_t;
-
-
-/**
- * cvmx_mio_ndf_dma_int_en
- *
- * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_ndf_dma_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t done                    : 1;       /**< DMA Engine request completion interrupt enable */
-#else
-        uint64_t done                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_ndf_dma_int_en_s     cn52xx;
-} cvmx_mio_ndf_dma_int_en_t;
-
-
-/**
- * cvmx_mio_pll_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_pll_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t bw_ctl                  : 5;       /**< Core PLL bandwidth control */
-#else
-        uint64_t bw_ctl                  : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_mio_pll_ctl_s            cn30xx;
-    struct cvmx_mio_pll_ctl_s            cn31xx;
-} cvmx_mio_pll_ctl_t;
-
-
-/**
- * cvmx_mio_pll_setting
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_pll_setting_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t setting                 : 17;      /**< Core PLL setting */
-#else
-        uint64_t setting                 : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_mio_pll_setting_s        cn30xx;
-    struct cvmx_mio_pll_setting_s        cn31xx;
-} cvmx_mio_pll_setting_t;
-
-
-/**
- * cvmx_mio_tws#_int
- *
- * MIO_TWSX_INT = TWSX Interrupt Register
- * 
- * This register contains the TWSI interrupt enable mask and the interrupt source bits.  Note: the
- * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence
- * must be written to the TWSI core to clear this interrupt.  The other interrupt source bits are write-
- * one-to-clear.  TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written
- * by a TWSI device).  ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above
- * for reasons).
- * 
- * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored.
- * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT /
- * TS_INT should be ignored.
- * 
- * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to
- * override the current state of the TWSI bus (SCL_OVR and SDA_OVR).  Setting an override bit high will
- * result in the open drain driver being activated, thus driving the corresponding signal low.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_twsx_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t scl                     : 1;       /**< SCL (NOT IN PASS1 OR PASS2) */
-        uint64_t sda                     : 1;       /**< SDA (NOT IN PASS1 OR PASS2) */
-        uint64_t scl_ovr                 : 1;       /**< SCL override (NOT IN PASS1 OR PASS2) */
-        uint64_t sda_ovr                 : 1;       /**< SDA override (NOT IN PASS1 OR PASS2) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t core_en                 : 1;       /**< TWSI core interrupt enable */
-        uint64_t ts_en                   : 1;       /**< MIO_TWS_TWSI_SW register update interrupt enable */
-        uint64_t st_en                   : 1;       /**< MIO_TWS_SW_TWSI register update interrupt enable */
-        uint64_t reserved_3_3            : 1;
-        uint64_t core_int                : 1;       /**< TWSI core interrupt */
-        uint64_t ts_int                  : 1;       /**< MIO_TWS_TWSI_SW register update interrupt */
-        uint64_t st_int                  : 1;       /**< MIO_TWS_SW_TWSI register update interrupt */
-#else
-        uint64_t st_int                  : 1;
-        uint64_t ts_int                  : 1;
-        uint64_t core_int                : 1;
-        uint64_t reserved_3_3            : 1;
-        uint64_t st_en                   : 1;
-        uint64_t ts_en                   : 1;
-        uint64_t core_en                 : 1;
-        uint64_t reserved_7_7            : 1;
-        uint64_t sda_ovr                 : 1;
-        uint64_t scl_ovr                 : 1;
-        uint64_t sda                     : 1;
-        uint64_t scl                     : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_mio_twsx_int_s           cn30xx;
-    struct cvmx_mio_twsx_int_s           cn31xx;
-    struct cvmx_mio_twsx_int_s           cn38xx;
-    struct cvmx_mio_twsx_int_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t core_en                 : 1;       /**< TWSI core interrupt enable */
-        uint64_t ts_en                   : 1;       /**< MIO_TWS_TWSI_SW register update interrupt enable */
-        uint64_t st_en                   : 1;       /**< MIO_TWS_SW_TWSI register update interrupt enable */
-        uint64_t reserved_3_3            : 1;
-        uint64_t core_int                : 1;       /**< TWSI core interrupt */
-        uint64_t ts_int                  : 1;       /**< MIO_TWS_TWSI_SW register update interrupt */
-        uint64_t st_int                  : 1;       /**< MIO_TWS_SW_TWSI register update interrupt */
-#else
-        uint64_t st_int                  : 1;
-        uint64_t ts_int                  : 1;
-        uint64_t core_int                : 1;
-        uint64_t reserved_3_3            : 1;
-        uint64_t st_en                   : 1;
-        uint64_t ts_en                   : 1;
-        uint64_t core_en                 : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } cn38xxp2;
-    struct cvmx_mio_twsx_int_s           cn50xx;
-    struct cvmx_mio_twsx_int_s           cn52xx;
-    struct cvmx_mio_twsx_int_s           cn52xxp1;
-    struct cvmx_mio_twsx_int_s           cn56xx;
-    struct cvmx_mio_twsx_int_s           cn56xxp1;
-    struct cvmx_mio_twsx_int_s           cn58xx;
-    struct cvmx_mio_twsx_int_s           cn58xxp1;
-} cvmx_mio_twsx_int_t;
-
-
-/**
- * cvmx_mio_tws#_sw_twsi
- *
- * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register
- * 
- * This register allows software to
- *    - initiate TWSI interface master-mode operations with a write and read the result with a read
- *    - load four bytes for later retrieval (slave mode) with a write and check validity with a read
- *    - launch a TWSI controller configuration read/write with a write and read the result with a read
- * 
- * This register should be read or written by software, and read by the TWSI device. The TWSI device can
- * use either two-byte or five-byte reads to reference this register.
- * 
- * The TWSI device considers this register valid when V==1 and SLONLY==1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_twsx_sw_twsi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t v                       : 1;       /**< Valid bit
-                                                         - Set on a write (should always be written with
-                                                           a 1)
-                                                         - Cleared when a TWSI master mode op completes
-                                                         - Cleared when a TWSI configuration register
-                                                           access completes
-                                                         - Cleared when the TWSI device reads the
-                                                           register if SLONLY==1 */
-        uint64_t slonly                  : 1;       /**< Slave Only Mode
-                                                         - No operation is initiated with a write when
-                                                           this bit is set - only D field is updated in
-                                                           this case
-                                                         - When clear, a write initiates either a TWSI
-                                                           master-mode operation or a TWSI configuration
-                                                           register access */
-        uint64_t eia                     : 1;       /**< Extended Internal Address - send additional
-                                                         internal address byte (MSB of IA is from IA field
-                                                         of MIO_TWS_SW_TWSI_EXT) (NOT IN PASS 1) */
-        uint64_t op                      : 4;       /**< Opcode field - When the register is written with
-                                                         SLONLY==0, initiate a read or write:
-                                                           0000 => 7-bit Byte Master Mode TWSI Op
-                                                           0001 => 7-bit Byte Combined Read Master Mode Op
-                                                                   7-bit Byte Write w/ IA Master Mode Op
-                                                           0010 => 10-bit Byte Master Mode TWSI Op
-                                                           0011 => 10-bit Byte Combined Read Master Mode Op
-                                                                   10-bit Byte Write w/ IA Master Mode Op
-                                                           0100 => TWSI Master Clock Register
-                                                           0110 => See EOP field
-                                                           1000 => 7-bit 4-byte Master Mode TWSI Op
-                                                           1001 => 7-bit 4-byte Comb. Read Master Mode Op
-                                                                   7-bit 4-byte Write w/ IA Master Mode Op
-                                                           1010 => 10-bit 4-byte Master Mode TWSI Op
-                                                           1011 => 10-bit 4-byte Comb. Read Master Mode Op
-                                                                   10-bit 4-byte Write w/ IA Master Mode Op */
-        uint64_t r                       : 1;       /**< Read bit or result
-                                                         - If set on a write when SLONLY==0, the
-                                                           operation is a read
-                                                         - On a read, this bit returns the result
-                                                           indication for the most recent master mode
-                                                           operation (1 = success, 0 = fail) */
-        uint64_t sovr                    : 1;       /**< Size Override - if set, use the SIZE field to
-                                                         determine Master Mode Op size rather than what
-                                                         the Opcode field specifies.  For operations
-                                                         greater than 4 bytes, the additional data will be
-                                                         contained in the D field of MIO_TWS_SW_TWSI_EXT
-                                                         (NOT IN PASS 1) */
-        uint64_t size                    : 3;       /**< Size in bytes of Master Mode Op if the Size
-                                                         Override bit is set.  Specified in -1 notation
-                                                         (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes)
-                                                         (NOT IN PASS 1) */
-        uint64_t scr                     : 2;       /**< Scratch - unused, but retain state */
-        uint64_t a                       : 10;      /**< Address field
-                                                         - the address of the remote device for a master
-                                                           mode operation
-                                                         - A<9:7> are only used for 10-bit addressing */
-        uint64_t ia                      : 5;       /**< Internal Address - Used when launching a master
-                                                         mode combined read / write with internal address
-                                                         (lower 3 bits are contained in the EOP_IA field) */
-        uint64_t eop_ia                  : 3;       /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0):
-                                                           000 => TWSI Slave Address Register
-                                                           001 => TWSI Data Register
-                                                           010 => TWSI Control Register
-                                                           011 => TWSI Clock Control Register (when R == 0)
-                                                           011 => TWSI Status Register (when R == 1)
-                                                           100 => TWSI Extended Slave Register
-                                                           111 => TWSI Soft Reset Register
-                                                         Also the lower 3 bits of Internal Address when
-                                                           launching a master mode combined read / write
-                                                           with internal address */
-        uint64_t d                       : 32;      /**< Data Field
-                                                         Used on a write when
-                                                           - initiating a master-mode write (SLONLY==0)
-                                                           - writing a TWSI config register (SLONLY==0)
-                                                           - a slave mode write (SLONLY==1)
-                                                         The read value is updated by
-                                                           - a write to this register
-                                                           - master mode completion (contains result or
-                                                             error code)
-                                                           - TWSI config register read (contains result) */
-#else
-        uint64_t d                       : 32;
-        uint64_t eop_ia                  : 3;
-        uint64_t ia                      : 5;
-        uint64_t a                       : 10;
-        uint64_t scr                     : 2;
-        uint64_t size                    : 3;
-        uint64_t sovr                    : 1;
-        uint64_t r                       : 1;
-        uint64_t op                      : 4;
-        uint64_t eia                     : 1;
-        uint64_t slonly                  : 1;
-        uint64_t v                       : 1;
-#endif
-    } s;
-    struct cvmx_mio_twsx_sw_twsi_s       cn30xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn31xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn38xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn38xxp2;
-    struct cvmx_mio_twsx_sw_twsi_s       cn50xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn52xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn52xxp1;
-    struct cvmx_mio_twsx_sw_twsi_s       cn56xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn56xxp1;
-    struct cvmx_mio_twsx_sw_twsi_s       cn58xx;
-    struct cvmx_mio_twsx_sw_twsi_s       cn58xxp1;
-} cvmx_mio_twsx_sw_twsi_t;
-
-
-/**
- * cvmx_mio_tws#_sw_twsi_ext
- *
- * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register
- * 
- * This register contains an additional byte of internal address and 4 additional bytes of data to be
- * used with TWSI master mode operations.  IA will be sent as the first byte of internal address when
- * performing master mode combined read / write with internal address operations and the EIA bit of
- * MIO_TWS_SW_TWSI is set.  D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR
- * must be set to perform operations greater than 4 bytes).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_twsx_sw_twsi_ext_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ia                      : 8;       /**< Extended Internal Address */
-        uint64_t d                       : 32;      /**< Extended Data Field */
-#else
-        uint64_t d                       : 32;
-        uint64_t ia                      : 8;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn30xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn31xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn38xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn38xxp2;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn50xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn52xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn52xxp1;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn56xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn56xxp1;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn58xx;
-    struct cvmx_mio_twsx_sw_twsi_ext_s   cn58xxp1;
-} cvmx_mio_twsx_sw_twsi_ext_t;
-
-
-/**
- * cvmx_mio_tws#_twsi_sw
- *
- * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register
- * 
- * This register allows the TWSI device to transfer data to software and later check that software has
- * received the information.
- * 
- * This register should be read or written by the TWSI device, and read by software. The TWSI device can
- * use one-byte or four-byte payload writes, and two-byte payload reads.
- * 
- * The TWSI device considers this register valid when V==1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_twsx_twsi_sw_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t v                       : 2;       /**< Valid Bits
-                                                         - Not directly writable
-                                                         - Set to 1 on any write by the TWSI device
-                                                         - Cleared on any read by software */
-        uint64_t reserved_32_61          : 30;
-        uint64_t d                       : 32;      /**< Data Field - updated on a write by the TWSI device */
-#else
-        uint64_t d                       : 32;
-        uint64_t reserved_32_61          : 30;
-        uint64_t v                       : 2;
-#endif
-    } s;
-    struct cvmx_mio_twsx_twsi_sw_s       cn30xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn31xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn38xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn38xxp2;
-    struct cvmx_mio_twsx_twsi_sw_s       cn50xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn52xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn52xxp1;
-    struct cvmx_mio_twsx_twsi_sw_s       cn56xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn56xxp1;
-    struct cvmx_mio_twsx_twsi_sw_s       cn58xx;
-    struct cvmx_mio_twsx_twsi_sw_s       cn58xxp1;
-} cvmx_mio_twsx_twsi_sw_t;
-
-
-/**
- * cvmx_mio_uart#_dlh
- *
- * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register
- * 
- * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
- * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
- * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
- * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
- * follows: baud rate = eclk / (16 * divisor).
- * 
- * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
- * register. BUSY bit is always clear in PASS3.
- * 
- * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
- * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
- * of eclk should be allowed to pass before transmitting or receiving data.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * IER and DLH registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_dlh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dlh                     : 8;       /**< Divisor Latch High Register */
-#else
-        uint64_t dlh                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_dlh_s          cn30xx;
-    struct cvmx_mio_uartx_dlh_s          cn31xx;
-    struct cvmx_mio_uartx_dlh_s          cn38xx;
-    struct cvmx_mio_uartx_dlh_s          cn38xxp2;
-    struct cvmx_mio_uartx_dlh_s          cn50xx;
-    struct cvmx_mio_uartx_dlh_s          cn52xx;
-    struct cvmx_mio_uartx_dlh_s          cn52xxp1;
-    struct cvmx_mio_uartx_dlh_s          cn56xx;
-    struct cvmx_mio_uartx_dlh_s          cn56xxp1;
-    struct cvmx_mio_uartx_dlh_s          cn58xx;
-    struct cvmx_mio_uartx_dlh_s          cn58xxp1;
-} cvmx_mio_uartx_dlh_t;
-typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
-
-
-/**
- * cvmx_mio_uart#_dll
- *
- * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register
- * 
- * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
- * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
- * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
- * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
- * follows: baud rate = eclk / (16 * divisor).
- * 
- * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
- * register. BUSY bit is always clear in PASS3.
- * 
- * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
- * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
- * of eclk should be allowed to pass before transmitting or receiving data.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * RBR, THR, and DLL registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_dll_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dll                     : 8;       /**< Divisor Latch Low Register */
-#else
-        uint64_t dll                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_dll_s          cn30xx;
-    struct cvmx_mio_uartx_dll_s          cn31xx;
-    struct cvmx_mio_uartx_dll_s          cn38xx;
-    struct cvmx_mio_uartx_dll_s          cn38xxp2;
-    struct cvmx_mio_uartx_dll_s          cn50xx;
-    struct cvmx_mio_uartx_dll_s          cn52xx;
-    struct cvmx_mio_uartx_dll_s          cn52xxp1;
-    struct cvmx_mio_uartx_dll_s          cn56xx;
-    struct cvmx_mio_uartx_dll_s          cn56xxp1;
-    struct cvmx_mio_uartx_dll_s          cn58xx;
-    struct cvmx_mio_uartx_dll_s          cn58xxp1;
-} cvmx_mio_uartx_dll_t;
-typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
-
-
-/**
- * cvmx_mio_uart#_far
- *
- * MIO_UARTX_FAR = MIO UARTX FIFO Access Register
- * 
- * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive
- * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are
- * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read
- * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the
- * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_far_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t far                     : 1;       /**< FIFO Access Register */
-#else
-        uint64_t far                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uartx_far_s          cn30xx;
-    struct cvmx_mio_uartx_far_s          cn31xx;
-    struct cvmx_mio_uartx_far_s          cn38xx;
-    struct cvmx_mio_uartx_far_s          cn38xxp2;
-    struct cvmx_mio_uartx_far_s          cn50xx;
-    struct cvmx_mio_uartx_far_s          cn52xx;
-    struct cvmx_mio_uartx_far_s          cn52xxp1;
-    struct cvmx_mio_uartx_far_s          cn56xx;
-    struct cvmx_mio_uartx_far_s          cn56xxp1;
-    struct cvmx_mio_uartx_far_s          cn58xx;
-    struct cvmx_mio_uartx_far_s          cn58xxp1;
-} cvmx_mio_uartx_far_t;
-typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
-
-
-/**
- * cvmx_mio_uart#_fcr
- *
- * MIO_UARTX_FCR = MIO UARTX FIFO Control Register
- * 
- * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO
- * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls
- * the THRE Interrupt empty threshold level.
- * 
- * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is
- * changed both the TX and RX FIFOs will be reset.
- * 
- * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is
- * self-clearing and it is not necessary to clear this bit.
- * 
- * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is
- * self-clearing and it is not necessary to clear this bit.
- * 
- * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty
- * threshold level at which THRE Interrupts are generated when the mode is active.  See the following
- * table for encodings:
- * 
- * TX Trigger
- * ----------
- * 00 = empty FIFO
- * 01 = 2 chars in FIFO
- * 10 = FIFO 1/4 full
- * 11 = FIFO 1/2 full
- * 
- * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7
- * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI).
- * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted.
- * See the following table for encodings:
- * 
- * RX Trigger
- * ----------
- * 00 = 1 char in FIFO
- * 01 = FIFO 1/4 full
- * 10 = FIFO 1/2 full
- * 11 = FIFO 2 chars less than full
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * IIR and FCR registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_fcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rxtrig                  : 2;       /**< RX Trigger */
-        uint64_t txtrig                  : 2;       /**< TX Trigger */
-        uint64_t reserved_3_3            : 1;
-        uint64_t txfr                    : 1;       /**< TX FIFO reset */
-        uint64_t rxfr                    : 1;       /**< RX FIFO reset */
-        uint64_t en                      : 1;       /**< FIFO enable */
-#else
-        uint64_t en                      : 1;
-        uint64_t rxfr                    : 1;
-        uint64_t txfr                    : 1;
-        uint64_t reserved_3_3            : 1;
-        uint64_t txtrig                  : 2;
-        uint64_t rxtrig                  : 2;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_fcr_s          cn30xx;
-    struct cvmx_mio_uartx_fcr_s          cn31xx;
-    struct cvmx_mio_uartx_fcr_s          cn38xx;
-    struct cvmx_mio_uartx_fcr_s          cn38xxp2;
-    struct cvmx_mio_uartx_fcr_s          cn50xx;
-    struct cvmx_mio_uartx_fcr_s          cn52xx;
-    struct cvmx_mio_uartx_fcr_s          cn52xxp1;
-    struct cvmx_mio_uartx_fcr_s          cn56xx;
-    struct cvmx_mio_uartx_fcr_s          cn56xxp1;
-    struct cvmx_mio_uartx_fcr_s          cn58xx;
-    struct cvmx_mio_uartx_fcr_s          cn58xxp1;
-} cvmx_mio_uartx_fcr_t;
-typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
-
-
-/**
- * cvmx_mio_uart#_htx
- *
- * MIO_UARTX_HTX = MIO UARTX Halt TX Register
- * 
- * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be
- * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will
- * have no effect.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_htx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t htx                     : 1;       /**< Halt TX */
-#else
-        uint64_t htx                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uartx_htx_s          cn30xx;
-    struct cvmx_mio_uartx_htx_s          cn31xx;
-    struct cvmx_mio_uartx_htx_s          cn38xx;
-    struct cvmx_mio_uartx_htx_s          cn38xxp2;
-    struct cvmx_mio_uartx_htx_s          cn50xx;
-    struct cvmx_mio_uartx_htx_s          cn52xx;
-    struct cvmx_mio_uartx_htx_s          cn52xxp1;
-    struct cvmx_mio_uartx_htx_s          cn56xx;
-    struct cvmx_mio_uartx_htx_s          cn56xxp1;
-    struct cvmx_mio_uartx_htx_s          cn58xx;
-    struct cvmx_mio_uartx_htx_s          cn58xxp1;
-} cvmx_mio_uartx_htx_t;
-typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
-
-
-/**
- * cvmx_mio_uart#_ier
- *
- * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register
- * 
- * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable
- * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt
- * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line
- * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI).
- * 
- * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode.
- * 
- * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
- * this register.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * IER and DLH registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_ier_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ptime                   : 1;       /**< Programmable THRE Interrupt mode enable */
-        uint64_t reserved_4_6            : 3;
-        uint64_t edssi                   : 1;       /**< Enable Modem Status Interrupt */
-        uint64_t elsi                    : 1;       /**< Enable Receiver Line Status Interrupt */
-        uint64_t etbei                   : 1;       /**< Enable Transmitter Holding Register Empty Interrupt */
-        uint64_t erbfi                   : 1;       /**< Enable Received Data Available Interrupt */
-#else
-        uint64_t erbfi                   : 1;
-        uint64_t etbei                   : 1;
-        uint64_t elsi                    : 1;
-        uint64_t edssi                   : 1;
-        uint64_t reserved_4_6            : 3;
-        uint64_t ptime                   : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_ier_s          cn30xx;
-    struct cvmx_mio_uartx_ier_s          cn31xx;
-    struct cvmx_mio_uartx_ier_s          cn38xx;
-    struct cvmx_mio_uartx_ier_s          cn38xxp2;
-    struct cvmx_mio_uartx_ier_s          cn50xx;
-    struct cvmx_mio_uartx_ier_s          cn52xx;
-    struct cvmx_mio_uartx_ier_s          cn52xxp1;
-    struct cvmx_mio_uartx_ier_s          cn56xx;
-    struct cvmx_mio_uartx_ier_s          cn56xxp1;
-    struct cvmx_mio_uartx_ier_s          cn58xx;
-    struct cvmx_mio_uartx_ier_s          cn58xxp1;
-} cvmx_mio_uartx_ier_t;
-typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
-
-
-/**
- * cvmx_mio_uart#_iir
- *
- * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register
- * 
- * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an
- * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs
- * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending
- * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt
- * reset control:
- * 
- * Interrupt   Priority   Interrupt         Interrupt                                       Interrupt
- * ID          Level      Type              Source                                          Reset By
- * ---------------------------------------------------------------------------------------------------------------------------------
- * 0001        -          None              None                                            -
- * 
- * 0110        Highest    Receiver Line     Overrun, parity, or framing errors or break     Reading the Line Status Register
- *                        Status            interrupt
- * 
- * 0100        Second     Received Data     Receiver data available (FIFOs disabled) or     Reading the Receiver Buffer Register
- *                        Available         RX FIFO trigger level reached (FIFOs            (FIFOs disabled) or the FIFO drops below
- *                                          enabled)                                        the trigger level (FIFOs enabled)
- * 
- * 1100        Second     Character         No characters in or out of the RX FIFO          Reading the Receiver Buffer Register
- *                        Timeout           during the last 4 character times and there
- *                        Indication        is at least 1 character in it during this
- *                                          time
- * 
- * 0010        Third      Transmitter       Transmitter Holding Register Empty              Reading the Interrupt Identity Register
- *                        Holding           (Programmable THRE Mode disabled) or TX         (if source of interrupt) or writing into
- *                        Register          FIFO at or below threshold (Programmable        THR (FIFOs or THRE Mode disabled) or TX
- *                        Empty             THRE Mode enabled)                              FIFO above threshold (FIFOs and THRE
- *                                                                                          Mode enabled)
- * 
- * 0000        Fourth     Modem Status      Clear To Send (CTS) or Data Set Ready (DSR)     Reading the Modem Status Register
- *                        Changed           or Ring Indicator (RI) or Data Carrier
- *                                          Detect (DCD) changed (note: if auto flow
- *                                          control mode is enabled, a change in CTS
- *                                          will not cause an interrupt)
- * 
- * 0111        Fifth      Busy Detect       Software has tried to write to the Line         Reading the UART Status Register
- *                        Indication        Control Register while the BUSY bit of the
- *                                          UART Status Register was set
- * 
- * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * IIR and FCR registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_iir_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t fen                     : 2;       /**< FIFO-enabled bits */
-        uint64_t reserved_4_5            : 2;
-        cvmx_uart_iid_t iid              : 4;       /**< Interrupt ID */
-#else
-        cvmx_uart_iid_t iid              : 4;
-        uint64_t reserved_4_5            : 2;
-        uint64_t fen                     : 2;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_iir_s          cn30xx;
-    struct cvmx_mio_uartx_iir_s          cn31xx;
-    struct cvmx_mio_uartx_iir_s          cn38xx;
-    struct cvmx_mio_uartx_iir_s          cn38xxp2;
-    struct cvmx_mio_uartx_iir_s          cn50xx;
-    struct cvmx_mio_uartx_iir_s          cn52xx;
-    struct cvmx_mio_uartx_iir_s          cn52xxp1;
-    struct cvmx_mio_uartx_iir_s          cn56xx;
-    struct cvmx_mio_uartx_iir_s          cn56xxp1;
-    struct cvmx_mio_uartx_iir_s          cn58xx;
-    struct cvmx_mio_uartx_iir_s          cn58xxp1;
-} cvmx_mio_uartx_iir_t;
-typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
-
-
-/**
- * cvmx_mio_uart#_lcr
- *
- * MIO_UARTX_LCR = MIO UARTX Line Control Register
- * 
- * The Line Control Register (LCR) controls the format of the data that is transmitted and received by
- * the UART.
- * 
- * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of
- * data bits per character that are transmitted and received. See the following table for encodings:
- * 
- * CLS
- * ---
- * 00 = 5 bits (bits 0-4 sent)
- * 01 = 6 bits (bits 0-5 sent)
- * 10 = 7 bits (bits 0-6 sent)
- * 11 = 8 bits (all bits sent)
- * 
- * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted
- * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are
- * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that
- * regardless of the number of stop bits selected the receiver will only check the first stop bit.
- * 
- * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and
- * detection in transmitted and received serial character respectively.
- * 
- * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd
- * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd
- * number of ones is transmitted or checked.
- * 
- * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout
- * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback
- * mode, the break condition is internally looped back to the receiver.
- * 
- * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the
- * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after
- * initial baud rate setup in order to access other registers.
- * 
- * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART
- * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable
- * because the BUSY bit is always clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_lcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dlab                    : 1;       /**< Divisor Latch Address bit */
-        uint64_t brk                     : 1;       /**< Break Control bit */
-        uint64_t reserved_5_5            : 1;
-        uint64_t eps                     : 1;       /**< Even Parity Select bit */
-        uint64_t pen                     : 1;       /**< Parity Enable bit */
-        uint64_t stop                    : 1;       /**< Stop Control bit */
-        cvmx_uart_bits_t cls             : 2;       /**< Character Length Select */
-#else
-        cvmx_uart_bits_t cls             : 2;
-        uint64_t stop                    : 1;
-        uint64_t pen                     : 1;
-        uint64_t eps                     : 1;
-        uint64_t reserved_5_5            : 1;
-        uint64_t brk                     : 1;
-        uint64_t dlab                    : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_lcr_s          cn30xx;
-    struct cvmx_mio_uartx_lcr_s          cn31xx;
-    struct cvmx_mio_uartx_lcr_s          cn38xx;
-    struct cvmx_mio_uartx_lcr_s          cn38xxp2;
-    struct cvmx_mio_uartx_lcr_s          cn50xx;
-    struct cvmx_mio_uartx_lcr_s          cn52xx;
-    struct cvmx_mio_uartx_lcr_s          cn52xxp1;
-    struct cvmx_mio_uartx_lcr_s          cn56xx;
-    struct cvmx_mio_uartx_lcr_s          cn56xxp1;
-    struct cvmx_mio_uartx_lcr_s          cn58xx;
-    struct cvmx_mio_uartx_lcr_s          cn58xxp1;
-} cvmx_mio_uartx_lcr_t;
-typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
-
-
-/**
- * cvmx_mio_uart#_lsr
- *
- * MIO_UARTX_LSR = MIO UARTX Line Status Register
- * 
- * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This
- * status can be read by the user at anytime.
- * 
- * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one
- * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO
- * mode, or when the receiver FIFO is empty, in FIFO mode.
- * 
- * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred
- * because a new data character was received before the previous data was read. In the non-FIFO mode, the
- * OE bit is set when a new character arrives in the receiver before the previous character was read from
- * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error
- * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is
- * retained and the data in the receive shift register is lost.
- * 
- * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the
- * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is
- * associated with a character received, it is revealed when the character with the parity error arrives
- * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break
- * interrupt has occurred, as indicated by the Break Interrupt (BI) bit.
- * 
- * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the
- * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received
- * data. In the FIFO mode, since the framing error is associated with a character received, it is
- * revealed when the character with the framing error is at the top of the FIFO. When a framing error
- * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start
- * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and
- * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has
- * occurred, as indicated by the Break Interrupt (BI) bit.
- * 
- * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed.
- * 
- * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in
- * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on
- * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the
- * FIFO mode, the character associated with the break condition is carried through the FIFO and is
- * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-
- * FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
- * 
- * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode
- * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is
- * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no
- * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the
- * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5
- * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE
- * Interrupts, which are then controlled by the FCR[5:4] threshold setting.
- * 
- * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the
- * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever
- * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is
- * typically used to make sure it is safe to change control registers. Changing control registers while
- * the transmitter is busy can result in corrupt data being transmitted.
- * 
- * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It
- * is set when there is at least one parity error, framing error, or break indication in the FIFO. This
- * bit is cleared when the LSR is read and the character with the error is at the top of the receiver
- * FIFO and there are no subsequent errors in the FIFO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_lsr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ferr                    : 1;       /**< Error in Receiver FIFO bit */
-        uint64_t temt                    : 1;       /**< Transmitter Empty bit */
-        uint64_t thre                    : 1;       /**< Transmitter Holding Register Empty bit */
-        uint64_t bi                      : 1;       /**< Break Interrupt bit */
-        uint64_t fe                      : 1;       /**< Framing Error bit */
-        uint64_t pe                      : 1;       /**< Parity Error bit */
-        uint64_t oe                      : 1;       /**< Overrun Error bit */
-        uint64_t dr                      : 1;       /**< Data Ready bit */
-#else
-        uint64_t dr                      : 1;
-        uint64_t oe                      : 1;
-        uint64_t pe                      : 1;
-        uint64_t fe                      : 1;
-        uint64_t bi                      : 1;
-        uint64_t thre                    : 1;
-        uint64_t temt                    : 1;
-        uint64_t ferr                    : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_lsr_s          cn30xx;
-    struct cvmx_mio_uartx_lsr_s          cn31xx;
-    struct cvmx_mio_uartx_lsr_s          cn38xx;
-    struct cvmx_mio_uartx_lsr_s          cn38xxp2;
-    struct cvmx_mio_uartx_lsr_s          cn50xx;
-    struct cvmx_mio_uartx_lsr_s          cn52xx;
-    struct cvmx_mio_uartx_lsr_s          cn52xxp1;
-    struct cvmx_mio_uartx_lsr_s          cn56xx;
-    struct cvmx_mio_uartx_lsr_s          cn56xxp1;
-    struct cvmx_mio_uartx_lsr_s          cn58xx;
-    struct cvmx_mio_uartx_lsr_s          cn58xxp1;
-} cvmx_mio_uartx_lsr_t;
-typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
-
-
-/**
- * cvmx_mio_uart#_mcr
- *
- * MIO_UARTX_MCR = MIO UARTX Modem Control Register
- * 
- * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART.
- * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the
- * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n.  In loopback mode, these outputs are
- * driven inactive high while the values in these locations are internally looped back to the inputs.
- * 
- * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated
- * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The
- * rts_n output will be de-asserted whenever RTS (bit 1) is set low.
- * 
- * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1
- * and OUT2 bits still function in Loopback mode.  The UART1 dtr_n, out1_n, and out2_n outputs are not
- * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback
- * mode.
- * 
- * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output
- * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This
- * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n,
- * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n)
- * are looped back to the inputs, internally.
- * 
- * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set,
- * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled.
- * 
- * Auto RTS becomes active when the following occurs:
- * 1. MCR bit 1 is set
- * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
- * 3. MCR bit 5 is set (must be set after FCR bit 0)
- * 
- * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the
- * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the
- * other UART stops sending serial data until the receiver FIFO has available space.
- * 
- * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one
- * additional character may be transmitted to the UART after rts_n has become inactive (due to data
- * already having entered the transmitter block in the other UART), setting the threshold to 2 less
- * than full allows maximum use of the FIFO with a safety zone of one character.
- * 
- * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n
- * again becomes active-low, signalling the other UART to continue sending data. It is important to note
- * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are
- * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive,
- * rts_n is controlled solely by MCR[1].
- * 
- * Auto CTS becomes active when the following occurs:
- * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
- * 2. MCR bit 5 is set (must be set after FCR bit 0)
- * 
- * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This
- * prevents overflowing the FIFO of the receiving UART.
- * 
- * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another
- * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the
- * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either
- * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode
- * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO
- * full status, software can poll this before each write to the Transmitter FIFO.
- * 
- * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the
- * FIFO may be read through the Transmit FIFO Level (TFL) register.
- * 
- * When the cts_n input becomes active-low again, transmission resumes. It is important to note that,
- * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are
- * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by
- * cts_n.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_mcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t afce                    : 1;       /**< Auto Flow Control Enable bit */
-        uint64_t loop                    : 1;       /**< Loopback bit */
-        uint64_t out2                    : 1;       /**< OUT2 output bit */
-        uint64_t out1                    : 1;       /**< OUT1 output bit */
-        uint64_t rts                     : 1;       /**< Request To Send output bit */
-        uint64_t dtr                     : 1;       /**< Data Terminal Ready output bit */
-#else
-        uint64_t dtr                     : 1;
-        uint64_t rts                     : 1;
-        uint64_t out1                    : 1;
-        uint64_t out2                    : 1;
-        uint64_t loop                    : 1;
-        uint64_t afce                    : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_mio_uartx_mcr_s          cn30xx;
-    struct cvmx_mio_uartx_mcr_s          cn31xx;
-    struct cvmx_mio_uartx_mcr_s          cn38xx;
-    struct cvmx_mio_uartx_mcr_s          cn38xxp2;
-    struct cvmx_mio_uartx_mcr_s          cn50xx;
-    struct cvmx_mio_uartx_mcr_s          cn52xx;
-    struct cvmx_mio_uartx_mcr_s          cn52xxp1;
-    struct cvmx_mio_uartx_mcr_s          cn56xx;
-    struct cvmx_mio_uartx_mcr_s          cn56xxp1;
-    struct cvmx_mio_uartx_mcr_s          cn58xx;
-    struct cvmx_mio_uartx_mcr_s          cn58xxp1;
-} cvmx_mio_uartx_mcr_t;
-typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
-
-
-/**
- * cvmx_mio_uart#_msr
- *
- * MIO_UARTX_MSR = MIO UARTX Modem Status Register
- * 
- * The Modem Status Register (MSR) contains the current status of the modem control input lines and if
- * they changed.
- * 
- * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n,
- * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n
- * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In
- * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and
- * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state
- * from a high to a low.
- * 
- * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software
- * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains
- * asserted.
- * 
- * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem
- * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI
- * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS
- * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2
- * (Out1), and DCD is the same as MCR bit 3 (Out2).
- * 
- * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip.
- * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode.  The UART1 dsr_n, ri_n, and dcd_n
- * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and
- * DCD bits will be '0' when not in Loopback mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_msr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dcd                     : 1;       /**< Data Carrier Detect input bit */
-        uint64_t ri                      : 1;       /**< Ring Indicator input bit */
-        uint64_t dsr                     : 1;       /**< Data Set Ready input bit */
-        uint64_t cts                     : 1;       /**< Clear To Send input bit */
-        uint64_t ddcd                    : 1;       /**< Delta Data Carrier Detect bit */
-        uint64_t teri                    : 1;       /**< Trailing Edge of Ring Indicator bit */
-        uint64_t ddsr                    : 1;       /**< Delta Data Set Ready bit */
-        uint64_t dcts                    : 1;       /**< Delta Clear To Send bit */
-#else
-        uint64_t dcts                    : 1;
-        uint64_t ddsr                    : 1;
-        uint64_t teri                    : 1;
-        uint64_t ddcd                    : 1;
-        uint64_t cts                     : 1;
-        uint64_t dsr                     : 1;
-        uint64_t ri                      : 1;
-        uint64_t dcd                     : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_msr_s          cn30xx;
-    struct cvmx_mio_uartx_msr_s          cn31xx;
-    struct cvmx_mio_uartx_msr_s          cn38xx;
-    struct cvmx_mio_uartx_msr_s          cn38xxp2;
-    struct cvmx_mio_uartx_msr_s          cn50xx;
-    struct cvmx_mio_uartx_msr_s          cn52xx;
-    struct cvmx_mio_uartx_msr_s          cn52xxp1;
-    struct cvmx_mio_uartx_msr_s          cn56xx;
-    struct cvmx_mio_uartx_msr_s          cn56xxp1;
-    struct cvmx_mio_uartx_msr_s          cn58xx;
-    struct cvmx_mio_uartx_msr_s          cn58xxp1;
-} cvmx_mio_uartx_msr_t;
-typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
-
-
-/**
- * cvmx_mio_uart#_rbr
- *
- * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register
- * 
- * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the
- * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the
- * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be
- * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When
- * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO
- * is full (64 characters) and this register is not read before the next data character arrives, then the
- * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs.
- * 
- * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
- * this register.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * RBR, THR, and DLL registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_rbr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rbr                     : 8;       /**< Receive Buffer Register */
-#else
-        uint64_t rbr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_rbr_s          cn30xx;
-    struct cvmx_mio_uartx_rbr_s          cn31xx;
-    struct cvmx_mio_uartx_rbr_s          cn38xx;
-    struct cvmx_mio_uartx_rbr_s          cn38xxp2;
-    struct cvmx_mio_uartx_rbr_s          cn50xx;
-    struct cvmx_mio_uartx_rbr_s          cn52xx;
-    struct cvmx_mio_uartx_rbr_s          cn52xxp1;
-    struct cvmx_mio_uartx_rbr_s          cn56xx;
-    struct cvmx_mio_uartx_rbr_s          cn56xxp1;
-    struct cvmx_mio_uartx_rbr_s          cn58xx;
-    struct cvmx_mio_uartx_rbr_s          cn58xxp1;
-} cvmx_mio_uartx_rbr_t;
-typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
-
-
-/**
- * cvmx_mio_uart#_rfl
- *
- * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register
- * 
- * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_rfl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t rfl                     : 7;       /**< Receive FIFO Level Register */
-#else
-        uint64_t rfl                     : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mio_uartx_rfl_s          cn30xx;
-    struct cvmx_mio_uartx_rfl_s          cn31xx;
-    struct cvmx_mio_uartx_rfl_s          cn38xx;
-    struct cvmx_mio_uartx_rfl_s          cn38xxp2;
-    struct cvmx_mio_uartx_rfl_s          cn50xx;
-    struct cvmx_mio_uartx_rfl_s          cn52xx;
-    struct cvmx_mio_uartx_rfl_s          cn52xxp1;
-    struct cvmx_mio_uartx_rfl_s          cn56xx;
-    struct cvmx_mio_uartx_rfl_s          cn56xxp1;
-    struct cvmx_mio_uartx_rfl_s          cn58xx;
-    struct cvmx_mio_uartx_rfl_s          cn58xxp1;
-} cvmx_mio_uartx_rfl_t;
-typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
-
-
-/**
- * cvmx_mio_uart#_rfw
- *
- * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register
- * 
- * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is
- * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each
- * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are
- * not enabled, this register is used to write data to the RBR.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_rfw_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t rffe                    : 1;       /**< Receive FIFO Framing Error */
-        uint64_t rfpe                    : 1;       /**< Receive FIFO Parity Error */
-        uint64_t rfwd                    : 8;       /**< Receive FIFO Write Data */
-#else
-        uint64_t rfwd                    : 8;
-        uint64_t rfpe                    : 1;
-        uint64_t rffe                    : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_mio_uartx_rfw_s          cn30xx;
-    struct cvmx_mio_uartx_rfw_s          cn31xx;
-    struct cvmx_mio_uartx_rfw_s          cn38xx;
-    struct cvmx_mio_uartx_rfw_s          cn38xxp2;
-    struct cvmx_mio_uartx_rfw_s          cn50xx;
-    struct cvmx_mio_uartx_rfw_s          cn52xx;
-    struct cvmx_mio_uartx_rfw_s          cn52xxp1;
-    struct cvmx_mio_uartx_rfw_s          cn56xx;
-    struct cvmx_mio_uartx_rfw_s          cn56xxp1;
-    struct cvmx_mio_uartx_rfw_s          cn58xx;
-    struct cvmx_mio_uartx_rfw_s          cn58xxp1;
-} cvmx_mio_uartx_rfw_t;
-typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
-
-
-/**
- * cvmx_mio_uart#_sbcr
- *
- * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register
- * 
- * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can
- * be used to remove the burden of having to perform a read-modify-write on the LCR.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_sbcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t sbcr                    : 1;       /**< Shadow Break Control */
-#else
-        uint64_t sbcr                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uartx_sbcr_s         cn30xx;
-    struct cvmx_mio_uartx_sbcr_s         cn31xx;
-    struct cvmx_mio_uartx_sbcr_s         cn38xx;
-    struct cvmx_mio_uartx_sbcr_s         cn38xxp2;
-    struct cvmx_mio_uartx_sbcr_s         cn50xx;
-    struct cvmx_mio_uartx_sbcr_s         cn52xx;
-    struct cvmx_mio_uartx_sbcr_s         cn52xxp1;
-    struct cvmx_mio_uartx_sbcr_s         cn56xx;
-    struct cvmx_mio_uartx_sbcr_s         cn56xxp1;
-    struct cvmx_mio_uartx_sbcr_s         cn58xx;
-    struct cvmx_mio_uartx_sbcr_s         cn58xxp1;
-} cvmx_mio_uartx_sbcr_t;
-typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
-
-
-/**
- * cvmx_mio_uart#_scr
- *
- * MIO_UARTX_SCR = MIO UARTX Scratchpad Register
- * 
- * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary
- * storage space.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_scr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t scr                     : 8;       /**< Scratchpad Register */
-#else
-        uint64_t scr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_scr_s          cn30xx;
-    struct cvmx_mio_uartx_scr_s          cn31xx;
-    struct cvmx_mio_uartx_scr_s          cn38xx;
-    struct cvmx_mio_uartx_scr_s          cn38xxp2;
-    struct cvmx_mio_uartx_scr_s          cn50xx;
-    struct cvmx_mio_uartx_scr_s          cn52xx;
-    struct cvmx_mio_uartx_scr_s          cn52xxp1;
-    struct cvmx_mio_uartx_scr_s          cn56xx;
-    struct cvmx_mio_uartx_scr_s          cn56xxp1;
-    struct cvmx_mio_uartx_scr_s          cn58xx;
-    struct cvmx_mio_uartx_scr_s          cn58xxp1;
-} cvmx_mio_uartx_scr_t;
-typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
-
-
-/**
- * cvmx_mio_uart#_sfe
- *
- * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register
- * 
- * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that
- * can be used to remove the burden of having to store the previously written value to the FCR in memory
- * and having to mask this value so that only the FIFO enable bit gets updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_sfe_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t sfe                     : 1;       /**< Shadow FIFO Enable */
-#else
-        uint64_t sfe                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uartx_sfe_s          cn30xx;
-    struct cvmx_mio_uartx_sfe_s          cn31xx;
-    struct cvmx_mio_uartx_sfe_s          cn38xx;
-    struct cvmx_mio_uartx_sfe_s          cn38xxp2;
-    struct cvmx_mio_uartx_sfe_s          cn50xx;
-    struct cvmx_mio_uartx_sfe_s          cn52xx;
-    struct cvmx_mio_uartx_sfe_s          cn52xxp1;
-    struct cvmx_mio_uartx_sfe_s          cn56xx;
-    struct cvmx_mio_uartx_sfe_s          cn56xxp1;
-    struct cvmx_mio_uartx_sfe_s          cn58xx;
-    struct cvmx_mio_uartx_sfe_s          cn58xxp1;
-} cvmx_mio_uartx_sfe_t;
-typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
-
-
-/**
- * cvmx_mio_uart#_srr
- *
- * MIO_UARTX_SRR = MIO UARTX Software Reset Register
- * 
- * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive
- * FIFO and/or the transmit FIFO.
- * 
- * Bit 0 of the SRR is the UART Soft Reset (USR) bit.  Setting this bit resets the UART.
- * 
- * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove
- * the burden on software having to store previously written FCR values (which are pretty static) just
- * to reset the receive FIFO.
- * 
- * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove
- * the burden on software having to store previously written FCR values (which are pretty static) just
- * to reset the transmit FIFO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_srr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t stfr                    : 1;       /**< Shadow TX FIFO Reset */
-        uint64_t srfr                    : 1;       /**< Shadow RX FIFO Reset */
-        uint64_t usr                     : 1;       /**< UART Soft Reset */
-#else
-        uint64_t usr                     : 1;
-        uint64_t srfr                    : 1;
-        uint64_t stfr                    : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_mio_uartx_srr_s          cn30xx;
-    struct cvmx_mio_uartx_srr_s          cn31xx;
-    struct cvmx_mio_uartx_srr_s          cn38xx;
-    struct cvmx_mio_uartx_srr_s          cn38xxp2;
-    struct cvmx_mio_uartx_srr_s          cn50xx;
-    struct cvmx_mio_uartx_srr_s          cn52xx;
-    struct cvmx_mio_uartx_srr_s          cn52xxp1;
-    struct cvmx_mio_uartx_srr_s          cn56xx;
-    struct cvmx_mio_uartx_srr_s          cn56xxp1;
-    struct cvmx_mio_uartx_srr_s          cn58xx;
-    struct cvmx_mio_uartx_srr_s          cn58xxp1;
-} cvmx_mio_uartx_srr_t;
-typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
-
-
-/**
- * cvmx_mio_uart#_srt
- *
- * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register
- * 
- * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that
- * can be used to remove the burden of having to store the previously written value to the FCR in memory
- * and having to mask this value so that only the RX Trigger bits get updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_srt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t srt                     : 2;       /**< Shadow RX Trigger */
-#else
-        uint64_t srt                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_uartx_srt_s          cn30xx;
-    struct cvmx_mio_uartx_srt_s          cn31xx;
-    struct cvmx_mio_uartx_srt_s          cn38xx;
-    struct cvmx_mio_uartx_srt_s          cn38xxp2;
-    struct cvmx_mio_uartx_srt_s          cn50xx;
-    struct cvmx_mio_uartx_srt_s          cn52xx;
-    struct cvmx_mio_uartx_srt_s          cn52xxp1;
-    struct cvmx_mio_uartx_srt_s          cn56xx;
-    struct cvmx_mio_uartx_srt_s          cn56xxp1;
-    struct cvmx_mio_uartx_srt_s          cn58xx;
-    struct cvmx_mio_uartx_srt_s          cn58xxp1;
-} cvmx_mio_uartx_srt_t;
-typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
-
-
-/**
- * cvmx_mio_uart#_srts
- *
- * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register
- * 
- * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can
- * be used to remove the burden of having to perform a read-modify-write on the MCR.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_srts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t srts                    : 1;       /**< Shadow Request To Send */
-#else
-        uint64_t srts                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uartx_srts_s         cn30xx;
-    struct cvmx_mio_uartx_srts_s         cn31xx;
-    struct cvmx_mio_uartx_srts_s         cn38xx;
-    struct cvmx_mio_uartx_srts_s         cn38xxp2;
-    struct cvmx_mio_uartx_srts_s         cn50xx;
-    struct cvmx_mio_uartx_srts_s         cn52xx;
-    struct cvmx_mio_uartx_srts_s         cn52xxp1;
-    struct cvmx_mio_uartx_srts_s         cn56xx;
-    struct cvmx_mio_uartx_srts_s         cn56xxp1;
-    struct cvmx_mio_uartx_srts_s         cn58xx;
-    struct cvmx_mio_uartx_srts_s         cn58xxp1;
-} cvmx_mio_uartx_srts_t;
-typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
-
-
-/**
- * cvmx_mio_uart#_stt
- *
- * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register
- * 
- * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that
- * can be used to remove the burden of having to store the previously written value to the FCR in memory
- * and having to mask this value so that only the TX Trigger bits get updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_stt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t stt                     : 2;       /**< Shadow TX Trigger */
-#else
-        uint64_t stt                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_uartx_stt_s          cn30xx;
-    struct cvmx_mio_uartx_stt_s          cn31xx;
-    struct cvmx_mio_uartx_stt_s          cn38xx;
-    struct cvmx_mio_uartx_stt_s          cn38xxp2;
-    struct cvmx_mio_uartx_stt_s          cn50xx;
-    struct cvmx_mio_uartx_stt_s          cn52xx;
-    struct cvmx_mio_uartx_stt_s          cn52xxp1;
-    struct cvmx_mio_uartx_stt_s          cn56xx;
-    struct cvmx_mio_uartx_stt_s          cn56xxp1;
-    struct cvmx_mio_uartx_stt_s          cn58xx;
-    struct cvmx_mio_uartx_stt_s          cn58xxp1;
-} cvmx_mio_uartx_stt_t;
-typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
-
-
-/**
- * cvmx_mio_uart#_tfl
- *
- * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register
- * 
- * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_tfl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t tfl                     : 7;       /**< Transmit FIFO Level Register */
-#else
-        uint64_t tfl                     : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mio_uartx_tfl_s          cn30xx;
-    struct cvmx_mio_uartx_tfl_s          cn31xx;
-    struct cvmx_mio_uartx_tfl_s          cn38xx;
-    struct cvmx_mio_uartx_tfl_s          cn38xxp2;
-    struct cvmx_mio_uartx_tfl_s          cn50xx;
-    struct cvmx_mio_uartx_tfl_s          cn52xx;
-    struct cvmx_mio_uartx_tfl_s          cn52xxp1;
-    struct cvmx_mio_uartx_tfl_s          cn56xx;
-    struct cvmx_mio_uartx_tfl_s          cn56xxp1;
-    struct cvmx_mio_uartx_tfl_s          cn58xx;
-    struct cvmx_mio_uartx_tfl_s          cn58xxp1;
-} cvmx_mio_uartx_tfl_t;
-typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
-
-
-/**
- * cvmx_mio_uart#_tfr
- *
- * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register
- * 
- * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is
- * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO.
- * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the
- * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_tfr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t tfr                     : 8;       /**< Transmit FIFO Read Register */
-#else
-        uint64_t tfr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_tfr_s          cn30xx;
-    struct cvmx_mio_uartx_tfr_s          cn31xx;
-    struct cvmx_mio_uartx_tfr_s          cn38xx;
-    struct cvmx_mio_uartx_tfr_s          cn38xxp2;
-    struct cvmx_mio_uartx_tfr_s          cn50xx;
-    struct cvmx_mio_uartx_tfr_s          cn52xx;
-    struct cvmx_mio_uartx_tfr_s          cn52xxp1;
-    struct cvmx_mio_uartx_tfr_s          cn56xx;
-    struct cvmx_mio_uartx_tfr_s          cn56xxp1;
-    struct cvmx_mio_uartx_tfr_s          cn58xx;
-    struct cvmx_mio_uartx_tfr_s          cn58xxp1;
-} cvmx_mio_uartx_tfr_t;
-typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
-
-
-/**
- * cvmx_mio_uart#_thr
- *
- * MIO_UARTX_THR = MIO UARTX Transmit Holding Register
- * 
- * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the
- * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of
- * the Line Status Register (LSR) is set.
- * 
- * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any
- * additional writes to the THR before the THRE is set again causes the THR data to be overwritten.
- * 
- * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may
- * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results
- * in the write data being lost.
- * 
- * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
- * this register.
- * 
- * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
- * RBR, THR, and DLL registers are the same.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_thr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t thr                     : 8;       /**< Transmit Holding Register */
-#else
-        uint64_t thr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uartx_thr_s          cn30xx;
-    struct cvmx_mio_uartx_thr_s          cn31xx;
-    struct cvmx_mio_uartx_thr_s          cn38xx;
-    struct cvmx_mio_uartx_thr_s          cn38xxp2;
-    struct cvmx_mio_uartx_thr_s          cn50xx;
-    struct cvmx_mio_uartx_thr_s          cn52xx;
-    struct cvmx_mio_uartx_thr_s          cn52xxp1;
-    struct cvmx_mio_uartx_thr_s          cn56xx;
-    struct cvmx_mio_uartx_thr_s          cn56xxp1;
-    struct cvmx_mio_uartx_thr_s          cn58xx;
-    struct cvmx_mio_uartx_thr_s          cn58xxp1;
-} cvmx_mio_uartx_thr_t;
-typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
-
-
-/**
- * cvmx_mio_uart#_usr
- *
- * MIO_UARTX_USR = MIO UARTX UART Status Register
- * 
- * The UART Status Register (USR) contains UART status information.
- * 
- * USR bit 0 is the BUSY bit.  When set this bit indicates that a serial transfer is in progress, when
- * clear it indicates that the UART is idle or inactive.
- * 
- * Note: In PASS3, the BUSY bit will always be clear.
- * 
- * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX
- * FIFO Not Empty (RFNE), and RX FIFO Full (RFF).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uartx_usr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t rff                     : 1;       /**< RX FIFO Full */
-        uint64_t rfne                    : 1;       /**< RX FIFO Not Empty */
-        uint64_t tfe                     : 1;       /**< TX FIFO Empty */
-        uint64_t tfnf                    : 1;       /**< TX FIFO Not Full */
-        uint64_t busy                    : 1;       /**< Busy bit (always 0 in PASS3) */
-#else
-        uint64_t busy                    : 1;
-        uint64_t tfnf                    : 1;
-        uint64_t tfe                     : 1;
-        uint64_t rfne                    : 1;
-        uint64_t rff                     : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_mio_uartx_usr_s          cn30xx;
-    struct cvmx_mio_uartx_usr_s          cn31xx;
-    struct cvmx_mio_uartx_usr_s          cn38xx;
-    struct cvmx_mio_uartx_usr_s          cn38xxp2;
-    struct cvmx_mio_uartx_usr_s          cn50xx;
-    struct cvmx_mio_uartx_usr_s          cn52xx;
-    struct cvmx_mio_uartx_usr_s          cn52xxp1;
-    struct cvmx_mio_uartx_usr_s          cn56xx;
-    struct cvmx_mio_uartx_usr_s          cn56xxp1;
-    struct cvmx_mio_uartx_usr_s          cn58xx;
-    struct cvmx_mio_uartx_usr_s          cn58xxp1;
-} cvmx_mio_uartx_usr_t;
-typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
-
-
-/**
- * cvmx_mio_uart2_dlh
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_dlh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dlh                     : 8;       /**< Divisor Latch High Register */
-#else
-        uint64_t dlh                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_dlh_s          cn52xx;
-    struct cvmx_mio_uart2_dlh_s          cn52xxp1;
-} cvmx_mio_uart2_dlh_t;
-
-
-/**
- * cvmx_mio_uart2_dll
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_dll_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dll                     : 8;       /**< Divisor Latch Low Register */
-#else
-        uint64_t dll                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_dll_s          cn52xx;
-    struct cvmx_mio_uart2_dll_s          cn52xxp1;
-} cvmx_mio_uart2_dll_t;
-
-
-/**
- * cvmx_mio_uart2_far
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_far_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t far                     : 1;       /**< FIFO Access Register */
-#else
-        uint64_t far                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uart2_far_s          cn52xx;
-    struct cvmx_mio_uart2_far_s          cn52xxp1;
-} cvmx_mio_uart2_far_t;
-
-
-/**
- * cvmx_mio_uart2_fcr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_fcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rxtrig                  : 2;       /**< RX Trigger */
-        uint64_t txtrig                  : 2;       /**< TX Trigger */
-        uint64_t reserved_3_3            : 1;
-        uint64_t txfr                    : 1;       /**< TX FIFO reset */
-        uint64_t rxfr                    : 1;       /**< RX FIFO reset */
-        uint64_t en                      : 1;       /**< FIFO enable */
-#else
-        uint64_t en                      : 1;
-        uint64_t rxfr                    : 1;
-        uint64_t txfr                    : 1;
-        uint64_t reserved_3_3            : 1;
-        uint64_t txtrig                  : 2;
-        uint64_t rxtrig                  : 2;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_fcr_s          cn52xx;
-    struct cvmx_mio_uart2_fcr_s          cn52xxp1;
-} cvmx_mio_uart2_fcr_t;
-
-
-/**
- * cvmx_mio_uart2_htx
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_htx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t htx                     : 1;       /**< Halt TX */
-#else
-        uint64_t htx                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uart2_htx_s          cn52xx;
-    struct cvmx_mio_uart2_htx_s          cn52xxp1;
-} cvmx_mio_uart2_htx_t;
-
-
-/**
- * cvmx_mio_uart2_ier
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_ier_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ptime                   : 1;       /**< Programmable THRE Interrupt mode enable */
-        uint64_t reserved_4_6            : 3;
-        uint64_t edssi                   : 1;       /**< Enable Modem Status Interrupt */
-        uint64_t elsi                    : 1;       /**< Enable Receiver Line Status Interrupt */
-        uint64_t etbei                   : 1;       /**< Enable Transmitter Holding Register Empty Interrupt */
-        uint64_t erbfi                   : 1;       /**< Enable Received Data Available Interrupt */
-#else
-        uint64_t erbfi                   : 1;
-        uint64_t etbei                   : 1;
-        uint64_t elsi                    : 1;
-        uint64_t edssi                   : 1;
-        uint64_t reserved_4_6            : 3;
-        uint64_t ptime                   : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_ier_s          cn52xx;
-    struct cvmx_mio_uart2_ier_s          cn52xxp1;
-} cvmx_mio_uart2_ier_t;
-
-
-/**
- * cvmx_mio_uart2_iir
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_iir_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t fen                     : 2;       /**< FIFO-enabled bits */
-        uint64_t reserved_4_5            : 2;
-        uint64_t iid                     : 4;       /**< Interrupt ID */
-#else
-        uint64_t iid                     : 4;
-        uint64_t reserved_4_5            : 2;
-        uint64_t fen                     : 2;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_iir_s          cn52xx;
-    struct cvmx_mio_uart2_iir_s          cn52xxp1;
-} cvmx_mio_uart2_iir_t;
-
-
-/**
- * cvmx_mio_uart2_lcr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_lcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dlab                    : 1;       /**< Divisor Latch Address bit */
-        uint64_t brk                     : 1;       /**< Break Control bit */
-        uint64_t reserved_5_5            : 1;
-        uint64_t eps                     : 1;       /**< Even Parity Select bit */
-        uint64_t pen                     : 1;       /**< Parity Enable bit */
-        uint64_t stop                    : 1;       /**< Stop Control bit */
-        uint64_t cls                     : 2;       /**< Character Length Select */
-#else
-        uint64_t cls                     : 2;
-        uint64_t stop                    : 1;
-        uint64_t pen                     : 1;
-        uint64_t eps                     : 1;
-        uint64_t reserved_5_5            : 1;
-        uint64_t brk                     : 1;
-        uint64_t dlab                    : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_lcr_s          cn52xx;
-    struct cvmx_mio_uart2_lcr_s          cn52xxp1;
-} cvmx_mio_uart2_lcr_t;
-
-
-/**
- * cvmx_mio_uart2_lsr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_lsr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t ferr                    : 1;       /**< Error in Receiver FIFO bit */
-        uint64_t temt                    : 1;       /**< Transmitter Empty bit */
-        uint64_t thre                    : 1;       /**< Transmitter Holding Register Empty bit */
-        uint64_t bi                      : 1;       /**< Break Interrupt bit */
-        uint64_t fe                      : 1;       /**< Framing Error bit */
-        uint64_t pe                      : 1;       /**< Parity Error bit */
-        uint64_t oe                      : 1;       /**< Overrun Error bit */
-        uint64_t dr                      : 1;       /**< Data Ready bit */
-#else
-        uint64_t dr                      : 1;
-        uint64_t oe                      : 1;
-        uint64_t pe                      : 1;
-        uint64_t fe                      : 1;
-        uint64_t bi                      : 1;
-        uint64_t thre                    : 1;
-        uint64_t temt                    : 1;
-        uint64_t ferr                    : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_lsr_s          cn52xx;
-    struct cvmx_mio_uart2_lsr_s          cn52xxp1;
-} cvmx_mio_uart2_lsr_t;
-
-
-/**
- * cvmx_mio_uart2_mcr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_mcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t afce                    : 1;       /**< Auto Flow Control Enable bit */
-        uint64_t loop                    : 1;       /**< Loopback bit */
-        uint64_t out2                    : 1;       /**< OUT2 output bit */
-        uint64_t out1                    : 1;       /**< OUT1 output bit */
-        uint64_t rts                     : 1;       /**< Request To Send output bit */
-        uint64_t dtr                     : 1;       /**< Data Terminal Ready output bit */
-#else
-        uint64_t dtr                     : 1;
-        uint64_t rts                     : 1;
-        uint64_t out1                    : 1;
-        uint64_t out2                    : 1;
-        uint64_t loop                    : 1;
-        uint64_t afce                    : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_mio_uart2_mcr_s          cn52xx;
-    struct cvmx_mio_uart2_mcr_s          cn52xxp1;
-} cvmx_mio_uart2_mcr_t;
-
-
-/**
- * cvmx_mio_uart2_msr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_msr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t dcd                     : 1;       /**< Data Carrier Detect input bit */
-        uint64_t ri                      : 1;       /**< Ring Indicator input bit */
-        uint64_t dsr                     : 1;       /**< Data Set Ready input bit */
-        uint64_t cts                     : 1;       /**< Clear To Send input bit */
-        uint64_t ddcd                    : 1;       /**< Delta Data Carrier Detect bit */
-        uint64_t teri                    : 1;       /**< Trailing Edge of Ring Indicator bit */
-        uint64_t ddsr                    : 1;       /**< Delta Data Set Ready bit */
-        uint64_t dcts                    : 1;       /**< Delta Clear To Send bit */
-#else
-        uint64_t dcts                    : 1;
-        uint64_t ddsr                    : 1;
-        uint64_t teri                    : 1;
-        uint64_t ddcd                    : 1;
-        uint64_t cts                     : 1;
-        uint64_t dsr                     : 1;
-        uint64_t ri                      : 1;
-        uint64_t dcd                     : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_msr_s          cn52xx;
-    struct cvmx_mio_uart2_msr_s          cn52xxp1;
-} cvmx_mio_uart2_msr_t;
-
-
-/**
- * cvmx_mio_uart2_rbr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_rbr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rbr                     : 8;       /**< Receive Buffer Register */
-#else
-        uint64_t rbr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_rbr_s          cn52xx;
-    struct cvmx_mio_uart2_rbr_s          cn52xxp1;
-} cvmx_mio_uart2_rbr_t;
-
-
-/**
- * cvmx_mio_uart2_rfl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_rfl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t rfl                     : 7;       /**< Receive FIFO Level Register */
-#else
-        uint64_t rfl                     : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mio_uart2_rfl_s          cn52xx;
-    struct cvmx_mio_uart2_rfl_s          cn52xxp1;
-} cvmx_mio_uart2_rfl_t;
-
-
-/**
- * cvmx_mio_uart2_rfw
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_rfw_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t rffe                    : 1;       /**< Receive FIFO Framing Error */
-        uint64_t rfpe                    : 1;       /**< Receive FIFO Parity Error */
-        uint64_t rfwd                    : 8;       /**< Receive FIFO Write Data */
-#else
-        uint64_t rfwd                    : 8;
-        uint64_t rfpe                    : 1;
-        uint64_t rffe                    : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_mio_uart2_rfw_s          cn52xx;
-    struct cvmx_mio_uart2_rfw_s          cn52xxp1;
-} cvmx_mio_uart2_rfw_t;
-
-
-/**
- * cvmx_mio_uart2_sbcr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_sbcr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t sbcr                    : 1;       /**< Shadow Break Control */
-#else
-        uint64_t sbcr                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uart2_sbcr_s         cn52xx;
-    struct cvmx_mio_uart2_sbcr_s         cn52xxp1;
-} cvmx_mio_uart2_sbcr_t;
-
-
-/**
- * cvmx_mio_uart2_scr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_scr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t scr                     : 8;       /**< Scratchpad Register */
-#else
-        uint64_t scr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_scr_s          cn52xx;
-    struct cvmx_mio_uart2_scr_s          cn52xxp1;
-} cvmx_mio_uart2_scr_t;
-
-
-/**
- * cvmx_mio_uart2_sfe
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_sfe_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t sfe                     : 1;       /**< Shadow FIFO Enable */
-#else
-        uint64_t sfe                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uart2_sfe_s          cn52xx;
-    struct cvmx_mio_uart2_sfe_s          cn52xxp1;
-} cvmx_mio_uart2_sfe_t;
-
-
-/**
- * cvmx_mio_uart2_srr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_srr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t stfr                    : 1;       /**< Shadow TX FIFO Reset */
-        uint64_t srfr                    : 1;       /**< Shadow RX FIFO Reset */
-        uint64_t usr                     : 1;       /**< UART Soft Reset */
-#else
-        uint64_t usr                     : 1;
-        uint64_t srfr                    : 1;
-        uint64_t stfr                    : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_mio_uart2_srr_s          cn52xx;
-    struct cvmx_mio_uart2_srr_s          cn52xxp1;
-} cvmx_mio_uart2_srr_t;
-
-
-/**
- * cvmx_mio_uart2_srt
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_srt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t srt                     : 2;       /**< Shadow RX Trigger */
-#else
-        uint64_t srt                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_uart2_srt_s          cn52xx;
-    struct cvmx_mio_uart2_srt_s          cn52xxp1;
-} cvmx_mio_uart2_srt_t;
-
-
-/**
- * cvmx_mio_uart2_srts
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_srts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t srts                    : 1;       /**< Shadow Request To Send */
-#else
-        uint64_t srts                    : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_mio_uart2_srts_s         cn52xx;
-    struct cvmx_mio_uart2_srts_s         cn52xxp1;
-} cvmx_mio_uart2_srts_t;
-
-
-/**
- * cvmx_mio_uart2_stt
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_stt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t stt                     : 2;       /**< Shadow TX Trigger */
-#else
-        uint64_t stt                     : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_mio_uart2_stt_s          cn52xx;
-    struct cvmx_mio_uart2_stt_s          cn52xxp1;
-} cvmx_mio_uart2_stt_t;
-
-
-/**
- * cvmx_mio_uart2_tfl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_tfl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t tfl                     : 7;       /**< Transmit FIFO Level Register */
-#else
-        uint64_t tfl                     : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mio_uart2_tfl_s          cn52xx;
-    struct cvmx_mio_uart2_tfl_s          cn52xxp1;
-} cvmx_mio_uart2_tfl_t;
-
-
-/**
- * cvmx_mio_uart2_tfr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_tfr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t tfr                     : 8;       /**< Transmit FIFO Read Register */
-#else
-        uint64_t tfr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_tfr_s          cn52xx;
-    struct cvmx_mio_uart2_tfr_s          cn52xxp1;
-} cvmx_mio_uart2_tfr_t;
-
-
-/**
- * cvmx_mio_uart2_thr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_thr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t thr                     : 8;       /**< Transmit Holding Register */
-#else
-        uint64_t thr                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mio_uart2_thr_s          cn52xx;
-    struct cvmx_mio_uart2_thr_s          cn52xxp1;
-} cvmx_mio_uart2_thr_t;
-
-
-/**
- * cvmx_mio_uart2_usr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mio_uart2_usr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t rff                     : 1;       /**< RX FIFO Full */
-        uint64_t rfne                    : 1;       /**< RX FIFO Not Empty */
-        uint64_t tfe                     : 1;       /**< TX FIFO Empty */
-        uint64_t tfnf                    : 1;       /**< TX FIFO Not Full */
-        uint64_t busy                    : 1;       /**< Busy bit (always 0 in PASS3) */
-#else
-        uint64_t busy                    : 1;
-        uint64_t tfnf                    : 1;
-        uint64_t tfe                     : 1;
-        uint64_t rfne                    : 1;
-        uint64_t rff                     : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_mio_uart2_usr_s          cn52xx;
-    struct cvmx_mio_uart2_usr_s          cn52xxp1;
-} cvmx_mio_uart2_usr_t;
-
-
-/**
- * cvmx_mix#_bist
- *
- * MIX_BIST = MIX BIST Register
- * 
- * Description:
- *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_bist_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t mrqdat                  : 1;       /**< Bist Results for NBR CSR RdReq RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t ipfdat                  : 1;       /**< Bist Results for MIX Inbound Packet RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t irfdat                  : 1;       /**< Bist Results for MIX I-Ring Entry RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t orfdat                  : 1;       /**< Bist Results for MIX O-Ring Entry RAM
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t orfdat                  : 1;
-        uint64_t irfdat                  : 1;
-        uint64_t ipfdat                  : 1;
-        uint64_t mrqdat                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_mixx_bist_s              cn52xx;
-    struct cvmx_mixx_bist_s              cn52xxp1;
-    struct cvmx_mixx_bist_s              cn56xx;
-    struct cvmx_mixx_bist_s              cn56xxp1;
-} cvmx_mixx_bist_t;
-
-
-/**
- * cvmx_mix#_ctl
- *
- * MIX_CTL = MIX Control Register
- * 
- * Description:
- *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t crc_strip               : 1;       /**< HW CRC Strip Enable
-                                                         When enabled, the last 4 bytes(CRC) of the ingress packet
-                                                         are not included in cumulative packet byte length.
-                                                         In other words, the cumulative LEN field for all
-                                                         I-Ring Buffer Entries associated with a given ingress
-                                                         packet will be 4 bytes less (so that the final 4B HW CRC
-                                                         packet data is not processed by software). */
-        uint64_t busy                    : 1;       /**< MIX Busy Status bit
-                                                         MIX will assert busy status any time there are:
-                                                           1) L2/DRAM reads in-flight (NCB-arb to read
-                                                              response)
-                                                           2) L2/DRAM writes in-flight (NCB-arb to write
-                                                              data is sent.
-                                                           3) L2/DRAM write commits in-flight (NCB-arb to write
-                                                              commit response).
-                                                         NOTE: After MIX_CTL[EN]=0, the MIX will eventually
-                                                         complete any "inflight" transactions, at which point the
-                                                         BUSY will de-assert. */
-        uint64_t en                      : 1;       /**< MIX Enable bit
-                                                         When EN=0, MIX will no longer arbitrate for
-                                                         any new L2/DRAM read/write requests on the NCB Bus.
-                                                         MIX will complete any requests that are currently
-                                                         pended for the NCB Bus. */
-        uint64_t reset                   : 1;       /**< MIX Soft Reset
-                                                         When SW writes a '1' to MIX_CTL[RESET], the
-                                                         MIX logic will be soft reset.
-                                                         NOTE: The MIX-AGL RSL-CSR accesses are not effected
-                                                         by soft reset (to allow RSL accesses during soft reset).
-                                                         NOTE: The MIX-MIX NCB-direct CSR accesses are not effected
-                                                         by soft reset (to allow RSL accesses during soft reset).
-                                                         NOTE: Writing '1' will create a "64 eclk" soft reset
-                                                         pulse chain used by both MIX/AGL subcomponents to
-                                                         soft reset the MIX/AGL. SW should avoid sending any MIX/AGL
-                                                         CSR R/Ws until after this 64 eclk reset window has
-                                                         expired (unpredictable results).
-                                                         NOTE: RESET is intentionally 'read as zero'.
-                                                         The intended "soft reset" sequence is:
-                                                            1) Write MIX_CTL[EN]=0
-                                                               [To prevent any NEW transactions from being started]
-                                                            2) Wait for MIX_CTL[BUSY]=0
-                                                               [To indicate that all inflight transactions have
-                                                                completed]
-                                                            3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
-                                                               and wait for the result.
-                                                               This will generate the soft-reset pulse chain that will
-                                                               reset MIX/AGL (except logic to gain access to CSRs).
-                                                            4) Re-Initialize the MIX/AGL just as would be done
-                                                               for a hard reset. */
-        uint64_t lendian                 : 1;       /**< Packet Little Endian Mode
-                                                         (0: Big Endian Mode/1: Little Endian Mode)
-                                                         When the mode is set, MIX will byte-swap packet data
-                                                         loads/stores at the MIX/NCB boundary. */
-        uint64_t nbtarb                  : 1;       /**< MIX CB-Request Arbitration Mode.
-                                                         When set to zero, the arbiter is fixed priority with
-                                                         the following priority scheme:
-                                                             Highest Priority: I-Ring Packet Write Request
-                                                                               O-Ring Packet Read Request
-                                                                               I-Ring Entry Write Request
-                                                                               I-Ring Entry Read Request
-                                                                               O-Ring Entry Read Request
-                                                         When set to one, the arbiter is round robin. */
-        uint64_t mrq_hwm                 : 2;       /**< MIX CB-Request FIFO Programmable High Water Mark.
-                                                         The MRQ contains 16 CB-Requests which are CSR Rd/Wr
-                                                         Requests. If the MRQ backs up with "HWM" entries,
-                                                         then new CB-Requests are 'stalled'.
-                                                            [0]: HWM = 16
-                                                            [1]: HWM = 15
-                                                            [2]: HWM = 14
-                                                            [3]: HWM = 13
-                                                         NOTE: This must only be written at power-on/boot time. */
-#else
-        uint64_t mrq_hwm                 : 2;
-        uint64_t nbtarb                  : 1;
-        uint64_t lendian                 : 1;
-        uint64_t reset                   : 1;
-        uint64_t en                      : 1;
-        uint64_t busy                    : 1;
-        uint64_t crc_strip               : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mixx_ctl_s               cn52xx;
-    struct cvmx_mixx_ctl_s               cn52xxp1;
-    struct cvmx_mixx_ctl_s               cn56xx;
-    struct cvmx_mixx_ctl_s               cn56xxp1;
-} cvmx_mixx_ctl_t;
-
-
-/**
- * cvmx_mix#_intena
- *
- * MIX_INTENA = MIX Local Interrupt Enable Mask Register
- * 
- * Description:
- *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_intena_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t orunena                 : 1;       /**< ORCNT UnderFlow Detected
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an ORCNT underflow condition
-                                                         MIX_ISR[ORUN]. */
-        uint64_t irunena                 : 1;       /**< IRCNT UnderFlow Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an IRCNT underflow condition
-                                                         MIX_ISR[IRUN]. */
-        uint64_t data_drpena             : 1;       /**< Data was dropped due to RX FIFO full Interrupt
-                                                         enable. If both the global interrupt mask bits
-                                                         (CIU_INTx_EN*[MII]) and the local interrupt mask
-                                                         bit(DATA_DRPENA) is set, than an interrupt is
-                                                         reported for this event. */
-        uint64_t ithena                  : 1;       /**< Inbound Ring Threshold Exceeded Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an Inbound Ring Threshold
-                                                         Exceeded event(IRTHRESH). */
-        uint64_t othena                  : 1;       /**< Outbound Ring Threshold Exceeded Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an Outbound Ring Threshold
-                                                         Exceeded event(ORTHRESH). */
-        uint64_t ivfena                  : 1;       /**< Inbound DoorBell(IDBELL) Overflow Detected
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an Inbound Doorbell Overflow
-                                                         event(IDBOVF). */
-        uint64_t ovfena                  : 1;       /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and this local interrupt mask bit is set, than an
-                                                         interrupt is reported for an Outbound Doorbell Overflow
-                                                         event(ODBOVF). */
-#else
-        uint64_t ovfena                  : 1;
-        uint64_t ivfena                  : 1;
-        uint64_t othena                  : 1;
-        uint64_t ithena                  : 1;
-        uint64_t data_drpena             : 1;
-        uint64_t irunena                 : 1;
-        uint64_t orunena                 : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mixx_intena_s            cn52xx;
-    struct cvmx_mixx_intena_s            cn52xxp1;
-    struct cvmx_mixx_intena_s            cn56xx;
-    struct cvmx_mixx_intena_s            cn56xxp1;
-} cvmx_mixx_intena_t;
-
-
-/**
- * cvmx_mix#_ircnt
- *
- * MIX_IRCNT = MIX I-Ring Pending Packet Counter
- * 
- * Description:
- *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_ircnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t ircnt                   : 20;      /**< Pending \# of I-Ring Packets.
-                                                         Whenever HW writes a completion code of Done, Trunc,
-                                                         CRCErr or Err, it increments the IRCNT (to indicate
-                                                         to SW the \# of pending Input packets in system memory).
-                                                         NOTE: The HW guarantees that the completion code write
-                                                         is always visible in system memory BEFORE it increments
-                                                         the IRCNT.
-                                                         Reads of IRCNT return the current inbound packet count.
-                                                         Writes of IRCNT decrement the count by the value
-                                                         written.
-                                                         This register is used to generate interrupts to alert
-                                                         SW of pending inbound MIX packets in system memory.
-                                                         NOTE: In the case of inbound packets that span multiple
-                                                         I-Ring entries, SW must keep track of the \# of I-Ring Entries
-                                                         associated with a given inbound packet to reclaim the
-                                                         proper \# of I-Ring Entries for re-use. */
-#else
-        uint64_t ircnt                   : 20;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_mixx_ircnt_s             cn52xx;
-    struct cvmx_mixx_ircnt_s             cn52xxp1;
-    struct cvmx_mixx_ircnt_s             cn56xx;
-    struct cvmx_mixx_ircnt_s             cn56xxp1;
-} cvmx_mixx_ircnt_t;
-
-
-/**
- * cvmx_mix#_irhwm
- *
- * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register
- * 
- * Description:
- *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_irhwm_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t ibplwm                  : 20;      /**< I-Ring BackPressure Low Water Mark Threshold.
-                                                         When the \#of available I-Ring Entries (IDBELL)
-                                                         is less than IBPLWM, the AGL-MAC will:
-                                                           a) In full-duplex mode: send periodic PAUSE packets.
-                                                           b) In half-duplex mode: Force collisions.
-                                                         This programmable mechanism is provided as a means
-                                                         to backpressure input traffic 'early' enough (so
-                                                         that packets are not 'dropped' by OCTEON). */
-        uint64_t irhwm                   : 20;      /**< I-Ring Entry High Water Mark Threshold.
-                                                         Used to determine when the \# of Inbound packets
-                                                         in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
-                                                         threshold.
-                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
-                                                         interrupt enable bits is zero and must be enabled
-                                                         to allow interrupts to be reported. */
-#else
-        uint64_t irhwm                   : 20;
-        uint64_t ibplwm                  : 20;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_mixx_irhwm_s             cn52xx;
-    struct cvmx_mixx_irhwm_s             cn52xxp1;
-    struct cvmx_mixx_irhwm_s             cn56xx;
-    struct cvmx_mixx_irhwm_s             cn56xxp1;
-} cvmx_mixx_irhwm_t;
-
-
-/**
- * cvmx_mix#_iring1
- *
- * MIX_IRING1 = MIX Inbound Ring Register \#1
- * 
- * Description:
- *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_iring1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t isize                   : 20;      /**< Represents the Inbound Ring Buffer's Size(in 8B
-                                                         words). The ring can be as large as 1M entries.
-                                                         NOTE: This CSR MUST BE setup written by SW poweron
-                                                         (when IDBELL/IRCNT=0). */
-        uint64_t reserved_36_39          : 4;
-        uint64_t ibase                   : 33;      /**< Represents the 8B-aligned base address of the first
-                                                         Inbound Ring entry in system memory.
-                                                         NOTE: SW MUST ONLY write to this register during
-                                                         power-on/boot code. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t ibase                   : 33;
-        uint64_t reserved_36_39          : 4;
-        uint64_t isize                   : 20;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_mixx_iring1_s            cn52xx;
-    struct cvmx_mixx_iring1_s            cn52xxp1;
-    struct cvmx_mixx_iring1_s            cn56xx;
-    struct cvmx_mixx_iring1_s            cn56xxp1;
-} cvmx_mixx_iring1_t;
-
-
-/**
- * cvmx_mix#_iring2
- *
- * MIX_IRING2 = MIX Inbound Ring Register \#2
- * 
- * Description:
- *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_iring2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_52_63          : 12;
-        uint64_t itlptr                  : 20;      /**< The Inbound Ring Tail Pointer selects the I-Ring
-                                                         Entry that the HW will process next. After the HW
-                                                         completes receiving an inbound packet, it increments
-                                                         the I-Ring Tail Pointer. [NOTE: The I-Ring Tail
-                                                         Pointer HW increment is always modulo ISIZE.
-                                                         NOTE: This field is 'read-only' to SW. */
-        uint64_t reserved_20_31          : 12;
-        uint64_t idbell                  : 20;      /**< Represents the cumulative total of pending
-                                                         Inbound Ring Buffer Entries. Each I-Ring
-                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
-                                                         along with a 2) a Byte Length.
-                                                         After SW inserts a new entry into the I-Ring Buffer,
-                                                         it "rings the doorbell for the inbound ring". When
-                                                         the MIX HW receives the doorbell ring, it advances
-                                                         the doorbell count for the I-Ring.
-                                                         SW must never cause the doorbell count for the
-                                                         I-Ring to exceed the size of the I-ring(ISIZE).
-                                                         A read of the CSR indicates the current doorbell
-                                                         count. */
-#else
-        uint64_t idbell                  : 20;
-        uint64_t reserved_20_31          : 12;
-        uint64_t itlptr                  : 20;
-        uint64_t reserved_52_63          : 12;
-#endif
-    } s;
-    struct cvmx_mixx_iring2_s            cn52xx;
-    struct cvmx_mixx_iring2_s            cn52xxp1;
-    struct cvmx_mixx_iring2_s            cn56xx;
-    struct cvmx_mixx_iring2_s            cn56xxp1;
-} cvmx_mixx_iring2_t;
-
-
-/**
- * cvmx_mix#_isr
- *
- * MIX_ISR = MIX Interrupt/Status Register
- * 
- * Description:
- *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_isr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t orun                    : 1;       /**< ORCNT UnderFlow Detected
-                                                         If SW writes a larger value than what is currently
-                                                         in the MIX_ORCNT[ORCNT], then HW will report the
-                                                         underflow condition.
-                                                         NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
-                                                         NOTE: If an ORUN underflow condition is detected,
-                                                         the integrity of the MIX/AGL HW state has
-                                                         been compromised. To recover, SW must issue a
-                                                         software reset sequence (see: MIX_CTL[RESET] */
-        uint64_t irun                    : 1;       /**< IRCNT UnderFlow Detected
-                                                         If SW writes a larger value than what is currently
-                                                         in the MIX_IRCNT[IRCNT], then HW will report the
-                                                         underflow condition.
-                                                         NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
-                                                         NOTE: If an IRUN underflow condition is detected,
-                                                         the integrity of the MIX/AGL HW state has
-                                                         been compromised. To recover, SW must issue a
-                                                         software reset sequence (see: MIX_CTL[RESET] */
-        uint64_t data_drp                : 1;       /**< Data was dropped due to RX FIFO full
-                                                         If this does occur, the DATA_DRP is set and the
-                                                         CIU_INTx_SUM0,4[MII] bits are set.
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and the local interrupt mask bit(DATA_DRPENA) is set, than an
-                                                         interrupt is reported for this event. */
-        uint64_t irthresh                : 1;       /**< Inbound Ring Packet Threshold Exceeded
-                                                         When the pending \#inbound packets in system
-                                                         memory(IRCNT) has exceeded a programmable threshold
-                                                         (IRHWM), then this bit is set. If this does occur,
-                                                         the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
-                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and the local interrupt mask bit(ITHENA) is set, than an
-                                                         interrupt is reported for this event. */
-        uint64_t orthresh                : 1;       /**< Outbound Ring Packet Threshold Exceeded
-                                                         When the pending \#outbound packets in system
-                                                         memory(ORCNT) has exceeded a programmable threshold
-                                                         (ORHWM), then this bit is set. If this does occur,
-                                                         the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
-                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and the local interrupt mask bit(OTHENA) is set, than an
-                                                         interrupt is reported for this event. */
-        uint64_t idblovf                 : 1;       /**< Inbound DoorBell(IDBELL) Overflow Detected
-                                                         If SW attempts to write to the MIX_IRING2[IDBELL]
-                                                         with a value greater than the remaining \#of
-                                                         I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
-                                                         the following occurs:
-                                                         1) The  MIX_IRING2[IDBELL] write is IGNORED
-                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
-                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and the local interrupt mask bit(IVFENA) is set, than an
-                                                         interrupt is reported for this event.
-                                                         SW should keep track of the \#I-Ring Entries in use
-                                                         (ie: cumulative \# of IDBELL writes),  and ensure that
-                                                         future IDBELL writes don't exceed the size of the
-                                                         I-Ring Buffer (MIX_IRING2[ISIZE]).
-                                                         SW must reclaim I-Ring Entries by keeping track of the
-                                                         \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
-                                                         NOTE: The MIX_IRCNT[IRCNT] register represents the
-                                                         total \#packets(not IRing Entries) and SW must further
-                                                         keep track of the \# of I-Ring Entries associated with
-                                                         each packet as they are processed.
-                                                         NOTE: There is no recovery from an IDBLOVF Interrupt.
-                                                         If it occurs, it's an indication that SW has
-                                                         overwritten the I-Ring buffer, and the only recourse
-                                                         is a HW reset. */
-        uint64_t odblovf                 : 1;       /**< Outbound DoorBell(ODBELL) Overflow Detected
-                                                         If SW attempts to write to the MIX_ORING2[ODBELL]
-                                                         with a value greater than the remaining \#of
-                                                         O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
-                                                         the following occurs:
-                                                         1) The  MIX_ORING2[ODBELL] write is IGNORED
-                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
-                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
-                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
-                                                         and the local interrupt mask bit(OVFENA) is set, than an
-                                                         interrupt is reported for this event.
-                                                         SW should keep track of the \#I-Ring Entries in use
-                                                         (ie: cumulative \# of ODBELL writes),  and ensure that
-                                                         future ODBELL writes don't exceed the size of the
-                                                         O-Ring Buffer (MIX_ORING2[OSIZE]).
-                                                         SW must reclaim O-Ring Entries by writing to the
-                                                         MIX_ORCNT[ORCNT]. .
-                                                         NOTE: There is no recovery from an ODBLOVF Interrupt.
-                                                         If it occurs, it's an indication that SW has
-                                                         overwritten the O-Ring buffer, and the only recourse
-                                                         is a HW reset. */
-#else
-        uint64_t odblovf                 : 1;
-        uint64_t idblovf                 : 1;
-        uint64_t orthresh                : 1;
-        uint64_t irthresh                : 1;
-        uint64_t data_drp                : 1;
-        uint64_t irun                    : 1;
-        uint64_t orun                    : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_mixx_isr_s               cn52xx;
-    struct cvmx_mixx_isr_s               cn52xxp1;
-    struct cvmx_mixx_isr_s               cn56xx;
-    struct cvmx_mixx_isr_s               cn56xxp1;
-} cvmx_mixx_isr_t;
-
-
-/**
- * cvmx_mix#_orcnt
- *
- * MIX_ORCNT = MIX O-Ring Packets Sent Counter
- * 
- * Description:
- *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_orcnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t orcnt                   : 20;      /**< Pending \# of O-Ring Packets.
-                                                         Whenever HW removes a packet from the O-Ring, it
-                                                         increments the ORCNT (to indicate to SW the \# of
-                                                         Output packets in system memory that can be reclaimed).
-                                                         Reads of ORCNT return the current count.
-                                                         Writes of ORCNT decrement the count by the value
-                                                         written.
-                                                         This register is used to generate interrupts to alert
-                                                         SW of pending outbound MIX packets that have been
-                                                         removed from system memory. (see MIX_ISR[ORTHRESH]
-                                                         description for more details).
-                                                         NOTE: For outbound packets, the \# of O-Ring Packets
-                                                         is equal to the \# of O-Ring Entries. */
-#else
-        uint64_t orcnt                   : 20;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_mixx_orcnt_s             cn52xx;
-    struct cvmx_mixx_orcnt_s             cn52xxp1;
-    struct cvmx_mixx_orcnt_s             cn56xx;
-    struct cvmx_mixx_orcnt_s             cn56xxp1;
-} cvmx_mixx_orcnt_t;
-
-
-/**
- * cvmx_mix#_orhwm
- *
- * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register
- * 
- * Description:
- *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_orhwm_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t orhwm                   : 20;      /**< O-Ring Entry High Water Mark Threshold.
-                                                         Used to determine when the \# of Outbound packets
-                                                         in system memory that can be reclaimed
-                                                         (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
-                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
-                                                         interrupt enable bits is zero and must be enabled
-                                                         to allow interrupts to be reported. */
-#else
-        uint64_t orhwm                   : 20;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_mixx_orhwm_s             cn52xx;
-    struct cvmx_mixx_orhwm_s             cn52xxp1;
-    struct cvmx_mixx_orhwm_s             cn56xx;
-    struct cvmx_mixx_orhwm_s             cn56xxp1;
-} cvmx_mixx_orhwm_t;
-
-
-/**
- * cvmx_mix#_oring1
- *
- * MIX_ORING1 = MIX Outbound Ring Register \#1
- * 
- * Description:
- *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_oring1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t osize                   : 20;      /**< Represents the Outbound Ring Buffer's Size(in 8B
-                                                         words). The ring can be as large as 1M entries.
-                                                         NOTE: This CSR MUST BE setup written by SW poweron
-                                                         (when ODBELL/ORCNT=0). */
-        uint64_t reserved_36_39          : 4;
-        uint64_t obase                   : 33;      /**< Represents the 8B-aligned base address of the first
-                                                         Outbound Ring(O-Ring) Entry in system memory.
-                                                         NOTE: SW MUST ONLY write to this register during
-                                                         power-on/boot code. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t obase                   : 33;
-        uint64_t reserved_36_39          : 4;
-        uint64_t osize                   : 20;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_mixx_oring1_s            cn52xx;
-    struct cvmx_mixx_oring1_s            cn52xxp1;
-    struct cvmx_mixx_oring1_s            cn56xx;
-    struct cvmx_mixx_oring1_s            cn56xxp1;
-} cvmx_mixx_oring1_t;
-
-
-/**
- * cvmx_mix#_oring2
- *
- * MIX_ORING2 = MIX Outbound Ring Register \#2
- * 
- * Description:
- *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
- *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_oring2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_52_63          : 12;
-        uint64_t otlptr                  : 20;      /**< The Outbound Ring Tail Pointer selects the O-Ring
-                                                         Entry that the HW will process next. After the HW
-                                                         completes sending an outbound packet, it increments
-                                                         the O-Ring Tail Pointer. [NOTE: The O-Ring Tail
-                                                         Pointer HW increment is always modulo
-                                                         MIX_ORING2[OSIZE].
-                                                         NOTE: This field is 'read-only' to SW. */
-        uint64_t reserved_20_31          : 12;
-        uint64_t odbell                  : 20;      /**< Represents the cumulative total of pending
-                                                         Outbound Ring(O-Ring) Buffer Entries. Each O-Ring
-                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
-                                                         along with a 2) a Byte Length.
-                                                         After SW inserts new entries into the O-Ring Buffer,
-                                                         it "rings the doorbell with the count of the newly
-                                                         inserted entries". When the MIX HW receives the
-                                                         doorbell ring, it increments the current doorbell
-                                                         count by the CSR write value.
-                                                         SW must never cause the doorbell count for the
-                                                         O-Ring to exceed the size of the ring(OSIZE).
-                                                         A read of the CSR indicates the current doorbell
-                                                         count. */
-#else
-        uint64_t odbell                  : 20;
-        uint64_t reserved_20_31          : 12;
-        uint64_t otlptr                  : 20;
-        uint64_t reserved_52_63          : 12;
-#endif
-    } s;
-    struct cvmx_mixx_oring2_s            cn52xx;
-    struct cvmx_mixx_oring2_s            cn52xxp1;
-    struct cvmx_mixx_oring2_s            cn56xx;
-    struct cvmx_mixx_oring2_s            cn56xxp1;
-} cvmx_mixx_oring2_t;
-
-
-/**
- * cvmx_mix#_remcnt
- *
- * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only)
- * 
- * Description:
- *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mixx_remcnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_52_63          : 12;
-        uint64_t iremcnt                 : 20;      /**< Remaining I-Ring Buffer Count
-                                                         Reflects the \# of unused/remaining I-Ring Entries
-                                                         that HW  currently detects in the I-Ring Buffer.
-                                                         HW uses this value to detect I-Ring Doorbell overflows.
-                                                         (see: MIX_ISR[IDBLOVF])
-                                                         When SW writes the MIX_IRING1[ISIZE], the IREMCNT
-                                                         is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only
-                                                         be written at power-on, when it's known that there are
-                                                         no I-Ring Entries currently in use by HW).
-                                                         When SW writes to the IDBELL register, the IREMCNT
-                                                         is decremented by the CSR write value.
-                                                         When HW issues an IRing Write Request(onto NCB Bus),
-                                                         the IREMCNT is incremented by 1. */
-        uint64_t reserved_20_31          : 12;
-        uint64_t oremcnt                 : 20;      /**< Remaining O-Ring Buffer Count
-                                                         Reflects the \# of unused/remaining O-Ring Entries
-                                                         that HW  currently detects in the O-Ring Buffer.
-                                                         HW uses this value to detect O-Ring Doorbell overflows.
-                                                         (see: MIX_ISR[ODBLOVF])
-                                                         When SW writes the MIX_IRING1[OSIZE], the OREMCNT
-                                                         is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only
-                                                         be written at power-on, when it's known that there are
-                                                         no O-Ring Entries currently in use by HW).
-                                                         When SW writes to the ODBELL register, the OREMCNT
-                                                         is decremented by the CSR write value.
-                                                         When SW writes to MIX_[OREMCNT], the OREMCNT is decremented
-                                                         by the CSR write value. */
-#else
-        uint64_t oremcnt                 : 20;
-        uint64_t reserved_20_31          : 12;
-        uint64_t iremcnt                 : 20;
-        uint64_t reserved_52_63          : 12;
-#endif
-    } s;
-    struct cvmx_mixx_remcnt_s            cn52xx;
-    struct cvmx_mixx_remcnt_s            cn52xxp1;
-    struct cvmx_mixx_remcnt_s            cn56xx;
-    struct cvmx_mixx_remcnt_s            cn56xxp1;
-} cvmx_mixx_remcnt_t;
-
-
-/**
- * cvmx_mpi_cfg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mpi_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t clkdiv                  : 13;      /**< Fsclk = Feclk / (2 * CLKDIV)
-                                                         CLKDIV = Feclk / (2 * Fsclk) */
-        uint64_t reserved_12_15          : 4;
-        uint64_t cslate                  : 1;       /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
-                                                            1, MPI_CS assert coincident with transaction
-                                                         NOTE: only used if CSENA == 1 */
-        uint64_t tritx                   : 1;       /**< If 0, MPI_TX pin is driven when slave is not
-                                                               expected to be driving
-                                                            1, MPI_TX pin is tristated when not transmitting
-                                                         NOTE: only used when WIREOR==1 */
-        uint64_t idleclks                : 2;       /**< Guarantee IDLECLKS idle sclk cycles between
-                                                         commands. */
-        uint64_t cshi                    : 1;       /**< If 0, CS is low asserted
-                                                         1, CS is high asserted */
-        uint64_t csena                   : 1;       /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
-                                                         1, CS is driven per MPI_TX intruction */
-        uint64_t int_ena                 : 1;       /**< If 0, polling is required
-                                                         1, MPI engine interrupts X end of transaction */
-        uint64_t lsbfirst                : 1;       /**< If 0, shift MSB first
-                                                         1, shift LSB first */
-        uint64_t wireor                  : 1;       /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
-                                                               MPI_TX pin is always driven
-                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
-                                                               MPI_TX pin is tristated when not transmitting
-                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
-                                                               MPI engine */
-        uint64_t clk_cont                : 1;       /**< If 0, clock idles to value given by IDLELO after
-                                                            completion of MPI transaction
-                                                         1, clock never idles, requires CS deassertion
-                                                            assertion between commands */
-        uint64_t idlelo                  : 1;       /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
-                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
-        uint64_t enable                  : 1;       /**< If 0, all MPI pins are GPIOs
-                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
-#else
-        uint64_t enable                  : 1;
-        uint64_t idlelo                  : 1;
-        uint64_t clk_cont                : 1;
-        uint64_t wireor                  : 1;
-        uint64_t lsbfirst                : 1;
-        uint64_t int_ena                 : 1;
-        uint64_t csena                   : 1;
-        uint64_t cshi                    : 1;
-        uint64_t idleclks                : 2;
-        uint64_t tritx                   : 1;
-        uint64_t cslate                  : 1;
-        uint64_t reserved_12_15          : 4;
-        uint64_t clkdiv                  : 13;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_mpi_cfg_s                cn30xx;
-    struct cvmx_mpi_cfg_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t clkdiv                  : 13;      /**< Fsclk = Feclk / (2 * CLKDIV)
-                                                         CLKDIV = Feclk / (2 * Fsclk) */
-        uint64_t reserved_11_15          : 5;
-        uint64_t tritx                   : 1;       /**< If 0, MPI_TX pin is driven when slave is not
-                                                               expected to be driving
-                                                            1, MPI_TX pin is tristated when not transmitting
-                                                         NOTE: only used when WIREOR==1 */
-        uint64_t idleclks                : 2;       /**< Guarantee IDLECLKS idle sclk cycles between
-                                                         commands. */
-        uint64_t cshi                    : 1;       /**< If 0, CS is low asserted
-                                                         1, CS is high asserted */
-        uint64_t csena                   : 1;       /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
-                                                         1, CS is driven per MPI_TX intruction */
-        uint64_t int_ena                 : 1;       /**< If 0, polling is required
-                                                         1, MPI engine interrupts X end of transaction */
-        uint64_t lsbfirst                : 1;       /**< If 0, shift MSB first
-                                                         1, shift LSB first */
-        uint64_t wireor                  : 1;       /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
-                                                               MPI_TX pin is always driven
-                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
-                                                               MPI_TX pin is tristated when not transmitting
-                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
-                                                               MPI engine */
-        uint64_t clk_cont                : 1;       /**< If 0, clock idles to value given by IDLELO after
-                                                            completion of MPI transaction
-                                                         1, clock never idles, requires CS deassertion
-                                                            assertion between commands */
-        uint64_t idlelo                  : 1;       /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
-                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
-        uint64_t enable                  : 1;       /**< If 0, all MPI pins are GPIOs
-                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
-#else
-        uint64_t enable                  : 1;
-        uint64_t idlelo                  : 1;
-        uint64_t clk_cont                : 1;
-        uint64_t wireor                  : 1;
-        uint64_t lsbfirst                : 1;
-        uint64_t int_ena                 : 1;
-        uint64_t csena                   : 1;
-        uint64_t cshi                    : 1;
-        uint64_t idleclks                : 2;
-        uint64_t tritx                   : 1;
-        uint64_t reserved_11_15          : 5;
-        uint64_t clkdiv                  : 13;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn31xx;
-    struct cvmx_mpi_cfg_s                cn50xx;
-} cvmx_mpi_cfg_t;
-
-
-/**
- * cvmx_mpi_dat#
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mpi_datx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t data                    : 8;       /**< Data to transmit/received */
-#else
-        uint64_t data                    : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_mpi_datx_s               cn30xx;
-    struct cvmx_mpi_datx_s               cn31xx;
-    struct cvmx_mpi_datx_s               cn50xx;
-} cvmx_mpi_datx_t;
-
-
-/**
- * cvmx_mpi_sts
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mpi_sts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t rxnum                   : 5;       /**< Number of bytes written for transaction */
-        uint64_t reserved_1_7            : 7;
-        uint64_t busy                    : 1;       /**< If 0, no MPI transaction in progress
-                                                         1, MPI engine is processing a transaction */
-#else
-        uint64_t busy                    : 1;
-        uint64_t reserved_1_7            : 7;
-        uint64_t rxnum                   : 5;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_mpi_sts_s                cn30xx;
-    struct cvmx_mpi_sts_s                cn31xx;
-    struct cvmx_mpi_sts_s                cn50xx;
-} cvmx_mpi_sts_t;
-
-
-/**
- * cvmx_mpi_tx
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_mpi_tx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t leavecs                 : 1;       /**< If 0, deassert CS after transaction is done
-                                                         1, leave CS asserted after transactrion is done */
-        uint64_t reserved_13_15          : 3;
-        uint64_t txnum                   : 5;       /**< Number of bytes to transmit */
-        uint64_t reserved_5_7            : 3;
-        uint64_t totnum                  : 5;       /**< Number of bytes to shift (transmit + receive) */
-#else
-        uint64_t totnum                  : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t txnum                   : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t leavecs                 : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_mpi_tx_s                 cn30xx;
-    struct cvmx_mpi_tx_s                 cn31xx;
-    struct cvmx_mpi_tx_s                 cn50xx;
-} cvmx_mpi_tx_t;
-
-
-/**
- * cvmx_ndf_bt_pg_info
- *
- * Notes:
- * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
- * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
- * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
- * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
- * 
- * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
- * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
- * 
- * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
- * field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_bt_pg_info_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t t_mult                  : 4;       /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
-                                                         command */
-        uint64_t adr_cyc                 : 4;       /**< # of column address cycles */
-        uint64_t size                    : 3;       /**< bytes per page in the nand device */
-#else
-        uint64_t size                    : 3;
-        uint64_t adr_cyc                 : 4;
-        uint64_t t_mult                  : 4;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_ndf_bt_pg_info_s         cn52xx;
-} cvmx_ndf_bt_pg_info_t;
-
-
-/**
- * cvmx_ndf_cmd
- *
- * Notes:
- * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
- * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
- * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
- * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t nf_cmd                  : 64;      /**< 8 Command Bytes */
-#else
-        uint64_t nf_cmd                  : 64;
-#endif
-    } s;
-    struct cvmx_ndf_cmd_s                cn52xx;
-} cvmx_ndf_cmd_t;
-
-
-/**
- * cvmx_ndf_drbell
- *
- * Notes:
- * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
- * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
- * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
- * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
- * non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
- * 
- * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
- * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
- * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
- * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
- * the last command in the sequence will be a bus release command. The execution unit will start execution of
- * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
- * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
- * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
- * CNT field by the number of the command sequences, loaded to the command fifo.
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_drbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t cnt                     : 8;       /**< Doorbell count register, 2's complement 8 bit value */
-#else
-        uint64_t cnt                     : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_ndf_drbell_s             cn52xx;
-} cvmx_ndf_drbell_t;
-
-
-/**
- * cvmx_ndf_ecc_cnt
- *
- * Notes:
- * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
- *         ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
- *         ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_ecc_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t xor_ecc                 : 24;      /**< result of XOR of ecc read bytes and ecc genarated
-                                                         bytes. The value pertains to the last 1 bit ecc err */
-        uint64_t ecc_err                 : 8;       /**< Count = \# of 1 bit errors fixed during boot
-                                                         This count saturates instead of wrapping around. */
-#else
-        uint64_t ecc_err                 : 8;
-        uint64_t xor_ecc                 : 24;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_ndf_ecc_cnt_s            cn52xx;
-} cvmx_ndf_ecc_cnt_t;
-
-
-/**
- * cvmx_ndf_int
- *
- * Notes:
- * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
- * 
- * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
- * last instruction out of the command fifo.
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t ovrf                    : 1;       /**< NDF_CMD write when fifo is full. Generally a
-                                                         fatal error. */
-        uint64_t ecc_mult                : 1;       /**< Multi bit ECC error detected during boot */
-        uint64_t ecc_1bit                : 1;       /**< Single bit ECC error detected and fixed during boot */
-        uint64_t sm_bad                  : 1;       /**< One of the state machines in a bad state */
-        uint64_t wdog                    : 1;       /**< Watch Dog timer expired during command execution */
-        uint64_t full                    : 1;       /**< Command fifo is full */
-        uint64_t empty                   : 1;       /**< Command fifo is empty */
-#else
-        uint64_t empty                   : 1;
-        uint64_t full                    : 1;
-        uint64_t wdog                    : 1;
-        uint64_t sm_bad                  : 1;
-        uint64_t ecc_1bit                : 1;
-        uint64_t ecc_mult                : 1;
-        uint64_t ovrf                    : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_ndf_int_s                cn52xx;
-} cvmx_ndf_int_t;
-
-
-/**
- * cvmx_ndf_int_en
- *
- * Notes:
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t ovrf                    : 1;       /**< Wrote to a full command fifo */
-        uint64_t ecc_mult                : 1;       /**< Multi bit ECC error detected during boot */
-        uint64_t ecc_1bit                : 1;       /**< Single bit ECC error detected and fixed during boot */
-        uint64_t sm_bad                  : 1;       /**< One of the state machines in a bad state */
-        uint64_t wdog                    : 1;       /**< Watch Dog timer expired during command execution */
-        uint64_t full                    : 1;       /**< Command fifo is full */
-        uint64_t empty                   : 1;       /**< Command fifo is empty */
-#else
-        uint64_t empty                   : 1;
-        uint64_t full                    : 1;
-        uint64_t wdog                    : 1;
-        uint64_t sm_bad                  : 1;
-        uint64_t ecc_1bit                : 1;
-        uint64_t ecc_mult                : 1;
-        uint64_t ovrf                    : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_ndf_int_en_s             cn52xx;
-} cvmx_ndf_int_en_t;
-
-
-/**
- * cvmx_ndf_misc
- *
- * Notes:
- * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
- *   the fifo size is 16 entries.
- * 
- * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
- *   represents number of eclk cycles.
- * 
- * FR_BYT  this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
- *   complete execution and exit. (fifo is 256 bytes when BT_DIS=0,  and 1536 bytes when BT_DIS=1)
- * 
- * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
- *   in response to RD_CMD bit being set to 1 by SW.
- * 
- * RD_VAL  this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
- *   to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
- * 
- * RD_CMD  this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
- *   RD_VAL bit in  this csr to see if next 8 bytes from the command fifo are available in the
- *   NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
- *   middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
- *   bit will be cleared on any NDF_CMD csr write by SW.
- * 
- * BT_DMA  this indicates to the NAND flash boot control state machine that boot dma read can begin.
- *   SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
- *   when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
- *   permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
- * 
- * BT_DIS  this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
- *   whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
- *   never be set when booting from nand flash and region zero is enabled.
- * 
- * EX_DIS  When 1, command execution stops after completing execution of all commands currently in the command
- *   fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
- *   will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
- *   is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
- * 
- * RST_FF  reset command fifo to make it empty, any command inflight is not aborted before reseting
- *   the fifo. The fifo comes up empty at the end of power on reset.
- * 
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_misc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t nbr_hwm                 : 3;       /**< Hi Water mark for NBR fifo or load/stores */
-        uint64_t wait_cnt                : 6;       /**< WAIT input filter count */
-        uint64_t fr_byt                  : 11;      /**< Number of unfilled Command fifo bytes */
-        uint64_t rd_done                 : 1;       /**< This W1C bit is set to 1 by HW when it completes
-                                                         command fifo read out, in response to RD_CMD */
-        uint64_t rd_val                  : 1;       /**< This RO bit is set to 1 by HW when it reads next 8
-                                                         bytes from Command fifo into the NDF_CMD csr
-                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
-        uint64_t rd_cmd                  : 1;       /**< When 1, HW reads out contents of the Command fifo 8
-                                                         bytes at a time into the NDF_CMD csr */
-        uint64_t bt_dma                  : 1;       /**< When set to 1, boot time dma is enabled */
-        uint64_t bt_dis                  : 1;       /**< When boot operation is over SW must set to 1
-                                                         causes boot state mchines to sleep */
-        uint64_t ex_dis                  : 1;       /**< When set to 1, suspends execution of commands at
-                                                         next command in the fifo. */
-        uint64_t rst_ff                  : 1;       /**< 1=reset command fifo to make it empty,
-                                                         0=normal operation */
-#else
-        uint64_t rst_ff                  : 1;
-        uint64_t ex_dis                  : 1;
-        uint64_t bt_dis                  : 1;
-        uint64_t bt_dma                  : 1;
-        uint64_t rd_cmd                  : 1;
-        uint64_t rd_val                  : 1;
-        uint64_t rd_done                 : 1;
-        uint64_t fr_byt                  : 11;
-        uint64_t wait_cnt                : 6;
-        uint64_t nbr_hwm                 : 3;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } s;
-    struct cvmx_ndf_misc_s               cn52xx;
-} cvmx_ndf_misc_t;
-
-
-/**
- * cvmx_ndf_st_reg
- *
- * Notes:
- * This CSR aggregates all state machines used in nand flash controller for debug.
- * Like all NDF_... registers, 64-bit operations must be used to access this register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_ndf_st_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t exe_idle                : 1;       /**< Command Execution status 1=IDLE, 0=Busy
-                                                         1 means execution of command sequence is complete
-                                                         and command fifo is empty */
-        uint64_t exe_sm                  : 4;       /**< Command Execution State machine states */
-        uint64_t bt_sm                   : 4;       /**< Boot load and Boot dma State machine states */
-        uint64_t rd_ff_bad               : 1;       /**< CMD fifo read back State machine in bad state */
-        uint64_t rd_ff                   : 2;       /**< CMD fifo read back State machine states */
-        uint64_t main_bad                : 1;       /**< Main State machine in bad state */
-        uint64_t main_sm                 : 3;       /**< Main State machine states */
-#else
-        uint64_t main_sm                 : 3;
-        uint64_t main_bad                : 1;
-        uint64_t rd_ff                   : 2;
-        uint64_t rd_ff_bad               : 1;
-        uint64_t bt_sm                   : 4;
-        uint64_t exe_sm                  : 4;
-        uint64_t exe_idle                : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_ndf_st_reg_s             cn52xx;
-} cvmx_ndf_st_reg_t;
-
-
-/**
- * cvmx_npei_bar1_index#
- *
- * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
- * 
- * General  5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
- * PktMem  10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
- * Rsvd     1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
- *                                   == NPEI_PKT_CNT_INT_ENB[PORT]
- *                                   == NPEI_PKT_TIME_INT_ENB[PORT]
- *                                   == NPEI_PKT_CNT_INT[PORT]
- *                                   == NPEI_PKT_TIME_INT[PORT]
- *                                   == NPEI_PKT_PCIE_PORT[PP]
- *                                   == NPEI_PKT_SLIST_ROR[ROR]
- *                                   == NPEI_PKT_SLIST_ROR[NSR] ?
- *                                   == NPEI_PKT_SLIST_ES[ES]
- *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
- *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
- *                                   == NPEI_PKTn_CNTS[CNT]
- * NPEI_CTL_STATUS[OUTn_ENB]         == NPEI_PKT_OUT_ENB[ENB]
- * NPEI_BASE_ADDRESS_OUTPUTn[BADDR]  == NPEI_PKTn_SLIST_BADDR[ADDR]
- * NPEI_DESC_OUTPUTn[SIZE]           == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE]
- * NPEI_Pn_DBPAIR_ADDR[NADDR]        == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
- * NPEI_PKT_CREDITSn[PTR_CNT]        == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
- * NPEI_P0_PAIR_CNTS[AVAIL]          == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
- * NPEI_P0_PAIR_CNTS[FCNT]           ==
- * NPEI_PKTS_SENTn[PKT_CNT]          == NPEI_PKTn_CNTS[CNT]
- * NPEI_OUTPUT_CONTROL[Pn_BMODE]     == NPEI_PKT_OUT_BMODE[BMODE]
- * NPEI_PKT_CREDITSn[PKT_CNT]        == NPEI_PKTn_CNTS[CNT]
- * NPEI_BUFF_SIZE_OUTPUTn[BSIZE]     == NPEI_PKT_SLIST_ID_SIZE[BSIZE]
- * NPEI_BUFF_SIZE_OUTPUTn[ISIZE]     == NPEI_PKT_SLIST_ID_SIZE[ISIZE]
- * NPEI_OUTPUT_CONTROL[On_CSRM]      == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT]
- * NPEI_OUTPUT_CONTROL[On_ES]        == NPEI_PKT_DATA_OUT_ES[ES]
- * NPEI_OUTPUT_CONTROL[On_NS]        == NPEI_PKT_DATA_OUT_NS[NSR] ?
- * NPEI_OUTPUT_CONTROL[On_RO]        == NPEI_PKT_DATA_OUT_ROR[ROR]
- * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT]  == NPEI_PKT_INT_LEVELS[CNT]
- * NPEI_PKTS_SENT_TIMEn[PKT_TIME]    == NPEI_PKT_INT_LEVELS[TIME]
- * NPEI_OUTPUT_CONTROL[IPTR_On]      == NPEI_PKT_IPTR[IPTR]
- * NPEI_PCIE_PORT_OUTPUT[]           == NPEI_PKT_PCIE_PORT[PP]
- * 
- *                  NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register
- * 
- * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
- * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16
- * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_npei_bar1_indexx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_18_31          : 14;
-        uint32_t addr_idx                : 14;      /**< Address bits [35:22] sent to L2C */
-        uint32_t ca                      : 1;       /**< Set '1' when access is not to be cached in L2. */
-        uint32_t end_swp                 : 2;       /**< Endian Swap Mode */
-        uint32_t addr_v                  : 1;       /**< Set '1' when the selected address range is valid. */
-#else
-        uint32_t addr_v                  : 1;
-        uint32_t end_swp                 : 2;
-        uint32_t ca                      : 1;
-        uint32_t addr_idx                : 14;
-        uint32_t reserved_18_31          : 14;
-#endif
-    } s;
-    struct cvmx_npei_bar1_indexx_s       cn52xx;
-    struct cvmx_npei_bar1_indexx_s       cn52xxp1;
-    struct cvmx_npei_bar1_indexx_s       cn56xx;
-    struct cvmx_npei_bar1_indexx_s       cn56xxp1;
-} cvmx_npei_bar1_indexx_t;
-
-
-/**
- * cvmx_npei_bist_status
- *
- * NPEI_BIST_STATUS = NPI's BIST Status Register
- * 
- * Results from BIST runs of NPEI's memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pkt_rdf                 : 1;       /**< BIST Status for PKT Read FIFO */
-        uint64_t reserved_60_62          : 3;
-        uint64_t pcr_gim                 : 1;       /**< BIST Status for PKT Gather Instr MEM */
-        uint64_t pkt_pif                 : 1;       /**< BIST Status for PKT INB FIFO */
-        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT pout_int_bstatus */
-        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT pcsr_instr_mem_bstatus */
-        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT pin_cnt_bstatus */
-        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT pcsr_in_done_bstatus */
-        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT pcsr_slist_bstatus */
-        uint64_t reserved_50_52          : 3;
-        uint64_t pkt_ind                 : 1;       /**< BIST Status for PKT Instruction Done MEM */
-        uint64_t pkt_slm                 : 1;       /**< BIST Status for PKT SList MEM */
-        uint64_t reserved_36_47          : 12;
-        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
-        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
-        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
-        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
-        uint64_t reserved_31_31          : 1;
-        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
-        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
-        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
-        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
-        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
-        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
-        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
-        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
-        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
-        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
-        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
-        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
-        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
-        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
-        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
-        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
-        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
-        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
-        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
-        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
-        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
-        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
-        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
-        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
-        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t reserved_2_2            : 1;
-        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
-        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
-#else
-        uint64_t ncb_cmd                 : 1;
-        uint64_t msi                     : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t dif3                    : 1;
-        uint64_t dif2                    : 1;
-        uint64_t dif1                    : 1;
-        uint64_t dif0                    : 1;
-        uint64_t csm1                    : 1;
-        uint64_t csm0                    : 1;
-        uint64_t p2n1_p1                 : 1;
-        uint64_t p2n1_p0                 : 1;
-        uint64_t p2n1_n                  : 1;
-        uint64_t p2n1_c1                 : 1;
-        uint64_t p2n1_c0                 : 1;
-        uint64_t p2n0_p1                 : 1;
-        uint64_t p2n0_p0                 : 1;
-        uint64_t p2n0_n                  : 1;
-        uint64_t p2n0_c1                 : 1;
-        uint64_t p2n0_c0                 : 1;
-        uint64_t p2n0_co                 : 1;
-        uint64_t p2n0_no                 : 1;
-        uint64_t p2n0_po                 : 1;
-        uint64_t p2n1_co                 : 1;
-        uint64_t p2n1_no                 : 1;
-        uint64_t p2n1_po                 : 1;
-        uint64_t cpl_p1                  : 1;
-        uint64_t cpl_p0                  : 1;
-        uint64_t n2p1_o                  : 1;
-        uint64_t n2p1_c                  : 1;
-        uint64_t n2p0_o                  : 1;
-        uint64_t n2p0_c                  : 1;
-        uint64_t reserved_31_31          : 1;
-        uint64_t d3_pst                  : 1;
-        uint64_t d2_pst                  : 1;
-        uint64_t d1_pst                  : 1;
-        uint64_t d0_pst                  : 1;
-        uint64_t reserved_36_47          : 12;
-        uint64_t pkt_slm                 : 1;
-        uint64_t pkt_ind                 : 1;
-        uint64_t reserved_50_52          : 3;
-        uint64_t pcsr_sl                 : 1;
-        uint64_t pcsr_id                 : 1;
-        uint64_t pcsr_cnt                : 1;
-        uint64_t pcsr_im                 : 1;
-        uint64_t pcsr_int                : 1;
-        uint64_t pkt_pif                 : 1;
-        uint64_t pcr_gim                 : 1;
-        uint64_t reserved_60_62          : 3;
-        uint64_t pkt_rdf                 : 1;
-#endif
-    } s;
-    struct cvmx_npei_bist_status_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pkt_rdf                 : 1;       /**< BIST Status for PKT Read FIFO */
-        uint64_t reserved_60_62          : 3;
-        uint64_t pcr_gim                 : 1;       /**< BIST Status for PKT Gather Instr MEM */
-        uint64_t pkt_pif                 : 1;       /**< BIST Status for PKT INB FIFO */
-        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT OUTB Interrupt MEM */
-        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT CSR Instr MEM */
-        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT INB Count MEM */
-        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT INB Instr Done MEM */
-        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT OUTB SLIST MEM */
-        uint64_t pkt_imem                : 1;       /**< BIST Status for PKT OUTB IFIFO */
-        uint64_t pkt_pfm                 : 1;       /**< BIST Status for PKT Front MEM */
-        uint64_t pkt_pof                 : 1;       /**< BIST Status for PKT OUTB FIFO */
-        uint64_t reserved_48_49          : 2;
-        uint64_t pkt_pop0                : 1;       /**< BIST Status for PKT OUTB Slist0 */
-        uint64_t pkt_pop1                : 1;       /**< BIST Status for PKT OUTB Slist1 */
-        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA MEM 0 */
-        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA MEM 1 */
-        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA MEM 2 */
-        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA MEM 3 */
-        uint64_t d4_mem                  : 1;       /**< BIST Status for DMA MEM 4 */
-        uint64_t ds_mem                  : 1;       /**< BIST Status for DMA  Memory */
-        uint64_t reserved_36_39          : 4;
-        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
-        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
-        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
-        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
-        uint64_t d4_pst                  : 1;       /**< BIST Status for DMA4 Pcie Store */
-        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
-        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
-        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
-        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
-        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
-        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
-        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
-        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
-        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
-        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
-        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
-        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
-        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
-        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
-        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
-        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
-        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
-        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
-        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
-        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
-        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
-        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
-        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
-        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
-        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif4                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
-        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
-#else
-        uint64_t ncb_cmd                 : 1;
-        uint64_t msi                     : 1;
-        uint64_t dif4                    : 1;
-        uint64_t dif3                    : 1;
-        uint64_t dif2                    : 1;
-        uint64_t dif1                    : 1;
-        uint64_t dif0                    : 1;
-        uint64_t csm1                    : 1;
-        uint64_t csm0                    : 1;
-        uint64_t p2n1_p1                 : 1;
-        uint64_t p2n1_p0                 : 1;
-        uint64_t p2n1_n                  : 1;
-        uint64_t p2n1_c1                 : 1;
-        uint64_t p2n1_c0                 : 1;
-        uint64_t p2n0_p1                 : 1;
-        uint64_t p2n0_p0                 : 1;
-        uint64_t p2n0_n                  : 1;
-        uint64_t p2n0_c1                 : 1;
-        uint64_t p2n0_c0                 : 1;
-        uint64_t p2n0_co                 : 1;
-        uint64_t p2n0_no                 : 1;
-        uint64_t p2n0_po                 : 1;
-        uint64_t p2n1_co                 : 1;
-        uint64_t p2n1_no                 : 1;
-        uint64_t p2n1_po                 : 1;
-        uint64_t cpl_p1                  : 1;
-        uint64_t cpl_p0                  : 1;
-        uint64_t n2p1_o                  : 1;
-        uint64_t n2p1_c                  : 1;
-        uint64_t n2p0_o                  : 1;
-        uint64_t n2p0_c                  : 1;
-        uint64_t d4_pst                  : 1;
-        uint64_t d3_pst                  : 1;
-        uint64_t d2_pst                  : 1;
-        uint64_t d1_pst                  : 1;
-        uint64_t d0_pst                  : 1;
-        uint64_t reserved_36_39          : 4;
-        uint64_t ds_mem                  : 1;
-        uint64_t d4_mem                  : 1;
-        uint64_t d3_mem                  : 1;
-        uint64_t d2_mem                  : 1;
-        uint64_t d1_mem                  : 1;
-        uint64_t d0_mem                  : 1;
-        uint64_t pkt_pop1                : 1;
-        uint64_t pkt_pop0                : 1;
-        uint64_t reserved_48_49          : 2;
-        uint64_t pkt_pof                 : 1;
-        uint64_t pkt_pfm                 : 1;
-        uint64_t pkt_imem                : 1;
-        uint64_t pcsr_sl                 : 1;
-        uint64_t pcsr_id                 : 1;
-        uint64_t pcsr_cnt                : 1;
-        uint64_t pcsr_im                 : 1;
-        uint64_t pcsr_int                : 1;
-        uint64_t pkt_pif                 : 1;
-        uint64_t pcr_gim                 : 1;
-        uint64_t reserved_60_62          : 3;
-        uint64_t pkt_rdf                 : 1;
-#endif
-    } cn52xx;
-    struct cvmx_npei_bist_status_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_46_63          : 18;
-        uint64_t d0_mem0                 : 1;       /**< BIST Status for DMA0 Memory */
-        uint64_t d1_mem1                 : 1;       /**< BIST Status for DMA1 Memory */
-        uint64_t d2_mem2                 : 1;       /**< BIST Status for DMA2 Memory */
-        uint64_t d3_mem3                 : 1;       /**< BIST Status for DMA3 Memory */
-        uint64_t dr0_mem                 : 1;       /**< BIST Status for DMA0 Store */
-        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA0 Memory */
-        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA1 Memory */
-        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA2 Memory */
-        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA3 Memory */
-        uint64_t dr1_mem                 : 1;       /**< BIST Status for DMA1 Store */
-        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
-        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
-        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
-        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
-        uint64_t dr2_mem                 : 1;       /**< BIST Status for DMA2 Store */
-        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
-        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
-        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
-        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
-        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
-        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
-        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
-        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
-        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
-        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
-        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
-        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
-        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
-        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
-        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
-        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
-        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
-        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
-        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
-        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
-        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
-        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
-        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
-        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
-        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dr3_mem                 : 1;       /**< BIST Status for DMA3 Store */
-        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
-        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
-#else
-        uint64_t ncb_cmd                 : 1;
-        uint64_t msi                     : 1;
-        uint64_t dr3_mem                 : 1;
-        uint64_t dif3                    : 1;
-        uint64_t dif2                    : 1;
-        uint64_t dif1                    : 1;
-        uint64_t dif0                    : 1;
-        uint64_t csm1                    : 1;
-        uint64_t csm0                    : 1;
-        uint64_t p2n1_p1                 : 1;
-        uint64_t p2n1_p0                 : 1;
-        uint64_t p2n1_n                  : 1;
-        uint64_t p2n1_c1                 : 1;
-        uint64_t p2n1_c0                 : 1;
-        uint64_t p2n0_p1                 : 1;
-        uint64_t p2n0_p0                 : 1;
-        uint64_t p2n0_n                  : 1;
-        uint64_t p2n0_c1                 : 1;
-        uint64_t p2n0_c0                 : 1;
-        uint64_t p2n0_co                 : 1;
-        uint64_t p2n0_no                 : 1;
-        uint64_t p2n0_po                 : 1;
-        uint64_t p2n1_co                 : 1;
-        uint64_t p2n1_no                 : 1;
-        uint64_t p2n1_po                 : 1;
-        uint64_t cpl_p1                  : 1;
-        uint64_t cpl_p0                  : 1;
-        uint64_t n2p1_o                  : 1;
-        uint64_t n2p1_c                  : 1;
-        uint64_t n2p0_o                  : 1;
-        uint64_t n2p0_c                  : 1;
-        uint64_t dr2_mem                 : 1;
-        uint64_t d3_pst                  : 1;
-        uint64_t d2_pst                  : 1;
-        uint64_t d1_pst                  : 1;
-        uint64_t d0_pst                  : 1;
-        uint64_t dr1_mem                 : 1;
-        uint64_t d3_mem                  : 1;
-        uint64_t d2_mem                  : 1;
-        uint64_t d1_mem                  : 1;
-        uint64_t d0_mem                  : 1;
-        uint64_t dr0_mem                 : 1;
-        uint64_t d3_mem3                 : 1;
-        uint64_t d2_mem2                 : 1;
-        uint64_t d1_mem1                 : 1;
-        uint64_t d0_mem0                 : 1;
-        uint64_t reserved_46_63          : 18;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_bist_status_cn52xx  cn56xx;
-    struct cvmx_npei_bist_status_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_58_63          : 6;
-        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT pout_int_bstatus */
-        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT pcsr_instr_mem_bstatus */
-        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT pin_cnt_bstatus */
-        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT pcsr_in_done_bstatus */
-        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT pcsr_slist_bstatus */
-        uint64_t pkt_pout                : 1;       /**< BIST Status for PKT OUT Count MEM */
-        uint64_t pkt_imem                : 1;       /**< BIST Status for PKT Instruction MEM */
-        uint64_t pkt_cntm                : 1;       /**< BIST Status for PKT Count MEM */
-        uint64_t pkt_ind                 : 1;       /**< BIST Status for PKT Instruction Done MEM */
-        uint64_t pkt_slm                 : 1;       /**< BIST Status for PKT SList MEM */
-        uint64_t pkt_odf                 : 1;       /**< BIST Status for PKT Output Data FIFO */
-        uint64_t pkt_oif                 : 1;       /**< BIST Status for PKT Output INFO FIFO */
-        uint64_t pkt_out                 : 1;       /**< BIST Status for PKT Output FIFO */
-        uint64_t pkt_i0                  : 1;       /**< BIST Status for PKT Instr0 */
-        uint64_t pkt_i1                  : 1;       /**< BIST Status for PKT Instr1 */
-        uint64_t pkt_s0                  : 1;       /**< BIST Status for PKT Slist0 */
-        uint64_t pkt_s1                  : 1;       /**< BIST Status for PKT Slist1 */
-        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA0 Memory */
-        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA1 Memory */
-        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA2 Memory */
-        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA3 Memory */
-        uint64_t d4_mem                  : 1;       /**< BIST Status for DMA4 Memory */
-        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
-        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
-        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
-        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
-        uint64_t d4_pst                  : 1;       /**< BIST Status for DMA4 Pcie Store */
-        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
-        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
-        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
-        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
-        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
-        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
-        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
-        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
-        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
-        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
-        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
-        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
-        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
-        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
-        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
-        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
-        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
-        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
-        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
-        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
-        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
-        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
-        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
-        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
-        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t dif4                    : 1;       /**< BIST Status for DMA Instr0 */
-        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
-        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
-#else
-        uint64_t ncb_cmd                 : 1;
-        uint64_t msi                     : 1;
-        uint64_t dif4                    : 1;
-        uint64_t dif3                    : 1;
-        uint64_t dif2                    : 1;
-        uint64_t dif1                    : 1;
-        uint64_t dif0                    : 1;
-        uint64_t csm1                    : 1;
-        uint64_t csm0                    : 1;
-        uint64_t p2n1_p1                 : 1;
-        uint64_t p2n1_p0                 : 1;
-        uint64_t p2n1_n                  : 1;
-        uint64_t p2n1_c1                 : 1;
-        uint64_t p2n1_c0                 : 1;
-        uint64_t p2n0_p1                 : 1;
-        uint64_t p2n0_p0                 : 1;
-        uint64_t p2n0_n                  : 1;
-        uint64_t p2n0_c1                 : 1;
-        uint64_t p2n0_c0                 : 1;
-        uint64_t p2n0_co                 : 1;
-        uint64_t p2n0_no                 : 1;
-        uint64_t p2n0_po                 : 1;
-        uint64_t p2n1_co                 : 1;
-        uint64_t p2n1_no                 : 1;
-        uint64_t p2n1_po                 : 1;
-        uint64_t cpl_p1                  : 1;
-        uint64_t cpl_p0                  : 1;
-        uint64_t n2p1_o                  : 1;
-        uint64_t n2p1_c                  : 1;
-        uint64_t n2p0_o                  : 1;
-        uint64_t n2p0_c                  : 1;
-        uint64_t d4_pst                  : 1;
-        uint64_t d3_pst                  : 1;
-        uint64_t d2_pst                  : 1;
-        uint64_t d1_pst                  : 1;
-        uint64_t d0_pst                  : 1;
-        uint64_t d4_mem                  : 1;
-        uint64_t d3_mem                  : 1;
-        uint64_t d2_mem                  : 1;
-        uint64_t d1_mem                  : 1;
-        uint64_t d0_mem                  : 1;
-        uint64_t pkt_s1                  : 1;
-        uint64_t pkt_s0                  : 1;
-        uint64_t pkt_i1                  : 1;
-        uint64_t pkt_i0                  : 1;
-        uint64_t pkt_out                 : 1;
-        uint64_t pkt_oif                 : 1;
-        uint64_t pkt_odf                 : 1;
-        uint64_t pkt_slm                 : 1;
-        uint64_t pkt_ind                 : 1;
-        uint64_t pkt_cntm                : 1;
-        uint64_t pkt_imem                : 1;
-        uint64_t pkt_pout                : 1;
-        uint64_t pcsr_sl                 : 1;
-        uint64_t pcsr_id                 : 1;
-        uint64_t pcsr_cnt                : 1;
-        uint64_t pcsr_im                 : 1;
-        uint64_t pcsr_int                : 1;
-        uint64_t reserved_58_63          : 6;
-#endif
-    } cn56xxp1;
-} cvmx_npei_bist_status_t;
-
-
-/**
- * cvmx_npei_bist_status2
- *
- * NPEI_BIST_STATUS2 = NPI's BIST Status Register2
- * 
- * Results from BIST runs of NPEI's memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_bist_status2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t prd_tag                 : 1;       /**< BIST Status for DMA PCIE RD Tag MEM */
-        uint64_t prd_st0                 : 1;       /**< BIST Status for DMA PCIE RD state MEM 0 */
-        uint64_t prd_st1                 : 1;       /**< BIST Status for DMA PCIE RD state MEM 1 */
-        uint64_t prd_err                 : 1;       /**< BIST Status for DMA PCIE RD ERR state MEM */
-        uint64_t nrd_st                  : 1;       /**< BIST Status for DMA L2C RD state MEM */
-        uint64_t nwe_st                  : 1;       /**< BIST Status for DMA L2C WR state MEM */
-        uint64_t nwe_wr0                 : 1;       /**< BIST Status for DMA L2C WR MEM 0 */
-        uint64_t nwe_wr1                 : 1;       /**< BIST Status for DMA L2C WR MEM 1 */
-        uint64_t pkt_rd                  : 1;       /**< BIST Status for Inbound PKT MEM */
-        uint64_t psc_p0                  : 1;       /**< BIST Status for PSC TLP 0 MEM */
-        uint64_t psc_p1                  : 1;       /**< BIST Status for PSC TLP 1 MEM */
-        uint64_t pkt_gd                  : 1;       /**< BIST Status for PKT OUTB Gather Data FIFO */
-        uint64_t pkt_gl                  : 1;       /**< BIST Status for PKT_OUTB Gather List FIFO */
-        uint64_t pkt_blk                 : 1;       /**< BIST Status for PKT OUTB Blocked FIFO */
-#else
-        uint64_t pkt_blk                 : 1;
-        uint64_t pkt_gl                  : 1;
-        uint64_t pkt_gd                  : 1;
-        uint64_t psc_p1                  : 1;
-        uint64_t psc_p0                  : 1;
-        uint64_t pkt_rd                  : 1;
-        uint64_t nwe_wr1                 : 1;
-        uint64_t nwe_wr0                 : 1;
-        uint64_t nwe_st                  : 1;
-        uint64_t nrd_st                  : 1;
-        uint64_t prd_err                 : 1;
-        uint64_t prd_st1                 : 1;
-        uint64_t prd_st0                 : 1;
-        uint64_t prd_tag                 : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_npei_bist_status2_s      cn52xx;
-    struct cvmx_npei_bist_status2_s      cn56xx;
-} cvmx_npei_bist_status2_t;
-
-
-/**
- * cvmx_npei_ctl_port0
- *
- * NPEI_CTL_PORT0 = NPEI's Control Port 0
- * 
- * Contains control for access for Port0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_ctl_port0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t waitl_com               : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional completions
-                                                         to the L2C from the PCIe.
-                                                         Set this for more conservative behavior. Clear
-                                                         this for more aggressive, higher-performance
-                                                         behavior */
-        uint64_t intd                    : 1;       /**< When '0' Intd wire asserted. Before mapping. */
-        uint64_t intc                    : 1;       /**< When '0' Intc wire asserted. Before mapping. */
-        uint64_t intb                    : 1;       /**< When '0' Intb wire asserted. Before mapping. */
-        uint64_t inta                    : 1;       /**< When '0' Inta wire asserted. Before mapping. */
-        uint64_t intd_map                : 2;       /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t intc_map                : 2;       /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t intb_map                : 2;       /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t inta_map                : 2;       /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t ctlp_ro                 : 1;       /**< Relaxed ordering enable for Completion TLPS. */
-        uint64_t reserved_6_6            : 1;
-        uint64_t ptlp_ro                 : 1;       /**< Relaxed ordering enable for Posted TLPS. */
-        uint64_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
-                                                         clear '0' BAR2 access will cause UR responses. */
-        uint64_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
-                                                         determine the endian swap mode. */
-        uint64_t bar2_cax                : 1;       /**< Value will be XORed with pcie-address[38] to
-                                                         determine the L2 cache attribute.
-                                                         Not cached in L2 if XOR result is 1 */
-        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional stores to
-                                                         the L2C from the PCIe.
-                                                         Most applications will not notice a difference, so
-                                                         should not set this bit. Setting the bit is more
-                                                         conservative on ordering, lower performance */
-#else
-        uint64_t wait_com                : 1;
-        uint64_t bar2_cax                : 1;
-        uint64_t bar2_esx                : 2;
-        uint64_t bar2_enb                : 1;
-        uint64_t ptlp_ro                 : 1;
-        uint64_t reserved_6_6            : 1;
-        uint64_t ctlp_ro                 : 1;
-        uint64_t inta_map                : 2;
-        uint64_t intb_map                : 2;
-        uint64_t intc_map                : 2;
-        uint64_t intd_map                : 2;
-        uint64_t inta                    : 1;
-        uint64_t intb                    : 1;
-        uint64_t intc                    : 1;
-        uint64_t intd                    : 1;
-        uint64_t waitl_com               : 1;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } s;
-    struct cvmx_npei_ctl_port0_s         cn52xx;
-    struct cvmx_npei_ctl_port0_s         cn52xxp1;
-    struct cvmx_npei_ctl_port0_s         cn56xx;
-    struct cvmx_npei_ctl_port0_s         cn56xxp1;
-} cvmx_npei_ctl_port0_t;
-
-
-/**
- * cvmx_npei_ctl_port1
- *
- * NPEI_CTL_PORT1 = NPEI's Control Port1
- * 
- * Contains control for access for Port1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_ctl_port1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t waitl_com               : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional completions
-                                                         to the L2C from the PCIe.
-                                                         Set this for more conservative behavior. Clear
-                                                         this for more aggressive, higher-performance */
-        uint64_t intd                    : 1;       /**< When '0' Intd wire asserted. Before mapping. */
-        uint64_t intc                    : 1;       /**< When '0' Intc wire asserted. Before mapping. */
-        uint64_t intb                    : 1;       /**< When '0' Intv wire asserted. Before mapping. */
-        uint64_t inta                    : 1;       /**< When '0' Inta wire asserted. Before mapping. */
-        uint64_t intd_map                : 2;       /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t intc_map                : 2;       /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t intb_map                : 2;       /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t inta_map                : 2;       /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
-                                                         INTD (11). */
-        uint64_t ctlp_ro                 : 1;       /**< Relaxed ordering enable for Completion TLPS. */
-        uint64_t reserved_6_6            : 1;
-        uint64_t ptlp_ro                 : 1;       /**< Relaxed ordering enable for Posted TLPS. */
-        uint64_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
-                                                         clear '0' BAR2 access will cause UR responses. */
-        uint64_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
-                                                         determine the endian swap mode. */
-        uint64_t bar2_cax                : 1;       /**< Value will be XORed with pcie-address[38] to
-                                                         determine the L2 cache attribute.
-                                                         Not cached in L2 if XOR result is 1 */
-        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional stores to
-                                                         the L2C from the PCIe.
-                                                         Most applications will not notice a difference, so
-                                                         should not set this bit. Setting the bit is more
-                                                         conservative on ordering, lower performance */
-#else
-        uint64_t wait_com                : 1;
-        uint64_t bar2_cax                : 1;
-        uint64_t bar2_esx                : 2;
-        uint64_t bar2_enb                : 1;
-        uint64_t ptlp_ro                 : 1;
-        uint64_t reserved_6_6            : 1;
-        uint64_t ctlp_ro                 : 1;
-        uint64_t inta_map                : 2;
-        uint64_t intb_map                : 2;
-        uint64_t intc_map                : 2;
-        uint64_t intd_map                : 2;
-        uint64_t inta                    : 1;
-        uint64_t intb                    : 1;
-        uint64_t intc                    : 1;
-        uint64_t intd                    : 1;
-        uint64_t waitl_com               : 1;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } s;
-    struct cvmx_npei_ctl_port1_s         cn52xx;
-    struct cvmx_npei_ctl_port1_s         cn52xxp1;
-    struct cvmx_npei_ctl_port1_s         cn56xx;
-    struct cvmx_npei_ctl_port1_s         cn56xxp1;
-} cvmx_npei_ctl_port1_t;
-
-
-/**
- * cvmx_npei_ctl_status
- *
- * NPEI_CTL_STATUS = NPEI Control Status Register
- * 
- * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space.
- * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space)
- * that requires the value of this register to be updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t p1_ntags                : 6;       /**< Number of tags avaiable for PCIe Port1.
-                                                         In RC mode 1 tag is needed for each outbound TLP
-                                                         that requires a CPL TLP. In Endpoint mode the
-                                                         number of tags required for a TLP request is
-                                                         1 per 64-bytes of CPL data + 1.
-                                                         This field should only be written as part of
-                                                         reset sequence, before issuing any reads, CFGs, or
-                                                         IO transactions from the core(s). */
-        uint64_t p0_ntags                : 6;       /**< Number of tags avaiable for PCIe Port0.
-                                                         In RC mode 1 tag is needed for each outbound TLP
-                                                         that requires a CPL TLP. In Endpoint mode the
-                                                         number of tags required for a TLP request is
-                                                         1 per 64-bytes of CPL data + 1.
-                                                         This field should only be written as part of
-                                                         reset sequence, before issuing any reads, CFGs, or
-                                                         IO transactions from the core(s). */
-        uint64_t cfg_rtry                : 16;      /**< The time x 0x10000 in core clocks to wait for a
-                                                         CPL to a CFG RD that does not carry a Retry Status.
-                                                         Until such time that the timeout occurs and Retry
-                                                         Status is received for a CFG RD, the Read CFG Read
-                                                         will be resent. A value of 0 disables retries and
-                                                         treats a CPL Retry as a CPL UR. */
-        uint64_t ring_en                 : 1;       /**< When '0' forces "relative Q position" received
-                                                         from PKO to be zero, and replicates the back-
-                                                         pressure indication for the first ring attached
-                                                         to a PKO port across all the rings attached to a
-                                                         PKO port. When '0', only rings 0-3 can be used. */
-        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
-                                                         link down state. This bit is only reset on raw
-                                                         reset so it can be read for state to determine if
-                                                         a reset occured. Bit is cleared when a '1' is
-                                                         written to this field. */
-        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
-                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
-        uint64_t pkt_bp                  : 4;       /**< Unused */
-        uint64_t host_mode               : 1;       /**< Host mode */
-        uint64_t chip_rev                : 8;       /**< The chip revision. */
-#else
-        uint64_t chip_rev                : 8;
-        uint64_t host_mode               : 1;
-        uint64_t pkt_bp                  : 4;
-        uint64_t arb                     : 1;
-        uint64_t lnk_rst                 : 1;
-        uint64_t ring_en                 : 1;
-        uint64_t cfg_rtry                : 16;
-        uint64_t p0_ntags                : 6;
-        uint64_t p1_ntags                : 6;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npei_ctl_status_s        cn52xx;
-    struct cvmx_npei_ctl_status_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t p1_ntags                : 6;       /**< Number of tags avaiable for PCIe Port1.
-                                                         In RC mode 1 tag is needed for each outbound TLP
-                                                         that requires a CPL TLP. In Endpoint mode the
-                                                         number of tags required for a TLP request is
-                                                         1 per 64-bytes of CPL data + 1.
-                                                         This field should only be written as part of
-                                                         reset sequence, before issuing any reads, CFGs, or
-                                                         IO transactions from the core(s). */
-        uint64_t p0_ntags                : 6;       /**< Number of tags avaiable for PCIe Port0.
-                                                         In RC mode 1 tag is needed for each outbound TLP
-                                                         that requires a CPL TLP. In Endpoint mode the
-                                                         number of tags required for a TLP request is
-                                                         1 per 64-bytes of CPL data + 1.
-                                                         This field should only be written as part of
-                                                         reset sequence, before issuing any reads, CFGs, or
-                                                         IO transactions from the core(s). */
-        uint64_t cfg_rtry                : 16;      /**< The time x 0x10000 in core clocks to wait for a
-                                                         CPL to a CFG RD that does not carry a Retry Status.
-                                                         Until such time that the timeout occurs and Retry
-                                                         Status is received for a CFG RD, the Read CFG Read
-                                                         will be resent. A value of 0 disables retries and
-                                                         treats a CPL Retry as a CPL UR. */
-        uint64_t reserved_15_15          : 1;
-        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
-                                                         link down state. This bit is only reset on raw
-                                                         reset so it can be read for state to determine if
-                                                         a reset occured. Bit is cleared when a '1' is
-                                                         written to this field. */
-        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
-                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
-        uint64_t reserved_9_12           : 4;
-        uint64_t host_mode               : 1;       /**< Host mode */
-        uint64_t chip_rev                : 8;       /**< The chip revision. */
-#else
-        uint64_t chip_rev                : 8;
-        uint64_t host_mode               : 1;
-        uint64_t reserved_9_12           : 4;
-        uint64_t arb                     : 1;
-        uint64_t lnk_rst                 : 1;
-        uint64_t reserved_15_15          : 1;
-        uint64_t cfg_rtry                : 16;
-        uint64_t p0_ntags                : 6;
-        uint64_t p1_ntags                : 6;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_ctl_status_s        cn56xx;
-    struct cvmx_npei_ctl_status_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
-                                                         link down state. This bit is only reset on raw
-                                                         reset so it can be read for state to determine if
-                                                         a reset occured. Bit is cleared when a '1' is
-                                                         written to this field. */
-        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
-                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
-        uint64_t pkt_bp                  : 4;       /**< Unused */
-        uint64_t host_mode               : 1;       /**< Host mode */
-        uint64_t chip_rev                : 8;       /**< The chip revision. */
-#else
-        uint64_t chip_rev                : 8;
-        uint64_t host_mode               : 1;
-        uint64_t pkt_bp                  : 4;
-        uint64_t arb                     : 1;
-        uint64_t lnk_rst                 : 1;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } cn56xxp1;
-} cvmx_npei_ctl_status_t;
-
-
-/**
- * cvmx_npei_ctl_status2
- *
- * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register
- * 
- * Contains control and status for NPEI.
- * Writes to this register are not ordered with writes/reads to the PCI Memory space.
- * To ensure that a write has completed the user must read the register before
- * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_ctl_status2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mps                     : 1;       /**< Max Payload Size
-                                                                  0  = 128B
-                                                                  1  = 256B
-                                                         Note: PCIE*_CFG030[MPS] must be set to the same
-                                                               value for proper function. */
-        uint64_t mrrs                    : 3;       /**< Max Read Request Size
-                                                                 0 = 128B
-                                                                 1 = 256B
-                                                                 2 = 512B
-                                                                 3 = 1024B
-                                                                 4 = 2048B
-                                                                 5 = 4096B
-                                                         Note: This field must not exceed the desired
-                                                               max read request size. This means this field
-                                                               should not exceed PCIE*_CFG030[MRRS]. */
-        uint64_t c1_w_flt                : 1;       /**< When '1' enables the window filter for reads and
-                                                         writes using the window registers.
-                                                         PCIE-Port1.
-                                                         Unfilter writes are:
-                                                         MIO,   SubId0
-                                                         MIO,   SubId7
-                                                         NPEI,  SubId0
-                                                         NPEI,  SubId7
-                                                         POW,   SubId7
-                                                         IPD,   SubId7
-                                                         USBN0, SubId7
-                                                         Unfiltered Reads are:
-                                                         MIO,   SubId0
-                                                         MIO,   SubId7
-                                                         NPEI,  SubId0
-                                                         NPEI,  SubId7
-                                                         POW,   SubId1
-                                                         POW,   SubId2
-                                                         POW,   SubId3
-                                                         POW,   SubId7
-                                                         IPD,   SubId7
-                                                         USBN0, SubId7 */
-        uint64_t c0_w_flt                : 1;       /**< When '1' enables the window filter for reads and
-                                                         writes using the window registers.
-                                                         PCIE-Port0.
-                                                         Unfilter writes are:
-                                                         MIO,   SubId0
-                                                         MIO,   SubId7
-                                                         NPEI,  SubId0
-                                                         NPEI,  SubId7
-                                                         POW,   SubId7
-                                                         IPD,   SubId7
-                                                         USBN0, SubId7
-                                                         Unfiltered Reads are:
-                                                         MIO,   SubId0
-                                                         MIO,   SubId7
-                                                         NPEI,  SubId0
-                                                         NPEI,  SubId7
-                                                         POW,   SubId1
-                                                         POW,   SubId2
-                                                         POW,   SubId3
-                                                         POW,   SubId7
-                                                         IPD,   SubId7
-                                                         USBN0, SubId7 */
-        uint64_t c1_b1_s                 : 3;       /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB,
-                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
-                                                         0 and 7 are reserved. */
-        uint64_t c0_b1_s                 : 3;       /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
-                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
-                                                         0 and 7 are reserved. */
-        uint64_t c1_wi_d                 : 1;       /**< When set '1' disables access to the Window
-                                                         Registers from the PCIe-Port1. */
-        uint64_t c1_b0_d                 : 1;       /**< When set '1' disables access from PCIe-Port1 to
-                                                         BAR-0 address offsets: Less Than 0x270,
-                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
-                                                         0x3CD0. */
-        uint64_t c0_wi_d                 : 1;       /**< When set '1' disables access to the Window
-                                                         Registers from the PCIe-Port0. */
-        uint64_t c0_b0_d                 : 1;       /**< When set '1' disables access from PCIe-Port0 to
-                                                         BAR-0 address offsets: Less Than 0x270,
-                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
-                                                         0x3CD0. */
-#else
-        uint64_t c0_b0_d                 : 1;
-        uint64_t c0_wi_d                 : 1;
-        uint64_t c1_b0_d                 : 1;
-        uint64_t c1_wi_d                 : 1;
-        uint64_t c0_b1_s                 : 3;
-        uint64_t c1_b1_s                 : 3;
-        uint64_t c0_w_flt                : 1;
-        uint64_t c1_w_flt                : 1;
-        uint64_t mrrs                    : 3;
-        uint64_t mps                     : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npei_ctl_status2_s       cn52xx;
-    struct cvmx_npei_ctl_status2_s       cn52xxp1;
-    struct cvmx_npei_ctl_status2_s       cn56xx;
-    struct cvmx_npei_ctl_status2_s       cn56xxp1;
-} cvmx_npei_ctl_status2_t;
-
-
-/**
- * cvmx_npei_data_out_cnt
- *
- * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT
- * 
- * The EXEC data out fifo-count and the data unload counter.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_data_out_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t p1_ucnt                 : 16;      /**< PCIE-Port1 Fifo Unload Count. This counter is
-                                                         incremented by '1' every time a word is removed
-                                                         from the Data Out FIFO, whose count is shown in
-                                                         P0_FCNT. */
-        uint64_t p1_fcnt                 : 6;       /**< PCIE-Port1 Data Out Fifo Count. Number of address
-                                                         data words to be sent out the PCIe port presently
-                                                         buffered in the FIFO. */
-        uint64_t p0_ucnt                 : 16;      /**< PCIE-Port0 Fifo Unload Count. This counter is
-                                                         incremented by '1' every time a word is removed
-                                                         from the Data Out FIFO, whose count is shown in
-                                                         P0_FCNT. */
-        uint64_t p0_fcnt                 : 6;       /**< PCIE-Port0 Data Out Fifo Count. Number of address
-                                                         data words to be sent out the PCIe port presently
-                                                         buffered in the FIFO. */
-#else
-        uint64_t p0_fcnt                 : 6;
-        uint64_t p0_ucnt                 : 16;
-        uint64_t p1_fcnt                 : 6;
-        uint64_t p1_ucnt                 : 16;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npei_data_out_cnt_s      cn52xx;
-    struct cvmx_npei_data_out_cnt_s      cn52xxp1;
-    struct cvmx_npei_data_out_cnt_s      cn56xx;
-    struct cvmx_npei_data_out_cnt_s      cn56xxp1;
-} cvmx_npei_data_out_cnt_t;
-
-
-/**
- * cvmx_npei_dbg_data
- *
- * NPEI_DBG_DATA = NPEI Debug Data Register
- * 
- * Value returned on the debug-data lines from the RSLs
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dbg_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
-        uint64_t reserved_25_26          : 2;
-        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
-                                                         0=1.25 Gbaud
-                                                         1=2.5 Gbaud
-                                                         2=3.125 Gbaud
-                                                         3=3.75 Gbaud */
-        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
-                                                         Core frequency = 50MHz*C_MUL */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t qlm1_spd                : 2;
-        uint64_t reserved_25_26          : 2;
-        uint64_t qlm0_rev_lanes          : 1;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_npei_dbg_data_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t qlm0_link_width         : 1;       /**< Link width of PCIe port 0
-                                                         0 = PCIe port 0 is 2 lanes,
-                                                             2 lane PCIe port 1 exists
-                                                         1 = PCIe port 0 is 4 lanes,
-                                                             PCIe port 1 does not exist */
-        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
-        uint64_t qlm1_mode               : 2;       /**< Sets the QLM1 Mode
-                                                         0=Reserved
-                                                         1=XAUI
-                                                         2=SGMII
-                                                         3=PICMG */
-        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
-                                                         0=1.25 Gbaud
-                                                         1=2.5 Gbaud
-                                                         2=3.125 Gbaud
-                                                         3=3.75 Gbaud */
-        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
-                                                         Core frequency = 50MHz*C_MUL */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t qlm1_spd                : 2;
-        uint64_t qlm1_mode               : 2;
-        uint64_t qlm0_rev_lanes          : 1;
-        uint64_t qlm0_link_width         : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn52xx;
-    struct cvmx_npei_dbg_data_cn52xx     cn52xxp1;
-    struct cvmx_npei_dbg_data_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t qlm2_rev_lanes          : 1;       /**< Lane reversal for PCIe port 1 */
-        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
-        uint64_t qlm3_spd                : 2;       /**< Sets the QLM3 frequency
-                                                         0=1.25 Gbaud
-                                                         1=2.5 Gbaud
-                                                         2=3.125 Gbaud
-                                                         3=3.75 Gbaud */
-        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
-                                                         0=1.25 Gbaud
-                                                         1=2.5 Gbaud
-                                                         2=3.125 Gbaud
-                                                         3=3.75 Gbaud */
-        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
-                                                         Core frequency = 50MHz*C_MUL */
-        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
-                                                         debug select value. */
-        uint64_t data                    : 17;      /**< Value on the debug data lines. */
-#else
-        uint64_t data                    : 17;
-        uint64_t dsel_ext                : 1;
-        uint64_t c_mul                   : 5;
-        uint64_t qlm1_spd                : 2;
-        uint64_t qlm3_spd                : 2;
-        uint64_t qlm0_rev_lanes          : 1;
-        uint64_t qlm2_rev_lanes          : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn56xx;
-    struct cvmx_npei_dbg_data_cn56xx     cn56xxp1;
-} cvmx_npei_dbg_data_t;
-
-
-/**
- * cvmx_npei_dbg_select
- *
- * NPEI_DBG_SELECT = Debug Select Register
- * 
- * Contains the debug select value last written to the RSLs.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dbg_select_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dbg_sel                 : 16;      /**< When this register is written its value is sent to
-                                                         all RSLs. */
-#else
-        uint64_t dbg_sel                 : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npei_dbg_select_s        cn52xx;
-    struct cvmx_npei_dbg_select_s        cn52xxp1;
-    struct cvmx_npei_dbg_select_s        cn56xx;
-    struct cvmx_npei_dbg_select_s        cn56xxp1;
-} cvmx_npei_dbg_select_t;
-
-
-/**
- * cvmx_npei_dma#_counts
- *
- * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts
- * 
- * Values for determing the number of instructions for DMA[0..4] in the NPEI.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dmax_counts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
-        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
-#else
-        uint64_t dbell                   : 32;
-        uint64_t fcnt                    : 7;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } s;
-    struct cvmx_npei_dmax_counts_s       cn52xx;
-    struct cvmx_npei_dmax_counts_s       cn52xxp1;
-    struct cvmx_npei_dmax_counts_s       cn56xx;
-    struct cvmx_npei_dmax_counts_s       cn56xxp1;
-} cvmx_npei_dmax_counts_t;
-
-
-/**
- * cvmx_npei_dma#_dbell
- *
- * NPEI_DMA_DBELL[0..4] = DMA Door Bell
- * 
- * The door bell register for DMA[0..4] queue.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_npei_dmax_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t dbell                   : 16;      /**< The value written to this register is added to the
-                                                         number of 8byte words to be read and processes for
-                                                         the low priority dma queue. */
-#else
-        uint32_t dbell                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_npei_dmax_dbell_s        cn52xx;
-    struct cvmx_npei_dmax_dbell_s        cn52xxp1;
-    struct cvmx_npei_dmax_dbell_s        cn56xx;
-    struct cvmx_npei_dmax_dbell_s        cn56xxp1;
-} cvmx_npei_dmax_dbell_t;
-
-
-/**
- * cvmx_npei_dma#_ibuff_saddr
- *
- * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
- * 
- * The address to start reading Instructions from for DMA[0..4].
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dmax_ibuff_saddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t idle                    : 1;       /**< DMA Engine IDLE state */
-        uint64_t saddr                   : 29;      /**< The 128 byte aligned starting address to read the
-                                                         first instruction. SADDR is address bit 35:7 of the
-                                                         first instructions address. */
-        uint64_t reserved_0_6            : 7;
-#else
-        uint64_t reserved_0_6            : 7;
-        uint64_t saddr                   : 29;
-        uint64_t idle                    : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } s;
-    struct cvmx_npei_dmax_ibuff_saddr_s  cn52xx;
-    struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t saddr                   : 29;      /**< The 128 byte aligned starting address to read the
-                                                         first instruction. SADDR is address bit 35:7 of the
-                                                         first instructions address. */
-        uint64_t reserved_0_6            : 7;
-#else
-        uint64_t reserved_0_6            : 7;
-        uint64_t saddr                   : 29;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_dmax_ibuff_saddr_s  cn56xx;
-    struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
-} cvmx_npei_dmax_ibuff_saddr_t;
-
-
-/**
- * cvmx_npei_dma#_naddr
- *
- * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address
- * 
- * Place NPEI will read the next Ichunk data from. This is valid when state is 0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dmax_naddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< The next L2C address to read DMA# instructions
-                                                         from. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_npei_dmax_naddr_s        cn52xx;
-    struct cvmx_npei_dmax_naddr_s        cn52xxp1;
-    struct cvmx_npei_dmax_naddr_s        cn56xx;
-    struct cvmx_npei_dmax_naddr_s        cn56xxp1;
-} cvmx_npei_dmax_naddr_t;
-
-
-/**
- * cvmx_npei_dma0_int_level
- *
- * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level
- * 
- * Thresholds for DMA count and timer interrupts for DMA0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma0_int_level_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t time                    : 32;      /**< Whenever the DMA_CNT0 timer exceeds
-                                                         this value, NPEI_INT_SUM[DTIME0] is set.
-                                                         The DMA_CNT0 timer increments every core clock
-                                                         whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared
-                                                         when NPEI_INT_SUM[DTIME0] is written with one. */
-        uint64_t cnt                     : 32;      /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value,
-                                                         NPEI_INT_SUM[DCNT0] is set. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t time                    : 32;
-#endif
-    } s;
-    struct cvmx_npei_dma0_int_level_s    cn52xx;
-    struct cvmx_npei_dma0_int_level_s    cn52xxp1;
-    struct cvmx_npei_dma0_int_level_s    cn56xx;
-    struct cvmx_npei_dma0_int_level_s    cn56xxp1;
-} cvmx_npei_dma0_int_level_t;
-
-
-/**
- * cvmx_npei_dma1_int_level
- *
- * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level
- * 
- * Thresholds for DMA count and timer interrupts for DMA1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma1_int_level_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t time                    : 32;      /**< Whenever the DMA_CNT1 timer exceeds
-                                                         this value, NPEI_INT_SUM[DTIME1] is set.
-                                                         The DMA_CNT1 timer increments every core clock
-                                                         whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared
-                                                         when NPEI_INT_SUM[DTIME1] is written with one. */
-        uint64_t cnt                     : 32;      /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value,
-                                                         NPEI_INT_SUM[DCNT1] is set. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t time                    : 32;
-#endif
-    } s;
-    struct cvmx_npei_dma1_int_level_s    cn52xx;
-    struct cvmx_npei_dma1_int_level_s    cn52xxp1;
-    struct cvmx_npei_dma1_int_level_s    cn56xx;
-    struct cvmx_npei_dma1_int_level_s    cn56xxp1;
-} cvmx_npei_dma1_int_level_t;
-
-
-/**
- * cvmx_npei_dma_cnts
- *
- * NPEI_DMA_CNTS = NPEI DMA Count
- * 
- * The DMA Count values for DMA0 and DMA1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_cnts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dma1                    : 32;      /**< The DMA counter 1.
-                                                         Writing this field will cause the written value to
-                                                         be subtracted from DMA1. SW should use a 4-byte
-                                                         write to access this field so as not to change the
-                                                         value of other fields in this register.
-                                                         HW will optionally increment this field after
-                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
-                                                         instruction. These increments may cause interrupts.
-                                                         Refer to NPEI_DMA1_INT_LEVEL and
-                                                         NPEI_INT_SUM[DCNT1,DTIME1]. */
-        uint64_t dma0                    : 32;      /**< The DMA counter 0.
-                                                         Writing this field will cause the written value to
-                                                         be subtracted from DMA0. SW should use a 4-byte
-                                                         write to access this field so as not to change the
-                                                         value of other fields in this register.
-                                                         HW will optionally increment this field after
-                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
-                                                         instruction. These increments may cause interrupts.
-                                                         Refer to NPEI_DMA0_INT_LEVEL and
-                                                         NPEI_INT_SUM[DCNT0,DTIME0]. */
-#else
-        uint64_t dma0                    : 32;
-        uint64_t dma1                    : 32;
-#endif
-    } s;
-    struct cvmx_npei_dma_cnts_s          cn52xx;
-    struct cvmx_npei_dma_cnts_s          cn52xxp1;
-    struct cvmx_npei_dma_cnts_s          cn56xx;
-    struct cvmx_npei_dma_cnts_s          cn56xxp1;
-} cvmx_npei_dma_cnts_t;
-
-
-/**
- * cvmx_npei_dma_control
- *
- * NPEI_DMA_CONTROL = DMA Control Register
- * 
- * Controls operation of the DMA IN/OUT.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t p_32b_m                 : 1;       /**< DMA PCIE 32-bit word read disable bit
-                                                         When 0, enable the feature */
-        uint64_t dma4_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
-                                                         0 to L2C memory when a DMA is done, the address
-                                                         to be written to will be treated as a Little
-                                                         Endian address. */
-        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
-                                                         field for a free page operation for the memory
-                                                         that contained the data. */
-        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
-                                                         this value is used for the DWB field of the
-                                                         operation. */
-        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
-                                                         be returned to when used. */
-        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
-                                                         if '0' then the number of bytes in the dma transfer
-                                                         will be added to the count register. */
-        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
-        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
-        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
-        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
-                                                         '1' use pointer values for address and register
-                                                         values for RO, ES, and NS, '0' use register
-                                                         values for address and pointer values for
-                                                         RO, ES, and NS. */
-        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
-                                                         This value should only be written once. After
-                                                         writing this value a new value will not be
-                                                         recognized until the end of the DMA I-Chunk is
-                                                         reached. */
-#else
-        uint64_t csize                   : 14;
-        uint64_t o_mode                  : 1;
-        uint64_t o_es                    : 2;
-        uint64_t o_ns                    : 1;
-        uint64_t o_ro                    : 1;
-        uint64_t o_add1                  : 1;
-        uint64_t fpa_que                 : 3;
-        uint64_t dwb_ichk                : 9;
-        uint64_t dwb_denb                : 1;
-        uint64_t b0_lend                 : 1;
-        uint64_t dma0_enb                : 1;
-        uint64_t dma1_enb                : 1;
-        uint64_t dma2_enb                : 1;
-        uint64_t dma3_enb                : 1;
-        uint64_t dma4_enb                : 1;
-        uint64_t p_32b_m                 : 1;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_npei_dma_control_s       cn52xx;
-    struct cvmx_npei_dma_control_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
-                                                         0 to L2C memory when a DMA is done, the address
-                                                         to be written to will be treated as a Little
-                                                         Endian address. */
-        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
-                                                         field for a free page operation for the memory
-                                                         that contained the data. */
-        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
-                                                         this value is used for the DWB field of the
-                                                         operation. */
-        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
-                                                         be returned to when used. */
-        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
-                                                         if '0' then the number of bytes in the dma transfer
-                                                         will be added to the count register. */
-        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
-        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
-        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
-        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
-                                                         '1' use pointer values for address and register
-                                                         values for RO, ES, and NS, '0' use register
-                                                         values for address and pointer values for
-                                                         RO, ES, and NS. */
-        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
-                                                         This value should only be written once. After
-                                                         writing this value a new value will not be
-                                                         recognized until the end of the DMA I-Chunk is
-                                                         reached. */
-#else
-        uint64_t csize                   : 14;
-        uint64_t o_mode                  : 1;
-        uint64_t o_es                    : 2;
-        uint64_t o_ns                    : 1;
-        uint64_t o_ro                    : 1;
-        uint64_t o_add1                  : 1;
-        uint64_t fpa_que                 : 3;
-        uint64_t dwb_ichk                : 9;
-        uint64_t dwb_denb                : 1;
-        uint64_t b0_lend                 : 1;
-        uint64_t dma0_enb                : 1;
-        uint64_t dma1_enb                : 1;
-        uint64_t dma2_enb                : 1;
-        uint64_t dma3_enb                : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_dma_control_s       cn56xx;
-    struct cvmx_npei_dma_control_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t dma4_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
-                                                         engine. After being enabled a DMA engine should not
-                                                         be dis-abled while processing instructions. */
-        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
-                                                         0 to L2C memory when a DMA is done, the address
-                                                         to be written to will be treated as a Little
-                                                         Endian address. */
-        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
-                                                         field for a free page operation for the memory
-                                                         that contained the data. */
-        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
-                                                         this value is used for the DWB field of the
-                                                         operation. */
-        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
-                                                         be returned to when used. */
-        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
-                                                         if '0' then the number of bytes in the dma transfer
-                                                         will be added to the count register. */
-        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
-        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
-        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
-        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
-                                                         '1' use pointer values for address and register
-                                                         values for RO, ES, and NS, '0' use register
-                                                         values for address and pointer values for
-                                                         RO, ES, and NS. */
-        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
-                                                         This value should only be written once. After
-                                                         writing this value a new value will not be
-                                                         recognized until the end of the DMA I-Chunk is
-                                                         reached. */
-#else
-        uint64_t csize                   : 14;
-        uint64_t o_mode                  : 1;
-        uint64_t o_es                    : 2;
-        uint64_t o_ns                    : 1;
-        uint64_t o_ro                    : 1;
-        uint64_t o_add1                  : 1;
-        uint64_t fpa_que                 : 3;
-        uint64_t dwb_ichk                : 9;
-        uint64_t dwb_denb                : 1;
-        uint64_t b0_lend                 : 1;
-        uint64_t dma0_enb                : 1;
-        uint64_t dma1_enb                : 1;
-        uint64_t dma2_enb                : 1;
-        uint64_t dma3_enb                : 1;
-        uint64_t dma4_enb                : 1;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } cn56xxp1;
-} cvmx_npei_dma_control_t;
-
-
-/**
- * cvmx_npei_dma_pcie_req_num
- *
- * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number
- * 
- * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_pcie_req_num_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dma_arb                 : 1;       /**< DMA_PKT Read Request Arbitration
-                                                         - 1: DMA0-4 and PKT are round robin. i.e.
-                                                             DMA0-DMA1-DMA2-DMA3-DMA4-PKT...
-                                                         - 0: DMA0-4 are round robin, pkt gets selected
-                                                             half the time. i.e.
-                                                             DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */
-        uint64_t reserved_53_62          : 10;
-        uint64_t pkt_cnt                 : 5;       /**< PKT outstanding PCIE Read Request Number for each
-                                                         PCIe port
-                                                         When PKT_CNT=x, for each PCIe port, the number
-                                                         of outstanding PCIe memory space reads by the PCIe
-                                                         packet input/output will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_45_47          : 3;
-        uint64_t dma4_cnt                : 5;       /**< DMA4 outstanding PCIE Read Request Number
-                                                         When DMA4_CNT=x, the number of outstanding PCIe
-                                                         memory space reads by the PCIe DMA engine 4
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_37_39          : 3;
-        uint64_t dma3_cnt                : 5;       /**< DMA3 outstanding PCIE Read Request Number
-                                                         When DMA3_CNT=x, the number of outstanding PCIe
-                                                         memory space reads by the PCIe DMA engine 3
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_29_31          : 3;
-        uint64_t dma2_cnt                : 5;       /**< DMA2 outstanding PCIE Read Request Number
-                                                         When DMA2_CNT=x, the number of outstanding PCIe
-                                                         memory space reads by the PCIe DMA engine 2
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_21_23          : 3;
-        uint64_t dma1_cnt                : 5;       /**< DMA1 outstanding PCIE Read Request Number
-                                                         When DMA1_CNT=x, the number of outstanding PCIe
-                                                         memory space reads by the PCIe DMA engine 1
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_13_15          : 3;
-        uint64_t dma0_cnt                : 5;       /**< DMA0 outstanding PCIE Read Request Number
-                                                         When DMA0_CNT=x, the number of outstanding PCIe
-                                                         memory space reads by the PCIe DMA engine 0
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-        uint64_t reserved_5_7            : 3;
-        uint64_t dma_cnt                 : 5;       /**< Total outstanding PCIE Read Request Number for each
-                                                         PCIe port
-                                                         When DMA_CNT=x, for each PCIe port, the total
-                                                         number of outstanding PCIe memory space reads
-                                                         by the PCIe DMA engines and packet input/output
-                                                         will not exceed x.
-                                                         Valid Number is between 1 and 16 */
-#else
-        uint64_t dma_cnt                 : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t dma0_cnt                : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t dma1_cnt                : 5;
-        uint64_t reserved_21_23          : 3;
-        uint64_t dma2_cnt                : 5;
-        uint64_t reserved_29_31          : 3;
-        uint64_t dma3_cnt                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t dma4_cnt                : 5;
-        uint64_t reserved_45_47          : 3;
-        uint64_t pkt_cnt                 : 5;
-        uint64_t reserved_53_62          : 10;
-        uint64_t dma_arb                 : 1;
-#endif
-    } s;
-    struct cvmx_npei_dma_pcie_req_num_s  cn52xx;
-    struct cvmx_npei_dma_pcie_req_num_s  cn56xx;
-} cvmx_npei_dma_pcie_req_num_t;
-
-
-/**
- * cvmx_npei_dma_state1
- *
- * NPEI_DMA_STATE1 = NPI's DMA State 1
- * 
- * Results from DMA state register 1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t d4_dwe                  : 8;       /**< DMA4 PICe Write State */
-        uint64_t d3_dwe                  : 8;       /**< DMA3 PICe Write State */
-        uint64_t d2_dwe                  : 8;       /**< DMA2 PICe Write State */
-        uint64_t d1_dwe                  : 8;       /**< DMA1 PICe Write State */
-        uint64_t d0_dwe                  : 8;       /**< DMA0 PICe Write State */
-#else
-        uint64_t d0_dwe                  : 8;
-        uint64_t d1_dwe                  : 8;
-        uint64_t d2_dwe                  : 8;
-        uint64_t d3_dwe                  : 8;
-        uint64_t d4_dwe                  : 8;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_npei_dma_state1_s        cn52xx;
-} cvmx_npei_dma_state1_t;
-
-
-/**
- * cvmx_npei_dma_state1_p1
- *
- * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State
- * 
- * DMA engine Debug information.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state1_p1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t d0_difst                : 7;       /**< DMA engine 0 dif instruction read state */
-        uint64_t d1_difst                : 7;       /**< DMA engine 1 dif instruction read state */
-        uint64_t d2_difst                : 7;       /**< DMA engine 2 dif instruction read state */
-        uint64_t d3_difst                : 7;       /**< DMA engine 3 dif instruction read state */
-        uint64_t d4_difst                : 7;       /**< DMA engine 4 dif instruction read state */
-        uint64_t d0_reqst                : 5;       /**< DMA engine 0 request data state */
-        uint64_t d1_reqst                : 5;       /**< DMA engine 1 request data state */
-        uint64_t d2_reqst                : 5;       /**< DMA engine 2 request data state */
-        uint64_t d3_reqst                : 5;       /**< DMA engine 3 request data state */
-        uint64_t d4_reqst                : 5;       /**< DMA engine 4 request data state */
-#else
-        uint64_t d4_reqst                : 5;
-        uint64_t d3_reqst                : 5;
-        uint64_t d2_reqst                : 5;
-        uint64_t d1_reqst                : 5;
-        uint64_t d0_reqst                : 5;
-        uint64_t d4_difst                : 7;
-        uint64_t d3_difst                : 7;
-        uint64_t d2_difst                : 7;
-        uint64_t d1_difst                : 7;
-        uint64_t d0_difst                : 7;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_npei_dma_state1_p1_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t d0_difst                : 7;       /**< DMA engine 0 dif instruction read state */
-        uint64_t d1_difst                : 7;       /**< DMA engine 1 dif instruction read state */
-        uint64_t d2_difst                : 7;       /**< DMA engine 2 dif instruction read state */
-        uint64_t d3_difst                : 7;       /**< DMA engine 3 dif instruction read state */
-        uint64_t reserved_25_31          : 7;
-        uint64_t d0_reqst                : 5;       /**< DMA engine 0 request data state */
-        uint64_t d1_reqst                : 5;       /**< DMA engine 1 request data state */
-        uint64_t d2_reqst                : 5;       /**< DMA engine 2 request data state */
-        uint64_t d3_reqst                : 5;       /**< DMA engine 3 request data state */
-        uint64_t reserved_0_4            : 5;
-#else
-        uint64_t reserved_0_4            : 5;
-        uint64_t d3_reqst                : 5;
-        uint64_t d2_reqst                : 5;
-        uint64_t d1_reqst                : 5;
-        uint64_t d0_reqst                : 5;
-        uint64_t reserved_25_31          : 7;
-        uint64_t d3_difst                : 7;
-        uint64_t d2_difst                : 7;
-        uint64_t d1_difst                : 7;
-        uint64_t d0_difst                : 7;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_dma_state1_p1_s     cn56xxp1;
-} cvmx_npei_dma_state1_p1_t;
-
-
-/**
- * cvmx_npei_dma_state2
- *
- * NPEI_DMA_STATE2 = NPI's DMA State 2
- * 
- * Results from DMA state register 2
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t ndwe                    : 4;       /**< DMA L2C Write State */
-        uint64_t reserved_21_23          : 3;
-        uint64_t ndre                    : 5;       /**< DMA L2C Read State */
-        uint64_t reserved_10_15          : 6;
-        uint64_t prd                     : 10;      /**< DMA PICe Read State */
-#else
-        uint64_t prd                     : 10;
-        uint64_t reserved_10_15          : 6;
-        uint64_t ndre                    : 5;
-        uint64_t reserved_21_23          : 3;
-        uint64_t ndwe                    : 4;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_npei_dma_state2_s        cn52xx;
-} cvmx_npei_dma_state2_t;
-
-
-/**
- * cvmx_npei_dma_state2_p1
- *
- * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State
- * 
- * DMA engine Debug information.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state2_p1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_45_63          : 19;
-        uint64_t d0_dffst                : 9;       /**< DMA engine 0 dif instruction fetch state */
-        uint64_t d1_dffst                : 9;       /**< DMA engine 1 dif instruction fetch state */
-        uint64_t d2_dffst                : 9;       /**< DMA engine 2 dif instruction fetch state */
-        uint64_t d3_dffst                : 9;       /**< DMA engine 3 dif instruction fetch state */
-        uint64_t d4_dffst                : 9;       /**< DMA engine 4 dif instruction fetch state */
-#else
-        uint64_t d4_dffst                : 9;
-        uint64_t d3_dffst                : 9;
-        uint64_t d2_dffst                : 9;
-        uint64_t d1_dffst                : 9;
-        uint64_t d0_dffst                : 9;
-        uint64_t reserved_45_63          : 19;
-#endif
-    } s;
-    struct cvmx_npei_dma_state2_p1_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_45_63          : 19;
-        uint64_t d0_dffst                : 9;       /**< DMA engine 0 dif instruction fetch state */
-        uint64_t d1_dffst                : 9;       /**< DMA engine 1 dif instruction fetch state */
-        uint64_t d2_dffst                : 9;       /**< DMA engine 2 dif instruction fetch state */
-        uint64_t d3_dffst                : 9;       /**< DMA engine 3 dif instruction fetch state */
-        uint64_t reserved_0_8            : 9;
-#else
-        uint64_t reserved_0_8            : 9;
-        uint64_t d3_dffst                : 9;
-        uint64_t d2_dffst                : 9;
-        uint64_t d1_dffst                : 9;
-        uint64_t d0_dffst                : 9;
-        uint64_t reserved_45_63          : 19;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_dma_state2_p1_s     cn56xxp1;
-} cvmx_npei_dma_state2_p1_t;
-
-
-/**
- * cvmx_npei_dma_state3_p1
- *
- * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State
- * 
- * DMA engine Debug information.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state3_p1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t d0_drest                : 15;      /**< DMA engine 0 dre state */
-        uint64_t d1_drest                : 15;      /**< DMA engine 1 dre state */
-        uint64_t d2_drest                : 15;      /**< DMA engine 2 dre state */
-        uint64_t d3_drest                : 15;      /**< DMA engine 3 dre state */
-#else
-        uint64_t d3_drest                : 15;
-        uint64_t d2_drest                : 15;
-        uint64_t d1_drest                : 15;
-        uint64_t d0_drest                : 15;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_npei_dma_state3_p1_s     cn52xxp1;
-    struct cvmx_npei_dma_state3_p1_s     cn56xxp1;
-} cvmx_npei_dma_state3_p1_t;
-
-
-/**
- * cvmx_npei_dma_state4_p1
- *
- * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State
- * 
- * DMA engine Debug information.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state4_p1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_52_63          : 12;
-        uint64_t d0_dwest                : 13;      /**< DMA engine 0 dwe state */
-        uint64_t d1_dwest                : 13;      /**< DMA engine 1 dwe state */
-        uint64_t d2_dwest                : 13;      /**< DMA engine 2 dwe state */
-        uint64_t d3_dwest                : 13;      /**< DMA engine 3 dwe state */
-#else
-        uint64_t d3_dwest                : 13;
-        uint64_t d2_dwest                : 13;
-        uint64_t d1_dwest                : 13;
-        uint64_t d0_dwest                : 13;
-        uint64_t reserved_52_63          : 12;
-#endif
-    } s;
-    struct cvmx_npei_dma_state4_p1_s     cn52xxp1;
-    struct cvmx_npei_dma_state4_p1_s     cn56xxp1;
-} cvmx_npei_dma_state4_p1_t;
-
-
-/**
- * cvmx_npei_dma_state5_p1
- *
- * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State
- * 
- * DMA engine Debug information.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_dma_state5_p1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t d4_drest                : 15;      /**< DMA engine 4 dre state */
-        uint64_t d4_dwest                : 13;      /**< DMA engine 4 dwe state */
-#else
-        uint64_t d4_dwest                : 13;
-        uint64_t d4_drest                : 15;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_npei_dma_state5_p1_s     cn56xxp1;
-} cvmx_npei_dma_state5_p1_t;
-
-
-/**
- * cvmx_npei_int_a_enb
- *
- * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register
- * 
- * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_a_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pout_err                : 1;       /**< Enables NPEI_INT_A_SUM[9] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pin_bp                  : 1;       /**< Enables NPEI_INT_A_SUM[8] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t p1_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[7] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t p0_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[6] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pgl_err                 : 1;       /**< Enables NPEI_INT_A_SUM[5] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pdi_err                 : 1;       /**< Enables NPEI_INT_A_SUM[4] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pop_err                 : 1;       /**< Enables NPEI_INT_A_SUM[3] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pins_err                : 1;       /**< Enables NPEI_INT_A_SUM[2] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t pins_err                : 1;
-        uint64_t pop_err                 : 1;
-        uint64_t pdi_err                 : 1;
-        uint64_t pgl_err                 : 1;
-        uint64_t p0_rdlk                 : 1;
-        uint64_t p1_rdlk                 : 1;
-        uint64_t pin_bp                  : 1;
-        uint64_t pout_err                : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_npei_int_a_enb_s         cn52xx;
-    struct cvmx_npei_int_a_enb_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_a_enb_s         cn56xx;
-} cvmx_npei_int_a_enb_t;
-
-
-/**
- * cvmx_npei_int_a_enb2
- *
- * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register
- * 
- * Used to enable the various interrupting conditions of NPEI
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_a_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pout_err                : 1;       /**< Enables NPEI_INT_A_SUM[9] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pin_bp                  : 1;       /**< Enables NPEI_INT_A_SUM[8] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t p1_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[7] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t p0_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[6] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pgl_err                 : 1;       /**< Enables NPEI_INT_A_SUM[5] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pdi_err                 : 1;       /**< Enables NPEI_INT_A_SUM[4] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pop_err                 : 1;       /**< Enables NPEI_INT_A_SUM[3] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pins_err                : 1;       /**< Enables NPEI_INT_A_SUM[2] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t pins_err                : 1;
-        uint64_t pop_err                 : 1;
-        uint64_t pdi_err                 : 1;
-        uint64_t pgl_err                 : 1;
-        uint64_t p0_rdlk                 : 1;
-        uint64_t p1_rdlk                 : 1;
-        uint64_t pin_bp                  : 1;
-        uint64_t pout_err                : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_npei_int_a_enb2_s        cn52xx;
-    struct cvmx_npei_int_a_enb2_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_a_enb2_s        cn56xx;
-} cvmx_npei_int_a_enb2_t;
-
-
-/**
- * cvmx_npei_int_a_sum
- *
- * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register
- * 
- * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and
- * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_a_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pout_err                : 1;       /**< Set when PKO sends packet data with the error bit
-                                                         set. */
-        uint64_t pin_bp                  : 1;       /**< Packet input count has exceeded the WMARK.
-                                                         See NPEI_PKT_IN_BP */
-        uint64_t p1_rdlk                 : 1;       /**< PCIe port 1 received a read lock. */
-        uint64_t p0_rdlk                 : 1;       /**< PCIe port 0 received a read lock. */
-        uint64_t pgl_err                 : 1;       /**< When a read error occurs on a packet gather list
-                                                         read this bit is set. */
-        uint64_t pdi_err                 : 1;       /**< When a read error occurs on a packet data read
-                                                         this bit is set. */
-        uint64_t pop_err                 : 1;       /**< When a read error occurs on a packet scatter
-                                                         pointer pair this bit is set. */
-        uint64_t pins_err                : 1;       /**< When a read error occurs on a packet instruction
-                                                         this bit is set. */
-        uint64_t dma1_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
-                                                         response from PCIe Port 1 */
-        uint64_t dma0_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
-                                                         response from PCIe Port 0 */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t pins_err                : 1;
-        uint64_t pop_err                 : 1;
-        uint64_t pdi_err                 : 1;
-        uint64_t pgl_err                 : 1;
-        uint64_t p0_rdlk                 : 1;
-        uint64_t p1_rdlk                 : 1;
-        uint64_t pin_bp                  : 1;
-        uint64_t pout_err                : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_npei_int_a_sum_s         cn52xx;
-    struct cvmx_npei_int_a_sum_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t dma1_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
-                                                         response from PCIe Port 1 */
-        uint64_t dma0_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
-                                                         response from PCIe Port 0 */
-#else
-        uint64_t dma0_cpl                : 1;
-        uint64_t dma1_cpl                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_a_sum_s         cn56xx;
-} cvmx_npei_int_a_sum_t;
-
-
-/**
- * cvmx_npei_int_enb
- *
- * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register
- * 
- * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_62_62          : 1;
-        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM[61] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM[29] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM[27] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM[22] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM[20] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_62          : 1;
-        uint64_t mio_inta                : 1;
-#endif
-    } s;
-    struct cvmx_npei_int_enb_s           cn52xx;
-    struct cvmx_npei_int_enb_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_62_62          : 1;
-        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM[61] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM[29] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM[27] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM[22] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM[20] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_62          : 1;
-        uint64_t mio_inta                : 1;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_enb_s           cn56xx;
-    struct cvmx_npei_int_enb_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_61_62          : 2;
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
-                                                         interrupt to the PCIE core for MSI/inta. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t reserved_61_62          : 2;
-        uint64_t mio_inta                : 1;
-#endif
-    } cn56xxp1;
-} cvmx_npei_int_enb_t;
-
-
-/**
- * cvmx_npei_int_enb2
- *
- * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register
- * 
- * Used to enable the various interrupting conditions of NPI
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM2[61] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM2[29] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM2[27] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM2[22] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM2[20] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_UM[0] to generate an
-                                                         interrupt on the RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } s;
-    struct cvmx_npei_int_enb2_s          cn52xx;
-    struct cvmx_npei_int_enb2_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM2[61] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM2[60] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM2[59] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM2[58] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM2[57] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM2[56] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM2[55] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM2[54] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM2[53] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM2[52] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM2[51] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM2[50] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM2[49] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM2[48] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM2[47] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM2[46] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM2[45] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM2[44] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM2[43] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM2[42] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM2[41] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM2[40] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM2[39] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM2[38] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM2[37] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM2[36] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM2[35] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM2[34] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM2[33] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM2[32] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM2[31] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM2[30] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM2[29] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM2[28] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM2[27] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM2[26] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM2[25] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM2[24] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM2[23] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM2[22] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM2[21] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM2[20] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM2[19] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM2[18] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM2[17] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM2[16] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM2[15] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM2[14] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM2[13] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM2[12] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM2[11] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM2[10] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM2[9] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM2[7] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM2[6] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM2[5] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM2[4] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM2[3] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM2[2] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM2[1] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM2[0] to generate an
-                                                         interrupt on the RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_enb2_s          cn56xx;
-    struct cvmx_npei_int_enb2_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_61_63          : 3;
-        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
-                                                         interrupt on the RSL. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_UM[0] to generate an
-                                                         interrupt on the RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t reserved_61_63          : 3;
-#endif
-    } cn56xxp1;
-} cvmx_npei_int_enb2_t;
-
-
-/**
- * cvmx_npei_int_info
- *
- * NPEI_INT_INFO = NPI Interrupt Information
- * 
- * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_info_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t pidbof                  : 6;       /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
-                                                         is set. This field when set will not change again
-                                                         unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */
-        uint64_t psldbof                 : 6;       /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit
-                                                         is set. This field when set will not change again
-                                                         unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */
-#else
-        uint64_t psldbof                 : 6;
-        uint64_t pidbof                  : 6;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_npei_int_info_s          cn52xx;
-    struct cvmx_npei_int_info_s          cn56xx;
-    struct cvmx_npei_int_info_s          cn56xxp1;
-} cvmx_npei_int_info_t;
-
-
-/**
- * cvmx_npei_int_sum
- *
- * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register
- * 
- * Set when an interrupt condition occurs, write '1' to clear.
- * 
- * HACK: These used to exist, how are TO handled?
- *  <3>     PO0_2SML R/W1C    0x0         0         The packet being sent out on Port0 is smaller          $R     NS
- *                                                            than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.
- * <7>     I0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
- *                                                 read instructions.
- * <15>    P0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
- *                                                 read packet data.
- * <23>    G0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
- *                                                 read a gather list.
- * <31>    P0_PTOUT R/W1C    0x0         0         Port-0 output had a read timeout on a DATA/INFO         $R     NS
- *                                                 pair.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
-        uint64_t reserved_62_62          : 1;
-        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
-                                                         the cooresponding bit in the NPEI_INT_A_ENB
-                                                         register is set. */
-        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
-        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
-        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 1 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 1. (cfg_pme_int) */
-        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 1. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t crs1_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
-        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 1. (cfg_sys_err_rc) */
-        uint64_t crs1_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
-        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 1. */
-        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 0 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 0. (cfg_pme_int) */
-        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 0. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t crs0_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
-        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 0. (cfg_sys_err_rc) */
-        uint64_t crs0_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
-        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
-        uint64_t ptime                   : 1;       /**< Packet Timer has an interrupt. Which rings can
-                                                         be found in NPEI_PKT_TIME_INT. */
-        uint64_t pcnt                    : 1;       /**< Packet Counter has an interrupt. Which rings can
-                                                         be found in NPEI_PKT_CNT_INT. */
-        uint64_t pidbof                  : 1;       /**< Packet Instruction Doorbell count overflowed. Which
-                                                         doorbell can be found in NPEI_INT_INFO[PIDBOF] */
-        uint64_t psldbof                 : 1;       /**< Packet Scatterlist Doorbell count overflowed. Which
-                                                         doorbell can be found in NPEI_INT_INFO[PSLDBOF] */
-        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
-                                                         DMA_CNT1 timer increments every core clock. When
-                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT1 timer. */
-        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
-                                                         DMA_CNT0 timer increments every core clock. When
-                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT0 timer. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
-                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
-                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
-        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t dma4dbo                 : 1;       /**< DMA4 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
-        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
-                                                         read-data/commit in 0xffff core clocks. */
-        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
-        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t psldbof                 : 1;
-        uint64_t pidbof                  : 1;
-        uint64_t pcnt                    : 1;
-        uint64_t ptime                   : 1;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_62          : 1;
-        uint64_t mio_inta                : 1;
-#endif
-    } s;
-    struct cvmx_npei_int_sum_s           cn52xx;
-    struct cvmx_npei_int_sum_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
-        uint64_t reserved_62_62          : 1;
-        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
-                                                         the cooresponding bit in the NPEI_INT_A_ENB
-                                                         register is set. */
-        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
-        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
-        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 1 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 1. (cfg_pme_int) */
-        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 1. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t crs1_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
-        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 1. (cfg_sys_err_rc) */
-        uint64_t crs1_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
-        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 1. */
-        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 0 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 0. (cfg_pme_int) */
-        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 0. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t crs0_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
-        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 0. (cfg_sys_err_rc) */
-        uint64_t crs0_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
-        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
-        uint64_t reserved_15_18          : 4;
-        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
-                                                         DMA_CNT1 timer increments every core clock. When
-                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT1 timer. */
-        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
-                                                         DMA_CNT0 timer increments every core clock. When
-                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT0 timer. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
-                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
-                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
-        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell count overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell count overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell count overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell count overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
-        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
-                                                         read-data/commit in 0xffff core clocks. */
-        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
-        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t reserved_15_18          : 4;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_62          : 1;
-        uint64_t mio_inta                : 1;
-#endif
-    } cn52xxp1;
-    struct cvmx_npei_int_sum_s           cn56xx;
-    struct cvmx_npei_int_sum_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
-        uint64_t reserved_61_62          : 2;
-        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
-        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
-        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
-                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
-                                                         is set. */
-        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core1. */
-        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
-                                                         register. Core0. */
-        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 1. */
-        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 1. */
-        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 1. */
-        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 1. */
-        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 1. */
-        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
-                                                         Core 0. */
-        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
-                                                         Core 0. */
-        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
-                                                         Core 0. */
-        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
-                                                         Core 0. */
-        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
-                                                         Core 0. */
-        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 1 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 1. (cfg_pme_int) */
-        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 1. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 1. (cfg_sys_err_rc) */
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 1. */
-        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
-                                                         Pcie Core 0 (hp_int).
-                                                         This interrupt will only be generated when
-                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
-                                                         not supported. */
-        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
-                                                         Pcie Core 0. (cfg_pme_int) */
-        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
-                                                         Pcie Core 0. (wake_n)
-                                                         Octeon will never generate this interrupt. */
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
-                                                         Pcie Core 0. (cfg_sys_err_rc) */
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
-                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
-        uint64_t reserved_15_18          : 4;
-        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
-                                                         DMA_CNT1 timer increments every core clock. When
-                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT1 timer. */
-        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
-                                                         DMA_CNT0 timer increments every core clock. When
-                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
-                                                         this bit is set. Writing a '1' to this bit also
-                                                         clears the DMA_CNT0 timer. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
-                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
-                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
-        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
-        uint64_t dma4dbo                 : 1;       /**< DMA4 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell overflow.
-                                                         Bit[32] of the doorbell count was set. */
-        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
-        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
-                                                         read-data/commit in 0xffff core clocks. */
-        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
-        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t dma4dbo                 : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t reserved_15_18          : 4;
-        uint64_t c0_aeri                 : 1;
-        uint64_t reserved_20_20          : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t reserved_22_22          : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t reserved_27_27          : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t reserved_29_29          : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t reserved_61_62          : 2;
-        uint64_t mio_inta                : 1;
-#endif
-    } cn56xxp1;
-} cvmx_npei_int_sum_t;
-
-
-/**
- * cvmx_npei_int_sum2
- *
- * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register
- * 
- * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_int_sum2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mio_inta                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t reserved_62_62          : 1;
-        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
-                                                         the cooresponding bit in the NPEI_INT_A_ENB2
-                                                         register is set. */
-        uint64_t c1_ldwn                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_ldwn                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_exc                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_exc                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_wf                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_wf                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_wf                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_wf                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_bx                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_wi                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_b2                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_b1                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_un_b0                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_bx                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_wi                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_b2                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_b1                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_up_b0                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_bx                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_wi                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_b2                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_b1                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_un_b0                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_bx                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_wi                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_b2                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_b1                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_up_b0                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_hpint                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_pmei                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_wake                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t crs1_dr                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_se                   : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t crs1_er                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c1_aeri                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_hpint                : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_pmei                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_wake                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t crs0_dr                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_se                   : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t crs0_er                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t c0_aeri                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t reserved_15_18          : 4;
-        uint64_t dtime1                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dtime0                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dcnt1                   : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dcnt0                   : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dma1fi                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dma0fi                  : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma3dbo                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dma2dbo                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dma1dbo                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t dma0dbo                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t iob2big                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t bar0_to                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t rml_wto                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-        uint64_t rml_rto                 : 1;       /**< Equal to the cooresponding bit if the
-                                                         NPEI_INT_SUM register. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t bar0_to                 : 1;
-        uint64_t iob2big                 : 1;
-        uint64_t dma0dbo                 : 1;
-        uint64_t dma1dbo                 : 1;
-        uint64_t dma2dbo                 : 1;
-        uint64_t dma3dbo                 : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t dma0fi                  : 1;
-        uint64_t dma1fi                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t reserved_15_18          : 4;
-        uint64_t c0_aeri                 : 1;
-        uint64_t crs0_er                 : 1;
-        uint64_t c0_se                   : 1;
-        uint64_t crs0_dr                 : 1;
-        uint64_t c0_wake                 : 1;
-        uint64_t c0_pmei                 : 1;
-        uint64_t c0_hpint                : 1;
-        uint64_t c1_aeri                 : 1;
-        uint64_t crs1_er                 : 1;
-        uint64_t c1_se                   : 1;
-        uint64_t crs1_dr                 : 1;
-        uint64_t c1_wake                 : 1;
-        uint64_t c1_pmei                 : 1;
-        uint64_t c1_hpint                : 1;
-        uint64_t c0_up_b0                : 1;
-        uint64_t c0_up_b1                : 1;
-        uint64_t c0_up_b2                : 1;
-        uint64_t c0_up_wi                : 1;
-        uint64_t c0_up_bx                : 1;
-        uint64_t c0_un_b0                : 1;
-        uint64_t c0_un_b1                : 1;
-        uint64_t c0_un_b2                : 1;
-        uint64_t c0_un_wi                : 1;
-        uint64_t c0_un_bx                : 1;
-        uint64_t c1_up_b0                : 1;
-        uint64_t c1_up_b1                : 1;
-        uint64_t c1_up_b2                : 1;
-        uint64_t c1_up_wi                : 1;
-        uint64_t c1_up_bx                : 1;
-        uint64_t c1_un_b0                : 1;
-        uint64_t c1_un_b1                : 1;
-        uint64_t c1_un_b2                : 1;
-        uint64_t c1_un_wi                : 1;
-        uint64_t c1_un_bx                : 1;
-        uint64_t c0_un_wf                : 1;
-        uint64_t c1_un_wf                : 1;
-        uint64_t c0_up_wf                : 1;
-        uint64_t c1_up_wf                : 1;
-        uint64_t c0_exc                  : 1;
-        uint64_t c1_exc                  : 1;
-        uint64_t c0_ldwn                 : 1;
-        uint64_t c1_ldwn                 : 1;
-        uint64_t int_a                   : 1;
-        uint64_t reserved_62_62          : 1;
-        uint64_t mio_inta                : 1;
-#endif
-    } s;
-    struct cvmx_npei_int_sum2_s          cn52xx;
-    struct cvmx_npei_int_sum2_s          cn52xxp1;
-    struct cvmx_npei_int_sum2_s          cn56xx;
-} cvmx_npei_int_sum2_t;
-
-
-/**
- * cvmx_npei_last_win_rdata0
- *
- * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0
- * 
- * The data from the last initiated window read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_last_win_rdata0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Last window read data. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_last_win_rdata0_s   cn52xx;
-    struct cvmx_npei_last_win_rdata0_s   cn52xxp1;
-    struct cvmx_npei_last_win_rdata0_s   cn56xx;
-    struct cvmx_npei_last_win_rdata0_s   cn56xxp1;
-} cvmx_npei_last_win_rdata0_t;
-
-
-/**
- * cvmx_npei_last_win_rdata1
- *
- * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1
- * 
- * The data from the last initiated window read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_last_win_rdata1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Last window read data. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_last_win_rdata1_s   cn52xx;
-    struct cvmx_npei_last_win_rdata1_s   cn52xxp1;
-    struct cvmx_npei_last_win_rdata1_s   cn56xx;
-    struct cvmx_npei_last_win_rdata1_s   cn56xxp1;
-} cvmx_npei_last_win_rdata1_t;
-
-
-/**
- * cvmx_npei_mem_access_ctl
- *
- * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control
- * 
- * Contains control for access to the PCIe address space.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_mem_access_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t max_word                : 4;       /**< The maximum number of words to merge into a single
-                                                         write operation from the PPs to the PCIe. Legal
-                                                         values are 1 to 16, where a '0' is treated as 16. */
-        uint64_t timer                   : 10;      /**< When the NPEI starts a PP to PCIe write it waits
-                                                         no longer than the value of TIMER in eclks to
-                                                         merge additional writes from the PPs into 1
-                                                         large write. The values for this field is 1 to
-                                                         1024 where a value of '0' is treated as 1024. */
-#else
-        uint64_t timer                   : 10;
-        uint64_t max_word                : 4;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_npei_mem_access_ctl_s    cn52xx;
-    struct cvmx_npei_mem_access_ctl_s    cn52xxp1;
-    struct cvmx_npei_mem_access_ctl_s    cn56xx;
-    struct cvmx_npei_mem_access_ctl_s    cn56xxp1;
-} cvmx_npei_mem_access_ctl_t;
-
-
-/**
- * cvmx_npei_mem_access_subid#
- *
- * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register
- * 
- * Contains address index and control bits for access to memory from Core PPs.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_mem_access_subidx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_42_63          : 22;
-        uint64_t zero                    : 1;       /**< Causes all byte reads to be zero length reads.
-                                                         Returns to the EXEC a zero for all read data. */
-        uint64_t port                    : 2;       /**< Port the request is sent to. */
-        uint64_t nmerge                  : 1;       /**< No merging is allowed in this window. */
-        uint64_t esr                     : 2;       /**< Endian-swap for Reads. */
-        uint64_t esw                     : 2;       /**< Endian-swap for Writes. */
-        uint64_t nsr                     : 1;       /**< No Snoop for Reads. */
-        uint64_t nsw                     : 1;       /**< No Snoop for Writes. */
-        uint64_t ror                     : 1;       /**< Relaxed Ordering for Reads. */
-        uint64_t row                     : 1;       /**< Relaxed Ordering for Writes. */
-        uint64_t ba                      : 30;      /**< PCIe Adddress Bits <63:34>. */
-#else
-        uint64_t ba                      : 30;
-        uint64_t row                     : 1;
-        uint64_t ror                     : 1;
-        uint64_t nsw                     : 1;
-        uint64_t nsr                     : 1;
-        uint64_t esw                     : 2;
-        uint64_t esr                     : 2;
-        uint64_t nmerge                  : 1;
-        uint64_t port                    : 2;
-        uint64_t zero                    : 1;
-        uint64_t reserved_42_63          : 22;
-#endif
-    } s;
-    struct cvmx_npei_mem_access_subidx_s cn52xx;
-    struct cvmx_npei_mem_access_subidx_s cn52xxp1;
-    struct cvmx_npei_mem_access_subidx_s cn56xx;
-    struct cvmx_npei_mem_access_subidx_s cn56xxp1;
-} cvmx_npei_mem_access_subidx_t;
-
-
-/**
- * cvmx_npei_msi_enb0
- *
- * NPEI_MSI_ENB0 = NPEI MSI Enable0
- * 
- * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_enb0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
-#else
-        uint64_t enb                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_enb0_s          cn52xx;
-    struct cvmx_npei_msi_enb0_s          cn52xxp1;
-    struct cvmx_npei_msi_enb0_s          cn56xx;
-    struct cvmx_npei_msi_enb0_s          cn56xxp1;
-} cvmx_npei_msi_enb0_t;
-
-
-/**
- * cvmx_npei_msi_enb1
- *
- * NPEI_MSI_ENB1 = NPEI MSI Enable1
- * 
- * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_enb1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
-#else
-        uint64_t enb                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_enb1_s          cn52xx;
-    struct cvmx_npei_msi_enb1_s          cn52xxp1;
-    struct cvmx_npei_msi_enb1_s          cn56xx;
-    struct cvmx_npei_msi_enb1_s          cn56xxp1;
-} cvmx_npei_msi_enb1_t;
-
-
-/**
- * cvmx_npei_msi_enb2
- *
- * NPEI_MSI_ENB2 = NPEI MSI Enable2
- * 
- * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
-#else
-        uint64_t enb                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_enb2_s          cn52xx;
-    struct cvmx_npei_msi_enb2_s          cn52xxp1;
-    struct cvmx_npei_msi_enb2_s          cn56xx;
-    struct cvmx_npei_msi_enb2_s          cn56xxp1;
-} cvmx_npei_msi_enb2_t;
-
-
-/**
- * cvmx_npei_msi_enb3
- *
- * NPEI_MSI_ENB3 = NPEI MSI Enable3
- * 
- * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_enb3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
-#else
-        uint64_t enb                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_enb3_s          cn52xx;
-    struct cvmx_npei_msi_enb3_s          cn52xxp1;
-    struct cvmx_npei_msi_enb3_s          cn56xx;
-    struct cvmx_npei_msi_enb3_s          cn56xxp1;
-} cvmx_npei_msi_enb3_t;
-
-
-/**
- * cvmx_npei_msi_rcv0
- *
- * NPEI_MSI_RCV0 = NPEI MSI Receive0
- * 
- * Contains bits [63:0] of the 256 bits oof MSI interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_rcv0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t intr                    : 64;      /**< Bits 63-0 of the 256 bits of MSI interrupt. */
-#else
-        uint64_t intr                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_rcv0_s          cn52xx;
-    struct cvmx_npei_msi_rcv0_s          cn52xxp1;
-    struct cvmx_npei_msi_rcv0_s          cn56xx;
-    struct cvmx_npei_msi_rcv0_s          cn56xxp1;
-} cvmx_npei_msi_rcv0_t;
-
-
-/**
- * cvmx_npei_msi_rcv1
- *
- * NPEI_MSI_RCV1 = NPEI MSI Receive1
- * 
- * Contains bits [127:64] of the 256 bits oof MSI interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_rcv1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t intr                    : 64;      /**< Bits 127-64 of the 256 bits of MSI interrupt. */
-#else
-        uint64_t intr                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_rcv1_s          cn52xx;
-    struct cvmx_npei_msi_rcv1_s          cn52xxp1;
-    struct cvmx_npei_msi_rcv1_s          cn56xx;
-    struct cvmx_npei_msi_rcv1_s          cn56xxp1;
-} cvmx_npei_msi_rcv1_t;
-
-
-/**
- * cvmx_npei_msi_rcv2
- *
- * NPEI_MSI_RCV2 = NPEI MSI Receive2
- * 
- * Contains bits [191:128] of the 256 bits oof MSI interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_rcv2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t intr                    : 64;      /**< Bits 191-128 of the 256 bits of MSI interrupt. */
-#else
-        uint64_t intr                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_rcv2_s          cn52xx;
-    struct cvmx_npei_msi_rcv2_s          cn52xxp1;
-    struct cvmx_npei_msi_rcv2_s          cn56xx;
-    struct cvmx_npei_msi_rcv2_s          cn56xxp1;
-} cvmx_npei_msi_rcv2_t;
-
-
-/**
- * cvmx_npei_msi_rcv3
- *
- * NPEI_MSI_RCV3 = NPEI MSI Receive3
- * 
- * Contains bits [255:192] of the 256 bits oof MSI interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_rcv3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t intr                    : 64;      /**< Bits 255-192 of the 256 bits of MSI interrupt. */
-#else
-        uint64_t intr                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_rcv3_s          cn52xx;
-    struct cvmx_npei_msi_rcv3_s          cn52xxp1;
-    struct cvmx_npei_msi_rcv3_s          cn56xx;
-    struct cvmx_npei_msi_rcv3_s          cn56xxp1;
-} cvmx_npei_msi_rcv3_t;
-
-
-/**
- * cvmx_npei_msi_rd_map
- *
- * NPEI_MSI_RD_MAP = NPEI MSI Read MAP
- * 
- * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_rd_map_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t rd_int                  : 8;       /**< The value of the map at the location PREVIOUSLY
-                                                         written to the MSI_INT field of this register. */
-        uint64_t msi_int                 : 8;       /**< Selects the value that would be received when the
-                                                         NPEI_PCIE_MSI_RCV register is written. */
-#else
-        uint64_t msi_int                 : 8;
-        uint64_t rd_int                  : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npei_msi_rd_map_s        cn52xx;
-    struct cvmx_npei_msi_rd_map_s        cn52xxp1;
-    struct cvmx_npei_msi_rd_map_s        cn56xx;
-    struct cvmx_npei_msi_rd_map_s        cn56xxp1;
-} cvmx_npei_msi_rd_map_t;
-
-
-/**
- * cvmx_npei_msi_w1c_enb0
- *
- * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0
- * 
- * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1c_enb0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
-                                                         cooresponding bit in NPEI_MSI_ENB0.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t clr                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1c_enb0_s      cn52xx;
-    struct cvmx_npei_msi_w1c_enb0_s      cn56xx;
-} cvmx_npei_msi_w1c_enb0_t;
-
-
-/**
- * cvmx_npei_msi_w1c_enb1
- *
- * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1
- * 
- * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1c_enb1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
-                                                         cooresponding bit in NPEI_MSI_ENB1.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t clr                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1c_enb1_s      cn52xx;
-    struct cvmx_npei_msi_w1c_enb1_s      cn56xx;
-} cvmx_npei_msi_w1c_enb1_t;
-
-
-/**
- * cvmx_npei_msi_w1c_enb2
- *
- * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2
- * 
- * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1c_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
-                                                         cooresponding bit in NPEI_MSI_ENB2.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t clr                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1c_enb2_s      cn52xx;
-    struct cvmx_npei_msi_w1c_enb2_s      cn56xx;
-} cvmx_npei_msi_w1c_enb2_t;
-
-
-/**
- * cvmx_npei_msi_w1c_enb3
- *
- * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3
- * 
- * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1c_enb3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
-                                                         cooresponding bit in NPEI_MSI_ENB3.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t clr                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1c_enb3_s      cn52xx;
-    struct cvmx_npei_msi_w1c_enb3_s      cn56xx;
-} cvmx_npei_msi_w1c_enb3_t;
-
-
-/**
- * cvmx_npei_msi_w1s_enb0
- *
- * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0
- * 
- * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1s_enb0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
-                                                         cooresponding bit in NPEI_MSI_ENB0.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t set                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1s_enb0_s      cn52xx;
-    struct cvmx_npei_msi_w1s_enb0_s      cn56xx;
-} cvmx_npei_msi_w1s_enb0_t;
-
-
-/**
- * cvmx_npei_msi_w1s_enb1
- *
- * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1
- * 
- * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1s_enb1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
-                                                         cooresponding bit in NPEI_MSI_ENB1.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t set                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1s_enb1_s      cn52xx;
-    struct cvmx_npei_msi_w1s_enb1_s      cn56xx;
-} cvmx_npei_msi_w1s_enb1_t;
-
-
-/**
- * cvmx_npei_msi_w1s_enb2
- *
- * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2
- * 
- * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1s_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
-                                                         cooresponding bit in NPEI_MSI_ENB2.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t set                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1s_enb2_s      cn52xx;
-    struct cvmx_npei_msi_w1s_enb2_s      cn56xx;
-} cvmx_npei_msi_w1s_enb2_t;
-
-
-/**
- * cvmx_npei_msi_w1s_enb3
- *
- * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3
- * 
- * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_w1s_enb3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
-                                                         cooresponding bit in NPEI_MSI_ENB3.
-                                                         A read to this address will return 0. */
-#else
-        uint64_t set                     : 64;
-#endif
-    } s;
-    struct cvmx_npei_msi_w1s_enb3_s      cn52xx;
-    struct cvmx_npei_msi_w1s_enb3_s      cn56xx;
-} cvmx_npei_msi_w1s_enb3_t;
-
-
-/**
- * cvmx_npei_msi_wr_map
- *
- * NPEI_MSI_WR_MAP = NPEI MSI Write MAP
- * 
- * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_msi_wr_map_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ciu_int                 : 8;       /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
-                                                         will be set when the value specified in the
-                                                         MSI_INT of this register is recevied during a
-                                                         write to the NPEI_PCIE_MSI_RCV register. */
-        uint64_t msi_int                 : 8;       /**< Selects the value that would be received when the
-                                                         NPEI_PCIE_MSI_RCV register is written. */
-#else
-        uint64_t msi_int                 : 8;
-        uint64_t ciu_int                 : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npei_msi_wr_map_s        cn52xx;
-    struct cvmx_npei_msi_wr_map_s        cn52xxp1;
-    struct cvmx_npei_msi_wr_map_s        cn56xx;
-    struct cvmx_npei_msi_wr_map_s        cn56xxp1;
-} cvmx_npei_msi_wr_map_t;
-
-
-/**
- * cvmx_npei_pcie_credit_cnt
- *
- * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count
- * 
- * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic
- * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two
- * PCIE ports to be reset to the value in this register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pcie_credit_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t p1_ccnt                 : 8;       /**< Port1 C-TLP FIFO Credits.
-                                                         Legal values are 0x25 to 0x80. */
-        uint64_t p1_ncnt                 : 8;       /**< Port1 N-TLP FIFO Credits.
-                                                         Legal values are 0x5 to 0x10. */
-        uint64_t p1_pcnt                 : 8;       /**< Port1 P-TLP FIFO Credits.
-                                                         Legal values are 0x25 to 0x80. */
-        uint64_t p0_ccnt                 : 8;       /**< Port0 C-TLP FIFO Credits.
-                                                         Legal values are 0x25 to 0x80. */
-        uint64_t p0_ncnt                 : 8;       /**< Port0 N-TLP FIFO Credits.
-                                                         Legal values are 0x5 to 0x10. */
-        uint64_t p0_pcnt                 : 8;       /**< Port0 P-TLP FIFO Credits.
-                                                         Legal values are 0x25 to 0x80. */
-#else
-        uint64_t p0_pcnt                 : 8;
-        uint64_t p0_ncnt                 : 8;
-        uint64_t p0_ccnt                 : 8;
-        uint64_t p1_pcnt                 : 8;
-        uint64_t p1_ncnt                 : 8;
-        uint64_t p1_ccnt                 : 8;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_npei_pcie_credit_cnt_s   cn52xx;
-    struct cvmx_npei_pcie_credit_cnt_s   cn56xx;
-} cvmx_npei_pcie_credit_cnt_t;
-
-
-/**
- * cvmx_npei_pcie_msi_rcv
- *
- * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive
- * 
- * Register where MSI writes are directed from the PCIe.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pcie_msi_rcv_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
-                                                         one of the NPEI_MSI_RCV# registers being set.
-                                                         Which bit is set is dependent on the previously
-                                                         written using the NPEI_MSI_WR_MAP register or if
-                                                         not previously written the reset value of the MAP. */
-#else
-        uint64_t intr                    : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_npei_pcie_msi_rcv_s      cn52xx;
-    struct cvmx_npei_pcie_msi_rcv_s      cn52xxp1;
-    struct cvmx_npei_pcie_msi_rcv_s      cn56xx;
-    struct cvmx_npei_pcie_msi_rcv_s      cn56xxp1;
-} cvmx_npei_pcie_msi_rcv_t;
-
-
-/**
- * cvmx_npei_pcie_msi_rcv_b1
- *
- * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1
- * 
- * Register where MSI writes are directed from the PCIe.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pcie_msi_rcv_b1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
-                                                         one of the NPEI_MSI_RCV# registers being set.
-                                                         Which bit is set is dependent on the previously
-                                                         written using the NPEI_MSI_WR_MAP register or if
-                                                         not previously written the reset value of the MAP. */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t intr                    : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npei_pcie_msi_rcv_b1_s   cn52xx;
-    struct cvmx_npei_pcie_msi_rcv_b1_s   cn52xxp1;
-    struct cvmx_npei_pcie_msi_rcv_b1_s   cn56xx;
-    struct cvmx_npei_pcie_msi_rcv_b1_s   cn56xxp1;
-} cvmx_npei_pcie_msi_rcv_b1_t;
-
-
-/**
- * cvmx_npei_pcie_msi_rcv_b2
- *
- * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2
- * 
- * Register where MSI writes are directed from the PCIe.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pcie_msi_rcv_b2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
-                                                         one of the NPEI_MSI_RCV# registers being set.
-                                                         Which bit is set is dependent on the previously
-                                                         written using the NPEI_MSI_WR_MAP register or if
-                                                         not previously written the reset value of the MAP. */
-        uint64_t reserved_0_15           : 16;
-#else
-        uint64_t reserved_0_15           : 16;
-        uint64_t intr                    : 8;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_npei_pcie_msi_rcv_b2_s   cn52xx;
-    struct cvmx_npei_pcie_msi_rcv_b2_s   cn52xxp1;
-    struct cvmx_npei_pcie_msi_rcv_b2_s   cn56xx;
-    struct cvmx_npei_pcie_msi_rcv_b2_s   cn56xxp1;
-} cvmx_npei_pcie_msi_rcv_b2_t;
-
-
-/**
- * cvmx_npei_pcie_msi_rcv_b3
- *
- * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3
- * 
- * Register where MSI writes are directed from the PCIe.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pcie_msi_rcv_b3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
-                                                         one of the NPEI_MSI_RCV# registers being set.
-                                                         Which bit is set is dependent on the previously
-                                                         written using the NPEI_MSI_WR_MAP register or if
-                                                         not previously written the reset value of the MAP. */
-        uint64_t reserved_0_23           : 24;
-#else
-        uint64_t reserved_0_23           : 24;
-        uint64_t intr                    : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pcie_msi_rcv_b3_s   cn52xx;
-    struct cvmx_npei_pcie_msi_rcv_b3_s   cn52xxp1;
-    struct cvmx_npei_pcie_msi_rcv_b3_s   cn56xx;
-    struct cvmx_npei_pcie_msi_rcv_b3_s   cn56xxp1;
-} cvmx_npei_pcie_msi_rcv_b3_t;
-
-
-/**
- * cvmx_npei_pkt#_cnts
- *
- * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts
- * 
- * The counters for output rings.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_cnts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_54_63          : 10;
-        uint64_t timer                   : 22;      /**< Timer incremented every 1024 core clocks
-                                                         when NPEI_PKTS#_CNTS[CNT] is non zero. Field
-                                                         cleared when NPEI_PKTS#_CNTS[CNT] goes to 0.
-                                                         Field is also cleared when NPEI_PKT_TIME_INT is
-                                                         cleared.
-                                                         The first increment of this count can occur
-                                                         between 0 to 1023 core clocks. */
-        uint64_t cnt                     : 32;      /**< ring counter. This field is incremented as
-                                                         packets are sent out and decremented in response to
-                                                         writes to this field.
-                                                         When NPEI_PKT_OUT_BMODE is '0' a value of 1 is
-                                                         added to the register for each packet, when '1'
-                                                         and the info-pointer is NOT used the length of the
-                                                         packet plus 8 is added, when '1' and info-pointer
-                                                         mode IS used the packet length is added to this
-                                                         field. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t timer                   : 22;
-        uint64_t reserved_54_63          : 10;
-#endif
-    } s;
-    struct cvmx_npei_pktx_cnts_s         cn52xx;
-    struct cvmx_npei_pktx_cnts_s         cn56xx;
-} cvmx_npei_pktx_cnts_t;
-
-
-/**
- * cvmx_npei_pkt#_in_bp
- *
- * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure
- * 
- * The counters and thresholds for input packets to apply backpressure to processing of the packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_in_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t wmark                   : 32;      /**< When CNT is greater than this threshold no more
-                                                         packets will be processed for this ring.
-                                                         When writing this field of the NPEI_PKT#_IN_BP
-                                                         register, use a 4-byte write so as to not write
-                                                         any other field of this register. */
-        uint64_t cnt                     : 32;      /**< ring counter. This field is incremented by one
-                                                         whenever OCTEON receives, buffers, and creates a
-                                                         work queue entry for a packet that arrives by the
-                                                         cooresponding input ring. A write to this field
-                                                         will be subtracted from the field value.
-                                                         When writing this field of the NPEI_PKT#_IN_BP
-                                                         register, use a 4-byte write so as to not write
-                                                         any other field of this register. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t wmark                   : 32;
-#endif
-    } s;
-    struct cvmx_npei_pktx_in_bp_s        cn52xx;
-    struct cvmx_npei_pktx_in_bp_s        cn56xx;
-} cvmx_npei_pktx_in_bp_t;
-
-
-/**
- * cvmx_npei_pkt#_instr_baddr
- *
- * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address
- * 
- * Start of Instruction for input packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_instr_baddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 61;      /**< Base address for Instructions. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t addr                    : 61;
-#endif
-    } s;
-    struct cvmx_npei_pktx_instr_baddr_s  cn52xx;
-    struct cvmx_npei_pktx_instr_baddr_s  cn56xx;
-} cvmx_npei_pktx_instr_baddr_t;
-
-
-/**
- * cvmx_npei_pkt#_instr_baoff_dbell
- *
- * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell
- * 
- * The doorbell and base address offset for next read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_instr_baoff_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t aoff                    : 32;      /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
-                                                         where the next instruction will be read. */
-        uint64_t dbell                   : 32;      /**< Instruction doorbell count. Writes to this field
-                                                         will increment the value here. Reads will return
-                                                         present value. A write of 0xffffffff will set the
-                                                         DBELL and AOFF fields to '0'. */
-#else
-        uint64_t dbell                   : 32;
-        uint64_t aoff                    : 32;
-#endif
-    } s;
-    struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
-    struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
-} cvmx_npei_pktx_instr_baoff_dbell_t;
-
-
-/**
- * cvmx_npei_pkt#_instr_fifo_rsize
- *
- * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size.
- * 
- * Fifo field and ring size for Instructions.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_instr_fifo_rsize_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t max                     : 9;       /**< Max Fifo Size. */
-        uint64_t rrp                     : 9;       /**< Fifo read pointer. */
-        uint64_t wrp                     : 9;       /**< Fifo write pointer. */
-        uint64_t fcnt                    : 5;       /**< Fifo count. */
-        uint64_t rsize                   : 32;      /**< Instruction ring size. */
-#else
-        uint64_t rsize                   : 32;
-        uint64_t fcnt                    : 5;
-        uint64_t wrp                     : 9;
-        uint64_t rrp                     : 9;
-        uint64_t max                     : 9;
-#endif
-    } s;
-    struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
-    struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
-} cvmx_npei_pktx_instr_fifo_rsize_t;
-
-
-/**
- * cvmx_npei_pkt#_instr_header
- *
- * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header.
- * 
- * VAlues used to build input packet header.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_instr_header_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
-        uint64_t reserved_38_42          : 5;
-        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
-        uint64_t reserved_35_35          : 1;
-        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
-        uint64_t reserved_22_27          : 6;
-        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
-                                                         USE_IHDR must be set whenever PBP is set. */
-        uint64_t reserved_16_20          : 5;
-        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t reserved_13_13          : 1;
-        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t reserved_0_5            : 6;
-#else
-        uint64_t reserved_0_5            : 6;
-        uint64_t skp_len                 : 7;
-        uint64_t reserved_13_13          : 1;
-        uint64_t par_mode                : 2;
-        uint64_t reserved_16_20          : 5;
-        uint64_t use_ihdr                : 1;
-        uint64_t reserved_22_27          : 6;
-        uint64_t rskp_len                : 7;
-        uint64_t reserved_35_35          : 1;
-        uint64_t rparmode                : 2;
-        uint64_t reserved_38_42          : 5;
-        uint64_t pbp                     : 1;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npei_pktx_instr_header_s cn52xx;
-    struct cvmx_npei_pktx_instr_header_s cn56xx;
-} cvmx_npei_pktx_instr_header_t;
-
-
-/**
- * cvmx_npei_pkt#_slist_baddr
- *
- * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address
- * 
- * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_slist_baddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 60;      /**< Base address for scatter list pointers. */
-        uint64_t reserved_0_3            : 4;
-#else
-        uint64_t reserved_0_3            : 4;
-        uint64_t addr                    : 60;
-#endif
-    } s;
-    struct cvmx_npei_pktx_slist_baddr_s  cn52xx;
-    struct cvmx_npei_pktx_slist_baddr_s  cn56xx;
-} cvmx_npei_pktx_slist_baddr_t;
-
-
-/**
- * cvmx_npei_pkt#_slist_baoff_dbell
- *
- * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell
- * 
- * The doorbell and base address offset for next read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_slist_baoff_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t aoff                    : 32;      /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
-                                                         where the next SList pointer will be read.
-                                                         A write of 0xFFFFFFFF to the DBELL field will
-                                                         clear DBELL and AOFF */
-        uint64_t dbell                   : 32;      /**< Scatter list doorbell count. Writes to this field
-                                                         will increment the value here. Reads will return
-                                                         present value. The value of this field is
-                                                         decremented as read operations are ISSUED for
-                                                         scatter pointers.
-                                                         A write of 0xFFFFFFFF will clear DBELL and AOFF */
-#else
-        uint64_t dbell                   : 32;
-        uint64_t aoff                    : 32;
-#endif
-    } s;
-    struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
-    struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
-} cvmx_npei_pktx_slist_baoff_dbell_t;
-
-
-/**
- * cvmx_npei_pkt#_slist_fifo_rsize
- *
- * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size.
- * 
- * The number of scatter pointer pairs in the scatter list.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pktx_slist_fifo_rsize_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rsize                   : 32;      /**< The number of scatter pointer pairs contained in
-                                                         the scatter list ring. */
-#else
-        uint64_t rsize                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
-    struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
-} cvmx_npei_pktx_slist_fifo_rsize_t;
-
-
-/**
- * cvmx_npei_pkt_cnt_int
- *
- * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt
- * 
- * The packets rings that are interrupting because of Packet Counters.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_cnt_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number is set when
-                                                         NPEI_PKT#_CNTS[CNT] is greater
-                                                         than NPEI_PKT_INT_LEVELS[CNT]. */
-#else
-        uint64_t port                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_cnt_int_s       cn52xx;
-    struct cvmx_npei_pkt_cnt_int_s       cn56xx;
-} cvmx_npei_pkt_cnt_int_t;
-
-
-/**
- * cvmx_npei_pkt_cnt_int_enb
- *
- * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable
- * 
- * Enable for the packets rings that are interrupting because of Packet Counters.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_cnt_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number when set
-                                                         allows NPEI_PKT_CNT_INT to generate an interrupt. */
-#else
-        uint64_t port                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_cnt_int_enb_s   cn52xx;
-    struct cvmx_npei_pkt_cnt_int_enb_s   cn56xx;
-} cvmx_npei_pkt_cnt_int_enb_t;
-
-
-/**
- * cvmx_npei_pkt_data_out_es
- *
- * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap
- * 
- * The Endian Swap for writing Data Out.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_data_out_es_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t es                      : 64;      /**< The endian swap mode for Packet rings 0 through 31.
-                                                         Two bits are used per ring (i.e. ring 0 [1:0],
-                                                         ring 1 [3:2], ....). */
-#else
-        uint64_t es                      : 64;
-#endif
-    } s;
-    struct cvmx_npei_pkt_data_out_es_s   cn52xx;
-    struct cvmx_npei_pkt_data_out_es_s   cn56xx;
-} cvmx_npei_pkt_data_out_es_t;
-
-
-/**
- * cvmx_npei_pkt_data_out_ns
- *
- * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop
- * 
- * The NS field for the TLP when writing packet data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_data_out_ns_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nsr                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will enable NS in TLP header. */
-#else
-        uint64_t nsr                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_data_out_ns_s   cn52xx;
-    struct cvmx_npei_pkt_data_out_ns_s   cn56xx;
-} cvmx_npei_pkt_data_out_ns_t;
-
-
-/**
- * cvmx_npei_pkt_data_out_ror
- *
- * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering
- * 
- * The ROR field for the TLP when writing Packet Data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_data_out_ror_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ror                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will enable ROR in TLP header. */
-#else
-        uint64_t ror                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_data_out_ror_s  cn52xx;
-    struct cvmx_npei_pkt_data_out_ror_s  cn56xx;
-} cvmx_npei_pkt_data_out_ror_t;
-
-
-/**
- * cvmx_npei_pkt_dpaddr
- *
- * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr
- * 
- * Used to detemine address and attributes for packet data writes.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_dpaddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dptr                    : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will use:
-                                                         the address[63:60] to write packet data
-                                                         comes from the DPTR[63:60] in the scatter-list
-                                                         pair and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. */
-#else
-        uint64_t dptr                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_dpaddr_s        cn52xx;
-    struct cvmx_npei_pkt_dpaddr_s        cn56xx;
-} cvmx_npei_pkt_dpaddr_t;
-
-
-/**
- * cvmx_npei_pkt_in_bp
- *
- * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure
- * 
- * Which input rings have backpressure applied.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_in_bp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bp                      : 32;      /**< A packet input  ring that has its count greater
-                                                         than its WMARK will have backpressure applied.
-                                                         Each of the 32 bits coorespond to an input ring.
-                                                         When '1' that ring has backpressure applied an
-                                                         will fetch no more instructions, but will process
-                                                         any previously fetched instructions. */
-#else
-        uint64_t bp                      : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_in_bp_s         cn52xx;
-    struct cvmx_npei_pkt_in_bp_s         cn56xx;
-} cvmx_npei_pkt_in_bp_t;
-
-
-/**
- * cvmx_npei_pkt_in_done#_cnts
- *
- * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts
- * 
- * Counters for instructions completed on Input rings.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_in_donex_cnts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< This field is incrmented by '1' when an instruction
-                                                         is completed. This field is incremented as the
-                                                         last of the data is read from the PCIe. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
-    struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
-} cvmx_npei_pkt_in_donex_cnts_t;
-
-
-/**
- * cvmx_npei_pkt_in_instr_counts
- *
- * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts
- * 
- * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_in_instr_counts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t wr_cnt                  : 32;      /**< Shows the number of packets sent to the IPD. */
-        uint64_t rd_cnt                  : 32;      /**< Shows the value of instructions that have had reads
-                                                         issued for them.
-                                                         to the Packet-ring is in reset. */
-#else
-        uint64_t rd_cnt                  : 32;
-        uint64_t wr_cnt                  : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
-    struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
-} cvmx_npei_pkt_in_instr_counts_t;
-
-
-/**
- * cvmx_npei_pkt_in_pcie_port
- *
- * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment
- * 
- * Assigns Packet Input rings to PCIe ports.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_in_pcie_port_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pp                      : 64;      /**< The PCIe port that the Packet ring number is
-                                                         assigned. Two bits are used per ring (i.e. ring 0
-                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
-                                                         that the Packetring is assign to PCIe Port 0, a '1'
-                                                         PCIe Port 1, '2' and '3' are reserved. */
-#else
-        uint64_t pp                      : 64;
-#endif
-    } s;
-    struct cvmx_npei_pkt_in_pcie_port_s  cn52xx;
-    struct cvmx_npei_pkt_in_pcie_port_s  cn56xx;
-} cvmx_npei_pkt_in_pcie_port_t;
-
-
-/**
- * cvmx_npei_pkt_input_control
- *
- * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control
- * 
- * Control for reads for gather list and instructions.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_input_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t pkt_rr                  : 1;       /**< When set '1' the input packet selection will be
-                                                         made with a Round Robin arbitration. When '0'
-                                                         the input packet ring is fixed in priority,
-                                                         where the lower ring number has higher priority. */
-        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
-                                                         calculating a DPTR. */
-        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather data. */
-        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather data. */
-        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather data. */
-        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
-                                                         ROR, ESR, and NSR. When clear '0' the value in
-                                                         DPTR will be used. In turn the bits not used for
-                                                         ROR, ESR, and NSR, will be used for bits [63:60]
-                                                         of the address used to fetch packet data. */
-        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather list and gather instruction. */
-        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather list and gather instruction. */
-        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather list and gather instruction. */
-#else
-        uint64_t ror                     : 1;
-        uint64_t esr                     : 2;
-        uint64_t nsr                     : 1;
-        uint64_t use_csr                 : 1;
-        uint64_t d_ror                   : 1;
-        uint64_t d_esr                   : 2;
-        uint64_t d_nsr                   : 1;
-        uint64_t pbp_dhi                 : 13;
-        uint64_t pkt_rr                  : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_npei_pkt_input_control_s cn52xx;
-    struct cvmx_npei_pkt_input_control_s cn56xx;
-} cvmx_npei_pkt_input_control_t;
-
-
-/**
- * cvmx_npei_pkt_instr_enb
- *
- * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable
- * 
- * Enables the instruction fetch for a Packet-ring.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_instr_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t enb                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring is enabled. */
-#else
-        uint64_t enb                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_instr_enb_s     cn52xx;
-    struct cvmx_npei_pkt_instr_enb_s     cn56xx;
-} cvmx_npei_pkt_instr_enb_t;
-
-
-/**
- * cvmx_npei_pkt_instr_rd_size
- *
- * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size
- * 
- * The number of instruction allowed to be read at one time.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_instr_rd_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t rdsize                  : 64;      /**< Number of instructions to be read in one PCIe read
-                                                         request for the 4 PKOport - 8 rings. Every two bits
-                                                         (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
-                                                         combinations.
-                                                         - 15:0  PKOPort0,Ring 7..0  31:16 PKOPort1,Ring 7..0
-                                                         - 47:32 PKOPort2,Ring 7..0  63:48 PKOPort3,Ring 7..0
-                                                         Two bit value are:
-                                                         0 - 1 Instruction
-                                                         1 - 2 Instructions
-                                                         2 - 3 Instructions
-                                                         3 - 4 Instructions */
-#else
-        uint64_t rdsize                  : 64;
-#endif
-    } s;
-    struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
-    struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
-} cvmx_npei_pkt_instr_rd_size_t;
-
-
-/**
- * cvmx_npei_pkt_instr_size
- *
- * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size
- * 
- * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_instr_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t is_64b                  : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring is a 64-byte instruction. */
-#else
-        uint64_t is_64b                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_instr_size_s    cn52xx;
-    struct cvmx_npei_pkt_instr_size_s    cn56xx;
-} cvmx_npei_pkt_instr_size_t;
-
-
-/**
- * cvmx_npei_pkt_int_levels
- *
- * 0x90F0 reserved NPEI_PKT_PCIE_PORT2
- * 
- * 
- *                  NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels
- * 
- * Output packet interrupt levels.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_int_levels_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_54_63          : 10;
-        uint64_t time                    : 22;      /**< When NPEI_PKT#_CNTS[TIME] is equal to this value
-                                                         an interrupt is generated. */
-        uint64_t cnt                     : 32;      /**< When NPEI_PKT#_CNTS[CNT] becomes
-                                                         greater than this value an interrupt is generated. */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t time                    : 22;
-        uint64_t reserved_54_63          : 10;
-#endif
-    } s;
-    struct cvmx_npei_pkt_int_levels_s    cn52xx;
-    struct cvmx_npei_pkt_int_levels_s    cn56xx;
-} cvmx_npei_pkt_int_levels_t;
-
-
-/**
- * cvmx_npei_pkt_iptr
- *
- * NPEI_PKT_IPTR = NPEI's Packet Info Poitner
- * 
- * Controls using the Info-Pointer to store length and data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_iptr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iptr                    : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will use the Info-Pointer to
-                                                         store length and data. */
-#else
-        uint64_t iptr                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_iptr_s          cn52xx;
-    struct cvmx_npei_pkt_iptr_s          cn56xx;
-} cvmx_npei_pkt_iptr_t;
-
-
-/**
- * cvmx_npei_pkt_out_bmode
- *
- * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode
- * 
- * Control the updating of the NPEI_PKT#_CNT register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_out_bmode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t bmode                   : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will have its NPEI_PKT#_CNT
-                                                         register updated with the number of bytes in the
-                                                         packet sent, when '0' the register will have a
-                                                         value of '1' added. */
-#else
-        uint64_t bmode                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_out_bmode_s     cn52xx;
-    struct cvmx_npei_pkt_out_bmode_s     cn56xx;
-} cvmx_npei_pkt_out_bmode_t;
-
-
-/**
- * cvmx_npei_pkt_out_enb
- *
- * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable
- * 
- * Enables the output packet engines.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_out_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t enb                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring is enabled.
-                                                         If an error occurs on reading pointers for an
-                                                         output ring, the ring will be disabled by clearing
-                                                         the bit associated with the ring to '0'. */
-#else
-        uint64_t enb                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_out_enb_s       cn52xx;
-    struct cvmx_npei_pkt_out_enb_s       cn56xx;
-} cvmx_npei_pkt_out_enb_t;
-
-
-/**
- * cvmx_npei_pkt_output_wmark
- *
- * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark
- * 
- * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_output_wmark_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wmark                   : 32;      /**< Value when DBELL count drops below backpressure
-                                                         for the ring will be applied to the PKO. */
-#else
-        uint64_t wmark                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_output_wmark_s  cn52xx;
-    struct cvmx_npei_pkt_output_wmark_s  cn56xx;
-} cvmx_npei_pkt_output_wmark_t;
-
-
-/**
- * cvmx_npei_pkt_pcie_port
- *
- * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment
- * 
- * Assigns Packet Ports to PCIe ports.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_pcie_port_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pp                      : 64;      /**< The PCIe port that the Packet ring number is
-                                                         assigned. Two bits are used per ring (i.e. ring 0
-                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
-                                                         that the Packetring is assign to PCIe Port 0, a '1'
-                                                         PCIe Port 1, '2' and '3' are reserved. */
-#else
-        uint64_t pp                      : 64;
-#endif
-    } s;
-    struct cvmx_npei_pkt_pcie_port_s     cn52xx;
-    struct cvmx_npei_pkt_pcie_port_s     cn56xx;
-} cvmx_npei_pkt_pcie_port_t;
-
-
-/**
- * cvmx_npei_pkt_port_in_rst
- *
- * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset
- * 
- * Vector bits related to ring-port for ones that are reset.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_port_in_rst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t in_rst                  : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the inbound Packet-ring is in reset. */
-        uint64_t out_rst                 : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the outbound Packet-ring is in reset. */
-#else
-        uint64_t out_rst                 : 32;
-        uint64_t in_rst                  : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_port_in_rst_s   cn52xx;
-    struct cvmx_npei_pkt_port_in_rst_s   cn56xx;
-} cvmx_npei_pkt_port_in_rst_t;
-
-
-/**
- * cvmx_npei_pkt_slist_es
- *
- * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap
- * 
- * The Endian Swap for Scatter List Read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_slist_es_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t es                      : 64;      /**< The endian swap mode for Packet rings 0 through 31.
-                                                         Two bits are used per ring (i.e. ring 0 [1:0],
-                                                         ring 1 [3:2], ....). */
-#else
-        uint64_t es                      : 64;
-#endif
-    } s;
-    struct cvmx_npei_pkt_slist_es_s      cn52xx;
-    struct cvmx_npei_pkt_slist_es_s      cn56xx;
-} cvmx_npei_pkt_slist_es_t;
-
-
-/**
- * cvmx_npei_pkt_slist_id_size
- *
- * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size
- * 
- * The Size of the information and data fields pointed to by Scatter List pointers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_slist_id_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t isize                   : 7;       /**< Information size. Legal sizes are 0 to 120. */
-        uint64_t bsize                   : 16;      /**< Data size. */
-#else
-        uint64_t bsize                   : 16;
-        uint64_t isize                   : 7;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_npei_pkt_slist_id_size_s cn52xx;
-    struct cvmx_npei_pkt_slist_id_size_s cn56xx;
-} cvmx_npei_pkt_slist_id_size_t;
-
-
-/**
- * cvmx_npei_pkt_slist_ns
- *
- * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop
- * 
- * The NS field for the TLP when fetching Scatter List.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_slist_ns_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t nsr                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will enable NS in TLP header. */
-#else
-        uint64_t nsr                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_slist_ns_s      cn52xx;
-    struct cvmx_npei_pkt_slist_ns_s      cn56xx;
-} cvmx_npei_pkt_slist_ns_t;
-
-
-/**
- * cvmx_npei_pkt_slist_ror
- *
- * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering
- * 
- * The ROR field for the TLP when fetching Scatter List.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_slist_ror_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ror                     : 32;      /**< When asserted '1' the vector bit cooresponding
-                                                         to the Packet-ring will enable ROR in TLP header. */
-#else
-        uint64_t ror                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_slist_ror_s     cn52xx;
-    struct cvmx_npei_pkt_slist_ror_s     cn56xx;
-} cvmx_npei_pkt_slist_ror_t;
-
-
-/**
- * cvmx_npei_pkt_time_int
- *
- * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt
- * 
- * The packets rings that are interrupting because of Packet Timers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_time_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number is set when
-                                                         NPEI_PKT#_CNTS[TIMER] is greater than
-                                                         NPEI_PKT_INT_LEVELS[TIME]. */
-#else
-        uint64_t port                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_time_int_s      cn52xx;
-    struct cvmx_npei_pkt_time_int_s      cn56xx;
-} cvmx_npei_pkt_time_int_t;
-
-
-/**
- * cvmx_npei_pkt_time_int_enb
- *
- * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable
- * 
- * The packets rings that are interrupting because of Packet Timers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_pkt_time_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number when set
-                                                         allows NPEI_PKT_TIME_INT to generate an interrupt. */
-#else
-        uint64_t port                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_pkt_time_int_enb_s  cn52xx;
-    struct cvmx_npei_pkt_time_int_enb_s  cn56xx;
-} cvmx_npei_pkt_time_int_enb_t;
-
-
-/**
- * cvmx_npei_rsl_int_blocks
- *
- * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register
- * 
- * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
- * that presently has an interrupt pending. The Field Description below supplies the name of the
- * register that software should read to find out why that intterupt bit is set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_rsl_int_blocks_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
-        uint64_t lmc1                    : 1;       /**< LMC1_MEM_CFG0 */
-        uint64_t agl                     : 1;       /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */
-        uint64_t reserved_24_27          : 4;
-        uint64_t asxpcs1                 : 1;       /**< PCS1_INT*_REG */
-        uint64_t asxpcs0                 : 1;       /**< PCS0_INT*_REG */
-        uint64_t reserved_21_21          : 1;
-        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
-        uint64_t spx1                    : 1;       /**< Always reads as zero */
-        uint64_t spx0                    : 1;       /**< Always reads as zero */
-        uint64_t lmc0                    : 1;       /**< LMC0_MEM_CFG0 */
-        uint64_t l2c                     : 1;       /**< L2C_INT_STAT */
-        uint64_t usb1                    : 1;       /**< Always reads as zero */
-        uint64_t rad                     : 1;       /**< RAD_REG_ERROR */
-        uint64_t usb                     : 1;       /**< USBN0_INT_SUM */
-        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
-        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
-        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
-        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
-        uint64_t reserved_8_8            : 1;
-        uint64_t zip                     : 1;       /**< ZIP_ERROR */
-        uint64_t dfa                     : 1;       /**< Always reads as zero */
-        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
-        uint64_t key                     : 1;       /**< KEY_INT_SUM */
-        uint64_t npei                    : 1;       /**< NPEI_INT_SUM */
-        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
-        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
-        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
-#else
-        uint64_t mio                     : 1;
-        uint64_t gmx0                    : 1;
-        uint64_t gmx1                    : 1;
-        uint64_t npei                    : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t ipd                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t tim                     : 1;
-        uint64_t pow                     : 1;
-        uint64_t usb                     : 1;
-        uint64_t rad                     : 1;
-        uint64_t usb1                    : 1;
-        uint64_t l2c                     : 1;
-        uint64_t lmc0                    : 1;
-        uint64_t spx0                    : 1;
-        uint64_t spx1                    : 1;
-        uint64_t pip                     : 1;
-        uint64_t reserved_21_21          : 1;
-        uint64_t asxpcs0                 : 1;
-        uint64_t asxpcs1                 : 1;
-        uint64_t reserved_24_27          : 4;
-        uint64_t agl                     : 1;
-        uint64_t lmc1                    : 1;
-        uint64_t iob                     : 1;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_npei_rsl_int_blocks_s    cn52xx;
-    struct cvmx_npei_rsl_int_blocks_s    cn52xxp1;
-    struct cvmx_npei_rsl_int_blocks_s    cn56xx;
-    struct cvmx_npei_rsl_int_blocks_s    cn56xxp1;
-} cvmx_npei_rsl_int_blocks_t;
-
-
-/**
- * cvmx_npei_scratch_1
- *
- * NPEI_SCRATCH_1 = NPEI's Scratch 1
- * 
- * A general purpose 64 bit register for SW use.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_scratch_1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< The value in this register is totaly SW dependent. */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_npei_scratch_1_s         cn52xx;
-    struct cvmx_npei_scratch_1_s         cn52xxp1;
-    struct cvmx_npei_scratch_1_s         cn56xx;
-    struct cvmx_npei_scratch_1_s         cn56xxp1;
-} cvmx_npei_scratch_1_t;
-
-
-/**
- * cvmx_npei_state1
- *
- * NPEI_STATE1 = NPEI State 1
- * 
- * State machines in NPEI. For debug.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_state1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cpl1                    : 12;      /**< CPL1 State */
-        uint64_t cpl0                    : 12;      /**< CPL0 State */
-        uint64_t arb                     : 1;       /**< ARB State */
-        uint64_t csr                     : 39;      /**< CSR State */
-#else
-        uint64_t csr                     : 39;
-        uint64_t arb                     : 1;
-        uint64_t cpl0                    : 12;
-        uint64_t cpl1                    : 12;
-#endif
-    } s;
-    struct cvmx_npei_state1_s            cn52xx;
-    struct cvmx_npei_state1_s            cn52xxp1;
-    struct cvmx_npei_state1_s            cn56xx;
-    struct cvmx_npei_state1_s            cn56xxp1;
-} cvmx_npei_state1_t;
-
-
-/**
- * cvmx_npei_state2
- *
- * NPEI_STATE2 = NPEI State 2
- * 
- * State machines in NPEI. For debug.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_state2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t npei                    : 1;       /**< NPEI State */
-        uint64_t rac                     : 1;       /**< RAC State */
-        uint64_t csm1                    : 15;      /**< CSM1 State */
-        uint64_t csm0                    : 15;      /**< CSM0 State */
-        uint64_t nnp0                    : 8;       /**< NNP0 State */
-        uint64_t nnd                     : 8;       /**< NND State */
-#else
-        uint64_t nnd                     : 8;
-        uint64_t nnp0                    : 8;
-        uint64_t csm0                    : 15;
-        uint64_t csm1                    : 15;
-        uint64_t rac                     : 1;
-        uint64_t npei                    : 1;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_npei_state2_s            cn52xx;
-    struct cvmx_npei_state2_s            cn52xxp1;
-    struct cvmx_npei_state2_s            cn56xx;
-    struct cvmx_npei_state2_s            cn56xxp1;
-} cvmx_npei_state2_t;
-
-
-/**
- * cvmx_npei_state3
- *
- * NPEI_STATE3 = NPEI State 3
- * 
- * State machines in NPEI. For debug.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_state3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t psm1                    : 15;      /**< PSM1 State */
-        uint64_t psm0                    : 15;      /**< PSM0 State */
-        uint64_t nsm1                    : 13;      /**< NSM1 State */
-        uint64_t nsm0                    : 13;      /**< NSM0 State */
-#else
-        uint64_t nsm0                    : 13;
-        uint64_t nsm1                    : 13;
-        uint64_t psm0                    : 15;
-        uint64_t psm1                    : 15;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } s;
-    struct cvmx_npei_state3_s            cn52xx;
-    struct cvmx_npei_state3_s            cn52xxp1;
-    struct cvmx_npei_state3_s            cn56xx;
-    struct cvmx_npei_state3_s            cn56xxp1;
-} cvmx_npei_state3_t;
-
-
-/**
- * cvmx_npei_win_rd_addr
- *
- * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register
- * 
- * The address to be read when the NPEI_WIN_RD_DATA register is read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_win_rd_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_51_63          : 13;
-        uint64_t ld_cmd                  : 2;       /**< The load command sent wit hthe read.
-                                                         0x0 == Load 8-bytes, 0x1 == Load 4-bytes,
-                                                         0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t rd_addr                 : 48;      /**< The address to be read from. Whenever the LSB of
-                                                         this register is written, the Read Operation will
-                                                         take place.
-                                                         [47:40] = NCB_ID
-                                                         [39:0]  = Address
-                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
-                                                              [39:32] == x, Not Used
-                                                              [31:27] == RSL_ID
-                                                              [12:0]  == RSL Register Offset */
-#else
-        uint64_t rd_addr                 : 48;
-        uint64_t iobit                   : 1;
-        uint64_t ld_cmd                  : 2;
-        uint64_t reserved_51_63          : 13;
-#endif
-    } s;
-    struct cvmx_npei_win_rd_addr_s       cn52xx;
-    struct cvmx_npei_win_rd_addr_s       cn52xxp1;
-    struct cvmx_npei_win_rd_addr_s       cn56xx;
-    struct cvmx_npei_win_rd_addr_s       cn56xxp1;
-} cvmx_npei_win_rd_addr_t;
-
-
-/**
- * cvmx_npei_win_rd_data
- *
- * NPEI_WIN_RD_DATA = NPEI Window Read Data Register
- * 
- * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR
- * register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_win_rd_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t rd_data                 : 64;      /**< The read data. */
-#else
-        uint64_t rd_data                 : 64;
-#endif
-    } s;
-    struct cvmx_npei_win_rd_data_s       cn52xx;
-    struct cvmx_npei_win_rd_data_s       cn52xxp1;
-    struct cvmx_npei_win_rd_data_s       cn56xx;
-    struct cvmx_npei_win_rd_data_s       cn56xxp1;
-} cvmx_npei_win_rd_data_t;
-
-
-/**
- * cvmx_npei_win_wr_addr
- *
- * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register
- * 
- * Contains the address to be writen to when a write operation is started by writing the
- * NPEI_WIN_WR_DATA register (see below).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_win_wr_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t wr_addr                 : 46;      /**< The address that will be written to when the
-                                                         NPEI_WIN_WR_DATA register is written.
-                                                         [47:40] = NCB_ID
-                                                         [39:3]  = Address
-                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
-                                                              [39:32] == x, Not Used
-                                                              [31:27] == RSL_ID
-                                                              [12:2]  == RSL Register Offset
-                                                              [1:0]   == x, Not Used */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t wr_addr                 : 46;
-        uint64_t iobit                   : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_npei_win_wr_addr_s       cn52xx;
-    struct cvmx_npei_win_wr_addr_s       cn52xxp1;
-    struct cvmx_npei_win_wr_addr_s       cn56xx;
-    struct cvmx_npei_win_wr_addr_s       cn56xxp1;
-} cvmx_npei_win_wr_addr_t;
-
-
-/**
- * cvmx_npei_win_wr_data
- *
- * NPEI_WIN_WR_DATA = NPEI Window Write Data Register
- * 
- * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register.
- * Writing the least-significant-byte of this register will cause a write operation to take place.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_win_wr_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t wr_data                 : 64;      /**< The data to be written. Whenever the LSB of this
-                                                         register is written, the Window Write will take
-                                                         place. */
-#else
-        uint64_t wr_data                 : 64;
-#endif
-    } s;
-    struct cvmx_npei_win_wr_data_s       cn52xx;
-    struct cvmx_npei_win_wr_data_s       cn52xxp1;
-    struct cvmx_npei_win_wr_data_s       cn56xx;
-    struct cvmx_npei_win_wr_data_s       cn56xxp1;
-} cvmx_npei_win_wr_data_t;
-
-
-/**
- * cvmx_npei_win_wr_mask
- *
- * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register
- * 
- * Contains the mask for the data in the NPEI_WIN_WR_DATA Register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_win_wr_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t wr_mask                 : 8;       /**< The data to be written. When a bit is '0'
-                                                         the corresponding byte will be written. */
-#else
-        uint64_t wr_mask                 : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_npei_win_wr_mask_s       cn52xx;
-    struct cvmx_npei_win_wr_mask_s       cn52xxp1;
-    struct cvmx_npei_win_wr_mask_s       cn56xx;
-    struct cvmx_npei_win_wr_mask_s       cn56xxp1;
-} cvmx_npei_win_wr_mask_t;
-
-
-/**
- * cvmx_npei_window_ctl
- *
- * NPEI_WINDOW_CTL = NPEI's Window Control
- * 
- * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1.
- * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next
- * RML access will start, and interrupt will be set, and in the case of reads no data will be returned.
- * 
- * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
- * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npei_window_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t time                    : 32;      /**< Time to wait in core clocks to wait for a
-                                                         BAR0 access to completeon the NCB
-                                                         before timing out. A value of 0 will cause no
-                                                         timeouts. A minimum value of 0x200000 should be
-                                                         used when this register is not set to 0x0. */
-#else
-        uint64_t time                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npei_window_ctl_s        cn52xx;
-    struct cvmx_npei_window_ctl_s        cn52xxp1;
-    struct cvmx_npei_window_ctl_s        cn56xx;
-    struct cvmx_npei_window_ctl_s        cn56xxp1;
-} cvmx_npei_window_ctl_t;
-
-
-/**
- * cvmx_npi_base_addr_input#
- *
- * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register
- * 
- * The address to start reading Instructions from for Input-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_base_addr_inputx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t baddr                   : 61;      /**< The address to read Instruction from for output 0.
-                                                         This address is 8-byte aligned, for this reason
-                                                         address bits [2:0] will always be zero. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t baddr                   : 61;
-#endif
-    } s;
-    struct cvmx_npi_base_addr_inputx_s   cn30xx;
-    struct cvmx_npi_base_addr_inputx_s   cn31xx;
-    struct cvmx_npi_base_addr_inputx_s   cn38xx;
-    struct cvmx_npi_base_addr_inputx_s   cn38xxp2;
-    struct cvmx_npi_base_addr_inputx_s   cn50xx;
-    struct cvmx_npi_base_addr_inputx_s   cn58xx;
-    struct cvmx_npi_base_addr_inputx_s   cn58xxp1;
-} cvmx_npi_base_addr_inputx_t;
-
-
-/**
- * cvmx_npi_base_addr_output#
- *
- * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register
- * 
- * The address to start reading Instructions from for Output-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_base_addr_outputx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t baddr                   : 61;      /**< The address to read Instruction from for output 0.
-                                                         This address is 8-byte aligned, for this reason
-                                                         address bits [2:0] will always be zero. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t baddr                   : 61;
-#endif
-    } s;
-    struct cvmx_npi_base_addr_outputx_s  cn30xx;
-    struct cvmx_npi_base_addr_outputx_s  cn31xx;
-    struct cvmx_npi_base_addr_outputx_s  cn38xx;
-    struct cvmx_npi_base_addr_outputx_s  cn38xxp2;
-    struct cvmx_npi_base_addr_outputx_s  cn50xx;
-    struct cvmx_npi_base_addr_outputx_s  cn58xx;
-    struct cvmx_npi_base_addr_outputx_s  cn58xxp1;
-} cvmx_npi_base_addr_outputx_t;
-
-
-/**
- * cvmx_npi_bist_status
- *
- * NPI_BIST_STATUS = NPI's BIST Status Register
- * 
- * Results from BIST runs of NPI's memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
-        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
-        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
-        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
-        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
-        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
-        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
-        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
-        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
-        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
-        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
-        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
-        uint64_t pof1_bs                 : 1;       /**< BIST Status for the pof1_fifo */
-        uint64_t pof2_bs                 : 1;       /**< BIST Status for the pof2_fifo */
-        uint64_t pof3_bs                 : 1;       /**< BIST Status for the pof3_fifo */
-        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
-        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
-        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
-        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
-        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
-#else
-        uint64_t dpi_bs                  : 1;
-        uint64_t pdf_bs                  : 1;
-        uint64_t dob_bs                  : 1;
-        uint64_t nus_bs                  : 1;
-        uint64_t pos_bs                  : 1;
-        uint64_t pof3_bs                 : 1;
-        uint64_t pof2_bs                 : 1;
-        uint64_t pof1_bs                 : 1;
-        uint64_t pof0_bs                 : 1;
-        uint64_t pig_bs                  : 1;
-        uint64_t pgf_bs                  : 1;
-        uint64_t rdnl_bs                 : 1;
-        uint64_t pcad_bs                 : 1;
-        uint64_t pcac_bs                 : 1;
-        uint64_t rdn_bs                  : 1;
-        uint64_t pcn_bs                  : 1;
-        uint64_t pcnc_bs                 : 1;
-        uint64_t rdp_bs                  : 1;
-        uint64_t dif_bs                  : 1;
-        uint64_t csr_bs                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_npi_bist_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
-        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
-        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
-        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
-        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
-        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
-        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
-        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
-        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
-        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
-        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
-        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
-        uint64_t reserved_5_7            : 3;
-        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
-        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
-        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
-        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
-        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
-#else
-        uint64_t dpi_bs                  : 1;
-        uint64_t pdf_bs                  : 1;
-        uint64_t dob_bs                  : 1;
-        uint64_t nus_bs                  : 1;
-        uint64_t pos_bs                  : 1;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pof0_bs                 : 1;
-        uint64_t pig_bs                  : 1;
-        uint64_t pgf_bs                  : 1;
-        uint64_t rdnl_bs                 : 1;
-        uint64_t pcad_bs                 : 1;
-        uint64_t pcac_bs                 : 1;
-        uint64_t rdn_bs                  : 1;
-        uint64_t pcn_bs                  : 1;
-        uint64_t pcnc_bs                 : 1;
-        uint64_t rdp_bs                  : 1;
-        uint64_t dif_bs                  : 1;
-        uint64_t csr_bs                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn30xx;
-    struct cvmx_npi_bist_status_s        cn31xx;
-    struct cvmx_npi_bist_status_s        cn38xx;
-    struct cvmx_npi_bist_status_s        cn38xxp2;
-    struct cvmx_npi_bist_status_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
-        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
-        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
-        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
-        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
-        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
-        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
-        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
-        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
-        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
-        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
-        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
-        uint64_t pof1_bs                 : 1;       /**< BIST Status for the pof1_fifo */
-        uint64_t reserved_5_6            : 2;
-        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
-        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
-        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
-        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
-        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
-#else
-        uint64_t dpi_bs                  : 1;
-        uint64_t pdf_bs                  : 1;
-        uint64_t dob_bs                  : 1;
-        uint64_t nus_bs                  : 1;
-        uint64_t pos_bs                  : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t pof1_bs                 : 1;
-        uint64_t pof0_bs                 : 1;
-        uint64_t pig_bs                  : 1;
-        uint64_t pgf_bs                  : 1;
-        uint64_t rdnl_bs                 : 1;
-        uint64_t pcad_bs                 : 1;
-        uint64_t pcac_bs                 : 1;
-        uint64_t rdn_bs                  : 1;
-        uint64_t pcn_bs                  : 1;
-        uint64_t pcnc_bs                 : 1;
-        uint64_t rdp_bs                  : 1;
-        uint64_t dif_bs                  : 1;
-        uint64_t csr_bs                  : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn50xx;
-    struct cvmx_npi_bist_status_s        cn58xx;
-    struct cvmx_npi_bist_status_s        cn58xxp1;
-} cvmx_npi_bist_status_t;
-
-
-/**
- * cvmx_npi_buff_size_output#
- *
- * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0
- * 
- * The size in bytes of the Data Bufffer and Information Buffer for output 0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_buff_size_outputx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t isize                   : 7;       /**< The number of bytes to move to the Info-Pointer
-                                                         from the front of the packet.
-                                                         Legal values are 0-120. */
-        uint64_t bsize                   : 16;      /**< The size in bytes of the area pointed to by
-                                                         buffer pointer for output packet data. */
-#else
-        uint64_t bsize                   : 16;
-        uint64_t isize                   : 7;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_npi_buff_size_outputx_s  cn30xx;
-    struct cvmx_npi_buff_size_outputx_s  cn31xx;
-    struct cvmx_npi_buff_size_outputx_s  cn38xx;
-    struct cvmx_npi_buff_size_outputx_s  cn38xxp2;
-    struct cvmx_npi_buff_size_outputx_s  cn50xx;
-    struct cvmx_npi_buff_size_outputx_s  cn58xx;
-    struct cvmx_npi_buff_size_outputx_s  cn58xxp1;
-} cvmx_npi_buff_size_outputx_t;
-
-
-/**
- * cvmx_npi_comp_ctl
- *
- * NPI_COMP_CTL = PCI Compensation Control
- * 
- * PCI Compensation Control
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_comp_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t pctl                    : 5;       /**< Bypass value for PCTL */
-        uint64_t nctl                    : 5;       /**< Bypass value for NCTL */
-#else
-        uint64_t nctl                    : 5;
-        uint64_t pctl                    : 5;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_npi_comp_ctl_s           cn50xx;
-    struct cvmx_npi_comp_ctl_s           cn58xx;
-    struct cvmx_npi_comp_ctl_s           cn58xxp1;
-} cvmx_npi_comp_ctl_t;
-
-
-/**
- * cvmx_npi_ctl_status
- *
- * NPI_CTL_STATUS = NPI's Control Status Register
- * 
- * Contains control ans status for NPI.
- * Writes to this register are not ordered with writes/reads to the PCI Memory space.
- * To ensure that a write has completed the user must read the register before
- * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_63_63          : 1;
-        uint64_t chip_rev                : 8;       /**< The revision of the N3. */
-        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
-                                                         Registers are disabled. */
-        uint64_t out3_enb                : 1;       /**< When asserted '1' the output3 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t out2_enb                : 1;       /**< When asserted '1' the output2 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t out1_enb                : 1;       /**< When asserted '1' the output1 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins3_enb                : 1;       /**< When asserted '1' the gather3 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins2_enb                : 1;       /**< When asserted '1' the gather2 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins1_enb                : 1;       /**< When asserted '1' the gather1 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins3_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather3 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t ins2_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather2 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t ins1_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather1 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather0 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
-                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
-        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional access to
-                                                         the L2C from the PCI. */
-        uint64_t reserved_37_39          : 3;
-        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
-                                                         write operation from the PPs to the PCI. Legal
-                                                         values are 1 to 32, where a '0' is treated as 32. */
-        uint64_t reserved_10_31          : 22;
-        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
-                                                         no longer than the value of TIMER in eclks to
-                                                         merge additional writes from the PPs into 1
-                                                         large write. The values for this field is 1 to
-                                                         1024 where a value of '0' is treated as 1024. */
-#else
-        uint64_t timer                   : 10;
-        uint64_t reserved_10_31          : 22;
-        uint64_t max_word                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t wait_com                : 1;
-        uint64_t pci_wdis                : 1;
-        uint64_t ins0_64b                : 1;
-        uint64_t ins1_64b                : 1;
-        uint64_t ins2_64b                : 1;
-        uint64_t ins3_64b                : 1;
-        uint64_t ins0_enb                : 1;
-        uint64_t ins1_enb                : 1;
-        uint64_t ins2_enb                : 1;
-        uint64_t ins3_enb                : 1;
-        uint64_t out0_enb                : 1;
-        uint64_t out1_enb                : 1;
-        uint64_t out2_enb                : 1;
-        uint64_t out3_enb                : 1;
-        uint64_t dis_pniw                : 1;
-        uint64_t chip_rev                : 8;
-        uint64_t reserved_63_63          : 1;
-#endif
-    } s;
-    struct cvmx_npi_ctl_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_63_63          : 1;
-        uint64_t chip_rev                : 8;       /**< The revision of the N3. */
-        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
-                                                         Registers are disabled. */
-        uint64_t reserved_51_53          : 3;
-        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t reserved_47_49          : 3;
-        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t reserved_43_45          : 3;
-        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather0 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
-                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
-        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional access to
-                                                         the L2C from the PCI. */
-        uint64_t reserved_37_39          : 3;
-        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
-                                                         write operation from the PPs to the PCI. Legal
-                                                         values are 1 to 32, where a '0' is treated as 32. */
-        uint64_t reserved_10_31          : 22;
-        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
-                                                         no longer than the value of TIMER in eclks to
-                                                         merge additional writes from the PPs into 1
-                                                         large write. The values for this field is 1 to
-                                                         1024 where a value of '0' is treated as 1024. */
-#else
-        uint64_t timer                   : 10;
-        uint64_t reserved_10_31          : 22;
-        uint64_t max_word                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t wait_com                : 1;
-        uint64_t pci_wdis                : 1;
-        uint64_t ins0_64b                : 1;
-        uint64_t reserved_43_45          : 3;
-        uint64_t ins0_enb                : 1;
-        uint64_t reserved_47_49          : 3;
-        uint64_t out0_enb                : 1;
-        uint64_t reserved_51_53          : 3;
-        uint64_t dis_pniw                : 1;
-        uint64_t chip_rev                : 8;
-        uint64_t reserved_63_63          : 1;
-#endif
-    } cn30xx;
-    struct cvmx_npi_ctl_status_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_63_63          : 1;
-        uint64_t chip_rev                : 8;       /**< The revision of the N3.
-                                                         0 => pass1.x, 1 => 2.0 */
-        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
-                                                         Registers are disabled. */
-        uint64_t reserved_52_53          : 2;
-        uint64_t out1_enb                : 1;       /**< When asserted '1' the output1 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t reserved_48_49          : 2;
-        uint64_t ins1_enb                : 1;       /**< When asserted '1' the gather1 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
-                                                         After enabling the values of the associated
-                                                         Address and Size Register should not be changed. */
-        uint64_t reserved_44_45          : 2;
-        uint64_t ins1_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather1 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
-                                                         gather0 engine are 64-Byte instructions, when
-                                                         de-asserted '0' instructions are 32-byte. */
-        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
-                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
-        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
-                                                         from the L2C before sending additional access to
-                                                         the L2C from the PCI. */
-        uint64_t reserved_37_39          : 3;
-        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
-                                                         write operation from the PPs to the PCI. Legal
-                                                         values are 1 to 32, where a '0' is treated as 32. */
-        uint64_t reserved_10_31          : 22;
-        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
-                                                         no longer than the value of TIMER in eclks to
-                                                         merge additional writes from the PPs into 1
-                                                         large write. The values for this field is 1 to
-                                                         1024 where a value of '0' is treated as 1024. */
-#else
-        uint64_t timer                   : 10;
-        uint64_t reserved_10_31          : 22;
-        uint64_t max_word                : 5;
-        uint64_t reserved_37_39          : 3;
-        uint64_t wait_com                : 1;
-        uint64_t pci_wdis                : 1;
-        uint64_t ins0_64b                : 1;
-        uint64_t ins1_64b                : 1;
-        uint64_t reserved_44_45          : 2;
-        uint64_t ins0_enb                : 1;
-        uint64_t ins1_enb                : 1;
-        uint64_t reserved_48_49          : 2;
-        uint64_t out0_enb                : 1;
-        uint64_t out1_enb                : 1;
-        uint64_t reserved_52_53          : 2;
-        uint64_t dis_pniw                : 1;
-        uint64_t chip_rev                : 8;
-        uint64_t reserved_63_63          : 1;
-#endif
-    } cn31xx;
-    struct cvmx_npi_ctl_status_s         cn38xx;
-    struct cvmx_npi_ctl_status_s         cn38xxp2;
-    struct cvmx_npi_ctl_status_cn31xx    cn50xx;
-    struct cvmx_npi_ctl_status_s         cn58xx;
-    struct cvmx_npi_ctl_status_s         cn58xxp1;
-} cvmx_npi_ctl_status_t;
-
-
-/**
- * cvmx_npi_dbg_select
- *
- * NPI_DBG_SELECT = Debug Select Register
- * 
- * Contains the debug select value in last written to the RSLs.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dbg_select_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dbg_sel                 : 16;      /**< When this register is written its value is sent to
-                                                         all RSLs. */
-#else
-        uint64_t dbg_sel                 : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npi_dbg_select_s         cn30xx;
-    struct cvmx_npi_dbg_select_s         cn31xx;
-    struct cvmx_npi_dbg_select_s         cn38xx;
-    struct cvmx_npi_dbg_select_s         cn38xxp2;
-    struct cvmx_npi_dbg_select_s         cn50xx;
-    struct cvmx_npi_dbg_select_s         cn58xx;
-    struct cvmx_npi_dbg_select_s         cn58xxp1;
-} cvmx_npi_dbg_select_t;
-
-
-/**
- * cvmx_npi_dma_control
- *
- * NPI_DMA_CONTROL = DMA Control Register
- * 
- * Controls operation of the DMA IN/OUT of the NPI.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dma_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPI is in the mode to write
-                                                         0 to L2C memory when a DMA is done, the address
-                                                         to be written to will be treated as a Little
-                                                         Endian address. This field is new to PASS-2. */
-        uint64_t dwb_denb                : 1;       /**< When set '1' the NPI will send a value in the DWB
-                                                         field for a free page operation for the memory
-                                                         that contained the data in N3. */
-        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
-                                                         this value is used for the DWB field of the
-                                                         operation. */
-        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
-                                                         be returned to when used. */
-        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
-                                                         if '0' then the number of bytes in the dma transfer
-                                                         will be added to the count register. */
-        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
-        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
-        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
-        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
-                                                         '1' use pointer values for address and register
-                                                         values for RO, ES, and NS, '0' use register
-                                                         values for address and pointer values for
-                                                         RO, ES, and NS. */
-        uint64_t hp_enb                  : 1;       /**< Enables the High Priority DMA.
-                                                         While this bit is disabled '0' then the value
-                                                         in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the
-                                                         starting address of the High Priority DMA engine.
-                                                         CSIZE field will be reloaded, for the High Priority
-                                                         DMA Engine. */
-        uint64_t lp_enb                  : 1;       /**< Enables the Low Priority DMA.
-                                                         While this bit is disabled '0' then the value
-                                                         in the NPI_LOWP_IBUFF_SADDR is re-loaded to the
-                                                         starting address of the Low Priority DMA engine.
-                                                         PASS-2: When this bit is '0' the value in the
-                                                         CSIZE field will be reloaded, for the Low Priority
-                                                         DMA Engine. */
-        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
-                                                         This value should only be written once. After
-                                                         writing this value a new value will not be
-                                                         recognized until the end of the DMA I-Chunk is
-                                                         reached. */
-#else
-        uint64_t csize                   : 14;
-        uint64_t lp_enb                  : 1;
-        uint64_t hp_enb                  : 1;
-        uint64_t o_mode                  : 1;
-        uint64_t o_es                    : 2;
-        uint64_t o_ns                    : 1;
-        uint64_t o_ro                    : 1;
-        uint64_t o_add1                  : 1;
-        uint64_t fpa_que                 : 3;
-        uint64_t dwb_ichk                : 9;
-        uint64_t dwb_denb                : 1;
-        uint64_t b0_lend                 : 1;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_npi_dma_control_s        cn30xx;
-    struct cvmx_npi_dma_control_s        cn31xx;
-    struct cvmx_npi_dma_control_s        cn38xx;
-    struct cvmx_npi_dma_control_s        cn38xxp2;
-    struct cvmx_npi_dma_control_s        cn50xx;
-    struct cvmx_npi_dma_control_s        cn58xx;
-    struct cvmx_npi_dma_control_s        cn58xxp1;
-} cvmx_npi_dma_control_t;
-
-
-/**
- * cvmx_npi_dma_highp_counts
- *
- * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts
- * 
- * Values for determing the number of instructions for High Priority DMA in the NPI.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dma_highp_counts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
-        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
-#else
-        uint64_t dbell                   : 32;
-        uint64_t fcnt                    : 7;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } s;
-    struct cvmx_npi_dma_highp_counts_s   cn30xx;
-    struct cvmx_npi_dma_highp_counts_s   cn31xx;
-    struct cvmx_npi_dma_highp_counts_s   cn38xx;
-    struct cvmx_npi_dma_highp_counts_s   cn38xxp2;
-    struct cvmx_npi_dma_highp_counts_s   cn50xx;
-    struct cvmx_npi_dma_highp_counts_s   cn58xx;
-    struct cvmx_npi_dma_highp_counts_s   cn58xxp1;
-} cvmx_npi_dma_highp_counts_t;
-
-
-/**
- * cvmx_npi_dma_highp_naddr
- *
- * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address
- * 
- * Place NPI will read the next Ichunk data from. This is valid when state is 0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dma_highp_naddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t state                   : 4;       /**< The DMA instruction engine state vector.
-                                                         Typical value is 0 (IDLE). */
-        uint64_t addr                    : 36;      /**< The next L2C address to read DMA instructions
-                                                         from for the High Priority DMA engine. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t state                   : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_npi_dma_highp_naddr_s    cn30xx;
-    struct cvmx_npi_dma_highp_naddr_s    cn31xx;
-    struct cvmx_npi_dma_highp_naddr_s    cn38xx;
-    struct cvmx_npi_dma_highp_naddr_s    cn38xxp2;
-    struct cvmx_npi_dma_highp_naddr_s    cn50xx;
-    struct cvmx_npi_dma_highp_naddr_s    cn58xx;
-    struct cvmx_npi_dma_highp_naddr_s    cn58xxp1;
-} cvmx_npi_dma_highp_naddr_t;
-
-
-/**
- * cvmx_npi_dma_lowp_counts
- *
- * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts
- * 
- * Values for determing the number of instructions for Low Priority DMA in the NPI.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dma_lowp_counts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_39_63          : 25;
-        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
-        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
-#else
-        uint64_t dbell                   : 32;
-        uint64_t fcnt                    : 7;
-        uint64_t reserved_39_63          : 25;
-#endif
-    } s;
-    struct cvmx_npi_dma_lowp_counts_s    cn30xx;
-    struct cvmx_npi_dma_lowp_counts_s    cn31xx;
-    struct cvmx_npi_dma_lowp_counts_s    cn38xx;
-    struct cvmx_npi_dma_lowp_counts_s    cn38xxp2;
-    struct cvmx_npi_dma_lowp_counts_s    cn50xx;
-    struct cvmx_npi_dma_lowp_counts_s    cn58xx;
-    struct cvmx_npi_dma_lowp_counts_s    cn58xxp1;
-} cvmx_npi_dma_lowp_counts_t;
-
-
-/**
- * cvmx_npi_dma_lowp_naddr
- *
- * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address
- * 
- * Place NPI will read the next Ichunk data from. This is valid when state is 0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_dma_lowp_naddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t state                   : 4;       /**< The DMA instruction engine state vector.
-                                                         Typical value is 0 (IDLE). */
-        uint64_t addr                    : 36;      /**< The next L2C address to read DMA instructions
-                                                         from for the Low Priority DMA engine. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t state                   : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_npi_dma_lowp_naddr_s     cn30xx;
-    struct cvmx_npi_dma_lowp_naddr_s     cn31xx;
-    struct cvmx_npi_dma_lowp_naddr_s     cn38xx;
-    struct cvmx_npi_dma_lowp_naddr_s     cn38xxp2;
-    struct cvmx_npi_dma_lowp_naddr_s     cn50xx;
-    struct cvmx_npi_dma_lowp_naddr_s     cn58xx;
-    struct cvmx_npi_dma_lowp_naddr_s     cn58xxp1;
-} cvmx_npi_dma_lowp_naddr_t;
-
-
-/**
- * cvmx_npi_highp_dbell
- *
- * NPI_HIGHP_DBELL = High Priority Door Bell
- * 
- * The door bell register for the high priority DMA queue.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_highp_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dbell                   : 16;      /**< The value written to this register is added to the
-                                                         number of 8byte words to be read and processes for
-                                                         the high priority dma queue. */
-#else
-        uint64_t dbell                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npi_highp_dbell_s        cn30xx;
-    struct cvmx_npi_highp_dbell_s        cn31xx;
-    struct cvmx_npi_highp_dbell_s        cn38xx;
-    struct cvmx_npi_highp_dbell_s        cn38xxp2;
-    struct cvmx_npi_highp_dbell_s        cn50xx;
-    struct cvmx_npi_highp_dbell_s        cn58xx;
-    struct cvmx_npi_highp_dbell_s        cn58xxp1;
-} cvmx_npi_highp_dbell_t;
-
-
-/**
- * cvmx_npi_highp_ibuff_saddr
- *
- * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address
- * 
- * The address to start reading Instructions from for HIGHP.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_highp_ibuff_saddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t saddr                   : 36;      /**< The starting address to read the first instruction. */
-#else
-        uint64_t saddr                   : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn30xx;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn31xx;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn38xx;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn38xxp2;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn50xx;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn58xx;
-    struct cvmx_npi_highp_ibuff_saddr_s  cn58xxp1;
-} cvmx_npi_highp_ibuff_saddr_t;
-
-
-/**
- * cvmx_npi_input_control
- *
- * NPI_INPUT_CONTROL = NPI's Input Control Register
- * 
- * Control for reads for gather list and instructions.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_input_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t pkt_rr                  : 1;       /**< When set '1' the input packet selection will be
-                                                         made with a Round Robin arbitration. When '0'
-                                                         the input packet port is fixed in priority,
-                                                         where the lower port number has higher priority.
-                                                         PASS3 Field */
-        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
-                                                         calculating a DPTR. */
-        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather data. */
-        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather data. */
-        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather data. */
-        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
-                                                         ROR, ESR, and NSR. When clear '0' the value in
-                                                         DPTR will be used. In turn the bits not used for
-                                                         ROR, ESR, and NSR, will be used for bits [63:60]
-                                                         of the address used to fetch packet data. */
-        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather list and gather instruction. */
-        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather list and gather instruction. */
-        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather list and gather instruction. */
-#else
-        uint64_t ror                     : 1;
-        uint64_t esr                     : 2;
-        uint64_t nsr                     : 1;
-        uint64_t use_csr                 : 1;
-        uint64_t d_ror                   : 1;
-        uint64_t d_esr                   : 2;
-        uint64_t d_nsr                   : 1;
-        uint64_t pbp_dhi                 : 13;
-        uint64_t pkt_rr                  : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_npi_input_control_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_22_63          : 42;
-        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
-                                                         calculating a DPTR. */
-        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather data. */
-        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather data. */
-        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather data. */
-        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
-                                                         ROR, ESR, and NSR. When clear '0' the value in
-                                                         DPTR will be used. In turn the bits not used for
-                                                         ROR, ESR, and NSR, will be used for bits [63:60]
-                                                         of the address used to fetch packet data. */
-        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
-                                                         gather list and gather instruction. */
-        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
-                                                         gather list and gather instruction. */
-        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
-                                                         gather list and gather instruction. */
-#else
-        uint64_t ror                     : 1;
-        uint64_t esr                     : 2;
-        uint64_t nsr                     : 1;
-        uint64_t use_csr                 : 1;
-        uint64_t d_ror                   : 1;
-        uint64_t d_esr                   : 2;
-        uint64_t d_nsr                   : 1;
-        uint64_t pbp_dhi                 : 13;
-        uint64_t reserved_22_63          : 42;
-#endif
-    } cn30xx;
-    struct cvmx_npi_input_control_cn30xx cn31xx;
-    struct cvmx_npi_input_control_s      cn38xx;
-    struct cvmx_npi_input_control_cn30xx cn38xxp2;
-    struct cvmx_npi_input_control_s      cn50xx;
-    struct cvmx_npi_input_control_s      cn58xx;
-    struct cvmx_npi_input_control_s      cn58xxp1;
-} cvmx_npi_input_control_t;
-
-
-/**
- * cvmx_npi_int_enb
- *
- * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register
- * 
- * Used to enable the various interrupting conditions of NPI
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
-                                                         interrupt. */
-        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
-                                                         interrupt. */
-        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
-                                                         interrupt. */
-        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
-                                                         interrupt. */
-        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
-                                                         interrupt. */
-        uint64_t i3_pperr                : 1;       /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i2_pperr                : 1;       /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p3_ptout                : 1;       /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p2_ptout                : 1;       /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p3_pperr                : 1;       /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p2_pperr                : 1;       /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t g3_rtout                : 1;       /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g2_rtout                : 1;       /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p3_perr                 : 1;       /**< Enables NPI_INT_SUM[P3_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p2_perr                 : 1;       /**< Enables NPI_INT_SUM[P2_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p3_rtout                : 1;       /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p2_rtout                : 1;       /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i3_overf                : 1;       /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i2_overf                : 1;       /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i3_rtout                : 1;       /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i2_rtout                : 1;       /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t po3_2sml                : 1;       /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po2_2sml                : 1;       /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
-                                                         interrupt. */
-        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
-                                                         interrupt. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
-                                                         interrupt. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
-                                                         interrupt. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t po2_2sml                : 1;
-        uint64_t po3_2sml                : 1;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t i2_rtout                : 1;
-        uint64_t i3_rtout                : 1;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t i2_overf                : 1;
-        uint64_t i3_overf                : 1;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t p2_rtout                : 1;
-        uint64_t p3_rtout                : 1;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t p2_perr                 : 1;
-        uint64_t p3_perr                 : 1;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t g2_rtout                : 1;
-        uint64_t g3_rtout                : 1;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t p2_pperr                : 1;
-        uint64_t p3_pperr                : 1;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t p2_ptout                : 1;
-        uint64_t p3_ptout                : 1;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t i2_pperr                : 1;
-        uint64_t i3_pperr                : 1;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } s;
-    struct cvmx_npi_int_enb_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
-                                                         interrupt. */
-        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
-                                                         interrupt. */
-        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
-                                                         interrupt. */
-        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
-                                                         interrupt. */
-        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
-                                                         interrupt. */
-        uint64_t reserved_36_38          : 3;
-        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_32_34          : 3;
-        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_28_30          : 3;
-        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_24_26          : 3;
-        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_20_22          : 3;
-        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_16_18          : 3;
-        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_12_14          : 3;
-        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t reserved_8_10           : 3;
-        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_4_6            : 3;
-        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
-                                                         interrupt. */
-        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
-                                                         interrupt. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
-                                                         interrupt. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
-                                                         interrupt. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t reserved_4_6            : 3;
-        uint64_t i0_rtout                : 1;
-        uint64_t reserved_8_10           : 3;
-        uint64_t i0_overf                : 1;
-        uint64_t reserved_12_14          : 3;
-        uint64_t p0_rtout                : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t p0_perr                 : 1;
-        uint64_t reserved_20_22          : 3;
-        uint64_t g0_rtout                : 1;
-        uint64_t reserved_24_26          : 3;
-        uint64_t p0_pperr                : 1;
-        uint64_t reserved_28_30          : 3;
-        uint64_t p0_ptout                : 1;
-        uint64_t reserved_32_34          : 3;
-        uint64_t i0_pperr                : 1;
-        uint64_t reserved_36_38          : 3;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } cn30xx;
-    struct cvmx_npi_int_enb_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
-                                                         interrupt. */
-        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
-                                                         interrupt. */
-        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
-                                                         interrupt. */
-        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
-                                                         interrupt. */
-        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
-                                                         interrupt. */
-        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
-                                                         interrupt. */
-        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
-                                                         interrupt. */
-        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
-                                                         interrupt. */
-        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
-                                                         interrupt. */
-        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
-                                                         interrupt. */
-        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
-                                                         interrupt. */
-        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
-                                                         interrupt. */
-        uint64_t reserved_37_38          : 2;
-        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_33_34          : 2;
-        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_29_30          : 2;
-        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_25_26          : 2;
-        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_21_22          : 2;
-        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
-                                                         interrupt. */
-        uint64_t reserved_17_18          : 2;
-        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_13_14          : 2;
-        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t reserved_9_10           : 2;
-        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t reserved_5_6            : 2;
-        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
-                                                         interrupt. */
-        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
-                                                         interrupt. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
-                                                         interrupt. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
-                                                         interrupt. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t reserved_9_10           : 2;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t reserved_13_14          : 2;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t reserved_17_18          : 2;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t reserved_21_22          : 2;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t reserved_25_26          : 2;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t reserved_29_30          : 2;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t reserved_33_34          : 2;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t reserved_37_38          : 2;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } cn31xx;
-    struct cvmx_npi_int_enb_s            cn38xx;
-    struct cvmx_npi_int_enb_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_42_63          : 22;
-        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
-                                                         interrupt. */
-        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
-                                                         interrupt. */
-        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
-                                                         interrupt. */
-        uint64_t i3_pperr                : 1;       /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i2_pperr                : 1;       /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p3_ptout                : 1;       /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p2_ptout                : 1;       /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p3_pperr                : 1;       /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p2_pperr                : 1;       /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
-                                                         interrupt. */
-        uint64_t g3_rtout                : 1;       /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g2_rtout                : 1;       /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p3_perr                 : 1;       /**< Enables NPI_INT_SUM[P3_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p2_perr                 : 1;       /**< Enables NPI_INT_SUM[P2_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
-                                                         interrupt. */
-        uint64_t p3_rtout                : 1;       /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p2_rtout                : 1;       /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i3_overf                : 1;       /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i2_overf                : 1;       /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
-                                                         interrupt. */
-        uint64_t i3_rtout                : 1;       /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i2_rtout                : 1;       /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
-                                                         interrupt. */
-        uint64_t po3_2sml                : 1;       /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po2_2sml                : 1;       /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
-                                                         interrupt. */
-        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
-                                                         interrupt. */
-        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
-                                                         interrupt. */
-        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
-                                                         interrupt. */
-        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
-                                                         interrupt. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t po2_2sml                : 1;
-        uint64_t po3_2sml                : 1;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t i2_rtout                : 1;
-        uint64_t i3_rtout                : 1;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t i2_overf                : 1;
-        uint64_t i3_overf                : 1;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t p2_rtout                : 1;
-        uint64_t p3_rtout                : 1;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t p2_perr                 : 1;
-        uint64_t p3_perr                 : 1;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t g2_rtout                : 1;
-        uint64_t g3_rtout                : 1;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t p2_pperr                : 1;
-        uint64_t p3_pperr                : 1;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t p2_ptout                : 1;
-        uint64_t p3_ptout                : 1;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t i2_pperr                : 1;
-        uint64_t i3_pperr                : 1;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t reserved_42_63          : 22;
-#endif
-    } cn38xxp2;
-    struct cvmx_npi_int_enb_cn31xx       cn50xx;
-    struct cvmx_npi_int_enb_s            cn58xx;
-    struct cvmx_npi_int_enb_s            cn58xxp1;
-} cvmx_npi_int_enb_t;
-
-
-/**
- * cvmx_npi_int_sum
- *
- * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register
- * 
- * Set when an interrupt condition occurs, write '1' to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full.
-                                                         PASS3 Field. */
-        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty.
-                                                         PASS3 Field. */
-        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO.
-                                                         PASS3 Field. */
-        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO.
-                                                         PASS3 Field. */
-        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO.
-                                                         PASS3 Field. */
-        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO.
-                                                         PASS3 Field. */
-        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0.
-                                                         PASS3 Field. */
-        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0.
-                                                         PASS3 Field. */
-        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max.
-                                                         PASS3 Field. */
-        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0.
-                                                         PASS3 Field. */
-        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max.
-                                                         PASS3 Field. */
-        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0.
-                                                         PASS3 Field. */
-        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full.
-                                                         PASS3 Field. */
-        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty.
-                                                         PASS3 Field. */
-        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full.
-                                                         PASS3 Field. */
-        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty.
-                                                         PASS3 Field. */
-        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full.
-                                                         PASS3 Field. */
-        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty.
-                                                         PASS3 Field. */
-        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full.
-                                                         PASS3 Field. */
-        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty.
-                                                         PASS3 Field. */
-        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
-        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
-                                                         from the PCI this bit may be set. */
-        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
-        uint64_t i3_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i2_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t p3_ptout                : 1;       /**< Port-3 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p2_ptout                : 1;       /**< Port-2 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p3_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p2_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t g3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t p3_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p2_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t i3_overf                : 1;       /**< Port-3 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i2_overf                : 1;       /**< Port-2 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t po3_2sml                : 1;       /**< The packet being sent out on Port3 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
-        uint64_t po2_2sml                : 1;       /**< The packet being sent out on Port2 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
-        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
-        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
-        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
-                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
-        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
-                                                         back from a RSL after sending a write command to
-                                                         a RSL. */
-        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
-                                                         back from a RSL after sending a read command to
-                                                         a RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t po2_2sml                : 1;
-        uint64_t po3_2sml                : 1;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t i2_rtout                : 1;
-        uint64_t i3_rtout                : 1;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t i2_overf                : 1;
-        uint64_t i3_overf                : 1;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t p2_rtout                : 1;
-        uint64_t p3_rtout                : 1;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t p2_perr                 : 1;
-        uint64_t p3_perr                 : 1;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t g2_rtout                : 1;
-        uint64_t g3_rtout                : 1;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t p2_pperr                : 1;
-        uint64_t p3_pperr                : 1;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t p2_ptout                : 1;
-        uint64_t p3_ptout                : 1;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t i2_pperr                : 1;
-        uint64_t i3_pperr                : 1;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } s;
-    struct cvmx_npi_int_sum_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full. */
-        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty. */
-        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO. */
-        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO. */
-        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO. */
-        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO. */
-        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
-        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
-        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max. */
-        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0. */
-        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max. */
-        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0. */
-        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full. */
-        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty. */
-        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full. */
-        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty. */
-        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full. */
-        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty. */
-        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full. */
-        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty. */
-        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
-        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
-                                                         from the PCI this bit may be set. */
-        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
-        uint64_t reserved_36_38          : 3;
-        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t reserved_32_34          : 3;
-        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t reserved_28_30          : 3;
-        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t reserved_24_26          : 3;
-        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t reserved_20_22          : 3;
-        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t reserved_16_18          : 3;
-        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t reserved_12_14          : 3;
-        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t reserved_8_10           : 3;
-        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t reserved_4_6            : 3;
-        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
-        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
-                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
-        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
-                                                         back from a RSL after sending a write command to
-                                                         a RSL. */
-        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
-                                                         back from a RSL after sending a read command to
-                                                         a RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t reserved_4_6            : 3;
-        uint64_t i0_rtout                : 1;
-        uint64_t reserved_8_10           : 3;
-        uint64_t i0_overf                : 1;
-        uint64_t reserved_12_14          : 3;
-        uint64_t p0_rtout                : 1;
-        uint64_t reserved_16_18          : 3;
-        uint64_t p0_perr                 : 1;
-        uint64_t reserved_20_22          : 3;
-        uint64_t g0_rtout                : 1;
-        uint64_t reserved_24_26          : 3;
-        uint64_t p0_pperr                : 1;
-        uint64_t reserved_28_30          : 3;
-        uint64_t p0_ptout                : 1;
-        uint64_t reserved_32_34          : 3;
-        uint64_t i0_pperr                : 1;
-        uint64_t reserved_36_38          : 3;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } cn30xx;
-    struct cvmx_npi_int_sum_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full. */
-        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty. */
-        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO. */
-        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO. */
-        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO. */
-        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO. */
-        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
-        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
-        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max. */
-        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0. */
-        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max. */
-        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0. */
-        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full. */
-        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty. */
-        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full. */
-        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty. */
-        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full. */
-        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty. */
-        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full. */
-        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty. */
-        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
-        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
-                                                         from the PCI this bit may be set. */
-        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
-        uint64_t reserved_37_38          : 2;
-        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t reserved_33_34          : 2;
-        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t reserved_29_30          : 2;
-        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t reserved_25_26          : 2;
-        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t reserved_21_22          : 2;
-        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t reserved_17_18          : 2;
-        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t reserved_13_14          : 2;
-        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t reserved_9_10           : 2;
-        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t reserved_5_6            : 2;
-        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
-        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
-        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
-                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
-        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
-                                                         back from a RSL after sending a write command to
-                                                         a RSL. */
-        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
-                                                         back from a RSL after sending a read command to
-                                                         a RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t reserved_5_6            : 2;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t reserved_9_10           : 2;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t reserved_13_14          : 2;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t reserved_17_18          : 2;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t reserved_21_22          : 2;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t reserved_25_26          : 2;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t reserved_29_30          : 2;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t reserved_33_34          : 2;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t reserved_37_38          : 2;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t fcr_s_e                 : 1;
-        uint64_t fcr_a_f                 : 1;
-        uint64_t pcr_s_e                 : 1;
-        uint64_t pcr_a_f                 : 1;
-        uint64_t q2_s_e                  : 1;
-        uint64_t q2_a_f                  : 1;
-        uint64_t q3_s_e                  : 1;
-        uint64_t q3_a_f                  : 1;
-        uint64_t com_s_e                 : 1;
-        uint64_t com_a_f                 : 1;
-        uint64_t pnc_s_e                 : 1;
-        uint64_t pnc_a_f                 : 1;
-        uint64_t rwx_s_e                 : 1;
-        uint64_t rdx_s_e                 : 1;
-        uint64_t pcf_p_e                 : 1;
-        uint64_t pcf_p_f                 : 1;
-        uint64_t pdf_p_e                 : 1;
-        uint64_t pdf_p_f                 : 1;
-        uint64_t q1_s_e                  : 1;
-        uint64_t q1_a_f                  : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } cn31xx;
-    struct cvmx_npi_int_sum_s            cn38xx;
-    struct cvmx_npi_int_sum_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_42_63          : 22;
-        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
-        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
-                                                         from the PCI this bit may be set. */
-        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
-        uint64_t i3_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i2_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
-                                                         this bit may be set. */
-        uint64_t p3_ptout                : 1;       /**< Port-3 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p2_ptout                : 1;       /**< Port-2 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
-                                                         pair. */
-        uint64_t p3_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p2_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
-                                                         pointer-pair, this bit may be set. */
-        uint64_t g3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read a gather list. */
-        uint64_t p3_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p2_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
-                                                         data this bit may be set. */
-        uint64_t p3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read packet data. */
-        uint64_t i3_overf                : 1;       /**< Port-3 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i2_overf                : 1;       /**< Port-2 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
-                                                         doorbell count was set. */
-        uint64_t i3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
-                                                         read instructions. */
-        uint64_t po3_2sml                : 1;       /**< The packet being sent out on Port3 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
-        uint64_t po2_2sml                : 1;       /**< The packet being sent out on Port2 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
-        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
-        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
-                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
-        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
-                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
-        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
-                                                         back from a RSL after sending a write command to
-                                                         a RSL. */
-        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
-                                                         back from a RSL after sending a read command to
-                                                         a RSL. */
-#else
-        uint64_t rml_rto                 : 1;
-        uint64_t rml_wto                 : 1;
-        uint64_t pci_rsl                 : 1;
-        uint64_t po0_2sml                : 1;
-        uint64_t po1_2sml                : 1;
-        uint64_t po2_2sml                : 1;
-        uint64_t po3_2sml                : 1;
-        uint64_t i0_rtout                : 1;
-        uint64_t i1_rtout                : 1;
-        uint64_t i2_rtout                : 1;
-        uint64_t i3_rtout                : 1;
-        uint64_t i0_overf                : 1;
-        uint64_t i1_overf                : 1;
-        uint64_t i2_overf                : 1;
-        uint64_t i3_overf                : 1;
-        uint64_t p0_rtout                : 1;
-        uint64_t p1_rtout                : 1;
-        uint64_t p2_rtout                : 1;
-        uint64_t p3_rtout                : 1;
-        uint64_t p0_perr                 : 1;
-        uint64_t p1_perr                 : 1;
-        uint64_t p2_perr                 : 1;
-        uint64_t p3_perr                 : 1;
-        uint64_t g0_rtout                : 1;
-        uint64_t g1_rtout                : 1;
-        uint64_t g2_rtout                : 1;
-        uint64_t g3_rtout                : 1;
-        uint64_t p0_pperr                : 1;
-        uint64_t p1_pperr                : 1;
-        uint64_t p2_pperr                : 1;
-        uint64_t p3_pperr                : 1;
-        uint64_t p0_ptout                : 1;
-        uint64_t p1_ptout                : 1;
-        uint64_t p2_ptout                : 1;
-        uint64_t p3_ptout                : 1;
-        uint64_t i0_pperr                : 1;
-        uint64_t i1_pperr                : 1;
-        uint64_t i2_pperr                : 1;
-        uint64_t i3_pperr                : 1;
-        uint64_t win_rto                 : 1;
-        uint64_t p_dperr                 : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t reserved_42_63          : 22;
-#endif
-    } cn38xxp2;
-    struct cvmx_npi_int_sum_cn31xx       cn50xx;
-    struct cvmx_npi_int_sum_s            cn58xx;
-    struct cvmx_npi_int_sum_s            cn58xxp1;
-} cvmx_npi_int_sum_t;
-
-
-/**
- * cvmx_npi_lowp_dbell
- *
- * NPI_LOWP_DBELL = Low Priority Door Bell
- * 
- * The door bell register for the low priority DMA queue.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_lowp_dbell_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dbell                   : 16;      /**< The value written to this register is added to the
-                                                         number of 8byte words to be read and processes for
-                                                         the low priority dma queue. */
-#else
-        uint64_t dbell                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_npi_lowp_dbell_s         cn30xx;
-    struct cvmx_npi_lowp_dbell_s         cn31xx;
-    struct cvmx_npi_lowp_dbell_s         cn38xx;
-    struct cvmx_npi_lowp_dbell_s         cn38xxp2;
-    struct cvmx_npi_lowp_dbell_s         cn50xx;
-    struct cvmx_npi_lowp_dbell_s         cn58xx;
-    struct cvmx_npi_lowp_dbell_s         cn58xxp1;
-} cvmx_npi_lowp_dbell_t;
-
-
-/**
- * cvmx_npi_lowp_ibuff_saddr
- *
- * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address
- * 
- * The address to start reading Instructions from for LOWP.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_lowp_ibuff_saddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t saddr                   : 36;      /**< The starting address to read the first instruction. */
-#else
-        uint64_t saddr                   : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn30xx;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn31xx;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn38xx;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn38xxp2;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn50xx;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn58xx;
-    struct cvmx_npi_lowp_ibuff_saddr_s   cn58xxp1;
-} cvmx_npi_lowp_ibuff_saddr_t;
-
-
-/**
- * cvmx_npi_mem_access_subid#
- *
- * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register
- * 
- * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.
- * Writes to this register are not ordered with writes/reads to the PCI Memory space.
- * To ensure that a write has completed the user must read the register before
- * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_mem_access_subidx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t shortl                  : 1;       /**< Generate CMD-6 on PCI(x) when '1'.
-                                                         Loads from the cores to the corresponding subid
-                                                         that are 32-bits or smaller:
-                                                         - Will generate the PCI-X "Memory Read DWORD"
-                                                           command in PCI-X mode. (Note that "Memory
-                                                           Read DWORD" appears much like an IO read on
-                                                           the PCI-X bus.)
-                                                         - Will generate the PCI "Memory Read" command
-                                                           in PCI-X mode, irrespective of the
-                                                           NPI_PCI_READ_CMD[CMD_SIZE] value.
-                                                         NOT IN PASS 1 NOR PASS 2 */
-        uint64_t nmerge                  : 1;       /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */
-        uint64_t esr                     : 2;       /**< Endian-Swap on read. */
-        uint64_t esw                     : 2;       /**< Endian-Swap on write. */
-        uint64_t nsr                     : 1;       /**< No-Snoop on read. */
-        uint64_t nsw                     : 1;       /**< No-Snoop on write. */
-        uint64_t ror                     : 1;       /**< Relax Read on read. */
-        uint64_t row                     : 1;       /**< Relax Order on write. */
-        uint64_t ba                      : 28;      /**< PCI Address bits [63:36]. */
-#else
-        uint64_t ba                      : 28;
-        uint64_t row                     : 1;
-        uint64_t ror                     : 1;
-        uint64_t nsw                     : 1;
-        uint64_t nsr                     : 1;
-        uint64_t esw                     : 2;
-        uint64_t esr                     : 2;
-        uint64_t nmerge                  : 1;
-        uint64_t shortl                  : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_npi_mem_access_subidx_s  cn30xx;
-    struct cvmx_npi_mem_access_subidx_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t esr                     : 2;       /**< Endian-Swap on read. */
-        uint64_t esw                     : 2;       /**< Endian-Swap on write. */
-        uint64_t nsr                     : 1;       /**< No-Snoop on read. */
-        uint64_t nsw                     : 1;       /**< No-Snoop on write. */
-        uint64_t ror                     : 1;       /**< Relax Read on read. */
-        uint64_t row                     : 1;       /**< Relax Order on write. */
-        uint64_t ba                      : 28;      /**< PCI Address bits [63:36]. */
-#else
-        uint64_t ba                      : 28;
-        uint64_t row                     : 1;
-        uint64_t ror                     : 1;
-        uint64_t nsw                     : 1;
-        uint64_t nsr                     : 1;
-        uint64_t esw                     : 2;
-        uint64_t esr                     : 2;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } cn31xx;
-    struct cvmx_npi_mem_access_subidx_s  cn38xx;
-    struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
-    struct cvmx_npi_mem_access_subidx_s  cn50xx;
-    struct cvmx_npi_mem_access_subidx_s  cn58xx;
-    struct cvmx_npi_mem_access_subidx_s  cn58xxp1;
-} cvmx_npi_mem_access_subidx_t;
-
-
-/**
- * cvmx_npi_msi_rcv
- *
- * NPI_MSI_RCV = NPI MSI Receive Vector Register
- * 
- * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_msi_rcv_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t int_vec                 : 64;      /**< Refer to PCI_MSI_RCV */
-#else
-        uint64_t int_vec                 : 64;
-#endif
-    } s;
-    struct cvmx_npi_msi_rcv_s            cn30xx;
-    struct cvmx_npi_msi_rcv_s            cn31xx;
-    struct cvmx_npi_msi_rcv_s            cn38xx;
-    struct cvmx_npi_msi_rcv_s            cn38xxp2;
-    struct cvmx_npi_msi_rcv_s            cn50xx;
-    struct cvmx_npi_msi_rcv_s            cn58xx;
-    struct cvmx_npi_msi_rcv_s            cn58xxp1;
-} cvmx_npi_msi_rcv_t;
-
-
-/**
- * cvmx_npi_num_desc_output#
- *
- * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0
- * 
- * The size of the Buffer/Info Pointer Pair ring for Output-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_num_desc_outputx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t size                    : 32;      /**< The size of the Buffer/Info Pointer Pair ring. */
-#else
-        uint64_t size                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npi_num_desc_outputx_s   cn30xx;
-    struct cvmx_npi_num_desc_outputx_s   cn31xx;
-    struct cvmx_npi_num_desc_outputx_s   cn38xx;
-    struct cvmx_npi_num_desc_outputx_s   cn38xxp2;
-    struct cvmx_npi_num_desc_outputx_s   cn50xx;
-    struct cvmx_npi_num_desc_outputx_s   cn58xx;
-    struct cvmx_npi_num_desc_outputx_s   cn58xxp1;
-} cvmx_npi_num_desc_outputx_t;
-
-
-/**
- * cvmx_npi_output_control
- *
- * NPI_OUTPUT_CONTROL = NPI's Output Control Register
- * 
- * The address to start reading Instructions from for Output-3.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_output_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t pkt_rr                  : 1;       /**< When set '1' the output packet selection will be
-                                                         made with a Round Robin arbitration. When '0'
-                                                         the output packet port is fixed in priority,
-                                                         where the lower port number has higher priority.
-                                                         PASS3 Field */
-        uint64_t p3_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT3 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p2_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT2 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t o3_es                   : 2;       /**< Endian Swap for Output3 Data. */
-        uint64_t o3_ns                   : 1;       /**< NoSnoop Enable for Output3 Data. */
-        uint64_t o3_ro                   : 1;       /**< Relaxed Ordering Enable for Output3 Data. */
-        uint64_t o2_es                   : 2;       /**< Endian Swap for Output2 Data. */
-        uint64_t o2_ns                   : 1;       /**< NoSnoop Enable for Output2 Data. */
-        uint64_t o2_ro                   : 1;       /**< Relaxed Ordering Enable for Output2 Data. */
-        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
-        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
-        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
-        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
-        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
-        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
-        uint64_t o3_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O3_ES,
-                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
-        uint64_t o2_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O2_ES,
-                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
-        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O1_ES,
-                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
-        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
-        uint64_t reserved_20_23          : 4;
-        uint64_t iptr_o3                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-3. */
-        uint64_t iptr_o2                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-2. */
-        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-1. */
-        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-0. */
-        uint64_t esr_sl3                 : 2;       /**< The Endian-Swap-Mode for Slist3 reads. */
-        uint64_t nsr_sl3                 : 1;       /**< Enables '1' NoSnoop for Slist3 reads. */
-        uint64_t ror_sl3                 : 1;       /**< Enables '1' Relaxed Ordering for Slist3 reads. */
-        uint64_t esr_sl2                 : 2;       /**< The Endian-Swap-Mode for Slist2 reads. */
-        uint64_t nsr_sl2                 : 1;       /**< Enables '1' NoSnoop for Slist2 reads. */
-        uint64_t ror_sl2                 : 1;       /**< Enables '1' Relaxed Ordering for Slist2 reads. */
-        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
-        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
-        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
-        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
-        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
-        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
-#else
-        uint64_t ror_sl0                 : 1;
-        uint64_t nsr_sl0                 : 1;
-        uint64_t esr_sl0                 : 2;
-        uint64_t ror_sl1                 : 1;
-        uint64_t nsr_sl1                 : 1;
-        uint64_t esr_sl1                 : 2;
-        uint64_t ror_sl2                 : 1;
-        uint64_t nsr_sl2                 : 1;
-        uint64_t esr_sl2                 : 2;
-        uint64_t ror_sl3                 : 1;
-        uint64_t nsr_sl3                 : 1;
-        uint64_t esr_sl3                 : 2;
-        uint64_t iptr_o0                 : 1;
-        uint64_t iptr_o1                 : 1;
-        uint64_t iptr_o2                 : 1;
-        uint64_t iptr_o3                 : 1;
-        uint64_t reserved_20_23          : 4;
-        uint64_t o0_csrm                 : 1;
-        uint64_t o1_csrm                 : 1;
-        uint64_t o2_csrm                 : 1;
-        uint64_t o3_csrm                 : 1;
-        uint64_t o0_ro                   : 1;
-        uint64_t o0_ns                   : 1;
-        uint64_t o0_es                   : 2;
-        uint64_t o1_ro                   : 1;
-        uint64_t o1_ns                   : 1;
-        uint64_t o1_es                   : 2;
-        uint64_t o2_ro                   : 1;
-        uint64_t o2_ns                   : 1;
-        uint64_t o2_es                   : 2;
-        uint64_t o3_ro                   : 1;
-        uint64_t o3_ns                   : 1;
-        uint64_t o3_es                   : 2;
-        uint64_t p0_bmode                : 1;
-        uint64_t p1_bmode                : 1;
-        uint64_t p2_bmode                : 1;
-        uint64_t p3_bmode                : 1;
-        uint64_t pkt_rr                  : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_npi_output_control_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_45_63          : 19;
-        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t reserved_32_43          : 12;
-        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
-        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
-        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
-        uint64_t reserved_25_27          : 3;
-        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
-        uint64_t reserved_17_23          : 7;
-        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-0. */
-        uint64_t reserved_4_15           : 12;
-        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
-        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
-        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
-#else
-        uint64_t ror_sl0                 : 1;
-        uint64_t nsr_sl0                 : 1;
-        uint64_t esr_sl0                 : 2;
-        uint64_t reserved_4_15           : 12;
-        uint64_t iptr_o0                 : 1;
-        uint64_t reserved_17_23          : 7;
-        uint64_t o0_csrm                 : 1;
-        uint64_t reserved_25_27          : 3;
-        uint64_t o0_ro                   : 1;
-        uint64_t o0_ns                   : 1;
-        uint64_t o0_es                   : 2;
-        uint64_t reserved_32_43          : 12;
-        uint64_t p0_bmode                : 1;
-        uint64_t reserved_45_63          : 19;
-#endif
-    } cn30xx;
-    struct cvmx_npi_output_control_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_46_63          : 18;
-        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t reserved_36_43          : 8;
-        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
-        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
-        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
-        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
-        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
-        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
-        uint64_t reserved_26_27          : 2;
-        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O1_ES,
-                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
-        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
-        uint64_t reserved_18_23          : 6;
-        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-1. */
-        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-0. */
-        uint64_t reserved_8_15           : 8;
-        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
-        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
-        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
-        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
-        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
-        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
-#else
-        uint64_t ror_sl0                 : 1;
-        uint64_t nsr_sl0                 : 1;
-        uint64_t esr_sl0                 : 2;
-        uint64_t ror_sl1                 : 1;
-        uint64_t nsr_sl1                 : 1;
-        uint64_t esr_sl1                 : 2;
-        uint64_t reserved_8_15           : 8;
-        uint64_t iptr_o0                 : 1;
-        uint64_t iptr_o1                 : 1;
-        uint64_t reserved_18_23          : 6;
-        uint64_t o0_csrm                 : 1;
-        uint64_t o1_csrm                 : 1;
-        uint64_t reserved_26_27          : 2;
-        uint64_t o0_ro                   : 1;
-        uint64_t o0_ns                   : 1;
-        uint64_t o0_es                   : 2;
-        uint64_t o1_ro                   : 1;
-        uint64_t o1_ns                   : 1;
-        uint64_t o1_es                   : 2;
-        uint64_t reserved_36_43          : 8;
-        uint64_t p0_bmode                : 1;
-        uint64_t p1_bmode                : 1;
-        uint64_t reserved_46_63          : 18;
-#endif
-    } cn31xx;
-    struct cvmx_npi_output_control_s     cn38xx;
-    struct cvmx_npi_output_control_cn38xxp2
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t p3_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT3 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p2_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT2 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t o3_es                   : 2;       /**< Endian Swap for Output3 Data. */
-        uint64_t o3_ns                   : 1;       /**< NoSnoop Enable for Output3 Data. */
-        uint64_t o3_ro                   : 1;       /**< Relaxed Ordering Enable for Output3 Data. */
-        uint64_t o2_es                   : 2;       /**< Endian Swap for Output2 Data. */
-        uint64_t o2_ns                   : 1;       /**< NoSnoop Enable for Output2 Data. */
-        uint64_t o2_ro                   : 1;       /**< Relaxed Ordering Enable for Output2 Data. */
-        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
-        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
-        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
-        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
-        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
-        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
-        uint64_t o3_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O3_ES,
-                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
-        uint64_t o2_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O2_ES,
-                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
-        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O1_ES,
-                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
-        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
-        uint64_t reserved_20_23          : 4;
-        uint64_t iptr_o3                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-3. */
-        uint64_t iptr_o2                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-2. */
-        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-1. */
-        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-0. */
-        uint64_t esr_sl3                 : 2;       /**< The Endian-Swap-Mode for Slist3 reads. */
-        uint64_t nsr_sl3                 : 1;       /**< Enables '1' NoSnoop for Slist3 reads. */
-        uint64_t ror_sl3                 : 1;       /**< Enables '1' Relaxed Ordering for Slist3 reads. */
-        uint64_t esr_sl2                 : 2;       /**< The Endian-Swap-Mode for Slist2 reads. */
-        uint64_t nsr_sl2                 : 1;       /**< Enables '1' NoSnoop for Slist2 reads. */
-        uint64_t ror_sl2                 : 1;       /**< Enables '1' Relaxed Ordering for Slist2 reads. */
-        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
-        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
-        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
-        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
-        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
-        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
-#else
-        uint64_t ror_sl0                 : 1;
-        uint64_t nsr_sl0                 : 1;
-        uint64_t esr_sl0                 : 2;
-        uint64_t ror_sl1                 : 1;
-        uint64_t nsr_sl1                 : 1;
-        uint64_t esr_sl1                 : 2;
-        uint64_t ror_sl2                 : 1;
-        uint64_t nsr_sl2                 : 1;
-        uint64_t esr_sl2                 : 2;
-        uint64_t ror_sl3                 : 1;
-        uint64_t nsr_sl3                 : 1;
-        uint64_t esr_sl3                 : 2;
-        uint64_t iptr_o0                 : 1;
-        uint64_t iptr_o1                 : 1;
-        uint64_t iptr_o2                 : 1;
-        uint64_t iptr_o3                 : 1;
-        uint64_t reserved_20_23          : 4;
-        uint64_t o0_csrm                 : 1;
-        uint64_t o1_csrm                 : 1;
-        uint64_t o2_csrm                 : 1;
-        uint64_t o3_csrm                 : 1;
-        uint64_t o0_ro                   : 1;
-        uint64_t o0_ns                   : 1;
-        uint64_t o0_es                   : 2;
-        uint64_t o1_ro                   : 1;
-        uint64_t o1_ns                   : 1;
-        uint64_t o1_es                   : 2;
-        uint64_t o2_ro                   : 1;
-        uint64_t o2_ns                   : 1;
-        uint64_t o2_es                   : 2;
-        uint64_t o3_ro                   : 1;
-        uint64_t o3_ns                   : 1;
-        uint64_t o3_es                   : 2;
-        uint64_t p0_bmode                : 1;
-        uint64_t p1_bmode                : 1;
-        uint64_t p2_bmode                : 1;
-        uint64_t p3_bmode                : 1;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } cn38xxp2;
-    struct cvmx_npi_output_control_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t pkt_rr                  : 1;       /**< When set '1' the output packet selection will be
-                                                         made with a Round Robin arbitration. When '0'
-                                                         the output packet port is fixed in priority,
-                                                         where the lower port number has higher priority.
-                                                         PASS2 Field */
-        uint64_t reserved_46_47          : 2;
-        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
-                                                         updated with the number of bytes in the packet
-                                                         sent, when '0' the register will have a value
-                                                         of '1' added. */
-        uint64_t reserved_36_43          : 8;
-        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
-        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
-        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
-        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
-        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
-        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
-        uint64_t reserved_26_27          : 2;
-        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O1_ES,
-                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
-        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
-                                                         comes from the DPTR[63:60] in the scatter-list pair,
-                                                         and the RO, NS, ES values come from the O0_ES,
-                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
-                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
-                                                         packet will be written to is ADDR[63:60] ==
-                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
-        uint64_t reserved_18_23          : 6;
-        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-1. */
-        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
-                                                         for output-0. */
-        uint64_t reserved_8_15           : 8;
-        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
-        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
-        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
-        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
-        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
-        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
-#else
-        uint64_t ror_sl0                 : 1;
-        uint64_t nsr_sl0                 : 1;
-        uint64_t esr_sl0                 : 2;
-        uint64_t ror_sl1                 : 1;
-        uint64_t nsr_sl1                 : 1;
-        uint64_t esr_sl1                 : 2;
-        uint64_t reserved_8_15           : 8;
-        uint64_t iptr_o0                 : 1;
-        uint64_t iptr_o1                 : 1;
-        uint64_t reserved_18_23          : 6;
-        uint64_t o0_csrm                 : 1;
-        uint64_t o1_csrm                 : 1;
-        uint64_t reserved_26_27          : 2;
-        uint64_t o0_ro                   : 1;
-        uint64_t o0_ns                   : 1;
-        uint64_t o0_es                   : 2;
-        uint64_t o1_ro                   : 1;
-        uint64_t o1_ns                   : 1;
-        uint64_t o1_es                   : 2;
-        uint64_t reserved_36_43          : 8;
-        uint64_t p0_bmode                : 1;
-        uint64_t p1_bmode                : 1;
-        uint64_t reserved_46_47          : 2;
-        uint64_t pkt_rr                  : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } cn50xx;
-    struct cvmx_npi_output_control_s     cn58xx;
-    struct cvmx_npi_output_control_s     cn58xxp1;
-} cvmx_npi_output_control_t;
-
-
-/**
- * cvmx_npi_p#_dbpair_addr
- *
- * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.
- * 
- * Contains the next address to read for Port's-0 Data/Buffer Pair.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_px_dbpair_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_63_63          : 1;
-        uint64_t state                   : 2;       /**< POS state machine vector. Used to tell when NADDR
-                                                         is valid (when STATE == 0). */
-        uint64_t naddr                   : 61;      /**< Bits [63:3] of the next Data-Info Pair to read.
-                                                         Value is only valid when STATE == 0. */
-#else
-        uint64_t naddr                   : 61;
-        uint64_t state                   : 2;
-        uint64_t reserved_63_63          : 1;
-#endif
-    } s;
-    struct cvmx_npi_px_dbpair_addr_s     cn30xx;
-    struct cvmx_npi_px_dbpair_addr_s     cn31xx;
-    struct cvmx_npi_px_dbpair_addr_s     cn38xx;
-    struct cvmx_npi_px_dbpair_addr_s     cn38xxp2;
-    struct cvmx_npi_px_dbpair_addr_s     cn50xx;
-    struct cvmx_npi_px_dbpair_addr_s     cn58xx;
-    struct cvmx_npi_px_dbpair_addr_s     cn58xxp1;
-} cvmx_npi_px_dbpair_addr_t;
-
-
-/**
- * cvmx_npi_p#_instr_addr
- *
- * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.
- * 
- * Contains the next address to read for Port's-0 Instructions.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_px_instr_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t state                   : 3;       /**< Gather engine state vector. Used to tell when
-                                                         NADDR is valid (when STATE == 0). */
-        uint64_t naddr                   : 61;      /**< Bits [63:3] of the next Instruction to read.
-                                                         Value is only valid when STATE == 0. */
-#else
-        uint64_t naddr                   : 61;
-        uint64_t state                   : 3;
-#endif
-    } s;
-    struct cvmx_npi_px_instr_addr_s      cn30xx;
-    struct cvmx_npi_px_instr_addr_s      cn31xx;
-    struct cvmx_npi_px_instr_addr_s      cn38xx;
-    struct cvmx_npi_px_instr_addr_s      cn38xxp2;
-    struct cvmx_npi_px_instr_addr_s      cn50xx;
-    struct cvmx_npi_px_instr_addr_s      cn58xx;
-    struct cvmx_npi_px_instr_addr_s      cn58xxp1;
-} cvmx_npi_px_instr_addr_t;
-
-
-/**
- * cvmx_npi_p#_instr_cnts
- *
- * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.
- * 
- * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_px_instr_cnts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t fcnt                    : 6;       /**< Number entries in the Instruction FIFO. */
-        uint64_t avail                   : 32;      /**< Doorbell count to be read. */
-#else
-        uint64_t avail                   : 32;
-        uint64_t fcnt                    : 6;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_npi_px_instr_cnts_s      cn30xx;
-    struct cvmx_npi_px_instr_cnts_s      cn31xx;
-    struct cvmx_npi_px_instr_cnts_s      cn38xx;
-    struct cvmx_npi_px_instr_cnts_s      cn38xxp2;
-    struct cvmx_npi_px_instr_cnts_s      cn50xx;
-    struct cvmx_npi_px_instr_cnts_s      cn58xx;
-    struct cvmx_npi_px_instr_cnts_s      cn58xxp1;
-} cvmx_npi_px_instr_cnts_t;
-
-
-/**
- * cvmx_npi_p#_pair_cnts
- *
- * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.
- * 
- * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_px_pair_cnts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t fcnt                    : 5;       /**< 16 - number entries in the D/I Pair FIFO. */
-        uint64_t avail                   : 32;      /**< Doorbell count to be read. */
-#else
-        uint64_t avail                   : 32;
-        uint64_t fcnt                    : 5;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } s;
-    struct cvmx_npi_px_pair_cnts_s       cn30xx;
-    struct cvmx_npi_px_pair_cnts_s       cn31xx;
-    struct cvmx_npi_px_pair_cnts_s       cn38xx;
-    struct cvmx_npi_px_pair_cnts_s       cn38xxp2;
-    struct cvmx_npi_px_pair_cnts_s       cn50xx;
-    struct cvmx_npi_px_pair_cnts_s       cn58xx;
-    struct cvmx_npi_px_pair_cnts_s       cn58xxp1;
-} cvmx_npi_px_pair_cnts_t;
-
-
-/**
- * cvmx_npi_pci_burst_size
- *
- * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register
- * 
- * Control the number of words the NPI will attempt to read / write to/from the PCI.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_pci_burst_size_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t wr_brst                 : 7;       /**< The number of 8B words to write to PCI in any one
-                                                         write operation. A zero is equal to 128. This
-                                                         value is used the packet reads and is clamped at
-                                                         a max of 112 for dma writes. */
-        uint64_t rd_brst                 : 7;       /**< Number of 8B words to read from PCI in any one
-                                                         read operation. Legal values are 1 to 127, where
-                                                         a 0 will be treated as a 1.
-                                                         "For reading of packet data value is limited to 64
-                                                         in PASS-2."
-                                                         This value does not control the size of a read
-                                                         caused by an IOBDMA from a PP. */
-#else
-        uint64_t rd_brst                 : 7;
-        uint64_t wr_brst                 : 7;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_npi_pci_burst_size_s     cn30xx;
-    struct cvmx_npi_pci_burst_size_s     cn31xx;
-    struct cvmx_npi_pci_burst_size_s     cn38xx;
-    struct cvmx_npi_pci_burst_size_s     cn38xxp2;
-    struct cvmx_npi_pci_burst_size_s     cn50xx;
-    struct cvmx_npi_pci_burst_size_s     cn58xx;
-    struct cvmx_npi_pci_burst_size_s     cn58xxp1;
-} cvmx_npi_pci_burst_size_t;
-
-
-/**
- * cvmx_npi_pci_int_arb_cfg
- *
- * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter
- * 
- * Controls operation of the Internal PCI Arbiter.  This register should
- * only be written when PRST# is asserted.  NPI_PCI_INT_ARB_CFG[EN] should
- * only be set when Octane is a host.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_pci_int_arb_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t hostmode                : 1;       /**< PCI Host Mode Pin (sampled for use by software).
-                                                         This bit reflects the sampled PCI_HOSTMODE pin.
-                                                         In HOST Mode, OCTEON drives the PCI_CLK_OUT and
-                                                         PCI initialization pattern during PCI_RST_N deassertion).
-                                                         *** NOTE: O9N PASS1 Addition */
-        uint64_t pci_ovr                 : 4;       /**< PCI Host Mode Bus Speed/Type Override
-                                                          When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting
-                                                          as the PCI Central Agent, samples the PCI_PCI100,
-                                                          PCI_M66EN and PCI_PCIXCAP pins to determine the
-                                                          'sampled' PCI Bus speed and Bus Type (PCI or PCIX).
-                                                          (see: PCI_CNT_REG[HM_SPEED,HM_PCIX])
-                                                          However, in some cases, SW may want to override the
-                                                          the 'sampled' PCI Bus Type/Speed, and use some
-                                                          SLOWER Bus frequency.
-                                                          The PCI_OVR field encoding represents the 'override'
-                                                          PCI Bus Type/Speed which will be used to generate the
-                                                          PCI_CLK_OUT and determines the PCI initialization pattern
-                                                          driven during PCI_RST_N deassertion.
-                                                              PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE)
-                                                              PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX)
-                                                              PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133)
-                                                         OVERRIDE TYPE SPEED |  Override Configuration
-                                                            [3]   [2]  [1:0] | TYPE       SPEED
-                                                           ------------------+-------------------------------
-                                                             0     x      xx | No override(uses 'sampled'
-                                                                             | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX)
-                                                             1     0      00 | PCI Mode    33MHz
-                                                             1     0      01 | PCI Mode    66MHz
-                                                             1     0      10 | RESERVED (DO NOT USE)
-                                                             1     0      11 | RESERVED (DO NOT USE)
-                                                             1     1      00 | RESERVED (DO NOT USE)
-                                                             1     1      01 | PCIX Mode   66MHz
-                                                             1     1      10 | PCIX Mode  100MHz
-                                                             1     1      11 | PCIX Mode  133MHz
-                                                          NOTES:
-                                                          - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on
-                                                            PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus
-                                                            Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX]
-                                                            which reflects the actual PCI Bus Type(0:PCI/1:PCIX).
-                                                          - Software should never 'up' configure the recommended values.
-                                                            In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0),
-                                                            then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode.
-                                                            Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01),
-                                                            then SW should NOT attempt to 'speed up' the bus [ie:
-                                                            SPEED[1:0]=10(100MHz)].
-                                                          - If PCI_OVR<3> is set prior to PCI reset de-assertion
-                                                            in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR]
-                                                            indicates the Bus Type/Speed that OCTEON drove on the
-                                                            DEVSEL/STOP/TRDY pins during reset de-assertion. (user
-                                                            should then ignore the 'sampled' Bus Type/Speed
-                                                            contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields.
-                                                          - If PCI_OVR<3> is clear prior to PCI reset de-assertion
-                                                            in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED])
-                                                            indicates the Bus Type/Speed that OCTEON drove on the
-                                                            DEVSEL/STOP/TRDY pins during reset de-assertion.
-                                                          *** NOTE: O9N PASS1 Addition */
-        uint64_t reserved_5_7            : 3;
-        uint64_t en                      : 1;       /**< Internal arbiter enable. */
-        uint64_t park_mod                : 1;       /**< Bus park mode. 0=park on last, 1=park on device. */
-        uint64_t park_dev                : 3;       /**< Bus park device. 0-3 External device, 4 = Octane. */
-#else
-        uint64_t park_dev                : 3;
-        uint64_t park_mod                : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_5_7            : 3;
-        uint64_t pci_ovr                 : 4;
-        uint64_t hostmode                : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_npi_pci_int_arb_cfg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t en                      : 1;       /**< Internal arbiter enable. */
-        uint64_t park_mod                : 1;       /**< Bus park mode. 0=park on last, 1=park on device. */
-        uint64_t park_dev                : 3;       /**< Bus park device. 0-3 External device, 4 = Octane. */
-#else
-        uint64_t park_dev                : 3;
-        uint64_t park_mod                : 1;
-        uint64_t en                      : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } cn30xx;
-    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
-    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
-    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
-    struct cvmx_npi_pci_int_arb_cfg_s    cn50xx;
-    struct cvmx_npi_pci_int_arb_cfg_s    cn58xx;
-    struct cvmx_npi_pci_int_arb_cfg_s    cn58xxp1;
-} cvmx_npi_pci_int_arb_cfg_t;
-
-
-/**
- * cvmx_npi_pci_read_cmd
- *
- * NPI_PCI_READ_CMD = NPI PCI Read Command Register
- * 
- * Controls the type of read command sent.
- * Writes to this register are not ordered with writes/reads to the PCI Memory space.
- * To ensure that a write has completed the user must read the register before
- * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
- * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
- * FIFO will use the value of this register after it has been updated.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_pci_read_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t cmd_size                : 11;      /**< Number bytes to be read is equal to or exceeds this
-                                                         size will cause the PCI in PCI mode to use a
-                                                         Memory-Read-Multiple. This register has a value
-                                                         from 8 to 2048. A value of 0-7 will be treated as
-                                                         a value of 2048. */
-#else
-        uint64_t cmd_size                : 11;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_npi_pci_read_cmd_s       cn30xx;
-    struct cvmx_npi_pci_read_cmd_s       cn31xx;
-    struct cvmx_npi_pci_read_cmd_s       cn38xx;
-    struct cvmx_npi_pci_read_cmd_s       cn38xxp2;
-    struct cvmx_npi_pci_read_cmd_s       cn50xx;
-    struct cvmx_npi_pci_read_cmd_s       cn58xx;
-    struct cvmx_npi_pci_read_cmd_s       cn58xxp1;
-} cvmx_npi_pci_read_cmd_t;
-
-
-/**
- * cvmx_npi_port32_instr_hdr
- *
- * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header
- * 
- * Contains bits [62:42] of the Instruction Header for port 32.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_port32_instr_hdr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
-        uint64_t rsv_f                   : 5;       /**< Reserved */
-        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
-        uint64_t rsv_e                   : 1;       /**< Reserved */
-        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
-        uint64_t rsv_d                   : 6;       /**< Reserved */
-        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
-                                                         USE_IHDR must be set whenever PBP is set. */
-        uint64_t rsv_c                   : 5;       /**< Reserved */
-        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_b                   : 1;       /**< Reserved
-                                                         instruction header sent to IPD. */
-        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_a                   : 6;       /**< Reserved */
-#else
-        uint64_t rsv_a                   : 6;
-        uint64_t skp_len                 : 7;
-        uint64_t rsv_b                   : 1;
-        uint64_t par_mode                : 2;
-        uint64_t rsv_c                   : 5;
-        uint64_t use_ihdr                : 1;
-        uint64_t rsv_d                   : 6;
-        uint64_t rskp_len                : 7;
-        uint64_t rsv_e                   : 1;
-        uint64_t rparmode                : 2;
-        uint64_t rsv_f                   : 5;
-        uint64_t pbp                     : 1;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npi_port32_instr_hdr_s   cn30xx;
-    struct cvmx_npi_port32_instr_hdr_s   cn31xx;
-    struct cvmx_npi_port32_instr_hdr_s   cn38xx;
-    struct cvmx_npi_port32_instr_hdr_s   cn38xxp2;
-    struct cvmx_npi_port32_instr_hdr_s   cn50xx;
-    struct cvmx_npi_port32_instr_hdr_s   cn58xx;
-    struct cvmx_npi_port32_instr_hdr_s   cn58xxp1;
-} cvmx_npi_port32_instr_hdr_t;
-
-
-/**
- * cvmx_npi_port33_instr_hdr
- *
- * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header
- * 
- * Contains bits [62:42] of the Instruction Header for port 33.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_port33_instr_hdr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
-        uint64_t rsv_f                   : 5;       /**< Reserved */
-        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
-        uint64_t rsv_e                   : 1;       /**< Reserved */
-        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
-        uint64_t rsv_d                   : 6;       /**< Reserved */
-        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
-                                                         USE_IHDR must be set whenever PBP is set. */
-        uint64_t rsv_c                   : 5;       /**< Reserved */
-        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_b                   : 1;       /**< Reserved
-                                                         instruction header sent to IPD. */
-        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_a                   : 6;       /**< Reserved */
-#else
-        uint64_t rsv_a                   : 6;
-        uint64_t skp_len                 : 7;
-        uint64_t rsv_b                   : 1;
-        uint64_t par_mode                : 2;
-        uint64_t rsv_c                   : 5;
-        uint64_t use_ihdr                : 1;
-        uint64_t rsv_d                   : 6;
-        uint64_t rskp_len                : 7;
-        uint64_t rsv_e                   : 1;
-        uint64_t rparmode                : 2;
-        uint64_t rsv_f                   : 5;
-        uint64_t pbp                     : 1;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npi_port33_instr_hdr_s   cn31xx;
-    struct cvmx_npi_port33_instr_hdr_s   cn38xx;
-    struct cvmx_npi_port33_instr_hdr_s   cn38xxp2;
-    struct cvmx_npi_port33_instr_hdr_s   cn50xx;
-    struct cvmx_npi_port33_instr_hdr_s   cn58xx;
-    struct cvmx_npi_port33_instr_hdr_s   cn58xxp1;
-} cvmx_npi_port33_instr_hdr_t;
-
-
-/**
- * cvmx_npi_port34_instr_hdr
- *
- * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header
- * 
- * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_port34_instr_hdr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
-        uint64_t rsv_f                   : 5;       /**< Reserved */
-        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
-        uint64_t rsv_e                   : 1;       /**< Reserved */
-        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
-        uint64_t rsv_d                   : 6;       /**< Reserved */
-        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
-                                                         USE_IHDR must be set whenever PBP is set. */
-        uint64_t rsv_c                   : 5;       /**< Reserved */
-        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_b                   : 1;       /**< Reserved
-                                                         instruction header sent to IPD. */
-        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_a                   : 6;       /**< Reserved */
-#else
-        uint64_t rsv_a                   : 6;
-        uint64_t skp_len                 : 7;
-        uint64_t rsv_b                   : 1;
-        uint64_t par_mode                : 2;
-        uint64_t rsv_c                   : 5;
-        uint64_t use_ihdr                : 1;
-        uint64_t rsv_d                   : 6;
-        uint64_t rskp_len                : 7;
-        uint64_t rsv_e                   : 1;
-        uint64_t rparmode                : 2;
-        uint64_t rsv_f                   : 5;
-        uint64_t pbp                     : 1;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npi_port34_instr_hdr_s   cn38xx;
-    struct cvmx_npi_port34_instr_hdr_s   cn38xxp2;
-    struct cvmx_npi_port34_instr_hdr_s   cn58xx;
-    struct cvmx_npi_port34_instr_hdr_s   cn58xxp1;
-} cvmx_npi_port34_instr_hdr_t;
-
-
-/**
- * cvmx_npi_port35_instr_hdr
- *
- * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header
- * 
- * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_port35_instr_hdr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_44_63          : 20;
-        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
-        uint64_t rsv_f                   : 5;       /**< Reserved */
-        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
-        uint64_t rsv_e                   : 1;       /**< Reserved */
-        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
-        uint64_t rsv_d                   : 6;       /**< Reserved */
-        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
-                                                         as part of the packet data, regardless of the
-                                                         value of bit [63] of the instruction header.
-                                                         USE_IHDR must be set whenever PBP is set. */
-        uint64_t rsv_c                   : 5;       /**< Reserved */
-        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_b                   : 1;       /**< Reserved
-                                                         instruction header sent to IPD. */
-        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
-                                                         is not raw and PBP is not set. */
-        uint64_t rsv_a                   : 6;       /**< Reserved */
-#else
-        uint64_t rsv_a                   : 6;
-        uint64_t skp_len                 : 7;
-        uint64_t rsv_b                   : 1;
-        uint64_t par_mode                : 2;
-        uint64_t rsv_c                   : 5;
-        uint64_t use_ihdr                : 1;
-        uint64_t rsv_d                   : 6;
-        uint64_t rskp_len                : 7;
-        uint64_t rsv_e                   : 1;
-        uint64_t rparmode                : 2;
-        uint64_t rsv_f                   : 5;
-        uint64_t pbp                     : 1;
-        uint64_t reserved_44_63          : 20;
-#endif
-    } s;
-    struct cvmx_npi_port35_instr_hdr_s   cn38xx;
-    struct cvmx_npi_port35_instr_hdr_s   cn38xxp2;
-    struct cvmx_npi_port35_instr_hdr_s   cn58xx;
-    struct cvmx_npi_port35_instr_hdr_s   cn58xxp1;
-} cvmx_npi_port35_instr_hdr_t;
-
-
-/**
- * cvmx_npi_port_bp_control
- *
- * NPI_PORT_BP_CONTROL = Port Backpressure Control
- * 
- * Enables Port Level Backpressure
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_port_bp_control_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t bp_on                   : 4;       /**< Port 35-32 port level backpressure applied. */
-        uint64_t enb                     : 4;       /**< Enables port level backpressure from the IPD. */
-#else
-        uint64_t enb                     : 4;
-        uint64_t bp_on                   : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_npi_port_bp_control_s    cn30xx;
-    struct cvmx_npi_port_bp_control_s    cn31xx;
-    struct cvmx_npi_port_bp_control_s    cn38xx;
-    struct cvmx_npi_port_bp_control_s    cn38xxp2;
-    struct cvmx_npi_port_bp_control_s    cn50xx;
-    struct cvmx_npi_port_bp_control_s    cn58xx;
-    struct cvmx_npi_port_bp_control_s    cn58xxp1;
-} cvmx_npi_port_bp_control_t;
-
-
-/**
- * cvmx_npi_rsl_int_blocks
- *
- * RSL_INT_BLOCKS = RSL Interrupt Blocks Register
- * 
- * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
- * that presently has an interrupt pending. The Field Description below supplies the name of the
- * register that software should read to find out why that intterupt bit is set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_rsl_int_blocks_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
-        uint64_t reserved_28_29          : 2;
-        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
-        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
-        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
-        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
-        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
-        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
-        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
-        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t reserved_13_14          : 2;
-        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
-        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
-        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
-        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
-        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t zip                     : 1;       /**< ZIP_ERROR */
-        uint64_t dfa                     : 1;       /**< DFA_ERR */
-        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
-        uint64_t key                     : 1;       /**< KEY_INT_SUM */
-        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
-        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
-        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
-        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
-#else
-        uint64_t mio                     : 1;
-        uint64_t gmx0                    : 1;
-        uint64_t gmx1                    : 1;
-        uint64_t npi                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rint_8                  : 1;
-        uint64_t ipd                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t tim                     : 1;
-        uint64_t pow                     : 1;
-        uint64_t reserved_13_14          : 2;
-        uint64_t rint_15                 : 1;
-        uint64_t l2c                     : 1;
-        uint64_t lmc                     : 1;
-        uint64_t spx0                    : 1;
-        uint64_t spx1                    : 1;
-        uint64_t pip                     : 1;
-        uint64_t rint_21                 : 1;
-        uint64_t asx0                    : 1;
-        uint64_t asx1                    : 1;
-        uint64_t rint_24                 : 1;
-        uint64_t rint_25                 : 1;
-        uint64_t rint_26                 : 1;
-        uint64_t rint_27                 : 1;
-        uint64_t reserved_28_29          : 2;
-        uint64_t iob                     : 1;
-        uint64_t rint_31                 : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npi_rsl_int_blocks_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
-        uint64_t rint_29                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_28                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
-        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
-        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
-        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
-        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
-        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
-        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
-        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_14                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t usb                     : 1;       /**< USBN_INT_SUM */
-        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
-        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
-        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
-        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
-        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t zip                     : 1;       /**< ZIP_ERROR */
-        uint64_t dfa                     : 1;       /**< DFA_ERR */
-        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
-        uint64_t key                     : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
-        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
-        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
-        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
-#else
-        uint64_t mio                     : 1;
-        uint64_t gmx0                    : 1;
-        uint64_t gmx1                    : 1;
-        uint64_t npi                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rint_8                  : 1;
-        uint64_t ipd                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t tim                     : 1;
-        uint64_t pow                     : 1;
-        uint64_t usb                     : 1;
-        uint64_t rint_14                 : 1;
-        uint64_t rint_15                 : 1;
-        uint64_t l2c                     : 1;
-        uint64_t lmc                     : 1;
-        uint64_t spx0                    : 1;
-        uint64_t spx1                    : 1;
-        uint64_t pip                     : 1;
-        uint64_t rint_21                 : 1;
-        uint64_t asx0                    : 1;
-        uint64_t asx1                    : 1;
-        uint64_t rint_24                 : 1;
-        uint64_t rint_25                 : 1;
-        uint64_t rint_26                 : 1;
-        uint64_t rint_27                 : 1;
-        uint64_t rint_28                 : 1;
-        uint64_t rint_29                 : 1;
-        uint64_t iob                     : 1;
-        uint64_t rint_31                 : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn30xx;
-    struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
-    struct cvmx_npi_rsl_int_blocks_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
-        uint64_t rint_29                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_28                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
-        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
-        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
-        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
-        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
-        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
-        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
-        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_14                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t rint_13                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
-        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
-        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
-        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
-        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
-        uint64_t zip                     : 1;       /**< ZIP_ERROR */
-        uint64_t dfa                     : 1;       /**< DFA_ERR */
-        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
-        uint64_t key                     : 1;       /**< KEY_INT_SUM */
-        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
-        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
-        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
-        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
-#else
-        uint64_t mio                     : 1;
-        uint64_t gmx0                    : 1;
-        uint64_t gmx1                    : 1;
-        uint64_t npi                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rint_8                  : 1;
-        uint64_t ipd                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t tim                     : 1;
-        uint64_t pow                     : 1;
-        uint64_t rint_13                 : 1;
-        uint64_t rint_14                 : 1;
-        uint64_t rint_15                 : 1;
-        uint64_t l2c                     : 1;
-        uint64_t lmc                     : 1;
-        uint64_t spx0                    : 1;
-        uint64_t spx1                    : 1;
-        uint64_t pip                     : 1;
-        uint64_t rint_21                 : 1;
-        uint64_t asx0                    : 1;
-        uint64_t asx1                    : 1;
-        uint64_t rint_24                 : 1;
-        uint64_t rint_25                 : 1;
-        uint64_t rint_26                 : 1;
-        uint64_t rint_27                 : 1;
-        uint64_t rint_28                 : 1;
-        uint64_t rint_29                 : 1;
-        uint64_t iob                     : 1;
-        uint64_t rint_31                 : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
-    struct cvmx_npi_rsl_int_blocks_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
-        uint64_t lmc1                    : 1;       /**< Always reads as zero */
-        uint64_t agl                     : 1;       /**< Always reads as zero */
-        uint64_t reserved_24_27          : 4;
-        uint64_t asx1                    : 1;       /**< Always reads as zero */
-        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
-        uint64_t reserved_21_21          : 1;
-        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
-        uint64_t spx1                    : 1;       /**< Always reads as zero */
-        uint64_t spx0                    : 1;       /**< Always reads as zero */
-        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
-        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
-        uint64_t reserved_15_15          : 1;
-        uint64_t rad                     : 1;       /**< Always reads as zero */
-        uint64_t usb                     : 1;       /**< USBN_INT_SUM */
-        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
-        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
-        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
-        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
-        uint64_t reserved_8_8            : 1;
-        uint64_t zip                     : 1;       /**< Always reads as zero */
-        uint64_t dfa                     : 1;       /**< Always reads as zero */
-        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
-        uint64_t key                     : 1;       /**< Always reads as zero */
-        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
-        uint64_t gmx1                    : 1;       /**< Always reads as zero */
-        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
-        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
-#else
-        uint64_t mio                     : 1;
-        uint64_t gmx0                    : 1;
-        uint64_t gmx1                    : 1;
-        uint64_t npi                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t reserved_8_8            : 1;
-        uint64_t ipd                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t tim                     : 1;
-        uint64_t pow                     : 1;
-        uint64_t usb                     : 1;
-        uint64_t rad                     : 1;
-        uint64_t reserved_15_15          : 1;
-        uint64_t l2c                     : 1;
-        uint64_t lmc                     : 1;
-        uint64_t spx0                    : 1;
-        uint64_t spx1                    : 1;
-        uint64_t pip                     : 1;
-        uint64_t reserved_21_21          : 1;
-        uint64_t asx0                    : 1;
-        uint64_t asx1                    : 1;
-        uint64_t reserved_24_27          : 4;
-        uint64_t agl                     : 1;
-        uint64_t lmc1                    : 1;
-        uint64_t iob                     : 1;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } cn50xx;
-    struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
-    struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
-} cvmx_npi_rsl_int_blocks_t;
-
-
-/**
- * cvmx_npi_size_input#
- *
- * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register
- * 
- * The size (in instructions) of Instruction Queue-0.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_size_inputx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t size                    : 32;      /**< The size of the Instruction Queue used by Octane.
-                                                         The value [SIZE] is in Instructions.
-                                                         A value of 0 in this field is illegal. */
-#else
-        uint64_t size                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npi_size_inputx_s        cn30xx;
-    struct cvmx_npi_size_inputx_s        cn31xx;
-    struct cvmx_npi_size_inputx_s        cn38xx;
-    struct cvmx_npi_size_inputx_s        cn38xxp2;
-    struct cvmx_npi_size_inputx_s        cn50xx;
-    struct cvmx_npi_size_inputx_s        cn58xx;
-    struct cvmx_npi_size_inputx_s        cn58xxp1;
-} cvmx_npi_size_inputx_t;
-
-
-/**
- * cvmx_npi_win_read_to
- *
- * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register
- * 
- * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_npi_win_read_to_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t time                    : 32;      /**< Time to wait in core clocks. A value of 0 will
-                                                         cause no timeouts. */
-#else
-        uint64_t time                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_npi_win_read_to_s        cn30xx;
-    struct cvmx_npi_win_read_to_s        cn31xx;
-    struct cvmx_npi_win_read_to_s        cn38xx;
-    struct cvmx_npi_win_read_to_s        cn38xxp2;
-    struct cvmx_npi_win_read_to_s        cn50xx;
-    struct cvmx_npi_win_read_to_s        cn58xx;
-    struct cvmx_npi_win_read_to_s        cn58xxp1;
-} cvmx_npi_win_read_to_t;
-
-
-/**
- * cvmx_pci_bar1_index#
- *
- * PCI_BAR1_INDEXX = PCI IndexX Register
- * 
- * Contains address index and control bits for access to memory ranges of Bar-1,
- * when PCI supplied address-bits [26:22] == X.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_bar1_indexx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_18_31          : 14;
-        uint32_t addr_idx                : 14;      /**< Address bits [35:22] sent to L2C */
-        uint32_t ca                      : 1;       /**< Set '1' when access is not to be cached in L2. */
-        uint32_t end_swp                 : 2;       /**< Endian Swap Mode */
-        uint32_t addr_v                  : 1;       /**< Set '1' when the selected address range is valid. */
-#else
-        uint32_t addr_v                  : 1;
-        uint32_t end_swp                 : 2;
-        uint32_t ca                      : 1;
-        uint32_t addr_idx                : 14;
-        uint32_t reserved_18_31          : 14;
-#endif
-    } s;
-    struct cvmx_pci_bar1_indexx_s        cn30xx;
-    struct cvmx_pci_bar1_indexx_s        cn31xx;
-    struct cvmx_pci_bar1_indexx_s        cn38xx;
-    struct cvmx_pci_bar1_indexx_s        cn38xxp2;
-    struct cvmx_pci_bar1_indexx_s        cn50xx;
-    struct cvmx_pci_bar1_indexx_s        cn58xx;
-    struct cvmx_pci_bar1_indexx_s        cn58xxp1;
-} cvmx_pci_bar1_indexx_t;
-
-
-/**
- * cvmx_pci_bist_reg
- *
- * PCI_BIST_REG = PCI PNI BIST Status Register
- * 
- * Contains the bist results for the PNI memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_bist_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t rsp_bs                  : 1;       /**< Bist Status For b12_rsp_fifo_bist
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t dma0_bs                 : 1;       /**< Bist Status For dmao_count
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t cmd0_bs                 : 1;       /**< Bist Status For npi_cmd0_pni_am0
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t cmd_bs                  : 1;       /**< Bist Status For npi_cmd_pni_am1
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t csr2p_bs                : 1;       /**< Bist Status For npi_csr_2_pni_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t csrr_bs                 : 1;       /**< Bist Status For npi_csr_rsp_2_pni_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t rsp2p_bs                : 1;       /**< Bist Status For npi_rsp_2_pni_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t csr2n_bs                : 1;       /**< Bist Status For pni_csr_2_npi_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t dat2n_bs                : 1;       /**< Bist Status For pni_data_2_npi_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-        uint64_t dbg2n_bs                : 1;       /**< Bist Status For pni_dbg_data_2_npi_am
-                                                         The value of this register is available 100,000
-                                                         core clocks + 21,000 pclks after:
-                                                         Host Mode - deassertion of pci_rst_n
-                                                         Non Host Mode - deassertion of pci_rst_n */
-#else
-        uint64_t dbg2n_bs                : 1;
-        uint64_t dat2n_bs                : 1;
-        uint64_t csr2n_bs                : 1;
-        uint64_t rsp2p_bs                : 1;
-        uint64_t csrr_bs                 : 1;
-        uint64_t csr2p_bs                : 1;
-        uint64_t cmd_bs                  : 1;
-        uint64_t cmd0_bs                 : 1;
-        uint64_t dma0_bs                 : 1;
-        uint64_t rsp_bs                  : 1;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_pci_bist_reg_s           cn50xx;
-} cvmx_pci_bist_reg_t;
-
-
-/**
- * cvmx_pci_cfg00
- *
- * Registers at address 0x1000 -> 0x17FF are PNI
- * Start at 0x100 into range
- * these are shifted by 2 to the left to make address
- *                Registers at address 0x1800 -> 0x18FF are CFG
- * these are shifted by 2 to the left to make address
- * 
- *           PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device)
- * 
- * This register contains the first 32-bits of the PCI config space registers
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg00_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t devid                   : 16;      /**< This is the device ID for OCTEON (90nm shhrink) */
-        uint32_t vendid                  : 16;      /**< This is the Cavium's vendor ID */
-#else
-        uint32_t vendid                  : 16;
-        uint32_t devid                   : 16;
-#endif
-    } s;
-    struct cvmx_pci_cfg00_s              cn30xx;
-    struct cvmx_pci_cfg00_s              cn31xx;
-    struct cvmx_pci_cfg00_s              cn38xx;
-    struct cvmx_pci_cfg00_s              cn38xxp2;
-    struct cvmx_pci_cfg00_s              cn50xx;
-    struct cvmx_pci_cfg00_s              cn58xx;
-    struct cvmx_pci_cfg00_s              cn58xxp1;
-} cvmx_pci_cfg00_t;
-
-
-/**
- * cvmx_pci_cfg01
- *
- * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg01_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dpe                     : 1;       /**< Detected Parity Error */
-        uint32_t sse                     : 1;       /**< Signaled System Error */
-        uint32_t rma                     : 1;       /**< Received Master Abort */
-        uint32_t rta                     : 1;       /**< Received Target Abort */
-        uint32_t sta                     : 1;       /**< Signaled Target Abort */
-        uint32_t devt                    : 2;       /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */
-        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
-        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Transactions Capable
-                                                         Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */
-        uint32_t reserved_22_22          : 1;
-        uint32_t m66                     : 1;       /**< 66MHz Capable */
-        uint32_t cle                     : 1;       /**< Capabilities List Enable */
-        uint32_t i_stat                  : 1;       /**< When INTx# is asserted by OCTEON this bit will be set.
-                                                         When deasserted by OCTEON this bit will be cleared. */
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_dis                   : 1;       /**< When asserted '1' disables the generation of INTx#
-                                                         by OCTEON. When disabled '0' allows assertion of INTx#
-                                                         by OCTEON. */
-        uint32_t fbbe                    : 1;       /**< Fast Back to Back Transaction Enable */
-        uint32_t see                     : 1;       /**< System Error Enable */
-        uint32_t ads                     : 1;       /**< Address/Data Stepping
-                                                         NOTE: Octeon does NOT support address/data stepping. */
-        uint32_t pee                     : 1;       /**< PERR# Enable */
-        uint32_t vps                     : 1;       /**< VGA Palette Snooping */
-        uint32_t mwice                   : 1;       /**< Memory Write & Invalidate Command Enable */
-        uint32_t scse                    : 1;       /**< Special Cycle Snooping Enable */
-        uint32_t me                      : 1;       /**< Master Enable
-                                                         Must be set for OCTEON to master a PCI/PCI-X
-                                                         transaction. This should always be set any time
-                                                         that OCTEON is connected to a PCI/PCI-X bus. */
-        uint32_t msae                    : 1;       /**< Memory Space Access Enable
-                                                         Must be set to recieve a PCI/PCI-X memory space
-                                                         transaction. This must always be set any time that
-                                                         OCTEON is connected to a PCI/PCI-X bus. */
-        uint32_t isae                    : 1;       /**< I/O Space Access Enable
-                                                         NOTE: For OCTEON, this bit MUST NEVER be set
-                                                         (it is read-only and OCTEON does not respond to I/O
-                                                         Space accesses). */
-#else
-        uint32_t isae                    : 1;
-        uint32_t msae                    : 1;
-        uint32_t me                      : 1;
-        uint32_t scse                    : 1;
-        uint32_t mwice                   : 1;
-        uint32_t vps                     : 1;
-        uint32_t pee                     : 1;
-        uint32_t ads                     : 1;
-        uint32_t see                     : 1;
-        uint32_t fbbe                    : 1;
-        uint32_t i_dis                   : 1;
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_stat                  : 1;
-        uint32_t cle                     : 1;
-        uint32_t m66                     : 1;
-        uint32_t reserved_22_22          : 1;
-        uint32_t fbb                     : 1;
-        uint32_t mdpe                    : 1;
-        uint32_t devt                    : 2;
-        uint32_t sta                     : 1;
-        uint32_t rta                     : 1;
-        uint32_t rma                     : 1;
-        uint32_t sse                     : 1;
-        uint32_t dpe                     : 1;
-#endif
-    } s;
-    struct cvmx_pci_cfg01_s              cn30xx;
-    struct cvmx_pci_cfg01_s              cn31xx;
-    struct cvmx_pci_cfg01_s              cn38xx;
-    struct cvmx_pci_cfg01_s              cn38xxp2;
-    struct cvmx_pci_cfg01_s              cn50xx;
-    struct cvmx_pci_cfg01_s              cn58xx;
-    struct cvmx_pci_cfg01_s              cn58xxp1;
-} cvmx_pci_cfg01_t;
-
-
-/**
- * cvmx_pci_cfg02
- *
- * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg02_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t cc                      : 24;      /**< Class Code (Processor/MIPS)
-                                                         (was 0x100000 in pass 1 and pass 2) */
-        uint32_t rid                     : 8;       /**< Revision ID
-                                                         (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */
-#else
-        uint32_t rid                     : 8;
-        uint32_t cc                      : 24;
-#endif
-    } s;
-    struct cvmx_pci_cfg02_s              cn30xx;
-    struct cvmx_pci_cfg02_s              cn31xx;
-    struct cvmx_pci_cfg02_s              cn38xx;
-    struct cvmx_pci_cfg02_s              cn38xxp2;
-    struct cvmx_pci_cfg02_s              cn50xx;
-    struct cvmx_pci_cfg02_s              cn58xx;
-    struct cvmx_pci_cfg02_s              cn58xxp1;
-} cvmx_pci_cfg02_t;
-
-
-/**
- * cvmx_pci_cfg03
- *
- * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg03_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t bcap                    : 1;       /**< BIST Capable */
-        uint32_t brb                     : 1;       /**< BIST Request/busy bit
-                                                         Note: OCTEON does not support PCI BIST, therefore
-                                                         this bit should remain zero. */
-        uint32_t reserved_28_29          : 2;
-        uint32_t bcod                    : 4;       /**< BIST Code */
-        uint32_t ht                      : 8;       /**< Header Type (Type 0) */
-        uint32_t lt                      : 8;       /**< Latency Timer
-                                                         (0=PCI)                 (0=PCI)
-                                                         (0x40=PCIX)             (0x40=PCIX) */
-        uint32_t cls                     : 8;       /**< Cache Line Size */
-#else
-        uint32_t cls                     : 8;
-        uint32_t lt                      : 8;
-        uint32_t ht                      : 8;
-        uint32_t bcod                    : 4;
-        uint32_t reserved_28_29          : 2;
-        uint32_t brb                     : 1;
-        uint32_t bcap                    : 1;
-#endif
-    } s;
-    struct cvmx_pci_cfg03_s              cn30xx;
-    struct cvmx_pci_cfg03_s              cn31xx;
-    struct cvmx_pci_cfg03_s              cn38xx;
-    struct cvmx_pci_cfg03_s              cn38xxp2;
-    struct cvmx_pci_cfg03_s              cn50xx;
-    struct cvmx_pci_cfg03_s              cn58xx;
-    struct cvmx_pci_cfg03_s              cn58xxp1;
-} cvmx_pci_cfg03_t;
-
-
-/**
- * cvmx_pci_cfg04
- *
- * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low)
- * 
- * Description: BAR0: 4KB 64-bit Prefetchable Memory Space
- *       [0]:     0 (Memory Space)
- *       [2:1]:   2 (64bit memory decoder)
- *       [3]:     1 (Prefetchable)
- *       [11:4]:  RAZ (to imply 4KB space)
- *       [31:12]: RW (User may define base address)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg04_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lbase                   : 20;      /**< Base Address[31:12]
-                                                         Base Address[30:12] read as zero if
-                                                         PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */
-        uint32_t lbasez                  : 8;       /**< Base Address[11:4] (Read as Zero) */
-        uint32_t pf                      : 1;       /**< Prefetchable Space */
-        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t lbasez                  : 8;
-        uint32_t lbase                   : 20;
-#endif
-    } s;
-    struct cvmx_pci_cfg04_s              cn30xx;
-    struct cvmx_pci_cfg04_s              cn31xx;
-    struct cvmx_pci_cfg04_s              cn38xx;
-    struct cvmx_pci_cfg04_s              cn38xxp2;
-    struct cvmx_pci_cfg04_s              cn50xx;
-    struct cvmx_pci_cfg04_s              cn58xx;
-    struct cvmx_pci_cfg04_s              cn58xxp1;
-} cvmx_pci_cfg04_t;
-
-
-/**
- * cvmx_pci_cfg05
- *
- * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg05_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t hbase                   : 32;      /**< Base Address[63:32] */
-#else
-        uint32_t hbase                   : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg05_s              cn30xx;
-    struct cvmx_pci_cfg05_s              cn31xx;
-    struct cvmx_pci_cfg05_s              cn38xx;
-    struct cvmx_pci_cfg05_s              cn38xxp2;
-    struct cvmx_pci_cfg05_s              cn50xx;
-    struct cvmx_pci_cfg05_s              cn58xx;
-    struct cvmx_pci_cfg05_s              cn58xxp1;
-} cvmx_pci_cfg05_t;
-
-
-/**
- * cvmx_pci_cfg06
- *
- * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low)
- * 
- * Description: BAR1: 128MB 64-bit Prefetchable Memory Space
- *       [0]:     0 (Memory Space)
- *       [2:1]:   2 (64bit memory decoder)
- *       [3]:     1 (Prefetchable)
- *       [26:4]:  RAZ (to imply 128MB space)
- *       [31:27]: RW (User may define base address)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg06_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lbase                   : 5;       /**< Base Address[31:27]
-                                                         In pass 3+:
-                                                           Base Address[29:27] read as zero if
-                                                            PCI_CTL_STATUS_2[BB1] is set
-                                                           Base Address[30] reads as zero if
-                                                            PCI_CTL_STATUS_2[BB1] is set and
-                                                            PCI_CTL_STATUS_2[BB1_SIZE] is set */
-        uint32_t lbasez                  : 23;      /**< Base Address[26:4] (Read as Zero) */
-        uint32_t pf                      : 1;       /**< Prefetchable Space */
-        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t lbasez                  : 23;
-        uint32_t lbase                   : 5;
-#endif
-    } s;
-    struct cvmx_pci_cfg06_s              cn30xx;
-    struct cvmx_pci_cfg06_s              cn31xx;
-    struct cvmx_pci_cfg06_s              cn38xx;
-    struct cvmx_pci_cfg06_s              cn38xxp2;
-    struct cvmx_pci_cfg06_s              cn50xx;
-    struct cvmx_pci_cfg06_s              cn58xx;
-    struct cvmx_pci_cfg06_s              cn58xxp1;
-} cvmx_pci_cfg06_t;
-
-
-/**
- * cvmx_pci_cfg07
- *
- * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg07_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t hbase                   : 32;      /**< Base Address[63:32] */
-#else
-        uint32_t hbase                   : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg07_s              cn30xx;
-    struct cvmx_pci_cfg07_s              cn31xx;
-    struct cvmx_pci_cfg07_s              cn38xx;
-    struct cvmx_pci_cfg07_s              cn38xxp2;
-    struct cvmx_pci_cfg07_s              cn50xx;
-    struct cvmx_pci_cfg07_s              cn58xx;
-    struct cvmx_pci_cfg07_s              cn58xxp1;
-} cvmx_pci_cfg07_t;
-
-
-/**
- * cvmx_pci_cfg08
- *
- * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low)
- * 
- * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space
- *       [0]:     0 (Memory Space)
- *       [2:1]:   2 (64bit memory decoder)
- *       [3]:     1 (Prefetchable)
- *       [31:4]:  RAZ
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg08_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lbasez                  : 28;      /**< Base Address[31:4] (Read as Zero) */
-        uint32_t pf                      : 1;       /**< Prefetchable Space */
-        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t lbasez                  : 28;
-#endif
-    } s;
-    struct cvmx_pci_cfg08_s              cn30xx;
-    struct cvmx_pci_cfg08_s              cn31xx;
-    struct cvmx_pci_cfg08_s              cn38xx;
-    struct cvmx_pci_cfg08_s              cn38xxp2;
-    struct cvmx_pci_cfg08_s              cn50xx;
-    struct cvmx_pci_cfg08_s              cn58xx;
-    struct cvmx_pci_cfg08_s              cn58xxp1;
-} cvmx_pci_cfg08_t;
-
-
-/**
- * cvmx_pci_cfg09
- *
- * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg09_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t hbase                   : 25;      /**< Base Address[63:39] */
-        uint32_t hbasez                  : 7;       /**< Base Address[38:31]  (Read as Zero) */
-#else
-        uint32_t hbasez                  : 7;
-        uint32_t hbase                   : 25;
-#endif
-    } s;
-    struct cvmx_pci_cfg09_s              cn30xx;
-    struct cvmx_pci_cfg09_s              cn31xx;
-    struct cvmx_pci_cfg09_s              cn38xx;
-    struct cvmx_pci_cfg09_s              cn38xxp2;
-    struct cvmx_pci_cfg09_s              cn50xx;
-    struct cvmx_pci_cfg09_s              cn58xx;
-    struct cvmx_pci_cfg09_s              cn58xxp1;
-} cvmx_pci_cfg09_t;
-
-
-/**
- * cvmx_pci_cfg10
- *
- * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg10_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t cisp                    : 32;      /**< CardBus CIS Pointer (UNUSED) */
-#else
-        uint32_t cisp                    : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg10_s              cn30xx;
-    struct cvmx_pci_cfg10_s              cn31xx;
-    struct cvmx_pci_cfg10_s              cn38xx;
-    struct cvmx_pci_cfg10_s              cn38xxp2;
-    struct cvmx_pci_cfg10_s              cn50xx;
-    struct cvmx_pci_cfg10_s              cn58xx;
-    struct cvmx_pci_cfg10_s              cn58xxp1;
-} cvmx_pci_cfg10_t;
-
-
-/**
- * cvmx_pci_cfg11
- *
- * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg11_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ssid                    : 16;      /**< SubSystem ID */
-        uint32_t ssvid                   : 16;      /**< Subsystem Vendor ID */
-#else
-        uint32_t ssvid                   : 16;
-        uint32_t ssid                    : 16;
-#endif
-    } s;
-    struct cvmx_pci_cfg11_s              cn30xx;
-    struct cvmx_pci_cfg11_s              cn31xx;
-    struct cvmx_pci_cfg11_s              cn38xx;
-    struct cvmx_pci_cfg11_s              cn38xxp2;
-    struct cvmx_pci_cfg11_s              cn50xx;
-    struct cvmx_pci_cfg11_s              cn58xx;
-    struct cvmx_pci_cfg11_s              cn58xxp1;
-} cvmx_pci_cfg11_t;
-
-
-/**
- * cvmx_pci_cfg12
- *
- * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg12_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t erbar                   : 16;      /**< Expansion ROM Base Address[31:16] 64KB in size */
-        uint32_t erbarz                  : 5;       /**< Expansion ROM Base Base Address (Read as Zero) */
-        uint32_t reserved_1_10           : 10;
-        uint32_t erbar_en                : 1;       /**< Expansion ROM Address Decode Enable */
-#else
-        uint32_t erbar_en                : 1;
-        uint32_t reserved_1_10           : 10;
-        uint32_t erbarz                  : 5;
-        uint32_t erbar                   : 16;
-#endif
-    } s;
-    struct cvmx_pci_cfg12_s              cn30xx;
-    struct cvmx_pci_cfg12_s              cn31xx;
-    struct cvmx_pci_cfg12_s              cn38xx;
-    struct cvmx_pci_cfg12_s              cn38xxp2;
-    struct cvmx_pci_cfg12_s              cn50xx;
-    struct cvmx_pci_cfg12_s              cn58xx;
-    struct cvmx_pci_cfg12_s              cn58xxp1;
-} cvmx_pci_cfg12_t;
-
-
-/**
- * cvmx_pci_cfg13
- *
- * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg13_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_8_31           : 24;
-        uint32_t cp                      : 8;       /**< Capabilities Pointer */
-#else
-        uint32_t cp                      : 8;
-        uint32_t reserved_8_31           : 24;
-#endif
-    } s;
-    struct cvmx_pci_cfg13_s              cn30xx;
-    struct cvmx_pci_cfg13_s              cn31xx;
-    struct cvmx_pci_cfg13_s              cn38xx;
-    struct cvmx_pci_cfg13_s              cn38xxp2;
-    struct cvmx_pci_cfg13_s              cn50xx;
-    struct cvmx_pci_cfg13_s              cn58xx;
-    struct cvmx_pci_cfg13_s              cn58xxp1;
-} cvmx_pci_cfg13_t;
-
-
-/**
- * cvmx_pci_cfg15
- *
- * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg15_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ml                      : 8;       /**< Maximum Latency */
-        uint32_t mg                      : 8;       /**< Minimum Grant */
-        uint32_t inta                    : 8;       /**< Interrupt Pin (INTA#) */
-        uint32_t il                      : 8;       /**< Interrupt Line */
-#else
-        uint32_t il                      : 8;
-        uint32_t inta                    : 8;
-        uint32_t mg                      : 8;
-        uint32_t ml                      : 8;
-#endif
-    } s;
-    struct cvmx_pci_cfg15_s              cn30xx;
-    struct cvmx_pci_cfg15_s              cn31xx;
-    struct cvmx_pci_cfg15_s              cn38xx;
-    struct cvmx_pci_cfg15_s              cn38xxp2;
-    struct cvmx_pci_cfg15_s              cn50xx;
-    struct cvmx_pci_cfg15_s              cn58xx;
-    struct cvmx_pci_cfg15_s              cn58xxp1;
-} cvmx_pci_cfg15_t;
-
-
-/**
- * cvmx_pci_cfg16
- *
- * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg16_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t trdnpr                  : 1;       /**< Target Read Delayed Transaction for I/O and
-                                                         non-prefetchable regions discarded. */
-        uint32_t trdard                  : 1;       /**< Target Read Delayed Transaction for all regions
-                                                         discarded. */
-        uint32_t rdsati                  : 1;       /**< Target(I/O and Memory) Read Delayed/Split at
-                                                          timeout/immediately (default timeout).
-                                                         Note: OCTEON requires that this bit MBZ(must be zero). */
-        uint32_t trdrs                   : 1;       /**< Target(I/O and Memory) Read Delayed/Split or Retry
-                                                         select (of the application interface is not ready)
-                                                          0 = Delayed Split Transaction
-                                                          1 = Retry Transaction (always Immediate Retry, no
-                                                              AT_REQ to application). */
-        uint32_t trtae                   : 1;       /**< Target(I/O and Memory) Read Target Abort Enable
-                                                         (if application interface is not ready at the
-                                                         latency timeout).
-                                                         Note: OCTEON as target will never target-abort,
-                                                         therefore this bit should never be set. */
-        uint32_t twsei                   : 1;       /**< Target(I/O) Write Split Enable (at timeout /
-                                                         immediately; default timeout) */
-        uint32_t twsen                   : 1;       /**< T(I/O) write split Enable (if the application
-                                                         interface is not ready) */
-        uint32_t twtae                   : 1;       /**< Target(I/O and Memory) Write Target Abort Enable
-                                                         (if the application interface is not ready at the
-                                                         start of the cycle).
-                                                         Note: OCTEON as target will never target-abort,
-                                                         therefore this bit should never be set. */
-        uint32_t tmae                    : 1;       /**< Target(Read/Write) Master Abort Enable; check
-                                                         at the start of each transaction.
-                                                         Note: This bit can be used to force a Master
-                                                         Abort when OCTEON is acting as the intended target
-                                                         device. */
-        uint32_t tslte                   : 3;       /**< Target Subsequent(2nd-last) Latency Timeout Enable
-                                                         Valid range: [1..7] and 0=8. */
-        uint32_t tilt                    : 4;       /**< Target Initial(1st data) Latency Timeout in PCI
-                                                         ModeValid range: [8..15] and 0=16. */
-        uint32_t pbe                     : 12;      /**< Programmable Boundary Enable to disconnect/prefetch
-                                                         for target burst read cycles to prefetchable
-                                                         region in PCI. A value of 1 indicates end of
-                                                         boundary (64 KB down to 16 Bytes). */
-        uint32_t dppmr                   : 1;       /**< Disconnect/Prefetch to prefetchable memory
-                                                         regions Enable. Prefetchable memory regions
-                                                         are always disconnected on a region boundary.
-                                                         Non-prefetchable regions for PCI are always
-                                                         disconnected on the first transfer.
-                                                         Note: OCTEON as target will never target-disconnect,
-                                                         therefore this bit should never be set. */
-        uint32_t reserved_2_2            : 1;
-        uint32_t tswc                    : 1;       /**< Target Split Write Control
-                                                         0 = Blocks all requests except PMW
-                                                         1 = Blocks all requests including PMW until
-                                                             split completion occurs. */
-        uint32_t mltd                    : 1;       /**< Master Latency Timer Disable
-                                                         Note: For OCTEON, it is recommended that this bit
-                                                         be set(to disable the Master Latency timer). */
-#else
-        uint32_t mltd                    : 1;
-        uint32_t tswc                    : 1;
-        uint32_t reserved_2_2            : 1;
-        uint32_t dppmr                   : 1;
-        uint32_t pbe                     : 12;
-        uint32_t tilt                    : 4;
-        uint32_t tslte                   : 3;
-        uint32_t tmae                    : 1;
-        uint32_t twtae                   : 1;
-        uint32_t twsen                   : 1;
-        uint32_t twsei                   : 1;
-        uint32_t trtae                   : 1;
-        uint32_t trdrs                   : 1;
-        uint32_t rdsati                  : 1;
-        uint32_t trdard                  : 1;
-        uint32_t trdnpr                  : 1;
-#endif
-    } s;
-    struct cvmx_pci_cfg16_s              cn30xx;
-    struct cvmx_pci_cfg16_s              cn31xx;
-    struct cvmx_pci_cfg16_s              cn38xx;
-    struct cvmx_pci_cfg16_s              cn38xxp2;
-    struct cvmx_pci_cfg16_s              cn50xx;
-    struct cvmx_pci_cfg16_s              cn58xx;
-    struct cvmx_pci_cfg16_s              cn58xxp1;
-} cvmx_pci_cfg16_t;
-
-
-/**
- * cvmx_pci_cfg17
- *
- * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message
- * Enable Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg17_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t tscme                   : 32;      /**< Target Split Completion Message Enable
-                                                          [31:30]: 00
-                                                          [29]: Split Completion Error Indication
-                                                          [28]: 0
-                                                          [27:20]: Split Completion Message Index
-                                                          [19:0]: 0x00000
-                                                         For OCTEON, this register is intended for debug use
-                                                         only. (as such, it is recommended NOT to be written
-                                                         with anything other than ZEROES). */
-#else
-        uint32_t tscme                   : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg17_s              cn30xx;
-    struct cvmx_pci_cfg17_s              cn31xx;
-    struct cvmx_pci_cfg17_s              cn38xx;
-    struct cvmx_pci_cfg17_s              cn38xxp2;
-    struct cvmx_pci_cfg17_s              cn50xx;
-    struct cvmx_pci_cfg17_s              cn58xx;
-    struct cvmx_pci_cfg17_s              cn58xxp1;
-} cvmx_pci_cfg17_t;
-
-
-/**
- * cvmx_pci_cfg18
- *
- * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request
- * Pending Sequences)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg18_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t tdsrps                  : 32;      /**< Target Delayed/Split Request Pending Sequences
-                                                         The application uses this address to remove a
-                                                         pending split sequence from the target queue by
-                                                         clearing the appropriate bit. Example: Clearing [14]
-                                                         clears the pending sequence \#14. An application
-                                                         or configuration write to this address can clear this
-                                                         register.
-                                                         For OCTEON, this register is intended for debug use
-                                                         only and MUST NEVER be written with anything other
-                                                         than ZEROES. */
-#else
-        uint32_t tdsrps                  : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg18_s              cn30xx;
-    struct cvmx_pci_cfg18_s              cn31xx;
-    struct cvmx_pci_cfg18_s              cn38xx;
-    struct cvmx_pci_cfg18_s              cn38xxp2;
-    struct cvmx_pci_cfg18_s              cn50xx;
-    struct cvmx_pci_cfg18_s              cn58xx;
-    struct cvmx_pci_cfg18_s              cn58xxp1;
-} cvmx_pci_cfg18_t;
-
-
-/**
- * cvmx_pci_cfg19
- *
- * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg19_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t mrbcm                   : 1;       /**< Master Request (Memory Read) Byte Count/Byte
-                                                         Enable select.
-                                                           0 = Byte Enables valid. In PCI mode, a burst
-                                                               transaction cannot be performed using
-                                                               Memory Read command=4'h6.
-                                                           1 = DWORD Byte Count valid (default). In PCI
-                                                               Mode, the memory read byte enables are
-                                                               automatically generated by the core.
-                                                          NOTE:  For OCTEON, this bit must always be one
-                                                          for proper operation. */
-        uint32_t mrbci                   : 1;       /**< Master Request (I/O and CR cycles) byte count/byte
-                                                         enable select.
-                                                           0 = Byte Enables valid (default)
-                                                           1 = DWORD byte count valid
-                                                          NOTE: For OCTEON, this bit must always be zero
-                                                          for proper operation (in support of
-                                                          Type0/1 Cfg Space accesses which require byte
-                                                          enable generation directly from a read mask). */
-        uint32_t mdwe                    : 1;       /**< Master (Retry) Deferred Write Enable (allow
-                                                         read requests to pass).
-                                                          NOTE: Applicable to PCI Mode I/O and memory
-                                                          transactions only.
-                                                           0 = New read requests are NOT accepted until
-                                                               the current write cycle completes. [Reads
-                                                               cannot pass writes]
-                                                           1 = New read requests are accepted, even when
-                                                               there is a write cycle pending [Reads can
-                                                               pass writes].
-                                                          NOTE: For OCTEON, this bit must always be zero
-                                                          for proper operation. */
-        uint32_t mdre                    : 1;       /**< Master (Retry) Deferred Read Enable (Allows
-                                                         read/write requests to pass).
-                                                          NOTE: Applicable to PCI mode I/O and memory
-                                                          transactions only.
-                                                           0 = New read/write requests are NOT accepted
-                                                               until the current read cycle completes.
-                                                               [Read/write requests CANNOT pass reads]
-                                                           1 = New read/write requests are accepted, even
-                                                               when there is a read cycle pending.
-                                                               [Read/write requests CAN pass reads]
-                                                          NOTE: For OCTEON, this bit must always be zero
-                                                          for proper operation. */
-        uint32_t mdrimc                  : 1;       /**< Master I/O Deferred/Split Request Outstanding
-                                                         Maximum Count
-                                                           0 = MDRRMC[26:24]
-                                                           1 = 1 */
-        uint32_t mdrrmc                  : 3;       /**< Master Deferred Read Request Outstanding Max
-                                                         Count (PCI only).
-                                                          CR4C[26:24]  Max SAC cycles   MAX DAC cycles
-                                                           000              8                4
-                                                           001              1                0
-                                                           010              2                1
-                                                           011              3                1
-                                                           100              4                2
-                                                           101              5                2
-                                                           110              6                3
-                                                           111              7                3
-                                                          For example, if these bits are programmed to
-                                                          100, the core can support 2 DAC cycles, 4 SAC
-                                                          cycles or a combination of 1 DAC and 2 SAC cycles.
-                                                          NOTE: For the PCI-X maximum outstanding split
-                                                          transactions, refer to CRE0[22:20] */
-        uint32_t tmes                    : 8;       /**< Target/Master Error Sequence \# */
-        uint32_t teci                    : 1;       /**< Target Error Command Indication
-                                                         0 = Delayed/Split
-                                                         1 = Others */
-        uint32_t tmei                    : 1;       /**< Target/Master Error Indication
-                                                         0 = Target
-                                                         1 = Master */
-        uint32_t tmse                    : 1;       /**< Target/Master System Error. This bit is set
-                                                         whenever ATM_SERR_O is active. */
-        uint32_t tmdpes                  : 1;       /**< Target/Master Data PERR# error status. This
-                                                         bit is set whenever ATM_DATA_PERR_O is active. */
-        uint32_t tmapes                  : 1;       /**< Target/Master Address PERR# error status. This
-                                                         bit is set whenever ATM_ADDR_PERR_O is active. */
-        uint32_t reserved_9_10           : 2;
-        uint32_t tibcd                   : 1;       /**< Target Illegal I/O DWORD byte combinations detected. */
-        uint32_t tibde                   : 1;       /**< Target Illegal I/O DWORD byte detection enable */
-        uint32_t reserved_6_6            : 1;
-        uint32_t tidomc                  : 1;       /**< Target I/O Delayed/Split request outstanding
-                                                         maximum count.
-                                                          0 = TDOMC[4:0]
-                                                          1 = 1 */
-        uint32_t tdomc                   : 5;       /**< Target Delayed/Split request outstanding maximum
-                                                         count. [1..31] and 0=32.
-                                                         NOTE: If the user programs these bits beyond the
-                                                         Designed Maximum outstanding count, then the
-                                                         designed maximum table depth will be used instead.
-                                                         No additional Deferred/Split transactions will be
-                                                         accepted if this outstanding maximum count
-                                                         is reached. Furthermore, no additional
-                                                         deferred/split transactions will be accepted if
-                                                         the I/O delay/ I/O Split Request outstanding
-                                                         maximum is reached.
-                                                         NOTE: For OCTEON in PCI Mode, this field MUST BE
-                                                         programmed to 1. (OCTEON can only handle 1 delayed
-                                                         read at a time).
-                                                         For OCTEON in PCIX Mode, this field can range from
-                                                         1-4. (The designed maximum table depth is 4
-                                                         for PCIX mode splits). */
-#else
-        uint32_t tdomc                   : 5;
-        uint32_t tidomc                  : 1;
-        uint32_t reserved_6_6            : 1;
-        uint32_t tibde                   : 1;
-        uint32_t tibcd                   : 1;
-        uint32_t reserved_9_10           : 2;
-        uint32_t tmapes                  : 1;
-        uint32_t tmdpes                  : 1;
-        uint32_t tmse                    : 1;
-        uint32_t tmei                    : 1;
-        uint32_t teci                    : 1;
-        uint32_t tmes                    : 8;
-        uint32_t mdrrmc                  : 3;
-        uint32_t mdrimc                  : 1;
-        uint32_t mdre                    : 1;
-        uint32_t mdwe                    : 1;
-        uint32_t mrbci                   : 1;
-        uint32_t mrbcm                   : 1;
-#endif
-    } s;
-    struct cvmx_pci_cfg19_s              cn30xx;
-    struct cvmx_pci_cfg19_s              cn31xx;
-    struct cvmx_pci_cfg19_s              cn38xx;
-    struct cvmx_pci_cfg19_s              cn38xxp2;
-    struct cvmx_pci_cfg19_s              cn50xx;
-    struct cvmx_pci_cfg19_s              cn58xx;
-    struct cvmx_pci_cfg19_s              cn58xxp1;
-} cvmx_pci_cfg19_t;
-
-
-/**
- * cvmx_pci_cfg20
- *
- * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg20_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t mdsp                    : 32;      /**< Master Deferred/Split sequence Pending
-                                                         For OCTEON, this register is intended for debug use
-                                                         only and MUST NEVER be written with anything other
-                                                         than ZEROES. */
-#else
-        uint32_t mdsp                    : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg20_s              cn30xx;
-    struct cvmx_pci_cfg20_s              cn31xx;
-    struct cvmx_pci_cfg20_s              cn38xx;
-    struct cvmx_pci_cfg20_s              cn38xxp2;
-    struct cvmx_pci_cfg20_s              cn50xx;
-    struct cvmx_pci_cfg20_s              cn58xx;
-    struct cvmx_pci_cfg20_s              cn58xxp1;
-} cvmx_pci_cfg20_t;
-
-
-/**
- * cvmx_pci_cfg21
- *
- * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg21_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t scmre                   : 32;      /**< Master Split Completion message received with
-                                                         error message.
-                                                         For OCTEON, this register is intended for debug use
-                                                         only and MUST NEVER be written with anything other
-                                                         than ZEROES. */
-#else
-        uint32_t scmre                   : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg21_s              cn30xx;
-    struct cvmx_pci_cfg21_s              cn31xx;
-    struct cvmx_pci_cfg21_s              cn38xx;
-    struct cvmx_pci_cfg21_s              cn38xxp2;
-    struct cvmx_pci_cfg21_s              cn50xx;
-    struct cvmx_pci_cfg21_s              cn58xx;
-    struct cvmx_pci_cfg21_s              cn58xxp1;
-} cvmx_pci_cfg21_t;
-
-
-/**
- * cvmx_pci_cfg22
- *
- * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg22_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t mac                     : 7;       /**< Master Arbiter Control
-                                                         [31:26]: Used only in Fixed Priority mode
-                                                                  (when [25]=1)
-                                                         [31:30]: MSI Request
-                                                            00 = Highest Priority
-                                                            01 = Medium Priority
-                                                            10 = Lowest Priority
-                                                            11 = RESERVED
-                                                         [29:28]: Target Split Completion
-                                                            00 = Highest Priority
-                                                            01 = Medium Priority
-                                                            10 = Lowest Priority
-                                                            11 = RESERVED
-                                                         [27:26]: New Request; Deferred Read,Deferred Write
-                                                            00 = Highest Priority
-                                                            01 = Medium Priority
-                                                            10 = Lowest Priority
-                                                            11 = RESERVED
-                                                         [25]: Fixed/Round Robin Priority Selector
-                                                            0 = Round Robin
-                                                            1 = Fixed
-                                                         NOTE: When [25]=1(fixed priority), the three levels
-                                                         [31:26] MUST BE programmed to have mutually exclusive
-                                                         priority levels for proper operation. (Failure to do
-                                                         so may result in PCI hangs). */
-        uint32_t reserved_19_24          : 6;
-        uint32_t flush                   : 1;       /**< AM_DO_FLUSH_I control
-                                                         NOTE: This bit MUST BE ONE for proper OCTEON operation */
-        uint32_t mra                     : 1;       /**< Master Retry Aborted */
-        uint32_t mtta                    : 1;       /**< Master TRDY timeout aborted */
-        uint32_t mrv                     : 8;       /**< Master Retry Value [1..255] and 0=infinite */
-        uint32_t mttv                    : 8;       /**< Master TRDY timeout value [1..255] and 0=disabled
-                                                         NOTE: For OCTEON, this bit must always be zero
-                                                         for proper operation. (OCTEON does not support
-                                                         master TRDY timeout - target is expected to be
-                                                         well behaved). */
-#else
-        uint32_t mttv                    : 8;
-        uint32_t mrv                     : 8;
-        uint32_t mtta                    : 1;
-        uint32_t mra                     : 1;
-        uint32_t flush                   : 1;
-        uint32_t reserved_19_24          : 6;
-        uint32_t mac                     : 7;
-#endif
-    } s;
-    struct cvmx_pci_cfg22_s              cn30xx;
-    struct cvmx_pci_cfg22_s              cn31xx;
-    struct cvmx_pci_cfg22_s              cn38xx;
-    struct cvmx_pci_cfg22_s              cn38xxp2;
-    struct cvmx_pci_cfg22_s              cn50xx;
-    struct cvmx_pci_cfg22_s              cn58xx;
-    struct cvmx_pci_cfg22_s              cn58xxp1;
-} cvmx_pci_cfg22_t;
-
-
-/**
- * cvmx_pci_cfg56
- *
- * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg56_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_23_31          : 9;
-        uint32_t most                    : 3;       /**< Maximum outstanding Split transactions
-                                                           Encoded Value    \#Max outstanding splits
-                                                               000                   1
-                                                               001                   2
-                                                               010                   3
-                                                               011                   4
-                                                               100                   8
-                                                               101                   8(clamped)
-                                                               110                   8(clamped)
-                                                               111                   8(clamped)
-                                                         NOTE: OCTEON only supports upto a MAXIMUM of 8
-                                                         outstanding master split transactions. */
-        uint32_t mmbc                    : 2;       /**< Maximum Memory Byte Count
-                                                                 [0=512B,1=1024B,2=2048B,3=4096B]
-                                                         NOTE: OCTEON does not support this field and has
-                                                         no effect on limiting the maximum memory byte count. */
-        uint32_t roe                     : 1;       /**< Relaxed Ordering Enable */
-        uint32_t dpere                   : 1;       /**< Data Parity Error Recovery Enable */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
-        uint32_t pxcid                   : 8;       /**< PCI-X Capability ID */
-#else
-        uint32_t pxcid                   : 8;
-        uint32_t ncp                     : 8;
-        uint32_t dpere                   : 1;
-        uint32_t roe                     : 1;
-        uint32_t mmbc                    : 2;
-        uint32_t most                    : 3;
-        uint32_t reserved_23_31          : 9;
-#endif
-    } s;
-    struct cvmx_pci_cfg56_s              cn30xx;
-    struct cvmx_pci_cfg56_s              cn31xx;
-    struct cvmx_pci_cfg56_s              cn38xx;
-    struct cvmx_pci_cfg56_s              cn38xxp2;
-    struct cvmx_pci_cfg56_s              cn50xx;
-    struct cvmx_pci_cfg56_s              cn58xx;
-    struct cvmx_pci_cfg56_s              cn58xxp1;
-} cvmx_pci_cfg56_t;
-
-
-/**
- * cvmx_pci_cfg57
- *
- * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg57_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t scemr                   : 1;       /**< Split Completion Error Message Received */
-        uint32_t mcrsd                   : 3;       /**< Maximum Cumulative Read Size designed */
-        uint32_t mostd                   : 3;       /**< Maximum Outstanding Split transaction designed */
-        uint32_t mmrbcd                  : 2;       /**< Maximum Memory Read byte count designed */
-        uint32_t dc                      : 1;       /**< Device Complexity
-                                                         0 = Simple Device
-                                                         1 = Bridge Device */
-        uint32_t usc                     : 1;       /**< Unexpected Split Completion */
-        uint32_t scd                     : 1;       /**< Split Completion Discarded */
-        uint32_t m133                    : 1;       /**< 133MHz Capable */
-        uint32_t w64                     : 1;       /**< Indicates a 32b(=0) or 64b(=1) device */
-        uint32_t bn                      : 8;       /**< Bus Number. Updated on all configuration write
-                                                         (0x11=PCI)             cycles. Its value is dependent upon the PCI/X
-                                                         (0xFF=PCIX)            mode. */
-        uint32_t dn                      : 5;       /**< Device Number. Updated on all configuration
-                                                         write cycles. */
-        uint32_t fn                      : 3;       /**< Function Number */
-#else
-        uint32_t fn                      : 3;
-        uint32_t dn                      : 5;
-        uint32_t bn                      : 8;
-        uint32_t w64                     : 1;
-        uint32_t m133                    : 1;
-        uint32_t scd                     : 1;
-        uint32_t usc                     : 1;
-        uint32_t dc                      : 1;
-        uint32_t mmrbcd                  : 2;
-        uint32_t mostd                   : 3;
-        uint32_t mcrsd                   : 3;
-        uint32_t scemr                   : 1;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pci_cfg57_s              cn30xx;
-    struct cvmx_pci_cfg57_s              cn31xx;
-    struct cvmx_pci_cfg57_s              cn38xx;
-    struct cvmx_pci_cfg57_s              cn38xxp2;
-    struct cvmx_pci_cfg57_s              cn50xx;
-    struct cvmx_pci_cfg57_s              cn58xx;
-    struct cvmx_pci_cfg57_s              cn58xxp1;
-} cvmx_pci_cfg57_t;
-
-
-/**
- * cvmx_pci_cfg58
- *
- * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg58_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmes                    : 5;       /**< PME Support (D0 to D3cold) */
-        uint32_t d2s                     : 1;       /**< D2_Support */
-        uint32_t d1s                     : 1;       /**< D1_Support */
-        uint32_t auxc                    : 3;       /**< AUX_Current (0..375mA) */
-        uint32_t dsi                     : 1;       /**< Device Specific Initialization */
-        uint32_t reserved_20_20          : 1;
-        uint32_t pmec                    : 1;       /**< PME Clock */
-        uint32_t pcimiv                  : 3;       /**< Indicates the version of the PCI
-                                                         Management
-                                                          Interface Specification with which the core
-                                                          complies.
-                                                            010b = Complies with PCI Management Interface
-                                                            Specification Revision 1.1 */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
-        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
-#else
-        uint32_t pmcid                   : 8;
-        uint32_t ncp                     : 8;
-        uint32_t pcimiv                  : 3;
-        uint32_t pmec                    : 1;
-        uint32_t reserved_20_20          : 1;
-        uint32_t dsi                     : 1;
-        uint32_t auxc                    : 3;
-        uint32_t d1s                     : 1;
-        uint32_t d2s                     : 1;
-        uint32_t pmes                    : 5;
-#endif
-    } s;
-    struct cvmx_pci_cfg58_s              cn30xx;
-    struct cvmx_pci_cfg58_s              cn31xx;
-    struct cvmx_pci_cfg58_s              cn38xx;
-    struct cvmx_pci_cfg58_s              cn38xxp2;
-    struct cvmx_pci_cfg58_s              cn50xx;
-    struct cvmx_pci_cfg58_s              cn58xx;
-    struct cvmx_pci_cfg58_s              cn58xxp1;
-} cvmx_pci_cfg58_t;
-
-
-/**
- * cvmx_pci_cfg59
- *
- * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s))
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg59_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmdia                   : 8;       /**< Power Management data input from application
-                                                         (PME_DATA) */
-        uint32_t bpccen                  : 1;       /**< BPCC_En (bus power/clock control) enable */
-        uint32_t bd3h                    : 1;       /**< B2_B3\#, B2/B3 Support for D3hot */
-        uint32_t reserved_16_21          : 6;
-        uint32_t pmess                   : 1;       /**< PME_Status sticky bit */
-        uint32_t pmedsia                 : 2;       /**< PME_Data_Scale input from application
-                                                         Device                  (PME_DATA_SCALE[1:0])
-                                                         Specific */
-        uint32_t pmds                    : 4;       /**< Power Management Data_select */
-        uint32_t pmeens                  : 1;       /**< PME_En sticky bit */
-        uint32_t reserved_2_7            : 6;
-        uint32_t ps                      : 2;       /**< Power State (D0 to D3)
-                                                         The N2 DOES NOT support D1/D2 Power Management
-                                                         states, therefore writing to this register has
-                                                         no effect (please refer to the PCI Power
-                                                         Management
-                                                         Specification v1.1 for further details about
-                                                         it?s R/W nature. This is not a conventional
-                                                         R/W style register. */
-#else
-        uint32_t ps                      : 2;
-        uint32_t reserved_2_7            : 6;
-        uint32_t pmeens                  : 1;
-        uint32_t pmds                    : 4;
-        uint32_t pmedsia                 : 2;
-        uint32_t pmess                   : 1;
-        uint32_t reserved_16_21          : 6;
-        uint32_t bd3h                    : 1;
-        uint32_t bpccen                  : 1;
-        uint32_t pmdia                   : 8;
-#endif
-    } s;
-    struct cvmx_pci_cfg59_s              cn30xx;
-    struct cvmx_pci_cfg59_s              cn31xx;
-    struct cvmx_pci_cfg59_s              cn38xx;
-    struct cvmx_pci_cfg59_s              cn38xxp2;
-    struct cvmx_pci_cfg59_s              cn50xx;
-    struct cvmx_pci_cfg59_s              cn58xx;
-    struct cvmx_pci_cfg59_s              cn58xxp1;
-} cvmx_pci_cfg59_t;
-
-
-/**
- * cvmx_pci_cfg60
- *
- * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg60_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t m64                     : 1;       /**< 32/64 b message */
-        uint32_t mme                     : 3;       /**< Multiple Message Enable(1,2,4,8,16,32) */
-        uint32_t mmc                     : 3;       /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */
-        uint32_t msien                   : 1;       /**< MSI Enable */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
-        uint32_t msicid                  : 8;       /**< MSI Capability ID */
-#else
-        uint32_t msicid                  : 8;
-        uint32_t ncp                     : 8;
-        uint32_t msien                   : 1;
-        uint32_t mmc                     : 3;
-        uint32_t mme                     : 3;
-        uint32_t m64                     : 1;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pci_cfg60_s              cn30xx;
-    struct cvmx_pci_cfg60_s              cn31xx;
-    struct cvmx_pci_cfg60_s              cn38xx;
-    struct cvmx_pci_cfg60_s              cn38xxp2;
-    struct cvmx_pci_cfg60_s              cn50xx;
-    struct cvmx_pci_cfg60_s              cn58xx;
-    struct cvmx_pci_cfg60_s              cn58xxp1;
-} cvmx_pci_cfg60_t;
-
-
-/**
- * cvmx_pci_cfg61
- *
- * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg61_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t msi31t2                 : 30;      /**< App Specific    MSI Address [31:2] */
-        uint32_t reserved_0_1            : 2;
-#else
-        uint32_t reserved_0_1            : 2;
-        uint32_t msi31t2                 : 30;
-#endif
-    } s;
-    struct cvmx_pci_cfg61_s              cn30xx;
-    struct cvmx_pci_cfg61_s              cn31xx;
-    struct cvmx_pci_cfg61_s              cn38xx;
-    struct cvmx_pci_cfg61_s              cn38xxp2;
-    struct cvmx_pci_cfg61_s              cn50xx;
-    struct cvmx_pci_cfg61_s              cn58xx;
-    struct cvmx_pci_cfg61_s              cn58xxp1;
-} cvmx_pci_cfg61_t;
-
-
-/**
- * cvmx_pci_cfg62
- *
- * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg62_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t msi                     : 32;      /**< MSI Address [63:32] */
-#else
-        uint32_t msi                     : 32;
-#endif
-    } s;
-    struct cvmx_pci_cfg62_s              cn30xx;
-    struct cvmx_pci_cfg62_s              cn31xx;
-    struct cvmx_pci_cfg62_s              cn38xx;
-    struct cvmx_pci_cfg62_s              cn38xxp2;
-    struct cvmx_pci_cfg62_s              cn50xx;
-    struct cvmx_pci_cfg62_s              cn58xx;
-    struct cvmx_pci_cfg62_s              cn58xxp1;
-} cvmx_pci_cfg62_t;
-
-
-/**
- * cvmx_pci_cfg63
- *
- * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_cfg63_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t msimd                   : 16;      /**< MSI Message Data */
-#else
-        uint32_t msimd                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_pci_cfg63_s              cn30xx;
-    struct cvmx_pci_cfg63_s              cn31xx;
-    struct cvmx_pci_cfg63_s              cn38xx;
-    struct cvmx_pci_cfg63_s              cn38xxp2;
-    struct cvmx_pci_cfg63_s              cn50xx;
-    struct cvmx_pci_cfg63_s              cn58xx;
-    struct cvmx_pci_cfg63_s              cn58xxp1;
-} cvmx_pci_cfg63_t;
-
-
-/**
- * cvmx_pci_cnt_reg
- *
- * PCI_CNT_REG = PCI Clock Count Register
- * 
- * This register is provided to software as a means to determine PCI Bus Type/Speed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_cnt_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t hm_pcix                 : 1;       /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX)
-                                                         This field represents what OCTEON(in Host mode)
-                                                         sampled as the 'intended' PCI Bus Type based on
-                                                         the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed
-                                                         encoding table). */
-        uint64_t hm_speed                : 2;       /**< PCI Host Mode Sampled Bus Speed
-                                                          This field represents what OCTEON(in Host mode)
-                                                          sampled as the 'intended' PCI Bus Speed based on
-                                                          the PCI100, PCI_M66EN and PCI_PCIXCAP pins.
-                                                          NOTE: This DOES NOT reflect what the actual PCI
-                                                          Bus Type/Speed values are. They only indicate what
-                                                          OCTEON sampled as the 'intended' values.
-                                                          PCI Host Mode Sampled Bus Type/Speed Table:
-                                                            M66EN | PCIXCAP | PCI100  |  HM_PCIX | HM_SPEED[1:0]
-                                                         ---------+---------+---------+----------+-------------
-                                                              0   |    0    |    0    | 0=PCI    |  00=33 MHz
-                                                              0   |    0    |    1    | 0=PCI    |  00=33 MHz
-                                                              0   |    Z    |    0    | 0=PCI    |  01=66 MHz
-                                                              0   |    Z    |    1    | 0=PCI    |  01=66 MHz
-                                                              1   |    0    |    0    | 0=PCI    |  01=66 MHz
-                                                              1   |    0    |    1    | 0=PCI    |  01=66 MHz
-                                                              1   |    Z    |    0    | 0=PCI    |  01=66 MHz
-                                                              1   |    Z    |    1    | 0=PCI    |  01=66 MHz
-                                                              0   |    1    |    1    | 1=PCIX   |  10=100 MHz
-                                                              1   |    1    |    1    | 1=PCIX   |  10=100 MHz
-                                                              0   |    1    |    0    | 1=PCIX   |  11=133 MHz
-                                                              1   |    1    |    0    | 1=PCIX   |  11=133 MHz
-                                                          NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification
-                                                          for more details on board level hookup to achieve these
-                                                          values.
-                                                          NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR]
-                                                          to override the 'sampled' PCI Bus Type/Speed.
-                                                          NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine
-                                                          the exact PCI(X) Bus speed.
-                                                          Example: PCI_REF_CLKIN=133MHz
-                                                             PCI_HOST_MODE=1
-                                                             PCI_M66EN=0
-                                                             PCI_PCIXCAP=1
-                                                             PCI_PCI100=1
-                                                          For this example, OCTEON will generate
-                                                          PCI_CLK_OUT=100MHz and drive the proper PCI
-                                                          Initialization sequence (DEVSEL#=Deasserted,
-                                                          STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N
-                                                          deassertion.
-                                                          NOTE: The HM_SPEED field is only valid after
-                                                          PLL_REF_CLK is active and PLL_DCOK is asserted.
-                                                          (see HRM description for power-on/reset sequence).
-                                                          NOTE: PCI_REF_CLKIN input must be 133MHz (and is used
-                                                          to generate the PCI_CLK_OUT pin in Host Mode).
-                                                          *** NOTE: O9N PASS1 Addition */
-        uint64_t ap_pcix                 : 1;       /**< PCI(X) Bus Type (0:PCI/1:PCIX)
-                                                         At PCI_RST_N de-assertion, the PCI Initialization
-                                                         pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
-                                                         captured to provide information to software regarding
-                                                         the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */
-        uint64_t ap_speed                : 2;       /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133)
-                                                                                    At PCI_RST_N de-assertion, the PCI Initialization
-                                                                                    pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
-                                                                                    captured to provide information to software regarding
-                                                                                    the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range.
-                                                                                    PCI-X Initialization Pattern(see PCIX Spec):
-                                                           PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode    MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz)
-                                                         -------------+----------+----------+-------+---------+----------+----------+------------------
-                                                            Deasserted Deasserted Deasserted PCI 33    --         30          0         33
-                                                                                             PCI 66    30         15         33         66
-                                                            Deasserted Deasserted Asserted   PCI-X     20         15         50         66
-                                                            Deasserted Asserted   Deasserted PCI-X     15         10         66        100
-                                                            Deasserted Asserted   Asserted   PCI-X     10         7.5       100        133
-                                                            Asserted   Deasserted Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
-                                                            Asserted   Deasserted Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
-                                                            Asserted   Asserted   Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
-                                                            Asserted   Asserted   Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
-                                                                                    NOTE: The PCI Bus speed 'assumed' from the initialization
-                                                                                    pattern is really intended for an operational range.
-                                                                                    For example: If PINIT=100, this indicates PCI-X in the
-                                                                                    100-133MHz range. The PCI_CNT field can be used to further
-                                                                                    determine a more exacting PCI Bus frequency value if
-                                                                                    required.
-                                                                                    *** NOTE: O9N PASS1 Addition */
-        uint64_t pcicnt                  : 32;      /**< Free Running PCI Clock counter.
-                                                         At PCI Reset, the PCICNT=0, and is auto-incremented
-                                                         on every PCI clock and will auto-wrap back to zero
-                                                         when saturated.
-                                                         NOTE: Writes override the auto-increment to allow
-                                                         software to preload any initial value.
-                                                         The PCICNT field is provided to software as a means
-                                                         to determine the PCI Bus Speed.
-                                                         Assuming software has knowledge of the core frequency
-                                                         (eclk), this register can be written with a value X,
-                                                         wait 'n' core clocks(eclk) and then read later(Y) to
-                                                         determine \#PCI clocks(Y-X) have elapsed within 'n' core
-                                                         clocks to determine the PCI input Clock frequency.
-                                                         *** NOTE: O9N PASS1 Addition */
-#else
-        uint64_t pcicnt                  : 32;
-        uint64_t ap_speed                : 2;
-        uint64_t ap_pcix                 : 1;
-        uint64_t hm_speed                : 2;
-        uint64_t hm_pcix                 : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_pci_cnt_reg_s            cn50xx;
-    struct cvmx_pci_cnt_reg_s            cn58xx;
-    struct cvmx_pci_cnt_reg_s            cn58xxp1;
-} cvmx_pci_cnt_reg_t;
-
-
-/**
- * cvmx_pci_ctl_status_2
- *
- * PCI_CTL_STATUS_2 = PCI Control Status 2 Register
- * 
- * Control status register accessable from both PCI and NCB.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_ctl_status_2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_29_31          : 3;
-        uint32_t bb1_hole                : 3;       /**< Big BAR 1 Hole
-                                                         NOT IN PASS 1 NOR PASS 2
-                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
-                                                         an encoded size of the upper BAR1 region which
-                                                         OCTEON will mask out (ie: not respond to).
-                                                         (see definition of BB1_HOLE and BB1_SIZ encodings
-                                                         in the PCI_CTL_STATUS_2[BB1] definition below). */
-        uint32_t bb1_siz                 : 1;       /**< Big BAR 1 Size
-                                                         NOT IN PASS 1 NOR PASS 2
-                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
-                                                         the programmable SIZE of BAR 1.
-                                                           - 0: 1GB / 1: 2GB */
-        uint32_t bb_ca                   : 1;       /**< Set to '1' for Big Bar Mode to do STT/LDT L2C
-                                                         operations.
-                                                         NOT IN PASS 1 NOR PASS 2 */
-        uint32_t bb_es                   : 2;       /**< Big Bar Node Endian Swap Mode
-                                                           - 0: No Swizzle
-                                                           - 1: Byte Swizzle (per-QW)
-                                                           - 2: Byte Swizzle (per-LW)
-                                                           - 3: LongWord Swizzle
-                                                         NOT IN PASS 1 NOR PASS 2 */
-        uint32_t bb1                     : 1;       /**< Big Bar 1 Enable
-                                                         NOT IN PASS 1 NOR PASS 2
-                                                         When PCI_CTL_STATUS_2[BB1] is set, the following differences
-                                                         occur:
-                                                         - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather
-                                                           than the default 128MB.
-                                                         - The following table indicates the effective size of
-                                                           BAR1 when BB1 is set:
-                                                             BB1_SIZ   BB1_HOLE  Effective size    Comment
-                                                           +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-                                                                0          0         1024 MB      Normal 1GB BAR
-                                                                0          1         1008 MB      1 GB, 16 MB hole
-                                                                0          2          992 MB      1 GB, 32 MB hole
-                                                                0          3          960 MB      1 GB, 64 MB hole
-                                                                0          4          896 MB      1 GB,128 MB hole
-                                                                0          5          768 MB      1 GB,256 MB hole
-                                                                0          6          512 MB      1 GB,512 MB hole
-                                                                0          7         Illegal
-                                                                1          0         2048 MB      Normal 2GB BAR
-                                                                1          1         2032 MB      2 GB, 16 MB hole
-                                                                1          2         2016 MB      2 GB, 32 MB hole
-                                                                1          3         1984 MB      2 GB, 64 MB hole
-                                                                1          4         1920 MB      2 GB,128 MB hole
-                                                                1          5         1792 MB      2 GB,256 MB hole
-                                                                1          6         1536 MB      2 GB,512 MB hole
-                                                                1          7         Illegal
-                                                         - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero
-                                                           and are ignored on write. BAR1 is an entirely ordinary
-                                                           1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
-                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
-                                                           as if the BAR were 1GB, but, OCTEON does not respond
-                                                           to addresses in the programmed holes.
-                                                         - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero
-                                                           and are ignored on write. BAR1 is an entirely ordinary
-                                                           2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
-                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
-                                                           as if the BAR were 2GB, but, OCTEON does not respond
-                                                           to addresses in the programmed holes.
-                                                         - Note that the BB1_HOLE value has no effect on the
-                                                           PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether
-                                                           OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE]
-                                                           behavior, however.
-                                                         - The first 128MB, i.e. addresses on the PCI bus in the range
-                                                             BAR1+0          .. BAR1+0x07FFFFFF
-                                                           access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's
-                                                           as before
-                                                         - The remaining address space, i.e. addresses
-                                                           on the PCI bus in the range
-                                                              BAR1+0x08000000 .. BAR1+size-1,
-                                                           where size is the size of BAR1 as selected by the above
-                                                           table (based on the BB1_SIZ and BB1_HOLE values), are mapped to
-                                                           OCTEON physical DRAM addresses as follows:
-                                                                   PCI Address Range         OCTEON Physical Address Range
-                                                           ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-                                                            BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size
-                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
-                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
-                                                           for these references.
-                                                           The consequences of any burst that crosses the end of the PCI
-                                                           Address Range for BAR1 are unpredicable.
-                                                         - The consequences of any burst access that crosses the boundary
-                                                           between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X
-                                                           mode. OCTEON may disconnect PCI references at this boundary. */
-        uint32_t bb0                     : 1;       /**< Big Bar 0 Enable
-                                                         NOT IN PASS 1 NOR PASS 2
-                                                         When PCI_CTL_STATUS_2[BB0] is set, the following
-                                                         differences occur:
-                                                         - OCTEON's BAR0 becomes 2GB rather than the default 4KB.
-                                                           PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write.
-                                                         - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON
-                                                           single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0
-                                                           writes, and splits (burstably) PCI-X BAR0 reads.)
-                                                         - The first 4KB, i.e. addresses on the PCI bus in the range
-                                                               BAR0+0      .. BAR0+0xFFF
-                                                           access OCTEON's PCI-type CSR's as when BB0 is clear.
-                                                         - The remaining address space, i.e. addresses on the PCI bus
-                                                           in the range
-                                                               BAR0+0x1000 .. BAR0+0x7FFFFFFF
-                                                           are mapped to OCTEON physical DRAM addresses as follows:
-                                                              PCI Address Range                  OCTEON Physical Address Range
-                                                           ------------------------------------+------------------------------
-                                                            BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF
-                                                            BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF
-                                                            BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF
-                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
-                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
-                                                           for these references.
-                                                           The consequences of any burst that crosses the end of the PCI
-                                                           Address Range for BAR0 are unpredicable.
-                                                         - The consequences of any burst access that crosses the boundary
-                                                           between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X
-                                                           mode. OCTEON may disconnect PCI references at this boundary.
-                                                         - The results of any burst read that crosses the boundary
-                                                           between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable.
-                                                           The consequences of any burst write that crosses this same
-                                                           boundary are unpredictable.
-                                                         - The results of any burst read that crosses the boundary
-                                                           between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable.
-                                                           The consequences of any burst write that crosses this same
-                                                           boundary are unpredictable. */
-        uint32_t erst_n                  : 1;       /**< Reset active Low. PASS-2 */
-        uint32_t bar2pres                : 1;       /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
-                                                         is NOT blown the value of this field is '0' after
-                                                         reset and BAR2 is NOT present. When the fuse IS
-                                                         blown the value of this field is '1' after reset
-                                                         and BAR2 is present. Note that SW can change this
-                                                         field after reset. This is a PASS-2 field. */
-        uint32_t scmtyp                  : 1;       /**< Split Completion Message CMD Type (0=RD/1=WR)
-                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
-        uint32_t scm                     : 1;       /**< Split Completion Message Detected (Read or Write) */
-        uint32_t en_wfilt                : 1;       /**< When '1' the window-access filter is enabled.
-                                                         Unfilter writes are:
-                                                         MIO, SubId0
-                                                         MIO, SubId7
-                                                         NPI, SubId0
-                                                         NPI, SubId7
-                                                         POW, SubId7
-                                                         DFA, SubId7
-                                                         IPD, SubId7
-                                                         Unfiltered Reads are:
-                                                         MIO, SubId0
-                                                         MIO, SubId7
-                                                         NPI, SubId0
-                                                         NPI, SubId7
-                                                         POW, SubId1
-                                                         POW, SubId2
-                                                         POW, SubId3
-                                                         POW, SubId7
-                                                         DFA, SubId7
-                                                         IPD, SubId7 */
-        uint32_t reserved_14_14          : 1;
-        uint32_t ap_pcix                 : 1;       /**< PCX Core Mode status (0=PCI Bus/1=PCIX)
-                                                         If one or more of PCI_DEVSEL_N, PCI_STOP_N, and
-                                                         PCI_TRDY_N are asserted at the rising edge of
-                                                         PCI_RST_N, the device enters PCI-X mode.
-                                                         Otherwise, the device enters conventional PCI
-                                                         mode at the rising edge of RST#. */
-        uint32_t ap_64ad                 : 1;       /**< PCX Core Bus status (0=32b Bus/1=64b Bus)
-                                                         When PCI_RST_N pin is de-asserted, the state
-                                                         of PCI_REQ64_N(driven by central agent) determines
-                                                         the width of the PCI/X bus. */
-        uint32_t b12_bist                : 1;       /**< Bist Status For Memeory In B12 */
-        uint32_t pmo_amod                : 1;       /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
-        uint32_t pmo_fpc                 : 3;       /**< PMO-ARB Fixed Priority Counter
-                                                         When PMO_AMOD=0 (FP mode), this field represents
-                                                         the \# of CMD1 requests that are issued (at higher
-                                                         priority) before a single lower priority CMD0
-                                                         is allowed to issue (to ensure foward progress).
-                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
-                                                           - ...
-                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
-        uint32_t tsr_hwm                 : 3;       /**< Target Split-Read ADB(allowable disconnect boundary)
-                                                         High Water Mark.
-                                                         Specifies the number of ADBs(128 Byte aligned chunks)
-                                                         that are accumulated(pending) BEFORE the Target Split
-                                                         completion is attempted on the PCI bus.
-                                                            - 0: RESERVED/ILLEGAL
-                                                            - 1: 2 Pending ADBs (129B-256B)
-                                                            - 2: 3 Pending ADBs (257B-384B)
-                                                            - 3: 4 Pending ADBs (385B-512B)
-                                                            - 4: 5 Pending ADBs (513B-640B)
-                                                            - 5: 6 Pending ADBs (641B-768B)
-                                                            - 6: 7 Pending ADBs (769B-896B)
-                                                            - 7: 8 Pending ADBs (897B-1024B)
-                                                         Example: Suppose a 1KB target memory request with
-                                                         starting byte offset address[6:0]=0x7F is split by
-                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
-                                                         The OCTEON will start the target split completion
-                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
-                                                         of data have been received from memory (even though
-                                                         the remaining 895B has not yet been received). The
-                                                         OCTEON will continue the split completion until it
-                                                         has consumed all of the pended split data. If the
-                                                         full transaction length(1KB) of data was NOT entirely
-                                                         transferred, then OCTEON will terminate the split
-                                                         completion and again wait for another 2 ADB-aligned data
-                                                         chunks(256B) of pended split data to be received from
-                                                         memory before starting another split completion request.
-                                                         This allows Octeon (as split completer), to send back
-                                                         multiple split completions for a given large split
-                                                         transaction without having to wait for the entire
-                                                         transaction length to be received from memory.
-                                                         NOTE: For split transaction sizes 'smaller' than the
-                                                         specified TSR_HWM value, the split completion
-                                                         is started when the last datum has been received from
-                                                         memory.
-                                                         NOTE: It is IMPERATIVE that this field NEVER BE
-                                                         written to a ZERO value. A value of zero is
-                                                         reserved/illegal and can result in PCIX bus hangs). */
-        uint32_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
-                                                         clear '0' BAR2 access will be target-aborted. */
-        uint32_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
-                                                         determine the endian swap mode. */
-        uint32_t bar2_cax                : 1;       /**< Value will be XORed with pci-address[38] to
-                                                         determine the L2 cache attribute.
-                                                         When XOR result is 1, not cached in L2 */
-#else
-        uint32_t bar2_cax                : 1;
-        uint32_t bar2_esx                : 2;
-        uint32_t bar2_enb                : 1;
-        uint32_t tsr_hwm                 : 3;
-        uint32_t pmo_fpc                 : 3;
-        uint32_t pmo_amod                : 1;
-        uint32_t b12_bist                : 1;
-        uint32_t ap_64ad                 : 1;
-        uint32_t ap_pcix                 : 1;
-        uint32_t reserved_14_14          : 1;
-        uint32_t en_wfilt                : 1;
-        uint32_t scm                     : 1;
-        uint32_t scmtyp                  : 1;
-        uint32_t bar2pres                : 1;
-        uint32_t erst_n                  : 1;
-        uint32_t bb0                     : 1;
-        uint32_t bb1                     : 1;
-        uint32_t bb_es                   : 2;
-        uint32_t bb_ca                   : 1;
-        uint32_t bb1_siz                 : 1;
-        uint32_t bb1_hole                : 3;
-        uint32_t reserved_29_31          : 3;
-#endif
-    } s;
-    struct cvmx_pci_ctl_status_2_s       cn30xx;
-    struct cvmx_pci_ctl_status_2_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t erst_n                  : 1;       /**< Reset active Low. */
-        uint32_t bar2pres                : 1;       /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
-                                                         is NOT blown the value of this field is '0' after
-                                                         reset and BAR2 is NOT present. When the fuse IS
-                                                         blown the value of this field is '1' after reset
-                                                         and BAR2 is present. Note that SW can change this
-                                                         field after reset. */
-        uint32_t scmtyp                  : 1;       /**< Split Completion Message CMD Type (0=RD/1=WR)
-                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
-        uint32_t scm                     : 1;       /**< Split Completion Message Detected (Read or Write) */
-        uint32_t en_wfilt                : 1;       /**< When '1' the window-access filter is enabled.
-                                                         Unfilter writes are:
-                                                         MIO,  SubId0
-                                                         MIO,  SubId7
-                                                         NPI,  SubId0
-                                                         NPI,  SubId7
-                                                         POW,  SubId7
-                                                         DFA,  SubId7
-                                                         IPD,  SubId7
-                                                         USBN, SubId7
-                                                         Unfiltered Reads are:
-                                                         MIO,  SubId0
-                                                         MIO,  SubId7
-                                                         NPI,  SubId0
-                                                         NPI,  SubId7
-                                                         POW,  SubId1
-                                                         POW,  SubId2
-                                                         POW,  SubId3
-                                                         POW,  SubId7
-                                                         DFA,  SubId7
-                                                         IPD,  SubId7
-                                                         USBN, SubId7 */
-        uint32_t reserved_14_14          : 1;
-        uint32_t ap_pcix                 : 1;       /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */
-        uint32_t ap_64ad                 : 1;       /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */
-        uint32_t b12_bist                : 1;       /**< Bist Status For Memeory In B12 */
-        uint32_t pmo_amod                : 1;       /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
-        uint32_t pmo_fpc                 : 3;       /**< PMO-ARB Fixed Priority Counter
-                                                         When PMO_AMOD=0 (FP mode), this field represents
-                                                         the \# of CMD1 requests that are issued (at higher
-                                                         priority) before a single lower priority CMD0
-                                                         is allowed to issue (to ensure foward progress).
-                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
-                                                           - ...
-                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
-        uint32_t tsr_hwm                 : 3;       /**< Target Split-Read ADB(allowable disconnect boundary)
-                                                         High Water Mark.
-                                                         Specifies the number of ADBs(128 Byte aligned chunks)
-                                                         that are accumulated(pending) BEFORE the Target Split
-                                                         completion is attempted on the PCI bus.
-                                                            - 0: RESERVED/ILLEGAL
-                                                            - 1: 2 Pending ADBs (129B-256B)
-                                                            - 2: 3 Pending ADBs (257B-384B)
-                                                            - 3: 4 Pending ADBs (385B-512B)
-                                                            - 4: 5 Pending ADBs (513B-640B)
-                                                            - 5: 6 Pending ADBs (641B-768B)
-                                                            - 6: 7 Pending ADBs (769B-896B)
-                                                            - 7: 8 Pending ADBs (897B-1024B)
-                                                         Example: Suppose a 1KB target memory request with
-                                                         starting byte offset address[6:0]=0x7F is split by
-                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
-                                                         The OCTEON will start the target split completion
-                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
-                                                         of data have been received from memory (even though
-                                                         the remaining 895B has not yet been received). The
-                                                         OCTEON will continue the split completion until it
-                                                         has consumed all of the pended split data. If the
-                                                         full transaction length(1KB) of data was NOT entirely
-                                                         transferred, then OCTEON will terminate the split
-                                                         completion and again wait for another 2 ADB-aligned data
-                                                         chunks(256B) of pended split data to be received from
-                                                         memory before starting another split completion request.
-                                                         This allows Octeon (as split completer), to send back
-                                                         multiple split completions for a given large split
-                                                         transaction without having to wait for the entire
-                                                         transaction length to be received from memory.
-                                                         NOTE: For split transaction sizes 'smaller' than the
-                                                         specified TSR_HWM value, the split completion
-                                                         is started when the last datum has been received from
-                                                         memory.
-                                                         NOTE: It is IMPERATIVE that this field NEVER BE
-                                                         written to a ZERO value. A value of zero is
-                                                         reserved/illegal and can result in PCIX bus hangs). */
-        uint32_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
-                                                         clear '0' BAR2 access will be target-aborted. */
-        uint32_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
-                                                         determine the endian swap mode. */
-        uint32_t bar2_cax                : 1;       /**< Value will be XORed with pci-address[38] to
-                                                         determine the L2 cache attribute.
-                                                         When XOR result is 1, not allocated in L2 cache */
-#else
-        uint32_t bar2_cax                : 1;
-        uint32_t bar2_esx                : 2;
-        uint32_t bar2_enb                : 1;
-        uint32_t tsr_hwm                 : 3;
-        uint32_t pmo_fpc                 : 3;
-        uint32_t pmo_amod                : 1;
-        uint32_t b12_bist                : 1;
-        uint32_t ap_64ad                 : 1;
-        uint32_t ap_pcix                 : 1;
-        uint32_t reserved_14_14          : 1;
-        uint32_t en_wfilt                : 1;
-        uint32_t scm                     : 1;
-        uint32_t scmtyp                  : 1;
-        uint32_t bar2pres                : 1;
-        uint32_t erst_n                  : 1;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } cn31xx;
-    struct cvmx_pci_ctl_status_2_s       cn38xx;
-    struct cvmx_pci_ctl_status_2_cn31xx  cn38xxp2;
-    struct cvmx_pci_ctl_status_2_s       cn50xx;
-    struct cvmx_pci_ctl_status_2_s       cn58xx;
-    struct cvmx_pci_ctl_status_2_s       cn58xxp1;
-} cvmx_pci_ctl_status_2_t;
-
-
-/**
- * cvmx_pci_dbell#
- *
- * PCI_DBELL0 = PCI Doorbell-0
- * 
- * The value to write to the doorbell 0 register. The value in this register is acted upon when the
- * least-significant-byte of this register is written.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_dbellx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t inc_val                 : 16;      /**< Software writes this register with the
-                                                         number of new Instructions to be processed
-                                                         on the Instruction Queue. When read this
-                                                         register contains the last write value. */
-#else
-        uint32_t inc_val                 : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_pci_dbellx_s             cn30xx;
-    struct cvmx_pci_dbellx_s             cn31xx;
-    struct cvmx_pci_dbellx_s             cn38xx;
-    struct cvmx_pci_dbellx_s             cn38xxp2;
-    struct cvmx_pci_dbellx_s             cn50xx;
-    struct cvmx_pci_dbellx_s             cn58xx;
-    struct cvmx_pci_dbellx_s             cn58xxp1;
-} cvmx_pci_dbellx_t;
-
-
-/**
- * cvmx_pci_dma_cnt#
- *
- * PCI_DMA_CNT0 = PCI DMA Count0
- * 
- * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the
- * least-significant-byte of this register is written.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_dma_cntx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dma_cnt                 : 32;      /**< Update with the number of DMAs completed or the
-                                                         number of bytes sent for DMA's associated with
-                                                         this counter. When this register is written the
-                                                         value written to [15:0] will be subtracted from
-                                                         the value in this register. */
-#else
-        uint32_t dma_cnt                 : 32;
-#endif
-    } s;
-    struct cvmx_pci_dma_cntx_s           cn30xx;
-    struct cvmx_pci_dma_cntx_s           cn31xx;
-    struct cvmx_pci_dma_cntx_s           cn38xx;
-    struct cvmx_pci_dma_cntx_s           cn38xxp2;
-    struct cvmx_pci_dma_cntx_s           cn50xx;
-    struct cvmx_pci_dma_cntx_s           cn58xx;
-    struct cvmx_pci_dma_cntx_s           cn58xxp1;
-} cvmx_pci_dma_cntx_t;
-
-
-/**
- * cvmx_pci_dma_int_lev#
- *
- * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0
- * 
- * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_dma_int_levx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pkt_cnt                 : 32;      /**< When PCI_DMA_CNT0 exceeds the value in this
-                                                         DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */
-#else
-        uint32_t pkt_cnt                 : 32;
-#endif
-    } s;
-    struct cvmx_pci_dma_int_levx_s       cn30xx;
-    struct cvmx_pci_dma_int_levx_s       cn31xx;
-    struct cvmx_pci_dma_int_levx_s       cn38xx;
-    struct cvmx_pci_dma_int_levx_s       cn38xxp2;
-    struct cvmx_pci_dma_int_levx_s       cn50xx;
-    struct cvmx_pci_dma_int_levx_s       cn58xx;
-    struct cvmx_pci_dma_int_levx_s       cn58xxp1;
-} cvmx_pci_dma_int_levx_t;
-
-
-/**
- * cvmx_pci_dma_time#
- *
- * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0
- * 
- * Time to wait from DMA being sent before issuing an interrupt.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_dma_timex_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dma_time                : 32;      /**< Number of PCI clock cycle to wait before
-                                                         setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2.
-                                                         After PCI_DMA_CNT0 becomes non-zero.
-                                                         The timer is reset when the
-                                                         PCI_INT_SUM[27] register is cleared. */
-#else
-        uint32_t dma_time                : 32;
-#endif
-    } s;
-    struct cvmx_pci_dma_timex_s          cn30xx;
-    struct cvmx_pci_dma_timex_s          cn31xx;
-    struct cvmx_pci_dma_timex_s          cn38xx;
-    struct cvmx_pci_dma_timex_s          cn38xxp2;
-    struct cvmx_pci_dma_timex_s          cn50xx;
-    struct cvmx_pci_dma_timex_s          cn58xx;
-    struct cvmx_pci_dma_timex_s          cn58xxp1;
-} cvmx_pci_dma_timex_t;
-
-
-/**
- * cvmx_pci_instr_count#
- *
- * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count
- * 
- * The number of instructions to be fetched by the Instruction-0 Engine.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_instr_countx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t icnt                    : 32;      /**< Number of Instructions to be fetched by the
-                                                         Instruction Engine.
-                                                         A write of any non zero value to this register
-                                                         will clear the value of this register. */
-#else
-        uint32_t icnt                    : 32;
-#endif
-    } s;
-    struct cvmx_pci_instr_countx_s       cn30xx;
-    struct cvmx_pci_instr_countx_s       cn31xx;
-    struct cvmx_pci_instr_countx_s       cn38xx;
-    struct cvmx_pci_instr_countx_s       cn38xxp2;
-    struct cvmx_pci_instr_countx_s       cn50xx;
-    struct cvmx_pci_instr_countx_s       cn58xx;
-    struct cvmx_pci_instr_countx_s       cn58xxp1;
-} cvmx_pci_instr_countx_t;
-
-
-/**
- * cvmx_pci_int_enb
- *
- * PCI_INT_ENB = PCI Interrupt Enable
- * 
- * Enables interrupt bits in the PCI_INT_SUM register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
-        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
-        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
-        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
-        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
-        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
-        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
-        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
-        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
-        uint64_t iptime3                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */
-        uint64_t iptime2                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */
-        uint64_t iptime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
-        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
-        uint64_t ipcnt3                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */
-        uint64_t ipcnt2                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */
-        uint64_t ipcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
-        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
-        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
-        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
-        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
-        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
-        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
-        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
-        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
-        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
-        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
-        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
-        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
-        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
-        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
-        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
-        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
-        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
-        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
-#else
-        uint64_t itr_wabt                : 1;
-        uint64_t imr_wabt                : 1;
-        uint64_t imr_wtto                : 1;
-        uint64_t itr_abt                 : 1;
-        uint64_t imr_abt                 : 1;
-        uint64_t imr_tto                 : 1;
-        uint64_t imsi_per                : 1;
-        uint64_t imsi_tabt               : 1;
-        uint64_t imsi_mabt               : 1;
-        uint64_t imsc_msg                : 1;
-        uint64_t itsr_abt                : 1;
-        uint64_t iserr                   : 1;
-        uint64_t iaperr                  : 1;
-        uint64_t idperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t irsl_int                : 1;
-        uint64_t ipcnt0                  : 1;
-        uint64_t ipcnt1                  : 1;
-        uint64_t ipcnt2                  : 1;
-        uint64_t ipcnt3                  : 1;
-        uint64_t iptime0                 : 1;
-        uint64_t iptime1                 : 1;
-        uint64_t iptime2                 : 1;
-        uint64_t iptime3                 : 1;
-        uint64_t idcnt0                  : 1;
-        uint64_t idcnt1                  : 1;
-        uint64_t idtime0                 : 1;
-        uint64_t idtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_pci_int_enb_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
-        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
-        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
-        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
-        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
-        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
-        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
-        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
-        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
-        uint64_t reserved_22_24          : 3;
-        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
-        uint64_t reserved_18_20          : 3;
-        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
-        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
-        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
-        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
-        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
-        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
-        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
-        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
-        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
-        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
-        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
-        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
-        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
-        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
-        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
-        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
-        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
-        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
-#else
-        uint64_t itr_wabt                : 1;
-        uint64_t imr_wabt                : 1;
-        uint64_t imr_wtto                : 1;
-        uint64_t itr_abt                 : 1;
-        uint64_t imr_abt                 : 1;
-        uint64_t imr_tto                 : 1;
-        uint64_t imsi_per                : 1;
-        uint64_t imsi_tabt               : 1;
-        uint64_t imsi_mabt               : 1;
-        uint64_t imsc_msg                : 1;
-        uint64_t itsr_abt                : 1;
-        uint64_t iserr                   : 1;
-        uint64_t iaperr                  : 1;
-        uint64_t idperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t irsl_int                : 1;
-        uint64_t ipcnt0                  : 1;
-        uint64_t reserved_18_20          : 3;
-        uint64_t iptime0                 : 1;
-        uint64_t reserved_22_24          : 3;
-        uint64_t idcnt0                  : 1;
-        uint64_t idcnt1                  : 1;
-        uint64_t idtime0                 : 1;
-        uint64_t idtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn30xx;
-    struct cvmx_pci_int_enb_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
-        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
-        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
-        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
-        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
-        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
-        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
-        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
-        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
-        uint64_t reserved_23_24          : 2;
-        uint64_t iptime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
-        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
-        uint64_t reserved_19_20          : 2;
-        uint64_t ipcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
-        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
-        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
-        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
-        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
-        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
-        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
-        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
-        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
-        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
-        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
-        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
-        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
-        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
-        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
-        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
-        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
-        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
-        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
-#else
-        uint64_t itr_wabt                : 1;
-        uint64_t imr_wabt                : 1;
-        uint64_t imr_wtto                : 1;
-        uint64_t itr_abt                 : 1;
-        uint64_t imr_abt                 : 1;
-        uint64_t imr_tto                 : 1;
-        uint64_t imsi_per                : 1;
-        uint64_t imsi_tabt               : 1;
-        uint64_t imsi_mabt               : 1;
-        uint64_t imsc_msg                : 1;
-        uint64_t itsr_abt                : 1;
-        uint64_t iserr                   : 1;
-        uint64_t iaperr                  : 1;
-        uint64_t idperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t irsl_int                : 1;
-        uint64_t ipcnt0                  : 1;
-        uint64_t ipcnt1                  : 1;
-        uint64_t reserved_19_20          : 2;
-        uint64_t iptime0                 : 1;
-        uint64_t iptime1                 : 1;
-        uint64_t reserved_23_24          : 2;
-        uint64_t idcnt0                  : 1;
-        uint64_t idcnt1                  : 1;
-        uint64_t idtime0                 : 1;
-        uint64_t idtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn31xx;
-    struct cvmx_pci_int_enb_s            cn38xx;
-    struct cvmx_pci_int_enb_s            cn38xxp2;
-    struct cvmx_pci_int_enb_cn31xx       cn50xx;
-    struct cvmx_pci_int_enb_s            cn58xx;
-    struct cvmx_pci_int_enb_s            cn58xxp1;
-} cvmx_pci_int_enb_t;
-
-
-/**
- * cvmx_pci_int_enb2
- *
- * PCI_INT_ENB2 = PCI Interrupt Enable2 Register
- * 
- * Enables interrupt bits in the PCI_INT_SUM2 register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_int_enb2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
-        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
-        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
-        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
-        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
-        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
-        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
-        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
-        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
-        uint64_t rptime3                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */
-        uint64_t rptime2                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */
-        uint64_t rptime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
-        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
-        uint64_t rpcnt3                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */
-        uint64_t rpcnt2                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */
-        uint64_t rpcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
-        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
-        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
-        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
-        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
-        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
-        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
-        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
-        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
-        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
-        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
-        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
-        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
-        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
-        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
-        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
-        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
-        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
-        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
-#else
-        uint64_t rtr_wabt                : 1;
-        uint64_t rmr_wabt                : 1;
-        uint64_t rmr_wtto                : 1;
-        uint64_t rtr_abt                 : 1;
-        uint64_t rmr_abt                 : 1;
-        uint64_t rmr_tto                 : 1;
-        uint64_t rmsi_per                : 1;
-        uint64_t rmsi_tabt               : 1;
-        uint64_t rmsi_mabt               : 1;
-        uint64_t rmsc_msg                : 1;
-        uint64_t rtsr_abt                : 1;
-        uint64_t rserr                   : 1;
-        uint64_t raperr                  : 1;
-        uint64_t rdperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rrsl_int                : 1;
-        uint64_t rpcnt0                  : 1;
-        uint64_t rpcnt1                  : 1;
-        uint64_t rpcnt2                  : 1;
-        uint64_t rpcnt3                  : 1;
-        uint64_t rptime0                 : 1;
-        uint64_t rptime1                 : 1;
-        uint64_t rptime2                 : 1;
-        uint64_t rptime3                 : 1;
-        uint64_t rdcnt0                  : 1;
-        uint64_t rdcnt1                  : 1;
-        uint64_t rdtime0                 : 1;
-        uint64_t rdtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_pci_int_enb2_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
-        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
-        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
-        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
-        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
-        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
-        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
-        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
-        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
-        uint64_t reserved_22_24          : 3;
-        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
-        uint64_t reserved_18_20          : 3;
-        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
-        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
-        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
-        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
-        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
-        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
-        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
-        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
-        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
-        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
-        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
-        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
-        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
-        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
-        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
-        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
-        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
-        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
-#else
-        uint64_t rtr_wabt                : 1;
-        uint64_t rmr_wabt                : 1;
-        uint64_t rmr_wtto                : 1;
-        uint64_t rtr_abt                 : 1;
-        uint64_t rmr_abt                 : 1;
-        uint64_t rmr_tto                 : 1;
-        uint64_t rmsi_per                : 1;
-        uint64_t rmsi_tabt               : 1;
-        uint64_t rmsi_mabt               : 1;
-        uint64_t rmsc_msg                : 1;
-        uint64_t rtsr_abt                : 1;
-        uint64_t rserr                   : 1;
-        uint64_t raperr                  : 1;
-        uint64_t rdperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rrsl_int                : 1;
-        uint64_t rpcnt0                  : 1;
-        uint64_t reserved_18_20          : 3;
-        uint64_t rptime0                 : 1;
-        uint64_t reserved_22_24          : 3;
-        uint64_t rdcnt0                  : 1;
-        uint64_t rdcnt1                  : 1;
-        uint64_t rdtime0                 : 1;
-        uint64_t rdtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn30xx;
-    struct cvmx_pci_int_enb2_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
-        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
-        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
-        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
-        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
-        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
-        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
-        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
-        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
-        uint64_t reserved_23_24          : 2;
-        uint64_t rptime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
-        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
-        uint64_t reserved_19_20          : 2;
-        uint64_t rpcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
-        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
-        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
-        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
-        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
-        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
-        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
-        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
-        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
-        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
-        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
-        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
-        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
-        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
-        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
-        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
-        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
-        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
-        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
-#else
-        uint64_t rtr_wabt                : 1;
-        uint64_t rmr_wabt                : 1;
-        uint64_t rmr_wtto                : 1;
-        uint64_t rtr_abt                 : 1;
-        uint64_t rmr_abt                 : 1;
-        uint64_t rmr_tto                 : 1;
-        uint64_t rmsi_per                : 1;
-        uint64_t rmsi_tabt               : 1;
-        uint64_t rmsi_mabt               : 1;
-        uint64_t rmsc_msg                : 1;
-        uint64_t rtsr_abt                : 1;
-        uint64_t rserr                   : 1;
-        uint64_t raperr                  : 1;
-        uint64_t rdperr                  : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rrsl_int                : 1;
-        uint64_t rpcnt0                  : 1;
-        uint64_t rpcnt1                  : 1;
-        uint64_t reserved_19_20          : 2;
-        uint64_t rptime0                 : 1;
-        uint64_t rptime1                 : 1;
-        uint64_t reserved_23_24          : 2;
-        uint64_t rdcnt0                  : 1;
-        uint64_t rdcnt1                  : 1;
-        uint64_t rdtime0                 : 1;
-        uint64_t rdtime1                 : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn31xx;
-    struct cvmx_pci_int_enb2_s           cn38xx;
-    struct cvmx_pci_int_enb2_s           cn38xxp2;
-    struct cvmx_pci_int_enb2_cn31xx      cn50xx;
-    struct cvmx_pci_int_enb2_s           cn58xx;
-    struct cvmx_pci_int_enb2_s           cn58xxp1;
-} cvmx_pci_int_enb2_t;
-
-
-/**
- * cvmx_pci_int_sum
- *
- * PCI_INT_SUM = PCI Interrupt Summary
- * 
- * The PCI Interrupt Summary Register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t ptime3                  : 1;       /**< When the value in the PCI_PKTS_SENT3
-                                                         register is not 0 the Sent-3 timer counts.
-                                                         When the Sent-3 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME3 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime2                  : 1;       /**< When the value in the PCI_PKTS_SENT2
-                                                         register is not 0 the Sent-2 timer counts.
-                                                         When the Sent-2 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME2 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
-                                                         register is not 0 the Sent-1 timer counts.
-                                                         When the Sent-1 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t pcnt3                   : 1;       /**< This bit indicates that PCI_PKTS_SENT3
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
-        uint64_t pcnt2                   : 1;       /**< This bit indicates that PCI_PKTS_SENT2
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
-        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
-                                                         is asserted by the MIO. */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
-                                                         O9N (as completer), has encountered an error
-                                                         which prevents the split transaction from
-                                                         completing. In this event, the O9N (as completer),
-                                                         sends a SCM (Split Completion Message) to the
-                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
-                                                            [31:28]: Message Class = 2(completer error)
-                                                            [27:20]: Message Index = 0x80
-                                                            [18:12]: Remaining Lower Address
-                                                            [11:0]: Remaining Byte Count */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
-                                                         for either a Split-Read/Write error case.
-                                                         Set if:
-                                                            a) A Split-Write SCM is detected with SCE=1.
-                                                            b) A Split-Read SCM is detected (regardless
-                                                               of SCE status).
-                                                         The Split completion message(SCM)
-                                                         is also latched into the PCI_SCM_REG[SCM] to
-                                                         assist SW with error recovery. */
-        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
-        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
-        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t pcnt1                   : 1;
-        uint64_t pcnt2                   : 1;
-        uint64_t pcnt3                   : 1;
-        uint64_t ptime0                  : 1;
-        uint64_t ptime1                  : 1;
-        uint64_t ptime2                  : 1;
-        uint64_t ptime3                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_pci_int_sum_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t reserved_22_24          : 3;
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t reserved_18_20          : 3;
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
-                                                         is asserted by the MIO */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
-                                                         N3K (as completer), has encountered an error
-                                                         which prevents the split transaction from
-                                                         completing. In this event, the N3K (as completer),
-                                                         sends a SCM (Split Completion Message) to the
-                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
-                                                            [31:28]: Message Class = 2(completer error)
-                                                            [27:20]: Message Index = 0x80
-                                                            [18:12]: Remaining Lower Address
-                                                            [11:0]: Remaining Byte Count */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
-                                                         for either a Split-Read/Write error case.
-                                                         Set if:
-                                                            a) A Split-Write SCM is detected with SCE=1.
-                                                            b) A Split-Read SCM is detected (regardless
-                                                               of SCE status).
-                                                         The Split completion message(SCM)
-                                                         is also latched into the PCI_SCM_REG[SCM] to
-                                                         assist SW with error recovery. */
-        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
-        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
-        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t reserved_18_20          : 3;
-        uint64_t ptime0                  : 1;
-        uint64_t reserved_22_24          : 3;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn30xx;
-    struct cvmx_pci_int_sum_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t reserved_23_24          : 2;
-        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
-                                                         register is not 0 the Sent-1 timer counts.
-                                                         When the Sent-1 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t reserved_19_20          : 2;
-        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
-                                                         is asserted by the MIO */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
-                                                         N3K (as completer), has encountered an error
-                                                         which prevents the split transaction from
-                                                         completing. In this event, the N3K (as completer),
-                                                         sends a SCM (Split Completion Message) to the
-                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
-                                                            [31:28]: Message Class = 2(completer error)
-                                                            [27:20]: Message Index = 0x80
-                                                            [18:12]: Remaining Lower Address
-                                                            [11:0]: Remaining Byte Count */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
-                                                         for either a Split-Read/Write error case.
-                                                         Set if:
-                                                            a) A Split-Write SCM is detected with SCE=1.
-                                                            b) A Split-Read SCM is detected (regardless
-                                                               of SCE status).
-                                                         The Split completion message(SCM)
-                                                         is also latched into the PCI_SCM_REG[SCM] to
-                                                         assist SW with error recovery. */
-        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
-        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
-        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t pcnt1                   : 1;
-        uint64_t reserved_19_20          : 2;
-        uint64_t ptime0                  : 1;
-        uint64_t ptime1                  : 1;
-        uint64_t reserved_23_24          : 2;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn31xx;
-    struct cvmx_pci_int_sum_s            cn38xx;
-    struct cvmx_pci_int_sum_s            cn38xxp2;
-    struct cvmx_pci_int_sum_cn31xx       cn50xx;
-    struct cvmx_pci_int_sum_s            cn58xx;
-    struct cvmx_pci_int_sum_s            cn58xxp1;
-} cvmx_pci_int_sum_t;
-
-
-/**
- * cvmx_pci_int_sum2
- *
- * PCI_INT_SUM2 = PCI Interrupt Summary2 Register
- * 
- * The PCI Interrupt Summary2 Register copy used for RSL interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_int_sum2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t ptime3                  : 1;       /**< When the value in the PCI_PKTS_SENT3
-                                                         register is not 0 the Sent-3 timer counts.
-                                                         When the Sent-3 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME3 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime2                  : 1;       /**< When the value in the PCI_PKTS_SENT2
-                                                         register is not 0 the Sent-2 timer counts.
-                                                         When the Sent-2 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME2 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
-                                                         register is not 0 the Sent-1 timer counts.
-                                                         When the Sent-1 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t pcnt3                   : 1;       /**< This bit indicates that PCI_PKTS_SENT3
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
-        uint64_t pcnt2                   : 1;       /**< This bit indicates that PCI_PKTS_SENT2
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
-        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
-                                                         generated an interrupt. */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
-        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
-        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
-        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t pcnt1                   : 1;
-        uint64_t pcnt2                   : 1;
-        uint64_t pcnt3                   : 1;
-        uint64_t ptime0                  : 1;
-        uint64_t ptime1                  : 1;
-        uint64_t ptime2                  : 1;
-        uint64_t ptime3                  : 1;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } s;
-    struct cvmx_pci_int_sum2_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t reserved_22_24          : 3;
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t reserved_18_20          : 3;
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
-                                                         generated an interrupt. */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
-        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
-        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
-        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t reserved_18_20          : 3;
-        uint64_t ptime0                  : 1;
-        uint64_t reserved_22_24          : 3;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn30xx;
-    struct cvmx_pci_int_sum2_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_34_63          : 30;
-        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
-                                                         when the mem area is disabled. */
-        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
-                                                         Read-Address Register took place. */
-        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 1. */
-        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
-                                                         required to set the FORCE-INT bit for counter 0. */
-        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
-                                                         register is not 0 the DMA_CNT1 timer counts.
-                                                         When the DMA1_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
-                                                         register is not 0 the DMA_CNT0 timer counts.
-                                                         When the DMA0_CNT timer has a value greater
-                                                         than the PCI_DMA_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV1 register. */
-        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
-                                                         value is greater than the value
-                                                         in the PCI_DMA_INT_LEV0 register. */
-        uint64_t reserved_23_24          : 2;
-        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
-                                                         register is not 0 the Sent-1 timer counts.
-                                                         When the Sent-1 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME1 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
-                                                         register is not 0 the Sent-0 timer counts.
-                                                         When the Sent-0 timer has a value greater
-                                                         than the PCI_PKTS_SENT_TIME0 register this
-                                                         bit is set. The timer is reset when bit is
-                                                         written with a one. */
-        uint64_t reserved_19_20          : 2;
-        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
-        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
-                                                         value is greater than the value
-                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
-        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
-                                                         generated an interrupt. */
-        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
-        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
-        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
-        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
-        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
-        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
-        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
-        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
-        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
-        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
-        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
-        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
-        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
-        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
-        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
-        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
-#else
-        uint64_t tr_wabt                 : 1;
-        uint64_t mr_wabt                 : 1;
-        uint64_t mr_wtto                 : 1;
-        uint64_t tr_abt                  : 1;
-        uint64_t mr_abt                  : 1;
-        uint64_t mr_tto                  : 1;
-        uint64_t msi_per                 : 1;
-        uint64_t msi_tabt                : 1;
-        uint64_t msi_mabt                : 1;
-        uint64_t msc_msg                 : 1;
-        uint64_t tsr_abt                 : 1;
-        uint64_t serr                    : 1;
-        uint64_t aperr                   : 1;
-        uint64_t dperr                   : 1;
-        uint64_t ill_rwr                 : 1;
-        uint64_t ill_rrd                 : 1;
-        uint64_t rsl_int                 : 1;
-        uint64_t pcnt0                   : 1;
-        uint64_t pcnt1                   : 1;
-        uint64_t reserved_19_20          : 2;
-        uint64_t ptime0                  : 1;
-        uint64_t ptime1                  : 1;
-        uint64_t reserved_23_24          : 2;
-        uint64_t dcnt0                   : 1;
-        uint64_t dcnt1                   : 1;
-        uint64_t dtime0                  : 1;
-        uint64_t dtime1                  : 1;
-        uint64_t dma0_fi                 : 1;
-        uint64_t dma1_fi                 : 1;
-        uint64_t win_wr                  : 1;
-        uint64_t ill_wr                  : 1;
-        uint64_t ill_rd                  : 1;
-        uint64_t reserved_34_63          : 30;
-#endif
-    } cn31xx;
-    struct cvmx_pci_int_sum2_s           cn38xx;
-    struct cvmx_pci_int_sum2_s           cn38xxp2;
-    struct cvmx_pci_int_sum2_cn31xx      cn50xx;
-    struct cvmx_pci_int_sum2_s           cn58xx;
-    struct cvmx_pci_int_sum2_s           cn58xxp1;
-} cvmx_pci_int_sum2_t;
-
-
-/**
- * cvmx_pci_msi_rcv
- *
- * PCI_MSI_RCV = PCI's MSI Received Vector Register
- * 
- * A bit is set in this register relative to the vector received during a MSI. The value in this
- * register is acted upon when the least-significant-byte of this register is written.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_msi_rcv_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_6_31           : 26;
-        uint32_t intr                    : 6;       /**< When an MSI is received on the PCI the bit selected
-                                                         by data [5:0] will be set in this register. To
-                                                         clear this bit a write must take place to the
-                                                         NPI_MSI_RCV register where any bit set to 1 is
-                                                         cleared. Reading this address will return an
-                                                         unpredicatable value. */
-#else
-        uint32_t intr                    : 6;
-        uint32_t reserved_6_31           : 26;
-#endif
-    } s;
-    struct cvmx_pci_msi_rcv_s            cn30xx;
-    struct cvmx_pci_msi_rcv_s            cn31xx;
-    struct cvmx_pci_msi_rcv_s            cn38xx;
-    struct cvmx_pci_msi_rcv_s            cn38xxp2;
-    struct cvmx_pci_msi_rcv_s            cn50xx;
-    struct cvmx_pci_msi_rcv_s            cn58xx;
-    struct cvmx_pci_msi_rcv_s            cn58xxp1;
-} cvmx_pci_msi_rcv_t;
-
-
-/**
- * cvmx_pci_pkt_credits#
- *
- * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0
- * 
- * Used to decrease the number of packets to be processed by the host from Output-0 and return
- * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the
- * least-significant-byte of this register is written.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_pkt_creditsx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pkt_cnt                 : 16;      /**< The value written to this field will be
-                                                         subtracted from PCI_PKTS_SENT0[PKT_CNT]. */
-        uint32_t ptr_cnt                 : 16;      /**< This field value is added to the
-                                                         NPI's internal Buffer/Info Pointer Pair count. */
-#else
-        uint32_t ptr_cnt                 : 16;
-        uint32_t pkt_cnt                 : 16;
-#endif
-    } s;
-    struct cvmx_pci_pkt_creditsx_s       cn30xx;
-    struct cvmx_pci_pkt_creditsx_s       cn31xx;
-    struct cvmx_pci_pkt_creditsx_s       cn38xx;
-    struct cvmx_pci_pkt_creditsx_s       cn38xxp2;
-    struct cvmx_pci_pkt_creditsx_s       cn50xx;
-    struct cvmx_pci_pkt_creditsx_s       cn58xx;
-    struct cvmx_pci_pkt_creditsx_s       cn58xxp1;
-} cvmx_pci_pkt_creditsx_t;
-
-
-/**
- * cvmx_pci_pkts_sent#
- *
- * PCI_PKTS_SENT0 = PCI Packets Sent 0
- * 
- * Number of packets sent to the host memory from PCI Output 0
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_pkts_sentx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pkt_cnt                 : 32;      /**< Each time a packet is written to the memory via
-                                                         PCI from PCI Output 0,  this counter is
-                                                         incremented by 1 or the byte count of the packet
-                                                         as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */
-#else
-        uint32_t pkt_cnt                 : 32;
-#endif
-    } s;
-    struct cvmx_pci_pkts_sentx_s         cn30xx;
-    struct cvmx_pci_pkts_sentx_s         cn31xx;
-    struct cvmx_pci_pkts_sentx_s         cn38xx;
-    struct cvmx_pci_pkts_sentx_s         cn38xxp2;
-    struct cvmx_pci_pkts_sentx_s         cn50xx;
-    struct cvmx_pci_pkts_sentx_s         cn58xx;
-    struct cvmx_pci_pkts_sentx_s         cn58xxp1;
-} cvmx_pci_pkts_sentx_t;
-
-
-/**
- * cvmx_pci_pkts_sent_int_lev#
- *
- * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0
- * 
- * Interrupt when number of packets sent is equal to or greater than the register value.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_pkts_sent_int_levx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pkt_cnt                 : 32;      /**< When corresponding port's PCI_PKTS_SENT0 value
-                                                         exceeds the value in this register, PCNT0 of the
-                                                         PCI_INT_SUM and PCI_INT_SUM2 will be set. */
-#else
-        uint32_t pkt_cnt                 : 32;
-#endif
-    } s;
-    struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
-    struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
-    struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
-    struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
-    struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
-    struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
-    struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
-} cvmx_pci_pkts_sent_int_levx_t;
-
-
-/**
- * cvmx_pci_pkts_sent_time#
- *
- * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0
- * 
- * Time to wait from packet being sent to host from Output-0 before issuing an interrupt.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_pkts_sent_timex_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pkt_time                : 32;      /**< Number of PCI clock cycle to wait before
-                                                         issuing an interrupt to the host when a
-                                                         packet from this port has been sent to the
-                                                         host.  The timer is reset when the
-                                                         PCI_INT_SUM[21] register is cleared. */
-#else
-        uint32_t pkt_time                : 32;
-#endif
-    } s;
-    struct cvmx_pci_pkts_sent_timex_s    cn30xx;
-    struct cvmx_pci_pkts_sent_timex_s    cn31xx;
-    struct cvmx_pci_pkts_sent_timex_s    cn38xx;
-    struct cvmx_pci_pkts_sent_timex_s    cn38xxp2;
-    struct cvmx_pci_pkts_sent_timex_s    cn50xx;
-    struct cvmx_pci_pkts_sent_timex_s    cn58xx;
-    struct cvmx_pci_pkts_sent_timex_s    cn58xxp1;
-} cvmx_pci_pkts_sent_timex_t;
-
-
-/**
- * cvmx_pci_read_cmd_6
- *
- * PCI_READ_CMD_6 = PCI Read Command 6 Register
- * 
- * Contains control inforamtion related to a received PCI Command 6.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_read_cmd_6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
-                                                         before informing the PCIX-Core that we have
-                                                         read data available for the outstanding Delayed
-                                                         read. 0 is treated as a 64.
-                                                         For reads to the expansion this value is not used. */
-        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
-                                                         this type of bhmstREAD command is received.
-                                                         0 = 1 32/64 bit word.
-                                                         1 = From address to end of 128B block.
-                                                         2 = From address to end of 128B block plus 128B.
-                                                         3 = From address to end of 128B block plus 256B.
-                                                         4 = From address to end of 128B block plus 384B.
-                                                         For reads to the expansion this value is not used. */
-#else
-        uint32_t prefetch                : 3;
-        uint32_t min_data                : 6;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_pci_read_cmd_6_s         cn30xx;
-    struct cvmx_pci_read_cmd_6_s         cn31xx;
-    struct cvmx_pci_read_cmd_6_s         cn38xx;
-    struct cvmx_pci_read_cmd_6_s         cn38xxp2;
-    struct cvmx_pci_read_cmd_6_s         cn50xx;
-    struct cvmx_pci_read_cmd_6_s         cn58xx;
-    struct cvmx_pci_read_cmd_6_s         cn58xxp1;
-} cvmx_pci_read_cmd_6_t;
-
-
-/**
- * cvmx_pci_read_cmd_c
- *
- * PCI_READ_CMD_C = PCI Read Command C Register
- * 
- * Contains control inforamtion related to a received PCI Command C.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_read_cmd_c_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
-                                                         before informing the PCIX-Core that we have
-                                                         read data available for the outstanding Delayed
-                                                         read. 0 is treated as a 64.
-                                                         For reads to the expansion this value is not used. */
-        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
-                                                         this type of READ command is received.
-                                                         0 = 1 32/64 bit word.
-                                                         1 = From address to end of 128B block.
-                                                         2 = From address to end of 128B block plus 128B.
-                                                         3 = From address to end of 128B block plus 256B.
-                                                         4 = From address to end of 128B block plus 384B.
-                                                         For reads to the expansion this value is not used. */
-#else
-        uint32_t prefetch                : 3;
-        uint32_t min_data                : 6;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_pci_read_cmd_c_s         cn30xx;
-    struct cvmx_pci_read_cmd_c_s         cn31xx;
-    struct cvmx_pci_read_cmd_c_s         cn38xx;
-    struct cvmx_pci_read_cmd_c_s         cn38xxp2;
-    struct cvmx_pci_read_cmd_c_s         cn50xx;
-    struct cvmx_pci_read_cmd_c_s         cn58xx;
-    struct cvmx_pci_read_cmd_c_s         cn58xxp1;
-} cvmx_pci_read_cmd_c_t;
-
-
-/**
- * cvmx_pci_read_cmd_e
- *
- * PCI_READ_CMD_E = PCI Read Command E Register
- * 
- * Contains control inforamtion related to a received PCI Command 6.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pci_read_cmd_e_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
-                                                         before informaing the PCIX-Core that we have
-                                                         read data available for the outstanding Delayed
-                                                         read. 0 is treated as a 64.
-                                                         For reads to the expansion this value is not used. */
-        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
-                                                         this type of READ command is received.
-                                                         0 = 1 32/64 bit word.
-                                                         1 = From address to end of 128B block.
-                                                         2 = From address to end of 128B block plus 128B.
-                                                         3 = From address to end of 128B block plus 256B.
-                                                         4 = From address to end of 128B block plus 384B.
-                                                         For reads to the expansion this value is not used. */
-#else
-        uint32_t prefetch                : 3;
-        uint32_t min_data                : 6;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_pci_read_cmd_e_s         cn30xx;
-    struct cvmx_pci_read_cmd_e_s         cn31xx;
-    struct cvmx_pci_read_cmd_e_s         cn38xx;
-    struct cvmx_pci_read_cmd_e_s         cn38xxp2;
-    struct cvmx_pci_read_cmd_e_s         cn50xx;
-    struct cvmx_pci_read_cmd_e_s         cn58xx;
-    struct cvmx_pci_read_cmd_e_s         cn58xxp1;
-} cvmx_pci_read_cmd_e_t;
-
-
-/**
- * cvmx_pci_read_timeout
- *
- * PCI_READ_TIMEOUT = PCI Read Timeour Register
- * 
- * The address to start reading Instructions from for Input-3.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_read_timeout_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t enb                     : 1;       /**< Enable the use of the Timeout function. */
-        uint64_t cnt                     : 31;      /**< The number of eclk cycles to wait after issuing
-                                                         a read request to the PNI before setting a
-                                                         timeout and not expecting the data to return.
-                                                         This is considered a fatal condition by the NPI. */
-#else
-        uint64_t cnt                     : 31;
-        uint64_t enb                     : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pci_read_timeout_s       cn30xx;
-    struct cvmx_pci_read_timeout_s       cn31xx;
-    struct cvmx_pci_read_timeout_s       cn38xx;
-    struct cvmx_pci_read_timeout_s       cn38xxp2;
-    struct cvmx_pci_read_timeout_s       cn50xx;
-    struct cvmx_pci_read_timeout_s       cn58xx;
-    struct cvmx_pci_read_timeout_s       cn58xxp1;
-} cvmx_pci_read_timeout_t;
-
-
-/**
- * cvmx_pci_scm_reg
- *
- * PCI_SCM_REG = PCI Master Split Completion Message Register
- * 
- * This register contains the Master Split Completion Message(SCM) generated when a master split
- * transaction is aborted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_scm_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t scm                     : 32;      /**< Contains the Split Completion Message (SCM)
-                                                         driven when a master-split transaction is aborted.
-                                                            [31:28]: Message Class
-                                                            [27:20]: Message Index
-                                                            [19]:    Reserved
-                                                            [18:12]: Remaining Lower Address
-                                                            [11:8]:  Upper Remaining Byte Count
-                                                            [7:0]:   Lower Remaining Byte Count
-                                                         Refer to the PCIX1.0a specification, Fig 2-40
-                                                         for additional details for the split completion
-                                                         message format. */
-#else
-        uint64_t scm                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pci_scm_reg_s            cn30xx;
-    struct cvmx_pci_scm_reg_s            cn31xx;
-    struct cvmx_pci_scm_reg_s            cn38xx;
-    struct cvmx_pci_scm_reg_s            cn38xxp2;
-    struct cvmx_pci_scm_reg_s            cn50xx;
-    struct cvmx_pci_scm_reg_s            cn58xx;
-    struct cvmx_pci_scm_reg_s            cn58xxp1;
-} cvmx_pci_scm_reg_t;
-
-
-/**
- * cvmx_pci_tsr_reg
- *
- * PCI_TSR_REG = PCI Target Split Attribute Register
- * 
- * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split
- * transaction is aborted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_tsr_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t tsr                     : 36;      /**< Contains the Target Split Attribute field when a
-                                                         target-split transaction is aborted.
-                                                           [35:32]: Upper Byte Count
-                                                           [31]:    BCM=Byte Count Modified
-                                                           [30]:    SCE=Split Completion Error
-                                                           [29]:    SCM=Split Completion Message
-                                                           [28:24]: RESERVED
-                                                           [23:16]: Completer Bus Number
-                                                           [15:11]: Completer Device Number
-                                                           [10:8]:  Completer Function Number
-                                                           [7:0]:   Lower Byte Count
-                                                         Refer to the PCIX1.0a specification, Fig 2-39
-                                                         for additional details on the completer attribute
-                                                         bit assignments. */
-#else
-        uint64_t tsr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_pci_tsr_reg_s            cn30xx;
-    struct cvmx_pci_tsr_reg_s            cn31xx;
-    struct cvmx_pci_tsr_reg_s            cn38xx;
-    struct cvmx_pci_tsr_reg_s            cn38xxp2;
-    struct cvmx_pci_tsr_reg_s            cn50xx;
-    struct cvmx_pci_tsr_reg_s            cn58xx;
-    struct cvmx_pci_tsr_reg_s            cn58xxp1;
-} cvmx_pci_tsr_reg_t;
-
-
-/**
- * cvmx_pci_win_rd_addr
- *
- * PCI_WIN_RD_ADDR = PCI Window Read Address Register
- * 
- * Writing the least-significant-byte of this register will cause a read operation to take place,
- * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA
- * register is read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_win_rd_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t reserved_0_47           : 48;
-#else
-        uint64_t reserved_0_47           : 48;
-        uint64_t iobit                   : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_pci_win_rd_addr_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t rd_addr                 : 46;      /**< The address to be read from. Whenever the LSB of
-                                                         this register is written, the Read Operation will
-                                                         take place.
-                                                         [47:40] = NCB_ID
-                                                         [39:3]  = Address
-                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
-                                                              [39:32] == x, Not Used
-                                                              [31:27] == RSL_ID
-                                                              [12:2]  == RSL Register Offset
-                                                              [1:0]   == x, Not Used */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t rd_addr                 : 46;
-        uint64_t iobit                   : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } cn30xx;
-    struct cvmx_pci_win_rd_addr_cn30xx   cn31xx;
-    struct cvmx_pci_win_rd_addr_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t rd_addr                 : 45;      /**< The address to be read from. Whenever the LSB of
-                                                         this register is written, the Read Operation will
-                                                         take place.
-                                                         [47:40] = NCB_ID
-                                                         [39:3]  = Address
-                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
-                                                              [39:32] == x, Not Used
-                                                              [31:27] == RSL_ID
-                                                              [12:3]  == RSL Register Offset
-                                                              [2:0]   == x, Not Used */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t rd_addr                 : 45;
-        uint64_t iobit                   : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } cn38xx;
-    struct cvmx_pci_win_rd_addr_cn38xx   cn38xxp2;
-    struct cvmx_pci_win_rd_addr_cn30xx   cn50xx;
-    struct cvmx_pci_win_rd_addr_cn38xx   cn58xx;
-    struct cvmx_pci_win_rd_addr_cn38xx   cn58xxp1;
-} cvmx_pci_win_rd_addr_t;
-
-
-/**
- * cvmx_pci_win_rd_data
- *
- * PCI_WIN_RD_DATA = PCI Window Read Data Register
- * 
- * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR
- * register was written.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_win_rd_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t rd_data                 : 64;      /**< The read data. */
-#else
-        uint64_t rd_data                 : 64;
-#endif
-    } s;
-    struct cvmx_pci_win_rd_data_s        cn30xx;
-    struct cvmx_pci_win_rd_data_s        cn31xx;
-    struct cvmx_pci_win_rd_data_s        cn38xx;
-    struct cvmx_pci_win_rd_data_s        cn38xxp2;
-    struct cvmx_pci_win_rd_data_s        cn50xx;
-    struct cvmx_pci_win_rd_data_s        cn58xx;
-    struct cvmx_pci_win_rd_data_s        cn58xxp1;
-} cvmx_pci_win_rd_data_t;
-
-
-/**
- * cvmx_pci_win_wr_addr
- *
- * PCI_WIN_WR_ADDR = PCI Window Write Address Register
- * 
- * Contains the address to be writen to when a write operation is started by writing the
- * PCI_WIN_WR_DATA register (see below).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_win_wr_addr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
-                                                         read as '0'. */
-        uint64_t wr_addr                 : 45;      /**< The address that will be written to when the
-                                                         PCI_WIN_WR_DATA register is written.
-                                                         [47:40] = NCB_ID
-                                                         [39:3]  = Address
-                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
-                                                              [39:32] == x, Not Used
-                                                              [31:27] == RSL_ID
-                                                              [12:3]  == RSL Register Offset
-                                                              [2:0]   == x, Not Used */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t wr_addr                 : 45;
-        uint64_t iobit                   : 1;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_pci_win_wr_addr_s        cn30xx;
-    struct cvmx_pci_win_wr_addr_s        cn31xx;
-    struct cvmx_pci_win_wr_addr_s        cn38xx;
-    struct cvmx_pci_win_wr_addr_s        cn38xxp2;
-    struct cvmx_pci_win_wr_addr_s        cn50xx;
-    struct cvmx_pci_win_wr_addr_s        cn58xx;
-    struct cvmx_pci_win_wr_addr_s        cn58xxp1;
-} cvmx_pci_win_wr_addr_t;
-
-
-/**
- * cvmx_pci_win_wr_data
- *
- * PCI_WIN_WR_DATA = PCI Window Write Data Register
- * 
- * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register.
- * Writing the least-significant-byte of this register will cause a write operation to take place.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_win_wr_data_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t wr_data                 : 64;      /**< The data to be written. Whenever the LSB of this
-                                                         register is written, the Window Write will take
-                                                         place. */
-#else
-        uint64_t wr_data                 : 64;
-#endif
-    } s;
-    struct cvmx_pci_win_wr_data_s        cn30xx;
-    struct cvmx_pci_win_wr_data_s        cn31xx;
-    struct cvmx_pci_win_wr_data_s        cn38xx;
-    struct cvmx_pci_win_wr_data_s        cn38xxp2;
-    struct cvmx_pci_win_wr_data_s        cn50xx;
-    struct cvmx_pci_win_wr_data_s        cn58xx;
-    struct cvmx_pci_win_wr_data_s        cn58xxp1;
-} cvmx_pci_win_wr_data_t;
-
-
-/**
- * cvmx_pci_win_wr_mask
- *
- * PCI_WIN_WR_MASK = PCI Window Write Mask Register
- * 
- * Contains the mask for the data in the PCI_WIN_WR_DATA Register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pci_win_wr_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t wr_mask                 : 8;       /**< The data to be written. When a bit is set '1'
-                                                         the corresponding byte will not be written. */
-#else
-        uint64_t wr_mask                 : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pci_win_wr_mask_s        cn30xx;
-    struct cvmx_pci_win_wr_mask_s        cn31xx;
-    struct cvmx_pci_win_wr_mask_s        cn38xx;
-    struct cvmx_pci_win_wr_mask_s        cn38xxp2;
-    struct cvmx_pci_win_wr_mask_s        cn50xx;
-    struct cvmx_pci_win_wr_mask_s        cn58xx;
-    struct cvmx_pci_win_wr_mask_s        cn58xxp1;
-} cvmx_pci_win_wr_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg000
- *
- * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg000_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t devid                   : 16;      /**< Device ID, writable through the DBI
-                                                          However, the application must not change this field.
-                                                         For EEPROM loads also see VENDID of this register. */
-        uint32_t vendid                  : 16;      /**< Vendor ID, writable through the DBI
-                                                          However, the application must not change this field.
-                                                         During and EPROM Load is a value of 0xFFFF is loaded to this
-                                                         field and a value of 0xFFFF is loaded to the DEVID field of
-                                                         this register, the value will not be loaded, EEPROM load will
-                                                         stop, and the FastLinkEnable bit will be set in the
-                                                         PCIE_CFG452 register. */
-#else
-        uint32_t vendid                  : 16;
-        uint32_t devid                   : 16;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg000_s          cn52xx;
-    struct cvmx_pcieep_cfg000_s          cn52xxp1;
-    struct cvmx_pcieep_cfg000_s          cn56xx;
-    struct cvmx_pcieep_cfg000_s          cn56xxp1;
-} cvmx_pcieep_cfg000_t;
-
-
-/**
- * cvmx_pcieep_cfg001
- *
- * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg001_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dpe                     : 1;       /**< Detected Parity Error */
-        uint32_t sse                     : 1;       /**< Signaled System Error */
-        uint32_t rma                     : 1;       /**< Received Master Abort */
-        uint32_t rta                     : 1;       /**< Received Target Abort */
-        uint32_t sta                     : 1;       /**< Signaled Target Abort */
-        uint32_t devt                    : 2;       /**< DEVSEL Timing
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
-        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t reserved_22_22          : 1;
-        uint32_t m66                     : 1;       /**< 66 MHz Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t cl                      : 1;       /**< Capabilities List
-                                                         Indicates presence of an extended capability item.
-                                                         Hardwired to 1. */
-        uint32_t i_stat                  : 1;       /**< INTx Status */
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_dis                   : 1;       /**< INTx Assertion Disable */
-        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Enable
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t see                     : 1;       /**< SERR# Enable */
-        uint32_t ids_wcc                 : 1;       /**< IDSEL Stepping/Wait Cycle Control
-                                                         Not applicable for PCI Express. Must be hardwired to 0 */
-        uint32_t per                     : 1;       /**< Parity Error Response */
-        uint32_t vps                     : 1;       /**< VGA Palette Snoop
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t mwice                   : 1;       /**< Memory Write and Invalidate
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t scse                    : 1;       /**< Special Cycle Enable
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t me                      : 1;       /**< Bus Master Enable */
-        uint32_t msae                    : 1;       /**< Memory Space Enable */
-        uint32_t isae                    : 1;       /**< I/O Space Enable */
-#else
-        uint32_t isae                    : 1;
-        uint32_t msae                    : 1;
-        uint32_t me                      : 1;
-        uint32_t scse                    : 1;
-        uint32_t mwice                   : 1;
-        uint32_t vps                     : 1;
-        uint32_t per                     : 1;
-        uint32_t ids_wcc                 : 1;
-        uint32_t see                     : 1;
-        uint32_t fbbe                    : 1;
-        uint32_t i_dis                   : 1;
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_stat                  : 1;
-        uint32_t cl                      : 1;
-        uint32_t m66                     : 1;
-        uint32_t reserved_22_22          : 1;
-        uint32_t fbb                     : 1;
-        uint32_t mdpe                    : 1;
-        uint32_t devt                    : 2;
-        uint32_t sta                     : 1;
-        uint32_t rta                     : 1;
-        uint32_t rma                     : 1;
-        uint32_t sse                     : 1;
-        uint32_t dpe                     : 1;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg001_s          cn52xx;
-    struct cvmx_pcieep_cfg001_s          cn52xxp1;
-    struct cvmx_pcieep_cfg001_s          cn56xx;
-    struct cvmx_pcieep_cfg001_s          cn56xxp1;
-} cvmx_pcieep_cfg001_t;
-
-
-/**
- * cvmx_pcieep_cfg002
- *
- * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg002_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t bcc                     : 8;       /**< Base Class Code, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t sc                      : 8;       /**< Subclass Code, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pi                      : 8;       /**< Programming Interface, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t rid                     : 8;       /**< Revision ID, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t rid                     : 8;
-        uint32_t pi                      : 8;
-        uint32_t sc                      : 8;
-        uint32_t bcc                     : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg002_s          cn52xx;
-    struct cvmx_pcieep_cfg002_s          cn52xxp1;
-    struct cvmx_pcieep_cfg002_s          cn56xx;
-    struct cvmx_pcieep_cfg002_s          cn56xxp1;
-} cvmx_pcieep_cfg002_t;
-
-
-/**
- * cvmx_pcieep_cfg003
- *
- * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg003_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t bist                    : 8;       /**< The BIST register functions are not supported.
-                                                         All 8 bits of the BIST register are hardwired to 0. */
-        uint32_t mfd                     : 1;       /**< Multi Function Device
-                                                         The Multi Function Device bit is writable through the DBI.
-                                                         However, this is a single function device. Therefore, the
-                                                         application must not write a 1 to this bit. */
-        uint32_t chf                     : 7;       /**< Configuration Header Format
-                                                         Hardwired to 0 for type 0. */
-        uint32_t lt                      : 8;       /**< Master Latency Timer
-                                                         Not applicable for PCI Express, hardwired to 0. */
-        uint32_t cls                     : 8;       /**< Cache Line Size
-                                                         The Cache Line Size register is RW for legacy compatibility
-                                                         purposes and is not applicable to PCI Express device
-                                                         functionality.
-                                                         Writing to the Cache Line Size register does not impact
-                                                         functionality. */
-#else
-        uint32_t cls                     : 8;
-        uint32_t lt                      : 8;
-        uint32_t chf                     : 7;
-        uint32_t mfd                     : 1;
-        uint32_t bist                    : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg003_s          cn52xx;
-    struct cvmx_pcieep_cfg003_s          cn52xxp1;
-    struct cvmx_pcieep_cfg003_s          cn56xx;
-    struct cvmx_pcieep_cfg003_s          cn56xxp1;
-} cvmx_pcieep_cfg003_t;
-
-
-/**
- * cvmx_pcieep_cfg004
- *
- * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg004_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lbab                    : 18;      /**< Lower bits of the BAR 0 base address */
-        uint32_t reserved_4_13           : 10;
-        uint32_t pf                      : 1;       /**< Prefetchable
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t typ                     : 2;       /**< BAR type
-                                                            o 00 = 32-bit BAR
-                                                            o 10 = 64-bit BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator
-                                                            o 0 = BAR 0 is a memory BAR
-                                                            o 1 = BAR 0 is an I/O BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t reserved_4_13           : 10;
-        uint32_t lbab                    : 18;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg004_s          cn52xx;
-    struct cvmx_pcieep_cfg004_s          cn52xxp1;
-    struct cvmx_pcieep_cfg004_s          cn56xx;
-    struct cvmx_pcieep_cfg004_s          cn56xxp1;
-} cvmx_pcieep_cfg004_t;
-
-
-/**
- * cvmx_pcieep_cfg004_mask
- *
- * PCIE_CFG004_MASK (BAR Mask 0 - Low)
- * The BAR 0 Mask register is invisible to host software and not readable from the application.
- * The BAR 0 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg004_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmask                   : 31;      /**< Bar Mask Low */
-        uint32_t enb                     : 1;       /**< Bar Enable
-                                                         o 0: BAR 0 is disabled
-                                                         o 1: BAR 0 is enabled
-                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
-                                                         register rather than as a mask bit because bit 0 of a BAR is
-                                                         always masked from writing by host software. Bit 0 must be
-                                                         written prior to writing the other mask bits. */
-#else
-        uint32_t enb                     : 1;
-        uint32_t lmask                   : 31;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg004_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg004_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg004_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg004_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg004_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg005
- *
- * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg005_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ubab                    : 32;      /**< Contains the upper 32 bits of the BAR 0 base address. */
-#else
-        uint32_t ubab                    : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg005_s          cn52xx;
-    struct cvmx_pcieep_cfg005_s          cn52xxp1;
-    struct cvmx_pcieep_cfg005_s          cn56xx;
-    struct cvmx_pcieep_cfg005_s          cn56xxp1;
-} cvmx_pcieep_cfg005_t;
-
-
-/**
- * cvmx_pcieep_cfg005_mask
- *
- * PCIE_CFG005_MASK = (BAR Mask 0 - High)
- * The BAR 0 Mask register is invisible to host software and not readable from the application.
- * The BAR 0 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg005_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umask                   : 32;      /**< Bar Mask High */
-#else
-        uint32_t umask                   : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg005_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg005_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg005_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg005_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg005_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg006
- *
- * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg006_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lbab                    : 6;       /**< Lower bits of the BAR 1 base address */
-        uint32_t reserved_4_25           : 22;
-        uint32_t pf                      : 1;       /**< Prefetchable
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t typ                     : 2;       /**< BAR type
-                                                            o 00 = 32-bit BAR
-                                                            o 10 = 64-bit BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator
-                                                            o 0 = BAR 0 is a memory BAR
-                                                            o 1 = BAR 0 is an I/O BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t reserved_4_25           : 22;
-        uint32_t lbab                    : 6;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg006_s          cn52xx;
-    struct cvmx_pcieep_cfg006_s          cn52xxp1;
-    struct cvmx_pcieep_cfg006_s          cn56xx;
-    struct cvmx_pcieep_cfg006_s          cn56xxp1;
-} cvmx_pcieep_cfg006_t;
-
-
-/**
- * cvmx_pcieep_cfg006_mask
- *
- * PCIE_CFG006_MASK (BAR Mask 1 - Low)
- * The BAR 1 Mask register is invisible to host software and not readable from the application.
- * The BAR 1 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg006_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmask                   : 31;      /**< Bar Mask Low */
-        uint32_t enb                     : 1;       /**< Bar Enable
-                                                         o 0: BAR 1 is disabled
-                                                         o 1: BAR 1 is enabled
-                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
-                                                         register rather than as a mask bit because bit 0 of a BAR is
-                                                         always masked from writing by host software. Bit 0 must be
-                                                         written prior to writing the other mask bits. */
-#else
-        uint32_t enb                     : 1;
-        uint32_t lmask                   : 31;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg006_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg006_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg006_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg006_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg006_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg007
- *
- * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg007_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ubab                    : 32;      /**< Contains the upper 32 bits of the BAR 1 base address. */
-#else
-        uint32_t ubab                    : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg007_s          cn52xx;
-    struct cvmx_pcieep_cfg007_s          cn52xxp1;
-    struct cvmx_pcieep_cfg007_s          cn56xx;
-    struct cvmx_pcieep_cfg007_s          cn56xxp1;
-} cvmx_pcieep_cfg007_t;
-
-
-/**
- * cvmx_pcieep_cfg007_mask
- *
- * PCIE_CFG007_MASK (BAR Mask 1 - High)
- * The BAR 1 Mask register is invisible to host software and not readable from the application.
- * The BAR 1 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg007_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umask                   : 32;      /**< Bar Mask High */
-#else
-        uint32_t umask                   : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg007_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg007_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg007_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg007_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg007_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg008
- *
- * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg008_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_4_31           : 28;
-        uint32_t pf                      : 1;       /**< Prefetchable
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t typ                     : 2;       /**< BAR type
-                                                            o 00 = 32-bit BAR
-                                                            o 10 = 64-bit BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t mspc                    : 1;       /**< Memory Space Indicator
-                                                            o 0 = BAR 0 is a memory BAR
-                                                            o 1 = BAR 0 is an I/O BAR
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t mspc                    : 1;
-        uint32_t typ                     : 2;
-        uint32_t pf                      : 1;
-        uint32_t reserved_4_31           : 28;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg008_s          cn52xx;
-    struct cvmx_pcieep_cfg008_s          cn52xxp1;
-    struct cvmx_pcieep_cfg008_s          cn56xx;
-    struct cvmx_pcieep_cfg008_s          cn56xxp1;
-} cvmx_pcieep_cfg008_t;
-
-
-/**
- * cvmx_pcieep_cfg008_mask
- *
- * PCIE_CFG008_MASK (BAR Mask 2 - Low)
- * The BAR 2 Mask register is invisible to host software and not readable from the application.
- * The BAR 2 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg008_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmask                   : 31;      /**< Bar Mask Low */
-        uint32_t enb                     : 1;       /**< Bar Enable
-                                                         o 0: BAR 2 is disabled
-                                                         o 1: BAR 2 is enabled
-                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
-                                                         register rather than as a mask bit because bit 0 of a BAR is
-                                                         always masked from writing by host software. Bit 0 must be
-                                                         written prior to writing the other mask bits. */
-#else
-        uint32_t enb                     : 1;
-        uint32_t lmask                   : 31;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg008_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg008_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg008_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg008_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg008_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg009
- *
- * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg009_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ubab                    : 25;      /**< Contains the upper 32 bits of the BAR 2 base address. */
-        uint32_t reserved_0_6            : 7;
-#else
-        uint32_t reserved_0_6            : 7;
-        uint32_t ubab                    : 25;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg009_s          cn52xx;
-    struct cvmx_pcieep_cfg009_s          cn52xxp1;
-    struct cvmx_pcieep_cfg009_s          cn56xx;
-    struct cvmx_pcieep_cfg009_s          cn56xxp1;
-} cvmx_pcieep_cfg009_t;
-
-
-/**
- * cvmx_pcieep_cfg009_mask
- *
- * PCIE_CFG009_MASK (BAR Mask 2 - High)
- * The BAR 2 Mask register is invisible to host software and not readable from the application.
- * The BAR 2 Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg009_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umask                   : 32;      /**< Bar Mask High */
-#else
-        uint32_t umask                   : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg009_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg009_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg009_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg009_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg009_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg010
- *
- * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg010_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t cisp                    : 32;      /**< CardBus CIS Pointer
-                                                         Optional, writable through the DBI. */
-#else
-        uint32_t cisp                    : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg010_s          cn52xx;
-    struct cvmx_pcieep_cfg010_s          cn52xxp1;
-    struct cvmx_pcieep_cfg010_s          cn56xx;
-    struct cvmx_pcieep_cfg010_s          cn56xxp1;
-} cvmx_pcieep_cfg010_t;
-
-
-/**
- * cvmx_pcieep_cfg011
- *
- * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg011_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ssid                    : 16;      /**< Subsystem ID
-                                                         Assigned by PCI-SIG, writable through the DBI.                                                                                                               However, the application must not change this field. */
-        uint32_t ssvid                   : 16;      /**< Subsystem Vendor ID
-                                                         Assigned by PCI-SIG, writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t ssvid                   : 16;
-        uint32_t ssid                    : 16;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg011_s          cn52xx;
-    struct cvmx_pcieep_cfg011_s          cn52xxp1;
-    struct cvmx_pcieep_cfg011_s          cn56xx;
-    struct cvmx_pcieep_cfg011_s          cn56xxp1;
-} cvmx_pcieep_cfg011_t;
-
-
-/**
- * cvmx_pcieep_cfg012
- *
- * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg012_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t eraddr                  : 16;      /**< Expansion ROM Address */
-        uint32_t reserved_1_15           : 15;
-        uint32_t er_en                   : 1;       /**< Expansion ROM Enable */
-#else
-        uint32_t er_en                   : 1;
-        uint32_t reserved_1_15           : 15;
-        uint32_t eraddr                  : 16;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg012_s          cn52xx;
-    struct cvmx_pcieep_cfg012_s          cn52xxp1;
-    struct cvmx_pcieep_cfg012_s          cn56xx;
-    struct cvmx_pcieep_cfg012_s          cn56xxp1;
-} cvmx_pcieep_cfg012_t;
-
-
-/**
- * cvmx_pcieep_cfg012_mask
- *
- * PCIE_CFG012_MASK (Exapansion ROM BAR Mask)
- * The ROM Mask register is invisible to host software and not readable from the application.
- * The ROM Mask register is only writable through the DBI.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg012_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t mask                    : 31;      /**< Bar Mask Low */
-        uint32_t enb                     : 1;       /**< Bar Enable
-                                                         o 0: BAR ROM is disabled
-                                                         o 1: BAR ROM is enabled
-                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
-                                                         register rather than as a mask bit because bit 0 of a BAR is
-                                                         always masked from writing by host software. Bit 0 must be
-                                                         written prior to writing the other mask bits. */
-#else
-        uint32_t enb                     : 1;
-        uint32_t mask                    : 31;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg012_mask_s     cn52xx;
-    struct cvmx_pcieep_cfg012_mask_s     cn52xxp1;
-    struct cvmx_pcieep_cfg012_mask_s     cn56xx;
-    struct cvmx_pcieep_cfg012_mask_s     cn56xxp1;
-} cvmx_pcieep_cfg012_mask_t;
-
-
-/**
- * cvmx_pcieep_cfg013
- *
- * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg013_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_8_31           : 24;
-        uint32_t cp                      : 8;       /**< First Capability Pointer.
-                                                         Points to Power Management Capability structure by
-                                                         default, writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t cp                      : 8;
-        uint32_t reserved_8_31           : 24;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg013_s          cn52xx;
-    struct cvmx_pcieep_cfg013_s          cn52xxp1;
-    struct cvmx_pcieep_cfg013_s          cn56xx;
-    struct cvmx_pcieep_cfg013_s          cn56xxp1;
-} cvmx_pcieep_cfg013_t;
-
-
-/**
- * cvmx_pcieep_cfg015
- *
- * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg015_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ml                      : 8;       /**< Maximum Latency     (Hardwired to 0) */
-        uint32_t mg                      : 8;       /**< Minimum Grant       (Hardwired to 0) */
-        uint32_t inta                    : 8;       /**< Interrupt Pin
-                                                         Identifies the legacy interrupt Message that the device
-                                                         (or device function) uses.
-                                                         The Interrupt Pin register is writable through the DBI.
-                                                         In a single-function configuration, only INTA is used.
-                                                         Therefore, the application must not change this field. */
-        uint32_t il                      : 8;       /**< Interrupt Line */
-#else
-        uint32_t il                      : 8;
-        uint32_t inta                    : 8;
-        uint32_t mg                      : 8;
-        uint32_t ml                      : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg015_s          cn52xx;
-    struct cvmx_pcieep_cfg015_s          cn52xxp1;
-    struct cvmx_pcieep_cfg015_s          cn56xx;
-    struct cvmx_pcieep_cfg015_s          cn56xxp1;
-} cvmx_pcieep_cfg015_t;
-
-
-/**
- * cvmx_pcieep_cfg016
- *
- * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space
- * (Power Management Capability ID/
- * Power Management Next Item Pointer/
- * Power Management Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg016_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmes                    : 5;       /**< PME_Support
-                                                         o Bit 11: If set, PME Messages can be generated from D0
-                                                         o Bit 12: If set, PME Messages can be generated from D1
-                                                         o Bit 13: If set, PME Messages can be generated from D2
-                                                         o Bit 14: If set, PME Messages can be generated from D3hot
-                                                         o Bit 15: If set, PME Messages can be generated from D3cold
-                                                         The PME_Support field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t d2s                     : 1;       /**< D2 Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t d1s                     : 1;       /**< D1 Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t auxc                    : 3;       /**< AUX Current, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t dsi                     : 1;       /**< Device Specific Initialization (DSI), writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t pme_clock               : 1;       /**< PME Clock, hardwired to 0 */
-        uint32_t pmsv                    : 3;       /**< Power Management Specification Version, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         Points to the MSI capabilities by default, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
-#else
-        uint32_t pmcid                   : 8;
-        uint32_t ncp                     : 8;
-        uint32_t pmsv                    : 3;
-        uint32_t pme_clock               : 1;
-        uint32_t reserved_20_20          : 1;
-        uint32_t dsi                     : 1;
-        uint32_t auxc                    : 3;
-        uint32_t d1s                     : 1;
-        uint32_t d2s                     : 1;
-        uint32_t pmes                    : 5;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg016_s          cn52xx;
-    struct cvmx_pcieep_cfg016_s          cn52xxp1;
-    struct cvmx_pcieep_cfg016_s          cn56xx;
-    struct cvmx_pcieep_cfg016_s          cn56xxp1;
-} cvmx_pcieep_cfg016_t;
-
-
-/**
- * cvmx_pcieep_cfg017
- *
- * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg017_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmdia                   : 8;       /**< Data register for additional information (not supported) */
-        uint32_t bpccee                  : 1;       /**< Bus Power/Clock Control Enable, hardwired to 0 */
-        uint32_t bd3h                    : 1;       /**< B2/B3 Support, hardwired to 0 */
-        uint32_t reserved_16_21          : 6;
-        uint32_t pmess                   : 1;       /**< PME Status
-                                                         Indicates if a previously enabled PME event occurred or not. */
-        uint32_t pmedsia                 : 2;       /**< Data Scale (not supported) */
-        uint32_t pmds                    : 4;       /**< Data Select (not supported) */
-        uint32_t pmeens                  : 1;       /**< PME Enable
-                                                         A value of 1 indicates that the device is enabled to
-                                                         generate PME. */
-        uint32_t reserved_4_7            : 4;
-        uint32_t nsr                     : 1;       /**< No Soft Reset, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_2_2            : 1;
-        uint32_t ps                      : 2;       /**< Power State
-                                                         Controls the device power state:
-                                                           o 00b: D0
-                                                           o 01b: D1
-                                                           o 10b: D2
-                                                           o 11b: D3
-                                                         The written value is ignored if the specific state is
-                                                         not supported. */
-#else
-        uint32_t ps                      : 2;
-        uint32_t reserved_2_2            : 1;
-        uint32_t nsr                     : 1;
-        uint32_t reserved_4_7            : 4;
-        uint32_t pmeens                  : 1;
-        uint32_t pmds                    : 4;
-        uint32_t pmedsia                 : 2;
-        uint32_t pmess                   : 1;
-        uint32_t reserved_16_21          : 6;
-        uint32_t bd3h                    : 1;
-        uint32_t bpccee                  : 1;
-        uint32_t pmdia                   : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg017_s          cn52xx;
-    struct cvmx_pcieep_cfg017_s          cn52xxp1;
-    struct cvmx_pcieep_cfg017_s          cn56xx;
-    struct cvmx_pcieep_cfg017_s          cn56xxp1;
-} cvmx_pcieep_cfg017_t;
-
-
-/**
- * cvmx_pcieep_cfg020
- *
- * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space
- * (MSI Capability ID/
- *  MSI Next Item Pointer/
- *  MSI Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg020_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t m64                     : 1;       /**< 64-bit Address Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t mme                     : 3;       /**< Multiple Message Enabled
-                                                         Indicates that multiple Message mode is enabled by system
-                                                         software. The number of Messages enabled must be less than
-                                                         or equal to the Multiple Message Capable value. */
-        uint32_t mmc                     : 3;       /**< Multiple Message Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t msien                   : 1;       /**< MSI Enabled
-                                                         When set, INTx must be disabled. */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         Points to PCI Express Capabilities by default,
-                                                         writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t msicid                  : 8;       /**< MSI Capability ID */
-#else
-        uint32_t msicid                  : 8;
-        uint32_t ncp                     : 8;
-        uint32_t msien                   : 1;
-        uint32_t mmc                     : 3;
-        uint32_t mme                     : 3;
-        uint32_t m64                     : 1;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg020_s          cn52xx;
-    struct cvmx_pcieep_cfg020_s          cn52xxp1;
-    struct cvmx_pcieep_cfg020_s          cn56xx;
-    struct cvmx_pcieep_cfg020_s          cn56xxp1;
-} cvmx_pcieep_cfg020_t;
-
-
-/**
- * cvmx_pcieep_cfg021
- *
- * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg021_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmsi                    : 30;      /**< Lower 32-bit Address */
-        uint32_t reserved_0_1            : 2;
-#else
-        uint32_t reserved_0_1            : 2;
-        uint32_t lmsi                    : 30;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg021_s          cn52xx;
-    struct cvmx_pcieep_cfg021_s          cn52xxp1;
-    struct cvmx_pcieep_cfg021_s          cn56xx;
-    struct cvmx_pcieep_cfg021_s          cn56xxp1;
-} cvmx_pcieep_cfg021_t;
-
-
-/**
- * cvmx_pcieep_cfg022
- *
- * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg022_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umsi                    : 32;      /**< Upper 32-bit Address */
-#else
-        uint32_t umsi                    : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg022_s          cn52xx;
-    struct cvmx_pcieep_cfg022_s          cn52xxp1;
-    struct cvmx_pcieep_cfg022_s          cn56xx;
-    struct cvmx_pcieep_cfg022_s          cn56xxp1;
-} cvmx_pcieep_cfg022_t;
-
-
-/**
- * cvmx_pcieep_cfg023
- *
- * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg023_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t msimd                   : 16;      /**< MSI Data
-                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
-                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
-#else
-        uint32_t msimd                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg023_s          cn52xx;
-    struct cvmx_pcieep_cfg023_s          cn52xxp1;
-    struct cvmx_pcieep_cfg023_s          cn56xx;
-    struct cvmx_pcieep_cfg023_s          cn56xxp1;
-} cvmx_pcieep_cfg023_t;
-
-
-/**
- * cvmx_pcieep_cfg028
- *
- * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space
- * (PCI Express Capabilities List Register/
- *  PCI Express Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg028_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t imn                     : 5;       /**< Interrupt Message Number
-                                                         Updated by hardware, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t si                      : 1;       /**< Slot Implemented
-                                                         This bit is writable through the DBI. However, it must be 0 for
-                                                         an Endpoint device. Therefore, the application must not write a
-                                                         1 to this bit. */
-        uint32_t dpt                     : 4;       /**< Device Port Type */
-        uint32_t pciecv                  : 4;       /**< PCI Express Capability Version */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         Writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t pcieid                  : 8;       /**< PCIE Capability ID */
-#else
-        uint32_t pcieid                  : 8;
-        uint32_t ncp                     : 8;
-        uint32_t pciecv                  : 4;
-        uint32_t dpt                     : 4;
-        uint32_t si                      : 1;
-        uint32_t imn                     : 5;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg028_s          cn52xx;
-    struct cvmx_pcieep_cfg028_s          cn52xxp1;
-    struct cvmx_pcieep_cfg028_s          cn56xx;
-    struct cvmx_pcieep_cfg028_s          cn56xxp1;
-} cvmx_pcieep_cfg028_t;
-
-
-/**
- * cvmx_pcieep_cfg029
- *
- * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg029_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_28_31          : 4;
-        uint32_t cspls                   : 2;       /**< Captured Slot Power Limit Scale
-                                                         From Message from RC, upstream port only. */
-        uint32_t csplv                   : 8;       /**< Captured Slot Power Limit Value
-                                                         From Message from RC, upstream port only. */
-        uint32_t reserved_16_17          : 2;
-        uint32_t rber                    : 1;       /**< Role-Based Error Reporting, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_12_14          : 3;
-        uint32_t el1al                   : 3;       /**< Endpoint L1 Acceptable Latency, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t el0al                   : 3;       /**< Endpoint L0s Acceptable Latency, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t etfs                    : 1;       /**< Extended Tag Field Supported
-                                                         This bit is writable through the DBI. However, the application
-                                                         must not write a 1 to this bit. */
-        uint32_t pfs                     : 2;       /**< Phantom Function Supported
-                                                         This field is writable through the DBI. However, Phantom
-                                                         Function is not supported. Therefore, the application must not
-                                                         write any value other than 0x0 to this field. */
-        uint32_t mpss                    : 3;       /**< Max_Payload_Size Supported, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t mpss                    : 3;
-        uint32_t pfs                     : 2;
-        uint32_t etfs                    : 1;
-        uint32_t el0al                   : 3;
-        uint32_t el1al                   : 3;
-        uint32_t reserved_12_14          : 3;
-        uint32_t rber                    : 1;
-        uint32_t reserved_16_17          : 2;
-        uint32_t csplv                   : 8;
-        uint32_t cspls                   : 2;
-        uint32_t reserved_28_31          : 4;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg029_s          cn52xx;
-    struct cvmx_pcieep_cfg029_s          cn52xxp1;
-    struct cvmx_pcieep_cfg029_s          cn56xx;
-    struct cvmx_pcieep_cfg029_s          cn56xxp1;
-} cvmx_pcieep_cfg029_t;
-
-
-/**
- * cvmx_pcieep_cfg030
- *
- * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space
- * (Device Control Register/Device Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg030_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_22_31          : 10;
-        uint32_t tp                      : 1;       /**< Transaction Pending
-                                                         Set to 1 when Non-Posted Requests are not yet completed
-                                                         and clear when they are completed. */
-        uint32_t ap_d                    : 1;       /**< Aux Power Detected
-                                                         Set to 1 if Aux power detected. */
-        uint32_t ur_d                    : 1;       /**< Unsupported Request Detected
-                                                          Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         UR_D occurs when we receive something we don't support.
-                                                         Unsupported requests are Nonfatal errors, so UR_D should
-                                                         cause NFE_D.  Receiving a  vendor defined message should
-                                                         cause an unsupported request. */
-        uint32_t fe_d                    : 1;       /**< Fatal Error Detected
-                                                          Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
-                                                         has a severity set to Fatal.  Malformed TLP's generally fit
-                                                         into this category. */
-        uint32_t nfe_d                   : 1;       /**< Non-Fatal Error detected
-                                                          Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
-                                                         that has a severity set to Nonfatal and does NOT meet Advisory
-                                                         Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
-                                                         most poisoned TLP's should be. */
-        uint32_t ce_d                    : 1;       /**< Correctable Error Detected
-                                                          Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
-                                                         for example a Replay Timer Timeout.  Also, it can be set if
-                                                         we get any of the errors in PCIE_CFG066 that has a severity
-                                                         set to Nonfatal and meets the Advisory Nonfatal criteria
-                                                         (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
-                                                         should be. */
-        uint32_t reserved_15_15          : 1;
-        uint32_t mrrs                    : 3;       /**< Max Read Request Size
-                                                          0 = 128B
-                                                          1 = 256B
-                                                          2 = 512B
-                                                          3 = 1024B
-                                                          4 = 2048B
-                                                          5 = 4096B
-                                                         Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
-                                                         NPEI_CTL_STATUS2[MRRS] must not exceed the
-                                                         desired max read request size. */
-        uint32_t ns_en                   : 1;       /**< Enable No Snoop */
-        uint32_t ap_en                   : 1;       /**< AUX Power PM Enable */
-        uint32_t pf_en                   : 1;       /**< Phantom Function Enable
-                                                         This bit should never be set - OCTEON requests never use
-                                                         phantom functions. */
-        uint32_t etf_en                  : 1;       /**< Extended Tag Field Enable
-                                                         This bit should never be set - OCTEON requests never use
-                                                         extended tags. */
-        uint32_t mps                     : 3;       /**< Max Payload Size
-                                                          Legal values:
-                                                           0  = 128B
-                                                           1  = 256B
-                                                          Larger sizes not supported by OCTEON.
-                                                         Note: NPEI_CTL_STATUS2[MPS] must be set to the same
-                                                               value for proper functionality. */
-        uint32_t ro_en                   : 1;       /**< Enable Relaxed Ordering */
-        uint32_t ur_en                   : 1;       /**< Unsupported Request Reporting Enable */
-        uint32_t fe_en                   : 1;       /**< Fatal Error Reporting Enable */
-        uint32_t nfe_en                  : 1;       /**< Non-Fatal Error Reporting Enable */
-        uint32_t ce_en                   : 1;       /**< Correctable Error Reporting Enable */
-#else
-        uint32_t ce_en                   : 1;
-        uint32_t nfe_en                  : 1;
-        uint32_t fe_en                   : 1;
-        uint32_t ur_en                   : 1;
-        uint32_t ro_en                   : 1;
-        uint32_t mps                     : 3;
-        uint32_t etf_en                  : 1;
-        uint32_t pf_en                   : 1;
-        uint32_t ap_en                   : 1;
-        uint32_t ns_en                   : 1;
-        uint32_t mrrs                    : 3;
-        uint32_t reserved_15_15          : 1;
-        uint32_t ce_d                    : 1;
-        uint32_t nfe_d                   : 1;
-        uint32_t fe_d                    : 1;
-        uint32_t ur_d                    : 1;
-        uint32_t ap_d                    : 1;
-        uint32_t tp                      : 1;
-        uint32_t reserved_22_31          : 10;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg030_s          cn52xx;
-    struct cvmx_pcieep_cfg030_s          cn52xxp1;
-    struct cvmx_pcieep_cfg030_s          cn56xx;
-    struct cvmx_pcieep_cfg030_s          cn56xxp1;
-} cvmx_pcieep_cfg030_t;
-
-
-/**
- * cvmx_pcieep_cfg031
- *
- * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space
- * (Link Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg031_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pnum                    : 8;       /**< Port Number, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_22_23          : 2;
-        uint32_t lbnc                    : 1;       /**< Link Bandwith Notification Capability */
-        uint32_t dllarc                  : 1;       /**< Data Link Layer Active Reporting Capable */
-        uint32_t sderc                   : 1;       /**< Surprise Down Error Reporting Capable
-                                                         Not supported, hardwired to 0x0. */
-        uint32_t cpm                     : 1;       /**< Clock Power Management
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t l1el                    : 3;       /**< L1 Exit Latency
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t l0el                    : 3;       /**< L0s Exit Latency
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t aslpms                  : 2;       /**< Active State Link PM Support
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t mlw                     : 6;       /**< Maximum Link Width
-                                                         The default value is the value you specify during hardware
-                                                         configuration (x1, x4, x8, or x16), writable through the DBI. */
-        uint32_t mls                     : 4;       /**< Maximum Link Speed
-                                                         Default value is 0x1 for 2.5 Gbps Link.
-                                                         This field is writable through the DBI. However, 0x1 is the
-                                                         only supported value. Therefore, the application must not write
-                                                         any value other than 0x1 to this field. */
-#else
-        uint32_t mls                     : 4;
-        uint32_t mlw                     : 6;
-        uint32_t aslpms                  : 2;
-        uint32_t l0el                    : 3;
-        uint32_t l1el                    : 3;
-        uint32_t cpm                     : 1;
-        uint32_t sderc                   : 1;
-        uint32_t dllarc                  : 1;
-        uint32_t lbnc                    : 1;
-        uint32_t reserved_22_23          : 2;
-        uint32_t pnum                    : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg031_s          cn52xx;
-    struct cvmx_pcieep_cfg031_s          cn52xxp1;
-    struct cvmx_pcieep_cfg031_s          cn56xx;
-    struct cvmx_pcieep_cfg031_s          cn56xxp1;
-} cvmx_pcieep_cfg031_t;
-
-
-/**
- * cvmx_pcieep_cfg032
- *
- * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space
- * (Link Control Register/Link Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg032_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t dlla                    : 1;       /**< Data Link Layer Active
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t scc                     : 1;       /**< Slot Clock Configuration
-                                                         Indicates that the component uses the same physical reference
-                                                         clock that the platform provides on the connector.
-                                                         Writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t lt                      : 1;       /**< Link Training
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t reserved_26_26          : 1;
-        uint32_t nlw                     : 6;       /**< Negotiated Link Width
-                                                         Set automatically by hardware after Link initialization. */
-        uint32_t ls                      : 4;       /**< Link Speed
-                                                         The negotiated Link speed: 2.5 Gbps */
-        uint32_t reserved_10_15          : 6;
-        uint32_t hawd                    : 1;       /**< Hardware Autonomous Width Disable
-                                                         (Not Supported) */
-        uint32_t ecpm                    : 1;       /**< Enable Clock Power Management
-                                                         Hardwired to 0 if Clock Power Management is disabled in
-                                                         the Link Capabilities register. */
-        uint32_t es                      : 1;       /**< Extended Synch */
-        uint32_t ccc                     : 1;       /**< Common Clock Configuration */
-        uint32_t rl                      : 1;       /**< Retrain Link
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t ld                      : 1;       /**< Link Disable
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t rcb                     : 1;       /**< Read Completion Boundary (RCB) */
-        uint32_t reserved_2_2            : 1;
-        uint32_t aslpc                   : 2;       /**< Active State Link PM Control */
-#else
-        uint32_t aslpc                   : 2;
-        uint32_t reserved_2_2            : 1;
-        uint32_t rcb                     : 1;
-        uint32_t ld                      : 1;
-        uint32_t rl                      : 1;
-        uint32_t ccc                     : 1;
-        uint32_t es                      : 1;
-        uint32_t ecpm                    : 1;
-        uint32_t hawd                    : 1;
-        uint32_t reserved_10_15          : 6;
-        uint32_t ls                      : 4;
-        uint32_t nlw                     : 6;
-        uint32_t reserved_26_26          : 1;
-        uint32_t lt                      : 1;
-        uint32_t scc                     : 1;
-        uint32_t dlla                    : 1;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg032_s          cn52xx;
-    struct cvmx_pcieep_cfg032_s          cn52xxp1;
-    struct cvmx_pcieep_cfg032_s          cn56xx;
-    struct cvmx_pcieep_cfg032_s          cn56xxp1;
-} cvmx_pcieep_cfg032_t;
-
-
-/**
- * cvmx_pcieep_cfg033
- *
- * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space
- * (Slot Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg033_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ps_num                  : 13;      /**< Physical Slot Number, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t nccs                    : 1;       /**< No Command Complete Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t emip                    : 1;       /**< Electromechanical Interlock Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t sp_ls                   : 2;       /**< Slot Power Limit Scale, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t sp_lv                   : 8;       /**< Slot Power Limit Value, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t hp_c                    : 1;       /**< Hot-Plug Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t hp_s                    : 1;       /**< Hot-Plug Surprise, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pip                     : 1;       /**< Power Indicator Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t aip                     : 1;       /**< Attention Indicator Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t mrlsp                   : 1;       /**< MRL Sensor Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pcp                     : 1;       /**< Power Controller Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t abp                     : 1;       /**< Attention Button Present, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t abp                     : 1;
-        uint32_t pcp                     : 1;
-        uint32_t mrlsp                   : 1;
-        uint32_t aip                     : 1;
-        uint32_t pip                     : 1;
-        uint32_t hp_s                    : 1;
-        uint32_t hp_c                    : 1;
-        uint32_t sp_lv                   : 8;
-        uint32_t sp_ls                   : 2;
-        uint32_t emip                    : 1;
-        uint32_t nccs                    : 1;
-        uint32_t ps_num                  : 13;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg033_s          cn52xx;
-    struct cvmx_pcieep_cfg033_s          cn52xxp1;
-    struct cvmx_pcieep_cfg033_s          cn56xx;
-    struct cvmx_pcieep_cfg033_s          cn56xxp1;
-} cvmx_pcieep_cfg033_t;
-
-
-/**
- * cvmx_pcieep_cfg034
- *
- * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space
- * (Slot Control Register/Slot Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg034_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_25_31          : 7;
-        uint32_t dlls_c                  : 1;       /**< Data Link Layer State Changed
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t emis                    : 1;       /**< Electromechanical Interlock Status */
-        uint32_t pds                     : 1;       /**< Presence Detect State */
-        uint32_t mrlss                   : 1;       /**< MRL Sensor State */
-        uint32_t ccint_d                 : 1;       /**< Command Completed */
-        uint32_t pd_c                    : 1;       /**< Presence Detect Changed */
-        uint32_t mrls_c                  : 1;       /**< MRL Sensor Changed */
-        uint32_t pf_d                    : 1;       /**< Power Fault Detected */
-        uint32_t abp_d                   : 1;       /**< Attention Button Pressed */
-        uint32_t reserved_13_15          : 3;
-        uint32_t dlls_en                 : 1;       /**< Data Link Layer State Changed Enable
-                                                         Not applicable for an upstream Port or Endpoint device,
-                                                         hardwired to 0. */
-        uint32_t emic                    : 1;       /**< Electromechanical Interlock Control */
-        uint32_t pcc                     : 1;       /**< Power Controller Control */
-        uint32_t pic                     : 2;       /**< Power Indicator Control */
-        uint32_t aic                     : 2;       /**< Attention Indicator Control */
-        uint32_t hpint_en                : 1;       /**< Hot-Plug Interrupt Enable */
-        uint32_t ccint_en                : 1;       /**< Command Completed Interrupt Enable */
-        uint32_t pd_en                   : 1;       /**< Presence Detect Changed Enable */
-        uint32_t mrls_en                 : 1;       /**< MRL Sensor Changed Enable */
-        uint32_t pf_en                   : 1;       /**< Power Fault Detected Enable */
-        uint32_t abp_en                  : 1;       /**< Attention Button Pressed Enable */
-#else
-        uint32_t abp_en                  : 1;
-        uint32_t pf_en                   : 1;
-        uint32_t mrls_en                 : 1;
-        uint32_t pd_en                   : 1;
-        uint32_t ccint_en                : 1;
-        uint32_t hpint_en                : 1;
-        uint32_t aic                     : 2;
-        uint32_t pic                     : 2;
-        uint32_t pcc                     : 1;
-        uint32_t emic                    : 1;
-        uint32_t dlls_en                 : 1;
-        uint32_t reserved_13_15          : 3;
-        uint32_t abp_d                   : 1;
-        uint32_t pf_d                    : 1;
-        uint32_t mrls_c                  : 1;
-        uint32_t pd_c                    : 1;
-        uint32_t ccint_d                 : 1;
-        uint32_t mrlss                   : 1;
-        uint32_t pds                     : 1;
-        uint32_t emis                    : 1;
-        uint32_t dlls_c                  : 1;
-        uint32_t reserved_25_31          : 7;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg034_s          cn52xx;
-    struct cvmx_pcieep_cfg034_s          cn52xxp1;
-    struct cvmx_pcieep_cfg034_s          cn56xx;
-    struct cvmx_pcieep_cfg034_s          cn56xxp1;
-} cvmx_pcieep_cfg034_t;
-
-
-/**
- * cvmx_pcieep_cfg037
- *
- * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space
- * (Device Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg037_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t ctds                    : 1;       /**< Completion Timeout Disable Supported */
-        uint32_t ctrs                    : 4;       /**< Completion Timeout Ranges Supported
-                                                         Value of 0 indicates that Completion Timeout Programming
-                                                         is not supported
-                                                         Completion timeout is 16.7ms. */
-#else
-        uint32_t ctrs                    : 4;
-        uint32_t ctds                    : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg037_s          cn52xx;
-    struct cvmx_pcieep_cfg037_s          cn52xxp1;
-    struct cvmx_pcieep_cfg037_s          cn56xx;
-    struct cvmx_pcieep_cfg037_s          cn56xxp1;
-} cvmx_pcieep_cfg037_t;
-
-
-/**
- * cvmx_pcieep_cfg038
- *
- * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space
- * (Device Control 2 Register/Device Status 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg038_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t ctd                     : 1;       /**< Completion Timeout Disable */
-        uint32_t ctv                     : 4;       /**< Completion Timeout Value
-                                                         Completion Timeout Programming is not supported
-                                                         Completion timeout is 16.7ms. */
-#else
-        uint32_t ctv                     : 4;
-        uint32_t ctd                     : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg038_s          cn52xx;
-    struct cvmx_pcieep_cfg038_s          cn52xxp1;
-    struct cvmx_pcieep_cfg038_s          cn56xx;
-    struct cvmx_pcieep_cfg038_s          cn56xxp1;
-} cvmx_pcieep_cfg038_t;
-
-
-/**
- * cvmx_pcieep_cfg039
- *
- * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space
- * (Link Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg039_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg039_s          cn52xx;
-    struct cvmx_pcieep_cfg039_s          cn52xxp1;
-    struct cvmx_pcieep_cfg039_s          cn56xx;
-    struct cvmx_pcieep_cfg039_s          cn56xxp1;
-} cvmx_pcieep_cfg039_t;
-
-
-/**
- * cvmx_pcieep_cfg040
- *
- * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space
- * (Link Control 2 Register/Link Status 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg040_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg040_s          cn52xx;
-    struct cvmx_pcieep_cfg040_s          cn52xxp1;
-    struct cvmx_pcieep_cfg040_s          cn56xx;
-    struct cvmx_pcieep_cfg040_s          cn56xxp1;
-} cvmx_pcieep_cfg040_t;
-
-
-/**
- * cvmx_pcieep_cfg041
- *
- * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space
- * (Slot Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg041_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg041_s          cn52xx;
-    struct cvmx_pcieep_cfg041_s          cn52xxp1;
-    struct cvmx_pcieep_cfg041_s          cn56xx;
-    struct cvmx_pcieep_cfg041_s          cn56xxp1;
-} cvmx_pcieep_cfg041_t;
-
-
-/**
- * cvmx_pcieep_cfg042
- *
- * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space
- * (Slot Control 2 Register/Slot Status 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg042_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg042_s          cn52xx;
-    struct cvmx_pcieep_cfg042_s          cn52xxp1;
-    struct cvmx_pcieep_cfg042_s          cn56xx;
-    struct cvmx_pcieep_cfg042_s          cn56xxp1;
-} cvmx_pcieep_cfg042_t;
-
-
-/**
- * cvmx_pcieep_cfg064
- *
- * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space
- * (PCI Express Enhanced Capability Header)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg064_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t nco                     : 12;      /**< Next Capability Offset */
-        uint32_t cv                      : 4;       /**< Capability Version */
-        uint32_t pcieec                  : 16;      /**< PCIE Express Extended Capability */
-#else
-        uint32_t pcieec                  : 16;
-        uint32_t cv                      : 4;
-        uint32_t nco                     : 12;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg064_s          cn52xx;
-    struct cvmx_pcieep_cfg064_s          cn52xxp1;
-    struct cvmx_pcieep_cfg064_s          cn56xx;
-    struct cvmx_pcieep_cfg064_s          cn56xxp1;
-} cvmx_pcieep_cfg064_t;
-
-
-/**
- * cvmx_pcieep_cfg065
- *
- * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space
- * (Uncorrectable Error Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg065_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t ures                    : 1;       /**< Unsupported Request Error Status */
-        uint32_t ecrces                  : 1;       /**< ECRC Error Status */
-        uint32_t mtlps                   : 1;       /**< Malformed TLP Status */
-        uint32_t ros                     : 1;       /**< Receiver Overflow Status */
-        uint32_t ucs                     : 1;       /**< Unexpected Completion Status */
-        uint32_t cas                     : 1;       /**< Completer Abort Status */
-        uint32_t cts                     : 1;       /**< Completion Timeout Status */
-        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Status */
-        uint32_t ptlps                   : 1;       /**< Poisoned TLP Status */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdes                    : 1;       /**< Surprise Down Error Status (not supported) */
-        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Status */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpes                   : 1;
-        uint32_t sdes                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlps                   : 1;
-        uint32_t fcpes                   : 1;
-        uint32_t cts                     : 1;
-        uint32_t cas                     : 1;
-        uint32_t ucs                     : 1;
-        uint32_t ros                     : 1;
-        uint32_t mtlps                   : 1;
-        uint32_t ecrces                  : 1;
-        uint32_t ures                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg065_s          cn52xx;
-    struct cvmx_pcieep_cfg065_s          cn52xxp1;
-    struct cvmx_pcieep_cfg065_s          cn56xx;
-    struct cvmx_pcieep_cfg065_s          cn56xxp1;
-} cvmx_pcieep_cfg065_t;
-
-
-/**
- * cvmx_pcieep_cfg066
- *
- * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space
- * (Uncorrectable Error Mask Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg066_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t urem                    : 1;       /**< Unsupported Request Error Mask */
-        uint32_t ecrcem                  : 1;       /**< ECRC Error Mask */
-        uint32_t mtlpm                   : 1;       /**< Malformed TLP Mask */
-        uint32_t rom                     : 1;       /**< Receiver Overflow Mask */
-        uint32_t ucm                     : 1;       /**< Unexpected Completion Mask */
-        uint32_t cam                     : 1;       /**< Completer Abort Mask */
-        uint32_t ctm                     : 1;       /**< Completion Timeout Mask */
-        uint32_t fcpem                   : 1;       /**< Flow Control Protocol Error Mask */
-        uint32_t ptlpm                   : 1;       /**< Poisoned TLP Mask */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdem                    : 1;       /**< Surprise Down Error Mask (not supported) */
-        uint32_t dlpem                   : 1;       /**< Data Link Protocol Error Mask */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpem                   : 1;
-        uint32_t sdem                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlpm                   : 1;
-        uint32_t fcpem                   : 1;
-        uint32_t ctm                     : 1;
-        uint32_t cam                     : 1;
-        uint32_t ucm                     : 1;
-        uint32_t rom                     : 1;
-        uint32_t mtlpm                   : 1;
-        uint32_t ecrcem                  : 1;
-        uint32_t urem                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg066_s          cn52xx;
-    struct cvmx_pcieep_cfg066_s          cn52xxp1;
-    struct cvmx_pcieep_cfg066_s          cn56xx;
-    struct cvmx_pcieep_cfg066_s          cn56xxp1;
-} cvmx_pcieep_cfg066_t;
-
-
-/**
- * cvmx_pcieep_cfg067
- *
- * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space
- * (Uncorrectable Error Severity Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg067_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t ures                    : 1;       /**< Unsupported Request Error Severity */
-        uint32_t ecrces                  : 1;       /**< ECRC Error Severity */
-        uint32_t mtlps                   : 1;       /**< Malformed TLP Severity */
-        uint32_t ros                     : 1;       /**< Receiver Overflow Severity */
-        uint32_t ucs                     : 1;       /**< Unexpected Completion Severity */
-        uint32_t cas                     : 1;       /**< Completer Abort Severity */
-        uint32_t cts                     : 1;       /**< Completion Timeout Severity */
-        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Severity */
-        uint32_t ptlps                   : 1;       /**< Poisoned TLP Severity */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdes                    : 1;       /**< Surprise Down Error Severity (not supported) */
-        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Severity */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpes                   : 1;
-        uint32_t sdes                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlps                   : 1;
-        uint32_t fcpes                   : 1;
-        uint32_t cts                     : 1;
-        uint32_t cas                     : 1;
-        uint32_t ucs                     : 1;
-        uint32_t ros                     : 1;
-        uint32_t mtlps                   : 1;
-        uint32_t ecrces                  : 1;
-        uint32_t ures                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg067_s          cn52xx;
-    struct cvmx_pcieep_cfg067_s          cn52xxp1;
-    struct cvmx_pcieep_cfg067_s          cn56xx;
-    struct cvmx_pcieep_cfg067_s          cn56xxp1;
-} cvmx_pcieep_cfg067_t;
-
-
-/**
- * cvmx_pcieep_cfg068
- *
- * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space
- * (Correctable Error Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg068_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_14_31          : 18;
-        uint32_t anfes                   : 1;       /**< Advisory Non-Fatal Error Status */
-        uint32_t rtts                    : 1;       /**< Reply Timer Timeout Status */
-        uint32_t reserved_9_11           : 3;
-        uint32_t rnrs                    : 1;       /**< REPLAY_NUM Rollover Status */
-        uint32_t bdllps                  : 1;       /**< Bad DLLP Status */
-        uint32_t btlps                   : 1;       /**< Bad TLP Status */
-        uint32_t reserved_1_5            : 5;
-        uint32_t res                     : 1;       /**< Receiver Error Status */
-#else
-        uint32_t res                     : 1;
-        uint32_t reserved_1_5            : 5;
-        uint32_t btlps                   : 1;
-        uint32_t bdllps                  : 1;
-        uint32_t rnrs                    : 1;
-        uint32_t reserved_9_11           : 3;
-        uint32_t rtts                    : 1;
-        uint32_t anfes                   : 1;
-        uint32_t reserved_14_31          : 18;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg068_s          cn52xx;
-    struct cvmx_pcieep_cfg068_s          cn52xxp1;
-    struct cvmx_pcieep_cfg068_s          cn56xx;
-    struct cvmx_pcieep_cfg068_s          cn56xxp1;
-} cvmx_pcieep_cfg068_t;
-
-
-/**
- * cvmx_pcieep_cfg069
- *
- * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space
- * (Correctable Error Mask Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg069_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_14_31          : 18;
-        uint32_t anfem                   : 1;       /**< Advisory Non-Fatal Error Mask */
-        uint32_t rttm                    : 1;       /**< Reply Timer Timeout Mask */
-        uint32_t reserved_9_11           : 3;
-        uint32_t rnrm                    : 1;       /**< REPLAY_NUM Rollover Mask */
-        uint32_t bdllpm                  : 1;       /**< Bad DLLP Mask */
-        uint32_t btlpm                   : 1;       /**< Bad TLP Mask */
-        uint32_t reserved_1_5            : 5;
-        uint32_t rem                     : 1;       /**< Receiver Error Mask */
-#else
-        uint32_t rem                     : 1;
-        uint32_t reserved_1_5            : 5;
-        uint32_t btlpm                   : 1;
-        uint32_t bdllpm                  : 1;
-        uint32_t rnrm                    : 1;
-        uint32_t reserved_9_11           : 3;
-        uint32_t rttm                    : 1;
-        uint32_t anfem                   : 1;
-        uint32_t reserved_14_31          : 18;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg069_s          cn52xx;
-    struct cvmx_pcieep_cfg069_s          cn52xxp1;
-    struct cvmx_pcieep_cfg069_s          cn56xx;
-    struct cvmx_pcieep_cfg069_s          cn56xxp1;
-} cvmx_pcieep_cfg069_t;
-
-
-/**
- * cvmx_pcieep_cfg070
- *
- * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space
- * (Advanced Error Capabilities and Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg070_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t ce                      : 1;       /**< ECRC Check Enable */
-        uint32_t cc                      : 1;       /**< ECRC Check Capable */
-        uint32_t ge                      : 1;       /**< ECRC Generation Enable */
-        uint32_t gc                      : 1;       /**< ECRC Generation Capability */
-        uint32_t fep                     : 5;       /**< First Error Pointer */
-#else
-        uint32_t fep                     : 5;
-        uint32_t gc                      : 1;
-        uint32_t ge                      : 1;
-        uint32_t cc                      : 1;
-        uint32_t ce                      : 1;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg070_s          cn52xx;
-    struct cvmx_pcieep_cfg070_s          cn52xxp1;
-    struct cvmx_pcieep_cfg070_s          cn56xx;
-    struct cvmx_pcieep_cfg070_s          cn56xxp1;
-} cvmx_pcieep_cfg070_t;
-
-
-/**
- * cvmx_pcieep_cfg071
- *
- * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space
- * (Header Log Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg071_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword1                  : 32;      /**< Header Log Register (first DWORD) */
-#else
-        uint32_t dword1                  : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg071_s          cn52xx;
-    struct cvmx_pcieep_cfg071_s          cn52xxp1;
-    struct cvmx_pcieep_cfg071_s          cn56xx;
-    struct cvmx_pcieep_cfg071_s          cn56xxp1;
-} cvmx_pcieep_cfg071_t;
-
-
-/**
- * cvmx_pcieep_cfg072
- *
- * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space
- * (Header Log Register 2)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg072_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword2                  : 32;      /**< Header Log Register (second DWORD) */
-#else
-        uint32_t dword2                  : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg072_s          cn52xx;
-    struct cvmx_pcieep_cfg072_s          cn52xxp1;
-    struct cvmx_pcieep_cfg072_s          cn56xx;
-    struct cvmx_pcieep_cfg072_s          cn56xxp1;
-} cvmx_pcieep_cfg072_t;
-
-
-/**
- * cvmx_pcieep_cfg073
- *
- * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space
- * (Header Log Register 3)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg073_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword3                  : 32;      /**< Header Log Register (third DWORD) */
-#else
-        uint32_t dword3                  : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg073_s          cn52xx;
-    struct cvmx_pcieep_cfg073_s          cn52xxp1;
-    struct cvmx_pcieep_cfg073_s          cn56xx;
-    struct cvmx_pcieep_cfg073_s          cn56xxp1;
-} cvmx_pcieep_cfg073_t;
-
-
-/**
- * cvmx_pcieep_cfg074
- *
- * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space
- * (Header Log Register 4)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg074_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword4                  : 32;      /**< Header Log Register (fourth DWORD) */
-#else
-        uint32_t dword4                  : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg074_s          cn52xx;
-    struct cvmx_pcieep_cfg074_s          cn52xxp1;
-    struct cvmx_pcieep_cfg074_s          cn56xx;
-    struct cvmx_pcieep_cfg074_s          cn56xxp1;
-} cvmx_pcieep_cfg074_t;
-
-
-/**
- * cvmx_pcieep_cfg448
- *
- * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space
- * (Ack Latency Timer and Replay Timer Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg448_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t rtl                     : 16;      /**< Replay Time Limit
-                                                         The replay timer expires when it reaches this limit. The PCI
-                                                         Express bus initiates a replay upon reception of a Nak or when
-                                                         the replay timer expires.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
-        uint32_t rtltl                   : 16;      /**< Round Trip Latency Time Limit
-                                                         The Ack/Nak latency timer expires when it reaches this limit.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
-#else
-        uint32_t rtltl                   : 16;
-        uint32_t rtl                     : 16;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg448_s          cn52xx;
-    struct cvmx_pcieep_cfg448_s          cn52xxp1;
-    struct cvmx_pcieep_cfg448_s          cn56xx;
-    struct cvmx_pcieep_cfg448_s          cn56xxp1;
-} cvmx_pcieep_cfg448_t;
-
-
-/**
- * cvmx_pcieep_cfg449
- *
- * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space
- * (Other Message Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg449_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t omr                     : 32;      /**< Other Message Register
-                                                         This register can be used for either of the following purposes:
-                                                         o To send a specific PCI Express Message, the application
-                                                           writes the payload of the Message into this register, then
-                                                           sets bit 0 of the Port Link Control Register to send the
-                                                           Message.
-                                                         o To store a corruption pattern for corrupting the LCRC on all
-                                                           TLPs, the application places a 32-bit corruption pattern into
-                                                           this register and enables this function by setting bit 25 of
-                                                           the Port Link Control Register. When enabled, the transmit
-                                                           LCRC result is XOR'd with this pattern before inserting
-                                                           it into the packet. */
-#else
-        uint32_t omr                     : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg449_s          cn52xx;
-    struct cvmx_pcieep_cfg449_s          cn52xxp1;
-    struct cvmx_pcieep_cfg449_s          cn56xx;
-    struct cvmx_pcieep_cfg449_s          cn56xxp1;
-} cvmx_pcieep_cfg449_t;
-
-
-/**
- * cvmx_pcieep_cfg450
- *
- * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space
- * (Port Force Link Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg450_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lpec                    : 8;       /**< Low Power Entrance Count
-                                                         The Power Management state will wait for this many clock cycles
-                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
-                                                         Power State (PS) field register to go low-power. This register
-                                                         is intended for applications that do not let the PCI Express
-                                                         bus handle a completion for configuration request to the
-                                                         Power Management Control and Status (PCIE_CFG017) register. */
-        uint32_t reserved_22_23          : 2;
-        uint32_t link_state              : 6;       /**< Link State
-                                                         The Link state that the PCI Express Bus will be forced to
-                                                         when bit 15 (Force Link) is set.
-                                                         State encoding:
-                                                         o DETECT_QUIET              00h
-                                                         o DETECT_ACT                01h
-                                                         o POLL_ACTIVE               02h
-                                                         o POLL_COMPLIANCE           03h
-                                                         o POLL_CONFIG               04h
-                                                         o PRE_DETECT_QUIET          05h
-                                                         o DETECT_WAIT               06h
-                                                         o CFG_LINKWD_START          07h
-                                                         o CFG_LINKWD_ACEPT          08h
-                                                         o CFG_LANENUM_WAIT          09h
-                                                         o CFG_LANENUM_ACEPT         0Ah
-                                                         o CFG_COMPLETE              0Bh
-                                                         o CFG_IDLE                  0Ch
-                                                         o RCVRY_LOCK                0Dh
-                                                         o RCVRY_SPEED               0Eh
-                                                         o RCVRY_RCVRCFG             0Fh
-                                                         o RCVRY_IDLE                10h
-                                                         o L0                        11h
-                                                         o L0S                       12h
-                                                         o L123_SEND_EIDLE           13h
-                                                         o L1_IDLE                   14h
-                                                         o L2_IDLE                   15h
-                                                         o L2_WAKE                   16h
-                                                         o DISABLED_ENTRY            17h
-                                                         o DISABLED_IDLE             18h
-                                                         o DISABLED                  19h
-                                                         o LPBK_ENTRY                1Ah
-                                                         o LPBK_ACTIVE               1Bh
-                                                         o LPBK_EXIT                 1Ch
-                                                         o LPBK_EXIT_TIMEOUT         1Dh
-                                                         o HOT_RESET_ENTRY           1Eh
-                                                         o HOT_RESET                 1Fh */
-        uint32_t force_link              : 1;       /**< Force Link
-                                                         Forces the Link to the state specified by the Link State field.
-                                                         The Force Link pulse will trigger Link re-negotiation.
-                                                         * As the The Force Link is a pulse, writing a 1 to it does
-                                                           trigger the forced link state event, even thought reading it
-                                                           always returns a 0. */
-        uint32_t reserved_8_14           : 7;
-        uint32_t link_num                : 8;       /**< Link Number
-                                                         Not used for Endpoint */
-#else
-        uint32_t link_num                : 8;
-        uint32_t reserved_8_14           : 7;
-        uint32_t force_link              : 1;
-        uint32_t link_state              : 6;
-        uint32_t reserved_22_23          : 2;
-        uint32_t lpec                    : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg450_s          cn52xx;
-    struct cvmx_pcieep_cfg450_s          cn52xxp1;
-    struct cvmx_pcieep_cfg450_s          cn56xx;
-    struct cvmx_pcieep_cfg450_s          cn56xxp1;
-} cvmx_pcieep_cfg450_t;
-
-
-/**
- * cvmx_pcieep_cfg451
- *
- * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space
- * (Ack Frequency Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg451_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t l1el                    : 3;       /**< L1 Entrance Latency
-                                                         Values correspond to:
-                                                         o 000: 1 ms
-                                                         o 001: 2 ms
-                                                         o 010: 4 ms
-                                                         o 011: 8 ms
-                                                         o 100: 16 ms
-                                                         o 101: 32 ms
-                                                         o 110 or 111: 64 ms */
-        uint32_t l0el                    : 3;       /**< L0s Entrance Latency
-                                                         Values correspond to:
-                                                         o 000: 1 ms
-                                                         o 001: 2 ms
-                                                         o 010: 3 ms
-                                                         o 011: 4 ms
-                                                         o 100: 5 ms
-                                                         o 101: 6 ms
-                                                         o 110 or 111: 7 ms */
-        uint32_t n_fts_cc                : 8;       /**< N_FTS when common clock is used.
-                                                         The number of Fast Training Sequence ordered sets to be
-                                                         transmitted when transitioning from L0s to L0. The maximum
-                                                         number of FTS ordered-sets that a component can request is 255.
-                                                          Note: A value of zero is not supported; a value of
-                                                                zero can cause the LTSSM to go into the recovery state
-                                                                when exiting from L0s. */
-        uint32_t n_fts                   : 8;       /**< N_FTS
-                                                         The number of Fast Training Sequence ordered sets to be
-                                                         transmitted when transitioning from L0s to L0. The maximum
-                                                         number of FTS ordered-sets that a component can request is 255.
-                                                         Note: A value of zero is not supported; a value of
-                                                               zero can cause the LTSSM to go into the recovery state
-                                                               when exiting from L0s. */
-        uint32_t ack_freq                : 8;       /**< Ack Frequency
-                                                         The number of pending Ack's specified here (up to 255) before
-                                                         sending an Ack. */
-#else
-        uint32_t ack_freq                : 8;
-        uint32_t n_fts                   : 8;
-        uint32_t n_fts_cc                : 8;
-        uint32_t l0el                    : 3;
-        uint32_t l1el                    : 3;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg451_s          cn52xx;
-    struct cvmx_pcieep_cfg451_s          cn52xxp1;
-    struct cvmx_pcieep_cfg451_s          cn56xx;
-    struct cvmx_pcieep_cfg451_s          cn56xxp1;
-} cvmx_pcieep_cfg451_t;
-
-
-/**
- * cvmx_pcieep_cfg452
- *
- * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space
- * (Port Link Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg452_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t eccrc                   : 1;       /**< Enable Corrupted CRC
-                                                         Causes corrupt LCRC for TLPs when set,
-                                                         using the pattern contained in the Other Message register.
-                                                         This is a test feature, not to be used in normal operation. */
-        uint32_t reserved_22_24          : 3;
-        uint32_t lme                     : 6;       /**< Link Mode Enable
-                                                         o 000001: x1
-                                                         o 000011: x2
-                                                         o 000111: x4
-                                                         o 001111: x8
-                                                         o 011111: x16 (not supported)
-                                                         o 111111: x32 (not supported)
-                                                         This field indicates the MAXIMUM number of lanes supported
-                                                         by the PCIe port. It is set to 0xF or 0x7 depending
-                                                         on the value of the QLM_CFG bits (0xF when QLM_CFG == 0
-                                                         otherwise 0x7). The value can be set less than 0xF or 0x7
-                                                         to limit the number of lanes the PCIe will attempt to use.
-                                                         If the value of 0xF or 0x7 set by the HW is not desired,
-                                                         this field can be programmed to a smaller value (i.e. EEPROM)
-                                                         See also MLW.
-                                                         (Note: The value of this field does NOT indicate the number
-                                                          of lanes in use by the PCIe. LME sets the max number of lanes
-                                                          in the PCIe core that COULD be used. As per the PCIe specs,
-                                                          the PCIe core can negotiate a smaller link width, so all
-                                                          of x8, x4, x2, and x1 are supported when LME=0xF,
-                                                          for example.) */
-        uint32_t reserved_8_15           : 8;
-        uint32_t flm                     : 1;       /**< Fast Link Mode
-                                                         Sets all internal timers to fast mode for simulation purposes.
-                                                         If during an eeprom load, the first word loaded is 0xffffffff,
-                                                         then the EEPROM load will be terminated and this bit will be set. */
-        uint32_t reserved_6_6            : 1;
-        uint32_t dllle                   : 1;       /**< DLL Link Enable
-                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
-                                                         Express bus does not transmit InitFC DLLPs and does not
-                                                         establish a Link. */
-        uint32_t reserved_4_4            : 1;
-        uint32_t ra                      : 1;       /**< Reset Assert
-                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
-                                                         state (downstream port only). */
-        uint32_t le                      : 1;       /**< Loopback Enable
-                                                         Turns on loopback. */
-        uint32_t sd                      : 1;       /**< Scramble Disable
-                                                         Turns off data scrambling. */
-        uint32_t omr                     : 1;       /**< Other Message Request
-                                                         When software writes a `1' to this bit, the PCI Express bus
-                                                         transmits the Message contained in the Other Message register. */
-#else
-        uint32_t omr                     : 1;
-        uint32_t sd                      : 1;
-        uint32_t le                      : 1;
-        uint32_t ra                      : 1;
-        uint32_t reserved_4_4            : 1;
-        uint32_t dllle                   : 1;
-        uint32_t reserved_6_6            : 1;
-        uint32_t flm                     : 1;
-        uint32_t reserved_8_15           : 8;
-        uint32_t lme                     : 6;
-        uint32_t reserved_22_24          : 3;
-        uint32_t eccrc                   : 1;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg452_s          cn52xx;
-    struct cvmx_pcieep_cfg452_s          cn52xxp1;
-    struct cvmx_pcieep_cfg452_s          cn56xx;
-    struct cvmx_pcieep_cfg452_s          cn56xxp1;
-} cvmx_pcieep_cfg452_t;
-
-
-/**
- * cvmx_pcieep_cfg453
- *
- * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space
- * (Lane Skew Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg453_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dlld                    : 1;       /**< Disable Lane-to-Lane Deskew
-                                                         Disables the internal Lane-to-Lane deskew logic. */
-        uint32_t reserved_26_30          : 5;
-        uint32_t ack_nak                 : 1;       /**< Ack/Nak Disable
-                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
-        uint32_t fcd                     : 1;       /**< Flow Control Disable
-                                                         Prevents the PCI Express bus from sending FC DLLPs. */
-        uint32_t ilst                    : 24;      /**< Insert Lane Skew for Transmit
-                                                         Causes skew between lanes for test purposes. There are three
-                                                         bits per Lane. The value is in units of one symbol time. For
-                                                         example, the value 010b for a Lane forces a skew of two symbol
-                                                         times for that Lane. The maximum skew value for any Lane is 5
-                                                         symbol times. */
-#else
-        uint32_t ilst                    : 24;
-        uint32_t fcd                     : 1;
-        uint32_t ack_nak                 : 1;
-        uint32_t reserved_26_30          : 5;
-        uint32_t dlld                    : 1;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg453_s          cn52xx;
-    struct cvmx_pcieep_cfg453_s          cn52xxp1;
-    struct cvmx_pcieep_cfg453_s          cn56xx;
-    struct cvmx_pcieep_cfg453_s          cn56xxp1;
-} cvmx_pcieep_cfg453_t;
-
-
-/**
- * cvmx_pcieep_cfg454
- *
- * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space
- * (Symbol Number Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg454_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_29_31          : 3;
-        uint32_t tmfcwt                  : 5;       /**< Timer Modifier for Flow Control Watchdog Timer
-                                                         Increases the timer value for the Flow Control watchdog timer,
-                                                         in increments of 16 clock cycles. */
-        uint32_t tmanlt                  : 5;       /**< Timer Modifier for Ack/Nak Latency Timer
-                                                         Increases the timer value for the Ack/Nak latency timer, in
-                                                         increments of 64 clock cycles. */
-        uint32_t tmrt                    : 5;       /**< Timer Modifier for Replay Timer
-                                                         Increases the timer value for the replay timer, in increments
-                                                         of 64 clock cycles. */
-        uint32_t reserved_11_13          : 3;
-        uint32_t nskps                   : 3;       /**< Number of SKP Symbols */
-        uint32_t reserved_4_7            : 4;
-        uint32_t ntss                    : 4;       /**< Number of TS Symbols
-                                                         Sets the number of TS identifier symbols that are sent in TS1
-                                                         and TS2 ordered sets. */
-#else
-        uint32_t ntss                    : 4;
-        uint32_t reserved_4_7            : 4;
-        uint32_t nskps                   : 3;
-        uint32_t reserved_11_13          : 3;
-        uint32_t tmrt                    : 5;
-        uint32_t tmanlt                  : 5;
-        uint32_t tmfcwt                  : 5;
-        uint32_t reserved_29_31          : 3;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg454_s          cn52xx;
-    struct cvmx_pcieep_cfg454_s          cn52xxp1;
-    struct cvmx_pcieep_cfg454_s          cn56xx;
-    struct cvmx_pcieep_cfg454_s          cn56xxp1;
-} cvmx_pcieep_cfg454_t;
-
-
-/**
- * cvmx_pcieep_cfg455
- *
- * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space
- * (Symbol Timer Register/Filter Mask Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg455_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t m_cfg0_filt             : 1;       /**< Mask filtering of received Configuration Requests (RC mode only) */
-        uint32_t m_io_filt               : 1;       /**< Mask filtering of received I/O Requests (RC mode only) */
-        uint32_t msg_ctrl                : 1;       /**< Message Control
-                                                         The application must not change this field. */
-        uint32_t m_cpl_ecrc_filt         : 1;       /**< Mask ECRC error filtering for Completions */
-        uint32_t m_ecrc_filt             : 1;       /**< Mask ECRC error filtering */
-        uint32_t m_cpl_len_err           : 1;       /**< Mask Length mismatch error for received Completions */
-        uint32_t m_cpl_attr_err          : 1;       /**< Mask Attributes mismatch error for received Completions */
-        uint32_t m_cpl_tc_err            : 1;       /**< Mask Traffic Class mismatch error for received Completions */
-        uint32_t m_cpl_fun_err           : 1;       /**< Mask function mismatch error for received Completions */
-        uint32_t m_cpl_rid_err           : 1;       /**< Mask Requester ID mismatch error for received Completions */
-        uint32_t m_cpl_tag_err           : 1;       /**< Mask Tag error rules for received Completions */
-        uint32_t m_lk_filt               : 1;       /**< Mask Locked Request filtering */
-        uint32_t m_cfg1_filt             : 1;       /**< Mask Type 1 Configuration Request filtering */
-        uint32_t m_bar_match             : 1;       /**< Mask BAR match filtering */
-        uint32_t m_pois_filt             : 1;       /**< Mask poisoned TLP filtering */
-        uint32_t m_fun                   : 1;       /**< Mask function */
-        uint32_t dfcwt                   : 1;       /**< Disable FC Watchdog Timer */
-        uint32_t reserved_11_14          : 4;
-        uint32_t skpiv                   : 11;      /**< SKP Interval Value */
-#else
-        uint32_t skpiv                   : 11;
-        uint32_t reserved_11_14          : 4;
-        uint32_t dfcwt                   : 1;
-        uint32_t m_fun                   : 1;
-        uint32_t m_pois_filt             : 1;
-        uint32_t m_bar_match             : 1;
-        uint32_t m_cfg1_filt             : 1;
-        uint32_t m_lk_filt               : 1;
-        uint32_t m_cpl_tag_err           : 1;
-        uint32_t m_cpl_rid_err           : 1;
-        uint32_t m_cpl_fun_err           : 1;
-        uint32_t m_cpl_tc_err            : 1;
-        uint32_t m_cpl_attr_err          : 1;
-        uint32_t m_cpl_len_err           : 1;
-        uint32_t m_ecrc_filt             : 1;
-        uint32_t m_cpl_ecrc_filt         : 1;
-        uint32_t msg_ctrl                : 1;
-        uint32_t m_io_filt               : 1;
-        uint32_t m_cfg0_filt             : 1;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg455_s          cn52xx;
-    struct cvmx_pcieep_cfg455_s          cn52xxp1;
-    struct cvmx_pcieep_cfg455_s          cn56xx;
-    struct cvmx_pcieep_cfg455_s          cn56xxp1;
-} cvmx_pcieep_cfg455_t;
-
-
-/**
- * cvmx_pcieep_cfg456
- *
- * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space
- * (Filter Mask Register 2)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg456_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_2_31           : 30;
-        uint32_t m_vend1_drp             : 1;       /**< Mask Vendor MSG Type 1 dropped silently */
-        uint32_t m_vend0_drp             : 1;       /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
-#else
-        uint32_t m_vend0_drp             : 1;
-        uint32_t m_vend1_drp             : 1;
-        uint32_t reserved_2_31           : 30;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg456_s          cn52xx;
-    struct cvmx_pcieep_cfg456_s          cn52xxp1;
-    struct cvmx_pcieep_cfg456_s          cn56xx;
-    struct cvmx_pcieep_cfg456_s          cn56xxp1;
-} cvmx_pcieep_cfg456_t;
-
-
-/**
- * cvmx_pcieep_cfg458
- *
- * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space
- * (Debug Register 0)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg458_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dbg_info_l32            : 32;      /**< Debug Info Lower 32 Bits */
-#else
-        uint32_t dbg_info_l32            : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg458_s          cn52xx;
-    struct cvmx_pcieep_cfg458_s          cn52xxp1;
-    struct cvmx_pcieep_cfg458_s          cn56xx;
-    struct cvmx_pcieep_cfg458_s          cn56xxp1;
-} cvmx_pcieep_cfg458_t;
-
-
-/**
- * cvmx_pcieep_cfg459
- *
- * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space
- * (Debug Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg459_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dbg_info_u32            : 32;      /**< Debug Info Upper 32 Bits */
-#else
-        uint32_t dbg_info_u32            : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg459_s          cn52xx;
-    struct cvmx_pcieep_cfg459_s          cn52xxp1;
-    struct cvmx_pcieep_cfg459_s          cn56xx;
-    struct cvmx_pcieep_cfg459_s          cn56xxp1;
-} cvmx_pcieep_cfg459_t;
-
-
-/**
- * cvmx_pcieep_cfg460
- *
- * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space
- * (Transmit Posted FC Credit Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg460_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tphfcc                  : 8;       /**< Transmit Posted Header FC Credits
-                                                         The Posted Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tpdfcc                  : 12;      /**< Transmit Posted Data FC Credits
-                                                         The Posted Data credits advertised by the receiver at the other
-                                                         end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tpdfcc                  : 12;
-        uint32_t tphfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg460_s          cn52xx;
-    struct cvmx_pcieep_cfg460_s          cn52xxp1;
-    struct cvmx_pcieep_cfg460_s          cn56xx;
-    struct cvmx_pcieep_cfg460_s          cn56xxp1;
-} cvmx_pcieep_cfg460_t;
-
-
-/**
- * cvmx_pcieep_cfg461
- *
- * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space
- * (Transmit Non-Posted FC Credit Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg461_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tchfcc                  : 8;       /**< Transmit Non-Posted Header FC Credits
-                                                         The Non-Posted Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tcdfcc                  : 12;      /**< Transmit Non-Posted Data FC Credits
-                                                         The Non-Posted Data credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tcdfcc                  : 12;
-        uint32_t tchfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg461_s          cn52xx;
-    struct cvmx_pcieep_cfg461_s          cn52xxp1;
-    struct cvmx_pcieep_cfg461_s          cn56xx;
-    struct cvmx_pcieep_cfg461_s          cn56xxp1;
-} cvmx_pcieep_cfg461_t;
-
-
-/**
- * cvmx_pcieep_cfg462
- *
- * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space
- * (Transmit Completion FC Credit Status )
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg462_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tchfcc                  : 8;       /**< Transmit Completion Header FC Credits
-                                                         The Completion Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tcdfcc                  : 12;      /**< Transmit Completion Data FC Credits
-                                                         The Completion Data credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tcdfcc                  : 12;
-        uint32_t tchfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg462_s          cn52xx;
-    struct cvmx_pcieep_cfg462_s          cn52xxp1;
-    struct cvmx_pcieep_cfg462_s          cn56xx;
-    struct cvmx_pcieep_cfg462_s          cn56xxp1;
-} cvmx_pcieep_cfg462_t;
-
-
-/**
- * cvmx_pcieep_cfg463
- *
- * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space
- * (Queue Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg463_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_3_31           : 29;
-        uint32_t rqne                    : 1;       /**< Received Queue Not Empty
-                                                         Indicates there is data in one or more of the receive buffers. */
-        uint32_t trbne                   : 1;       /**< Transmit Retry Buffer Not Empty
-                                                         Indicates that there is data in the transmit retry buffer. */
-        uint32_t rtlpfccnr               : 1;       /**< Received TLP FC Credits Not Returned
-                                                         Indicates that the PCI Express bus has sent a TLP but has not
-                                                         yet received an UpdateFC DLLP indicating that the credits for
-                                                         that TLP have been restored by the receiver at the other end of
-                                                         the Link. */
-#else
-        uint32_t rtlpfccnr               : 1;
-        uint32_t trbne                   : 1;
-        uint32_t rqne                    : 1;
-        uint32_t reserved_3_31           : 29;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg463_s          cn52xx;
-    struct cvmx_pcieep_cfg463_s          cn52xxp1;
-    struct cvmx_pcieep_cfg463_s          cn56xx;
-    struct cvmx_pcieep_cfg463_s          cn56xxp1;
-} cvmx_pcieep_cfg463_t;
-
-
-/**
- * cvmx_pcieep_cfg464
- *
- * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space
- * (VC Transmit Arbitration Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg464_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wrr_vc3                 : 8;       /**< WRR Weight for VC3 */
-        uint32_t wrr_vc2                 : 8;       /**< WRR Weight for VC2 */
-        uint32_t wrr_vc1                 : 8;       /**< WRR Weight for VC1 */
-        uint32_t wrr_vc0                 : 8;       /**< WRR Weight for VC0 */
-#else
-        uint32_t wrr_vc0                 : 8;
-        uint32_t wrr_vc1                 : 8;
-        uint32_t wrr_vc2                 : 8;
-        uint32_t wrr_vc3                 : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg464_s          cn52xx;
-    struct cvmx_pcieep_cfg464_s          cn52xxp1;
-    struct cvmx_pcieep_cfg464_s          cn56xx;
-    struct cvmx_pcieep_cfg464_s          cn56xxp1;
-} cvmx_pcieep_cfg464_t;
-
-
-/**
- * cvmx_pcieep_cfg465
- *
- * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space
- * (VC Transmit Arbitration Register 2)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg465_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wrr_vc7                 : 8;       /**< WRR Weight for VC7 */
-        uint32_t wrr_vc6                 : 8;       /**< WRR Weight for VC6 */
-        uint32_t wrr_vc5                 : 8;       /**< WRR Weight for VC5 */
-        uint32_t wrr_vc4                 : 8;       /**< WRR Weight for VC4 */
-#else
-        uint32_t wrr_vc4                 : 8;
-        uint32_t wrr_vc5                 : 8;
-        uint32_t wrr_vc6                 : 8;
-        uint32_t wrr_vc7                 : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg465_s          cn52xx;
-    struct cvmx_pcieep_cfg465_s          cn52xxp1;
-    struct cvmx_pcieep_cfg465_s          cn56xx;
-    struct cvmx_pcieep_cfg465_s          cn56xxp1;
-} cvmx_pcieep_cfg465_t;
-
-
-/**
- * cvmx_pcieep_cfg466
- *
- * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space
- * (VC0 Posted Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg466_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t rx_queue_order          : 1;       /**< VC Ordering for Receive Queues
-                                                         Determines the VC ordering rule for the receive queues, used
-                                                         only in the segmented-buffer configuration,
-                                                         writable through the DBI:
-                                                         o 1: Strict ordering, higher numbered VCs have higher priority
-                                                         o 0: Round robin
-                                                         However, the application must not change this field. */
-        uint32_t type_ordering           : 1;       /**< TLP Type Ordering for VC0
-                                                         Determines the TLP type ordering rule for VC0 receive queues,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI:
-                                                         o 1: Ordering of received TLPs follows the rules in
-                                                              PCI Express Base Specification, Revision 1.1
-                                                         o 0: Strict ordering for received TLPs: Posted, then
-                                                              Completion, then Non-Posted
-                                                         However, the application must not change this field. */
-        uint32_t reserved_24_29          : 6;
-        uint32_t queue_mode              : 3;       /**< VC0 Posted TLP Queue Mode
-                                                         The operating mode of the Posted receive queue for VC0, used
-                                                         only in the segmented-buffer configuration, writable through
-                                                         the DBI. However, the application must not change this field.
-                                                         Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Posted Header Credits
-                                                         The number of initial Posted header credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Posted Data Credits
-                                                         The number of initial Posted data credits for VC0, used for all
-                                                         receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_29          : 6;
-        uint32_t type_ordering           : 1;
-        uint32_t rx_queue_order          : 1;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg466_s          cn52xx;
-    struct cvmx_pcieep_cfg466_s          cn52xxp1;
-    struct cvmx_pcieep_cfg466_s          cn56xx;
-    struct cvmx_pcieep_cfg466_s          cn56xxp1;
-} cvmx_pcieep_cfg466_t;
-
-
-/**
- * cvmx_pcieep_cfg467
- *
- * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space
- * (VC0 Non-Posted Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg467_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t queue_mode              : 3;       /**< VC0 Non-Posted TLP Queue Mode
-                                                         The operating mode of the Non-Posted receive queue for VC0,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI. Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Non-Posted Header Credits
-                                                         The number of initial Non-Posted header credits for VC0, used
-                                                         for all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Non-Posted Data Credits
-                                                         The number of initial Non-Posted data credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg467_s          cn52xx;
-    struct cvmx_pcieep_cfg467_s          cn52xxp1;
-    struct cvmx_pcieep_cfg467_s          cn56xx;
-    struct cvmx_pcieep_cfg467_s          cn56xxp1;
-} cvmx_pcieep_cfg467_t;
-
-
-/**
- * cvmx_pcieep_cfg468
- *
- * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space
- * (VC0 Completion Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg468_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t queue_mode              : 3;       /**< VC0 Completion TLP Queue Mode
-                                                         The operating mode of the Completion receive queue for VC0,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI. Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Completion Header Credits
-                                                         The number of initial Completion header credits for VC0, used
-                                                         for all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Completion Data Credits
-                                                         The number of initial Completion data credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg468_s          cn52xx;
-    struct cvmx_pcieep_cfg468_s          cn52xxp1;
-    struct cvmx_pcieep_cfg468_s          cn56xx;
-    struct cvmx_pcieep_cfg468_s          cn56xxp1;
-} cvmx_pcieep_cfg468_t;
-
-
-/**
- * cvmx_pcieep_cfg490
- *
- * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space
- * (VC0 Posted Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg490_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Posted Header Queue Depth
-                                                         Sets the number of entries in the Posted header queue for VC0
-                                                         when using the segmented-buffer configuration, writable through
-                                                         the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Posted Data Queue Depth
-                                                         Sets the number of entries in the Posted data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg490_s          cn52xx;
-    struct cvmx_pcieep_cfg490_s          cn52xxp1;
-    struct cvmx_pcieep_cfg490_s          cn56xx;
-    struct cvmx_pcieep_cfg490_s          cn56xxp1;
-} cvmx_pcieep_cfg490_t;
-
-
-/**
- * cvmx_pcieep_cfg491
- *
- * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space
- * (VC0 Non-Posted Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg491_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Non-Posted Header Queue Depth
-                                                         Sets the number of entries in the Non-Posted header queue for
-                                                         VC0 when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Non-Posted Data Queue Depth
-                                                         Sets the number of entries in the Non-Posted data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg491_s          cn52xx;
-    struct cvmx_pcieep_cfg491_s          cn52xxp1;
-    struct cvmx_pcieep_cfg491_s          cn56xx;
-    struct cvmx_pcieep_cfg491_s          cn56xxp1;
-} cvmx_pcieep_cfg491_t;
-
-
-/**
- * cvmx_pcieep_cfg492
- *
- * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space
- * (VC0 Completion Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg492_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Completion Header Queue Depth
-                                                         Sets the number of entries in the Completion header queue for
-                                                         VC0 when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Completion Data Queue Depth
-                                                         Sets the number of entries in the Completion data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg492_s          cn52xx;
-    struct cvmx_pcieep_cfg492_s          cn52xxp1;
-    struct cvmx_pcieep_cfg492_s          cn56xx;
-    struct cvmx_pcieep_cfg492_s          cn56xxp1;
-} cvmx_pcieep_cfg492_t;
-
-
-/**
- * cvmx_pcieep_cfg516
- *
- * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space
- * (PHY Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg516_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t phy_stat                : 32;      /**< PHY Status */
-#else
-        uint32_t phy_stat                : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg516_s          cn52xx;
-    struct cvmx_pcieep_cfg516_s          cn52xxp1;
-    struct cvmx_pcieep_cfg516_s          cn56xx;
-    struct cvmx_pcieep_cfg516_s          cn56xxp1;
-} cvmx_pcieep_cfg516_t;
-
-
-/**
- * cvmx_pcieep_cfg517
- *
- * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space
- * (PHY Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pcieep_cfg517_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t phy_ctrl                : 32;      /**< PHY Control */
-#else
-        uint32_t phy_ctrl                : 32;
-#endif
-    } s;
-    struct cvmx_pcieep_cfg517_s          cn52xx;
-    struct cvmx_pcieep_cfg517_s          cn52xxp1;
-    struct cvmx_pcieep_cfg517_s          cn56xx;
-    struct cvmx_pcieep_cfg517_s          cn56xxp1;
-} cvmx_pcieep_cfg517_t;
-
-
-/**
- * cvmx_pcierc#_cfg000
- *
- * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg000_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t devid                   : 16;      /**< Device ID, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t vendid                  : 16;      /**< Vendor ID, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t vendid                  : 16;
-        uint32_t devid                   : 16;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg000_s         cn52xx;
-    struct cvmx_pciercx_cfg000_s         cn52xxp1;
-    struct cvmx_pciercx_cfg000_s         cn56xx;
-    struct cvmx_pciercx_cfg000_s         cn56xxp1;
-} cvmx_pciercx_cfg000_t;
-
-
-/**
- * cvmx_pcierc#_cfg001
- *
- * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg001_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dpe                     : 1;       /**< Detected Parity Error */
-        uint32_t sse                     : 1;       /**< Signaled System Error */
-        uint32_t rma                     : 1;       /**< Received Master Abort */
-        uint32_t rta                     : 1;       /**< Received Target Abort */
-        uint32_t sta                     : 1;       /**< Signaled Target Abort */
-        uint32_t devt                    : 2;       /**< DEVSEL Timing
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
-        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t reserved_22_22          : 1;
-        uint32_t m66                     : 1;       /**< 66 MHz Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t cl                      : 1;       /**< Capabilities List
-                                                         Indicates presence of an extended capability item.
-                                                         Hardwired to 1. */
-        uint32_t i_stat                  : 1;       /**< INTx Status */
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_dis                   : 1;       /**< INTx Assertion Disable */
-        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Enable
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t see                     : 1;       /**< SERR# Enable */
-        uint32_t ids_wcc                 : 1;       /**< IDSEL Stepping/Wait Cycle Control
-                                                         Not applicable for PCI Express. Must be hardwired to 0 */
-        uint32_t per                     : 1;       /**< Parity Error Response */
-        uint32_t vps                     : 1;       /**< VGA Palette Snoop
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t mwice                   : 1;       /**< Memory Write and Invalidate
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t scse                    : 1;       /**< Special Cycle Enable
-                                                         Not applicable for PCI Express. Must be hardwired to 0. */
-        uint32_t me                      : 1;       /**< Bus Master Enable */
-        uint32_t msae                    : 1;       /**< Memory Space Enable */
-        uint32_t isae                    : 1;       /**< I/O Space Enable */
-#else
-        uint32_t isae                    : 1;
-        uint32_t msae                    : 1;
-        uint32_t me                      : 1;
-        uint32_t scse                    : 1;
-        uint32_t mwice                   : 1;
-        uint32_t vps                     : 1;
-        uint32_t per                     : 1;
-        uint32_t ids_wcc                 : 1;
-        uint32_t see                     : 1;
-        uint32_t fbbe                    : 1;
-        uint32_t i_dis                   : 1;
-        uint32_t reserved_11_18          : 8;
-        uint32_t i_stat                  : 1;
-        uint32_t cl                      : 1;
-        uint32_t m66                     : 1;
-        uint32_t reserved_22_22          : 1;
-        uint32_t fbb                     : 1;
-        uint32_t mdpe                    : 1;
-        uint32_t devt                    : 2;
-        uint32_t sta                     : 1;
-        uint32_t rta                     : 1;
-        uint32_t rma                     : 1;
-        uint32_t sse                     : 1;
-        uint32_t dpe                     : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg001_s         cn52xx;
-    struct cvmx_pciercx_cfg001_s         cn52xxp1;
-    struct cvmx_pciercx_cfg001_s         cn56xx;
-    struct cvmx_pciercx_cfg001_s         cn56xxp1;
-} cvmx_pciercx_cfg001_t;
-
-
-/**
- * cvmx_pcierc#_cfg002
- *
- * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg002_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t bcc                     : 8;       /**< Base Class Code, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t sc                      : 8;       /**< Subclass Code, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pi                      : 8;       /**< Programming Interface, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t rid                     : 8;       /**< Revision ID, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t rid                     : 8;
-        uint32_t pi                      : 8;
-        uint32_t sc                      : 8;
-        uint32_t bcc                     : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg002_s         cn52xx;
-    struct cvmx_pciercx_cfg002_s         cn52xxp1;
-    struct cvmx_pciercx_cfg002_s         cn56xx;
-    struct cvmx_pciercx_cfg002_s         cn56xxp1;
-} cvmx_pciercx_cfg002_t;
-
-
-/**
- * cvmx_pcierc#_cfg003
- *
- * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg003_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t bist                    : 8;       /**< The BIST register functions are not supported.
-                                                         All 8 bits of the BIST register are hardwired to 0. */
-        uint32_t mfd                     : 1;       /**< Multi Function Device
-                                                         The Multi Function Device bit is writable through the DBI.
-                                                         However, this is a single function device. Therefore, the
-                                                         application must not write a 1 to this bit. */
-        uint32_t chf                     : 7;       /**< Configuration Header Format
-                                                         Hardwired to 1. */
-        uint32_t lt                      : 8;       /**< Master Latency Timer
-                                                         Not applicable for PCI Express, hardwired to 0. */
-        uint32_t cls                     : 8;       /**< Cache Line Size
-                                                         The Cache Line Size register is RW for legacy compatibility
-                                                         purposes and is not applicable to PCI Express device
-                                                         functionality. */
-#else
-        uint32_t cls                     : 8;
-        uint32_t lt                      : 8;
-        uint32_t chf                     : 7;
-        uint32_t mfd                     : 1;
-        uint32_t bist                    : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg003_s         cn52xx;
-    struct cvmx_pciercx_cfg003_s         cn52xxp1;
-    struct cvmx_pciercx_cfg003_s         cn56xx;
-    struct cvmx_pciercx_cfg003_s         cn56xxp1;
-} cvmx_pciercx_cfg003_t;
-
-
-/**
- * cvmx_pcierc#_cfg004
- *
- * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg004_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg004_s         cn52xx;
-    struct cvmx_pciercx_cfg004_s         cn52xxp1;
-    struct cvmx_pciercx_cfg004_s         cn56xx;
-    struct cvmx_pciercx_cfg004_s         cn56xxp1;
-} cvmx_pciercx_cfg004_t;
-
-
-/**
- * cvmx_pcierc#_cfg005
- *
- * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg005_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg005_s         cn52xx;
-    struct cvmx_pciercx_cfg005_s         cn52xxp1;
-    struct cvmx_pciercx_cfg005_s         cn56xx;
-    struct cvmx_pciercx_cfg005_s         cn56xxp1;
-} cvmx_pciercx_cfg005_t;
-
-
-/**
- * cvmx_pcierc#_cfg006
- *
- * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg006_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t slt                     : 8;       /**< Secondary Latency Timer
-                                                         Not applicable to PCI Express, hardwired to 0x00. */
-        uint32_t subbnum                 : 8;       /**< Subordinate Bus Number */
-        uint32_t sbnum                   : 8;       /**< Secondary Bus Number */
-        uint32_t pbnum                   : 8;       /**< Primary Bus Number */
-#else
-        uint32_t pbnum                   : 8;
-        uint32_t sbnum                   : 8;
-        uint32_t subbnum                 : 8;
-        uint32_t slt                     : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg006_s         cn52xx;
-    struct cvmx_pciercx_cfg006_s         cn52xxp1;
-    struct cvmx_pciercx_cfg006_s         cn56xx;
-    struct cvmx_pciercx_cfg006_s         cn56xxp1;
-} cvmx_pciercx_cfg006_t;
-
-
-/**
- * cvmx_pcierc#_cfg007
- *
- * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg007_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dpe                     : 1;       /**< Detected Parity Error */
-        uint32_t sse                     : 1;       /**< Signaled System Error */
-        uint32_t rma                     : 1;       /**< Received Master Abort */
-        uint32_t rta                     : 1;       /**< Received Target Abort */
-        uint32_t sta                     : 1;       /**< Signaled Target Abort */
-        uint32_t devt                    : 2;       /**< DEVSEL Timing
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
-        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t reserved_22_22          : 1;
-        uint32_t m66                     : 1;       /**< 66 MHz Capable
-                                                         Not applicable for PCI Express. Hardwired to 0. */
-        uint32_t reserved_16_20          : 5;
-        uint32_t lio_limi                : 4;       /**< I/O Space Limit */
-        uint32_t reserved_9_11           : 3;
-        uint32_t io32b                   : 1;       /**< 32-Bit I/O Space */
-        uint32_t lio_base                : 4;       /**< I/O Space Base */
-        uint32_t reserved_1_3            : 3;
-        uint32_t io32a                   : 1;       /**< 32-Bit I/O Space
-                                                         o 0 = 16-bit I/O addressing
-                                                         o 1 = 32-bit I/O addressing
-                                                         This bit is writable through the DBI. When the application
-                                                         writes to this bit through the DBI, the same value is written
-                                                         to bit 8 of this register. */
-#else
-        uint32_t io32a                   : 1;
-        uint32_t reserved_1_3            : 3;
-        uint32_t lio_base                : 4;
-        uint32_t io32b                   : 1;
-        uint32_t reserved_9_11           : 3;
-        uint32_t lio_limi                : 4;
-        uint32_t reserved_16_20          : 5;
-        uint32_t m66                     : 1;
-        uint32_t reserved_22_22          : 1;
-        uint32_t fbb                     : 1;
-        uint32_t mdpe                    : 1;
-        uint32_t devt                    : 2;
-        uint32_t sta                     : 1;
-        uint32_t rta                     : 1;
-        uint32_t rma                     : 1;
-        uint32_t sse                     : 1;
-        uint32_t dpe                     : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg007_s         cn52xx;
-    struct cvmx_pciercx_cfg007_s         cn52xxp1;
-    struct cvmx_pciercx_cfg007_s         cn56xx;
-    struct cvmx_pciercx_cfg007_s         cn56xxp1;
-} cvmx_pciercx_cfg007_t;
-
-
-/**
- * cvmx_pcierc#_cfg008
- *
- * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg008_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ml_addr                 : 12;      /**< Memory Limit Address */
-        uint32_t reserved_16_19          : 4;
-        uint32_t mb_addr                 : 12;      /**< Memory Base Address */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t mb_addr                 : 12;
-        uint32_t reserved_16_19          : 4;
-        uint32_t ml_addr                 : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg008_s         cn52xx;
-    struct cvmx_pciercx_cfg008_s         cn52xxp1;
-    struct cvmx_pciercx_cfg008_s         cn56xx;
-    struct cvmx_pciercx_cfg008_s         cn56xxp1;
-} cvmx_pciercx_cfg008_t;
-
-
-/**
- * cvmx_pcierc#_cfg009
- *
- * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg009_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmem_limit              : 12;      /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */
-        uint32_t reserved_17_19          : 3;
-        uint32_t mem64b                  : 1;       /**< 64-Bit Memory Addressing
-                                                         o 0 = 32-bit memory addressing
-                                                         o 1 = 64-bit memory addressing */
-        uint32_t lmem_base               : 12;      /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */
-        uint32_t reserved_1_3            : 3;
-        uint32_t mem64a                  : 1;       /**< 64-Bit Memory Addressing
-                                                         o 0 = 32-bit memory addressing
-                                                         o 1 = 64-bit memory addressing
-                                                         This bit is writable through the DBI. When the application
-                                                         writes to this bit through the DBI, the same value is written
-                                                         to bit 16 of this register. */
-#else
-        uint32_t mem64a                  : 1;
-        uint32_t reserved_1_3            : 3;
-        uint32_t lmem_base               : 12;
-        uint32_t mem64b                  : 1;
-        uint32_t reserved_17_19          : 3;
-        uint32_t lmem_limit              : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg009_s         cn52xx;
-    struct cvmx_pciercx_cfg009_s         cn52xxp1;
-    struct cvmx_pciercx_cfg009_s         cn56xx;
-    struct cvmx_pciercx_cfg009_s         cn56xxp1;
-} cvmx_pciercx_cfg009_t;
-
-
-/**
- * cvmx_pcierc#_cfg010
- *
- * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg010_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umem_base               : 32;      /**< Upper 32 Bits of Base Address of Prefetchable Memory Space
-                                                         Used only when 64-bit prefetchable memory addressing is
-                                                         enabled. */
-#else
-        uint32_t umem_base               : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg010_s         cn52xx;
-    struct cvmx_pciercx_cfg010_s         cn52xxp1;
-    struct cvmx_pciercx_cfg010_s         cn56xx;
-    struct cvmx_pciercx_cfg010_s         cn56xxp1;
-} cvmx_pciercx_cfg010_t;
-
-
-/**
- * cvmx_pcierc#_cfg011
- *
- * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg011_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umem_limit              : 32;      /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space
-                                                         Used only when 64-bit prefetchable memory addressing is
-                                                         enabled. */
-#else
-        uint32_t umem_limit              : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg011_s         cn52xx;
-    struct cvmx_pciercx_cfg011_s         cn52xxp1;
-    struct cvmx_pciercx_cfg011_s         cn56xx;
-    struct cvmx_pciercx_cfg011_s         cn56xxp1;
-} cvmx_pciercx_cfg011_t;
-
-
-/**
- * cvmx_pcierc#_cfg012
- *
- * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg012_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t uio_limit               : 16;      /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported
-                                                         for devices on the secondary side) */
-        uint32_t uio_base                : 16;      /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported
-                                                         for devices on the secondary side) */
-#else
-        uint32_t uio_base                : 16;
-        uint32_t uio_limit               : 16;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg012_s         cn52xx;
-    struct cvmx_pciercx_cfg012_s         cn52xxp1;
-    struct cvmx_pciercx_cfg012_s         cn56xx;
-    struct cvmx_pciercx_cfg012_s         cn56xxp1;
-} cvmx_pciercx_cfg012_t;
-
-
-/**
- * cvmx_pcierc#_cfg013
- *
- * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg013_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_8_31           : 24;
-        uint32_t cp                      : 8;       /**< First Capability Pointer.
-                                                         Points to Power Management Capability structure by
-                                                         default, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t cp                      : 8;
-        uint32_t reserved_8_31           : 24;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg013_s         cn52xx;
-    struct cvmx_pciercx_cfg013_s         cn52xxp1;
-    struct cvmx_pciercx_cfg013_s         cn56xx;
-    struct cvmx_pciercx_cfg013_s         cn56xxp1;
-} cvmx_pciercx_cfg013_t;
-
-
-/**
- * cvmx_pcierc#_cfg014
- *
- * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg014_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg014_s         cn52xx;
-    struct cvmx_pciercx_cfg014_s         cn52xxp1;
-    struct cvmx_pciercx_cfg014_s         cn56xx;
-    struct cvmx_pciercx_cfg014_s         cn56xxp1;
-} cvmx_pciercx_cfg014_t;
-
-
-/**
- * cvmx_pcierc#_cfg015
- *
- * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg015_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_28_31          : 4;
-        uint32_t dtsees                  : 1;       /**< Discard Timer SERR Enable Status
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t dts                     : 1;       /**< Discard Timer Status
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t sdt                     : 1;       /**< Secondary Discard Timer
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t pdt                     : 1;       /**< Primary Discard Timer
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Transactions Enable
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t sbrst                   : 1;       /**< Secondary Bus Reset
-                                                         Hot reset. Causes TS1s with the hot reset bit to be sent to
-                                                         the link partner. When set, SW should wait 2ms before
-                                                         clearing. The link partner normally responds by sending TS1s
-                                                         with the hot reset bit set, which will cause a link
-                                                         down event - refer to "PCIe Link-Down Reset in RC Mode"
-                                                         section. */
-        uint32_t mam                     : 1;       /**< Master Abort Mode
-                                                         Not applicable to PCI Express, hardwired to 0. */
-        uint32_t vga16d                  : 1;       /**< VGA 16-Bit Decode */
-        uint32_t vgae                    : 1;       /**< VGA Enable */
-        uint32_t isae                    : 1;       /**< ISA Enable */
-        uint32_t see                     : 1;       /**< SERR Enable */
-        uint32_t pere                    : 1;       /**< Parity Error Response Enable */
-        uint32_t inta                    : 8;       /**< Interrupt Pin
-                                                         Identifies the legacy interrupt Message that the device
-                                                         (or device function) uses.
-                                                         The Interrupt Pin register is writable through the DBI.
-                                                         In a single-function configuration, only INTA is used.
-                                                         Therefore, the application must not change this field. */
-        uint32_t il                      : 8;       /**< Interrupt Line */
-#else
-        uint32_t il                      : 8;
-        uint32_t inta                    : 8;
-        uint32_t pere                    : 1;
-        uint32_t see                     : 1;
-        uint32_t isae                    : 1;
-        uint32_t vgae                    : 1;
-        uint32_t vga16d                  : 1;
-        uint32_t mam                     : 1;
-        uint32_t sbrst                   : 1;
-        uint32_t fbbe                    : 1;
-        uint32_t pdt                     : 1;
-        uint32_t sdt                     : 1;
-        uint32_t dts                     : 1;
-        uint32_t dtsees                  : 1;
-        uint32_t reserved_28_31          : 4;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg015_s         cn52xx;
-    struct cvmx_pciercx_cfg015_s         cn52xxp1;
-    struct cvmx_pciercx_cfg015_s         cn56xx;
-    struct cvmx_pciercx_cfg015_s         cn56xxp1;
-} cvmx_pciercx_cfg015_t;
-
-
-/**
- * cvmx_pcierc#_cfg016
- *
- * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space
- * (Power Management Capability ID/
- * Power Management Next Item Pointer/
- * Power Management Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg016_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmes                    : 5;       /**< PME_Support
-                                                         A value of 0 for any bit indicates that the
-                                                         device (or function) is not capable of generating PME Messages
-                                                         while in that power state:
-                                                         o Bit 11: If set, PME Messages can be generated from D0
-                                                         o Bit 12: If set, PME Messages can be generated from D1
-                                                         o Bit 13: If set, PME Messages can be generated from D2
-                                                         o Bit 14: If set, PME Messages can be generated from D3hot
-                                                         o Bit 15: If set, PME Messages can be generated from D3cold
-                                                         The PME_Support field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t d2s                     : 1;       /**< D2 Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t d1s                     : 1;       /**< D1 Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t auxc                    : 3;       /**< AUX Current, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t dsi                     : 1;       /**< Device Specific Initialization (DSI), writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t pme_clock               : 1;       /**< PME Clock, hardwired to 0 */
-        uint32_t pmsv                    : 3;       /**< Power Management Specification Version, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         Points to the MSI capabilities by default, writable
-                                                         through the DBI. */
-        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
-#else
-        uint32_t pmcid                   : 8;
-        uint32_t ncp                     : 8;
-        uint32_t pmsv                    : 3;
-        uint32_t pme_clock               : 1;
-        uint32_t reserved_20_20          : 1;
-        uint32_t dsi                     : 1;
-        uint32_t auxc                    : 3;
-        uint32_t d1s                     : 1;
-        uint32_t d2s                     : 1;
-        uint32_t pmes                    : 5;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg016_s         cn52xx;
-    struct cvmx_pciercx_cfg016_s         cn52xxp1;
-    struct cvmx_pciercx_cfg016_s         cn56xx;
-    struct cvmx_pciercx_cfg016_s         cn56xxp1;
-} cvmx_pciercx_cfg016_t;
-
-
-/**
- * cvmx_pcierc#_cfg017
- *
- * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg017_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pmdia                   : 8;       /**< Data register for additional information (not supported) */
-        uint32_t bpccee                  : 1;       /**< Bus Power/Clock Control Enable, hardwired to 0 */
-        uint32_t bd3h                    : 1;       /**< B2/B3 Support, hardwired to 0 */
-        uint32_t reserved_16_21          : 6;
-        uint32_t pmess                   : 1;       /**< PME Status
-                                                         Indicates if a previously enabled PME event occurred or not. */
-        uint32_t pmedsia                 : 2;       /**< Data Scale (not supported) */
-        uint32_t pmds                    : 4;       /**< Data Select (not supported) */
-        uint32_t pmeens                  : 1;       /**< PME Enable
-                                                         A value of 1 indicates that the device is enabled to
-                                                         generate PME. */
-        uint32_t reserved_4_7            : 4;
-        uint32_t nsr                     : 1;       /**< No Soft Reset, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_2_2            : 1;
-        uint32_t ps                      : 2;       /**< Power State
-                                                         Controls the device power state:
-                                                           o 00b: D0
-                                                           o 01b: D1
-                                                           o 10b: D2
-                                                           o 11b: D3
-                                                         The written value is ignored if the specific state is
-                                                         not supported. */
-#else
-        uint32_t ps                      : 2;
-        uint32_t reserved_2_2            : 1;
-        uint32_t nsr                     : 1;
-        uint32_t reserved_4_7            : 4;
-        uint32_t pmeens                  : 1;
-        uint32_t pmds                    : 4;
-        uint32_t pmedsia                 : 2;
-        uint32_t pmess                   : 1;
-        uint32_t reserved_16_21          : 6;
-        uint32_t bd3h                    : 1;
-        uint32_t bpccee                  : 1;
-        uint32_t pmdia                   : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg017_s         cn52xx;
-    struct cvmx_pciercx_cfg017_s         cn52xxp1;
-    struct cvmx_pciercx_cfg017_s         cn56xx;
-    struct cvmx_pciercx_cfg017_s         cn56xxp1;
-} cvmx_pciercx_cfg017_t;
-
-
-/**
- * cvmx_pcierc#_cfg020
- *
- * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space
- * (MSI Capability ID/
- *  MSI Next Item Pointer/
- *  MSI Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg020_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t m64                     : 1;       /**< 64-bit Address Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t mme                     : 3;       /**< Multiple Message Enabled
-                                                         Indicates that multiple Message mode is enabled by system
-                                                         software. The number of Messages enabled must be less than
-                                                         or equal to the Multiple Message Capable value. */
-        uint32_t mmc                     : 3;       /**< Multiple Message Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t msien                   : 1;       /**< MSI Enabled
-                                                         When set, INTx must be disabled.
-                                                         This bit must never be set, as internal-MSI is not supported in
-                                                         RC mode. (Note that this has no effect on external MSI, which
-                                                         will be commonly used in RC mode.) */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         Points to PCI Express Capabilities by default,
-                                                         writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t msicid                  : 8;       /**< MSI Capability ID */
-#else
-        uint32_t msicid                  : 8;
-        uint32_t ncp                     : 8;
-        uint32_t msien                   : 1;
-        uint32_t mmc                     : 3;
-        uint32_t mme                     : 3;
-        uint32_t m64                     : 1;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg020_s         cn52xx;
-    struct cvmx_pciercx_cfg020_s         cn52xxp1;
-    struct cvmx_pciercx_cfg020_s         cn56xx;
-    struct cvmx_pciercx_cfg020_s         cn56xxp1;
-} cvmx_pciercx_cfg020_t;
-
-
-/**
- * cvmx_pcierc#_cfg021
- *
- * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg021_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lmsi                    : 30;      /**< Lower 32-bit Address */
-        uint32_t reserved_0_1            : 2;
-#else
-        uint32_t reserved_0_1            : 2;
-        uint32_t lmsi                    : 30;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg021_s         cn52xx;
-    struct cvmx_pciercx_cfg021_s         cn52xxp1;
-    struct cvmx_pciercx_cfg021_s         cn56xx;
-    struct cvmx_pciercx_cfg021_s         cn56xxp1;
-} cvmx_pciercx_cfg021_t;
-
-
-/**
- * cvmx_pcierc#_cfg022
- *
- * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg022_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t umsi                    : 32;      /**< Upper 32-bit Address */
-#else
-        uint32_t umsi                    : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg022_s         cn52xx;
-    struct cvmx_pciercx_cfg022_s         cn52xxp1;
-    struct cvmx_pciercx_cfg022_s         cn56xx;
-    struct cvmx_pciercx_cfg022_s         cn56xxp1;
-} cvmx_pciercx_cfg022_t;
-
-
-/**
- * cvmx_pcierc#_cfg023
- *
- * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg023_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t msimd                   : 16;      /**< MSI Data
-                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
-                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
-#else
-        uint32_t msimd                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg023_s         cn52xx;
-    struct cvmx_pciercx_cfg023_s         cn52xxp1;
-    struct cvmx_pciercx_cfg023_s         cn56xx;
-    struct cvmx_pciercx_cfg023_s         cn56xxp1;
-} cvmx_pciercx_cfg023_t;
-
-
-/**
- * cvmx_pcierc#_cfg028
- *
- * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space
- * (PCI Express Capabilities List Register/
- *  PCI Express Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg028_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t imn                     : 5;       /**< Interrupt Message Number
-                                                         Updated by hardware, writable through the DBI.
-                                                          However, the application must not change this field. */
-        uint32_t si                      : 1;       /**< Slot Implemented
-                                                         This bit is writable through the DBI. However, it must 0 for an
-                                                         Endpoint device. Therefore, the application must not write a
-                                                         1 to this bit. */
-        uint32_t dpt                     : 4;       /**< Device Port Type */
-        uint32_t pciecv                  : 4;       /**< PCI Express Capability Version */
-        uint32_t ncp                     : 8;       /**< Next Capability Pointer
-                                                         writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t pcieid                  : 8;       /**< PCIE Capability ID */
-#else
-        uint32_t pcieid                  : 8;
-        uint32_t ncp                     : 8;
-        uint32_t pciecv                  : 4;
-        uint32_t dpt                     : 4;
-        uint32_t si                      : 1;
-        uint32_t imn                     : 5;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg028_s         cn52xx;
-    struct cvmx_pciercx_cfg028_s         cn52xxp1;
-    struct cvmx_pciercx_cfg028_s         cn56xx;
-    struct cvmx_pciercx_cfg028_s         cn56xxp1;
-} cvmx_pciercx_cfg028_t;
-
-
-/**
- * cvmx_pcierc#_cfg029
- *
- * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg029_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_28_31          : 4;
-        uint32_t cspls                   : 2;       /**< Captured Slot Power Limit Scale
-                                                         Not applicable for RC port, upstream port only. */
-        uint32_t csplv                   : 8;       /**< Captured Slot Power Limit Value
-                                                         Not applicable for RC port, upstream port only. */
-        uint32_t reserved_16_17          : 2;
-        uint32_t rber                    : 1;       /**< Role-Based Error Reporting, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_12_14          : 3;
-        uint32_t el1al                   : 3;       /**< Endpoint L1 Acceptable Latency, writable through the DBI
-                                                         Must be 0x0 for non-endpoint devices. */
-        uint32_t el0al                   : 3;       /**< Endpoint L0s Acceptable Latency, writable through the DBI
-                                                         Must be 0x0 for non-endpoint devices. */
-        uint32_t etfs                    : 1;       /**< Extended Tag Field Supported
-                                                         This bit is writable through the DBI. However, the application
-                                                         must not write a 1 to this bit. */
-        uint32_t pfs                     : 2;       /**< Phantom Function Supported
-                                                         This field is writable through the DBI. However, Phantom
-                                                         Function is not supported. Therefore, the application must not
-                                                         write any value other than 0x0 to this field. */
-        uint32_t mpss                    : 3;       /**< Max_Payload_Size Supported, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t mpss                    : 3;
-        uint32_t pfs                     : 2;
-        uint32_t etfs                    : 1;
-        uint32_t el0al                   : 3;
-        uint32_t el1al                   : 3;
-        uint32_t reserved_12_14          : 3;
-        uint32_t rber                    : 1;
-        uint32_t reserved_16_17          : 2;
-        uint32_t csplv                   : 8;
-        uint32_t cspls                   : 2;
-        uint32_t reserved_28_31          : 4;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg029_s         cn52xx;
-    struct cvmx_pciercx_cfg029_s         cn52xxp1;
-    struct cvmx_pciercx_cfg029_s         cn56xx;
-    struct cvmx_pciercx_cfg029_s         cn56xxp1;
-} cvmx_pciercx_cfg029_t;
-
-
-/**
- * cvmx_pcierc#_cfg030
- *
- * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space
- * (Device Control Register/Device Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg030_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_22_31          : 10;
-        uint32_t tp                      : 1;       /**< Transaction Pending
-                                                         Set to 1 when Non-Posted Requests are not yet completed
-                                                         and clear when they are completed. */
-        uint32_t ap_d                    : 1;       /**< Aux Power Detected
-                                                         Set to 1 if Aux power detected. */
-        uint32_t ur_d                    : 1;       /**< Unsupported Request Detected
-                                                         Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         UR_D occurs when we receive something we don't support.
-                                                         Unsupported requests are Nonfatal errors, so UR_D should
-                                                         cause NFE_D.  Receiving a  vendor defined message should
-                                                         cause an unsupported request. */
-        uint32_t fe_d                    : 1;       /**< Fatal Error Detected
-                                                         Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
-                                                         has a severity set to Fatal.  Malformed TLP's generally fit
-                                                         into this category. */
-        uint32_t nfe_d                   : 1;       /**< Non-Fatal Error detected
-                                                         Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
-                                                         that has a severity set to Nonfatal and does NOT meet Advisory
-                                                         Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
-                                                         most poisoned TLP's should be. */
-        uint32_t ce_d                    : 1;       /**< Correctable Error Detected
-                                                          Errors are logged in this register regardless of whether
-                                                          error reporting is enabled in the Device Control register.
-                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
-                                                         for example a Replay Timer Timeout.  Also, it can be set if
-                                                         we get any of the errors in PCIE_CFG066 that has a severity
-                                                         set to Nonfatal and meets the Advisory Nonfatal criteria
-                                                         (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
-                                                         should be. */
-        uint32_t reserved_15_15          : 1;
-        uint32_t mrrs                    : 3;       /**< Max Read Request Size
-                                                          0 = 128B
-                                                          1 = 256B
-                                                          2 = 512B
-                                                          3 = 1024B
-                                                          4 = 2048B
-                                                          5 = 4096B
-                                                         Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
-                                                         NPEI_CTL_STATUS2[MRRS] must not exceed the
-                                                         desired max read request size. */
-        uint32_t ns_en                   : 1;       /**< Enable No Snoop */
-        uint32_t ap_en                   : 1;       /**< AUX Power PM Enable */
-        uint32_t pf_en                   : 1;       /**< Phantom Function Enable
-                                                         This bit should never be set - OCTEON requests never use
-                                                         phantom functions. */
-        uint32_t etf_en                  : 1;       /**< Extended Tag Field Enable
-                                                         This bit should never be set - OCTEON requests never use
-                                                         extended tags. */
-        uint32_t mps                     : 3;       /**< Max Payload Size
-                                                          Legal values:
-                                                           0  = 128B
-                                                           1  = 256B
-                                                          Larger sizes not supported.
-                                                         Note: Both PCI Express Ports must be set to the same value
-                                                               for Peer-to-Peer to function properly.
-                                                         Note: NPEI_CTL_STATUS2[MPS] must also be set to the same
-                                                               value for proper functionality. */
-        uint32_t ro_en                   : 1;       /**< Enable Relaxed Ordering */
-        uint32_t ur_en                   : 1;       /**< Unsupported Request Reporting Enable */
-        uint32_t fe_en                   : 1;       /**< Fatal Error Reporting Enable */
-        uint32_t nfe_en                  : 1;       /**< Non-Fatal Error Reporting Enable */
-        uint32_t ce_en                   : 1;       /**< Correctable Error Reporting Enable */
-#else
-        uint32_t ce_en                   : 1;
-        uint32_t nfe_en                  : 1;
-        uint32_t fe_en                   : 1;
-        uint32_t ur_en                   : 1;
-        uint32_t ro_en                   : 1;
-        uint32_t mps                     : 3;
-        uint32_t etf_en                  : 1;
-        uint32_t pf_en                   : 1;
-        uint32_t ap_en                   : 1;
-        uint32_t ns_en                   : 1;
-        uint32_t mrrs                    : 3;
-        uint32_t reserved_15_15          : 1;
-        uint32_t ce_d                    : 1;
-        uint32_t nfe_d                   : 1;
-        uint32_t fe_d                    : 1;
-        uint32_t ur_d                    : 1;
-        uint32_t ap_d                    : 1;
-        uint32_t tp                      : 1;
-        uint32_t reserved_22_31          : 10;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg030_s         cn52xx;
-    struct cvmx_pciercx_cfg030_s         cn52xxp1;
-    struct cvmx_pciercx_cfg030_s         cn56xx;
-    struct cvmx_pciercx_cfg030_s         cn56xxp1;
-} cvmx_pciercx_cfg030_t;
-
-
-/**
- * cvmx_pcierc#_cfg031
- *
- * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space
- * (Link Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg031_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t pnum                    : 8;       /**< Port Number, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t reserved_22_23          : 2;
-        uint32_t lbnc                    : 1;       /**< Link Bandwith Notification Capability */
-        uint32_t dllarc                  : 1;       /**< Data Link Layer Active Reporting Capable
-                                                         Set to 1 for Root Complex devices and 0 for Endpoint devices. */
-        uint32_t sderc                   : 1;       /**< Surprise Down Error Reporting Capable
-                                                         Not supported, hardwired to 0x0. */
-        uint32_t cpm                     : 1;       /**< Clock Power Management
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t l1el                    : 3;       /**< L1 Exit Latency
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t l0el                    : 3;       /**< L0s Exit Latency
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t aslpms                  : 2;       /**< Active State Link PM Support
-                                                         The default value is the value you specify during hardware
-                                                         configuration, writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t mlw                     : 6;       /**< Maximum Link Width
-                                                         The default value is the value you specify during hardware
-                                                         configuration (x1, x4, x8, or x16), writable through the DBI.
-                                                         The SW needs to set this to 0x8 or 0x4 depending on the max
-                                                         number of lanes (QLM_CFG == 0 set to 0x8 else 0x4). */
-        uint32_t mls                     : 4;       /**< Maximum Link Speed
-                                                         Default value is 0x1 for 2.5 Gbps Link.
-                                                         This field is writable through the DBI. However, 0x1 is the
-                                                         only supported value. Therefore, the application must not write
-                                                         any value other than 0x1 to this field. */
-#else
-        uint32_t mls                     : 4;
-        uint32_t mlw                     : 6;
-        uint32_t aslpms                  : 2;
-        uint32_t l0el                    : 3;
-        uint32_t l1el                    : 3;
-        uint32_t cpm                     : 1;
-        uint32_t sderc                   : 1;
-        uint32_t dllarc                  : 1;
-        uint32_t lbnc                    : 1;
-        uint32_t reserved_22_23          : 2;
-        uint32_t pnum                    : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg031_s         cn52xx;
-    struct cvmx_pciercx_cfg031_s         cn52xxp1;
-    struct cvmx_pciercx_cfg031_s         cn56xx;
-    struct cvmx_pciercx_cfg031_s         cn56xxp1;
-} cvmx_pciercx_cfg031_t;
-
-
-/**
- * cvmx_pcierc#_cfg032
- *
- * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space
- * (Link Control Register/Link Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg032_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lab                     : 1;       /**< Link Autonomous Bandwidth Status */
-        uint32_t lbm                     : 1;       /**< Link Bandwidth Management Status */
-        uint32_t dlla                    : 1;       /**< Data Link Layer Active */
-        uint32_t scc                     : 1;       /**< Slot Clock Configuration
-                                                         Indicates that the component uses the same physical reference
-                                                         clock that the platform provides on the connector. The default
-                                                         value is the value you select during hardware configuration,
-                                                         writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t lt                      : 1;       /**< Link Training */
-        uint32_t reserved_26_26          : 1;
-        uint32_t nlw                     : 6;       /**< Negotiated Link Width
-                                                         Set automatically by hardware after Link initialization. */
-        uint32_t ls                      : 4;       /**< Link Speed
-                                                         The negotiated Link speed: 2.5 Gbps */
-        uint32_t reserved_12_15          : 4;
-        uint32_t lab_int_enb             : 1;       /**< Link Autonomous Bandwidth Interrupt Enable
-                                                         This interrupt is for Gen2 and is not supported. This bit should
-                                                         always be written to zero. */
-        uint32_t lbm_int_enb             : 1;       /**< Link Bandwidth Management Interrupt Enable
-                                                         This interrupt is for Gen2 and is not supported. This bit should
-                                                         always be written to zero. */
-        uint32_t hawd                    : 1;       /**< Hardware Autonomous Width Disable
-                                                         (Not Supported) */
-        uint32_t ecpm                    : 1;       /**< Enable Clock Power Management
-                                                         Hardwired to 0 if Clock Power Management is disabled in
-                                                         the Link Capabilities register. */
-        uint32_t es                      : 1;       /**< Extended Synch */
-        uint32_t ccc                     : 1;       /**< Common Clock Configuration */
-        uint32_t rl                      : 1;       /**< Retrain Link */
-        uint32_t ld                      : 1;       /**< Link Disable */
-        uint32_t rcb                     : 1;       /**< Read Completion Boundary (RCB), writable through the DBI
-                                                         However, the application must not change this field
-                                                         because an RCB of 64 bytes is not supported. */
-        uint32_t reserved_2_2            : 1;
-        uint32_t aslpc                   : 2;       /**< Active State Link PM Control */
-#else
-        uint32_t aslpc                   : 2;
-        uint32_t reserved_2_2            : 1;
-        uint32_t rcb                     : 1;
-        uint32_t ld                      : 1;
-        uint32_t rl                      : 1;
-        uint32_t ccc                     : 1;
-        uint32_t es                      : 1;
-        uint32_t ecpm                    : 1;
-        uint32_t hawd                    : 1;
-        uint32_t lbm_int_enb             : 1;
-        uint32_t lab_int_enb             : 1;
-        uint32_t reserved_12_15          : 4;
-        uint32_t ls                      : 4;
-        uint32_t nlw                     : 6;
-        uint32_t reserved_26_26          : 1;
-        uint32_t lt                      : 1;
-        uint32_t scc                     : 1;
-        uint32_t dlla                    : 1;
-        uint32_t lbm                     : 1;
-        uint32_t lab                     : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg032_s         cn52xx;
-    struct cvmx_pciercx_cfg032_s         cn52xxp1;
-    struct cvmx_pciercx_cfg032_s         cn56xx;
-    struct cvmx_pciercx_cfg032_s         cn56xxp1;
-} cvmx_pciercx_cfg032_t;
-
-
-/**
- * cvmx_pcierc#_cfg033
- *
- * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space
- * (Slot Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg033_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ps_num                  : 13;      /**< Physical Slot Number, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t nccs                    : 1;       /**< No Command Complete Support, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t emip                    : 1;       /**< Electromechanical Interlock Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t sp_ls                   : 2;       /**< Slot Power Limit Scale, writable through the DBI. */
-        uint32_t sp_lv                   : 8;       /**< Slot Power Limit Value, writable through the DBI. */
-        uint32_t hp_c                    : 1;       /**< Hot-Plug Capable, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t hp_s                    : 1;       /**< Hot-Plug Surprise, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pip                     : 1;       /**< Power Indicator Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t aip                     : 1;       /**< Attention Indicator Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t mrlsp                   : 1;       /**< MRL Sensor Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t pcp                     : 1;       /**< Power Controller Present, writable through the DBI
-                                                         However, the application must not change this field. */
-        uint32_t abp                     : 1;       /**< Attention Button Present, writable through the DBI
-                                                         However, the application must not change this field. */
-#else
-        uint32_t abp                     : 1;
-        uint32_t pcp                     : 1;
-        uint32_t mrlsp                   : 1;
-        uint32_t aip                     : 1;
-        uint32_t pip                     : 1;
-        uint32_t hp_s                    : 1;
-        uint32_t hp_c                    : 1;
-        uint32_t sp_lv                   : 8;
-        uint32_t sp_ls                   : 2;
-        uint32_t emip                    : 1;
-        uint32_t nccs                    : 1;
-        uint32_t ps_num                  : 13;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg033_s         cn52xx;
-    struct cvmx_pciercx_cfg033_s         cn52xxp1;
-    struct cvmx_pciercx_cfg033_s         cn56xx;
-    struct cvmx_pciercx_cfg033_s         cn56xxp1;
-} cvmx_pciercx_cfg033_t;
-
-
-/**
- * cvmx_pcierc#_cfg034
- *
- * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space
- * (Slot Control Register/Slot Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg034_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_25_31          : 7;
-        uint32_t dlls_c                  : 1;       /**< Data Link Layer State Changed */
-        uint32_t emis                    : 1;       /**< Electromechanical Interlock Status */
-        uint32_t pds                     : 1;       /**< Presence Detect State */
-        uint32_t mrlss                   : 1;       /**< MRL Sensor State */
-        uint32_t ccint_d                 : 1;       /**< Command Completed */
-        uint32_t pd_c                    : 1;       /**< Presence Detect Changed */
-        uint32_t mrls_c                  : 1;       /**< MRL Sensor Changed */
-        uint32_t pf_d                    : 1;       /**< Power Fault Detected */
-        uint32_t abp_d                   : 1;       /**< Attention Button Pressed */
-        uint32_t reserved_13_15          : 3;
-        uint32_t dlls_en                 : 1;       /**< Data Link Layer State Changed Enable */
-        uint32_t emic                    : 1;       /**< Electromechanical Interlock Control */
-        uint32_t pcc                     : 1;       /**< Power Controller Control */
-        uint32_t pic                     : 2;       /**< Power Indicator Control */
-        uint32_t aic                     : 2;       /**< Attention Indicator Control */
-        uint32_t hpint_en                : 1;       /**< Hot-Plug Interrupt Enable */
-        uint32_t ccint_en                : 1;       /**< Command Completed Interrupt Enable */
-        uint32_t pd_en                   : 1;       /**< Presence Detect Changed Enable */
-        uint32_t mrls_en                 : 1;       /**< MRL Sensor Changed Enable */
-        uint32_t pf_en                   : 1;       /**< Power Fault Detected Enable */
-        uint32_t abp_en                  : 1;       /**< Attention Button Pressed Enable */
-#else
-        uint32_t abp_en                  : 1;
-        uint32_t pf_en                   : 1;
-        uint32_t mrls_en                 : 1;
-        uint32_t pd_en                   : 1;
-        uint32_t ccint_en                : 1;
-        uint32_t hpint_en                : 1;
-        uint32_t aic                     : 2;
-        uint32_t pic                     : 2;
-        uint32_t pcc                     : 1;
-        uint32_t emic                    : 1;
-        uint32_t dlls_en                 : 1;
-        uint32_t reserved_13_15          : 3;
-        uint32_t abp_d                   : 1;
-        uint32_t pf_d                    : 1;
-        uint32_t mrls_c                  : 1;
-        uint32_t pd_c                    : 1;
-        uint32_t ccint_d                 : 1;
-        uint32_t mrlss                   : 1;
-        uint32_t pds                     : 1;
-        uint32_t emis                    : 1;
-        uint32_t dlls_c                  : 1;
-        uint32_t reserved_25_31          : 7;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg034_s         cn52xx;
-    struct cvmx_pciercx_cfg034_s         cn52xxp1;
-    struct cvmx_pciercx_cfg034_s         cn56xx;
-    struct cvmx_pciercx_cfg034_s         cn56xxp1;
-} cvmx_pciercx_cfg034_t;
-
-
-/**
- * cvmx_pcierc#_cfg035
- *
- * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space
- * (Root Control Register/Root Capabilities Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg035_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_17_31          : 15;
-        uint32_t crssv                   : 1;       /**< CRS Software Visibility
-                                                         Not supported, hardwired to 0x0. */
-        uint32_t reserved_5_15           : 11;
-        uint32_t crssve                  : 1;       /**< CRS Software Visibility Enable
-                                                         Not supported, hardwired to 0x0. */
-        uint32_t pmeie                   : 1;       /**< PME Interrupt Enable */
-        uint32_t sefee                   : 1;       /**< System Error on Fatal Error Enable */
-        uint32_t senfee                  : 1;       /**< System Error on Non-fatal Error Enable */
-        uint32_t secee                   : 1;       /**< System Error on Correctable Error Enable */
-#else
-        uint32_t secee                   : 1;
-        uint32_t senfee                  : 1;
-        uint32_t sefee                   : 1;
-        uint32_t pmeie                   : 1;
-        uint32_t crssve                  : 1;
-        uint32_t reserved_5_15           : 11;
-        uint32_t crssv                   : 1;
-        uint32_t reserved_17_31          : 15;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg035_s         cn52xx;
-    struct cvmx_pciercx_cfg035_s         cn52xxp1;
-    struct cvmx_pciercx_cfg035_s         cn56xx;
-    struct cvmx_pciercx_cfg035_s         cn56xxp1;
-} cvmx_pciercx_cfg035_t;
-
-
-/**
- * cvmx_pcierc#_cfg036
- *
- * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space
- * (Root Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg036_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_18_31          : 14;
-        uint32_t pme_pend                : 1;       /**< PME Pending */
-        uint32_t pme_stat                : 1;       /**< PME Status */
-        uint32_t pme_rid                 : 16;      /**< PME Requester ID */
-#else
-        uint32_t pme_rid                 : 16;
-        uint32_t pme_stat                : 1;
-        uint32_t pme_pend                : 1;
-        uint32_t reserved_18_31          : 14;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg036_s         cn52xx;
-    struct cvmx_pciercx_cfg036_s         cn52xxp1;
-    struct cvmx_pciercx_cfg036_s         cn56xx;
-    struct cvmx_pciercx_cfg036_s         cn56xxp1;
-} cvmx_pciercx_cfg036_t;
-
-
-/**
- * cvmx_pcierc#_cfg037
- *
- * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space
- * (Device Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg037_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t ctds                    : 1;       /**< Completion Timeout Disable Supported */
-        uint32_t ctrs                    : 4;       /**< Completion Timeout Ranges Supported
-                                                         Value of 0 indicates that Completion Timeout Programming
-                                                         is not supported.
-                                                         Completion timeout is 16.7ms. */
-#else
-        uint32_t ctrs                    : 4;
-        uint32_t ctds                    : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg037_s         cn52xx;
-    struct cvmx_pciercx_cfg037_s         cn52xxp1;
-    struct cvmx_pciercx_cfg037_s         cn56xx;
-    struct cvmx_pciercx_cfg037_s         cn56xxp1;
-} cvmx_pciercx_cfg037_t;
-
-
-/**
- * cvmx_pcierc#_cfg038
- *
- * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space
- * (Device Control 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg038_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t ctd                     : 1;       /**< Completion Timeout Disable */
-        uint32_t ctv                     : 4;       /**< Completion Timeout Value
-                                                         Completion Timeout Programming is not supported
-                                                         Completion timeout is 16.7ms. */
-#else
-        uint32_t ctv                     : 4;
-        uint32_t ctd                     : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg038_s         cn52xx;
-    struct cvmx_pciercx_cfg038_s         cn52xxp1;
-    struct cvmx_pciercx_cfg038_s         cn56xx;
-    struct cvmx_pciercx_cfg038_s         cn56xxp1;
-} cvmx_pciercx_cfg038_t;
-
-
-/**
- * cvmx_pcierc#_cfg039
- *
- * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space
- * (Link Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg039_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg039_s         cn52xx;
-    struct cvmx_pciercx_cfg039_s         cn52xxp1;
-    struct cvmx_pciercx_cfg039_s         cn56xx;
-    struct cvmx_pciercx_cfg039_s         cn56xxp1;
-} cvmx_pciercx_cfg039_t;
-
-
-/**
- * cvmx_pcierc#_cfg040
- *
- * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space
- * (Link Control 2 Register/Link Status 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg040_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg040_s         cn52xx;
-    struct cvmx_pciercx_cfg040_s         cn52xxp1;
-    struct cvmx_pciercx_cfg040_s         cn56xx;
-    struct cvmx_pciercx_cfg040_s         cn56xxp1;
-} cvmx_pciercx_cfg040_t;
-
-
-/**
- * cvmx_pcierc#_cfg041
- *
- * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space
- * (Slot Capabilities 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg041_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg041_s         cn52xx;
-    struct cvmx_pciercx_cfg041_s         cn52xxp1;
-    struct cvmx_pciercx_cfg041_s         cn56xx;
-    struct cvmx_pciercx_cfg041_s         cn56xxp1;
-} cvmx_pciercx_cfg041_t;
-
-
-/**
- * cvmx_pcierc#_cfg042
- *
- * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space
- * (Slot Control 2 Register/Slot Status 2 Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg042_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_0_31           : 32;
-#else
-        uint32_t reserved_0_31           : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg042_s         cn52xx;
-    struct cvmx_pciercx_cfg042_s         cn52xxp1;
-    struct cvmx_pciercx_cfg042_s         cn56xx;
-    struct cvmx_pciercx_cfg042_s         cn56xxp1;
-} cvmx_pciercx_cfg042_t;
-
-
-/**
- * cvmx_pcierc#_cfg064
- *
- * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space
- * (PCI Express Enhanced Capability Header)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg064_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t nco                     : 12;      /**< Next Capability Offset */
-        uint32_t cv                      : 4;       /**< Capability Version */
-        uint32_t pcieec                  : 16;      /**< PCIE Express Extended Capability */
-#else
-        uint32_t pcieec                  : 16;
-        uint32_t cv                      : 4;
-        uint32_t nco                     : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg064_s         cn52xx;
-    struct cvmx_pciercx_cfg064_s         cn52xxp1;
-    struct cvmx_pciercx_cfg064_s         cn56xx;
-    struct cvmx_pciercx_cfg064_s         cn56xxp1;
-} cvmx_pciercx_cfg064_t;
-
-
-/**
- * cvmx_pcierc#_cfg065
- *
- * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space
- * (Uncorrectable Error Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg065_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t ures                    : 1;       /**< Unsupported Request Error Status */
-        uint32_t ecrces                  : 1;       /**< ECRC Error Status */
-        uint32_t mtlps                   : 1;       /**< Malformed TLP Status */
-        uint32_t ros                     : 1;       /**< Receiver Overflow Status */
-        uint32_t ucs                     : 1;       /**< Unexpected Completion Status */
-        uint32_t cas                     : 1;       /**< Completer Abort Status */
-        uint32_t cts                     : 1;       /**< Completion Timeout Status */
-        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Status */
-        uint32_t ptlps                   : 1;       /**< Poisoned TLP Status */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdes                    : 1;       /**< Surprise Down Error Status (not supported) */
-        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Status */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpes                   : 1;
-        uint32_t sdes                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlps                   : 1;
-        uint32_t fcpes                   : 1;
-        uint32_t cts                     : 1;
-        uint32_t cas                     : 1;
-        uint32_t ucs                     : 1;
-        uint32_t ros                     : 1;
-        uint32_t mtlps                   : 1;
-        uint32_t ecrces                  : 1;
-        uint32_t ures                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg065_s         cn52xx;
-    struct cvmx_pciercx_cfg065_s         cn52xxp1;
-    struct cvmx_pciercx_cfg065_s         cn56xx;
-    struct cvmx_pciercx_cfg065_s         cn56xxp1;
-} cvmx_pciercx_cfg065_t;
-
-
-/**
- * cvmx_pcierc#_cfg066
- *
- * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space
- * (Uncorrectable Error Mask Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg066_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t urem                    : 1;       /**< Unsupported Request Error Mask */
-        uint32_t ecrcem                  : 1;       /**< ECRC Error Mask */
-        uint32_t mtlpm                   : 1;       /**< Malformed TLP Mask */
-        uint32_t rom                     : 1;       /**< Receiver Overflow Mask */
-        uint32_t ucm                     : 1;       /**< Unexpected Completion Mask */
-        uint32_t cam                     : 1;       /**< Completer Abort Mask */
-        uint32_t ctm                     : 1;       /**< Completion Timeout Mask */
-        uint32_t fcpem                   : 1;       /**< Flow Control Protocol Error Mask */
-        uint32_t ptlpm                   : 1;       /**< Poisoned TLP Mask */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdem                    : 1;       /**< Surprise Down Error Mask (not supported) */
-        uint32_t dlpem                   : 1;       /**< Data Link Protocol Error Mask */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpem                   : 1;
-        uint32_t sdem                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlpm                   : 1;
-        uint32_t fcpem                   : 1;
-        uint32_t ctm                     : 1;
-        uint32_t cam                     : 1;
-        uint32_t ucm                     : 1;
-        uint32_t rom                     : 1;
-        uint32_t mtlpm                   : 1;
-        uint32_t ecrcem                  : 1;
-        uint32_t urem                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg066_s         cn52xx;
-    struct cvmx_pciercx_cfg066_s         cn52xxp1;
-    struct cvmx_pciercx_cfg066_s         cn56xx;
-    struct cvmx_pciercx_cfg066_s         cn56xxp1;
-} cvmx_pciercx_cfg066_t;
-
-
-/**
- * cvmx_pcierc#_cfg067
- *
- * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space
- * (Uncorrectable Error Severity Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg067_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t ures                    : 1;       /**< Unsupported Request Error Severity */
-        uint32_t ecrces                  : 1;       /**< ECRC Error Severity */
-        uint32_t mtlps                   : 1;       /**< Malformed TLP Severity */
-        uint32_t ros                     : 1;       /**< Receiver Overflow Severity */
-        uint32_t ucs                     : 1;       /**< Unexpected Completion Severity */
-        uint32_t cas                     : 1;       /**< Completer Abort Severity */
-        uint32_t cts                     : 1;       /**< Completion Timeout Severity */
-        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Severity */
-        uint32_t ptlps                   : 1;       /**< Poisoned TLP Severity */
-        uint32_t reserved_6_11           : 6;
-        uint32_t sdes                    : 1;       /**< Surprise Down Error Severity (not supported) */
-        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Severity */
-        uint32_t reserved_0_3            : 4;
-#else
-        uint32_t reserved_0_3            : 4;
-        uint32_t dlpes                   : 1;
-        uint32_t sdes                    : 1;
-        uint32_t reserved_6_11           : 6;
-        uint32_t ptlps                   : 1;
-        uint32_t fcpes                   : 1;
-        uint32_t cts                     : 1;
-        uint32_t cas                     : 1;
-        uint32_t ucs                     : 1;
-        uint32_t ros                     : 1;
-        uint32_t mtlps                   : 1;
-        uint32_t ecrces                  : 1;
-        uint32_t ures                    : 1;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg067_s         cn52xx;
-    struct cvmx_pciercx_cfg067_s         cn52xxp1;
-    struct cvmx_pciercx_cfg067_s         cn56xx;
-    struct cvmx_pciercx_cfg067_s         cn56xxp1;
-} cvmx_pciercx_cfg067_t;
-
-
-/**
- * cvmx_pcierc#_cfg068
- *
- * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space
- * (Correctable Error Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg068_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_14_31          : 18;
-        uint32_t anfes                   : 1;       /**< Advisory Non-Fatal Error Status */
-        uint32_t rtts                    : 1;       /**< Replay Timer Timeout Status */
-        uint32_t reserved_9_11           : 3;
-        uint32_t rnrs                    : 1;       /**< REPLAY_NUM Rollover Status */
-        uint32_t bdllps                  : 1;       /**< Bad DLLP Status */
-        uint32_t btlps                   : 1;       /**< Bad TLP Status */
-        uint32_t reserved_1_5            : 5;
-        uint32_t res                     : 1;       /**< Receiver Error Status */
-#else
-        uint32_t res                     : 1;
-        uint32_t reserved_1_5            : 5;
-        uint32_t btlps                   : 1;
-        uint32_t bdllps                  : 1;
-        uint32_t rnrs                    : 1;
-        uint32_t reserved_9_11           : 3;
-        uint32_t rtts                    : 1;
-        uint32_t anfes                   : 1;
-        uint32_t reserved_14_31          : 18;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg068_s         cn52xx;
-    struct cvmx_pciercx_cfg068_s         cn52xxp1;
-    struct cvmx_pciercx_cfg068_s         cn56xx;
-    struct cvmx_pciercx_cfg068_s         cn56xxp1;
-} cvmx_pciercx_cfg068_t;
-
-
-/**
- * cvmx_pcierc#_cfg069
- *
- * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space
- * (Correctable Error Mask Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg069_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_14_31          : 18;
-        uint32_t anfem                   : 1;       /**< Advisory Non-Fatal Error Mask */
-        uint32_t rttm                    : 1;       /**< Replay Timer Timeout Mask */
-        uint32_t reserved_9_11           : 3;
-        uint32_t rnrm                    : 1;       /**< REPLAY_NUM Rollover Mask */
-        uint32_t bdllpm                  : 1;       /**< Bad DLLP Mask */
-        uint32_t btlpm                   : 1;       /**< Bad TLP Mask */
-        uint32_t reserved_1_5            : 5;
-        uint32_t rem                     : 1;       /**< Receiver Error Mask */
-#else
-        uint32_t rem                     : 1;
-        uint32_t reserved_1_5            : 5;
-        uint32_t btlpm                   : 1;
-        uint32_t bdllpm                  : 1;
-        uint32_t rnrm                    : 1;
-        uint32_t reserved_9_11           : 3;
-        uint32_t rttm                    : 1;
-        uint32_t anfem                   : 1;
-        uint32_t reserved_14_31          : 18;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg069_s         cn52xx;
-    struct cvmx_pciercx_cfg069_s         cn52xxp1;
-    struct cvmx_pciercx_cfg069_s         cn56xx;
-    struct cvmx_pciercx_cfg069_s         cn56xxp1;
-} cvmx_pciercx_cfg069_t;
-
-
-/**
- * cvmx_pcierc#_cfg070
- *
- * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space
- * (Advanced Capabilities and Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg070_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t ce                      : 1;       /**< ECRC Check Enable */
-        uint32_t cc                      : 1;       /**< ECRC Check Capable */
-        uint32_t ge                      : 1;       /**< ECRC Generation Enable */
-        uint32_t gc                      : 1;       /**< ECRC Generation Capability */
-        uint32_t fep                     : 5;       /**< First Error Pointer */
-#else
-        uint32_t fep                     : 5;
-        uint32_t gc                      : 1;
-        uint32_t ge                      : 1;
-        uint32_t cc                      : 1;
-        uint32_t ce                      : 1;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg070_s         cn52xx;
-    struct cvmx_pciercx_cfg070_s         cn52xxp1;
-    struct cvmx_pciercx_cfg070_s         cn56xx;
-    struct cvmx_pciercx_cfg070_s         cn56xxp1;
-} cvmx_pciercx_cfg070_t;
-
-
-/**
- * cvmx_pcierc#_cfg071
- *
- * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space
- *                  (Header Log Register 1)
- * 
- * The Header Log registers collect the header for the TLP corresponding to a detected error.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg071_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword1                  : 32;      /**< Header Log Register (first DWORD) */
-#else
-        uint32_t dword1                  : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg071_s         cn52xx;
-    struct cvmx_pciercx_cfg071_s         cn52xxp1;
-    struct cvmx_pciercx_cfg071_s         cn56xx;
-    struct cvmx_pciercx_cfg071_s         cn56xxp1;
-} cvmx_pciercx_cfg071_t;
-
-
-/**
- * cvmx_pcierc#_cfg072
- *
- * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space
- *                  (Header Log Register 2)
- * 
- * The Header Log registers collect the header for the TLP corresponding to a detected error.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg072_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword2                  : 32;      /**< Header Log Register (second DWORD) */
-#else
-        uint32_t dword2                  : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg072_s         cn52xx;
-    struct cvmx_pciercx_cfg072_s         cn52xxp1;
-    struct cvmx_pciercx_cfg072_s         cn56xx;
-    struct cvmx_pciercx_cfg072_s         cn56xxp1;
-} cvmx_pciercx_cfg072_t;
-
-
-/**
- * cvmx_pcierc#_cfg073
- *
- * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space
- *                  (Header Log Register 3)
- * 
- * The Header Log registers collect the header for the TLP corresponding to a detected error.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg073_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword3                  : 32;      /**< Header Log Register (third DWORD) */
-#else
-        uint32_t dword3                  : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg073_s         cn52xx;
-    struct cvmx_pciercx_cfg073_s         cn52xxp1;
-    struct cvmx_pciercx_cfg073_s         cn56xx;
-    struct cvmx_pciercx_cfg073_s         cn56xxp1;
-} cvmx_pciercx_cfg073_t;
-
-
-/**
- * cvmx_pcierc#_cfg074
- *
- * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space
- *                  (Header Log Register 4)
- * 
- * The Header Log registers collect the header for the TLP corresponding to a detected error.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg074_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dword4                  : 32;      /**< Header Log Register (fourth DWORD) */
-#else
-        uint32_t dword4                  : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg074_s         cn52xx;
-    struct cvmx_pciercx_cfg074_s         cn52xxp1;
-    struct cvmx_pciercx_cfg074_s         cn56xx;
-    struct cvmx_pciercx_cfg074_s         cn56xxp1;
-} cvmx_pciercx_cfg074_t;
-
-
-/**
- * cvmx_pcierc#_cfg075
- *
- * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space
- * (Root Error Command Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg075_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_3_31           : 29;
-        uint32_t fere                    : 1;       /**< Fatal Error Reporting Enable */
-        uint32_t nfere                   : 1;       /**< Non-Fatal Error Reporting Enable */
-        uint32_t cere                    : 1;       /**< Correctable Error Reporting Enable */
-#else
-        uint32_t cere                    : 1;
-        uint32_t nfere                   : 1;
-        uint32_t fere                    : 1;
-        uint32_t reserved_3_31           : 29;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg075_s         cn52xx;
-    struct cvmx_pciercx_cfg075_s         cn52xxp1;
-    struct cvmx_pciercx_cfg075_s         cn56xx;
-    struct cvmx_pciercx_cfg075_s         cn56xxp1;
-} cvmx_pciercx_cfg075_t;
-
-
-/**
- * cvmx_pcierc#_cfg076
- *
- * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space
- * (Root Error Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg076_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t aeimn                   : 5;       /**< Advanced Error Interrupt Message Number,
-                                                         writable through the DBI */
-        uint32_t reserved_7_26           : 20;
-        uint32_t femr                    : 1;       /**< Fatal Error Messages Received */
-        uint32_t nfemr                   : 1;       /**< Non-Fatal Error Messages Received */
-        uint32_t fuf                     : 1;       /**< First Uncorrectable Fatal */
-        uint32_t multi_efnfr             : 1;       /**< Multiple ERR_FATAL/NONFATAL Received */
-        uint32_t efnfr                   : 1;       /**< ERR_FATAL/NONFATAL Received */
-        uint32_t multi_ecr               : 1;       /**< Multiple ERR_COR Received */
-        uint32_t ecr                     : 1;       /**< ERR_COR Received */
-#else
-        uint32_t ecr                     : 1;
-        uint32_t multi_ecr               : 1;
-        uint32_t efnfr                   : 1;
-        uint32_t multi_efnfr             : 1;
-        uint32_t fuf                     : 1;
-        uint32_t nfemr                   : 1;
-        uint32_t femr                    : 1;
-        uint32_t reserved_7_26           : 20;
-        uint32_t aeimn                   : 5;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg076_s         cn52xx;
-    struct cvmx_pciercx_cfg076_s         cn52xxp1;
-    struct cvmx_pciercx_cfg076_s         cn56xx;
-    struct cvmx_pciercx_cfg076_s         cn56xxp1;
-} cvmx_pciercx_cfg076_t;
-
-
-/**
- * cvmx_pcierc#_cfg077
- *
- * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space
- * (Error Source Identification Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg077_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t efnfsi                  : 16;      /**< ERR_FATAL/NONFATAL Source Identification */
-        uint32_t ecsi                    : 16;      /**< ERR_COR Source Identification */
-#else
-        uint32_t ecsi                    : 16;
-        uint32_t efnfsi                  : 16;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg077_s         cn52xx;
-    struct cvmx_pciercx_cfg077_s         cn52xxp1;
-    struct cvmx_pciercx_cfg077_s         cn56xx;
-    struct cvmx_pciercx_cfg077_s         cn56xxp1;
-} cvmx_pciercx_cfg077_t;
-
-
-/**
- * cvmx_pcierc#_cfg448
- *
- * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space
- * (Ack Latency Timer and Replay Timer Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg448_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t rtl                     : 16;      /**< Replay Time Limit
-                                                         The replay timer expires when it reaches this limit. The PCI
-                                                         Express bus initiates a replay upon reception of a Nak or when
-                                                         the replay timer expires.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
-        uint32_t rtltl                   : 16;      /**< Round Trip Latency Time Limit
-                                                         The Ack/Nak latency timer expires when it reaches this limit.
-                                                         The default is then updated based on the Negotiated Link Width
-                                                         and Max_Payload_Size. */
-#else
-        uint32_t rtltl                   : 16;
-        uint32_t rtl                     : 16;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg448_s         cn52xx;
-    struct cvmx_pciercx_cfg448_s         cn52xxp1;
-    struct cvmx_pciercx_cfg448_s         cn56xx;
-    struct cvmx_pciercx_cfg448_s         cn56xxp1;
-} cvmx_pciercx_cfg448_t;
-
-
-/**
- * cvmx_pcierc#_cfg449
- *
- * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space
- * (Other Message Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg449_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t omr                     : 32;      /**< Other Message Register
-                                                         This register can be used for either of the following purposes:
-                                                         o To send a specific PCI Express Message, the application
-                                                           writes the payload of the Message into this register, then
-                                                           sets bit 0 of the Port Link Control Register to send the
-                                                           Message.
-                                                         o To store a corruption pattern for corrupting the LCRC on all
-                                                           TLPs, the application places a 32-bit corruption pattern into
-                                                           this register and enables this function by setting bit 25 of
-                                                           the Port Link Control Register. When enabled, the transmit
-                                                           LCRC result is XOR'd with this pattern before inserting
-                                                           it into the packet. */
-#else
-        uint32_t omr                     : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg449_s         cn52xx;
-    struct cvmx_pciercx_cfg449_s         cn52xxp1;
-    struct cvmx_pciercx_cfg449_s         cn56xx;
-    struct cvmx_pciercx_cfg449_s         cn56xxp1;
-} cvmx_pciercx_cfg449_t;
-
-
-/**
- * cvmx_pcierc#_cfg450
- *
- * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space
- * (Port Force Link Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg450_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t lpec                    : 8;       /**< Low Power Entrance Count
-                                                         The Power Management state will wait for this many clock cycles
-                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
-                                                         Power State (PS) field register to go low-power. This register
-                                                         is intended for applications that do not let the PCI Express
-                                                         bus handle a completion for configuration request to the
-                                                         Power Management Control and Status (PCIE_CFG017) register. */
-        uint32_t reserved_22_23          : 2;
-        uint32_t link_state              : 6;       /**< Link State
-                                                         The Link state that the PCI Express Bus will be forced to
-                                                         when bit 15 (Force Link) is set.
-                                                         State encoding:
-                                                         o DETECT_QUIET              00h
-                                                         o DETECT_ACT                01h
-                                                         o POLL_ACTIVE               02h
-                                                         o POLL_COMPLIANCE           03h
-                                                         o POLL_CONFIG               04h
-                                                         o PRE_DETECT_QUIET          05h
-                                                         o DETECT_WAIT               06h
-                                                         o CFG_LINKWD_START          07h
-                                                         o CFG_LINKWD_ACEPT          08h
-                                                         o CFG_LANENUM_WAIT          09h
-                                                         o CFG_LANENUM_ACEPT         0Ah
-                                                         o CFG_COMPLETE              0Bh
-                                                         o CFG_IDLE                  0Ch
-                                                         o RCVRY_LOCK                0Dh
-                                                         o RCVRY_SPEED               0Eh
-                                                         o RCVRY_RCVRCFG             0Fh
-                                                         o RCVRY_IDLE                10h
-                                                         o L0                        11h
-                                                         o L0S                       12h
-                                                         o L123_SEND_EIDLE           13h
-                                                         o L1_IDLE                   14h
-                                                         o L2_IDLE                   15h
-                                                         o L2_WAKE                   16h
-                                                         o DISABLED_ENTRY            17h
-                                                         o DISABLED_IDLE             18h
-                                                         o DISABLED                  19h
-                                                         o LPBK_ENTRY                1Ah
-                                                         o LPBK_ACTIVE               1Bh
-                                                         o LPBK_EXIT                 1Ch
-                                                         o LPBK_EXIT_TIMEOUT         1Dh
-                                                         o HOT_RESET_ENTRY           1Eh
-                                                         o HOT_RESET                 1Fh */
-        uint32_t force_link              : 1;       /**< Force Link
-                                                         Forces the Link to the state specified by the Link State field.
-                                                         The Force Link pulse will trigger Link re-negotiation.
-                                                         * As the The Force Link is a pulse, writing a 1 to it does
-                                                           trigger the forced link state event, even thought reading it
-                                                           always returns a 0. */
-        uint32_t reserved_8_14           : 7;
-        uint32_t link_num                : 8;       /**< Link Number */
-#else
-        uint32_t link_num                : 8;
-        uint32_t reserved_8_14           : 7;
-        uint32_t force_link              : 1;
-        uint32_t link_state              : 6;
-        uint32_t reserved_22_23          : 2;
-        uint32_t lpec                    : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg450_s         cn52xx;
-    struct cvmx_pciercx_cfg450_s         cn52xxp1;
-    struct cvmx_pciercx_cfg450_s         cn56xx;
-    struct cvmx_pciercx_cfg450_s         cn56xxp1;
-} cvmx_pciercx_cfg450_t;
-
-
-/**
- * cvmx_pcierc#_cfg451
- *
- * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space
- * (Ack Frequency Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg451_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t l1el                    : 3;       /**< L1 Entrance Latency
-                                                         Values correspond to:
-                                                         o 000: 1 ms
-                                                         o 001: 2 ms
-                                                         o 010: 4 ms
-                                                         o 011: 8 ms
-                                                         o 100: 16 ms
-                                                         o 101: 32 ms
-                                                         o 110 or 111: 64 ms */
-        uint32_t l0el                    : 3;       /**< L0s Entrance Latency
-                                                         Values correspond to:
-                                                         o 000: 1 ms
-                                                         o 001: 2 ms
-                                                         o 010: 3 ms
-                                                         o 011: 4 ms
-                                                         o 100: 5 ms
-                                                         o 101: 6 ms
-                                                         o 110 or 111: 7 ms */
-        uint32_t n_fts_cc                : 8;       /**< N_FTS when common clock is used.
-                                                         The number of Fast Training Sequence ordered sets to be
-                                                         transmitted when transitioning from L0s to L0. The maximum
-                                                         number of FTS ordered-sets that a component can request is 255.
-                                                          Note: The core does not support a value of zero; a value of
-                                                                zero can cause the LTSSM to go into the recovery state
-                                                                when exiting from L0s. */
-        uint32_t n_fts                   : 8;       /**< N_FTS
-                                                         The number of Fast Training Sequence ordered sets to be
-                                                         transmitted when transitioning from L0s to L0. The maximum
-                                                         number of FTS ordered-sets that a component can request is 255.
-                                                         Note: The core does not support a value of zero; a value of
-                                                               zero can cause the LTSSM to go into the recovery state
-                                                               when exiting from L0s. */
-        uint32_t ack_freq                : 8;       /**< Ack Frequency
-                                                         The number of pending Ack's specified here (up to 255) before
-                                                         sending an Ack. */
-#else
-        uint32_t ack_freq                : 8;
-        uint32_t n_fts                   : 8;
-        uint32_t n_fts_cc                : 8;
-        uint32_t l0el                    : 3;
-        uint32_t l1el                    : 3;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg451_s         cn52xx;
-    struct cvmx_pciercx_cfg451_s         cn52xxp1;
-    struct cvmx_pciercx_cfg451_s         cn56xx;
-    struct cvmx_pciercx_cfg451_s         cn56xxp1;
-} cvmx_pciercx_cfg451_t;
-
-
-/**
- * cvmx_pcierc#_cfg452
- *
- * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space
- * (Port Link Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg452_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t eccrc                   : 1;       /**< Enable Corrupted CRC
-                                                         Causes corrupt LCRC for TLPs when set,
-                                                         using the pattern contained in the Other Message register.
-                                                         This is a test feature, not to be used in normal operation. */
-        uint32_t reserved_22_24          : 3;
-        uint32_t lme                     : 6;       /**< Link Mode Enable
-                                                         o 000001: x1
-                                                         o 000011: x2
-                                                         o 000111: x4
-                                                         o 001111: x8
-                                                         o 011111: x16 (not supported)
-                                                         o 111111: x32 (not supported)
-                                                         This field indicates the MAXIMUM number of lanes supported
-                                                         by the PCIe port. It is normally set to 0xF or 0x7 depending
-                                                         on the value of the QLM_CFG bits (0xF when QLM_CFG == 0
-                                                         otherwise 0x7). The value can be set less than 0xF or 0x7
-                                                         to limit the number of lanes the PCIe will attempt to use.
-                                                         The programming of this field needs to be done by SW BEFORE
-                                                         enabling the link. See also MLW.
-                                                         (Note: The value of this field does NOT indicate the number
-                                                          of lanes in use by the PCIe. LME sets the max number of lanes
-                                                          in the PCIe core that COULD be used. As per the PCIe specs,
-                                                          the PCIe core can negotiate a smaller link width, so all
-                                                          of x8, x4, x2, and x1 are supported when LME=0xF,
-                                                          for example.) */
-        uint32_t reserved_8_15           : 8;
-        uint32_t flm                     : 1;       /**< Fast Link Mode
-                                                         Sets all internal timers to fast mode for simulation purposes. */
-        uint32_t reserved_6_6            : 1;
-        uint32_t dllle                   : 1;       /**< DLL Link Enable
-                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
-                                                         Express bus does not transmit InitFC DLLPs and does not
-                                                         establish a Link. */
-        uint32_t reserved_4_4            : 1;
-        uint32_t ra                      : 1;       /**< Reset Assert
-                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
-                                                         state (downstream port only). */
-        uint32_t le                      : 1;       /**< Loopback Enable
-                                                         Turns on loopback. */
-        uint32_t sd                      : 1;       /**< Scramble Disable
-                                                         Turns off data scrambling. */
-        uint32_t omr                     : 1;       /**< Other Message Request
-                                                         When software writes a `1' to this bit, the PCI Express bus
-                                                         transmits the Message contained in the Other Message register. */
-#else
-        uint32_t omr                     : 1;
-        uint32_t sd                      : 1;
-        uint32_t le                      : 1;
-        uint32_t ra                      : 1;
-        uint32_t reserved_4_4            : 1;
-        uint32_t dllle                   : 1;
-        uint32_t reserved_6_6            : 1;
-        uint32_t flm                     : 1;
-        uint32_t reserved_8_15           : 8;
-        uint32_t lme                     : 6;
-        uint32_t reserved_22_24          : 3;
-        uint32_t eccrc                   : 1;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg452_s         cn52xx;
-    struct cvmx_pciercx_cfg452_s         cn52xxp1;
-    struct cvmx_pciercx_cfg452_s         cn56xx;
-    struct cvmx_pciercx_cfg452_s         cn56xxp1;
-} cvmx_pciercx_cfg452_t;
-
-
-/**
- * cvmx_pcierc#_cfg453
- *
- * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space
- * (Lane Skew Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg453_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dlld                    : 1;       /**< Disable Lane-to-Lane Deskew
-                                                         Disables the internal Lane-to-Lane deskew logic. */
-        uint32_t reserved_26_30          : 5;
-        uint32_t ack_nak                 : 1;       /**< Ack/Nak Disable
-                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
-        uint32_t fcd                     : 1;       /**< Flow Control Disable
-                                                         Prevents the PCI Express bus from sending FC DLLPs. */
-        uint32_t ilst                    : 24;      /**< Insert Lane Skew for Transmit (not supported for x16)
-                                                         Causes skew between lanes for test purposes. There are three
-                                                         bits per Lane. The value is in units of one symbol time. For
-                                                         example, the value 010b for a Lane forces a skew of two symbol
-                                                         times for that Lane. The maximum skew value for any Lane is 5
-                                                         symbol times. */
-#else
-        uint32_t ilst                    : 24;
-        uint32_t fcd                     : 1;
-        uint32_t ack_nak                 : 1;
-        uint32_t reserved_26_30          : 5;
-        uint32_t dlld                    : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg453_s         cn52xx;
-    struct cvmx_pciercx_cfg453_s         cn52xxp1;
-    struct cvmx_pciercx_cfg453_s         cn56xx;
-    struct cvmx_pciercx_cfg453_s         cn56xxp1;
-} cvmx_pciercx_cfg453_t;
-
-
-/**
- * cvmx_pcierc#_cfg454
- *
- * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space
- * (Symbol Number Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg454_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_29_31          : 3;
-        uint32_t tmfcwt                  : 5;       /**< Timer Modifier for Flow Control Watchdog Timer
-                                                         Increases the timer value for the Flow Control watchdog timer,
-                                                         in increments of 16 clock cycles. */
-        uint32_t tmanlt                  : 5;       /**< Timer Modifier for Ack/Nak Latency Timer
-                                                         Increases the timer value for the Ack/Nak latency timer, in
-                                                         increments of 64 clock cycles. */
-        uint32_t tmrt                    : 5;       /**< Timer Modifier for Replay Timer
-                                                         Increases the timer value for the replay timer, in increments
-                                                         of 64 clock cycles. */
-        uint32_t reserved_11_13          : 3;
-        uint32_t nskps                   : 3;       /**< Number of SKP Symbols */
-        uint32_t reserved_4_7            : 4;
-        uint32_t ntss                    : 4;       /**< Number of TS Symbols
-                                                         Sets the number of TS identifier symbols that are sent in TS1
-                                                         and TS2 ordered sets. */
-#else
-        uint32_t ntss                    : 4;
-        uint32_t reserved_4_7            : 4;
-        uint32_t nskps                   : 3;
-        uint32_t reserved_11_13          : 3;
-        uint32_t tmrt                    : 5;
-        uint32_t tmanlt                  : 5;
-        uint32_t tmfcwt                  : 5;
-        uint32_t reserved_29_31          : 3;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg454_s         cn52xx;
-    struct cvmx_pciercx_cfg454_s         cn52xxp1;
-    struct cvmx_pciercx_cfg454_s         cn56xx;
-    struct cvmx_pciercx_cfg454_s         cn56xxp1;
-} cvmx_pciercx_cfg454_t;
-
-
-/**
- * cvmx_pcierc#_cfg455
- *
- * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space
- * (Symbol Timer Register/Filter Mask Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg455_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t m_cfg0_filt             : 1;       /**< Mask filtering of received Configuration Requests (RC mode only) */
-        uint32_t m_io_filt               : 1;       /**< Mask filtering of received I/O Requests (RC mode only) */
-        uint32_t msg_ctrl                : 1;       /**< Message Control
-                                                         The application must not change this field. */
-        uint32_t m_cpl_ecrc_filt         : 1;       /**< Mask ECRC error filtering for Completions */
-        uint32_t m_ecrc_filt             : 1;       /**< Mask ECRC error filtering */
-        uint32_t m_cpl_len_err           : 1;       /**< Mask Length mismatch error for received Completions */
-        uint32_t m_cpl_attr_err          : 1;       /**< Mask Attributes mismatch error for received Completions */
-        uint32_t m_cpl_tc_err            : 1;       /**< Mask Traffic Class mismatch error for received Completions */
-        uint32_t m_cpl_fun_err           : 1;       /**< Mask function mismatch error for received Completions */
-        uint32_t m_cpl_rid_err           : 1;       /**< Mask Requester ID mismatch error for received Completions */
-        uint32_t m_cpl_tag_err           : 1;       /**< Mask Tag error rules for received Completions */
-        uint32_t m_lk_filt               : 1;       /**< Mask Locked Request filtering */
-        uint32_t m_cfg1_filt             : 1;       /**< Mask Type 1 Configuration Request filtering */
-        uint32_t m_bar_match             : 1;       /**< Mask BAR match filtering */
-        uint32_t m_pois_filt             : 1;       /**< Mask poisoned TLP filtering */
-        uint32_t m_fun                   : 1;       /**< Mask function */
-        uint32_t dfcwt                   : 1;       /**< Disable FC Watchdog Timer */
-        uint32_t reserved_11_14          : 4;
-        uint32_t skpiv                   : 11;      /**< SKP Interval Value */
-#else
-        uint32_t skpiv                   : 11;
-        uint32_t reserved_11_14          : 4;
-        uint32_t dfcwt                   : 1;
-        uint32_t m_fun                   : 1;
-        uint32_t m_pois_filt             : 1;
-        uint32_t m_bar_match             : 1;
-        uint32_t m_cfg1_filt             : 1;
-        uint32_t m_lk_filt               : 1;
-        uint32_t m_cpl_tag_err           : 1;
-        uint32_t m_cpl_rid_err           : 1;
-        uint32_t m_cpl_fun_err           : 1;
-        uint32_t m_cpl_tc_err            : 1;
-        uint32_t m_cpl_attr_err          : 1;
-        uint32_t m_cpl_len_err           : 1;
-        uint32_t m_ecrc_filt             : 1;
-        uint32_t m_cpl_ecrc_filt         : 1;
-        uint32_t msg_ctrl                : 1;
-        uint32_t m_io_filt               : 1;
-        uint32_t m_cfg0_filt             : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg455_s         cn52xx;
-    struct cvmx_pciercx_cfg455_s         cn52xxp1;
-    struct cvmx_pciercx_cfg455_s         cn56xx;
-    struct cvmx_pciercx_cfg455_s         cn56xxp1;
-} cvmx_pciercx_cfg455_t;
-
-
-/**
- * cvmx_pcierc#_cfg456
- *
- * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space
- * (Filter Mask Register 2)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg456_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_2_31           : 30;
-        uint32_t m_vend1_drp             : 1;       /**< Mask Vendor MSG Type 1 dropped silently */
-        uint32_t m_vend0_drp             : 1;       /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
-#else
-        uint32_t m_vend0_drp             : 1;
-        uint32_t m_vend1_drp             : 1;
-        uint32_t reserved_2_31           : 30;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg456_s         cn52xx;
-    struct cvmx_pciercx_cfg456_s         cn52xxp1;
-    struct cvmx_pciercx_cfg456_s         cn56xx;
-    struct cvmx_pciercx_cfg456_s         cn56xxp1;
-} cvmx_pciercx_cfg456_t;
-
-
-/**
- * cvmx_pcierc#_cfg458
- *
- * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space
- * (Debug Register 0)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg458_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dbg_info_l32            : 32;      /**< The value on cxpl_debug_info[31:0]. */
-#else
-        uint32_t dbg_info_l32            : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg458_s         cn52xx;
-    struct cvmx_pciercx_cfg458_s         cn52xxp1;
-    struct cvmx_pciercx_cfg458_s         cn56xx;
-    struct cvmx_pciercx_cfg458_s         cn56xxp1;
-} cvmx_pciercx_cfg458_t;
-
-
-/**
- * cvmx_pcierc#_cfg459
- *
- * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space
- * (Debug Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg459_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dbg_info_u32            : 32;      /**< The value on cxpl_debug_info[63:32]. */
-#else
-        uint32_t dbg_info_u32            : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg459_s         cn52xx;
-    struct cvmx_pciercx_cfg459_s         cn52xxp1;
-    struct cvmx_pciercx_cfg459_s         cn56xx;
-    struct cvmx_pciercx_cfg459_s         cn56xxp1;
-} cvmx_pciercx_cfg459_t;
-
-
-/**
- * cvmx_pcierc#_cfg460
- *
- * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space
- * (Transmit Posted FC Credit Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg460_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tphfcc                  : 8;       /**< Transmit Posted Header FC Credits
-                                                         The Posted Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tpdfcc                  : 12;      /**< Transmit Posted Data FC Credits
-                                                         The Posted Data credits advertised by the receiver at the other
-                                                         end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tpdfcc                  : 12;
-        uint32_t tphfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg460_s         cn52xx;
-    struct cvmx_pciercx_cfg460_s         cn52xxp1;
-    struct cvmx_pciercx_cfg460_s         cn56xx;
-    struct cvmx_pciercx_cfg460_s         cn56xxp1;
-} cvmx_pciercx_cfg460_t;
-
-
-/**
- * cvmx_pcierc#_cfg461
- *
- * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space
- * (Transmit Non-Posted FC Credit Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg461_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tchfcc                  : 8;       /**< Transmit Non-Posted Header FC Credits
-                                                         The Non-Posted Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tcdfcc                  : 12;      /**< Transmit Non-Posted Data FC Credits
-                                                         The Non-Posted Data credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tcdfcc                  : 12;
-        uint32_t tchfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg461_s         cn52xx;
-    struct cvmx_pciercx_cfg461_s         cn52xxp1;
-    struct cvmx_pciercx_cfg461_s         cn56xx;
-    struct cvmx_pciercx_cfg461_s         cn56xxp1;
-} cvmx_pciercx_cfg461_t;
-
-
-/**
- * cvmx_pcierc#_cfg462
- *
- * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space
- * (Transmit Completion FC Credit Status )
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg462_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t tchfcc                  : 8;       /**< Transmit Completion Header FC Credits
-                                                         The Completion Header credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-        uint32_t tcdfcc                  : 12;      /**< Transmit Completion Data FC Credits
-                                                         The Completion Data credits advertised by the receiver at the
-                                                         other end of the Link, updated with each UpdateFC DLLP. */
-#else
-        uint32_t tcdfcc                  : 12;
-        uint32_t tchfcc                  : 8;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg462_s         cn52xx;
-    struct cvmx_pciercx_cfg462_s         cn52xxp1;
-    struct cvmx_pciercx_cfg462_s         cn56xx;
-    struct cvmx_pciercx_cfg462_s         cn56xxp1;
-} cvmx_pciercx_cfg462_t;
-
-
-/**
- * cvmx_pcierc#_cfg463
- *
- * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space
- * (Queue Status)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg463_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_3_31           : 29;
-        uint32_t rqne                    : 1;       /**< Received Queue Not Empty
-                                                         Indicates there is data in one or more of the receive buffers. */
-        uint32_t trbne                   : 1;       /**< Transmit Retry Buffer Not Empty
-                                                         Indicates that there is data in the transmit retry buffer. */
-        uint32_t rtlpfccnr               : 1;       /**< Received TLP FC Credits Not Returned
-                                                         Indicates that the PCI Express bus has sent a TLP but has not
-                                                         yet received an UpdateFC DLLP indicating that the credits for
-                                                         that TLP have been restored by the receiver at the other end of
-                                                         the Link. */
-#else
-        uint32_t rtlpfccnr               : 1;
-        uint32_t trbne                   : 1;
-        uint32_t rqne                    : 1;
-        uint32_t reserved_3_31           : 29;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg463_s         cn52xx;
-    struct cvmx_pciercx_cfg463_s         cn52xxp1;
-    struct cvmx_pciercx_cfg463_s         cn56xx;
-    struct cvmx_pciercx_cfg463_s         cn56xxp1;
-} cvmx_pciercx_cfg463_t;
-
-
-/**
- * cvmx_pcierc#_cfg464
- *
- * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space
- * (VC Transmit Arbitration Register 1)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg464_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wrr_vc3                 : 8;       /**< WRR Weight for VC3 */
-        uint32_t wrr_vc2                 : 8;       /**< WRR Weight for VC2 */
-        uint32_t wrr_vc1                 : 8;       /**< WRR Weight for VC1 */
-        uint32_t wrr_vc0                 : 8;       /**< WRR Weight for VC0 */
-#else
-        uint32_t wrr_vc0                 : 8;
-        uint32_t wrr_vc1                 : 8;
-        uint32_t wrr_vc2                 : 8;
-        uint32_t wrr_vc3                 : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg464_s         cn52xx;
-    struct cvmx_pciercx_cfg464_s         cn52xxp1;
-    struct cvmx_pciercx_cfg464_s         cn56xx;
-    struct cvmx_pciercx_cfg464_s         cn56xxp1;
-} cvmx_pciercx_cfg464_t;
-
-
-/**
- * cvmx_pcierc#_cfg465
- *
- * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space
- * (VC Transmit Arbitration Register 2)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg465_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wrr_vc7                 : 8;       /**< WRR Weight for VC7 */
-        uint32_t wrr_vc6                 : 8;       /**< WRR Weight for VC6 */
-        uint32_t wrr_vc5                 : 8;       /**< WRR Weight for VC5 */
-        uint32_t wrr_vc4                 : 8;       /**< WRR Weight for VC4 */
-#else
-        uint32_t wrr_vc4                 : 8;
-        uint32_t wrr_vc5                 : 8;
-        uint32_t wrr_vc6                 : 8;
-        uint32_t wrr_vc7                 : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg465_s         cn52xx;
-    struct cvmx_pciercx_cfg465_s         cn52xxp1;
-    struct cvmx_pciercx_cfg465_s         cn56xx;
-    struct cvmx_pciercx_cfg465_s         cn56xxp1;
-} cvmx_pciercx_cfg465_t;
-
-
-/**
- * cvmx_pcierc#_cfg466
- *
- * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space
- * (VC0 Posted Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg466_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t rx_queue_order          : 1;       /**< VC Ordering for Receive Queues
-                                                         Determines the VC ordering rule for the receive queues, used
-                                                         only in the segmented-buffer configuration,
-                                                         writable through the DBI:
-                                                         o 1: Strict ordering, higher numbered VCs have higher priority
-                                                         o 0: Round robin
-                                                         However, the application must not change this field. */
-        uint32_t type_ordering           : 1;       /**< TLP Type Ordering for VC0
-                                                         Determines the TLP type ordering rule for VC0 receive queues,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI:
-                                                         o 1: Ordering of received TLPs follows the rules in
-                                                              PCI Express Base Specification, Revision 1.1
-                                                         o 0: Strict ordering for received TLPs: Posted, then
-                                                              Completion, then Non-Posted
-                                                         However, the application must not change this field. */
-        uint32_t reserved_24_29          : 6;
-        uint32_t queue_mode              : 3;       /**< VC0 Posted TLP Queue Mode
-                                                         The operating mode of the Posted receive queue for VC0, used
-                                                         only in the segmented-buffer configuration, writable through
-                                                         the DBI. However, the application must not change this field.
-                                                         Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Posted Header Credits
-                                                         The number of initial Posted header credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Posted Data Credits
-                                                         The number of initial Posted data credits for VC0, used for all
-                                                         receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_29          : 6;
-        uint32_t type_ordering           : 1;
-        uint32_t rx_queue_order          : 1;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg466_s         cn52xx;
-    struct cvmx_pciercx_cfg466_s         cn52xxp1;
-    struct cvmx_pciercx_cfg466_s         cn56xx;
-    struct cvmx_pciercx_cfg466_s         cn56xxp1;
-} cvmx_pciercx_cfg466_t;
-
-
-/**
- * cvmx_pcierc#_cfg467
- *
- * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space
- * (VC0 Non-Posted Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg467_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t queue_mode              : 3;       /**< VC0 Non-Posted TLP Queue Mode
-                                                         The operating mode of the Non-Posted receive queue for VC0,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI. Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Non-Posted Header Credits
-                                                         The number of initial Non-Posted header credits for VC0, used
-                                                         for all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Non-Posted Data Credits
-                                                         The number of initial Non-Posted data credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg467_s         cn52xx;
-    struct cvmx_pciercx_cfg467_s         cn52xxp1;
-    struct cvmx_pciercx_cfg467_s         cn56xx;
-    struct cvmx_pciercx_cfg467_s         cn56xxp1;
-} cvmx_pciercx_cfg467_t;
-
-
-/**
- * cvmx_pcierc#_cfg468
- *
- * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space
- * (VC0 Completion Receive Queue Control)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg468_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_24_31          : 8;
-        uint32_t queue_mode              : 3;       /**< VC0 Completion TLP Queue Mode
-                                                         The operating mode of the Completion receive queue for VC0,
-                                                         used only in the segmented-buffer configuration, writable
-                                                         through the DBI. Only one bit can be set at a time:
-                                                         o Bit 23: Bypass
-                                                         o Bit 22: Cut-through
-                                                         o Bit 21: Store-and-forward
-                                                         However, the application must not change this field. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t header_credits          : 8;       /**< VC0 Completion Header Credits
-                                                         The number of initial Completion header credits for VC0, used
-                                                         for all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t data_credits            : 12;      /**< VC0 Completion Data Credits
-                                                         The number of initial Completion data credits for VC0, used for
-                                                         all receive queue buffer configurations.
-                                                         This field is writable through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_credits            : 12;
-        uint32_t header_credits          : 8;
-        uint32_t reserved_20_20          : 1;
-        uint32_t queue_mode              : 3;
-        uint32_t reserved_24_31          : 8;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg468_s         cn52xx;
-    struct cvmx_pciercx_cfg468_s         cn52xxp1;
-    struct cvmx_pciercx_cfg468_s         cn56xx;
-    struct cvmx_pciercx_cfg468_s         cn56xxp1;
-} cvmx_pciercx_cfg468_t;
-
-
-/**
- * cvmx_pcierc#_cfg490
- *
- * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space
- * (VC0 Posted Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg490_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Posted Header Queue Depth
-                                                         Sets the number of entries in the Posted header queue for VC0
-                                                         when using the segmented-buffer configuration, writable through
-                                                         the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Posted Data Queue Depth
-                                                         Sets the number of entries in the Posted data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg490_s         cn52xx;
-    struct cvmx_pciercx_cfg490_s         cn52xxp1;
-    struct cvmx_pciercx_cfg490_s         cn56xx;
-    struct cvmx_pciercx_cfg490_s         cn56xxp1;
-} cvmx_pciercx_cfg490_t;
-
-
-/**
- * cvmx_pcierc#_cfg491
- *
- * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space
- * (VC0 Non-Posted Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg491_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Non-Posted Header Queue Depth
-                                                         Sets the number of entries in the Non-Posted header queue for
-                                                         VC0 when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Non-Posted Data Queue Depth
-                                                         Sets the number of entries in the Non-Posted data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg491_s         cn52xx;
-    struct cvmx_pciercx_cfg491_s         cn52xxp1;
-    struct cvmx_pciercx_cfg491_s         cn56xx;
-    struct cvmx_pciercx_cfg491_s         cn56xxp1;
-} cvmx_pciercx_cfg491_t;
-
-
-/**
- * cvmx_pcierc#_cfg492
- *
- * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space
- * (VC0 Completion Buffer Depth)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg492_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_26_31          : 6;
-        uint32_t header_depth            : 10;      /**< VC0 Completion Header Queue Depth
-                                                         Sets the number of entries in the Completion header queue for
-                                                         VC0 when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-        uint32_t reserved_14_15          : 2;
-        uint32_t data_depth              : 14;      /**< VC0 Completion Data Queue Depth
-                                                         Sets the number of entries in the Completion data queue for VC0
-                                                         when using the segmented-buffer configuration, writable
-                                                         through the DBI.
-                                                         However, the application must not change this field. */
-#else
-        uint32_t data_depth              : 14;
-        uint32_t reserved_14_15          : 2;
-        uint32_t header_depth            : 10;
-        uint32_t reserved_26_31          : 6;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg492_s         cn52xx;
-    struct cvmx_pciercx_cfg492_s         cn52xxp1;
-    struct cvmx_pciercx_cfg492_s         cn56xx;
-    struct cvmx_pciercx_cfg492_s         cn56xxp1;
-} cvmx_pciercx_cfg492_t;
-
-
-/**
- * cvmx_pcierc#_cfg516
- *
- * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space
- * (PHY Status Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg516_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t phy_stat                : 32;      /**< PHY Status */
-#else
-        uint32_t phy_stat                : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg516_s         cn52xx;
-    struct cvmx_pciercx_cfg516_s         cn52xxp1;
-    struct cvmx_pciercx_cfg516_s         cn56xx;
-    struct cvmx_pciercx_cfg516_s         cn56xxp1;
-} cvmx_pciercx_cfg516_t;
-
-
-/**
- * cvmx_pcierc#_cfg517
- *
- * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space
- * (PHY Control Register)
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_pciercx_cfg517_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t phy_ctrl                : 32;      /**< PHY Control */
-#else
-        uint32_t phy_ctrl                : 32;
-#endif
-    } s;
-    struct cvmx_pciercx_cfg517_s         cn52xx;
-    struct cvmx_pciercx_cfg517_s         cn52xxp1;
-    struct cvmx_pciercx_cfg517_s         cn56xx;
-    struct cvmx_pciercx_cfg517_s         cn56xxp1;
-} cvmx_pciercx_cfg517_t;
-
-
-/**
- * cvmx_pcm#_dma_cfg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_dma_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t rdpend                  : 1;       /**< If 0, no L2C read responses pending
-                                                            1, L2C read responses are outstanding
-                                                         NOTE: When restarting after stopping a running TDM
-                                                         engine, software must wait for RDPEND to read 0
-                                                         before writing PCMn_TDM_CFG[ENABLE] to a 1 */
-        uint64_t reserved_54_62          : 9;
-        uint64_t rxslots                 : 10;      /**< Number of 8-bit slots to receive per frame
-                                                         (number of slots in a receive superframe) */
-        uint64_t reserved_42_43          : 2;
-        uint64_t txslots                 : 10;      /**< Number of 8-bit slots to transmit per frame
-                                                         (number of slots in a transmit superframe) */
-        uint64_t reserved_30_31          : 2;
-        uint64_t rxst                    : 10;      /**< Number of frame writes for interrupt */
-        uint64_t reserved_19_19          : 1;
-        uint64_t useldt                  : 1;       /**< If 0, use LDI command to read from L2C
-                                                         1, use LDT command to read from L2C */
-        uint64_t txrd                    : 10;      /**< Number of frame reads for interrupt */
-        uint64_t fetchsiz                : 4;       /**< FETCHSIZ+1 timeslots are read when threshold is
-                                                         reached. */
-        uint64_t thresh                  : 4;       /**< If number of bytes remaining in the DMA fifo is <=
-                                                         THRESH, initiate a fetch of timeslot data from the
-                                                         transmit memory region.
-                                                         NOTE: there are only 16B of buffer for each engine
-                                                         so the seetings for FETCHSIZ and THRESH must be
-                                                         such that the buffer will not be overrun:
-                                                         
-                                                         THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */
-#else
-        uint64_t thresh                  : 4;
-        uint64_t fetchsiz                : 4;
-        uint64_t txrd                    : 10;
-        uint64_t useldt                  : 1;
-        uint64_t reserved_19_19          : 1;
-        uint64_t rxst                    : 10;
-        uint64_t reserved_30_31          : 2;
-        uint64_t txslots                 : 10;
-        uint64_t reserved_42_43          : 2;
-        uint64_t rxslots                 : 10;
-        uint64_t reserved_54_62          : 9;
-        uint64_t rdpend                  : 1;
-#endif
-    } s;
-    struct cvmx_pcmx_dma_cfg_s           cn30xx;
-    struct cvmx_pcmx_dma_cfg_s           cn31xx;
-    struct cvmx_pcmx_dma_cfg_s           cn50xx;
-} cvmx_pcmx_dma_cfg_t;
-
-
-/**
- * cvmx_pcm#_int_ena
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_int_ena_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rxovf                   : 1;       /**< Enable interrupt if RX byte overflows */
-        uint64_t txempty                 : 1;       /**< Enable interrupt on TX byte empty */
-        uint64_t txrd                    : 1;       /**< Enable DMA engine frame read interrupts */
-        uint64_t txwrap                  : 1;       /**< Enable TX region wrap interrupts */
-        uint64_t rxst                    : 1;       /**< Enable DMA engine frame store interrupts */
-        uint64_t rxwrap                  : 1;       /**< Enable RX region wrap interrupts */
-        uint64_t fsyncextra              : 1;       /**< Enable FSYNC extra interrupts
-                                                         NOTE: FSYNCEXTRA errors are defined as an FSYNC
-                                                         found in the "wrong" spot of a frame given the
-                                                         programming of PCMn_CLK_CFG[NUMSLOTS] and
-                                                         PCMn_CLK_CFG[EXTRABIT]. */
-        uint64_t fsyncmissed             : 1;       /**< Enable FSYNC missed interrupts
-                                                         NOTE: FSYNCMISSED errors are defined as an FSYNC
-                                                         missing from the correct spot in a frame given
-                                                         the programming of PCMn_CLK_CFG[NUMSLOTS] and
-                                                         PCMn_CLK_CFG[EXTRABIT]. */
-#else
-        uint64_t fsyncmissed             : 1;
-        uint64_t fsyncextra              : 1;
-        uint64_t rxwrap                  : 1;
-        uint64_t rxst                    : 1;
-        uint64_t txwrap                  : 1;
-        uint64_t txrd                    : 1;
-        uint64_t txempty                 : 1;
-        uint64_t rxovf                   : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pcmx_int_ena_s           cn30xx;
-    struct cvmx_pcmx_int_ena_s           cn31xx;
-    struct cvmx_pcmx_int_ena_s           cn50xx;
-} cvmx_pcmx_int_ena_t;
-
-
-/**
- * cvmx_pcm#_int_sum
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rxovf                   : 1;       /**< RX byte overflowed */
-        uint64_t txempty                 : 1;       /**< TX byte was empty when sampled */
-        uint64_t txrd                    : 1;       /**< DMA engine frame read interrupt occurred */
-        uint64_t txwrap                  : 1;       /**< TX region wrap interrupt occurred */
-        uint64_t rxst                    : 1;       /**< DMA engine frame store interrupt occurred */
-        uint64_t rxwrap                  : 1;       /**< RX region wrap interrupt occurred */
-        uint64_t fsyncextra              : 1;       /**< FSYNC extra interrupt occurred */
-        uint64_t fsyncmissed             : 1;       /**< FSYNC missed interrupt occurred */
-#else
-        uint64_t fsyncmissed             : 1;
-        uint64_t fsyncextra              : 1;
-        uint64_t rxwrap                  : 1;
-        uint64_t rxst                    : 1;
-        uint64_t txwrap                  : 1;
-        uint64_t txrd                    : 1;
-        uint64_t txempty                 : 1;
-        uint64_t rxovf                   : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pcmx_int_sum_s           cn30xx;
-    struct cvmx_pcmx_int_sum_s           cn31xx;
-    struct cvmx_pcmx_int_sum_s           cn50xx;
-} cvmx_pcmx_int_sum_t;
-
-
-/**
- * cvmx_pcm#_rxaddr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxaddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Address of the next write to the receive memory
-                                                         region */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_pcmx_rxaddr_s            cn30xx;
-    struct cvmx_pcmx_rxaddr_s            cn31xx;
-    struct cvmx_pcmx_rxaddr_s            cn50xx;
-} cvmx_pcmx_rxaddr_t;
-
-
-/**
- * cvmx_pcm#_rxcnt
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxcnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt                     : 16;      /**< Number of superframes in receive memory region */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcmx_rxcnt_s             cn30xx;
-    struct cvmx_pcmx_rxcnt_s             cn31xx;
-    struct cvmx_pcmx_rxcnt_s             cn50xx;
-} cvmx_pcmx_rxcnt_t;
-
-
-/**
- * cvmx_pcm#_rxmsk0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 63 to 0
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk0_s            cn30xx;
-    struct cvmx_pcmx_rxmsk0_s            cn31xx;
-    struct cvmx_pcmx_rxmsk0_s            cn50xx;
-} cvmx_pcmx_rxmsk0_t;
-
-
-/**
- * cvmx_pcm#_rxmsk1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 127 to 64
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk1_s            cn30xx;
-    struct cvmx_pcmx_rxmsk1_s            cn31xx;
-    struct cvmx_pcmx_rxmsk1_s            cn50xx;
-} cvmx_pcmx_rxmsk1_t;
-
-
-/**
- * cvmx_pcm#_rxmsk2
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 191 to 128
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk2_s            cn30xx;
-    struct cvmx_pcmx_rxmsk2_s            cn31xx;
-    struct cvmx_pcmx_rxmsk2_s            cn50xx;
-} cvmx_pcmx_rxmsk2_t;
-
-
-/**
- * cvmx_pcm#_rxmsk3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 255 to 192
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk3_s            cn30xx;
-    struct cvmx_pcmx_rxmsk3_s            cn31xx;
-    struct cvmx_pcmx_rxmsk3_s            cn50xx;
-} cvmx_pcmx_rxmsk3_t;
-
-
-/**
- * cvmx_pcm#_rxmsk4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 319 to 256
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk4_s            cn30xx;
-    struct cvmx_pcmx_rxmsk4_s            cn31xx;
-    struct cvmx_pcmx_rxmsk4_s            cn50xx;
-} cvmx_pcmx_rxmsk4_t;
-
-
-/**
- * cvmx_pcm#_rxmsk5
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 383 to 320
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk5_s            cn30xx;
-    struct cvmx_pcmx_rxmsk5_s            cn31xx;
-    struct cvmx_pcmx_rxmsk5_s            cn50xx;
-} cvmx_pcmx_rxmsk5_t;
-
-
-/**
- * cvmx_pcm#_rxmsk6
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 447 to 384
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk6_s            cn30xx;
-    struct cvmx_pcmx_rxmsk6_s            cn31xx;
-    struct cvmx_pcmx_rxmsk6_s            cn50xx;
-} cvmx_pcmx_rxmsk6_t;
-
-
-/**
- * cvmx_pcm#_rxmsk7
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxmsk7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Receive mask bits for slots 511 to 448
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_rxmsk7_s            cn30xx;
-    struct cvmx_pcmx_rxmsk7_s            cn31xx;
-    struct cvmx_pcmx_rxmsk7_s            cn50xx;
-} cvmx_pcmx_rxmsk7_t;
-
-
-/**
- * cvmx_pcm#_rxstart
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_rxstart_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 33;      /**< Starting address for the receive memory region */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t addr                    : 33;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_pcmx_rxstart_s           cn30xx;
-    struct cvmx_pcmx_rxstart_s           cn31xx;
-    struct cvmx_pcmx_rxstart_s           cn50xx;
-} cvmx_pcmx_rxstart_t;
-
-
-/**
- * cvmx_pcm#_tdm_cfg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_tdm_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t drvtim                  : 16;      /**< Number of ECLKs from start of bit time to stop
-                                                         driving last bit of timeslot (if not driving next
-                                                         timeslot) */
-        uint64_t samppt                  : 16;      /**< Number of ECLKs from start of bit time to sample
-                                                         data bit. */
-        uint64_t reserved_3_31           : 29;
-        uint64_t lsbfirst                : 1;       /**< If 0, shift/receive MSB first
-                                                         1, shift/receive LSB first */
-        uint64_t useclk1                 : 1;       /**< If 0, this PCM is based on BCLK/FSYNC0
-                                                         1, this PCM is based on BCLK/FSYNC1 */
-        uint64_t enable                  : 1;       /**< If 1, PCM is enabled, otherwise pins are GPIOs
-                                                         NOTE: when TDM is disabled by detection of an
-                                                         FSYNC error all transmission and reception is
-                                                         halted.  In addition, PCMn_TX/RXADDR are updated
-                                                         to point to the position at which the error was
-                                                         detected. */
-#else
-        uint64_t enable                  : 1;
-        uint64_t useclk1                 : 1;
-        uint64_t lsbfirst                : 1;
-        uint64_t reserved_3_31           : 29;
-        uint64_t samppt                  : 16;
-        uint64_t drvtim                  : 16;
-#endif
-    } s;
-    struct cvmx_pcmx_tdm_cfg_s           cn30xx;
-    struct cvmx_pcmx_tdm_cfg_s           cn31xx;
-    struct cvmx_pcmx_tdm_cfg_s           cn50xx;
-} cvmx_pcmx_tdm_cfg_t;
-
-
-/**
- * cvmx_pcm#_tdm_dbg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_tdm_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t debuginfo               : 64;      /**< Miscellaneous debug information */
-#else
-        uint64_t debuginfo               : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_tdm_dbg_s           cn30xx;
-    struct cvmx_pcmx_tdm_dbg_s           cn31xx;
-    struct cvmx_pcmx_tdm_dbg_s           cn50xx;
-} cvmx_pcmx_tdm_dbg_t;
-
-
-/**
- * cvmx_pcm#_txaddr
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txaddr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 33;      /**< Address of the next read from the transmit memory
-                                                         region */
-        uint64_t fram                    : 3;       /**< Frame offset
-                                                         NOTE: this is used to extract the correct byte from
-                                                         each 64b word read from the transmit memory region */
-#else
-        uint64_t fram                    : 3;
-        uint64_t addr                    : 33;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_pcmx_txaddr_s            cn30xx;
-    struct cvmx_pcmx_txaddr_s            cn31xx;
-    struct cvmx_pcmx_txaddr_s            cn50xx;
-} cvmx_pcmx_txaddr_t;
-
-
-/**
- * cvmx_pcm#_txcnt
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txcnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t cnt                     : 16;      /**< Number of superframes in transmit memory region */
-#else
-        uint64_t cnt                     : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcmx_txcnt_s             cn30xx;
-    struct cvmx_pcmx_txcnt_s             cn31xx;
-    struct cvmx_pcmx_txcnt_s             cn50xx;
-} cvmx_pcmx_txcnt_t;
-
-
-/**
- * cvmx_pcm#_txmsk0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 63 to 0
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk0_s            cn30xx;
-    struct cvmx_pcmx_txmsk0_s            cn31xx;
-    struct cvmx_pcmx_txmsk0_s            cn50xx;
-} cvmx_pcmx_txmsk0_t;
-
-
-/**
- * cvmx_pcm#_txmsk1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 127 to 64
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk1_s            cn30xx;
-    struct cvmx_pcmx_txmsk1_s            cn31xx;
-    struct cvmx_pcmx_txmsk1_s            cn50xx;
-} cvmx_pcmx_txmsk1_t;
-
-
-/**
- * cvmx_pcm#_txmsk2
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 191 to 128
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk2_s            cn30xx;
-    struct cvmx_pcmx_txmsk2_s            cn31xx;
-    struct cvmx_pcmx_txmsk2_s            cn50xx;
-} cvmx_pcmx_txmsk2_t;
-
-
-/**
- * cvmx_pcm#_txmsk3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 255 to 192
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk3_s            cn30xx;
-    struct cvmx_pcmx_txmsk3_s            cn31xx;
-    struct cvmx_pcmx_txmsk3_s            cn50xx;
-} cvmx_pcmx_txmsk3_t;
-
-
-/**
- * cvmx_pcm#_txmsk4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 319 to 256
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk4_s            cn30xx;
-    struct cvmx_pcmx_txmsk4_s            cn31xx;
-    struct cvmx_pcmx_txmsk4_s            cn50xx;
-} cvmx_pcmx_txmsk4_t;
-
-
-/**
- * cvmx_pcm#_txmsk5
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 383 to 320
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk5_s            cn30xx;
-    struct cvmx_pcmx_txmsk5_s            cn31xx;
-    struct cvmx_pcmx_txmsk5_s            cn50xx;
-} cvmx_pcmx_txmsk5_t;
-
-
-/**
- * cvmx_pcm#_txmsk6
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 447 to 384
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk6_s            cn30xx;
-    struct cvmx_pcmx_txmsk6_s            cn31xx;
-    struct cvmx_pcmx_txmsk6_s            cn50xx;
-} cvmx_pcmx_txmsk6_t;
-
-
-/**
- * cvmx_pcm#_txmsk7
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txmsk7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 511 to 448
-                                                         (1 means transmit, 0 means don't transmit) */
-#else
-        uint64_t mask                    : 64;
-#endif
-    } s;
-    struct cvmx_pcmx_txmsk7_s            cn30xx;
-    struct cvmx_pcmx_txmsk7_s            cn31xx;
-    struct cvmx_pcmx_txmsk7_s            cn50xx;
-} cvmx_pcmx_txmsk7_t;
-
-
-/**
- * cvmx_pcm#_txstart
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcmx_txstart_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 33;      /**< Starting address for the transmit memory region */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t addr                    : 33;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_pcmx_txstart_s           cn30xx;
-    struct cvmx_pcmx_txstart_s           cn31xx;
-    struct cvmx_pcmx_txstart_s           cn50xx;
-} cvmx_pcmx_txstart_t;
-
-
-/**
- * cvmx_pcm_clk#_cfg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcm_clkx_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fsyncgood               : 1;       /**< FSYNC status
-                                                         If 1, the last frame had a correctly positioned
-                                                               fsync pulse
-                                                         If 0, none/extra fsync pulse seen on most recent
-                                                               frame
-                                                         NOTE: this is intended for startup. the FSYNCEXTRA
-                                                         and FSYNCMISSING interrupts are intended for
-                                                         detecting loss of sync during normal operation. */
-        uint64_t reserved_48_62          : 15;
-        uint64_t fsyncsamp               : 16;      /**< Number of ECLKs from internal BCLK edge to
-                                                         sample FSYNC
-                                                         NOTE: used to sync to the start of a frame and to
-                                                         check for FSYNC errors. */
-        uint64_t reserved_26_31          : 6;
-        uint64_t fsynclen                : 5;       /**< Number of 1/2 BCLKs FSYNC is asserted for
-                                                         NOTE: only used when GEN==1 */
-        uint64_t fsyncloc                : 5;       /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
-                                                         bit 0.
-                                                         NOTE: also used to detect framing errors and
-                                                         therefore must have a correct value even if GEN==0 */
-        uint64_t numslots                : 10;      /**< Number of 8-bit slots in a frame
-                                                         NOTE: this, along with EXTRABIT and Fbclk
-                                                         determines FSYNC frequency when GEN == 1
-                                                         NOTE: also used to detect framing errors and
-                                                         therefore must have a correct value even if GEN==0 */
-        uint64_t extrabit                : 1;       /**< If 0, no frame bit
-                                                         If 1, add one extra bit time for frame bit
-                                                         NOTE: if GEN == 1, then FSYNC will be delayed one
-                                                         extra bit time.
-                                                         NOTE: also used to detect framing errors and
-                                                         therefore must have a correct value even if GEN==0
-                                                         NOTE: the extra bit comes from the LSB/MSB of the
-                                                         first byte of the frame in the transmit memory
-                                                         region.  LSB vs MSB is determined from the setting
-                                                         of PCMn_TDM_CFG[LSBFIRST]. */
-        uint64_t bitlen                  : 2;       /**< Number of BCLKs in a bit time.
-                                                         0 : 1 BCLK
-                                                         1 : 2 BCLKs
-                                                         2 : 4 BCLKs
-                                                         3 : operation undefined */
-        uint64_t bclkpol                 : 1;       /**< If 0, BCLK rise edge is start of bit time
-                                                         If 1, BCLK fall edge is start of bit time
-                                                         NOTE: also used to detect framing errors and
-                                                         therefore must have a correct value even if GEN==0 */
-        uint64_t fsyncpol                : 1;       /**< If 0, FSYNC idles low, asserts high
-                                                         If 1, FSYNC idles high, asserts low
-                                                         NOTE: also used to detect framing errors and
-                                                         therefore must have a correct value even if GEN==0 */
-        uint64_t ena                     : 1;       /**< If 0, Clock receiving logic is doing nothing
-                                                         1, Clock receiving logic is looking for sync */
-#else
-        uint64_t ena                     : 1;
-        uint64_t fsyncpol                : 1;
-        uint64_t bclkpol                 : 1;
-        uint64_t bitlen                  : 2;
-        uint64_t extrabit                : 1;
-        uint64_t numslots                : 10;
-        uint64_t fsyncloc                : 5;
-        uint64_t fsynclen                : 5;
-        uint64_t reserved_26_31          : 6;
-        uint64_t fsyncsamp               : 16;
-        uint64_t reserved_48_62          : 15;
-        uint64_t fsyncgood               : 1;
-#endif
-    } s;
-    struct cvmx_pcm_clkx_cfg_s           cn30xx;
-    struct cvmx_pcm_clkx_cfg_s           cn31xx;
-    struct cvmx_pcm_clkx_cfg_s           cn50xx;
-} cvmx_pcm_clkx_cfg_t;
-
-
-/**
- * cvmx_pcm_clk#_dbg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcm_clkx_dbg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t debuginfo               : 64;      /**< Miscellaneous debug information */
-#else
-        uint64_t debuginfo               : 64;
-#endif
-    } s;
-    struct cvmx_pcm_clkx_dbg_s           cn30xx;
-    struct cvmx_pcm_clkx_dbg_s           cn31xx;
-    struct cvmx_pcm_clkx_dbg_s           cn50xx;
-} cvmx_pcm_clkx_dbg_t;
-
-
-/**
- * cvmx_pcm_clk#_gen
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcm_clkx_gen_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t deltasamp               : 16;      /**< Signed number of ECLKs to move sampled BCLK edge
-                                                         NOTE: the complete number of ECLKs to move is:
-                                                                   NUMSAMP + 2 + 1 + DELTASAMP
-                                                               NUMSAMP to compensate for sampling delay
-                                                               + 2 to compensate for dual-rank synchronizer
-                                                               + 1 for uncertainity
-                                                               + DELTASAMP to CMA/debugging */
-        uint64_t numsamp                 : 16;      /**< Number of ECLK samples to detect BCLK change when
-                                                         receiving clock. */
-        uint64_t n                       : 32;      /**< Determines BCLK frequency when generating clock
-                                                         NOTE: Fbclk = Feclk * N / 2^32
-                                                               N = (Fbclk / Feclk) * 2^32
-                                                         NOTE: writing N == 0 stops the clock generator, and
-                                                               causes bclk and fsync to be RECEIVED */
-#else
-        uint64_t n                       : 32;
-        uint64_t numsamp                 : 16;
-        uint64_t deltasamp               : 16;
-#endif
-    } s;
-    struct cvmx_pcm_clkx_gen_s           cn30xx;
-    struct cvmx_pcm_clkx_gen_s           cn31xx;
-    struct cvmx_pcm_clkx_gen_s           cn50xx;
-} cvmx_pcm_clkx_gen_t;
-
-
-/**
- * cvmx_pcs#_an#_adv_reg
- *
- * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification,
- * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating
- * that the chip cannot operate in the corresponding modes.
- * 
- * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.
- * 
- * 
- * 
- * PCS_AN_ADV_REG = AN Advertisement Register4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_anx_adv_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t np                      : 1;       /**< Always 0, no next page capability supported */
-        uint64_t reserved_14_14          : 1;
-        uint64_t rem_flt                 : 2;       /**< [<13>,<12>]
-                                                         0    0  Link OK  XMIT=DATA
-                                                         0    1  Link failure (loss of sync, XMIT!= DATA)
-                                                         1    0  local device Offline
-                                                         1    1  AN Error failure to complete AN
-                                                                 AN Error is set if resolution function
-                                                                 precludes operation with link partner */
-        uint64_t reserved_9_11           : 3;
-        uint64_t pause                   : 2;       /**< [<8>, <7>] Pause frame flow capability across link
-                                                                  Exchanged during Auto Negotiation
-                                                         0    0  No Pause
-                                                         0    1  Symmetric pause
-                                                         1    0  Asymmetric Pause
-                                                         1    1  Both symm and asymm pause to local device */
-        uint64_t hfd                     : 1;       /**< 1 means local device Half Duplex capable */
-        uint64_t fd                      : 1;       /**< 1 means local device Full Duplex capable */
-        uint64_t reserved_0_4            : 5;
-#else
-        uint64_t reserved_0_4            : 5;
-        uint64_t fd                      : 1;
-        uint64_t hfd                     : 1;
-        uint64_t pause                   : 2;
-        uint64_t reserved_9_11           : 3;
-        uint64_t rem_flt                 : 2;
-        uint64_t reserved_14_14          : 1;
-        uint64_t np                      : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_anx_adv_reg_s       cn52xx;
-    struct cvmx_pcsx_anx_adv_reg_s       cn52xxp1;
-    struct cvmx_pcsx_anx_adv_reg_s       cn56xx;
-    struct cvmx_pcsx_anx_adv_reg_s       cn56xxp1;
-} cvmx_pcsx_anx_adv_reg_t;
-
-
-/**
- * cvmx_pcs#_an#_ext_st_reg
- *
- * NOTE:
- * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1
- * the an_results_reg is valid.
- * 
- * 
- * PCS_AN_EXT_ST_REG = AN Extended Status Register15
- * as per IEEE802.3 Clause 22
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_anx_ext_st_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t thou_xfd                : 1;       /**< 1 means PHY is 1000BASE-X Full Dup capable */
-        uint64_t thou_xhd                : 1;       /**< 1 means PHY is 1000BASE-X Half Dup capable */
-        uint64_t thou_tfd                : 1;       /**< 1 means PHY is 1000BASE-T Full Dup capable */
-        uint64_t thou_thd                : 1;       /**< 1 means PHY is 1000BASE-T Half Dup capable */
-        uint64_t reserved_0_11           : 12;
-#else
-        uint64_t reserved_0_11           : 12;
-        uint64_t thou_thd                : 1;
-        uint64_t thou_tfd                : 1;
-        uint64_t thou_xhd                : 1;
-        uint64_t thou_xfd                : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_anx_ext_st_reg_s    cn52xx;
-    struct cvmx_pcsx_anx_ext_st_reg_s    cn52xxp1;
-    struct cvmx_pcsx_anx_ext_st_reg_s    cn56xx;
-    struct cvmx_pcsx_anx_ext_st_reg_s    cn56xxp1;
-} cvmx_pcsx_anx_ext_st_reg_t;
-
-
-/**
- * cvmx_pcs#_an#_lp_abil_reg
- *
- * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5
- * as per IEEE802.3 Clause 37
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_anx_lp_abil_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t np                      : 1;       /**< 1=lp next page capable, 0=lp not next page capable */
-        uint64_t ack                     : 1;       /**< 1=Acknowledgement received */
-        uint64_t rem_flt                 : 2;       /**< [<13>,<12>] Link Partner's link status
-                                                         0    0  Link OK
-                                                         0    1  Offline
-                                                         1    0  Link failure
-                                                         1    1  AN Error */
-        uint64_t reserved_9_11           : 3;
-        uint64_t pause                   : 2;       /**< [<8>, <7>] Link Partner Pause setting
-                                                         0    0  No Pause
-                                                         0    1  Symmetric pause
-                                                         1    0  Asymmetric Pause
-                                                         1    1  Both symm and asymm pause to local device */
-        uint64_t hfd                     : 1;       /**< 1 means link partner Half Duplex capable */
-        uint64_t fd                      : 1;       /**< 1 means link partner Full Duplex capable */
-        uint64_t reserved_0_4            : 5;
-#else
-        uint64_t reserved_0_4            : 5;
-        uint64_t fd                      : 1;
-        uint64_t hfd                     : 1;
-        uint64_t pause                   : 2;
-        uint64_t reserved_9_11           : 3;
-        uint64_t rem_flt                 : 2;
-        uint64_t ack                     : 1;
-        uint64_t np                      : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_anx_lp_abil_reg_s   cn52xx;
-    struct cvmx_pcsx_anx_lp_abil_reg_s   cn52xxp1;
-    struct cvmx_pcsx_anx_lp_abil_reg_s   cn56xx;
-    struct cvmx_pcsx_anx_lp_abil_reg_s   cn56xxp1;
-} cvmx_pcsx_anx_lp_abil_reg_t;
-
-
-/**
- * cvmx_pcs#_an#_results_reg
- *
- * PCS_AN_RESULTS_REG = AN Results Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_anx_results_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t pause                   : 2;       /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII)
-                                                         0    0  Disable Pause, TX and RX
-                                                         0    1  Enable pause frames RX only
-                                                         1    0  Enable Pause frames TX only
-                                                         1    1  Enable pause frames TX and RX */
-        uint64_t spd                     : 2;       /**< [<4>, <3>] Link Speed Selection
-                                                         0    0  10Mb/s
-                                                         0    1  100Mb/s
-                                                         1    0  1000Mb/s
-                                                         1    1  RSVD */
-        uint64_t an_cpt                  : 1;       /**< 1=AN Completed, 0=AN not completed or failed */
-        uint64_t dup                     : 1;       /**< 1=Full Duplex, 0=Half Duplex */
-        uint64_t link_ok                 : 1;       /**< 1=Link up(OK), 0=Link down */
-#else
-        uint64_t link_ok                 : 1;
-        uint64_t dup                     : 1;
-        uint64_t an_cpt                  : 1;
-        uint64_t spd                     : 2;
-        uint64_t pause                   : 2;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_pcsx_anx_results_reg_s   cn52xx;
-    struct cvmx_pcsx_anx_results_reg_s   cn52xxp1;
-    struct cvmx_pcsx_anx_results_reg_s   cn56xx;
-    struct cvmx_pcsx_anx_results_reg_s   cn56xxp1;
-} cvmx_pcsx_anx_results_reg_t;
-
-
-/**
- * cvmx_pcs#_int#_en_reg
- *
- * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising
- * 
- * 
- * PCS Interrupt Enable Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_intx_en_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t dup                     : 1;       /**< Enable duplex mode changed interrupt */
-        uint64_t sync_bad_en             : 1;       /**< Enable rx sync st machine in bad state interrupt */
-        uint64_t an_bad_en               : 1;       /**< Enable AN state machine bad state interrupt */
-        uint64_t rxlock_en               : 1;       /**< Enable rx code group sync/bit lock failure interrupt */
-        uint64_t rxbad_en                : 1;       /**< Enable rx state machine in bad state interrupt */
-        uint64_t rxerr_en                : 1;       /**< Enable RX error condition interrupt */
-        uint64_t txbad_en                : 1;       /**< Enable tx state machine in bad state interrupt */
-        uint64_t txfifo_en               : 1;       /**< Enable tx fifo overflow condition interrupt */
-        uint64_t txfifu_en               : 1;       /**< Enable tx fifo underflow condition intrrupt */
-        uint64_t an_err_en               : 1;       /**< Enable AN Error condition interrupt */
-        uint64_t xmit_en                 : 1;       /**< Enable XMIT variable state change interrupt */
-        uint64_t lnkspd_en               : 1;       /**< Enable Link Speed has changed interrupt */
-#else
-        uint64_t lnkspd_en               : 1;
-        uint64_t xmit_en                 : 1;
-        uint64_t an_err_en               : 1;
-        uint64_t txfifu_en               : 1;
-        uint64_t txfifo_en               : 1;
-        uint64_t txbad_en                : 1;
-        uint64_t rxerr_en                : 1;
-        uint64_t rxbad_en                : 1;
-        uint64_t rxlock_en               : 1;
-        uint64_t an_bad_en               : 1;
-        uint64_t sync_bad_en             : 1;
-        uint64_t dup                     : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_pcsx_intx_en_reg_s       cn52xx;
-    struct cvmx_pcsx_intx_en_reg_s       cn52xxp1;
-    struct cvmx_pcsx_intx_en_reg_s       cn56xx;
-    struct cvmx_pcsx_intx_en_reg_s       cn56xxp1;
-} cvmx_pcsx_intx_en_reg_t;
-
-
-/**
- * cvmx_pcs#_int#_reg
- *
- * SGMII bit [12] is really a misnomer, it is a decode  of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes.
- * 
- * Note: MODE bit
- * When MODE=1,  1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37.
- * When MODE=0,  SGMII mode is selected and the following note will apply.
- * Repeat note from SGM_AN_ADV register
- * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
- * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
- * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
- * 
- * PCS Interrupt Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_intx_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t dup                     : 1;       /**< Set whenever Duplex mode changes on the link */
-        uint64_t sync_bad                : 1;       /**< Set by HW whenever rx sync st machine reaches a bad
-                                                         state. Should never be set during normal operation */
-        uint64_t an_bad                  : 1;       /**< Set by HW whenever AN st machine reaches a bad
-                                                         state. Should never be set during normal operation */
-        uint64_t rxlock                  : 1;       /**< Set by HW whenever code group Sync or bit lock
-                                                         failure occurs
-                                                         Cannot fire in loopback1 mode */
-        uint64_t rxbad                   : 1;       /**< Set by HW whenever rx st machine reaches a  bad
-                                                         state. Should never be set during normal operation */
-        uint64_t rxerr                   : 1;       /**< Set whenever RX receives a code group error in
-                                                         10 bit to 8 bit decode logic
-                                                         Cannot fire in loopback1 mode */
-        uint64_t txbad                   : 1;       /**< Set by HW whenever tx st machine reaches a bad
-                                                         state. Should never be set during normal operation */
-        uint64_t txfifo                  : 1;       /**< Set whenever HW detects a TX fifo overflow
-                                                         condition */
-        uint64_t txfifu                  : 1;       /**< Set whenever HW detects a TX fifo underflowflow
-                                                         condition */
-        uint64_t an_err                  : 1;       /**< AN Error, AN resolution function failed */
-        uint64_t xmit                    : 1;       /**< Set whenever HW detects a change in the XMIT
-                                                         variable. XMIT variable states are IDLE, CONFIG and
-                                                         DATA */
-        uint64_t lnkspd                  : 1;       /**< Set by HW whenever Link Speed has changed */
-#else
-        uint64_t lnkspd                  : 1;
-        uint64_t xmit                    : 1;
-        uint64_t an_err                  : 1;
-        uint64_t txfifu                  : 1;
-        uint64_t txfifo                  : 1;
-        uint64_t txbad                   : 1;
-        uint64_t rxerr                   : 1;
-        uint64_t rxbad                   : 1;
-        uint64_t rxlock                  : 1;
-        uint64_t an_bad                  : 1;
-        uint64_t sync_bad                : 1;
-        uint64_t dup                     : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_pcsx_intx_reg_s          cn52xx;
-    struct cvmx_pcsx_intx_reg_s          cn52xxp1;
-    struct cvmx_pcsx_intx_reg_s          cn56xx;
-    struct cvmx_pcsx_intx_reg_s          cn56xxp1;
-} cvmx_pcsx_intx_reg_t;
-
-
-/**
- * cvmx_pcs#_link#_timer_count_reg
- *
- * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_linkx_timer_count_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t count                   : 16;      /**< (core clock period times 1024) times "COUNT" should
-                                                         be 1.6ms(SGMII)/10ms(otherwise) which is the link
-                                                         timer used in auto negotiation.
-                                                         Reset assums a 700MHz eclk for 1.6ms link timer */
-#else
-        uint64_t count                   : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
-    struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
-    struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
-    struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
-} cvmx_pcsx_linkx_timer_count_reg_t;
-
-
-/**
- * cvmx_pcs#_log_anl#_reg
- *
- * PCS Logic Analyzer Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_log_anlx_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t lafifovfl               : 1;       /**< 1=logic analyser fif overflowed during packetization
-                                                         Write 1 to clear this bit */
-        uint64_t la_en                   : 1;       /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
-        uint64_t pkt_sz                  : 2;       /**< [<1>, <0>]  Logic Analyzer Packet Size
-                                                         0    0   Packet size 1k bytes
-                                                         0    1   Packet size 4k bytes
-                                                         1    0   Packet size 8k bytes
-                                                         1    1   Packet size 16k bytes */
-#else
-        uint64_t pkt_sz                  : 2;
-        uint64_t la_en                   : 1;
-        uint64_t lafifovfl               : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pcsx_log_anlx_reg_s      cn52xx;
-    struct cvmx_pcsx_log_anlx_reg_s      cn52xxp1;
-    struct cvmx_pcsx_log_anlx_reg_s      cn56xx;
-    struct cvmx_pcsx_log_anlx_reg_s      cn56xxp1;
-} cvmx_pcsx_log_anlx_reg_t;
-
-
-/**
- * cvmx_pcs#_misc#_ctl_reg
- *
- * SGMII Misc Control Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_miscx_ctl_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t sgmii                   : 1;       /**< 1=SGMII or 1000Base-X mode selected,
-                                                         0=XAUI or PCIE mode selected
-                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
-        uint64_t gmxeno                  : 1;       /**< GMX Enable override. When set to 1, forces GMX to
-                                                         appear disabled. The enable/disable status of GMX
-                                                         is checked only at SOP of every packet. */
-        uint64_t loopbck2                : 1;       /**< Sets external loopback mode to return rx data back
-                                                         out via tx data path. 0=no loopback, 1=loopback */
-        uint64_t mac_phy                 : 1;       /**< 0=MAC, 1=PHY decides the tx_config_reg value to be
-                                                         sent during auto negotiation.
-                                                         See SGMII spec ENG-46158 from CISCO */
-        uint64_t mode                    : 1;       /**< 0=SGMII or 1= 1000 Base X */
-        uint64_t an_ovrd                 : 1;       /**< 0=disable, 1= enable over ride AN results
-                                                         Auto negotiation is allowed to happen but the
-                                                         results are ignored when set. Duplex and Link speed
-                                                         values are set from the pcs_mr_ctrl reg */
-        uint64_t samp_pt                 : 7;       /**< Byte# in elongated frames for 10/100Mb/s operation
-                                                         for data sampling on RX side in PCS.
-                                                         Recommended values are 0x5 for 100Mb/s operation
-                                                         and 0x32 for 10Mb/s operation.
-                                                         For 10Mb/s operaton this field should be set to a
-                                                         value less than 99 and greater than 0. If set out
-                                                         of this range a value of 50 will be used for actual
-                                                         sampling internally without affecting the CSR field
-                                                         For 100Mb/s operation this field should be set to a
-                                                         value less than 9 and greater than 0. If set out of
-                                                         this range a value of 5 will be used for actual
-                                                         sampling internally without affecting the CSR field */
-#else
-        uint64_t samp_pt                 : 7;
-        uint64_t an_ovrd                 : 1;
-        uint64_t mode                    : 1;
-        uint64_t mac_phy                 : 1;
-        uint64_t loopbck2                : 1;
-        uint64_t gmxeno                  : 1;
-        uint64_t sgmii                   : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pcsx_miscx_ctl_reg_s     cn52xx;
-    struct cvmx_pcsx_miscx_ctl_reg_s     cn52xxp1;
-    struct cvmx_pcsx_miscx_ctl_reg_s     cn56xx;
-    struct cvmx_pcsx_miscx_ctl_reg_s     cn56xxp1;
-} cvmx_pcsx_miscx_ctl_reg_t;
-
-
-/**
- * cvmx_pcs#_mr#_control_reg
- *
- * PCS_MR_CONTROL_REG = Control Register0
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_mrx_control_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t reset                   : 1;       /**< 1=SW Reset, the bit will return to 0 after pcs has
-                                                         been reset. Takes 32 eclk cycles to reset pcs */
-        uint64_t loopbck1                : 1;       /**< 0=normal operation, 1=loopback. The loopback mode
-                                                         will return(loopback) tx data from GMII tx back to
-                                                         GMII rx interface. The loopback happens in the pcs
-                                                         module. Auto Negotiation will be disabled even if
-                                                         the AN_EN bit is set, during loopback */
-        uint64_t spdlsb                  : 1;       /**< See bit 6 description */
-        uint64_t an_en                   : 1;       /**< 1=AN Enable, 0=AN Disable */
-        uint64_t pwr_dn                  : 1;       /**< 1=Power Down(HW reset), 0=Normal operation */
-        uint64_t reserved_10_10          : 1;
-        uint64_t rst_an                  : 1;       /**< If bit 12 is set and bit 3 of status reg is 1
-                                                         Auto Negotiation begins. Else,SW writes are ignored
-                                                         and this bit remians at 0. This bit clears itself
-                                                         to 0, when AN starts. */
-        uint64_t dup                     : 1;       /**< 1=full duplex, 0=half duplex; effective only if AN
-                                                         disabled. If status register bits [15:9] and and
-                                                         extended status reg bits [15:12] allow only one
-                                                         duplex mode|, this bit will correspond to that
-                                                         value and any attempt to write will be ignored. */
-        uint64_t coltst                  : 1;       /**< 1=enable COL signal test, 0=disable test
-                                                         During COL test, the COL signal will reflect the
-                                                         GMII TX_EN signal with less than 16BT delay */
-        uint64_t spdmsb                  : 1;       /**< [<6>, <13>]Link Speed effective only if AN disabled
-                                                         0    0  10Mb/s
-                                                         0    1  100Mb/s
-                                                         1    0  1000Mb/s
-                                                         1    1  RSVD */
-        uint64_t uni                     : 1;       /**< Unidirectional (Std 802.3-2005, Clause 66.2)
-                                                         This bit will override the AN_EN bit and disable
-                                                         auto-negotiation variable mr_an_enable, when set
-                                                         Used in both 1000Base-X and SGMII modes */
-        uint64_t reserved_0_4            : 5;
-#else
-        uint64_t reserved_0_4            : 5;
-        uint64_t uni                     : 1;
-        uint64_t spdmsb                  : 1;
-        uint64_t coltst                  : 1;
-        uint64_t dup                     : 1;
-        uint64_t rst_an                  : 1;
-        uint64_t reserved_10_10          : 1;
-        uint64_t pwr_dn                  : 1;
-        uint64_t an_en                   : 1;
-        uint64_t spdlsb                  : 1;
-        uint64_t loopbck1                : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_mrx_control_reg_s   cn52xx;
-    struct cvmx_pcsx_mrx_control_reg_s   cn52xxp1;
-    struct cvmx_pcsx_mrx_control_reg_s   cn56xx;
-    struct cvmx_pcsx_mrx_control_reg_s   cn56xxp1;
-} cvmx_pcsx_mrx_control_reg_t;
-
-
-/**
- * cvmx_pcs#_mr#_status_reg
- *
- * NOTE:
- * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results
- * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set,
- * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values
- * from the pcs_mr_ctrl reg.
- * 
- *  PCS_MR_STATUS_REG = Status Register1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_mrx_status_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t hun_t4                  : 1;       /**< 1 means 100Base-T4 capable */
-        uint64_t hun_xfd                 : 1;       /**< 1 means 100Base-X Full Duplex */
-        uint64_t hun_xhd                 : 1;       /**< 1 means 100Base-X Half Duplex */
-        uint64_t ten_fd                  : 1;       /**< 1 means 10Mb/s Full Duplex */
-        uint64_t ten_hd                  : 1;       /**< 1 means 10Mb/s Half Duplex */
-        uint64_t hun_t2fd                : 1;       /**< 1 means 100Base-T2 Full Duplex */
-        uint64_t hun_t2hd                : 1;       /**< 1 means 100Base-T2 Half Duplex */
-        uint64_t ext_st                  : 1;       /**< 1 means extended status info in reg15 */
-        uint64_t reserved_7_7            : 1;
-        uint64_t prb_sup                 : 1;       /**< 1 means able to work without preamble bytes at the
-                                                         beginning of frames. 0 means not able to accept
-                                                         frames without preamble bytes preceding them. */
-        uint64_t an_cpt                  : 1;       /**< 1 means Auto Negotiation is complete and the
-                                                         contents of the an_results_reg are valid. */
-        uint64_t rm_flt                  : 1;       /**< Set to 1 when remote flt condition occurs. This bit
-                                                         implements a latching Hi behavior. It is cleared by
-                                                         SW read of this reg or when reset bit [15] in
-                                                         Control Reg is asserted.
-                                                         See an adv reg[13:12] for flt conditions */
-        uint64_t an_abil                 : 1;       /**< 1 means Auto Negotiation capable */
-        uint64_t lnk_st                  : 1;       /**< 1=link up, 0=link down. Set during AN process
-                                                         Set whenever XMIT=DATA. Latching Lo behavior when
-                                                         link goes down. Link down value of the bit stays
-                                                         low until SW reads the reg. */
-        uint64_t reserved_1_1            : 1;
-        uint64_t extnd                   : 1;       /**< Always 0, no extended capability regs present */
-#else
-        uint64_t extnd                   : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t lnk_st                  : 1;
-        uint64_t an_abil                 : 1;
-        uint64_t rm_flt                  : 1;
-        uint64_t an_cpt                  : 1;
-        uint64_t prb_sup                 : 1;
-        uint64_t reserved_7_7            : 1;
-        uint64_t ext_st                  : 1;
-        uint64_t hun_t2hd                : 1;
-        uint64_t hun_t2fd                : 1;
-        uint64_t ten_hd                  : 1;
-        uint64_t ten_fd                  : 1;
-        uint64_t hun_xhd                 : 1;
-        uint64_t hun_xfd                 : 1;
-        uint64_t hun_t4                  : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_mrx_status_reg_s    cn52xx;
-    struct cvmx_pcsx_mrx_status_reg_s    cn52xxp1;
-    struct cvmx_pcsx_mrx_status_reg_s    cn56xx;
-    struct cvmx_pcsx_mrx_status_reg_s    cn56xxp1;
-} cvmx_pcsx_mrx_status_reg_t;
-
-
-/**
- * cvmx_pcs#_rx#_states_reg
- *
- * PCS_RX_STATES_REG = RX State Machines states register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_rxx_states_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t rx_bad                  : 1;       /**< Receive state machine in an illegal state */
-        uint64_t rx_st                   : 5;       /**< Receive state machine state */
-        uint64_t sync_bad                : 1;       /**< Receive synchronization SM in an illegal state */
-        uint64_t sync                    : 4;       /**< Receive synchronization SM state */
-        uint64_t an_bad                  : 1;       /**< Auto Negotiation state machine in an illegal state */
-        uint64_t an_st                   : 4;       /**< Auto Negotiation state machine state */
-#else
-        uint64_t an_st                   : 4;
-        uint64_t an_bad                  : 1;
-        uint64_t sync                    : 4;
-        uint64_t sync_bad                : 1;
-        uint64_t rx_st                   : 5;
-        uint64_t rx_bad                  : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_rxx_states_reg_s    cn52xx;
-    struct cvmx_pcsx_rxx_states_reg_s    cn52xxp1;
-    struct cvmx_pcsx_rxx_states_reg_s    cn56xx;
-    struct cvmx_pcsx_rxx_states_reg_s    cn56xxp1;
-} cvmx_pcsx_rxx_states_reg_t;
-
-
-/**
- * cvmx_pcs#_rx#_sync_reg
- *
- * Note:
- * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved.
- * 
- * 
- *  PCS_RX_SYNC_REG = Code Group synchronization reg
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_rxx_sync_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t sync                    : 1;       /**< 1 means code group synchronization achieved */
-        uint64_t bit_lock                : 1;       /**< 1 means bit lock achieved */
-#else
-        uint64_t bit_lock                : 1;
-        uint64_t sync                    : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pcsx_rxx_sync_reg_s      cn52xx;
-    struct cvmx_pcsx_rxx_sync_reg_s      cn52xxp1;
-    struct cvmx_pcsx_rxx_sync_reg_s      cn56xx;
-    struct cvmx_pcsx_rxx_sync_reg_s      cn56xxp1;
-} cvmx_pcsx_rxx_sync_reg_t;
-
-
-/**
- * cvmx_pcs#_sgm#_an_adv_reg
- *
- * SGMII AN Advertisement Register (sent out as tx_config_reg)
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_sgmx_an_adv_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t link                    : 1;       /**< Link status 1 Link Up, 0 Link Down */
-        uint64_t ack                     : 1;       /**< Auto negotiation ack */
-        uint64_t reserved_13_13          : 1;
-        uint64_t dup                     : 1;       /**< Duplex mode 1=full duplex, 0=half duplex */
-        uint64_t speed                   : 2;       /**< Link Speed
-                                                         0    0  10Mb/s
-                                                         0    1  100Mb/s
-                                                         1    0  1000Mb/s
-                                                         1    1  RSVD */
-        uint64_t reserved_1_9            : 9;
-        uint64_t one                     : 1;       /**< Always set to match tx_config_reg<0> */
-#else
-        uint64_t one                     : 1;
-        uint64_t reserved_1_9            : 9;
-        uint64_t speed                   : 2;
-        uint64_t dup                     : 1;
-        uint64_t reserved_13_13          : 1;
-        uint64_t ack                     : 1;
-        uint64_t link                    : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn52xx;
-    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn52xxp1;
-    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn56xx;
-    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn56xxp1;
-} cvmx_pcsx_sgmx_an_adv_reg_t;
-
-
-/**
- * cvmx_pcs#_sgm#_lp_adv_reg
- *
- * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
- * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
- * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
- * 
- * SGMII LP Advertisement Register (received as rx_config_reg)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_sgmx_lp_adv_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t link                    : 1;       /**< Link status 1 Link Up, 0 Link Down */
-        uint64_t reserved_13_14          : 2;
-        uint64_t dup                     : 1;       /**< Duplex mode 1=full duplex, 0=half duplex */
-        uint64_t speed                   : 2;       /**< Link Speed
-                                                         0    0  10Mb/s
-                                                         0    1  100Mb/s
-                                                         1    0  1000Mb/s
-                                                         1    1  RSVD */
-        uint64_t reserved_1_9            : 9;
-        uint64_t one                     : 1;       /**< Always set to match tx_config_reg<0> */
-#else
-        uint64_t one                     : 1;
-        uint64_t reserved_1_9            : 9;
-        uint64_t speed                   : 2;
-        uint64_t dup                     : 1;
-        uint64_t reserved_13_14          : 2;
-        uint64_t link                    : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn52xx;
-    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn52xxp1;
-    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn56xx;
-    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn56xxp1;
-} cvmx_pcsx_sgmx_lp_adv_reg_t;
-
-
-/**
- * cvmx_pcs#_tx#_states_reg
- *
- * PCS_TX_STATES_REG = TX State Machines states register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_txx_states_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t xmit                    : 2;       /**< 0=undefined, 1=config, 2=idle, 3=data */
-        uint64_t tx_bad                  : 1;       /**< Xmit state machine in a bad state */
-        uint64_t ord_st                  : 4;       /**< Xmit ordered set state machine state */
-#else
-        uint64_t ord_st                  : 4;
-        uint64_t tx_bad                  : 1;
-        uint64_t xmit                    : 2;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_pcsx_txx_states_reg_s    cn52xx;
-    struct cvmx_pcsx_txx_states_reg_s    cn52xxp1;
-    struct cvmx_pcsx_txx_states_reg_s    cn56xx;
-    struct cvmx_pcsx_txx_states_reg_s    cn56xxp1;
-} cvmx_pcsx_txx_states_reg_t;
-
-
-/**
- * cvmx_pcs#_tx_rx#_polarity_reg
- *
- * PCS_POLARITY_REG = TX_RX polarity reg
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsx_tx_rxx_polarity_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t rxovrd                  : 1;       /**< When 0, <2> determines polarity
-                                                         when 1, <1> determines polarity */
-        uint64_t autorxpl                : 1;       /**< Auto RX polarity detected. 1=inverted, 0=normal
-                                                         This bit always represents the correct rx polarity
-                                                         setting needed for successful rx path operartion,
-                                                         once a successful code group sync is obtained */
-        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-#else
-        uint64_t txplrt                  : 1;
-        uint64_t rxplrt                  : 1;
-        uint64_t autorxpl                : 1;
-        uint64_t rxovrd                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
-    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
-    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
-    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
-} cvmx_pcsx_tx_rxx_polarity_reg_t;
-
-
-/**
- * cvmx_pcsx#_10gbx_status_reg
- *
- * PCSX_10GBX_STATUS_REG = 10gbx_status_reg
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_10gbx_status_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t alignd                  : 1;       /**< 1=Lane alignment achieved, 0=Lanes not aligned */
-        uint64_t pattst                  : 1;       /**< Always at 0, no pattern testing capability */
-        uint64_t reserved_4_10           : 7;
-        uint64_t l3sync                  : 1;       /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */
-        uint64_t l2sync                  : 1;       /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */
-        uint64_t l1sync                  : 1;       /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */
-        uint64_t l0sync                  : 1;       /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */
-#else
-        uint64_t l0sync                  : 1;
-        uint64_t l1sync                  : 1;
-        uint64_t l2sync                  : 1;
-        uint64_t l3sync                  : 1;
-        uint64_t reserved_4_10           : 7;
-        uint64_t pattst                  : 1;
-        uint64_t alignd                  : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
-    struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
-    struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
-    struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
-} cvmx_pcsxx_10gbx_status_reg_t;
-
-
-/**
- * cvmx_pcsx#_bist_status_reg
- *
- * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1
- * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0].
- * See pcs.csr  for sgmii/1000Base-X logic analyzer mode.
- * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
- * 
- * 
- *  PCSX Bist Status Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_bist_status_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t bist_status             : 1;       /**< 1=bist failure, 0=bisted memory ok or bist in progress
-                                                         pcsx.tx_sm.drf8x36m1_async_bist */
-#else
-        uint64_t bist_status             : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_pcsxx_bist_status_reg_s  cn52xx;
-    struct cvmx_pcsxx_bist_status_reg_s  cn52xxp1;
-    struct cvmx_pcsxx_bist_status_reg_s  cn56xx;
-    struct cvmx_pcsxx_bist_status_reg_s  cn56xxp1;
-} cvmx_pcsxx_bist_status_reg_t;
-
-
-/**
- * cvmx_pcsx#_bit_lock_status_reg
- *
- * LN_SWAP for XAUI is to simplify interconnection layout between devices
- * 
- * 
- * PCSX Bit Lock Status Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_bit_lock_status_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t bitlck3                 : 1;       /**< Receive Lane 3 bit lock status */
-        uint64_t bitlck2                 : 1;       /**< Receive Lane 2 bit lock status */
-        uint64_t bitlck1                 : 1;       /**< Receive Lane 1 bit lock status */
-        uint64_t bitlck0                 : 1;       /**< Receive Lane 0 bit lock status */
-#else
-        uint64_t bitlck0                 : 1;
-        uint64_t bitlck1                 : 1;
-        uint64_t bitlck2                 : 1;
-        uint64_t bitlck3                 : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
-    struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
-    struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
-    struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
-} cvmx_pcsxx_bit_lock_status_reg_t;
-
-
-/**
- * cvmx_pcsx#_control1_reg
- *
- * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
- * For normal operation(sgmii or 1000Base-X), this bit must be 0.
- * See pcsx.csr for xaui logic analyzer mode.
- * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
- * 
- * 
- *  PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3
- * 
- * 
- *  PCSX_CONTROL1_REG = Control Register1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_control1_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t reset                   : 1;       /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
-                                                         has been reset. Takes 32 eclk cycles to reset pcs
-                                                         0=Normal operation */
-        uint64_t loopbck1                : 1;       /**< 0=normal operation, 1=internal loopback mode
-                                                         xgmii tx data received from gmx tx port is returned
-                                                         back into gmx, xgmii rx port. */
-        uint64_t spdsel1                 : 1;       /**< See bit 6 description */
-        uint64_t reserved_12_12          : 1;
-        uint64_t lo_pwr                  : 1;       /**< The status of this bit has no effect on operation
-                                                         of the PCS sublayer. */
-        uint64_t reserved_7_10           : 4;
-        uint64_t spdsel0                 : 1;       /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has
-                                                         no effect.
-                                                         [<6>, <13>]Link Speed selection
-                                                           1    1   Bits 5:2 select speed */
-        uint64_t spd                     : 4;       /**< Always select 10Gb/s, writes have no effect */
-        uint64_t reserved_0_1            : 2;
-#else
-        uint64_t reserved_0_1            : 2;
-        uint64_t spd                     : 4;
-        uint64_t spdsel0                 : 1;
-        uint64_t reserved_7_10           : 4;
-        uint64_t lo_pwr                  : 1;
-        uint64_t reserved_12_12          : 1;
-        uint64_t spdsel1                 : 1;
-        uint64_t loopbck1                : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsxx_control1_reg_s     cn52xx;
-    struct cvmx_pcsxx_control1_reg_s     cn52xxp1;
-    struct cvmx_pcsxx_control1_reg_s     cn56xx;
-    struct cvmx_pcsxx_control1_reg_s     cn56xxp1;
-} cvmx_pcsxx_control1_reg_t;
-
-
-/**
- * cvmx_pcsx#_control2_reg
- *
- * PCSX_CONTROL2_REG = Control Register2
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_control2_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t type                    : 2;       /**< Always 2'b01, 10GBASE-X only supported */
-#else
-        uint64_t type                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pcsxx_control2_reg_s     cn52xx;
-    struct cvmx_pcsxx_control2_reg_s     cn52xxp1;
-    struct cvmx_pcsxx_control2_reg_s     cn56xx;
-    struct cvmx_pcsxx_control2_reg_s     cn56xxp1;
-} cvmx_pcsxx_control2_reg_t;
-
-
-/**
- * cvmx_pcsx#_int_en_reg
- *
- * PCSX Interrupt Enable Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_int_en_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t algnlos_en              : 1;       /**< Enable ALGNLOS interrupt */
-        uint64_t synlos_en               : 1;       /**< Enable SYNLOS interrupt */
-        uint64_t bitlckls_en             : 1;       /**< Enable BITLCKLS interrupt */
-        uint64_t rxsynbad_en             : 1;       /**< Enable RXSYNBAD  interrupt */
-        uint64_t rxbad_en                : 1;       /**< Enable RXBAD  interrupt */
-        uint64_t txflt_en                : 1;       /**< Enable TXFLT   interrupt */
-#else
-        uint64_t txflt_en                : 1;
-        uint64_t rxbad_en                : 1;
-        uint64_t rxsynbad_en             : 1;
-        uint64_t bitlckls_en             : 1;
-        uint64_t synlos_en               : 1;
-        uint64_t algnlos_en              : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_pcsxx_int_en_reg_s       cn52xx;
-    struct cvmx_pcsxx_int_en_reg_s       cn52xxp1;
-    struct cvmx_pcsxx_int_en_reg_s       cn56xx;
-    struct cvmx_pcsxx_int_en_reg_s       cn56xxp1;
-} cvmx_pcsxx_int_en_reg_t;
-
-
-/**
- * cvmx_pcsx#_int_reg
- *
- * PCSX Interrupt Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t algnlos                 : 1;       /**< Set when XAUI lanes lose alignment */
-        uint64_t synlos                  : 1;       /**< Set when Code group sync lost on 1 or more  lanes */
-        uint64_t bitlckls                : 1;       /**< Set when Bit lock lost on 1 or more xaui lanes */
-        uint64_t rxsynbad                : 1;       /**< Set when RX code grp sync st machine in bad state
-                                                         in one of the 4 xaui lanes */
-        uint64_t rxbad                   : 1;       /**< Set when RX state machine in bad state */
-        uint64_t txflt                   : 1;       /**< None defined at this time, always 0x0 */
-#else
-        uint64_t txflt                   : 1;
-        uint64_t rxbad                   : 1;
-        uint64_t rxsynbad                : 1;
-        uint64_t bitlckls                : 1;
-        uint64_t synlos                  : 1;
-        uint64_t algnlos                 : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_pcsxx_int_reg_s          cn52xx;
-    struct cvmx_pcsxx_int_reg_s          cn52xxp1;
-    struct cvmx_pcsxx_int_reg_s          cn56xx;
-    struct cvmx_pcsxx_int_reg_s          cn56xxp1;
-} cvmx_pcsxx_int_reg_t;
-
-
-/**
- * cvmx_pcsx#_log_anl_reg
- *
- * PCSX Logic Analyzer Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_log_anl_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t enc_mode                : 1;       /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
-                                                         See .../rtl/pcs/readme_logic_analyzer.txt for details */
-        uint64_t drop_ln                 : 2;       /**< xaui lane# to drop from logic analyzer packets
-                                                         [<5>, <4>]  Drop lane \#
-                                                          0    0   Drop lane 0 data
-                                                          0    1   Drop lane 1 data
-                                                          1    0   Drop lane 2 data
-                                                          1    1   Drop lane 3 data */
-        uint64_t lafifovfl               : 1;       /**< 1=logic analyser fif overflowed one or more times
-                                                         during packetization.
-                                                         Write 1 to clear this bit */
-        uint64_t la_en                   : 1;       /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
-        uint64_t pkt_sz                  : 2;       /**< [<1>, <0>]  Logic Analyzer Packet Size
-                                                         0    0   Packet size 1k bytes
-                                                         0    1   Packet size 4k bytes
-                                                         1    0   Packet size 8k bytes
-                                                         1    1   Packet size 16k bytes */
-#else
-        uint64_t pkt_sz                  : 2;
-        uint64_t la_en                   : 1;
-        uint64_t lafifovfl               : 1;
-        uint64_t drop_ln                 : 2;
-        uint64_t enc_mode                : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_pcsxx_log_anl_reg_s      cn52xx;
-    struct cvmx_pcsxx_log_anl_reg_s      cn52xxp1;
-    struct cvmx_pcsxx_log_anl_reg_s      cn56xx;
-    struct cvmx_pcsxx_log_anl_reg_s      cn56xxp1;
-} cvmx_pcsxx_log_anl_reg_t;
-
-
-/**
- * cvmx_pcsx#_misc_ctl_reg
- *
- * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6>  ^  [4[RXPLRT<1>]];
- * 
- * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2>  ^  [4[TXPLRT<0>]];
- * 
- * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities
- * 
- * 
- * 
- * PCSX Misc Control Register
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_misc_ctl_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t tx_swap                 : 1;       /**< 0=do not swap xaui lanes going out to qlm's
-                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
-        uint64_t rx_swap                 : 1;       /**< 0=do not swap xaui lanes coming in from qlm's
-                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
-        uint64_t xaui                    : 1;       /**< 1=XAUI mode selected, 0=not XAUI mode selected
-                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
-        uint64_t gmxeno                  : 1;       /**< GMX port enable override, GMX en/dis status is held
-                                                         during data packet reception. */
-#else
-        uint64_t gmxeno                  : 1;
-        uint64_t xaui                    : 1;
-        uint64_t rx_swap                 : 1;
-        uint64_t tx_swap                 : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pcsxx_misc_ctl_reg_s     cn52xx;
-    struct cvmx_pcsxx_misc_ctl_reg_s     cn52xxp1;
-    struct cvmx_pcsxx_misc_ctl_reg_s     cn56xx;
-    struct cvmx_pcsxx_misc_ctl_reg_s     cn56xxp1;
-} cvmx_pcsxx_misc_ctl_reg_t;
-
-
-/**
- * cvmx_pcsx#_rx_sync_states_reg
- *
- * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_rx_sync_states_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t sync3st                 : 4;       /**< Receive lane 3 code grp sync state machine state */
-        uint64_t sync2st                 : 4;       /**< Receive lane 2 code grp sync state machine state */
-        uint64_t sync1st                 : 4;       /**< Receive lane 1 code grp sync state machine state */
-        uint64_t sync0st                 : 4;       /**< Receive lane 0 code grp sync state machine state */
-#else
-        uint64_t sync0st                 : 4;
-        uint64_t sync1st                 : 4;
-        uint64_t sync2st                 : 4;
-        uint64_t sync3st                 : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
-    struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
-    struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
-    struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
-} cvmx_pcsxx_rx_sync_states_reg_t;
-
-
-/**
- * cvmx_pcsx#_spd_abil_reg
- *
- * PCSX_SPD_ABIL_REG = Speed ability register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_spd_abil_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t tenpasst                : 1;       /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
-        uint64_t tengb                   : 1;       /**< Always 1, 10Gb/s supported */
-#else
-        uint64_t tengb                   : 1;
-        uint64_t tenpasst                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pcsxx_spd_abil_reg_s     cn52xx;
-    struct cvmx_pcsxx_spd_abil_reg_s     cn52xxp1;
-    struct cvmx_pcsxx_spd_abil_reg_s     cn56xx;
-    struct cvmx_pcsxx_spd_abil_reg_s     cn56xxp1;
-} cvmx_pcsxx_spd_abil_reg_t;
-
-
-/**
- * cvmx_pcsx#_status1_reg
- *
- * PCSX_STATUS1_REG = Status Register1
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_status1_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t flt                     : 1;       /**< 1=Fault condition detected, 0=No fault condition
-                                                         This bit is a logical OR of Status2 reg bits 11,10 */
-        uint64_t reserved_3_6            : 4;
-        uint64_t rcv_lnk                 : 1;       /**< 1=Receive Link up, 0=Receive Link down
-                                                         Latching Low version of r_10gbx_status_reg[12],
-                                                         Link down status continues until SW read. */
-        uint64_t lpable                  : 1;       /**< Always set to 1 for Low Power ablility indication */
-        uint64_t reserved_0_0            : 1;
-#else
-        uint64_t reserved_0_0            : 1;
-        uint64_t lpable                  : 1;
-        uint64_t rcv_lnk                 : 1;
-        uint64_t reserved_3_6            : 4;
-        uint64_t flt                     : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pcsxx_status1_reg_s      cn52xx;
-    struct cvmx_pcsxx_status1_reg_s      cn52xxp1;
-    struct cvmx_pcsxx_status1_reg_s      cn56xx;
-    struct cvmx_pcsxx_status1_reg_s      cn56xxp1;
-} cvmx_pcsxx_status1_reg_t;
-
-
-/**
- * cvmx_pcsx#_status2_reg
- *
- * PCSX_STATUS2_REG = Status Register2
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_status2_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t dev                     : 2;       /**< Always at 2'b10, means a Device present at the addr */
-        uint64_t reserved_12_13          : 2;
-        uint64_t xmtflt                  : 1;       /**< 0=No xmit fault, 1=xmit fault. Implements latching
-                                                         High function until SW read. */
-        uint64_t rcvflt                  : 1;       /**< 0=No rcv fault, 1=rcv fault. Implements latching
-                                                         High function until SW read */
-        uint64_t reserved_3_9            : 7;
-        uint64_t tengb_w                 : 1;       /**< Always 0, no 10GBASE-W capability */
-        uint64_t tengb_x                 : 1;       /**< Always 1, 10GBASE-X capable */
-        uint64_t tengb_r                 : 1;       /**< Always 0, no 10GBASE-R capability */
-#else
-        uint64_t tengb_r                 : 1;
-        uint64_t tengb_x                 : 1;
-        uint64_t tengb_w                 : 1;
-        uint64_t reserved_3_9            : 7;
-        uint64_t rcvflt                  : 1;
-        uint64_t xmtflt                  : 1;
-        uint64_t reserved_12_13          : 2;
-        uint64_t dev                     : 2;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pcsxx_status2_reg_s      cn52xx;
-    struct cvmx_pcsxx_status2_reg_s      cn52xxp1;
-    struct cvmx_pcsxx_status2_reg_s      cn56xx;
-    struct cvmx_pcsxx_status2_reg_s      cn56xxp1;
-} cvmx_pcsxx_status2_reg_t;
-
-
-/**
- * cvmx_pcsx#_tx_rx_polarity_reg
- *
- * PCSX_POLARITY_REG = TX_RX polarity reg
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_tx_rx_polarity_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t xor_rxplrt              : 4;       /**< Per lane RX polarity control */
-        uint64_t xor_txplrt              : 4;       /**< Per lane TX polarity control */
-        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-#else
-        uint64_t txplrt                  : 1;
-        uint64_t rxplrt                  : 1;
-        uint64_t xor_txplrt              : 4;
-        uint64_t xor_rxplrt              : 4;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
-    struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
-#else
-        uint64_t txplrt                  : 1;
-        uint64_t rxplrt                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn52xxp1;
-    struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
-    struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
-} cvmx_pcsxx_tx_rx_polarity_reg_t;
-
-
-/**
- * cvmx_pcsx#_tx_rx_states_reg
- *
- * PCSX_TX_RX_STATES_REG = Transmit Receive States Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pcsxx_tx_rx_states_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t term_err                : 1;       /**< 1=Check end function detected error in packet
-                                                         terminate ||T|| column or the one after it */
-        uint64_t syn3bad                 : 1;       /**< 1=lane 3 code grp sync state machine in bad state */
-        uint64_t syn2bad                 : 1;       /**< 1=lane 2 code grp sync state machine in bad state */
-        uint64_t syn1bad                 : 1;       /**< 1=lane 1 code grp sync state machine in bad state */
-        uint64_t syn0bad                 : 1;       /**< 1=lane 0 code grp sync state machine in bad state */
-        uint64_t rxbad                   : 1;       /**< 1=Rcv state machine in a bad state, HW malfunction */
-        uint64_t algn_st                 : 3;       /**< Lane alignment state machine state state */
-        uint64_t rx_st                   : 2;       /**< Receive state machine state state */
-        uint64_t tx_st                   : 3;       /**< Transmit state machine state state */
-#else
-        uint64_t tx_st                   : 3;
-        uint64_t rx_st                   : 2;
-        uint64_t algn_st                 : 3;
-        uint64_t rxbad                   : 1;
-        uint64_t syn0bad                 : 1;
-        uint64_t syn1bad                 : 1;
-        uint64_t syn2bad                 : 1;
-        uint64_t syn3bad                 : 1;
-        uint64_t term_err                : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
-    struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t syn3bad                 : 1;       /**< 1=lane 3 code grp sync state machine in bad state */
-        uint64_t syn2bad                 : 1;       /**< 1=lane 2 code grp sync state machine in bad state */
-        uint64_t syn1bad                 : 1;       /**< 1=lane 1 code grp sync state machine in bad state */
-        uint64_t syn0bad                 : 1;       /**< 1=lane 0 code grp sync state machine in bad state */
-        uint64_t rxbad                   : 1;       /**< 1=Rcv state machine in a bad state, HW malfunction */
-        uint64_t algn_st                 : 3;       /**< Lane alignment state machine state state */
-        uint64_t rx_st                   : 2;       /**< Receive state machine state state */
-        uint64_t tx_st                   : 3;       /**< Transmit state machine state state */
-#else
-        uint64_t tx_st                   : 3;
-        uint64_t rx_st                   : 2;
-        uint64_t algn_st                 : 3;
-        uint64_t rxbad                   : 1;
-        uint64_t syn0bad                 : 1;
-        uint64_t syn1bad                 : 1;
-        uint64_t syn2bad                 : 1;
-        uint64_t syn3bad                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn52xxp1;
-    struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
-    struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
-} cvmx_pcsxx_tx_rx_states_reg_t;
-
-
-/**
- * cvmx_pesc#_bist_status
- *
- * PESC_BIST_STATUS = PESC Bist Status
- * 
- * Contains the diffrent interrupt summary bits of the PESC.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t rqdata5                 : 1;       /**< Rx Queue Data Memory5. */
-        uint64_t ctlp_or                 : 1;       /**< C-TLP Order Fifo. */
-        uint64_t ntlp_or                 : 1;       /**< N-TLP Order Fifo. */
-        uint64_t ptlp_or                 : 1;       /**< P-TLP Order Fifo. */
-        uint64_t retry                   : 1;       /**< Retry Buffer. */
-        uint64_t rqdata0                 : 1;       /**< Rx Queue Data Memory0. */
-        uint64_t rqdata1                 : 1;       /**< Rx Queue Data Memory1. */
-        uint64_t rqdata2                 : 1;       /**< Rx Queue Data Memory2. */
-        uint64_t rqdata3                 : 1;       /**< Rx Queue Data Memory3. */
-        uint64_t rqdata4                 : 1;       /**< Rx Queue Data Memory4. */
-        uint64_t rqhdr1                  : 1;       /**< Rx Queue Header1. */
-        uint64_t rqhdr0                  : 1;       /**< Rx Queue Header0. */
-        uint64_t sot                     : 1;       /**< SOT Buffer. */
-#else
-        uint64_t sot                     : 1;
-        uint64_t rqhdr0                  : 1;
-        uint64_t rqhdr1                  : 1;
-        uint64_t rqdata4                 : 1;
-        uint64_t rqdata3                 : 1;
-        uint64_t rqdata2                 : 1;
-        uint64_t rqdata1                 : 1;
-        uint64_t rqdata0                 : 1;
-        uint64_t retry                   : 1;
-        uint64_t ptlp_or                 : 1;
-        uint64_t ntlp_or                 : 1;
-        uint64_t ctlp_or                 : 1;
-        uint64_t rqdata5                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pescx_bist_status_s      cn52xx;
-    struct cvmx_pescx_bist_status_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t ctlp_or                 : 1;       /**< C-TLP Order Fifo. */
-        uint64_t ntlp_or                 : 1;       /**< N-TLP Order Fifo. */
-        uint64_t ptlp_or                 : 1;       /**< P-TLP Order Fifo. */
-        uint64_t retry                   : 1;       /**< Retry Buffer. */
-        uint64_t rqdata0                 : 1;       /**< Rx Queue Data Memory0. */
-        uint64_t rqdata1                 : 1;       /**< Rx Queue Data Memory1. */
-        uint64_t rqdata2                 : 1;       /**< Rx Queue Data Memory2. */
-        uint64_t rqdata3                 : 1;       /**< Rx Queue Data Memory3. */
-        uint64_t rqdata4                 : 1;       /**< Rx Queue Data Memory4. */
-        uint64_t rqhdr1                  : 1;       /**< Rx Queue Header1. */
-        uint64_t rqhdr0                  : 1;       /**< Rx Queue Header0. */
-        uint64_t sot                     : 1;       /**< SOT Buffer. */
-#else
-        uint64_t sot                     : 1;
-        uint64_t rqhdr0                  : 1;
-        uint64_t rqhdr1                  : 1;
-        uint64_t rqdata4                 : 1;
-        uint64_t rqdata3                 : 1;
-        uint64_t rqdata2                 : 1;
-        uint64_t rqdata1                 : 1;
-        uint64_t rqdata0                 : 1;
-        uint64_t retry                   : 1;
-        uint64_t ptlp_or                 : 1;
-        uint64_t ntlp_or                 : 1;
-        uint64_t ctlp_or                 : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn52xxp1;
-    struct cvmx_pescx_bist_status_s      cn56xx;
-    struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
-} cvmx_pescx_bist_status_t;
-
-
-/**
- * cvmx_pesc#_bist_status2
- *
- * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
- * 
- * Results from BIST runs of PESC's memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_bist_status2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t cto_p2e                 : 1;       /**< BIST Status for the cto_p2e_fifo */
-        uint64_t e2p_cpl                 : 1;       /**< BIST Status for the e2p_cpl_fifo */
-        uint64_t e2p_n                   : 1;       /**< BIST Status for the e2p_n_fifo */
-        uint64_t e2p_p                   : 1;       /**< BIST Status for the e2p_p_fifo */
-        uint64_t e2p_rsl                 : 1;       /**< BIST Status for the e2p_rsl__fifo */
-        uint64_t dbg_p2e                 : 1;       /**< BIST Status for the dbg_p2e_fifo */
-        uint64_t peai_p2e                : 1;       /**< BIST Status for the peai__pesc_fifo */
-        uint64_t rsl_p2e                 : 1;       /**< BIST Status for the rsl_p2e_fifo */
-        uint64_t pef_tpf1                : 1;       /**< BIST Status for the pef_tlp_p_fifo1 */
-        uint64_t pef_tpf0                : 1;       /**< BIST Status for the pef_tlp_p_fifo0 */
-        uint64_t pef_tnf                 : 1;       /**< BIST Status for the pef_tlp_n_fifo */
-        uint64_t pef_tcf1                : 1;       /**< BIST Status for the pef_tlp_cpl_fifo1 */
-        uint64_t pef_tc0                 : 1;       /**< BIST Status for the pef_tlp_cpl_fifo0 */
-        uint64_t ppf                     : 1;       /**< BIST Status for the ppf_fifo */
-#else
-        uint64_t ppf                     : 1;
-        uint64_t pef_tc0                 : 1;
-        uint64_t pef_tcf1                : 1;
-        uint64_t pef_tnf                 : 1;
-        uint64_t pef_tpf0                : 1;
-        uint64_t pef_tpf1                : 1;
-        uint64_t rsl_p2e                 : 1;
-        uint64_t peai_p2e                : 1;
-        uint64_t dbg_p2e                 : 1;
-        uint64_t e2p_rsl                 : 1;
-        uint64_t e2p_p                   : 1;
-        uint64_t e2p_n                   : 1;
-        uint64_t e2p_cpl                 : 1;
-        uint64_t cto_p2e                 : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_pescx_bist_status2_s     cn52xx;
-    struct cvmx_pescx_bist_status2_s     cn52xxp1;
-    struct cvmx_pescx_bist_status2_s     cn56xx;
-    struct cvmx_pescx_bist_status2_s     cn56xxp1;
-} cvmx_pescx_bist_status2_t;
-
-
-/**
- * cvmx_pesc#_cfg_rd
- *
- * PESC_CFG_RD = PESC Configuration Read
- * 
- * Allows read access to the configuration in the PCIe Core.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_cfg_rd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 32;      /**< Data. */
-        uint64_t addr                    : 32;      /**< Address to read. A write to this register
-                                                         starts a read operation. */
-#else
-        uint64_t addr                    : 32;
-        uint64_t data                    : 32;
-#endif
-    } s;
-    struct cvmx_pescx_cfg_rd_s           cn52xx;
-    struct cvmx_pescx_cfg_rd_s           cn52xxp1;
-    struct cvmx_pescx_cfg_rd_s           cn56xx;
-    struct cvmx_pescx_cfg_rd_s           cn56xxp1;
-} cvmx_pescx_cfg_rd_t;
-
-
-/**
- * cvmx_pesc#_cfg_wr
- *
- * PESC_CFG_WR = PESC Configuration Write
- * 
- * Allows write access to the configuration in the PCIe Core.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_cfg_wr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 32;      /**< Data to write. A write to this register starts
-                                                         a write operation. */
-        uint64_t addr                    : 32;      /**< Address to write. A write to this register starts
-                                                         a write operation. */
-#else
-        uint64_t addr                    : 32;
-        uint64_t data                    : 32;
-#endif
-    } s;
-    struct cvmx_pescx_cfg_wr_s           cn52xx;
-    struct cvmx_pescx_cfg_wr_s           cn52xxp1;
-    struct cvmx_pescx_cfg_wr_s           cn56xx;
-    struct cvmx_pescx_cfg_wr_s           cn56xxp1;
-} cvmx_pescx_cfg_wr_t;
-
-
-/**
- * cvmx_pesc#_cpl_lut_valid
- *
- * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid
- * 
- * Bit set for outstanding tag read.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_cpl_lut_valid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t tag                     : 32;      /**< Bit vector set cooresponds to an outstanding tag
-                                                         expecting a completion. */
-#else
-        uint64_t tag                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pescx_cpl_lut_valid_s    cn52xx;
-    struct cvmx_pescx_cpl_lut_valid_s    cn52xxp1;
-    struct cvmx_pescx_cpl_lut_valid_s    cn56xx;
-    struct cvmx_pescx_cpl_lut_valid_s    cn56xxp1;
-} cvmx_pescx_cpl_lut_valid_t;
-
-
-/**
- * cvmx_pesc#_ctl_status
- *
- * PESC_CTL_STATUS = PESC Control Status
- * 
- * General control and status of the PESC.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t dnum                    : 5;       /**< Primary bus device number. */
-        uint64_t pbus                    : 8;       /**< Primary bus number. */
-        uint64_t qlm_cfg                 : 2;       /**< The QLM configuration pad bits. */
-        uint64_t lane_swp                : 1;       /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1'
-                                                         enables LANE SWAP. THis bit has no effect on PEDC0.
-                                                         This bit should be set before enabling PEDC1. */
-        uint64_t pm_xtoff                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
-        uint64_t pm_xpme                 : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core pm_xmt_pme port. EP mode. */
-        uint64_t ob_p_cmd                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
-        uint64_t reserved_7_8            : 2;
-        uint64_t nf_ecrc                 : 1;       /**< Do not forward peer-to-peer ECRC TLPs. */
-        uint64_t dly_one                 : 1;       /**< When set the output client state machines will
-                                                         wait one cycle before starting a new TLP out. */
-        uint64_t lnk_enb                 : 1;       /**< When set '1' the link is enabled when '0' the
-                                                         link is disabled. This bit only is active when in
-                                                         RC mode. */
-        uint64_t ro_ctlp                 : 1;       /**< When set '1' C-TLPs that have the RO bit set will
-                                                         not wait for P-TLPs that normaly would be sent
-                                                         first. */
-        uint64_t reserved_2_2            : 1;
-        uint64_t inv_ecrc                : 1;       /**< When '1' causes the LSB of the ECRC to be inverted. */
-        uint64_t inv_lcrc                : 1;       /**< When '1' causes the LSB of the LCRC to be inverted. */
-#else
-        uint64_t inv_lcrc                : 1;
-        uint64_t inv_ecrc                : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t ro_ctlp                 : 1;
-        uint64_t lnk_enb                 : 1;
-        uint64_t dly_one                 : 1;
-        uint64_t nf_ecrc                 : 1;
-        uint64_t reserved_7_8            : 2;
-        uint64_t ob_p_cmd                : 1;
-        uint64_t pm_xpme                 : 1;
-        uint64_t pm_xtoff                : 1;
-        uint64_t lane_swp                : 1;
-        uint64_t qlm_cfg                 : 2;
-        uint64_t pbus                    : 8;
-        uint64_t dnum                    : 5;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_pescx_ctl_status_s       cn52xx;
-    struct cvmx_pescx_ctl_status_s       cn52xxp1;
-    struct cvmx_pescx_ctl_status_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t dnum                    : 5;       /**< Primary bus device number. */
-        uint64_t pbus                    : 8;       /**< Primary bus number. */
-        uint64_t qlm_cfg                 : 2;       /**< The QLM configuration pad bits. */
-        uint64_t reserved_12_12          : 1;
-        uint64_t pm_xtoff                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
-        uint64_t pm_xpme                 : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core pm_xmt_pme port. EP mode. */
-        uint64_t ob_p_cmd                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
-                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
-        uint64_t reserved_7_8            : 2;
-        uint64_t nf_ecrc                 : 1;       /**< Do not forward peer-to-peer ECRC TLPs. */
-        uint64_t dly_one                 : 1;       /**< When set the output client state machines will
-                                                         wait one cycle before starting a new TLP out. */
-        uint64_t lnk_enb                 : 1;       /**< When set '1' the link is enabled when '0' the
-                                                         link is disabled. This bit only is active when in
-                                                         RC mode. */
-        uint64_t ro_ctlp                 : 1;       /**< When set '1' C-TLPs that have the RO bit set will
-                                                         not wait for P-TLPs that normaly would be sent
-                                                         first. */
-        uint64_t reserved_2_2            : 1;
-        uint64_t inv_ecrc                : 1;       /**< When '1' causes the LSB of the ECRC to be inverted. */
-        uint64_t inv_lcrc                : 1;       /**< When '1' causes the LSB of the LCRC to be inverted. */
-#else
-        uint64_t inv_lcrc                : 1;
-        uint64_t inv_ecrc                : 1;
-        uint64_t reserved_2_2            : 1;
-        uint64_t ro_ctlp                 : 1;
-        uint64_t lnk_enb                 : 1;
-        uint64_t dly_one                 : 1;
-        uint64_t nf_ecrc                 : 1;
-        uint64_t reserved_7_8            : 2;
-        uint64_t ob_p_cmd                : 1;
-        uint64_t pm_xpme                 : 1;
-        uint64_t pm_xtoff                : 1;
-        uint64_t reserved_12_12          : 1;
-        uint64_t qlm_cfg                 : 2;
-        uint64_t pbus                    : 8;
-        uint64_t dnum                    : 5;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn56xx;
-    struct cvmx_pescx_ctl_status_cn56xx  cn56xxp1;
-} cvmx_pescx_ctl_status_t;
-
-
-/**
- * cvmx_pesc#_ctl_status2
- *
- * Below are in PESC
- * 
- *                  PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
- * 
- * Results from BIST runs of PESC's memories.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_ctl_status2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t pclk_run                : 1;       /**< When the pce_clk is running this bit will be '1'.
-                                                         Writing a '1' to this location will cause the
-                                                         bit to be cleared, but if the pce_clk is running
-                                                         this bit will be re-set. */
-        uint64_t pcierst                 : 1;       /**< Set to '1' when PCIe is in reset. */
-#else
-        uint64_t pcierst                 : 1;
-        uint64_t pclk_run                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pescx_ctl_status2_s      cn52xx;
-    struct cvmx_pescx_ctl_status2_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t pcierst                 : 1;       /**< Set to '1' when PCIe is in reset. */
-#else
-        uint64_t pcierst                 : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } cn52xxp1;
-    struct cvmx_pescx_ctl_status2_s      cn56xx;
-    struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
-} cvmx_pescx_ctl_status2_t;
-
-
-/**
- * cvmx_pesc#_dbg_info
- *
- * PESC(0..1)_DBG_INFO = PESC Debug Information
- * 
- * General debug info.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_dbg_info_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t ecrc_e                  : 1;       /**< Received a ECRC error.
-                                                         radm_ecrc_err */
-        uint64_t rawwpp                  : 1;       /**< Received a write with poisoned payload
-                                                         radm_rcvd_wreq_poisoned */
-        uint64_t racpp                   : 1;       /**< Received a completion with poisoned payload
-                                                         radm_rcvd_cpl_poisoned */
-        uint64_t ramtlp                  : 1;       /**< Received a malformed TLP
-                                                         radm_mlf_tlp_err */
-        uint64_t rarwdns                 : 1;       /**< Recieved a request which device does not support
-                                                         radm_rcvd_ur_req */
-        uint64_t caar                    : 1;       /**< Completer aborted a request
-                                                         radm_rcvd_ca_req
-                                                         This bit will never be set because Octeon does
-                                                         not generate Completer Aborts. */
-        uint64_t racca                   : 1;       /**< Received a completion with CA status
-                                                         radm_rcvd_cpl_ca */
-        uint64_t racur                   : 1;       /**< Received a completion with UR status
-                                                         radm_rcvd_cpl_ur */
-        uint64_t rauc                    : 1;       /**< Received an unexpected completion
-                                                         radm_unexp_cpl_err */
-        uint64_t rqo                     : 1;       /**< Receive queue overflow. Normally happens only when
-                                                         flow control advertisements are ignored
-                                                         radm_qoverflow */
-        uint64_t fcuv                    : 1;       /**< Flow Control Update Violation (opt. checks)
-                                                         int_xadm_fc_prot_err */
-        uint64_t rpe                     : 1;       /**< When the PHY reports 8B/10B decode error
-                                                         (RxStatus = 3b100) or disparity error
-                                                         (RxStatus = 3b111), the signal rmlh_rcvd_err will
-                                                         be asserted.
-                                                         rmlh_rcvd_err */
-        uint64_t fcpvwt                  : 1;       /**< Flow Control Protocol Violation (Watchdog Timer)
-                                                         rtlh_fc_prot_err */
-        uint64_t dpeoosd                 : 1;       /**< DLLP protocol error (out of sequence DLLP)
-                                                         rdlh_prot_err */
-        uint64_t rtwdle                  : 1;       /**< Received TLP with DataLink Layer Error
-                                                         rdlh_bad_tlp_err */
-        uint64_t rdwdle                  : 1;       /**< Received DLLP with DataLink Layer Error
-                                                         rdlh_bad_dllp_err */
-        uint64_t mre                     : 1;       /**< Max Retries Exceeded
-                                                         xdlh_replay_num_rlover_err */
-        uint64_t rte                     : 1;       /**< Replay Timer Expired
-                                                         xdlh_replay_timeout_err
-                                                         This bit is set when the REPLAY_TIMER expires in
-                                                         the PCIE core. The probability of this bit being
-                                                         set will increase with the traffic load. */
-        uint64_t acto                    : 1;       /**< A Completion Timeout Occured
-                                                         pedc_radm_cpl_timeout */
-        uint64_t rvdm                    : 1;       /**< Received Vendor-Defined Message
-                                                         pedc_radm_vendor_msg */
-        uint64_t rumep                   : 1;       /**< Received Unlock Message (EP Mode Only)
-                                                         pedc_radm_msg_unlock */
-        uint64_t rptamrc                 : 1;       /**< Received PME Turnoff Acknowledge Message
-                                                         (RC Mode only)
-                                                         pedc_radm_pm_to_ack */
-        uint64_t rpmerc                  : 1;       /**< Received PME Message (RC Mode only)
-                                                         pedc_radm_pm_pme */
-        uint64_t rfemrc                  : 1;       /**< Received Fatal Error Message (RC Mode only)
-                                                         pedc_radm_fatal_err
-                                                         Bit set when a message with ERR_FATAL is set. */
-        uint64_t rnfemrc                 : 1;       /**< Received Non-Fatal Error Message (RC Mode only)
-                                                         pedc_radm_nonfatal_err */
-        uint64_t rcemrc                  : 1;       /**< Received Correctable Error Message (RC Mode only)
-                                                         pedc_radm_correctable_err */
-        uint64_t rpoison                 : 1;       /**< Received Poisoned TLP
-                                                         pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
-        uint64_t recrce                  : 1;       /**< Received ECRC Error
-                                                         pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
-        uint64_t rtlplle                 : 1;       /**< Received TLP has link layer error
-                                                         pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
-        uint64_t rtlpmal                 : 1;       /**< Received TLP is malformed or a message.
-                                                         pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
-                                                         If the core receives a MSG (or Vendor Message)
-                                                         this bit will be set. */
-        uint64_t spoison                 : 1;       /**< Poisoned TLP sent
-                                                         peai__client0_tlp_ep & peai__client0_tlp_hv */
-#else
-        uint64_t spoison                 : 1;
-        uint64_t rtlpmal                 : 1;
-        uint64_t rtlplle                 : 1;
-        uint64_t recrce                  : 1;
-        uint64_t rpoison                 : 1;
-        uint64_t rcemrc                  : 1;
-        uint64_t rnfemrc                 : 1;
-        uint64_t rfemrc                  : 1;
-        uint64_t rpmerc                  : 1;
-        uint64_t rptamrc                 : 1;
-        uint64_t rumep                   : 1;
-        uint64_t rvdm                    : 1;
-        uint64_t acto                    : 1;
-        uint64_t rte                     : 1;
-        uint64_t mre                     : 1;
-        uint64_t rdwdle                  : 1;
-        uint64_t rtwdle                  : 1;
-        uint64_t dpeoosd                 : 1;
-        uint64_t fcpvwt                  : 1;
-        uint64_t rpe                     : 1;
-        uint64_t fcuv                    : 1;
-        uint64_t rqo                     : 1;
-        uint64_t rauc                    : 1;
-        uint64_t racur                   : 1;
-        uint64_t racca                   : 1;
-        uint64_t caar                    : 1;
-        uint64_t rarwdns                 : 1;
-        uint64_t ramtlp                  : 1;
-        uint64_t racpp                   : 1;
-        uint64_t rawwpp                  : 1;
-        uint64_t ecrc_e                  : 1;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_pescx_dbg_info_s         cn52xx;
-    struct cvmx_pescx_dbg_info_s         cn52xxp1;
-    struct cvmx_pescx_dbg_info_s         cn56xx;
-    struct cvmx_pescx_dbg_info_s         cn56xxp1;
-} cvmx_pescx_dbg_info_t;
-
-
-/**
- * cvmx_pesc#_dbg_info_en
- *
- * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable
- * 
- * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_dbg_info_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t ecrc_e                  : 1;       /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */
-        uint64_t rawwpp                  : 1;       /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */
-        uint64_t racpp                   : 1;       /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */
-        uint64_t ramtlp                  : 1;       /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */
-        uint64_t rarwdns                 : 1;       /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */
-        uint64_t caar                    : 1;       /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */
-        uint64_t racca                   : 1;       /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */
-        uint64_t racur                   : 1;       /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */
-        uint64_t rauc                    : 1;       /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */
-        uint64_t rqo                     : 1;       /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */
-        uint64_t fcuv                    : 1;       /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */
-        uint64_t rpe                     : 1;       /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */
-        uint64_t fcpvwt                  : 1;       /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */
-        uint64_t dpeoosd                 : 1;       /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */
-        uint64_t rtwdle                  : 1;       /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */
-        uint64_t rdwdle                  : 1;       /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */
-        uint64_t mre                     : 1;       /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */
-        uint64_t rte                     : 1;       /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */
-        uint64_t acto                    : 1;       /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */
-        uint64_t rvdm                    : 1;       /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */
-        uint64_t rumep                   : 1;       /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */
-        uint64_t rptamrc                 : 1;       /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */
-        uint64_t rpmerc                  : 1;       /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */
-        uint64_t rfemrc                  : 1;       /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */
-        uint64_t rnfemrc                 : 1;       /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */
-        uint64_t rcemrc                  : 1;       /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */
-        uint64_t rpoison                 : 1;       /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */
-        uint64_t recrce                  : 1;       /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */
-        uint64_t rtlplle                 : 1;       /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */
-        uint64_t rtlpmal                 : 1;       /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */
-        uint64_t spoison                 : 1;       /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */
-#else
-        uint64_t spoison                 : 1;
-        uint64_t rtlpmal                 : 1;
-        uint64_t rtlplle                 : 1;
-        uint64_t recrce                  : 1;
-        uint64_t rpoison                 : 1;
-        uint64_t rcemrc                  : 1;
-        uint64_t rnfemrc                 : 1;
-        uint64_t rfemrc                  : 1;
-        uint64_t rpmerc                  : 1;
-        uint64_t rptamrc                 : 1;
-        uint64_t rumep                   : 1;
-        uint64_t rvdm                    : 1;
-        uint64_t acto                    : 1;
-        uint64_t rte                     : 1;
-        uint64_t mre                     : 1;
-        uint64_t rdwdle                  : 1;
-        uint64_t rtwdle                  : 1;
-        uint64_t dpeoosd                 : 1;
-        uint64_t fcpvwt                  : 1;
-        uint64_t rpe                     : 1;
-        uint64_t fcuv                    : 1;
-        uint64_t rqo                     : 1;
-        uint64_t rauc                    : 1;
-        uint64_t racur                   : 1;
-        uint64_t racca                   : 1;
-        uint64_t caar                    : 1;
-        uint64_t rarwdns                 : 1;
-        uint64_t ramtlp                  : 1;
-        uint64_t racpp                   : 1;
-        uint64_t rawwpp                  : 1;
-        uint64_t ecrc_e                  : 1;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_pescx_dbg_info_en_s      cn52xx;
-    struct cvmx_pescx_dbg_info_en_s      cn52xxp1;
-    struct cvmx_pescx_dbg_info_en_s      cn56xx;
-    struct cvmx_pescx_dbg_info_en_s      cn56xxp1;
-} cvmx_pescx_dbg_info_en_t;
-
-
-/**
- * cvmx_pesc#_diag_status
- *
- * PESC_DIAG_STATUS = PESC Diagnostic Status
- * 
- * Selection control for the cores diagnostic bus.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_diag_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t pm_dst                  : 1;       /**< Current power management DSTATE. */
-        uint64_t pm_stat                 : 1;       /**< Power Management Status. */
-        uint64_t pm_en                   : 1;       /**< Power Management Event Enable. */
-        uint64_t aux_en                  : 1;       /**< Auxilary Power Enable. */
-#else
-        uint64_t aux_en                  : 1;
-        uint64_t pm_en                   : 1;
-        uint64_t pm_stat                 : 1;
-        uint64_t pm_dst                  : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pescx_diag_status_s      cn52xx;
-    struct cvmx_pescx_diag_status_s      cn52xxp1;
-    struct cvmx_pescx_diag_status_s      cn56xx;
-    struct cvmx_pescx_diag_status_s      cn56xxp1;
-} cvmx_pescx_diag_status_t;
-
-
-/**
- * cvmx_pesc#_p2n_bar0_start
- *
- * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start
- * 
- * The starting address for addresses to forwarded to the NPEI in RC Mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_p2n_bar0_start_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 50;      /**< The starting address of the 16KB address space that
-                                                         is the BAR0 address space. */
-        uint64_t reserved_0_13           : 14;
-#else
-        uint64_t reserved_0_13           : 14;
-        uint64_t addr                    : 50;
-#endif
-    } s;
-    struct cvmx_pescx_p2n_bar0_start_s   cn52xx;
-    struct cvmx_pescx_p2n_bar0_start_s   cn52xxp1;
-    struct cvmx_pescx_p2n_bar0_start_s   cn56xx;
-    struct cvmx_pescx_p2n_bar0_start_s   cn56xxp1;
-} cvmx_pescx_p2n_bar0_start_t;
-
-
-/**
- * cvmx_pesc#_p2n_bar1_start
- *
- * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start
- * 
- * The starting address for addresses to forwarded to the NPEI in RC Mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_p2n_bar1_start_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 38;      /**< The starting address of the 64KB address space
-                                                         that is the BAR1 address space. */
-        uint64_t reserved_0_25           : 26;
-#else
-        uint64_t reserved_0_25           : 26;
-        uint64_t addr                    : 38;
-#endif
-    } s;
-    struct cvmx_pescx_p2n_bar1_start_s   cn52xx;
-    struct cvmx_pescx_p2n_bar1_start_s   cn52xxp1;
-    struct cvmx_pescx_p2n_bar1_start_s   cn56xx;
-    struct cvmx_pescx_p2n_bar1_start_s   cn56xxp1;
-} cvmx_pescx_p2n_bar1_start_t;
-
-
-/**
- * cvmx_pesc#_p2n_bar2_start
- *
- * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start
- * 
- * The starting address for addresses to forwarded to the NPEI in RC Mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_p2n_bar2_start_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 25;      /**< The starting address of the 2^39 address space
-                                                         that is the BAR2 address space. */
-        uint64_t reserved_0_38           : 39;
-#else
-        uint64_t reserved_0_38           : 39;
-        uint64_t addr                    : 25;
-#endif
-    } s;
-    struct cvmx_pescx_p2n_bar2_start_s   cn52xx;
-    struct cvmx_pescx_p2n_bar2_start_s   cn52xxp1;
-    struct cvmx_pescx_p2n_bar2_start_s   cn56xx;
-    struct cvmx_pescx_p2n_bar2_start_s   cn56xxp1;
-} cvmx_pescx_p2n_bar2_start_t;
-
-
-/**
- * cvmx_pesc#_p2p_bar#_end
- *
- * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End
- * 
- * The ending address for addresses to forwarded to the PCIe peer port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_p2p_barx_end_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 52;      /**< The ending address of the address window created
-                                                         this field and the PESC_P2P_BAR0_START[63:12]
-                                                         field. The full 64-bits of address are created by:
-                                                         [ADDR[63:12], 12'b0]. */
-        uint64_t reserved_0_11           : 12;
-#else
-        uint64_t reserved_0_11           : 12;
-        uint64_t addr                    : 52;
-#endif
-    } s;
-    struct cvmx_pescx_p2p_barx_end_s     cn52xx;
-    struct cvmx_pescx_p2p_barx_end_s     cn52xxp1;
-    struct cvmx_pescx_p2p_barx_end_s     cn56xx;
-    struct cvmx_pescx_p2p_barx_end_s     cn56xxp1;
-} cvmx_pescx_p2p_barx_end_t;
-
-
-/**
- * cvmx_pesc#_p2p_bar#_start
- *
- * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start
- * 
- * The starting address and enable for addresses to forwarded to the PCIe peer port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_p2p_barx_start_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t addr                    : 52;      /**< The starting address of the address window created
-                                                         this field and the PESC_P2P_BAR0_END[63:12] field.
-                                                         The full 64-bits of address are created by:
-                                                         [ADDR[63:12], 12'b0]. */
-        uint64_t reserved_0_11           : 12;
-#else
-        uint64_t reserved_0_11           : 12;
-        uint64_t addr                    : 52;
-#endif
-    } s;
-    struct cvmx_pescx_p2p_barx_start_s   cn52xx;
-    struct cvmx_pescx_p2p_barx_start_s   cn52xxp1;
-    struct cvmx_pescx_p2p_barx_start_s   cn56xx;
-    struct cvmx_pescx_p2p_barx_start_s   cn56xxp1;
-} cvmx_pescx_p2p_barx_start_t;
-
-
-/**
- * cvmx_pesc#_tlp_credits
- *
- * PESC_TLP_CREDITS = PESC TLP Credits
- * 
- * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are
- * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pescx_tlp_credits_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pescx_tlp_credits_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t peai_ppf                : 8;       /**< TLP credits for Completion TLPs in the Peer.
-                                                         Legal values are 0x24 to 0x80. */
-        uint64_t pesc_cpl                : 8;       /**< TLP credits for Completion TLPs in the Peer.
-                                                         Legal values are 0x24 to 0x80. */
-        uint64_t pesc_np                 : 8;       /**< TLP credits for Non-Posted TLPs in the Peer.
-                                                         Legal values are 0x4 to 0x10. */
-        uint64_t pesc_p                  : 8;       /**< TLP credits for Posted TLPs in the Peer.
-                                                         Legal values are 0x24 to 0x80. */
-        uint64_t npei_cpl                : 8;       /**< TLP credits for Completion TLPs in the NPEI.
-                                                         Legal values are 0x24 to 0x80. */
-        uint64_t npei_np                 : 8;       /**< TLP credits for Non-Posted TLPs in the NPEI.
-                                                         Legal values are 0x4 to 0x10. */
-        uint64_t npei_p                  : 8;       /**< TLP credits for Posted TLPs in the NPEI.
-                                                         Legal values are 0x24 to 0x80. */
-#else
-        uint64_t npei_p                  : 8;
-        uint64_t npei_np                 : 8;
-        uint64_t npei_cpl                : 8;
-        uint64_t pesc_p                  : 8;
-        uint64_t pesc_np                 : 8;
-        uint64_t pesc_cpl                : 8;
-        uint64_t peai_ppf                : 8;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } cn52xx;
-    struct cvmx_pescx_tlp_credits_cn52xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t peai_ppf                : 8;       /**< TLP credits in core clk pre-buffer that holds TLPs
-                                                         being sent from PCIe Core to NPEI or PEER. */
-        uint64_t pesc_cpl                : 5;       /**< TLP credits for Completion TLPs in the Peer. */
-        uint64_t pesc_np                 : 5;       /**< TLP credits for Non-Posted TLPs in the Peer. */
-        uint64_t pesc_p                  : 5;       /**< TLP credits for Posted TLPs in the Peer. */
-        uint64_t npei_cpl                : 5;       /**< TLP credits for Completion TLPs in the NPEI. */
-        uint64_t npei_np                 : 5;       /**< TLP credits for Non-Posted TLPs in the NPEI. */
-        uint64_t npei_p                  : 5;       /**< TLP credits for Posted TLPs in the NPEI. */
-#else
-        uint64_t npei_p                  : 5;
-        uint64_t npei_np                 : 5;
-        uint64_t npei_cpl                : 5;
-        uint64_t pesc_p                  : 5;
-        uint64_t pesc_np                 : 5;
-        uint64_t pesc_cpl                : 5;
-        uint64_t peai_ppf                : 8;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } cn52xxp1;
-    struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
-    struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
-} cvmx_pescx_tlp_credits_t;
-
-
-/**
- * cvmx_pip_bck_prs
- *
- * PIP_BCK_PRS = PIP's Back Pressure Register
- * 
- * When to assert backpressure based on the todo list filling up
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_bck_prs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bckprs                  : 1;       /**< PIP is currently asserting backpressure to IOB
-                                                         Backpressure from PIP will assert when the
-                                                         entries to the todo list exceed HIWATER.
-                                                         Backpressure will be held until the todo entries
-                                                         is less than or equal to LOWATER. */
-        uint64_t reserved_13_62          : 50;
-        uint64_t hiwater                 : 5;       /**< Water mark in the todo list to assert backpressure
-                                                         Legal values are 1-26.  A 0 value will deadlock
-                                                         the machine.  A value > 26, will trash memory */
-        uint64_t reserved_5_7            : 3;
-        uint64_t lowater                 : 5;       /**< Water mark in the todo list to release backpressure
-                                                         The LOWATER value should be < HIWATER. */
-#else
-        uint64_t lowater                 : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t hiwater                 : 5;
-        uint64_t reserved_13_62          : 50;
-        uint64_t bckprs                  : 1;
-#endif
-    } s;
-    struct cvmx_pip_bck_prs_s            cn38xx;
-    struct cvmx_pip_bck_prs_s            cn38xxp2;
-    struct cvmx_pip_bck_prs_s            cn56xx;
-    struct cvmx_pip_bck_prs_s            cn56xxp1;
-    struct cvmx_pip_bck_prs_s            cn58xx;
-    struct cvmx_pip_bck_prs_s            cn58xxp1;
-} cvmx_pip_bck_prs_t;
-
-
-/**
- * cvmx_pip_bist_status
- *
- * PIP_BIST_STATUS = PIP's BIST Results
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t bist                    : 18;      /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         BIST. */
-#else
-        uint64_t bist                    : 18;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_pip_bist_status_s        cn30xx;
-    struct cvmx_pip_bist_status_s        cn31xx;
-    struct cvmx_pip_bist_status_s        cn38xx;
-    struct cvmx_pip_bist_status_s        cn38xxp2;
-    struct cvmx_pip_bist_status_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t bist                    : 17;      /**< BIST Results.
-                                                         HW sets a bit in BIST for for memory that fails
-                                                         BIST. */
-#else
-        uint64_t bist                    : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn50xx;
-    struct cvmx_pip_bist_status_s        cn52xx;
-    struct cvmx_pip_bist_status_s        cn52xxp1;
-    struct cvmx_pip_bist_status_s        cn56xx;
-    struct cvmx_pip_bist_status_s        cn56xxp1;
-    struct cvmx_pip_bist_status_s        cn58xx;
-    struct cvmx_pip_bist_status_s        cn58xxp1;
-} cvmx_pip_bist_status_t;
-
-
-/**
- * cvmx_pip_crc_ctl#
- *
- * PIP_CRC_CTL = PIP CRC Control Register
- * 
- * Controls datapath reflection when calculating CRC
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_crc_ctlx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t invres                  : 1;       /**< Invert the result */
-        uint64_t reflect                 : 1;       /**< Reflect the bits in each byte.
-                                                          Byte order does not change.
-                                                         - 0: CRC is calculated MSB to LSB
-                                                         - 1: CRC is calculated LSB to MSB */
-#else
-        uint64_t reflect                 : 1;
-        uint64_t invres                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pip_crc_ctlx_s           cn38xx;
-    struct cvmx_pip_crc_ctlx_s           cn38xxp2;
-    struct cvmx_pip_crc_ctlx_s           cn58xx;
-    struct cvmx_pip_crc_ctlx_s           cn58xxp1;
-} cvmx_pip_crc_ctlx_t;
-
-
-/**
- * cvmx_pip_crc_iv#
- *
- * PIP_CRC_IV = PIP CRC IV Register
- * 
- * Determines the IV used by the CRC algorithm
- *
- * Notes:
- * * PIP_CRC_IV
- * PIP_CRC_IV controls the initial state of the CRC algorithm.  Octane can
- * support a wide range of CRC algorithms and as such, the IV must be
- * carefully constructed to meet the specific algorithm.  The code below
- * determines the value to program into Octane based on the algorthim's IV
- * and width.  In the case of Octane, the width should always be 32.
- * 
- * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for
- * ports 16-31.
- * 
- *  unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
- *  [
- *    int i;
- *    int doit;
- *    unsigned int current_val = algorithm_iv;
- * 
- *    for(i = 0; i < w; i++) [
- *      doit = current_val & 0x1;
- * 
- *      if(doit) current_val ^= poly;
- *      assert(!(current_val & 0x1));
- * 
- *      current_val = (current_val >> 1) | (doit << (w-1));
- *    ]
- * 
- *    return current_val;
- *  ]
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_crc_ivx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iv                      : 32;      /**< IV used by the CRC algorithm.  Default is FCS32. */
-#else
-        uint64_t iv                      : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pip_crc_ivx_s            cn38xx;
-    struct cvmx_pip_crc_ivx_s            cn38xxp2;
-    struct cvmx_pip_crc_ivx_s            cn58xx;
-    struct cvmx_pip_crc_ivx_s            cn58xxp1;
-} cvmx_pip_crc_ivx_t;
-
-
-/**
- * cvmx_pip_dec_ipsec#
- *
- * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC
- * 
- * PIP sets the dec_ipsec based on TCP or UDP destination port.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_dec_ipsecx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t tcp                     : 1;       /**< This DPRT should be used for TCP packets */
-        uint64_t udp                     : 1;       /**< This DPRT should be used for UDP packets */
-        uint64_t dprt                    : 16;      /**< UDP or TCP destination port to match on */
-#else
-        uint64_t dprt                    : 16;
-        uint64_t udp                     : 1;
-        uint64_t tcp                     : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_pip_dec_ipsecx_s         cn30xx;
-    struct cvmx_pip_dec_ipsecx_s         cn31xx;
-    struct cvmx_pip_dec_ipsecx_s         cn38xx;
-    struct cvmx_pip_dec_ipsecx_s         cn38xxp2;
-    struct cvmx_pip_dec_ipsecx_s         cn50xx;
-    struct cvmx_pip_dec_ipsecx_s         cn52xx;
-    struct cvmx_pip_dec_ipsecx_s         cn52xxp1;
-    struct cvmx_pip_dec_ipsecx_s         cn56xx;
-    struct cvmx_pip_dec_ipsecx_s         cn56xxp1;
-    struct cvmx_pip_dec_ipsecx_s         cn58xx;
-    struct cvmx_pip_dec_ipsecx_s         cn58xxp1;
-} cvmx_pip_dec_ipsecx_t;
-
-
-/**
- * cvmx_pip_dsa_src_grp
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_dsa_src_grp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t map15                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map14                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map13                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map12                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map11                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map10                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map9                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map8                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map7                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map6                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map5                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map4                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map3                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map2                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map1                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map0                    : 4;       /**< DSA Group Algorithm
-                                                         Use the DSA source id to compute GRP
-                                                         (56xx pass2 only) */
-#else
-        uint64_t map0                    : 4;
-        uint64_t map1                    : 4;
-        uint64_t map2                    : 4;
-        uint64_t map3                    : 4;
-        uint64_t map4                    : 4;
-        uint64_t map5                    : 4;
-        uint64_t map6                    : 4;
-        uint64_t map7                    : 4;
-        uint64_t map8                    : 4;
-        uint64_t map9                    : 4;
-        uint64_t map10                   : 4;
-        uint64_t map11                   : 4;
-        uint64_t map12                   : 4;
-        uint64_t map13                   : 4;
-        uint64_t map14                   : 4;
-        uint64_t map15                   : 4;
-#endif
-    } s;
-    struct cvmx_pip_dsa_src_grp_s        cn52xx;
-    struct cvmx_pip_dsa_src_grp_s        cn52xxp1;
-    struct cvmx_pip_dsa_src_grp_s        cn56xx;
-} cvmx_pip_dsa_src_grp_t;
-
-
-/**
- * cvmx_pip_dsa_vid_grp
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_dsa_vid_grp_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t map15                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map14                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map13                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map12                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map11                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map10                   : 4;       /**< DSA Group Algorithm */
-        uint64_t map9                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map8                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map7                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map6                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map5                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map4                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map3                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map2                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map1                    : 4;       /**< DSA Group Algorithm */
-        uint64_t map0                    : 4;       /**< DSA Group Algorithm
-                                                         Use the DSA source id to compute GRP
-                                                         (56xx pass2 only) */
-#else
-        uint64_t map0                    : 4;
-        uint64_t map1                    : 4;
-        uint64_t map2                    : 4;
-        uint64_t map3                    : 4;
-        uint64_t map4                    : 4;
-        uint64_t map5                    : 4;
-        uint64_t map6                    : 4;
-        uint64_t map7                    : 4;
-        uint64_t map8                    : 4;
-        uint64_t map9                    : 4;
-        uint64_t map10                   : 4;
-        uint64_t map11                   : 4;
-        uint64_t map12                   : 4;
-        uint64_t map13                   : 4;
-        uint64_t map14                   : 4;
-        uint64_t map15                   : 4;
-#endif
-    } s;
-    struct cvmx_pip_dsa_vid_grp_s        cn52xx;
-    struct cvmx_pip_dsa_vid_grp_s        cn52xxp1;
-    struct cvmx_pip_dsa_vid_grp_s        cn56xx;
-} cvmx_pip_dsa_vid_grp_t;
-
-
-/**
- * cvmx_pip_frm_len_chk#
- *
- * Notes:
- * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, and PKO loopback ports.
- * PIP_FRM_LEN_CHK1 is used for PCI RAW packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_frm_len_chkx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t maxlen                  : 16;      /**< Byte count for Max-sized frame check
-                                                         Failing packets set the MAXERR interrupt and are
-                                                         optionally sent with opcode==MAXERR
-                                                         The effective MAXLEN used by HW is
-                                                         PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS */
-        uint64_t minlen                  : 16;      /**< Byte count for Min-sized frame check
-                                                         Failing packets set the MINERR interrupt and are
-                                                         optionally sent with opcode==MINERR */
-#else
-        uint64_t minlen                  : 16;
-        uint64_t maxlen                  : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pip_frm_len_chkx_s       cn50xx;
-    struct cvmx_pip_frm_len_chkx_s       cn52xx;
-    struct cvmx_pip_frm_len_chkx_s       cn52xxp1;
-    struct cvmx_pip_frm_len_chkx_s       cn56xx;
-    struct cvmx_pip_frm_len_chkx_s       cn56xxp1;
-} cvmx_pip_frm_len_chkx_t;
-
-
-/**
- * cvmx_pip_gbl_cfg
- *
- * PIP_GBL_CFG = PIP's Global Config Register
- * 
- * Global config information that applies to all ports.
- *
- * Notes:
- * * IP6_UDP
- * IPv4 allows optional UDP checksum by sending the all 0's patterns.  IPv6
- * outlaws this and the spec says to always check UDP checksum.  This mode
- * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's
- * pattern will cause a UDP checksum pass.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_gbl_cfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_19_63          : 45;
-        uint64_t tag_syn                 : 1;       /**< Do not include src_crc for TCP/SYN&!ACK packets
-                                                         0 = include src_crc
-                                                         1 = tag hash is dst_crc for TCP/SYN&!ACK packets */
-        uint64_t ip6_udp                 : 1;       /**< IPv6/UDP checksum is not optional
-                                                         0 = Allow optional checksum code
-                                                         1 = Do not allow optional checksum code */
-        uint64_t max_l2                  : 1;       /**< Config bit to choose the largest L2 frame size
-                                                         Chooses the value of the L2 Type/Length field
-                                                         to classify the frame as length.
-                                                         0 = 1500 / 0x5dc
-                                                         1 = 1535 / 0x5ff */
-        uint64_t reserved_11_15          : 5;
-        uint64_t raw_shf                 : 3;       /**< RAW Packet shift amount
-                                                         Number of bytes to pad a packet that has been
-                                                         received on a PCI RAW port. */
-        uint64_t reserved_3_7            : 5;
-        uint64_t nip_shf                 : 3;       /**< Non-IP shift amount
-                                                         Number of bytes to pad a packet that has been
-                                                         classified as not IP. */
-#else
-        uint64_t nip_shf                 : 3;
-        uint64_t reserved_3_7            : 5;
-        uint64_t raw_shf                 : 3;
-        uint64_t reserved_11_15          : 5;
-        uint64_t max_l2                  : 1;
-        uint64_t ip6_udp                 : 1;
-        uint64_t tag_syn                 : 1;
-        uint64_t reserved_19_63          : 45;
-#endif
-    } s;
-    struct cvmx_pip_gbl_cfg_s            cn30xx;
-    struct cvmx_pip_gbl_cfg_s            cn31xx;
-    struct cvmx_pip_gbl_cfg_s            cn38xx;
-    struct cvmx_pip_gbl_cfg_s            cn38xxp2;
-    struct cvmx_pip_gbl_cfg_s            cn50xx;
-    struct cvmx_pip_gbl_cfg_s            cn52xx;
-    struct cvmx_pip_gbl_cfg_s            cn52xxp1;
-    struct cvmx_pip_gbl_cfg_s            cn56xx;
-    struct cvmx_pip_gbl_cfg_s            cn56xxp1;
-    struct cvmx_pip_gbl_cfg_s            cn58xx;
-    struct cvmx_pip_gbl_cfg_s            cn58xxp1;
-} cvmx_pip_gbl_cfg_t;
-
-
-/**
- * cvmx_pip_gbl_ctl
- *
- * PIP_GBL_CTL = PIP's Global Control Register
- * 
- * Global control information.  These are the global checker enables for
- * IPv4/IPv6 and TCP/UDP parsing.  The enables effect all ports.
- *
- * Notes:
- * The following text describes the conditions in which each checker will
- * assert and flag an exception.  By disabling the checker, the exception will
- * not be flagged and the packet will be parsed as best it can.  Note, by
- * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and
- * L4_MAL could cause bits to be seen in the wrong place.  IP_CHK and L4_CHK
- * means that the packet was corrupted).
- * 
- * * IP_CHK
- *   Indicates that an IPv4 packet contained an IPv4 header checksum
- *   violations.  Only applies to packets classified as IPv4.
- * 
- * * IP_MAL
- *   Indicates that the packet was malformed.  Malformed packets are defined as
- *   packets that are not long enough to cover the IP header or not long enough
- *   to cover the length in the IP header.
- * 
- * * IP_HOP
- *   Indicates that the IPv4 TTL field or IPv6 HOP field is zero.
- * 
- * * IP4_OPTS
- *   Indicates the presence of IPv4 options.  It is set when the length != 5.
- *   This only applies to packets classified as IPv4.
- * 
- * * IP6_EEXT
- *   Indicate the presence of IPv6 early extension headers.  These bits only
- *   apply to packets classified as IPv6.  Bit 0 will flag early extensions
- *   when next_header is any one of the following...
- * 
- *         - hop-by-hop (0)
- *         - destination (60)
- *         - routing (43)
- * 
- *   Bit 1 will flag early extentions when next_header is NOT any of the
- *   following...
- * 
- *         - TCP (6)
- *         - UDP (17)
- *         - fragmentation (44)
- *         - ICMP (58)
- *         - IPSEC ESP (50)
- *         - IPSEC AH (51)
- *         - IPCOMP
- * 
- * * L4_MAL
- *   Indicates that a TCP or UDP packet is not long enough to cover the TCP or
- *   UDP header.
- * 
- * * L4_PRT
- *   Indicates that a TCP or UDP packet has an illegal port number - either the
- *   source or destination port is zero.
- * 
- * * L4_CHK
- *   Indicates that a packet classified as either TCP or UDP contains an L4
- *   checksum failure
- * 
- * * L4_LEN
- *   Indicates that the TCP or UDP length does not match the the IP length.
- * 
- * * TCP_FLAG
- *   Indicates any of the following conditions...
- * 
- *         [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag
- *         6'b000001: (FIN only)
- *         6'b000000: (0)
- *         6'bxxx1x1: (RST+FIN+*)
- *         6'b1xxx1x: (URG+SYN+*)
- *         6'bxxx11x: (RST+SYN+*)
- *         6'bxxxx11: (SYN+FIN+*)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_gbl_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t dsa_grp_tvid            : 1;       /**< DSA Group Algorithm
-                                                         Use the DSA source id to compute GRP
-                                                         (56xx pass2 only) */
-        uint64_t dsa_grp_scmd            : 1;       /**< DSA Group Algorithm
-                                                         Use the DSA source id to compute GRP when the
-                                                         DSA tag command to TO_CPU
-                                                         (56xx pass2 only) */
-        uint64_t dsa_grp_sid             : 1;       /**< DSA Group Algorithm
-                                                         Use the DSA VLAN id to compute GRP
-                                                         (56xx pass2 only) */
-        uint64_t reserved_21_23          : 3;
-        uint64_t ring_en                 : 1;       /**< Enable PCIe ring information in WQE */
-        uint64_t reserved_17_19          : 3;
-        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
-                                                         Only applies to the packet interface prts (0-31)
-                                                         (PASS2 only) */
-        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN
-                                                         (PASS2 only) */
-        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN
-                                                         (PASS2 only) */
-        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
-        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
-        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
-        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
-        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
-        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
-        uint64_t reserved_6_7            : 2;
-        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
-        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
-        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
-        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
-        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
-#else
-        uint64_t ip_chk                  : 1;
-        uint64_t ip_mal                  : 1;
-        uint64_t ip_hop                  : 1;
-        uint64_t ip4_opts                : 1;
-        uint64_t ip6_eext                : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t l4_mal                  : 1;
-        uint64_t l4_prt                  : 1;
-        uint64_t l4_chk                  : 1;
-        uint64_t l4_len                  : 1;
-        uint64_t tcp_flag                : 1;
-        uint64_t l2_mal                  : 1;
-        uint64_t vs_qos                  : 1;
-        uint64_t vs_wqe                  : 1;
-        uint64_t ignrs                   : 1;
-        uint64_t reserved_17_19          : 3;
-        uint64_t ring_en                 : 1;
-        uint64_t reserved_21_23          : 3;
-        uint64_t dsa_grp_sid             : 1;
-        uint64_t dsa_grp_scmd            : 1;
-        uint64_t dsa_grp_tvid            : 1;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } s;
-    struct cvmx_pip_gbl_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
-                                                         Only applies to the packet interface prts (0-31) */
-        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN */
-        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN */
-        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
-        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
-        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
-        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
-        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
-        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
-        uint64_t reserved_6_7            : 2;
-        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
-        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
-        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
-        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
-        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
-#else
-        uint64_t ip_chk                  : 1;
-        uint64_t ip_mal                  : 1;
-        uint64_t ip_hop                  : 1;
-        uint64_t ip4_opts                : 1;
-        uint64_t ip6_eext                : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t l4_mal                  : 1;
-        uint64_t l4_prt                  : 1;
-        uint64_t l4_chk                  : 1;
-        uint64_t l4_len                  : 1;
-        uint64_t tcp_flag                : 1;
-        uint64_t l2_mal                  : 1;
-        uint64_t vs_qos                  : 1;
-        uint64_t vs_wqe                  : 1;
-        uint64_t ignrs                   : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn30xx;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn31xx;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn38xx;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn38xxp2;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn50xx;
-    struct cvmx_pip_gbl_ctl_s            cn52xx;
-    struct cvmx_pip_gbl_ctl_s            cn52xxp1;
-    struct cvmx_pip_gbl_ctl_s            cn56xx;
-    struct cvmx_pip_gbl_ctl_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t ring_en                 : 1;       /**< Enable PCIe ring information in WQE */
-        uint64_t reserved_17_19          : 3;
-        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
-                                                         Only applies to the packet interface prts (0-31) */
-        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN */
-        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
-                                                         0=use the 1st (network order) VLAN
-                                                         1=use the 2nd (network order) VLAN */
-        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
-        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
-        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
-        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
-        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
-        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
-        uint64_t reserved_6_7            : 2;
-        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
-        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
-        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
-        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
-        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
-#else
-        uint64_t ip_chk                  : 1;
-        uint64_t ip_mal                  : 1;
-        uint64_t ip_hop                  : 1;
-        uint64_t ip4_opts                : 1;
-        uint64_t ip6_eext                : 2;
-        uint64_t reserved_6_7            : 2;
-        uint64_t l4_mal                  : 1;
-        uint64_t l4_prt                  : 1;
-        uint64_t l4_chk                  : 1;
-        uint64_t l4_len                  : 1;
-        uint64_t tcp_flag                : 1;
-        uint64_t l2_mal                  : 1;
-        uint64_t vs_qos                  : 1;
-        uint64_t vs_wqe                  : 1;
-        uint64_t ignrs                   : 1;
-        uint64_t reserved_17_19          : 3;
-        uint64_t ring_en                 : 1;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } cn56xxp1;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn58xx;
-    struct cvmx_pip_gbl_ctl_cn30xx       cn58xxp1;
-} cvmx_pip_gbl_ctl_t;
-
-
-/**
- * cvmx_pip_hg_pri_qos
- *
- * Notes:
- * This register controls accesses to the HG_QOS_TABLE.  To write an entry of
- * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level,
- * UP_QOS=1.  To read an entry of the table, write PIP_HG_PRI_QOS with
- * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read
- * PIP_HG_PRI_QOS.  The table data will be in PIP_HG_PRI_QOS[QOS].
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_hg_pri_qos_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t up_qos                  : 1;       /**< When written to '1', updates the entry in the
-                                                         HG_QOS_TABLE as specified by PRI to a value of
-                                                         QOS as follows
-                                                         HG_QOS_TABLE[PRI] = QOS */
-        uint64_t reserved_11_11          : 1;
-        uint64_t qos                     : 3;       /**< QOS Map level to priority
-                                                         (56xx pass2 only) */
-        uint64_t reserved_6_7            : 2;
-        uint64_t pri                     : 6;       /**< The priority level from HiGig header
-                                                         HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
-                                                         HiGig2       PRI = [DP[1:0], TC[3:0]]
-                                                         (56xx pass2 only) */
-#else
-        uint64_t pri                     : 6;
-        uint64_t reserved_6_7            : 2;
-        uint64_t qos                     : 3;
-        uint64_t reserved_11_11          : 1;
-        uint64_t up_qos                  : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pip_hg_pri_qos_s         cn52xx;
-    struct cvmx_pip_hg_pri_qos_s         cn52xxp1;
-    struct cvmx_pip_hg_pri_qos_s         cn56xx;
-} cvmx_pip_hg_pri_qos_t;
-
-
-/**
- * cvmx_pip_int_en
- *
- * PIP_INT_EN = PIP's Interrupt Enable Register
- * 
- * Determines if hardward should raise an interrupt to software
- * when an exception event occurs.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pip_int_en_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow
-                                                         (not used in O2P) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure
-                                                         (not used in O2P) */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
-                                                         (not used in O2P) */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn30xx;
-    struct cvmx_pip_int_en_cn30xx        cn31xx;
-    struct cvmx_pip_int_en_cn30xx        cn38xx;
-    struct cvmx_pip_int_en_cn30xx        cn38xxp2;
-    struct cvmx_pip_int_en_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn50xx;
-    struct cvmx_pip_int_en_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn52xx;
-    struct cvmx_pip_int_en_cn52xx        cn52xxp1;
-    struct cvmx_pip_int_en_s             cn56xx;
-    struct cvmx_pip_int_en_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
-                                                         (Disabled in 56xx) */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xxp1;
-    struct cvmx_pip_int_en_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t reserved_9_11           : 3;
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn58xx;
-    struct cvmx_pip_int_en_cn30xx        cn58xxp1;
-} cvmx_pip_int_en_t;
-
-
-/**
- * cvmx_pip_int_reg
- *
- * PIP_INT_REG = PIP's Interrupt Register
- * 
- * Any exception event that occurs is captured in the PIP_INT_REG.
- * PIP_INT_REG will set the exception bit regardless of the value
- * of PIP_INT_EN.  PIP_INT_EN only controls if an interrupt is
- * raised to software.
- *
- * Notes:
- * * TODOOVR
- *   The PIP Todo list stores packets that have been received and require work
- *   queue entry generation.
- * 
- * * SKPRUNT
- *   If a packet size is less then the amount programmed in the per port
- *   skippers, then there will be nothing to parse and the entire packet will
- *   basically be skipped over.  This is probably not what the user desired, so
- *   there is an indication to software.
- * 
- * * BADTAG
- *   A tag is considered bad when it is resued by a new packet before it was
- *   released by PIP.  PIP considers a tag released by one of two methods.
- *   . QOS dropped so that it is released over the pip__ipd_release bus.
- *   . WorkQ entry is validated by the pip__ipd_done signal
- * 
- * * PRTNXA
- *   If PIP receives a packet that is not in the valid port range, the port
- *   processed will be mapped into the valid port space (the mapping is
- *   currently unpredictable) and the PRTNXA bit will be set.  PRTNXA will be
- *   set for packets received under the following conditions:
- * 
- *   * packet ports (ports 0-31)
- *     - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-31
- *     - GMX_INF_MODE[TYPE]==1 (XAUI),  received port is 1-31
- *   * upper ports (pci and loopback ports 32-63)
- *     - received port is 40-47 or 52-63
- * 
- * * BCKPRS
- *   PIP can assert backpressure to the receive logic when the todo list
- *   exceeds a high-water mark.  When this
- *   occurs, PIP can raise an interrupt to software.
- * 
- * * PKTDRP
- *   PIP can drop packets based on QOS results received from IPD.  If the QOS
- *   algorithm decides to drop a packet, PIP will assert an interrupt.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_pip_int_reg_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow
-                                                         (not used in O2P) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure
-                                                         (not used in O2P) */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
-                                                         (not used in O2P) */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn30xx;
-    struct cvmx_pip_int_reg_cn30xx       cn31xx;
-    struct cvmx_pip_int_reg_cn30xx       cn38xx;
-    struct cvmx_pip_int_reg_cn30xx       cn38xxp2;
-    struct cvmx_pip_int_reg_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn50xx;
-    struct cvmx_pip_int_reg_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t reserved_1_1            : 1;
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t reserved_1_1            : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn52xx;
-    struct cvmx_pip_int_reg_cn52xx       cn52xxp1;
-    struct cvmx_pip_int_reg_s            cn56xx;
-    struct cvmx_pip_int_reg_cn56xxp1
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
-        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
-        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
-                                                         (Disabled in 56xx) */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t minerr                  : 1;
-        uint64_t maxerr                  : 1;
-        uint64_t lenerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } cn56xxp1;
-    struct cvmx_pip_int_reg_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
-                                                         stripping in IPD is enable */
-        uint64_t reserved_9_11           : 3;
-        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
-        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
-        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
-        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
-                                                         This interrupt can occur with received PARTIAL
-                                                         packets that are truncated to SKIP bytes or
-                                                         smaller. */
-        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
-        uint64_t prtnxa                  : 1;       /**< Non-existent port */
-        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
-        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
-        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
-#else
-        uint64_t pktdrp                  : 1;
-        uint64_t crcerr                  : 1;
-        uint64_t bckprs                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t badtag                  : 1;
-        uint64_t skprunt                 : 1;
-        uint64_t todoovr                 : 1;
-        uint64_t feperr                  : 1;
-        uint64_t beperr                  : 1;
-        uint64_t reserved_9_11           : 3;
-        uint64_t punyerr                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } cn58xx;
-    struct cvmx_pip_int_reg_cn30xx       cn58xxp1;
-} cvmx_pip_int_reg_t;
-
-
-/**
- * cvmx_pip_ip_offset
- *
- * PIP_IP_OFFSET = Location of the IP in the workQ entry
- * 
- * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires
- *
- * Notes:
- * In normal configurations, OFFSET must be set in the 0..4 range to allow the
- * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4
- * checksum for TCP/UDP packets.
- * 
- * The MAX value of OFFSET is determined by the the types of packets that can
- * be sent to PIP as follows...
- * 
- * Packet Type              MAX OFFSET
- * IPv4/TCP/UDP             7
- * IPv6/TCP/UDP             5
- * IPv6/without L4 parsing  6
- * 
- * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase
- * to 6.  Here are the following programming restrictions for IPv6 packets and
- * OFFSET==6:
- * 
- *  . PIP_GBL_CTL[TCP_FLAG] == 0
- *  . PIP_GBL_CTL[L4_LEN]   == 0
- *  . PIP_GBL_CTL[L4_CHK]   == 0
- *  . PIP_GBL_CTL[L4_PRT]   == 0
- *  . PIP_GBL_CTL[L4_MAL]   == 0
- *  . PIP_DEC_IPSEC[TCP]    == 0
- *  . PIP_DEC_IPSEC[UDP]    == 0
- *  . PIP_PRT_TAG[IP6_DPRT] == 0
- *  . PIP_PRT_TAG[IP6_SPRT] == 0
- *  . PIP_PRT_TAG[TCP6_TAG] == 0
- *  . PIP_GBL_CFG[TAG_SYN]  == 0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_ip_offset_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t offset                  : 3;       /**< Number of 8B ticks to include in workQ entry
-                                                          prior to IP data
-                                                         - 0:  0 Bytes / IP start at WORD4 of workQ entry
-                                                         - 1:  8 Bytes / IP start at WORD5 of workQ entry
-                                                         - 2: 16 Bytes / IP start at WORD6 of workQ entry
-                                                         - 3: 24 Bytes / IP start at WORD7 of workQ entry
-                                                         - 4: 32 Bytes / IP start at WORD8 of workQ entry
-                                                         - 5: 40 Bytes / IP start at WORD9 of workQ entry
-                                                         - 6: 48 Bytes / IP start at WORD10 of workQ entry
-                                                         - 7: 56 Bytes / IP start at WORD11 of workQ entry */
-#else
-        uint64_t offset                  : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_pip_ip_offset_s          cn30xx;
-    struct cvmx_pip_ip_offset_s          cn31xx;
-    struct cvmx_pip_ip_offset_s          cn38xx;
-    struct cvmx_pip_ip_offset_s          cn38xxp2;
-    struct cvmx_pip_ip_offset_s          cn50xx;
-    struct cvmx_pip_ip_offset_s          cn52xx;
-    struct cvmx_pip_ip_offset_s          cn52xxp1;
-    struct cvmx_pip_ip_offset_s          cn56xx;
-    struct cvmx_pip_ip_offset_s          cn56xxp1;
-    struct cvmx_pip_ip_offset_s          cn58xx;
-    struct cvmx_pip_ip_offset_s          cn58xxp1;
-} cvmx_pip_ip_offset_t;
-
-
-/**
- * cvmx_pip_prt_cfg#
- *
- * PIP_PRT_CFGX = Per port config information
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_prt_cfgx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_53_63          : 11;
-        uint64_t pad_len                 : 1;       /**< When set, disables the length check for pkts with
-                                                         padding in the client data */
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
-        uint64_t lenerr_en               : 1;       /**< L2 length error check enable
-                                                         Frame was received with length error */
-        uint64_t maxerr_en               : 1;       /**< Max frame error check enable
-                                                         Frame was received with length > max_length */
-        uint64_t minerr_en               : 1;       /**< Min frame error check enable
-                                                         Frame was received with length < min_length */
-        uint64_t grp_wat_47              : 4;       /**< GRP Watcher enable
-                                                         (Watchers 4-7) */
-        uint64_t qos_wat_47              : 4;       /**< QOS Watcher enable
-                                                         (Watchers 4-7) */
-        uint64_t reserved_37_39          : 3;
-        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
-                                                         Normally, IPD will never drop a packet that PIP
-                                                         indicates is RAW.
-                                                         0=never drop RAW packets based on RED algorithm
-                                                         1=allow RAW packet drops based on RED algorithm
-                                                         (PASS2 only) */
-        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
-                                                         calculating mask tag hash
-                                                         (PASS2 only) */
-        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
-                                                         (PASS2 only) */
-        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35)
-                                                         (PASS2 only) */
-        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
-                                                         (PASS2 only) */
-        uint64_t hg_qos                  : 1;       /**< When set, uses the HiGig priority bits as a
-                                                         lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
-                                                         to determine the QOS value
-                                                         HG_QOS must not be set when HIGIG_EN=0
-                                                         (56xx pass2 only) */
-        uint64_t qos                     : 3;       /**< Default QOS level of the port */
-        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
-        uint64_t qos_vsel                : 1;       /**< Which QOS in PIP_QOS_VLAN to use
-                                                         0 = PIP_QOS_VLAN[QOS]
-                                                         1 = PIP_QOS_VLAN[QOS1]
-                                                         (56xx pass2 only) */
-        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
-                                                         if VLAN exists, it is used
-                                                         else if IP exists, Diffserv is used
-                                                         else the per port default is used
-                                                         Watchers are still highest priority */
-        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
-        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
-        uint64_t reserved_13_15          : 3;
-        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
-        uint64_t higig_en                : 1;       /**< Enable HiGig parsing
-                                                         Should not be set for PCIe ports (ports 32-35)
-                                                         When HIGIG_EN=1:
-                                                          DSA_EN field below must be zero
-                                                          SKIP field below is both Skip I size and the
-                                                            size of the HiGig* header (12 or 16 bytes)
-                                                         (56xx pass2 only) */
-        uint64_t dsa_en                  : 1;       /**< Enable DSA tag parsing
-                                                         When DSA_EN=1:
-                                                          HIGIG_EN field above must be zero
-                                                          SKIP field below is size of DSA tag (4, 8, or
-                                                            12 bytes) rather than the size of Skip I
-                                                          total SKIP (Skip I + header + Skip II
-                                                            must be zero
-                                                          INST_HDR field above must be zero (non-PCIe
-                                                            ports)
-                                                          For PCIe ports, NPEI_PKT*_INSTR_HDR[USE_IHDR]
-                                                            and PCIE_INST_HDR[R] should be clear
-                                                          MODE field below must be "skip to L2"
-                                                         (56xx pass2 only) */
-        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
-                                                         0 = no packet inspection (Uninterpreted)
-                                                         1 = L2 parsing / skip to L2
-                                                         2 = IP parsing / skip to L3
-                                                         3 = PCI Raw (illegal for software to set) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details. */
-#else
-        uint64_t skip                    : 7;
-        uint64_t reserved_7_7            : 1;
-        cvmx_pip_port_parse_mode_t mode  : 2;
-        uint64_t dsa_en                  : 1;
-        uint64_t higig_en                : 1;
-        uint64_t crc_en                  : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t qos_vlan                : 1;
-        uint64_t qos_diff                : 1;
-        uint64_t qos_vod                 : 1;
-        uint64_t qos_vsel                : 1;
-        uint64_t qos_wat                 : 4;
-        uint64_t qos                     : 3;
-        uint64_t hg_qos                  : 1;
-        uint64_t grp_wat                 : 4;
-        uint64_t inst_hdr                : 1;
-        uint64_t dyn_rs                  : 1;
-        uint64_t tag_inc                 : 2;
-        uint64_t rawdrp                  : 1;
-        uint64_t reserved_37_39          : 3;
-        uint64_t qos_wat_47              : 4;
-        uint64_t grp_wat_47              : 4;
-        uint64_t minerr_en               : 1;
-        uint64_t maxerr_en               : 1;
-        uint64_t lenerr_en               : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t pad_len                 : 1;
-        uint64_t reserved_53_63          : 11;
-#endif
-    } s;
-    struct cvmx_pip_prt_cfgx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
-                                                         Normally, IPD will never drop a packet that PIP
-                                                         indicates is RAW.
-                                                         0=never drop RAW packets based on RED algorithm
-                                                         1=allow RAW packet drops based on RED algorithm */
-        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
-                                                         calculating mask tag hash */
-        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size */
-        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35) */
-        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable */
-        uint64_t reserved_27_27          : 1;
-        uint64_t qos                     : 3;       /**< Default QOS level of the port */
-        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
-        uint64_t reserved_18_19          : 2;
-        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
-        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
-        uint64_t reserved_10_15          : 6;
-        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
-                                                         0 = no packet inspection (Uninterpreted)
-                                                         1 = L2 parsing / skip to L2
-                                                         2 = IP parsing / skip to L3
-                                                         3 = PCI Raw (illegal for software to set) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details. */
-#else
-        uint64_t skip                    : 7;
-        uint64_t reserved_7_7            : 1;
-        cvmx_pip_port_parse_mode_t mode  : 2;
-        uint64_t reserved_10_15          : 6;
-        uint64_t qos_vlan                : 1;
-        uint64_t qos_diff                : 1;
-        uint64_t reserved_18_19          : 2;
-        uint64_t qos_wat                 : 4;
-        uint64_t qos                     : 3;
-        uint64_t reserved_27_27          : 1;
-        uint64_t grp_wat                 : 4;
-        uint64_t inst_hdr                : 1;
-        uint64_t dyn_rs                  : 1;
-        uint64_t tag_inc                 : 2;
-        uint64_t rawdrp                  : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } cn30xx;
-    struct cvmx_pip_prt_cfgx_cn30xx      cn31xx;
-    struct cvmx_pip_prt_cfgx_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
-                                                         Normally, IPD will never drop a packet that PIP
-                                                         indicates is RAW.
-                                                         0=never drop RAW packets based on RED algorithm
-                                                         1=allow RAW packet drops based on RED algorithm
-                                                         (PASS2 only) */
-        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
-                                                         calculating mask tag hash
-                                                         (PASS2 only) */
-        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
-                                                         (PASS2 only) */
-        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35)
-                                                         (PASS2 only) */
-        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
-                                                         (PASS2 only) */
-        uint64_t reserved_27_27          : 1;
-        uint64_t qos                     : 3;       /**< Default QOS level of the port */
-        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
-        uint64_t reserved_18_19          : 2;
-        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
-        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
-        uint64_t reserved_13_15          : 3;
-        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
-        uint64_t reserved_10_11          : 2;
-        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
-                                                         0 = no packet inspection (Uninterpreted)
-                                                         1 = L2 parsing / skip to L2
-                                                         2 = IP parsing / skip to L3
-                                                         3 = PCI Raw (illegal for software to set) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details. */
-#else
-        uint64_t skip                    : 7;
-        uint64_t reserved_7_7            : 1;
-        cvmx_pip_port_parse_mode_t mode  : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t crc_en                  : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t qos_vlan                : 1;
-        uint64_t qos_diff                : 1;
-        uint64_t reserved_18_19          : 2;
-        uint64_t qos_wat                 : 4;
-        uint64_t qos                     : 3;
-        uint64_t reserved_27_27          : 1;
-        uint64_t grp_wat                 : 4;
-        uint64_t inst_hdr                : 1;
-        uint64_t dyn_rs                  : 1;
-        uint64_t tag_inc                 : 2;
-        uint64_t rawdrp                  : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } cn38xx;
-    struct cvmx_pip_prt_cfgx_cn38xx      cn38xxp2;
-    struct cvmx_pip_prt_cfgx_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_53_63          : 11;
-        uint64_t pad_len                 : 1;       /**< When set, disables the length check for pkts with
-                                                         padding in the client data */
-        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
-        uint64_t lenerr_en               : 1;       /**< L2 length error check enable
-                                                         Frame was received with length error */
-        uint64_t maxerr_en               : 1;       /**< Max frame error check enable
-                                                         Frame was received with length > max_length */
-        uint64_t minerr_en               : 1;       /**< Min frame error check enable
-                                                         Frame was received with length < min_length */
-        uint64_t grp_wat_47              : 4;       /**< GRP Watcher enable
-                                                         (Watchers 4-7) */
-        uint64_t qos_wat_47              : 4;       /**< QOS Watcher enable
-                                                         (Watchers 4-7) */
-        uint64_t reserved_37_39          : 3;
-        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
-                                                         Normally, IPD will never drop a packet that PIP
-                                                         indicates is RAW.
-                                                         0=never drop RAW packets based on RED algorithm
-                                                         1=allow RAW packet drops based on RED algorithm */
-        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
-                                                         calculating mask tag hash */
-        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size */
-        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35) */
-        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable */
-        uint64_t reserved_27_27          : 1;
-        uint64_t qos                     : 3;       /**< Default QOS level of the port */
-        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable
-                                                         (Watchers 0-3) */
-        uint64_t reserved_19_19          : 1;
-        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
-                                                         if VLAN exists, it is used
-                                                         else if IP exists, Diffserv is used
-                                                         else the per port default is used
-                                                         Watchers are still highest priority */
-        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
-        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
-        uint64_t reserved_13_15          : 3;
-        uint64_t crc_en                  : 1;       /**< CRC Checking enabled
-                                                         (Disabled in 5020) */
-        uint64_t reserved_10_11          : 2;
-        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
-                                                         0 = no packet inspection (Uninterpreted)
-                                                         1 = L2 parsing / skip to L2
-                                                         2 = IP parsing / skip to L3
-                                                         3 = PCI Raw (illegal for software to set) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details. */
-#else
-        uint64_t skip                    : 7;
-        uint64_t reserved_7_7            : 1;
-        cvmx_pip_port_parse_mode_t mode  : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t crc_en                  : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t qos_vlan                : 1;
-        uint64_t qos_diff                : 1;
-        uint64_t qos_vod                 : 1;
-        uint64_t reserved_19_19          : 1;
-        uint64_t qos_wat                 : 4;
-        uint64_t qos                     : 3;
-        uint64_t reserved_27_27          : 1;
-        uint64_t grp_wat                 : 4;
-        uint64_t inst_hdr                : 1;
-        uint64_t dyn_rs                  : 1;
-        uint64_t tag_inc                 : 2;
-        uint64_t rawdrp                  : 1;
-        uint64_t reserved_37_39          : 3;
-        uint64_t qos_wat_47              : 4;
-        uint64_t grp_wat_47              : 4;
-        uint64_t minerr_en               : 1;
-        uint64_t maxerr_en               : 1;
-        uint64_t lenerr_en               : 1;
-        uint64_t vlan_len                : 1;
-        uint64_t pad_len                 : 1;
-        uint64_t reserved_53_63          : 11;
-#endif
-    } cn50xx;
-    struct cvmx_pip_prt_cfgx_s           cn52xx;
-    struct cvmx_pip_prt_cfgx_s           cn52xxp1;
-    struct cvmx_pip_prt_cfgx_s           cn56xx;
-    struct cvmx_pip_prt_cfgx_cn50xx      cn56xxp1;
-    struct cvmx_pip_prt_cfgx_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
-                                                         Normally, IPD will never drop a packet that PIP
-                                                         indicates is RAW.
-                                                         0=never drop RAW packets based on RED algorithm
-                                                         1=allow RAW packet drops based on RED algorithm
-                                                         (PASS2 only) */
-        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
-                                                         calculating mask tag hash
-                                                         (PASS2 only) */
-        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
-                                                         (PASS2 only) */
-        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
-                                                         (not for PCI prts, 32-35)
-                                                         (PASS2 only) */
-        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
-                                                         (PASS2 only) */
-        uint64_t reserved_27_27          : 1;
-        uint64_t qos                     : 3;       /**< Default QOS level of the port */
-        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
-        uint64_t reserved_19_19          : 1;
-        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
-                                                         if VLAN exists, it is used
-                                                         else if IP exists, Diffserv is used
-                                                         else the per port default is used
-                                                         Watchers are still highest priority */
-        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
-        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
-        uint64_t reserved_13_15          : 3;
-        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
-        uint64_t reserved_10_11          : 2;
-        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
-                                                         0 = no packet inspection (Uninterpreted)
-                                                         1 = L2 parsing / skip to L2
-                                                         2 = IP parsing / skip to L3
-                                                         3 = PCI Raw (illegal for software to set) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
-                                                         apply to packets on PCI ports when a PKT_INST_HDR
-                                                         is present.  See section 7.2.7 - Legal Skip
-                                                         Values for further details. */
-#else
-        uint64_t skip                    : 7;
-        uint64_t reserved_7_7            : 1;
-        cvmx_pip_port_parse_mode_t mode  : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t crc_en                  : 1;
-        uint64_t reserved_13_15          : 3;
-        uint64_t qos_vlan                : 1;
-        uint64_t qos_diff                : 1;
-        uint64_t qos_vod                 : 1;
-        uint64_t reserved_19_19          : 1;
-        uint64_t qos_wat                 : 4;
-        uint64_t qos                     : 3;
-        uint64_t reserved_27_27          : 1;
-        uint64_t grp_wat                 : 4;
-        uint64_t inst_hdr                : 1;
-        uint64_t dyn_rs                  : 1;
-        uint64_t tag_inc                 : 2;
-        uint64_t rawdrp                  : 1;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } cn58xx;
-    struct cvmx_pip_prt_cfgx_cn58xx      cn58xxp1;
-} cvmx_pip_prt_cfgx_t;
-
-
-/**
- * cvmx_pip_prt_tag#
- *
- * PIP_PRT_TAGX = Per port config information
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_prt_tagx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t grptagbase              : 4;       /**< Offset to use when computing group from tag bits
-                                                         when GRPTAG is set.
-                                                         (PASS2 only) */
-        uint64_t grptagmask              : 4;       /**< Which bits of the tag to exclude when computing
-                                                         group when GRPTAG is set.
-                                                         (PASS2 only) */
-        uint64_t grptag                  : 1;       /**< When set, use the lower bit of the tag to compute
-                                                         the group in the work queue entry
-                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE
-                                                         (PASS2 only) */
-        uint64_t grptag_mskip            : 1;       /**< When set, GRPTAG will be used regardless if the
-                                                         packet IS_IP. */
-        uint64_t tag_mode                : 2;       /**< Which tag algorithm to use
-                                                         0 = always use tuple tag algorithm
-                                                         1 = always use mask tag algorithm
-                                                         2 = if packet is IP, use tuple else use mask
-                                                         3 = tuple XOR mask
-                                                         (PASS2 only) */
-        uint64_t inc_vs                  : 2;       /**< determines the VLAN ID (VID) to be included in
-                                                         tuple tag when VLAN stacking is detected
-                                                         0 = do not include VID in tuple tag generation
-                                                         1 = include VID (VLAN0) in hash
-                                                         2 = include VID (VLAN1) in hash
-                                                         3 = include VID ([VLAN0,VLAN1]) in hash
-                                                         (PASS2 only) */
-        uint64_t inc_vlan                : 1;       /**< when set, the VLAN ID is included in tuple tag
-                                                         when VLAN stacking is not detected
-                                                         0 = do not include VID in tuple tag generation
-                                                         1 = include VID in hash
-                                                         (PASS2 only) */
-        uint64_t inc_prt_flag            : 1;       /**< sets whether the port is included in tuple tag */
-        uint64_t ip6_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
-                                                         included in tuple tag for IPv6 packets */
-        uint64_t ip4_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
-                                                         included in tuple tag for IPv4 */
-        uint64_t ip6_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
-                                                         included in tuple tag for IPv6 packets */
-        uint64_t ip4_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
-                                                         included in tuple tag for IPv4 */
-        uint64_t ip6_nxth_flag           : 1;       /**< sets whether ipv6 includes next header in tuple
-                                                         tag hash */
-        uint64_t ip4_pctl_flag           : 1;       /**< sets whether ipv4 includes protocol in tuple
-                                                         tag hash */
-        uint64_t ip6_dst_flag            : 1;       /**< sets whether ipv6 includes dst address in tuple
-                                                         tag hash */
-        uint64_t ip4_dst_flag            : 1;       /**< sets whether ipv4 includes dst address in tuple
-                                                         tag hash */
-        uint64_t ip6_src_flag            : 1;       /**< sets whether ipv6 includes src address in tuple
-                                                         tag hash */
-        uint64_t ip4_src_flag            : 1;       /**< sets whether ipv4 includes src address in tuple
-                                                         tag hash */
-        cvmx_pow_tag_type_t tcp6_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv6)
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t tcp4_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv4)
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t ip6_tag_type : 2;       /**< sets whether IPv6 packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t ip4_tag_type : 2;       /**< sets whether IPv4 packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t non_tag_type : 2;       /**< sets whether non-IP packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        uint64_t grp                     : 4;       /**< 4-bit value indicating the group to schedule to */
-#else
-        uint64_t grp                     : 4;
-        cvmx_pow_tag_type_t non_tag_type : 2;
-        cvmx_pow_tag_type_t ip4_tag_type : 2;
-        cvmx_pow_tag_type_t ip6_tag_type : 2;
-        cvmx_pow_tag_type_t tcp4_tag_type : 2;
-        cvmx_pow_tag_type_t tcp6_tag_type : 2;
-        uint64_t ip4_src_flag            : 1;
-        uint64_t ip6_src_flag            : 1;
-        uint64_t ip4_dst_flag            : 1;
-        uint64_t ip6_dst_flag            : 1;
-        uint64_t ip4_pctl_flag           : 1;
-        uint64_t ip6_nxth_flag           : 1;
-        uint64_t ip4_sprt_flag           : 1;
-        uint64_t ip6_sprt_flag           : 1;
-        uint64_t ip4_dprt_flag           : 1;
-        uint64_t ip6_dprt_flag           : 1;
-        uint64_t inc_prt_flag            : 1;
-        uint64_t inc_vlan                : 1;
-        uint64_t inc_vs                  : 2;
-        uint64_t tag_mode                : 2;
-        uint64_t grptag_mskip            : 1;
-        uint64_t grptag                  : 1;
-        uint64_t grptagmask              : 4;
-        uint64_t grptagbase              : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_pip_prt_tagx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t grptagbase              : 4;       /**< Offset to use when computing group from tag bits
-                                                         when GRPTAG is set. */
-        uint64_t grptagmask              : 4;       /**< Which bits of the tag to exclude when computing
-                                                         group when GRPTAG is set. */
-        uint64_t grptag                  : 1;       /**< When set, use the lower bit of the tag to compute
-                                                         the group in the work queue entry
-                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
-        uint64_t reserved_30_30          : 1;
-        uint64_t tag_mode                : 2;       /**< Which tag algorithm to use
-                                                         0 = always use tuple tag algorithm
-                                                         1 = always use mask tag algorithm
-                                                         2 = if packet is IP, use tuple else use mask
-                                                         3 = tuple XOR mask */
-        uint64_t inc_vs                  : 2;       /**< determines the VLAN ID (VID) to be included in
-                                                         tuple tag when VLAN stacking is detected
-                                                         0 = do not include VID in tuple tag generation
-                                                         1 = include VID (VLAN0) in hash
-                                                         2 = include VID (VLAN1) in hash
-                                                         3 = include VID ([VLAN0,VLAN1]) in hash */
-        uint64_t inc_vlan                : 1;       /**< when set, the VLAN ID is included in tuple tag
-                                                         when VLAN stacking is not detected
-                                                         0 = do not include VID in tuple tag generation
-                                                         1 = include VID in hash */
-        uint64_t inc_prt_flag            : 1;       /**< sets whether the port is included in tuple tag */
-        uint64_t ip6_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
-                                                         included in tuple tag for IPv6 packets */
-        uint64_t ip4_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
-                                                         included in tuple tag for IPv4 */
-        uint64_t ip6_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
-                                                         included in tuple tag for IPv6 packets */
-        uint64_t ip4_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
-                                                         included in tuple tag for IPv4 */
-        uint64_t ip6_nxth_flag           : 1;       /**< sets whether ipv6 includes next header in tuple
-                                                         tag hash */
-        uint64_t ip4_pctl_flag           : 1;       /**< sets whether ipv4 includes protocol in tuple
-                                                         tag hash */
-        uint64_t ip6_dst_flag            : 1;       /**< sets whether ipv6 includes dst address in tuple
-                                                         tag hash */
-        uint64_t ip4_dst_flag            : 1;       /**< sets whether ipv4 includes dst address in tuple
-                                                         tag hash */
-        uint64_t ip6_src_flag            : 1;       /**< sets whether ipv6 includes src address in tuple
-                                                         tag hash */
-        uint64_t ip4_src_flag            : 1;       /**< sets whether ipv4 includes src address in tuple
-                                                         tag hash */
-        cvmx_pow_tag_type_t tcp6_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv6)
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t tcp4_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv4)
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t ip6_tag_type : 2;       /**< sets whether IPv6 packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t ip4_tag_type : 2;       /**< sets whether IPv4 packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        cvmx_pow_tag_type_t non_tag_type : 2;       /**< sets whether non-IP packet tag type
-                                                         0 = ordered tags
-                                                         1 = atomic tags
-                                                         2 = Null tags */
-        uint64_t grp                     : 4;       /**< 4-bit value indicating the group to schedule to */
-#else
-        uint64_t grp                     : 4;
-        cvmx_pow_tag_type_t non_tag_type : 2;
-        cvmx_pow_tag_type_t ip4_tag_type : 2;
-        cvmx_pow_tag_type_t ip6_tag_type : 2;
-        cvmx_pow_tag_type_t tcp4_tag_type : 2;
-        cvmx_pow_tag_type_t tcp6_tag_type : 2;
-        uint64_t ip4_src_flag            : 1;
-        uint64_t ip6_src_flag            : 1;
-        uint64_t ip4_dst_flag            : 1;
-        uint64_t ip6_dst_flag            : 1;
-        uint64_t ip4_pctl_flag           : 1;
-        uint64_t ip6_nxth_flag           : 1;
-        uint64_t ip4_sprt_flag           : 1;
-        uint64_t ip6_sprt_flag           : 1;
-        uint64_t ip4_dprt_flag           : 1;
-        uint64_t ip6_dprt_flag           : 1;
-        uint64_t inc_prt_flag            : 1;
-        uint64_t inc_vlan                : 1;
-        uint64_t inc_vs                  : 2;
-        uint64_t tag_mode                : 2;
-        uint64_t reserved_30_30          : 1;
-        uint64_t grptag                  : 1;
-        uint64_t grptagmask              : 4;
-        uint64_t grptagbase              : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } cn30xx;
-    struct cvmx_pip_prt_tagx_cn30xx      cn31xx;
-    struct cvmx_pip_prt_tagx_cn30xx      cn38xx;
-    struct cvmx_pip_prt_tagx_cn30xx      cn38xxp2;
-    struct cvmx_pip_prt_tagx_s           cn50xx;
-    struct cvmx_pip_prt_tagx_s           cn52xx;
-    struct cvmx_pip_prt_tagx_s           cn52xxp1;
-    struct cvmx_pip_prt_tagx_s           cn56xx;
-    struct cvmx_pip_prt_tagx_s           cn56xxp1;
-    struct cvmx_pip_prt_tagx_s           cn58xx;
-    struct cvmx_pip_prt_tagx_s           cn58xxp1;
-} cvmx_pip_prt_tagx_t;
-
-
-/**
- * cvmx_pip_qos_diff#
- *
- * PIP_QOS_DIFFX = QOS Diffserv Tables
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_qos_diffx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t qos                     : 3;       /**< Diffserv QOS level */
-#else
-        uint64_t qos                     : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_pip_qos_diffx_s          cn30xx;
-    struct cvmx_pip_qos_diffx_s          cn31xx;
-    struct cvmx_pip_qos_diffx_s          cn38xx;
-    struct cvmx_pip_qos_diffx_s          cn38xxp2;
-    struct cvmx_pip_qos_diffx_s          cn50xx;
-    struct cvmx_pip_qos_diffx_s          cn52xx;
-    struct cvmx_pip_qos_diffx_s          cn52xxp1;
-    struct cvmx_pip_qos_diffx_s          cn56xx;
-    struct cvmx_pip_qos_diffx_s          cn56xxp1;
-    struct cvmx_pip_qos_diffx_s          cn58xx;
-    struct cvmx_pip_qos_diffx_s          cn58xxp1;
-} cvmx_pip_qos_diffx_t;
-
-
-/**
- * cvmx_pip_qos_vlan#
- *
- * PIP_QOS_VLANX = QOS VLAN Tables
- * 
- * If the PIP indentifies a packet to be DSA/VLAN tagged, then the QOS
- * can be set based on the DSA/VLAN user priority.  These eight register
- * comprise the QOS values for all DSA/VLAN user priority values.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_qos_vlanx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t qos1                    : 3;       /**< DSA/VLAN QOS level
-                                                         Selected when PIP_PRT_CFGx[QOS_VSEL] = 1
-                                                         (56xx pass2 only) */
-        uint64_t reserved_3_3            : 1;
-        uint64_t qos                     : 3;       /**< VLAN QOS level */
-#else
-        uint64_t qos                     : 3;
-        uint64_t reserved_3_3            : 1;
-        uint64_t qos1                    : 3;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_pip_qos_vlanx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t qos                     : 3;       /**< VLAN QOS level */
-#else
-        uint64_t qos                     : 3;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn31xx;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn38xx;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn38xxp2;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn50xx;
-    struct cvmx_pip_qos_vlanx_s          cn52xx;
-    struct cvmx_pip_qos_vlanx_s          cn52xxp1;
-    struct cvmx_pip_qos_vlanx_s          cn56xx;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn56xxp1;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn58xx;
-    struct cvmx_pip_qos_vlanx_cn30xx     cn58xxp1;
-} cvmx_pip_qos_vlanx_t;
-
-
-/**
- * cvmx_pip_qos_watch#
- *
- * PIP_QOS_WATCHX = QOS Watcher Tables
- * 
- * Sets up the Configuration CSRs for the four QOS Watchers.
- * Each Watcher can be set to look for a specific protocol,
- * TCP/UDP destination port, or Ethertype to override the
- * default QOS value.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_qos_watchx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t mask                    : 16;      /**< Mask off a range of values (PASS2 only) */
-        uint64_t reserved_28_31          : 4;
-        uint64_t grp                     : 4;       /**< The GRP number of the watcher (PASS2 only) */
-        uint64_t reserved_23_23          : 1;
-        uint64_t qos                     : 3;       /**< The QOS level of the watcher */
-        uint64_t reserved_19_19          : 1;
-        cvmx_pip_qos_watch_types match_type : 3;    /**< The field for the watcher match against
-                                                         0 = disable across all ports
-                                                         1 = protocol (ipv4)
-                                                           = next_header (ipv6)
-                                                         2 = TCP destination port
-                                                         3 = UDP destination port */
-        uint64_t match_value             : 16;      /**< The value to watch for */
-#else
-        uint64_t match_value             : 16;
-        cvmx_pip_qos_watch_types match_type : 3;
-        uint64_t reserved_19_19          : 1;
-        uint64_t qos                     : 3;
-        uint64_t reserved_23_23          : 1;
-        uint64_t grp                     : 4;
-        uint64_t reserved_28_31          : 4;
-        uint64_t mask                    : 16;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_pip_qos_watchx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t mask                    : 16;      /**< Mask off a range of values */
-        uint64_t reserved_28_31          : 4;
-        uint64_t grp                     : 4;       /**< The GRP number of the watcher */
-        uint64_t reserved_23_23          : 1;
-        uint64_t qos                     : 3;       /**< The QOS level of the watcher */
-        uint64_t reserved_18_19          : 2;
-        cvmx_pip_qos_watch_types match_type : 2;    /**< The field for the watcher match against
-                                                         0 = disable across all ports
-                                                         1 = protocol (ipv4)
-                                                           = next_header (ipv6)
-                                                         2 = TCP destination port
-                                                         3 = UDP destination port */
-        uint64_t match_value             : 16;      /**< The value to watch for */
-#else
-        uint64_t match_value             : 16;
-        cvmx_pip_qos_watch_types match_type : 2;
-        uint64_t reserved_18_19          : 2;
-        uint64_t qos                     : 3;
-        uint64_t reserved_23_23          : 1;
-        uint64_t grp                     : 4;
-        uint64_t reserved_28_31          : 4;
-        uint64_t mask                    : 16;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } cn30xx;
-    struct cvmx_pip_qos_watchx_cn30xx    cn31xx;
-    struct cvmx_pip_qos_watchx_cn30xx    cn38xx;
-    struct cvmx_pip_qos_watchx_cn30xx    cn38xxp2;
-    struct cvmx_pip_qos_watchx_s         cn50xx;
-    struct cvmx_pip_qos_watchx_s         cn52xx;
-    struct cvmx_pip_qos_watchx_s         cn52xxp1;
-    struct cvmx_pip_qos_watchx_s         cn56xx;
-    struct cvmx_pip_qos_watchx_s         cn56xxp1;
-    struct cvmx_pip_qos_watchx_cn30xx    cn58xx;
-    struct cvmx_pip_qos_watchx_cn30xx    cn58xxp1;
-} cvmx_pip_qos_watchx_t;
-
-
-/**
- * cvmx_pip_raw_word
- *
- * PIP_RAW_WORD = The RAW Word2 of the workQ entry.
- * 
- * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_raw_word_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_56_63          : 8;
-        uint64_t word                    : 56;      /**< Word2 of the workQ entry
-                                                         The 8-bit bufs field is still set by HW (IPD) */
-#else
-        uint64_t word                    : 56;
-        uint64_t reserved_56_63          : 8;
-#endif
-    } s;
-    struct cvmx_pip_raw_word_s           cn30xx;
-    struct cvmx_pip_raw_word_s           cn31xx;
-    struct cvmx_pip_raw_word_s           cn38xx;
-    struct cvmx_pip_raw_word_s           cn38xxp2;
-    struct cvmx_pip_raw_word_s           cn50xx;
-    struct cvmx_pip_raw_word_s           cn52xx;
-    struct cvmx_pip_raw_word_s           cn52xxp1;
-    struct cvmx_pip_raw_word_s           cn56xx;
-    struct cvmx_pip_raw_word_s           cn56xxp1;
-    struct cvmx_pip_raw_word_s           cn58xx;
-    struct cvmx_pip_raw_word_s           cn58xxp1;
-} cvmx_pip_raw_word_t;
-
-
-/**
- * cvmx_pip_sft_rst
- *
- * PIP_SFT_RST = PIP Soft Reset
- * 
- * When written to a '1', resets the pip block
- *
- * Notes:
- * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles
- * in duration).  Although this will reset much of PIP's internal state, some
- * CSRs will not reset.
- * 
- * . PIP_BIST_STATUS
- * . PIP_STAT0_PRT*
- * . PIP_STAT1_PRT*
- * . PIP_STAT2_PRT*
- * . PIP_STAT3_PRT*
- * . PIP_STAT4_PRT*
- * . PIP_STAT5_PRT*
- * . PIP_STAT6_PRT*
- * . PIP_STAT7_PRT*
- * . PIP_STAT8_PRT*
- * . PIP_STAT9_PRT*
- * . PIP_STAT_INB_PKTS*
- * . PIP_STAT_INB_OCTS*
- * . PIP_STAT_INB_ERRS*
- * . PIP_TAG_INC*
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_sft_rst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rst                     : 1;       /**< Soft Reset */
-#else
-        uint64_t rst                     : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_pip_sft_rst_s            cn30xx;
-    struct cvmx_pip_sft_rst_s            cn31xx;
-    struct cvmx_pip_sft_rst_s            cn38xx;
-    struct cvmx_pip_sft_rst_s            cn50xx;
-    struct cvmx_pip_sft_rst_s            cn52xx;
-    struct cvmx_pip_sft_rst_s            cn52xxp1;
-    struct cvmx_pip_sft_rst_s            cn56xx;
-    struct cvmx_pip_sft_rst_s            cn56xxp1;
-    struct cvmx_pip_sft_rst_s            cn58xx;
-    struct cvmx_pip_sft_rst_s            cn58xxp1;
-} cvmx_pip_sft_rst_t;
-
-
-/**
- * cvmx_pip_stat0_prt#
- *
- * PIP Statistics Counters
- * 
- * Note: special stat counter behavior
- * 
- * 1) Read and write operations must arbitrate for the statistics resources
- *     along with the packet engines which are incrementing the counters.
- *     In order to not drop packet information, the packet HW is always a
- *     higher priority and the CSR requests will only be satisified when
- *     there are idle cycles.  This can potentially cause long delays if the
- *     system becomes full.
- * 
- * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is
- *     set, then all read accesses will clear the register.  In addition,
- *     any write to a stats register will also reset the register to zero.
- *     Please note that the clearing operations must obey rule \#1 above.
- * 
- * 3) all counters are wrapping - software must ensure they are read periodically
- * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat0_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t drp_pkts                : 32;      /**< Inbound packets marked to be dropped by the IPD
-                                                         QOS widget per port */
-        uint64_t drp_octs                : 32;      /**< Inbound octets marked to be dropped by the IPD
-                                                         QOS widget per port */
-#else
-        uint64_t drp_octs                : 32;
-        uint64_t drp_pkts                : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat0_prtx_s         cn30xx;
-    struct cvmx_pip_stat0_prtx_s         cn31xx;
-    struct cvmx_pip_stat0_prtx_s         cn38xx;
-    struct cvmx_pip_stat0_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat0_prtx_s         cn50xx;
-    struct cvmx_pip_stat0_prtx_s         cn52xx;
-    struct cvmx_pip_stat0_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat0_prtx_s         cn56xx;
-    struct cvmx_pip_stat0_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat0_prtx_s         cn58xx;
-    struct cvmx_pip_stat0_prtx_s         cn58xxp1;
-} cvmx_pip_stat0_prtx_t;
-
-
-/**
- * cvmx_pip_stat1_prt#
- *
- * PIP_STAT1_PRTX = PIP_STAT_OCTS
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat1_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t octs                    : 48;      /**< Number of octets received by PIP (good and bad) */
-#else
-        uint64_t octs                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_pip_stat1_prtx_s         cn30xx;
-    struct cvmx_pip_stat1_prtx_s         cn31xx;
-    struct cvmx_pip_stat1_prtx_s         cn38xx;
-    struct cvmx_pip_stat1_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat1_prtx_s         cn50xx;
-    struct cvmx_pip_stat1_prtx_s         cn52xx;
-    struct cvmx_pip_stat1_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat1_prtx_s         cn56xx;
-    struct cvmx_pip_stat1_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat1_prtx_s         cn58xx;
-    struct cvmx_pip_stat1_prtx_s         cn58xxp1;
-} cvmx_pip_stat1_prtx_t;
-
-
-/**
- * cvmx_pip_stat2_prt#
- *
- * PIP_STAT2_PRTX = PIP_STAT_PKTS     / PIP_STAT_RAW
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat2_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t pkts                    : 32;      /**< Number of packets processed by PIP */
-        uint64_t raw                     : 32;      /**< RAWFULL + RAWSCH Packets without an L1/L2 error
-                                                         received by PIP per port */
-#else
-        uint64_t raw                     : 32;
-        uint64_t pkts                    : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat2_prtx_s         cn30xx;
-    struct cvmx_pip_stat2_prtx_s         cn31xx;
-    struct cvmx_pip_stat2_prtx_s         cn38xx;
-    struct cvmx_pip_stat2_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat2_prtx_s         cn50xx;
-    struct cvmx_pip_stat2_prtx_s         cn52xx;
-    struct cvmx_pip_stat2_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat2_prtx_s         cn56xx;
-    struct cvmx_pip_stat2_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat2_prtx_s         cn58xx;
-    struct cvmx_pip_stat2_prtx_s         cn58xxp1;
-} cvmx_pip_stat2_prtx_t;
-
-
-/**
- * cvmx_pip_stat3_prt#
- *
- * PIP_STAT3_PRTX = PIP_STAT_BCST     / PIP_STAT_MCST
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat3_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bcst                    : 32;      /**< Number of indentified L2 broadcast packets
-                                                         Does not include multicast packets
-                                                         Only includes packets whose parse mode is
-                                                         SKIP_TO_L2. */
-        uint64_t mcst                    : 32;      /**< Number of indentified L2 multicast packets
-                                                         Does not include broadcast packets
-                                                         Only includes packets whose parse mode is
-                                                         SKIP_TO_L2. */
-#else
-        uint64_t mcst                    : 32;
-        uint64_t bcst                    : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat3_prtx_s         cn30xx;
-    struct cvmx_pip_stat3_prtx_s         cn31xx;
-    struct cvmx_pip_stat3_prtx_s         cn38xx;
-    struct cvmx_pip_stat3_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat3_prtx_s         cn50xx;
-    struct cvmx_pip_stat3_prtx_s         cn52xx;
-    struct cvmx_pip_stat3_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat3_prtx_s         cn56xx;
-    struct cvmx_pip_stat3_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat3_prtx_s         cn58xx;
-    struct cvmx_pip_stat3_prtx_s         cn58xxp1;
-} cvmx_pip_stat3_prtx_t;
-
-
-/**
- * cvmx_pip_stat4_prt#
- *
- * PIP_STAT4_PRTX = PIP_STAT_HIST1    / PIP_STAT_HIST0
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat4_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t h65to127                : 32;      /**< Number of 65-127B packets */
-        uint64_t h64                     : 32;      /**< Number of 1-64B packets */
-#else
-        uint64_t h64                     : 32;
-        uint64_t h65to127                : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat4_prtx_s         cn30xx;
-    struct cvmx_pip_stat4_prtx_s         cn31xx;
-    struct cvmx_pip_stat4_prtx_s         cn38xx;
-    struct cvmx_pip_stat4_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat4_prtx_s         cn50xx;
-    struct cvmx_pip_stat4_prtx_s         cn52xx;
-    struct cvmx_pip_stat4_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat4_prtx_s         cn56xx;
-    struct cvmx_pip_stat4_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat4_prtx_s         cn58xx;
-    struct cvmx_pip_stat4_prtx_s         cn58xxp1;
-} cvmx_pip_stat4_prtx_t;
-
-
-/**
- * cvmx_pip_stat5_prt#
- *
- * PIP_STAT5_PRTX = PIP_STAT_HIST3    / PIP_STAT_HIST2
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat5_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t h256to511               : 32;      /**< Number of 256-511B packets */
-        uint64_t h128to255               : 32;      /**< Number of 128-255B packets */
-#else
-        uint64_t h128to255               : 32;
-        uint64_t h256to511               : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat5_prtx_s         cn30xx;
-    struct cvmx_pip_stat5_prtx_s         cn31xx;
-    struct cvmx_pip_stat5_prtx_s         cn38xx;
-    struct cvmx_pip_stat5_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat5_prtx_s         cn50xx;
-    struct cvmx_pip_stat5_prtx_s         cn52xx;
-    struct cvmx_pip_stat5_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat5_prtx_s         cn56xx;
-    struct cvmx_pip_stat5_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat5_prtx_s         cn58xx;
-    struct cvmx_pip_stat5_prtx_s         cn58xxp1;
-} cvmx_pip_stat5_prtx_t;
-
-
-/**
- * cvmx_pip_stat6_prt#
- *
- * PIP_STAT6_PRTX = PIP_STAT_HIST5    / PIP_STAT_HIST4
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat6_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t h1024to1518             : 32;      /**< Number of 1024-1518B packets */
-        uint64_t h512to1023              : 32;      /**< Number of 512-1023B packets */
-#else
-        uint64_t h512to1023              : 32;
-        uint64_t h1024to1518             : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat6_prtx_s         cn30xx;
-    struct cvmx_pip_stat6_prtx_s         cn31xx;
-    struct cvmx_pip_stat6_prtx_s         cn38xx;
-    struct cvmx_pip_stat6_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat6_prtx_s         cn50xx;
-    struct cvmx_pip_stat6_prtx_s         cn52xx;
-    struct cvmx_pip_stat6_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat6_prtx_s         cn56xx;
-    struct cvmx_pip_stat6_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat6_prtx_s         cn58xx;
-    struct cvmx_pip_stat6_prtx_s         cn58xxp1;
-} cvmx_pip_stat6_prtx_t;
-
-
-/**
- * cvmx_pip_stat7_prt#
- *
- * PIP_STAT7_PRTX = PIP_STAT_FCS      / PIP_STAT_HIST6
- *
- *
- * Notes:
- * FCS is not checked on the PCI ports 32..35.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat7_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fcs                     : 32;      /**< Number of packets with FCS or Align opcode errors */
-        uint64_t h1519                   : 32;      /**< Number of 1519-max packets */
-#else
-        uint64_t h1519                   : 32;
-        uint64_t fcs                     : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat7_prtx_s         cn30xx;
-    struct cvmx_pip_stat7_prtx_s         cn31xx;
-    struct cvmx_pip_stat7_prtx_s         cn38xx;
-    struct cvmx_pip_stat7_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat7_prtx_s         cn50xx;
-    struct cvmx_pip_stat7_prtx_s         cn52xx;
-    struct cvmx_pip_stat7_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat7_prtx_s         cn56xx;
-    struct cvmx_pip_stat7_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat7_prtx_s         cn58xx;
-    struct cvmx_pip_stat7_prtx_s         cn58xxp1;
-} cvmx_pip_stat7_prtx_t;
-
-
-/**
- * cvmx_pip_stat8_prt#
- *
- * PIP_STAT8_PRTX = PIP_STAT_FRAG     / PIP_STAT_UNDER
- *
- *
- * Notes:
- * FCS is not checked on the PCI ports 32..35.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat8_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t frag                    : 32;      /**< Number of packets with length < min and FCS error */
-        uint64_t undersz                 : 32;      /**< Number of packets with length < min */
-#else
-        uint64_t undersz                 : 32;
-        uint64_t frag                    : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat8_prtx_s         cn30xx;
-    struct cvmx_pip_stat8_prtx_s         cn31xx;
-    struct cvmx_pip_stat8_prtx_s         cn38xx;
-    struct cvmx_pip_stat8_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat8_prtx_s         cn50xx;
-    struct cvmx_pip_stat8_prtx_s         cn52xx;
-    struct cvmx_pip_stat8_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat8_prtx_s         cn56xx;
-    struct cvmx_pip_stat8_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat8_prtx_s         cn58xx;
-    struct cvmx_pip_stat8_prtx_s         cn58xxp1;
-} cvmx_pip_stat8_prtx_t;
-
-
-/**
- * cvmx_pip_stat9_prt#
- *
- * PIP_STAT9_PRTX = PIP_STAT_JABBER   / PIP_STAT_OVER
- *
- *
- * Notes:
- * FCS is not checked on the PCI ports 32..35.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat9_prtx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t jabber                  : 32;      /**< Number of packets with length > max and FCS error */
-        uint64_t oversz                  : 32;      /**< Number of packets with length > max */
-#else
-        uint64_t oversz                  : 32;
-        uint64_t jabber                  : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat9_prtx_s         cn30xx;
-    struct cvmx_pip_stat9_prtx_s         cn31xx;
-    struct cvmx_pip_stat9_prtx_s         cn38xx;
-    struct cvmx_pip_stat9_prtx_s         cn38xxp2;
-    struct cvmx_pip_stat9_prtx_s         cn50xx;
-    struct cvmx_pip_stat9_prtx_s         cn52xx;
-    struct cvmx_pip_stat9_prtx_s         cn52xxp1;
-    struct cvmx_pip_stat9_prtx_s         cn56xx;
-    struct cvmx_pip_stat9_prtx_s         cn56xxp1;
-    struct cvmx_pip_stat9_prtx_s         cn58xx;
-    struct cvmx_pip_stat9_prtx_s         cn58xxp1;
-} cvmx_pip_stat9_prtx_t;
-
-
-/**
- * cvmx_pip_stat_ctl
- *
- * PIP_STAT_CTL = PIP's Stat Control Register
- * 
- * Controls how the PIP statistics counters are handled.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t rdclr                   : 1;       /**< Stat registers are read and clear
-                                                         0 = stat registers hold value when read
-                                                         1 = stat registers are cleared when read */
-#else
-        uint64_t rdclr                   : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_pip_stat_ctl_s           cn30xx;
-    struct cvmx_pip_stat_ctl_s           cn31xx;
-    struct cvmx_pip_stat_ctl_s           cn38xx;
-    struct cvmx_pip_stat_ctl_s           cn38xxp2;
-    struct cvmx_pip_stat_ctl_s           cn50xx;
-    struct cvmx_pip_stat_ctl_s           cn52xx;
-    struct cvmx_pip_stat_ctl_s           cn52xxp1;
-    struct cvmx_pip_stat_ctl_s           cn56xx;
-    struct cvmx_pip_stat_ctl_s           cn56xxp1;
-    struct cvmx_pip_stat_ctl_s           cn58xx;
-    struct cvmx_pip_stat_ctl_s           cn58xxp1;
-} cvmx_pip_stat_ctl_t;
-
-
-/**
- * cvmx_pip_stat_inb_errs#
- *
- * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port
- * 
- * Inbound stats collect all data sent to PIP from all packet interfaces.
- * Its the raw counts of everything that comes into the block.  The counts
- * will reflect all error packets and packets dropped by the PKI RED engine.
- * These counts are intended for system debug, but could convey useful
- * information in production systems.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat_inb_errsx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t errs                    : 16;      /**< Number of packets with GMX/SPX/PCI errors
-                                                         received by PIP */
-#else
-        uint64_t errs                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pip_stat_inb_errsx_s     cn30xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn31xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn38xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn38xxp2;
-    struct cvmx_pip_stat_inb_errsx_s     cn50xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn52xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn52xxp1;
-    struct cvmx_pip_stat_inb_errsx_s     cn56xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn56xxp1;
-    struct cvmx_pip_stat_inb_errsx_s     cn58xx;
-    struct cvmx_pip_stat_inb_errsx_s     cn58xxp1;
-} cvmx_pip_stat_inb_errsx_t;
-
-
-/**
- * cvmx_pip_stat_inb_octs#
- *
- * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port
- * 
- * Inbound stats collect all data sent to PIP from all packet interfaces.
- * Its the raw counts of everything that comes into the block.  The counts
- * will reflect all error packets and packets dropped by the PKI RED engine.
- * These counts are intended for system debug, but could convey useful
- * information in production systems.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat_inb_octsx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t octs                    : 48;      /**< Total number of octets from all packets received
-                                                         by PIP */
-#else
-        uint64_t octs                    : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_pip_stat_inb_octsx_s     cn30xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn31xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn38xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn38xxp2;
-    struct cvmx_pip_stat_inb_octsx_s     cn50xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn52xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn52xxp1;
-    struct cvmx_pip_stat_inb_octsx_s     cn56xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn56xxp1;
-    struct cvmx_pip_stat_inb_octsx_s     cn58xx;
-    struct cvmx_pip_stat_inb_octsx_s     cn58xxp1;
-} cvmx_pip_stat_inb_octsx_t;
-
-
-/**
- * cvmx_pip_stat_inb_pkts#
- *
- * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port
- * 
- * Inbound stats collect all data sent to PIP from all packet interfaces.
- * Its the raw counts of everything that comes into the block.  The counts
- * will reflect all error packets and packets dropped by the PKI RED engine.
- * These counts are intended for system debug, but could convey useful
- * information in production systems.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_stat_inb_pktsx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pkts                    : 32;      /**< Number of packets without GMX/SPX/PCI errors
-                                                         received by PIP */
-#else
-        uint64_t pkts                    : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pip_stat_inb_pktsx_s     cn30xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn31xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn38xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn38xxp2;
-    struct cvmx_pip_stat_inb_pktsx_s     cn50xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn52xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn52xxp1;
-    struct cvmx_pip_stat_inb_pktsx_s     cn56xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn56xxp1;
-    struct cvmx_pip_stat_inb_pktsx_s     cn58xx;
-    struct cvmx_pip_stat_inb_pktsx_s     cn58xxp1;
-} cvmx_pip_stat_inb_pktsx_t;
-
-
-/**
- * cvmx_pip_tag_inc#
- *
- * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm
- * 
- * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_tag_incx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t en                      : 8;       /**< Which bytes to include in mask tag algorithm
-                                                         Broken into 4, 16-entry masks to cover 128B
-                                                         PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use
-                                                         registers  0-15 map to PIP_PRT_CFG[TAG_INC] == 0
-                                                         registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1
-                                                         registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2
-                                                         registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3
-                                                         [7] coresponds to the MSB of the 8B word
-                                                         [0] coresponds to the LSB of the 8B word
-                                                         (PASS2 only) */
-#else
-        uint64_t en                      : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pip_tag_incx_s           cn30xx;
-    struct cvmx_pip_tag_incx_s           cn31xx;
-    struct cvmx_pip_tag_incx_s           cn38xx;
-    struct cvmx_pip_tag_incx_s           cn38xxp2;
-    struct cvmx_pip_tag_incx_s           cn50xx;
-    struct cvmx_pip_tag_incx_s           cn52xx;
-    struct cvmx_pip_tag_incx_s           cn52xxp1;
-    struct cvmx_pip_tag_incx_s           cn56xx;
-    struct cvmx_pip_tag_incx_s           cn56xxp1;
-    struct cvmx_pip_tag_incx_s           cn58xx;
-    struct cvmx_pip_tag_incx_s           cn58xxp1;
-} cvmx_pip_tag_incx_t;
-
-
-/**
- * cvmx_pip_tag_mask
- *
- * PIP_TAG_MASK = Mask bit in the tag generation
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_tag_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mask                    : 16;      /**< When set, MASK clears individual bits of lower 16
-                                                         bits of the computed tag.  Does not effect RAW
-                                                         or INSTR HDR packets. */
-#else
-        uint64_t mask                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pip_tag_mask_s           cn30xx;
-    struct cvmx_pip_tag_mask_s           cn31xx;
-    struct cvmx_pip_tag_mask_s           cn38xx;
-    struct cvmx_pip_tag_mask_s           cn38xxp2;
-    struct cvmx_pip_tag_mask_s           cn50xx;
-    struct cvmx_pip_tag_mask_s           cn52xx;
-    struct cvmx_pip_tag_mask_s           cn52xxp1;
-    struct cvmx_pip_tag_mask_s           cn56xx;
-    struct cvmx_pip_tag_mask_s           cn56xxp1;
-    struct cvmx_pip_tag_mask_s           cn58xx;
-    struct cvmx_pip_tag_mask_s           cn58xxp1;
-} cvmx_pip_tag_mask_t;
-
-
-/**
- * cvmx_pip_tag_secret
- *
- * PIP_TAG_SECRET = Initial value in tag generation
- * 
- * The source and destination IV's provide a mechanism for each Octeon to be unique.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_tag_secret_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t dst                     : 16;      /**< Secret for the destination tuple tag CRC calc */
-        uint64_t src                     : 16;      /**< Secret for the source tuple tag CRC calc */
-#else
-        uint64_t src                     : 16;
-        uint64_t dst                     : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pip_tag_secret_s         cn30xx;
-    struct cvmx_pip_tag_secret_s         cn31xx;
-    struct cvmx_pip_tag_secret_s         cn38xx;
-    struct cvmx_pip_tag_secret_s         cn38xxp2;
-    struct cvmx_pip_tag_secret_s         cn50xx;
-    struct cvmx_pip_tag_secret_s         cn52xx;
-    struct cvmx_pip_tag_secret_s         cn52xxp1;
-    struct cvmx_pip_tag_secret_s         cn56xx;
-    struct cvmx_pip_tag_secret_s         cn56xxp1;
-    struct cvmx_pip_tag_secret_s         cn58xx;
-    struct cvmx_pip_tag_secret_s         cn58xxp1;
-} cvmx_pip_tag_secret_t;
-
-
-/**
- * cvmx_pip_todo_entry
- *
- * PIP_TODO_ENTRY = Head entry of the Todo list (debug only)
- * 
- * Summary of the current packet that has completed and waiting to be processed
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pip_todo_entry_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t val                     : 1;       /**< Entry is valid */
-        uint64_t reserved_62_62          : 1;
-        uint64_t entry                   : 62;      /**< Todo list entry summary */
-#else
-        uint64_t entry                   : 62;
-        uint64_t reserved_62_62          : 1;
-        uint64_t val                     : 1;
-#endif
-    } s;
-    struct cvmx_pip_todo_entry_s         cn30xx;
-    struct cvmx_pip_todo_entry_s         cn31xx;
-    struct cvmx_pip_todo_entry_s         cn38xx;
-    struct cvmx_pip_todo_entry_s         cn38xxp2;
-    struct cvmx_pip_todo_entry_s         cn50xx;
-    struct cvmx_pip_todo_entry_s         cn52xx;
-    struct cvmx_pip_todo_entry_s         cn52xxp1;
-    struct cvmx_pip_todo_entry_s         cn56xx;
-    struct cvmx_pip_todo_entry_s         cn56xxp1;
-    struct cvmx_pip_todo_entry_s         cn58xx;
-    struct cvmx_pip_todo_entry_s         cn58xxp1;
-} cvmx_pip_todo_entry_t;
-
-
-/**
- * cvmx_pko_mem_count0
- *
- * Notes:
- * Total number of packets seen by PKO, per port
- * A write to this address will clear the entry whose index is specified as COUNT[5:0].
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_count0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t count                   : 32;      /**< Total number of packets seen by PKO */
-#else
-        uint64_t count                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pko_mem_count0_s         cn30xx;
-    struct cvmx_pko_mem_count0_s         cn31xx;
-    struct cvmx_pko_mem_count0_s         cn38xx;
-    struct cvmx_pko_mem_count0_s         cn38xxp2;
-    struct cvmx_pko_mem_count0_s         cn50xx;
-    struct cvmx_pko_mem_count0_s         cn52xx;
-    struct cvmx_pko_mem_count0_s         cn52xxp1;
-    struct cvmx_pko_mem_count0_s         cn56xx;
-    struct cvmx_pko_mem_count0_s         cn56xxp1;
-    struct cvmx_pko_mem_count0_s         cn58xx;
-    struct cvmx_pko_mem_count0_s         cn58xxp1;
-} cvmx_pko_mem_count0_t;
-
-
-/**
- * cvmx_pko_mem_count1
- *
- * Notes:
- * Total number of bytes seen by PKO, per port
- * A write to this address will clear the entry whose index is specified as COUNT[5:0].
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_count1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t count                   : 48;      /**< Total number of bytes seen by PKO */
-#else
-        uint64_t count                   : 48;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_pko_mem_count1_s         cn30xx;
-    struct cvmx_pko_mem_count1_s         cn31xx;
-    struct cvmx_pko_mem_count1_s         cn38xx;
-    struct cvmx_pko_mem_count1_s         cn38xxp2;
-    struct cvmx_pko_mem_count1_s         cn50xx;
-    struct cvmx_pko_mem_count1_s         cn52xx;
-    struct cvmx_pko_mem_count1_s         cn52xxp1;
-    struct cvmx_pko_mem_count1_s         cn56xx;
-    struct cvmx_pko_mem_count1_s         cn56xxp1;
-    struct cvmx_pko_mem_count1_s         cn58xx;
-    struct cvmx_pko_mem_count1_s         cn58xxp1;
-} cvmx_pko_mem_count1_t;
-
-
-/**
- * cvmx_pko_mem_debug0
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fau                     : 28;      /**< Fetch and add command words */
-        uint64_t cmd                     : 14;      /**< Command word */
-        uint64_t segs                    : 6;       /**< Number of segments/gather size */
-        uint64_t size                    : 16;      /**< Packet length in bytes */
-#else
-        uint64_t size                    : 16;
-        uint64_t segs                    : 6;
-        uint64_t cmd                     : 14;
-        uint64_t fau                     : 28;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug0_s         cn30xx;
-    struct cvmx_pko_mem_debug0_s         cn31xx;
-    struct cvmx_pko_mem_debug0_s         cn38xx;
-    struct cvmx_pko_mem_debug0_s         cn38xxp2;
-    struct cvmx_pko_mem_debug0_s         cn50xx;
-    struct cvmx_pko_mem_debug0_s         cn52xx;
-    struct cvmx_pko_mem_debug0_s         cn52xxp1;
-    struct cvmx_pko_mem_debug0_s         cn56xx;
-    struct cvmx_pko_mem_debug0_s         cn56xxp1;
-    struct cvmx_pko_mem_debug0_s         cn58xx;
-    struct cvmx_pko_mem_debug0_s         cn58xxp1;
-} cvmx_pko_mem_debug0_t;
-
-
-/**
- * cvmx_pko_mem_debug1
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t ptr                     : 40;      /**< Data pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug1_s         cn30xx;
-    struct cvmx_pko_mem_debug1_s         cn31xx;
-    struct cvmx_pko_mem_debug1_s         cn38xx;
-    struct cvmx_pko_mem_debug1_s         cn38xxp2;
-    struct cvmx_pko_mem_debug1_s         cn50xx;
-    struct cvmx_pko_mem_debug1_s         cn52xx;
-    struct cvmx_pko_mem_debug1_s         cn52xxp1;
-    struct cvmx_pko_mem_debug1_s         cn56xx;
-    struct cvmx_pko_mem_debug1_s         cn56xxp1;
-    struct cvmx_pko_mem_debug1_s         cn58xx;
-    struct cvmx_pko_mem_debug1_s         cn58xxp1;
-} cvmx_pko_mem_debug1_t;
-
-
-/**
- * cvmx_pko_mem_debug10
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug10_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug10_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fau                     : 28;      /**< Fetch and add command words */
-        uint64_t cmd                     : 14;      /**< Command word */
-        uint64_t segs                    : 6;       /**< Number of segments/gather size */
-        uint64_t size                    : 16;      /**< Packet length in bytes */
-#else
-        uint64_t size                    : 16;
-        uint64_t segs                    : 6;
-        uint64_t cmd                     : 14;
-        uint64_t fau                     : 28;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug10_cn30xx   cn31xx;
-    struct cvmx_pko_mem_debug10_cn30xx   cn38xx;
-    struct cvmx_pko_mem_debug10_cn30xx   cn38xxp2;
-    struct cvmx_pko_mem_debug10_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t ptrs1                   : 17;      /**< Internal state */
-        uint64_t reserved_17_31          : 15;
-        uint64_t ptrs2                   : 17;      /**< Internal state */
-#else
-        uint64_t ptrs2                   : 17;
-        uint64_t reserved_17_31          : 15;
-        uint64_t ptrs1                   : 17;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug10_cn50xx   cn52xx;
-    struct cvmx_pko_mem_debug10_cn50xx   cn52xxp1;
-    struct cvmx_pko_mem_debug10_cn50xx   cn56xx;
-    struct cvmx_pko_mem_debug10_cn50xx   cn56xxp1;
-    struct cvmx_pko_mem_debug10_cn50xx   cn58xx;
-    struct cvmx_pko_mem_debug10_cn50xx   cn58xxp1;
-} cvmx_pko_mem_debug10_t;
-
-
-/**
- * cvmx_pko_mem_debug11
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.out.sta.state[22:0]
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug11_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t reserved_0_39           : 40;
-#else
-        uint64_t reserved_0_39           : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug11_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t ptr                     : 40;      /**< Data pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug11_cn30xx   cn31xx;
-    struct cvmx_pko_mem_debug11_cn30xx   cn38xx;
-    struct cvmx_pko_mem_debug11_cn30xx   cn38xxp2;
-    struct cvmx_pko_mem_debug11_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t maj                     : 1;       /**< Internal state */
-        uint64_t uid                     : 3;       /**< Internal state */
-        uint64_t sop                     : 1;       /**< Internal state */
-        uint64_t len                     : 1;       /**< Internal state */
-        uint64_t chk                     : 1;       /**< Internal state */
-        uint64_t cnt                     : 13;      /**< Internal state */
-        uint64_t mod                     : 3;       /**< Internal state */
-#else
-        uint64_t mod                     : 3;
-        uint64_t cnt                     : 13;
-        uint64_t chk                     : 1;
-        uint64_t len                     : 1;
-        uint64_t sop                     : 1;
-        uint64_t uid                     : 3;
-        uint64_t maj                     : 1;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug11_cn50xx   cn52xx;
-    struct cvmx_pko_mem_debug11_cn50xx   cn52xxp1;
-    struct cvmx_pko_mem_debug11_cn50xx   cn56xx;
-    struct cvmx_pko_mem_debug11_cn50xx   cn56xxp1;
-    struct cvmx_pko_mem_debug11_cn50xx   cn58xx;
-    struct cvmx_pko_mem_debug11_cn50xx   cn58xxp1;
-} cvmx_pko_mem_debug11_t;
-
-
-/**
- * cvmx_pko_mem_debug12
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0]
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug12_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug12_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
-#else
-        uint64_t data                    : 64;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug12_cn30xx   cn31xx;
-    struct cvmx_pko_mem_debug12_cn30xx   cn38xx;
-    struct cvmx_pko_mem_debug12_cn30xx   cn38xxp2;
-    struct cvmx_pko_mem_debug12_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t fau                     : 28;      /**< Fetch and add command words */
-        uint64_t cmd                     : 14;      /**< Command word */
-        uint64_t segs                    : 6;       /**< Number of segments/gather size */
-        uint64_t size                    : 16;      /**< Packet length in bytes */
-#else
-        uint64_t size                    : 16;
-        uint64_t segs                    : 6;
-        uint64_t cmd                     : 14;
-        uint64_t fau                     : 28;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug12_cn50xx   cn52xx;
-    struct cvmx_pko_mem_debug12_cn50xx   cn52xxp1;
-    struct cvmx_pko_mem_debug12_cn50xx   cn56xx;
-    struct cvmx_pko_mem_debug12_cn50xx   cn56xxp1;
-    struct cvmx_pko_mem_debug12_cn50xx   cn58xx;
-    struct cvmx_pko_mem_debug12_cn50xx   cn58xxp1;
-} cvmx_pko_mem_debug12_t;
-
-
-/**
- * cvmx_pko_mem_debug13
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0]
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug13_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t reserved_0_55           : 56;
-#else
-        uint64_t reserved_0_55           : 56;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug13_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_51_63          : 13;
-        uint64_t widx                    : 17;      /**< PDB widx */
-        uint64_t ridx2                   : 17;      /**< PDB ridx2 */
-        uint64_t widx2                   : 17;      /**< PDB widx2 */
-#else
-        uint64_t widx2                   : 17;
-        uint64_t ridx2                   : 17;
-        uint64_t widx                    : 17;
-        uint64_t reserved_51_63          : 13;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug13_cn30xx   cn31xx;
-    struct cvmx_pko_mem_debug13_cn30xx   cn38xx;
-    struct cvmx_pko_mem_debug13_cn30xx   cn38xxp2;
-    struct cvmx_pko_mem_debug13_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t ptr                     : 40;      /**< Data pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug13_cn50xx   cn52xx;
-    struct cvmx_pko_mem_debug13_cn50xx   cn52xxp1;
-    struct cvmx_pko_mem_debug13_cn50xx   cn56xx;
-    struct cvmx_pko_mem_debug13_cn50xx   cn56xxp1;
-    struct cvmx_pko_mem_debug13_cn50xx   cn58xx;
-    struct cvmx_pko_mem_debug13_cn50xx   cn58xxp1;
-} cvmx_pko_mem_debug13_t;
-
-
-/**
- * cvmx_pko_mem_debug14
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
- * This CSR is a memory of 120 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug14_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug14_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t ridx                    : 17;      /**< PDB ridx */
-#else
-        uint64_t ridx                    : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug14_cn30xx   cn31xx;
-    struct cvmx_pko_mem_debug14_cn30xx   cn38xx;
-    struct cvmx_pko_mem_debug14_cn30xx   cn38xxp2;
-    struct cvmx_pko_mem_debug14_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Command words */
-#else
-        uint64_t data                    : 64;
-#endif
-    } cn52xx;
-    struct cvmx_pko_mem_debug14_cn52xx   cn52xxp1;
-    struct cvmx_pko_mem_debug14_cn52xx   cn56xx;
-    struct cvmx_pko_mem_debug14_cn52xx   cn56xxp1;
-} cvmx_pko_mem_debug14_t;
-
-
-/**
- * cvmx_pko_mem_debug2
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t ptr                     : 40;      /**< Data pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug2_s         cn30xx;
-    struct cvmx_pko_mem_debug2_s         cn31xx;
-    struct cvmx_pko_mem_debug2_s         cn38xx;
-    struct cvmx_pko_mem_debug2_s         cn38xxp2;
-    struct cvmx_pko_mem_debug2_s         cn50xx;
-    struct cvmx_pko_mem_debug2_s         cn52xx;
-    struct cvmx_pko_mem_debug2_s         cn52xxp1;
-    struct cvmx_pko_mem_debug2_s         cn56xx;
-    struct cvmx_pko_mem_debug2_s         cn56xxp1;
-    struct cvmx_pko_mem_debug2_s         cn58xx;
-    struct cvmx_pko_mem_debug2_s         cn58xxp1;
-} cvmx_pko_mem_debug2_t;
-
-
-/**
- * cvmx_pko_mem_debug3
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug3_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t i                       : 1;       /**< "I"  value used for free operation */
-        uint64_t back                    : 4;       /**< Back value used for free operation */
-        uint64_t pool                    : 3;       /**< Pool value used for free operation */
-        uint64_t size                    : 16;      /**< Size in bytes */
-        uint64_t ptr                     : 40;      /**< Data pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t pool                    : 3;
-        uint64_t back                    : 4;
-        uint64_t i                       : 1;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug3_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug3_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug3_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug3_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
-#else
-        uint64_t data                    : 64;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug3_cn50xx    cn52xx;
-    struct cvmx_pko_mem_debug3_cn50xx    cn52xxp1;
-    struct cvmx_pko_mem_debug3_cn50xx    cn56xx;
-    struct cvmx_pko_mem_debug3_cn50xx    cn56xxp1;
-    struct cvmx_pko_mem_debug3_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug3_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug3_t;
-
-
-/**
- * cvmx_pko_mem_debug4
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug4_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
-#else
-        uint64_t data                    : 64;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug4_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug4_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug4_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug4_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cmnd_segs               : 3;       /**< Internal state */
-        uint64_t cmnd_siz                : 16;      /**< Internal state */
-        uint64_t cmnd_off                : 6;       /**< Internal state */
-        uint64_t uid                     : 3;       /**< Internal state */
-        uint64_t dread_sop               : 1;       /**< Internal state */
-        uint64_t init_dwrite             : 1;       /**< Internal state */
-        uint64_t chk_once                : 1;       /**< Internal state */
-        uint64_t chk_mode                : 1;       /**< Internal state */
-        uint64_t active                  : 1;       /**< Internal state */
-        uint64_t static_p                : 1;       /**< Internal state */
-        uint64_t qos                     : 3;       /**< Internal state */
-        uint64_t qcb_ridx                : 5;       /**< Internal state */
-        uint64_t qid_off_max             : 4;       /**< Internal state */
-        uint64_t qid_off                 : 4;       /**< Internal state */
-        uint64_t qid_base                : 8;       /**< Internal state */
-        uint64_t wait                    : 1;       /**< Internal state */
-        uint64_t minor                   : 2;       /**< Internal state */
-        uint64_t major                   : 3;       /**< Internal state */
-#else
-        uint64_t major                   : 3;
-        uint64_t minor                   : 2;
-        uint64_t wait                    : 1;
-        uint64_t qid_base                : 8;
-        uint64_t qid_off                 : 4;
-        uint64_t qid_off_max             : 4;
-        uint64_t qcb_ridx                : 5;
-        uint64_t qos                     : 3;
-        uint64_t static_p                : 1;
-        uint64_t active                  : 1;
-        uint64_t chk_mode                : 1;
-        uint64_t chk_once                : 1;
-        uint64_t init_dwrite             : 1;
-        uint64_t dread_sop               : 1;
-        uint64_t uid                     : 3;
-        uint64_t cmnd_off                : 6;
-        uint64_t cmnd_siz                : 16;
-        uint64_t cmnd_segs               : 3;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug4_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t curr_siz                : 8;       /**< Internal state */
-        uint64_t curr_off                : 16;      /**< Internal state */
-        uint64_t cmnd_segs               : 6;       /**< Internal state */
-        uint64_t cmnd_siz                : 16;      /**< Internal state */
-        uint64_t cmnd_off                : 6;       /**< Internal state */
-        uint64_t uid                     : 2;       /**< Internal state */
-        uint64_t dread_sop               : 1;       /**< Internal state */
-        uint64_t init_dwrite             : 1;       /**< Internal state */
-        uint64_t chk_once                : 1;       /**< Internal state */
-        uint64_t chk_mode                : 1;       /**< Internal state */
-        uint64_t wait                    : 1;       /**< Internal state */
-        uint64_t minor                   : 2;       /**< Internal state */
-        uint64_t major                   : 3;       /**< Internal state */
-#else
-        uint64_t major                   : 3;
-        uint64_t minor                   : 2;
-        uint64_t wait                    : 1;
-        uint64_t chk_mode                : 1;
-        uint64_t chk_once                : 1;
-        uint64_t init_dwrite             : 1;
-        uint64_t dread_sop               : 1;
-        uint64_t uid                     : 2;
-        uint64_t cmnd_off                : 6;
-        uint64_t cmnd_siz                : 16;
-        uint64_t cmnd_segs               : 6;
-        uint64_t curr_off                : 16;
-        uint64_t curr_siz                : 8;
-#endif
-    } cn52xx;
-    struct cvmx_pko_mem_debug4_cn52xx    cn52xxp1;
-    struct cvmx_pko_mem_debug4_cn52xx    cn56xx;
-    struct cvmx_pko_mem_debug4_cn52xx    cn56xxp1;
-    struct cvmx_pko_mem_debug4_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug4_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug4_t;
-
-
-/**
- * cvmx_pko_mem_debug5
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
- * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug5_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dwri_mod                : 1;       /**< Dwrite mod */
-        uint64_t dwri_sop                : 1;       /**< Dwrite sop needed */
-        uint64_t dwri_len                : 1;       /**< Dwrite len */
-        uint64_t dwri_cnt                : 13;      /**< Dwrite count */
-        uint64_t cmnd_siz                : 16;      /**< Copy of cmnd.size */
-        uint64_t uid                     : 1;       /**< UID */
-        uint64_t xfer_wor                : 1;       /**< Transfer work needed */
-        uint64_t xfer_dwr                : 1;       /**< Transfer dwrite needed */
-        uint64_t cbuf_fre                : 1;       /**< Cbuf needs free */
-        uint64_t reserved_27_27          : 1;
-        uint64_t chk_mode                : 1;       /**< Checksum mode */
-        uint64_t active                  : 1;       /**< Port is active */
-        uint64_t qos                     : 3;       /**< Current QOS round */
-        uint64_t qcb_ridx                : 5;       /**< Buffer read  index for QCB */
-        uint64_t qid_off                 : 3;       /**< Offset to be added to QID_BASE for current queue */
-        uint64_t qid_base                : 7;       /**< Absolute QID of the queue array base = &QUEUES[0] */
-        uint64_t wait                    : 1;       /**< State wait when set */
-        uint64_t minor                   : 2;       /**< State minor code */
-        uint64_t major                   : 4;       /**< State major code */
-#else
-        uint64_t major                   : 4;
-        uint64_t minor                   : 2;
-        uint64_t wait                    : 1;
-        uint64_t qid_base                : 7;
-        uint64_t qid_off                 : 3;
-        uint64_t qcb_ridx                : 5;
-        uint64_t qos                     : 3;
-        uint64_t active                  : 1;
-        uint64_t chk_mode                : 1;
-        uint64_t reserved_27_27          : 1;
-        uint64_t cbuf_fre                : 1;
-        uint64_t xfer_dwr                : 1;
-        uint64_t xfer_wor                : 1;
-        uint64_t uid                     : 1;
-        uint64_t cmnd_siz                : 16;
-        uint64_t dwri_cnt                : 13;
-        uint64_t dwri_len                : 1;
-        uint64_t dwri_sop                : 1;
-        uint64_t dwri_mod                : 1;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug5_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug5_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug5_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug5_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t curr_ptr                : 29;      /**< Internal state */
-        uint64_t curr_siz                : 16;      /**< Internal state */
-        uint64_t curr_off                : 16;      /**< Internal state */
-        uint64_t cmnd_segs               : 3;       /**< Internal state */
-#else
-        uint64_t cmnd_segs               : 3;
-        uint64_t curr_off                : 16;
-        uint64_t curr_siz                : 16;
-        uint64_t curr_ptr                : 29;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug5_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_54_63          : 10;
-        uint64_t nxt_inflt               : 6;       /**< Internal state */
-        uint64_t curr_ptr                : 40;      /**< Internal state */
-        uint64_t curr_siz                : 8;       /**< Internal state */
-#else
-        uint64_t curr_siz                : 8;
-        uint64_t curr_ptr                : 40;
-        uint64_t nxt_inflt               : 6;
-        uint64_t reserved_54_63          : 10;
-#endif
-    } cn52xx;
-    struct cvmx_pko_mem_debug5_cn52xx    cn52xxp1;
-    struct cvmx_pko_mem_debug5_cn52xx    cn56xx;
-    struct cvmx_pko_mem_debug5_cn52xx    cn56xxp1;
-    struct cvmx_pko_mem_debug5_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug5_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug5_t;
-
-
-/**
- * cvmx_pko_mem_debug6
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t qid_offres              : 4;       /**< Internal state */
-        uint64_t qid_offths              : 4;       /**< Internal state */
-        uint64_t preempter               : 1;       /**< Internal state */
-        uint64_t preemptee               : 1;       /**< Internal state */
-        uint64_t preempted               : 1;       /**< Internal state */
-        uint64_t active                  : 1;       /**< Internal state */
-        uint64_t statc                   : 1;       /**< Internal state */
-        uint64_t qos                     : 3;       /**< Internal state */
-        uint64_t qcb_ridx                : 5;       /**< Internal state */
-        uint64_t qid_offmax              : 4;       /**< Internal state */
-        uint64_t reserved_0_11           : 12;
-#else
-        uint64_t reserved_0_11           : 12;
-        uint64_t qid_offmax              : 4;
-        uint64_t qcb_ridx                : 5;
-        uint64_t qos                     : 3;
-        uint64_t statc                   : 1;
-        uint64_t active                  : 1;
-        uint64_t preempted               : 1;
-        uint64_t preemptee               : 1;
-        uint64_t preempter               : 1;
-        uint64_t qid_offths              : 4;
-        uint64_t qid_offres              : 4;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug6_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t qid_offm                : 3;       /**< Qid offset max */
-        uint64_t static_p                : 1;       /**< Static port when set */
-        uint64_t work_min                : 3;       /**< Work minor */
-        uint64_t dwri_chk                : 1;       /**< Dwrite checksum mode */
-        uint64_t dwri_uid                : 1;       /**< Dwrite UID */
-        uint64_t dwri_mod                : 2;       /**< Dwrite mod */
-#else
-        uint64_t dwri_mod                : 2;
-        uint64_t dwri_uid                : 1;
-        uint64_t dwri_chk                : 1;
-        uint64_t work_min                : 3;
-        uint64_t static_p                : 1;
-        uint64_t qid_offm                : 3;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug6_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug6_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug6_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug6_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t curr_ptr                : 11;      /**< Internal state */
-#else
-        uint64_t curr_ptr                : 11;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug6_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_37_63          : 27;
-        uint64_t qid_offres              : 4;       /**< Internal state */
-        uint64_t qid_offths              : 4;       /**< Internal state */
-        uint64_t preempter               : 1;       /**< Internal state */
-        uint64_t preemptee               : 1;       /**< Internal state */
-        uint64_t preempted               : 1;       /**< Internal state */
-        uint64_t active                  : 1;       /**< Internal state */
-        uint64_t statc                   : 1;       /**< Internal state */
-        uint64_t qos                     : 3;       /**< Internal state */
-        uint64_t qcb_ridx                : 5;       /**< Internal state */
-        uint64_t qid_offmax              : 4;       /**< Internal state */
-        uint64_t qid_off                 : 4;       /**< Internal state */
-        uint64_t qid_base                : 8;       /**< Internal state */
-#else
-        uint64_t qid_base                : 8;
-        uint64_t qid_off                 : 4;
-        uint64_t qid_offmax              : 4;
-        uint64_t qcb_ridx                : 5;
-        uint64_t qos                     : 3;
-        uint64_t statc                   : 1;
-        uint64_t active                  : 1;
-        uint64_t preempted               : 1;
-        uint64_t preemptee               : 1;
-        uint64_t preempter               : 1;
-        uint64_t qid_offths              : 4;
-        uint64_t qid_offres              : 4;
-        uint64_t reserved_37_63          : 27;
-#endif
-    } cn52xx;
-    struct cvmx_pko_mem_debug6_cn52xx    cn52xxp1;
-    struct cvmx_pko_mem_debug6_cn52xx    cn56xx;
-    struct cvmx_pko_mem_debug6_cn52xx    cn56xxp1;
-    struct cvmx_pko_mem_debug6_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug6_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug6_t;
-
-
-/**
- * cvmx_pko_mem_debug7
- *
- * Notes:
- * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
- * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
-        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
-        uint64_t reserved_0_57           : 58;
-#else
-        uint64_t reserved_0_57           : 58;
-        uint64_t tail                    : 1;
-        uint64_t qos                     : 5;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug7_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_58_63          : 6;
-        uint64_t dwb                     : 9;       /**< Calculated DWB count used for free operation */
-        uint64_t start                   : 33;      /**< Calculated start address used for free operation */
-        uint64_t size                    : 16;      /**< Packet length in bytes */
-#else
-        uint64_t size                    : 16;
-        uint64_t start                   : 33;
-        uint64_t dwb                     : 9;
-        uint64_t reserved_58_63          : 6;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug7_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug7_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug7_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug7_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
-        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
-        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
-        uint64_t buf_ptr                 : 33;      /**< Command word pointer */
-        uint64_t qcb_widx                : 6;       /**< Buffer write index for QCB */
-        uint64_t qcb_ridx                : 6;       /**< Buffer read  index for QCB */
-#else
-        uint64_t qcb_ridx                : 6;
-        uint64_t qcb_widx                : 6;
-        uint64_t buf_ptr                 : 33;
-        uint64_t buf_siz                 : 13;
-        uint64_t tail                    : 1;
-        uint64_t qos                     : 5;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug7_cn50xx    cn52xx;
-    struct cvmx_pko_mem_debug7_cn50xx    cn52xxp1;
-    struct cvmx_pko_mem_debug7_cn50xx    cn56xx;
-    struct cvmx_pko_mem_debug7_cn50xx    cn56xxp1;
-    struct cvmx_pko_mem_debug7_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug7_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug7_t;
-
-
-/**
- * cvmx_pko_mem_debug8
- *
- * Notes:
- * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
- * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug8_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_59_63          : 5;
-        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
-        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
-        uint64_t reserved_0_44           : 45;
-#else
-        uint64_t reserved_0_44           : 45;
-        uint64_t buf_siz                 : 13;
-        uint64_t tail                    : 1;
-        uint64_t reserved_59_63          : 5;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug8_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
-        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
-        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
-        uint64_t buf_ptr                 : 33;      /**< Command word pointer */
-        uint64_t qcb_widx                : 6;       /**< Buffer write index for QCB */
-        uint64_t qcb_ridx                : 6;       /**< Buffer read  index for QCB */
-#else
-        uint64_t qcb_ridx                : 6;
-        uint64_t qcb_widx                : 6;
-        uint64_t buf_ptr                 : 33;
-        uint64_t buf_siz                 : 13;
-        uint64_t tail                    : 1;
-        uint64_t qos                     : 5;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug8_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug8_cn30xx    cn38xx;
-    struct cvmx_pko_mem_debug8_cn30xx    cn38xxp2;
-    struct cvmx_pko_mem_debug8_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t doorbell                : 20;      /**< Doorbell count */
-        uint64_t reserved_6_7            : 2;
-        uint64_t static_p                : 1;       /**< Static priority */
-        uint64_t s_tail                  : 1;       /**< Static tail */
-        uint64_t static_q                : 1;       /**< Static priority */
-        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
-#else
-        uint64_t qos                     : 3;
-        uint64_t static_q                : 1;
-        uint64_t s_tail                  : 1;
-        uint64_t static_p                : 1;
-        uint64_t reserved_6_7            : 2;
-        uint64_t doorbell                : 20;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug8_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t preempter               : 1;       /**< Preempter */
-        uint64_t doorbell                : 20;      /**< Doorbell count */
-        uint64_t reserved_7_7            : 1;
-        uint64_t preemptee               : 1;       /**< Preemptee */
-        uint64_t static_p                : 1;       /**< Static priority */
-        uint64_t s_tail                  : 1;       /**< Static tail */
-        uint64_t static_q                : 1;       /**< Static priority */
-        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
-#else
-        uint64_t qos                     : 3;
-        uint64_t static_q                : 1;
-        uint64_t s_tail                  : 1;
-        uint64_t static_p                : 1;
-        uint64_t preemptee               : 1;
-        uint64_t reserved_7_7            : 1;
-        uint64_t doorbell                : 20;
-        uint64_t preempter               : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn52xx;
-    struct cvmx_pko_mem_debug8_cn52xx    cn52xxp1;
-    struct cvmx_pko_mem_debug8_cn52xx    cn56xx;
-    struct cvmx_pko_mem_debug8_cn52xx    cn56xxp1;
-    struct cvmx_pko_mem_debug8_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug8_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug8_t;
-
-
-/**
- * cvmx_pko_mem_debug9
- *
- * Notes:
- * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_debug9_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t ptrs0                   : 17;      /**< Internal state */
-        uint64_t reserved_0_31           : 32;
-#else
-        uint64_t reserved_0_31           : 32;
-        uint64_t ptrs0                   : 17;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } s;
-    struct cvmx_pko_mem_debug9_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t doorbell                : 20;      /**< Doorbell count */
-        uint64_t reserved_5_7            : 3;
-        uint64_t s_tail                  : 1;       /**< reads as zero (S_TAIL cannot be read) */
-        uint64_t static_q                : 1;       /**< reads as zero (STATIC_Q cannot be read) */
-        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
-#else
-        uint64_t qos                     : 3;
-        uint64_t static_q                : 1;
-        uint64_t s_tail                  : 1;
-        uint64_t reserved_5_7            : 3;
-        uint64_t doorbell                : 20;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn30xx;
-    struct cvmx_pko_mem_debug9_cn30xx    cn31xx;
-    struct cvmx_pko_mem_debug9_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t doorbell                : 20;      /**< Doorbell count */
-        uint64_t reserved_6_7            : 2;
-        uint64_t static_p                : 1;       /**< Static priority (port) */
-        uint64_t s_tail                  : 1;       /**< Static tail */
-        uint64_t static_q                : 1;       /**< Static priority */
-        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
-#else
-        uint64_t qos                     : 3;
-        uint64_t static_q                : 1;
-        uint64_t s_tail                  : 1;
-        uint64_t static_p                : 1;
-        uint64_t reserved_6_7            : 2;
-        uint64_t doorbell                : 20;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn38xx;
-    struct cvmx_pko_mem_debug9_cn38xx    cn38xxp2;
-    struct cvmx_pko_mem_debug9_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_49_63          : 15;
-        uint64_t ptrs0                   : 17;      /**< Internal state */
-        uint64_t reserved_17_31          : 15;
-        uint64_t ptrs3                   : 17;      /**< Internal state */
-#else
-        uint64_t ptrs3                   : 17;
-        uint64_t reserved_17_31          : 15;
-        uint64_t ptrs0                   : 17;
-        uint64_t reserved_49_63          : 15;
-#endif
-    } cn50xx;
-    struct cvmx_pko_mem_debug9_cn50xx    cn52xx;
-    struct cvmx_pko_mem_debug9_cn50xx    cn52xxp1;
-    struct cvmx_pko_mem_debug9_cn50xx    cn56xx;
-    struct cvmx_pko_mem_debug9_cn50xx    cn56xxp1;
-    struct cvmx_pko_mem_debug9_cn50xx    cn58xx;
-    struct cvmx_pko_mem_debug9_cn50xx    cn58xxp1;
-} cvmx_pko_mem_debug9_t;
-
-
-/**
- * cvmx_pko_mem_port_ptrs
- *
- * Notes:
- * Sets the port to engine mapping, per port.  Ports marked as static priority need not be contiguous,
- * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff.  If EID==8
- * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface.
- * EID==15 can be used for unused PKO-internal ports.
- * BP_PORT==63 means that the PKO-internal port is not backpressured.
- * BP_PORTs are assumed to belong to an interface as follows:
- *   36 <= BP_PORT < 40 -> loopback   interface
- *   32 <= BP_PORT < 36 -> PCIe       interface
- *   0  <= BP_PORT < 16 -> SGMII/Xaui interface 0
- * The reset configuration is the following:
- *   PID EID(ext port) BP_PORT QOS_MASK STATIC_P
- *   -------------------------------------------
- *     0   0( 0)             0     0xff        0
- *     1   1( 1)             1     0xff        0
- *     2   2( 2)             2     0xff        0
- *     3   3( 3)             3     0xff        0
- *     4   0( 0)             4     0xff        0
- *     5   1( 1)             5     0xff        0
- *     6   2( 2)             6     0xff        0
- *     7   3( 3)             7     0xff        0
- *     8   0( 0)             8     0xff        0
- *     9   1( 1)             9     0xff        0
- *    10   2( 2)            10     0xff        0
- *    11   3( 3)            11     0xff        0
- *    12   0( 0)            12     0xff        0
- *    13   1( 1)            13     0xff        0
- *    14   2( 2)            14     0xff        0
- *    15   3( 3)            15     0xff        0
- *   -------------------------------------------
- *    16   0( 0)             0     0xff        0
- *    17   1( 1)             1     0xff        0
- *    18   2( 2)             2     0xff        0
- *    19   3( 3)             3     0xff        0
- *    20   0( 0)             4     0xff        0
- *    21   1( 1)             5     0xff        0
- *    22   2( 2)             6     0xff        0
- *    23   3( 3)             7     0xff        0
- *    24   0( 0)             8     0xff        0
- *    25   1( 1)             9     0xff        0
- *    26   2( 2)            10     0xff        0
- *    27   3( 3)            11     0xff        0
- *    28   0( 0)            12     0xff        0
- *    29   1( 1)            13     0xff        0
- *    30   2( 2)            14     0xff        0
- *    31   3( 3)            15     0xff        0
- *   -------------------------------------------
- *    32   8(32)            32     0xff        0
- *    33   8(33)            33     0xff        0
- *    34   8(34)            34     0xff        0
- *    35   8(35)            35     0xff        0
- *   -------------------------------------------
- *    36   9(36)            36     0xff        0
- *    37   9(37)            37     0xff        0
- *    38   9(38)            38     0xff        0
- *    39   9(39)            39     0xff        0
- * 
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_port_ptrs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_62_63          : 2;
-        uint64_t static_p                : 1;       /**< Set if this PID has static priority */
-        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
-        uint64_t reserved_16_52          : 37;
-        uint64_t bp_port                 : 6;       /**< PID listens to BP_PORT for per-packet backpressure
-                                                         Legal BP_PORTs: 0-39, 63 (63 means no BP) */
-        uint64_t eid                     : 4;       /**< Engine ID to which this port is mapped
-                                                         Legal EIDs: 0-9, 15 (15 only if port not used) */
-        uint64_t pid                     : 6;       /**< Port ID[5:0] */
-#else
-        uint64_t pid                     : 6;
-        uint64_t eid                     : 4;
-        uint64_t bp_port                 : 6;
-        uint64_t reserved_16_52          : 37;
-        uint64_t qos_mask                : 8;
-        uint64_t static_p                : 1;
-        uint64_t reserved_62_63          : 2;
-#endif
-    } s;
-    struct cvmx_pko_mem_port_ptrs_s      cn52xx;
-    struct cvmx_pko_mem_port_ptrs_s      cn52xxp1;
-    struct cvmx_pko_mem_port_ptrs_s      cn56xx;
-    struct cvmx_pko_mem_port_ptrs_s      cn56xxp1;
-} cvmx_pko_mem_port_ptrs_t;
-
-
-/**
- * cvmx_pko_mem_port_qos
- *
- * Notes:
- * Sets the QOS mask, per port.  These QOS_MASK bits are logically and physically the same QOS_MASK
- * bits in PKO_MEM_PORT_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
- * operation without affecting any other port state.  The engine to which port PID is mapped is engine
- * EID.  Note that the port to engine mapping must be the same as was previously programmed via the
- * PKO_MEM_PORT_PTRS CSR.
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_port_qos_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_61_63          : 3;
-        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
-        uint64_t reserved_10_52          : 43;
-        uint64_t eid                     : 4;       /**< Engine ID to which this port is mapped
-                                                         Legal EIDs: 0-9 */
-        uint64_t pid                     : 6;       /**< Port ID[5:0] */
-#else
-        uint64_t pid                     : 6;
-        uint64_t eid                     : 4;
-        uint64_t reserved_10_52          : 43;
-        uint64_t qos_mask                : 8;
-        uint64_t reserved_61_63          : 3;
-#endif
-    } s;
-    struct cvmx_pko_mem_port_qos_s       cn52xx;
-    struct cvmx_pko_mem_port_qos_s       cn52xxp1;
-    struct cvmx_pko_mem_port_qos_s       cn56xx;
-    struct cvmx_pko_mem_port_qos_s       cn56xxp1;
-} cvmx_pko_mem_port_qos_t;
-
-
-/**
- * cvmx_pko_mem_port_rate0
- *
- * Notes:
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_port_rate0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_51_63          : 13;
-        uint64_t rate_word               : 19;      /**< Rate limiting adder per 8 byte */
-        uint64_t rate_pkt                : 24;      /**< Rate limiting adder per packet */
-        uint64_t reserved_6_7            : 2;
-        uint64_t pid                     : 6;       /**< Port ID[5:0] */
-#else
-        uint64_t pid                     : 6;
-        uint64_t reserved_6_7            : 2;
-        uint64_t rate_pkt                : 24;
-        uint64_t rate_word               : 19;
-        uint64_t reserved_51_63          : 13;
-#endif
-    } s;
-    struct cvmx_pko_mem_port_rate0_s     cn52xx;
-    struct cvmx_pko_mem_port_rate0_s     cn52xxp1;
-    struct cvmx_pko_mem_port_rate0_s     cn56xx;
-    struct cvmx_pko_mem_port_rate0_s     cn56xxp1;
-} cvmx_pko_mem_port_rate0_t;
-
-
-/**
- * cvmx_pko_mem_port_rate1
- *
- * Notes:
- * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding
- * accumulator to zero.
- * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_port_rate1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rate_lim                : 24;      /**< Rate limiting accumulator limit */
-        uint64_t reserved_6_7            : 2;
-        uint64_t pid                     : 6;       /**< Port ID[5:0] */
-#else
-        uint64_t pid                     : 6;
-        uint64_t reserved_6_7            : 2;
-        uint64_t rate_lim                : 24;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pko_mem_port_rate1_s     cn52xx;
-    struct cvmx_pko_mem_port_rate1_s     cn52xxp1;
-    struct cvmx_pko_mem_port_rate1_s     cn56xx;
-    struct cvmx_pko_mem_port_rate1_s     cn56xxp1;
-} cvmx_pko_mem_port_rate1_t;
-
-
-/**
- * cvmx_pko_mem_queue_ptrs
- *
- * Notes:
- * Sets the queue to port mapping and the initial command buffer pointer, per queue
- * Each queue may map to at most one port.  No more than 16 queues may map to a port.  The set of
- * queues that is mapped to a port must be a contiguous array of queues.  The port to which queue QID
- * is mapped is port PID.  The index of queue QID in port PID's queue list is IDX.  The last queue in
- * port PID's queue array must have its TAIL bit set.  Unused queues must be mapped to port 63.
- * STATIC_Q marks queue QID as having static priority.  STATIC_P marks the port PID to which QID is
- * mapped as having at least one queue with static priority.  If any QID that maps to PID has static
- * priority, then all QID that map to PID must have STATIC_P set.  Queues marked as static priority
- * must be contiguous and begin at IDX 0.  The last queue that is marked as having static priority
- * must have its S_TAIL bit set.
- * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_queue_ptrs_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t s_tail                  : 1;       /**< Set if this QID is the tail of the static queues */
-        uint64_t static_p                : 1;       /**< Set if any QID in this PID has static priority */
-        uint64_t static_q                : 1;       /**< Set if this QID has static priority */
-        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
-        uint64_t buf_ptr                 : 36;      /**< Command buffer pointer, <23:17> MBZ */
-        uint64_t tail                    : 1;       /**< Set if this QID is the tail of the queue array */
-        uint64_t index                   : 3;       /**< Index[2:0] (distance from head) in the queue array */
-        uint64_t port                    : 6;       /**< Port ID to which this queue is mapped */
-        uint64_t queue                   : 7;       /**< Queue ID[6:0] */
-#else
-        uint64_t queue                   : 7;
-        uint64_t port                    : 6;
-        uint64_t index                   : 3;
-        uint64_t tail                    : 1;
-        uint64_t buf_ptr                 : 36;
-        uint64_t qos_mask                : 8;
-        uint64_t static_q                : 1;
-        uint64_t static_p                : 1;
-        uint64_t s_tail                  : 1;
-#endif
-    } s;
-    struct cvmx_pko_mem_queue_ptrs_s     cn30xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn31xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn38xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn38xxp2;
-    struct cvmx_pko_mem_queue_ptrs_s     cn50xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn52xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn52xxp1;
-    struct cvmx_pko_mem_queue_ptrs_s     cn56xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn56xxp1;
-    struct cvmx_pko_mem_queue_ptrs_s     cn58xx;
-    struct cvmx_pko_mem_queue_ptrs_s     cn58xxp1;
-} cvmx_pko_mem_queue_ptrs_t;
-
-
-/**
- * cvmx_pko_mem_queue_qos
- *
- * Notes:
- * Sets the QOS mask, per queue.  These QOS_MASK bits are logically and physically the same QOS_MASK
- * bits in PKO_MEM_QUEUE_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
- * operation without affecting any other queue state.  The port to which queue QID is mapped is port
- * PID.  Note that the queue to port mapping must be the same as was previously programmed via the
- * PKO_MEM_QUEUE_PTRS CSR.
- * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_mem_queue_qos_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_61_63          : 3;
-        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
-        uint64_t reserved_13_52          : 40;
-        uint64_t pid                     : 6;       /**< Port ID to which this queue is mapped */
-        uint64_t qid                     : 7;       /**< Queue ID */
-#else
-        uint64_t qid                     : 7;
-        uint64_t pid                     : 6;
-        uint64_t reserved_13_52          : 40;
-        uint64_t qos_mask                : 8;
-        uint64_t reserved_61_63          : 3;
-#endif
-    } s;
-    struct cvmx_pko_mem_queue_qos_s      cn30xx;
-    struct cvmx_pko_mem_queue_qos_s      cn31xx;
-    struct cvmx_pko_mem_queue_qos_s      cn38xx;
-    struct cvmx_pko_mem_queue_qos_s      cn38xxp2;
-    struct cvmx_pko_mem_queue_qos_s      cn50xx;
-    struct cvmx_pko_mem_queue_qos_s      cn52xx;
-    struct cvmx_pko_mem_queue_qos_s      cn52xxp1;
-    struct cvmx_pko_mem_queue_qos_s      cn56xx;
-    struct cvmx_pko_mem_queue_qos_s      cn56xxp1;
-    struct cvmx_pko_mem_queue_qos_s      cn58xx;
-    struct cvmx_pko_mem_queue_qos_s      cn58xxp1;
-} cvmx_pko_mem_queue_qos_t;
-
-
-/**
- * cvmx_pko_reg_bist_result
- *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_bist_result_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_pko_reg_bist_result_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_27_63          : 37;
-        uint64_t psb2                    : 5;       /**< BiST result of the PSB   memories (0=pass, !0=fail) */
-        uint64_t count                   : 1;       /**< BiST result of the COUNT memories (0=pass, !0=fail) */
-        uint64_t rif                     : 1;       /**< BiST result of the RIF   memories (0=pass, !0=fail) */
-        uint64_t wif                     : 1;       /**< BiST result of the WIF   memories (0=pass, !0=fail) */
-        uint64_t ncb                     : 1;       /**< BiST result of the NCB   memories (0=pass, !0=fail) */
-        uint64_t out                     : 1;       /**< BiST result of the OUT   memories (0=pass, !0=fail) */
-        uint64_t crc                     : 1;       /**< BiST result of the CRC   memories (0=pass, !0=fail) */
-        uint64_t chk                     : 1;       /**< BiST result of the CHK   memories (0=pass, !0=fail) */
-        uint64_t qsb                     : 2;       /**< BiST result of the QSB   memories (0=pass, !0=fail) */
-        uint64_t qcb                     : 2;       /**< BiST result of the QCB   memories (0=pass, !0=fail) */
-        uint64_t pdb                     : 4;       /**< BiST result of the PDB   memories (0=pass, !0=fail) */
-        uint64_t psb                     : 7;       /**< BiST result of the PSB   memories (0=pass, !0=fail) */
-#else
-        uint64_t psb                     : 7;
-        uint64_t pdb                     : 4;
-        uint64_t qcb                     : 2;
-        uint64_t qsb                     : 2;
-        uint64_t chk                     : 1;
-        uint64_t crc                     : 1;
-        uint64_t out                     : 1;
-        uint64_t ncb                     : 1;
-        uint64_t wif                     : 1;
-        uint64_t rif                     : 1;
-        uint64_t count                   : 1;
-        uint64_t psb2                    : 5;
-        uint64_t reserved_27_63          : 37;
-#endif
-    } cn30xx;
-    struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
-    struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
-    struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
-    struct cvmx_pko_reg_bist_result_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_33_63          : 31;
-        uint64_t csr                     : 1;       /**< BiST result of CSR      memories (0=pass, !0=fail) */
-        uint64_t iob                     : 1;       /**< BiST result of IOB      memories (0=pass, !0=fail) */
-        uint64_t out_crc                 : 1;       /**< BiST result of OUT_CRC  memories (0=pass, !0=fail) */
-        uint64_t out_ctl                 : 3;       /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
-        uint64_t out_sta                 : 1;       /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
-        uint64_t out_wif                 : 1;       /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
-        uint64_t prt_chk                 : 3;       /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
-        uint64_t prt_nxt                 : 1;       /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
-        uint64_t prt_psb                 : 6;       /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
-        uint64_t ncb_inb                 : 2;       /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
-        uint64_t prt_qcb                 : 2;       /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
-        uint64_t prt_qsb                 : 3;       /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
-        uint64_t dat_dat                 : 4;       /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
-        uint64_t dat_ptr                 : 4;       /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
-#else
-        uint64_t dat_ptr                 : 4;
-        uint64_t dat_dat                 : 4;
-        uint64_t prt_qsb                 : 3;
-        uint64_t prt_qcb                 : 2;
-        uint64_t ncb_inb                 : 2;
-        uint64_t prt_psb                 : 6;
-        uint64_t prt_nxt                 : 1;
-        uint64_t prt_chk                 : 3;
-        uint64_t out_wif                 : 1;
-        uint64_t out_sta                 : 1;
-        uint64_t out_ctl                 : 3;
-        uint64_t out_crc                 : 1;
-        uint64_t iob                     : 1;
-        uint64_t csr                     : 1;
-        uint64_t reserved_33_63          : 31;
-#endif
-    } cn50xx;
-    struct cvmx_pko_reg_bist_result_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_35_63          : 29;
-        uint64_t csr                     : 1;       /**< BiST result of CSR      memories (0=pass, !0=fail) */
-        uint64_t iob                     : 1;       /**< BiST result of IOB      memories (0=pass, !0=fail) */
-        uint64_t out_dat                 : 1;       /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
-        uint64_t out_ctl                 : 3;       /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
-        uint64_t out_sta                 : 1;       /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
-        uint64_t out_wif                 : 1;       /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
-        uint64_t prt_chk                 : 3;       /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
-        uint64_t prt_nxt                 : 1;       /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
-        uint64_t prt_psb                 : 8;       /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
-        uint64_t ncb_inb                 : 2;       /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
-        uint64_t prt_qcb                 : 2;       /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
-        uint64_t prt_qsb                 : 3;       /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
-        uint64_t prt_ctl                 : 2;       /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
-        uint64_t dat_dat                 : 2;       /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
-        uint64_t dat_ptr                 : 4;       /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
-#else
-        uint64_t dat_ptr                 : 4;
-        uint64_t dat_dat                 : 2;
-        uint64_t prt_ctl                 : 2;
-        uint64_t prt_qsb                 : 3;
-        uint64_t prt_qcb                 : 2;
-        uint64_t ncb_inb                 : 2;
-        uint64_t prt_psb                 : 8;
-        uint64_t prt_nxt                 : 1;
-        uint64_t prt_chk                 : 3;
-        uint64_t out_wif                 : 1;
-        uint64_t out_sta                 : 1;
-        uint64_t out_ctl                 : 3;
-        uint64_t out_dat                 : 1;
-        uint64_t iob                     : 1;
-        uint64_t csr                     : 1;
-        uint64_t reserved_35_63          : 29;
-#endif
-    } cn52xx;
-    struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
-    struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
-    struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
-    struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
-    struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
-} cvmx_pko_reg_bist_result_t;
-
-
-/**
- * cvmx_pko_reg_cmd_buf
- *
- * Notes:
- * Sets the command buffer parameters
- * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
- * lists to be used when freeing command buffer segments.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_cmd_buf_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_23_63          : 41;
-        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
-        uint64_t reserved_13_19          : 7;
-        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
-#else
-        uint64_t size                    : 13;
-        uint64_t reserved_13_19          : 7;
-        uint64_t pool                    : 3;
-        uint64_t reserved_23_63          : 41;
-#endif
-    } s;
-    struct cvmx_pko_reg_cmd_buf_s        cn30xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn31xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn38xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn38xxp2;
-    struct cvmx_pko_reg_cmd_buf_s        cn50xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn52xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn52xxp1;
-    struct cvmx_pko_reg_cmd_buf_s        cn56xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn56xxp1;
-    struct cvmx_pko_reg_cmd_buf_s        cn58xx;
-    struct cvmx_pko_reg_cmd_buf_s        cn58xxp1;
-} cvmx_pko_reg_cmd_buf_t;
-
-
-/**
- * cvmx_pko_reg_crc_ctl#
- *
- * Notes:
- * Controls datapath reflection when calculating CRC
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_crc_ctlx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t invres                  : 1;       /**< Invert the result */
-        uint64_t refin                   : 1;       /**< Reflect the bits in each byte.
-                                                          Byte order does not change.
-                                                         - 0: CRC is calculated MSB to LSB
-                                                         - 1: CRC is calculated MLB to MSB */
-#else
-        uint64_t refin                   : 1;
-        uint64_t invres                  : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pko_reg_crc_ctlx_s       cn38xx;
-    struct cvmx_pko_reg_crc_ctlx_s       cn38xxp2;
-    struct cvmx_pko_reg_crc_ctlx_s       cn58xx;
-    struct cvmx_pko_reg_crc_ctlx_s       cn58xxp1;
-} cvmx_pko_reg_crc_ctlx_t;
-
-
-/**
- * cvmx_pko_reg_crc_enable
- *
- * Notes:
- * Enables CRC for the GMX ports.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_crc_enable_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t enable                  : 32;      /**< Mask for ports 31-0 to enable CRC
-                                                         Mask bit==0 means CRC not enabled
-                                                         Mask bit==1 means CRC     enabled
-                                                         Note that CRC should be enabled only when using SPI4.2 */
-#else
-        uint64_t enable                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pko_reg_crc_enable_s     cn38xx;
-    struct cvmx_pko_reg_crc_enable_s     cn38xxp2;
-    struct cvmx_pko_reg_crc_enable_s     cn58xx;
-    struct cvmx_pko_reg_crc_enable_s     cn58xxp1;
-} cvmx_pko_reg_crc_enable_t;
-
-
-/**
- * cvmx_pko_reg_crc_iv#
- *
- * Notes:
- * Determines the IV used by the CRC algorithm
- * * PKO_CRC_IV
- *  PKO_CRC_IV controls the initial state of the CRC algorithm.  Octane can
- *  support a wide range of CRC algorithms and as such, the IV must be
- *  carefully constructed to meet the specific algorithm.  The code below
- *  determines the value to program into Octane based on the algorthim's IV
- *  and width.  In the case of Octane, the width should always be 32.
- * 
- *  PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for
- *  ports 16-31.
- * 
- *   @verbatim
- *   unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
- *   [
- *     int i;
- *     int doit;
- *     unsigned int current_val = algorithm_iv;
- * 
- *     for(i = 0; i < w; i++) [
- *       doit = current_val & 0x1;
- * 
- *       if(doit) current_val ^= poly;
- *       assert(!(current_val & 0x1));
- * 
- *       current_val = (current_val >> 1) | (doit << (w-1));
- *     ]
- * 
- *     return current_val;
- *   ]
- *   @endverbatim
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_crc_ivx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iv                      : 32;      /**< IV used by the CRC algorithm.  Default is FCS32. */
-#else
-        uint64_t iv                      : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pko_reg_crc_ivx_s        cn38xx;
-    struct cvmx_pko_reg_crc_ivx_s        cn38xxp2;
-    struct cvmx_pko_reg_crc_ivx_s        cn58xx;
-    struct cvmx_pko_reg_crc_ivx_s        cn58xxp1;
-} cvmx_pko_reg_crc_ivx_t;
-
-
-/**
- * cvmx_pko_reg_debug0
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t asserts                 : 64;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 64;
-#endif
-    } s;
-    struct cvmx_pko_reg_debug0_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t asserts                 : 17;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn30xx;
-    struct cvmx_pko_reg_debug0_cn30xx    cn31xx;
-    struct cvmx_pko_reg_debug0_cn30xx    cn38xx;
-    struct cvmx_pko_reg_debug0_cn30xx    cn38xxp2;
-    struct cvmx_pko_reg_debug0_s         cn50xx;
-    struct cvmx_pko_reg_debug0_s         cn52xx;
-    struct cvmx_pko_reg_debug0_s         cn52xxp1;
-    struct cvmx_pko_reg_debug0_s         cn56xx;
-    struct cvmx_pko_reg_debug0_s         cn56xxp1;
-    struct cvmx_pko_reg_debug0_s         cn58xx;
-    struct cvmx_pko_reg_debug0_s         cn58xxp1;
-} cvmx_pko_reg_debug0_t;
-
-
-/**
- * cvmx_pko_reg_debug1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_debug1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t asserts                 : 64;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 64;
-#endif
-    } s;
-    struct cvmx_pko_reg_debug1_s         cn50xx;
-    struct cvmx_pko_reg_debug1_s         cn52xx;
-    struct cvmx_pko_reg_debug1_s         cn52xxp1;
-    struct cvmx_pko_reg_debug1_s         cn56xx;
-    struct cvmx_pko_reg_debug1_s         cn56xxp1;
-    struct cvmx_pko_reg_debug1_s         cn58xx;
-    struct cvmx_pko_reg_debug1_s         cn58xxp1;
-} cvmx_pko_reg_debug1_t;
-
-
-/**
- * cvmx_pko_reg_debug2
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_debug2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t asserts                 : 64;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 64;
-#endif
-    } s;
-    struct cvmx_pko_reg_debug2_s         cn50xx;
-    struct cvmx_pko_reg_debug2_s         cn52xx;
-    struct cvmx_pko_reg_debug2_s         cn52xxp1;
-    struct cvmx_pko_reg_debug2_s         cn56xx;
-    struct cvmx_pko_reg_debug2_s         cn56xxp1;
-    struct cvmx_pko_reg_debug2_s         cn58xx;
-    struct cvmx_pko_reg_debug2_s         cn58xxp1;
-} cvmx_pko_reg_debug2_t;
-
-
-/**
- * cvmx_pko_reg_debug3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_debug3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t asserts                 : 64;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 64;
-#endif
-    } s;
-    struct cvmx_pko_reg_debug3_s         cn50xx;
-    struct cvmx_pko_reg_debug3_s         cn52xx;
-    struct cvmx_pko_reg_debug3_s         cn52xxp1;
-    struct cvmx_pko_reg_debug3_s         cn56xx;
-    struct cvmx_pko_reg_debug3_s         cn56xxp1;
-    struct cvmx_pko_reg_debug3_s         cn58xx;
-    struct cvmx_pko_reg_debug3_s         cn58xxp1;
-} cvmx_pko_reg_debug3_t;
-
-
-/**
- * cvmx_pko_reg_engine_inflight
- *
- * Notes:
- * Sets the maximum number of inflight packets, per engine.  Values greater than 4 are illegal.
- * Setting an engine's value to 0 effectively stops the engine.
- * Note that engines 4-7 do not exist
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_engine_inflight_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t engine9                 : 4;       /**< Maximum number of inflight packets for engine9 */
-        uint64_t engine8                 : 4;       /**< Maximum number of inflight packets for engine8 */
-        uint64_t engine7                 : 4;       /**< Maximum number of inflight packets for engine7 */
-        uint64_t engine6                 : 4;       /**< Maximum number of inflight packets for engine6 */
-        uint64_t engine5                 : 4;       /**< Maximum number of inflight packets for engine5 */
-        uint64_t engine4                 : 4;       /**< Maximum number of inflight packets for engine4 */
-        uint64_t engine3                 : 4;       /**< Maximum number of inflight packets for engine3 */
-        uint64_t engine2                 : 4;       /**< Maximum number of inflight packets for engine2 */
-        uint64_t engine1                 : 4;       /**< Maximum number of inflight packets for engine1 */
-        uint64_t engine0                 : 4;       /**< Maximum number of inflight packets for engine0 */
-#else
-        uint64_t engine0                 : 4;
-        uint64_t engine1                 : 4;
-        uint64_t engine2                 : 4;
-        uint64_t engine3                 : 4;
-        uint64_t engine4                 : 4;
-        uint64_t engine5                 : 4;
-        uint64_t engine6                 : 4;
-        uint64_t engine7                 : 4;
-        uint64_t engine8                 : 4;
-        uint64_t engine9                 : 4;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_pko_reg_engine_inflight_s cn52xx;
-    struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
-    struct cvmx_pko_reg_engine_inflight_s cn56xx;
-    struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
-} cvmx_pko_reg_engine_inflight_t;
-
-
-/**
- * cvmx_pko_reg_engine_thresh
- *
- * Notes:
- * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers.
- * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will
- * be sent until all of it has been written into the PKO's internal buffer.  Note that a packet is
- * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8.  When enabled and the
- * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
- * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
- * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
- * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_engine_thresh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t mask                    : 10;      /**< Mask[n]=0 disables packet send threshold for engine n
-                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS */
-#else
-        uint64_t mask                    : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_pko_reg_engine_thresh_s  cn52xx;
-    struct cvmx_pko_reg_engine_thresh_s  cn52xxp1;
-    struct cvmx_pko_reg_engine_thresh_s  cn56xx;
-    struct cvmx_pko_reg_engine_thresh_s  cn56xxp1;
-} cvmx_pko_reg_engine_thresh_t;
-
-
-/**
- * cvmx_pko_reg_error
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_error_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t currzero                : 1;       /**< A packet data pointer has size=0 */
-        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
-        uint64_t parity                  : 1;       /**< Read parity error at port data buffer */
-#else
-        uint64_t parity                  : 1;
-        uint64_t doorbell                : 1;
-        uint64_t currzero                : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_pko_reg_error_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
-        uint64_t parity                  : 1;       /**< Read parity error at port data buffer */
-#else
-        uint64_t parity                  : 1;
-        uint64_t doorbell                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn30xx;
-    struct cvmx_pko_reg_error_cn30xx     cn31xx;
-    struct cvmx_pko_reg_error_cn30xx     cn38xx;
-    struct cvmx_pko_reg_error_cn30xx     cn38xxp2;
-    struct cvmx_pko_reg_error_s          cn50xx;
-    struct cvmx_pko_reg_error_s          cn52xx;
-    struct cvmx_pko_reg_error_s          cn52xxp1;
-    struct cvmx_pko_reg_error_s          cn56xx;
-    struct cvmx_pko_reg_error_s          cn56xxp1;
-    struct cvmx_pko_reg_error_s          cn58xx;
-    struct cvmx_pko_reg_error_s          cn58xxp1;
-} cvmx_pko_reg_error_t;
-
-
-/**
- * cvmx_pko_reg_flags
- *
- * Notes:
- * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation.  When set, ENA_DWB
- * enables the use of DontWriteBacks during the buffer freeing operations.  When not set, STORE_BE inverts
- * bits[2:0] of the STORE0 byte write address.  When set, RESET causes a 4-cycle reset pulse to the
- * entire box.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_flags_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t reset                   : 1;       /**< Reset oneshot pulse */
-        uint64_t store_be                : 1;       /**< Force STORE0 byte write address to big endian */
-        uint64_t ena_dwb                 : 1;       /**< Set to enable DontWriteBacks */
-        uint64_t ena_pko                 : 1;       /**< Set to enable the PKO picker */
-#else
-        uint64_t ena_pko                 : 1;
-        uint64_t ena_dwb                 : 1;
-        uint64_t store_be                : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_pko_reg_flags_s          cn30xx;
-    struct cvmx_pko_reg_flags_s          cn31xx;
-    struct cvmx_pko_reg_flags_s          cn38xx;
-    struct cvmx_pko_reg_flags_s          cn38xxp2;
-    struct cvmx_pko_reg_flags_s          cn50xx;
-    struct cvmx_pko_reg_flags_s          cn52xx;
-    struct cvmx_pko_reg_flags_s          cn52xxp1;
-    struct cvmx_pko_reg_flags_s          cn56xx;
-    struct cvmx_pko_reg_flags_s          cn56xxp1;
-    struct cvmx_pko_reg_flags_s          cn58xx;
-    struct cvmx_pko_reg_flags_s          cn58xxp1;
-} cvmx_pko_reg_flags_t;
-
-
-/**
- * cvmx_pko_reg_gmx_port_mode
- *
- * Notes:
- * The system has a total of 4 + 0 + 4 + 4 ports and 4 + 0 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP).
- * This CSR sets the number of GMX0 ports and amount of local storage per engine.
- * It has no effect on the number of ports or amount of local storage per engine for
- * PCI or LOOP.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
- * storage.  Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
- * increases the local storage per PKO GMX engine by a power of 2.
- * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
- * 
- * MODE[n] GM[0] PCI   LOOP  GM[0]                      PCI            LOOP
- *         ports ports ports storage/engine             storage/engine storage/engine
- * 0       4     4     4       2.5kB                    2.5kB          2.5kB
- * 1       4     4     4       2.5kB                    2.5kB          2.5kB
- * 2       4     4     4       2.5kB                    2.5kB          2.5kB
- * 3       2     4     4       5.0kB                    2.5kB          2.5kB
- * 4       1     4     4      10.0kB                    2.5kB          2.5kB
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_gmx_port_mode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mode1                   : 3;       /**< # of GM1 ports = 16 >> MODE1, 0 <= MODE1 <= 5 */
-        uint64_t mode0                   : 3;       /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 5 */
-#else
-        uint64_t mode0                   : 3;
-        uint64_t mode1                   : 3;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn30xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn31xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn38xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn38xxp2;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn50xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn52xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn52xxp1;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn56xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn56xxp1;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn58xx;
-    struct cvmx_pko_reg_gmx_port_mode_s  cn58xxp1;
-} cvmx_pko_reg_gmx_port_mode_t;
-
-
-/**
- * cvmx_pko_reg_int_mask
- *
- * Notes:
- * When a mask bit is set, the corresponding interrupt is enabled.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_int_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t currzero                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
-        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
-        uint64_t parity                  : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
-#else
-        uint64_t parity                  : 1;
-        uint64_t doorbell                : 1;
-        uint64_t currzero                : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_pko_reg_int_mask_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
-        uint64_t parity                  : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
-#else
-        uint64_t parity                  : 1;
-        uint64_t doorbell                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } cn30xx;
-    struct cvmx_pko_reg_int_mask_cn30xx  cn31xx;
-    struct cvmx_pko_reg_int_mask_cn30xx  cn38xx;
-    struct cvmx_pko_reg_int_mask_cn30xx  cn38xxp2;
-    struct cvmx_pko_reg_int_mask_s       cn50xx;
-    struct cvmx_pko_reg_int_mask_s       cn52xx;
-    struct cvmx_pko_reg_int_mask_s       cn52xxp1;
-    struct cvmx_pko_reg_int_mask_s       cn56xx;
-    struct cvmx_pko_reg_int_mask_s       cn56xxp1;
-    struct cvmx_pko_reg_int_mask_s       cn58xx;
-    struct cvmx_pko_reg_int_mask_s       cn58xxp1;
-} cvmx_pko_reg_int_mask_t;
-
-
-/**
- * cvmx_pko_reg_queue_mode
- *
- * Notes:
- * Sets the number of queues and amount of local storage per queue
- * The system has a total of 256 queues and (256*8) words of local command storage.  This CSR sets the
- * number of queues that are used.  Increasing the value of MODE by 1 decreases the number of queues
- * by a power of 2 and increases the local storage per queue by a power of 2.
- * MODEn queues storage/queue
- * 0     256     64B ( 8 words)
- * 1     128    128B (16 words)
- * 2      64    256B (32 words)
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_queue_mode_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t mode                    : 2;       /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
-#else
-        uint64_t mode                    : 2;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pko_reg_queue_mode_s     cn30xx;
-    struct cvmx_pko_reg_queue_mode_s     cn31xx;
-    struct cvmx_pko_reg_queue_mode_s     cn38xx;
-    struct cvmx_pko_reg_queue_mode_s     cn38xxp2;
-    struct cvmx_pko_reg_queue_mode_s     cn50xx;
-    struct cvmx_pko_reg_queue_mode_s     cn52xx;
-    struct cvmx_pko_reg_queue_mode_s     cn52xxp1;
-    struct cvmx_pko_reg_queue_mode_s     cn56xx;
-    struct cvmx_pko_reg_queue_mode_s     cn56xxp1;
-    struct cvmx_pko_reg_queue_mode_s     cn58xx;
-    struct cvmx_pko_reg_queue_mode_s     cn58xxp1;
-} cvmx_pko_reg_queue_mode_t;
-
-
-/**
- * cvmx_pko_reg_queue_ptrs1
- *
- * Notes:
- * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255
- * and to allow up mapping of up to 16 queues per port.  When programming queues 128-255, the
- * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or
- * PKO_MEM_QUEUE_QOS for each queue.
- * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
- * programming.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_queue_ptrs1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t idx3                    : 1;       /**< [3] of Index (distance from head) in the queue array */
-        uint64_t qid7                    : 1;       /**< [7] of Queue ID */
-#else
-        uint64_t qid7                    : 1;
-        uint64_t idx3                    : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn50xx;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn52xx;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn52xxp1;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn56xx;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn56xxp1;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn58xx;
-    struct cvmx_pko_reg_queue_ptrs1_s    cn58xxp1;
-} cvmx_pko_reg_queue_ptrs1_t;
-
-
-/**
- * cvmx_pko_reg_read_idx
- *
- * Notes:
- * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
- * as memories.  The names of these CSRs begin with the prefix "PKO_MEM_".
- * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
- * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
- * contents of a CSR memory can be read with consecutive CSR read commands.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pko_reg_read_idx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t inc                     : 8;       /**< Increment to add to current index for next index */
-        uint64_t index                   : 8;       /**< Index to use for next memory CSR read */
-#else
-        uint64_t index                   : 8;
-        uint64_t inc                     : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_pko_reg_read_idx_s       cn30xx;
-    struct cvmx_pko_reg_read_idx_s       cn31xx;
-    struct cvmx_pko_reg_read_idx_s       cn38xx;
-    struct cvmx_pko_reg_read_idx_s       cn38xxp2;
-    struct cvmx_pko_reg_read_idx_s       cn50xx;
-    struct cvmx_pko_reg_read_idx_s       cn52xx;
-    struct cvmx_pko_reg_read_idx_s       cn52xxp1;
-    struct cvmx_pko_reg_read_idx_s       cn56xx;
-    struct cvmx_pko_reg_read_idx_s       cn56xxp1;
-    struct cvmx_pko_reg_read_idx_s       cn58xx;
-    struct cvmx_pko_reg_read_idx_s       cn58xxp1;
-} cvmx_pko_reg_read_idx_t;
-
-
-/**
- * cvmx_pow_bist_stat
- *
- * POW_BIST_STAT = POW BIST Status Register
- * 
- * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).
- * 
- * Also contains the BIST status for the PP's.  Each bit in the PP field is the OR of all BIST
- * results for the corresponding physical PP ('0' = pass, '1' = fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_bist_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pp                      : 16;      /**< Physical PP BIST status */
-        uint64_t reserved_0_15           : 16;
-#else
-        uint64_t reserved_0_15           : 16;
-        uint64_t pp                      : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_bist_stat_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t pp                      : 1;       /**< Physical PP BIST status */
-        uint64_t reserved_9_15           : 7;
-        uint64_t cam                     : 1;       /**< POW CAM BIST status */
-        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
-        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
-        uint64_t index                   : 1;       /**< Index memory BIST status */
-        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
-        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
-        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
-        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
-        uint64_t adr                     : 1;       /**< Address memory BIST status */
-#else
-        uint64_t adr                     : 1;
-        uint64_t pend                    : 1;
-        uint64_t nbr0                    : 1;
-        uint64_t nbr1                    : 1;
-        uint64_t fidx                    : 1;
-        uint64_t index                   : 1;
-        uint64_t nbt0                    : 1;
-        uint64_t nbt1                    : 1;
-        uint64_t cam                     : 1;
-        uint64_t reserved_9_15           : 7;
-        uint64_t pp                      : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn30xx;
-    struct cvmx_pow_bist_stat_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t pp                      : 2;       /**< Physical PP BIST status */
-        uint64_t reserved_9_15           : 7;
-        uint64_t cam                     : 1;       /**< POW CAM BIST status */
-        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
-        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
-        uint64_t index                   : 1;       /**< Index memory BIST status */
-        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
-        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
-        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
-        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
-        uint64_t adr                     : 1;       /**< Address memory BIST status */
-#else
-        uint64_t adr                     : 1;
-        uint64_t pend                    : 1;
-        uint64_t nbr0                    : 1;
-        uint64_t nbr1                    : 1;
-        uint64_t fidx                    : 1;
-        uint64_t index                   : 1;
-        uint64_t nbt0                    : 1;
-        uint64_t nbt1                    : 1;
-        uint64_t cam                     : 1;
-        uint64_t reserved_9_15           : 7;
-        uint64_t pp                      : 2;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn31xx;
-    struct cvmx_pow_bist_stat_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t pp                      : 16;      /**< Physical PP BIST status */
-        uint64_t reserved_10_15          : 6;
-        uint64_t cam                     : 1;       /**< POW CAM BIST status */
-        uint64_t nbt                     : 1;       /**< NCB transmitter memory BIST status */
-        uint64_t index                   : 1;       /**< Index memory BIST status */
-        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
-        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
-        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
-        uint64_t pend1                   : 1;       /**< Pending switch memory 1 BIST status */
-        uint64_t pend0                   : 1;       /**< Pending switch memory 0 BIST status */
-        uint64_t adr1                    : 1;       /**< Address memory 1 BIST status */
-        uint64_t adr0                    : 1;       /**< Address memory 0 BIST status */
-#else
-        uint64_t adr0                    : 1;
-        uint64_t adr1                    : 1;
-        uint64_t pend0                   : 1;
-        uint64_t pend1                   : 1;
-        uint64_t nbr0                    : 1;
-        uint64_t nbr1                    : 1;
-        uint64_t fidx                    : 1;
-        uint64_t index                   : 1;
-        uint64_t nbt                     : 1;
-        uint64_t cam                     : 1;
-        uint64_t reserved_10_15          : 6;
-        uint64_t pp                      : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } cn38xx;
-    struct cvmx_pow_bist_stat_cn38xx     cn38xxp2;
-    struct cvmx_pow_bist_stat_cn31xx     cn50xx;
-    struct cvmx_pow_bist_stat_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t pp                      : 4;       /**< Physical PP BIST status */
-        uint64_t reserved_9_15           : 7;
-        uint64_t cam                     : 1;       /**< POW CAM BIST status */
-        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
-        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
-        uint64_t index                   : 1;       /**< Index memory BIST status */
-        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
-        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
-        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
-        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
-        uint64_t adr                     : 1;       /**< Address memory BIST status */
-#else
-        uint64_t adr                     : 1;
-        uint64_t pend                    : 1;
-        uint64_t nbr0                    : 1;
-        uint64_t nbr1                    : 1;
-        uint64_t fidx                    : 1;
-        uint64_t index                   : 1;
-        uint64_t nbt0                    : 1;
-        uint64_t nbt1                    : 1;
-        uint64_t cam                     : 1;
-        uint64_t reserved_9_15           : 7;
-        uint64_t pp                      : 4;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn52xx;
-    struct cvmx_pow_bist_stat_cn52xx     cn52xxp1;
-    struct cvmx_pow_bist_stat_cn56xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t pp                      : 12;      /**< Physical PP BIST status */
-        uint64_t reserved_10_15          : 6;
-        uint64_t cam                     : 1;       /**< POW CAM BIST status */
-        uint64_t nbt                     : 1;       /**< NCB transmitter memory BIST status */
-        uint64_t index                   : 1;       /**< Index memory BIST status */
-        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
-        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
-        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
-        uint64_t pend1                   : 1;       /**< Pending switch memory 1 BIST status */
-        uint64_t pend0                   : 1;       /**< Pending switch memory 0 BIST status */
-        uint64_t adr1                    : 1;       /**< Address memory 1 BIST status */
-        uint64_t adr0                    : 1;       /**< Address memory 0 BIST status */
-#else
-        uint64_t adr0                    : 1;
-        uint64_t adr1                    : 1;
-        uint64_t pend0                   : 1;
-        uint64_t pend1                   : 1;
-        uint64_t nbr0                    : 1;
-        uint64_t nbr1                    : 1;
-        uint64_t fidx                    : 1;
-        uint64_t index                   : 1;
-        uint64_t nbt                     : 1;
-        uint64_t cam                     : 1;
-        uint64_t reserved_10_15          : 6;
-        uint64_t pp                      : 12;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn56xx;
-    struct cvmx_pow_bist_stat_cn56xx     cn56xxp1;
-    struct cvmx_pow_bist_stat_cn38xx     cn58xx;
-    struct cvmx_pow_bist_stat_cn38xx     cn58xxp1;
-} cvmx_pow_bist_stat_t;
-
-
-/**
- * cvmx_pow_ds_pc
- *
- * POW_DS_PC = POW De-Schedule Performance Counter
- * 
- * Counts the number of de-schedule requests.  Write to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_ds_pc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ds_pc                   : 32;      /**< De-schedule performance counter */
-#else
-        uint64_t ds_pc                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_ds_pc_s              cn30xx;
-    struct cvmx_pow_ds_pc_s              cn31xx;
-    struct cvmx_pow_ds_pc_s              cn38xx;
-    struct cvmx_pow_ds_pc_s              cn38xxp2;
-    struct cvmx_pow_ds_pc_s              cn50xx;
-    struct cvmx_pow_ds_pc_s              cn52xx;
-    struct cvmx_pow_ds_pc_s              cn52xxp1;
-    struct cvmx_pow_ds_pc_s              cn56xx;
-    struct cvmx_pow_ds_pc_s              cn56xxp1;
-    struct cvmx_pow_ds_pc_s              cn58xx;
-    struct cvmx_pow_ds_pc_s              cn58xxp1;
-} cvmx_pow_ds_pc_t;
-
-
-/**
- * cvmx_pow_ecc_err
- *
- * POW_ECC_ERR = POW ECC Error Register
- * 
- * Contains the single and double error bits and the corresponding interrupt enables for the ECC-
- * protected POW index memory.  Also contains the syndrome value in the event of an ECC error.
- * 
- * Also contains the remote pointer error bit and interrupt enable.  RPE is set when the POW detected
- * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer
- * for the L2/DRAM input queue did not match the last entry on the the list).   This is caused by
- * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work
- * queue entries.
- * 
- * This register also contains the illegal operation error bits and the corresponding interrupt
- * enables as follows:
- * 
- *  <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
- *  <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
- *  <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
- *  <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
- *  <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
- *  <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
- *  <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
- *  <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
- *  <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
- *  <9> Received illegal opcode
- * <10> Received ADD_WORK with tag specified as NULL_NULL
- * <11> Received DBG load from PP with DBG load pending
- * <12> Received CSR load from PP with CSR load pending
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_ecc_err_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_45_63          : 19;
-        uint64_t iop_ie                  : 13;      /**< Illegal operation interrupt enables */
-        uint64_t reserved_29_31          : 3;
-        uint64_t iop                     : 13;      /**< Illegal operation errors */
-        uint64_t reserved_14_15          : 2;
-        uint64_t rpe_ie                  : 1;       /**< Remote pointer error interrupt enable */
-        uint64_t rpe                     : 1;       /**< Remote pointer error */
-        uint64_t reserved_9_11           : 3;
-        uint64_t syn                     : 5;       /**< Syndrome value (only valid when DBE or SBE is set) */
-        uint64_t dbe_ie                  : 1;       /**< Double bit error interrupt enable */
-        uint64_t sbe_ie                  : 1;       /**< Single bit error interrupt enable */
-        uint64_t dbe                     : 1;       /**< Double bit error */
-        uint64_t sbe                     : 1;       /**< Single bit error */
-#else
-        uint64_t sbe                     : 1;
-        uint64_t dbe                     : 1;
-        uint64_t sbe_ie                  : 1;
-        uint64_t dbe_ie                  : 1;
-        uint64_t syn                     : 5;
-        uint64_t reserved_9_11           : 3;
-        uint64_t rpe                     : 1;
-        uint64_t rpe_ie                  : 1;
-        uint64_t reserved_14_15          : 2;
-        uint64_t iop                     : 13;
-        uint64_t reserved_29_31          : 3;
-        uint64_t iop_ie                  : 13;
-        uint64_t reserved_45_63          : 19;
-#endif
-    } s;
-    struct cvmx_pow_ecc_err_s            cn30xx;
-    struct cvmx_pow_ecc_err_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t rpe_ie                  : 1;       /**< Remote pointer error interrupt enable */
-        uint64_t rpe                     : 1;       /**< Remote pointer error */
-        uint64_t reserved_9_11           : 3;
-        uint64_t syn                     : 5;       /**< Syndrome value (only valid when DBE or SBE is set) */
-        uint64_t dbe_ie                  : 1;       /**< Double bit error interrupt enable */
-        uint64_t sbe_ie                  : 1;       /**< Single bit error interrupt enable */
-        uint64_t dbe                     : 1;       /**< Double bit error */
-        uint64_t sbe                     : 1;       /**< Single bit error */
-#else
-        uint64_t sbe                     : 1;
-        uint64_t dbe                     : 1;
-        uint64_t sbe_ie                  : 1;
-        uint64_t dbe_ie                  : 1;
-        uint64_t syn                     : 5;
-        uint64_t reserved_9_11           : 3;
-        uint64_t rpe                     : 1;
-        uint64_t rpe_ie                  : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } cn31xx;
-    struct cvmx_pow_ecc_err_s            cn38xx;
-    struct cvmx_pow_ecc_err_cn31xx       cn38xxp2;
-    struct cvmx_pow_ecc_err_s            cn50xx;
-    struct cvmx_pow_ecc_err_s            cn52xx;
-    struct cvmx_pow_ecc_err_s            cn52xxp1;
-    struct cvmx_pow_ecc_err_s            cn56xx;
-    struct cvmx_pow_ecc_err_s            cn56xxp1;
-    struct cvmx_pow_ecc_err_s            cn58xx;
-    struct cvmx_pow_ecc_err_s            cn58xxp1;
-} cvmx_pow_ecc_err_t;
-
-
-/**
- * cvmx_pow_int_ctl
- *
- * POW_INT_CTL = POW Internal Control Register
- * 
- * Contains POW internal control values (for internal use, not typically for customer use):
- * 
- * PFR_DIS = Disable high-performance pre-fetch reset mode.
- * 
- * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less
- * than or equal to this value.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_int_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t pfr_dis                 : 1;       /**< High-perf pre-fetch reset mode disable */
-        uint64_t nbr_thr                 : 5;       /**< NBR busy threshold */
-#else
-        uint64_t nbr_thr                 : 5;
-        uint64_t pfr_dis                 : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_pow_int_ctl_s            cn30xx;
-    struct cvmx_pow_int_ctl_s            cn31xx;
-    struct cvmx_pow_int_ctl_s            cn38xx;
-    struct cvmx_pow_int_ctl_s            cn38xxp2;
-    struct cvmx_pow_int_ctl_s            cn50xx;
-    struct cvmx_pow_int_ctl_s            cn52xx;
-    struct cvmx_pow_int_ctl_s            cn52xxp1;
-    struct cvmx_pow_int_ctl_s            cn56xx;
-    struct cvmx_pow_int_ctl_s            cn56xxp1;
-    struct cvmx_pow_int_ctl_s            cn58xx;
-    struct cvmx_pow_int_ctl_s            cn58xxp1;
-} cvmx_pow_int_ctl_t;
-
-
-/**
- * cvmx_pow_iq_cnt#
- *
- * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level)
- * 
- * Contains a read-only count of the number of work queue entries for each QOS level.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_iq_cntx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iq_cnt                  : 32;      /**< Input queue count for QOS level X */
-#else
-        uint64_t iq_cnt                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_iq_cntx_s            cn30xx;
-    struct cvmx_pow_iq_cntx_s            cn31xx;
-    struct cvmx_pow_iq_cntx_s            cn38xx;
-    struct cvmx_pow_iq_cntx_s            cn38xxp2;
-    struct cvmx_pow_iq_cntx_s            cn50xx;
-    struct cvmx_pow_iq_cntx_s            cn52xx;
-    struct cvmx_pow_iq_cntx_s            cn52xxp1;
-    struct cvmx_pow_iq_cntx_s            cn56xx;
-    struct cvmx_pow_iq_cntx_s            cn56xxp1;
-    struct cvmx_pow_iq_cntx_s            cn58xx;
-    struct cvmx_pow_iq_cntx_s            cn58xxp1;
-} cvmx_pow_iq_cntx_t;
-
-
-/**
- * cvmx_pow_iq_com_cnt
- *
- * POW_IQ_COM_CNT = POW Input Queue Combined Count Register
- * 
- * Contains a read-only count of the total number of work queue entries in all QOS levels.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_iq_com_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iq_cnt                  : 32;      /**< Input queue combined count */
-#else
-        uint64_t iq_cnt                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_iq_com_cnt_s         cn30xx;
-    struct cvmx_pow_iq_com_cnt_s         cn31xx;
-    struct cvmx_pow_iq_com_cnt_s         cn38xx;
-    struct cvmx_pow_iq_com_cnt_s         cn38xxp2;
-    struct cvmx_pow_iq_com_cnt_s         cn50xx;
-    struct cvmx_pow_iq_com_cnt_s         cn52xx;
-    struct cvmx_pow_iq_com_cnt_s         cn52xxp1;
-    struct cvmx_pow_iq_com_cnt_s         cn56xx;
-    struct cvmx_pow_iq_com_cnt_s         cn56xxp1;
-    struct cvmx_pow_iq_com_cnt_s         cn58xx;
-    struct cvmx_pow_iq_com_cnt_s         cn58xxp1;
-} cvmx_pow_iq_com_cnt_t;
-
-
-/**
- * cvmx_pow_iq_int
- *
- * POW_IQ_INT = POW Input Queue Interrupt Register
- * 
- * Contains the bits (1 per QOS level) that can trigger the input queue interrupt.  An IQ_INT bit
- * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_iq_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t iq_int                  : 8;       /**< Input queue interrupt bits */
-#else
-        uint64_t iq_int                  : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pow_iq_int_s             cn52xx;
-    struct cvmx_pow_iq_int_s             cn52xxp1;
-    struct cvmx_pow_iq_int_s             cn56xx;
-    struct cvmx_pow_iq_int_s             cn56xxp1;
-} cvmx_pow_iq_int_t;
-
-
-/**
- * cvmx_pow_iq_int_en
- *
- * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register
- * 
- * Contains the bits (1 per QOS level) that enable the input queue interrupt.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_iq_int_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t int_en                  : 8;       /**< Input queue interrupt enable bits */
-#else
-        uint64_t int_en                  : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pow_iq_int_en_s          cn52xx;
-    struct cvmx_pow_iq_int_en_s          cn52xxp1;
-    struct cvmx_pow_iq_int_en_s          cn56xx;
-    struct cvmx_pow_iq_int_en_s          cn56xxp1;
-} cvmx_pow_iq_int_en_t;
-
-
-/**
- * cvmx_pow_iq_thr#
- *
- * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level)
- * 
- * Threshold value for triggering input queue interrupts.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_iq_thrx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iq_thr                  : 32;      /**< Input queue threshold for QOS level X */
-#else
-        uint64_t iq_thr                  : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_iq_thrx_s            cn52xx;
-    struct cvmx_pow_iq_thrx_s            cn52xxp1;
-    struct cvmx_pow_iq_thrx_s            cn56xx;
-    struct cvmx_pow_iq_thrx_s            cn56xxp1;
-} cvmx_pow_iq_thrx_t;
-
-
-/**
- * cvmx_pow_nos_cnt
- *
- * POW_NOS_CNT = POW No-schedule Count Register
- * 
- * Contains the number of work queue entries on the no-schedule list.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_nos_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t nos_cnt                 : 12;      /**< # of work queue entries on the no-schedule list */
-#else
-        uint64_t nos_cnt                 : 12;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_pow_nos_cnt_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t nos_cnt                 : 7;       /**< # of work queue entries on the no-schedule list */
-#else
-        uint64_t nos_cnt                 : 7;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } cn30xx;
-    struct cvmx_pow_nos_cnt_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t nos_cnt                 : 9;       /**< # of work queue entries on the no-schedule list */
-#else
-        uint64_t nos_cnt                 : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } cn31xx;
-    struct cvmx_pow_nos_cnt_s            cn38xx;
-    struct cvmx_pow_nos_cnt_s            cn38xxp2;
-    struct cvmx_pow_nos_cnt_cn31xx       cn50xx;
-    struct cvmx_pow_nos_cnt_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t nos_cnt                 : 10;      /**< # of work queue entries on the no-schedule list */
-#else
-        uint64_t nos_cnt                 : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } cn52xx;
-    struct cvmx_pow_nos_cnt_cn52xx       cn52xxp1;
-    struct cvmx_pow_nos_cnt_s            cn56xx;
-    struct cvmx_pow_nos_cnt_s            cn56xxp1;
-    struct cvmx_pow_nos_cnt_s            cn58xx;
-    struct cvmx_pow_nos_cnt_s            cn58xxp1;
-} cvmx_pow_nos_cnt_t;
-
-
-/**
- * cvmx_pow_nw_tim
- *
- * POW_NW_TIM = POW New Work Timer Period Register
- * 
- * Sets the minimum period for a new work request timeout.  Period is specified in n-1 notation
- * where the increment value is 1024 clock cycles.  Thus, a value of 0x0 in this register translates
- * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc...  Note: the
- * maximum period for a new work request timeout is 2 times the minimum period.  Note: the new work
- * request timeout counter is reset when this register is written.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_nw_tim_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_10_63          : 54;
-        uint64_t nw_tim                  : 10;      /**< New work timer period */
-#else
-        uint64_t nw_tim                  : 10;
-        uint64_t reserved_10_63          : 54;
-#endif
-    } s;
-    struct cvmx_pow_nw_tim_s             cn30xx;
-    struct cvmx_pow_nw_tim_s             cn31xx;
-    struct cvmx_pow_nw_tim_s             cn38xx;
-    struct cvmx_pow_nw_tim_s             cn38xxp2;
-    struct cvmx_pow_nw_tim_s             cn50xx;
-    struct cvmx_pow_nw_tim_s             cn52xx;
-    struct cvmx_pow_nw_tim_s             cn52xxp1;
-    struct cvmx_pow_nw_tim_s             cn56xx;
-    struct cvmx_pow_nw_tim_s             cn56xxp1;
-    struct cvmx_pow_nw_tim_s             cn58xx;
-    struct cvmx_pow_nw_tim_s             cn58xxp1;
-} cvmx_pow_nw_tim_t;
-
-
-/**
- * cvmx_pow_pf_rst_msk
- *
- * POW_PF_RST_MSK = POW Prefetch Reset Mask
- * 
- * Resets the work prefetch engine when work is stored in an internal buffer (either when the add
- * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level
- * (1 bit per QOS level).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_pf_rst_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t rst_msk                 : 8;       /**< Prefetch engine reset mask */
-#else
-        uint64_t rst_msk                 : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_pow_pf_rst_msk_s         cn50xx;
-    struct cvmx_pow_pf_rst_msk_s         cn52xx;
-    struct cvmx_pow_pf_rst_msk_s         cn52xxp1;
-    struct cvmx_pow_pf_rst_msk_s         cn56xx;
-    struct cvmx_pow_pf_rst_msk_s         cn56xxp1;
-    struct cvmx_pow_pf_rst_msk_s         cn58xx;
-    struct cvmx_pow_pf_rst_msk_s         cn58xxp1;
-} cvmx_pow_pf_rst_msk_t;
-
-
-/**
- * cvmx_pow_pp_grp_msk#
- *
- * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP)
- * 
- * Selects which group(s) a PP belongs to.  A '1' in any bit position sets the PP's membership in
- * the corresponding group.  A value of 0x0 will prevent the PP from receiving new work.  Note:
- * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to
- * maximize POW performance.
- * 
- * Also contains the QOS level priorities for each PP.  0x0 is highest priority, and 0x7 the lowest.
- * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level.
- * Priority values 0x8 through 0xe are reserved and should not be used.  For a given PP, priorities
- * should begin at 0x0 and remain contiguous throughout the range.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_pp_grp_mskx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t qos7_pri                : 4;       /**< PPX priority for QOS level 7 */
-        uint64_t qos6_pri                : 4;       /**< PPX priority for QOS level 6 */
-        uint64_t qos5_pri                : 4;       /**< PPX priority for QOS level 5 */
-        uint64_t qos4_pri                : 4;       /**< PPX priority for QOS level 4 */
-        uint64_t qos3_pri                : 4;       /**< PPX priority for QOS level 3 */
-        uint64_t qos2_pri                : 4;       /**< PPX priority for QOS level 2 */
-        uint64_t qos1_pri                : 4;       /**< PPX priority for QOS level 1 */
-        uint64_t qos0_pri                : 4;       /**< PPX priority for QOS level 0 */
-        uint64_t grp_msk                 : 16;      /**< PPX group mask */
-#else
-        uint64_t grp_msk                 : 16;
-        uint64_t qos0_pri                : 4;
-        uint64_t qos1_pri                : 4;
-        uint64_t qos2_pri                : 4;
-        uint64_t qos3_pri                : 4;
-        uint64_t qos4_pri                : 4;
-        uint64_t qos5_pri                : 4;
-        uint64_t qos6_pri                : 4;
-        uint64_t qos7_pri                : 4;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_pow_pp_grp_mskx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t grp_msk                 : 16;      /**< PPX group mask */
-#else
-        uint64_t grp_msk                 : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn30xx;
-    struct cvmx_pow_pp_grp_mskx_cn30xx   cn31xx;
-    struct cvmx_pow_pp_grp_mskx_cn30xx   cn38xx;
-    struct cvmx_pow_pp_grp_mskx_cn30xx   cn38xxp2;
-    struct cvmx_pow_pp_grp_mskx_s        cn50xx;
-    struct cvmx_pow_pp_grp_mskx_s        cn52xx;
-    struct cvmx_pow_pp_grp_mskx_s        cn52xxp1;
-    struct cvmx_pow_pp_grp_mskx_s        cn56xx;
-    struct cvmx_pow_pp_grp_mskx_s        cn56xxp1;
-    struct cvmx_pow_pp_grp_mskx_s        cn58xx;
-    struct cvmx_pow_pp_grp_mskx_s        cn58xxp1;
-} cvmx_pow_pp_grp_mskx_t;
-
-
-/**
- * cvmx_pow_qos_rnd#
- *
- * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds)
- * 
- * Contains the round definitions for issuing new work.  Each round consists of 8 bits with each bit
- * corresponding to a QOS level.  There are 4 rounds contained in each register for a total of 32
- * rounds.  The issue logic traverses through the rounds sequentially (lowest round to highest round)
- * in an attempt to find new work for each PP.  Within each round, the issue logic traverses through
- * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear
- * bit in the round mask.  Note: setting a QOS level to all zeroes in all issue round registers will
- * prevent work from being issued from that QOS level.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_qos_rndx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t rnd_p3                  : 8;       /**< Round mask for round Xx4+3 */
-        uint64_t rnd_p2                  : 8;       /**< Round mask for round Xx4+2 */
-        uint64_t rnd_p1                  : 8;       /**< Round mask for round Xx4+1 */
-        uint64_t rnd                     : 8;       /**< Round mask for round Xx4 */
-#else
-        uint64_t rnd                     : 8;
-        uint64_t rnd_p1                  : 8;
-        uint64_t rnd_p2                  : 8;
-        uint64_t rnd_p3                  : 8;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_qos_rndx_s           cn30xx;
-    struct cvmx_pow_qos_rndx_s           cn31xx;
-    struct cvmx_pow_qos_rndx_s           cn38xx;
-    struct cvmx_pow_qos_rndx_s           cn38xxp2;
-    struct cvmx_pow_qos_rndx_s           cn50xx;
-    struct cvmx_pow_qos_rndx_s           cn52xx;
-    struct cvmx_pow_qos_rndx_s           cn52xxp1;
-    struct cvmx_pow_qos_rndx_s           cn56xx;
-    struct cvmx_pow_qos_rndx_s           cn56xxp1;
-    struct cvmx_pow_qos_rndx_s           cn58xx;
-    struct cvmx_pow_qos_rndx_s           cn58xxp1;
-} cvmx_pow_qos_rndx_t;
-
-
-/**
- * cvmx_pow_qos_thr#
- *
- * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level)
- * 
- * Contains the thresholds for allocating POW internal storage buffers.  If the number of remaining
- * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for
- * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries
- * will be buffered externally rather than internally.  This register also contains a read-only count
- * of the current number of free buffers (FREE_CNT), the number of internal buffers currently
- * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list
- * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_qos_thrx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t des_cnt                 : 12;      /**< # of buffers on de-schedule list */
-        uint64_t buf_cnt                 : 12;      /**< # of internal buffers allocated to QOS level X */
-        uint64_t free_cnt                : 12;      /**< # of total free buffers */
-        uint64_t reserved_23_23          : 1;
-        uint64_t max_thr                 : 11;      /**< Max threshold for QOS level X */
-        uint64_t reserved_11_11          : 1;
-        uint64_t min_thr                 : 11;      /**< Min threshold for QOS level X */
-#else
-        uint64_t min_thr                 : 11;
-        uint64_t reserved_11_11          : 1;
-        uint64_t max_thr                 : 11;
-        uint64_t reserved_23_23          : 1;
-        uint64_t free_cnt                : 12;
-        uint64_t buf_cnt                 : 12;
-        uint64_t des_cnt                 : 12;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_pow_qos_thrx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_55_63          : 9;
-        uint64_t des_cnt                 : 7;       /**< # of buffers on de-schedule list */
-        uint64_t reserved_43_47          : 5;
-        uint64_t buf_cnt                 : 7;       /**< # of internal buffers allocated to QOS level X */
-        uint64_t reserved_31_35          : 5;
-        uint64_t free_cnt                : 7;       /**< # of total free buffers */
-        uint64_t reserved_18_23          : 6;
-        uint64_t max_thr                 : 6;       /**< Max threshold for QOS level X */
-        uint64_t reserved_6_11           : 6;
-        uint64_t min_thr                 : 6;       /**< Min threshold for QOS level X */
-#else
-        uint64_t min_thr                 : 6;
-        uint64_t reserved_6_11           : 6;
-        uint64_t max_thr                 : 6;
-        uint64_t reserved_18_23          : 6;
-        uint64_t free_cnt                : 7;
-        uint64_t reserved_31_35          : 5;
-        uint64_t buf_cnt                 : 7;
-        uint64_t reserved_43_47          : 5;
-        uint64_t des_cnt                 : 7;
-        uint64_t reserved_55_63          : 9;
-#endif
-    } cn30xx;
-    struct cvmx_pow_qos_thrx_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_57_63          : 7;
-        uint64_t des_cnt                 : 9;       /**< # of buffers on de-schedule list */
-        uint64_t reserved_45_47          : 3;
-        uint64_t buf_cnt                 : 9;       /**< # of internal buffers allocated to QOS level X */
-        uint64_t reserved_33_35          : 3;
-        uint64_t free_cnt                : 9;       /**< # of total free buffers */
-        uint64_t reserved_20_23          : 4;
-        uint64_t max_thr                 : 8;       /**< Max threshold for QOS level X */
-        uint64_t reserved_8_11           : 4;
-        uint64_t min_thr                 : 8;       /**< Min threshold for QOS level X */
-#else
-        uint64_t min_thr                 : 8;
-        uint64_t reserved_8_11           : 4;
-        uint64_t max_thr                 : 8;
-        uint64_t reserved_20_23          : 4;
-        uint64_t free_cnt                : 9;
-        uint64_t reserved_33_35          : 3;
-        uint64_t buf_cnt                 : 9;
-        uint64_t reserved_45_47          : 3;
-        uint64_t des_cnt                 : 9;
-        uint64_t reserved_57_63          : 7;
-#endif
-    } cn31xx;
-    struct cvmx_pow_qos_thrx_s           cn38xx;
-    struct cvmx_pow_qos_thrx_s           cn38xxp2;
-    struct cvmx_pow_qos_thrx_cn31xx      cn50xx;
-    struct cvmx_pow_qos_thrx_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_58_63          : 6;
-        uint64_t des_cnt                 : 10;      /**< # of buffers on de-schedule list */
-        uint64_t reserved_46_47          : 2;
-        uint64_t buf_cnt                 : 10;      /**< # of internal buffers allocated to QOS level X */
-        uint64_t reserved_34_35          : 2;
-        uint64_t free_cnt                : 10;      /**< # of total free buffers */
-        uint64_t reserved_21_23          : 3;
-        uint64_t max_thr                 : 9;       /**< Max threshold for QOS level X */
-        uint64_t reserved_9_11           : 3;
-        uint64_t min_thr                 : 9;       /**< Min threshold for QOS level X */
-#else
-        uint64_t min_thr                 : 9;
-        uint64_t reserved_9_11           : 3;
-        uint64_t max_thr                 : 9;
-        uint64_t reserved_21_23          : 3;
-        uint64_t free_cnt                : 10;
-        uint64_t reserved_34_35          : 2;
-        uint64_t buf_cnt                 : 10;
-        uint64_t reserved_46_47          : 2;
-        uint64_t des_cnt                 : 10;
-        uint64_t reserved_58_63          : 6;
-#endif
-    } cn52xx;
-    struct cvmx_pow_qos_thrx_cn52xx      cn52xxp1;
-    struct cvmx_pow_qos_thrx_s           cn56xx;
-    struct cvmx_pow_qos_thrx_s           cn56xxp1;
-    struct cvmx_pow_qos_thrx_s           cn58xx;
-    struct cvmx_pow_qos_thrx_s           cn58xxp1;
-} cvmx_pow_qos_thrx_t;
-
-
-/**
- * cvmx_pow_ts_pc
- *
- * POW_TS_PC = POW Tag Switch Performance Counter
- * 
- * Counts the number of tag switch requests.  Write to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_ts_pc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ts_pc                   : 32;      /**< Tag switch performance counter */
-#else
-        uint64_t ts_pc                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_ts_pc_s              cn30xx;
-    struct cvmx_pow_ts_pc_s              cn31xx;
-    struct cvmx_pow_ts_pc_s              cn38xx;
-    struct cvmx_pow_ts_pc_s              cn38xxp2;
-    struct cvmx_pow_ts_pc_s              cn50xx;
-    struct cvmx_pow_ts_pc_s              cn52xx;
-    struct cvmx_pow_ts_pc_s              cn52xxp1;
-    struct cvmx_pow_ts_pc_s              cn56xx;
-    struct cvmx_pow_ts_pc_s              cn56xxp1;
-    struct cvmx_pow_ts_pc_s              cn58xx;
-    struct cvmx_pow_ts_pc_s              cn58xxp1;
-} cvmx_pow_ts_pc_t;
-
-
-/**
- * cvmx_pow_wa_com_pc
- *
- * POW_WA_COM_PC = POW Work Add Combined Performance Counter
- * 
- * Counts the number of add new work requests for all QOS levels.  Write to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wa_com_pc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wa_pc                   : 32;      /**< Work add combined performance counter */
-#else
-        uint64_t wa_pc                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_wa_com_pc_s          cn30xx;
-    struct cvmx_pow_wa_com_pc_s          cn31xx;
-    struct cvmx_pow_wa_com_pc_s          cn38xx;
-    struct cvmx_pow_wa_com_pc_s          cn38xxp2;
-    struct cvmx_pow_wa_com_pc_s          cn50xx;
-    struct cvmx_pow_wa_com_pc_s          cn52xx;
-    struct cvmx_pow_wa_com_pc_s          cn52xxp1;
-    struct cvmx_pow_wa_com_pc_s          cn56xx;
-    struct cvmx_pow_wa_com_pc_s          cn56xxp1;
-    struct cvmx_pow_wa_com_pc_s          cn58xx;
-    struct cvmx_pow_wa_com_pc_s          cn58xxp1;
-} cvmx_pow_wa_com_pc_t;
-
-
-/**
- * cvmx_pow_wa_pc#
- *
- * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level)
- * 
- * Counts the number of add new work requests for each QOS level.  Write to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wa_pcx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t wa_pc                   : 32;      /**< Work add performance counter for QOS level X */
-#else
-        uint64_t wa_pc                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_wa_pcx_s             cn30xx;
-    struct cvmx_pow_wa_pcx_s             cn31xx;
-    struct cvmx_pow_wa_pcx_s             cn38xx;
-    struct cvmx_pow_wa_pcx_s             cn38xxp2;
-    struct cvmx_pow_wa_pcx_s             cn50xx;
-    struct cvmx_pow_wa_pcx_s             cn52xx;
-    struct cvmx_pow_wa_pcx_s             cn52xxp1;
-    struct cvmx_pow_wa_pcx_s             cn56xx;
-    struct cvmx_pow_wa_pcx_s             cn56xxp1;
-    struct cvmx_pow_wa_pcx_s             cn58xx;
-    struct cvmx_pow_wa_pcx_s             cn58xxp1;
-} cvmx_pow_wa_pcx_t;
-
-
-/**
- * cvmx_pow_wq_int
- *
- * POW_WQ_INT = POW Work Queue Interrupt Register
- * 
- * Contains the bits (1 per group) that set work queue interrupts and are used to clear these
- * interrupts.  Also contains the input queue interrupt temporary disable bits (1 per group).  For
- * more information regarding this register, see the interrupt section.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wq_int_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t iq_dis                  : 16;      /**< Input queue interrupt temporary disable mask
-                                                         Corresponding WQ_INT<*> bit cannot be set due to
-                                                         IQ_CNT/IQ_THR check when this bit is set.
-                                                         Corresponding IQ_DIS bit is cleared by HW whenever:
-                                                          - POW_WQ_INT_CNT*[IQ_CNT] is zero, or
-                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
-                                                            counter POW_WQ_INT_PC[PC]==0 */
-        uint64_t wq_int                  : 16;      /**< Work queue interrupt bits
-                                                         Corresponding WQ_INT bit is set by HW whenever:
-                                                          - POW_WQ_INT_CNT*[IQ_CNT] >=
-                                                            POW_WQ_INT_THR*[IQ_THR] and the threshold
-                                                            interrupt is not disabled.
-                                                            IQ_DIS<*>==1 disables the interrupt.
-                                                            POW_WQ_INT_THR*[IQ_THR]==0 disables the int.
-                                                          - POW_WQ_INT_CNT*[DS_CNT] >=
-                                                            POW_WQ_INT_THR*[DS_THR] and the threshold
-                                                            interrupt is not disabled
-                                                            POW_WQ_INT_THR*[DS_THR]==0 disables the int.
-                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
-                                                            counter POW_WQ_INT_PC[PC]==0 and
-                                                            POW_WQ_INT_THR*[TC_EN]==1 and at least one of:
-                                                            - POW_WQ_INT_CNT*[IQ_CNT] > 0
-                                                            - POW_WQ_INT_CNT*[DS_CNT] > 0 */
-#else
-        uint64_t wq_int                  : 16;
-        uint64_t iq_dis                  : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_wq_int_s             cn30xx;
-    struct cvmx_pow_wq_int_s             cn31xx;
-    struct cvmx_pow_wq_int_s             cn38xx;
-    struct cvmx_pow_wq_int_s             cn38xxp2;
-    struct cvmx_pow_wq_int_s             cn50xx;
-    struct cvmx_pow_wq_int_s             cn52xx;
-    struct cvmx_pow_wq_int_s             cn52xxp1;
-    struct cvmx_pow_wq_int_s             cn56xx;
-    struct cvmx_pow_wq_int_s             cn56xxp1;
-    struct cvmx_pow_wq_int_s             cn58xx;
-    struct cvmx_pow_wq_int_s             cn58xxp1;
-} cvmx_pow_wq_int_t;
-
-
-/**
- * cvmx_pow_wq_int_cnt#
- *
- * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group)
- * 
- * Contains a read-only copy of the counts used to trigger work queue interrupts.  For more
- * information regarding this register, see the interrupt section.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wq_int_cntx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
-                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
-                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
-                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
-                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT_THR* is written by SW
-                                                          - TC_CNT==1 and periodic counter
-                                                            POW_WQ_INT_PC[PC]==0
-                                                         Otherwise, HW decrements TC_CNT whenever the
-                                                         periodic counter POW_WQ_INT_PC[PC]==0.
-                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
-        uint64_t ds_cnt                  : 12;      /**< De-schedule executable count for group X */
-        uint64_t iq_cnt                  : 12;      /**< Input queue executable count for group X */
-#else
-        uint64_t iq_cnt                  : 12;
-        uint64_t ds_cnt                  : 12;
-        uint64_t tc_cnt                  : 4;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } s;
-    struct cvmx_pow_wq_int_cntx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
-                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
-                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
-                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
-                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT_THR* is written by SW
-                                                          - TC_CNT==1 and periodic counter
-                                                            POW_WQ_INT_PC[PC]==0
-                                                         Otherwise, HW decrements TC_CNT whenever the
-                                                         periodic counter POW_WQ_INT_PC[PC]==0.
-                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
-        uint64_t reserved_19_23          : 5;
-        uint64_t ds_cnt                  : 7;       /**< De-schedule executable count for group X */
-        uint64_t reserved_7_11           : 5;
-        uint64_t iq_cnt                  : 7;       /**< Input queue executable count for group X */
-#else
-        uint64_t iq_cnt                  : 7;
-        uint64_t reserved_7_11           : 5;
-        uint64_t ds_cnt                  : 7;
-        uint64_t reserved_19_23          : 5;
-        uint64_t tc_cnt                  : 4;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn30xx;
-    struct cvmx_pow_wq_int_cntx_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
-                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
-                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
-                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
-                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT_THR* is written by SW
-                                                          - TC_CNT==1 and periodic counter
-                                                            POW_WQ_INT_PC[PC]==0
-                                                         Otherwise, HW decrements TC_CNT whenever the
-                                                         periodic counter POW_WQ_INT_PC[PC]==0.
-                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
-        uint64_t reserved_21_23          : 3;
-        uint64_t ds_cnt                  : 9;       /**< De-schedule executable count for group X */
-        uint64_t reserved_9_11           : 3;
-        uint64_t iq_cnt                  : 9;       /**< Input queue executable count for group X */
-#else
-        uint64_t iq_cnt                  : 9;
-        uint64_t reserved_9_11           : 3;
-        uint64_t ds_cnt                  : 9;
-        uint64_t reserved_21_23          : 3;
-        uint64_t tc_cnt                  : 4;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn31xx;
-    struct cvmx_pow_wq_int_cntx_s        cn38xx;
-    struct cvmx_pow_wq_int_cntx_s        cn38xxp2;
-    struct cvmx_pow_wq_int_cntx_cn31xx   cn50xx;
-    struct cvmx_pow_wq_int_cntx_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_28_63          : 36;
-        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
-                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
-                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
-                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
-                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
-                                                            with a 1 by SW
-                                                          - corresponding POW_WQ_INT_THR* is written by SW
-                                                          - TC_CNT==1 and periodic counter
-                                                            POW_WQ_INT_PC[PC]==0
-                                                         Otherwise, HW decrements TC_CNT whenever the
-                                                         periodic counter POW_WQ_INT_PC[PC]==0.
-                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
-        uint64_t reserved_22_23          : 2;
-        uint64_t ds_cnt                  : 10;      /**< De-schedule executable count for group X */
-        uint64_t reserved_10_11          : 2;
-        uint64_t iq_cnt                  : 10;      /**< Input queue executable count for group X */
-#else
-        uint64_t iq_cnt                  : 10;
-        uint64_t reserved_10_11          : 2;
-        uint64_t ds_cnt                  : 10;
-        uint64_t reserved_22_23          : 2;
-        uint64_t tc_cnt                  : 4;
-        uint64_t reserved_28_63          : 36;
-#endif
-    } cn52xx;
-    struct cvmx_pow_wq_int_cntx_cn52xx   cn52xxp1;
-    struct cvmx_pow_wq_int_cntx_s        cn56xx;
-    struct cvmx_pow_wq_int_cntx_s        cn56xxp1;
-    struct cvmx_pow_wq_int_cntx_s        cn58xx;
-    struct cvmx_pow_wq_int_cntx_s        cn58xxp1;
-} cvmx_pow_wq_int_cntx_t;
-
-
-/**
- * cvmx_pow_wq_int_pc
- *
- * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register
- * 
- * Contains the threshold value for the work queue interrupt periodic counter and also a read-only
- * copy of the periodic counter.  For more information regarding this register, see the interrupt
- * section.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wq_int_pc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_60_63          : 4;
-        uint64_t pc                      : 28;      /**< Work queue interrupt periodic counter */
-        uint64_t reserved_28_31          : 4;
-        uint64_t pc_thr                  : 20;      /**< Work queue interrupt periodic counter threshold */
-        uint64_t reserved_0_7            : 8;
-#else
-        uint64_t reserved_0_7            : 8;
-        uint64_t pc_thr                  : 20;
-        uint64_t reserved_28_31          : 4;
-        uint64_t pc                      : 28;
-        uint64_t reserved_60_63          : 4;
-#endif
-    } s;
-    struct cvmx_pow_wq_int_pc_s          cn30xx;
-    struct cvmx_pow_wq_int_pc_s          cn31xx;
-    struct cvmx_pow_wq_int_pc_s          cn38xx;
-    struct cvmx_pow_wq_int_pc_s          cn38xxp2;
-    struct cvmx_pow_wq_int_pc_s          cn50xx;
-    struct cvmx_pow_wq_int_pc_s          cn52xx;
-    struct cvmx_pow_wq_int_pc_s          cn52xxp1;
-    struct cvmx_pow_wq_int_pc_s          cn56xx;
-    struct cvmx_pow_wq_int_pc_s          cn56xxp1;
-    struct cvmx_pow_wq_int_pc_s          cn58xx;
-    struct cvmx_pow_wq_int_pc_s          cn58xxp1;
-} cvmx_pow_wq_int_pc_t;
-
-
-/**
- * cvmx_pow_wq_int_thr#
- *
- * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group)
- * 
- * Contains the thresholds for enabling and setting work queue interrupts.  For more information
- * regarding this register, see the interrupt section.
- * 
- * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are
- * therefore not available for incoming work queue entries.  Additionally, any PP that is not in the
- * NULL_NULL state consumes a buffer.  Thus in a 4 PP system, it is not advisable to set either
- * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504.  Doing so may prevent the interrupt from
- * ever triggering.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_wq_int_thrx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
-                                                         TC_EN must be zero when TC_THR==0 */
-        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
-                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
-        uint64_t reserved_23_23          : 1;
-        uint64_t ds_thr                  : 11;      /**< De-schedule count threshold for group X
-                                                         DS_THR==0 disables the threshold interrupt */
-        uint64_t reserved_11_11          : 1;
-        uint64_t iq_thr                  : 11;      /**< Input queue count threshold for group X
-                                                         IQ_THR==0 disables the threshold interrupt */
-#else
-        uint64_t iq_thr                  : 11;
-        uint64_t reserved_11_11          : 1;
-        uint64_t ds_thr                  : 11;
-        uint64_t reserved_23_23          : 1;
-        uint64_t tc_thr                  : 4;
-        uint64_t tc_en                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } s;
-    struct cvmx_pow_wq_int_thrx_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
-                                                         TC_EN must be zero when TC_THR==0 */
-        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
-                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
-        uint64_t reserved_18_23          : 6;
-        uint64_t ds_thr                  : 6;       /**< De-schedule count threshold for group X
-                                                         DS_THR==0 disables the threshold interrupt */
-        uint64_t reserved_6_11           : 6;
-        uint64_t iq_thr                  : 6;       /**< Input queue count threshold for group X
-                                                         IQ_THR==0 disables the threshold interrupt */
-#else
-        uint64_t iq_thr                  : 6;
-        uint64_t reserved_6_11           : 6;
-        uint64_t ds_thr                  : 6;
-        uint64_t reserved_18_23          : 6;
-        uint64_t tc_thr                  : 4;
-        uint64_t tc_en                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn30xx;
-    struct cvmx_pow_wq_int_thrx_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
-                                                         TC_EN must be zero when TC_THR==0 */
-        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
-                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
-        uint64_t reserved_20_23          : 4;
-        uint64_t ds_thr                  : 8;       /**< De-schedule count threshold for group X
-                                                         DS_THR==0 disables the threshold interrupt */
-        uint64_t reserved_8_11           : 4;
-        uint64_t iq_thr                  : 8;       /**< Input queue count threshold for group X
-                                                         IQ_THR==0 disables the threshold interrupt */
-#else
-        uint64_t iq_thr                  : 8;
-        uint64_t reserved_8_11           : 4;
-        uint64_t ds_thr                  : 8;
-        uint64_t reserved_20_23          : 4;
-        uint64_t tc_thr                  : 4;
-        uint64_t tc_en                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn31xx;
-    struct cvmx_pow_wq_int_thrx_s        cn38xx;
-    struct cvmx_pow_wq_int_thrx_s        cn38xxp2;
-    struct cvmx_pow_wq_int_thrx_cn31xx   cn50xx;
-    struct cvmx_pow_wq_int_thrx_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_29_63          : 35;
-        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
-                                                         TC_EN must be zero when TC_THR==0 */
-        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
-                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
-        uint64_t reserved_21_23          : 3;
-        uint64_t ds_thr                  : 9;       /**< De-schedule count threshold for group X
-                                                         DS_THR==0 disables the threshold interrupt */
-        uint64_t reserved_9_11           : 3;
-        uint64_t iq_thr                  : 9;       /**< Input queue count threshold for group X
-                                                         IQ_THR==0 disables the threshold interrupt */
-#else
-        uint64_t iq_thr                  : 9;
-        uint64_t reserved_9_11           : 3;
-        uint64_t ds_thr                  : 9;
-        uint64_t reserved_21_23          : 3;
-        uint64_t tc_thr                  : 4;
-        uint64_t tc_en                   : 1;
-        uint64_t reserved_29_63          : 35;
-#endif
-    } cn52xx;
-    struct cvmx_pow_wq_int_thrx_cn52xx   cn52xxp1;
-    struct cvmx_pow_wq_int_thrx_s        cn56xx;
-    struct cvmx_pow_wq_int_thrx_s        cn56xxp1;
-    struct cvmx_pow_wq_int_thrx_s        cn58xx;
-    struct cvmx_pow_wq_int_thrx_s        cn58xxp1;
-} cvmx_pow_wq_int_thrx_t;
-
-
-/**
- * cvmx_pow_ws_pc#
- *
- * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group)
- * 
- * Counts the number of work schedules for each group.  Write to clear.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_pow_ws_pcx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t ws_pc                   : 32;      /**< Work schedule performance counter for group X */
-#else
-        uint64_t ws_pc                   : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_pow_ws_pcx_s             cn30xx;
-    struct cvmx_pow_ws_pcx_s             cn31xx;
-    struct cvmx_pow_ws_pcx_s             cn38xx;
-    struct cvmx_pow_ws_pcx_s             cn38xxp2;
-    struct cvmx_pow_ws_pcx_s             cn50xx;
-    struct cvmx_pow_ws_pcx_s             cn52xx;
-    struct cvmx_pow_ws_pcx_s             cn52xxp1;
-    struct cvmx_pow_ws_pcx_s             cn56xx;
-    struct cvmx_pow_ws_pcx_s             cn56xxp1;
-    struct cvmx_pow_ws_pcx_s             cn58xx;
-    struct cvmx_pow_ws_pcx_s             cn58xxp1;
-} cvmx_pow_ws_pcx_t;
-
-
-/**
- * cvmx_rad_mem_debug0
- *
- * Notes:
- * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_mem_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t iword                   : 64;      /**< IWord */
-#else
-        uint64_t iword                   : 64;
-#endif
-    } s;
-    struct cvmx_rad_mem_debug0_s         cn52xx;
-    struct cvmx_rad_mem_debug0_s         cn52xxp1;
-    struct cvmx_rad_mem_debug0_s         cn56xx;
-    struct cvmx_rad_mem_debug0_s         cn56xxp1;
-} cvmx_rad_mem_debug0_t;
-
-
-/**
- * cvmx_rad_mem_debug1
- *
- * Notes:
- * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_mem_debug1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t p_dat                   : 64;      /**< P data */
-#else
-        uint64_t p_dat                   : 64;
-#endif
-    } s;
-    struct cvmx_rad_mem_debug1_s         cn52xx;
-    struct cvmx_rad_mem_debug1_s         cn52xxp1;
-    struct cvmx_rad_mem_debug1_s         cn56xx;
-    struct cvmx_rad_mem_debug1_s         cn56xxp1;
-} cvmx_rad_mem_debug1_t;
-
-
-/**
- * cvmx_rad_mem_debug2
- *
- * Notes:
- * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.  A read of any entry that has not been
- * previously written is illegal and will result in unpredictable CSR read data.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_mem_debug2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t q_dat                   : 64;      /**< Q data */
-#else
-        uint64_t q_dat                   : 64;
-#endif
-    } s;
-    struct cvmx_rad_mem_debug2_s         cn52xx;
-    struct cvmx_rad_mem_debug2_s         cn52xxp1;
-    struct cvmx_rad_mem_debug2_s         cn56xx;
-    struct cvmx_rad_mem_debug2_s         cn56xxp1;
-} cvmx_rad_mem_debug2_t;
-
-
-/**
- * cvmx_rad_reg_bist_result
- *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_bist_result_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t sta                     : 1;       /**< BiST result of the STA     memories */
-        uint64_t ncb_oub                 : 1;       /**< BiST result of the NCB_OUB memories */
-        uint64_t ncb_inb                 : 2;       /**< BiST result of the NCB_INB memories */
-        uint64_t dat                     : 2;       /**< BiST result of the DAT     memories */
-#else
-        uint64_t dat                     : 2;
-        uint64_t ncb_inb                 : 2;
-        uint64_t ncb_oub                 : 1;
-        uint64_t sta                     : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_rad_reg_bist_result_s    cn52xx;
-    struct cvmx_rad_reg_bist_result_s    cn52xxp1;
-    struct cvmx_rad_reg_bist_result_s    cn56xx;
-    struct cvmx_rad_reg_bist_result_s    cn56xxp1;
-} cvmx_rad_reg_bist_result_t;
-
-
-/**
- * cvmx_rad_reg_cmd_buf
- *
- * Notes:
- * Sets the command buffer parameters
- * The size of the command buffer segments is measured in uint64s.  The pool specifies 1 of 8 free
- * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
- * pointer each time that the command buffer segment is exhausted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_cmd_buf_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_58_63          : 6;
-        uint64_t dwb                     : 9;       /**< Number of DontWriteBacks */
-        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
-        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
-        uint64_t ptr                     : 33;      /**< Initial command buffer pointer[39:7] (128B-aligned) */
-#else
-        uint64_t ptr                     : 33;
-        uint64_t size                    : 13;
-        uint64_t pool                    : 3;
-        uint64_t dwb                     : 9;
-        uint64_t reserved_58_63          : 6;
-#endif
-    } s;
-    struct cvmx_rad_reg_cmd_buf_s        cn52xx;
-    struct cvmx_rad_reg_cmd_buf_s        cn52xxp1;
-    struct cvmx_rad_reg_cmd_buf_s        cn56xx;
-    struct cvmx_rad_reg_cmd_buf_s        cn56xxp1;
-} cvmx_rad_reg_cmd_buf_t;
-
-
-/**
- * cvmx_rad_reg_ctl
- *
- * Notes:
- * MAX_READ is a throttle to control NCB usage.  Values >8 are illegal.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t max_read                : 4;       /**< Maximum number of outstanding data read commands */
-        uint64_t store_le                : 1;       /**< Force STORE0 byte write address to little endian */
-        uint64_t reset                   : 1;       /**< Reset oneshot pulse (lasts for 4 cycles) */
-#else
-        uint64_t reset                   : 1;
-        uint64_t store_le                : 1;
-        uint64_t max_read                : 4;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_rad_reg_ctl_s            cn52xx;
-    struct cvmx_rad_reg_ctl_s            cn52xxp1;
-    struct cvmx_rad_reg_ctl_s            cn56xx;
-    struct cvmx_rad_reg_ctl_s            cn56xxp1;
-} cvmx_rad_reg_ctl_t;
-
-
-/**
- * cvmx_rad_reg_debug0
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_57_63          : 7;
-        uint64_t loop                    : 25;      /**< Loop offset */
-        uint64_t reserved_22_31          : 10;
-        uint64_t iridx                   : 6;       /**< IWords read index */
-        uint64_t reserved_14_15          : 2;
-        uint64_t iwidx                   : 6;       /**< IWords write index */
-        uint64_t owordqv                 : 1;       /**< Valid for OWORDQ */
-        uint64_t owordpv                 : 1;       /**< Valid for OWORDP */
-        uint64_t commit                  : 1;       /**< Waiting for write commit */
-        uint64_t state                   : 5;       /**< Main state */
-#else
-        uint64_t state                   : 5;
-        uint64_t commit                  : 1;
-        uint64_t owordpv                 : 1;
-        uint64_t owordqv                 : 1;
-        uint64_t iwidx                   : 6;
-        uint64_t reserved_14_15          : 2;
-        uint64_t iridx                   : 6;
-        uint64_t reserved_22_31          : 10;
-        uint64_t loop                    : 25;
-        uint64_t reserved_57_63          : 7;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug0_s         cn52xx;
-    struct cvmx_rad_reg_debug0_s         cn52xxp1;
-    struct cvmx_rad_reg_debug0_s         cn56xx;
-    struct cvmx_rad_reg_debug0_s         cn56xxp1;
-} cvmx_rad_reg_debug0_t;
-
-
-/**
- * cvmx_rad_reg_debug1
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cword                   : 64;      /**< CWord */
-#else
-        uint64_t cword                   : 64;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug1_s         cn52xx;
-    struct cvmx_rad_reg_debug1_s         cn52xxp1;
-    struct cvmx_rad_reg_debug1_s         cn56xx;
-    struct cvmx_rad_reg_debug1_s         cn56xxp1;
-} cvmx_rad_reg_debug1_t;
-
-
-/**
- * cvmx_rad_reg_debug10
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug10_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t flags                   : 8;       /**< OCTL flags */
-        uint64_t size                    : 16;      /**< OCTL size (bytes) */
-        uint64_t ptr                     : 40;      /**< OCTL pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t flags                   : 8;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug10_s        cn52xx;
-    struct cvmx_rad_reg_debug10_s        cn52xxp1;
-    struct cvmx_rad_reg_debug10_s        cn56xx;
-    struct cvmx_rad_reg_debug10_s        cn56xxp1;
-} cvmx_rad_reg_debug10_t;
-
-
-/**
- * cvmx_rad_reg_debug11
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug11_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t q                       : 1;       /**< OCTL q flag */
-        uint64_t p                       : 1;       /**< OCTL p flag */
-        uint64_t wc                      : 1;       /**< OCTL write commit flag */
-        uint64_t eod                     : 1;       /**< OCTL eod flag */
-        uint64_t sod                     : 1;       /**< OCTL sod flag */
-        uint64_t index                   : 8;       /**< OCTL index */
-#else
-        uint64_t index                   : 8;
-        uint64_t sod                     : 1;
-        uint64_t eod                     : 1;
-        uint64_t wc                      : 1;
-        uint64_t p                       : 1;
-        uint64_t q                       : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug11_s        cn52xx;
-    struct cvmx_rad_reg_debug11_s        cn52xxp1;
-    struct cvmx_rad_reg_debug11_s        cn56xx;
-    struct cvmx_rad_reg_debug11_s        cn56xxp1;
-} cvmx_rad_reg_debug11_t;
-
-
-/**
- * cvmx_rad_reg_debug12
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug12_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t asserts                 : 15;      /**< Various assertion checks */
-#else
-        uint64_t asserts                 : 15;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug12_s        cn52xx;
-    struct cvmx_rad_reg_debug12_s        cn52xxp1;
-    struct cvmx_rad_reg_debug12_s        cn56xx;
-    struct cvmx_rad_reg_debug12_s        cn56xxp1;
-} cvmx_rad_reg_debug12_t;
-
-
-/**
- * cvmx_rad_reg_debug2
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t owordp                  : 64;      /**< OWordP */
-#else
-        uint64_t owordp                  : 64;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug2_s         cn52xx;
-    struct cvmx_rad_reg_debug2_s         cn52xxp1;
-    struct cvmx_rad_reg_debug2_s         cn56xx;
-    struct cvmx_rad_reg_debug2_s         cn56xxp1;
-} cvmx_rad_reg_debug2_t;
-
-
-/**
- * cvmx_rad_reg_debug3
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t owordq                  : 64;      /**< OWordQ */
-#else
-        uint64_t owordq                  : 64;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug3_s         cn52xx;
-    struct cvmx_rad_reg_debug3_s         cn52xxp1;
-    struct cvmx_rad_reg_debug3_s         cn56xx;
-    struct cvmx_rad_reg_debug3_s         cn56xxp1;
-} cvmx_rad_reg_debug3_t;
-
-
-/**
- * cvmx_rad_reg_debug4
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t rword                   : 64;      /**< RWord */
-#else
-        uint64_t rword                   : 64;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug4_s         cn52xx;
-    struct cvmx_rad_reg_debug4_s         cn52xxp1;
-    struct cvmx_rad_reg_debug4_s         cn56xx;
-    struct cvmx_rad_reg_debug4_s         cn56xxp1;
-} cvmx_rad_reg_debug4_t;
-
-
-/**
- * cvmx_rad_reg_debug5
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_53_63          : 11;
-        uint64_t niropc7                 : 3;       /**< NCBI ropc (stage7 grant) */
-        uint64_t nirque7                 : 2;       /**< NCBI rque (stage7 grant) */
-        uint64_t nirval7                 : 5;       /**< NCBI rval (stage7 grant) */
-        uint64_t niropc6                 : 3;       /**< NCBI ropc (stage6 arb) */
-        uint64_t nirque6                 : 2;       /**< NCBI rque (stage6 arb) */
-        uint64_t nirarb6                 : 1;       /**< NCBI rarb (stage6 arb) */
-        uint64_t nirval6                 : 5;       /**< NCBI rval (stage6 arb) */
-        uint64_t niridx1                 : 4;       /**< NCBI ridx1 */
-        uint64_t niwidx1                 : 4;       /**< NCBI widx1 */
-        uint64_t niridx0                 : 4;       /**< NCBI ridx0 */
-        uint64_t niwidx0                 : 4;       /**< NCBI widx0 */
-        uint64_t wccreds                 : 2;       /**< WC credits */
-        uint64_t fpacreds                : 2;       /**< POW credits */
-        uint64_t reserved_10_11          : 2;
-        uint64_t powcreds                : 2;       /**< POW credits */
-        uint64_t n1creds                 : 4;       /**< NCBI1 credits */
-        uint64_t n0creds                 : 4;       /**< NCBI0 credits */
-#else
-        uint64_t n0creds                 : 4;
-        uint64_t n1creds                 : 4;
-        uint64_t powcreds                : 2;
-        uint64_t reserved_10_11          : 2;
-        uint64_t fpacreds                : 2;
-        uint64_t wccreds                 : 2;
-        uint64_t niwidx0                 : 4;
-        uint64_t niridx0                 : 4;
-        uint64_t niwidx1                 : 4;
-        uint64_t niridx1                 : 4;
-        uint64_t nirval6                 : 5;
-        uint64_t nirarb6                 : 1;
-        uint64_t nirque6                 : 2;
-        uint64_t niropc6                 : 3;
-        uint64_t nirval7                 : 5;
-        uint64_t nirque7                 : 2;
-        uint64_t niropc7                 : 3;
-        uint64_t reserved_53_63          : 11;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug5_s         cn52xx;
-    struct cvmx_rad_reg_debug5_s         cn52xxp1;
-    struct cvmx_rad_reg_debug5_s         cn56xx;
-    struct cvmx_rad_reg_debug5_s         cn56xxp1;
-} cvmx_rad_reg_debug5_t;
-
-
-/**
- * cvmx_rad_reg_debug6
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cnt                     : 8;       /**< CCTL count[7:0] (bytes) */
-        uint64_t size                    : 16;      /**< CCTL size (bytes) */
-        uint64_t ptr                     : 40;      /**< CCTL pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t cnt                     : 8;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug6_s         cn52xx;
-    struct cvmx_rad_reg_debug6_s         cn52xxp1;
-    struct cvmx_rad_reg_debug6_s         cn56xx;
-    struct cvmx_rad_reg_debug6_s         cn56xxp1;
-} cvmx_rad_reg_debug6_t;
-
-
-/**
- * cvmx_rad_reg_debug7
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t cnt                     : 15;      /**< CCTL count[22:8] (bytes) */
-#else
-        uint64_t cnt                     : 15;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug7_s         cn52xx;
-    struct cvmx_rad_reg_debug7_s         cn52xxp1;
-    struct cvmx_rad_reg_debug7_s         cn56xx;
-    struct cvmx_rad_reg_debug7_s         cn56xxp1;
-} cvmx_rad_reg_debug7_t;
-
-
-/**
- * cvmx_rad_reg_debug8
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug8_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t flags                   : 8;       /**< ICTL flags */
-        uint64_t size                    : 16;      /**< ICTL size (bytes) */
-        uint64_t ptr                     : 40;      /**< ICTL pointer */
-#else
-        uint64_t ptr                     : 40;
-        uint64_t size                    : 16;
-        uint64_t flags                   : 8;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug8_s         cn52xx;
-    struct cvmx_rad_reg_debug8_s         cn52xxp1;
-    struct cvmx_rad_reg_debug8_s         cn56xx;
-    struct cvmx_rad_reg_debug8_s         cn56xxp1;
-} cvmx_rad_reg_debug8_t;
-
-
-/**
- * cvmx_rad_reg_debug9
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_debug9_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t eod                     : 1;       /**< ICTL eod flag */
-        uint64_t ini                     : 1;       /**< ICTL init flag */
-        uint64_t q                       : 1;       /**< ICTL q enable */
-        uint64_t p                       : 1;       /**< ICTL p enable */
-        uint64_t mul                     : 8;       /**< ICTL multiplier */
-        uint64_t index                   : 8;       /**< ICTL index */
-#else
-        uint64_t index                   : 8;
-        uint64_t mul                     : 8;
-        uint64_t p                       : 1;
-        uint64_t q                       : 1;
-        uint64_t ini                     : 1;
-        uint64_t eod                     : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_rad_reg_debug9_s         cn52xx;
-    struct cvmx_rad_reg_debug9_s         cn52xxp1;
-    struct cvmx_rad_reg_debug9_s         cn56xx;
-    struct cvmx_rad_reg_debug9_s         cn56xxp1;
-} cvmx_rad_reg_debug9_t;
-
-
-/**
- * cvmx_rad_reg_error
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_error_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
-#else
-        uint64_t doorbell                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_rad_reg_error_s          cn52xx;
-    struct cvmx_rad_reg_error_s          cn52xxp1;
-    struct cvmx_rad_reg_error_s          cn56xx;
-    struct cvmx_rad_reg_error_s          cn56xxp1;
-} cvmx_rad_reg_error_t;
-
-
-/**
- * cvmx_rad_reg_int_mask
- *
- * Notes:
- * When a mask bit is set, the corresponding interrupt is enabled.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_int_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t doorbell                : 1;       /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
-#else
-        uint64_t doorbell                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_rad_reg_int_mask_s       cn52xx;
-    struct cvmx_rad_reg_int_mask_s       cn52xxp1;
-    struct cvmx_rad_reg_int_mask_s       cn56xx;
-    struct cvmx_rad_reg_int_mask_s       cn56xxp1;
-} cvmx_rad_reg_int_mask_t;
-
-
-/**
- * cvmx_rad_reg_polynomial
- *
- * Notes:
- * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_polynomial_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t coeffs                  : 8;       /**< coefficients of GF(2^8) irreducible polynomial */
-#else
-        uint64_t coeffs                  : 8;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_rad_reg_polynomial_s     cn52xx;
-    struct cvmx_rad_reg_polynomial_s     cn52xxp1;
-    struct cvmx_rad_reg_polynomial_s     cn56xx;
-    struct cvmx_rad_reg_polynomial_s     cn56xxp1;
-} cvmx_rad_reg_polynomial_t;
-
-
-/**
- * cvmx_rad_reg_read_idx
- *
- * Notes:
- * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
- * as memories.  The names of these CSRs begin with the prefix "RAD_MEM_".
- * IDX[15:0] is the read index.  INC[15:0] is an increment that is added to IDX[15:0] after any CSR read.
- * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
- * contents of a CSR memory can be read with consecutive CSR read commands.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rad_reg_read_idx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t inc                     : 16;      /**< Increment to add to current index for next index */
-        uint64_t index                   : 16;      /**< Index to use for next memory CSR read */
-#else
-        uint64_t index                   : 16;
-        uint64_t inc                     : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_rad_reg_read_idx_s       cn52xx;
-    struct cvmx_rad_reg_read_idx_s       cn52xxp1;
-    struct cvmx_rad_reg_read_idx_s       cn56xx;
-    struct cvmx_rad_reg_read_idx_s       cn56xxp1;
-} cvmx_rad_reg_read_idx_t;
-
-
-/**
- * cvmx_rnm_bist_status
- *
- * RNM_BIST_STATUS = RNM's BIST Status Register
- * 
- * The RNM's Memory Bist Status register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rnm_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t rrc                     : 1;       /**< Status of RRC block bist. */
-        uint64_t mem                     : 1;       /**< Status of MEM block bist. */
-#else
-        uint64_t mem                     : 1;
-        uint64_t rrc                     : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_rnm_bist_status_s        cn30xx;
-    struct cvmx_rnm_bist_status_s        cn31xx;
-    struct cvmx_rnm_bist_status_s        cn38xx;
-    struct cvmx_rnm_bist_status_s        cn38xxp2;
-    struct cvmx_rnm_bist_status_s        cn50xx;
-    struct cvmx_rnm_bist_status_s        cn52xx;
-    struct cvmx_rnm_bist_status_s        cn52xxp1;
-    struct cvmx_rnm_bist_status_s        cn56xx;
-    struct cvmx_rnm_bist_status_s        cn56xxp1;
-    struct cvmx_rnm_bist_status_s        cn58xx;
-    struct cvmx_rnm_bist_status_s        cn58xxp1;
-} cvmx_rnm_bist_status_t;
-
-
-/**
- * cvmx_rnm_ctl_status
- *
- * RNM_CTL_STATUS = RNM's Control/Status Register
- * 
- * The RNM's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_rnm_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t ent_sel                 : 4;       /**< ? */
-        uint64_t exp_ent                 : 1;       /**< Exported entropy enable for random number generator */
-        uint64_t rng_rst                 : 1;       /**< Reset RNG as core reset. */
-        uint64_t rnm_rst                 : 1;       /**< Reset the RNM as core reset except for register
-                                                         logic. */
-        uint64_t rng_en                  : 1;       /**< Enable the output of the RNG. */
-        uint64_t ent_en                  : 1;       /**< Entropy enable for random number generator. */
-#else
-        uint64_t ent_en                  : 1;
-        uint64_t rng_en                  : 1;
-        uint64_t rnm_rst                 : 1;
-        uint64_t rng_rst                 : 1;
-        uint64_t exp_ent                 : 1;
-        uint64_t ent_sel                 : 4;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_rnm_ctl_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t rng_rst                 : 1;       /**< Reset RNG as core reset. */
-        uint64_t rnm_rst                 : 1;       /**< Reset the RNM as core reset except for register
-                                                         logic. */
-        uint64_t rng_en                  : 1;       /**< Enable the output of the RNG. */
-        uint64_t ent_en                  : 1;       /**< Entropy enable for random number generator. */
-#else
-        uint64_t ent_en                  : 1;
-        uint64_t rng_en                  : 1;
-        uint64_t rnm_rst                 : 1;
-        uint64_t rng_rst                 : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } cn30xx;
-    struct cvmx_rnm_ctl_status_cn30xx    cn31xx;
-    struct cvmx_rnm_ctl_status_cn30xx    cn38xx;
-    struct cvmx_rnm_ctl_status_cn30xx    cn38xxp2;
-    struct cvmx_rnm_ctl_status_s         cn50xx;
-    struct cvmx_rnm_ctl_status_s         cn52xx;
-    struct cvmx_rnm_ctl_status_s         cn52xxp1;
-    struct cvmx_rnm_ctl_status_s         cn56xx;
-    struct cvmx_rnm_ctl_status_s         cn56xxp1;
-    struct cvmx_rnm_ctl_status_s         cn58xx;
-    struct cvmx_rnm_ctl_status_s         cn58xxp1;
-} cvmx_rnm_ctl_status_t;
-
-
-/**
- * cvmx_smi#_clk
- *
- * SMI_CLK = Clock Control Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_smix_clk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_25_63          : 39;
-        uint64_t mode                    : 1;       /**< IEEE operating mode
-                                                         0=Clause 22 complient
-                                                         1=Clause 45 complient */
-        uint64_t reserved_21_23          : 3;
-        uint64_t sample_hi               : 5;       /**< When to sample read data (extended bits) */
-        uint64_t sample_mode             : 1;       /**< Read Data sampling mode
-                                                         According to the 802.3 spec, on reads, the STA
-                                                         transitions MDC and the PHY drives MDIO with
-                                                         some delay relative to that edge.  This is edge1.
-                                                         The STA then samples MDIO on the next rising edge
-                                                         of MDC.  This is edge2. Octeon can sample the
-                                                         read data relative to either edge.
-                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
-                                                            relative to edge2
-                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
-                                                            relative to edge1 */
-        uint64_t reserved_14_14          : 1;
-        uint64_t clk_idle                : 1;       /**< Do not toggle MDC on idle cycles */
-        uint64_t preamble                : 1;       /**< Send PREAMBLE on SMI transacton */
-        uint64_t sample                  : 4;       /**< When to sample read data
-                                                         (number of eclks after the rising edge of mdc)
-                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
-                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
-        uint64_t phase                   : 8;       /**< MDC Clock Phase
-                                                         (number of eclks that make up an mdc phase)
-                                                         (PHASE > 2) */
-#else
-        uint64_t phase                   : 8;
-        uint64_t sample                  : 4;
-        uint64_t preamble                : 1;
-        uint64_t clk_idle                : 1;
-        uint64_t reserved_14_14          : 1;
-        uint64_t sample_mode             : 1;
-        uint64_t sample_hi               : 5;
-        uint64_t reserved_21_23          : 3;
-        uint64_t mode                    : 1;
-        uint64_t reserved_25_63          : 39;
-#endif
-    } s;
-    struct cvmx_smix_clk_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_21_63          : 43;
-        uint64_t sample_hi               : 5;       /**< When to sample read data (extended bits) */
-        uint64_t sample_mode             : 1;       /**< Read Data sampling mode
-                                                         According to the 802.3 spec, on reads, the STA
-                                                         transitions MDC and the PHY drives MDIO with
-                                                         some delay relative to that edge.  This is edge1.
-                                                         The STA then samples MDIO on the next rising edge
-                                                         of MDC.  This is edge2. Octeon can sample the
-                                                         read data relative to either edge.
-                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
-                                                            relative to edge2
-                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
-                                                            relative to edge1 */
-        uint64_t reserved_14_14          : 1;
-        uint64_t clk_idle                : 1;       /**< Do not toggle MDC on idle cycles */
-        uint64_t preamble                : 1;       /**< Send PREAMBLE on SMI transacton */
-        uint64_t sample                  : 4;       /**< When to sample read data
-                                                         (number of eclks after the rising edge of mdc)
-                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
-                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
-        uint64_t phase                   : 8;       /**< MDC Clock Phase
-                                                         (number of eclks that make up an mdc phase)
-                                                         (PHASE > 2) */
-#else
-        uint64_t phase                   : 8;
-        uint64_t sample                  : 4;
-        uint64_t preamble                : 1;
-        uint64_t clk_idle                : 1;
-        uint64_t reserved_14_14          : 1;
-        uint64_t sample_mode             : 1;
-        uint64_t sample_hi               : 5;
-        uint64_t reserved_21_63          : 43;
-#endif
-    } cn30xx;
-    struct cvmx_smix_clk_cn30xx          cn31xx;
-    struct cvmx_smix_clk_cn30xx          cn38xx;
-    struct cvmx_smix_clk_cn30xx          cn38xxp2;
-    struct cvmx_smix_clk_s               cn50xx;
-    struct cvmx_smix_clk_s               cn52xx;
-    struct cvmx_smix_clk_s               cn52xxp1;
-    struct cvmx_smix_clk_s               cn56xx;
-    struct cvmx_smix_clk_s               cn56xxp1;
-    struct cvmx_smix_clk_cn30xx          cn58xx;
-    struct cvmx_smix_clk_cn30xx          cn58xxp1;
-} cvmx_smix_clk_t;
-
-
-/**
- * cvmx_smi#_cmd
- *
- * SMI_CMD = Force a Read/Write command to the PHY
- *
- *
- * Notes:
- * Writes to this register will create SMI xactions.  Software will poll on (depending on the xaction type).
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_smix_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t phy_op                  : 2;       /**< PHY Opcode
-                                                         0=write
-                                                         1=read */
-        uint64_t reserved_13_15          : 3;
-        uint64_t phy_adr                 : 5;       /**< PHY Address */
-        uint64_t reserved_5_7            : 3;
-        uint64_t reg_adr                 : 5;       /**< PHY Register Offset */
-#else
-        uint64_t reg_adr                 : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t phy_adr                 : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t phy_op                  : 2;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_smix_cmd_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t phy_op                  : 1;       /**< PHY Opcode
-                                                         0=write
-                                                         1=read */
-        uint64_t reserved_13_15          : 3;
-        uint64_t phy_adr                 : 5;       /**< PHY Address */
-        uint64_t reserved_5_7            : 3;
-        uint64_t reg_adr                 : 5;       /**< PHY Register Offset */
-#else
-        uint64_t reg_adr                 : 5;
-        uint64_t reserved_5_7            : 3;
-        uint64_t phy_adr                 : 5;
-        uint64_t reserved_13_15          : 3;
-        uint64_t phy_op                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } cn30xx;
-    struct cvmx_smix_cmd_cn30xx          cn31xx;
-    struct cvmx_smix_cmd_cn30xx          cn38xx;
-    struct cvmx_smix_cmd_cn30xx          cn38xxp2;
-    struct cvmx_smix_cmd_s               cn50xx;
-    struct cvmx_smix_cmd_s               cn52xx;
-    struct cvmx_smix_cmd_s               cn52xxp1;
-    struct cvmx_smix_cmd_s               cn56xx;
-    struct cvmx_smix_cmd_s               cn56xxp1;
-    struct cvmx_smix_cmd_cn30xx          cn58xx;
-    struct cvmx_smix_cmd_cn30xx          cn58xxp1;
-} cvmx_smix_cmd_t;
-
-
-/**
- * cvmx_smi#_en
- *
- * SMI_EN = Enable the SMI interface
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_smix_en_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t en                      : 1;       /**< Interface enable
-                                                         0=SMI Interface is down / no transactions, no MDC
-                                                         1=SMI Interface is up */
-#else
-        uint64_t en                      : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_smix_en_s                cn30xx;
-    struct cvmx_smix_en_s                cn31xx;
-    struct cvmx_smix_en_s                cn38xx;
-    struct cvmx_smix_en_s                cn38xxp2;
-    struct cvmx_smix_en_s                cn50xx;
-    struct cvmx_smix_en_s                cn52xx;
-    struct cvmx_smix_en_s                cn52xxp1;
-    struct cvmx_smix_en_s                cn56xx;
-    struct cvmx_smix_en_s                cn56xxp1;
-    struct cvmx_smix_en_s                cn58xx;
-    struct cvmx_smix_en_s                cn58xxp1;
-} cvmx_smix_en_t;
-
-
-/**
- * cvmx_smi#_rd_dat
- *
- * SMI_RD_DAT = SMI Read Data
- *
- *
- * Notes:
- * VAL will assert when the read xaction completes.  A read to this register
- * will clear VAL.  PENDING indicates that an SMI RD transaction is in flight.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_smix_rd_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t pending                 : 1;       /**< Read Xaction Pending */
-        uint64_t val                     : 1;       /**< Read Data Valid */
-        uint64_t dat                     : 16;      /**< Read Data */
-#else
-        uint64_t dat                     : 16;
-        uint64_t val                     : 1;
-        uint64_t pending                 : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_smix_rd_dat_s            cn30xx;
-    struct cvmx_smix_rd_dat_s            cn31xx;
-    struct cvmx_smix_rd_dat_s            cn38xx;
-    struct cvmx_smix_rd_dat_s            cn38xxp2;
-    struct cvmx_smix_rd_dat_s            cn50xx;
-    struct cvmx_smix_rd_dat_s            cn52xx;
-    struct cvmx_smix_rd_dat_s            cn52xxp1;
-    struct cvmx_smix_rd_dat_s            cn56xx;
-    struct cvmx_smix_rd_dat_s            cn56xxp1;
-    struct cvmx_smix_rd_dat_s            cn58xx;
-    struct cvmx_smix_rd_dat_s            cn58xxp1;
-} cvmx_smix_rd_dat_t;
-
-
-/**
- * cvmx_smi#_wr_dat
- *
- * SMI_WR_DAT = SMI Write Data
- *
- *
- * Notes:
- * VAL will assert when the write xaction completes.  A read to this register
- * will clear VAL.  PENDING indicates that an SMI WR transaction is in flight.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_smix_wr_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t pending                 : 1;       /**< Write Xaction Pending */
-        uint64_t val                     : 1;       /**< Write Data Valid */
-        uint64_t dat                     : 16;      /**< Write Data */
-#else
-        uint64_t dat                     : 16;
-        uint64_t val                     : 1;
-        uint64_t pending                 : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } s;
-    struct cvmx_smix_wr_dat_s            cn30xx;
-    struct cvmx_smix_wr_dat_s            cn31xx;
-    struct cvmx_smix_wr_dat_s            cn38xx;
-    struct cvmx_smix_wr_dat_s            cn38xxp2;
-    struct cvmx_smix_wr_dat_s            cn50xx;
-    struct cvmx_smix_wr_dat_s            cn52xx;
-    struct cvmx_smix_wr_dat_s            cn52xxp1;
-    struct cvmx_smix_wr_dat_s            cn56xx;
-    struct cvmx_smix_wr_dat_s            cn56xxp1;
-    struct cvmx_smix_wr_dat_s            cn58xx;
-    struct cvmx_smix_wr_dat_s            cn58xxp1;
-} cvmx_smix_wr_dat_t;
-
-
-/**
- * cvmx_spx#_bckprs_cnt
- *
- * Notes:
- * The back pressure watcher counts the number of cycles in which the spi
- * receiver receives data once the TPA for a particular port has been
- * deasserted.  The desired port to watch can be selected with the
- * SPX_TPA_SEL[PRTSEL] field.
- * 
- * This register can be cleared by simply writting all 1's to it.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_bckprs_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Number of cycles when back-pressure is received */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_spxx_bckprs_cnt_s        cn38xx;
-    struct cvmx_spxx_bckprs_cnt_s        cn38xxp2;
-    struct cvmx_spxx_bckprs_cnt_s        cn58xx;
-    struct cvmx_spxx_bckprs_cnt_s        cn58xxp1;
-} cvmx_spxx_bckprs_cnt_t;
-
-
-/**
- * cvmx_spx#_bist_stat
- *
- * Notes:
- * Bist results encoding
- * - 0: good (or bist in progress/never run)
- * - 1: bad
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_bist_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t stat2                   : 1;       /**< Bist Results/No Repair (Tx calendar table)
-                                                         (spx.stx.cal.calendar) */
-        uint64_t stat1                   : 1;       /**< Bist Results/No Repair (Rx calendar table)
-                                                         (spx.srx.spi4.cal.calendar) */
-        uint64_t stat0                   : 1;       /**< Bist Results/No Repair (Spi4 receive datapath FIFO)
-                                                         (spx.srx.spi4.dat.dpr) */
-#else
-        uint64_t stat0                   : 1;
-        uint64_t stat1                   : 1;
-        uint64_t stat2                   : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_spxx_bist_stat_s         cn38xx;
-    struct cvmx_spxx_bist_stat_s         cn38xxp2;
-    struct cvmx_spxx_bist_stat_s         cn58xx;
-    struct cvmx_spxx_bist_stat_s         cn58xxp1;
-} cvmx_spxx_bist_stat_t;
-
-
-/**
- * cvmx_spx#_clk_ctl
- *
- * Notes:
- * * SRXDLCK
- *   When asserted, this bit locks the Spi4 receive DLLs.  This bit also
- *   acts as the Spi4 receiver reset and must be asserted before the
- *   training sequences are used to initialize the interface.  This bit
- *   only applies to the receiver interface.
- * 
- * * RCVTRN
- *   Once the SRXDLCK bit is asserted and the DLLs have locked and the
- *   system has been programmed, software should assert this bit in order
- *   to start looking for valid training sequence and synchronize the
- *   interface. This bit only applies to the receiver interface.
- * 
- * * DRPTRN
- *   The Spi4 receiver can either convert training packets into NOPs or
- *   drop them entirely.  Dropping ticks allows the interface to deskew
- *   periodically if the dclk and eclk ratios are close. This bit only
- *   applies to the receiver interface.
- * 
- * * SNDTRN
- *   When software sets this bit, it indicates that the Spi4 transmit
- *   interface has been setup and has seen the calendare status.  Once the
- *   transmitter begins sending training data, the receiving device is free
- *   to start traversing the calendar table to synch the link.
- * 
- * * STATRCV
- *   This bit determines which status clock edge to sample the status
- *   channel in Spi4 mode.  Since the status channel is in the opposite
- *   direction to the datapath, the STATRCV actually effects the
- *   transmitter/TX block.
- * 
- * * STATDRV
- *   This bit determines which status clock edge to drive the status
- *   channel in Spi4 mode.  Since the status channel is in the opposite
- *   direction to the datapath, the STATDRV actually effects the
- *   receiver/RX block.
- * 
- * * RUNBIST
- *   RUNBIST will beginning BIST/BISR in all the SPX compilied memories.
- *   These memories are...
- * 
- *       * spx.srx.spi4.dat.dpr        // FIFO Spi4 to IMX
- *       * spx.stx.cal.calendar        // Spi4 TX calendar table
- *       * spx.srx.spi4.cal.calendar   // Spi4 RX calendar table
- * 
- *   RUNBIST must never be asserted when the interface is enabled.
- *   Furthmore, setting RUNBIST at any other time is destructive and can
- *   cause data and configuration corruption.  The entire interface must be
- *   reconfigured when this bit is set.
- * 
- * * CLKDLY
- *   Static clock positioning mostly intended for use in quarter clocking
- *   schemes.  The delay window is not large enough for slow clock freq,
- *   therefore clock and data must be statically positioned with CSRs.  By
- *   changing the clock position relative to the data bits, we give the
- *   system a wider window.
- * 
- * * SEETRN
- *   In systems in which no training data is sent to N2 or N2 cannot
- *   correctly sample the training data, software may pulse this bit by
- *   writing a '1' followed by a '0' in order to correctly set the
- *   receivers state.  The receive data bus should be idle at this time
- *   (only NOPs on the bus).  If N2 cannot see at least on training
- *   sequence, the data bus will not send any data to the core.  The
- *   interface will hang.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_clk_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t seetrn                  : 1;       /**< Force the Spi4 receive into seeing a traing
-                                                         sequence */
-        uint64_t reserved_12_15          : 4;
-        uint64_t clkdly                  : 5;       /**< Set the spx__clkdly lines to this value to
-                                                         control the delay on the incoming dclk
-                                                         (spx__clkdly) */
-        uint64_t runbist                 : 1;       /**< Write this bit to begin BIST testing in SPX */
-        uint64_t statdrv                 : 1;       /**< Spi4 status channel drive mode
-                                                         - 1: Drive STAT on posedge of SCLK
-                                                         - 0: Drive STAT on negedge of SCLK */
-        uint64_t statrcv                 : 1;       /**< Spi4 status channel sample mode
-                                                         - 1: Sample STAT on posedge of SCLK
-                                                         - 0: Sample STAT on negedge of SCLK */
-        uint64_t sndtrn                  : 1;       /**< Start sending training patterns on the Spi4
-                                                         Tx Interface */
-        uint64_t drptrn                  : 1;       /**< Drop blocks of training packets */
-        uint64_t rcvtrn                  : 1;       /**< Write this bit once the DLL is locked to sync
-                                                         on the training seqeunce */
-        uint64_t srxdlck                 : 1;       /**< Write this bit to lock the Spi4 receive DLL */
-#else
-        uint64_t srxdlck                 : 1;
-        uint64_t rcvtrn                  : 1;
-        uint64_t drptrn                  : 1;
-        uint64_t sndtrn                  : 1;
-        uint64_t statrcv                 : 1;
-        uint64_t statdrv                 : 1;
-        uint64_t runbist                 : 1;
-        uint64_t clkdly                  : 5;
-        uint64_t reserved_12_15          : 4;
-        uint64_t seetrn                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_spxx_clk_ctl_s           cn38xx;
-    struct cvmx_spxx_clk_ctl_s           cn38xxp2;
-    struct cvmx_spxx_clk_ctl_s           cn58xx;
-    struct cvmx_spxx_clk_ctl_s           cn58xxp1;
-} cvmx_spxx_clk_ctl_t;
-
-
-/**
- * cvmx_spx#_clk_stat
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_clk_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_11_63          : 53;
-        uint64_t stxcal                  : 1;       /**< The transistion from Sync to Calendar on status
-                                                         channel */
-        uint64_t reserved_9_9            : 1;
-        uint64_t srxtrn                  : 1;       /**< Saw a good data training sequence */
-        uint64_t s4clk1                  : 1;       /**< Saw '1' on Spi4 transmit status forward clk input */
-        uint64_t s4clk0                  : 1;       /**< Saw '0' on Spi4 transmit status forward clk input */
-        uint64_t d4clk1                  : 1;       /**< Saw '1' on Spi4 receive data forward clk input */
-        uint64_t d4clk0                  : 1;       /**< Saw '0' on Spi4 receive data forward clk input */
-        uint64_t reserved_0_3            : 4;
-#else
-        uint64_t reserved_0_3            : 4;
-        uint64_t d4clk0                  : 1;
-        uint64_t d4clk1                  : 1;
-        uint64_t s4clk0                  : 1;
-        uint64_t s4clk1                  : 1;
-        uint64_t srxtrn                  : 1;
-        uint64_t reserved_9_9            : 1;
-        uint64_t stxcal                  : 1;
-        uint64_t reserved_11_63          : 53;
-#endif
-    } s;
-    struct cvmx_spxx_clk_stat_s          cn38xx;
-    struct cvmx_spxx_clk_stat_s          cn38xxp2;
-    struct cvmx_spxx_clk_stat_s          cn58xx;
-    struct cvmx_spxx_clk_stat_s          cn58xxp1;
-} cvmx_spxx_clk_stat_t;
-
-
-/**
- * cvmx_spx#_dbg_deskew_ctl
- *
- * Notes:
- * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
- * that Spec for more details.
- * 
- *   The basic idea is to allow software to disable the auto-deskew widgets
- *   and make any adjustments by hand.  These steps should only be taken
- *   once the RCVTRN bit is set and before any real traffic is sent on the
- *   Spi4 bus.  Great care should be taken when messing with these bits as
- *   improper programmings can cause catestrophic or intermitent problems.
- * 
- *   The params we have to test are the MUX tap selects and the XCV delay
- *   tap selects.
- * 
- *   For the muxes, we can set each tap to a random value and then read
- *   back the taps.  To write...
- * 
- *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
- *    SPXX_DBG_DESKEW_CTL[OFFSET]   = mux tap value (2-bits)
- *    SPXX_DBG_DESKEW_CTL[MUX]      = go bit
- * 
- *   Notice this can all happen with a single CSR write.  To read, first
- *   set the bit you to look at with the SPXX_DBG_DESKEW_CTL[BITSEL], then
- *   simply read SPXX_DBG_DESKEW_STATE[MUXSEL]...
- * 
- *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
- *    SPXX_DBG_DESKEW_STATE[MUXSEL] = 2-bit value
- * 
- *   For the xcv delay taps, the CSR controls increment and decrement the
- *   5-bit count value in the XCV.  This is a saturating counter, so it
- *   will not wrap when decrementing below zero or incrementing above 31.
- * 
- *   To write...
- * 
- *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
- *    SPXX_DBG_DESKEW_CTL[OFFSET]   = tap value increment or decrement amount (5-bits)
- *    SPXX_DBG_DESKEW_CTL[INC|DEC]  = go bit
- * 
- *   These values are copied in SPX, so that they can be read back by
- *   software by a similar mechanism to the MUX selects...
- * 
- *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
- *    SPXX_DBG_DESKEW_STATE[OFFSET] = 5-bit value
- * 
- *   In addition, there is a reset bit that sets all the state back to the
- *   default/starting value of 0x10.
- * 
- *    SPXX_DBG_DESKEW_CTL[CLRDLY]   = 1
- * 
- * SINGLE STEP TRAINING MODE (WILMA)
- *     Debug feature that will enable the user to single-step the debug
- *     logic to watch initial movement and trends by putting the training
- *     machine in single step mode.
- * 
- * * SPX*_DBG_DESKEW_CTL[SSTEP]
- *        This will put the training control logic into single step mode.  We
- *        will not deskew in this scenario and will require the TX device to
- *        send continuous training sequences.
- * 
- *        It is required that SRX*_COM_CTL[INF_EN] be clear so that suspect
- *        data does not flow into the chip.
- * 
- *        Deasserting SPX*_DBG_DESKEW_CTL[SSTEP] will attempt to deskew as per
- *        the normal definition.  Single step mode is for debug only.  Special
- *        care must be given to correctly deskew the interface if normal
- *        operation is desired.
- * 
- * * SPX*_DBG_DESKEW_CTL[SSTEP_GO]
- *        Each write of '1' to SSTEP_GO will go through a single training
- *        iteration and will perform...
- * 
- *        - DLL update, if SPX*_DBG_DESKEW_CTL[DLLDIS] is clear
- *        - coarse update, if SPX*_TRN4_CTL[MUX_EN] is set
- *        - single fine update, if SPX*_TRN4_CTL[MACRO_EN] is set and an edge
- *       was detected after walked +/- SPX*_TRN4_CTL[MAXDIST] taps.
- * 
- *        Writes to this register have no effect if the interface is not in
- *        SSTEP mode (SPX*_DBG_DESKEW_CTL[SSTEP]).
- * 
- *        The WILMA mode will be cleared at the final state transition, so
- *        that software can set SPX*_DBG_DESKEW_CTL[SSTEP] and
- *        SPX*_DBG_DESKEW_CTL[SSTEP_GO] before setting SPX*_CLK_CTL[RCVTRN]
- *        and the machine will go through the initial iteration and stop -
- *        waiting for another SPX*_DBG_DESKEW_CTL[SSTEP_GO] or an interface
- *        enable.
- * 
- * * SPX*_DBG_DESKEW_CTL[FALL8]
- *   Determines how many pattern matches are required during training
- *   operations to fallout of training and begin processing the normal data
- *   stream.  The default value is 10 pattern matches.  The pattern that is
- *   used is dependent on the SPX*_DBG_DESKEW_CTL[FALLNOP] CSR which
- *   determines between non-training packets (the default) and NOPs.
- * 
- * * SPX*_DBG_DESKEW_CTL[FALLNOP]
- *   Determines the pattern that is required during training operations to
- *   fallout of training and begin processing the normal data stream.  The
- *   default value is to match against non-training data.  Setting this
- *   bit, changes the behavior to watch for NOPs packet instead.
- * 
- *   This bit should not be changed dynamically while the link is
- *   operational.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_dbg_deskew_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_30_63          : 34;
-        uint64_t fallnop                 : 1;       /**< Training fallout on NOP matches instead of
-                                                         non-training matches.
-                                                         (spx_csr__spi4_fallout_nop) */
-        uint64_t fall8                   : 1;       /**< Training fallout at 8 pattern matches instead of 10
-                                                         (spx_csr__spi4_fallout_8_match) */
-        uint64_t reserved_26_27          : 2;
-        uint64_t sstep_go                : 1;       /**< Single Step Training Sequence
-                                                         (spx_csr__spi4_single_step_go) */
-        uint64_t sstep                   : 1;       /**< Single Step Training Mode
-                                                         (spx_csr__spi4_single_step_mode) */
-        uint64_t reserved_22_23          : 2;
-        uint64_t clrdly                  : 1;       /**< Resets the offset control in the XCV
-                                                         (spx_csr__spi4_dll_clr_dly) */
-        uint64_t dec                     : 1;       /**< Decrement the offset by OFFSET for the Spi4
-                                                         bit selected by BITSEL
-                                                         (spx_csr__spi4_dbg_trn_dec) */
-        uint64_t inc                     : 1;       /**< Increment the offset by OFFSET for the Spi4
-                                                         bit selected by BITSEL
-                                                         (spx_csr__spi4_dbg_trn_inc) */
-        uint64_t mux                     : 1;       /**< Set the mux select tap for the Spi4 bit
-                                                         selected by BITSEL
-                                                         (spx_csr__spi4_dbg_trn_mux) */
-        uint64_t offset                  : 5;       /**< Adds or subtracts (Based on INC or DEC) the
-                                                         offset to Spi4 bit BITSEL.
-                                                         (spx_csr__spi4_dbg_trn_offset) */
-        uint64_t bitsel                  : 5;       /**< Select the Spi4 CTL or DAT bit
-                                                         15-0 : Spi4 DAT[15:0]
-                                                         16   : Spi4 CTL
-                                                         - 31-17: Invalid
-                                                         (spx_csr__spi4_dbg_trn_bitsel) */
-        uint64_t offdly                  : 6;       /**< Set the spx__offset lines to this value when
-                                                         not in macro sequence
-                                                         (spx_csr__spi4_mac_offdly) */
-        uint64_t dllfrc                  : 1;       /**< Force the Spi4 RX DLL to update
-                                                         (spx_csr__spi4_dll_force) */
-        uint64_t dlldis                  : 1;       /**< Disable sending the update signal to the Spi4
-                                                         RX DLL when set
-                                                         (spx_csr__spi4_dll_trn_en) */
-#else
-        uint64_t dlldis                  : 1;
-        uint64_t dllfrc                  : 1;
-        uint64_t offdly                  : 6;
-        uint64_t bitsel                  : 5;
-        uint64_t offset                  : 5;
-        uint64_t mux                     : 1;
-        uint64_t inc                     : 1;
-        uint64_t dec                     : 1;
-        uint64_t clrdly                  : 1;
-        uint64_t reserved_22_23          : 2;
-        uint64_t sstep                   : 1;
-        uint64_t sstep_go                : 1;
-        uint64_t reserved_26_27          : 2;
-        uint64_t fall8                   : 1;
-        uint64_t fallnop                 : 1;
-        uint64_t reserved_30_63          : 34;
-#endif
-    } s;
-    struct cvmx_spxx_dbg_deskew_ctl_s    cn38xx;
-    struct cvmx_spxx_dbg_deskew_ctl_s    cn38xxp2;
-    struct cvmx_spxx_dbg_deskew_ctl_s    cn58xx;
-    struct cvmx_spxx_dbg_deskew_ctl_s    cn58xxp1;
-} cvmx_spxx_dbg_deskew_ctl_t;
-
-
-/**
- * cvmx_spx#_dbg_deskew_state
- *
- * Notes:
- * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
- * that Spec for more details.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_dbg_deskew_state_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t testres                 : 1;       /**< Training Test Mode Result
-                                                         (srx_spi4__test_mode_result) */
-        uint64_t unxterm                 : 1;       /**< Unexpected training terminiation
-                                                         (srx_spi4__top_unxexp_trn_term) */
-        uint64_t muxsel                  : 2;       /**< The mux select value of the bit selected by
-                                                         SPX_DBG_DESKEW_CTL[BITSEL]
-                                                         (srx_spi4__trn_mux_sel) */
-        uint64_t offset                  : 5;       /**< The counter value of the bit selected by
-                                                         SPX_DBG_DESKEW_CTL[BITSEL]
-                                                         (srx_spi4__xcv_tap_select) */
-#else
-        uint64_t offset                  : 5;
-        uint64_t muxsel                  : 2;
-        uint64_t unxterm                 : 1;
-        uint64_t testres                 : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_spxx_dbg_deskew_state_s  cn38xx;
-    struct cvmx_spxx_dbg_deskew_state_s  cn38xxp2;
-    struct cvmx_spxx_dbg_deskew_state_s  cn58xx;
-    struct cvmx_spxx_dbg_deskew_state_s  cn58xxp1;
-} cvmx_spxx_dbg_deskew_state_t;
-
-
-/**
- * cvmx_spx#_drv_ctl
- *
- * Notes:
- * These bits all come from Duke - he will provide documentation and
- * explanation.  I'll just butcher it.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_drv_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_0_63           : 64;
-#else
-        uint64_t reserved_0_63           : 64;
-#endif
-    } s;
-    struct cvmx_spxx_drv_ctl_cn38xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t stx4ncmp                : 4;       /**< Duke (spx__spi4_tx_nctl_comp) */
-        uint64_t stx4pcmp                : 4;       /**< Duke (spx__spi4_tx_pctl_comp) */
-        uint64_t srx4cmp                 : 8;       /**< Duke (spx__spi4_rx_rctl_comp) */
-#else
-        uint64_t srx4cmp                 : 8;
-        uint64_t stx4pcmp                : 4;
-        uint64_t stx4ncmp                : 4;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn38xx;
-    struct cvmx_spxx_drv_ctl_cn38xx      cn38xxp2;
-    struct cvmx_spxx_drv_ctl_cn58xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t stx4ncmp                : 4;       /**< Duke (spx__spi4_tx_nctl_comp) */
-        uint64_t stx4pcmp                : 4;       /**< Duke (spx__spi4_tx_pctl_comp) */
-        uint64_t reserved_10_15          : 6;
-        uint64_t srx4cmp                 : 10;      /**< Duke (spx__spi4_rx_rctl_comp) */
-#else
-        uint64_t srx4cmp                 : 10;
-        uint64_t reserved_10_15          : 6;
-        uint64_t stx4pcmp                : 4;
-        uint64_t stx4ncmp                : 4;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } cn58xx;
-    struct cvmx_spxx_drv_ctl_cn58xx      cn58xxp1;
-} cvmx_spxx_drv_ctl_t;
-
-
-/**
- * cvmx_spx#_err_ctl
- *
- * SPX_ERR_CTL - Spi error control register
- *
- *
- * Notes:
- * * DIPPAY, DIPCLS, PRTNXA
- * These bits control whether or not the packet's ERR bit is set when any of
- * the these error is detected.  If the corresponding error's bit is clear,
- * the packet ERR will be set.  If the error bit is set, the SPX will simply
- * pass through the ERR bit without modifying it in anyway - the error bit
- * may or may not have been set by the transmitter device.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_err_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t prtnxa                  : 1;       /**< Spi4 - set the ERR bit on packets in which the
-                                                         port is out-of-range */
-        uint64_t dipcls                  : 1;       /**< Spi4 DIPERR on closing control words cause the
-                                                         ERR bit to be set */
-        uint64_t dippay                  : 1;       /**< Spi4 DIPERR on payload control words cause the
-                                                         ERR bit to be set */
-        uint64_t reserved_4_5            : 2;
-        uint64_t errcnt                  : 4;       /**< Number of Dip4 errors before bringing down the
-                                                         interface */
-#else
-        uint64_t errcnt                  : 4;
-        uint64_t reserved_4_5            : 2;
-        uint64_t dippay                  : 1;
-        uint64_t dipcls                  : 1;
-        uint64_t prtnxa                  : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_spxx_err_ctl_s           cn38xx;
-    struct cvmx_spxx_err_ctl_s           cn38xxp2;
-    struct cvmx_spxx_err_ctl_s           cn58xx;
-    struct cvmx_spxx_err_ctl_s           cn58xxp1;
-} cvmx_spxx_err_ctl_t;
-
-
-/**
- * cvmx_spx#_int_dat
- *
- * SPX_INT_DAT - Interrupt Data Register
- *
- *
- * Notes:
- * Note: The SPX_INT_DAT[MUL] bit is set when multiple errors have been
- * detected that would set any of the data fields: PRT, RSVOP, and CALBNK.
- * 
- * The following errors will cause MUL to assert for PRT conflicts.
- * - ABNORM
- * - APERR
- * - DPERR
- * 
- * The following errors will cause MUL to assert for RSVOP conflicts.
- * - RSVERR
- * 
- * The following errors will cause MUL to assert for CALBNK conflicts.
- * - CALERR
- * 
- * The following errors will cause MUL to assert if multiple interrupts are
- * asserted.
- * - TPAOVR
- * 
- * The MUL bit will be cleared once all outstanding errors have been
- * cleared by software (not just MUL errors - all errors).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_int_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t mul                     : 1;       /**< Multiple errors have occured */
-        uint64_t reserved_14_30          : 17;
-        uint64_t calbnk                  : 2;       /**< Spi4 Calendar table parity error bank */
-        uint64_t rsvop                   : 4;       /**< Spi4 reserved control word */
-        uint64_t prt                     : 8;       /**< Port associated with error */
-#else
-        uint64_t prt                     : 8;
-        uint64_t rsvop                   : 4;
-        uint64_t calbnk                  : 2;
-        uint64_t reserved_14_30          : 17;
-        uint64_t mul                     : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_spxx_int_dat_s           cn38xx;
-    struct cvmx_spxx_int_dat_s           cn38xxp2;
-    struct cvmx_spxx_int_dat_s           cn58xx;
-    struct cvmx_spxx_int_dat_s           cn58xxp1;
-} cvmx_spxx_int_dat_t;
-
-
-/**
- * cvmx_spx#_int_msk
- *
- * SPX_INT_MSK - Interrupt Mask Register
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_int_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
-        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
-                                                         SPX_ERR_CTL[ERRCNT] */
-        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
-        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
-        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
-        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
-        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
-        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow (Spi3 or Spi4) */
-        uint64_t reserved_2_3            : 2;
-        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
-        uint64_t prtnxa                  : 1;       /**< Port out of range */
-#else
-        uint64_t prtnxa                  : 1;
-        uint64_t abnorm                  : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t spiovr                  : 1;
-        uint64_t clserr                  : 1;
-        uint64_t drwnng                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t tpaovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t syncerr                 : 1;
-        uint64_t calerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_spxx_int_msk_s           cn38xx;
-    struct cvmx_spxx_int_msk_s           cn38xxp2;
-    struct cvmx_spxx_int_msk_s           cn58xx;
-    struct cvmx_spxx_int_msk_s           cn58xxp1;
-} cvmx_spxx_int_msk_t;
-
-
-/**
- * cvmx_spx#_int_reg
- *
- * SPX_INT_REG - Interrupt Register
- *
- *
- * Notes:
- * * PRTNXA
- *   This error indicates that the port on the Spi bus was not a valid port
- *   for the system.  Spi4 accesses occur on payload control bit-times. The
- *   SRX can be configured with the exact number of ports available (by
- *   SRX_COM_CTL[PRTS] register).  Any Spi access to anthing outside the range
- *   of 0 .. (SRX_COM_CTL[PRTS] - 1) is considered an error.  The offending
- *   port is logged in SPX_INT_DAT[PRT] if there are no pending interrupts in
- *   SPX_INT_REG that require SPX_INT_DAT[PRT].
- * 
- *   SRX will not drop the packet with the bogus port address.  Instead, the
- *   port will be mapped into the supported port range.  The remapped address
- *   in simply...
- * 
- *            Address = [ interfaceId, ADR[3:0] ]
- * 
- *   If the SPX detects that a PRTNXA error has occured, the packet will
- *   have its ERR bit set (or'ed in with the ERR bit from the transmitter)
- *   if the SPX_ERR_CTL[PRTNXA] bit is clear.
- * 
- *   In Spi4 mode, SPX will generate an interrupt for every 8B data burst
- *   associated with the invalid address.  The SPX_INT_DAT[MUL] bit will never
- *   be set.
- * 
- * * ABNORM
- *   This bit simply indicates that a given packet had abnormal terminiation.
- *   In Spi4 mode, this means that packet completed with an EOPS[1:0] code of
- *   2'b01.  This error can also be thought of as the application specific
- *   error (as mentioned in the Spi4 spec).  The offending port is logged in
- *   SPX_INT_DAT[PRT] if there are no pending interrupts in SPX_INT_REG that
- *   require SPX_INT_DAT[PRT].
- * 
- *   The ABNORM error is only raised when the ERR bit that comes from the
- *   Spi interface is set.  It will never assert if any internal condition
- *   causes the ERR bit to assert (e.g. PRTNXA or DPERR).
- * 
- * * SPIOVR
- *   This error indicates that the FIFOs that manage the async crossing from
- *   the Spi clocks to the core clock domains have overflowed.  This is a
- *   fatal error and can cause much data/control corruption since ticks will
- *   be dropped and reordered.  This is purely a function of clock ratios and
- *   correct system ratios should make this an impossible condition.
- * 
- * * CLSERR
- *   This is a Spi4 error that indicates that a given data transfer burst
- *   that did not terminate with an EOP, did not end with the 16B alignment
- *   as per the Spi4 spec.  The offending port cannot be logged since the
- *   block does not know the streamm terminated until the port switches.
- *   At that time, that packet has already been pushed down the pipe.
- * 
- *   The CLSERR bit does not actually check the Spi4 burst - just how data
- *   is accumulated for the downstream logic.  Bursts that are separted by
- *   idles or training will still be merged into accumulated transfers and
- *   will not fire the CLSERR condition.  The checker is really checking
- *   non-8B aligned, non-EOP data ticks that are sent downstream.  These
- *   ticks are what will really mess up the core.
- * 
- *   This is an expensive fix, so we'll probably let it ride.  We never
- *   claim to check Spi4 protocol anyway.
- * 
- * * DRWNNG
- *   This error indicates that the Spi4 FIFO that services the GMX has
- *   overflowed.  Like the SPIOVR error condition, correct system ratios
- *   should make this an impossible condition.
- * 
- * * RSVERR
- *   This Spi4 error indicates that the Spi4 receiver has seen a reserve
- *   control packet.  A reserve control packet is an invalid combiniation
- *   of bits on DAT[15:12].  Basically this is DAT[15] == 1'b0 and DAT[12]
- *   == 1'b1 (an SOP without a payload command).  The RSVERR indicates an
- *   error has occured and SPX_INT_DAT[RSVOP] holds the first reserved
- *   opcode and will be set if there are no pending interrupts in
- *   SPX_INT_REG that require SPX_INT_DAT[RSVOP].
- * 
- * * TPAOVR
- *   This bit indicates that the TPA Watcher has flagged an event.  See the
- *   TPA Watcher for a more detailed discussion.
- * 
- * * DIPERR
- *   This bit indicates that the Spi4 receiver has encountered a DIP4
- *   miscompare on the datapath.  A DIPERR can occur in an IDLE or a
- *   control word that frames a data burst.  If the DIPERR occurs on a
- *   framing word there are three cases.
- * 
- *   1) DIPERR occurs at the end of a data burst.  The previous packet is
- *      marked with the ERR bit to be processed later if
- *      SPX_ERR_CTL[DIPCLS] is clear.
- *   2) DIPERR occurs on a payload word.  The subsequent packet is marked
- *      with the ERR bit to be processed later if SPX_ERR_CTL[DIPPAY] is
- *      clear.
- *   3) DIPERR occurs on a control word that closes on packet and is a
- *      payload for another packet.  In this case, both packets will have
- *      their ERR bit marked depending on the respective values of
- *      SPX_ERR_CTL[DIPCLS] and SPX_ERR_CTL[DIPPAY] as discussed above.
- * 
- * * SYNCERR
- *   This bit indicates that the Spi4 receiver has encountered
- *   SPX_ERR_CTL[ERRCNT] consecutive Spi4 DIP4 errors and the interface
- *   should be synched.
- * 
- * * CALERR
- *   This bit indicates that the Spi4 calendar table encountered a parity
- *   error.  This error bit is associated with the calendar table on the RX
- *   interface - the interface that receives the Spi databus.  Parity errors
- *   can occur during normal operation when the calendar table is constantly
- *   being read for the port information, or during initialization time, when
- *   the user has access.  Since the calendar table is split into two banks,
- *   SPX_INT_DAT[CALBNK] indicates which banks have taken a parity error.
- *   CALBNK[1] indicates the error occured in the upper bank, while CALBNK[0]
- *   indicates that the error occured in the lower bank.  SPX_INT_DAT[CALBNK]
- *   will be set if there are no pending interrupts in SPX_INT_REG that
- *   require SPX_INT_DAT[CALBNK].
- * 
- * * SPF
- *   This bit indicates that a Spi fatal error has occurred.  A fatal error
- *   is defined as any error condition for which the corresponding
- *   SPX_INT_SYNC bit is set.  Therefore, conservative systems can halt the
- *   interface on any error condition although this is not strictly
- *   necessary.  Some error are much more fatal in nature than others.
- * 
- *   PRTNXA, SPIOVR, CLSERR, DRWNNG, DIPERR, CALERR, and SYNCERR are examples
- *   of fatal error for different reasons - usually because multiple port
- *   streams could be effected.  ABNORM, RSVERR, and TPAOVR are conditions
- *   that are contained to a single packet which allows the interface to drop
- *   a single packet and remain up and stable.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t spf                     : 1;       /**< Spi interface down */
-        uint64_t reserved_12_30          : 19;
-        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
-        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
-                                                         SPX_ERR_CTL[ERRCNT] */
-        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
-        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
-        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
-        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
-        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
-        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow */
-        uint64_t reserved_2_3            : 2;
-        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
-        uint64_t prtnxa                  : 1;       /**< Port out of range */
-#else
-        uint64_t prtnxa                  : 1;
-        uint64_t abnorm                  : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t spiovr                  : 1;
-        uint64_t clserr                  : 1;
-        uint64_t drwnng                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t tpaovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t syncerr                 : 1;
-        uint64_t calerr                  : 1;
-        uint64_t reserved_12_30          : 19;
-        uint64_t spf                     : 1;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_spxx_int_reg_s           cn38xx;
-    struct cvmx_spxx_int_reg_s           cn38xxp2;
-    struct cvmx_spxx_int_reg_s           cn58xx;
-    struct cvmx_spxx_int_reg_s           cn58xxp1;
-} cvmx_spxx_int_reg_t;
-
-
-/**
- * cvmx_spx#_int_sync
- *
- * SPX_INT_SYNC - Interrupt Sync Register
- *
- *
- * Notes:
- * This mask set indicates which exception condition should cause the
- * SPX_INT_REG[SPF] bit to assert
- * 
- * It is recommended that software set the PRTNXA, SPIOVR, CLSERR, DRWNNG,
- * DIPERR, CALERR, and SYNCERR errors as synchronization events.  Software is
- * free to synchronize the bus on other conditions, but this is the minimum
- * recommended set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_int_sync_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_12_63          : 52;
-        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
-        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
-                                                         SPX_ERR_CTL[ERRCNT] */
-        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
-        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
-        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
-        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
-        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
-        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow (Spi3 or Spi4) */
-        uint64_t reserved_2_3            : 2;
-        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
-        uint64_t prtnxa                  : 1;       /**< Port out of range */
-#else
-        uint64_t prtnxa                  : 1;
-        uint64_t abnorm                  : 1;
-        uint64_t reserved_2_3            : 2;
-        uint64_t spiovr                  : 1;
-        uint64_t clserr                  : 1;
-        uint64_t drwnng                  : 1;
-        uint64_t rsverr                  : 1;
-        uint64_t tpaovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t syncerr                 : 1;
-        uint64_t calerr                  : 1;
-        uint64_t reserved_12_63          : 52;
-#endif
-    } s;
-    struct cvmx_spxx_int_sync_s          cn38xx;
-    struct cvmx_spxx_int_sync_s          cn38xxp2;
-    struct cvmx_spxx_int_sync_s          cn58xx;
-    struct cvmx_spxx_int_sync_s          cn58xxp1;
-} cvmx_spxx_int_sync_t;
-
-
-/**
- * cvmx_spx#_tpa_acc
- *
- * SPX_TPA_ACC - TPA watcher byte accumulator
- *
- *
- * Notes:
- * This field allows the user to access the TPA watcher accumulator counter.
- * This register reflects the number of bytes sent to IMX once the port
- * specified by SPX_TPA_SEL[PRTSEL] has lost its TPA.  The SPX_INT_REG[TPAOVR]
- * bit is asserted when CNT >= SPX_TPA_MAX[MAX].  The CNT will continue to
- * increment until the TPA for the port is asserted.  At that point the CNT
- * value is frozen until software clears the interrupt bit.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_tpa_acc_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< TPA watcher accumulate count */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_spxx_tpa_acc_s           cn38xx;
-    struct cvmx_spxx_tpa_acc_s           cn38xxp2;
-    struct cvmx_spxx_tpa_acc_s           cn58xx;
-    struct cvmx_spxx_tpa_acc_s           cn58xxp1;
-} cvmx_spxx_tpa_acc_t;
-
-
-/**
- * cvmx_spx#_tpa_max
- *
- * SPX_TPA_MAX - TPA watcher assertion threshold
- *
- *
- * Notes:
- * The TPA watcher has the ability to notify the system with an interrupt when
- * too much data has been received on loss of TPA.  The user sets the
- * SPX_TPA_MAX[MAX] register and when the watcher has accumulated that many
- * ticks, then the interrupt is conditionally raised (based on interrupt mask
- * bits).  This feature will be disabled if the programmed count is zero.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_tpa_max_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t max                     : 32;      /**< TPA watcher TPA threshold */
-#else
-        uint64_t max                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_spxx_tpa_max_s           cn38xx;
-    struct cvmx_spxx_tpa_max_s           cn38xxp2;
-    struct cvmx_spxx_tpa_max_s           cn58xx;
-    struct cvmx_spxx_tpa_max_s           cn58xxp1;
-} cvmx_spxx_tpa_max_t;
-
-
-/**
- * cvmx_spx#_tpa_sel
- *
- * SPX_TPA_SEL - TPA watcher port selector
- *
- *
- * Notes:
- * The TPA Watcher is primarily a debug vehicle used to help initial bringup
- * of a system.  The TPA watcher counts bytes that roll in from the Spi
- * interface.  The user programs the Spi port to watch using
- * SPX_TPA_SEL[PRTSEL].  Once the TPA is deasserted for that port, the watcher
- * begins to count the data ticks that have been delivered to the inbound
- * datapath (and eventually to the IOB).  The result is that we can derive
- * turn-around times of the other device by watching how much data was sent
- * after a loss of TPA through the SPX_TPA_ACC[CNT] register.  An optional
- * interrupt may be raised as well.  See SPX_TPA_MAX for further information.
- * 
- * TPA's can be deasserted for a number of reasons...
- * 
- * 1) IPD indicates backpressure
- * 2) The GMX inbound FIFO is filling up and should BP
- * 3) User has out an override on the TPA wires
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_tpa_sel_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t prtsel                  : 4;       /**< TPA watcher port select */
-#else
-        uint64_t prtsel                  : 4;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_spxx_tpa_sel_s           cn38xx;
-    struct cvmx_spxx_tpa_sel_s           cn38xxp2;
-    struct cvmx_spxx_tpa_sel_s           cn58xx;
-    struct cvmx_spxx_tpa_sel_s           cn58xxp1;
-} cvmx_spxx_tpa_sel_t;
-
-
-/**
- * cvmx_spx#_trn4_ctl
- *
- * Notes:
- * These bits are controls for the Spi4 RX bit deskew logic.  See that Spec
- * for further details.
- * 
- * * BOOT_BIT
- *   On the initial training synchronization sequence, the hardware has the
- *   BOOT_BIT set which means that it will continueously perform macro
- *   operations.  Once the BOOT_BIT is cleared, the macro machine will finish
- *   the macro operation is working on and then return to the idle state.
- *   Subsequent training sequences will only go through a single macro
- *   operation in order to do slight deskews.
- * 
- * * JITTER
- *   Minimum value is 1.  This parameter must be set for Spi4 mode using
- *   auto-bit deskew.  Regardless of the original intent, this field must be
- *   set non-zero for deskew to function correctly.
- * 
- *   The thought is the JITTER range is no longer required since the macro
- *   machine was enhanced to understand about edge direction.  Originally
- *   these bits were intended to compensate for clock jitter.
- * 
- *   dly:    this is the intrinsic delay of each delay element
- *              tap currently, it is 70ps-110ps.
- *   jitter: amount of jitter we expect in the system (~200ps)
- *   j:      number of taps to account for jitter
- * 
- *   j = ((jitter / dly) + 1)
- * 
- * * TRNTEST
- *   This mode is used to test systems to make sure that the bit deskew
- *   parameters have been correctly setup.  After configuration, software can
- *   set the TRNTEST mode bit.  This should be done before SRX_COM_CTL[ST_EN]
- *   is set such that we can be sure that the TX device is simply sending
- *   continuous training patterns.
- * 
- *   The test mode samples every incoming bit-time and makes sure that it is
- *   either a training control or a training data packet.  If any other data
- *   is observed, then SPX_DBG_DESKEW_STATE[TESTRES] will assert signaling a
- *   test failure.
- * 
- *   Software must clear TRNTEST before training is terminated.
- * 
- * * Example Spi4 RX init flow...
- * 
- * 1) set the CLKDLY lines (SPXX_CLK_CTL[CLKDLY])
- *    - these bits must be set before the DLL can successfully lock
- * 
- * 2) set the SRXDLCK (SPXX_CLK_CTL[SRXDLCK])
- *    - this is the DLL lock bit which also acts as a block reset
- * 
- * 3) wait for the DLLs lock
- * 
- * 4) set any desired fields in SPXX_DBG_DESKEW_CTL
- *    - This register has only one field that most users will care about.
- *      When set, DLLDIS will disable sending update pulses to the Spi4 RX
- *      DLLs.  This pulse allows the DLL to adjust to clock variations over
- *      time.  In general, it is desired behavior.
- * 
- * 5) set fields in SPXX_TRN4_CTL
- *    - These fields deal with the MUX training sequence
- *      * MUX_EN
- *        This is the enable bit for the mux select.  The MUX select will
- *        run in the training sequence between the DLL and the Macro
- *        sequence when enabled.  Once the MUX selects are selected, the
- *        entire macro sequence must be rerun.  The expectation is that
- *        this is only run at boot time and this is bit cleared at/around
- *        step \#8.
- *    - These fields deal with the Macro training sequence
- *      * MACRO_EN
- *        This is the enable bit for the macro sequence.  Macro sequences
- *        will run after the DLL and MUX training sequences.  Each macro
- *        sequence can move the offset by one value.
- *      * MAXDIST
- *        This is how far we will search for an edge.  Example...
- * 
- *           dly:    this is the intrinsic delay of each delay element
- *                   tap currently, it is 70ps-110ps.
- *           U:      bit time period in time units.
- * 
- *           MAXDIST = MIN(16, ((bit_time / 2) / dly)
- * 
- *           Each MAXDIST iteration consists of an edge detect in the early
- *           and late (+/-) directions in an attempt to center the data.  This
- *           requires two training transistions, the control/data and
- *           data/control transistions which comprise a training sequence.
- *           Therefore, the number of training sequences required for a single
- *           macro operation is simply MAXDIST.
- * 
- * 6) set the RCVTRN go bit (SPXX_CLK_CTL[RCVTRN])
- *    - this bit synchs on the first valid complete training cycle and
- *      starts to process the training packets
- * 
- * 6b) This is where software could manually set the controls as opposed to
- *     letting the hardware do it.  See the SPXX_DBG_DESKEW_CTL register
- *        description for more detail.
- * 
- * 7) the TX device must continue to send training packets for the initial
- *    time period.
- *    - this can be determined by...
- * 
- *      DLL: one training sequence for the DLL adjustment (regardless of enable/disable)
- *      MUX: one training sequence for the Flop MUX taps (regardless of enable/disable)
- *      INIT_SEQUENCES: max number of taps that we must move
- * 
- *         INIT_SEQUENCES = MIN(16, ((bit_time / 2) / dly))
- * 
- *         INIT_TRN = DLL + MUX + ROUNDUP((INIT_SEQUENCES * (MAXDIST + 2)))
- * 
- * 
- *    - software can either wait a fixed amount of time based on the clock
- *      frequencies or poll the SPXX_CLK_STAT[SRXTRN] register.  Each
- *      assertion of SRXTRN means that at least one training sequence has
- *      been received.  Software can poll, clear, and repeat on this bit to
- *      eventually count all required transistions.
- * 
- *      int cnt = 0;
- *      while (cnt < INIT_TRN) [
- *             if (SPXX_CLK_STAT[SRXTRN]) [
- *                cnt++;
- *                SPXX_CLK_STAT[SRXTRN] = 0;
- *             ]
- *      ]
- * 
- *   - subsequent training sequences will normally move the taps only
- *     one position, so the ALPHA equation becomes...
- * 
- *     MAC   = (MAXDIST == 0) ? 1 : ROUNDUP((1 * (MAXDIST + 2))) + 1
- * 
- *        ALPHA = DLL + MUX + MAC
- * 
- *     ergo, MAXDIST simplifies to...
- * 
- *        ALPHA = (MAXDIST == 0) ? 3 : MAXDIST + 5
- * 
- *        DLL and MUX and MAC will always require at least a training sequence
- *        each - even if disabled.  If the macro sequence is enabled, an
- *        additional training sequenece at the end is necessary.  The extra
- *        sequence allows for all training state to be cleared before resuming
- *        normal operation.
- * 
- * 8) after the recevier gets enough training sequences in order to achieve
- *    deskew lock, set SPXX_TRN4_CTL[CLR_BOOT]
- *    - this disables the continuous macro sequences and puts into into one
- *      macro sequnence per training operation
- *    - optionally, the machine can choose to fall out of training if
- *      enough NOPs follow the training operation (require at least 32 NOPs
- *      to follow the training sequence).
- * 
- *    There must be at least MAXDIST + 3 training sequences after the
- *    SPXX_TRN4_CTL[CLR_BOOT] is set or sufficient NOPs from the TX device.
- * 
- * 9) the TX device continues to send training sequences until the RX
- *    device sends a calendar transistion.  This is controlled by
- *    SRXX_COM_CTL[ST_EN].  Other restrictions require other Spi parameters
- *    (e.g. the calendar table) to be setup before this bit can be enabled.
- *    Once the entire interface is properly programmed, software writes
- *    SRXX_COM_CTL[INF_EN].  At this point, the Spi4 packets will begin to
- *    be sent into the N2K core and processed by the chip.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spxx_trn4_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_13_63          : 51;
-        uint64_t trntest                 : 1;       /**< Training Test Mode
-                                                         This bit is only for initial bringup
-                                                         (spx_csr__spi4_trn_test_mode) */
-        uint64_t jitter                  : 3;       /**< Accounts for jitter when the macro sequence is
-                                                         locking.  The value is how many consecutive
-                                                         transititions before declaring en edge.  Minimum
-                                                         value is 1.  This parameter must be set for Spi4
-                                                         mode using auto-bit deskew.
-                                                         (spx_csr__spi4_mac_jitter) */
-        uint64_t clr_boot                : 1;       /**< Clear the macro boot sequence mode bit
-                                                         (spx_csr__spi4_mac_clr_boot) */
-        uint64_t set_boot                : 1;       /**< Enable the macro boot sequence mode bit
-                                                         (spx_csr__spi4_mac_set_boot) */
-        uint64_t maxdist                 : 5;       /**< This field defines how far from center the
-                                                         deskew logic will search in a single macro
-                                                          sequence (spx_csr__spi4_mac_iters) */
-        uint64_t macro_en                : 1;       /**< Allow the macro sequence to center the sample
-                                                         point in the data window through hardware
-                                                         (spx_csr__spi4_mac_trn_en) */
-        uint64_t mux_en                  : 1;       /**< Enable the hardware machine that selects the
-                                                         proper coarse FLOP selects
-                                                         (spx_csr__spi4_mux_trn_en) */
-#else
-        uint64_t mux_en                  : 1;
-        uint64_t macro_en                : 1;
-        uint64_t maxdist                 : 5;
-        uint64_t set_boot                : 1;
-        uint64_t clr_boot                : 1;
-        uint64_t jitter                  : 3;
-        uint64_t trntest                 : 1;
-        uint64_t reserved_13_63          : 51;
-#endif
-    } s;
-    struct cvmx_spxx_trn4_ctl_s          cn38xx;
-    struct cvmx_spxx_trn4_ctl_s          cn38xxp2;
-    struct cvmx_spxx_trn4_ctl_s          cn58xx;
-    struct cvmx_spxx_trn4_ctl_s          cn58xxp1;
-} cvmx_spxx_trn4_ctl_t;
-
-
-/**
- * cvmx_spx0_pll_bw_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spx0_pll_bw_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t bw_ctl                  : 5;       /**< Core PLL bandwidth control */
-#else
-        uint64_t bw_ctl                  : 5;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_spx0_pll_bw_ctl_s        cn38xx;
-    struct cvmx_spx0_pll_bw_ctl_s        cn38xxp2;
-} cvmx_spx0_pll_bw_ctl_t;
-
-
-/**
- * cvmx_spx0_pll_setting
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_spx0_pll_setting_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t setting                 : 17;      /**< Core PLL setting */
-#else
-        uint64_t setting                 : 17;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_spx0_pll_setting_s       cn38xx;
-    struct cvmx_spx0_pll_setting_s       cn38xxp2;
-} cvmx_spx0_pll_setting_t;
-
-
-/**
- * cvmx_srx#_com_ctl
- *
- * SRX_COM_CTL - Spi receive common control
- *
- *
- * Notes:
- * Restrictions:
- * Both the calendar table and the LEN and M parameters must be completely
- * setup before writing the Interface enable (INF_EN) and Status channel
- * enabled (ST_EN) asserted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_com_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t prts                    : 4;       /**< Number of ports in the receiver (write: ports - 1)
-                                                         - 0:  1 port
-                                                         - 1:  2 ports
-                                                         - 2:  3 ports
-                                                          - ...
-                                                          - 15: 16 ports */
-        uint64_t st_en                   : 1;       /**< Status channel enabled
-                                                         This is to allow configs without a status channel.
-                                                         This bit should not be modified once the
-                                                         interface is enabled. */
-        uint64_t reserved_1_2            : 2;
-        uint64_t inf_en                  : 1;       /**< Interface enable
-                                                         The master switch that enables the entire
-                                                         interface. SRX will not validiate any data until
-                                                         this bit is set. This bit should not be modified
-                                                         once the interface is enabled. */
-#else
-        uint64_t inf_en                  : 1;
-        uint64_t reserved_1_2            : 2;
-        uint64_t st_en                   : 1;
-        uint64_t prts                    : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_srxx_com_ctl_s           cn38xx;
-    struct cvmx_srxx_com_ctl_s           cn38xxp2;
-    struct cvmx_srxx_com_ctl_s           cn58xx;
-    struct cvmx_srxx_com_ctl_s           cn58xxp1;
-} cvmx_srxx_com_ctl_t;
-
-
-/**
- * cvmx_srx#_ign_rx_full
- *
- * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure
- *
- *
- * Notes:
- * * IGNORE
- * If a device can not or should not assert backpressure, then setting DROP
- * will force STARVING status on the status channel for all ports.  This
- * eliminates any back pressure from N2.
- * 
- * This implies that it's ok drop packets when the FIFOS fill up.
- * 
- * A side effect of this mode is that the TPA Watcher will effectively be
- * disabled.  Since the DROP mode forces all TPA lines asserted, the TPA
- * Watcher will never find a cycle where the TPA for the selected port is
- * deasserted in order to increment its count.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_ign_rx_full_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t ignore                  : 16;      /**< This port should ignore backpressure hints from
-                                                          GMX when the RX FIFO fills up
-                                                         - 0: Use GMX backpressure
-                                                         - 1: Ignore GMX backpressure */
-#else
-        uint64_t ignore                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_srxx_ign_rx_full_s       cn38xx;
-    struct cvmx_srxx_ign_rx_full_s       cn38xxp2;
-    struct cvmx_srxx_ign_rx_full_s       cn58xx;
-    struct cvmx_srxx_ign_rx_full_s       cn58xxp1;
-} cvmx_srxx_ign_rx_full_t;
-
-
-/**
- * cvmx_srx#_spi4_cal#
- *
- * specify the RSL base addresses for the block
- * SRX_SPI4_CAL - Spi4 Calender table
- * direct_calendar_write / direct_calendar_read
- *
- * Notes:
- * There are 32 calendar table CSR's, each containing 4 entries for a
- *     total of 128 entries.  In the above definition...
- * 
- *           n = calendar table offset * 4
- * 
- *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
- *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
- *        and would contain entries (16*4) = 64, 65, 66, and 67.
- * 
- * Restrictions:
- *          Calendar table entry accesses (read or write) can only occur
- *          if the interface is disabled.  All other accesses will be
- *          unpredictable.
- * 
- *          Both the calendar table and the LEN and M parameters must be
- *          completely setup before writing the Interface enable (INF_EN) and
- *          Status channel enabled (ST_EN) asserted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_spi4_calx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t oddpar                  : 1;       /**< Odd parity over SRX_SPI4_CAL[15:0]
-                                                         (^SRX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
-        uint64_t prt3                    : 4;       /**< Status for port n+3 */
-        uint64_t prt2                    : 4;       /**< Status for port n+2 */
-        uint64_t prt1                    : 4;       /**< Status for port n+1 */
-        uint64_t prt0                    : 4;       /**< Status for port n+0 */
-#else
-        uint64_t prt0                    : 4;
-        uint64_t prt1                    : 4;
-        uint64_t prt2                    : 4;
-        uint64_t prt3                    : 4;
-        uint64_t oddpar                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_srxx_spi4_calx_s         cn38xx;
-    struct cvmx_srxx_spi4_calx_s         cn38xxp2;
-    struct cvmx_srxx_spi4_calx_s         cn58xx;
-    struct cvmx_srxx_spi4_calx_s         cn58xxp1;
-} cvmx_srxx_spi4_calx_t;
-
-
-/**
- * cvmx_srx#_spi4_stat
- *
- * SRX_SPI4_STAT - Spi4 status channel control
- *
- *
- * Notes:
- * Restrictions:
- *    Both the calendar table and the LEN and M parameters must be
- *    completely setup before writing the Interface enable (INF_EN) and
- *    Status channel enabled (ST_EN) asserted.
- * 
- * Current rev only supports LVTTL status IO
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_spi4_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t m                       : 8;       /**< CALENDAR_M (from spi4.2 spec) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t len                     : 7;       /**< CALENDAR_LEN (from spi4.2 spec) */
-#else
-        uint64_t len                     : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t m                       : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_srxx_spi4_stat_s         cn38xx;
-    struct cvmx_srxx_spi4_stat_s         cn38xxp2;
-    struct cvmx_srxx_spi4_stat_s         cn58xx;
-    struct cvmx_srxx_spi4_stat_s         cn58xxp1;
-} cvmx_srxx_spi4_stat_t;
-
-
-/**
- * cvmx_srx#_sw_tick_ctl
- *
- * SRX_SW_TICK_CTL - Create a software tick of Spi4 data.  A write to this register will create a data tick.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_sw_tick_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t eop                     : 1;       /**< SW Tick EOP
-                                                         (PASS3 only) */
-        uint64_t sop                     : 1;       /**< SW Tick SOP
-                                                         (PASS3 only) */
-        uint64_t mod                     : 4;       /**< SW Tick MOD - valid byte count
-                                                         (PASS3 only) */
-        uint64_t opc                     : 4;       /**< SW Tick ERR - packet had an error
-                                                         (PASS3 only) */
-        uint64_t adr                     : 4;       /**< SW Tick port address
-                                                         (PASS3 only) */
-#else
-        uint64_t adr                     : 4;
-        uint64_t opc                     : 4;
-        uint64_t mod                     : 4;
-        uint64_t sop                     : 1;
-        uint64_t eop                     : 1;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_srxx_sw_tick_ctl_s       cn38xx;
-    struct cvmx_srxx_sw_tick_ctl_s       cn58xx;
-    struct cvmx_srxx_sw_tick_ctl_s       cn58xxp1;
-} cvmx_srxx_sw_tick_ctl_t;
-
-
-/**
- * cvmx_srx#_sw_tick_dat
- *
- * SRX_SW_TICK_DAT - Create a software tick of Spi4 data
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_srxx_sw_tick_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t dat                     : 64;      /**< Data tick when SRX_SW_TICK_CTL is written
-                                                         (PASS3 only) */
-#else
-        uint64_t dat                     : 64;
-#endif
-    } s;
-    struct cvmx_srxx_sw_tick_dat_s       cn38xx;
-    struct cvmx_srxx_sw_tick_dat_s       cn58xx;
-    struct cvmx_srxx_sw_tick_dat_s       cn58xxp1;
-} cvmx_srxx_sw_tick_dat_t;
-
-
-/**
- * cvmx_stx#_arb_ctl
- *
- * STX_ARB_CTL - Spi transmit arbitration control
- *
- *
- * Notes:
- * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
- * parameter will have to be adjusted.  Please see the
- * STX_SPI4_DAT[MAX_T] section for additional information.  In
- * addition, the min_burst can only be guaranteed on the initial data
- * burst of a given packet (i.e. the first data burst which contains
- * the SOP tick).  All subsequent bursts could be truncated by training
- * sequences at any point during transmission and could be arbitrarily
- * small.  This mode is only for use in Spi4 mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_arb_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t mintrn                  : 1;       /**< Hold off training cycles until STX_MIN_BST[MINB]
-                                                         is satisfied */
-        uint64_t reserved_4_4            : 1;
-        uint64_t igntpa                  : 1;       /**< User switch to ignore any TPA information from the
-                                                         Spi interface. This CSR forces all TPA terms to
-                                                         be masked out.  It is only intended as backdoor
-                                                         or debug feature. */
-        uint64_t reserved_0_2            : 3;
-#else
-        uint64_t reserved_0_2            : 3;
-        uint64_t igntpa                  : 1;
-        uint64_t reserved_4_4            : 1;
-        uint64_t mintrn                  : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_stxx_arb_ctl_s           cn38xx;
-    struct cvmx_stxx_arb_ctl_s           cn38xxp2;
-    struct cvmx_stxx_arb_ctl_s           cn58xx;
-    struct cvmx_stxx_arb_ctl_s           cn58xxp1;
-} cvmx_stxx_arb_ctl_t;
-
-
-/**
- * cvmx_stx#_bckprs_cnt
- *
- * Notes:
- * This register reports the total number of cycles (STX data clks -
- * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA
- * or is otherwise receiving backpressure.
- * 
- * In Spi4 mode, this is defined as a loss of TPA which is indicated when
- * the receiving device reports SATISFIED for the given port.  The calendar
- * status is brought into N2 on the spi4_tx*_sclk and synchronized into the
- * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk
- * clock (internally, this the stx_clk).  The counter will update on the
- * rising edge in which backpressure is reported.
- * 
- * This register will be cleared when software writes all '1's to
- * the STX_BCKPRS_CNT.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_bckprs_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Number of cycles when back-pressure is received
-                                                         for port defined in STX_STAT_CTL[BCKPRS] */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_stxx_bckprs_cnt_s        cn38xx;
-    struct cvmx_stxx_bckprs_cnt_s        cn38xxp2;
-    struct cvmx_stxx_bckprs_cnt_s        cn58xx;
-    struct cvmx_stxx_bckprs_cnt_s        cn58xxp1;
-} cvmx_stxx_bckprs_cnt_t;
-
-
-/**
- * cvmx_stx#_com_ctl
- *
- * STX_COM_CTL - TX Common Control Register
- *
- *
- * Notes:
- * Restrictions:
- * Both the calendar table and the LEN and M parameters must be
- * completely setup before writing the Interface enable (INF_EN) and
- * Status channel enabled (ST_EN) asserted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_com_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t st_en                   : 1;       /**< Status channel enabled */
-        uint64_t reserved_1_2            : 2;
-        uint64_t inf_en                  : 1;       /**< Interface enable */
-#else
-        uint64_t inf_en                  : 1;
-        uint64_t reserved_1_2            : 2;
-        uint64_t st_en                   : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_stxx_com_ctl_s           cn38xx;
-    struct cvmx_stxx_com_ctl_s           cn38xxp2;
-    struct cvmx_stxx_com_ctl_s           cn58xx;
-    struct cvmx_stxx_com_ctl_s           cn58xxp1;
-} cvmx_stxx_com_ctl_t;
-
-
-/**
- * cvmx_stx#_dip_cnt
- *
- * Notes:
- * * DIPMAX
- *   This counts the number of consecutive DIP2 states in which the the
- *   received DIP2 is bad.  The expected range is 1-15 cycles with the
- *   value of 0 meaning disabled.
- * 
- * * FRMMAX
- *   This counts the number of consecutive unexpected framing patterns (11)
- *   states.  The expected range is 1-15 cycles with the value of 0 meaning
- *   disabled.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_dip_cnt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t frmmax                  : 4;       /**< Number of consecutive unexpected framing patterns
-                                                         before loss of sync */
-        uint64_t dipmax                  : 4;       /**< Number of consecutive DIP2 error before loss
-                                                         of sync */
-#else
-        uint64_t dipmax                  : 4;
-        uint64_t frmmax                  : 4;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_stxx_dip_cnt_s           cn38xx;
-    struct cvmx_stxx_dip_cnt_s           cn38xxp2;
-    struct cvmx_stxx_dip_cnt_s           cn58xx;
-    struct cvmx_stxx_dip_cnt_s           cn58xxp1;
-} cvmx_stxx_dip_cnt_t;
-
-
-/**
- * cvmx_stx#_ign_cal
- *
- * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_ign_cal_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t igntpa                  : 16;      /**< Ignore Calendar Status from Spi4 Status Channel
-                                                          per Spi4 port
-                                                         - 0: Use the status channel info
-                                                         - 1: Grant the given port MAX_BURST1 credits */
-#else
-        uint64_t igntpa                  : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_stxx_ign_cal_s           cn38xx;
-    struct cvmx_stxx_ign_cal_s           cn38xxp2;
-    struct cvmx_stxx_ign_cal_s           cn58xx;
-    struct cvmx_stxx_ign_cal_s           cn58xxp1;
-} cvmx_stxx_ign_cal_t;
-
-
-/**
- * cvmx_stx#_int_msk
- *
- * Notes:
- * If the bit is enabled, then the coresponding exception condition will
- * result in an interrupt to the system.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_int_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
-        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
-        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
-        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
-        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
-        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
-        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
-        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
-#else
-        uint64_t calpar0                 : 1;
-        uint64_t calpar1                 : 1;
-        uint64_t ovrbst                  : 1;
-        uint64_t datovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t nosync                  : 1;
-        uint64_t unxfrm                  : 1;
-        uint64_t frmerr                  : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_stxx_int_msk_s           cn38xx;
-    struct cvmx_stxx_int_msk_s           cn38xxp2;
-    struct cvmx_stxx_int_msk_s           cn58xx;
-    struct cvmx_stxx_int_msk_s           cn58xxp1;
-} cvmx_stxx_int_msk_t;
-
-
-/**
- * cvmx_stx#_int_reg
- *
- * Notes:
- * * CALPAR0
- *   This bit indicates that the Spi4 calendar table encountered a parity
- *   error on bank0 of the calendar table memory.  This error bit is
- *   associated with the calendar table on the TX interface - the interface
- *   that drives the Spi databus.  The calendar table is used in Spi4 mode
- *   when using the status channel.  Parity errors can occur during normal
- *   operation when the calendar table is constantly being read for the port
- *   information, or during initialization time, when the user has access.
- *   This errors will force the the status channel to the reset state and
- *   begin driving training sequences.  The status channel will also reset.
- *   Software must follow the init sequence to resynch the interface.  This
- *   includes toggling INF_EN which will cancel all outstanding accumulated
- *   credits.
- * 
- * * CALPAR1
- *   Identical to CALPAR0 except that it indicates that the error occured
- *   on bank1 (instead of bank0).
- * 
- * * OVRBST
- *   STX can track upto a 512KB data burst.  Any packet larger than that is
- *   illegal and will cause confusion in the STX state machine.  BMI is
- *   responsible for throwing away these out of control packets from the
- *   input and the Execs should never generate them on the output.  This is
- *   a fatal error and should have STX_INT_SYNC[OVRBST] set.
- * 
- * * DATOVR
- *   FIFO where the Spi4 data ramps upto its transmit frequency has
- *   overflowed.  This is a fatal error and should have
- *   STX_INT_SYNC[DATOVR] set.
- * 
- * * DIPERR
- *   This bit will fire if any DIP2 error is caught by the Spi4 status
- *   channel.
- * 
- * * NOSYNC
- *   This bit indicates that the number of consecutive DIP2 errors exceeds
- *   STX_DIP_CNT[MAXDIP] and that the interface should be taken down.  The
- *   datapath will be notified and send continuous training sequences until
- *   software resynchronizes the interface.  This error condition should
- *   have STX_INT_SYNC[NOSYNC] set.
- * 
- * * UNXFRM
- *   Unexpected framing data was seen on the status channel.
- * 
- * * FRMERR
- *   This bit indicates that the number of consecutive unexpected framing
- *   sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken
- *   down.  The datapath will be notified and send continuous training
- *   sequences until software resynchronizes the interface.  This error
- *   condition should have STX_INT_SYNC[FRMERR] set.
- * 
- * * SYNCERR
- *   Indicates that an exception marked in STX_INT_SYNC has occured and the
- *   TX datapath is disabled.  It is recommended that the OVRBST, DATOVR,
- *   NOSYNC, and FRMERR error conditions all have their bits set in the
- *   STX_INT_SYNC register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_int_reg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t syncerr                 : 1;       /**< Interface encountered a fatal error */
-        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
-        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
-        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
-        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
-        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
-        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
-        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
-        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
-#else
-        uint64_t calpar0                 : 1;
-        uint64_t calpar1                 : 1;
-        uint64_t ovrbst                  : 1;
-        uint64_t datovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t nosync                  : 1;
-        uint64_t unxfrm                  : 1;
-        uint64_t frmerr                  : 1;
-        uint64_t syncerr                 : 1;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_stxx_int_reg_s           cn38xx;
-    struct cvmx_stxx_int_reg_s           cn38xxp2;
-    struct cvmx_stxx_int_reg_s           cn58xx;
-    struct cvmx_stxx_int_reg_s           cn58xxp1;
-} cvmx_stxx_int_reg_t;
-
-
-/**
- * cvmx_stx#_int_sync
- *
- * Notes:
- * If the bit is enabled, then the coresponding exception condition is flagged
- * to be fatal.  In Spi4 mode, the exception condition will result in a loss
- * of sync condition on the Spi4 interface and the datapath will send
- * continuous traing sequences.
- * 
- * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and
- * FRMERR errors as synchronization events.  Software is free to
- * synchronize the bus on other conditions, but this is the minimum
- * recommended set.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_int_sync_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_8_63           : 56;
-        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
-        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
-        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
-        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
-        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
-        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
-        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
-        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
-#else
-        uint64_t calpar0                 : 1;
-        uint64_t calpar1                 : 1;
-        uint64_t ovrbst                  : 1;
-        uint64_t datovr                  : 1;
-        uint64_t diperr                  : 1;
-        uint64_t nosync                  : 1;
-        uint64_t unxfrm                  : 1;
-        uint64_t frmerr                  : 1;
-        uint64_t reserved_8_63           : 56;
-#endif
-    } s;
-    struct cvmx_stxx_int_sync_s          cn38xx;
-    struct cvmx_stxx_int_sync_s          cn38xxp2;
-    struct cvmx_stxx_int_sync_s          cn58xx;
-    struct cvmx_stxx_int_sync_s          cn58xxp1;
-} cvmx_stxx_int_sync_t;
-
-
-/**
- * cvmx_stx#_min_bst
- *
- * STX_MIN_BST - Min Burst to enforce when inserting training sequence
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_min_bst_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_9_63           : 55;
-        uint64_t minb                    : 9;       /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
-                                                         the number of 8B blocks to send before inserting
-                                                         a training sequence.  Normally MINB will be set
-                                                         to GMX_TX_SPI_THRESH[THRESH].  MINB should always
-                                                         be set to an even number (ie. multiple of 16B) */
-#else
-        uint64_t minb                    : 9;
-        uint64_t reserved_9_63           : 55;
-#endif
-    } s;
-    struct cvmx_stxx_min_bst_s           cn38xx;
-    struct cvmx_stxx_min_bst_s           cn38xxp2;
-    struct cvmx_stxx_min_bst_s           cn58xx;
-    struct cvmx_stxx_min_bst_s           cn58xxp1;
-} cvmx_stxx_min_bst_t;
-
-
-/**
- * cvmx_stx#_spi4_cal#
- *
- * specify the RSL base addresses for the block
- * STX_SPI4_CAL - Spi4 Calender table
- * direct_calendar_write / direct_calendar_read
- *
- * Notes:
- * There are 32 calendar table CSR's, each containing 4 entries for a
- *     total of 128 entries.  In the above definition...
- * 
- *           n = calendar table offset * 4
- * 
- *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
- *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
- *        and would contain entries (16*4) = 64, 65, 66, and 67.
- * 
- * Restrictions:
- *        Calendar table entry accesses (read or write) can only occur
- *        if the interface is disabled.  All other accesses will be
- *        unpredictable.
- * 
- *     Both the calendar table and the LEN and M parameters must be
- *     completely setup before writing the Interface enable (INF_EN) and
- *     Status channel enabled (ST_EN) asserted.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_spi4_calx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t oddpar                  : 1;       /**< Odd parity over STX_SPI4_CAL[15:0]
-                                                         (^STX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
-        uint64_t prt3                    : 4;       /**< Status for port n+3 */
-        uint64_t prt2                    : 4;       /**< Status for port n+2 */
-        uint64_t prt1                    : 4;       /**< Status for port n+1 */
-        uint64_t prt0                    : 4;       /**< Status for port n+0 */
-#else
-        uint64_t prt0                    : 4;
-        uint64_t prt1                    : 4;
-        uint64_t prt2                    : 4;
-        uint64_t prt3                    : 4;
-        uint64_t oddpar                  : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_stxx_spi4_calx_s         cn38xx;
-    struct cvmx_stxx_spi4_calx_s         cn38xxp2;
-    struct cvmx_stxx_spi4_calx_s         cn58xx;
-    struct cvmx_stxx_spi4_calx_s         cn58xxp1;
-} cvmx_stxx_spi4_calx_t;
-
-
-/**
- * cvmx_stx#_spi4_dat
- *
- * STX_SPI4_DAT - Spi4 datapath channel control register
- *
- *
- * Notes:
- * Restrictions:
- * * DATA_MAX_T must be in MOD 4 cycles
- * 
- * * DATA_MAX_T must at least 0x20
- * 
- * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce
- * 
- * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall
- *   waiting for min bursts to complete.  In the worst case, this will
- *   add the entire min burst transmission time to the interval between
- *   trainging sequence.  The observed MAX_T on the Spi4 bus will be...
- * 
- *                STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4)
- * 
- *      If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
- *      parameter will have to be adjusted.  Please see the
- *      STX_SPI4_DAT[MAX_T] section for additional information.  In
- *      addition, the min_burst can only be guaranteed on the initial data
- *      burst of a given packet (i.e. the first data burst which contains
- *      the SOP tick).  All subsequent bursts could be truncated by training
- *      sequences at any point during transmission and could be arbitrarily
- *      small.  This mode is only for use in Spi4 mode.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_spi4_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t alpha                   : 16;      /**< alpha (from spi4.2 spec) */
-        uint64_t max_t                   : 16;      /**< DATA_MAX_T (from spi4.2 spec) */
-#else
-        uint64_t max_t                   : 16;
-        uint64_t alpha                   : 16;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_stxx_spi4_dat_s          cn38xx;
-    struct cvmx_stxx_spi4_dat_s          cn38xxp2;
-    struct cvmx_stxx_spi4_dat_s          cn58xx;
-    struct cvmx_stxx_spi4_dat_s          cn58xxp1;
-} cvmx_stxx_spi4_dat_t;
-
-
-/**
- * cvmx_stx#_spi4_stat
- *
- * STX_SPI4_STAT - Spi4 status channel control register
- *
- *
- * Notes:
- * Restrictions:
- * Both the calendar table and the LEN and M parameters must be
- * completely setup before writing the Interface enable (INF_EN) and
- * Status channel enabled (ST_EN) asserted.
- * 
- * The calendar table will only be enabled when LEN > 0.
- * 
- * Current rev will only support LVTTL status IO.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_spi4_stat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t m                       : 8;       /**< CALENDAR_M (from spi4.2 spec) */
-        uint64_t reserved_7_7            : 1;
-        uint64_t len                     : 7;       /**< CALENDAR_LEN (from spi4.2 spec) */
-#else
-        uint64_t len                     : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t m                       : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_stxx_spi4_stat_s         cn38xx;
-    struct cvmx_stxx_spi4_stat_s         cn38xxp2;
-    struct cvmx_stxx_spi4_stat_s         cn58xx;
-    struct cvmx_stxx_spi4_stat_s         cn58xxp1;
-} cvmx_stxx_spi4_stat_t;
-
-
-/**
- * cvmx_stx#_stat_bytes_hi
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_stat_bytes_hi_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Number of bytes sent (CNT[63:32]) */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_stxx_stat_bytes_hi_s     cn38xx;
-    struct cvmx_stxx_stat_bytes_hi_s     cn38xxp2;
-    struct cvmx_stxx_stat_bytes_hi_s     cn58xx;
-    struct cvmx_stxx_stat_bytes_hi_s     cn58xxp1;
-} cvmx_stxx_stat_bytes_hi_t;
-
-
-/**
- * cvmx_stx#_stat_bytes_lo
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_stat_bytes_lo_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Number of bytes sent (CNT[31:0]) */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_stxx_stat_bytes_lo_s     cn38xx;
-    struct cvmx_stxx_stat_bytes_lo_s     cn38xxp2;
-    struct cvmx_stxx_stat_bytes_lo_s     cn58xx;
-    struct cvmx_stxx_stat_bytes_lo_s     cn58xxp1;
-} cvmx_stxx_stat_bytes_lo_t;
-
-
-/**
- * cvmx_stx#_stat_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_stat_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_5_63           : 59;
-        uint64_t clr                     : 1;       /**< Clear all statistics counters
-                                                         - STX_STAT_PKT_XMT
-                                                         - STX_STAT_BYTES_HI
-                                                         - STX_STAT_BYTES_LO */
-        uint64_t bckprs                  : 4;       /**< The selected port for STX_BCKPRS_CNT */
-#else
-        uint64_t bckprs                  : 4;
-        uint64_t clr                     : 1;
-        uint64_t reserved_5_63           : 59;
-#endif
-    } s;
-    struct cvmx_stxx_stat_ctl_s          cn38xx;
-    struct cvmx_stxx_stat_ctl_s          cn38xxp2;
-    struct cvmx_stxx_stat_ctl_s          cn58xx;
-    struct cvmx_stxx_stat_ctl_s          cn58xxp1;
-} cvmx_stxx_stat_ctl_t;
-
-
-/**
- * cvmx_stx#_stat_pkt_xmt
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_stxx_stat_pkt_xmt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t cnt                     : 32;      /**< Number of packets sent */
-#else
-        uint64_t cnt                     : 32;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_stxx_stat_pkt_xmt_s      cn38xx;
-    struct cvmx_stxx_stat_pkt_xmt_s      cn38xxp2;
-    struct cvmx_stxx_stat_pkt_xmt_s      cn58xx;
-    struct cvmx_stxx_stat_pkt_xmt_s      cn58xxp1;
-} cvmx_stxx_stat_pkt_xmt_t;
-
-
-/**
- * cvmx_tim_mem_debug0
- *
- * Notes:
- * Internal per-ring state intended for debug use only - tim.ctl[47:0]
- * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_mem_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t ena                     : 1;       /**< Ring timer enable */
-        uint64_t reserved_46_46          : 1;
-        uint64_t count                   : 22;      /**< Time offset for the ring
-                                                         Set to INTERVAL and counts down by 1 every 1024
-                                                         cycles when ENA==1. The HW forces a bucket
-                                                         traversal (and resets COUNT to INTERVAL) whenever
-                                                         the decrement would cause COUNT to go negative.
-                                                         COUNT is unpredictable whenever ENA==0.
-                                                         COUNT is reset to INTERVAL whenever TIM_MEM_RING1
-                                                         is written for the ring. */
-        uint64_t reserved_22_23          : 2;
-        uint64_t interval                : 22;      /**< Timer interval - 1 */
-#else
-        uint64_t interval                : 22;
-        uint64_t reserved_22_23          : 2;
-        uint64_t count                   : 22;
-        uint64_t reserved_46_46          : 1;
-        uint64_t ena                     : 1;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_tim_mem_debug0_s         cn30xx;
-    struct cvmx_tim_mem_debug0_s         cn31xx;
-    struct cvmx_tim_mem_debug0_s         cn38xx;
-    struct cvmx_tim_mem_debug0_s         cn38xxp2;
-    struct cvmx_tim_mem_debug0_s         cn50xx;
-    struct cvmx_tim_mem_debug0_s         cn52xx;
-    struct cvmx_tim_mem_debug0_s         cn52xxp1;
-    struct cvmx_tim_mem_debug0_s         cn56xx;
-    struct cvmx_tim_mem_debug0_s         cn56xxp1;
-    struct cvmx_tim_mem_debug0_s         cn58xx;
-    struct cvmx_tim_mem_debug0_s         cn58xxp1;
-} cvmx_tim_mem_debug0_t;
-
-
-/**
- * cvmx_tim_mem_debug1
- *
- * Notes:
- * Internal per-ring state intended for debug use only - tim.sta[63:0]
- * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_mem_debug1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t bucket                  : 13;      /**< Current bucket[12:0]
-                                                         Reset to 0 whenever TIM_MEM_RING0 is written for
-                                                         the ring. Incremented (modulo BSIZE) once per
-                                                         bucket traversal.
-                                                         See TIM_MEM_DEBUG2[BUCKET]. */
-        uint64_t base                    : 31;      /**< Pointer[35:5] to bucket[0] */
-        uint64_t bsize                   : 20;      /**< Number of buckets - 1 */
-#else
-        uint64_t bsize                   : 20;
-        uint64_t base                    : 31;
-        uint64_t bucket                  : 13;
-#endif
-    } s;
-    struct cvmx_tim_mem_debug1_s         cn30xx;
-    struct cvmx_tim_mem_debug1_s         cn31xx;
-    struct cvmx_tim_mem_debug1_s         cn38xx;
-    struct cvmx_tim_mem_debug1_s         cn38xxp2;
-    struct cvmx_tim_mem_debug1_s         cn50xx;
-    struct cvmx_tim_mem_debug1_s         cn52xx;
-    struct cvmx_tim_mem_debug1_s         cn52xxp1;
-    struct cvmx_tim_mem_debug1_s         cn56xx;
-    struct cvmx_tim_mem_debug1_s         cn56xxp1;
-    struct cvmx_tim_mem_debug1_s         cn58xx;
-    struct cvmx_tim_mem_debug1_s         cn58xxp1;
-} cvmx_tim_mem_debug1_t;
-
-
-/**
- * cvmx_tim_mem_debug2
- *
- * Notes:
- * Internal per-ring state intended for debug use only - tim.sta[95:64]
- * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_mem_debug2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_24_63          : 40;
-        uint64_t cpool                   : 3;       /**< Free list used to free chunks */
-        uint64_t csize                   : 13;      /**< Number of words per chunk */
-        uint64_t reserved_7_7            : 1;
-        uint64_t bucket                  : 7;       /**< Current bucket[19:13]
-                                                         See TIM_MEM_DEBUG1[BUCKET]. */
-#else
-        uint64_t bucket                  : 7;
-        uint64_t reserved_7_7            : 1;
-        uint64_t csize                   : 13;
-        uint64_t cpool                   : 3;
-        uint64_t reserved_24_63          : 40;
-#endif
-    } s;
-    struct cvmx_tim_mem_debug2_s         cn30xx;
-    struct cvmx_tim_mem_debug2_s         cn31xx;
-    struct cvmx_tim_mem_debug2_s         cn38xx;
-    struct cvmx_tim_mem_debug2_s         cn38xxp2;
-    struct cvmx_tim_mem_debug2_s         cn50xx;
-    struct cvmx_tim_mem_debug2_s         cn52xx;
-    struct cvmx_tim_mem_debug2_s         cn52xxp1;
-    struct cvmx_tim_mem_debug2_s         cn56xx;
-    struct cvmx_tim_mem_debug2_s         cn56xxp1;
-    struct cvmx_tim_mem_debug2_s         cn58xx;
-    struct cvmx_tim_mem_debug2_s         cn58xxp1;
-} cvmx_tim_mem_debug2_t;
-
-
-/**
- * cvmx_tim_mem_ring0
- *
- * Notes:
- * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring.
- * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is
- * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].)
- * BASE is a 32-byte aligned pointer[35:0].  Only pointer[35:5] are stored because pointer[4:0] = 0.
- * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_mem_ring0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_55_63          : 9;
-        uint64_t first_bucket            : 31;      /**< Pointer[35:5] to bucket[0] */
-        uint64_t num_buckets             : 20;      /**< Number of buckets - 1 */
-        uint64_t ring                    : 4;       /**< Ring ID */
-#else
-        uint64_t ring                    : 4;
-        uint64_t num_buckets             : 20;
-        uint64_t first_bucket            : 31;
-        uint64_t reserved_55_63          : 9;
-#endif
-    } s;
-    struct cvmx_tim_mem_ring0_s          cn30xx;
-    struct cvmx_tim_mem_ring0_s          cn31xx;
-    struct cvmx_tim_mem_ring0_s          cn38xx;
-    struct cvmx_tim_mem_ring0_s          cn38xxp2;
-    struct cvmx_tim_mem_ring0_s          cn50xx;
-    struct cvmx_tim_mem_ring0_s          cn52xx;
-    struct cvmx_tim_mem_ring0_s          cn52xxp1;
-    struct cvmx_tim_mem_ring0_s          cn56xx;
-    struct cvmx_tim_mem_ring0_s          cn56xxp1;
-    struct cvmx_tim_mem_ring0_s          cn58xx;
-    struct cvmx_tim_mem_ring0_s          cn58xxp1;
-} cvmx_tim_mem_ring0_t;
-
-
-/**
- * cvmx_tim_mem_ring1
- *
- * Notes:
- * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring
- * if it was pending or active prior to the transition. (SW must delay to ensure the completion
- * of the traversal before reprogramming the ring.)
- * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value.
- * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].)
- * CSIZE must be at least 16.  It is illegal to program CSIZE to a value that is less than 16.
- * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
- * CSR read operations to this address can be performed.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_mem_ring1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_43_63          : 21;
-        uint64_t enable                  : 1;       /**< Ring timer enable
-                                                         When clear, the ring is disabled and TIM
-                                                         will not traverse any new buckets for the ring. */
-        uint64_t pool                    : 3;       /**< Free list used to free chunks */
-        uint64_t words_per_chunk         : 13;      /**< Number of words per chunk */
-        uint64_t interval                : 22;      /**< Timer interval - 1, measured in 1024 cycle ticks */
-        uint64_t ring                    : 4;       /**< Ring ID */
-#else
-        uint64_t ring                    : 4;
-        uint64_t interval                : 22;
-        uint64_t words_per_chunk         : 13;
-        uint64_t pool                    : 3;
-        uint64_t enable                  : 1;
-        uint64_t reserved_43_63          : 21;
-#endif
-    } s;
-    struct cvmx_tim_mem_ring1_s          cn30xx;
-    struct cvmx_tim_mem_ring1_s          cn31xx;
-    struct cvmx_tim_mem_ring1_s          cn38xx;
-    struct cvmx_tim_mem_ring1_s          cn38xxp2;
-    struct cvmx_tim_mem_ring1_s          cn50xx;
-    struct cvmx_tim_mem_ring1_s          cn52xx;
-    struct cvmx_tim_mem_ring1_s          cn52xxp1;
-    struct cvmx_tim_mem_ring1_s          cn56xx;
-    struct cvmx_tim_mem_ring1_s          cn56xxp1;
-    struct cvmx_tim_mem_ring1_s          cn58xx;
-    struct cvmx_tim_mem_ring1_s          cn58xxp1;
-} cvmx_tim_mem_ring1_t;
-
-
-/**
- * cvmx_tim_reg_bist_result
- *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_reg_bist_result_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t sta                     : 2;       /**< BiST result of the STA   memories (0=pass, !0=fail) */
-        uint64_t ncb                     : 1;       /**< BiST result of the NCB   memories (0=pass, !0=fail) */
-        uint64_t ctl                     : 1;       /**< BiST result of the CTL   memories (0=pass, !0=fail) */
-#else
-        uint64_t ctl                     : 1;
-        uint64_t ncb                     : 1;
-        uint64_t sta                     : 2;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_tim_reg_bist_result_s    cn30xx;
-    struct cvmx_tim_reg_bist_result_s    cn31xx;
-    struct cvmx_tim_reg_bist_result_s    cn38xx;
-    struct cvmx_tim_reg_bist_result_s    cn38xxp2;
-    struct cvmx_tim_reg_bist_result_s    cn50xx;
-    struct cvmx_tim_reg_bist_result_s    cn52xx;
-    struct cvmx_tim_reg_bist_result_s    cn52xxp1;
-    struct cvmx_tim_reg_bist_result_s    cn56xx;
-    struct cvmx_tim_reg_bist_result_s    cn56xxp1;
-    struct cvmx_tim_reg_bist_result_s    cn58xx;
-    struct cvmx_tim_reg_bist_result_s    cn58xxp1;
-} cvmx_tim_reg_bist_result_t;
-
-
-/**
- * cvmx_tim_reg_error
- *
- * Notes:
- * A ring is in error if its interval has elapsed more than once without having been serviced.
- * During a CSR write to this register, the write data is used as a mask to clear the selected mask
- * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_reg_error_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mask                    : 16;      /**< Bit mask indicating the rings in error */
-#else
-        uint64_t mask                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_tim_reg_error_s          cn30xx;
-    struct cvmx_tim_reg_error_s          cn31xx;
-    struct cvmx_tim_reg_error_s          cn38xx;
-    struct cvmx_tim_reg_error_s          cn38xxp2;
-    struct cvmx_tim_reg_error_s          cn50xx;
-    struct cvmx_tim_reg_error_s          cn52xx;
-    struct cvmx_tim_reg_error_s          cn52xxp1;
-    struct cvmx_tim_reg_error_s          cn56xx;
-    struct cvmx_tim_reg_error_s          cn56xxp1;
-    struct cvmx_tim_reg_error_s          cn58xx;
-    struct cvmx_tim_reg_error_s          cn58xxp1;
-} cvmx_tim_reg_error_t;
-
-
-/**
- * cvmx_tim_reg_flags
- *
- * Notes:
- * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all
- * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.)
- * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there
- * are no more new bucket traversals (for any ring).
- * 
- * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may
- * have been previous ones. If there are ring bucket traversals that were already pending but
- * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet)
- * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until
- * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete
- * after the 1->0 ENA_TIM transition, though.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_reg_flags_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t reset                   : 1;       /**< Reset oneshot pulse for free-running structures */
-        uint64_t enable_dwb              : 1;       /**< Enables non-zero DonwWriteBacks when set
-                                                         When set, enables the use of
-                                                         DontWriteBacks during the buffer freeing
-                                                         operations. */
-        uint64_t enable_timers           : 1;       /**< Enables the TIM section when set
-                                                         When set, TIM is in normal operation.
-                                                         When clear, time is effectively stopped for all
-                                                         rings in TIM. */
-#else
-        uint64_t enable_timers           : 1;
-        uint64_t enable_dwb              : 1;
-        uint64_t reset                   : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_tim_reg_flags_s          cn30xx;
-    struct cvmx_tim_reg_flags_s          cn31xx;
-    struct cvmx_tim_reg_flags_s          cn38xx;
-    struct cvmx_tim_reg_flags_s          cn38xxp2;
-    struct cvmx_tim_reg_flags_s          cn50xx;
-    struct cvmx_tim_reg_flags_s          cn52xx;
-    struct cvmx_tim_reg_flags_s          cn52xxp1;
-    struct cvmx_tim_reg_flags_s          cn56xx;
-    struct cvmx_tim_reg_flags_s          cn56xxp1;
-    struct cvmx_tim_reg_flags_s          cn58xx;
-    struct cvmx_tim_reg_flags_s          cn58xxp1;
-} cvmx_tim_reg_flags_t;
-
-
-/**
- * cvmx_tim_reg_int_mask
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- * When mask bit is set, the interrupt is enabled.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_reg_int_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t mask                    : 16;      /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */
-#else
-        uint64_t mask                    : 16;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_tim_reg_int_mask_s       cn30xx;
-    struct cvmx_tim_reg_int_mask_s       cn31xx;
-    struct cvmx_tim_reg_int_mask_s       cn38xx;
-    struct cvmx_tim_reg_int_mask_s       cn38xxp2;
-    struct cvmx_tim_reg_int_mask_s       cn50xx;
-    struct cvmx_tim_reg_int_mask_s       cn52xx;
-    struct cvmx_tim_reg_int_mask_s       cn52xxp1;
-    struct cvmx_tim_reg_int_mask_s       cn56xx;
-    struct cvmx_tim_reg_int_mask_s       cn56xxp1;
-    struct cvmx_tim_reg_int_mask_s       cn58xx;
-    struct cvmx_tim_reg_int_mask_s       cn58xxp1;
-} cvmx_tim_reg_int_mask_t;
-
-
-/**
- * cvmx_tim_reg_read_idx
- *
- * Notes:
- * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
- * as memories.  The names of these CSRs begin with the prefix "TIM_MEM_".
- * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
- * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
- * contents of a CSR memory can be read with consecutive CSR read commands.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tim_reg_read_idx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t inc                     : 8;       /**< Increment to add to current index for next index */
-        uint64_t index                   : 8;       /**< Index to use for next memory CSR read */
-#else
-        uint64_t index                   : 8;
-        uint64_t inc                     : 8;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } s;
-    struct cvmx_tim_reg_read_idx_s       cn30xx;
-    struct cvmx_tim_reg_read_idx_s       cn31xx;
-    struct cvmx_tim_reg_read_idx_s       cn38xx;
-    struct cvmx_tim_reg_read_idx_s       cn38xxp2;
-    struct cvmx_tim_reg_read_idx_s       cn50xx;
-    struct cvmx_tim_reg_read_idx_s       cn52xx;
-    struct cvmx_tim_reg_read_idx_s       cn52xxp1;
-    struct cvmx_tim_reg_read_idx_s       cn56xx;
-    struct cvmx_tim_reg_read_idx_s       cn56xxp1;
-    struct cvmx_tim_reg_read_idx_s       cn58xx;
-    struct cvmx_tim_reg_read_idx_s       cn58xxp1;
-} cvmx_tim_reg_read_idx_t;
-
-
-/**
- * cvmx_tra_bist_status
- *
- * TRA_BIST_STATUS = Trace Buffer BiST Status
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t tcf                     : 1;       /**< Bist Results for TCF memory
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t tdf1                    : 1;       /**< Bist Results for TDF memory 1
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-        uint64_t tdf0                    : 1;       /**< Bist Results for TCF memory 0
-                                                         - 0: GOOD (or bist in progress/never run)
-                                                         - 1: BAD */
-#else
-        uint64_t tdf0                    : 1;
-        uint64_t tdf1                    : 1;
-        uint64_t tcf                     : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } s;
-    struct cvmx_tra_bist_status_s        cn31xx;
-    struct cvmx_tra_bist_status_s        cn38xx;
-    struct cvmx_tra_bist_status_s        cn38xxp2;
-    struct cvmx_tra_bist_status_s        cn52xx;
-    struct cvmx_tra_bist_status_s        cn52xxp1;
-    struct cvmx_tra_bist_status_s        cn56xx;
-    struct cvmx_tra_bist_status_s        cn56xxp1;
-    struct cvmx_tra_bist_status_s        cn58xx;
-    struct cvmx_tra_bist_status_s        cn58xxp1;
-} cvmx_tra_bist_status_t;
-
-
-/**
- * cvmx_tra_ctl
- *
- * TRA_CTL = Trace Buffer Control
- * 
- * Description:
- *
- * Notes:
- * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1).
- * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_15_63          : 49;
-        uint64_t ignore_o                : 1;       /**< Ignore overflow during wrap mode
-                                                         If set and wrapping mode is enabled, then tracing
-                                                         will not stop at the overflow condition.  Each
-                                                         write during an overflow will overwrite the
-                                                         oldest, unread entry and the read pointer is
-                                                         incremented by one entry.  This bit has no effect
-                                                         if WRAP=0. */
-        uint64_t mcd0_ena                : 1;       /**< MCD0 enable
-                                                         If set and any PP sends the MCD0 signal, the
-                                                         tracing is disabled. */
-        uint64_t mcd0_thr                : 1;       /**< MCD0_threshold
-                                                         At a fill threshold event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
-        uint64_t mcd0_trg                : 1;       /**< MCD0_trigger
-                                                         At an end trigger event, sends an MCD0
-                                                         wire pulse that can cause cores to enter debug
-                                                         mode, if enabled.  This MCD0 wire pulse will not
-                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
-        uint64_t ciu_thr                 : 1;       /**< CIU_threshold
-                                                         When set during a fill threshold event,
-                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
-                                                         core interrupts, if enabled. */
-        uint64_t ciu_trg                 : 1;       /**< CIU_trigger
-                                                         When set during an end trigger event,
-                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
-                                                         core interrupts, if enabled. */
-        uint64_t full_thr                : 2;       /**< Full Threshhold
-                                                         0=none
-                                                         1=1/2 full
-                                                         2=3/4 full
-                                                         3=4/4 full */
-        uint64_t time_grn                : 3;       /**< Timestamp granularity
-                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
-        uint64_t trig_ctl                : 2;       /**< Trigger Control
-                                                         Note: trigger events are written to the trace
-                                                         0=no triggers
-                                                         1=trigger0=start trigger, trigger1=stop trigger
-                                                         2=(trigger0 || trigger1)=start trigger
-                                                         3=(trigger0 || trigger1)=stop trigger */
-        uint64_t wrap                    : 1;       /**< Wrap mode
-                                                         When WRAP=0, the trace buffer will disable itself
-                                                         after having logged 1024 entries.  When WRAP=1,
-                                                         the trace buffer will never disable itself.
-                                                         In this case, tracing may or may not be
-                                                         temporarily suspended during the overflow
-                                                         condition (see IGNORE_O above).
-                                                         0=do not wrap
-                                                         1=wrap */
-        uint64_t ena                     : 1;       /**< Enable Trace
-                                                         Master enable.  Tracing only happens when ENA=1.
-                                                         When ENA changes from 0 to 1, the read and write
-                                                         pointers are reset to 0x00 to begin a new trace.
-                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
-                                                         above).  When using triggers, tracing occurs only
-                                                         between start and stop triggers (including the
-                                                         triggers themselves).
-                                                         0=disable
-                                                         1=enable */
-#else
-        uint64_t ena                     : 1;
-        uint64_t wrap                    : 1;
-        uint64_t trig_ctl                : 2;
-        uint64_t time_grn                : 3;
-        uint64_t full_thr                : 2;
-        uint64_t ciu_trg                 : 1;
-        uint64_t ciu_thr                 : 1;
-        uint64_t mcd0_trg                : 1;
-        uint64_t mcd0_thr                : 1;
-        uint64_t mcd0_ena                : 1;
-        uint64_t ignore_o                : 1;
-        uint64_t reserved_15_63          : 49;
-#endif
-    } s;
-    struct cvmx_tra_ctl_s                cn31xx;
-    struct cvmx_tra_ctl_s                cn38xx;
-    struct cvmx_tra_ctl_s                cn38xxp2;
-    struct cvmx_tra_ctl_s                cn52xx;
-    struct cvmx_tra_ctl_s                cn52xxp1;
-    struct cvmx_tra_ctl_s                cn56xx;
-    struct cvmx_tra_ctl_s                cn56xxp1;
-    struct cvmx_tra_ctl_s                cn58xx;
-    struct cvmx_tra_ctl_s                cn58xxp1;
-} cvmx_tra_ctl_t;
-
-
-/**
- * cvmx_tra_cycles_since
- *
- * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers
- * 
- * Description:
- *
- * Notes:
- * This CSR is obsolete.  Use TRA_CYCLES_SINCE1 instead.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_cycles_since_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cycles                  : 48;      /**< Cycles since the last entry was written */
-        uint64_t rptr                    : 8;       /**< Read pointer */
-        uint64_t wptr                    : 8;       /**< Write pointer */
-#else
-        uint64_t wptr                    : 8;
-        uint64_t rptr                    : 8;
-        uint64_t cycles                  : 48;
-#endif
-    } s;
-    struct cvmx_tra_cycles_since_s       cn31xx;
-    struct cvmx_tra_cycles_since_s       cn38xx;
-    struct cvmx_tra_cycles_since_s       cn38xxp2;
-    struct cvmx_tra_cycles_since_s       cn52xx;
-    struct cvmx_tra_cycles_since_s       cn52xxp1;
-    struct cvmx_tra_cycles_since_s       cn56xx;
-    struct cvmx_tra_cycles_since_s       cn56xxp1;
-    struct cvmx_tra_cycles_since_s       cn58xx;
-    struct cvmx_tra_cycles_since_s       cn58xxp1;
-} cvmx_tra_cycles_since_t;
-
-
-/**
- * cvmx_tra_cycles_since1
- *
- * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_cycles_since1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t cycles                  : 40;      /**< Cycles since the last entry was written */
-        uint64_t reserved_22_23          : 2;
-        uint64_t rptr                    : 10;      /**< Read pointer */
-        uint64_t reserved_10_11          : 2;
-        uint64_t wptr                    : 10;      /**< Write pointer */
-#else
-        uint64_t wptr                    : 10;
-        uint64_t reserved_10_11          : 2;
-        uint64_t rptr                    : 10;
-        uint64_t reserved_22_23          : 2;
-        uint64_t cycles                  : 40;
-#endif
-    } s;
-    struct cvmx_tra_cycles_since1_s      cn52xx;
-    struct cvmx_tra_cycles_since1_s      cn52xxp1;
-    struct cvmx_tra_cycles_since1_s      cn56xx;
-    struct cvmx_tra_cycles_since1_s      cn56xxp1;
-    struct cvmx_tra_cycles_since1_s      cn58xx;
-    struct cvmx_tra_cycles_since1_s      cn58xxp1;
-} cvmx_tra_cycles_since1_t;
-
-
-/**
- * cvmx_tra_filt_adr_adr
- *
- * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_filt_adr_adr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Unmasked Address
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_filt_adr_adr_s       cn31xx;
-    struct cvmx_tra_filt_adr_adr_s       cn38xx;
-    struct cvmx_tra_filt_adr_adr_s       cn38xxp2;
-    struct cvmx_tra_filt_adr_adr_s       cn52xx;
-    struct cvmx_tra_filt_adr_adr_s       cn52xxp1;
-    struct cvmx_tra_filt_adr_adr_s       cn56xx;
-    struct cvmx_tra_filt_adr_adr_s       cn56xxp1;
-    struct cvmx_tra_filt_adr_adr_s       cn58xx;
-    struct cvmx_tra_filt_adr_adr_s       cn58xxp1;
-} cvmx_tra_filt_adr_adr_t;
-
-
-/**
- * cvmx_tra_filt_adr_msk
- *
- * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_filt_adr_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Address Mask
-                                                         The combination of TRA_FILT_ADR_ADR and
-                                                         TRA_FILT_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
-                                                         is set, TRA_FILT_ADR_MSK must be zero to
-                                                         guarantee that any IOBDMAs enter the trace. */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_filt_adr_msk_s       cn31xx;
-    struct cvmx_tra_filt_adr_msk_s       cn38xx;
-    struct cvmx_tra_filt_adr_msk_s       cn38xxp2;
-    struct cvmx_tra_filt_adr_msk_s       cn52xx;
-    struct cvmx_tra_filt_adr_msk_s       cn52xxp1;
-    struct cvmx_tra_filt_adr_msk_s       cn56xx;
-    struct cvmx_tra_filt_adr_msk_s       cn56xxp1;
-    struct cvmx_tra_filt_adr_msk_s       cn58xx;
-    struct cvmx_tra_filt_adr_msk_s       cn58xxp1;
-} cvmx_tra_filt_adr_msk_t;
-
-
-/**
- * cvmx_tra_filt_cmd
- *
- * TRA_FILT_CMD = Trace Buffer Filter Command Mask
- * 
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs
- * enter the trace.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_filt_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t saa                     : 1;       /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t saa                     : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_tra_filt_cmd_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn31xx;
-    struct cvmx_tra_filt_cmd_cn31xx      cn38xx;
-    struct cvmx_tra_filt_cmd_cn31xx      cn38xxp2;
-    struct cvmx_tra_filt_cmd_s           cn52xx;
-    struct cvmx_tra_filt_cmd_s           cn52xxp1;
-    struct cvmx_tra_filt_cmd_s           cn56xx;
-    struct cvmx_tra_filt_cmd_s           cn56xxp1;
-    struct cvmx_tra_filt_cmd_s           cn58xx;
-    struct cvmx_tra_filt_cmd_s           cn58xxp1;
-} cvmx_tra_filt_cmd_t;
-
-
-/**
- * cvmx_tra_filt_did
- *
- * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_filt_did_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t illegal                 : 19;      /**< Illegal destinations */
-        uint64_t pow                     : 1;       /**< Enable tracing of requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-        uint64_t illegal2                : 3;       /**< Illegal destinations */
-        uint64_t rng                     : 1;       /**< Enable tracing of requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-        uint64_t zip                     : 1;       /**< Enable tracing of requests to ZIP
-                                                         (doorbell stores are legal) */
-        uint64_t dfa                     : 1;       /**< Enable tracing of requests to DFA
-                                                         (CSR's and operations are legal) */
-        uint64_t fpa                     : 1;       /**< Enable tracing of requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-        uint64_t key                     : 1;       /**< Enable tracing of requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-        uint64_t pci                     : 1;       /**< Enable tracing of requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-        uint64_t illegal3                : 2;       /**< Illegal destinations */
-        uint64_t mio                     : 1;       /**< Enable tracing of CIU and GPIO CSR's */
-#else
-        uint64_t mio                     : 1;
-        uint64_t illegal3                : 2;
-        uint64_t pci                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rng                     : 1;
-        uint64_t illegal2                : 3;
-        uint64_t pow                     : 1;
-        uint64_t illegal                 : 19;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_tra_filt_did_s           cn31xx;
-    struct cvmx_tra_filt_did_s           cn38xx;
-    struct cvmx_tra_filt_did_s           cn38xxp2;
-    struct cvmx_tra_filt_did_s           cn52xx;
-    struct cvmx_tra_filt_did_s           cn52xxp1;
-    struct cvmx_tra_filt_did_s           cn56xx;
-    struct cvmx_tra_filt_did_s           cn56xxp1;
-    struct cvmx_tra_filt_did_s           cn58xx;
-    struct cvmx_tra_filt_did_s           cn58xxp1;
-} cvmx_tra_filt_did_t;
-
-
-/**
- * cvmx_tra_filt_sid
- *
- * TRA_FILT_SID = Trace Buffer Filter SourceId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_filt_sid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t dwb                     : 1;       /**< Enable tracing of requests from the IOB DWB engine */
-        uint64_t iobreq                  : 1;       /**< Enable tracing of requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-        uint64_t pko                     : 1;       /**< Enable tracing of read requests from PKO */
-        uint64_t pki                     : 1;       /**< Enable tracing of write requests from PIP/IPD */
-        uint64_t pp                      : 16;      /**< Enable tracing from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-        uint64_t pp                      : 16;
-        uint64_t pki                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t iobreq                  : 1;
-        uint64_t dwb                     : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_tra_filt_sid_s           cn31xx;
-    struct cvmx_tra_filt_sid_s           cn38xx;
-    struct cvmx_tra_filt_sid_s           cn38xxp2;
-    struct cvmx_tra_filt_sid_s           cn52xx;
-    struct cvmx_tra_filt_sid_s           cn52xxp1;
-    struct cvmx_tra_filt_sid_s           cn56xx;
-    struct cvmx_tra_filt_sid_s           cn56xxp1;
-    struct cvmx_tra_filt_sid_s           cn58xx;
-    struct cvmx_tra_filt_sid_s           cn58xxp1;
-} cvmx_tra_filt_sid_t;
-
-
-/**
- * cvmx_tra_int_status
- *
- * TRA_INT_STATUS = Trace Buffer Interrupt Status
- * 
- * Description:
- *
- * Notes:
- * During a CSR write to this register, the write data is used as a mask to clear the selected status
- * bits (status'[3:0] = status[3:0] & ~write_data[3:0]).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_int_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_4_63           : 60;
-        uint64_t mcd0_thr                : 1;       /**< MCD0 full threshold interrupt status
-                                                         0=trace buffer did not generate MCD0 wire pulse
-                                                         1=trace buffer did     generate MCD0 wire pulse
-                                                           and prevents additional MCD0_THR MCD0 wire pulses */
-        uint64_t mcd0_trg                : 1;       /**< MCD0 end trigger interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt
-                                                           and prevents additional MCD0_TRG MCD0 wire pulses */
-        uint64_t ciu_thr                 : 1;       /**< CIU full threshold interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt */
-        uint64_t ciu_trg                 : 1;       /**< CIU end trigger interrupt status
-                                                         0=trace buffer did not generate interrupt
-                                                         1=trace buffer did     generate interrupt */
-#else
-        uint64_t ciu_trg                 : 1;
-        uint64_t ciu_thr                 : 1;
-        uint64_t mcd0_trg                : 1;
-        uint64_t mcd0_thr                : 1;
-        uint64_t reserved_4_63           : 60;
-#endif
-    } s;
-    struct cvmx_tra_int_status_s         cn31xx;
-    struct cvmx_tra_int_status_s         cn38xx;
-    struct cvmx_tra_int_status_s         cn38xxp2;
-    struct cvmx_tra_int_status_s         cn52xx;
-    struct cvmx_tra_int_status_s         cn52xxp1;
-    struct cvmx_tra_int_status_s         cn56xx;
-    struct cvmx_tra_int_status_s         cn56xxp1;
-    struct cvmx_tra_int_status_s         cn58xx;
-    struct cvmx_tra_int_status_s         cn58xxp1;
-} cvmx_tra_int_status_t;
-
-
-/**
- * cvmx_tra_read_dat
- *
- * TRA_READ_DAT = Trace Buffer Read Data
- * 
- * Description:
- *
- * Notes:
- * This CSR is a memory of 1024 entries.  When the trace was enabled, the read pointer was set to entry
- * 0 by hardware.  Each read to this address increments the read pointer.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_read_dat_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t data                    : 64;      /**< Trace buffer data for current entry */
-#else
-        uint64_t data                    : 64;
-#endif
-    } s;
-    struct cvmx_tra_read_dat_s           cn31xx;
-    struct cvmx_tra_read_dat_s           cn38xx;
-    struct cvmx_tra_read_dat_s           cn38xxp2;
-    struct cvmx_tra_read_dat_s           cn52xx;
-    struct cvmx_tra_read_dat_s           cn52xxp1;
-    struct cvmx_tra_read_dat_s           cn56xx;
-    struct cvmx_tra_read_dat_s           cn56xxp1;
-    struct cvmx_tra_read_dat_s           cn58xx;
-    struct cvmx_tra_read_dat_s           cn58xxp1;
-} cvmx_tra_read_dat_t;
-
-
-/**
- * cvmx_tra_trig0_adr_adr
- *
- * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig0_adr_adr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Unmasked Address
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_trig0_adr_adr_s      cn31xx;
-    struct cvmx_tra_trig0_adr_adr_s      cn38xx;
-    struct cvmx_tra_trig0_adr_adr_s      cn38xxp2;
-    struct cvmx_tra_trig0_adr_adr_s      cn52xx;
-    struct cvmx_tra_trig0_adr_adr_s      cn52xxp1;
-    struct cvmx_tra_trig0_adr_adr_s      cn56xx;
-    struct cvmx_tra_trig0_adr_adr_s      cn56xxp1;
-    struct cvmx_tra_trig0_adr_adr_s      cn58xx;
-    struct cvmx_tra_trig0_adr_adr_s      cn58xxp1;
-} cvmx_tra_trig0_adr_adr_t;
-
-
-/**
- * cvmx_tra_trig0_adr_msk
- *
- * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig0_adr_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Address Mask
-                                                         The combination of TRA_TRIG0_ADR_ADR and
-                                                         TRA_TRIG0_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_trig0_adr_msk_s      cn31xx;
-    struct cvmx_tra_trig0_adr_msk_s      cn38xx;
-    struct cvmx_tra_trig0_adr_msk_s      cn38xxp2;
-    struct cvmx_tra_trig0_adr_msk_s      cn52xx;
-    struct cvmx_tra_trig0_adr_msk_s      cn52xxp1;
-    struct cvmx_tra_trig0_adr_msk_s      cn56xx;
-    struct cvmx_tra_trig0_adr_msk_s      cn56xxp1;
-    struct cvmx_tra_trig0_adr_msk_s      cn58xx;
-    struct cvmx_tra_trig0_adr_msk_s      cn58xxp1;
-} cvmx_tra_trig0_adr_msk_t;
-
-
-/**
- * cvmx_tra_trig0_cmd
- *
- * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask
- * 
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs
- * are recognized as triggers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig0_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t saa                     : 1;       /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t saa                     : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_tra_trig0_cmd_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn31xx;
-    struct cvmx_tra_trig0_cmd_cn31xx     cn38xx;
-    struct cvmx_tra_trig0_cmd_cn31xx     cn38xxp2;
-    struct cvmx_tra_trig0_cmd_s          cn52xx;
-    struct cvmx_tra_trig0_cmd_s          cn52xxp1;
-    struct cvmx_tra_trig0_cmd_s          cn56xx;
-    struct cvmx_tra_trig0_cmd_s          cn56xxp1;
-    struct cvmx_tra_trig0_cmd_s          cn58xx;
-    struct cvmx_tra_trig0_cmd_s          cn58xxp1;
-} cvmx_tra_trig0_cmd_t;
-
-
-/**
- * cvmx_tra_trig0_did
- *
- * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig0_did_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t illegal                 : 19;      /**< Illegal destinations */
-        uint64_t pow                     : 1;       /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-        uint64_t illegal2                : 3;       /**< Illegal destinations */
-        uint64_t rng                     : 1;       /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-        uint64_t zip                     : 1;       /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-        uint64_t dfa                     : 1;       /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-        uint64_t fpa                     : 1;       /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-        uint64_t key                     : 1;       /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-        uint64_t pci                     : 1;       /**< Enable triggering on requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-        uint64_t illegal3                : 2;       /**< Illegal destinations */
-        uint64_t mio                     : 1;       /**< Enable triggering on CIU and GPIO CSR's */
-#else
-        uint64_t mio                     : 1;
-        uint64_t illegal3                : 2;
-        uint64_t pci                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rng                     : 1;
-        uint64_t illegal2                : 3;
-        uint64_t pow                     : 1;
-        uint64_t illegal                 : 19;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_tra_trig0_did_s          cn31xx;
-    struct cvmx_tra_trig0_did_s          cn38xx;
-    struct cvmx_tra_trig0_did_s          cn38xxp2;
-    struct cvmx_tra_trig0_did_s          cn52xx;
-    struct cvmx_tra_trig0_did_s          cn52xxp1;
-    struct cvmx_tra_trig0_did_s          cn56xx;
-    struct cvmx_tra_trig0_did_s          cn56xxp1;
-    struct cvmx_tra_trig0_did_s          cn58xx;
-    struct cvmx_tra_trig0_did_s          cn58xxp1;
-} cvmx_tra_trig0_did_t;
-
-
-/**
- * cvmx_tra_trig0_sid
- *
- * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig0_sid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t dwb                     : 1;       /**< Enable triggering on requests from the IOB DWB engine */
-        uint64_t iobreq                  : 1;       /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-        uint64_t pko                     : 1;       /**< Enable triggering on read requests from PKO */
-        uint64_t pki                     : 1;       /**< Enable triggering on write requests from PIP/IPD */
-        uint64_t pp                      : 16;      /**< Enable triggering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-        uint64_t pp                      : 16;
-        uint64_t pki                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t iobreq                  : 1;
-        uint64_t dwb                     : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_tra_trig0_sid_s          cn31xx;
-    struct cvmx_tra_trig0_sid_s          cn38xx;
-    struct cvmx_tra_trig0_sid_s          cn38xxp2;
-    struct cvmx_tra_trig0_sid_s          cn52xx;
-    struct cvmx_tra_trig0_sid_s          cn52xxp1;
-    struct cvmx_tra_trig0_sid_s          cn56xx;
-    struct cvmx_tra_trig0_sid_s          cn56xxp1;
-    struct cvmx_tra_trig0_sid_s          cn58xx;
-    struct cvmx_tra_trig0_sid_s          cn58xxp1;
-} cvmx_tra_trig0_sid_t;
-
-
-/**
- * cvmx_tra_trig1_adr_adr
- *
- * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig1_adr_adr_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Unmasked Address
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_trig1_adr_adr_s      cn31xx;
-    struct cvmx_tra_trig1_adr_adr_s      cn38xx;
-    struct cvmx_tra_trig1_adr_adr_s      cn38xxp2;
-    struct cvmx_tra_trig1_adr_adr_s      cn52xx;
-    struct cvmx_tra_trig1_adr_adr_s      cn52xxp1;
-    struct cvmx_tra_trig1_adr_adr_s      cn56xx;
-    struct cvmx_tra_trig1_adr_adr_s      cn56xxp1;
-    struct cvmx_tra_trig1_adr_adr_s      cn58xx;
-    struct cvmx_tra_trig1_adr_adr_s      cn58xxp1;
-} cvmx_tra_trig1_adr_adr_t;
-
-
-/**
- * cvmx_tra_trig1_adr_msk
- *
- * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig1_adr_msk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t adr                     : 36;      /**< Address Mask
-                                                         The combination of TRA_TRIG1_ADR_ADR and
-                                                         TRA_TRIG1_ADR_MSK is a masked address to
-                                                         enable tracing of only those commands whose
-                                                         masked address matches.  When a mask bit is not
-                                                         set, the corresponding address bits are assumed
-                                                         to match.  Also, note that IOBDMAs do not have
-                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
-                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
-                                                         guarantee that any IOBDMAs are recognized as
-                                                         triggers. */
-#else
-        uint64_t adr                     : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_tra_trig1_adr_msk_s      cn31xx;
-    struct cvmx_tra_trig1_adr_msk_s      cn38xx;
-    struct cvmx_tra_trig1_adr_msk_s      cn38xxp2;
-    struct cvmx_tra_trig1_adr_msk_s      cn52xx;
-    struct cvmx_tra_trig1_adr_msk_s      cn52xxp1;
-    struct cvmx_tra_trig1_adr_msk_s      cn56xx;
-    struct cvmx_tra_trig1_adr_msk_s      cn56xxp1;
-    struct cvmx_tra_trig1_adr_msk_s      cn58xx;
-    struct cvmx_tra_trig1_adr_msk_s      cn58xxp1;
-} cvmx_tra_trig1_adr_msk_t;
-
-
-/**
- * cvmx_tra_trig1_cmd
- *
- * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask
- * 
- * Description:
- *
- * Notes:
- * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
- * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs
- * are recognized as triggers.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig1_cmd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_17_63          : 47;
-        uint64_t saa                     : 1;       /**< Enable SAA     tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t saa                     : 1;
-        uint64_t reserved_17_63          : 47;
-#endif
-    } s;
-    struct cvmx_tra_trig1_cmd_cn31xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_16_63          : 48;
-        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
-                                                         0=disable, 1=enable */
-        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
-                                                         0=disable, 1=enable */
-        uint64_t stt                     : 1;       /**< Enable STT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stp                     : 1;       /**< Enable STP     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stc                     : 1;       /**< Enable STC     tracing
-                                                         0=disable, 1=enable */
-        uint64_t stf                     : 1;       /**< Enable STF     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
-                                                         0=disable, 1=enable */
-        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
-                                                         0=disable, 1=enable */
-        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
-                                                         0=disable, 1=enable */
-        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
-                                                         0=disable, 1=enable */
-        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
-                                                         0=disable, 1=enable */
-#else
-        uint64_t dwb                     : 1;
-        uint64_t pl2                     : 1;
-        uint64_t psl1                    : 1;
-        uint64_t ldd                     : 1;
-        uint64_t ldi                     : 1;
-        uint64_t ldt                     : 1;
-        uint64_t stf                     : 1;
-        uint64_t stc                     : 1;
-        uint64_t stp                     : 1;
-        uint64_t stt                     : 1;
-        uint64_t iobld8                  : 1;
-        uint64_t iobld16                 : 1;
-        uint64_t iobld32                 : 1;
-        uint64_t iobld64                 : 1;
-        uint64_t iobst                   : 1;
-        uint64_t iobdma                  : 1;
-        uint64_t reserved_16_63          : 48;
-#endif
-    } cn31xx;
-    struct cvmx_tra_trig1_cmd_cn31xx     cn38xx;
-    struct cvmx_tra_trig1_cmd_cn31xx     cn38xxp2;
-    struct cvmx_tra_trig1_cmd_s          cn52xx;
-    struct cvmx_tra_trig1_cmd_s          cn52xxp1;
-    struct cvmx_tra_trig1_cmd_s          cn56xx;
-    struct cvmx_tra_trig1_cmd_s          cn56xxp1;
-    struct cvmx_tra_trig1_cmd_s          cn58xx;
-    struct cvmx_tra_trig1_cmd_s          cn58xxp1;
-} cvmx_tra_trig1_cmd_t;
-
-
-/**
- * cvmx_tra_trig1_did
- *
- * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig1_did_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_32_63          : 32;
-        uint64_t illegal                 : 19;      /**< Illegal destinations */
-        uint64_t pow                     : 1;       /**< Enable triggering on requests to POW
-                                                         (get work, add work, status/memory/index
-                                                         loads, NULLRd loads, CSR's) */
-        uint64_t illegal2                : 3;       /**< Illegal destinations */
-        uint64_t rng                     : 1;       /**< Enable triggering on requests to RNG
-                                                         (loads/IOBDMA's are legal) */
-        uint64_t zip                     : 1;       /**< Enable triggering on requests to ZIP
-                                                         (doorbell stores are legal) */
-        uint64_t dfa                     : 1;       /**< Enable triggering on requests to DFA
-                                                         (CSR's and operations are legal) */
-        uint64_t fpa                     : 1;       /**< Enable triggering on requests to FPA
-                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
-        uint64_t key                     : 1;       /**< Enable triggering on requests to KEY memory
-                                                         (loads/IOBDMA's/stores are legal) */
-        uint64_t pci                     : 1;       /**< Enable triggering on requests to PCI and RSL-type
-                                                         CSR's (RSL CSR's, PCI bus operations, PCI
-                                                         CSR's) */
-        uint64_t illegal3                : 2;       /**< Illegal destinations */
-        uint64_t mio                     : 1;       /**< Enable triggering on CIU and GPIO CSR's */
-#else
-        uint64_t mio                     : 1;
-        uint64_t illegal3                : 2;
-        uint64_t pci                     : 1;
-        uint64_t key                     : 1;
-        uint64_t fpa                     : 1;
-        uint64_t dfa                     : 1;
-        uint64_t zip                     : 1;
-        uint64_t rng                     : 1;
-        uint64_t illegal2                : 3;
-        uint64_t pow                     : 1;
-        uint64_t illegal                 : 19;
-        uint64_t reserved_32_63          : 32;
-#endif
-    } s;
-    struct cvmx_tra_trig1_did_s          cn31xx;
-    struct cvmx_tra_trig1_did_s          cn38xx;
-    struct cvmx_tra_trig1_did_s          cn38xxp2;
-    struct cvmx_tra_trig1_did_s          cn52xx;
-    struct cvmx_tra_trig1_did_s          cn52xxp1;
-    struct cvmx_tra_trig1_did_s          cn56xx;
-    struct cvmx_tra_trig1_did_s          cn56xxp1;
-    struct cvmx_tra_trig1_did_s          cn58xx;
-    struct cvmx_tra_trig1_did_s          cn58xxp1;
-} cvmx_tra_trig1_did_t;
-
-
-/**
- * cvmx_tra_trig1_sid
- *
- * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask
- * 
- * Description:
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_tra_trig1_sid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t dwb                     : 1;       /**< Enable triggering on requests from the IOB DWB engine */
-        uint64_t iobreq                  : 1;       /**< Enable triggering on requests from FPA,TIM,DFA,
-                                                         PCI,ZIP,POW, and PKO (writes) */
-        uint64_t pko                     : 1;       /**< Enable triggering on read requests from PKO */
-        uint64_t pki                     : 1;       /**< Enable triggering on write requests from PIP/IPD */
-        uint64_t pp                      : 16;      /**< Enable trigering from PP[N] with matching SourceID
-                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
-#else
-        uint64_t pp                      : 16;
-        uint64_t pki                     : 1;
-        uint64_t pko                     : 1;
-        uint64_t iobreq                  : 1;
-        uint64_t dwb                     : 1;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_tra_trig1_sid_s          cn31xx;
-    struct cvmx_tra_trig1_sid_s          cn38xx;
-    struct cvmx_tra_trig1_sid_s          cn38xxp2;
-    struct cvmx_tra_trig1_sid_s          cn52xx;
-    struct cvmx_tra_trig1_sid_s          cn52xxp1;
-    struct cvmx_tra_trig1_sid_s          cn56xx;
-    struct cvmx_tra_trig1_sid_s          cn56xxp1;
-    struct cvmx_tra_trig1_sid_s          cn58xx;
-    struct cvmx_tra_trig1_sid_s          cn58xxp1;
-} cvmx_tra_trig1_sid_t;
-
-
-/**
- * cvmx_usbc#_daint
- *
- * Device All Endpoints Interrupt Register (DAINT)
- * 
- * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register
- * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints
- * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively).
- * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
- * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt
- * bits are used. Bits in this register are set and cleared when the application sets and clears
- * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_daint_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t outepint                : 16;      /**< OUT Endpoint Interrupt Bits (OutEPInt)
-                                                         One bit per OUT endpoint:
-                                                         Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
-        uint32_t inepint                 : 16;      /**< IN Endpoint Interrupt Bits (InEpInt)
-                                                         One bit per IN Endpoint:
-                                                         Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */
-#else
-        uint32_t inepint                 : 16;
-        uint32_t outepint                : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_daint_s            cn30xx;
-    struct cvmx_usbcx_daint_s            cn31xx;
-    struct cvmx_usbcx_daint_s            cn50xx;
-    struct cvmx_usbcx_daint_s            cn52xx;
-    struct cvmx_usbcx_daint_s            cn52xxp1;
-    struct cvmx_usbcx_daint_s            cn56xx;
-    struct cvmx_usbcx_daint_s            cn56xxp1;
-} cvmx_usbcx_daint_t;
-
-
-/**
- * cvmx_usbc#_daintmsk
- *
- * Device All Endpoints Interrupt Mask Register (DAINTMSK)
- * 
- * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register
- * to interrupt the application when an event occurs on a device endpoint. However, the Device
- * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
- * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_daintmsk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t outepmsk                : 16;      /**< OUT EP Interrupt Mask Bits (OutEpMsk)
-                                                         One per OUT Endpoint:
-                                                         Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
-        uint32_t inepmsk                 : 16;      /**< IN EP Interrupt Mask Bits (InEpMsk)
-                                                         One bit per IN Endpoint:
-                                                         Bit 0 for IN EP 0, bit 15 for IN EP 15 */
-#else
-        uint32_t inepmsk                 : 16;
-        uint32_t outepmsk                : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_daintmsk_s         cn30xx;
-    struct cvmx_usbcx_daintmsk_s         cn31xx;
-    struct cvmx_usbcx_daintmsk_s         cn50xx;
-    struct cvmx_usbcx_daintmsk_s         cn52xx;
-    struct cvmx_usbcx_daintmsk_s         cn52xxp1;
-    struct cvmx_usbcx_daintmsk_s         cn56xx;
-    struct cvmx_usbcx_daintmsk_s         cn56xxp1;
-} cvmx_usbcx_daintmsk_t;
-
-
-/**
- * cvmx_usbc#_dcfg
- *
- * Device Configuration Register (DCFG)
- * 
- * This register configures the core in Device mode after power-on or after certain control
- * commands or enumeration. Do not make changes to this register after initial programming.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_23_31          : 9;
-        uint32_t epmiscnt                : 5;       /**< IN Endpoint Mismatch Count (EPMisCnt)
-                                                         The application programs this filed with a count that determines
-                                                         when the core generates an Endpoint Mismatch interrupt
-                                                         (GINTSTS.EPMis). The core loads this value into an internal
-                                                         counter and decrements it. The counter is reloaded whenever
-                                                         there is a match or when the counter expires. The width of this
-                                                         counter depends on the depth of the Token Queue. */
-        uint32_t reserved_13_17          : 5;
-        uint32_t perfrint                : 2;       /**< Periodic Frame Interval (PerFrInt)
-                                                         Indicates the time within a (micro)frame at which the application
-                                                         must be notified using the End Of Periodic Frame Interrupt. This
-                                                         can be used to determine if all the isochronous traffic for that
-                                                         (micro)frame is complete.
-                                                         * 2'b00: 80% of the (micro)frame interval
-                                                         * 2'b01: 85%
-                                                         * 2'b10: 90%
-                                                         * 2'b11: 95% */
-        uint32_t devaddr                 : 7;       /**< Device Address (DevAddr)
-                                                         The application must program this field after every SetAddress
-                                                         control command. */
-        uint32_t reserved_3_3            : 1;
-        uint32_t nzstsouthshk            : 1;       /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
-                                                         The application can use this field to select the handshake the
-                                                         core sends on receiving a nonzero-length data packet during
-                                                         the OUT transaction of a control transfer's Status stage.
-                                                         * 1'b1: Send a STALL handshake on a nonzero-length status
-                                                                 OUT transaction and do not send the received OUT packet to
-                                                                 the application.
-                                                         * 1'b0: Send the received OUT packet to the application (zero-
-                                                                 length or nonzero-length) and send a handshake based on
-                                                                 the NAK and STALL bits for the endpoint in the Device
-                                                                 Endpoint Control register. */
-        uint32_t devspd                  : 2;       /**< Device Speed (DevSpd)
-                                                         Indicates the speed at which the application requires the core to
-                                                         enumerate, or the maximum speed the application can support.
-                                                         However, the actual bus speed is determined only after the
-                                                         chirp sequence is completed, and is based on the speed of the
-                                                         USB host to which the core is connected. See "Device
-                                                         Initialization" on page 249 for details.
-                                                         * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
-                                                         * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
-                                                         * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
-                                                                  you select 6 MHz LS mode, you must do a soft reset.
-                                                         * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */
-#else
-        uint32_t devspd                  : 2;
-        uint32_t nzstsouthshk            : 1;
-        uint32_t reserved_3_3            : 1;
-        uint32_t devaddr                 : 7;
-        uint32_t perfrint                : 2;
-        uint32_t reserved_13_17          : 5;
-        uint32_t epmiscnt                : 5;
-        uint32_t reserved_23_31          : 9;
-#endif
-    } s;
-    struct cvmx_usbcx_dcfg_s             cn30xx;
-    struct cvmx_usbcx_dcfg_s             cn31xx;
-    struct cvmx_usbcx_dcfg_s             cn50xx;
-    struct cvmx_usbcx_dcfg_s             cn52xx;
-    struct cvmx_usbcx_dcfg_s             cn52xxp1;
-    struct cvmx_usbcx_dcfg_s             cn56xx;
-    struct cvmx_usbcx_dcfg_s             cn56xxp1;
-} cvmx_usbcx_dcfg_t;
-
-
-/**
- * cvmx_usbc#_dctl
- *
- * Device Control Register (DCTL)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_12_31          : 20;
-        uint32_t pwronprgdone            : 1;       /**< Power-On Programming Done (PWROnPrgDone)
-                                                         The application uses this bit to indicate that register
-                                                         programming is completed after a wake-up from Power Down
-                                                         mode. For more information, see "Device Mode Suspend and
-                                                         Resume With Partial Power-Down" on page 357. */
-        uint32_t cgoutnak                : 1;       /**< Clear Global OUT NAK (CGOUTNak)
-                                                         A write to this field clears the Global OUT NAK. */
-        uint32_t sgoutnak                : 1;       /**< Set Global OUT NAK (SGOUTNak)
-                                                         A write to this field sets the Global OUT NAK.
-                                                         The application uses this bit to send a NAK handshake on all
-                                                         OUT endpoints.
-                                                         The application should set the this bit only after making sure
-                                                         that the Global OUT NAK Effective bit in the Core Interrupt
-                                                         Register (GINTSTS.GOUTNakEff) is cleared. */
-        uint32_t cgnpinnak               : 1;       /**< Clear Global Non-Periodic IN NAK (CGNPInNak)
-                                                         A write to this field clears the Global Non-Periodic IN NAK. */
-        uint32_t sgnpinnak               : 1;       /**< Set Global Non-Periodic IN NAK (SGNPInNak)
-                                                         A write to this field sets the Global Non-Periodic IN NAK.The
-                                                         application uses this bit to send a NAK handshake on all non-
-                                                         periodic IN endpoints. The core can also set this bit when a
-                                                         timeout condition is detected on a non-periodic endpoint.
-                                                         The application should set this bit only after making sure that
-                                                         the Global IN NAK Effective bit in the Core Interrupt Register
-                                                         (GINTSTS.GINNakEff) is cleared. */
-        uint32_t tstctl                  : 3;       /**< Test Control (TstCtl)
-                                                         * 3'b000: Test mode disabled
-                                                         * 3'b001: Test_J mode
-                                                         * 3'b010: Test_K mode
-                                                         * 3'b011: Test_SE0_NAK mode
-                                                         * 3'b100: Test_Packet mode
-                                                         * 3'b101: Test_Force_Enable
-                                                         * Others: Reserved */
-        uint32_t goutnaksts              : 1;       /**< Global OUT NAK Status (GOUTNakSts)
-                                                         * 1'b0: A handshake is sent based on the FIFO Status and the
-                                                                 NAK and STALL bit settings.
-                                                         * 1'b1: No data is written to the RxFIFO, irrespective of space
-                                                                 availability. Sends a NAK handshake on all packets, except
-                                                                 on SETUP transactions. All isochronous OUT packets are
-                                                                 dropped. */
-        uint32_t gnpinnaksts             : 1;       /**< Global Non-Periodic IN NAK Status (GNPINNakSts)
-                                                         * 1'b0: A handshake is sent out based on the data availability
-                                                                 in the transmit FIFO.
-                                                         * 1'b1: A NAK handshake is sent out on all non-periodic IN
-                                                                 endpoints, irrespective of the data availability in the transmit
-                                                                 FIFO. */
-        uint32_t sftdiscon               : 1;       /**< Soft Disconnect (SftDiscon)
-                                                         The application uses this bit to signal the O2P USB core to do a
-                                                         soft disconnect. As long as this bit is set, the host will not see
-                                                         that the device is connected, and the device will not receive
-                                                         signals on the USB. The core stays in the disconnected state
-                                                         until the application clears this bit.
-                                                         The minimum duration for which the core must keep this bit set
-                                                         is specified in Minimum Duration for Soft Disconnect  .
-                                                         * 1'b0: Normal operation. When this bit is cleared after a soft
-                                                         disconnect, the core drives the phy_opmode_o signal on the
-                                                         UTMI+ to 2'b00, which generates a device connect event to
-                                                         the USB host. When the device is reconnected, the USB host
-                                                         restarts device enumeration.
-                                                         * 1'b1: The core drives the phy_opmode_o signal on the
-                                                         UTMI+ to 2'b01, which generates a device disconnect event
-                                                         to the USB host. */
-        uint32_t rmtwkupsig              : 1;       /**< Remote Wakeup Signaling (RmtWkUpSig)
-                                                         When the application sets this bit, the core initiates remote
-                                                         signaling to wake up the USB host.The application must set this
-                                                         bit to get the core out of Suspended state and must clear this bit
-                                                         after the core comes out of Suspended state. */
-#else
-        uint32_t rmtwkupsig              : 1;
-        uint32_t sftdiscon               : 1;
-        uint32_t gnpinnaksts             : 1;
-        uint32_t goutnaksts              : 1;
-        uint32_t tstctl                  : 3;
-        uint32_t sgnpinnak               : 1;
-        uint32_t cgnpinnak               : 1;
-        uint32_t sgoutnak                : 1;
-        uint32_t cgoutnak                : 1;
-        uint32_t pwronprgdone            : 1;
-        uint32_t reserved_12_31          : 20;
-#endif
-    } s;
-    struct cvmx_usbcx_dctl_s             cn30xx;
-    struct cvmx_usbcx_dctl_s             cn31xx;
-    struct cvmx_usbcx_dctl_s             cn50xx;
-    struct cvmx_usbcx_dctl_s             cn52xx;
-    struct cvmx_usbcx_dctl_s             cn52xxp1;
-    struct cvmx_usbcx_dctl_s             cn56xx;
-    struct cvmx_usbcx_dctl_s             cn56xxp1;
-} cvmx_usbcx_dctl_t;
-
-
-/**
- * cvmx_usbc#_diepctl#
- *
- * Device IN Endpoint-n Control Register (DIEPCTLn)
- * 
- * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_diepctlx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t epena                   : 1;       /**< Endpoint Enable (EPEna)
-                                                         Indicates that data is ready to be transmitted on the endpoint.
-                                                         The core clears this bit before setting any of the following
-                                                         interrupts on this endpoint:
-                                                         * Endpoint Disabled
-                                                         * Transfer Completed */
-        uint32_t epdis                   : 1;       /**< Endpoint Disable (EPDis)
-                                                         The application sets this bit to stop transmitting data on an
-                                                         endpoint, even before the transfer for that endpoint is complete.
-                                                         The application must wait for the Endpoint Disabled interrupt
-                                                         before treating the endpoint as disabled. The core clears this bit
-                                                         before setting the Endpoint Disabled Interrupt. The application
-                                                         should set this bit only if Endpoint Enable is already set for this
-                                                         endpoint. */
-        uint32_t setd1pid                : 1;       /**< For Interrupt/BULK enpoints:
-                                                          Set DATA1 PID (SetD1PID)
-                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
-                                                          this register to DATA1.
-                                                         For Isochronous endpoints:
-                                                          Set Odd (micro)frame (SetOddFr)
-                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
-                                                          field to odd (micro)frame. */
-        uint32_t setd0pid                : 1;       /**< For Interrupt/BULK enpoints:
-                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
-                                                          this register to DATA0.
-                                                         For Isochronous endpoints:
-                                                          Set Odd (micro)frame (SetEvenFr)
-                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
-                                                          field to even (micro)frame. */
-        uint32_t snak                    : 1;       /**< Set NAK (SNAK)
-                                                         A write to this bit sets the NAK bit for the endpoint.
-                                                         Using this bit, the application can control the transmission of
-                                                         NAK handshakes on an endpoint. The core can also set this bit
-                                                         for an endpoint after a SETUP packet is received on the
-                                                         endpoint. */
-        uint32_t cnak                    : 1;       /**< Clear NAK (CNAK)
-                                                         A write to this bit clears the NAK bit for the endpoint. */
-        uint32_t txfnum                  : 4;       /**< TxFIFO Number (TxFNum)
-                                                         Non-periodic endpoints must set this bit to zero.  Periodic
-                                                         endpoints must map this to the corresponding Periodic TxFIFO
-                                                         number.
-                                                         * 4'h0: Non-Periodic TxFIFO
-                                                         * Others: Specified Periodic TxFIFO number */
-        uint32_t stall                   : 1;       /**< STALL Handshake (Stall)
-                                                         For non-control, non-isochronous endpoints:
-                                                          The application sets this bit to stall all tokens from the USB host
-                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
-                                                          Global OUT NAK is set along with this bit, the STALL bit takes
-                                                          priority.  Only the application can clear this bit, never the core.
-                                                         For control endpoints:
-                                                          The application can only set this bit, and the core clears it, when
-                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
-                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
-                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
-                                                          the core always responds to SETUP data packets with an ACK handshake. */
-        uint32_t reserved_20_20          : 1;
-        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
-                                                         This is the transfer type supported by this logical endpoint.
-                                                         * 2'b00: Control
-                                                         * 2'b01: Isochronous
-                                                         * 2'b10: Bulk
-                                                         * 2'b11: Interrupt */
-        uint32_t naksts                  : 1;       /**< NAK Status (NAKSts)
-                                                         Indicates the following:
-                                                         * 1'b0: The core is transmitting non-NAK handshakes based
-                                                                 on the FIFO status
-                                                         * 1'b1: The core is transmitting NAK handshakes on this
-                                                                 endpoint.
-                                                         When either the application or the core sets this bit:
-                                                         * For non-isochronous IN endpoints: The core stops
-                                                           transmitting any data on an IN endpoint, even if data is
-                                                           available in the TxFIFO.
-                                                         * For isochronous IN endpoints: The core sends out a zero-
-                                                           length data packet, even if data is available in the TxFIFO.
-                                                         Irrespective of this bit's setting, the core always responds to
-                                                         SETUP data packets with an ACK handshake. */
-        uint32_t dpid                    : 1;       /**< For interrupt/bulk IN and OUT endpoints:
-                                                          Endpoint Data PID (DPID)
-                                                          Contains the PID of the packet to be received or transmitted on
-                                                          this endpoint.  The application should program the PID of the first
-                                                          packet to be received or transmitted on this endpoint, after the
-                                                          endpoint is activated.  Applications use the SetD1PID and
-                                                          SetD0PID fields of this register to program either DATA0 or
-                                                          DATA1 PID.
-                                                          * 1'b0: DATA0
-                                                          * 1'b1: DATA1
-                                                         For isochronous IN and OUT endpoints:
-                                                          Even/Odd (Micro)Frame (EO_FrNum)
-                                                          Indicates the (micro)frame number in which the core transmits/
-                                                          receives isochronous data for this endpoint.  The application
-                                                          should program the even/odd (micro) frame number in which it
-                                                          intends to transmit/receive isochronous data for this endpoint
-                                                          using the SetEvnFr and SetOddFr fields in this register.
-                                                          * 1'b0: Even (micro)frame
-                                                          * 1'b1: Odd (micro)frame */
-        uint32_t usbactep                : 1;       /**< USB Active Endpoint (USBActEP)
-                                                         Indicates whether this endpoint is active in the current
-                                                         configuration and interface.  The core clears this bit for all
-                                                         endpoints (other than EP 0) after detecting a USB reset.  After
-                                                         receiving the SetConfiguration and SetInterface commands, the
-                                                         application must program endpoint registers accordingly and set
-                                                         this bit. */
-        uint32_t nextep                  : 4;       /**< Next Endpoint (NextEp)
-                                                         Applies to non-periodic IN endpoints only.
-                                                         Indicates the endpoint number to be fetched after the data for
-                                                         the current endpoint is fetched. The core can access this field,
-                                                         even when the Endpoint Enable (EPEna) bit is not set. This
-                                                         field is not valid in Slave mode. */
-        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
-                                                         Applies to IN and OUT endpoints.
-                                                         The application must program this field with the maximum
-                                                         packet size for the current logical endpoint.  This value is in
-                                                         bytes. */
-#else
-        uint32_t mps                     : 11;
-        uint32_t nextep                  : 4;
-        uint32_t usbactep                : 1;
-        uint32_t dpid                    : 1;
-        uint32_t naksts                  : 1;
-        uint32_t eptype                  : 2;
-        uint32_t reserved_20_20          : 1;
-        uint32_t stall                   : 1;
-        uint32_t txfnum                  : 4;
-        uint32_t cnak                    : 1;
-        uint32_t snak                    : 1;
-        uint32_t setd0pid                : 1;
-        uint32_t setd1pid                : 1;
-        uint32_t epdis                   : 1;
-        uint32_t epena                   : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_diepctlx_s         cn30xx;
-    struct cvmx_usbcx_diepctlx_s         cn31xx;
-    struct cvmx_usbcx_diepctlx_s         cn50xx;
-    struct cvmx_usbcx_diepctlx_s         cn52xx;
-    struct cvmx_usbcx_diepctlx_s         cn52xxp1;
-    struct cvmx_usbcx_diepctlx_s         cn56xx;
-    struct cvmx_usbcx_diepctlx_s         cn56xxp1;
-} cvmx_usbcx_diepctlx_t;
-
-
-/**
- * cvmx_usbc#_diepint#
- *
- * Device Endpoint-n Interrupt Register (DIEPINTn)
- * 
- * This register indicates the status of an endpoint with respect to
- * USB- and AHB-related events. The application must read this register
- * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
- * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt,
- * respectively) is set. Before the application can read this register,
- * it must first read the Device All Endpoints Interrupt (DAINT) register
- * to get the exact endpoint number for the Device Endpoint-n Interrupt
- * register. The application must clear the appropriate bit in this register
- * to clear the corresponding bits in the DAINT and GINTSTS registers.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_diepintx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_7_31           : 25;
-        uint32_t inepnakeff              : 1;       /**< IN Endpoint NAK Effective (INEPNakEff)
-                                                         Applies to periodic IN endpoints only.
-                                                         Indicates that the IN endpoint NAK bit set by the application has
-                                                         taken effect in the core. This bit can be cleared when the
-                                                         application clears the IN endpoint NAK by writing to
-                                                         DIEPCTLn.CNAK.
-                                                         This interrupt indicates that the core has sampled the NAK bit
-                                                         set (either by the application or by the core).
-                                                         This interrupt does not necessarily mean that a NAK handshake
-                                                         is sent on the USB. A STALL bit takes priority over a NAK bit. */
-        uint32_t intknepmis              : 1;       /**< IN Token Received with EP Mismatch (INTknEPMis)
-                                                         Applies to non-periodic IN endpoints only.
-                                                         Indicates that the data in the top of the non-periodic TxFIFO
-                                                         belongs to an endpoint other than the one for which the IN
-                                                         token was received. This interrupt is asserted on the endpoint
-                                                         for which the IN token was received. */
-        uint32_t intkntxfemp             : 1;       /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-                                                         Applies only to non-periodic IN endpoints.
-                                                         Indicates that an IN token was received when the associated
-                                                         TxFIFO (periodic/non-periodic) was empty. This interrupt is
-                                                         asserted on the endpoint for which the IN token was received. */
-        uint32_t timeout                 : 1;       /**< Timeout Condition (TimeOUT)
-                                                         Applies to non-isochronous IN endpoints only.
-                                                         Indicates that the core has detected a timeout condition on the
-                                                         USB for the last IN token on this endpoint. */
-        uint32_t ahberr                  : 1;       /**< AHB Error (AHBErr)
-                                                         This is generated only in Internal DMA mode when there is an
-                                                         AHB error during an AHB read/write. The application can read
-                                                         the corresponding endpoint DMA address register to get the
-                                                         error address. */
-        uint32_t epdisbld                : 1;       /**< Endpoint Disabled Interrupt (EPDisbld)
-                                                         This bit indicates that the endpoint is disabled per the
-                                                         application's request. */
-        uint32_t xfercompl               : 1;       /**< Transfer Completed Interrupt (XferCompl)
-                                                         Indicates that the programmed transfer is complete on the AHB
-                                                         as well as on the USB, for this endpoint. */
-#else
-        uint32_t xfercompl               : 1;
-        uint32_t epdisbld                : 1;
-        uint32_t ahberr                  : 1;
-        uint32_t timeout                 : 1;
-        uint32_t intkntxfemp             : 1;
-        uint32_t intknepmis              : 1;
-        uint32_t inepnakeff              : 1;
-        uint32_t reserved_7_31           : 25;
-#endif
-    } s;
-    struct cvmx_usbcx_diepintx_s         cn30xx;
-    struct cvmx_usbcx_diepintx_s         cn31xx;
-    struct cvmx_usbcx_diepintx_s         cn50xx;
-    struct cvmx_usbcx_diepintx_s         cn52xx;
-    struct cvmx_usbcx_diepintx_s         cn52xxp1;
-    struct cvmx_usbcx_diepintx_s         cn56xx;
-    struct cvmx_usbcx_diepintx_s         cn56xxp1;
-} cvmx_usbcx_diepintx_t;
-
-
-/**
- * cvmx_usbc#_diepmsk
- *
- * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK)
- * 
- * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers
- * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
- * for a specific status in the DIEPINTn register can be masked by writing to the corresponding
- * bit in this register. Status bits are masked by default.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_diepmsk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_7_31           : 25;
-        uint32_t inepnakeffmsk           : 1;       /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
-        uint32_t intknepmismsk           : 1;       /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
-        uint32_t intkntxfempmsk          : 1;       /**< IN Token Received When TxFIFO Empty Mask
-                                                         (INTknTXFEmpMsk) */
-        uint32_t timeoutmsk              : 1;       /**< Timeout Condition Mask (TimeOUTMsk)
-                                                         (Non-isochronous endpoints) */
-        uint32_t ahberrmsk               : 1;       /**< AHB Error Mask (AHBErrMsk) */
-        uint32_t epdisbldmsk             : 1;       /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
-        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Interrupt Mask (XferComplMsk) */
-#else
-        uint32_t xfercomplmsk            : 1;
-        uint32_t epdisbldmsk             : 1;
-        uint32_t ahberrmsk               : 1;
-        uint32_t timeoutmsk              : 1;
-        uint32_t intkntxfempmsk          : 1;
-        uint32_t intknepmismsk           : 1;
-        uint32_t inepnakeffmsk           : 1;
-        uint32_t reserved_7_31           : 25;
-#endif
-    } s;
-    struct cvmx_usbcx_diepmsk_s          cn30xx;
-    struct cvmx_usbcx_diepmsk_s          cn31xx;
-    struct cvmx_usbcx_diepmsk_s          cn50xx;
-    struct cvmx_usbcx_diepmsk_s          cn52xx;
-    struct cvmx_usbcx_diepmsk_s          cn52xxp1;
-    struct cvmx_usbcx_diepmsk_s          cn56xx;
-    struct cvmx_usbcx_diepmsk_s          cn56xxp1;
-} cvmx_usbcx_diepmsk_t;
-
-
-/**
- * cvmx_usbc#_dieptsiz#
- *
- * Device Endpoint-n Transfer Size Register (DIEPTSIZn)
- * 
- * The application must modify this register before enabling the endpoint.
- * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna),
- * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
- * This register is used only for endpoints other than Endpoint 0.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dieptsizx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_31_31          : 1;
-        uint32_t mc                      : 2;       /**< Multi Count (MC)
-                                                         Applies to IN endpoints only.
-                                                         For periodic IN endpoints, this field indicates the number of
-                                                         packets that must be transmitted per microframe on the USB.
-                                                         The core uses this field to calculate the data PID for
-                                                         isochronous IN endpoints.
-                                                         * 2'b01: 1 packet
-                                                         * 2'b10: 2 packets
-                                                         * 2'b11: 3 packets
-                                                         For non-periodic IN endpoints, this field is valid only in Internal
-                                                         DMA mode. It specifies the number of packets the core should
-                                                         fetch for an IN endpoint before it switches to the endpoint
-                                                         pointed to by the Next Endpoint field of the Device Endpoint-n
-                                                         Control register (DIEPCTLn.NextEp) */
-        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
-                                                         Indicates the total number of USB packets that constitute the
-                                                         Transfer Size amount of data for this endpoint.
-                                                         IN Endpoints: This field is decremented every time a packet
-                                                         (maximum size or short packet) is read from the TxFIFO. */
-        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
-                                                         This field contains the transfer size in bytes for the current
-                                                         endpoint.
-                                                         The core only interrupts the application after it has exhausted
-                                                         the transfer size amount of data. The transfer size can be set to
-                                                         the maximum packet size of the endpoint, to be interrupted at
-                                                         the end of each packet.
-                                                         IN Endpoints: The core decrements this field every time a
-                                                         packet from the external memory is written to the TxFIFO. */
-#else
-        uint32_t xfersize                : 19;
-        uint32_t pktcnt                  : 10;
-        uint32_t mc                      : 2;
-        uint32_t reserved_31_31          : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_dieptsizx_s        cn30xx;
-    struct cvmx_usbcx_dieptsizx_s        cn31xx;
-    struct cvmx_usbcx_dieptsizx_s        cn50xx;
-    struct cvmx_usbcx_dieptsizx_s        cn52xx;
-    struct cvmx_usbcx_dieptsizx_s        cn52xxp1;
-    struct cvmx_usbcx_dieptsizx_s        cn56xx;
-    struct cvmx_usbcx_dieptsizx_s        cn56xxp1;
-} cvmx_usbcx_dieptsizx_t;
-
-
-/**
- * cvmx_usbc#_doepctl#
- *
- * Device OUT Endpoint-n Control Register (DOEPCTLn)
- * 
- * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_doepctlx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t epena                   : 1;       /**< Endpoint Enable (EPEna)
-                                                         Indicates that the application has allocated the memory tp start
-                                                         receiving data from the USB.
-                                                         The core clears this bit before setting any of the following
-                                                         interrupts on this endpoint:
-                                                         * SETUP Phase Done
-                                                         * Endpoint Disabled
-                                                         * Transfer Completed
-                                                         For control OUT endpoints in DMA mode, this bit must be set
-                                                         to be able to transfer SETUP data packets in memory. */
-        uint32_t epdis                   : 1;       /**< Endpoint Disable (EPDis)
-                                                         The application sets this bit to stop transmitting data on an
-                                                         endpoint, even before the transfer for that endpoint is complete.
-                                                         The application must wait for the Endpoint Disabled interrupt
-                                                         before treating the endpoint as disabled. The core clears this bit
-                                                         before setting the Endpoint Disabled Interrupt. The application
-                                                         should set this bit only if Endpoint Enable is already set for this
-                                                         endpoint. */
-        uint32_t setd1pid                : 1;       /**< For Interrupt/BULK enpoints:
-                                                          Set DATA1 PID (SetD1PID)
-                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
-                                                          this register to DATA1.
-                                                         For Isochronous endpoints:
-                                                          Set Odd (micro)frame (SetOddFr)
-                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
-                                                          field to odd (micro)frame. */
-        uint32_t setd0pid                : 1;       /**< For Interrupt/BULK enpoints:
-                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
-                                                          this register to DATA0.
-                                                         For Isochronous endpoints:
-                                                          Set Odd (micro)frame (SetEvenFr)
-                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
-                                                          field to even (micro)frame. */
-        uint32_t snak                    : 1;       /**< Set NAK (SNAK)
-                                                         A write to this bit sets the NAK bit for the endpoint.
-                                                         Using this bit, the application can control the transmission of
-                                                         NAK handshakes on an endpoint. The core can also set this bit
-                                                         for an endpoint after a SETUP packet is received on the
-                                                         endpoint. */
-        uint32_t cnak                    : 1;       /**< Clear NAK (CNAK)
-                                                         A write to this bit clears the NAK bit for the endpoint. */
-        uint32_t reserved_22_25          : 4;
-        uint32_t stall                   : 1;       /**< STALL Handshake (Stall)
-                                                         For non-control, non-isochronous endpoints:
-                                                          The application sets this bit to stall all tokens from the USB host
-                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
-                                                          Global OUT NAK is set along with this bit, the STALL bit takes
-                                                          priority.  Only the application can clear this bit, never the core.
-                                                         For control endpoints:
-                                                          The application can only set this bit, and the core clears it, when
-                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
-                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
-                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
-                                                          the core always responds to SETUP data packets with an ACK handshake. */
-        uint32_t snp                     : 1;       /**< Snoop Mode (Snp)
-                                                         This bit configures the endpoint to Snoop mode.  In Snoop mode,
-                                                         the core does not check the correctness of OUT packets before
-                                                         transferring them to application memory. */
-        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
-                                                         This is the transfer type supported by this logical endpoint.
-                                                         * 2'b00: Control
-                                                         * 2'b01: Isochronous
-                                                         * 2'b10: Bulk
-                                                         * 2'b11: Interrupt */
-        uint32_t naksts                  : 1;       /**< NAK Status (NAKSts)
-                                                         Indicates the following:
-                                                         * 1'b0: The core is transmitting non-NAK handshakes based
-                                                                 on the FIFO status
-                                                         * 1'b1: The core is transmitting NAK handshakes on this
-                                                                 endpoint.
-                                                         When either the application or the core sets this bit:
-                                                         * The core stops receiving any data on an OUT endpoint, even
-                                                           if there is space in the RxFIFO to accomodate the incoming
-                                                           packet. */
-        uint32_t dpid                    : 1;       /**< For interrupt/bulk IN and OUT endpoints:
-                                                          Endpoint Data PID (DPID)
-                                                          Contains the PID of the packet to be received or transmitted on
-                                                          this endpoint.  The application should program the PID of the first
-                                                          packet to be received or transmitted on this endpoint, after the
-                                                          endpoint is activated.  Applications use the SetD1PID and
-                                                          SetD0PID fields of this register to program either DATA0 or
-                                                          DATA1 PID.
-                                                          * 1'b0: DATA0
-                                                          * 1'b1: DATA1
-                                                         For isochronous IN and OUT endpoints:
-                                                          Even/Odd (Micro)Frame (EO_FrNum)
-                                                          Indicates the (micro)frame number in which the core transmits/
-                                                          receives isochronous data for this endpoint.  The application
-                                                          should program the even/odd (micro) frame number in which it
-                                                          intends to transmit/receive isochronous data for this endpoint
-                                                          using the SetEvnFr and SetOddFr fields in this register.
-                                                          * 1'b0: Even (micro)frame
-                                                          * 1'b1: Odd (micro)frame */
-        uint32_t usbactep                : 1;       /**< USB Active Endpoint (USBActEP)
-                                                         Indicates whether this endpoint is active in the current
-                                                         configuration and interface.  The core clears this bit for all
-                                                         endpoints (other than EP 0) after detecting a USB reset.  After
-                                                         receiving the SetConfiguration and SetInterface commands, the
-                                                         application must program endpoint registers accordingly and set
-                                                         this bit. */
-        uint32_t reserved_11_14          : 4;
-        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
-                                                         Applies to IN and OUT endpoints.
-                                                         The application must program this field with the maximum
-                                                         packet size for the current logical endpoint.  This value is in
-                                                         bytes. */
-#else
-        uint32_t mps                     : 11;
-        uint32_t reserved_11_14          : 4;
-        uint32_t usbactep                : 1;
-        uint32_t dpid                    : 1;
-        uint32_t naksts                  : 1;
-        uint32_t eptype                  : 2;
-        uint32_t snp                     : 1;
-        uint32_t stall                   : 1;
-        uint32_t reserved_22_25          : 4;
-        uint32_t cnak                    : 1;
-        uint32_t snak                    : 1;
-        uint32_t setd0pid                : 1;
-        uint32_t setd1pid                : 1;
-        uint32_t epdis                   : 1;
-        uint32_t epena                   : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_doepctlx_s         cn30xx;
-    struct cvmx_usbcx_doepctlx_s         cn31xx;
-    struct cvmx_usbcx_doepctlx_s         cn50xx;
-    struct cvmx_usbcx_doepctlx_s         cn52xx;
-    struct cvmx_usbcx_doepctlx_s         cn52xxp1;
-    struct cvmx_usbcx_doepctlx_s         cn56xx;
-    struct cvmx_usbcx_doepctlx_s         cn56xxp1;
-} cvmx_usbcx_doepctlx_t;
-
-
-/**
- * cvmx_usbc#_doepint#
- *
- * Device Endpoint-n Interrupt Register (DOEPINTn)
- * 
- * This register indicates the status of an endpoint with respect to USB- and AHB-related events.
- * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints
- * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively)
- * is set. Before the application can read this register, it must first read the Device All
- * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n
- * Interrupt register. The application must clear the appropriate bit in this register to clear the
- * corresponding bits in the DAINT and GINTSTS registers.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_doepintx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t outtknepdis             : 1;       /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-                                                         Applies only to control OUT endpoints.
-                                                         Indicates that an OUT token was received when the endpoint
-                                                         was not yet enabled. This interrupt is asserted on the endpoint
-                                                         for which the OUT token was received. */
-        uint32_t setup                   : 1;       /**< SETUP Phase Done (SetUp)
-                                                         Applies to control OUT endpoints only.
-                                                         Indicates that the SETUP phase for the control endpoint is
-                                                         complete and no more back-to-back SETUP packets were
-                                                         received for the current control transfer. On this interrupt, the
-                                                         application can decode the received SETUP data packet. */
-        uint32_t ahberr                  : 1;       /**< AHB Error (AHBErr)
-                                                         This is generated only in Internal DMA mode when there is an
-                                                         AHB error during an AHB read/write. The application can read
-                                                         the corresponding endpoint DMA address register to get the
-                                                         error address. */
-        uint32_t epdisbld                : 1;       /**< Endpoint Disabled Interrupt (EPDisbld)
-                                                         This bit indicates that the endpoint is disabled per the
-                                                         application's request. */
-        uint32_t xfercompl               : 1;       /**< Transfer Completed Interrupt (XferCompl)
-                                                         Indicates that the programmed transfer is complete on the AHB
-                                                         as well as on the USB, for this endpoint. */
-#else
-        uint32_t xfercompl               : 1;
-        uint32_t epdisbld                : 1;
-        uint32_t ahberr                  : 1;
-        uint32_t setup                   : 1;
-        uint32_t outtknepdis             : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_usbcx_doepintx_s         cn30xx;
-    struct cvmx_usbcx_doepintx_s         cn31xx;
-    struct cvmx_usbcx_doepintx_s         cn50xx;
-    struct cvmx_usbcx_doepintx_s         cn52xx;
-    struct cvmx_usbcx_doepintx_s         cn52xxp1;
-    struct cvmx_usbcx_doepintx_s         cn56xx;
-    struct cvmx_usbcx_doepintx_s         cn56xxp1;
-} cvmx_usbcx_doepintx_t;
-
-
-/**
- * cvmx_usbc#_doepmsk
- *
- * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK)
- * 
- * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers
- * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt
- * for a specific status in the DOEPINTn register can be masked by writing into the
- * corresponding bit in this register. Status bits are masked by default.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_doepmsk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t outtknepdismsk          : 1;       /**< OUT Token Received when Endpoint Disabled Mask
-                                                         (OUTTknEPdisMsk)
-                                                         Applies to control OUT endpoints only. */
-        uint32_t setupmsk                : 1;       /**< SETUP Phase Done Mask (SetUPMsk)
-                                                         Applies to control endpoints only. */
-        uint32_t ahberrmsk               : 1;       /**< AHB Error (AHBErrMsk) */
-        uint32_t epdisbldmsk             : 1;       /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
-        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Interrupt Mask (XferComplMsk) */
-#else
-        uint32_t xfercomplmsk            : 1;
-        uint32_t epdisbldmsk             : 1;
-        uint32_t ahberrmsk               : 1;
-        uint32_t setupmsk                : 1;
-        uint32_t outtknepdismsk          : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_usbcx_doepmsk_s          cn30xx;
-    struct cvmx_usbcx_doepmsk_s          cn31xx;
-    struct cvmx_usbcx_doepmsk_s          cn50xx;
-    struct cvmx_usbcx_doepmsk_s          cn52xx;
-    struct cvmx_usbcx_doepmsk_s          cn52xxp1;
-    struct cvmx_usbcx_doepmsk_s          cn56xx;
-    struct cvmx_usbcx_doepmsk_s          cn56xxp1;
-} cvmx_usbcx_doepmsk_t;
-
-
-/**
- * cvmx_usbc#_doeptsiz#
- *
- * Device Endpoint-n Transfer Size Register (DOEPTSIZn)
- * 
- * The application must modify this register before enabling the endpoint.
- * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
- * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application
- * can only read this register once the core has cleared the Endpoint Enable bit.
- * This register is used only for endpoints other than Endpoint 0.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_doeptsizx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_31_31          : 1;
-        uint32_t mc                      : 2;       /**< Multi Count (MC)
-                                                         Received Data PID (RxDPID)
-                                                         Applies to isochronous OUT endpoints only.
-                                                         This is the data PID received in the last packet for this endpoint.
-                                                         2'b00: DATA0
-                                                         2'b01: DATA1
-                                                         2'b10: DATA2
-                                                         2'b11: MDATA
-                                                         SETUP Packet Count (SUPCnt)
-                                                         Applies to control OUT Endpoints only.
-                                                         This field specifies the number of back-to-back SETUP data
-                                                         packets the endpoint can receive.
-                                                         2'b01: 1 packet
-                                                         2'b10: 2 packets
-                                                         2'b11: 3 packets */
-        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
-                                                         Indicates the total number of USB packets that constitute the
-                                                         Transfer Size amount of data for this endpoint.
-                                                         OUT Endpoints: This field is decremented every time a
-                                                         packet (maximum size or short packet) is written to the
-                                                         RxFIFO. */
-        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
-                                                         This field contains the transfer size in bytes for the current
-                                                         endpoint.
-                                                         The core only interrupts the application after it has exhausted
-                                                         the transfer size amount of data. The transfer size can be set to
-                                                         the maximum packet size of the endpoint, to be interrupted at
-                                                         the end of each packet.
-                                                         OUT Endpoints: The core decrements this field every time a
-                                                         packet is read from the RxFIFO and written to the external
-                                                         memory. */
-#else
-        uint32_t xfersize                : 19;
-        uint32_t pktcnt                  : 10;
-        uint32_t mc                      : 2;
-        uint32_t reserved_31_31          : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_doeptsizx_s        cn30xx;
-    struct cvmx_usbcx_doeptsizx_s        cn31xx;
-    struct cvmx_usbcx_doeptsizx_s        cn50xx;
-    struct cvmx_usbcx_doeptsizx_s        cn52xx;
-    struct cvmx_usbcx_doeptsizx_s        cn52xxp1;
-    struct cvmx_usbcx_doeptsizx_s        cn56xx;
-    struct cvmx_usbcx_doeptsizx_s        cn56xxp1;
-} cvmx_usbcx_doeptsizx_t;
-
-
-/**
- * cvmx_usbc#_dptxfsiz#
- *
- * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ)
- * 
- * This register holds the memory start address of each periodic TxFIFO to implemented
- * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
- * This register is repeated for each periodic FIFO instantiated.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dptxfsizx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dptxfsize               : 16;      /**< Device Periodic TxFIFO Size (DPTxFSize)
-                                                         This value is in terms of 32-bit words.
-                                                         * Minimum value is 4
-                                                         * Maximum value is 768 */
-        uint32_t dptxfstaddr             : 16;      /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr)
-                                                         Holds the start address in the RAM for this periodic FIFO. */
-#else
-        uint32_t dptxfstaddr             : 16;
-        uint32_t dptxfsize               : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_dptxfsizx_s        cn30xx;
-    struct cvmx_usbcx_dptxfsizx_s        cn31xx;
-    struct cvmx_usbcx_dptxfsizx_s        cn50xx;
-    struct cvmx_usbcx_dptxfsizx_s        cn52xx;
-    struct cvmx_usbcx_dptxfsizx_s        cn52xxp1;
-    struct cvmx_usbcx_dptxfsizx_s        cn56xx;
-    struct cvmx_usbcx_dptxfsizx_s        cn56xxp1;
-} cvmx_usbcx_dptxfsizx_t;
-
-
-/**
- * cvmx_usbc#_dsts
- *
- * Device Status Register (DSTS)
- * 
- * This register indicates the status of the core with respect to USB-related events.
- * It must be read on interrupts from Device All Interrupts (DAINT) register.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dsts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_22_31          : 10;
-        uint32_t soffn                   : 14;      /**< Frame or Microframe Number of the Received SOF (SOFFN)
-                                                         When the core is operating at high speed, this field contains a
-                                                         microframe number. When the core is operating at full or low
-                                                         speed, this field contains a frame number. */
-        uint32_t reserved_4_7            : 4;
-        uint32_t errticerr               : 1;       /**< Erratic Error (ErrticErr)
-                                                         The core sets this bit to report any erratic errors
-                                                         (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
-                                                         least 2 ms, due to PHY error) seen on the UTMI+.
-                                                         Due to erratic errors, the O2P USB core goes into Suspended
-                                                         state and an interrupt is generated to the application with Early
-                                                         Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
-                                                         If the early suspend is asserted due to an erratic error, the
-                                                         application can only perform a soft disconnect recover. */
-        uint32_t enumspd                 : 2;       /**< Enumerated Speed (EnumSpd)
-                                                         Indicates the speed at which the O2P USB core has come up
-                                                         after speed detection through a chirp sequence.
-                                                         * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
-                                                         * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
-                                                         * 2'b10: Low speed (PHY clock is running at 6 MHz)
-                                                         * 2'b11: Full speed (PHY clock is running at 48 MHz)
-                                                         Low speed is not supported for devices using a UTMI+ PHY. */
-        uint32_t suspsts                 : 1;       /**< Suspend Status (SuspSts)
-                                                         In Device mode, this bit is set as long as a Suspend condition is
-                                                         detected on the USB. The core enters the Suspended state
-                                                         when there is no activity on the phy_line_state_i signal for an
-                                                         extended period of time. The core comes out of the suspend:
-                                                         * When there is any activity on the phy_line_state_i signal
-                                                         * When the application writes to the Remote Wakeup Signaling
-                                                           bit in the Device Control register (DCTL.RmtWkUpSig). */
-#else
-        uint32_t suspsts                 : 1;
-        uint32_t enumspd                 : 2;
-        uint32_t errticerr               : 1;
-        uint32_t reserved_4_7            : 4;
-        uint32_t soffn                   : 14;
-        uint32_t reserved_22_31          : 10;
-#endif
-    } s;
-    struct cvmx_usbcx_dsts_s             cn30xx;
-    struct cvmx_usbcx_dsts_s             cn31xx;
-    struct cvmx_usbcx_dsts_s             cn50xx;
-    struct cvmx_usbcx_dsts_s             cn52xx;
-    struct cvmx_usbcx_dsts_s             cn52xxp1;
-    struct cvmx_usbcx_dsts_s             cn56xx;
-    struct cvmx_usbcx_dsts_s             cn56xxp1;
-} cvmx_usbcx_dsts_t;
-
-
-/**
- * cvmx_usbc#_dtknqr1
- *
- * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1)
- * 
- * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token
- * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number.
- * A read from this register returns the first 5 endpoint entries of the IN Token Sequence
- * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
- * token is discarded.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dtknqr1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t eptkn                   : 24;      /**< Endpoint Token (EPTkn)
-                                                         Four bits per token represent the endpoint number of the token:
-                                                         * Bits [31:28]: Endpoint number of Token 5
-                                                         * Bits [27:24]: Endpoint number of Token 4
-                                                         - .......
-                                                         * Bits [15:12]: Endpoint number of Token 1
-                                                         * Bits [11:8]: Endpoint number of Token 0 */
-        uint32_t wrapbit                 : 1;       /**< Wrap Bit (WrapBit)
-                                                         This bit is set when the write pointer wraps. It is cleared when
-                                                         the learning queue is cleared. */
-        uint32_t reserved_5_6            : 2;
-        uint32_t intknwptr               : 5;       /**< IN Token Queue Write Pointer (INTknWPtr) */
-#else
-        uint32_t intknwptr               : 5;
-        uint32_t reserved_5_6            : 2;
-        uint32_t wrapbit                 : 1;
-        uint32_t eptkn                   : 24;
-#endif
-    } s;
-    struct cvmx_usbcx_dtknqr1_s          cn30xx;
-    struct cvmx_usbcx_dtknqr1_s          cn31xx;
-    struct cvmx_usbcx_dtknqr1_s          cn50xx;
-    struct cvmx_usbcx_dtknqr1_s          cn52xx;
-    struct cvmx_usbcx_dtknqr1_s          cn52xxp1;
-    struct cvmx_usbcx_dtknqr1_s          cn56xx;
-    struct cvmx_usbcx_dtknqr1_s          cn56xxp1;
-} cvmx_usbcx_dtknqr1_t;
-
-
-/**
- * cvmx_usbc#_dtknqr2
- *
- * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2)
- * 
- * A read from this register returns the next 8 endpoint entries of the learning queue.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dtknqr2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
-                                                         Four bits per token represent the endpoint number of the token:
-                                                         * Bits [31:28]: Endpoint number of Token 13
-                                                         * Bits [27:24]: Endpoint number of Token 12
-                                                         - .......
-                                                         * Bits [7:4]: Endpoint number of Token 7
-                                                         * Bits [3:0]: Endpoint number of Token 6 */
-#else
-        uint32_t eptkn                   : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_dtknqr2_s          cn30xx;
-    struct cvmx_usbcx_dtknqr2_s          cn31xx;
-    struct cvmx_usbcx_dtknqr2_s          cn50xx;
-    struct cvmx_usbcx_dtknqr2_s          cn52xx;
-    struct cvmx_usbcx_dtknqr2_s          cn52xxp1;
-    struct cvmx_usbcx_dtknqr2_s          cn56xx;
-    struct cvmx_usbcx_dtknqr2_s          cn56xxp1;
-} cvmx_usbcx_dtknqr2_t;
-
-
-/**
- * cvmx_usbc#_dtknqr3
- *
- * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3)
- * 
- * A read from this register returns the next 8 endpoint entries of the learning queue.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dtknqr3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
-                                                         Four bits per token represent the endpoint number of the token:
-                                                         * Bits [31:28]: Endpoint number of Token 21
-                                                         * Bits [27:24]: Endpoint number of Token 20
-                                                         - .......
-                                                         * Bits [7:4]: Endpoint number of Token 15
-                                                         * Bits [3:0]: Endpoint number of Token 14 */
-#else
-        uint32_t eptkn                   : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_dtknqr3_s          cn30xx;
-    struct cvmx_usbcx_dtknqr3_s          cn31xx;
-    struct cvmx_usbcx_dtknqr3_s          cn50xx;
-    struct cvmx_usbcx_dtknqr3_s          cn52xx;
-    struct cvmx_usbcx_dtknqr3_s          cn52xxp1;
-    struct cvmx_usbcx_dtknqr3_s          cn56xx;
-    struct cvmx_usbcx_dtknqr3_s          cn56xxp1;
-} cvmx_usbcx_dtknqr3_t;
-
-
-/**
- * cvmx_usbc#_dtknqr4
- *
- * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4)
- * 
- * A read from this register returns the last 8 endpoint entries of the learning queue.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_dtknqr4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
-                                                         Four bits per token represent the endpoint number of the token:
-                                                         * Bits [31:28]: Endpoint number of Token 29
-                                                         * Bits [27:24]: Endpoint number of Token 28
-                                                         - .......
-                                                         * Bits [7:4]: Endpoint number of Token 23
-                                                         * Bits [3:0]: Endpoint number of Token 22 */
-#else
-        uint32_t eptkn                   : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_dtknqr4_s          cn30xx;
-    struct cvmx_usbcx_dtknqr4_s          cn31xx;
-    struct cvmx_usbcx_dtknqr4_s          cn50xx;
-    struct cvmx_usbcx_dtknqr4_s          cn52xx;
-    struct cvmx_usbcx_dtknqr4_s          cn52xxp1;
-    struct cvmx_usbcx_dtknqr4_s          cn56xx;
-    struct cvmx_usbcx_dtknqr4_s          cn56xxp1;
-} cvmx_usbcx_dtknqr4_t;
-
-
-/**
- * cvmx_usbc#_gahbcfg
- *
- * Core AHB Configuration Register (GAHBCFG)
- * 
- * This register can be used to configure the core after power-on or a change in mode of operation.
- * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
- * interface to the O2P USB core. In general, software need not know about this interface except to
- * program the values as specified.
- * 
- * The application must program this register as part of the O2P USB core initialization.
- * Do not change this register after the initial programming.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gahbcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_9_31           : 23;
-        uint32_t ptxfemplvl              : 1;       /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
-                                                         Software should set this bit to 0x1.
-                                                         Indicates when the Periodic TxFIFO Empty Interrupt bit in the
-                                                         Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
-                                                         bit is used only in Slave mode.
-                                                         * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
-                                                           TxFIFO is half empty
-                                                         * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
-                                                           TxFIFO is completely empty */
-        uint32_t nptxfemplvl             : 1;       /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
-                                                         Software should set this bit to 0x1.
-                                                         Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
-                                                         the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
-                                                         This bit is used only in Slave mode.
-                                                         * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
-                                                            Periodic TxFIFO is half empty
-                                                         * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
-                                                            Periodic TxFIFO is completely empty */
-        uint32_t reserved_6_6            : 1;
-        uint32_t dmaen                   : 1;       /**< DMA Enable (DMAEn)
-                                                         * 1'b0: Core operates in Slave mode
-                                                         * 1'b1: Core operates in a DMA mode */
-        uint32_t hbstlen                 : 4;       /**< Burst Length/Type (HBstLen)
-                                                         This field has not effect and should be left as 0x0. */
-        uint32_t glblintrmsk             : 1;       /**< Global Interrupt Mask (GlblIntrMsk)
-                                                         Software should set this field to 0x1.
-                                                         The application uses this bit to mask  or unmask the interrupt
-                                                         line assertion to itself. Irrespective of this bit's setting, the
-                                                         interrupt status registers are updated by the core.
-                                                         * 1'b0: Mask the interrupt assertion to the application.
-                                                         * 1'b1: Unmask the interrupt assertion to the application. */
-#else
-        uint32_t glblintrmsk             : 1;
-        uint32_t hbstlen                 : 4;
-        uint32_t dmaen                   : 1;
-        uint32_t reserved_6_6            : 1;
-        uint32_t nptxfemplvl             : 1;
-        uint32_t ptxfemplvl              : 1;
-        uint32_t reserved_9_31           : 23;
-#endif
-    } s;
-    struct cvmx_usbcx_gahbcfg_s          cn30xx;
-    struct cvmx_usbcx_gahbcfg_s          cn31xx;
-    struct cvmx_usbcx_gahbcfg_s          cn50xx;
-    struct cvmx_usbcx_gahbcfg_s          cn52xx;
-    struct cvmx_usbcx_gahbcfg_s          cn52xxp1;
-    struct cvmx_usbcx_gahbcfg_s          cn56xx;
-    struct cvmx_usbcx_gahbcfg_s          cn56xxp1;
-} cvmx_usbcx_gahbcfg_t;
-
-
-/**
- * cvmx_usbc#_ghwcfg1
- *
- * User HW Config1 Register (GHWCFG1)
- * 
- * This register contains the logical endpoint direction(s) of the O2P USB core.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_ghwcfg1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t epdir                   : 32;      /**< Endpoint Direction (epdir)
-                                                         Two bits per endpoint represent the direction.
-                                                         * 2'b00: BIDIR (IN and OUT) endpoint
-                                                         * 2'b01: IN endpoint
-                                                         * 2'b10: OUT endpoint
-                                                         * 2'b11: Reserved
-                                                         Bits [31:30]: Endpoint 15 direction
-                                                         Bits [29:28]: Endpoint 14 direction
-                                                         - ...
-                                                         Bits [3:2]: Endpoint 1 direction
-                                                         Bits[1:0]: Endpoint 0 direction (always BIDIR) */
-#else
-        uint32_t epdir                   : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_ghwcfg1_s          cn30xx;
-    struct cvmx_usbcx_ghwcfg1_s          cn31xx;
-    struct cvmx_usbcx_ghwcfg1_s          cn50xx;
-    struct cvmx_usbcx_ghwcfg1_s          cn52xx;
-    struct cvmx_usbcx_ghwcfg1_s          cn52xxp1;
-    struct cvmx_usbcx_ghwcfg1_s          cn56xx;
-    struct cvmx_usbcx_ghwcfg1_s          cn56xxp1;
-} cvmx_usbcx_ghwcfg1_t;
-
-
-/**
- * cvmx_usbc#_ghwcfg2
- *
- * User HW Config2 Register (GHWCFG2)
- * 
- * This register contains configuration options of the O2P USB core.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_ghwcfg2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_31_31          : 1;
-        uint32_t tknqdepth               : 5;       /**< Device Mode IN Token Sequence Learning Queue Depth
-                                                         (TknQDepth)
-                                                         Range: 0-30 */
-        uint32_t ptxqdepth               : 2;       /**< Host Mode Periodic Request Queue Depth (PTxQDepth)
-                                                         * 2'b00: 2
-                                                         * 2'b01: 4
-                                                         * 2'b10: 8
-                                                         * Others: Reserved */
-        uint32_t nptxqdepth              : 2;       /**< Non-Periodic Request Queue Depth (NPTxQDepth)
-                                                         * 2'b00: 2
-                                                         * 2'b01: 4
-                                                         * 2'b10: 8
-                                                         * Others: Reserved */
-        uint32_t reserved_20_21          : 2;
-        uint32_t dynfifosizing           : 1;       /**< Dynamic FIFO Sizing Enabled (DynFifoSizing)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t periosupport            : 1;       /**< Periodic OUT Channels Supported in Host Mode
-                                                         (PerioSupport)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t numhstchnl              : 4;       /**< Number of Host Channels (NumHstChnl)
-                                                         Indicates the number of host channels supported by the core in
-                                                         Host mode. The range of this field is 0-15: 0 specifies 1
-                                                         channel, 15 specifies 16 channels. */
-        uint32_t numdeveps               : 4;       /**< Number of Device Endpoints (NumDevEps)
-                                                         Indicates the number of device endpoints supported by the core
-                                                         in Device mode in addition to control endpoint 0. The range of
-                                                         this field is 1-15. */
-        uint32_t fsphytype               : 2;       /**< Full-Speed PHY Interface Type (FSPhyType)
-                                                         * 2'b00: Full-speed interface not supported
-                                                         * 2'b01: Dedicated full-speed interface
-                                                         * 2'b10: FS pins shared with UTMI+ pins
-                                                         * 2'b11: FS pins shared with ULPI pins */
-        uint32_t hsphytype               : 2;       /**< High-Speed PHY Interface Type (HSPhyType)
-                                                         * 2'b00: High-Speed interface not supported
-                                                         * 2'b01: UTMI+
-                                                         * 2'b10: ULPI
-                                                         * 2'b11: UTMI+ and ULPI */
-        uint32_t singpnt                 : 1;       /**< Point-to-Point (SingPnt)
-                                                         * 1'b0: Multi-point application
-                                                         * 1'b1: Single-point application */
-        uint32_t otgarch                 : 2;       /**< Architecture (OtgArch)
-                                                         * 2'b00: Slave-Only
-                                                         * 2'b01: External DMA
-                                                         * 2'b10: Internal DMA
-                                                         * Others: Reserved */
-        uint32_t otgmode                 : 3;       /**< Mode of Operation (OtgMode)
-                                                         * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
-                                                         * 3'b001: SRP-Capable OTG (Host & Device)
-                                                         * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
-                                                         Device)
-                                                         * 3'b011: SRP-Capable Device
-                                                         * 3'b100: Non-OTG Device
-                                                         * 3'b101: SRP-Capable Host
-                                                         * 3'b110: Non-OTG Host
-                                                         * Others: Reserved */
-#else
-        uint32_t otgmode                 : 3;
-        uint32_t otgarch                 : 2;
-        uint32_t singpnt                 : 1;
-        uint32_t hsphytype               : 2;
-        uint32_t fsphytype               : 2;
-        uint32_t numdeveps               : 4;
-        uint32_t numhstchnl              : 4;
-        uint32_t periosupport            : 1;
-        uint32_t dynfifosizing           : 1;
-        uint32_t reserved_20_21          : 2;
-        uint32_t nptxqdepth              : 2;
-        uint32_t ptxqdepth               : 2;
-        uint32_t tknqdepth               : 5;
-        uint32_t reserved_31_31          : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_ghwcfg2_s          cn30xx;
-    struct cvmx_usbcx_ghwcfg2_s          cn31xx;
-    struct cvmx_usbcx_ghwcfg2_s          cn50xx;
-    struct cvmx_usbcx_ghwcfg2_s          cn52xx;
-    struct cvmx_usbcx_ghwcfg2_s          cn52xxp1;
-    struct cvmx_usbcx_ghwcfg2_s          cn56xx;
-    struct cvmx_usbcx_ghwcfg2_s          cn56xxp1;
-} cvmx_usbcx_ghwcfg2_t;
-
-
-/**
- * cvmx_usbc#_ghwcfg3
- *
- * User HW Config3 Register (GHWCFG3)
- * 
- * This register contains the configuration options of the O2P USB core.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_ghwcfg3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dfifodepth              : 16;      /**< DFIFO Depth (DfifoDepth)
-                                                         This value is in terms of 32-bit words.
-                                                         * Minimum value is 32
-                                                         * Maximum value is 32768 */
-        uint32_t reserved_13_15          : 3;
-        uint32_t ahbphysync              : 1;       /**< AHB and PHY Synchronous (AhbPhySync)
-                                                         Indicates whether AHB and PHY clocks are synchronous to
-                                                         each other.
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes
-                                                         This bit is tied to 1. */
-        uint32_t rsttype                 : 1;       /**< Reset Style for Clocked always Blocks in RTL (RstType)
-                                                         * 1'b0: Asynchronous reset is used in the core
-                                                         * 1'b1: Synchronous reset is used in the core */
-        uint32_t optfeature              : 1;       /**< Optional Features Removed (OptFeature)
-                                                         Indicates whether the User ID register, GPIO interface ports,
-                                                         and SOF toggle and counter ports were removed for gate count
-                                                         optimization. */
-        uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support
-                                                         * 1'b0: Vendor Control Interface is not available on the core.
-                                                         * 1'b1: Vendor Control Interface is available. */
-        uint32_t i2c_selection           : 1;       /**< I2C Selection
-                                                         * 1'b0: I2C Interface is not available on the core.
-                                                         * 1'b1: I2C Interface is available on the core. */
-        uint32_t otgen                   : 1;       /**< OTG Function Enabled (OtgEn)
-                                                         The application uses this bit to indicate the O2P USB core's
-                                                         OTG capabilities.
-                                                         * 1'b0: Not OTG capable
-                                                         * 1'b1: OTG Capable */
-        uint32_t pktsizewidth            : 3;       /**< Width of Packet Size Counters (PktSizeWidth)
-                                                         * 3'b000: 4 bits
-                                                         * 3'b001: 5 bits
-                                                         * 3'b010: 6 bits
-                                                         * 3'b011: 7 bits
-                                                         * 3'b100: 8 bits
-                                                         * 3'b101: 9 bits
-                                                         * 3'b110: 10 bits
-                                                         * Others: Reserved */
-        uint32_t xfersizewidth           : 4;       /**< Width of Transfer Size Counters (XferSizeWidth)
-                                                         * 4'b0000: 11 bits
-                                                         * 4'b0001: 12 bits
-                                                         - ...
-                                                         * 4'b1000: 19 bits
-                                                         * Others: Reserved */
-#else
-        uint32_t xfersizewidth           : 4;
-        uint32_t pktsizewidth            : 3;
-        uint32_t otgen                   : 1;
-        uint32_t i2c_selection           : 1;
-        uint32_t vendor_control_interface_support : 1;
-        uint32_t optfeature              : 1;
-        uint32_t rsttype                 : 1;
-        uint32_t ahbphysync              : 1;
-        uint32_t reserved_13_15          : 3;
-        uint32_t dfifodepth              : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_ghwcfg3_s          cn30xx;
-    struct cvmx_usbcx_ghwcfg3_s          cn31xx;
-    struct cvmx_usbcx_ghwcfg3_s          cn50xx;
-    struct cvmx_usbcx_ghwcfg3_s          cn52xx;
-    struct cvmx_usbcx_ghwcfg3_s          cn52xxp1;
-    struct cvmx_usbcx_ghwcfg3_s          cn56xx;
-    struct cvmx_usbcx_ghwcfg3_s          cn56xxp1;
-} cvmx_usbcx_ghwcfg3_t;
-
-
-/**
- * cvmx_usbc#_ghwcfg4
- *
- * User HW Config4 Register (GHWCFG4)
- * 
- * This register contains the configuration options of the O2P USB core.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_ghwcfg4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_30_31          : 2;
-        uint32_t numdevmodinend          : 4;       /**< Enable dedicatd transmit FIFO for device IN endpoints. */
-        uint32_t endedtrfifo             : 1;       /**< Enable dedicatd transmit FIFO for device IN endpoints. */
-        uint32_t sessendfltr             : 1;       /**< "session_end" Filter Enabled (SessEndFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t bvalidfltr              : 1;       /**< "b_valid" Filter Enabled (BValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t avalidfltr              : 1;       /**< "a_valid" Filter Enabled (AValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t vbusvalidfltr           : 1;       /**< "vbus_valid" Filter Enabled (VBusValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t iddgfltr                : 1;       /**< "iddig" Filter Enable (IddgFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t numctleps               : 4;       /**< Number of Device Mode Control Endpoints in Addition to
-                                                         Endpoint 0 (NumCtlEps)
-                                                         Range: 1-15 */
-        uint32_t phydatawidth            : 2;       /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
-                                                         (PhyDataWidth)
-                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
-                                                         to UTMI+.
-                                                         * 2'b00: 8 bits
-                                                         * 2'b01: 16 bits
-                                                         * 2'b10: 8/16 bits, software selectable
-                                                         * Others: Reserved */
-        uint32_t reserved_6_13           : 8;
-        uint32_t ahbfreq                 : 1;       /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t enablepwropt            : 1;       /**< Enable Power Optimization? (EnablePwrOpt)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t numdevperioeps          : 4;       /**< Number of Device Mode Periodic IN Endpoints
-                                                         (NumDevPerioEps)
-                                                         Range: 0-15 */
-#else
-        uint32_t numdevperioeps          : 4;
-        uint32_t enablepwropt            : 1;
-        uint32_t ahbfreq                 : 1;
-        uint32_t reserved_6_13           : 8;
-        uint32_t phydatawidth            : 2;
-        uint32_t numctleps               : 4;
-        uint32_t iddgfltr                : 1;
-        uint32_t vbusvalidfltr           : 1;
-        uint32_t avalidfltr              : 1;
-        uint32_t bvalidfltr              : 1;
-        uint32_t sessendfltr             : 1;
-        uint32_t endedtrfifo             : 1;
-        uint32_t numdevmodinend          : 4;
-        uint32_t reserved_30_31          : 2;
-#endif
-    } s;
-    struct cvmx_usbcx_ghwcfg4_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_25_31          : 7;
-        uint32_t sessendfltr             : 1;       /**< "session_end" Filter Enabled (SessEndFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t bvalidfltr              : 1;       /**< "b_valid" Filter Enabled (BValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t avalidfltr              : 1;       /**< "a_valid" Filter Enabled (AValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t vbusvalidfltr           : 1;       /**< "vbus_valid" Filter Enabled (VBusValidFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t iddgfltr                : 1;       /**< "iddig" Filter Enable (IddgFltr)
-                                                         * 1'b0: No filter
-                                                         * 1'b1: Filter */
-        uint32_t numctleps               : 4;       /**< Number of Device Mode Control Endpoints in Addition to
-                                                         Endpoint 0 (NumCtlEps)
-                                                         Range: 1-15 */
-        uint32_t phydatawidth            : 2;       /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
-                                                         (PhyDataWidth)
-                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
-                                                         to UTMI+.
-                                                         * 2'b00: 8 bits
-                                                         * 2'b01: 16 bits
-                                                         * 2'b10: 8/16 bits, software selectable
-                                                         * Others: Reserved */
-        uint32_t reserved_6_13           : 8;
-        uint32_t ahbfreq                 : 1;       /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t enablepwropt            : 1;       /**< Enable Power Optimization? (EnablePwrOpt)
-                                                         * 1'b0: No
-                                                         * 1'b1: Yes */
-        uint32_t numdevperioeps          : 4;       /**< Number of Device Mode Periodic IN Endpoints
-                                                         (NumDevPerioEps)
-                                                         Range: 0-15 */
-#else
-        uint32_t numdevperioeps          : 4;
-        uint32_t enablepwropt            : 1;
-        uint32_t ahbfreq                 : 1;
-        uint32_t reserved_6_13           : 8;
-        uint32_t phydatawidth            : 2;
-        uint32_t numctleps               : 4;
-        uint32_t iddgfltr                : 1;
-        uint32_t vbusvalidfltr           : 1;
-        uint32_t avalidfltr              : 1;
-        uint32_t bvalidfltr              : 1;
-        uint32_t sessendfltr             : 1;
-        uint32_t reserved_25_31          : 7;
-#endif
-    } cn30xx;
-    struct cvmx_usbcx_ghwcfg4_cn30xx     cn31xx;
-    struct cvmx_usbcx_ghwcfg4_s          cn50xx;
-    struct cvmx_usbcx_ghwcfg4_s          cn52xx;
-    struct cvmx_usbcx_ghwcfg4_s          cn52xxp1;
-    struct cvmx_usbcx_ghwcfg4_s          cn56xx;
-    struct cvmx_usbcx_ghwcfg4_s          cn56xxp1;
-} cvmx_usbcx_ghwcfg4_t;
-
-
-/**
- * cvmx_usbc#_gintmsk
- *
- * Core Interrupt Mask Register (GINTMSK)
- * 
- * This register works with the Core Interrupt register to interrupt the application.
- * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
- * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
- * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gintmsk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wkupintmsk              : 1;       /**< Resume/Remote Wakeup Detected Interrupt Mask
-                                                         (WkUpIntMsk) */
-        uint32_t sessreqintmsk           : 1;       /**< Session Request/New Session Detected Interrupt Mask
-                                                         (SessReqIntMsk) */
-        uint32_t disconnintmsk           : 1;       /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */
-        uint32_t conidstschngmsk         : 1;       /**< Connector ID Status Change Mask (ConIDStsChngMsk) */
-        uint32_t reserved_27_27          : 1;
-        uint32_t ptxfempmsk              : 1;       /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */
-        uint32_t hchintmsk               : 1;       /**< Host Channels Interrupt Mask (HChIntMsk) */
-        uint32_t prtintmsk               : 1;       /**< Host Port Interrupt Mask (PrtIntMsk) */
-        uint32_t reserved_23_23          : 1;
-        uint32_t fetsuspmsk              : 1;       /**< Data Fetch Suspended Mask (FetSuspMsk) */
-        uint32_t incomplpmsk             : 1;       /**< Incomplete Periodic Transfer Mask (incomplPMsk)
-                                                         Incomplete Isochronous OUT Transfer Mask
-                                                         (incompISOOUTMsk) */
-        uint32_t incompisoinmsk          : 1;       /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */
-        uint32_t oepintmsk               : 1;       /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */
-        uint32_t inepintmsk              : 1;       /**< IN Endpoints Interrupt Mask (INEPIntMsk) */
-        uint32_t epmismsk                : 1;       /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */
-        uint32_t reserved_16_16          : 1;
-        uint32_t eopfmsk                 : 1;       /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */
-        uint32_t isooutdropmsk           : 1;       /**< Isochronous OUT Packet Dropped Interrupt Mask
-                                                         (ISOOutDropMsk) */
-        uint32_t enumdonemsk             : 1;       /**< Enumeration Done Mask (EnumDoneMsk) */
-        uint32_t usbrstmsk               : 1;       /**< USB Reset Mask (USBRstMsk) */
-        uint32_t usbsuspmsk              : 1;       /**< USB Suspend Mask (USBSuspMsk) */
-        uint32_t erlysuspmsk             : 1;       /**< Early Suspend Mask (ErlySuspMsk) */
-        uint32_t i2cint                  : 1;       /**< I2C Interrupt Mask (I2CINT) */
-        uint32_t ulpickintmsk            : 1;       /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk)
-                                                         I2C Carkit Interrupt Mask (I2CCKINTMsk) */
-        uint32_t goutnakeffmsk           : 1;       /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */
-        uint32_t ginnakeffmsk            : 1;       /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */
-        uint32_t nptxfempmsk             : 1;       /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */
-        uint32_t rxflvlmsk               : 1;       /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */
-        uint32_t sofmsk                  : 1;       /**< Start of (micro)Frame Mask (SofMsk) */
-        uint32_t otgintmsk               : 1;       /**< OTG Interrupt Mask (OTGIntMsk) */
-        uint32_t modemismsk              : 1;       /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */
-        uint32_t reserved_0_0            : 1;
-#else
-        uint32_t reserved_0_0            : 1;
-        uint32_t modemismsk              : 1;
-        uint32_t otgintmsk               : 1;
-        uint32_t sofmsk                  : 1;
-        uint32_t rxflvlmsk               : 1;
-        uint32_t nptxfempmsk             : 1;
-        uint32_t ginnakeffmsk            : 1;
-        uint32_t goutnakeffmsk           : 1;
-        uint32_t ulpickintmsk            : 1;
-        uint32_t i2cint                  : 1;
-        uint32_t erlysuspmsk             : 1;
-        uint32_t usbsuspmsk              : 1;
-        uint32_t usbrstmsk               : 1;
-        uint32_t enumdonemsk             : 1;
-        uint32_t isooutdropmsk           : 1;
-        uint32_t eopfmsk                 : 1;
-        uint32_t reserved_16_16          : 1;
-        uint32_t epmismsk                : 1;
-        uint32_t inepintmsk              : 1;
-        uint32_t oepintmsk               : 1;
-        uint32_t incompisoinmsk          : 1;
-        uint32_t incomplpmsk             : 1;
-        uint32_t fetsuspmsk              : 1;
-        uint32_t reserved_23_23          : 1;
-        uint32_t prtintmsk               : 1;
-        uint32_t hchintmsk               : 1;
-        uint32_t ptxfempmsk              : 1;
-        uint32_t reserved_27_27          : 1;
-        uint32_t conidstschngmsk         : 1;
-        uint32_t disconnintmsk           : 1;
-        uint32_t sessreqintmsk           : 1;
-        uint32_t wkupintmsk              : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_gintmsk_s          cn30xx;
-    struct cvmx_usbcx_gintmsk_s          cn31xx;
-    struct cvmx_usbcx_gintmsk_s          cn50xx;
-    struct cvmx_usbcx_gintmsk_s          cn52xx;
-    struct cvmx_usbcx_gintmsk_s          cn52xxp1;
-    struct cvmx_usbcx_gintmsk_s          cn56xx;
-    struct cvmx_usbcx_gintmsk_s          cn56xxp1;
-} cvmx_usbcx_gintmsk_t;
-
-
-/**
- * cvmx_usbc#_gintsts
- *
- * Core Interrupt Register (GINTSTS)
- * 
- * This register interrupts the application for system-level events in the current mode of operation
- * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
- * while others are valid in Device mode only. This register also indicates the current mode of operation.
- * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
- * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
- * interrupts, FIFO interrupt conditions are cleared automatically.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gintsts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t wkupint                 : 1;       /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
-                                                         In Device mode, this interrupt is asserted when a resume is
-                                                         detected on the USB. In Host mode, this interrupt is asserted
-                                                         when a remote wakeup is detected on the USB.
-                                                         For more information on how to use this interrupt, see "Partial
-                                                         Power-Down and Clock Gating Programming Model" on
-                                                         page 353. */
-        uint32_t sessreqint              : 1;       /**< Session Request/New Session Detected Interrupt (SessReqInt)
-                                                         In Host mode, this interrupt is asserted when a session request
-                                                         is detected from the device. In Device mode, this interrupt is
-                                                         asserted when the utmiotg_bvalid signal goes high.
-                                                         For more information on how to use this interrupt, see "Partial
-                                                         Power-Down and Clock Gating Programming Model" on
-                                                         page 353. */
-        uint32_t disconnint              : 1;       /**< Disconnect Detected Interrupt (DisconnInt)
-                                                         Asserted when a device disconnect is detected. */
-        uint32_t conidstschng            : 1;       /**< Connector ID Status Change (ConIDStsChng)
-                                                         The core sets this bit when there is a change in connector ID
-                                                         status. */
-        uint32_t reserved_27_27          : 1;
-        uint32_t ptxfemp                 : 1;       /**< Periodic TxFIFO Empty (PTxFEmp)
-                                                         Asserted when the Periodic Transmit FIFO is either half or
-                                                         completely empty and there is space for at least one entry to be
-                                                         written in the Periodic Request Queue. The half or completely
-                                                         empty status is determined by the Periodic TxFIFO Empty Level
-                                                         bit in the Core AHB Configuration register
-                                                         (GAHBCFG.PTxFEmpLvl). */
-        uint32_t hchint                  : 1;       /**< Host Channels Interrupt (HChInt)
-                                                         The core sets this bit to indicate that an interrupt is pending on
-                                                         one of the channels of the core (in Host mode). The application
-                                                         must read the Host All Channels Interrupt (HAINT) register to
-                                                         determine the exact number of the channel on which the
-                                                         interrupt occurred, and then read the corresponding Host
-                                                         Channel-n Interrupt (HCINTn) register to determine the exact
-                                                         cause of the interrupt. The application must clear the
-                                                         appropriate status bit in the HCINTn register to clear this bit. */
-        uint32_t prtint                  : 1;       /**< Host Port Interrupt (PrtInt)
-                                                         The core sets this bit to indicate a change in port status of one
-                                                         of the O2P USB core ports in Host mode. The application must
-                                                         read the Host Port Control and Status (HPRT) register to
-                                                         determine the exact event that caused this interrupt. The
-                                                         application must clear the appropriate status bit in the Host Port
-                                                         Control and Status register to clear this bit. */
-        uint32_t reserved_23_23          : 1;
-        uint32_t fetsusp                 : 1;       /**< Data Fetch Suspended (FetSusp)
-                                                         This interrupt is valid only in DMA mode. This interrupt indicates
-                                                         that the core has stopped fetching data for IN endpoints due to
-                                                         the unavailability of TxFIFO space or Request Queue space.
-                                                         This interrupt is used by the application for an endpoint
-                                                         mismatch algorithm. */
-        uint32_t incomplp                : 1;       /**< Incomplete Periodic Transfer (incomplP)
-                                                         In Host mode, the core sets this interrupt bit when there are
-                                                         incomplete periodic transactions still pending which are
-                                                         scheduled for the current microframe.
-                                                         Incomplete Isochronous OUT Transfer (incompISOOUT)
-                                                         The Device mode, the core sets this interrupt to indicate that
-                                                         there is at least one isochronous OUT endpoint on which the
-                                                         transfer is not completed in the current microframe. This
-                                                         interrupt is asserted along with the End of Periodic Frame
-                                                         Interrupt (EOPF) bit in this register. */
-        uint32_t incompisoin             : 1;       /**< Incomplete Isochronous IN Transfer (incompISOIN)
-                                                         The core sets this interrupt to indicate that there is at least one
-                                                         isochronous IN endpoint on which the transfer is not completed
-                                                         in the current microframe. This interrupt is asserted along with
-                                                         the End of Periodic Frame Interrupt (EOPF) bit in this register. */
-        uint32_t oepint                  : 1;       /**< OUT Endpoints Interrupt (OEPInt)
-                                                         The core sets this bit to indicate that an interrupt is pending on
-                                                         one of the OUT endpoints of the core (in Device mode). The
-                                                         application must read the Device All Endpoints Interrupt
-                                                         (DAINT) register to determine the exact number of the OUT
-                                                         endpoint on which the interrupt occurred, and then read the
-                                                         corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
-                                                         register to determine the exact cause of the interrupt. The
-                                                         application must clear the appropriate status bit in the
-                                                         corresponding DOEPINTn register to clear this bit. */
-        uint32_t iepint                  : 1;       /**< IN Endpoints Interrupt (IEPInt)
-                                                         The core sets this bit to indicate that an interrupt is pending on
-                                                         one of the IN endpoints of the core (in Device mode). The
-                                                         application must read the Device All Endpoints Interrupt
-                                                         (DAINT) register to determine the exact number of the IN
-                                                         endpoint on which the interrupt occurred, and then read the
-                                                         corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
-                                                         register to determine the exact cause of the interrupt. The
-                                                         application must clear the appropriate status bit in the
-                                                         corresponding DIEPINTn register to clear this bit. */
-        uint32_t epmis                   : 1;       /**< Endpoint Mismatch Interrupt (EPMis)
-                                                         Indicates that an IN token has been received for a non-periodic
-                                                         endpoint, but the data for another endpoint is present in the top
-                                                         of the Non-Periodic Transmit FIFO and the IN endpoint
-                                                         mismatch count programmed by the application has expired. */
-        uint32_t reserved_16_16          : 1;
-        uint32_t eopf                    : 1;       /**< End of Periodic Frame Interrupt (EOPF)
-                                                         Indicates that the period specified in the Periodic Frame Interval
-                                                         field of the Device Configuration register (DCFG.PerFrInt) has
-                                                         been reached in the current microframe. */
-        uint32_t isooutdrop              : 1;       /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
-                                                         The core sets this bit when it fails to write an isochronous OUT
-                                                         packet into the RxFIFO because the RxFIFO doesn't have
-                                                         enough space to accommodate a maximum packet size packet
-                                                         for the isochronous OUT endpoint. */
-        uint32_t enumdone                : 1;       /**< Enumeration Done (EnumDone)
-                                                         The core sets this bit to indicate that speed enumeration is
-                                                         complete. The application must read the Device Status (DSTS)
-                                                         register to obtain the enumerated speed. */
-        uint32_t usbrst                  : 1;       /**< USB Reset (USBRst)
-                                                         The core sets this bit to indicate that a reset is detected on the
-                                                         USB. */
-        uint32_t usbsusp                 : 1;       /**< USB Suspend (USBSusp)
-                                                         The core sets this bit to indicate that a suspend was detected
-                                                         on the USB. The core enters the Suspended state when there
-                                                         is no activity on the phy_line_state_i signal for an extended
-                                                         period of time. */
-        uint32_t erlysusp                : 1;       /**< Early Suspend (ErlySusp)
-                                                         The core sets this bit to indicate that an Idle state has been
-                                                         detected on the USB for 3 ms. */
-        uint32_t i2cint                  : 1;       /**< I2C Interrupt (I2CINT)
-                                                         This bit is always 0x0. */
-        uint32_t ulpickint               : 1;       /**< ULPI Carkit Interrupt (ULPICKINT)
-                                                         This bit is always 0x0. */
-        uint32_t goutnakeff              : 1;       /**< Global OUT NAK Effective (GOUTNakEff)
-                                                         Indicates that the Set Global OUT NAK bit in the Device Control
-                                                         register (DCTL.SGOUTNak), set by the application, has taken
-                                                         effect in the core. This bit can be cleared by writing the Clear
-                                                         Global OUT NAK bit in the Device Control register
-                                                         (DCTL.CGOUTNak). */
-        uint32_t ginnakeff               : 1;       /**< Global IN Non-Periodic NAK Effective (GINNakEff)
-                                                         Indicates that the Set Global Non-Periodic IN NAK bit in the
-                                                         Device Control register (DCTL.SGNPInNak), set by the
-                                                         application, has taken effect in the core. That is, the core has
-                                                         sampled the Global IN NAK bit set by the application. This bit
-                                                         can be cleared by clearing the Clear Global Non-Periodic IN
-                                                         NAK bit in the Device Control register (DCTL.CGNPInNak).
-                                                         This interrupt does not necessarily mean that a NAK handshake
-                                                         is sent out on the USB. The STALL bit takes precedence over
-                                                         the NAK bit. */
-        uint32_t nptxfemp                : 1;       /**< Non-Periodic TxFIFO Empty (NPTxFEmp)
-                                                         This interrupt is asserted when the Non-Periodic TxFIFO is
-                                                         either half or completely empty, and there is space for at least
-                                                         one entry to be written to the Non-Periodic Transmit Request
-                                                         Queue. The half or completely empty status is determined by
-                                                         the Non-Periodic TxFIFO Empty Level bit in the Core AHB
-                                                         Configuration register (GAHBCFG.NPTxFEmpLvl). */
-        uint32_t rxflvl                  : 1;       /**< RxFIFO Non-Empty (RxFLvl)
-                                                         Indicates that there is at least one packet pending to be read
-                                                         from the RxFIFO. */
-        uint32_t sof                     : 1;       /**< Start of (micro)Frame (Sof)
-                                                         In Host mode, the core sets this bit to indicate that an SOF
-                                                         (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
-                                                         USB. The application must write a 1 to this bit to clear the
-                                                         interrupt.
-                                                         In Device mode, in the core sets this bit to indicate that an SOF
-                                                         token has been received on the USB. The application can read
-                                                         the Device Status register to get the current (micro)frame
-                                                         number. This interrupt is seen only when the core is operating
-                                                         at either HS or FS. */
-        uint32_t otgint                  : 1;       /**< OTG Interrupt (OTGInt)
-                                                         The core sets this bit to indicate an OTG protocol event. The
-                                                         application must read the OTG Interrupt Status (GOTGINT)
-                                                         register to determine the exact event that caused this interrupt.
-                                                         The application must clear the appropriate status bit in the
-                                                         GOTGINT register to clear this bit. */
-        uint32_t modemis                 : 1;       /**< Mode Mismatch Interrupt (ModeMis)
-                                                         The core sets this bit when the application is trying to access:
-                                                         * A Host mode register, when the core is operating in Device
-                                                         mode
-                                                         * A Device mode register, when the core is operating in Host
-                                                           mode
-                                                           The register access is completed on the AHB with an OKAY
-                                                           response, but is ignored by the core internally and doesn't
-                                                         affect the operation of the core. */
-        uint32_t curmod                  : 1;       /**< Current Mode of Operation (CurMod)
-                                                         Indicates the current mode of operation.
-                                                         * 1'b0: Device mode
-                                                         * 1'b1: Host mode */
-#else
-        uint32_t curmod                  : 1;
-        uint32_t modemis                 : 1;
-        uint32_t otgint                  : 1;
-        uint32_t sof                     : 1;
-        uint32_t rxflvl                  : 1;
-        uint32_t nptxfemp                : 1;
-        uint32_t ginnakeff               : 1;
-        uint32_t goutnakeff              : 1;
-        uint32_t ulpickint               : 1;
-        uint32_t i2cint                  : 1;
-        uint32_t erlysusp                : 1;
-        uint32_t usbsusp                 : 1;
-        uint32_t usbrst                  : 1;
-        uint32_t enumdone                : 1;
-        uint32_t isooutdrop              : 1;
-        uint32_t eopf                    : 1;
-        uint32_t reserved_16_16          : 1;
-        uint32_t epmis                   : 1;
-        uint32_t iepint                  : 1;
-        uint32_t oepint                  : 1;
-        uint32_t incompisoin             : 1;
-        uint32_t incomplp                : 1;
-        uint32_t fetsusp                 : 1;
-        uint32_t reserved_23_23          : 1;
-        uint32_t prtint                  : 1;
-        uint32_t hchint                  : 1;
-        uint32_t ptxfemp                 : 1;
-        uint32_t reserved_27_27          : 1;
-        uint32_t conidstschng            : 1;
-        uint32_t disconnint              : 1;
-        uint32_t sessreqint              : 1;
-        uint32_t wkupint                 : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_gintsts_s          cn30xx;
-    struct cvmx_usbcx_gintsts_s          cn31xx;
-    struct cvmx_usbcx_gintsts_s          cn50xx;
-    struct cvmx_usbcx_gintsts_s          cn52xx;
-    struct cvmx_usbcx_gintsts_s          cn52xxp1;
-    struct cvmx_usbcx_gintsts_s          cn56xx;
-    struct cvmx_usbcx_gintsts_s          cn56xxp1;
-} cvmx_usbcx_gintsts_t;
-
-
-/**
- * cvmx_usbc#_gnptxfsiz
- *
- * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
- * 
- * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gnptxfsiz_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t nptxfdep                : 16;      /**< Non-Periodic TxFIFO Depth (NPTxFDep)
-                                                         This value is in terms of 32-bit words.
-                                                         Minimum value is 16
-                                                         Maximum value is 32768 */
-        uint32_t nptxfstaddr             : 16;      /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
-                                                         This field contains the memory start address for Non-Periodic
-                                                         Transmit FIFO RAM. */
-#else
-        uint32_t nptxfstaddr             : 16;
-        uint32_t nptxfdep                : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_gnptxfsiz_s        cn30xx;
-    struct cvmx_usbcx_gnptxfsiz_s        cn31xx;
-    struct cvmx_usbcx_gnptxfsiz_s        cn50xx;
-    struct cvmx_usbcx_gnptxfsiz_s        cn52xx;
-    struct cvmx_usbcx_gnptxfsiz_s        cn52xxp1;
-    struct cvmx_usbcx_gnptxfsiz_s        cn56xx;
-    struct cvmx_usbcx_gnptxfsiz_s        cn56xxp1;
-} cvmx_usbcx_gnptxfsiz_t;
-
-
-/**
- * cvmx_usbc#_gnptxsts
- *
- * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
- * 
- * This read-only register contains the free space information for the Non-Periodic TxFIFO and
- * the Non-Periodic Transmit Request Queue
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gnptxsts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_31_31          : 1;
-        uint32_t nptxqtop                : 7;       /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
-                                                         Entry in the Non-Periodic Tx Request Queue that is currently
-                                                         being processed by the MAC.
-                                                         * Bits [30:27]: Channel/endpoint number
-                                                         * Bits [26:25]:
-                                                           - 2'b00: IN/OUT token
-                                                           - 2'b01: Zero-length transmit packet (device IN/host OUT)
-                                                           - 2'b10: PING/CSPLIT token
-                                                           - 2'b11: Channel halt command
-                                                         * Bit [24]: Terminate (last entry for selected channel/endpoint) */
-        uint32_t nptxqspcavail           : 8;       /**< Non-Periodic Transmit Request Queue Space Available
-                                                         (NPTxQSpcAvail)
-                                                         Indicates the amount of free space available in the Non-
-                                                         Periodic Transmit Request Queue. This queue holds both IN
-                                                         and OUT requests in Host mode. Device mode has only IN
-                                                         requests.
-                                                         * 8'h0: Non-Periodic Transmit Request Queue is full
-                                                         * 8'h1: 1 location available
-                                                         * 8'h2: 2 locations available
-                                                         * n: n locations available (0..8)
-                                                         * Others: Reserved */
-        uint32_t nptxfspcavail           : 16;      /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
-                                                         Indicates the amount of free space available in the Non-
-                                                         Periodic TxFIFO.
-                                                         Values are in terms of 32-bit words.
-                                                         * 16'h0: Non-Periodic TxFIFO is full
-                                                         * 16'h1: 1 word available
-                                                         * 16'h2: 2 words available
-                                                         * 16'hn: n words available (where 0..32768)
-                                                         * 16'h8000: 32768 words available
-                                                         * Others: Reserved */
-#else
-        uint32_t nptxfspcavail           : 16;
-        uint32_t nptxqspcavail           : 8;
-        uint32_t nptxqtop                : 7;
-        uint32_t reserved_31_31          : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_gnptxsts_s         cn30xx;
-    struct cvmx_usbcx_gnptxsts_s         cn31xx;
-    struct cvmx_usbcx_gnptxsts_s         cn50xx;
-    struct cvmx_usbcx_gnptxsts_s         cn52xx;
-    struct cvmx_usbcx_gnptxsts_s         cn52xxp1;
-    struct cvmx_usbcx_gnptxsts_s         cn56xx;
-    struct cvmx_usbcx_gnptxsts_s         cn56xxp1;
-} cvmx_usbcx_gnptxsts_t;
-
-
-/**
- * cvmx_usbc#_gotgctl
- *
- * OTG Control and Status Register (GOTGCTL)
- * 
- * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gotgctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t bsesvld                 : 1;       /**< B-Session Valid (BSesVld)
-                                                         Valid only when O2P USB core is configured as a USB device.
-                                                         Indicates the Device mode transceiver status.
-                                                         * 1'b0: B-session is not valid.
-                                                         * 1'b1: B-session is valid. */
-        uint32_t asesvld                 : 1;       /**< A-Session Valid (ASesVld)
-                                                         Valid only when O2P USB core is configured as a USB host.
-                                                         Indicates the Host mode transceiver status.
-                                                         * 1'b0: A-session is not valid
-                                                         * 1'b1: A-session is valid */
-        uint32_t dbnctime                : 1;       /**< Long/Short Debounce Time (DbncTime)
-                                                         In the present version of the core this bit will only read as '0'. */
-        uint32_t conidsts                : 1;       /**< Connector ID Status (ConIDSts)
-                                                         Indicates the connector ID status on a connect event.
-                                                         * 1'b0: The O2P USB core is in A-device mode
-                                                         * 1'b1: The O2P USB core is in B-device mode */
-        uint32_t reserved_12_15          : 4;
-        uint32_t devhnpen                : 1;       /**< Device HNP Enabled (DevHNPEn)
-                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
-        uint32_t hstsethnpen             : 1;       /**< Host Set HNP Enable (HstSetHNPEn)
-                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
-        uint32_t hnpreq                  : 1;       /**< HNP Request (HNPReq)
-                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
-        uint32_t hstnegscs               : 1;       /**< Host Negotiation Success (HstNegScs)
-                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
-        uint32_t reserved_2_7            : 6;
-        uint32_t sesreq                  : 1;       /**< Session Request (SesReq)
-                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
-        uint32_t sesreqscs               : 1;       /**< Session Request Success (SesReqScs)
-                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
-#else
-        uint32_t sesreqscs               : 1;
-        uint32_t sesreq                  : 1;
-        uint32_t reserved_2_7            : 6;
-        uint32_t hstnegscs               : 1;
-        uint32_t hnpreq                  : 1;
-        uint32_t hstsethnpen             : 1;
-        uint32_t devhnpen                : 1;
-        uint32_t reserved_12_15          : 4;
-        uint32_t conidsts                : 1;
-        uint32_t dbnctime                : 1;
-        uint32_t asesvld                 : 1;
-        uint32_t bsesvld                 : 1;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_usbcx_gotgctl_s          cn30xx;
-    struct cvmx_usbcx_gotgctl_s          cn31xx;
-    struct cvmx_usbcx_gotgctl_s          cn50xx;
-    struct cvmx_usbcx_gotgctl_s          cn52xx;
-    struct cvmx_usbcx_gotgctl_s          cn52xxp1;
-    struct cvmx_usbcx_gotgctl_s          cn56xx;
-    struct cvmx_usbcx_gotgctl_s          cn56xxp1;
-} cvmx_usbcx_gotgctl_t;
-
-
-/**
- * cvmx_usbc#_gotgint
- *
- * OTG Interrupt Register (GOTGINT)
- * 
- * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
- * to clear the OTG interrupt. It is shown in Interrupt .:
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gotgint_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_20_31          : 12;
-        uint32_t dbncedone               : 1;       /**< Debounce Done (DbnceDone)
-                                                         In the present version of the code this bit is tied to '0'. */
-        uint32_t adevtoutchg             : 1;       /**< A-Device Timeout Change (ADevTOUTChg)
-                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
-        uint32_t hstnegdet               : 1;       /**< Host Negotiation Detected (HstNegDet)
-                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
-        uint32_t reserved_10_16          : 7;
-        uint32_t hstnegsucstschng        : 1;       /**< Host Negotiation Success Status Change (HstNegSucStsChng)
-                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
-        uint32_t sesreqsucstschng        : 1;       /**< Session Request Success Status Change
-                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
-        uint32_t reserved_3_7            : 5;
-        uint32_t sesenddet               : 1;       /**< Session End Detected (SesEndDet)
-                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
-        uint32_t reserved_0_1            : 2;
-#else
-        uint32_t reserved_0_1            : 2;
-        uint32_t sesenddet               : 1;
-        uint32_t reserved_3_7            : 5;
-        uint32_t sesreqsucstschng        : 1;
-        uint32_t hstnegsucstschng        : 1;
-        uint32_t reserved_10_16          : 7;
-        uint32_t hstnegdet               : 1;
-        uint32_t adevtoutchg             : 1;
-        uint32_t dbncedone               : 1;
-        uint32_t reserved_20_31          : 12;
-#endif
-    } s;
-    struct cvmx_usbcx_gotgint_s          cn30xx;
-    struct cvmx_usbcx_gotgint_s          cn31xx;
-    struct cvmx_usbcx_gotgint_s          cn50xx;
-    struct cvmx_usbcx_gotgint_s          cn52xx;
-    struct cvmx_usbcx_gotgint_s          cn52xxp1;
-    struct cvmx_usbcx_gotgint_s          cn56xx;
-    struct cvmx_usbcx_gotgint_s          cn56xxp1;
-} cvmx_usbcx_gotgint_t;
-
-
-/**
- * cvmx_usbc#_grstctl
- *
- * Core Reset Register (GRSTCTL)
- * 
- * The application uses this register to reset various hardware features inside the core.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grstctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ahbidle                 : 1;       /**< AHB Master Idle (AHBIdle)
-                                                         Indicates that the AHB Master State Machine is in the IDLE
-                                                         condition. */
-        uint32_t dmareq                  : 1;       /**< DMA Request Signal (DMAReq)
-                                                         Indicates that the DMA request is in progress. Used for debug. */
-        uint32_t reserved_11_29          : 19;
-        uint32_t txfnum                  : 5;       /**< TxFIFO Number (TxFNum)
-                                                         This is the FIFO number that must be flushed using the TxFIFO
-                                                         Flush bit. This field must not be changed until the core clears
-                                                         the TxFIFO Flush bit.
-                                                         * 5'h0: Non-Periodic TxFIFO flush
-                                                         * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
-                                                         TxFIFO flush in Host mode
-                                                         * 5'h2: Periodic TxFIFO 2 flush in Device mode
-                                                         - ...
-                                                         * 5'hF: Periodic TxFIFO 15 flush in Device mode
-                                                         * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
-                                                         core */
-        uint32_t txfflsh                 : 1;       /**< TxFIFO Flush (TxFFlsh)
-                                                         This bit selectively flushes a single or all transmit FIFOs, but
-                                                         cannot do so if the core is in the midst of a transaction.
-                                                         The application must only write this bit after checking that the
-                                                         core is neither writing to the TxFIFO nor reading from the
-                                                         TxFIFO.
-                                                         The application must wait until the core clears this bit before
-                                                         performing any operations. This bit takes 8 clocks (of phy_clk or
-                                                         hclk, whichever is slower) to clear. */
-        uint32_t rxfflsh                 : 1;       /**< RxFIFO Flush (RxFFlsh)
-                                                         The application can flush the entire RxFIFO using this bit, but
-                                                         must first ensure that the core is not in the middle of a
-                                                         transaction.
-                                                         The application must only write to this bit after checking that the
-                                                         core is neither reading from the RxFIFO nor writing to the
-                                                         RxFIFO.
-                                                         The application must wait until the bit is cleared before
-                                                         performing any other operations. This bit will take 8 clocks
-                                                         (slowest of PHY or AHB clock) to clear. */
-        uint32_t intknqflsh              : 1;       /**< IN Token Sequence Learning Queue Flush (INTknQFlsh)
-                                                         The application writes this bit to flush the IN Token Sequence
-                                                         Learning Queue. */
-        uint32_t frmcntrrst              : 1;       /**< Host Frame Counter Reset (FrmCntrRst)
-                                                         The application writes this bit to reset the (micro)frame number
-                                                         counter inside the core. When the (micro)frame counter is reset,
-                                                         the subsequent SOF sent out by the core will have a
-                                                         (micro)frame number of 0. */
-        uint32_t hsftrst                 : 1;       /**< HClk Soft Reset (HSftRst)
-                                                         The application uses this bit to flush the control logic in the AHB
-                                                         Clock domain. Only AHB Clock Domain pipelines are reset.
-                                                         * FIFOs are not flushed with this bit.
-                                                         * All state machines in the AHB clock domain are reset to the
-                                                           Idle state after terminating the transactions on the AHB,
-                                                           following the protocol.
-                                                         * CSR control bits used by the AHB clock domain state
-                                                           machines are cleared.
-                                                         * To clear this interrupt, status mask bits that control the
-                                                           interrupt status and are generated by the AHB clock domain
-                                                           state machine are cleared.
-                                                         * Because interrupt status bits are not cleared, the application
-                                                           can get the status of any core events that occurred after it set
-                                                           this bit.
-                                                           This is a self-clearing bit that the core clears after all necessary
-                                                           logic is reset in the core. This may take several clocks,
-                                                           depending on the core's current state. */
-        uint32_t csftrst                 : 1;       /**< Core Soft Reset (CSftRst)
-                                                         Resets the hclk and phy_clock domains as follows:
-                                                         * Clears the interrupts and all the CSR registers except the
-                                                           following register bits:
-                                                           - PCGCCTL.RstPdwnModule
-                                                           - PCGCCTL.GateHclk
-                                                           - PCGCCTL.PwrClmp
-                                                           - PCGCCTL.StopPPhyLPwrClkSelclk
-                                                           - GUSBCFG.PhyLPwrClkSel
-                                                           - GUSBCFG.DDRSel
-                                                           - GUSBCFG.PHYSel
-                                                           - GUSBCFG.FSIntf
-                                                           - GUSBCFG.ULPI_UTMI_Sel
-                                                           - GUSBCFG.PHYIf
-                                                           - HCFG.FSLSPclkSel
-                                                           - DCFG.DevSpd
-                                                         * All module state machines (except the AHB Slave Unit) are
-                                                           reset to the IDLE state, and all the transmit FIFOs and the
-                                                           receive FIFO are flushed.
-                                                         * Any transactions on the AHB Master are terminated as soon
-                                                           as possible, after gracefully completing the last data phase of
-                                                           an AHB transfer. Any transactions on the USB are terminated
-                                                           immediately.
-                                                           The application can write to this bit any time it wants to reset
-                                                           the core. This is a self-clearing bit and the core clears this bit
-                                                           after all the necessary logic is reset in the core, which may take
-                                                           several clocks, depending on the current state of the core.
-                                                           Once this bit is cleared software should wait at least 3 PHY
-                                                           clocks before doing any access to the PHY domain
-                                                           (synchronization delay). Software should also should check that
-                                                           bit 31 of this register is 1 (AHB Master is IDLE) before starting
-                                                           any operation.
-                                                           Typically software reset is used during software development
-                                                           and also when you dynamically change the PHY selection bits
-                                                           in the USB configuration registers listed above. When you
-                                                           change the PHY, the corresponding clock for the PHY is
-                                                           selected and used in the PHY domain. Once a new clock is
-                                                           selected, the PHY domain has to be reset for proper operation. */
-#else
-        uint32_t csftrst                 : 1;
-        uint32_t hsftrst                 : 1;
-        uint32_t frmcntrrst              : 1;
-        uint32_t intknqflsh              : 1;
-        uint32_t rxfflsh                 : 1;
-        uint32_t txfflsh                 : 1;
-        uint32_t txfnum                  : 5;
-        uint32_t reserved_11_29          : 19;
-        uint32_t dmareq                  : 1;
-        uint32_t ahbidle                 : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_grstctl_s          cn30xx;
-    struct cvmx_usbcx_grstctl_s          cn31xx;
-    struct cvmx_usbcx_grstctl_s          cn50xx;
-    struct cvmx_usbcx_grstctl_s          cn52xx;
-    struct cvmx_usbcx_grstctl_s          cn52xxp1;
-    struct cvmx_usbcx_grstctl_s          cn56xx;
-    struct cvmx_usbcx_grstctl_s          cn56xxp1;
-} cvmx_usbcx_grstctl_t;
-
-
-/**
- * cvmx_usbc#_grxfsiz
- *
- * Receive FIFO Size Register (GRXFSIZ)
- * 
- * The application can program the RAM size that must be allocated to the RxFIFO.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grxfsiz_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t rxfdep                  : 16;      /**< RxFIFO Depth (RxFDep)
-                                                         This value is in terms of 32-bit words.
-                                                         * Minimum value is 16
-                                                         * Maximum value is 32768 */
-#else
-        uint32_t rxfdep                  : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_grxfsiz_s          cn30xx;
-    struct cvmx_usbcx_grxfsiz_s          cn31xx;
-    struct cvmx_usbcx_grxfsiz_s          cn50xx;
-    struct cvmx_usbcx_grxfsiz_s          cn52xx;
-    struct cvmx_usbcx_grxfsiz_s          cn52xxp1;
-    struct cvmx_usbcx_grxfsiz_s          cn56xx;
-    struct cvmx_usbcx_grxfsiz_s          cn56xxp1;
-} cvmx_usbcx_grxfsiz_t;
-
-
-/**
- * cvmx_usbc#_grxstspd
- *
- * Receive Status Debug Read Register, Device Mode (GRXSTSPD)
- * 
- * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
- * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSPH instead.
- * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
- *       The offset difference shown in this document is for software clarity and is actually ignored by the
- *       hardware.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grxstspd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_25_31          : 7;
-        uint32_t fn                      : 4;       /**< Frame Number (FN)
-                                                         This is the least significant 4 bits of the (micro)frame number in
-                                                         which the packet is received on the USB.  This field is supported
-                                                         only when the isochronous OUT endpoints are supported. */
-        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
-                                                         Indicates the status of the received packet
-                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
-                                                         * 4'b0010: OUT data packet received
-                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
-                                                         * 4'b0110: SETUP data packet received
-                                                         * Others: Reserved */
-        uint32_t dpid                    : 2;       /**< Data PID (DPID)
-                                                         * 2'b00: DATA0
-                                                         * 2'b10: DATA1
-                                                         * 2'b01: DATA2
-                                                         * 2'b11: MDATA */
-        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
-                                                         Indicates the byte count of the received data packet */
-        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
-                                                         Indicates the endpoint number to which the current received
-                                                         packet belongs. */
-#else
-        uint32_t epnum                   : 4;
-        uint32_t bcnt                    : 11;
-        uint32_t dpid                    : 2;
-        uint32_t pktsts                  : 4;
-        uint32_t fn                      : 4;
-        uint32_t reserved_25_31          : 7;
-#endif
-    } s;
-    struct cvmx_usbcx_grxstspd_s         cn30xx;
-    struct cvmx_usbcx_grxstspd_s         cn31xx;
-    struct cvmx_usbcx_grxstspd_s         cn50xx;
-    struct cvmx_usbcx_grxstspd_s         cn52xx;
-    struct cvmx_usbcx_grxstspd_s         cn52xxp1;
-    struct cvmx_usbcx_grxstspd_s         cn56xx;
-    struct cvmx_usbcx_grxstspd_s         cn56xxp1;
-} cvmx_usbcx_grxstspd_t;
-
-
-/**
- * cvmx_usbc#_grxstsph
- *
- * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
- * 
- * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
- * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSPD instead.
- * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
- *       The offset difference shown in this document is for software clarity and is actually ignored by the
- *       hardware.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grxstsph_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
-                                                         Indicates the status of the received packet
-                                                         * 4'b0010: IN data packet received
-                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
-                                                         * 4'b0101: Data toggle error (triggers an interrupt)
-                                                         * 4'b0111: Channel halted (triggers an interrupt)
-                                                         * Others: Reserved */
-        uint32_t dpid                    : 2;       /**< Data PID (DPID)
-                                                         * 2'b00: DATA0
-                                                         * 2'b10: DATA1
-                                                         * 2'b01: DATA2
-                                                         * 2'b11: MDATA */
-        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
-                                                         Indicates the byte count of the received IN data packet */
-        uint32_t chnum                   : 4;       /**< Channel Number (ChNum)
-                                                         Indicates the channel number to which the current received
-                                                         packet belongs. */
-#else
-        uint32_t chnum                   : 4;
-        uint32_t bcnt                    : 11;
-        uint32_t dpid                    : 2;
-        uint32_t pktsts                  : 4;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_usbcx_grxstsph_s         cn30xx;
-    struct cvmx_usbcx_grxstsph_s         cn31xx;
-    struct cvmx_usbcx_grxstsph_s         cn50xx;
-    struct cvmx_usbcx_grxstsph_s         cn52xx;
-    struct cvmx_usbcx_grxstsph_s         cn52xxp1;
-    struct cvmx_usbcx_grxstsph_s         cn56xx;
-    struct cvmx_usbcx_grxstsph_s         cn56xxp1;
-} cvmx_usbcx_grxstsph_t;
-
-
-/**
- * cvmx_usbc#_grxstsrd
- *
- * Receive Status Debug Read Register, Device Mode (GRXSTSRD)
- * 
- * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
- * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSRH instead.
- * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
- *       The offset difference shown in this document is for software clarity and is actually ignored by the
- *       hardware.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grxstsrd_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_25_31          : 7;
-        uint32_t fn                      : 4;       /**< Frame Number (FN)
-                                                         This is the least significant 4 bits of the (micro)frame number in
-                                                         which the packet is received on the USB.  This field is supported
-                                                         only when the isochronous OUT endpoints are supported. */
-        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
-                                                         Indicates the status of the received packet
-                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
-                                                         * 4'b0010: OUT data packet received
-                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
-                                                         * 4'b0110: SETUP data packet received
-                                                         * Others: Reserved */
-        uint32_t dpid                    : 2;       /**< Data PID (DPID)
-                                                         * 2'b00: DATA0
-                                                         * 2'b10: DATA1
-                                                         * 2'b01: DATA2
-                                                         * 2'b11: MDATA */
-        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
-                                                         Indicates the byte count of the received data packet */
-        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
-                                                         Indicates the endpoint number to which the current received
-                                                         packet belongs. */
-#else
-        uint32_t epnum                   : 4;
-        uint32_t bcnt                    : 11;
-        uint32_t dpid                    : 2;
-        uint32_t pktsts                  : 4;
-        uint32_t fn                      : 4;
-        uint32_t reserved_25_31          : 7;
-#endif
-    } s;
-    struct cvmx_usbcx_grxstsrd_s         cn30xx;
-    struct cvmx_usbcx_grxstsrd_s         cn31xx;
-    struct cvmx_usbcx_grxstsrd_s         cn50xx;
-    struct cvmx_usbcx_grxstsrd_s         cn52xx;
-    struct cvmx_usbcx_grxstsrd_s         cn52xxp1;
-    struct cvmx_usbcx_grxstsrd_s         cn56xx;
-    struct cvmx_usbcx_grxstsrd_s         cn56xxp1;
-} cvmx_usbcx_grxstsrd_t;
-
-
-/**
- * cvmx_usbc#_grxstsrh
- *
- * Receive Status Debug Read Register, Host Mode (GRXSTSRH)
- * 
- * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
- * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSRD instead.
- * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
- *       The offset difference shown in this document is for software clarity and is actually ignored by the
- *       hardware.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_grxstsrh_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_21_31          : 11;
-        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
-                                                         Indicates the status of the received packet
-                                                         * 4'b0010: IN data packet received
-                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
-                                                         * 4'b0101: Data toggle error (triggers an interrupt)
-                                                         * 4'b0111: Channel halted (triggers an interrupt)
-                                                         * Others: Reserved */
-        uint32_t dpid                    : 2;       /**< Data PID (DPID)
-                                                         * 2'b00: DATA0
-                                                         * 2'b10: DATA1
-                                                         * 2'b01: DATA2
-                                                         * 2'b11: MDATA */
-        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
-                                                         Indicates the byte count of the received IN data packet */
-        uint32_t chnum                   : 4;       /**< Channel Number (ChNum)
-                                                         Indicates the channel number to which the current received
-                                                         packet belongs. */
-#else
-        uint32_t chnum                   : 4;
-        uint32_t bcnt                    : 11;
-        uint32_t dpid                    : 2;
-        uint32_t pktsts                  : 4;
-        uint32_t reserved_21_31          : 11;
-#endif
-    } s;
-    struct cvmx_usbcx_grxstsrh_s         cn30xx;
-    struct cvmx_usbcx_grxstsrh_s         cn31xx;
-    struct cvmx_usbcx_grxstsrh_s         cn50xx;
-    struct cvmx_usbcx_grxstsrh_s         cn52xx;
-    struct cvmx_usbcx_grxstsrh_s         cn52xxp1;
-    struct cvmx_usbcx_grxstsrh_s         cn56xx;
-    struct cvmx_usbcx_grxstsrh_s         cn56xxp1;
-} cvmx_usbcx_grxstsrh_t;
-
-
-/**
- * cvmx_usbc#_gsnpsid
- *
- * Synopsys ID Register (GSNPSID)
- * 
- * This is a read-only register that contains the release number of the core being used.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gsnpsid_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t synopsysid              : 32;      /**< 0x4F54\<version\>A, release number of the core being used.
-                                                         0x4F54220A => pass1.x,  0x4F54240A => pass2.x */
-#else
-        uint32_t synopsysid              : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_gsnpsid_s          cn30xx;
-    struct cvmx_usbcx_gsnpsid_s          cn31xx;
-    struct cvmx_usbcx_gsnpsid_s          cn50xx;
-    struct cvmx_usbcx_gsnpsid_s          cn52xx;
-    struct cvmx_usbcx_gsnpsid_s          cn52xxp1;
-    struct cvmx_usbcx_gsnpsid_s          cn56xx;
-    struct cvmx_usbcx_gsnpsid_s          cn56xxp1;
-} cvmx_usbcx_gsnpsid_t;
-
-
-/**
- * cvmx_usbc#_gusbcfg
- *
- * Core USB Configuration Register (GUSBCFG)
- * 
- * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
- * It contains USB and USB-PHY related configuration parameters. The application must program this register
- * before starting any transactions on either the AHB or the USB.
- * Do not make changes to this register after the initial programming.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_gusbcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_17_31          : 15;
-        uint32_t otgi2csel               : 1;       /**< UTMIFS or I2C Interface Select (OtgI2CSel)
-                                                         This bit is always 0x0. */
-        uint32_t phylpwrclksel           : 1;       /**< PHY Low-Power Clock Select (PhyLPwrClkSel)
-                                                         Software should set this bit to 0x0.
-                                                         Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
-                                                         FS and LS modes, the PHY can usually operate on a 48-MHz
-                                                         clock to save power.
-                                                         * 1'b0: 480-MHz Internal PLL clock
-                                                         * 1'b1: 48-MHz External Clock
-                                                         In 480 MHz mode, the UTMI interface operates at either 60 or
-                                                         30-MHz, depending upon whether 8- or 16-bit data width is
-                                                         selected. In 48-MHz mode, the UTMI interface operates at 48
-                                                         MHz in FS mode and at either 48 or 6 MHz in LS mode
-                                                         (depending on the PHY vendor).
-                                                         This bit drives the utmi_fsls_low_power core output signal, and
-                                                         is valid only for UTMI+ PHYs. */
-        uint32_t reserved_14_14          : 1;
-        uint32_t usbtrdtim               : 4;       /**< USB Turnaround Time (USBTrdTim)
-                                                         Sets the turnaround time in PHY clocks.
-                                                         Specifies the response time for a MAC request to the Packet
-                                                         FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
-                                                         This must be programmed to 0x5. */
-        uint32_t hnpcap                  : 1;       /**< HNP-Capable (HNPCap)
-                                                         This bit is always 0x0. */
-        uint32_t srpcap                  : 1;       /**< SRP-Capable (SRPCap)
-                                                         This bit is always 0x0. */
-        uint32_t ddrsel                  : 1;       /**< ULPI DDR Select (DDRSel)
-                                                         Software should set this bit to 0x0. */
-        uint32_t physel                  : 1;       /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
-                                                         Software should set this bit to 0x0. */
-        uint32_t fsintf                  : 1;       /**< Full-Speed Serial Interface Select (FSIntf)
-                                                         Software should set this bit to 0x0. */
-        uint32_t ulpi_utmi_sel           : 1;       /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel)
-                                                         This bit is always 0x0. */
-        uint32_t phyif                   : 1;       /**< PHY Interface (PHYIf)
-                                                         This bit is always 0x1. */
-        uint32_t toutcal                 : 3;       /**< HS/FS Timeout Calibration (TOutCal)
-                                                         The number of PHY clocks that the application programs in this
-                                                         field is added to the high-speed/full-speed interpacket timeout
-                                                         duration in the core to account for any additional delays
-                                                         introduced by the PHY. This may be required, since the delay
-                                                         introduced by the PHY in generating the linestate condition may
-                                                         vary from one PHY to another.
-                                                         The USB standard timeout value for high-speed operation is
-                                                         736 to 816 (inclusive) bit times. The USB standard timeout
-                                                         value for full-speed operation is 16 to 18 (inclusive) bit times.
-                                                         The application must program this field based on the speed of
-                                                         enumeration. The number of bit times added per PHY clock are:
-                                                         High-speed operation:
-                                                         * One 30-MHz PHY clock = 16 bit times
-                                                         * One 60-MHz PHY clock = 8 bit times
-                                                         Full-speed operation:
-                                                         * One 30-MHz PHY clock = 0.4 bit times
-                                                         * One 60-MHz PHY clock = 0.2 bit times
-                                                         * One 48-MHz PHY clock = 0.25 bit times */
-#else
-        uint32_t toutcal                 : 3;
-        uint32_t phyif                   : 1;
-        uint32_t ulpi_utmi_sel           : 1;
-        uint32_t fsintf                  : 1;
-        uint32_t physel                  : 1;
-        uint32_t ddrsel                  : 1;
-        uint32_t srpcap                  : 1;
-        uint32_t hnpcap                  : 1;
-        uint32_t usbtrdtim               : 4;
-        uint32_t reserved_14_14          : 1;
-        uint32_t phylpwrclksel           : 1;
-        uint32_t otgi2csel               : 1;
-        uint32_t reserved_17_31          : 15;
-#endif
-    } s;
-    struct cvmx_usbcx_gusbcfg_s          cn30xx;
-    struct cvmx_usbcx_gusbcfg_s          cn31xx;
-    struct cvmx_usbcx_gusbcfg_s          cn50xx;
-    struct cvmx_usbcx_gusbcfg_s          cn52xx;
-    struct cvmx_usbcx_gusbcfg_s          cn52xxp1;
-    struct cvmx_usbcx_gusbcfg_s          cn56xx;
-    struct cvmx_usbcx_gusbcfg_s          cn56xxp1;
-} cvmx_usbcx_gusbcfg_t;
-
-
-/**
- * cvmx_usbc#_haint
- *
- * Host All Channels Interrupt Register (HAINT)
- * 
- * When a significant event occurs on a channel, the Host All Channels Interrupt register
- * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
- * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
- * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
- * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_haint_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t haint                   : 16;      /**< Channel Interrupts (HAINT)
-                                                         One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
-#else
-        uint32_t haint                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_haint_s            cn30xx;
-    struct cvmx_usbcx_haint_s            cn31xx;
-    struct cvmx_usbcx_haint_s            cn50xx;
-    struct cvmx_usbcx_haint_s            cn52xx;
-    struct cvmx_usbcx_haint_s            cn52xxp1;
-    struct cvmx_usbcx_haint_s            cn56xx;
-    struct cvmx_usbcx_haint_s            cn56xxp1;
-} cvmx_usbcx_haint_t;
-
-
-/**
- * cvmx_usbc#_haintmsk
- *
- * Host All Channels Interrupt Mask Register (HAINTMSK)
- * 
- * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
- * register to interrupt the application when an event occurs on a channel. There is one
- * interrupt mask bit per channel, up to a maximum of 16 bits.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_haintmsk_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t haintmsk                : 16;      /**< Channel Interrupt Mask (HAINTMsk)
-                                                         One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
-#else
-        uint32_t haintmsk                : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_haintmsk_s         cn30xx;
-    struct cvmx_usbcx_haintmsk_s         cn31xx;
-    struct cvmx_usbcx_haintmsk_s         cn50xx;
-    struct cvmx_usbcx_haintmsk_s         cn52xx;
-    struct cvmx_usbcx_haintmsk_s         cn52xxp1;
-    struct cvmx_usbcx_haintmsk_s         cn56xx;
-    struct cvmx_usbcx_haintmsk_s         cn56xxp1;
-} cvmx_usbcx_haintmsk_t;
-
-
-/**
- * cvmx_usbc#_hcchar#
- *
- * Host Channel-n Characteristics Register (HCCHAR)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hccharx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t chena                   : 1;       /**< Channel Enable (ChEna)
-                                                         This field is set by the application and cleared by the OTG host.
-                                                         * 1'b0: Channel disabled
-                                                         * 1'b1: Channel enabled */
-        uint32_t chdis                   : 1;       /**< Channel Disable (ChDis)
-                                                         The application sets this bit to stop transmitting/receiving data
-                                                         on a channel, even before the transfer for that channel is
-                                                         complete. The application must wait for the Channel Disabled
-                                                         interrupt before treating the channel as disabled. */
-        uint32_t oddfrm                  : 1;       /**< Odd Frame (OddFrm)
-                                                         This field is set (reset) by the application to indicate that the
-                                                         OTG host must perform a transfer in an odd (micro)frame. This
-                                                         field is applicable for only periodic (isochronous and interrupt)
-                                                         transactions.
-                                                         * 1'b0: Even (micro)frame
-                                                         * 1'b1: Odd (micro)frame */
-        uint32_t devaddr                 : 7;       /**< Device Address (DevAddr)
-                                                         This field selects the specific device serving as the data source
-                                                         or sink. */
-        uint32_t ec                      : 2;       /**< Multi Count (MC) / Error Count (EC)
-                                                         When the Split Enable bit of the Host Channel-n Split Control
-                                                         register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
-                                                         to the host the number of transactions that should be executed
-                                                         per microframe for this endpoint.
-                                                         * 2'b00: Reserved. This field yields undefined results.
-                                                         * 2'b01: 1 transaction
-                                                         * 2'b10: 2 transactions to be issued for this endpoint per
-                                                                  microframe
-                                                         * 2'b11: 3 transactions to be issued for this endpoint per
-                                                                  microframe
-                                                         When HCSPLTn.SpltEna is set (1'b1), this field indicates the
-                                                         number of immediate retries to be performed for a periodic split
-                                                         transactions on transaction errors. This field must be set to at
-                                                         least 2'b01. */
-        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
-                                                         Indicates the transfer type selected.
-                                                         * 2'b00: Control
-                                                         * 2'b01: Isochronous
-                                                         * 2'b10: Bulk
-                                                         * 2'b11: Interrupt */
-        uint32_t lspddev                 : 1;       /**< Low-Speed Device (LSpdDev)
-                                                         This field is set by the application to indicate that this channel is
-                                                         communicating to a low-speed device. */
-        uint32_t reserved_16_16          : 1;
-        uint32_t epdir                   : 1;       /**< Endpoint Direction (EPDir)
-                                                         Indicates whether the transaction is IN or OUT.
-                                                         * 1'b0: OUT
-                                                         * 1'b1: IN */
-        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
-                                                         Indicates the endpoint number on the device serving as the
-                                                         data source or sink. */
-        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
-                                                         Indicates the maximum packet size of the associated endpoint. */
-#else
-        uint32_t mps                     : 11;
-        uint32_t epnum                   : 4;
-        uint32_t epdir                   : 1;
-        uint32_t reserved_16_16          : 1;
-        uint32_t lspddev                 : 1;
-        uint32_t eptype                  : 2;
-        uint32_t ec                      : 2;
-        uint32_t devaddr                 : 7;
-        uint32_t oddfrm                  : 1;
-        uint32_t chdis                   : 1;
-        uint32_t chena                   : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_hccharx_s          cn30xx;
-    struct cvmx_usbcx_hccharx_s          cn31xx;
-    struct cvmx_usbcx_hccharx_s          cn50xx;
-    struct cvmx_usbcx_hccharx_s          cn52xx;
-    struct cvmx_usbcx_hccharx_s          cn52xxp1;
-    struct cvmx_usbcx_hccharx_s          cn56xx;
-    struct cvmx_usbcx_hccharx_s          cn56xxp1;
-} cvmx_usbcx_hccharx_t;
-
-
-/**
- * cvmx_usbc#_hcfg
- *
- * Host Configuration Register (HCFG)
- * 
- * This register configures the core after power-on. Do not make changes to this register after initializing the host.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hcfg_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_3_31           : 29;
-        uint32_t fslssupp                : 1;       /**< FS- and LS-Only Support (FSLSSupp)
-                                                         The application uses this bit to control the core's enumeration
-                                                         speed. Using this bit, the application can make the core
-                                                         enumerate as a FS host, even if the connected device supports
-                                                         HS traffic. Do not make changes to this field after initial
-                                                         programming.
-                                                         * 1'b0: HS/FS/LS, based on the maximum speed supported by
-                                                           the connected device
-                                                         * 1'b1: FS/LS-only, even if the connected device can support HS */
-        uint32_t fslspclksel             : 2;       /**< FS/LS PHY Clock Select (FSLSPclkSel)
-                                                         When the core is in FS Host mode
-                                                         * 2'b00: PHY clock is running at 30/60 MHz
-                                                         * 2'b01: PHY clock is running at 48 MHz
-                                                         * Others: Reserved
-                                                         When the core is in LS Host mode
-                                                         * 2'b00: PHY clock is running at 30/60 MHz. When the
-                                                                  UTMI+/ULPI PHY Low Power mode is not selected, use
-                                                                  30/60 MHz.
-                                                         * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
-                                                                  PHY Low Power mode is selected, use 48MHz if the PHY
-                                                                  supplies a 48 MHz clock during LS mode.
-                                                         * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
-                                                                  use 6 MHz when the UTMI+ PHY Low Power mode is
-                                                                  selected and the PHY supplies a 6 MHz clock during LS
-                                                                  mode. If you select a 6 MHz clock during LS mode, you must
-                                                                  do a soft reset.
-                                                         * 2'b11: Reserved */
-#else
-        uint32_t fslspclksel             : 2;
-        uint32_t fslssupp                : 1;
-        uint32_t reserved_3_31           : 29;
-#endif
-    } s;
-    struct cvmx_usbcx_hcfg_s             cn30xx;
-    struct cvmx_usbcx_hcfg_s             cn31xx;
-    struct cvmx_usbcx_hcfg_s             cn50xx;
-    struct cvmx_usbcx_hcfg_s             cn52xx;
-    struct cvmx_usbcx_hcfg_s             cn52xxp1;
-    struct cvmx_usbcx_hcfg_s             cn56xx;
-    struct cvmx_usbcx_hcfg_s             cn56xxp1;
-} cvmx_usbcx_hcfg_t;
-
-
-/**
- * cvmx_usbc#_hcint#
- *
- * Host Channel-n Interrupt Register (HCINT)
- * 
- * This register indicates the status of a channel with respect to USB- and AHB-related events.
- * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
- * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
- * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
- * Interrupt register. The application must clear the appropriate bit in this register to clear the
- * corresponding bits in the HAINT and GINTSTS registers.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hcintx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_11_31          : 21;
-        uint32_t datatglerr              : 1;       /**< Data Toggle Error (DataTglErr) */
-        uint32_t frmovrun                : 1;       /**< Frame Overrun (FrmOvrun) */
-        uint32_t bblerr                  : 1;       /**< Babble Error (BblErr) */
-        uint32_t xacterr                 : 1;       /**< Transaction Error (XactErr) */
-        uint32_t nyet                    : 1;       /**< NYET Response Received Interrupt (NYET) */
-        uint32_t ack                     : 1;       /**< ACK Response Received Interrupt (ACK) */
-        uint32_t nak                     : 1;       /**< NAK Response Received Interrupt (NAK) */
-        uint32_t stall                   : 1;       /**< STALL Response Received Interrupt (STALL) */
-        uint32_t ahberr                  : 1;       /**< This bit is always 0x0. */
-        uint32_t chhltd                  : 1;       /**< Channel Halted (ChHltd)
-                                                         Indicates the transfer completed abnormally either because of
-                                                         any USB transaction error or in response to disable request by
-                                                         the application. */
-        uint32_t xfercompl               : 1;       /**< Transfer Completed (XferCompl)
-                                                         Transfer completed normally without any errors. */
-#else
-        uint32_t xfercompl               : 1;
-        uint32_t chhltd                  : 1;
-        uint32_t ahberr                  : 1;
-        uint32_t stall                   : 1;
-        uint32_t nak                     : 1;
-        uint32_t ack                     : 1;
-        uint32_t nyet                    : 1;
-        uint32_t xacterr                 : 1;
-        uint32_t bblerr                  : 1;
-        uint32_t frmovrun                : 1;
-        uint32_t datatglerr              : 1;
-        uint32_t reserved_11_31          : 21;
-#endif
-    } s;
-    struct cvmx_usbcx_hcintx_s           cn30xx;
-    struct cvmx_usbcx_hcintx_s           cn31xx;
-    struct cvmx_usbcx_hcintx_s           cn50xx;
-    struct cvmx_usbcx_hcintx_s           cn52xx;
-    struct cvmx_usbcx_hcintx_s           cn52xxp1;
-    struct cvmx_usbcx_hcintx_s           cn56xx;
-    struct cvmx_usbcx_hcintx_s           cn56xxp1;
-} cvmx_usbcx_hcintx_t;
-
-
-/**
- * cvmx_usbc#_hcintmsk#
- *
- * Host Channel-n Interrupt Mask Register (HCINTMSKn)
- * 
- * This register reflects the mask for each channel status described in the previous section.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hcintmskx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_11_31          : 21;
-        uint32_t datatglerrmsk           : 1;       /**< Data Toggle Error Mask (DataTglErrMsk) */
-        uint32_t frmovrunmsk             : 1;       /**< Frame Overrun Mask (FrmOvrunMsk) */
-        uint32_t bblerrmsk               : 1;       /**< Babble Error Mask (BblErrMsk) */
-        uint32_t xacterrmsk              : 1;       /**< Transaction Error Mask (XactErrMsk) */
-        uint32_t nyetmsk                 : 1;       /**< NYET Response Received Interrupt Mask (NyetMsk) */
-        uint32_t ackmsk                  : 1;       /**< ACK Response Received Interrupt Mask (AckMsk) */
-        uint32_t nakmsk                  : 1;       /**< NAK Response Received Interrupt Mask (NakMsk) */
-        uint32_t stallmsk                : 1;       /**< STALL Response Received Interrupt Mask (StallMsk) */
-        uint32_t ahberrmsk               : 1;       /**< AHB Error Mask (AHBErrMsk) */
-        uint32_t chhltdmsk               : 1;       /**< Channel Halted Mask (ChHltdMsk) */
-        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Mask (XferComplMsk) */
-#else
-        uint32_t xfercomplmsk            : 1;
-        uint32_t chhltdmsk               : 1;
-        uint32_t ahberrmsk               : 1;
-        uint32_t stallmsk                : 1;
-        uint32_t nakmsk                  : 1;
-        uint32_t ackmsk                  : 1;
-        uint32_t nyetmsk                 : 1;
-        uint32_t xacterrmsk              : 1;
-        uint32_t bblerrmsk               : 1;
-        uint32_t frmovrunmsk             : 1;
-        uint32_t datatglerrmsk           : 1;
-        uint32_t reserved_11_31          : 21;
-#endif
-    } s;
-    struct cvmx_usbcx_hcintmskx_s        cn30xx;
-    struct cvmx_usbcx_hcintmskx_s        cn31xx;
-    struct cvmx_usbcx_hcintmskx_s        cn50xx;
-    struct cvmx_usbcx_hcintmskx_s        cn52xx;
-    struct cvmx_usbcx_hcintmskx_s        cn52xxp1;
-    struct cvmx_usbcx_hcintmskx_s        cn56xx;
-    struct cvmx_usbcx_hcintmskx_s        cn56xxp1;
-} cvmx_usbcx_hcintmskx_t;
-
-
-/**
- * cvmx_usbc#_hcsplt#
- *
- * Host Channel-n Split Control Register (HCSPLT)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hcspltx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t spltena                 : 1;       /**< Split Enable (SpltEna)
-                                                         The application sets this field to indicate that this channel is
-                                                         enabled to perform split transactions. */
-        uint32_t reserved_17_30          : 14;
-        uint32_t compsplt                : 1;       /**< Do Complete Split (CompSplt)
-                                                         The application sets this field to request the OTG host to
-                                                         perform a complete split transaction. */
-        uint32_t xactpos                 : 2;       /**< Transaction Position (XactPos)
-                                                         This field is used to determine whether to send all, first, middle,
-                                                         or last payloads with each OUT transaction.
-                                                         * 2'b11: All. This is the entire data payload is of this transaction
-                                                                  (which is less than or equal to 188 bytes).
-                                                         * 2'b10: Begin. This is the first data payload of this transaction
-                                                                  (which is larger than 188 bytes).
-                                                         * 2'b00: Mid. This is the middle payload of this transaction
-                                                                  (which is larger than 188 bytes).
-                                                         * 2'b01: End. This is the last payload of this transaction (which
-                                                                  is larger than 188 bytes). */
-        uint32_t hubaddr                 : 7;       /**< Hub Address (HubAddr)
-                                                         This field holds the device address of the transaction
-                                                         translator's hub. */
-        uint32_t prtaddr                 : 7;       /**< Port Address (PrtAddr)
-                                                         This field is the port number of the recipient transaction
-                                                         translator. */
-#else
-        uint32_t prtaddr                 : 7;
-        uint32_t hubaddr                 : 7;
-        uint32_t xactpos                 : 2;
-        uint32_t compsplt                : 1;
-        uint32_t reserved_17_30          : 14;
-        uint32_t spltena                 : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_hcspltx_s          cn30xx;
-    struct cvmx_usbcx_hcspltx_s          cn31xx;
-    struct cvmx_usbcx_hcspltx_s          cn50xx;
-    struct cvmx_usbcx_hcspltx_s          cn52xx;
-    struct cvmx_usbcx_hcspltx_s          cn52xxp1;
-    struct cvmx_usbcx_hcspltx_s          cn56xx;
-    struct cvmx_usbcx_hcspltx_s          cn56xxp1;
-} cvmx_usbcx_hcspltx_t;
-
-
-/**
- * cvmx_usbc#_hctsiz#
- *
- * Host Channel-n Transfer Size Register (HCTSIZ)
- *
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hctsizx_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t dopng                   : 1;       /**< Do Ping (DoPng)
-                                                         Setting this field to 1 directs the host to do PING protocol. */
-        uint32_t pid                     : 2;       /**< PID (Pid)
-                                                         The application programs this field with the type of PID to use
-                                                         for the initial transaction. The host will maintain this field for the
-                                                         rest of the transfer.
-                                                         * 2'b00: DATA0
-                                                         * 2'b01: DATA2
-                                                         * 2'b10: DATA1
-                                                         * 2'b11: MDATA (non-control)/SETUP (control) */
-        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
-                                                         This field is programmed by the application with the expected
-                                                         number of packets to be transmitted (OUT) or received (IN).
-                                                         The host decrements this count on every successful
-                                                         transmission or reception of an OUT/IN packet. Once this count
-                                                         reaches zero, the application is interrupted to indicate normal
-                                                         completion. */
-        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
-                                                         For an OUT, this field is the number of data bytes the host will
-                                                         send during the transfer.
-                                                         For an IN, this field is the buffer size that the application has
-                                                         reserved for the transfer. The application is expected to
-                                                         program this field as an integer multiple of the maximum packet
-                                                         size for IN transactions (periodic and non-periodic). */
-#else
-        uint32_t xfersize                : 19;
-        uint32_t pktcnt                  : 10;
-        uint32_t pid                     : 2;
-        uint32_t dopng                   : 1;
-#endif
-    } s;
-    struct cvmx_usbcx_hctsizx_s          cn30xx;
-    struct cvmx_usbcx_hctsizx_s          cn31xx;
-    struct cvmx_usbcx_hctsizx_s          cn50xx;
-    struct cvmx_usbcx_hctsizx_s          cn52xx;
-    struct cvmx_usbcx_hctsizx_s          cn52xxp1;
-    struct cvmx_usbcx_hctsizx_s          cn56xx;
-    struct cvmx_usbcx_hctsizx_s          cn56xxp1;
-} cvmx_usbcx_hctsizx_t;
-
-
-/**
- * cvmx_usbc#_hfir
- *
- * Host Frame Interval Register (HFIR)
- * 
- * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hfir_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_16_31          : 16;
-        uint32_t frint                   : 16;      /**< Frame Interval (FrInt)
-                                                         The value that the application programs to this field specifies
-                                                         the interval between two consecutive SOFs (FS) or micro-
-                                                         SOFs (HS) or Keep-Alive tokens (HS). This field contains the
-                                                         number of PHY clocks that constitute the required frame
-                                                         interval. The default value set in this field for a FS operation
-                                                         when the PHY clock frequency is 60 MHz. The application can
-                                                         write a value to this register only after the Port Enable bit of
-                                                         the Host Port Control and Status register (HPRT.PrtEnaPort)
-                                                         has been set. If no value is programmed, the core calculates
-                                                         the value based on the PHY clock specified in the FS/LS PHY
-                                                         Clock Select field of the Host Configuration register
-                                                         (HCFG.FSLSPclkSel). Do not change the value of this field
-                                                         after the initial configuration.
-                                                         * 125 us (PHY clock frequency for HS)
-                                                         * 1 ms (PHY clock frequency for FS/LS) */
-#else
-        uint32_t frint                   : 16;
-        uint32_t reserved_16_31          : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_hfir_s             cn30xx;
-    struct cvmx_usbcx_hfir_s             cn31xx;
-    struct cvmx_usbcx_hfir_s             cn50xx;
-    struct cvmx_usbcx_hfir_s             cn52xx;
-    struct cvmx_usbcx_hfir_s             cn52xxp1;
-    struct cvmx_usbcx_hfir_s             cn56xx;
-    struct cvmx_usbcx_hfir_s             cn56xxp1;
-} cvmx_usbcx_hfir_t;
-
-
-/**
- * cvmx_usbc#_hfnum
- *
- * Host Frame Number/Frame Time Remaining Register (HFNUM)
- * 
- * This register indicates the current frame number.
- * It also indicates the time remaining (in terms of the number of PHY clocks)
- * in the current (micro)frame.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hfnum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t frrem                   : 16;      /**< Frame Time Remaining (FrRem)
-                                                         Indicates the amount of time remaining in the current
-                                                         microframe (HS) or frame (FS/LS), in terms of PHY clocks.
-                                                         This field decrements on each PHY clock. When it reaches
-                                                         zero, this field is reloaded with the value in the Frame Interval
-                                                         register and a new SOF is transmitted on the USB. */
-        uint32_t frnum                   : 16;      /**< Frame Number (FrNum)
-                                                         This field increments when a new SOF is transmitted on the
-                                                         USB, and is reset to 0 when it reaches 16'h3FFF. */
-#else
-        uint32_t frnum                   : 16;
-        uint32_t frrem                   : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_hfnum_s            cn30xx;
-    struct cvmx_usbcx_hfnum_s            cn31xx;
-    struct cvmx_usbcx_hfnum_s            cn50xx;
-    struct cvmx_usbcx_hfnum_s            cn52xx;
-    struct cvmx_usbcx_hfnum_s            cn52xxp1;
-    struct cvmx_usbcx_hfnum_s            cn56xx;
-    struct cvmx_usbcx_hfnum_s            cn56xxp1;
-} cvmx_usbcx_hfnum_t;
-
-
-/**
- * cvmx_usbc#_hprt
- *
- * Host Port Control and Status Register (HPRT)
- * 
- * This register is available in both Host and Device modes.
- * Currently, the OTG Host supports only one port.
- * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
- * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
- * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
- * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
- * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
- * to clear the interrupt.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hprt_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_19_31          : 13;
-        uint32_t prtspd                  : 2;       /**< Port Speed (PrtSpd)
-                                                         Indicates the speed of the device attached to this port.
-                                                         * 2'b00: High speed
-                                                         * 2'b01: Full speed
-                                                         * 2'b10: Low speed
-                                                         * 2'b11: Reserved */
-        uint32_t prttstctl               : 4;       /**< Port Test Control (PrtTstCtl)
-                                                         The application writes a nonzero value to this field to put
-                                                         the port into a Test mode, and the corresponding pattern is
-                                                         signaled on the port.
-                                                         * 4'b0000: Test mode disabled
-                                                         * 4'b0001: Test_J mode
-                                                         * 4'b0010: Test_K mode
-                                                         * 4'b0011: Test_SE0_NAK mode
-                                                         * 4'b0100: Test_Packet mode
-                                                         * 4'b0101: Test_Force_Enable
-                                                         * Others: Reserved
-                                                         PrtSpd must be zero (i.e. the interface must be in high-speed
-                                                         mode) to use the PrtTstCtl test modes. */
-        uint32_t prtpwr                  : 1;       /**< Port Power (PrtPwr)
-                                                         The application uses this field to control power to this port,
-                                                         and the core clears this bit on an overcurrent condition.
-                                                         * 1'b0: Power off
-                                                         * 1'b1: Power on */
-        uint32_t prtlnsts                : 2;       /**< Port Line Status (PrtLnSts)
-                                                         Indicates the current logic level USB data lines
-                                                         * Bit [10]: Logic level of D-
-                                                         * Bit [11]: Logic level of D+ */
-        uint32_t reserved_9_9            : 1;
-        uint32_t prtrst                  : 1;       /**< Port Reset (PrtRst)
-                                                         When the application sets this bit, a reset sequence is
-                                                         started on this port. The application must time the reset
-                                                         period and clear this bit after the reset sequence is
-                                                         complete.
-                                                         * 1'b0: Port not in reset
-                                                         * 1'b1: Port in reset
-                                                         The application must leave this bit set for at least a
-                                                         minimum duration mentioned below to start a reset on the
-                                                         port. The application can leave it set for another 10 ms in
-                                                         addition to the required minimum duration, before clearing
-                                                         the bit, even though there is no maximum limit set by the
-                                                         USB standard.
-                                                         * High speed: 50 ms
-                                                         * Full speed/Low speed: 10 ms */
-        uint32_t prtsusp                 : 1;       /**< Port Suspend (PrtSusp)
-                                                         The application sets this bit to put this port in Suspend
-                                                         mode. The core only stops sending SOFs when this is set.
-                                                         To stop the PHY clock, the application must set the Port
-                                                         Clock Stop bit, which will assert the suspend input pin of
-                                                         the PHY.
-                                                         The read value of this bit reflects the current suspend
-                                                         status of the port. This bit is cleared by the core after a
-                                                         remote wakeup signal is detected or the application sets
-                                                         the Port Reset bit or Port Resume bit in this register or the
-                                                         Resume/Remote Wakeup Detected Interrupt bit or
-                                                         Disconnect Detected Interrupt bit in the Core Interrupt
-                                                         register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
-                                                         respectively).
-                                                         * 1'b0: Port not in Suspend mode
-                                                         * 1'b1: Port in Suspend mode */
-        uint32_t prtres                  : 1;       /**< Port Resume (PrtRes)
-                                                         The application sets this bit to drive resume signaling on
-                                                         the port. The core continues to drive the resume signal
-                                                         until the application clears this bit.
-                                                         If the core detects a USB remote wakeup sequence, as
-                                                         indicated by the Port Resume/Remote Wakeup Detected
-                                                         Interrupt bit of the Core Interrupt register
-                                                         (GINTSTS.WkUpInt), the core starts driving resume
-                                                         signaling without application intervention and clears this bit
-                                                         when it detects a disconnect condition. The read value of
-                                                         this bit indicates whether the core is currently driving
-                                                         resume signaling.
-                                                         * 1'b0: No resume driven
-                                                         * 1'b1: Resume driven */
-        uint32_t prtovrcurrchng          : 1;       /**< Port Overcurrent Change (PrtOvrCurrChng)
-                                                         The core sets this bit when the status of the Port
-                                                         Overcurrent Active bit (bit 4) in this register changes. */
-        uint32_t prtovrcurract           : 1;       /**< Port Overcurrent Active (PrtOvrCurrAct)
-                                                         Indicates the overcurrent condition of the port.
-                                                         * 1'b0: No overcurrent condition
-                                                         * 1'b1: Overcurrent condition */
-        uint32_t prtenchng               : 1;       /**< Port Enable/Disable Change (PrtEnChng)
-                                                         The core sets this bit when the status of the Port Enable bit
-                                                         [2] of this register changes. */
-        uint32_t prtena                  : 1;       /**< Port Enable (PrtEna)
-                                                         A port is enabled only by the core after a reset sequence,
-                                                         and is disabled by an overcurrent condition, a disconnect
-                                                         condition, or by the application clearing this bit. The
-                                                         application cannot set this bit by a register write. It can only
-                                                         clear it to disable the port. This bit does not trigger any
-                                                         interrupt to the application.
-                                                         * 1'b0: Port disabled
-                                                         * 1'b1: Port enabled */
-        uint32_t prtconndet              : 1;       /**< Port Connect Detected (PrtConnDet)
-                                                         The core sets this bit when a device connection is detected
-                                                         to trigger an interrupt to the application using the Host Port
-                                                         Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
-                                                         The application must write a 1 to this bit to clear the
-                                                         interrupt. */
-        uint32_t prtconnsts              : 1;       /**< Port Connect Status (PrtConnSts)
-                                                         * 0: No device is attached to the port.
-                                                         * 1: A device is attached to the port. */
-#else
-        uint32_t prtconnsts              : 1;
-        uint32_t prtconndet              : 1;
-        uint32_t prtena                  : 1;
-        uint32_t prtenchng               : 1;
-        uint32_t prtovrcurract           : 1;
-        uint32_t prtovrcurrchng          : 1;
-        uint32_t prtres                  : 1;
-        uint32_t prtsusp                 : 1;
-        uint32_t prtrst                  : 1;
-        uint32_t reserved_9_9            : 1;
-        uint32_t prtlnsts                : 2;
-        uint32_t prtpwr                  : 1;
-        uint32_t prttstctl               : 4;
-        uint32_t prtspd                  : 2;
-        uint32_t reserved_19_31          : 13;
-#endif
-    } s;
-    struct cvmx_usbcx_hprt_s             cn30xx;
-    struct cvmx_usbcx_hprt_s             cn31xx;
-    struct cvmx_usbcx_hprt_s             cn50xx;
-    struct cvmx_usbcx_hprt_s             cn52xx;
-    struct cvmx_usbcx_hprt_s             cn52xxp1;
-    struct cvmx_usbcx_hprt_s             cn56xx;
-    struct cvmx_usbcx_hprt_s             cn56xxp1;
-} cvmx_usbcx_hprt_t;
-
-
-/**
- * cvmx_usbc#_hptxfsiz
- *
- * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
- * 
- * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hptxfsiz_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ptxfsize                : 16;      /**< Host Periodic TxFIFO Depth (PTxFSize)
-                                                         This value is in terms of 32-bit words.
-                                                         * Minimum value is 16
-                                                         * Maximum value is 32768 */
-        uint32_t ptxfstaddr              : 16;      /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */
-#else
-        uint32_t ptxfstaddr              : 16;
-        uint32_t ptxfsize                : 16;
-#endif
-    } s;
-    struct cvmx_usbcx_hptxfsiz_s         cn30xx;
-    struct cvmx_usbcx_hptxfsiz_s         cn31xx;
-    struct cvmx_usbcx_hptxfsiz_s         cn50xx;
-    struct cvmx_usbcx_hptxfsiz_s         cn52xx;
-    struct cvmx_usbcx_hptxfsiz_s         cn52xxp1;
-    struct cvmx_usbcx_hptxfsiz_s         cn56xx;
-    struct cvmx_usbcx_hptxfsiz_s         cn56xxp1;
-} cvmx_usbcx_hptxfsiz_t;
-
-
-/**
- * cvmx_usbc#_hptxsts
- *
- * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
- * 
- * This read-only register contains the free space information for the Periodic TxFIFO and
- * the Periodic Transmit Request Queue
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_hptxsts_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t ptxqtop                 : 8;       /**< Top of the Periodic Transmit Request Queue (PTxQTop)
-                                                         This indicates the entry in the Periodic Tx Request Queue that
-                                                         is currently being processes by the MAC.
-                                                         This register is used for debugging.
-                                                         * Bit [31]: Odd/Even (micro)frame
-                                                           - 1'b0: send in even (micro)frame
-                                                           - 1'b1: send in odd (micro)frame
-                                                         * Bits [30:27]: Channel/endpoint number
-                                                         * Bits [26:25]: Type
-                                                           - 2'b00: IN/OUT
-                                                           - 2'b01: Zero-length packet
-                                                           - 2'b10: CSPLIT
-                                                           - 2'b11: Disable channel command
-                                                         * Bit [24]: Terminate (last entry for the selected
-                                                           channel/endpoint) */
-        uint32_t ptxqspcavail            : 8;       /**< Periodic Transmit Request Queue Space Available
-                                                         (PTxQSpcAvail)
-                                                         Indicates the number of free locations available to be written in
-                                                         the Periodic Transmit Request Queue. This queue holds both
-                                                         IN and OUT requests.
-                                                         * 8'h0: Periodic Transmit Request Queue is full
-                                                         * 8'h1: 1 location available
-                                                         * 8'h2: 2 locations available
-                                                         * n: n locations available (0..8)
-                                                         * Others: Reserved */
-        uint32_t ptxfspcavail            : 16;      /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
-                                                         Indicates the number of free locations available to be written to
-                                                         in the Periodic TxFIFO.
-                                                         Values are in terms of 32-bit words
-                                                         * 16'h0: Periodic TxFIFO is full
-                                                         * 16'h1: 1 word available
-                                                         * 16'h2: 2 words available
-                                                         * 16'hn: n words available (where 0..32768)
-                                                         * 16'h8000: 32768 words available
-                                                         * Others: Reserved */
-#else
-        uint32_t ptxfspcavail            : 16;
-        uint32_t ptxqspcavail            : 8;
-        uint32_t ptxqtop                 : 8;
-#endif
-    } s;
-    struct cvmx_usbcx_hptxsts_s          cn30xx;
-    struct cvmx_usbcx_hptxsts_s          cn31xx;
-    struct cvmx_usbcx_hptxsts_s          cn50xx;
-    struct cvmx_usbcx_hptxsts_s          cn52xx;
-    struct cvmx_usbcx_hptxsts_s          cn52xxp1;
-    struct cvmx_usbcx_hptxsts_s          cn56xx;
-    struct cvmx_usbcx_hptxsts_s          cn56xxp1;
-} cvmx_usbcx_hptxsts_t;
-
-
-/**
- * cvmx_usbc#_nptxdfifo#
- *
- * NPTX Data Fifo (NPTXDFIFO)
- * 
- * A slave mode application uses this register to access the Tx FIFO for channel n.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_nptxdfifox_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t data                    : 32;      /**< Reserved */
-#else
-        uint32_t data                    : 32;
-#endif
-    } s;
-    struct cvmx_usbcx_nptxdfifox_s       cn30xx;
-    struct cvmx_usbcx_nptxdfifox_s       cn31xx;
-    struct cvmx_usbcx_nptxdfifox_s       cn50xx;
-    struct cvmx_usbcx_nptxdfifox_s       cn52xx;
-    struct cvmx_usbcx_nptxdfifox_s       cn52xxp1;
-    struct cvmx_usbcx_nptxdfifox_s       cn56xx;
-    struct cvmx_usbcx_nptxdfifox_s       cn56xxp1;
-} cvmx_usbcx_nptxdfifox_t;
-
-
-/**
- * cvmx_usbc#_pcgcctl
- *
- * Power and Clock Gating Control Register (PCGCCTL)
- * 
- * The application can use this register to control the core's power-down and clock gating features.
- */
-typedef union
-{
-    uint32_t u32;
-    struct cvmx_usbcx_pcgcctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint32_t reserved_5_31           : 27;
-        uint32_t physuspended            : 1;       /**< PHY Suspended. (PhySuspended)
-                                                         Indicates that the PHY has been suspended. After the
-                                                         application sets the Stop Pclk bit (bit 0), this bit is updated once
-                                                         the PHY is suspended.
-                                                         Since the UTMI+ PHY suspend is controlled through a port, the
-                                                         UTMI+ PHY is suspended immediately after Stop Pclk is set.
-                                                         However, the ULPI PHY takes a few clocks to suspend,
-                                                         because the suspend information is conveyed through the ULPI
-                                                         protocol to the ULPI PHY. */
-        uint32_t rstpdwnmodule           : 1;       /**< Reset Power-Down Modules (RstPdwnModule)
-                                                         This bit is valid only in Partial Power-Down mode. The
-                                                         application sets this bit when the power is turned off. The
-                                                         application clears this bit after the power is turned on and the
-                                                         PHY clock is up. */
-        uint32_t pwrclmp                 : 1;       /**< Power Clamp (PwrClmp)
-                                                         This bit is only valid in Partial Power-Down mode. The
-                                                         application sets this bit before the power is turned off to clamp
-                                                         the signals between the power-on modules and the power-off
-                                                         modules. The application clears the bit to disable the clamping
-                                                         before the power is turned on. */
-        uint32_t gatehclk                : 1;       /**< Gate Hclk (GateHclk)
-                                                         The application sets this bit to gate hclk to modules other than
-                                                         the AHB Slave and Master and wakeup logic when the USB is
-                                                         suspended or the session is not valid. The application clears
-                                                         this bit when the USB is resumed or a new session starts. */
-        uint32_t stoppclk                : 1;       /**< Stop Pclk (StopPclk)
-                                                         The application sets this bit to stop the PHY clock (phy_clk)
-                                                         when the USB is suspended, the session is not valid, or the
-                                                         device is disconnected. The application clears this bit when the
-                                                         USB is resumed or a new session starts. */
-#else
-        uint32_t stoppclk                : 1;
-        uint32_t gatehclk                : 1;
-        uint32_t pwrclmp                 : 1;
-        uint32_t rstpdwnmodule           : 1;
-        uint32_t physuspended            : 1;
-        uint32_t reserved_5_31           : 27;
-#endif
-    } s;
-    struct cvmx_usbcx_pcgcctl_s          cn30xx;
-    struct cvmx_usbcx_pcgcctl_s          cn31xx;
-    struct cvmx_usbcx_pcgcctl_s          cn50xx;
-    struct cvmx_usbcx_pcgcctl_s          cn52xx;
-    struct cvmx_usbcx_pcgcctl_s          cn52xxp1;
-    struct cvmx_usbcx_pcgcctl_s          cn56xx;
-    struct cvmx_usbcx_pcgcctl_s          cn56xxp1;
-} cvmx_usbcx_pcgcctl_t;
-
-
-/**
- * cvmx_usbn#_bist_status
- *
- * USBN_BIST_STATUS = USBN's Control and Status
- * 
- * Contain general control bits and status information for the USBN.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_bist_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_7_63           : 57;
-        uint64_t u2nc_bis                : 1;       /**< Bist status U2N CTL FIFO Memory. */
-        uint64_t u2nf_bis                : 1;       /**< Bist status U2N FIFO Memory. */
-        uint64_t e2hc_bis                : 1;       /**< Bist status E2H CTL FIFO Memory. */
-        uint64_t n2uf_bis                : 1;       /**< Bist status N2U  FIFO Memory. */
-        uint64_t usbc_bis                : 1;       /**< Bist status USBC FIFO Memory. */
-        uint64_t nif_bis                 : 1;       /**< Bist status for Inbound Memory. */
-        uint64_t nof_bis                 : 1;       /**< Bist status for Outbound Memory. */
-#else
-        uint64_t nof_bis                 : 1;
-        uint64_t nif_bis                 : 1;
-        uint64_t usbc_bis                : 1;
-        uint64_t n2uf_bis                : 1;
-        uint64_t e2hc_bis                : 1;
-        uint64_t u2nf_bis                : 1;
-        uint64_t u2nc_bis                : 1;
-        uint64_t reserved_7_63           : 57;
-#endif
-    } s;
-    struct cvmx_usbnx_bist_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_3_63           : 61;
-        uint64_t usbc_bis                : 1;       /**< Bist status USBC FIFO Memory. */
-        uint64_t nif_bis                 : 1;       /**< Bist status for Inbound Memory. */
-        uint64_t nof_bis                 : 1;       /**< Bist status for Outbound Memory. */
-#else
-        uint64_t nof_bis                 : 1;
-        uint64_t nif_bis                 : 1;
-        uint64_t usbc_bis                : 1;
-        uint64_t reserved_3_63           : 61;
-#endif
-    } cn30xx;
-    struct cvmx_usbnx_bist_status_cn30xx cn31xx;
-    struct cvmx_usbnx_bist_status_s      cn50xx;
-    struct cvmx_usbnx_bist_status_s      cn52xx;
-    struct cvmx_usbnx_bist_status_s      cn52xxp1;
-    struct cvmx_usbnx_bist_status_s      cn56xx;
-    struct cvmx_usbnx_bist_status_s      cn56xxp1;
-} cvmx_usbnx_bist_status_t;
-
-
-/**
- * cvmx_usbn#_clk_ctl
- *
- * USBN_CLK_CTL = USBN's Clock Control
- * 
- * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_clk_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t divide2                 : 2;       /**< The 'hclk' used by the USB subsystem is derived
-                                                         from the eclk.
-                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
-                                                         be zero because it is not implemented, so the maximum
-                                                         ratio of eclk/hclk is currently 16.
-                                                         The actual divide number for hclk is:
-                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
-        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
-                                                         generate the hclk in the USB Subsystem is held
-                                                         in reset. This bit must be set to '0' before
-                                                         changing the value os DIVIDE in this register.
-                                                         The reset to the HCLK_DIVIDERis also asserted
-                                                         when core reset is asserted. */
-        uint64_t p_x_on                  : 1;       /**< Force USB-PHY on during suspend.
-                                                         '1' USB-PHY XO block is powered-down during
-                                                             suspend.
-                                                         '0' USB-PHY XO block is powered-up during
-                                                             suspend.
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t reserved_14_15          : 2;
-        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
-                                                             remain powered in Suspend Mode.
-                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
-                                                             powered down in suspend mode.
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
-                                                         Selects the reference clock / crystal frequency.
-                                                         '11': Reserved
-                                                         '10': 48 MHz (reserved when a crystal is used)
-                                                         '01': 24 MHz (reserved when a crystal is used)
-                                                         '00': 12 MHz
-                                                         The value of this field must be set while POR is
-                                                         active.
-                                                         NOTE: if a crystal is used as a reference clock,
-                                                         this field must be set to 12 MHz. */
-        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
-        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
-                                                         in the USBC, for normal operation this must be '0'. */
-        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
-                                                         to '1' transition. */
-        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
-                                                         Resets all the PHYS registers and state machines. */
-        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
-                                                         '0' the hclk will not be generated. SEE DIVIDE
-                                                         field of this register. */
-        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the phy_clk functionality in the USB Subsystem is
-                                                         help in reset. This bit should not be set to '1'
-                                                         until the time it takes 6 clocks (hclk or phy_clk,
-                                                         whichever is slower) has passed. Under normal
-                                                         operation once this bit is set to '1' it should not
-                                                         be set to '0'. */
-        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the hclk functioanlity in the USB Subsystem is
-                                                         held in reset.This bit should not be set to '1'
-                                                         until 12ms after phy_clk is stable. Under normal
-                                                         operation, once this bit is set to '1' it should
-                                                         not be set to '0'. */
-        uint64_t divide                  : 3;       /**< The frequency of 'hclk' used by the USB subsystem
-                                                         is the eclk frequency divided by the value of
-                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
-                                                         DIVIDE2 of this register.
-                                                         The hclk frequency should be less than 125Mhz.
-                                                         After writing a value to this field the SW should
-                                                         read the field for the value written.
-                                                         The ENABLE field of this register should not be set
-                                                         until AFTER this field is set and then read. */
-#else
-        uint64_t divide                  : 3;
-        uint64_t hrst                    : 1;
-        uint64_t prst                    : 1;
-        uint64_t enable                  : 1;
-        uint64_t por                     : 1;
-        uint64_t s_bist                  : 1;
-        uint64_t sd_mode                 : 2;
-        uint64_t cdiv_byp                : 1;
-        uint64_t p_c_sel                 : 2;
-        uint64_t p_com_on                : 1;
-        uint64_t reserved_14_15          : 2;
-        uint64_t p_x_on                  : 1;
-        uint64_t hclk_rst                : 1;
-        uint64_t divide2                 : 2;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } s;
-    struct cvmx_usbnx_clk_ctl_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_18_63          : 46;
-        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
-                                                         generate the hclk in the USB Subsystem is held
-                                                         in reset. This bit must be set to '0' before
-                                                         changing the value os DIVIDE in this register.
-                                                         The reset to the HCLK_DIVIDERis also asserted
-                                                         when core reset is asserted. */
-        uint64_t p_x_on                  : 1;       /**< Force USB-PHY on during suspend.
-                                                         '1' USB-PHY XO block is powered-down during
-                                                             suspend.
-                                                         '0' USB-PHY XO block is powered-up during
-                                                             suspend.
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t p_rclk                  : 1;       /**< Phy refrence clock enable.
-                                                         '1' The PHY PLL uses the XO block output as a
-                                                         reference.
-                                                         '0' Reserved. */
-        uint64_t p_xenbn                 : 1;       /**< Phy external clock enable.
-                                                         '1' The XO block uses the clock from a crystal.
-                                                         '0' The XO block uses an external clock supplied
-                                                             on the XO pin. USB_XI should be tied to
-                                                             ground for this usage. */
-        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
-                                                             remain powered in Suspend Mode.
-                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
-                                                             powered down in suspend mode.
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
-                                                         Selects the reference clock / crystal frequency.
-                                                         '11': Reserved
-                                                         '10': 48 MHz
-                                                         '01': 24 MHz
-                                                         '00': 12 MHz
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
-        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
-                                                         in the USBC, for normal operation this must be '0'. */
-        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
-                                                         to '1' transition. */
-        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
-                                                         Resets all the PHYS registers and state machines. */
-        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
-                                                         '0' the hclk will not be generated. */
-        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the phy_clk functionality in the USB Subsystem is
-                                                         help in reset. This bit should not be set to '1'
-                                                         until the time it takes 6 clocks (hclk or phy_clk,
-                                                         whichever is slower) has passed. Under normal
-                                                         operation once this bit is set to '1' it should not
-                                                         be set to '0'. */
-        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the hclk functioanlity in the USB Subsystem is
-                                                         held in reset.This bit should not be set to '1'
-                                                         until 12ms after phy_clk is stable. Under normal
-                                                         operation, once this bit is set to '1' it should
-                                                         not be set to '0'. */
-        uint64_t divide                  : 3;       /**< The 'hclk' used by the USB subsystem is derived
-                                                         from the eclk. The eclk will be divided by the
-                                                         value of this field +1 to determine the hclk
-                                                         frequency. (Also see HRST of this register).
-                                                         The hclk frequency must be less than 125 MHz. */
-#else
-        uint64_t divide                  : 3;
-        uint64_t hrst                    : 1;
-        uint64_t prst                    : 1;
-        uint64_t enable                  : 1;
-        uint64_t por                     : 1;
-        uint64_t s_bist                  : 1;
-        uint64_t sd_mode                 : 2;
-        uint64_t cdiv_byp                : 1;
-        uint64_t p_c_sel                 : 2;
-        uint64_t p_com_on                : 1;
-        uint64_t p_xenbn                 : 1;
-        uint64_t p_rclk                  : 1;
-        uint64_t p_x_on                  : 1;
-        uint64_t hclk_rst                : 1;
-        uint64_t reserved_18_63          : 46;
-#endif
-    } cn30xx;
-    struct cvmx_usbnx_clk_ctl_cn30xx     cn31xx;
-    struct cvmx_usbnx_clk_ctl_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_20_63          : 44;
-        uint64_t divide2                 : 2;       /**< The 'hclk' used by the USB subsystem is derived
-                                                         from the eclk.
-                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
-                                                         be zero because it is not implemented, so the maximum
-                                                         ratio of eclk/hclk is currently 16.
-                                                         The actual divide number for hclk is:
-                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
-        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
-                                                         generate the hclk in the USB Subsystem is held
-                                                         in reset. This bit must be set to '0' before
-                                                         changing the value os DIVIDE in this register.
-                                                         The reset to the HCLK_DIVIDERis also asserted
-                                                         when core reset is asserted. */
-        uint64_t reserved_16_16          : 1;
-        uint64_t p_rtype                 : 2;       /**< PHY reference clock type
-                                                         '0' The USB-PHY uses a 12MHz crystal as a clock
-                                                             source at the USB_XO and USB_XI pins
-                                                         '1' Reserved
-                                                         '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
-                                                             at the USB_XO pin. USB_XI should be tied to
-                                                             ground in this case.
-                                                         '3' Reserved
-                                                         (bit 14 was P_XENBN on 3xxx)
-                                                         (bit 15 was P_RCLK on 3xxx) */
-        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
-                                                             remain powered in Suspend Mode.
-                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
-                                                             powered down in suspend mode.
-                                                         The value of this field must be set while POR is
-                                                         active. */
-        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
-                                                         Selects the reference clock / crystal frequency.
-                                                         '11': Reserved
-                                                         '10': 48 MHz (reserved when a crystal is used)
-                                                         '01': 24 MHz (reserved when a crystal is used)
-                                                         '00': 12 MHz
-                                                         The value of this field must be set while POR is
-                                                         active.
-                                                         NOTE: if a crystal is used as a reference clock,
-                                                         this field must be set to 12 MHz. */
-        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
-        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
-                                                         in the USBC, for normal operation this must be '0'. */
-        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
-                                                         to '1' transition. */
-        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
-                                                         Resets all the PHYS registers and state machines. */
-        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
-                                                         '0' the hclk will not be generated. SEE DIVIDE
-                                                         field of this register. */
-        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the phy_clk functionality in the USB Subsystem is
-                                                         help in reset. This bit should not be set to '1'
-                                                         until the time it takes 6 clocks (hclk or phy_clk,
-                                                         whichever is slower) has passed. Under normal
-                                                         operation once this bit is set to '1' it should not
-                                                         be set to '0'. */
-        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
-                                                         the hclk functioanlity in the USB Subsystem is
-                                                         held in reset.This bit should not be set to '1'
-                                                         until 12ms after phy_clk is stable. Under normal
-                                                         operation, once this bit is set to '1' it should
-                                                         not be set to '0'. */
-        uint64_t divide                  : 3;       /**< The frequency of 'hclk' used by the USB subsystem
-                                                         is the eclk frequency divided by the value of
-                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
-                                                         DIVIDE2 of this register.
-                                                         The hclk frequency should be less than 125Mhz.
-                                                         After writing a value to this field the SW should
-                                                         read the field for the value written.
-                                                         The ENABLE field of this register should not be set
-                                                         until AFTER this field is set and then read. */
-#else
-        uint64_t divide                  : 3;
-        uint64_t hrst                    : 1;
-        uint64_t prst                    : 1;
-        uint64_t enable                  : 1;
-        uint64_t por                     : 1;
-        uint64_t s_bist                  : 1;
-        uint64_t sd_mode                 : 2;
-        uint64_t cdiv_byp                : 1;
-        uint64_t p_c_sel                 : 2;
-        uint64_t p_com_on                : 1;
-        uint64_t p_rtype                 : 2;
-        uint64_t reserved_16_16          : 1;
-        uint64_t hclk_rst                : 1;
-        uint64_t divide2                 : 2;
-        uint64_t reserved_20_63          : 44;
-#endif
-    } cn50xx;
-    struct cvmx_usbnx_clk_ctl_cn50xx     cn52xx;
-    struct cvmx_usbnx_clk_ctl_cn50xx     cn52xxp1;
-    struct cvmx_usbnx_clk_ctl_cn50xx     cn56xx;
-    struct cvmx_usbnx_clk_ctl_cn50xx     cn56xxp1;
-} cvmx_usbnx_clk_ctl_t;
-
-
-/**
- * cvmx_usbn#_ctl_status
- *
- * USBN_CTL_STATUS = USBN's Control And Status Register
- * 
- * Contains general control and status information for the USBN block.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_6_63           : 58;
-        uint64_t dma_0pag                : 1;       /**< When '1' sets the DMA engine will set the zero-Page
-                                                         bit in the L2C store operation to the IOB. */
-        uint64_t dma_stt                 : 1;       /**< When '1' sets the DMA engine to use STT operations. */
-        uint64_t dma_test                : 1;       /**< When '1' sets the DMA engine into Test-Mode.
-                                                         For normal operation this bit should be '0'. */
-        uint64_t inv_a2                  : 1;       /**< When '1' causes the address[2] driven on the AHB
-                                                         for USB-CORE FIFO access to be inverted. Also data
-                                                         writen to and read from the AHB will have it byte
-                                                         order swapped. If the orginal order was A-B-C-D the
-                                                         new byte order will be D-C-B-A. */
-        uint64_t l2c_emod                : 2;       /**< Endian format for data from/to the L2C.
-                                                         IN:   A-B-C-D-E-F-G-H
-                                                         OUT0: A-B-C-D-E-F-G-H
-                                                         OUT1: H-G-F-E-D-C-B-A
-                                                         OUT2: D-C-B-A-H-G-F-E
-                                                         OUT3: E-F-G-H-A-B-C-D */
-#else
-        uint64_t l2c_emod                : 2;
-        uint64_t inv_a2                  : 1;
-        uint64_t dma_test                : 1;
-        uint64_t dma_stt                 : 1;
-        uint64_t dma_0pag                : 1;
-        uint64_t reserved_6_63           : 58;
-#endif
-    } s;
-    struct cvmx_usbnx_ctl_status_s       cn30xx;
-    struct cvmx_usbnx_ctl_status_s       cn31xx;
-    struct cvmx_usbnx_ctl_status_s       cn50xx;
-    struct cvmx_usbnx_ctl_status_s       cn52xx;
-    struct cvmx_usbnx_ctl_status_s       cn52xxp1;
-    struct cvmx_usbnx_ctl_status_s       cn56xx;
-    struct cvmx_usbnx_ctl_status_s       cn56xxp1;
-} cvmx_usbnx_ctl_status_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn0
- *
- * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel0.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn0_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn0_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn1
- *
- * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel1.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn1_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn1_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn2
- *
- * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel2.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn2_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn2_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn3
- *
- * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel3.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn3_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn3_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn4
- *
- * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel4.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn4_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn4_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn5
- *
- * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel5.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn5_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn5_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn6
- *
- * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel6.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn6_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn6_t;
-
-
-/**
- * cvmx_usbn#_dma0_inb_chn7
- *
- * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
- * 
- * Contains the starting address for use when USB0 writes to L2C via Channel7.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_inb_chn7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn30xx;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn31xx;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn50xx;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn52xx;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn52xxp1;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn56xx;
-    struct cvmx_usbnx_dma0_inb_chn7_s    cn56xxp1;
-} cvmx_usbnx_dma0_inb_chn7_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn0
- *
- * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel0.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn0_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn0_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn1
- *
- * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel1.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn1_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn1_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn1_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn2
- *
- * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel2.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn2_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn2_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn2_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn3
- *
- * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel3.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn3_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn3_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn3_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn4
- *
- * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel4.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn4_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn4_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn4_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn5
- *
- * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel5.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn5_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn5_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn5_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn6
- *
- * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel6.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn6_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn6_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn6_t;
-
-
-/**
- * cvmx_usbn#_dma0_outb_chn7
- *
- * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
- * 
- * Contains the starting address for use when USB0 reads from L2C via Channel7.
- * Writing of this register sets the base address.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma0_outb_chn7_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_36_63          : 28;
-        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
-#else
-        uint64_t addr                    : 36;
-        uint64_t reserved_36_63          : 28;
-#endif
-    } s;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn30xx;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn31xx;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn50xx;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn52xx;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn52xxp1;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn56xx;
-    struct cvmx_usbnx_dma0_outb_chn7_s   cn56xxp1;
-} cvmx_usbnx_dma0_outb_chn7_t;
-
-
-/**
- * cvmx_usbn#_dma_test
- *
- * USBN_DMA_TEST = USBN's DMA TestRegister
- * 
- * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_dma_test_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_40_63          : 24;
-        uint64_t done                    : 1;       /**< This field is set when a DMA completes. Writing a
-                                                         '1' to this field clears this bit. */
-        uint64_t req                     : 1;       /**< DMA Request. Writing a 1 to this register
-                                                         will cause a DMA request as specified in the other
-                                                         fields of this register to take place. This field
-                                                         will always read as '0'. */
-        uint64_t f_addr                  : 18;      /**< The address to read from in the Data-Fifo. */
-        uint64_t count                   : 11;      /**< DMA Request Count. */
-        uint64_t channel                 : 5;       /**< DMA Channel/Enpoint. */
-        uint64_t burst                   : 4;       /**< DMA Burst Size. */
-#else
-        uint64_t burst                   : 4;
-        uint64_t channel                 : 5;
-        uint64_t count                   : 11;
-        uint64_t f_addr                  : 18;
-        uint64_t req                     : 1;
-        uint64_t done                    : 1;
-        uint64_t reserved_40_63          : 24;
-#endif
-    } s;
-    struct cvmx_usbnx_dma_test_s         cn30xx;
-    struct cvmx_usbnx_dma_test_s         cn31xx;
-    struct cvmx_usbnx_dma_test_s         cn50xx;
-    struct cvmx_usbnx_dma_test_s         cn52xx;
-    struct cvmx_usbnx_dma_test_s         cn52xxp1;
-    struct cvmx_usbnx_dma_test_s         cn56xx;
-    struct cvmx_usbnx_dma_test_s         cn56xxp1;
-} cvmx_usbnx_dma_test_t;
-
-
-/**
- * cvmx_usbn#_int_enb
- *
- * USBN_INT_ENB = USBN's Interrupt Enable
- * 
- * The USBN's interrupt enable register.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_int_enb_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t nd4o_dpf                : 1;       /**< When set (1) and bit 37 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_dpe                : 1;       /**< When set (1) and bit 36 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_rpf                : 1;       /**< When set (1) and bit 35 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_rpe                : 1;       /**< When set (1) and bit 34 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t ltl_f_pf                : 1;       /**< When set (1) and bit 33 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t ltl_f_pe                : 1;       /**< When set (1) and bit 32 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t u2n_c_pe                : 1;       /**< When set (1) and bit 31 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t u2n_c_pf                : 1;       /**< When set (1) and bit 30 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t u2n_d_pf                : 1;       /**< When set (1) and bit 29 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t u2n_d_pe                : 1;       /**< When set (1) and bit 28 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t n2u_pe                  : 1;       /**< When set (1) and bit 27 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t n2u_pf                  : 1;       /**< When set (1) and bit 26 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t uod_pf                  : 1;       /**< When set (1) and bit 25 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t uod_pe                  : 1;       /**< When set (1) and bit 24 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q3_e                 : 1;       /**< When set (1) and bit 23 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q3_f                 : 1;       /**< When set (1) and bit 22 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q2_e                 : 1;       /**< When set (1) and bit 21 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q2_f                 : 1;       /**< When set (1) and bit 20 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rg_fi_f                 : 1;       /**< When set (1) and bit 19 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rg_fi_e                 : 1;       /**< When set (1) and bit 18 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2_fi_f                 : 1;       /**< When set (1) and bit 17 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2_fi_e                 : 1;       /**< When set (1) and bit 16 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2c_a_f                 : 1;       /**< When set (1) and bit 15 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2c_s_e                 : 1;       /**< When set (1) and bit 14 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t dcred_f                 : 1;       /**< When set (1) and bit 13 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t dcred_e                 : 1;       /**< When set (1) and bit 12 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lt_pu_f                 : 1;       /**< When set (1) and bit 11 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lt_po_e                 : 1;       /**< When set (1) and bit 10 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nt_pu_f                 : 1;       /**< When set (1) and bit 9 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nt_po_e                 : 1;       /**< When set (1) and bit 8 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pt_pu_f                 : 1;       /**< When set (1) and bit 7 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pt_po_e                 : 1;       /**< When set (1) and bit 6 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lr_pu_f                 : 1;       /**< When set (1) and bit 5 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lr_po_e                 : 1;       /**< When set (1) and bit 4 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nr_pu_f                 : 1;       /**< When set (1) and bit 3 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nr_po_e                 : 1;       /**< When set (1) and bit 2 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pr_pu_f                 : 1;       /**< When set (1) and bit 1 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pr_po_e                 : 1;       /**< When set (1) and bit 0 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-#else
-        uint64_t pr_po_e                 : 1;
-        uint64_t pr_pu_f                 : 1;
-        uint64_t nr_po_e                 : 1;
-        uint64_t nr_pu_f                 : 1;
-        uint64_t lr_po_e                 : 1;
-        uint64_t lr_pu_f                 : 1;
-        uint64_t pt_po_e                 : 1;
-        uint64_t pt_pu_f                 : 1;
-        uint64_t nt_po_e                 : 1;
-        uint64_t nt_pu_f                 : 1;
-        uint64_t lt_po_e                 : 1;
-        uint64_t lt_pu_f                 : 1;
-        uint64_t dcred_e                 : 1;
-        uint64_t dcred_f                 : 1;
-        uint64_t l2c_s_e                 : 1;
-        uint64_t l2c_a_f                 : 1;
-        uint64_t l2_fi_e                 : 1;
-        uint64_t l2_fi_f                 : 1;
-        uint64_t rg_fi_e                 : 1;
-        uint64_t rg_fi_f                 : 1;
-        uint64_t rq_q2_f                 : 1;
-        uint64_t rq_q2_e                 : 1;
-        uint64_t rq_q3_f                 : 1;
-        uint64_t rq_q3_e                 : 1;
-        uint64_t uod_pe                  : 1;
-        uint64_t uod_pf                  : 1;
-        uint64_t n2u_pf                  : 1;
-        uint64_t n2u_pe                  : 1;
-        uint64_t u2n_d_pe                : 1;
-        uint64_t u2n_d_pf                : 1;
-        uint64_t u2n_c_pf                : 1;
-        uint64_t u2n_c_pe                : 1;
-        uint64_t ltl_f_pe                : 1;
-        uint64_t ltl_f_pf                : 1;
-        uint64_t nd4o_rpe                : 1;
-        uint64_t nd4o_rpf                : 1;
-        uint64_t nd4o_dpe                : 1;
-        uint64_t nd4o_dpf                : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_usbnx_int_enb_s          cn30xx;
-    struct cvmx_usbnx_int_enb_s          cn31xx;
-    struct cvmx_usbnx_int_enb_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t nd4o_dpf                : 1;       /**< When set (1) and bit 37 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_dpe                : 1;       /**< When set (1) and bit 36 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_rpf                : 1;       /**< When set (1) and bit 35 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nd4o_rpe                : 1;       /**< When set (1) and bit 34 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t ltl_f_pf                : 1;       /**< When set (1) and bit 33 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t ltl_f_pe                : 1;       /**< When set (1) and bit 32 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t reserved_26_31          : 6;
-        uint64_t uod_pf                  : 1;       /**< When set (1) and bit 25 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t uod_pe                  : 1;       /**< When set (1) and bit 24 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q3_e                 : 1;       /**< When set (1) and bit 23 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q3_f                 : 1;       /**< When set (1) and bit 22 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q2_e                 : 1;       /**< When set (1) and bit 21 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rq_q2_f                 : 1;       /**< When set (1) and bit 20 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rg_fi_f                 : 1;       /**< When set (1) and bit 19 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t rg_fi_e                 : 1;       /**< When set (1) and bit 18 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2_fi_f                 : 1;       /**< When set (1) and bit 17 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2_fi_e                 : 1;       /**< When set (1) and bit 16 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2c_a_f                 : 1;       /**< When set (1) and bit 15 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t l2c_s_e                 : 1;       /**< When set (1) and bit 14 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t dcred_f                 : 1;       /**< When set (1) and bit 13 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t dcred_e                 : 1;       /**< When set (1) and bit 12 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lt_pu_f                 : 1;       /**< When set (1) and bit 11 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lt_po_e                 : 1;       /**< When set (1) and bit 10 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nt_pu_f                 : 1;       /**< When set (1) and bit 9 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nt_po_e                 : 1;       /**< When set (1) and bit 8 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pt_pu_f                 : 1;       /**< When set (1) and bit 7 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pt_po_e                 : 1;       /**< When set (1) and bit 6 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lr_pu_f                 : 1;       /**< When set (1) and bit 5 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t lr_po_e                 : 1;       /**< When set (1) and bit 4 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nr_pu_f                 : 1;       /**< When set (1) and bit 3 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t nr_po_e                 : 1;       /**< When set (1) and bit 2 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pr_pu_f                 : 1;       /**< When set (1) and bit 1 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-        uint64_t pr_po_e                 : 1;       /**< When set (1) and bit 0 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-#else
-        uint64_t pr_po_e                 : 1;
-        uint64_t pr_pu_f                 : 1;
-        uint64_t nr_po_e                 : 1;
-        uint64_t nr_pu_f                 : 1;
-        uint64_t lr_po_e                 : 1;
-        uint64_t lr_pu_f                 : 1;
-        uint64_t pt_po_e                 : 1;
-        uint64_t pt_pu_f                 : 1;
-        uint64_t nt_po_e                 : 1;
-        uint64_t nt_pu_f                 : 1;
-        uint64_t lt_po_e                 : 1;
-        uint64_t lt_pu_f                 : 1;
-        uint64_t dcred_e                 : 1;
-        uint64_t dcred_f                 : 1;
-        uint64_t l2c_s_e                 : 1;
-        uint64_t l2c_a_f                 : 1;
-        uint64_t l2_fi_e                 : 1;
-        uint64_t l2_fi_f                 : 1;
-        uint64_t rg_fi_e                 : 1;
-        uint64_t rg_fi_f                 : 1;
-        uint64_t rq_q2_f                 : 1;
-        uint64_t rq_q2_e                 : 1;
-        uint64_t rq_q3_f                 : 1;
-        uint64_t rq_q3_e                 : 1;
-        uint64_t uod_pe                  : 1;
-        uint64_t uod_pf                  : 1;
-        uint64_t reserved_26_31          : 6;
-        uint64_t ltl_f_pe                : 1;
-        uint64_t ltl_f_pf                : 1;
-        uint64_t nd4o_rpe                : 1;
-        uint64_t nd4o_rpf                : 1;
-        uint64_t nd4o_dpe                : 1;
-        uint64_t nd4o_dpf                : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } cn50xx;
-    struct cvmx_usbnx_int_enb_cn50xx     cn52xx;
-    struct cvmx_usbnx_int_enb_cn50xx     cn52xxp1;
-    struct cvmx_usbnx_int_enb_cn50xx     cn56xx;
-    struct cvmx_usbnx_int_enb_cn50xx     cn56xxp1;
-} cvmx_usbnx_int_enb_t;
-
-
-/**
- * cvmx_usbn#_int_sum
- *
- * USBN_INT_SUM = USBN's Interrupt Summary Register
- * 
- * Contains the diffrent interrupt summary bits of the USBN.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_int_sum_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t nd4o_dpf                : 1;       /**< NCB DMA Out Data Fifo Push Full. */
-        uint64_t nd4o_dpe                : 1;       /**< NCB DMA Out Data Fifo Pop Empty. */
-        uint64_t nd4o_rpf                : 1;       /**< NCB DMA Out Request Fifo Push Full. */
-        uint64_t nd4o_rpe                : 1;       /**< NCB DMA Out Request Fifo Pop Empty. */
-        uint64_t ltl_f_pf                : 1;       /**< L2C Transfer Length Fifo Push Full. */
-        uint64_t ltl_f_pe                : 1;       /**< L2C Transfer Length Fifo Pop Empty. */
-        uint64_t u2n_c_pe                : 1;       /**< U2N Control Fifo Pop Empty. */
-        uint64_t u2n_c_pf                : 1;       /**< U2N Control Fifo Push Full. */
-        uint64_t u2n_d_pf                : 1;       /**< U2N Data Fifo Push Full. */
-        uint64_t u2n_d_pe                : 1;       /**< U2N Data Fifo Pop Empty. */
-        uint64_t n2u_pe                  : 1;       /**< N2U Fifo Pop Empty. */
-        uint64_t n2u_pf                  : 1;       /**< N2U Fifo Push Full. */
-        uint64_t uod_pf                  : 1;       /**< UOD Fifo Push Full. */
-        uint64_t uod_pe                  : 1;       /**< UOD Fifo Pop Empty. */
-        uint64_t rq_q3_e                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
-        uint64_t rq_q3_f                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
-        uint64_t rq_q2_e                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
-        uint64_t rq_q2_f                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
-        uint64_t rg_fi_f                 : 1;       /**< Register Request Fifo Pushed When Full. */
-        uint64_t rg_fi_e                 : 1;       /**< Register Request Fifo Pushed When Full. */
-        uint64_t lt_fi_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t lt_fi_e                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t l2c_a_f                 : 1;       /**< L2C Credit Count Added When Full. */
-        uint64_t l2c_s_e                 : 1;       /**< L2C Credit Count Subtracted When Empty. */
-        uint64_t dcred_f                 : 1;       /**< Data CreditFifo Pushed When Full. */
-        uint64_t dcred_e                 : 1;       /**< Data Credit Fifo Pushed When Full. */
-        uint64_t lt_pu_f                 : 1;       /**< L2C Trasaction Fifo Pushed When Full. */
-        uint64_t lt_po_e                 : 1;       /**< L2C Trasaction Fifo Popped When Full. */
-        uint64_t nt_pu_f                 : 1;       /**< NPI Trasaction Fifo Pushed When Full. */
-        uint64_t nt_po_e                 : 1;       /**< NPI Trasaction Fifo Popped When Full. */
-        uint64_t pt_pu_f                 : 1;       /**< PP  Trasaction Fifo Pushed When Full. */
-        uint64_t pt_po_e                 : 1;       /**< PP  Trasaction Fifo Popped When Full. */
-        uint64_t lr_pu_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t lr_po_e                 : 1;       /**< L2C Request Fifo Popped When Empty. */
-        uint64_t nr_pu_f                 : 1;       /**< NPI Request Fifo Pushed When Full. */
-        uint64_t nr_po_e                 : 1;       /**< NPI Request Fifo Popped When Empty. */
-        uint64_t pr_pu_f                 : 1;       /**< PP  Request Fifo Pushed When Full. */
-        uint64_t pr_po_e                 : 1;       /**< PP  Request Fifo Popped When Empty. */
-#else
-        uint64_t pr_po_e                 : 1;
-        uint64_t pr_pu_f                 : 1;
-        uint64_t nr_po_e                 : 1;
-        uint64_t nr_pu_f                 : 1;
-        uint64_t lr_po_e                 : 1;
-        uint64_t lr_pu_f                 : 1;
-        uint64_t pt_po_e                 : 1;
-        uint64_t pt_pu_f                 : 1;
-        uint64_t nt_po_e                 : 1;
-        uint64_t nt_pu_f                 : 1;
-        uint64_t lt_po_e                 : 1;
-        uint64_t lt_pu_f                 : 1;
-        uint64_t dcred_e                 : 1;
-        uint64_t dcred_f                 : 1;
-        uint64_t l2c_s_e                 : 1;
-        uint64_t l2c_a_f                 : 1;
-        uint64_t lt_fi_e                 : 1;
-        uint64_t lt_fi_f                 : 1;
-        uint64_t rg_fi_e                 : 1;
-        uint64_t rg_fi_f                 : 1;
-        uint64_t rq_q2_f                 : 1;
-        uint64_t rq_q2_e                 : 1;
-        uint64_t rq_q3_f                 : 1;
-        uint64_t rq_q3_e                 : 1;
-        uint64_t uod_pe                  : 1;
-        uint64_t uod_pf                  : 1;
-        uint64_t n2u_pf                  : 1;
-        uint64_t n2u_pe                  : 1;
-        uint64_t u2n_d_pe                : 1;
-        uint64_t u2n_d_pf                : 1;
-        uint64_t u2n_c_pf                : 1;
-        uint64_t u2n_c_pe                : 1;
-        uint64_t ltl_f_pe                : 1;
-        uint64_t ltl_f_pf                : 1;
-        uint64_t nd4o_rpe                : 1;
-        uint64_t nd4o_rpf                : 1;
-        uint64_t nd4o_dpe                : 1;
-        uint64_t nd4o_dpf                : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } s;
-    struct cvmx_usbnx_int_sum_s          cn30xx;
-    struct cvmx_usbnx_int_sum_s          cn31xx;
-    struct cvmx_usbnx_int_sum_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t nd4o_dpf                : 1;       /**< NCB DMA Out Data Fifo Push Full. */
-        uint64_t nd4o_dpe                : 1;       /**< NCB DMA Out Data Fifo Pop Empty. */
-        uint64_t nd4o_rpf                : 1;       /**< NCB DMA Out Request Fifo Push Full. */
-        uint64_t nd4o_rpe                : 1;       /**< NCB DMA Out Request Fifo Pop Empty. */
-        uint64_t ltl_f_pf                : 1;       /**< L2C Transfer Length Fifo Push Full. */
-        uint64_t ltl_f_pe                : 1;       /**< L2C Transfer Length Fifo Pop Empty. */
-        uint64_t reserved_26_31          : 6;
-        uint64_t uod_pf                  : 1;       /**< UOD Fifo Push Full. */
-        uint64_t uod_pe                  : 1;       /**< UOD Fifo Pop Empty. */
-        uint64_t rq_q3_e                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
-        uint64_t rq_q3_f                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
-        uint64_t rq_q2_e                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
-        uint64_t rq_q2_f                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
-        uint64_t rg_fi_f                 : 1;       /**< Register Request Fifo Pushed When Full. */
-        uint64_t rg_fi_e                 : 1;       /**< Register Request Fifo Pushed When Full. */
-        uint64_t lt_fi_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t lt_fi_e                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t l2c_a_f                 : 1;       /**< L2C Credit Count Added When Full. */
-        uint64_t l2c_s_e                 : 1;       /**< L2C Credit Count Subtracted When Empty. */
-        uint64_t dcred_f                 : 1;       /**< Data CreditFifo Pushed When Full. */
-        uint64_t dcred_e                 : 1;       /**< Data Credit Fifo Pushed When Full. */
-        uint64_t lt_pu_f                 : 1;       /**< L2C Trasaction Fifo Pushed When Full. */
-        uint64_t lt_po_e                 : 1;       /**< L2C Trasaction Fifo Popped When Full. */
-        uint64_t nt_pu_f                 : 1;       /**< NPI Trasaction Fifo Pushed When Full. */
-        uint64_t nt_po_e                 : 1;       /**< NPI Trasaction Fifo Popped When Full. */
-        uint64_t pt_pu_f                 : 1;       /**< PP  Trasaction Fifo Pushed When Full. */
-        uint64_t pt_po_e                 : 1;       /**< PP  Trasaction Fifo Popped When Full. */
-        uint64_t lr_pu_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
-        uint64_t lr_po_e                 : 1;       /**< L2C Request Fifo Popped When Empty. */
-        uint64_t nr_pu_f                 : 1;       /**< NPI Request Fifo Pushed When Full. */
-        uint64_t nr_po_e                 : 1;       /**< NPI Request Fifo Popped When Empty. */
-        uint64_t pr_pu_f                 : 1;       /**< PP  Request Fifo Pushed When Full. */
-        uint64_t pr_po_e                 : 1;       /**< PP  Request Fifo Popped When Empty. */
-#else
-        uint64_t pr_po_e                 : 1;
-        uint64_t pr_pu_f                 : 1;
-        uint64_t nr_po_e                 : 1;
-        uint64_t nr_pu_f                 : 1;
-        uint64_t lr_po_e                 : 1;
-        uint64_t lr_pu_f                 : 1;
-        uint64_t pt_po_e                 : 1;
-        uint64_t pt_pu_f                 : 1;
-        uint64_t nt_po_e                 : 1;
-        uint64_t nt_pu_f                 : 1;
-        uint64_t lt_po_e                 : 1;
-        uint64_t lt_pu_f                 : 1;
-        uint64_t dcred_e                 : 1;
-        uint64_t dcred_f                 : 1;
-        uint64_t l2c_s_e                 : 1;
-        uint64_t l2c_a_f                 : 1;
-        uint64_t lt_fi_e                 : 1;
-        uint64_t lt_fi_f                 : 1;
-        uint64_t rg_fi_e                 : 1;
-        uint64_t rg_fi_f                 : 1;
-        uint64_t rq_q2_f                 : 1;
-        uint64_t rq_q2_e                 : 1;
-        uint64_t rq_q3_f                 : 1;
-        uint64_t rq_q3_e                 : 1;
-        uint64_t uod_pe                  : 1;
-        uint64_t uod_pf                  : 1;
-        uint64_t reserved_26_31          : 6;
-        uint64_t ltl_f_pe                : 1;
-        uint64_t ltl_f_pf                : 1;
-        uint64_t nd4o_rpe                : 1;
-        uint64_t nd4o_rpf                : 1;
-        uint64_t nd4o_dpe                : 1;
-        uint64_t nd4o_dpf                : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } cn50xx;
-    struct cvmx_usbnx_int_sum_cn50xx     cn52xx;
-    struct cvmx_usbnx_int_sum_cn50xx     cn52xxp1;
-    struct cvmx_usbnx_int_sum_cn50xx     cn56xx;
-    struct cvmx_usbnx_int_sum_cn50xx     cn56xxp1;
-} cvmx_usbnx_int_sum_t;
-
-
-/**
- * cvmx_usbn#_usbp_ctl_status
- *
- * USBN_USBP_CTL_STATUS = USBP Control And Status Register
- * 
- * Contains general control and status information for the USBN block.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_usbnx_usbp_ctl_status_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
-        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
-        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
-        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
-        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
-        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
-        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
-        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
-        uint64_t portreset               : 1;       /**< Per_Port Reset */
-        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
-        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
-        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
-        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
-        uint64_t bist_done               : 1;       /**< PHY Bist Done.
-                                                         Asserted at the end of the PHY BIST sequence. */
-        uint64_t bist_err                : 1;       /**< PHY Bist Error.
-                                                         Indicates an internal error was detected during
-                                                         the BIST sequence. */
-        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
-                                                         Presents either internaly generated signals or
-                                                         test register contents, based upon the value of
-                                                         test_data_out_sel. */
-        uint64_t siddq                   : 1;       /**< Drives the USBP (USB-PHY) SIDDQ input.
-                                                         Normally should be set to zero.
-                                                         When customers have no intent to use USB PHY
-                                                         interface, they should:
-                                                           - still provide 3.3V to USB_VDD33, and
-                                                           - tie USB_REXT to 3.3V supply, and
-                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
-        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
-        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
-                                                         with byte-counts between packets. When set to 0
-                                                         the L2C DMA address is incremented to the next
-                                                         4-byte aligned address after adding byte-count. */
-        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
-                                                         set to '0' for operation. */
-        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
-        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
-        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D+ line. '1' pull down-resistance is connected
-                                                         to D+/ '0' pull down resistance is not connected
-                                                         to D+. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D- line. '1' pull down-resistance is connected
-                                                         to D-. '0' pull down resistance is not connected
-                                                         to D-. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
-                                                         USB is acting as device. This field needs to be
-                                                         set while the USB is in reset. */
-        uint64_t tuning                  : 4;       /**< Transmitter Tuning for High-Speed Operation.
-                                                         Tunes the current supply and rise/fall output
-                                                         times for high-speed operation.
-                                                         [20:19] == 11: Current supply increased
-                                                         approximately 9%
-                                                         [20:19] == 10: Current supply increased
-                                                         approximately 4.5%
-                                                         [20:19] == 01: Design default.
-                                                         [20:19] == 00: Current supply decreased
-                                                         approximately 4.5%
-                                                         [22:21] == 11: Rise and fall times are increased.
-                                                         [22:21] == 10: Design default.
-                                                         [22:21] == 01: Rise and fall times are decreased.
-                                                         [22:21] == 00: Rise and fall times are decreased
-                                                         further as compared to the 01 setting. */
-        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
-                                                         Enables or disables bit stuffing on data[15:8]
-                                                         when bit-stuffing is enabled. */
-        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
-                                                         Enables or disables bit stuffing on data[7:0]
-                                                         when bit-stuffing is enabled. */
-        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
-                                                         '1': During data transmission the receive is
-                                                         enabled.
-                                                         '0': During data transmission the receive is
-                                                         disabled.
-                                                         Must be '0' for normal operation. */
-        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
-                                                         '1' The PHY's analog_test pin is enabled for the
-                                                         input and output of applicable analog test signals.
-                                                         '0' THe analog_test pin is disabled. */
-        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
-                                                         Used to activate BIST in the PHY. */
-        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
-                                                         '1' test_data_out[3:0] (PHY) register contents
-                                                         are output. '0' internaly generated signals are
-                                                         output. */
-        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
-                                                         Specifies the register address for writing to or
-                                                         reading from the PHY test interface register. */
-        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
-                                                         This is a test bus. Data is present on [3:0],
-                                                         and its corresponding select (enable) is present
-                                                         on bits [7:4]. */
-        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
-                                                         This is a test signal. When the USB Core is
-                                                         powered up (not in Susned Mode), an automatic
-                                                         tester can use this to disable phy_clock and
-                                                         free_clk, then re-eanable them with an aligned
-                                                         phase.
-                                                         '1': The phy_clk and free_clk outputs are
-                                                         disabled. "0": The phy_clock and free_clk outputs
-                                                         are available within a specific period after the
-                                                         de-assertion. */
-#else
-        uint64_t ate_reset               : 1;
-        uint64_t tdata_in                : 8;
-        uint64_t taddr_in                : 4;
-        uint64_t tdata_sel               : 1;
-        uint64_t bist_enb                : 1;
-        uint64_t vtest_enb               : 1;
-        uint64_t loop_enb                : 1;
-        uint64_t tx_bs_en                : 1;
-        uint64_t tx_bs_enh               : 1;
-        uint64_t tuning                  : 4;
-        uint64_t hst_mode                : 1;
-        uint64_t dm_pulld                : 1;
-        uint64_t dp_pulld                : 1;
-        uint64_t tclk                    : 1;
-        uint64_t usbp_bist               : 1;
-        uint64_t usbc_end                : 1;
-        uint64_t dma_bmode               : 1;
-        uint64_t txpreemphasistune       : 1;
-        uint64_t siddq                   : 1;
-        uint64_t tdata_out               : 4;
-        uint64_t bist_err                : 1;
-        uint64_t bist_done               : 1;
-        uint64_t hsbist                  : 1;
-        uint64_t fsbist                  : 1;
-        uint64_t lsbist                  : 1;
-        uint64_t drvvbus                 : 1;
-        uint64_t portreset               : 1;
-        uint64_t otgdisable              : 1;
-        uint64_t otgtune                 : 3;
-        uint64_t compdistune             : 3;
-        uint64_t sqrxtune                : 3;
-        uint64_t txhsxvtune              : 2;
-        uint64_t txfslstune              : 4;
-        uint64_t txvreftune              : 4;
-        uint64_t txrisetune              : 1;
-#endif
-    } s;
-    struct cvmx_usbnx_usbp_ctl_status_cn30xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_38_63          : 26;
-        uint64_t bist_done               : 1;       /**< PHY Bist Done.
-                                                         Asserted at the end of the PHY BIST sequence. */
-        uint64_t bist_err                : 1;       /**< PHY Bist Error.
-                                                         Indicates an internal error was detected during
-                                                         the BIST sequence. */
-        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
-                                                         Presents either internaly generated signals or
-                                                         test register contents, based upon the value of
-                                                         test_data_out_sel. */
-        uint64_t reserved_30_31          : 2;
-        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
-                                                         with byte-counts between packets. When set to 0
-                                                         the L2C DMA address is incremented to the next
-                                                         4-byte aligned address after adding byte-count. */
-        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
-                                                         set to '0' for operation. */
-        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
-        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
-        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D+ line. '1' pull down-resistance is connected
-                                                         to D+/ '0' pull down resistance is not connected
-                                                         to D+. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D- line. '1' pull down-resistance is connected
-                                                         to D-. '0' pull down resistance is not connected
-                                                         to D-. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
-                                                         USB is acting as device. This field needs to be
-                                                         set while the USB is in reset. */
-        uint64_t tuning                  : 4;       /**< Transmitter Tuning for High-Speed Operation.
-                                                         Tunes the current supply and rise/fall output
-                                                         times for high-speed operation.
-                                                         [20:19] == 11: Current supply increased
-                                                         approximately 9%
-                                                         [20:19] == 10: Current supply increased
-                                                         approximately 4.5%
-                                                         [20:19] == 01: Design default.
-                                                         [20:19] == 00: Current supply decreased
-                                                         approximately 4.5%
-                                                         [22:21] == 11: Rise and fall times are increased.
-                                                         [22:21] == 10: Design default.
-                                                         [22:21] == 01: Rise and fall times are decreased.
-                                                         [22:21] == 00: Rise and fall times are decreased
-                                                         further as compared to the 01 setting. */
-        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
-                                                         Enables or disables bit stuffing on data[15:8]
-                                                         when bit-stuffing is enabled. */
-        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
-                                                         Enables or disables bit stuffing on data[7:0]
-                                                         when bit-stuffing is enabled. */
-        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
-                                                         '1': During data transmission the receive is
-                                                         enabled.
-                                                         '0': During data transmission the receive is
-                                                         disabled.
-                                                         Must be '0' for normal operation. */
-        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
-                                                         '1' The PHY's analog_test pin is enabled for the
-                                                         input and output of applicable analog test signals.
-                                                         '0' THe analog_test pin is disabled. */
-        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
-                                                         Used to activate BIST in the PHY. */
-        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
-                                                         '1' test_data_out[3:0] (PHY) register contents
-                                                         are output. '0' internaly generated signals are
-                                                         output. */
-        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
-                                                         Specifies the register address for writing to or
-                                                         reading from the PHY test interface register. */
-        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
-                                                         This is a test bus. Data is present on [3:0],
-                                                         and its corresponding select (enable) is present
-                                                         on bits [7:4]. */
-        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
-                                                         This is a test signal. When the USB Core is
-                                                         powered up (not in Susned Mode), an automatic
-                                                         tester can use this to disable phy_clock and
-                                                         free_clk, then re-eanable them with an aligned
-                                                         phase.
-                                                         '1': The phy_clk and free_clk outputs are
-                                                         disabled. "0": The phy_clock and free_clk outputs
-                                                         are available within a specific period after the
-                                                         de-assertion. */
-#else
-        uint64_t ate_reset               : 1;
-        uint64_t tdata_in                : 8;
-        uint64_t taddr_in                : 4;
-        uint64_t tdata_sel               : 1;
-        uint64_t bist_enb                : 1;
-        uint64_t vtest_enb               : 1;
-        uint64_t loop_enb                : 1;
-        uint64_t tx_bs_en                : 1;
-        uint64_t tx_bs_enh               : 1;
-        uint64_t tuning                  : 4;
-        uint64_t hst_mode                : 1;
-        uint64_t dm_pulld                : 1;
-        uint64_t dp_pulld                : 1;
-        uint64_t tclk                    : 1;
-        uint64_t usbp_bist               : 1;
-        uint64_t usbc_end                : 1;
-        uint64_t dma_bmode               : 1;
-        uint64_t reserved_30_31          : 2;
-        uint64_t tdata_out               : 4;
-        uint64_t bist_err                : 1;
-        uint64_t bist_done               : 1;
-        uint64_t reserved_38_63          : 26;
-#endif
-    } cn30xx;
-    struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
-    struct cvmx_usbnx_usbp_ctl_status_cn50xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
-        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
-        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
-        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
-        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
-        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
-        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
-        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
-        uint64_t portreset               : 1;       /**< Per_Port Reset */
-        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
-        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
-        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
-        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
-        uint64_t bist_done               : 1;       /**< PHY Bist Done.
-                                                         Asserted at the end of the PHY BIST sequence. */
-        uint64_t bist_err                : 1;       /**< PHY Bist Error.
-                                                         Indicates an internal error was detected during
-                                                         the BIST sequence. */
-        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
-                                                         Presents either internaly generated signals or
-                                                         test register contents, based upon the value of
-                                                         test_data_out_sel. */
-        uint64_t reserved_31_31          : 1;
-        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
-        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
-                                                         with byte-counts between packets. When set to 0
-                                                         the L2C DMA address is incremented to the next
-                                                         4-byte aligned address after adding byte-count. */
-        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
-                                                         set to '0' for operation. */
-        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
-        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
-        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D+ line. '1' pull down-resistance is connected
-                                                         to D+/ '0' pull down resistance is not connected
-                                                         to D+. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D- line. '1' pull down-resistance is connected
-                                                         to D-. '0' pull down resistance is not connected
-                                                         to D-. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
-                                                         USB is acting as device. This field needs to be
-                                                         set while the USB is in reset. */
-        uint64_t reserved_19_22          : 4;
-        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
-                                                         Enables or disables bit stuffing on data[15:8]
-                                                         when bit-stuffing is enabled. */
-        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
-                                                         Enables or disables bit stuffing on data[7:0]
-                                                         when bit-stuffing is enabled. */
-        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
-                                                         '1': During data transmission the receive is
-                                                         enabled.
-                                                         '0': During data transmission the receive is
-                                                         disabled.
-                                                         Must be '0' for normal operation. */
-        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
-                                                         '1' The PHY's analog_test pin is enabled for the
-                                                         input and output of applicable analog test signals.
-                                                         '0' THe analog_test pin is disabled. */
-        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
-                                                         Used to activate BIST in the PHY. */
-        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
-                                                         '1' test_data_out[3:0] (PHY) register contents
-                                                         are output. '0' internaly generated signals are
-                                                         output. */
-        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
-                                                         Specifies the register address for writing to or
-                                                         reading from the PHY test interface register. */
-        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
-                                                         This is a test bus. Data is present on [3:0],
-                                                         and its corresponding select (enable) is present
-                                                         on bits [7:4]. */
-        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
-                                                         This is a test signal. When the USB Core is
-                                                         powered up (not in Susned Mode), an automatic
-                                                         tester can use this to disable phy_clock and
-                                                         free_clk, then re-eanable them with an aligned
-                                                         phase.
-                                                         '1': The phy_clk and free_clk outputs are
-                                                         disabled. "0": The phy_clock and free_clk outputs
-                                                         are available within a specific period after the
-                                                         de-assertion. */
-#else
-        uint64_t ate_reset               : 1;
-        uint64_t tdata_in                : 8;
-        uint64_t taddr_in                : 4;
-        uint64_t tdata_sel               : 1;
-        uint64_t bist_enb                : 1;
-        uint64_t vtest_enb               : 1;
-        uint64_t loop_enb                : 1;
-        uint64_t tx_bs_en                : 1;
-        uint64_t tx_bs_enh               : 1;
-        uint64_t reserved_19_22          : 4;
-        uint64_t hst_mode                : 1;
-        uint64_t dm_pulld                : 1;
-        uint64_t dp_pulld                : 1;
-        uint64_t tclk                    : 1;
-        uint64_t usbp_bist               : 1;
-        uint64_t usbc_end                : 1;
-        uint64_t dma_bmode               : 1;
-        uint64_t txpreemphasistune       : 1;
-        uint64_t reserved_31_31          : 1;
-        uint64_t tdata_out               : 4;
-        uint64_t bist_err                : 1;
-        uint64_t bist_done               : 1;
-        uint64_t hsbist                  : 1;
-        uint64_t fsbist                  : 1;
-        uint64_t lsbist                  : 1;
-        uint64_t drvvbus                 : 1;
-        uint64_t portreset               : 1;
-        uint64_t otgdisable              : 1;
-        uint64_t otgtune                 : 3;
-        uint64_t compdistune             : 3;
-        uint64_t sqrxtune                : 3;
-        uint64_t txhsxvtune              : 2;
-        uint64_t txfslstune              : 4;
-        uint64_t txvreftune              : 4;
-        uint64_t txrisetune              : 1;
-#endif
-    } cn50xx;
-    struct cvmx_usbnx_usbp_ctl_status_cn52xx
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
-        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
-        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
-        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
-        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
-        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
-        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
-        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
-        uint64_t portreset               : 1;       /**< Per_Port Reset */
-        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
-        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
-        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
-        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
-        uint64_t bist_done               : 1;       /**< PHY Bist Done.
-                                                         Asserted at the end of the PHY BIST sequence. */
-        uint64_t bist_err                : 1;       /**< PHY Bist Error.
-                                                         Indicates an internal error was detected during
-                                                         the BIST sequence. */
-        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
-                                                         Presents either internaly generated signals or
-                                                         test register contents, based upon the value of
-                                                         test_data_out_sel. */
-        uint64_t siddq                   : 1;       /**< Drives the USBP (USB-PHY) SIDDQ input.
-                                                         Normally should be set to zero.
-                                                         When customers have no intent to use USB PHY
-                                                         interface, they should:
-                                                           - still provide 3.3V to USB_VDD33, and
-                                                           - tie USB_REXT to 3.3V supply, and
-                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
-        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
-        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
-                                                         with byte-counts between packets. When set to 0
-                                                         the L2C DMA address is incremented to the next
-                                                         4-byte aligned address after adding byte-count. */
-        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
-                                                         set to '0' for operation. */
-        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
-        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
-        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D+ line. '1' pull down-resistance is connected
-                                                         to D+/ '0' pull down resistance is not connected
-                                                         to D+. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
-                                                         This signal enables the pull-down resistance on
-                                                         the D- line. '1' pull down-resistance is connected
-                                                         to D-. '0' pull down resistance is not connected
-                                                         to D-. When an A/B device is acting as a host
-                                                         (downstream-facing port), dp_pulldown and
-                                                         dm_pulldown are enabled. This must not toggle
-                                                         during normal opeartion. */
-        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
-                                                         USB is acting as device. This field needs to be
-                                                         set while the USB is in reset. */
-        uint64_t reserved_19_22          : 4;
-        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
-                                                         Enables or disables bit stuffing on data[15:8]
-                                                         when bit-stuffing is enabled. */
-        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
-                                                         Enables or disables bit stuffing on data[7:0]
-                                                         when bit-stuffing is enabled. */
-        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
-                                                         '1': During data transmission the receive is
-                                                         enabled.
-                                                         '0': During data transmission the receive is
-                                                         disabled.
-                                                         Must be '0' for normal operation. */
-        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
-                                                         '1' The PHY's analog_test pin is enabled for the
-                                                         input and output of applicable analog test signals.
-                                                         '0' THe analog_test pin is disabled. */
-        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
-                                                         Used to activate BIST in the PHY. */
-        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
-                                                         '1' test_data_out[3:0] (PHY) register contents
-                                                         are output. '0' internaly generated signals are
-                                                         output. */
-        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
-                                                         Specifies the register address for writing to or
-                                                         reading from the PHY test interface register. */
-        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
-                                                         This is a test bus. Data is present on [3:0],
-                                                         and its corresponding select (enable) is present
-                                                         on bits [7:4]. */
-        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
-                                                         This is a test signal. When the USB Core is
-                                                         powered up (not in Susned Mode), an automatic
-                                                         tester can use this to disable phy_clock and
-                                                         free_clk, then re-eanable them with an aligned
-                                                         phase.
-                                                         '1': The phy_clk and free_clk outputs are
-                                                         disabled. "0": The phy_clock and free_clk outputs
-                                                         are available within a specific period after the
-                                                         de-assertion. */
-#else
-        uint64_t ate_reset               : 1;
-        uint64_t tdata_in                : 8;
-        uint64_t taddr_in                : 4;
-        uint64_t tdata_sel               : 1;
-        uint64_t bist_enb                : 1;
-        uint64_t vtest_enb               : 1;
-        uint64_t loop_enb                : 1;
-        uint64_t tx_bs_en                : 1;
-        uint64_t tx_bs_enh               : 1;
-        uint64_t reserved_19_22          : 4;
-        uint64_t hst_mode                : 1;
-        uint64_t dm_pulld                : 1;
-        uint64_t dp_pulld                : 1;
-        uint64_t tclk                    : 1;
-        uint64_t usbp_bist               : 1;
-        uint64_t usbc_end                : 1;
-        uint64_t dma_bmode               : 1;
-        uint64_t txpreemphasistune       : 1;
-        uint64_t siddq                   : 1;
-        uint64_t tdata_out               : 4;
-        uint64_t bist_err                : 1;
-        uint64_t bist_done               : 1;
-        uint64_t hsbist                  : 1;
-        uint64_t fsbist                  : 1;
-        uint64_t lsbist                  : 1;
-        uint64_t drvvbus                 : 1;
-        uint64_t portreset               : 1;
-        uint64_t otgdisable              : 1;
-        uint64_t otgtune                 : 3;
-        uint64_t compdistune             : 3;
-        uint64_t sqrxtune                : 3;
-        uint64_t txhsxvtune              : 2;
-        uint64_t txfslstune              : 4;
-        uint64_t txvreftune              : 4;
-        uint64_t txrisetune              : 1;
-#endif
-    } cn52xx;
-    struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
-    struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx;
-    struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
-} cvmx_usbnx_usbp_ctl_status_t;
-
-
-/**
- * cvmx_zip_cmd_bist_result
- *
- * Notes:
- * Access to the internal BiST results
- * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_cmd_bist_result_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_31_63          : 33;
-        uint64_t zip_core                : 27;      /**< BiST result of the ZIP_CORE memories */
-        uint64_t zip_ctl                 : 4;       /**< BiST result of the ZIP_CTL  memories */
-#else
-        uint64_t zip_ctl                 : 4;
-        uint64_t zip_core                : 27;
-        uint64_t reserved_31_63          : 33;
-#endif
-    } s;
-    struct cvmx_zip_cmd_bist_result_s    cn31xx;
-    struct cvmx_zip_cmd_bist_result_s    cn38xx;
-    struct cvmx_zip_cmd_bist_result_s    cn38xxp2;
-    struct cvmx_zip_cmd_bist_result_s    cn56xx;
-    struct cvmx_zip_cmd_bist_result_s    cn56xxp1;
-    struct cvmx_zip_cmd_bist_result_s    cn58xx;
-    struct cvmx_zip_cmd_bist_result_s    cn58xxp1;
-} cvmx_zip_cmd_bist_result_t;
-
-
-/**
- * cvmx_zip_cmd_buf
- *
- * Notes:
- * Sets the command buffer parameters
- * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
- * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
- * pointer each time that the command buffer segment is exhausted.
- * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
- * this register to effectively reset the command buffer state machine.  New commands will then be
- * read from the newly specified command buffer pointer.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_cmd_buf_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_58_63          : 6;
-        uint64_t dwb                     : 9;       /**< Number of DontWriteBacks */
-        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
-        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
-        uint64_t ptr                     : 33;      /**< Initial command buffer pointer[39:7] (128B-aligned) */
-#else
-        uint64_t ptr                     : 33;
-        uint64_t size                    : 13;
-        uint64_t pool                    : 3;
-        uint64_t dwb                     : 9;
-        uint64_t reserved_58_63          : 6;
-#endif
-    } s;
-    struct cvmx_zip_cmd_buf_s            cn31xx;
-    struct cvmx_zip_cmd_buf_s            cn38xx;
-    struct cvmx_zip_cmd_buf_s            cn38xxp2;
-    struct cvmx_zip_cmd_buf_s            cn56xx;
-    struct cvmx_zip_cmd_buf_s            cn56xxp1;
-    struct cvmx_zip_cmd_buf_s            cn58xx;
-    struct cvmx_zip_cmd_buf_s            cn58xxp1;
-} cvmx_zip_cmd_buf_t;
-
-
-/**
- * cvmx_zip_cmd_ctl
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_cmd_ctl_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_2_63           : 62;
-        uint64_t forceclk                : 1;       /**< Force zip_ctl__clock_on_b == 1 when set */
-        uint64_t reset                   : 1;       /**< Reset oneshot pulse for zip core */
-#else
-        uint64_t reset                   : 1;
-        uint64_t forceclk                : 1;
-        uint64_t reserved_2_63           : 62;
-#endif
-    } s;
-    struct cvmx_zip_cmd_ctl_s            cn31xx;
-    struct cvmx_zip_cmd_ctl_s            cn38xx;
-    struct cvmx_zip_cmd_ctl_s            cn38xxp2;
-    struct cvmx_zip_cmd_ctl_s            cn56xx;
-    struct cvmx_zip_cmd_ctl_s            cn56xxp1;
-    struct cvmx_zip_cmd_ctl_s            cn58xx;
-    struct cvmx_zip_cmd_ctl_s            cn58xxp1;
-} cvmx_zip_cmd_ctl_t;
-
-
-/**
- * cvmx_zip_constants
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_constants_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_48_63          : 16;
-        uint64_t depth                   : 16;      /**< Maximum search depth for compression */
-        uint64_t onfsize                 : 12;      /**< Output near full threshhold in bytes */
-        uint64_t ctxsize                 : 12;      /**< Context size in bytes */
-        uint64_t reserved_1_7            : 7;
-        uint64_t disabled                : 1;       /**< 1=zip unit isdisabled, 0=zip unit not disabled */
-#else
-        uint64_t disabled                : 1;
-        uint64_t reserved_1_7            : 7;
-        uint64_t ctxsize                 : 12;
-        uint64_t onfsize                 : 12;
-        uint64_t depth                   : 16;
-        uint64_t reserved_48_63          : 16;
-#endif
-    } s;
-    struct cvmx_zip_constants_s          cn31xx;
-    struct cvmx_zip_constants_s          cn38xx;
-    struct cvmx_zip_constants_s          cn38xxp2;
-    struct cvmx_zip_constants_s          cn56xx;
-    struct cvmx_zip_constants_s          cn56xxp1;
-    struct cvmx_zip_constants_s          cn58xx;
-    struct cvmx_zip_constants_s          cn58xxp1;
-} cvmx_zip_constants_t;
-
-
-/**
- * cvmx_zip_debug0
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_debug0_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_14_63          : 50;
-        uint64_t asserts                 : 14;      /**< FIFO assertion checks */
-#else
-        uint64_t asserts                 : 14;
-        uint64_t reserved_14_63          : 50;
-#endif
-    } s;
-    struct cvmx_zip_debug0_s             cn31xx;
-    struct cvmx_zip_debug0_s             cn38xx;
-    struct cvmx_zip_debug0_s             cn38xxp2;
-    struct cvmx_zip_debug0_s             cn56xx;
-    struct cvmx_zip_debug0_s             cn56xxp1;
-    struct cvmx_zip_debug0_s             cn58xx;
-    struct cvmx_zip_debug0_s             cn58xxp1;
-} cvmx_zip_debug0_t;
-
-
-/**
- * cvmx_zip_error
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- *
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_error_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
-#else
-        uint64_t doorbell                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_zip_error_s              cn31xx;
-    struct cvmx_zip_error_s              cn38xx;
-    struct cvmx_zip_error_s              cn38xxp2;
-    struct cvmx_zip_error_s              cn56xx;
-    struct cvmx_zip_error_s              cn56xxp1;
-    struct cvmx_zip_error_s              cn58xx;
-    struct cvmx_zip_error_s              cn58xxp1;
-} cvmx_zip_error_t;
-
-
-/**
- * cvmx_zip_int_mask
- *
- * Notes:
- * Note that this CSR is present only in chip revisions beginning with pass2.
- * When a mask bit is set, the corresponding interrupt is enabled.
- */
-typedef union
-{
-    uint64_t u64;
-    struct cvmx_zip_int_mask_s
-    {
-#if __BYTE_ORDER == __BIG_ENDIAN
-        uint64_t reserved_1_63           : 63;
-        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
-#else
-        uint64_t doorbell                : 1;
-        uint64_t reserved_1_63           : 63;
-#endif
-    } s;
-    struct cvmx_zip_int_mask_s           cn31xx;
-    struct cvmx_zip_int_mask_s           cn38xx;
-    struct cvmx_zip_int_mask_s           cn38xxp2;
-    struct cvmx_zip_int_mask_s           cn56xx;
-    struct cvmx_zip_int_mask_s           cn56xxp1;
-    struct cvmx_zip_int_mask_s           cn58xx;
-    struct cvmx_zip_int_mask_s           cn58xxp1;
-} cvmx_zip_int_mask_t;
+#include "cvmx-agl-defs.h"
+#include "cvmx-asxx-defs.h"
+#include "cvmx-asx0-defs.h"
+#include "cvmx-ciu-defs.h"
+#include "cvmx-dbg-defs.h"
+#include "cvmx-dfa-defs.h"
+#include "cvmx-dfm-defs.h"
+#include "cvmx-dpi-defs.h"
+#include "cvmx-fpa-defs.h"
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-gpio-defs.h"
+#include "cvmx-iob-defs.h"
+#include "cvmx-ipd-defs.h"
+#include "cvmx-key-defs.h"
+#include "cvmx-l2c-defs.h"
+#include "cvmx-l2d-defs.h"
+#include "cvmx-l2t-defs.h"
+#include "cvmx-led-defs.h"
+#include "cvmx-lmcx-defs.h"
+#include "cvmx-mio-defs.h"
+#include "cvmx-mixx-defs.h"
+#include "cvmx-mpi-defs.h"
+#include "cvmx-ndf-defs.h"
+#include "cvmx-npei-defs.h"
+#include "cvmx-npi-defs.h"
+#include "cvmx-pci-defs.h"
+#include "cvmx-pcieepx-defs.h"
+#include "cvmx-pciercx-defs.h"
+#include "cvmx-pcmx-defs.h"
+#include "cvmx-pcm-defs.h"
+#include "cvmx-pcsx-defs.h"
+#include "cvmx-pcsxx-defs.h"
+#include "cvmx-pemx-defs.h"
+#include "cvmx-pescx-defs.h"
+#include "cvmx-pip-defs.h"
+#include "cvmx-pko-defs.h"
+#include "cvmx-pow-defs.h"
+#include "cvmx-rad-defs.h"
+#include "cvmx-rnm-defs.h"
+#include "cvmx-sli-defs.h"
+#include "cvmx-smix-defs.h"
+#include "cvmx-smi-defs.h"
+#include "cvmx-spxx-defs.h"
+#include "cvmx-spx0-defs.h"
+#include "cvmx-sriox-defs.h"
+#include "cvmx-sriomaintx-defs.h"
+#include "cvmx-srxx-defs.h"
+#include "cvmx-stxx-defs.h"
+#include "cvmx-tim-defs.h"
+#include "cvmx-tra-defs.h"
+#include "cvmx-uahcx-defs.h"
+#include "cvmx-uctlx-defs.h"
+#include "cvmx-usbcx-defs.h"
+#include "cvmx-usbnx-defs.h"
+#include "cvmx-zip-defs.h"
+
+#include "cvmx-pexp-defs.h"
 #endif /* __CVMX_CSR_TYPEDEFS_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-csr.h b/sys/contrib/octeon-sdk/cvmx-csr.h
index 80a8939..412662e 100644
--- a/sys/contrib/octeon-sdk/cvmx-csr.h
+++ b/sys/contrib/octeon-sdk/cvmx-csr.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Configuration and status register (CSR) address and type definitions for
  * Octoen.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 #ifndef __CVMX_CSR_H__
@@ -59,7 +61,6 @@
 
 #include "cvmx-platform.h"
 #include "cvmx-csr-enums.h"
-#include "cvmx-csr-addresses.h"
 #include "cvmx-csr-typedefs.h"
 
 /* Map the HW names to the SDK historical names */
@@ -163,7 +164,7 @@ typedef cvmx_tim_reg_flags_t            cvmx_tim_control_t;
 #define CVMX_MIO_BOOT_REG_CFG0		CVMX_MIO_BOOT_REG_CFGX(0)
 #define CVMX_MIO_BOOT_REG_TIM0		CVMX_MIO_BOOT_REG_TIMX(0)
 
-/* The CN3XXX and CN58XX chips use to not have a LMC number
+/* The CN3XXX and CN58XX chips used to not have a LMC number
     passed to the address macros. These are here to supply backwards
     compatability with old code. Code should really use the new addresses
     with bus arguments for support on other chips */
@@ -199,7 +200,7 @@ typedef cvmx_tim_reg_flags_t            cvmx_tim_control_t;
 #define CVMX_LMC_WODT_CTL0              CVMX_LMCX_WODT_CTL0(0)
 #define CVMX_LMC_WODT_CTL1              CVMX_LMCX_WODT_CTL1(0)
 
-/* The CN3XXX and CN58XX chips use to not have a TWSI bus number
+/* The CN3XXX and CN58XX chips used to not have a TWSI bus number
     passed to the address macros. These are here to supply backwards
     compatability with old code. Code should really use the new addresses
     with bus arguments for support on other chips */
@@ -208,7 +209,7 @@ typedef cvmx_tim_reg_flags_t            cvmx_tim_control_t;
 #define CVMX_MIO_TWS_SW_TWSI_EXT    CVMX_MIO_TWSX_SW_TWSI_EXT(0)
 #define CVMX_MIO_TWS_TWSI_SW        CVMX_MIO_TWSX_TWSI_SW(0)
 
-/* The CN3XXX and CN58XX chips use to not have a SMI/MDIO bus number
+/* The CN3XXX and CN58XX chips used to not have a SMI/MDIO bus number
     passed to the address macros. These are here to supply backwards
     compatability with old code. Code should really use the new addresses
     with bus arguments for support on other chips */
diff --git a/sys/contrib/octeon-sdk/cvmx-cvmmem.h b/sys/contrib/octeon-sdk/cvmx-cvmmem.h
deleted file mode 100644
index 7d79ee9..0000000
--- a/sys/contrib/octeon-sdk/cvmx-cvmmem.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * Interfaces and definitions for processor local memory
- *
- * <hr>$Revision: 41586 $<hr>
- */
-
-#ifndef __CVMX_CVMMEM_H__
-#define __CVMX_CVMMEM_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-
-
-
-
-
-
-
-
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif // __CVMX_CVMMEM_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-dbg-defs.h b/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
new file mode 100644
index 0000000..e435deb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
@@ -0,0 +1,156 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-dbg-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dbg.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_DBG_TYPEDEFS_H__
+#define __CVMX_DBG_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
+static inline uint64_t CVMX_DBG_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
+}
+#else
+#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
+#endif
+
+/**
+ * cvmx_dbg_data
+ *
+ * DBG_DATA = Debug Data Register
+ *
+ * Value returned on the debug-data lines from the RSLs
+ */
+union cvmx_dbg_data
+{
+	uint64_t u64;
+	struct cvmx_dbg_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_dbg_data_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t pll_mul                      : 3;  /**< pll_mul pins sampled at DCOK assertion */
+	uint64_t reserved_23_27               : 5;
+	uint64_t c_mul                        : 5;  /**< Core PLL multiplier sampled at DCOK assertion */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t reserved_23_27               : 5;
+	uint64_t pll_mul                      : 3;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn30xx;
+	struct cvmx_dbg_data_cn30xx           cn31xx;
+	struct cvmx_dbg_data_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t d_mul                        : 4;  /**< D_MUL pins sampled on DCOK assertion */
+	uint64_t dclk_mul2                    : 1;  /**< Should always be set for fast DDR-II operation */
+	uint64_t cclk_div2                    : 1;  /**< Should always be clear for fast core clock */
+	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t cclk_div2                    : 1;
+	uint64_t dclk_mul2                    : 1;
+	uint64_t d_mul                        : 4;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn38xx;
+	struct cvmx_dbg_data_cn38xx           cn38xxp2;
+	struct cvmx_dbg_data_cn30xx           cn50xx;
+	struct cvmx_dbg_data_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t rem                          : 6;  /**< Remaining debug_select pins sampled at DCOK */
+	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t rem                          : 6;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn58xx;
+	struct cvmx_dbg_data_cn58xx           cn58xxp1;
+};
+typedef union cvmx_dbg_data cvmx_dbg_data_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-handler.S b/sys/contrib/octeon-sdk/cvmx-debug-handler.S
new file mode 100644
index 0000000..35389cc
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-debug-handler.S
@@ -0,0 +1,271 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+#undef __ASSEMBLY__
+#define __ASSEMBLY__
+
+#ifdef __linux__
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#else
+#include <machine/asm.h>
+#include <machine/regdef.h>
+#endif
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-asm.h>
+#include <asm/octeon/octeon-boot-info.h>
+#else
+#include "executive-config.h"
+#include "cvmx-asm.h"
+
+#ifndef __OCTEON_NEWLIB__
+#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+#else
+#include "octeon-boot-info.h"
+#endif
+
+#endif
+
+/* The registers saving/restoring is split into two because k0 is stored in the COP0_DESAVE register.  */
+#define REGS0 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25
+#define REGS1 27,28,29,30,31
+
+#define SAVE_REGISTER(reg)	\
+	sd reg, 0(k0);		\
+	addi k0, 8
+
+#define RESTORE_REGISTER(reg)	\
+	ld reg, -8(k0);		\
+	addi k0, -8
+
+#define SAVE_COP0(reg)		\
+	dmfc0 k1,reg;		\
+	sd k1, 0(k0);		\
+	addi k0, 8
+
+#define RESTORE_COP0(reg)	\
+	ld k1, -8(k0);		\
+	addi k0, -8;		\
+	dmtc0 k1,reg	
+
+#define SAVE_ADDRESS(addr)	\
+	dli k1, addr;		\
+	ld k1, 0(k1);		\
+	sd k1, 0(k0);		\
+	addi k0, 8
+
+#define RESTORE_ADDRESS(addr)	\
+	dli t0, addr;		\
+	ld k1, -8(k0);		\
+	sd k1, 0(t0);		\
+	addi k0, -8
+
+#define REG_SAVE_BASE_DIV_4  (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 2)
+
+
+#define HW_INSTRUCTION_BREAKPOINT_STATUS            (0xFFFFFFFFFF301000)
+#define HW_INSTRUCTION_BREAKPOINT_ADDRESS(num)      (0xFFFFFFFFFF301100 + 0x100 * (num))
+#define HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF301108 + 0x100 * (num))
+#define HW_INSTRUCTION_BREAKPOINT_ASID(num)         (0xFFFFFFFFFF301110 + 0x100 * (num))
+#define HW_INSTRUCTION_BREAKPOINT_CONTROL(num)      (0xFFFFFFFFFF301118 + 0x100 * (num))
+
+#define HW_DATA_BREAKPOINT_STATUS                   (0xFFFFFFFFFF302000)
+#define HW_DATA_BREAKPOINT_ADDRESS(num)             (0xFFFFFFFFFF302100 + 0x100 * (num))
+#define HW_DATA_BREAKPOINT_ADDRESS_MASK(num)        (0xFFFFFFFFFF302108 + 0x100 * (num))
+#define HW_DATA_BREAKPOINT_ASID(num)                (0xFFFFFFFFFF302110 + 0x100 * (num))
+#define HW_DATA_BREAKPOINT_CONTROL(num)             (0xFFFFFFFFFF302118 + 0x100 * (num))
+
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#define loadaddr(reg, addr, shift) \
+	dla	reg, addr##_all; \
+        mfc0    $1, $15, 1; \
+        andi    $1, 0xff; \
+        sll     $1, shift; \
+	add	reg, reg, $1
+#else
+#define loadaddr(reg, addr, shift) \
+	dla	reg, addr
+#endif
+
+
+	.set	noreorder
+	.set	noat
+
+	.text
+
+// Detect debug-mode exception, save all registers, create a stack and then
+// call the stage3 C function.
+
+	.ent	__cvmx_debug_handler_stage2
+	.globl	__cvmx_debug_handler_stage2
+__cvmx_debug_handler_stage2:
+	// Save off k0 in COP0_DESAVE
+	dmtc0	k0, COP0_DESAVE
+
+	// Use reserved space in kseg0 to save off some temp regs
+        mfc0    k0, $15, 1  // read exception base reg.
+        andi    k0, 0xff    // mask off core ID
+        sll     k0, 12      // multiply by 4096 (512 dwords) DEBUG_NUMREGS
+
+        addiu   k0,  REG_SAVE_BASE_DIV_4    
+        addiu   k0,  REG_SAVE_BASE_DIV_4
+        addiu   k0,  REG_SAVE_BASE_DIV_4
+        addiu   k0,  REG_SAVE_BASE_DIV_4
+		// add base offset - after exeption vectors for all cores
+
+        rotr    k0, k0, 31   // set bit 31 for kseg0 access
+        addi    k0, 1
+        rotr    k0, k0, 1
+
+	// save off k1 and at ($1) off to the bootloader reg save area
+	// at is used by dla
+	sd      $1, 8(k0)	// save at for temp usage
+	sd      k1, 216(k0)	// save k1 for temp usage
+
+
+	// Detect debug-mode exception.
+	// If COP0_MULTICOREDEBUG[DExecC] is set,
+	dmfc0	k1, COP0_MULTICOREDEBUG
+	bbit0	k1, 16, noexc
+	nop
+
+	// COP0_DEBUG[DINT,DIB,DDBS,DBp,DSS] are not set and
+	dmfc0	k1, COP0_DEBUG
+	andi	k1, 0x3f
+	bnez	k1, noexc
+	nop
+
+	// COP0_DEBUG[DExecC] is set.
+	dmfc0	k1, COP0_DEBUG
+	dext	k1,k1,10,5
+	beqz	k1,noexc
+	nop
+	
+	// We don't handle debug-mode exceptions in delay-slots so DEBUG[DBD]
+	// should not be set.  If yes spin forever.
+	dmfc0	k1, COP0_DEBUG
+1:
+	bbit1	k1, 31, 1b
+	nop
+
+	// It's a debug-mode exception.  Flag the occurence.  Also if it's
+	// expected just ignore it but returning the subsequent instruction
+	// after the fault.
+	
+	loadaddr (k1, __cvmx_debug_mode_exception_occured, 3)
+	sd	k1, 0(k1)
+
+	loadaddr (k1, __cvmx_debug_mode_exception_ignore, 3)
+	ld	k1, 0(k1)
+	beqz	k1, noexc
+	nop
+
+	// Restore k1 and at from the bootloader reg save area
+	ld      $1, 8(k0)	// save at for temp usage
+	ld      k1, 216(k0)	// save k1 for temp usage
+
+	dmfc0	k0, COP0_DEPC
+	// Skip the faulting instruction.
+	daddiu	k0, 4
+	jr	k0
+	dmfc0	k0, COP0_DESAVE
+
+noexc:	
+
+	loadaddr (k1, __cvmx_debug_save_regs_area, 8)
+
+	// Restore at
+	ld      $1, 8(k0)	// restore at for temp usage
+
+	.irp	n, REGS0
+	sd	$\n, 0(k1)
+	addiu	k1, 8
+	.endr
+
+	move	$25, k1
+	ld      k1, 216(k0)	// restore k1 for temp usage
+	move	k0, $25
+
+	// Store out k0, we can use $25 here because we just saved it
+	dmfc0	$25, COP0_DESAVE
+	sd	$25, 0(k0)
+	addiu	k0, 8
+
+	.irp	n, REGS1
+	sd	$\n, 0(k0)
+	addiu	k0, 8
+	.endr
+
+	loadaddr(sp, __cvmx_debug_stack_top, 3)
+	// Load the stack pointer as a pointer size.
+#ifdef _ABIN32
+	lw	sp,0(sp)
+#else
+	ld	sp,0(sp)
+#endif
+	jal	__cvmx_debug_handler_stage3
+	nop
+
+	loadaddr(k0, __cvmx_debug_save_regs_area, 8)
+
+	.irp	n, REGS0
+	ld	$\n, 0(k0)
+	addiu	k0, 8
+	.endr
+
+	// Restore k0 to COP0_DESAVE via k1
+	ld	k1, 0(k0)
+	addiu	k0, 8
+	dmtc0	k1, COP0_DESAVE
+
+	.irp	n, REGS1
+	ld	$\n, 0(k0)
+	addiu	k0, 8
+	.endr
+	
+	dmfc0	k0, COP0_DESAVE
+	// Flush the icache; by adding and removing SW breakpoints we change
+	// the instruction stream.
+	synci 	0($0)
+	deret
+	nop
+
+	.end	__cvmx_debug_handler_stage2
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-remote.c b/sys/contrib/octeon-sdk/cvmx-debug-remote.c
new file mode 100644
index 0000000..b0808eb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-debug-remote.c
@@ -0,0 +1,95 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-debug.h>
+
+#define cvmx_interrupt_in_isr 0
+
+#else
+#include "executive-config.h"
+#include "cvmx.h"
+#include "cvmx-debug.h"
+
+#ifndef __OCTEON_NEWLIB__
+extern int cvmx_interrupt_in_isr;
+#else
+#define cvmx_interrupt_in_isr 0
+#endif
+
+#endif
+
+
+static void cvmx_debug_remote_mem_wait_for_resume(volatile cvmx_debug_core_context_t *context, cvmx_debug_state_t state)
+{
+    //
+    // If we are stepping and not stepping into an interrupt and the debug
+    // exception happened in an interrupt, continue the execution.
+     //
+    if(!state.step_isr &&
+       (context->cop0.debug & 0x1) && /* Single stepping */
+       !(context->cop0.debug & 0x1e) && /* Did not hit a breakpoint */
+       ((context->cop0.status & 0x2) || cvmx_interrupt_in_isr))
+        return;
+
+    context->remote_controlled = 1;
+    CVMX_SYNCW;
+    while (context->remote_controlled)
+        ;
+    CVMX_SYNCW;
+}
+
+static void cvmx_debug_memory_change_core(int oldcore, int newcore)
+{
+  /* FIXME, this should change the core on the host side too. */
+}
+
+cvmx_debug_comm_t cvmx_debug_remote_comm =
+{
+  .init = NULL,
+  .install_break_handler = NULL,
+  .needs_proxy = 0,
+  .getpacket = NULL,
+  .putpacket = NULL,
+  .wait_for_resume = cvmx_debug_remote_mem_wait_for_resume,
+  .change_core = cvmx_debug_memory_change_core,
+};
diff --git a/sys/contrib/octeon-sdk/cvmx-debug-uart.c b/sys/contrib/octeon-sdk/cvmx-debug-uart.c
new file mode 100644
index 0000000..47ca34e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-debug-uart.c
@@ -0,0 +1,239 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-debug.h>
+#include <asm/octeon/cvmx-uart.h>
+#include <asm/octeon/octeon-boot-info.h>
+#include <asm/octeon/cvmx-spinlock.h>
+
+int cvmx_debug_uart = 1;
+
+#else
+#include <limits.h>
+#include "executive-config.h"
+#include "cvmx.h"
+#include "cvmx-debug.h"
+#include "cvmx-uart.h"
+#include "cvmx-spinlock.h"
+
+#ifndef __OCTEON_NEWLIB__
+#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+#else
+#include "octeon-boot-info.h"
+#endif
+
+#endif
+
+
+#ifdef __OCTEON_NEWLIB__
+#pragma weak cvmx_uart_enable_intr
+int cvmx_debug_uart = 1;
+#endif
+
+
+/* Default to second uart port for backward compatibility.  The default (if
+   -debug does not set the uart number) can now be overridden with
+   CVMX_DEBUG_COMM_UART_NUM. */
+#ifndef CVMX_DEBUG_COMM_UART_NUM
+# define CVMX_DEBUG_COMM_UART_NUM 1
+#endif
+
+static CVMX_SHARED cvmx_spinlock_t cvmx_debug_uart_lock;
+
+/**
+ * Interrupt handler for debugger Control-C interrupts.
+ *
+ * @param irq_number IRQ interrupt number
+ * @param registers  CPU registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+void cvmx_debug_uart_process_debug_interrupt(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    cvmx_uart_lsr_t lsrval;
+
+    /* Check for a Control-C interrupt from the debugger. This loop will eat
+        all input received on the uart */
+    lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
+    while (lsrval.s.dr)
+    {
+        int c = cvmx_read_csr(CVMX_MIO_UARTX_RBR(cvmx_debug_uart));
+        if (c == '\003')
+        {
+            register uint64_t tmp;
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+            fflush(stderr);
+            fflush(stdout);
+#endif
+            /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
+                set the MCD0 to be not masked by this core so we know
+                the signal is received by someone */
+            asm volatile (
+                "dmfc0 %0, $22\n"
+                "ori   %0, %0, 0x1110\n"
+                "dmtc0 %0, $22\n"
+                : "=r" (tmp));
+        }
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
+    }
+}
+
+
+static void cvmx_debug_uart_init(void)
+{
+    if (cvmx_debug_uart == -1)
+	cvmx_debug_uart = CVMX_DEBUG_COMM_UART_NUM;
+}
+
+static void cvmx_debug_uart_install_break_handler(void)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef __OCTEON_NEWLIB__
+    if (cvmx_uart_enable_intr)
+#endif
+        cvmx_uart_enable_intr(cvmx_debug_uart, cvmx_debug_uart_process_debug_interrupt);
+#endif
+}
+
+/* Get a packet from the UART, return 0 on failure and 1 on success. */
+
+static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
+{
+    while (1)
+    {
+	unsigned char checksum;
+        int timedout = 0;
+	size_t count;
+	char ch;
+
+        ch = cvmx_uart_read_byte_with_timeout(cvmx_debug_uart, &timedout, __SHRT_MAX__);
+
+        if (timedout)
+            return 0;
+
+        /* if this is not the start character, ignore it. */
+        if (ch != '$')
+            continue;
+
+        retry:
+        checksum = 0;
+        count = 0;
+
+        /* now, read until a # or end of buffer is found */
+        while (count < size)
+        {
+            ch = cvmx_uart_read_byte(cvmx_debug_uart);
+            if (ch == '$')
+                goto retry;
+            if (ch == '#')
+                break;
+            checksum = checksum + ch;
+            buffer[count] = ch;
+            count = count + 1;
+        }
+        buffer[count] = 0;
+
+        if (ch == '#')
+        {
+	    char csumchars[2];
+	    unsigned xmitcsum;
+	    int n;
+
+            csumchars[0] = cvmx_uart_read_byte(cvmx_debug_uart);
+            csumchars[1] = cvmx_uart_read_byte(cvmx_debug_uart);
+	    n = sscanf(csumchars, "%2x", &xmitcsum);
+	    if (n != 1)
+		return 1;
+
+            return checksum == xmitcsum;
+        }
+    }
+    return 0;
+}
+
+static int cvmx_debug_uart_putpacket(char *packet)
+{
+    size_t i;
+    unsigned char csum;
+    unsigned char *ptr = (unsigned char *) packet;
+    char csumstr[3];
+
+    for (csum = 0, i = 0; ptr[i]; i++)
+      csum += ptr[i];
+    sprintf(csumstr, "%02x", csum);
+
+    cvmx_spinlock_lock(&cvmx_debug_uart_lock);
+    cvmx_uart_write_byte(cvmx_debug_uart, '$');
+    cvmx_uart_write_string(cvmx_debug_uart, packet);
+    cvmx_uart_write_byte(cvmx_debug_uart, '#');
+    cvmx_uart_write_string(cvmx_debug_uart, csumstr);
+    cvmx_spinlock_unlock(&cvmx_debug_uart_lock);
+
+    return 0;
+}
+
+static void cvmx_debug_uart_change_core(int oldcore, int newcore)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    cvmx_ciu_intx0_t irq_control;
+
+    irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2));
+    irq_control.s.uart |= (1<<cvmx_debug_uart);
+    cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64);
+
+    /* Disable interrupts to this core since he is about to die */
+    irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2));
+    irq_control.s.uart &= ~(1<<cvmx_debug_uart);
+    cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
+#endif
+}
+
+cvmx_debug_comm_t cvmx_debug_uart_comm =
+{
+  .init = cvmx_debug_uart_init,
+  .install_break_handler = cvmx_debug_uart_install_break_handler,
+  .needs_proxy = 1,
+  .getpacket = cvmx_debug_uart_getpacket,
+  .putpacket = cvmx_debug_uart_putpacket,
+  .wait_for_resume = NULL,
+  .change_core = cvmx_debug_uart_change_core,
+};
diff --git a/sys/contrib/octeon-sdk/cvmx-debug.c b/sys/contrib/octeon-sdk/cvmx-debug.c
new file mode 100644
index 0000000..e615cbc
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-debug.c
@@ -0,0 +1,1436 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/*
+ * @file
+ *
+ * Interface to debug exception handler
+ *
+ * <hr>$Revision: 50060 $<hr>
+ */
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-debug.h>
+#include <asm/octeon/cvmx-core.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/octeon-boot-info.h>
+#else
+#include <stdint.h>
+#include "executive-config.h"
+#include "cvmx.h"
+#include "cvmx-debug.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-core.h"
+#include "cvmx-coremask.h"
+
+#ifndef __OCTEON_NEWLIB__
+#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+#else
+#include "octeon-boot-info.h"
+#endif
+
+#endif
+
+#ifdef CVMX_DEBUG_LOGGING
+# undef CVMX_DEBUG_LOGGING
+# define CVMX_DEBUG_LOGGING 1
+#else
+# define CVMX_DEBUG_LOGGING 0
+#endif
+
+#ifndef CVMX_DEBUG_ATTACH
+# define CVMX_DEBUG_ATTACH 1
+#endif
+
+#define CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_STATUS            (0xFFFFFFFFFF301000ull)
+#define CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS(num)      (0xFFFFFFFFFF301100ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF301108ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ASID(num)         (0xFFFFFFFFFF301110ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_CONTROL(num)      (0xFFFFFFFFFF301118ull + 0x100 * (num))
+
+#define CVMX_DEBUG_HW_DATA_BREAKPOINT_STATUS                   (0xFFFFFFFFFF302000ull)
+#define CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS(num)             (0xFFFFFFFFFF302100ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS_MASK(num)        (0xFFFFFFFFFF302108ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_DATA_BREAKPOINT_ASID(num)                (0xFFFFFFFFFF302110ull + 0x100 * (num))
+#define CVMX_DEBUG_HW_DATA_BREAKPOINT_CONTROL(num)             (0xFFFFFFFFFF302118ull + 0x100 * (num))
+
+#define ERET_INSN  0x42000018U      /* Hexcode for eret */
+#define ISR_DELAY_COUNTER     120000000       /* Could be tuned down */
+
+extern cvmx_debug_comm_t cvmx_debug_uart_comm;
+extern cvmx_debug_comm_t cvmx_debug_remote_comm;
+static const cvmx_debug_comm_t *cvmx_debug_comms[COMM_SIZE] = {&cvmx_debug_uart_comm, &cvmx_debug_remote_comm};
+
+
+
+static cvmx_debug_globals_t *cvmx_debug_globals;
+
+/**
+ * @file
+ *
+ */
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+uint64_t __cvmx_debug_save_regs_area[32];
+
+volatile uint64_t __cvmx_debug_mode_exception_ignore;
+volatile uint64_t __cvmx_debug_mode_exception_occured;
+
+static char cvmx_debug_stack[8*1024] __attribute ((aligned (16)));
+char *__cvmx_debug_stack_top = &cvmx_debug_stack[8*1024];
+
+#ifndef __OCTEON_NEWLIB__
+extern int cvmx_interrupt_in_isr;
+#else
+#define cvmx_interrupt_in_isr 0
+#endif
+
+#else
+uint64_t __cvmx_debug_save_regs_area_all[OCTEON_NUM_CORES][32];
+#define __cvmx_debug_save_regs_area __cvmx_debug_save_regs_area_all[cvmx_get_core_num()]
+
+volatile uint64_t __cvmx_debug_mode_exception_ignore_all[OCTEON_NUM_CORES];
+#define __cvmx_debug_mode_exception_ignore __cvmx_debug_mode_exception_ignore_all[cvmx_get_core_num()]
+volatile uint64_t __cvmx_debug_mode_exception_occured_all[OCTEON_NUM_CORES];
+#define __cvmx_debug_mode_exception_occured __cvmx_debug_mode_exception_occured_all[cvmx_get_core_num()]
+
+static char cvmx_debug_stack_all[OCTEON_NUM_CORES][8*1024] __attribute ((aligned (16)));
+char *__cvmx_debug_stack_top_all[OCTEON_NUM_CORES];
+
+#define cvmx_interrupt_in_isr 0
+
+#endif
+
+
+static inline uint32_t cvmx_debug_core_mask(void)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef __OCTEON_NEWLIB__
+  extern int __octeon_core_mask;
+  return __octeon_core_mask;
+#endif
+return cvmx_sysinfo_get()->core_mask;
+#else
+return octeon_get_boot_coremask ();
+#endif
+}
+
+static inline void cvmx_debug_update_state(cvmx_debug_state_t state)
+{
+    memcpy(cvmx_debug_globals->state, &state, sizeof(cvmx_debug_state_t));
+}
+
+static inline cvmx_debug_state_t cvmx_debug_get_state(void)
+{
+    cvmx_debug_state_t state;
+    memcpy(&state, cvmx_debug_globals->state, sizeof(cvmx_debug_state_t));
+    return state;
+}
+
+static void cvmx_debug_printf(char *format, ...) __attribute__((format(__printf__, 1, 2)));
+static void cvmx_debug_printf(char *format, ...)
+{
+    va_list ap;
+
+    if (!CVMX_DEBUG_LOGGING)
+        return;
+
+    va_start(ap, format);
+    cvmx_dvprintf(format, ap);
+    va_end(ap);
+}
+
+static inline int __cvmx_debug_in_focus(cvmx_debug_state_t state, unsigned core)
+{
+    return state.focus_core == core;
+}
+
+static void cvmx_debug_install_handler(unsigned core)
+{
+    extern void __cvmx_debug_handler_stage2(void);
+    int32_t *trampoline = CASTPTR(int32_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, BOOTLOADER_DEBUG_TRAMPOLINE_CORE));
+    trampoline += core;
+
+    *trampoline = (int32_t)(long)&__cvmx_debug_handler_stage2;
+
+    cvmx_debug_printf("Debug handled installed on core %d at %p\n", core, trampoline);
+}
+
+static int cvmx_debug_enabled(void)
+{
+    return cvmx_debug_booted() || CVMX_DEBUG_ATTACH;
+}
+
+static void cvmx_debug_init_globals(void)
+{
+    int toclear = 0;
+    uint64_t phys;
+    void *a;
+
+    if (cvmx_debug_globals)
+        return;
+
+    if (cvmx_get_core_num() != 0)
+    {
+        volatile size_t i;
+        /* Delay here just enough for the writing of the version. */
+        for(i = 0; i < sizeof(cvmx_debug_globals_t)/2 + 8; i++)
+          ;
+    }
+
+    a = cvmx_bootmem_alloc_named(sizeof(cvmx_debug_globals_t), 8, CVMX_DEBUG_GLOBALS_BLOCK_NAME);
+    if (a)
+    {
+       phys = cvmx_ptr_to_phys(a);
+       toclear = 1;
+    }
+    else
+    {
+        const cvmx_bootmem_named_block_desc_t *debug_globals_nblk;
+        debug_globals_nblk = cvmx_bootmem_find_named_block (CVMX_DEBUG_GLOBALS_BLOCK_NAME);
+        phys = debug_globals_nblk->base_addr;
+    }
+    cvmx_debug_globals = CASTPTR(cvmx_debug_globals_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, phys));
+    cvmx_debug_printf("Debug named block at %p\n", cvmx_debug_globals);
+    if (toclear)
+        cvmx_debug_printf("Debug named block cleared\n");
+
+    if (toclear)
+    {
+        memset (cvmx_debug_globals, 0, sizeof(cvmx_debug_globals_t));
+        cvmx_debug_globals->version = CVMX_DEBUG_GLOBALS_VERSION;
+        cvmx_debug_globals->tlb_entries = cvmx_core_get_tlb_entries();
+    }
+    else
+    {
+        volatile size_t i;
+        /* Delay here just enough for the writing of the version. */
+        for(i = 0; i < sizeof(cvmx_debug_globals_t) + 8; i++)
+          ;
+    }
+}
+
+
+static void cvmx_debug_globals_check_version(void)
+{
+    if (cvmx_debug_globals->version != CVMX_DEBUG_GLOBALS_VERSION)
+    {
+        cvmx_dprintf("Wrong version on the globals struct spinining; expected %d, got:  %d.\n", (int)CVMX_DEBUG_GLOBALS_VERSION, (int)(cvmx_debug_globals->version));
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        panic("Wrong version.\n");
+#endif
+        while (1)
+            ;
+    }
+}
+
+static inline volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void);
+static inline void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context);
+
+void cvmx_debug_init(void)
+{
+    cvmx_debug_state_t state;
+    int core;
+    const cvmx_debug_comm_t *comm;
+    cvmx_spinlock_t *lock;
+    unsigned int coremask = cvmx_debug_core_mask();
+
+    if (!cvmx_debug_enabled())
+        return;
+
+    cvmx_debug_init_globals();
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    // Put a barrier until all cores have got to this point.
+    cvmx_coremask_barrier_sync(coremask);
+#endif
+    cvmx_debug_globals_check_version();
+
+
+    comm = cvmx_debug_comms[cvmx_debug_globals->comm_type];
+    lock = &cvmx_debug_globals->lock;
+
+    core = cvmx_get_core_num();
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    /*  Install the debugger handler on the cores. */
+    {
+        int core1 = 0;
+        for (core1 = 0; core1 < OCTEON_NUM_CORES; core1++)
+        {
+            if ((1<<core1) & coremask)
+                cvmx_debug_install_handler(core1);
+        }
+    }
+#else
+    cvmx_debug_install_handler(core);
+#endif
+
+    if (comm->init)
+        comm->init();
+
+    {
+        cvmx_spinlock_lock(lock);
+        state = cvmx_debug_get_state();
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        state.known_cores |= coremask;
+        state.core_finished &= ~coremask;
+#else
+        state.known_cores |= (1 << core);
+        state.core_finished &= ~(1 << core);
+#endif
+        cvmx_debug_update_state(state);
+        cvmx_spinlock_unlock(lock);
+    }
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    // Put a barrier until all cores have got to this point.
+    cvmx_coremask_barrier_sync(coremask);
+
+    if (cvmx_coremask_first_core(coremask))
+#endif
+    {
+        cvmx_debug_printf("cvmx_debug_init core: %d\n", core);
+        state = cvmx_debug_get_state();
+        state.focus_core = core;
+        state.active_cores = state.known_cores;
+        state.focus_switch = 1;
+        state.step_isr = 1;
+        cvmx_debug_printf("Known cores at init: 0x%x\n", (int)state.known_cores);
+        cvmx_debug_update_state(state);
+
+        /* Initialize __cvmx_debug_stack_top_all. */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        {
+            int i;
+            for (i = 0; i < OCTEON_NUM_CORES; i++)
+                __cvmx_debug_stack_top_all[i] = &cvmx_debug_stack_all[i][8*1024];
+        }
+#endif
+        cvmx_debug_globals->init_complete = 1;
+        CVMX_SYNCW;
+    }
+    while (!cvmx_debug_globals->init_complete)
+    {
+        /* Spin waiting for init to complete */
+    }
+
+    if (cvmx_debug_booted())
+        cvmx_debug_trigger_exception();
+
+    /*  Install the break handler after might tripper the debugger exception. */
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    if (cvmx_coremask_first_core(coremask))
+#endif
+    {
+        if (comm->install_break_handler)
+            comm->install_break_handler();
+    }
+}
+
+static int cvmx_debug_putpacket_noformat(char *packet);
+
+static __attribute__ ((format (printf, 1, 2))) int cvmx_debug_putpacket(char *format, ...)
+{
+    va_list ap;
+    size_t n;
+    char packet[CVMX_DEBUG_MAX_RESPONSE_SIZE];
+
+    if (cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket == NULL)
+        return 0;
+
+    va_start(ap, format);
+    n = vsnprintf(packet, sizeof(packet), format, ap);
+    va_end(ap);
+
+    if (n >= sizeof(packet))
+    {
+        cvmx_debug_printf("packet truncated (needed %d bytes): %s\n", (int)n, packet);
+        return 0;
+    }
+    return cvmx_debug_putpacket_noformat(packet);
+}
+
+static int cvmx_debug_putpacket_noformat(char *packet)
+{
+    if (cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket == NULL)
+        return 0;
+    cvmx_debug_printf("Reply: %s\n", packet);
+    return cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket(packet);
+}
+
+static int cvmx_debug_active_core(cvmx_debug_state_t state, int core)
+{
+    return state.active_cores & (1 << core);
+}
+
+static volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void)
+{
+    return &cvmx_debug_globals->contextes[cvmx_get_core_num()];
+}
+
+static volatile uint64_t *cvmx_debug_regnum_to_context_ref(int regnum, volatile cvmx_debug_core_context_t *context)
+{
+    /* Must be kept in sync with mips_octeon_reg_names in gdb/mips-tdep.c. */
+    if (regnum < 32)
+        return &context->regs[regnum];
+    switch (regnum)
+    {
+        case 32: return &context->cop0.status;
+        case 33: return &context->lo;
+        case 34: return &context->hi;
+        case 35: return &context->cop0.badvaddr;
+        case 36: return &context->cop0.cause;
+        case 37: return &context->cop0.depc;
+        default: return NULL;
+    }
+}
+
+static int cvmx_debug_probe_load(unsigned char *ptr, unsigned char *result)
+{
+    volatile unsigned char *p = ptr;
+    int ok;
+    unsigned char tem;
+
+    {
+        __cvmx_debug_mode_exception_ignore = 1;
+        __cvmx_debug_mode_exception_occured = 0;
+        /* We don't handle debug-mode exceptions in delay slots.  Avoid them.  */
+        asm volatile (".set push		\n\t"
+                      ".set noreorder	\n\t"
+                      "nop			\n\t"
+                      "lbu %0, %1		\n\t"
+                      "nop			\n\t"
+                      ".set pop" : "=r"(tem) : "m"(*p));
+        ok = __cvmx_debug_mode_exception_occured == 0;
+        __cvmx_debug_mode_exception_ignore = 0;
+        __cvmx_debug_mode_exception_occured = 0;
+	*result = tem;
+    }
+    return ok;
+}
+
+static int cvmx_debug_probe_store(unsigned char *ptr)
+{
+    volatile unsigned char *p = ptr;
+    int ok;
+
+    __cvmx_debug_mode_exception_ignore = 1;
+    __cvmx_debug_mode_exception_occured = 0;
+    /* We don't handle debug-mode exceptions in delay slots.  Avoid them.  */
+    asm volatile (".set push		\n\t"
+                  ".set noreorder	\n\t"
+                  "nop			\n\t"
+                  "sb $0, %0		\n\t"
+                  "nop			\n\t"
+                  ".set pop" : "=m"(*p));
+    ok = __cvmx_debug_mode_exception_occured == 0;
+
+    __cvmx_debug_mode_exception_ignore = 0;
+    __cvmx_debug_mode_exception_occured = 0;
+    return ok;
+}
+
+/* Put the hex value of t into str. */
+static void strhex(char *str, unsigned char t)
+{
+  char a[] = "0123456789ABCDEF";
+  str[0] = a[(t>>4)];
+  str[1] = a[t&0xF];
+  str[2] = 0;
+}
+
+/**
+  * Initialize the performance counter control registers.
+  *
+  */
+static void cvmx_debug_set_perf_control_reg (int perf_event, int perf_counter)
+{
+    volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+    cvmx_core_perf_control_t control;
+
+    control.u32 = 0;
+    control.s.u = 1;
+    control.s.s = 1;
+    control.s.k = 1;
+    control.s.ex = 1;
+    control.s.w = 1;
+    control.s.m = 1 - perf_counter;
+    control.s.event = perf_event;
+
+    context->cop0.perfctrl[perf_counter] = control.u32;
+}
+
+static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
+{
+    const char *buf = packet;
+    cvmx_debug_command_t result = COMMAND_NOP;
+    cvmx_debug_state_t state = cvmx_debug_get_state();
+
+    /* A one letter command code represents what to do.  */
+    switch (*buf++)
+    {
+        case '?':   /* What protocol do I speak? */
+            cvmx_debug_putpacket_noformat("S0A");
+            break;
+
+        case '\003':   /* Control-C */
+            cvmx_debug_putpacket_noformat("T9");
+            break;
+
+        case 'F':   /* Change the focus core */
+        {
+            int core;
+            sscanf(buf, "%x", &core);
+
+            /* Only cores in the exception handler may become the focus.
+            If a core not in the exception handler got focus the
+            debugger would hang since nobody would talk to it.  */
+            if (state.handler_cores & (1 << core))
+            {
+                /* Focus change reply must be sent before the focus
+                changes. Otherwise the new focus core will eat our ACK
+                from the debugger.  */
+                cvmx_debug_putpacket("F%02x", core);
+                cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core(state.focus_core, core);
+                state.focus_core = core;
+                cvmx_debug_update_state(state);
+                break;
+            }
+            else
+                cvmx_debug_putpacket_noformat("!Core is not in the exception handler. Focus not changed.");
+        /* Nothing changed, so we send back the old value */
+        }
+        /* fall through */
+        case 'f':   /* Get the focus core */
+            cvmx_debug_putpacket("F%02x", (unsigned)state.focus_core);
+            break;
+
+        case 'J': /* Set the flag for skip-over-isr in Single-Stepping mode */
+        {
+            if (*buf == '1')
+                state.step_isr = 1;   /* Step in ISR */
+            else
+                state.step_isr = 0;   /* Step over ISR */
+            cvmx_debug_update_state(state);
+        }
+        /* Fall through. The reply to the set step-isr command is the
+           same as the get step-isr command */
+
+        case 'j':   /* Reply with step_isr status  */
+            cvmx_debug_putpacket("J%x", (unsigned)state.step_isr);
+            break;
+
+
+        case 'I':   /* Set the active cores */
+        {
+            long long active_cores;
+            sscanf(buf, "%llx", &active_cores);
+            /* Limit the active mask to the known to exist cores */
+            state.active_cores = active_cores & state.known_cores;
+
+            /* Lazy user hack to have 0 be all cores */
+            if (state.active_cores == 0)
+                state.active_cores = state.known_cores;
+
+            /* The focus core must be in the active_cores mask */
+            if ((state.active_cores & (1 << state.focus_core)) == 0)
+            {
+                cvmx_debug_putpacket_noformat("!Focus core was added to the masked.");
+                state.active_cores |= 1 << state.focus_core;
+            }
+
+            cvmx_debug_update_state(state);
+        }
+        /* Fall through. The reply to the set active cores command is the
+           same as the get active cores command */
+
+        case 'i':   /* Get the active cores */
+            cvmx_debug_putpacket("I%llx", (long long) state.active_cores);
+            break;
+
+        case 'A':   /* Setting the step mode all or one */
+        {
+            if (*buf == '1')
+                state.step_all = 1;   /* A step or continue will start all cores */
+            else
+                state.step_all = 0;   /* A step or continue only affects the focus core */
+            cvmx_debug_update_state(state);
+        }
+        /* Fall through. The reply to the set step-all command is the
+           same as the get step-all command */
+
+        case 'a':   /* Getting the current step mode */
+            cvmx_debug_putpacket("A%x", (unsigned)state.step_all);
+            break;
+
+        case 'g':   /* read a register from global place. */
+        {
+            volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+            int regno;
+            volatile uint64_t *reg;
+
+            /* Get the register number to read */
+            sscanf(buf, "%x", &regno);
+
+            reg = cvmx_debug_regnum_to_context_ref(regno, context);
+            if (!reg)
+                cvmx_debug_printf("Register #%d is not valid\n", regno);
+            cvmx_debug_putpacket("%llx", (unsigned long long) *reg);
+        }
+        break;
+
+        case 'G':   /* set the value of a register. */
+        {
+            volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+            int regno;
+            volatile uint64_t *reg;
+            long long value;
+
+            /* Get the register number to read */
+            if (sscanf(buf, "%x,%llx", &regno, &value) != 2)
+            {
+                cvmx_debug_printf("G packet corrupt: %s\n", buf);
+                goto error_packet;
+            }
+
+            reg = cvmx_debug_regnum_to_context_ref(regno, context);
+            if (!reg)
+            {
+                cvmx_debug_printf("Register #%d is not valid\n", regno);
+                goto error_packet;
+            }
+            *reg = value;
+        }
+        break;
+
+        case 'm':   /* Memory read. mAA..AA,LLLL  Read LLLL bytes at address AA..AA */
+        {
+            long long addr, i, length;
+            unsigned char *ptr;
+            char *reply;
+
+            if (sscanf(buf, "%llx,%llx", &addr, &length) != 2)
+            {
+                cvmx_debug_printf("m packet corrupt: %s\n", buf);
+                goto error_packet;
+            }
+            if (length >= 1024)
+            {
+                cvmx_debug_printf("m packet length out of range: %lld\n", length);
+                goto error_packet;
+            }
+
+            reply = __builtin_alloca(length * 2 + 1);
+            ptr = (unsigned char *)(long)addr;
+            for (i = 0; i < length; i++)
+            {
+                /* Probe memory.  If not accessible fail.   */
+                unsigned char t;
+                if (!cvmx_debug_probe_load(&ptr[i], &t))
+                  goto error_packet;
+                strhex(&reply[i * 2], t);
+            }
+            cvmx_debug_putpacket_noformat(reply);
+        }
+        break;
+
+        case 'M':   /* Memory write. MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
+        {
+            long long addr, i, length;
+            unsigned char *ptr;
+            char value[1024];
+
+            if (sscanf(buf, "%llx,%llx:%1024s", &addr, &length, value) != 3)
+            {
+                cvmx_debug_printf("M packet corrupt: %s\n", buf);
+                goto error_packet;
+            }
+            
+            ptr = (unsigned char *)(long)addr;
+            for (i = 0; i < length; i++)
+            {
+                int c;
+                int n;
+                char tempstr[3] = {0, 0, 0};
+                memcpy (tempstr, &value[i * 2], 2);
+            
+                n = sscanf(tempstr, "%2x", &c);
+                if (n != 1)
+                {
+                    cvmx_debug_printf("M packet corrupt: %s\n", &value[i * 2]);
+                    goto error_packet;
+                }
+                /* Probe memory.  If not accessible fail.   */
+                if (!cvmx_debug_probe_store(&ptr[i]))
+                {
+                    cvmx_debug_printf("M cannot write: %p\n", &ptr[i]);
+                    goto error_packet;
+                }
+                ptr[i] = c;
+            }
+            cvmx_debug_putpacket_noformat("+");
+        }
+        break;
+
+        case 'e':  /* Set/get performance counter events. e[1234]XX..X: [01]
+                      is the performance counter to set X is the performance
+                      event.  [34] is to get the same thing.  */
+        {
+            int perf_event = 0;
+            int counter, encoded_counter;
+            volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+            sscanf(buf, "%1d%x", &encoded_counter, &perf_event);
+
+            switch (encoded_counter)
+            {
+                case 1: /* Set performance counter0 event. */
+                case 2: /* Set performance counter1 event. */
+
+                counter = encoded_counter - 1;
+                context->cop0.perfval[counter] = 0;
+                cvmx_debug_set_perf_control_reg(perf_event, counter);
+                break;
+
+                case 3: /* Get performance counter0 event. */
+                case 4: /* Get performance counter1 event. */
+                {
+                    cvmx_core_perf_control_t c;
+                    counter = encoded_counter - 3;
+                    /* Pass performance counter0 event and counter to
+                       the debugger.  */
+                    c.u32 = context->cop0.perfctrl[counter];
+                    cvmx_debug_putpacket("%llx,%llx", (long long) context->cop0.perfval[counter], (long long) c.s.event);
+                }
+                break;
+            }
+        }
+        break;
+
+#if 0
+        case 't': /* Return the trace buffer read data register contents. */
+        {
+            uint64_t tra_data;
+            uint64_t tra_ctl;
+            char tmp[64];
+
+            /* If trace buffer is disabled no trace data information is available. */
+            if ((tra_ctl & 0x1) == 0)
+            {
+                cvmx_debug_putpacket_noformat("!Trace buffer not enabled\n");
+                cvmx_debug_putpacket_noformat("t");
+            }
+            else
+            {
+                cvmx_debug_putpacket_noformat("!Trace buffer is enabled\n");
+                tra_data = cvmx_read_csr(OCTEON_TRA_READ_DATA);
+                mem2hex (&tra_data, tmp, 8);
+                strcpy (debug_output_buffer, "t");
+                strcat (debug_output_buffer, tmp);
+                cvmx_debug_putpacket_noformat(debug_output_buffer);
+            }
+        }
+        break;
+#endif
+
+        case 'Z': /* Insert hardware breakpoint: Z[di]NN..N,AA.A, [di] data or
+                     instruction, NN..Nth at address AA..A */
+        {
+            enum type
+            {
+                WP_LOAD = 1,
+                WP_STORE = 2,
+                WP_ACCESS = 3
+            };
+
+            int num, size;
+            long long addr;
+            enum type type;
+            char bp_type;
+            const int BE = 1, TE = 4;
+            int n;
+            volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+
+            n = sscanf(buf, "%c%x,%llx,%x,%x", &bp_type, &num, &addr, &size, &type);
+            switch (bp_type)
+            {
+                case 'i':	// Instruction hardware breakpoint
+                    if (n != 3 || num > 4)
+                    {
+                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        goto error_packet;
+                    }
+
+                    context->hw_ibp.address[num] = addr;
+                    context->hw_ibp.address_mask[num] = 0;
+                    context->hw_ibp.asid[num] = 0;
+                    context->hw_ibp.control[num] = BE | TE;
+                    break;
+
+                case 'd':	// Data hardware breakpoint
+                {
+                    uint64_t dbc = 0xff0 | BE | TE;
+                    uint64_t dbm;
+                    if (n != 5 || num > 4)
+                    {
+                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        goto error_packet;
+                    }
+
+                    /* Set DBC[BE,TE,BLM]. */
+                    context->hw_dbp.address[num] = addr;
+                    context->hw_dbp.asid[num] = 0;
+
+                    dbc |= type == WP_STORE ? 0x1000 : type == WP_LOAD ? 0x2000 : 0;
+                    /* Mask the bits depending on the size for
+                    debugger to stop while accessing parts of the
+                    memory location.  */
+                    dbm = (size == 8) ? 0x7 : ((size == 4) ? 3
+                                        : (size == 2) ? 1 : 0);
+                    context->hw_dbp.address_mask[num] = dbm;
+                    context->hw_dbp.control[num] = dbc;
+                    break;
+                }
+                default:
+                    cvmx_debug_printf("z packet corrupt: %s\n", buf);
+                    goto error_packet;
+            }
+        }
+        break;
+
+        case 'z': /* Remove hardware breakpoint: z[di]NN..N remove NN..Nth
+breakpoint.  */
+        {
+            int num;
+            char bp_type;
+            volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
+
+            if (sscanf(buf, "%c%x", &bp_type, &num) != 2 || num > 4)
+            {
+                cvmx_debug_printf("z packet corrupt: %s\n", buf);
+                goto error_packet;
+            }
+
+            switch (bp_type)
+            {
+                case 'i':	// Instruction hardware breakpoint
+                    context->hw_ibp.address[num] = 0;
+                    context->hw_ibp.address_mask[num] = 0;
+                    context->hw_ibp.asid[num] = 0;
+                    context->hw_ibp.control[num] = 0;
+                    break;
+                case 'd':	// Data hardware breakpoint
+                    context->hw_dbp.address[num] = 0;
+                    context->hw_dbp.address_mask[num] = 0;
+                    context->hw_dbp.asid[num] = 0;
+                    context->hw_dbp.control[num] = 0;
+                    break;
+                default:
+                    cvmx_debug_printf("z packet corrupt: %s\n", buf);
+                    goto error_packet;
+            }
+        }
+        break;
+
+        case 's':   /* Single step. sAA..AA Step one instruction from AA..AA (optional) */
+            result = COMMAND_STEP;
+            break;
+
+        case 'c':   /* Continue. cAA..AA Continue at address AA..AA (optional) */
+            result = COMMAND_CONTINUE;
+            break;
+
+        case '+':   /* Don't know. I think it is a communications sync */
+            /* Ignoring this command */
+            break;
+
+        default:
+            cvmx_debug_printf("Unknown debug command: %s\n", buf - 1);
+error_packet:
+            cvmx_debug_putpacket_noformat("-");
+            break;
+    }
+
+    return result;
+}
+
+static cvmx_debug_command_t cvmx_debug_process_next_packet(void)
+{
+    char packet[CVMX_DEBUG_MAX_REQUEST_SIZE];
+    if (cvmx_debug_comms[cvmx_debug_globals->comm_type]->getpacket(packet, CVMX_DEBUG_MAX_REQUEST_SIZE))
+    {
+        cvmx_debug_printf("Request: %s\n", packet);
+        return cvmx_debug_process_packet(packet);
+    }
+    return COMMAND_NOP;
+}
+
+/* If a core isn't in the active core mask we need to start him up again. We
+   can only do this if the core didn't hit a breakpoint or single step. If the
+   core hit CVMX_CIU_DINT interrupt (generally happens when while executing
+   _exit() at the end of the program). Remove the core from known cores so
+   that when the cores in active core mask are done executing the program, the
+   focus will not be transfered to this core.  */
+
+static int cvmx_debug_stop_core(cvmx_debug_state_t state, unsigned core, cvmx_debug_register_t *debug_reg, int proxy)
+{
+    if (!cvmx_debug_active_core(state, core) && !debug_reg->s.dbp && !debug_reg->s.dss && (debug_reg->s.dint != 1))
+    {
+        debug_reg->s.sst = 0;
+        cvmx_debug_printf("Core #%d not in active cores, continuing.\n", core);
+        return 0;
+    }
+    if ((state.core_finished & (1<<core)) && proxy)
+      return 0;
+    return 1;
+}
+
+/* check to see if current exc is single-stepped and  that no other exc
+   was also simultaneously noticed. */
+static int cvmx_debug_single_step_exc(cvmx_debug_register_t *debug_reg)
+{
+    if (debug_reg->s.dss && !debug_reg->s.dib && !debug_reg->s.dbp && !debug_reg->s.ddbs && !debug_reg->s.ddbl)
+        return 1;
+    return 0;
+}
+
+static void cvmx_debug_set_focus_core(cvmx_debug_state_t *state, int core)
+{
+    if (state->ever_been_in_debug)
+        cvmx_debug_putpacket("!Core %2x taking focus.", core);
+    cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core (state->focus_core, core);
+    state->focus_core = core;
+}
+
+static void cvmx_debug_may_elect_as_focus_core(cvmx_debug_state_t *state, int core, cvmx_debug_register_t *debug_reg)
+{
+    /* If another core has already elected itself as the focus core, we're late.  */
+    if (state->handler_cores & (1 << state->focus_core))
+        return;
+
+    /* If we hit a breakpoint, elect ourselves.  */
+    if (debug_reg->s.dib || debug_reg->s.dbp || debug_reg->s.ddbs || debug_reg->s.ddbl)
+        cvmx_debug_set_focus_core(state, core);
+
+    /* It is possible the focus core has completed processing and exited the
+       program. When this happens the focus core will not be in
+       known_cores. If this is the case we need to elect a new focus. */
+    if ((state->known_cores & (1 << state->focus_core)) == 0)
+        cvmx_debug_set_focus_core(state, core);
+}
+
+static void cvmx_debug_send_stop_reason(cvmx_debug_register_t *debug_reg, volatile cvmx_debug_core_context_t *context)
+{
+    /* Handle Debug Data Breakpoint Store/Load Exception. */
+    if (debug_reg->s.ddbs || debug_reg->s.ddbl)
+        cvmx_debug_putpacket("T8:%x", (int) context->hw_dbp.status);
+    else
+        cvmx_debug_putpacket_noformat("T9");
+}
+
+
+static void cvmx_debug_clear_status(volatile cvmx_debug_core_context_t *context)
+{
+    /* SW needs to clear the BreakStatus bits after a watchpoint is hit or on
+       reset.  */
+    context->hw_dbp.status &= ~0x3fff;
+
+    /* Clear MCD0, which is write-1-to-clear.  */
+    context->cop0.multicoredebug |= 1;
+}
+
+static void cvmx_debug_sync_up_cores(void)
+{
+    cvmx_debug_state_t state;
+    do {
+        state = cvmx_debug_get_state();
+    } while (state.step_all && state.handler_cores != 0);
+}
+
+/* Delay the focus core a little if it is likely another core needs to steal
+   focus. Once we enter the main loop focus can't be stolen */
+static void cvmx_debug_delay_focus_core(cvmx_debug_state_t state, unsigned core, cvmx_debug_register_t *debug_reg)
+{
+    volatile int i;
+    if (debug_reg->s.dss || debug_reg->s.dbp || core != state.focus_core)
+        return;
+    for (i = 0; i < 24000; i++)
+    {
+        asm volatile (".set push		\n\t"
+                      ".set noreorder		\n\t"
+                      "nop			\n\t"
+                      "nop			\n\t"
+                      "nop			\n\t"
+                      "nop			\n\t"
+                      ".set pop");
+        /* Spin giving the breakpoint core time to steal focus */
+    }
+
+}
+
+/* If this core was single-stepping in a group,
+   && it was not the last focus-core,
+   && last focus-core happens to be inside an ISR, blocking focus-switch
+   then burn some cycles, to avoid unnecessary focus toggles. */
+static void cvmx_debug_delay_isr_core(unsigned core, uint32_t depc, int single_stepped_exc_only,
+                                      cvmx_debug_state_t state)
+{
+    volatile uint64_t i;
+    if(!single_stepped_exc_only || state.step_isr || core == state.focus_core || state.focus_switch)
+        return;
+
+    cvmx_debug_printf ("Core #%u spinning for focus at 0x%x\n", core, (unsigned int)depc);
+
+    for(i = ISR_DELAY_COUNTER; i > 0 ; i--)
+    {
+       state = cvmx_debug_get_state();
+       /* Spin giving the focus core time to service ISR */
+       /* But cut short the loop, if we can.  Shrink down i, only once. */
+       if (i > 600000 && state.focus_switch)
+           i = 500000;
+    }
+    
+}
+
+static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile cvmx_debug_core_context_t *context)
+{
+    unsigned core = cvmx_get_core_num();
+    cvmx_debug_state_t state = cvmx_debug_get_state();
+    cvmx_debug_command_t command = COMMAND_NOP;
+    int single_stepped_exc_only = cvmx_debug_single_step_exc (debug_reg);
+
+    /* All cores should respect the focus core if it has to
+       stop focus switching while servicing an interrupt.
+       If the system is single-stepping, then the following
+       code path is valid. If the current core tripped on a
+       break-point or some other error while going through
+       an ISR, then we shouldn't be returning unconditionally.
+       In that case (non-single-step case) we must enter
+       the debugger exception stub fully. */
+    if (!state.step_isr && (cvmx_interrupt_in_isr || (context->cop0.status & 0x2ULL)) && single_stepped_exc_only)
+    {
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        state = cvmx_debug_get_state();
+        /* If this is the focus core, switch off focus switching
+           till ISR_DELAY_COUNTER. This will let focus core
+           keep the focus until the ISR is completed. */
+        if(state.focus_switch && core == state.focus_core)
+        {
+            cvmx_debug_printf ("Core #%u stopped focus stealing at 0x%llx\n", core, (unsigned long long)context->cop0.depc);
+            state.focus_switch = 0;
+        }
+        /* Alow other cores to steal focus.
+           Focus core has completed ISR. */
+        if (*(uint32_t*)((__SIZE_TYPE__)context->cop0.depc) == ERET_INSN && core == state.focus_core)
+        {
+            cvmx_debug_printf ("Core #%u resumed focus stealing at 0x%llx\n", core, (unsigned long long)context->cop0.depc);
+            state.focus_switch = 1;
+        }
+        cvmx_debug_update_state(state);
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+        cvmx_debug_printf ("Core #%u resumed skipping isr.\n", core);
+        return 0;
+    }
+
+    /* Delay the focus core a little if it is likely another core needs to
+       steal focus. Once we enter the main loop focus can't be stolen */
+    cvmx_debug_delay_focus_core(state, core, debug_reg);
+
+    cvmx_debug_delay_isr_core (core, context->cop0.depc, single_stepped_exc_only, state);
+
+    /* The following section of code does two critical things. First, it
+       populates the handler_cores bitmask of all cores in the exception
+       handler. Only one core at a time can update this field. Second it
+       changes the focus core if needed. */
+    {
+        cvmx_debug_printf("Core #%d stopped\n", core);
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        state = cvmx_debug_get_state();
+
+        state.handler_cores |= (1 << core);
+        cvmx_debug_may_elect_as_focus_core(&state, core, debug_reg);
+
+/* Push all updates before exiting the critical section */
+        state.focus_switch = 1;
+        cvmx_debug_update_state(state);
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+    }
+    if (__cvmx_debug_in_focus(state, core))
+        cvmx_debug_send_stop_reason(debug_reg, context);
+
+    do {
+        state = cvmx_debug_get_state();
+        /* Note the focus core can change in this loop. */
+        if (__cvmx_debug_in_focus(state, core))
+        {
+            command = cvmx_debug_process_next_packet();
+            state = cvmx_debug_get_state();
+            /* When resuming let the other cores resume as well with
+               step-all.  */
+            if (command != COMMAND_NOP && state.step_all)
+            {
+                state.command = command;
+                cvmx_debug_update_state(state);
+            }
+        }
+        /* When steping all cores, update the non focus core's command too. */
+        else if (state.step_all)
+            command = state.command;
+
+        /* If we did not get a command and the communication changed return,
+           we are changing the communications. */
+        if (command == COMMAND_NOP && cvmx_debug_globals->comm_changed)
+        {
+            /* FIXME, this should a sync not based on cvmx_coremask_barrier_sync.  */
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+            /* Sync up.  */
+            cvmx_coremask_barrier_sync(state.handler_cores);
+#endif
+            return 1;
+        }
+    } while (command == COMMAND_NOP);
+
+    debug_reg->s.sst = command == COMMAND_STEP;
+    cvmx_debug_printf("Core #%d running\n", core);
+
+    {
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        state = cvmx_debug_get_state();
+        state.handler_cores ^= (1 << core);
+        cvmx_debug_update_state(state);
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+    }
+
+    cvmx_debug_sync_up_cores();
+    /* Now that all cores are out, reset the command.  */
+    if (__cvmx_debug_in_focus(state, core))
+    {
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        state = cvmx_debug_get_state();
+        state.command = COMMAND_NOP;
+        cvmx_debug_update_state(state);
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+    }
+    return 0;
+}
+
+static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context)
+{
+    unsigned i;
+    memcpy((char *) context->regs, __cvmx_debug_save_regs_area, sizeof(context->regs));
+    asm("mflo %0" : "=r"(context->lo));
+    asm("mfhi %0" : "=r"(context->hi));
+    CVMX_MF_COP0(context->cop0.index, COP0_INDEX);
+    CVMX_MF_COP0(context->cop0.entrylo[0], COP0_ENTRYLO0);
+    CVMX_MF_COP0(context->cop0.entrylo[1], COP0_ENTRYLO1);
+    CVMX_MF_COP0(context->cop0.entryhi, COP0_ENTRYHI);
+    CVMX_MF_COP0(context->cop0.pagemask, COP0_PAGEMASK);
+    CVMX_MF_COP0(context->cop0.status, COP0_STATUS);
+    CVMX_MF_COP0(context->cop0.cause, COP0_CAUSE);
+    CVMX_MF_COP0(context->cop0.debug, COP0_DEBUG);
+    CVMX_MF_COP0(context->cop0.multicoredebug, COP0_MULTICOREDEBUG);
+    CVMX_MF_COP0(context->cop0.perfval[0], COP0_PERFVALUE0);
+    CVMX_MF_COP0(context->cop0.perfval[1], COP0_PERFVALUE1);
+    CVMX_MF_COP0(context->cop0.perfctrl[0], COP0_PERFCONTROL0);
+    CVMX_MF_COP0(context->cop0.perfctrl[1], COP0_PERFCONTROL1);
+    /* Save DEPC and DESAVE since debug-mode exceptions (see
+       debug_probe_{load,store}) can clobber these.  */
+    CVMX_MF_COP0(context->cop0.depc, COP0_DEPC);
+    CVMX_MF_COP0(context->cop0.desave, COP0_DESAVE);
+
+    context->hw_ibp.status = cvmx_read_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_STATUS);
+    for (i = 0; i < 4; i++)
+    {
+        context->hw_ibp.address[i] = cvmx_read_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS(i));
+        context->hw_ibp.address_mask[i] = cvmx_read_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(i));
+        context->hw_ibp.asid[i] = cvmx_read_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ASID(i));
+        context->hw_ibp.control[i] = cvmx_read_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_CONTROL(i));
+    }
+
+    context->hw_dbp.status = cvmx_read_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_STATUS);
+    for (i = 0; i < 4; i++)
+    {
+        context->hw_dbp.address[i] = cvmx_read_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS(i));
+        context->hw_dbp.address_mask[i] = cvmx_read_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS_MASK(i));
+        context->hw_dbp.asid[i] = cvmx_read_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ASID(i));
+        context->hw_dbp.control[i] = cvmx_read_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_CONTROL(i));
+    }
+
+    for (i = 0; i < cvmx_debug_globals->tlb_entries; i++)
+    {
+        CVMX_MT_COP0(i, COP0_INDEX);
+        asm volatile ("tlbr");
+        CVMX_MF_COP0(context->tlbs[i].entrylo[0], COP0_ENTRYLO0);
+        CVMX_MF_COP0(context->tlbs[i].entrylo[1], COP0_ENTRYLO1);
+        CVMX_MF_COP0(context->tlbs[i].entryhi, COP0_ENTRYHI);
+        CVMX_MF_COP0(context->tlbs[i].pagemask, COP0_PAGEMASK);
+    }
+    CVMX_SYNCW;
+}
+
+static void cvmx_debug_restore_core_context(volatile cvmx_debug_core_context_t *context)
+{
+    int i;
+    memcpy(__cvmx_debug_save_regs_area, (char *) context->regs, sizeof(context->regs));
+    asm("mtlo %0" :: "r"(context->lo));
+    asm("mthi %0" :: "r"(context->hi));
+    /* We don't change the TLB so no need to restore it.  */
+    cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_STATUS, context->hw_dbp.status);
+    for (i = 0; i < 4; i++)
+    {
+        cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS(i), context->hw_dbp.address[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ADDRESS_MASK(i), context->hw_dbp.address_mask[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_ASID(i), context->hw_dbp.asid[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_CONTROL(i), context->hw_dbp.control[i]);
+    }
+    cvmx_write_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_STATUS, context->hw_ibp.status);
+    for (i = 0; i < 4; i++)
+    {
+        cvmx_write_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS(i), context->hw_ibp.address[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(i), context->hw_ibp.address_mask[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_ASID(i), context->hw_ibp.asid[i]);
+        cvmx_write_csr(CVMX_DEBUG_HW_INSTRUCTION_BREAKPOINT_CONTROL(i), context->hw_ibp.control[i]);
+    }
+    CVMX_MT_COP0(context->cop0.index, COP0_INDEX);
+    CVMX_MT_COP0(context->cop0.entrylo[0], COP0_ENTRYLO0);
+    CVMX_MT_COP0(context->cop0.entrylo[1], COP0_ENTRYLO1);
+    CVMX_MT_COP0(context->cop0.entryhi, COP0_ENTRYHI);
+    CVMX_MT_COP0(context->cop0.pagemask, COP0_PAGEMASK);
+    CVMX_MT_COP0(context->cop0.status, COP0_STATUS);
+    CVMX_MT_COP0(context->cop0.cause, COP0_CAUSE);
+    CVMX_MT_COP0(context->cop0.debug, COP0_DEBUG);
+    CVMX_MT_COP0(context->cop0.multicoredebug, COP0_MULTICOREDEBUG);
+    CVMX_MT_COP0(context->cop0.perfval[0], COP0_PERFVALUE0);
+    CVMX_MT_COP0(context->cop0.perfval[1], COP0_PERFVALUE1);
+    CVMX_MT_COP0(context->cop0.perfctrl[0], COP0_PERFCONTROL0);
+    CVMX_MT_COP0(context->cop0.perfctrl[1], COP0_PERFCONTROL1);
+    CVMX_MT_COP0(context->cop0.depc, COP0_DEPC);
+    CVMX_MT_COP0(context->cop0.desave, COP0_DESAVE);
+}
+
+static inline void cvmx_debug_print_cause(volatile cvmx_debug_core_context_t *context)
+{
+    if (!CVMX_DEBUG_LOGGING)
+        return;
+    if (context->cop0.multicoredebug & 1)
+        cvmx_dprintf("MCD0 was pulsed\n");
+    if (context->cop0.multicoredebug & (1 << 16))
+        cvmx_dprintf("Exception %lld in Debug Mode\n", (long long)((context->cop0.debug >> 10) & 0x1f));
+    if (context->cop0.debug & (1 << 19))
+        cvmx_dprintf("DDBSImpr\n");
+    if (context->cop0.debug & (1 << 18))
+        cvmx_dprintf("DDBLImpr\n");
+    if (context->cop0.debug & (1 << 5))
+        cvmx_dprintf("DINT\n");
+    if (context->cop0.debug & (1 << 4))
+        cvmx_dprintf("Debug Instruction Breakpoint (DIB) exception\n");
+    if (context->cop0.debug & (1 << 3))
+        cvmx_dprintf("Debug Date Break Store (DDBS) exception\n");
+    if (context->cop0.debug & (1 << 2))
+        cvmx_dprintf("Debug Date Break Load (DDBL) exception\n");
+    if (context->cop0.debug & (1 << 1))
+        cvmx_dprintf("Debug Breakpoint (DBp) exception\n");
+    if (context->cop0.debug & (1 << 0))
+        cvmx_dprintf("Debug Single Step (DSS) exception\n");
+}
+
+void __cvmx_debug_handler_stage3 (void)
+{
+    volatile cvmx_debug_core_context_t *context;
+    int comms_changed = 0;
+
+    cvmx_debug_printf("Entering debug exception handler\n");
+    cvmx_debug_printf("Debug named block at %p\n", cvmx_debug_globals);
+    if (__cvmx_debug_mode_exception_occured)
+    {
+        uint64_t depc;
+        CVMX_MF_COP0(depc, COP0_DEPC);
+        cvmx_dprintf("Unexpected debug-mode exception occured at 0x%llx, 0x%llx spinning\n", (long long) depc, (long long)(__cvmx_debug_mode_exception_occured));
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        panic("Unexpected debug-mode exception occured at 0x%llx, 0x%llx\n", (long long) depc, (long long)(__cvmx_debug_mode_exception_occured));
+#endif
+        while (1)
+            ;
+    }
+
+    context = cvmx_debug_core_context();
+    cvmx_debug_save_core_context(context);
+
+    {
+        cvmx_debug_state_t state;
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        state = cvmx_debug_get_state();
+        state.ever_been_in_debug = 1;
+        cvmx_debug_update_state (state);
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+    }
+    cvmx_debug_print_cause(context);
+
+    do
+    {
+        int needs_proxy;
+        comms_changed = 0;
+        /* If the communication changes, change it. */
+        cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+        if (cvmx_debug_globals->comm_changed)
+        {
+            cvmx_debug_printf("Communication changed: %d\n", (int)cvmx_debug_globals->comm_changed);
+            if (cvmx_debug_globals->comm_changed > COMM_SIZE)
+            {
+                cvmx_dprintf("Unknown communication spinning: %lld > %d.\n", (long long)cvmx_debug_globals->comm_changed, (int)(COMM_SIZE));
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+                panic("Unknown communication.\n");
+#endif
+                while (1)
+                    ;
+            }
+            cvmx_debug_globals->comm_type = cvmx_debug_globals->comm_changed - 1;
+            cvmx_debug_globals->comm_changed = 0;
+        }
+        cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+        needs_proxy = cvmx_debug_comms[cvmx_debug_globals->comm_type]->needs_proxy;
+
+        {
+            cvmx_debug_register_t debug_reg;
+            cvmx_debug_state_t state;
+            unsigned core = cvmx_get_core_num();
+
+            state = cvmx_debug_get_state();
+            debug_reg.u64 = context->cop0.debug;
+            /* All cores stop on any exception.  See if we want nothing from this and
+               it should resume.  This needs to be done for non proxy based debugging
+               so that some non active-cores can control the other cores.  */
+            if (!cvmx_debug_stop_core(state, core, &debug_reg, needs_proxy))
+            {
+                context->cop0.debug = debug_reg.u64;
+                break;
+            }
+        }
+
+        if (needs_proxy)
+        {
+            cvmx_debug_register_t debug_reg;
+            debug_reg.u64 = context->cop0.debug;
+            cvmx_debug_printf("Starting to proxy\n");
+            comms_changed = cvmx_debug_perform_proxy(&debug_reg, context);
+            context->cop0.debug = debug_reg.u64;
+        }
+        else
+        {
+            cvmx_debug_printf("Starting to wait for remote host\n");
+            cvmx_debug_comms[cvmx_debug_globals->comm_type]->wait_for_resume(context, cvmx_debug_get_state());
+        }
+    } while (comms_changed);
+
+    cvmx_debug_clear_status(context);
+
+    cvmx_debug_restore_core_context(context);
+    cvmx_debug_printf("Exiting debug exception handler\n");
+}
+
+void cvmx_debug_trigger_exception(void)
+{
+  /* Set CVMX_CIU_DINT to enter debug exception handler.  */
+  cvmx_write_csr (CVMX_CIU_DINT, 1 << cvmx_get_core_num ());
+  /* Perform an immediate read after every write to an RSL register to force
+     the write to complete. It doesn't matter what RSL read we do, so we
+     choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
+  cvmx_read_csr (CVMX_MIO_BOOT_BIST_STAT);
+}
+
+/**
+ * Inform debugger about the end of the program. This is
+ * called from crt0 after all the C cleanup code finishes.
+ * Our current stack is the C one, not the debug exception
+ * stack. */
+void cvmx_debug_finish(void)
+{
+    unsigned coreid = cvmx_get_core_num();
+    cvmx_debug_state_t state;
+
+    cvmx_debug_printf ("Debug _exit reached!, core %d, cvmx_debug_globals = %p\n", coreid, cvmx_debug_globals);
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    fflush (stdout);
+    fflush (stderr);
+#endif
+
+    cvmx_spinlock_lock(&cvmx_debug_globals->lock);
+    state = cvmx_debug_get_state();
+    state.known_cores ^= (1 << coreid);
+    state.core_finished |= (1<<coreid);
+    cvmx_debug_update_state(state);
+
+    /* Tell the user the core has finished. */
+    if (state.ever_been_in_debug)
+        cvmx_debug_putpacket("!Core %d finish.", coreid);
+
+    /* Notify the debugger if all cores have completed the program */
+    if ((cvmx_debug_core_mask () & state.core_finished) == cvmx_debug_core_mask ())
+    {
+        cvmx_debug_printf("All cores done!\n");
+        if (state.ever_been_in_debug)
+            cvmx_debug_putpacket_noformat("D0");
+    }
+    if (state.focus_core == coreid && state.known_cores != 0)
+    {
+        /* Loop through cores looking for someone to handle interrupts.
+           Since we already check that known_cores is non zero, this
+           should always find a core */
+        unsigned newcore;
+        for (newcore = 0; newcore < CVMX_DEBUG_MAX_CORES; newcore++)
+        {
+           if (state.known_cores & (1<<newcore))
+           {
+               cvmx_debug_printf("Routing uart interrupts to Core #%u.\n", newcore);
+               cvmx_debug_set_focus_core(&state, newcore);
+               cvmx_debug_update_state(state);
+               break;
+            }
+        }
+    }
+    cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
+
+    /* If we ever been in the debug, report to it that we have exited the core. */
+    if (state.ever_been_in_debug)
+        cvmx_debug_trigger_exception();
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-debug.h b/sys/contrib/octeon-sdk/cvmx-debug.h
new file mode 100644
index 0000000..21472e1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-debug.h
@@ -0,0 +1,457 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Interface to debug exception handler
+ *
+ * <hr>$Revision:  $<hr>
+ */
+
+#ifndef __CVMX_DEBUG_H__
+#define __CVMX_DEBUG_H__
+
+#include "cvmx-core.h"
+#include "cvmx-spinlock.h"
+
+
+#define CVMX_DEBUG_MAX_REQUEST_SIZE 1024 + 34 /* Enough room for setting memory of 512 bytes. */
+#define CVMX_DEBUG_MAX_RESPONSE_SIZE 1024 + 5
+
+#define CVMX_DEBUG_GLOBALS_BLOCK_NAME "cvmx-debug-globals"
+#define CVMX_DEBUG_GLOBALS_VERSION 3
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+void cvmx_debug_init(void);
+void cvmx_debug_finish(void);
+void cvmx_debug_trigger_exception(void);
+
+#ifdef __OCTEON_NEWLIB__
+extern int __octeon_debug_booted;
+
+static inline int cvmx_debug_booted(void)
+{
+  return __octeon_debug_booted;
+}
+
+#else
+
+static inline int cvmx_debug_booted(void)
+{
+    return cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG;
+}
+#endif
+
+/* There are 64 TLB entries in CN5XXX and 32 TLB entries in CN3XXX and
+   128 TLB entries in CN6XXX. */
+#define CVMX_DEBUG_N_TLB_ENTRIES 128
+
+/* Maximium number of hardware breakpoints/watchpoints allowed */
+#define CVMX_DEBUG_MAX_OCTEON_HW_BREAKPOINTS 4
+
+typedef struct
+{
+    volatile uint64_t remote_controlled;
+    uint64_t regs[32];
+    uint64_t lo;
+    uint64_t hi;
+
+#define CVMX_DEBUG_BASIC_CONTEXT                \
+    F(remote_controlled);                       \
+    {   int i;                                  \
+        for (i = 0; i < 32; i++)                \
+            F(regs[i]);                         \
+    }                                           \
+    F(lo);                                      \
+    F(hi);
+
+    struct {
+        uint64_t index;
+        uint64_t entrylo[2];
+        uint64_t entryhi;
+        uint64_t pagemask;
+        uint64_t status;
+        uint64_t badvaddr;
+        uint64_t cause;
+        uint64_t depc;
+        uint64_t desave;
+        uint64_t debug;
+        uint64_t multicoredebug;
+        uint64_t perfval[2];
+        uint64_t perfctrl[2];
+    } cop0;
+
+#define CVMX_DEBUG_COP0_CONTEXT                 \
+    F(cop0.index);                              \
+    F(cop0.entrylo[0]);                         \
+    F(cop0.entrylo[1]);                         \
+    F(cop0.entryhi);                            \
+    F(cop0.pagemask);                           \
+    F(cop0.status);                             \
+    F(cop0.badvaddr);                           \
+    F(cop0.cause);                              \
+    F(cop0.depc);                               \
+    F(cop0.desave);                             \
+    F(cop0.debug);                              \
+    F(cop0.multicoredebug);                     \
+    F(cop0.perfval[0]);                         \
+    F(cop0.perfval[1]);                         \
+    F(cop0.perfctrl[0]);                        \
+    F(cop0.perfctrl[1]);
+
+    struct
+    {
+        uint64_t status;
+        uint64_t address[4];
+        uint64_t address_mask[4];
+        uint64_t asid[4];
+        uint64_t control[4];
+    } hw_ibp, hw_dbp;
+
+/* Hardware Instruction Break Point */
+
+#define CVMX_DEBUG_HW_IBP_CONTEXT		\
+    F(hw_ibp.status);				\
+    F(hw_ibp.address[0]);			\
+    F(hw_ibp.address[1]);			\
+    F(hw_ibp.address[2]);			\
+    F(hw_ibp.address[3]);			\
+    F(hw_ibp.address_mask[0]);			\
+    F(hw_ibp.address_mask[1]);			\
+    F(hw_ibp.address_mask[2]);			\
+    F(hw_ibp.address_mask[3]);			\
+    F(hw_ibp.asid[0]);				\
+    F(hw_ibp.asid[1]);				\
+    F(hw_ibp.asid[2]);				\
+    F(hw_ibp.asid[3]);				\
+    F(hw_ibp.control[0]);			\
+    F(hw_ibp.control[1]);			\
+    F(hw_ibp.control[2]);			\
+    F(hw_ibp.control[3]);
+
+/* Hardware Data Break Point */
+#define CVMX_DEBUG_HW_DBP_CONTEXT		\
+    F(hw_dbp.status);				\
+    F(hw_dbp.address[0]);			\
+    F(hw_dbp.address[1]);			\
+    F(hw_dbp.address[2]);			\
+    F(hw_dbp.address[3]);			\
+    F(hw_dbp.address_mask[0]);			\
+    F(hw_dbp.address_mask[1]);			\
+    F(hw_dbp.address_mask[2]);			\
+    F(hw_dbp.address_mask[3]);			\
+    F(hw_dbp.asid[0]);				\
+    F(hw_dbp.asid[1]);				\
+    F(hw_dbp.asid[2]);				\
+    F(hw_dbp.asid[3]);				\
+    F(hw_dbp.control[0]);			\
+    F(hw_dbp.control[1]);			\
+    F(hw_dbp.control[2]);			\
+    F(hw_dbp.control[3]);
+
+
+    struct cvmx_debug_tlb_t
+    {
+        uint64_t entryhi;
+        uint64_t pagemask;
+        uint64_t entrylo[2];
+        uint64_t reserved;
+    } tlbs[CVMX_DEBUG_N_TLB_ENTRIES];
+
+#define CVMX_DEBUG_TLB_CONTEXT                          \
+    {   int i;                                          \
+        for (i = 0; i < CVMX_DEBUG_N_TLB_ENTRIES; i++)  \
+        {                                               \
+            F(tlbs[i].entryhi);                         \
+            F(tlbs[i].pagemask);                        \
+            F(tlbs[i].entrylo[0]);                      \
+            F(tlbs[i].entrylo[1]);                      \
+        }                                               \
+    }
+
+} cvmx_debug_core_context_t;
+
+typedef struct cvmx_debug_tlb_t cvmx_debug_tlb_t;
+
+
+
+typedef enum cvmx_debug_comm_type_e
+{
+    COMM_UART,
+    COMM_REMOTE,
+    COMM_SIZE
+}cvmx_debug_comm_type_t;
+
+typedef enum
+{
+    COMMAND_NOP = 0,            /**< Core doesn't need to do anything. Just stay in exception handler */
+    COMMAND_STEP,               /**< Core needs to perform a single instruction step */
+    COMMAND_CONTINUE            /**< Core need to start running. Doesn't return until some debug event occurs */
+} cvmx_debug_command_t;
+
+/* Every field in this struct has to be uint32_t. */
+typedef struct 
+{
+    uint32_t	known_cores;
+    uint32_t    step_isr;	/**< True if we are going to step into ISR's. */
+    uint32_t    focus_switch;	/**< Focus can be switched. */	
+    uint32_t    core_finished;	/**< True if a core has finished and not been processed yet.  */
+    uint32_t	command;	/**< Command for all cores (cvmx_debug_command_t) */
+    uint32_t    step_all;	/**< True if step and continue should affect all cores. False, only the focus core is affected */
+    uint32_t    focus_core;	/**< Core currently under control of the debugger */
+    uint32_t    active_cores;	/**< Bitmask of cores that should stop on a breakpoint */
+    uint32_t    handler_cores;	/**< Bitmask of cores currently running the exception handler */
+    uint32_t	ever_been_in_debug; /**< True if we have been ever been in the debugger stub at all.  */
+}__attribute__ ((aligned(sizeof(uint64_t)))) cvmx_debug_state_t;
+
+typedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1];
+
+/* Total number of cores in Octeon. */
+#define CVMX_DEBUG_MAX_CORES 16
+
+typedef struct cvmx_debug_globals_s
+{
+    uint64_t version; /* This is always the first element of this struct */
+    uint64_t comm_type; /* cvmx_debug_comm_type_t */
+    volatile uint64_t comm_changed; /* cvmx_debug_comm_type_t+1 when someone wants to change it. */
+    volatile uint64_t init_complete;
+    uint32_t tlb_entries;
+    uint32_t state[sizeof(cvmx_debug_state_t)/sizeof(uint32_t)];
+    cvmx_spinlock_t lock;
+
+    volatile cvmx_debug_core_context_t contextes[CVMX_DEBUG_MAX_CORES];
+} cvmx_debug_globals_t;
+
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    rsrvd:32;   /**< Unused */
+        uint64_t    dbd:1;      /**< Indicates whether the last debug exception or
+                                    exception in Debug Mode occurred in a branch or
+                                    jump delay slot */
+        uint64_t    dm:1;       /**< Indicates that the processor is operating in Debug
+                                    Mode: */
+        uint64_t    nodcr:1;    /**< Indicates whether the dseg segment is present */
+        uint64_t    lsnm:1;     /**< Controls access of loads/stores between the dseg
+                                    segment and remaining memory when the dseg
+                                    segment is present */
+        uint64_t    doze:1;     /**< Indicates that the processor was in a low-power mode
+                                    when a debug exception occurred */
+        uint64_t    halt:1;     /**< Indicates that the internal processor system bus clock
+                                    was stopped when the debug exception occurred */
+        uint64_t    countdm:1;  /**< Controls or indicates the Count register behavior in
+                                    Debug Mode. Implementations can have fixed
+                                    behavior, in which case this bit is read-only (R), or
+                                    the implementation can allow this bit to control the
+                                    behavior, in which case this bit is read/write (R/W).
+                                    The reset value of this bit indicates the behavior after
+                                    reset, and depends on the implementation.
+                                    Encoding of the bit is:
+                                    - 0      Count register stopped in Debug Mode Count register is running in Debug
+                                    - 1      Mode
+                                    This bit is read-only (R) and reads as zero if not implemented. */
+        uint64_t    ibusep:1;   /**< Indicates if a Bus Error exception is pending from an
+                                    instruction fetch. Set when an instruction fetch bus
+                                    error event occurs or a 1 is written to the bit by
+                                    software. Cleared when a Bus Error exception on an
+                                    instruction fetch is taken by the processor. If IBusEP
+                                    is set when IEXI is cleared, a Bus Error exception on
+                                    an instruction fetch is taken by the processor, and
+                                    IBusEP is cleared.
+                                    In Debug Mode, a Bus Error exception applies to a
+                                    Debug Mode Bus Error exception.
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    mcheckp:1;  /**< Indicates if a Machine Check exception is pending.
+                                    Set when a machine check event occurs or a 1 is
+                                    written to the bit by software. Cleared when a
+                                    Machine Check exception is taken by the processor.
+                                    If MCheckP is set when IEXI is cleared, a Machine
+                                    Check exception is taken by the processor, and
+                                    MCheckP is cleared.
+                                    In Debug Mode, a Machine Check exception applies
+                                    to a Debug Mode Machine Check exception.
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    cacheep:1;  /**< Indicates if a Cache Error is pending. Set when a
+                                    cache error event occurs or a 1 is written to the bit by
+                                    software. Cleared when a Cache Error exception is
+                                    taken by the processor. If CacheEP is set when IEXI
+                                    is cleared, a Cache Error exception is taken by the
+                                    processor, and CacheEP is cleared.
+                                    In Debug Mode, a Cache Error exception applies to a
+                                    Debug Mode Cache Error exception.
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    dbusep:1;   /**< Indicates if a Data Access Bus Error exception is
+                                    pending. Set when a data access bus error event
+                                    occurs or a 1 is written to the bit by software. Cleared
+                                    when a Bus Error exception on data access is taken by
+                                    the processor. If DBusEP is set when IEXI is cleared,
+                                    a Bus Error exception on data access is taken by the
+                                    processor, and DBusEP is cleared.
+                                    In Debug Mode, a Bus Error exception applies to a
+                                    Debug Mode Bus Error exception.
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    iexi:1;     /**< An Imprecise Error eXception Inhibit (IEXI) controls
+                                    exceptions taken due to imprecise error indications.
+                                    Set when the processor takes a debug exception or an
+                                    exception in Debug Mode occurs. Cleared by
+                                    execution of the DERET instruction. Otherwise
+                                    modifiable by Debug Mode software.
+                                    When IEXI is set, then the imprecise error exceptions
+                                    from bus errors on instruction fetches or data
+                                    accesses, cache errors, or machine checks are
+                                    inhibited and deferred until the bit is cleared.
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    ddbsimpr:1; /**< Indicates that a Debug Data Break Store Imprecise
+                                    exception due to a store was the cause of the debug
+                                    exception, or that an imprecise data hardware break
+                                    due to a store was indicated after another debug
+                                    exception occurred. Cleared on exception in Debug
+                                    Mode.
+                                        - 0 No match of an imprecise data hardware breakpoint on store
+                                        - 1 Match of imprecise data hardware breakpoint on store
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    ddblimpr:1; /**< Indicates that a Debug Data Break Load Imprecise
+                                    exception due to a load was the cause of the debug
+                                    exception, or that an imprecise data hardware break
+                                    due to a load was indicated after another debug
+                                    exception occurred. Cleared on exception in Debug
+                                    Mode.
+                                        - 0 No match of an imprecise data hardware breakpoint on load
+                                        - 1 Match of imprecise data hardware breakpoint on load
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    ejtagver:3; /**< Provides the EJTAG version.
+                                        - 0      Version 1 and 2.0
+                                        - 1      Version 2.5
+                                        - 2      Version 2.6
+                                        - 3-7    Reserved */
+        uint64_t    dexccode:5; /**< Indicates the cause of the latest exception in Debug
+                                    Mode.
+                                    The field is encoded as the ExcCode field in the
+                                    Cause register for those exceptions that can occur in
+                                    Debug Mode (the encoding is shown in MIPS32 and
+                                    MIPS64 specifications), with addition of code 30
+                                    with the mnemonic CacheErr for cache errors and the
+                                    use of code 9 with mnemonic Bp for the SDBBP
+                                    instruction.
+                                    This value is undefined after a debug exception. */
+        uint64_t    nosst:1;    /**< Indicates whether the single-step feature controllable
+                                    by the SSt bit is available in this implementation:
+                                          - 0      Single-step feature available
+                                          - 1      No single-step feature available
+                                    A minimum number of hardware instruction
+                                    breakpoints must be available if no single-step
+                                    feature is implemented in hardware. Refer to Section
+                                    4.8.1 on page 69 for more information. */
+        uint64_t    sst:1;      /**< Controls whether single-step feature is enabled:
+                                          - 0       No enable of single-step feature
+                                          - 1       Single-step feature enabled
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented due to no single-step feature (NoSSt is
+                                    1). */
+        uint64_t    rsrvd2:2;   /**< Must be zero */
+        uint64_t    dint:1;     /**< Indicates that a Debug Interrupt exception occurred.
+                                    Cleared on exception in Debug Mode.
+                                          - 0       No Debug Interrupt exception
+                                          - 1       Debug Interrupt exception
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    dib:1;      /**< Indicates that a Debug Instruction Break exception
+                                    occurred. Cleared on exception in Debug Mode.
+                                          - 0       No Debug Instruction Break exception
+                                          - 1       Debug Instruction Break exception
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    ddbs:1;     /**< Indicates that a Debug Data Break Store exception
+                                    occurred on a store due to a precise data hardware
+                                    break. Cleared on exception in Debug Mode.
+                                          - 0       No Debug Data Break Store Exception
+                                          - 1       Debug Data Break Store Exception
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    ddbl:1;     /**< Indicates that a Debug Data Break Load exception
+                                    occurred on a load due to a precise data hardware
+                                    break. Cleared on exception in Debug Mode.
+                                          - 0       No Debug Data Break Store Exception
+                                          - 1       Debug Data Break Store Exception
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+        uint64_t    dbp:1;      /**< Indicates that a Debug Breakpoint exception
+                                    occurred. Cleared on exception in Debug Mode.
+                                          - 0      No Debug Breakpoint exception
+                                          - 1      Debug Breakpoint exception */
+        uint64_t    dss:1;      /**< Indicates that a Debug Single Step exception
+                                    occurred. Cleared on exception in Debug Mode.
+                                          - 0       No debug single-step exception
+                                          - 1       Debug single-step exception
+                                    This bit is read-only (R) and reads as zero if not
+                                    implemented. */
+    } s;
+} cvmx_debug_register_t;
+
+
+typedef struct
+{
+    void (*init)(void);
+    void (*install_break_handler)(void);
+    int needs_proxy;
+    int (*getpacket)(char *, size_t);
+    int (*putpacket)(char *);
+    void (*wait_for_resume)(volatile cvmx_debug_core_context_t *, cvmx_debug_state_t);
+    void (*change_core)(int, int);
+} cvmx_debug_comm_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_DEBUG_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa-defs.h b/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
new file mode 100644
index 0000000..42ee0c8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
@@ -0,0 +1,4982 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-dfa-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dfa.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_DFA_TYPEDEFS_H__
+#define __CVMX_DFA_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC()
+static inline uint64_t CVMX_DFA_BIST0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370007F0ull);
+}
+#else
+#define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC()
+static inline uint64_t CVMX_DFA_BIST1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370007F8ull);
+}
+#else
+#define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
+static inline uint64_t CVMX_DFA_BST0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
+}
+#else
+#define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
+static inline uint64_t CVMX_DFA_BST1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
+}
+#else
+#define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
+static inline uint64_t CVMX_DFA_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000000ull);
+}
+#else
+#define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(0x0001180030000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC()
+static inline uint64_t CVMX_DFA_CONFIG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000000ull);
+}
+#else
+#define CVMX_DFA_CONFIG (CVMX_ADD_IO_SEG(0x0001180037000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC()
+static inline uint64_t CVMX_DFA_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000020ull);
+}
+#else
+#define CVMX_DFA_CONTROL (CVMX_ADD_IO_SEG(0x0001180037000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
+static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001370000000000ull);
+}
+#else
+#define CVMX_DFA_DBELL (CVMX_ADD_IO_SEG(0x0001370000000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000210ull);
+}
+#else
+#define CVMX_DFA_DDR2_ADDR (CVMX_ADD_IO_SEG(0x0001180030000210ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000080ull);
+}
+#else
+#define CVMX_DFA_DDR2_BUS (CVMX_ADD_IO_SEG(0x0001180030000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000208ull);
+}
+#else
+#define CVMX_DFA_DDR2_CFG (CVMX_ADD_IO_SEG(0x0001180030000208ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000090ull);
+}
+#else
+#define CVMX_DFA_DDR2_COMP (CVMX_ADD_IO_SEG(0x0001180030000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000268ull);
+}
+#else
+#define CVMX_DFA_DDR2_EMRS (CVMX_ADD_IO_SEG(0x0001180030000268ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000078ull);
+}
+#else
+#define CVMX_DFA_DDR2_FCNT (CVMX_ADD_IO_SEG(0x0001180030000078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000260ull);
+}
+#else
+#define CVMX_DFA_DDR2_MRS (CVMX_ADD_IO_SEG(0x0001180030000260ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000070ull);
+}
+#else
+#define CVMX_DFA_DDR2_OPT (CVMX_ADD_IO_SEG(0x0001180030000070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000088ull);
+}
+#else
+#define CVMX_DFA_DDR2_PLL (CVMX_ADD_IO_SEG(0x0001180030000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000218ull);
+}
+#else
+#define CVMX_DFA_DDR2_TMG (CVMX_ADD_IO_SEG(0x0001180030000218ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC()
+static inline uint64_t CVMX_DFA_DEBUG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000040ull);
+}
+#else
+#define CVMX_DFA_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180037000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC()
+static inline uint64_t CVMX_DFA_DEBUG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000048ull);
+}
+#else
+#define CVMX_DFA_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180037000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC()
+static inline uint64_t CVMX_DFA_DEBUG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000050ull);
+}
+#else
+#define CVMX_DFA_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180037000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC()
+static inline uint64_t CVMX_DFA_DEBUG3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000058ull);
+}
+#else
+#define CVMX_DFA_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180037000058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
+static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001370600000000ull);
+}
+#else
+#define CVMX_DFA_DIFCTL (CVMX_ADD_IO_SEG(0x0001370600000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
+static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001370200000000ull);
+}
+#else
+#define CVMX_DFA_DIFRDPTR (CVMX_ADD_IO_SEG(0x0001370200000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC()
+static inline uint64_t CVMX_DFA_DTCFADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000060ull);
+}
+#else
+#define CVMX_DFA_DTCFADR (CVMX_ADD_IO_SEG(0x0001180037000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
+static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000200ull);
+}
+#else
+#define CVMX_DFA_ECLKCFG (CVMX_ADD_IO_SEG(0x0001180030000200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
+static inline uint64_t CVMX_DFA_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000028ull);
+}
+#else
+#define CVMX_DFA_ERR (CVMX_ADD_IO_SEG(0x0001180030000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC()
+static inline uint64_t CVMX_DFA_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000028ull);
+}
+#else
+#define CVMX_DFA_ERROR (CVMX_ADD_IO_SEG(0x0001180037000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC()
+static inline uint64_t CVMX_DFA_INTMSK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000030ull);
+}
+#else
+#define CVMX_DFA_INTMSK (CVMX_ADD_IO_SEG(0x0001180037000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000008ull);
+}
+#else
+#define CVMX_DFA_MEMCFG0 (CVMX_ADD_IO_SEG(0x0001180030000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000010ull);
+}
+#else
+#define CVMX_DFA_MEMCFG1 (CVMX_ADD_IO_SEG(0x0001180030000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000060ull);
+}
+#else
+#define CVMX_DFA_MEMCFG2 (CVMX_ADD_IO_SEG(0x0001180030000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000030ull);
+}
+#else
+#define CVMX_DFA_MEMFADR (CVMX_ADD_IO_SEG(0x0001180030000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000038ull);
+}
+#else
+#define CVMX_DFA_MEMFCR (CVMX_ADD_IO_SEG(0x0001180030000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC()
+static inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001370700000000ull);
+}
+#else
+#define CVMX_DFA_MEMHIDAT (CVMX_ADD_IO_SEG(0x0001370700000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
+static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000018ull);
+}
+#else
+#define CVMX_DFA_MEMRLD (CVMX_ADD_IO_SEG(0x0001180030000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
+static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000020ull);
+}
+#else
+#define CVMX_DFA_NCBCTL (CVMX_ADD_IO_SEG(0x0001180030000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC()
+static inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000090ull);
+}
+#else
+#define CVMX_DFA_PFC0_CNT (CVMX_ADD_IO_SEG(0x0001180037000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC()
+static inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000088ull);
+}
+#else
+#define CVMX_DFA_PFC0_CTL (CVMX_ADD_IO_SEG(0x0001180037000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC()
+static inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370000A0ull);
+}
+#else
+#define CVMX_DFA_PFC1_CNT (CVMX_ADD_IO_SEG(0x00011800370000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC()
+static inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000098ull);
+}
+#else
+#define CVMX_DFA_PFC1_CTL (CVMX_ADD_IO_SEG(0x0001180037000098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC()
+static inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370000B0ull);
+}
+#else
+#define CVMX_DFA_PFC2_CNT (CVMX_ADD_IO_SEG(0x00011800370000B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC()
+static inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370000A8ull);
+}
+#else
+#define CVMX_DFA_PFC2_CTL (CVMX_ADD_IO_SEG(0x00011800370000A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC()
+static inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370000C0ull);
+}
+#else
+#define CVMX_DFA_PFC3_CNT (CVMX_ADD_IO_SEG(0x00011800370000C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC()
+static inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800370000B8ull);
+}
+#else
+#define CVMX_DFA_PFC3_CTL (CVMX_ADD_IO_SEG(0x00011800370000B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC()
+static inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180037000080ull);
+}
+#else
+#define CVMX_DFA_PFC_GCTL (CVMX_ADD_IO_SEG(0x0001180037000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
+static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000068ull);
+}
+#else
+#define CVMX_DFA_RODT_COMP_CTL (CVMX_ADD_IO_SEG(0x0001180030000068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000040ull);
+}
+#else
+#define CVMX_DFA_SBD_DBG0 (CVMX_ADD_IO_SEG(0x0001180030000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000048ull);
+}
+#else
+#define CVMX_DFA_SBD_DBG1 (CVMX_ADD_IO_SEG(0x0001180030000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000050ull);
+}
+#else
+#define CVMX_DFA_SBD_DBG2 (CVMX_ADD_IO_SEG(0x0001180030000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180030000058ull);
+}
+#else
+#define CVMX_DFA_SBD_DBG3 (CVMX_ADD_IO_SEG(0x0001180030000058ull))
+#endif
+
+/**
+ * cvmx_dfa_bist0
+ *
+ * DFA_BIST0 = DFA Bist Status (per-DTC)
+ *
+ * Description:
+ */
+union cvmx_dfa_bist0
+{
+	uint64_t u64;
+	struct cvmx_dfa_bist0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t mwb                          : 1;  /**< Bist Results for MWB RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_25_27               : 3;
+	uint64_t gfb                          : 1;  /**< Bist Results for GFB RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_18_23               : 6;
+	uint64_t stx                          : 2;  /**< Bist Results for STX RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_10_15               : 6;
+	uint64_t dtx                          : 2;  /**< Bist Results for DTX RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t rdf                          : 1;  /**< Bist Results for RWB[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t pdb                          : 1;  /**< Bist Results for PDB RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdb                          : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t rdf                          : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dtx                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t stx                          : 2;
+	uint64_t reserved_18_23               : 6;
+	uint64_t gfb                          : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t mwb                          : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_dfa_bist0_s               cn63xx;
+	struct cvmx_dfa_bist0_s               cn63xxp1;
+};
+typedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t;
+
+/**
+ * cvmx_dfa_bist1
+ *
+ * DFA_BIST1 = DFA Bist Status (Globals)
+ *
+ * Description:
+ */
+union cvmx_dfa_bist1
+{
+	uint64_t u64;
+	struct cvmx_dfa_bist1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t ram3                         : 1;  /**< Bist Results for RAM3 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram2                         : 1;  /**< Bist Results for RAM2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ram1                         : 1;  /**< Bist Results for RAM1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gutv                         : 1;  /**< Bist Results for GUTV RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gutp                         : 1;  /**< Bist Results for NCD RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ncd                          : 1;  /**< Bist Results for NCD RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gif                          : 1;  /**< Bist Results for GIF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gib                          : 1;  /**< Bist Results for GIB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t gfu                          : 1;
+	uint64_t gib                          : 1;
+	uint64_t gif                          : 1;
+	uint64_t ncd                          : 1;
+	uint64_t gutp                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t gutv                         : 1;
+	uint64_t crq                          : 1;
+	uint64_t ram1                         : 1;
+	uint64_t ram2                         : 1;
+	uint64_t ram3                         : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_dfa_bist1_s               cn63xx;
+	struct cvmx_dfa_bist1_s               cn63xxp1;
+};
+typedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t;
+
+/**
+ * cvmx_dfa_bst0
+ *
+ * DFA_BST0 = DFA Bist Status
+ *
+ * Description:
+ */
+union cvmx_dfa_bst0
+{
+	uint64_t u64;
+	struct cvmx_dfa_bst0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rdf                          : 16; /**< Bist Results for RDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t pdf                          : 16; /**< Bist Results for PDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdf                          : 16;
+	uint64_t rdf                          : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_dfa_bst0_s                cn31xx;
+	struct cvmx_dfa_bst0_s                cn38xx;
+	struct cvmx_dfa_bst0_s                cn38xxp2;
+	struct cvmx_dfa_bst0_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t rdf                          : 4;  /**< Bist Results for RDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pdf                          : 4;  /**< Bist Results for PDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t pdf                          : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t rdf                          : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn58xx;
+	struct cvmx_dfa_bst0_cn58xx           cn58xxp1;
+};
+typedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t;
+
+/**
+ * cvmx_dfa_bst1
+ *
+ * DFA_BST1 = DFA Bist Status
+ *
+ * Description:
+ */
+union cvmx_dfa_bst1
+{
+	uint64_t u64;
+	struct cvmx_dfa_bst1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ifu                          : 1;  /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t drf                          : 1;  /**< Bist Results for DRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t crf                          : 1;  /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p0_bwb                       : 1;  /**< Bist Results for P0_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p1_bwb                       : 1;  /**< Bist Results for P1_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p0_brf                       : 8;  /**< Bist Results for P0_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p1_brf                       : 8;  /**< Bist Results for P1_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t p1_brf                       : 8;
+	uint64_t p0_brf                       : 8;
+	uint64_t p1_bwb                       : 1;
+	uint64_t p0_bwb                       : 1;
+	uint64_t crf                          : 1;
+	uint64_t drf                          : 1;
+	uint64_t gfu                          : 1;
+	uint64_t ifu                          : 1;
+	uint64_t crq                          : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_dfa_bst1_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ifu                          : 1;  /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t drf                          : 1;  /**< Bist Results for DRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t crf                          : 1;  /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_0_17                : 18;
+#else
+	uint64_t reserved_0_17                : 18;
+	uint64_t crf                          : 1;
+	uint64_t drf                          : 1;
+	uint64_t gfu                          : 1;
+	uint64_t ifu                          : 1;
+	uint64_t crq                          : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} cn31xx;
+	struct cvmx_dfa_bst1_s                cn38xx;
+	struct cvmx_dfa_bst1_s                cn38xxp2;
+	struct cvmx_dfa_bst1_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t crq                          : 1;  /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ifu                          : 1;  /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t gfu                          : 1;  /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_19_19               : 1;
+	uint64_t crf                          : 1;  /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p0_bwb                       : 1;  /**< Bist Results for P0_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p1_bwb                       : 1;  /**< Bist Results for P1_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p0_brf                       : 8;  /**< Bist Results for P0_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t p1_brf                       : 8;  /**< Bist Results for P1_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t p1_brf                       : 8;
+	uint64_t p0_brf                       : 8;
+	uint64_t p1_bwb                       : 1;
+	uint64_t p0_bwb                       : 1;
+	uint64_t crf                          : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t gfu                          : 1;
+	uint64_t ifu                          : 1;
+	uint64_t crq                          : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} cn58xx;
+	struct cvmx_dfa_bst1_cn58xx           cn58xxp1;
+};
+typedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t;
+
+/**
+ * cvmx_dfa_cfg
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  DFA_CFG = DFA Configuration
+ *
+ * Description:
+ */
+union cvmx_dfa_cfg
+{
+	uint64_t u64;
+	struct cvmx_dfa_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t nrpl_ena                     : 1;  /**< When set, allows the per-node replication feature to be
+                                                         enabled.
+                                                         In 36-bit mode: The IWORD0[31:30]=SNREPL field AND
+                                                         bits [21:20] of the Next Node ptr are used in generating
+                                                         the next node address (see OCTEON HRM - DFA Chapter for
+                                                         psuedo-code of DTE next node address generation).
+                                                         NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode),
+                                                         (regardless of IWORD0[NRPLEN]), the Resultant Word1+
+                                                         [[47:44],[23:20]] = Next Node's [27:20] bits. This allows
+                                                         SW to use the RESERVED bits of the final node for SW
+                                                         caching. Also, if required, SW will use [22:21]=Node
+                                                         Replication to re-start the same graph walk(if graph
+                                                         walk prematurely terminated (ie: DATA_GONE).
+                                                         In 18-bit mode: The IWORD0[31:30]=SNREPL field AND
+                                                         bit [16:14] of the Next Node ptr are used in generating
+                                                         the next node address (see OCTEON HRM - DFA Chapter for
+                                                         psuedo-code of DTE next node address generation).
+                                                         If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [
+                                                            If next node ptr[16] is set [
+                                                              next node ptr[15:14] indicates the next node repl
+                                                              next node ptr[13:0]  indicates the position of the
+                                                                 node relative to the first normal node (i.e.
+                                                                 IWORD3[Msize] must be added to get the final node)
+                                                            ]
+                                                            else If next node ptr[16] is not set [
+                                                              next node ptr[15:0] indicates the next node id
+                                                              next node repl = 0
+                                                            ]
+                                                         ]
+                                                         NOTE: For 18b node replication, MAX node space=64KB(2^16)
+                                                         is used in detecting terminal node space(see HRM for full
+                                                         description).
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-node" replication. */
+	uint64_t nxor_ena                     : 1;  /**< When set, allows the DTE Instruction IWORD0[NXOREN]
+                                                         to be used to enable/disable the per-node address 'scramble'
+                                                         of the LLM address to lessen the effects of bank conflicts.
+                                                         If IWORD0[NXOREN] is also set, then:
+                                                         In 36-bit mode: The node_Id[7:0] 8-bit value is XORed
+                                                         against the LLM address addr[9:2].
+                                                         In 18-bit mode: The node_id[6:0] 7-bit value is XORed
+                                                         against the LLM address addr[8:2]. (note: we don't address
+                                                         scramble outside the mode's node space).
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-node" address scramble.
+                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
+                                                         read/write operations. */
+	uint64_t gxor_ena                     : 1;  /**< When set, the DTE Instruction IWORD0[GXOR]
+                                                         field is used to 'scramble' the LLM address
+                                                         to lessen the effects of bank conflicts.
+                                                         In 36-bit mode: The GXOR[7:0] 8-bit value is XORed
+                                                         against the LLM address addr[9:2].
+                                                         In 18-bit mode: GXOR[6:0] 7-bit value is XORed against
+                                                         the LLM address addr[8:2]. (note: we don't address
+                                                         scramble outside the mode's node space)
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-graph" address scramble.
+                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
+                                                         read/write operations. */
+	uint64_t sarb                         : 1;  /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA
+                                                         requests issued from either CP2 or the DTE (NCB-CSR
+                                                         or DFA HW engine).
+                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                            - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t sarb                         : 1;
+	uint64_t gxor_ena                     : 1;
+	uint64_t nxor_ena                     : 1;
+	uint64_t nrpl_ena                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_dfa_cfg_s                 cn38xx;
+	struct cvmx_dfa_cfg_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t sarb                         : 1;  /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA
+                                                         requests issued from either CP2 or the DTE (NCB-CSR
+                                                         or DFA HW engine).
+                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                            - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t sarb                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn38xxp2;
+	struct cvmx_dfa_cfg_s                 cn58xx;
+	struct cvmx_dfa_cfg_s                 cn58xxp1;
+};
+typedef union cvmx_dfa_cfg cvmx_dfa_cfg_t;
+
+/**
+ * cvmx_dfa_config
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  DFA_CONFIG = DFA Configuration Register
+ *
+ * Description:
+ */
+union cvmx_dfa_config
+{
+	uint64_t u64;
+	struct cvmx_dfa_config_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t repl_ena                     : 1;  /**< Replication Mode Enable
+                                                         *** o63-P2 NEW ***
+                                                         When set, enables replication mode performance enhancement
+                                                         feature. This enables the DFA to communicate address
+                                                         replication information during memory references to the DFM
+                                                         (memory controller). This in turn is used by the DFM to support
+                                                         graph data in multiple banks (or bank sets), so that the least
+                                                         full bank can be selected to minimize the effects of DDR3 bank
+                                                         conflicts (ie: tRC=row cycle time).
+                                                         SWNOTE: Using this mode requires the DFA SW compiler and DFA
+                                                         driver to be aware of the o63-P2 address replication changes.
+                                                         This involves changes to the MLOAD/GWALK DFA instruction format
+                                                         (see: IWORD2.SREPL), as well as changes to node arc and metadata
+                                                         definitions which now support an additional REPL field.
+                                                         When clear, replication mode is disabled, and DFA will interpret
+                                                         o63-P1 DFA instructions and node-arc formats which DO NOT have
+                                                         address replication information. */
+	uint64_t clmskcrip                    : 4;  /**< Cluster Cripple Mask
+                                                         A one in each bit of the mask represents which DTE cluster to
+                                                         cripple.
+                                                         NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0]
+                                                         is the only bit used.
+                                                         o2 has 4 clusters, where all CLMSKCRIP mask bits are used.
+                                                         SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t cldtecrip                    : 3;  /**< Encoding which represents \#of DTEs to cripple for each
+                                                         cluster. Typically DTE_CLCRIP=0 which enables all DTEs
+                                                         within each cluster. However, when the DFA performance
+                                                         counters are used, SW may want to limit the \#of DTEs
+                                                         per cluster available, as there are only 4 parallel
+                                                         performance counters.
+                                                            DTE_CLCRIP | \#DTEs crippled(per cluster)
+                                                         ------------+-----------------------------
+                                                                0    |  0      DTE[15:0]:ON
+                                                                1    |  1/2    DTE[15:8]:OFF  /DTE[7:0]:ON
+                                                                2    |  1/4    DTE[15:12]:OFF /DTE[11:0]:ON
+                                                                3    |  3/4    DTE[15:4]:OFF  /DTE[3:0]:ON
+                                                                4    |  1/8    DTE[15:14]:OFF /DTE[13:0]:ON
+                                                                5    |  5/8    DTE[15:6]:OFF  /DTE[5:0]:ON
+                                                                6    |  3/8    DTE[15:10]:OFF /DTE[9:0]:ON
+                                                                7    |  7/8    DTE[15:2]:OFF  /DTE[1:0]:ON
+                                                         NOTE: Higher numbered DTEs are crippled first. For instance,
+                                                         on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then
+                                                         DTE#s [15:8] within the cluster are crippled and only
+                                                         DTE#s [7:0] are available.
+                                                         IMPNOTE: The encodings are done in such a way as to later
+                                                         be used with fuses (for future o2 revisions which will disable
+                                                         some \#of DTEs). Blowing a fuse has the effect that there will
+                                                         always be fewer DTEs available. [ie: we never want a customer
+                                                         to blow additional fuses to get more DTEs].
+                                                         SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t dteclkdis                    : 1;  /**< DFA Clock Disable Source
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled (to conserve overall chip clocking
+                                                         power when the DFA function is not used).
+                                                         NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR
+                                                         operations to the DFA (will result in NCB Bus Timeout
+                                                         errors).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will
+                                                         be forced into this register at reset. If the fuse bit
+                                                         contains '1', writes to DTECLKDIS are disallowed and
+                                                         will always be read as '1'. */
+#else
+	uint64_t dteclkdis                    : 1;
+	uint64_t cldtecrip                    : 3;
+	uint64_t clmskcrip                    : 4;
+	uint64_t repl_ena                     : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_dfa_config_s              cn63xx;
+	struct cvmx_dfa_config_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t clmskcrip                    : 4;  /**< Cluster Cripple Mask
+                                                         A one in each bit of the mask represents which DTE cluster to
+                                                         cripple.
+                                                         NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0]
+                                                         is the only bit used.
+                                                         o2 has 4 clusters, where all CLMSKCRIP mask bits are used.
+                                                         SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t cldtecrip                    : 3;  /**< Encoding which represents \#of DTEs to cripple for each
+                                                         cluster. Typically DTE_CLCRIP=0 which enables all DTEs
+                                                         within each cluster. However, when the DFA performance
+                                                         counters are used, SW may want to limit the \#of DTEs
+                                                         per cluster available, as there are only 4 parallel
+                                                         performance counters.
+                                                            DTE_CLCRIP | \#DTEs crippled(per cluster)
+                                                         ------------+-----------------------------
+                                                                0    |  0      DTE[15:0]:ON
+                                                                1    |  1/2    DTE[15:8]:OFF  /DTE[7:0]:ON
+                                                                2    |  1/4    DTE[15:12]:OFF /DTE[11:0]:ON
+                                                                3    |  3/4    DTE[15:4]:OFF  /DTE[3:0]:ON
+                                                                4    |  1/8    DTE[15:14]:OFF /DTE[13:0]:ON
+                                                                5    |  5/8    DTE[15:6]:OFF  /DTE[5:0]:ON
+                                                                6    |  3/8    DTE[15:10]:OFF /DTE[9:0]:ON
+                                                                7    |  7/8    DTE[15:2]:OFF  /DTE[1:0]:ON
+                                                         NOTE: Higher numbered DTEs are crippled first. For instance,
+                                                         on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then
+                                                         DTE#s [15:8] within the cluster are crippled and only
+                                                         DTE#s [7:0] are available.
+                                                         IMPNOTE: The encodings are done in such a way as to later
+                                                         be used with fuses (for future o2 revisions which will disable
+                                                         some \#of DTEs). Blowing a fuse has the effect that there will
+                                                         always be fewer DTEs available. [ie: we never want a customer
+                                                         to blow additional fuses to get more DTEs].
+                                                         SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will
+                                                         be forced into this register at reset. Any fuse bits that
+                                                         contain '1' will be disallowed during a write and will always
+                                                         be read as '1'. */
+	uint64_t dteclkdis                    : 1;  /**< DFA Clock Disable Source
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled (to conserve overall chip clocking
+                                                         power when the DFA function is not used).
+                                                         NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR
+                                                         operations to the DFA (will result in NCB Bus Timeout
+                                                         errors).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will
+                                                         be forced into this register at reset. If the fuse bit
+                                                         contains '1', writes to DTECLKDIS are disallowed and
+                                                         will always be read as '1'. */
+#else
+	uint64_t dteclkdis                    : 1;
+	uint64_t cldtecrip                    : 3;
+	uint64_t clmskcrip                    : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfa_config cvmx_dfa_config_t;
+
+/**
+ * cvmx_dfa_control
+ *
+ * DFA_CONTROL = DFA Control Register
+ *
+ * Description:
+ */
+union cvmx_dfa_control
+{
+	uint64_t u64;
+	struct cvmx_dfa_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sbdnum                       : 4;  /**< SBD Debug Entry#
+                                                         *FOR INTERNAL USE ONLY*
+                                                         DFA Scoreboard debug control
+                                                         Selects which one of 8 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
+                                                         *FOR INTERNAL USE ONLY*
+                                                         DFA Scoreboard debug control
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+	uint64_t reserved_3_4                 : 2;
+	uint64_t pmode                        : 1;  /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t qmode                        : 1;  /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t imode                        : 1;  /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t imode                        : 1;
+	uint64_t qmode                        : 1;
+	uint64_t pmode                        : 1;
+	uint64_t reserved_3_4                 : 2;
+	uint64_t sbdlck                       : 1;
+	uint64_t sbdnum                       : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_dfa_control_s             cn63xx;
+	struct cvmx_dfa_control_s             cn63xxp1;
+};
+typedef union cvmx_dfa_control cvmx_dfa_control_t;
+
+/**
+ * cvmx_dfa_dbell
+ *
+ * DFA_DBELL = DFA Doorbell Register
+ *
+ * Description:
+ *  NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00.
+ *        To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00.
+ *
+ *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect.
+ *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect.
+ */
+union cvmx_dfa_dbell
+{
+	uint64_t u64;
+	struct cvmx_dfa_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dbell                        : 20; /**< Represents the cumulative total of pending
+                                                         DFA instructions which SW has previously written
+                                                         into the DFA Instruction FIFO (DIF) in main memory.
+                                                         Each DFA instruction contains a fixed size 32B
+                                                         instruction word which is executed by the DFA HW.
+                                                         The DBL register can hold up to 1M-1 (2^20-1)
+                                                         pending DFA instruction requests.
+                                                         During a read (by SW), the 'most recent' contents
+                                                         of the DFA_DBELL register are returned at the time
+                                                         the NCB-INB bus is driven.
+                                                         NOTE: Since DFA HW updates this register, its
+                                                         contents are unpredictable in SW. */
+#else
+	uint64_t dbell                        : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_dfa_dbell_s               cn31xx;
+	struct cvmx_dfa_dbell_s               cn38xx;
+	struct cvmx_dfa_dbell_s               cn38xxp2;
+	struct cvmx_dfa_dbell_s               cn58xx;
+	struct cvmx_dfa_dbell_s               cn58xxp1;
+	struct cvmx_dfa_dbell_s               cn63xx;
+	struct cvmx_dfa_dbell_s               cn63xxp1;
+};
+typedef union cvmx_dfa_dbell cvmx_dfa_dbell_t;
+
+/**
+ * cvmx_dfa_ddr2_addr
+ *
+ * DFA_DDR2_ADDR = DFA DDR2  fclk-domain Memory Address Config Register
+ *
+ *
+ * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK
+ *              etc.
+ */
+union cvmx_dfa_ddr2_addr
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t rdimm_ena                    : 1;  /**< If there is a need to insert a register chip on the
+                                                         system (the equivalent of a registered DIMM) to
+                                                         provide better setup for the command and control bits
+                                                         turn this mode on.
+                                                             RDIMM_ENA
+                                                                0           Registered Mode OFF
+                                                                1           Registered Mode ON */
+	uint64_t num_rnks                     : 2;  /**< NUM_RNKS is programmed based on how many ranks there
+                                                         are in the system. This needs to be programmed correctly
+                                                         regardless of whether we are in RNK_LO mode or not.
+                                                            NUM_RNKS     \# of Ranks
+                                                              0              1
+                                                              1              2
+                                                              2              4
+                                                              3              RESERVED */
+	uint64_t rnk_lo                       : 1;  /**< When this mode is turned on, consecutive addresses
+                                                         outside the bank boundary
+                                                         are programmed to go to different ranks in order to
+                                                         minimize bank conflicts. It is useful in 4-bank DDR2
+                                                         parts based memory to extend out the \#physical banks
+                                                         available and minimize bank conflicts.
+                                                         On 8 bank ddr2 parts, this mode is not very useful
+                                                         because this mode does come with
+                                                         a penalty which is that every successive reads that
+                                                         cross rank boundary will need a 1 cycle bubble
+                                                         inserted to prevent bus turnaround conflicts.
+                                                            RNK_LO
+                                                             0      - OFF
+                                                             1      - ON */
+	uint64_t num_colrows                  : 3;  /**< NUM_COLROWS    is used to set the MSB of the ROW_ADDR
+                                                         and the LSB of RANK address when not in RNK_LO mode.
+                                                         Calculate the sum of \#COL and \#ROW and program the
+                                                         controller appropriately
+                                                            RANK_LSB        \#COLs + \#ROWs
+                                                            ------------------------------
+                                                             - 000:                   22
+                                                             - 001:                   23
+                                                             - 010:                   24
+                                                             - 011:                   25
+                                                            - 100-111:             RESERVED */
+	uint64_t num_cols                     : 2;  /**< The Long word address that the controller receives
+                                                         needs to be converted to Row, Col, Rank and Bank
+                                                         addresses depending on the memory part's micro arch.
+                                                         NUM_COL tells the controller how many colum bits
+                                                         there are and the controller uses this info to map
+                                                         the LSB of the row address
+                                                             - 00: num_cols = 9
+                                                             - 01: num_cols = 10
+                                                             - 10: num_cols = 11
+                                                             - 11: RESERVED */
+#else
+	uint64_t num_cols                     : 2;
+	uint64_t num_colrows                  : 3;
+	uint64_t rnk_lo                       : 1;
+	uint64_t num_rnks                     : 2;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_addr_s           cn31xx;
+};
+typedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t;
+
+/**
+ * cvmx_dfa_ddr2_bus
+ *
+ * DFA_DDR2_BUS = DFA DDR Bus Activity Counter
+ *
+ *
+ * Description: This counter counts \# cycles that the memory bus is doing a read/write/command
+ *              Useful to benchmark the bus utilization as a ratio of
+ *              \#Cycles of Data Transfer/\#Cycles since init or
+ *              \#Cycles of Data Transfer/\#Cycles that memory controller is active
+ */
+union cvmx_dfa_ddr2_bus
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_bus_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t bus_cnt                      : 47; /**< Counter counts the \# cycles of Data transfer */
+#else
+	uint64_t bus_cnt                      : 47;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_bus_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t;
+
+/**
+ * cvmx_dfa_ddr2_cfg
+ *
+ * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register
+ *
+ * Description:
+ */
+union cvmx_dfa_ddr2_cfg
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_41_63               : 23;
+	uint64_t trfc                         : 5;  /**< Establishes tRFC(from DDR2 data sheets) in \# of
+                                                         4 fclk intervals.
+                                                         General Equation:
+                                                         TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))]
+                                                         Example:
+                                                            tRFC(data-sheet-ns) = 127.5ns
+                                                            Operational Frequency: 533MHz DDR rate
+                                                                [fclk=266MHz(3.75ns)]
+                                                         Then:
+                                                            TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)]
+                                                                      = 9 */
+	uint64_t mrs_pgm                      : 1;  /**< When clear, the HW initialization sequence fixes
+                                                         some of the *MRS register bit definitions.
+                                                            EMRS:
+                                                              A[14:13] = 0 RESERVED
+                                                              A[12] = 0    Output Buffers Enabled (FIXED)
+                                                              A[11] = 0    RDQS Disabled (FIXED)
+                                                              A[10] = 0    DQSn Enabled (FIXED)
+                                                              A[9:7] = 0   OCD Not supported (FIXED)
+                                                              A[6] = 0     RTT Disabled (FIXED)
+                                                              A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1)
+                                                                            Additive LATENCY (Programmable)
+                                                              A[2]=0       RTT Disabled (FIXED)
+                                                              A[1]=DFA_DDR2_TMG[DIC] (Programmable)
+                                                              A[0] = 0     DLL Enabled (FIXED)
+                                                            MRS:
+                                                              A[14:13] = 0 RESERVED
+                                                              A[12] = 0    Fast Active Power Down Mode (FIXED)
+                                                              A[11:9] = DFA_DDR2_TMG[TWR](Programmable)
+                                                              A[8] = 1     DLL Reset (FIXED)
+                                                              A[7] = 0     Test Mode (FIXED)
+                                                              A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable)
+                                                              A[3] = 0     Burst Type(must be 0:Sequential) (FIXED)
+                                                              A[2:0] = 2   Burst Length=4 (must be 0:Sequential) (FIXED)
+                                                         When set, the HW initialization sequence sources
+                                                         the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are
+                                                         driven onto the DFA_A[] pins. (this allows the MRS/EMRS
+                                                         fields to be completely programmable - however care
+                                                         must be taken by software).
+                                                         This mode is useful for customers who wish to:
+                                                            1) override the FIXED definitions(above), or
+                                                            2) Use a "clamshell mode" of operation where the
+                                                               address bits(per rank) are swizzled on the
+                                                               board to reduce stub lengths for optimal
+                                                               frequency operation.
+                                                         Use this in combination with DFA_DDR2_CFG[RNK_MSK]
+                                                         to specify the INIT sequence for each of the 4
+                                                         supported ranks. */
+	uint64_t fpip                         : 3;  /**< Early Fill Programmable Pipe [\#fclks]
+                                                         This field dictates the \#fclks prior to the arrival
+                                                         of fill data(in fclk domain), to start the 'early' fill
+                                                         command pipe (in the eclk domain) so as to minimize the
+                                                         overall fill latency.
+                                                         The programmable early fill command signal is synchronized
+                                                         into the eclk domain, where it is used to pull data out of
+                                                         asynchronous RAM as fast as possible.
+                                                         NOTE: A value of FPIP=0 is the 'safest' setting and will
+                                                         result in the early fill command pipe starting in the
+                                                         same cycle as the fill data.
+                                                         General Equation: (for FPIP)
+                                                             FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)]
+                                                         where:
+                                                           EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)]
+                                                         Example: FCLK=200MHz/ECLK=600MHz
+                                                            FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)]
+                                                            FPIP <= 3 */
+	uint64_t reserved_29_31               : 3;
+	uint64_t ref_int                      : 13; /**< Refresh Interval (represented in \#of fclk
+                                                         increments).
+                                                         Each refresh interval will generate a single
+                                                         auto-refresh command sequence which implicitly targets
+                                                         all banks within the device:
+                                                         Example: For fclk=200MHz(5ns)/400MHz(DDR):
+                                                           trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet]
+                                                           REF_INT = ROUND_DOWN[(trefint/fclk)]
+                                                                   = ROUND_DOWN[(3900ns/5ns)]
+                                                                   = 780 fclks (0x30c)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t tskw                         : 2;  /**< Board Skew (represented in \#fclks)
+                                                         Represents additional board skew of DQ/DQS.
+                                                             - 00: board-skew = 0 fclk
+                                                             - 01: board-skew = 1 fclk
+                                                             - 10: board-skew = 2 fclk
+                                                             - 11: board-skew = 3 fclk
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t rnk_msk                      : 4;  /**< Controls the CS_N[3:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_DDR2_CFG[INIT]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the RNK_MSK[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per rank(or clam). In a clamshell configuration,
+                                                         the N3K DFA_A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         separate HW init sequences each unique rank address
+                                                         mapping. Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_DDR2_MRS/EMRS registers with
+                                                         the data that will be driven onto the A[14:0] wires
+                                                         during the EMRS/MRS mode register write(s).
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0]
+                                                         is driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t silo_qc                      : 1;  /**< Enables Quarter Cycle move of the Rd sampling window */
+	uint64_t silo_hc                      : 1;  /**< A combination of SILO_HC, SILO_QC and TSKW
+                                                         specifies the positioning of the sampling strobe
+                                                         when receiving read data back from DDR2. This is
+                                                         done to offset any board trace induced delay on
+                                                         the DQ and DQS which inherently makes these
+                                                         asynchronous with respect to the internal clk of
+                                                         controller. TSKW moves this sampling window by
+                                                         integer cycles. SILO_QC and HC move this quarter
+                                                         and half a cycle respectively. */
+	uint64_t sil_lat                      : 2;  /**< Silo Latency (\#fclks): On reads, determines how many
+                                                         additional fclks to wait (on top of CASLAT+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t bprch                        : 1;  /**< Tristate Enable (back porch) (\#fclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t fprch                        : 1;  /**< Tristate Enable (front porch) (\#fclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t init                         : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for the LLM Memory Port is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port
+                                                               a) PRTENA=1
+                                                           2) Wait 200us (to ensure a stable clock
+                                                              to the DDR2) - as per DDR2 spec.
+                                                           3) Write a '1' to the INIT which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_DDR2* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t prtena                       : 1;  /**< Enable DFA Memory
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for DFA-LLM memory port. */
+#else
+	uint64_t prtena                       : 1;
+	uint64_t init                         : 1;
+	uint64_t fprch                        : 1;
+	uint64_t bprch                        : 1;
+	uint64_t sil_lat                      : 2;
+	uint64_t silo_hc                      : 1;
+	uint64_t silo_qc                      : 1;
+	uint64_t rnk_msk                      : 4;
+	uint64_t tskw                         : 2;
+	uint64_t reserved_14_15               : 2;
+	uint64_t ref_int                      : 13;
+	uint64_t reserved_29_31               : 3;
+	uint64_t fpip                         : 3;
+	uint64_t mrs_pgm                      : 1;
+	uint64_t trfc                         : 5;
+	uint64_t reserved_41_63               : 23;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_cfg_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t;
+
+/**
+ * cvmx_dfa_ddr2_comp
+ *
+ * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration
+ *
+ *
+ * Description: The following are registers to program the DDR2 PLL and DLL
+ */
+union cvmx_dfa_ddr2_comp
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_comp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dfa__pctl                    : 4;  /**< DFA DDR pctl from compensation circuit
+                                                         Internal DBG only */
+	uint64_t dfa__nctl                    : 4;  /**< DFA DDR nctl from compensation circuit
+                                                         Internal DBG only */
+	uint64_t reserved_9_55                : 47;
+	uint64_t pctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t comp_bypass                  : 1;  /**< Compensation Bypass */
+#else
+	uint64_t comp_bypass                  : 1;
+	uint64_t nctl_csr                     : 4;
+	uint64_t pctl_csr                     : 4;
+	uint64_t reserved_9_55                : 47;
+	uint64_t dfa__nctl                    : 4;
+	uint64_t dfa__pctl                    : 4;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_comp_s           cn31xx;
+};
+typedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t;
+
+/**
+ * cvmx_dfa_ddr2_emrs
+ *
+ * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0]
+ * Description: This register contains the data driven onto the Address[14:0] lines during  DDR INIT
+ * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
+ * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
+ * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
+ * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
+ *
+ * Notes:
+ * For DDR-II please consult your device's data sheet for further details:
+ *
+ */
+union cvmx_dfa_ddr2_emrs
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_emrs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t emrs1_ocd                    : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)"
+                                                         step \#12a "EMRS OCD Default Command" A[9:7]=111
+                                                         of DDR2 HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2):
+                                                         Power Up and initialization sequence).
+                                                            A[14:13] = 0, RESERVED
+                                                            A[12] = 0, Output Buffers Enabled
+                                                            A[11] = 0, RDQS Disabled (we do not support RDQS)
+                                                            A[10] = 0, DQSn Enabled
+                                                            A[9:7] = 7, OCD Calibration Mode Default
+                                                            A[6] = 0, ODT Disabled
+                                                            A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
+                                                            A[2]=0    Termination Res RTT (ODT off Default)
+                                                            [A6,A2] = 0 -> ODT Disabled
+                                                                      1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
+                                                            A[1]=0  Normal Output Driver Imp mode
+                                                                    (1 - weak ie., 60% of normal drive strength)
+                                                            A[0] = 0 DLL Enabled */
+	uint64_t reserved_15_15               : 1;
+	uint64_t emrs1                        : 15; /**< Memory Address[14:0] during:
+                                                           a) Step \#7 "EMRS1 to enable DLL (A[0]=0)"
+                                                           b) Step \#12b "EMRS OCD Calibration Mode Exit"
+                                                         steps of DDR2 HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up and
+                                                         initialization sequence).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Output Buffers Enabled
+                                                           A[11] = 0, RDQS Disabled (we do not support RDQS)
+                                                           A[10] = 0, DQSn Enabled
+                                                           A[9:7] = 0, OCD Calibration Mode exit/maintain
+                                                           A[6] = 0, ODT Disabled
+                                                           A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
+                                                           A[2]=0    Termination Res RTT (ODT off Default)
+                                                           [A6,A2] = 0 -> ODT Disabled
+                                                                     1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
+                                                           A[1]=0  Normal Output Driver Imp mode
+                                                                   (1 - weak ie., 60% of normal drive strength)
+                                                           A[0] = 0 DLL Enabled */
+#else
+	uint64_t emrs1                        : 15;
+	uint64_t reserved_15_15               : 1;
+	uint64_t emrs1_ocd                    : 15;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_emrs_s           cn31xx;
+};
+typedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t;
+
+/**
+ * cvmx_dfa_ddr2_fcnt
+ *
+ * DFA_DDR2_FCNT = DFA FCLK Counter
+ *
+ *
+ * Description: This FCLK cycle counter gets going after memory has been initialized
+ */
+union cvmx_dfa_ddr2_fcnt
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_fcnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t fcyc_cnt                     : 47; /**< Counter counts FCLK cycles or \# cycles that the memory
+                                                         controller has requests queued up depending on FCNT_MODE
+                                                         If FCNT_MODE = 0, this counter counts the \# FCLK cycles
+                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
+                                                         controller is active with memory requests. */
+#else
+	uint64_t fcyc_cnt                     : 47;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_fcnt_s           cn31xx;
+};
+typedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t;
+
+/**
+ * cvmx_dfa_ddr2_mrs
+ *
+ * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0]
+ * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT
+ * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
+ * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
+ * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
+ * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
+ *
+ * Notes:
+ * For DDR-II please consult your device's data sheet for further details:
+ *
+ */
+union cvmx_dfa_ddr2_mrs
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_mrs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t mrs                          : 15; /**< Memory Address[14:0] during "MRS without resetting
+                                                         DLL A[8]=0" step of HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
+                                                         and initialization sequence - Step \#11).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Fast Active Power Down Mode
+                                                           A[11:9] = DFA_DDR2_TMG[TWR]
+                                                           A[8] = 0, for DLL Reset
+                                                           A[7] =0  Test Mode (must be 0 for normal operation)
+                                                           A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4)
+                                                           A[3]=0    Burst Type(must be 0:Sequential)
+                                                           A[2:0]=2  Burst Length=4(default) */
+	uint64_t reserved_15_15               : 1;
+	uint64_t mrs_dll                      : 15; /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1"
+                                                         step of HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
+                                                         and initialization sequence - Step \#8).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Fast Active Power Down Mode
+                                                           A[11:9] = DFA_DDR2_TMG[TWR]
+                                                           A[8] = 1, for DLL Reset
+                                                           A[7] = 0  Test Mode (must be 0 for normal operation)
+                                                           A[6:4]=DFA_DDR2_TMG[CASLAT]    CAS LATENCY (default 4)
+                                                           A[3] = 0    Burst Type(must be 0:Sequential)
+                                                           A[2:0] = 2  Burst Length=4(default) */
+#else
+	uint64_t mrs_dll                      : 15;
+	uint64_t reserved_15_15               : 1;
+	uint64_t mrs                          : 15;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_mrs_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t;
+
+/**
+ * cvmx_dfa_ddr2_opt
+ *
+ * DFA_DDR2_OPT = DFA DDR2 Optimization Registers
+ *
+ *
+ * Description: The following are registers to tweak certain parameters to boost performance
+ */
+union cvmx_dfa_ddr2_opt
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_opt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t max_read_batch               : 5;  /**< Maximum number of consecutive read to service before
+                                                         allowing write to interrupt. */
+	uint64_t max_write_batch              : 5;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+#else
+	uint64_t max_write_batch              : 5;
+	uint64_t max_read_batch               : 5;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_opt_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t;
+
+/**
+ * cvmx_dfa_ddr2_pll
+ *
+ * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration
+ *
+ *
+ * Description: The following are registers to program the DDR2 PLL and DLL
+ */
+union cvmx_dfa_ddr2_pll
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_pll_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pll_setting                  : 17; /**< Internal Debug Use Only */
+	uint64_t reserved_32_46               : 15;
+	uint64_t setting90                    : 5;  /**< Contains the setting of DDR DLL; Internal DBG only */
+	uint64_t reserved_21_26               : 6;
+	uint64_t dll_setting                  : 5;  /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+	uint64_t dll_byp                      : 1;  /**< DLL Bypass. When set, the DDR90 DLL is bypassed and
+                                                         the DLL behaves in Open Loop giving a fixed delay
+                                                         set by DLL_SETTING */
+	uint64_t qdll_ena                     : 1;  /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         erst deassertion will reset the DDR 90 DLL. Allow
+                                                         200 micro seconds for Lock before DDR Init. */
+	uint64_t bw_ctl                       : 4;  /**< Internal Use Only - for Debug */
+	uint64_t bw_upd                       : 1;  /**< Internal Use Only - for Debug */
+	uint64_t pll_div2                     : 1;  /**< PLL Output is further divided by 2. Useful for slow
+                                                         fclk frequencies where the PLL may be out of range. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t pll_ratio                    : 5;  /**< Bits <6:2> sets the clk multiplication ratio
+                                                         If the fclk frequency desired is less than 260MHz
+                                                         (lower end saturation point of the pll), write 2x
+                                                         the ratio desired in this register and set PLL_DIV2 */
+	uint64_t pll_bypass                   : 1;  /**< PLL Bypass. Uses the ref_clk without multiplication. */
+	uint64_t pll_init                     : 1;  /**< Need a 0 to 1 pulse on this CSR to get the DFA
+                                                         Clk Generator Started. Write this register before
+                                                         starting anything. Allow 200 uS for PLL Lock before
+                                                         doing anything. */
+#else
+	uint64_t pll_init                     : 1;
+	uint64_t pll_bypass                   : 1;
+	uint64_t pll_ratio                    : 5;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t pll_div2                     : 1;
+	uint64_t bw_upd                       : 1;
+	uint64_t bw_ctl                       : 4;
+	uint64_t qdll_ena                     : 1;
+	uint64_t dll_byp                      : 1;
+	uint64_t dll_setting                  : 5;
+	uint64_t reserved_21_26               : 6;
+	uint64_t setting90                    : 5;
+	uint64_t reserved_32_46               : 15;
+	uint64_t pll_setting                  : 17;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_pll_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t;
+
+/**
+ * cvmx_dfa_ddr2_tmg
+ *
+ * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register
+ *
+ *
+ * Description: The following are registers to program the DDR2 memory timing parameters.
+ */
+union cvmx_dfa_ddr2_tmg
+{
+	uint64_t u64;
+	struct cvmx_dfa_ddr2_tmg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t fcnt_mode                    : 1;  /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles
+                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
+                                                         controller is active with memory requests. */
+	uint64_t cnt_clr                      : 1;  /**< Clears the FCLK Cyc & Bus Util counter */
+	uint64_t cavmipo                      : 1;  /**< RESERVED */
+	uint64_t ctr_rst                      : 1;  /**< Reset oneshot pulse for refresh counter & Perf counters
+                                                         SW should first write this field to a one to clear
+                                                         & then write to a zero for normal operation */
+	uint64_t odt_rtt                      : 2;  /**< DDR2 Termination Resistor Setting
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                              00 = ODT Disabled
+                                                              01 = 75 ohm Termination
+                                                              10 = 150 ohm Termination
+                                                              11 = 50 ohm Termination */
+	uint64_t dqsn_ena                     : 1;  /**< For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                              0 - DQSN Enable
+                                                              1 - DQSN Disable */
+	uint64_t dic                          : 1;  /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                              0 = Normal
+                                                              1 = Reduced */
+	uint64_t r2r_slot                     : 1;  /**< A 1 on this register will force the controller to
+                                                         slot a bubble between every reads */
+	uint64_t tfaw                         : 5;  /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in
+                                                         8-bank parts.
+                                                              TFAW = 5'b0 for DDR2-4bank
+                                                              TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
+	uint64_t twtr                         : 4;  /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 1
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1000-1111: RESERVED */
+	uint64_t twr                          : 3;  /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / clkFreq)
+                                                         TYP=15ns
+                                                              - 000: RESERVED
+                                                              - 001: 2
+                                                              - 010: 3
+                                                              - 011: 4
+                                                              - 100: 5
+                                                              - 101: 6
+                                                              - 110-111: RESERVED */
+	uint64_t trp                          : 4;  /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 1
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1000-1111: RESERVED
+                                                         When using parts with 8 banks (DFA_CFG->MAX_BNK
+                                                         is 1), load tRP cycles + 1 into this register. */
+	uint64_t tras                         : 5;  /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=45ns
+                                                              - 00000-0001: RESERVED
+                                                              - 00010: 2
+                                                              - ...
+                                                              - 10100: 20
+                                                              - 10101-11111: RESERVED */
+	uint64_t trrd                         : 3;  /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in fclk cycles)
+                                                         For DDR2, TYP=7.5ns
+                                                             - 000: RESERVED
+                                                             - 001: 1 tCYC
+                                                             - 010: 2 tCYC
+                                                             - 011: 3 tCYC
+                                                             - 100: 4 tCYC
+                                                             - 101: 5 tCYC
+                                                             - 110-111: RESERVED */
+	uint64_t trcd                         : 4;  /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 2 (2 is the smallest value allowed)
+                                                              - 0002: 2
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1110-1111: RESERVED */
+	uint64_t addlat                       : 3;  /**< When in Posted CAS mode ADDLAT needs to be programmed
+                                                         to tRCD-1
+                                                               ADDLAT         \#additional latency cycles
+                                                                000              0
+                                                                001              1 (tRCD = 2 fclk's)
+                                                                010              2 (tRCD = 3 fclk's)
+                                                                011              3 (tRCD = 4 fclk's)
+                                                                100              4 (tRCD = 5 fclk's)
+                                                                101              5 (tRCD = 6 fclk's)
+                                                                110              6 (tRCD = 7 fclk's)
+                                                                111              7 (tRCD = 8 fclk's) */
+	uint64_t pocas                        : 1;  /**< Posted CAS mode. When 1, we use DDR2's Posted CAS
+                                                         feature. When using this mode, ADDLAT needs to be
+                                                         programmed as well */
+	uint64_t caslat                       : 3;  /**< CAS Latency in \# fclk Cycles
+                                                         CASLAT           \#  CAS latency cycles
+                                                          000 - 010           RESERVED
+                                                          011                    3
+                                                          100                    4
+                                                          101                    5
+                                                          110                    6
+                                                          111                    7 */
+	uint64_t tmrd                         : 2;  /**< tMRD Cycles
+                                                         (Represented in fclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3 */
+	uint64_t ddr2t                        : 1;  /**< When 2T mode is turned on, command signals are
+                                                         setup a cycle ahead of when the CS is enabled
+                                                         and kept for a total of 2 cycles. This mode is
+                                                         enabled in higher speeds when there is difficulty
+                                                         meeting setup. Performance could
+                                                         be negatively affected in 2T mode */
+#else
+	uint64_t ddr2t                        : 1;
+	uint64_t tmrd                         : 2;
+	uint64_t caslat                       : 3;
+	uint64_t pocas                        : 1;
+	uint64_t addlat                       : 3;
+	uint64_t trcd                         : 4;
+	uint64_t trrd                         : 3;
+	uint64_t tras                         : 5;
+	uint64_t trp                          : 4;
+	uint64_t twr                          : 3;
+	uint64_t twtr                         : 4;
+	uint64_t tfaw                         : 5;
+	uint64_t r2r_slot                     : 1;
+	uint64_t dic                          : 1;
+	uint64_t dqsn_ena                     : 1;
+	uint64_t odt_rtt                      : 2;
+	uint64_t ctr_rst                      : 1;
+	uint64_t cavmipo                      : 1;
+	uint64_t cnt_clr                      : 1;
+	uint64_t fcnt_mode                    : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfa_ddr2_tmg_s            cn31xx;
+};
+typedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t;
+
+/**
+ * cvmx_dfa_debug0
+ *
+ * DFA_DEBUG0 = DFA Scoreboard Debug \#0 Register
+ * *FOR INTERNAL USE ONLY*
+ * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_debug0
+{
+	uint64_t u64;
+	struct cvmx_dfa_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd0                         : 64; /**< DFA ScoreBoard \#0 Data
+                                                         (DFA Scoreboard Debug)
+                                                            [63:38]   (26) rptr[28:3]: Result Base Pointer (QW-aligned)
+                                                            [37:22]   (16) Cumulative Result Write Counter (for HDR write)
+                                                            [21]       (1) Waiting for GRdRsp EOT
+                                                            [20]       (1) Waiting for GRdReq Issue (to NRQ)
+                                                            [19]       (1) GLPTR/GLCNT Valid
+                                                            [18]       (1) Completion Mark Detected
+                                                            [17:15]    (3) Completion Code [0=PDGONE/1=PERR/2=RFULL/3=TERM]
+                                                            [14]       (1) Completion Detected
+                                                            [13]       (1) Waiting for HDR RWrCmtRsp
+                                                            [12]       (1) Waiting for LAST RESULT RWrCmtRsp
+                                                            [11]       (1) Waiting for HDR RWrReq
+                                                            [10]        (1) Waiting for RWrReq
+                                                            [9]        (1) Waiting for WQWrReq issue
+                                                            [8]        (1) Waiting for PRdRsp EOT
+                                                            [7]        (1) Waiting for PRdReq Issue (to NRQ)
+                                                            [6]        (1) Packet Data Valid
+                                                            [5]        (1) WQVLD
+                                                            [4]        (1) WQ Done Point (either WQWrReq issued (for WQPTR<>0) OR HDR RWrCmtRsp)
+                                                            [3]        (1) Resultant write STF/P Mode
+                                                            [2]        (1) Packet Data LDT mode
+                                                            [1]        (1) Gather Mode
+                                                            [0]        (1) Valid */
+#else
+	uint64_t sbd0                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_debug0_s              cn63xx;
+	struct cvmx_dfa_debug0_s              cn63xxp1;
+};
+typedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t;
+
+/**
+ * cvmx_dfa_debug1
+ *
+ * DFA_DEBUG1 = DFA Scoreboard Debug \#1 Register
+ * *FOR INTERNAL USE ONLY*
+ * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_debug1
+{
+	uint64_t u64;
+	struct cvmx_dfa_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd1                         : 64; /**< DFA ScoreBoard \#1 Data
+                                                         DFA Scoreboard Debug Data
+                                                            [63:56]   (8) UNUSED
+                                                            [55:16]  (40) Packet Data Pointer
+                                                            [15:0]   (16) Packet Data Counter */
+#else
+	uint64_t sbd1                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_debug1_s              cn63xx;
+	struct cvmx_dfa_debug1_s              cn63xxp1;
+};
+typedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t;
+
+/**
+ * cvmx_dfa_debug2
+ *
+ * DFA_DEBUG2 = DFA Scoreboard Debug \#2 Register
+ *
+ * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_debug2
+{
+	uint64_t u64;
+	struct cvmx_dfa_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd2                         : 64; /**< DFA ScoreBoard \#2 Data
+                                                         [63:45] (19) UNUSED
+                                                         [44:42]  (3) Instruction Type
+                                                         [41:5]  (37) rwptr[39:3]: Result Write Pointer
+                                                         [4:0]    (5) prwcnt[4:0]: Pending Result Write Counter */
+#else
+	uint64_t sbd2                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_debug2_s              cn63xx;
+	struct cvmx_dfa_debug2_s              cn63xxp1;
+};
+typedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t;
+
+/**
+ * cvmx_dfa_debug3
+ *
+ * DFA_DEBUG3 = DFA Scoreboard Debug \#3 Register
+ *
+ * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_debug3
+{
+	uint64_t u64;
+	struct cvmx_dfa_debug3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd3                         : 64; /**< DFA ScoreBoard \#3 Data
+                                                         [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned)
+                                                         [52:16] (37) glptr[39:3]: Gather List Pointer
+                                                         [15:0]  (16) glcnt Gather List Counter */
+#else
+	uint64_t sbd3                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_debug3_s              cn63xx;
+	struct cvmx_dfa_debug3_s              cn63xxp1;
+};
+typedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t;
+
+/**
+ * cvmx_dfa_difctl
+ *
+ * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register
+ *
+ * Description:
+ *  NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b110.
+ *        To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b110.
+ *
+ *  NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could
+ *  cause the DFA and FPA HW to become unpredictable.
+ *
+ *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect.
+ *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect.
+ */
+union cvmx_dfa_difctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_difctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwbcnt                       : 8;  /**< Represents the \# of cache lines in the instruction
+                                                         buffer that may be dirty and should not be
+                                                         written-back to memory when the instruction
+                                                         chunk is returned to the Free Page list.
+                                                         NOTE: Typically SW will want to mark all DFA
+                                                         Instruction memory returned to the Free Page list
+                                                         as DWB (Don't WriteBack), therefore SW should
+                                                         seed this register as:
+                                                           DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */
+	uint64_t pool                         : 3;  /**< Represents the 3bit buffer pool-id  used by DFA HW
+                                                         when the DFA instruction chunk is recycled back
+                                                         to the Free Page List maintained by the FPA HW
+                                                         (once the DFA instruction has been issued). */
+	uint64_t size                         : 9;  /**< Represents the \# of 32B instructions contained
+                                                         within each DFA instruction chunk. At Power-on,
+                                                         SW will seed the SIZE register with a fixed
+                                                         chunk-size. (Must be at least 3)
+                                                         DFA HW uses this field to determine the size
+                                                         of each DFA instruction chunk, in order to:
+                                                            a) determine when to read the next DFA
+                                                               instruction chunk pointer which is
+                                                               written by SW at the end of the current
+                                                               DFA instruction chunk (see DFA description
+                                                               of next chunk buffer Ptr for format).
+                                                            b) determine when a DFA instruction chunk
+                                                               can be returned to the Free Page List
+                                                               maintained by the FPA HW. */
+#else
+	uint64_t size                         : 9;
+	uint64_t pool                         : 3;
+	uint64_t dwbcnt                       : 8;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_dfa_difctl_s              cn31xx;
+	struct cvmx_dfa_difctl_s              cn38xx;
+	struct cvmx_dfa_difctl_s              cn38xxp2;
+	struct cvmx_dfa_difctl_s              cn58xx;
+	struct cvmx_dfa_difctl_s              cn58xxp1;
+	struct cvmx_dfa_difctl_s              cn63xx;
+	struct cvmx_dfa_difctl_s              cn63xxp1;
+};
+typedef union cvmx_dfa_difctl cvmx_dfa_difctl_t;
+
+/**
+ * cvmx_dfa_difrdptr
+ *
+ * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register
+ *
+ * Description:
+ *  NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01.
+ *        To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01.
+ *
+ *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect.
+ *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect.
+ */
+union cvmx_dfa_difrdptr
+{
+	uint64_t u64;
+	struct cvmx_dfa_difrdptr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t rdptr                        : 35; /**< Represents the 32B-aligned address of the current
+                                                         instruction in the DFA Instruction FIFO in main
+                                                         memory. The RDPTR must be seeded by software at
+                                                         boot time, and is then maintained thereafter
+                                                         by DFA HW.
+                                                         During the seed write (by SW), RDPTR[6:5]=0,
+                                                         since DFA instruction chunks must be 128B aligned.
+                                                         During a read (by SW), the 'most recent' contents
+                                                         of the RDPTR register are returned at the time
+                                                         the NCB-INB bus is driven.
+                                                         NOTE: Since DFA HW updates this register, its
+                                                         contents are unpredictable in SW (unless
+                                                         its guaranteed that no new DoorBell register
+                                                         writes have occurred and the DoorBell register is
+                                                         read as zero). */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t rdptr                        : 35;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_dfa_difrdptr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t rdptr                        : 31; /**< Represents the 32B-aligned address of the current
+                                                         instruction in the DFA Instruction FIFO in main
+                                                         memory. The RDPTR must be seeded by software at
+                                                         boot time, and is then maintained thereafter
+                                                         by DFA HW.
+                                                         During the seed write (by SW), RDPTR[6:5]=0,
+                                                         since DFA instruction chunks must be 128B aligned.
+                                                         During a read (by SW), the 'most recent' contents
+                                                         of the RDPTR register are returned at the time
+                                                         the NCB-INB bus is driven.
+                                                         NOTE: Since DFA HW updates this register, its
+                                                         contents are unpredictable in SW (unless
+                                                         its guaranteed that no new DoorBell register
+                                                         writes have occurred and the DoorBell register is
+                                                         read as zero). */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t rdptr                        : 31;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_dfa_difrdptr_cn31xx       cn38xx;
+	struct cvmx_dfa_difrdptr_cn31xx       cn38xxp2;
+	struct cvmx_dfa_difrdptr_cn31xx       cn58xx;
+	struct cvmx_dfa_difrdptr_cn31xx       cn58xxp1;
+	struct cvmx_dfa_difrdptr_s            cn63xx;
+	struct cvmx_dfa_difrdptr_s            cn63xxp1;
+};
+typedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t;
+
+/**
+ * cvmx_dfa_dtcfadr
+ *
+ * DFA_DTCFADR = DFA DTC Failing Address Register
+ *
+ * Description: DFA Node Cache Failing Address/Control Error Capture information
+ * This register contains useful information to help in isolating a Node Cache RAM failure.
+ * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the
+ * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]).
+ */
+union cvmx_dfa_dtcfadr
+{
+	uint64_t u64;
+	struct cvmx_dfa_dtcfadr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t ram3fadr                     : 12; /**< DFA RAM3 Failing Address
+                                                         If DFA_ERR[DC0PERR<2>]=1, this field indicates the
+                                                         failing RAM3 Address. The failing address is locked
+                                                         down until the DC0PERR<2> W1C occurs. */
+	uint64_t reserved_25_31               : 7;
+	uint64_t ram2fadr                     : 9;  /**< DFA RAM2 Failing Address
+                                                         If DFA_ERR[DC0PERR<1>]=1, this field indicates the
+                                                         failing RAM2 Address. The failing address is locked
+                                                         down until the DC0PERR<1> W1C occurs. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t ram1fadr                     : 14; /**< DFA RAM1 Failing Address
+                                                         If DFA_ERR[DC0PERR<0>]=1, this field indicates the
+                                                         failing RAM1 Address. The failing address is locked
+                                                         down until the DC0PERR<0> W1C occurs. */
+#else
+	uint64_t ram1fadr                     : 14;
+	uint64_t reserved_14_15               : 2;
+	uint64_t ram2fadr                     : 9;
+	uint64_t reserved_25_31               : 7;
+	uint64_t ram3fadr                     : 12;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_dfa_dtcfadr_s             cn63xx;
+	struct cvmx_dfa_dtcfadr_s             cn63xxp1;
+};
+typedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t;
+
+/**
+ * cvmx_dfa_eclkcfg
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  DFA_ECLKCFG = DFA eclk-domain Configuration Registers
+ *
+ * Description:
+ */
+union cvmx_dfa_eclkcfg
+{
+	uint64_t u64;
+	struct cvmx_dfa_eclkcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t sbdnum                       : 3;  /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 8 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+	uint64_t reserved_15_15               : 1;
+	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+	uint64_t dcmode                       : 1;  /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t dtmode                       : 1;  /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t pmode                        : 1;  /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t qmode                        : 1;  /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t imode                        : 1;  /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t sarb                         : 1;  /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA requests
+                                                         issued from either CP2 or the DTE (NCB-CSR or DFA HW engine).
+                                                          - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                          - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t dteclkdis                    : 1;  /**< DFA DTE Clock Disable
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled.
+                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
+                                                         the DFA via the NCB Bus. All DFA Operations must be
+                                                         issued solely through the CP2 interface. */
+	uint64_t maxbnk                       : 1;  /**< Maximum Banks per-device (used by the address mapper
+                                                         when extracting address bits for the memory bank#.
+                                                                 - 0: 4 banks/device
+                                                                 - 1: 8 banks/device */
+	uint64_t dfa_frstn                    : 1;  /**< Hold this 0 until the DFA DDR PLL and DLL lock
+                                                         and then write a 1. A 1 on this register deasserts
+                                                         the internal frst_n. Refer to DFA_DDR2_PLL registers for more
+                                                         startup information.
+                                                         Startup sequence if DFA interface needs to be ON:
+                                                          After valid power up,
+                                                          Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS
+                                                          to the appropriate values
+                                                          Wait a few cycles
+                                                          Write a 1 DFA_DDR2_PLL -> PLL_INIT
+                                                          Wait 100 microseconds
+                                                          Write a 1 to DFA_DDR2_PLL -> QDLL_ENA
+                                                          Wait 10 microseconds
+                                                          Write a 1 to this register DFA_FRSTN to pull DFA out of
+                                                          reset
+                                                          Now the DFA block is ready to be initialized (follow the
+                                                          DDR init sequence). */
+#else
+	uint64_t dfa_frstn                    : 1;
+	uint64_t maxbnk                       : 1;
+	uint64_t dteclkdis                    : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t sarb                         : 1;
+	uint64_t imode                        : 1;
+	uint64_t qmode                        : 1;
+	uint64_t pmode                        : 1;
+	uint64_t dtmode                       : 1;
+	uint64_t dcmode                       : 1;
+	uint64_t sbdlck                       : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t sbdnum                       : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_dfa_eclkcfg_s             cn31xx;
+};
+typedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t;
+
+/**
+ * cvmx_dfa_err
+ *
+ * DFA_ERR = DFA ERROR Register
+ *
+ * Description:
+ */
+union cvmx_dfa_err
+{
+	uint64_t u64;
+	struct cvmx_dfa_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
+                                                         When set, doorbell overflow conditions are reported. */
+	uint64_t dblovf                       : 1;  /**< Doorbell Overflow detected - Status bit
+                                                         When set, the 20b accumulated doorbell register
+                                                         had overflowed (SW wrote too many doorbell requests).
+                                                         If the DBLINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         NOTE: Detection of a Doorbell Register overflow
+                                                         is a catastrophic error which may leave the DFA
+                                                         HW in an unrecoverable state. */
+	uint64_t cp2pina                      : 1;  /**< CP2 LW Mode Parity Error Interrupt Enable bit.
+                                                         When set, all PP-generated LW Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 36b of data) are reported. */
+	uint64_t cp2perr                      : 1;  /**< PP-CP2 Parity Error Detected - Status bit
+                                                         When set, a parity error had been detected for a
+                                                         PP-generated LW Mode read transaction.
+                                                         If the CP2PINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+	uint64_t cp2parena                    : 1;  /**< CP2 LW Mode Parity Error Enable
+                                                         When set, all PP-generated LW Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 36b of data) are reported.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no PP-CP2 transactions
+                                                         (preferrably during power-on software initialization). */
+	uint64_t dtepina                      : 1;  /**< DTE Parity Error Interrupt Enable bit
+                                                         (for 18b SIMPLE mode ONLY).
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported. */
+	uint64_t dteperr                      : 1;  /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY)
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported. */
+	uint64_t dteparena                    : 1;  /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY)
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no DFA thread engines active
+                                                         (preferrably during power-on). */
+	uint64_t dtesyn                       : 7;  /**< DTE 29b ECC Failing 6bit Syndrome
+                                                         When DTESBE or DTEDBE are set, this field contains
+                                                         the failing 7b ECC syndrome. */
+	uint64_t dtedbina                     : 1;  /**< DTE 29b Double Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any DTE-generated
+                                                         36b SIMPLE Mode read which encounters a double bit
+                                                         error. */
+	uint64_t dtesbina                     : 1;  /**< DTE 29b Single Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any DTE-generated
+                                                         36b SIMPLE Mode read which encounters a single bit
+                                                         error (which is also corrected). */
+	uint64_t dtedbe                       : 1;  /**< DTE 29b Double Bit Error Detected - Status bit
+                                                         When set, a double bit error had been detected
+                                                         for a DTE-generated 36b SIMPLE Mode read transaction.
+                                                         The DTESYN contains the failing syndrome.
+                                                         If the DTEDBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure.
+                                                         NOTE: DTE-generated 18b SIMPLE Mode Read transactions
+                                                         do not participate in ECC check/correct). */
+	uint64_t dtesbe                       : 1;  /**< DTE 29b Single Bit Error Corrected - Status bit
+                                                         When set, a single bit error had been detected and
+                                                         corrected for a DTE-generated 36b SIMPLE Mode read
+                                                         transaction.
+                                                         If the DTEDBE=0, then the DTESYN contains the
+                                                         failing syndrome (used during correction).
+                                                         NOTE: DTE-generated 18b SIMPLE Mode Read
+                                                         transactions do not participate in ECC check/correct).
+                                                         If the DTESBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+	uint64_t dteeccena                    : 1;  /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY)
+                                                         When set, 29b ECC is enabled on all DTE-generated
+                                                         36b SIMPLE Mode read transactions.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no DFA thread engines active
+                                                         (preferrably during power-on software initialization). */
+	uint64_t cp2syn                       : 8;  /**< PP-CP2 QW ECC Failing 8bit Syndrome
+                                                         When CP2SBE or CP2DBE are set, this field contains
+                                                         the failing ECC 8b syndrome.
+                                                         Refer to CP2ECCENA. */
+	uint64_t cp2dbina                     : 1;  /**< PP-CP2 Double Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any PP-generated
+                                                         QW Mode read which encounters a double bit error.
+                                                         Refer to CP2DBE. */
+	uint64_t cp2sbina                     : 1;  /**< PP-CP2 Single Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any PP-generated
+                                                         QW Mode read which encounters a single bit error
+                                                         (which is also corrected).
+                                                         Refer to CP2SBE. */
+	uint64_t cp2dbe                       : 1;  /**< PP-CP2 Double Bit Error Detected - Status bit
+                                                         When set, a double bit error had been detected
+                                                         for a PP-generated QW Mode read transaction.
+                                                         The CP2SYN contains the failing syndrome.
+                                                          NOTE: PP-generated LW Mode Read transactions
+                                                         do not participate in ECC check/correct).
+                                                         Refer to CP2ECCENA.
+                                                         If the CP2DBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+	uint64_t cp2sbe                       : 1;  /**< PP-CP2 Single Bit Error Corrected - Status bit
+                                                         When set, a single bit error had been detected and
+                                                         corrected for a PP-generated QW Mode read
+                                                         transaction.
+                                                         If the CP2DBE=0, then the CP2SYN contains the
+                                                         failing syndrome (used during correction).
+                                                         Refer to CP2ECCENA.
+                                                         If the CP2SBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure.
+                                                         NOTE: PP-generated LW Mode Read transactions
+                                                         do not participate in ECC check/correct). */
+	uint64_t cp2eccena                    : 1;  /**< PP-CP2 QW ECC Enable (for QW Mode transactions)
+                                                         When set, 8bit QW ECC is enabled on all PP-generated
+                                                         QW Mode read transactions, CP2SBE and
+                                                         CP2DBE may be set, and CP2SYN may be filled.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no PP-CP2 transactions
+                                                         (preferrably during power-on software initialization).
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store. */
+#else
+	uint64_t cp2eccena                    : 1;
+	uint64_t cp2sbe                       : 1;
+	uint64_t cp2dbe                       : 1;
+	uint64_t cp2sbina                     : 1;
+	uint64_t cp2dbina                     : 1;
+	uint64_t cp2syn                       : 8;
+	uint64_t dteeccena                    : 1;
+	uint64_t dtesbe                       : 1;
+	uint64_t dtedbe                       : 1;
+	uint64_t dtesbina                     : 1;
+	uint64_t dtedbina                     : 1;
+	uint64_t dtesyn                       : 7;
+	uint64_t dteparena                    : 1;
+	uint64_t dteperr                      : 1;
+	uint64_t dtepina                      : 1;
+	uint64_t cp2parena                    : 1;
+	uint64_t cp2perr                      : 1;
+	uint64_t cp2pina                      : 1;
+	uint64_t dblovf                       : 1;
+	uint64_t dblina                       : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_dfa_err_s                 cn31xx;
+	struct cvmx_dfa_err_s                 cn38xx;
+	struct cvmx_dfa_err_s                 cn38xxp2;
+	struct cvmx_dfa_err_s                 cn58xx;
+	struct cvmx_dfa_err_s                 cn58xxp1;
+};
+typedef union cvmx_dfa_err cvmx_dfa_err_t;
+
+/**
+ * cvmx_dfa_error
+ *
+ * DFA_ERROR = DFA ERROR Register
+ *
+ * Description:
+ */
+union cvmx_dfa_error
+{
+	uint64_t u64;
+	struct cvmx_dfa_error_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t cndrd                        : 1;  /**< If DC0PERR[0]=1 indicating a RAM1 Parity error,
+                                                         this additional bit further specifies that the
+                                                         RAM1 parity error was detected during a CND-RD
+                                                         (Cache Node Metadata Read).
+
+                                                         For CNDRD Parity Error, the previous CNA arc fetch
+                                                         information is written to RWORD1+ as follows:
+                                                            RWORD1+[NTYPE]=MNODE
+                                                            RWORD1+[NDNID]=cna.ndnid
+                                                            RWORD1+[NHMSK]=cna.hmsk
+                                                            RWORD1+[NNPTR]=cna.nnptr[13:0] */
+	uint64_t reserved_4_15                : 12;
+	uint64_t dc0perr                      : 3;  /**< RAM[3:1] Parity Error Detected from Node Cluster \#0
+                                                         See also DFA_DTCFADR register which contains the
+                                                         failing addresses for the internal node cache RAMs. */
+	uint64_t dblovf                       : 1;  /**< Doorbell Overflow detected - Status bit
+                                                         When set, the 20b accumulated doorbell register
+                                                         had overflowed (SW wrote too many doorbell requests).
+                                                         If the DBLINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         NOTE: Detection of a Doorbell Register overflow
+                                                         is a catastrophic error which may leave the DFA
+                                                         HW in an unrecoverable state. */
+#else
+	uint64_t dblovf                       : 1;
+	uint64_t dc0perr                      : 3;
+	uint64_t reserved_4_15                : 12;
+	uint64_t cndrd                        : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_dfa_error_s               cn63xx;
+	struct cvmx_dfa_error_s               cn63xxp1;
+};
+typedef union cvmx_dfa_error cvmx_dfa_error_t;
+
+/**
+ * cvmx_dfa_intmsk
+ *
+ * DFA_INTMSK = DFA ERROR Interrupt Mask Register
+ *
+ * Description:
+ */
+union cvmx_dfa_intmsk
+{
+	uint64_t u64;
+	struct cvmx_dfa_intmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t dc0pena                      : 3;  /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */
+	uint64_t dblina                       : 1;  /**< Doorbell Overflow Interrupt Enable bit.
+                                                         When set, doorbell overflow conditions are reported. */
+#else
+	uint64_t dblina                       : 1;
+	uint64_t dc0pena                      : 3;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_dfa_intmsk_s              cn63xx;
+	struct cvmx_dfa_intmsk_s              cn63xxp1;
+};
+typedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t;
+
+/**
+ * cvmx_dfa_memcfg0
+ *
+ * DFA_MEMCFG0 = DFA Memory Configuration
+ *
+ * Description:
+ */
+union cvmx_dfa_memcfg0
+{
+	uint64_t u64;
+	struct cvmx_dfa_memcfg0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rldqck90_rst                 : 1;  /**< RLDCK90 and RLDQK90 DLL SW Reset
+                                                         When written with a '1' the RLDCK90 and RLDQK90 DLL are
+                                                         in soft-reset. */
+	uint64_t rldck_rst                    : 1;  /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset
+                                                         When written with a '1' the RLDCK zero delay DLL is in
+                                                         soft-reset. */
+	uint64_t clkdiv                       : 2;  /**< RLDCLK Divisor Select
+                                                           - 0: RLDx_CK_H/L = Core Clock /2
+                                                           - 1: RESERVED (must not be used)
+                                                           - 2: RLDx_CK_H/L = Core Clock /3
+                                                           - 3: RLDx_CK_H/L = Core Clock /4
+                                                         The DFA LLM interface(s) are tied to the core clock
+                                                         frequency through this programmable clock divisor.
+                                                         Examples:
+                                                            Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV
+                                                           -----------------+--------------------+--------
+                                                                 800        |    400/(800-DDR)   |  /2
+                                                                1000        |    333/(666-DDR)   |  /3
+                                                                 800        |    200/(400-DDR)   |  /4
+                                                         NOTE: This value MUST BE programmed BEFORE doing a
+                                                         Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits). */
+	uint64_t lpp_ena                      : 1;  /**< PP Linear Port Addressing Mode Enable
+                                                         When enabled, PP-core LLM accesses to the lower-512MB
+                                                         LLM address space are sent to the single DFA port
+                                                         which is enabled. NOTE: If LPP_ENA=1, only
+                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
+                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
+                                                         PP-core LLM accesses to the upper-512MB LLM address
+                                                         space are sent to the other 'disabled' DFA port.
+                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
+                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
+                                                         ENA_P1 CAN NEVER BOTH be set).
+                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
+                                                         disabled port, such that each port can be sequentially
+                                                         addressed (ie: disable LW address interleaving).
+                                                         Enabling this bit allows BOTH PORTs to be active and
+                                                         sequentially addressable. The single port that is
+                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
+                                                         space, and the other 'disabled' port will respond to the
+                                                         high-512MB LLM address space.
+                                                         Example usage:
+                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
+                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
+                                                         USAGE NOTE:
+                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
+                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
+                                                         sequence WILL NOT occur for the disabled port.
+                                                         If LPP_ENA=1 and SW does initialize the disabled port
+                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
+                                                         the HW init sequence WILL occur to the disabled port. */
+	uint64_t bunk_init                    : 2;  /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t init_p0                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
+                                                              RLDRAM operation.
+                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
+                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
+                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
+                                                              the SAME TIME. This step puts all three DLLs in
+                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
+                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
+                                                              This step takes the RLDCK DLL out of soft-reset so
+                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
+                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
+                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
+                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
+                                                              of soft-reset.
+                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
+                                                           7) Enable memory port(s):  ENA_P0=1/ENA_P1=1
+                                                           8) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
+                                                              intended to be initialized.
+                                                          10) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence to that'specific' port.
+                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
+                                                              [to ensure the HW init sequence has completed
+                                                              before writing to ANY of the DFA_MEM* registers]
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
+                                                              refreshes to BOTH bunks.
+                                                         NOTE: In some cases (where the address wires are routed
+                                                         differently between the front and back 'bunks'),
+                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
+                                                         control the Hardware initialization sequence for a
+                                                         'specific bunk'. In these cases, SW would setup the
+                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t init_p1                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
+                                                              RLDRAM operation.
+                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
+                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
+                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
+                                                              the SAME TIME. This step puts all three DLLs in
+                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
+                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
+                                                              This step takes the RLDCK DLL out of soft-reset so
+                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
+                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
+                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
+                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
+                                                              of soft-reset.
+                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
+                                                           7) Enable memory port(s) ENA_P0=1/ENA_P1=1
+                                                           8) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
+                                                              intended to be initialized.
+                                                          10) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence to that'specific' port.
+                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
+                                                              [to ensure the HW init sequence has completed
+                                                              before writing to ANY of the DFA_MEM* registers]
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
+                                                              refreshes to BOTH bunks.
+                                                         NOTE: In some cases (where the address wires are routed
+                                                         differently between the front and back 'bunks'),
+                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
+                                                         control the Hardware initialization sequence for a
+                                                         'specific bunk'. In these cases, SW would setup the
+                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+	uint64_t r2r_pbunk                    : 1;  /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t pbunk                        : 3;  /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s). */
+	uint64_t blen                         : 1;  /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */
+	uint64_t bprch                        : 2;  /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t fprch                        : 2;  /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t wr_dly                       : 4;  /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+	uint64_t rw_dly                       : 4;  /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+	uint64_t sil_lat                      : 2;  /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t mtype                        : 1;  /**< FCRAM-II Memory Type
+                                                         *** CN58XX UNSUPPORTED *** */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ena_p0                       : 1;  /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: a customer is at
+                                                         liberty to enable either Port#0 or Port#1 or both.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t ena_p1                       : 1;  /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: a customer is at
+                                                         liberty to enable either Port#0 or Port#1 or both.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+	uint64_t ena_p1                       : 1;
+	uint64_t ena_p0                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mtype                        : 1;
+	uint64_t sil_lat                      : 2;
+	uint64_t rw_dly                       : 4;
+	uint64_t wr_dly                       : 4;
+	uint64_t fprch                        : 2;
+	uint64_t bprch                        : 2;
+	uint64_t blen                         : 1;
+	uint64_t pbunk                        : 3;
+	uint64_t r2r_pbunk                    : 1;
+	uint64_t init_p1                      : 1;
+	uint64_t init_p0                      : 1;
+	uint64_t bunk_init                    : 2;
+	uint64_t lpp_ena                      : 1;
+	uint64_t clkdiv                       : 2;
+	uint64_t rldck_rst                    : 1;
+	uint64_t rldqck90_rst                 : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_dfa_memcfg0_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lpp_ena                      : 1;  /**< PP Linear Port Addressing Mode Enable
+                                                         When enabled, PP-core LLM accesses to the lower-512MB
+                                                         LLM address space are sent to the single DFA port
+                                                         which is enabled. NOTE: If LPP_ENA=1, only
+                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
+                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
+                                                         PP-core LLM accesses to the upper-512MB LLM address
+                                                         space are sent to the other 'disabled' DFA port.
+                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
+                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
+                                                         ENA_P1 CAN NEVER BOTH be set).
+                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
+                                                         disabled port, such that each port can be sequentially
+                                                         addressed (ie: disable LW address interleaving).
+                                                         Enabling this bit allows BOTH PORTs to be active and
+                                                         sequentially addressable. The single port that is
+                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
+                                                         space, and the other 'disabled' port will respond to the
+                                                         high-512MB LLM address space.
+                                                         Example usage:
+                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
+                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
+                                                         USAGE NOTE:
+                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
+                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
+                                                         sequence WILL NOT occur for the disabled port.
+                                                         If LPP_ENA=1 and SW does initialize the disabled port
+                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
+                                                         the HW init sequence WILL occur to the disabled port. */
+	uint64_t bunk_init                    : 2;  /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
+                                                         initialized independently. In other words, a HW init
+                                                         must be done for Bunk#0, and then another HW init
+                                                         must be done for Bunk#1 at power-on. */
+	uint64_t init_p0                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t init_p1                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+	uint64_t r2r_pbunk                    : 1;  /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
+                                                         ZERO(for optimal performance). However, if electrically,
+                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
+                                                         should be set (but at a cost to performance (1/2 BW). */
+	uint64_t pbunk                        : 3;  /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s).
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
+                                                         "Redundant Bunk" scheme is employed to provide the
+                                                         highest overall performance (1 Req/ MCLK cycle).
+                                                         In this mode, it's imperative that SW set the PBUNK
+                                                         field +1 'above' the highest address bit. (such that
+                                                         the PBUNK extracted from the address will always be
+                                                         zero). In this mode, the CS_N[1:0] pins are driven
+                                                         to each redundant bunk based on a TDM scheme:
+                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
+	uint64_t blen                         : 1;  /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
+                                                         decomposed into 2 separate BL2(LW) requests to the
+                                                         Low-Latency memory.
+                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
+                                                         treated as 1 BL4(QW) request to the low latency memory.
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization before the DFA LLM
+                                                         (low latency memory) is used.
+                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
+                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
+                                                         multi-bunk(clam) board design.
+                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
+                                                         SW SHOULD use CP2 QW read/write requests (for
+                                                         optimal low-latency bus performance).
+                                                         [LW length read/write requests(in BL4 mode) use 50%
+                                                         of the available bus bandwidth]
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
+                                                         be used with FCRAM-II devices which support BL2 mode
+                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
+                                                         transfers).
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
+                                                         write requests (FCRAM-II+ device specification has removed
+                                                         the variable write mask function from the devices).
+                                                         As such, if this mode is used, SW must be careful to
+                                                         issue only PP-CP2 QW write requests. */
+	uint64_t bprch                        : 2;  /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t fprch                        : 2;  /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t wr_dly                       : 4;  /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
+                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
+                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
+                                                            grepl>=2x, writes require redundant bunk writes
+                                                            which require an additional 2 cycles before slotting
+                                                            the next read.
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+	uint64_t rw_dly                       : 4;  /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+	uint64_t sil_lat                      : 2;  /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t mtype                        : 1;  /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
+                                                         NOTE: N3K-P1 only supports RLDRAM-II
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
+                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
+                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
+                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
+                                                         in a clamshell configuration such that clam0 is
+                                                         addressed independently of clam1, and DQ is shared
+                                                         for optimal performance. As such it's imperative that
+                                                         the QS are conditionally received (and are NOT
+                                                         free-running), as the N3K receive data capture silos
+                                                         OR the clam0/1 QS strobes.
+                                                         NOTE: If this bit is SET, the ASX0/1
+                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
+                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ena_p0                       : 1;  /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
+                                                         Port#1 MUST ALSO be enabled.
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t ena_p1                       : 1;  /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: For N3K-P1, If the customer wishes to use a
+                                                         single port, s/he must enable Port#1 (and not Port#0).
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+	uint64_t ena_p1                       : 1;
+	uint64_t ena_p0                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mtype                        : 1;
+	uint64_t sil_lat                      : 2;
+	uint64_t rw_dly                       : 4;
+	uint64_t wr_dly                       : 4;
+	uint64_t fprch                        : 2;
+	uint64_t bprch                        : 2;
+	uint64_t blen                         : 1;
+	uint64_t pbunk                        : 3;
+	uint64_t r2r_pbunk                    : 1;
+	uint64_t init_p1                      : 1;
+	uint64_t init_p0                      : 1;
+	uint64_t bunk_init                    : 2;
+	uint64_t lpp_ena                      : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn38xx;
+	struct cvmx_dfa_memcfg0_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t bunk_init                    : 2;  /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
+                                                         initialized independently. In other words, a HW init
+                                                         must be done for Bunk#0, and then another HW init
+                                                         must be done for Bunk#1 at power-on. */
+	uint64_t init_p0                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t init_p1                      : 1;  /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+	uint64_t r2r_pbunk                    : 1;  /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
+                                                         ZERO(for optimal performance). However, if electrically,
+                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
+                                                         should be set (but at a cost to performance (1/2 BW). */
+	uint64_t pbunk                        : 3;  /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s).
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
+                                                         "Redundant Bunk" scheme is employed to provide the
+                                                         highest overall performance (1 Req/ MCLK cycle).
+                                                         In this mode, it's imperative that SW set the PBUNK
+                                                         field +1 'above' the highest address bit. (such that
+                                                         the PBUNK extracted from the address will always be
+                                                         zero). In this mode, the CS_N[1:0] pins are driven
+                                                         to each redundant bunk based on a TDM scheme:
+                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
+	uint64_t blen                         : 1;  /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
+                                                         decomposed into 2 separate BL2(LW) requests to the
+                                                         Low-Latency memory.
+                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
+                                                         treated as 1 BL4(QW) request to the low latency memory.
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization before the DFA LLM
+                                                         (low latency memory) is used.
+                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
+                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
+                                                         multi-bunk(clam) board design.
+                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
+                                                         SW SHOULD use CP2 QW read/write requests (for
+                                                         optimal low-latency bus performance).
+                                                         [LW length read/write requests(in BL4 mode) use 50%
+                                                         of the available bus bandwidth]
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
+                                                         be used with FCRAM-II devices which support BL2 mode
+                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
+                                                         transfers).
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
+                                                         write requests (FCRAM-II+ device specification has removed
+                                                         the variable write mask function from the devices).
+                                                         As such, if this mode is used, SW must be careful to
+                                                         issue only PP-CP2 QW write requests. */
+	uint64_t bprch                        : 2;  /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t fprch                        : 2;  /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t wr_dly                       : 4;  /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
+                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
+                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
+                                                            grepl>=2x, writes require redundant bunk writes
+                                                            which require an additional 2 cycles before slotting
+                                                            the next read.
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+	uint64_t rw_dly                       : 4;  /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+	uint64_t sil_lat                      : 2;  /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t mtype                        : 1;  /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
+                                                         NOTE: N3K-P1 only supports RLDRAM-II
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
+                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
+                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
+                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
+                                                         in a clamshell configuration such that clam0 is
+                                                         addressed independently of clam1, and DQ is shared
+                                                         for optimal performance. As such it's imperative that
+                                                         the QS are conditionally received (and are NOT
+                                                         free-running), as the N3K receive data capture silos
+                                                         OR the clam0/1 QS strobes.
+                                                         NOTE: If this bit is SET, the ASX0/1
+                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
+                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ena_p0                       : 1;  /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
+                                                         Port#1 MUST ALSO be enabled.
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+	uint64_t ena_p1                       : 1;  /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: For N3K-P1, If the customer wishes to use a
+                                                         single port, s/he must enable Port#1 (and not Port#0).
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+	uint64_t ena_p1                       : 1;
+	uint64_t ena_p0                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mtype                        : 1;
+	uint64_t sil_lat                      : 2;
+	uint64_t rw_dly                       : 4;
+	uint64_t wr_dly                       : 4;
+	uint64_t fprch                        : 2;
+	uint64_t bprch                        : 2;
+	uint64_t blen                         : 1;
+	uint64_t pbunk                        : 3;
+	uint64_t r2r_pbunk                    : 1;
+	uint64_t init_p1                      : 1;
+	uint64_t init_p0                      : 1;
+	uint64_t bunk_init                    : 2;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn38xxp2;
+	struct cvmx_dfa_memcfg0_s             cn58xx;
+	struct cvmx_dfa_memcfg0_s             cn58xxp1;
+};
+typedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t;
+
+/**
+ * cvmx_dfa_memcfg1
+ *
+ * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration
+ *
+ * Description:
+ */
+union cvmx_dfa_memcfg1
+{
+	uint64_t u64;
+	struct cvmx_dfa_memcfg1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ref_intlo                    : 9;  /**< Burst Refresh Interval[8:0] (\#dclks)
+                                                         For finer refresh interval granularity control.
+                                                         This field provides an additional level of granularity
+                                                         for the refresh interval. It specifies the additional
+                                                         \#dclks [0...511] to be added to the REF_INT[3:0] field.
+                                                         For RLDRAM-II: For dclk(400MHz=2.5ns):
+                                                         Example: 64K AREF cycles required within tREF=32ms
+                                                             trefint = tREF(ms)/(64K cycles/8banks)
+                                                                         = 32ms/8K = 3.9us = 3900ns
+                                                             REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512]
+                                                                          = ROUND_DOWN[(3900/2.5)/512]
+                                                                          = 3
+                                                             REF_INTLO[8:0] = MOD[(trefint/dclk)/512]
+                                                                            = MOD[(3900/2.5)/512]
+                                                                            = 24
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t aref_ena                     : 1;  /**< Auto Refresh Cycle Enable
+                                                         INTERNAL USE ONLY:
+                                                         NOTE: This mode bit is ONLY intended to be used by
+                                                         low-level power-on initialization routines in the
+                                                         event that the hardware initialization routine
+                                                         does not work. It allows SW to create AREF
+                                                         commands on the RLDRAM bus directly.
+                                                         When this bit is set, ALL RLDRAM writes (issued by
+                                                         a PP through the NCB or CP2) are converted to AREF
+                                                         commands on the RLDRAM bus. The write-address is
+                                                         presented on the A[20:0]/BA[2:0] pins (for which
+                                                         the RLDRAM only interprets BA[2:0]).
+                                                         When this bit is set, only writes are allowed
+                                                         and MUST use grepl=0 (1x).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
+                                                         (SW can set one or the other, but never both!)
+                                                         NOTE: AREF commands generated using this method target
+                                                         the 'addressed' bunk. */
+	uint64_t mrs_ena                      : 1;  /**< Mode Register Set Cycle Enable
+                                                         INTERNAL USE ONLY:
+                                                         NOTE: This mode bit is ONLY intended to be used by
+                                                         low-level power-on initialization routines in the
+                                                         event that the hardware initialization routine
+                                                         does not work. It allows SW to create MRS
+                                                         commands on the RLDRAM bus directly.
+                                                         When this bit is set, ALL RLDRAM writes (issued by
+                                                         a PP through the NCB or CP2) are converted to MRS
+                                                         commands on the RLDRAM bus. The write-address is
+                                                         presented on the A[20:0]/BA[2:0] pins (for which
+                                                         the RLDRAM only interprets A[17:0]).
+                                                         When this bit is set, only writes are allowed
+                                                         and MUST use grepl=0 (1x).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
+                                                         (SW can set one or the other, but never both!)
+                                                         NOTE: MRS commands generated using this method target
+                                                         the 'addressed' bunk. */
+	uint64_t tmrsc                        : 3;  /**< Mode Register Set Cycle Time (represented in \#mclks)
+                                                              - 000-001: RESERVED
+                                                              - 010: tMRSC = 2 mclks
+                                                              - 011: tMRSC = 3 mclks
+                                                              - ...
+                                                              - 111: tMRSC = 7 mclks
+                                                         NOTE: The device tMRSC parameter is a function of CL
+                                                         (which during HW initialization is not known. Its
+                                                         recommended to load tMRSC(MAX) value to avoid timing
+                                                         violations.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t trc                          : 4;  /**< Row Cycle Time (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0010: RESERVED
+                                                              - 0011: tRC = 3 mclks
+                                                              - 0100: tRC = 4 mclks
+                                                              - 0101: tRC = 5 mclks
+                                                              - 0110: tRC = 6 mclks
+                                                              - 0111: tRC = 7 mclks
+                                                              - 1000: tRC = 8 mclks
+                                                              - 1001: tRC = 9 mclks
+                                                              - 1010-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t twl                          : 4;  /**< Write Latency (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0001: RESERVED
+                                                              - 0010: Write Latency (WL=2.0 mclk)
+                                                              - 0011: Write Latency (WL=3.0 mclks)
+                                                              - 0100: Write Latency (WL=4.0 mclks)
+                                                              - 0101: Write Latency (WL=5.0 mclks)
+                                                              - 0110: Write Latency (WL=6.0 mclks)
+                                                              - 0111: Write Latency (WL=7.0 mclks)
+                                                              - 1000: Write Latency (WL=8.0 mclks)
+                                                              - 1001: Write Latency (WL=9.0 mclks)
+                                                              - 1010: Write Latency (WL=10.0 mclks)
+                                                              - 1011-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t trl                          : 4;  /**< Read Latency (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0010: RESERVED
+                                                              - 0011: Read Latency = 3 mclks
+                                                              - 0100: Read Latency = 4 mclks
+                                                              - 0101: Read Latency = 5 mclks
+                                                              - 0110: Read Latency = 6 mclks
+                                                              - 0111: Read Latency = 7 mclks
+                                                              - 1000: Read Latency = 8 mclks
+                                                              - 1001: Read Latency = 9 mclks
+                                                              - 1010: Read Latency = 10 mclks
+                                                              - 1011-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t tskw                         : 2;  /**< Board Skew (represented in \#dclks)
+                                                         Represents additional board skew of DQ/DQS.
+                                                             - 00: board-skew = 0 dclk
+                                                             - 01: board-skew = 1 dclk
+                                                             - 10: board-skew = 2 dclk
+                                                             - 11: board-skew = 3 dclk
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t ref_int                      : 4;  /**< Refresh Interval (represented in \#of 512 dclk
+                                                         increments).
+                                                              - 0000: RESERVED
+                                                              - 0001: 1 * 512  = 512 dclks
+                                                              - ...
+                                                              - 1111: 15 * 512 = 7680 dclks
+                                                         NOTE: For finer level of granularity, refer to
+                                                         REF_INTLO[8:0] field.
+                                                         For RLDRAM-II, each refresh interval will
+                                                         generate a burst of 8 AREF commands, one to each of
+                                                         8 explicit banks (referenced using the RLD_BA[2:0]
+                                                         pins.
+                                                         Example: For mclk=200MHz/dclk(400MHz=2.5ns):
+                                                           64K AREF cycles required within tREF=32ms
+                                                             trefint = tREF(ms)/(64K cycles/8banks)
+                                                                     = 32ms/8K = 3.9us = 3900ns
+                                                             REF_INT = ROUND_DOWN[(trefint/dclk)/512]
+                                                                     = ROUND_DOWN[(3900/2.5)/512]
+                                                                     = 3
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t ref_int                      : 4;
+	uint64_t tskw                         : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t trl                          : 4;
+	uint64_t twl                          : 4;
+	uint64_t trc                          : 4;
+	uint64_t tmrsc                        : 3;
+	uint64_t mrs_ena                      : 1;
+	uint64_t aref_ena                     : 1;
+	uint64_t ref_intlo                    : 9;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_dfa_memcfg1_s             cn38xx;
+	struct cvmx_dfa_memcfg1_s             cn38xxp2;
+	struct cvmx_dfa_memcfg1_s             cn58xx;
+	struct cvmx_dfa_memcfg1_s             cn58xxp1;
+};
+typedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t;
+
+/**
+ * cvmx_dfa_memcfg2
+ *
+ * DFA_MEMCFG2 = DFA Memory Config Register \#2
+ * *** NOTE: Pass2 Addition
+ *
+ * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II
+ */
+union cvmx_dfa_memcfg2
+{
+	uint64_t u64;
+	struct cvmx_dfa_memcfg2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t dteclkdis                    : 1;  /**< DFA DTE Clock Disable
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled.
+                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
+                                                         the DFA via the NCB Bus. All DFA Operations must be
+                                                         issued solely through the CP2 interface.
+
+                                                         NOTE: When DTECLKDIS=1, if CP2 Errors are encountered
+                                                         (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR
+                                                         does not reflect the failing address/ctl information. */
+	uint64_t silrst                       : 1;  /**< LLM-PHY Silo Reset
+                                                         When a '1' is written (when the previous
+                                                         value was a '0') causes the the LLM-PHY Silo read/write
+                                                         pointers to be reset.
+                                                         NOTE: SW MUST WAIT 400 dclks after the LAST HW Init
+                                                         sequence was launched (ie: INIT_START 0->1 CSR write),
+                                                         before the SILRST can be triggered (0->1). */
+	uint64_t trfc                         : 5;  /**< FCRAM-II Refresh Interval
+                                                         *** CN58XX UNSUPPORTED *** */
+	uint64_t refshort                     : 1;  /**< FCRAM Short Refresh Mode
+                                                         *** CN58XX UNSUPPORTED *** */
+	uint64_t ua_start                     : 2;  /**< FCRAM-II Upper Addres Start
+                                                         *** CN58XX UNSUPPORTED *** */
+	uint64_t maxbnk                       : 1;  /**< Maximum Banks per-device (used by the address mapper
+                                                         when extracting address bits for the memory bank#.
+                                                           - 0: 4 banks/device
+                                                           - 1: 8 banks/device */
+	uint64_t fcram2p                      : 1;  /**< FCRAM-II+ Mode Enable
+                                                         *** CN58XX UNSUPPORTED *** */
+#else
+	uint64_t fcram2p                      : 1;
+	uint64_t maxbnk                       : 1;
+	uint64_t ua_start                     : 2;
+	uint64_t refshort                     : 1;
+	uint64_t trfc                         : 5;
+	uint64_t silrst                       : 1;
+	uint64_t dteclkdis                    : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_dfa_memcfg2_s             cn38xx;
+	struct cvmx_dfa_memcfg2_s             cn38xxp2;
+	struct cvmx_dfa_memcfg2_s             cn58xx;
+	struct cvmx_dfa_memcfg2_s             cn58xxp1;
+};
+typedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t;
+
+/**
+ * cvmx_dfa_memfadr
+ *
+ * DFA_MEMFADR = RLDRAM Failing Address/Control Register
+ *
+ * Description: DFA Memory Failing Address/Control Error Capture information
+ * This register contains useful information to help in isolating an RLDRAM memory failure.
+ * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is
+ * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt
+ * via the FSRC field.
+ * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED.
+ */
+union cvmx_dfa_memfadr
+{
+	uint64_t u64;
+	struct cvmx_dfa_memfadr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t maddr                        : 24; /**< Memory Address */
+#else
+	uint64_t maddr                        : 24;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_dfa_memfadr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t fdst                         : 9;  /**< Fill-Destination
+                                                            FSRC[1:0]    | FDST[8:0]
+                                                            -------------+-------------------------------------
+                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
+                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
+                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
+                                                           where:
+                                                               DTE: DFA Thread Engine ID#
+                                                               PP: Packet Processor ID#
+                                                               FID: Fill-ID# (unique per PP)
+                                                               WIDX:  16b SIMPLE Mode (index)
+                                                               DMODE: (0=16b SIMPLE/1=32b SIMPLE)
+                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
+                                                               INDEX: (0=Low LW/1=High LW)
+                                                         NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 32-bit load/store. */
+	uint64_t fsrc                         : 2;  /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
+	uint64_t pnum                         : 1;  /**< Memory Port
+                                                         NOTE: For O2P, this bit will always return zero. */
+	uint64_t bnum                         : 3;  /**< Memory Bank
+                                                         When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0].
+                                                         (RANK[1] can be inferred from MADDR[24:0]) */
+	uint64_t maddr                        : 25; /**< Memory Address */
+#else
+	uint64_t maddr                        : 25;
+	uint64_t bnum                         : 3;
+	uint64_t pnum                         : 1;
+	uint64_t fsrc                         : 2;
+	uint64_t fdst                         : 9;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn31xx;
+	struct cvmx_dfa_memfadr_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t fdst                         : 9;  /**< Fill-Destination
+                                                            FSRC[1:0]    | FDST[8:0]
+                                                            -------------+-------------------------------------
+                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
+                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
+                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
+                                                           where:
+                                                               DTE: DFA Thread Engine ID#
+                                                               PP: Packet Processor ID#
+                                                               FID: Fill-ID# (unique per PP)
+                                                               WIDX:  18b SIMPLE Mode (index)
+                                                               DMODE: (0=18b SIMPLE/1=36b SIMPLE)
+                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
+                                                               INDEX: (0=Low LW/1=High LW)
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store. */
+	uint64_t fsrc                         : 2;  /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
+	uint64_t pnum                         : 1;  /**< Memory Port
+                                                         NOTE: the port id's are reversed
+                                                            PNUM==0 => port#1
+                                                            PNUM==1 => port#0 */
+	uint64_t bnum                         : 3;  /**< Memory Bank */
+	uint64_t maddr                        : 24; /**< Memory Address */
+#else
+	uint64_t maddr                        : 24;
+	uint64_t bnum                         : 3;
+	uint64_t pnum                         : 1;
+	uint64_t fsrc                         : 2;
+	uint64_t fdst                         : 9;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} cn38xx;
+	struct cvmx_dfa_memfadr_cn38xx        cn38xxp2;
+	struct cvmx_dfa_memfadr_cn38xx        cn58xx;
+	struct cvmx_dfa_memfadr_cn38xx        cn58xxp1;
+};
+typedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t;
+
+/**
+ * cvmx_dfa_memfcr
+ *
+ * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0]
+ * *** CN58XX UNSUPPORTED ***
+ *
+ * Notes:
+ * For FCRAM-II please consult your device's data sheet for further details:
+ * MRS Definition:
+ *    A[13:8]=0   RESERVED
+ *    A[7]=0      TEST MODE     (N3K requires test mode 0:"disabled")
+ *    A[6:4]      CAS LATENCY   (fully programmable - SW must ensure that the value programmed
+ *                               into DFA_MEM_CFG0[TRL] corresponds with this value).
+ *    A[3]=0      BURST TYPE    (N3K requires 0:"Sequential" Burst Type)
+ *    A[2:0]      BURST LENGTH  Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4)
+ *
+ *                                  In BL2 mode(for highest performance), only 1/2 the phsyical
+ *                                  memory is unique (ie: each bunk stores the same information).
+ *                                  In BL4 mode(highest capacity), all of the physical memory
+ *                                  is unique (ie: each bunk is uniquely addressable).
+ * EMRS Definition:
+ *    A[13:12]    REFRESH MODE  (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes)
+ *
+ *                              (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT]
+ *                              is also reflected in the Refresh Mode encoding).
+ *    A[11:7]=0   RESERVED
+ *    A[6:5]=2    STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture
+ *                              silos rely on a conditional QS strobe)
+ *    A[4:3]      DIC(QS)       QS Drive Strength: fully programmable (consult your FCRAM-II data sheet)
+ *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
+ *    A[2:1]      DIC(DQ)       DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet)
+ *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
+ *    A[0]        DLL           DLL Enable: Programmable [0:DLL Enable/1: DLL Disable]
+ *
+ * EMRS2 Definition: (for FCRAM-II+)
+ *    A[13:11]=0                RESERVED
+ *    A[10:8]     ODTDS         On Die Termination (DS+/-)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ *    A[7:6]=0    MBW           Multi-Bank Write: (N3K requires use of 0:"single bank" mode only)
+ *    A[5:3]      ODTin         On Die Termination (input pin)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ *    A[2:0]      ODTDQ         On Die Termination (DQ)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ */
+union cvmx_dfa_memfcr
+{
+	uint64_t u64;
+	struct cvmx_dfa_memfcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t emrs2                        : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+)
+                                                         *** CN58XX UNSUPPORTED *** */
+	uint64_t reserved_31_31               : 1;
+	uint64_t emrs                         : 15; /**< Memory Address[14:0] during EMRS
+                                                         *** CN58XX UNSUPPORTED ***
+                                                           A[0]=1: DLL Enabled) */
+	uint64_t reserved_15_15               : 1;
+	uint64_t mrs                          : 15; /**< FCRAM Memory Address[14:0] during MRS
+                                                         *** CN58XX UNSUPPORTED ***
+                                                           A[6:4]=4  CAS LATENCY=4(default)
+                                                           A[3]=0    Burst Type(must be 0:Sequential)
+                                                           A[2:0]=2  Burst Length=4(default) */
+#else
+	uint64_t mrs                          : 15;
+	uint64_t reserved_15_15               : 1;
+	uint64_t emrs                         : 15;
+	uint64_t reserved_31_31               : 1;
+	uint64_t emrs2                        : 15;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfa_memfcr_s              cn38xx;
+	struct cvmx_dfa_memfcr_s              cn38xxp2;
+	struct cvmx_dfa_memfcr_s              cn58xx;
+	struct cvmx_dfa_memfcr_s              cn58xxp1;
+};
+typedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t;
+
+/**
+ * cvmx_dfa_memhidat
+ *
+ * DFA_MEMHIDAT = DFA NCB-Direct CSR access to DFM Memory Space (High QW)
+ *
+ * Description:
+ * DFA supports NCB-Direct CSR acccesses to DFM Memory space for debug purposes. Unfortunately, NCB-Direct accesses
+ * are limited to QW-size(64bits), whereas the minimum access granularity for DFM Memory space is OW(128bits). To
+ * support writes to DFM Memory space, the Hi-QW of data is sourced from the DFA_MEMHIDAT register. Recall, the
+ * OW(128b) in DDR3 memory space is fixed format:
+ *     OWDATA[127:118]: OWECC[9:0] 10bits of in-band OWECC SEC/DED codeword
+ *                      This can be precomputed/written by SW OR
+ *                      if DFM_FNTCTL[ECC_WENA]=1, DFM hardware will auto-compute the 10b OWECC and place in the
+ *                      OWDATA[127:118] before being written to memory.
+ *     OWDATA[117:0]:   Memory Data (contains fixed MNODE/MONODE arc formats for use by DTEs(thread engines).
+ *                      Or, a user may choose to treat DFM Memory Space as 'scratch pad' in which case the
+ *                      OWDATA[117:0] may contain user-specified information accessible via NCB-Direct CSR mode
+ *                      accesses to DFA Memory Space.
+ *  NOTE: To write to the DFA_MEMHIDAT register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b111.
+ *        To read the DFA_MEMHIDAT register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b111.
+ *
+ *  NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect.
+ *  NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect.
+ */
+union cvmx_dfa_memhidat
+{
+	uint64_t u64;
+	struct cvmx_dfa_memhidat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hidat                        : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3
+                                                         Memory accesses.
+                                                         All DFM DDR3 memory accesses are OW(128b) references,
+                                                         and since NCB-Direct Mode writes only support QW(64b),
+                                                         the Hi QW of data must be sourced from a CSR register.
+                                                         NOTE: This single register is 'shared' for ALL DFM
+                                                         DDR3 Memory writes. */
+#else
+	uint64_t hidat                        : 64;
+#endif
+	} s;
+	struct cvmx_dfa_memhidat_s            cn63xx;
+	struct cvmx_dfa_memhidat_s            cn63xxp1;
+};
+typedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t;
+
+/**
+ * cvmx_dfa_memrld
+ *
+ * DFA_MEMRLD = DFA RLDRAM MRS Register Values
+ *
+ * Description:
+ */
+union cvmx_dfa_memrld
+{
+	uint64_t u64;
+	struct cvmx_dfa_memrld_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t mrsdat                       : 23; /**< This field represents the data driven onto the
+                                                         A[22:0] address lines during MRS(Mode Register Set)
+                                                         commands (during a HW init sequence). This field
+                                                         corresponds with the Mode Register Bit Map from
+                                                         your RLDRAM-II device specific data sheet.
+                                                            A[17:10]: RESERVED
+                                                            A[9]:     ODT (on die termination)
+                                                            A[8]:     Impedance Matching
+                                                            A[7]:     DLL Reset
+                                                            A[6]:     UNUSED
+                                                            A[5]:     Address Mux  (for N3K: MUST BE ZERO)
+                                                            A[4:3]:   Burst Length (for N3K: MUST BE ZERO)
+                                                            A[2:0]:   Configuration (see data sheet for
+                                                                      specific RLDRAM-II device).
+                                                               - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5]
+                                                               - 010:     CFG=2 [tRC=6/tRL=6/tWL=7]
+                                                               - 011:     CFG=3 [tRC=8/tRL=8/tWL=9]
+                                                               - 100-111: RESERVED
+                                                          NOTE: For additional density, the RLDRAM-II parts
+                                                          can be 'clamshelled' (ie: two devices mounted on
+                                                          different sides of the PCB board), since the BGA
+                                                          pinout supports 'mirroring'.
+                                                          To support a clamshell design, SW must preload
+                                                          the MRSDAT[22:0] with the proper A[22:0] pin mapping
+                                                          which is dependent on the 'selected' bunk/clam
+                                                          (see also: DFA_MEMCFG0[BUNK_INIT] field).
+                                                          NOTE: Care MUST BE TAKEN NOT to write to this register
+                                                          within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1).
+                                                          NOTE: This should only be written to a different value
+                                                          during power-on SW initialization. */
+#else
+	uint64_t mrsdat                       : 23;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_dfa_memrld_s              cn38xx;
+	struct cvmx_dfa_memrld_s              cn38xxp2;
+	struct cvmx_dfa_memrld_s              cn58xx;
+	struct cvmx_dfa_memrld_s              cn58xxp1;
+};
+typedef union cvmx_dfa_memrld cvmx_dfa_memrld_t;
+
+/**
+ * cvmx_dfa_ncbctl
+ *
+ * DFA_NCBCTL = DFA NCB CTL Register
+ *
+ * Description:
+ */
+union cvmx_dfa_ncbctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_ncbctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t sbdnum                       : 5;  /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 32 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+	uint64_t dcmode                       : 1;  /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t dtmode                       : 1;  /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t pmode                        : 1;  /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t qmode                        : 1;  /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t imode                        : 1;  /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t imode                        : 1;
+	uint64_t qmode                        : 1;
+	uint64_t pmode                        : 1;
+	uint64_t dtmode                       : 1;
+	uint64_t dcmode                       : 1;
+	uint64_t sbdlck                       : 1;
+	uint64_t sbdnum                       : 5;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_dfa_ncbctl_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sbdnum                       : 4;  /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 16 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+	uint64_t sbdlck                       : 1;  /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+	uint64_t dcmode                       : 1;  /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t dtmode                       : 1;  /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t pmode                        : 1;  /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t qmode                        : 1;  /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+	uint64_t imode                        : 1;  /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t imode                        : 1;
+	uint64_t qmode                        : 1;
+	uint64_t pmode                        : 1;
+	uint64_t dtmode                       : 1;
+	uint64_t dcmode                       : 1;
+	uint64_t sbdlck                       : 1;
+	uint64_t sbdnum                       : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn38xx;
+	struct cvmx_dfa_ncbctl_cn38xx         cn38xxp2;
+	struct cvmx_dfa_ncbctl_s              cn58xx;
+	struct cvmx_dfa_ncbctl_s              cn58xxp1;
+};
+typedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t;
+
+/**
+ * cvmx_dfa_pfc0_cnt
+ *
+ * DFA_PFC0_CNT = DFA Performance Counter \#0
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc0_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc0_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pfcnt0                       : 64; /**< Performance Counter \#0
+                                                         When DFA_PFC_GCTL[CNT0ENA]=1, the event selected
+                                                         by DFA_PFC0_CTL[EVSEL] is counted.
+                                                         See also DFA_PFC_GCTL[CNT0WCLR] and DFA_PFC_GCTL
+                                                         [CNT0RCLR] for special clear count cases available
+                                                         for SW data collection. */
+#else
+	uint64_t pfcnt0                       : 64;
+#endif
+	} s;
+	struct cvmx_dfa_pfc0_cnt_s            cn63xx;
+	struct cvmx_dfa_pfc0_cnt_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t;
+
+/**
+ * cvmx_dfa_pfc0_ctl
+ *
+ * DFA_PFC0_CTL = DFA Performance Counter#0 Control
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc0_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc0_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t evsel                        : 6;  /**< Performance Counter#0 Event Selector
+                                                         // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph)
+                                                          - 0:  \#Total Cycles
+                                                          - 1:  \#LDNODE visits
+                                                          - 2:  \#SDNODE visits
+                                                          - 3:  \#DNODE visits (LD/SD)
+                                                          - 4:  \#LCNODE visits
+                                                          - 5:  \#SCNODE visits
+                                                          - 6:  \#CNODE visits (LC/SC)
+                                                          - 7:  \#LMNODE visits
+                                                          - 8:  \#SMNODE visits
+                                                          - 9:  \#MNODE visits (LM/SM)
+                                                           - 10: \#MONODE visits
+                                                           - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
+                                                           - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
+                                                           - 13: \#MEMORY visits (MNODE+MONODE)
+                                                           - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
+                                                           - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
+                                                           - 16: \#RESCANs detected (occur when HASH collision is detected)
+                                                           - 17: \#GWALK iterations STALLED - Packet data/Result Buffer
+                                                           - 18: \#GWALK iterations NON-STALLED
+                                                           - 19: \#CLOAD iterations
+                                                           - 20: \#MLOAD iterations
+                                                               [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#].
+                                                           - 21: \#RWORD1+ writes
+                                                           - 22: \#cycles Cluster is busy
+                                                           - 23: \#GWALK Instructions
+                                                           - 24: \#CLOAD Instructions
+                                                           - 25: \#MLOAD Instructions
+                                                               [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#].
+                                                           - 26: \#GFREE Instructions
+                                                           - 27-30: RESERVED
+                                                           - 31: \# Node Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE,EDNODE] registers
+                                                         //=============================================================
+                                                         // Events [32-63] are used ONLY FOR PMODE=0(per-cluster DTE mode):
+                                                           - 32: \#cycles a specific cluster-DTE remains active(valid state)
+                                                           - 33: \#cycles a specific cluster-DTE waits for Memory Response Data
+                                                           - 34: \#cycles a specific cluster-DTE waits in resource stall state
+                                                                  (waiting for packet data or result buffer space)
+                                                           - 35: \#cycles a specific cluster-DTE waits in resource pending state
+                                                           - 36-63: RESERVED
+                                                         //============================================================= */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t cldte                        : 4;  /**< Performance Counter#0 Cluster DTE Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster's DTE# for all events
+                                                         associated with Performance Counter#0. */
+	uint64_t clnum                        : 2;  /**< Performance Counter#0 Cluster Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster# for all events
+                                                         associated with Performance Counter#0. */
+#else
+	uint64_t clnum                        : 2;
+	uint64_t cldte                        : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t evsel                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_dfa_pfc0_ctl_s            cn63xx;
+	struct cvmx_dfa_pfc0_ctl_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t;
+
+/**
+ * cvmx_dfa_pfc1_cnt
+ *
+ * DFA_PFC1_CNT = DFA Performance Counter \#1
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc1_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc1_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pfcnt1                       : 64; /**< Performance Counter \#1
+                                                         When DFA_PFC_GCTL[CNT1ENA]=1, the event selected
+                                                         by DFA_PFC1_CTL[EVSEL] is counted.
+                                                         See also DFA_PFC_GCTL[CNT1WCLR] and DFA_PFC_GCTL
+                                                         [CNT1RCLR] for special clear count cases available
+                                                         for SW data collection. */
+#else
+	uint64_t pfcnt1                       : 64;
+#endif
+	} s;
+	struct cvmx_dfa_pfc1_cnt_s            cn63xx;
+	struct cvmx_dfa_pfc1_cnt_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t;
+
+/**
+ * cvmx_dfa_pfc1_ctl
+ *
+ * DFA_PFC1_CTL = DFA Performance Counter#1 Control
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc1_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc1_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t evsel                        : 6;  /**< Performance Counter#1 Event Selector
+                                                         - 0:  \#Cycles
+                                                         - 1:  \#LDNODE visits
+                                                         - 2:  \#SDNODE visits
+                                                         - 3:  \#DNODE visits (LD/SD)
+                                                         - 4:  \#LCNODE visits
+                                                         - 5:  \#SCNODE visits
+                                                         - 6:  \#CNODE visits (LC/SC)
+                                                         - 7:  \#LMNODE visits
+                                                         - 8:  \#SMNODE visits
+                                                         - 9:  \#MNODE visits (LM/SM)
+                                                          - 10: \#MONODE visits
+                                                          - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
+                                                          - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
+                                                          - 13: \#MEMORY visits (MNODE+MONODE)
+                                                          - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
+                                                          - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
+                                                          - 16: \#RESCANs detected (occur when HASH collision is detected)
+                                                          - 17: \#GWALK STALLs detected - Packet data/Result Buffer
+                                                          - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
+                                                          - 19: \#CLOAD DTE cycles
+                                                          - 20: \#MLOAD DTE cycles
+                                                          - 21: \#cycles waiting for Memory Response Data
+                                                          - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
+                                                          - 23: \#cycles waiting in resource pending state
+                                                          - 24: \#RWORD1+ writes
+                                                          - 25: \#DTE-VLD cycles
+                                                          - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
+                                                          - 27: \#GWALK Instructions
+                                                          - 28: \#CLOAD Instructions
+                                                          - 29: \#MLOAD Instructions
+                                                          - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
+                                                          - 31: RESERVED
+                                                          - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t cldte                        : 4;  /**< Performance Counter#1 Cluster DTE Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster's DTE# for all events
+                                                         associated with Performance Counter#1. */
+	uint64_t clnum                        : 2;  /**< Performance Counter#1 Cluster Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster# for all events
+                                                         associated with Performance Counter#1. */
+#else
+	uint64_t clnum                        : 2;
+	uint64_t cldte                        : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t evsel                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_dfa_pfc1_ctl_s            cn63xx;
+	struct cvmx_dfa_pfc1_ctl_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t;
+
+/**
+ * cvmx_dfa_pfc2_cnt
+ *
+ * DFA_PFC2_CNT = DFA Performance Counter \#2
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc2_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc2_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pfcnt2                       : 64; /**< Performance Counter \#2
+                                                         When DFA_PFC_GCTL[CNT2ENA]=1, the event selected
+                                                         by DFA_PFC2_CTL[EVSEL] is counted.
+                                                         See also DFA_PFC_GCTL[CNT2WCLR] and DFA_PFC_GCTL
+                                                         [CNT2RCLR] for special clear count cases available
+                                                         for SW data collection. */
+#else
+	uint64_t pfcnt2                       : 64;
+#endif
+	} s;
+	struct cvmx_dfa_pfc2_cnt_s            cn63xx;
+	struct cvmx_dfa_pfc2_cnt_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t;
+
+/**
+ * cvmx_dfa_pfc2_ctl
+ *
+ * DFA_PFC2_CTL = DFA Performance Counter#2 Control
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc2_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc2_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t evsel                        : 6;  /**< Performance Counter#2 Event Selector
+                                                         - 0:  \#Cycles
+                                                         - 1:  \#LDNODE visits
+                                                         - 2:  \#SDNODE visits
+                                                         - 3:  \#DNODE visits (LD/SD)
+                                                         - 4:  \#LCNODE visits
+                                                         - 5:  \#SCNODE visits
+                                                         - 6:  \#CNODE visits (LC/SC)
+                                                         - 7:  \#LMNODE visits
+                                                         - 8:  \#SMNODE visits
+                                                         - 9:  \#MNODE visits (LM/SM)
+                                                          - 10: \#MONODE visits
+                                                          - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
+                                                          - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
+                                                          - 13: \#MEMORY visits (MNODE+MONODE)
+                                                          - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
+                                                          - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
+                                                          - 16: \#RESCANs detected (occur when HASH collision is detected)
+                                                          - 17: \#GWALK STALLs detected - Packet data/Result Buffer
+                                                          - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
+                                                          - 19: \#CLOAD DTE cycles
+                                                          - 20: \#MLOAD DTE cycles
+                                                          - 21: \#cycles waiting for Memory Response Data
+                                                          - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
+                                                          - 23: \#cycles waiting in resource pending state
+                                                          - 24: \#RWORD1+ writes
+                                                          - 25: \#DTE-VLD cycles
+                                                          - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
+                                                          - 27: \#GWALK Instructions
+                                                          - 28: \#CLOAD Instructions
+                                                          - 29: \#MLOAD Instructions
+                                                          - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
+                                                          - 31: RESERVED
+                                                          - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t cldte                        : 4;  /**< Performance Counter#2 Cluster DTE Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster's DTE# for all events
+                                                         associated with Performance Counter#2. */
+	uint64_t clnum                        : 2;  /**< Performance Counter#2 Cluster Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster# for all events
+                                                         associated with Performance Counter#2. */
+#else
+	uint64_t clnum                        : 2;
+	uint64_t cldte                        : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t evsel                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_dfa_pfc2_ctl_s            cn63xx;
+	struct cvmx_dfa_pfc2_ctl_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t;
+
+/**
+ * cvmx_dfa_pfc3_cnt
+ *
+ * DFA_PFC3_CNT = DFA Performance Counter \#3
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc3_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc3_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pfcnt3                       : 64; /**< Performance Counter \#3
+                                                         When DFA_PFC_GCTL[CNT3ENA]=1, the event selected
+                                                         by DFA_PFC3_CTL[EVSEL] is counted.
+                                                         See also DFA_PFC_GCTL[CNT3WCLR] and DFA_PFC_GCTL
+                                                         [CNT3RCLR] for special clear count cases available
+                                                         for SW data collection. */
+#else
+	uint64_t pfcnt3                       : 64;
+#endif
+	} s;
+	struct cvmx_dfa_pfc3_cnt_s            cn63xx;
+	struct cvmx_dfa_pfc3_cnt_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t;
+
+/**
+ * cvmx_dfa_pfc3_ctl
+ *
+ * DFA_PFC3_CTL = DFA Performance Counter#3 Control
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc3_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc3_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t evsel                        : 6;  /**< Performance Counter#3 Event Selector
+                                                         - 0:  \#Cycles
+                                                         - 1:  \#LDNODE visits
+                                                         - 2:  \#SDNODE visits
+                                                         - 3:  \#DNODE visits (LD/SD)
+                                                         - 4:  \#LCNODE visits
+                                                         - 5:  \#SCNODE visits
+                                                         - 6:  \#CNODE visits (LC/SC)
+                                                         - 7:  \#LMNODE visits
+                                                         - 8:  \#SMNODE visits
+                                                         - 9:  \#MNODE visits (LM/SM)
+                                                          - 10: \#MONODE visits
+                                                          - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
+                                                          - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
+                                                          - 13: \#MEMORY visits (MNODE+MONODE)
+                                                          - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
+                                                          - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
+                                                          - 16: \#RESCANs detected (occur when HASH collision is detected)
+                                                          - 17: \#GWALK STALLs detected - Packet data/Result Buffer
+                                                          - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
+                                                          - 19: \#CLOAD DTE cycles
+                                                          - 20: \#MLOAD DTE cycles
+                                                          - 21: \#cycles waiting for Memory Response Data
+                                                          - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
+                                                          - 23: \#cycles waiting in resource pending state
+                                                          - 24: \#RWORD1+ writes
+                                                          - 25: \#DTE-VLD cycles
+                                                          - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
+                                                          - 27: \#GWALK Instructions
+                                                          - 28: \#CLOAD Instructions
+                                                          - 29: \#MLOAD Instructions
+                                                          - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
+                                                          - 31: RESERVED
+                                                          - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t cldte                        : 4;  /**< Performance Counter#3 Cluster DTE Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster's DTE# for all events
+                                                         associated with Performance Counter#3. */
+	uint64_t clnum                        : 2;  /**< Performance Counter#3 Cluster Selector
+                                                         When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
+                                                         is used to select/monitor the cluster# for all events
+                                                         associated with Performance Counter#3. */
+#else
+	uint64_t clnum                        : 2;
+	uint64_t cldte                        : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t evsel                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_dfa_pfc3_ctl_s            cn63xx;
+	struct cvmx_dfa_pfc3_ctl_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t;
+
+/**
+ * cvmx_dfa_pfc_gctl
+ *
+ * DFA_PFC_GCTL = DFA Performance Counter Global Control
+ * *FOR INTERNAL USE ONLY*
+ * Description:
+ */
+union cvmx_dfa_pfc_gctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_pfc_gctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t vgid                         : 8;  /**< Virtual Graph Id#
+                                                         When PMODE=1(per-graph selector), this field is used
+                                                         to select/monitor only those events which are
+                                                         associated with this selected VGID(virtual graph ID).
+                                                         This field is used globally across all four performance
+                                                         counters.
+                                                         IMPNOTE: I implemented a global VGID across all 4 performance
+                                                         counters to save wires/area. */
+	uint64_t pmode                        : 1;  /**< Select Mode
+                                                         - 0: Events are selected on a per-cluster DTE# (CLNUM/CLDTE)
+                                                          DFA_PFCx_CTL[CLNUM,CLDTE] specifies the cluster-DTE for
+                                                          each 1(of 4) performance counters.
+                                                         - 1: Events are selected on a per-graph basis (VGID=virtual Graph ID).
+                                                          NOTE: Only EVSEL=[0...31] can be used in conjunction with PMODE=1.
+                                                          DFA_PFC_GCTL[VGID] specifies the Virtual graph ID used across
+                                                          all four performance counters. */
+	uint64_t ednode                       : 2;  /**< Ending DNODE Selector
+                                                         When ENODE=0/1(*DNODE), this field is used to further
+                                                         specify the Ending DNODE transition sub-type:
+                                                           - 0: ALL DNODE sub-types
+                                                           - 1: ->D2e (explicit DNODE transition node-arc alone transitions to DNODE)
+                                                           - 2: ->D2i (implicit DNODE transition:arc-present triggers transition)
+                                                           - 3: ->D1r (rescan DNODE transition) */
+	uint64_t enode                        : 3;  /**< Ending Node Selector
+                                                         When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the ENODE
+                                                         field is used to select Ending Node, and the SNODE
+                                                         field is used to select the Starting Node.
+                                                          - 0: LDNODE
+                                                          - 1: SDNODE
+                                                          - 2: LCNODE
+                                                          - 3: SCNODE
+                                                          - 4: LMNODE
+                                                          - 5: SMNODE
+                                                          - 6: MONODE
+                                                          - 7: RESERVED */
+	uint64_t snode                        : 3;  /**< Starting Node Selector
+                                                         When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the SNODE
+                                                         field is used to select Starting Node, and the ENODE
+                                                         field is used to select the Ending Node.
+                                                          - 0: LDNODE
+                                                          - 1: SDNODE
+                                                          - 2: LCNODE
+                                                          - 3: SCNODE
+                                                          - 4: LMNODE
+                                                          - 5: SMNODE
+                                                          - 6: MONODE
+                                                          - 7: RESERVED */
+	uint64_t cnt3rclr                     : 1;  /**< Performance Counter \#3 Read Clear
+                                                         If this bit is set, CSR reads to the DFA_PFC3_CNT
+                                                         will clear the count value. This allows SW to maintain
+                                                         'cumulative' counters to avoid HW wraparound. */
+	uint64_t cnt2rclr                     : 1;  /**< Performance Counter \#2 Read Clear
+                                                         If this bit is set, CSR reads to the DFA_PFC2_CNT
+                                                         will clear the count value. This allows SW to maintain
+                                                         'cumulative' counters to avoid HW wraparound. */
+	uint64_t cnt1rclr                     : 1;  /**< Performance Counter \#1 Read Clear
+                                                         If this bit is set, CSR reads to the DFA_PFC1_CNT
+                                                         will clear the count value. This allows SW to maintain
+                                                         'cumulative' counters to avoid HW wraparound. */
+	uint64_t cnt0rclr                     : 1;  /**< Performance Counter \#0 Read Clear
+                                                         If this bit is set, CSR reads to the DFA_PFC0_CNT
+                                                         will clear the count value. This allows SW to maintain
+                                                         'cumulative' counters to avoid HW wraparound. */
+	uint64_t cnt3wclr                     : 1;  /**< Performance Counter \#3 Write Clear
+                                                         If this bit is set, CSR writes to the DFA_PFC3_CNT
+                                                         will clear the count value.
+                                                         If this bit is clear, CSR writes to the DFA_PFC3_CNT
+                                                         will continue the count from the written value. */
+	uint64_t cnt2wclr                     : 1;  /**< Performance Counter \#2 Write Clear
+                                                         If this bit is set, CSR writes to the DFA_PFC2_CNT
+                                                         will clear the count value.
+                                                         If this bit is clear, CSR writes to the DFA_PFC2_CNT
+                                                         will continue the count from the written value. */
+	uint64_t cnt1wclr                     : 1;  /**< Performance Counter \#1 Write Clear
+                                                         If this bit is set, CSR writes to the DFA_PFC1_CNT
+                                                         will clear the count value.
+                                                         If this bit is clear, CSR writes to the DFA_PFC1_CNT
+                                                         will continue the count from the written value. */
+	uint64_t cnt0wclr                     : 1;  /**< Performance Counter \#0 Write Clear
+                                                         If this bit is set, CSR writes to the DFA_PFC0_CNT
+                                                         will clear the count value.
+                                                         If this bit is clear, CSR writes to the DFA_PFC0_CNT
+                                                         will continue the count from the written value. */
+	uint64_t cnt3ena                      : 1;  /**< Performance Counter 3 Enable
+                                                         When this bit is set, the performance counter \#3
+                                                         is enabled. */
+	uint64_t cnt2ena                      : 1;  /**< Performance Counter 2 Enable
+                                                         When this bit is set, the performance counter \#2
+                                                         is enabled. */
+	uint64_t cnt1ena                      : 1;  /**< Performance Counter 1 Enable
+                                                         When this bit is set, the performance counter \#1
+                                                         is enabled. */
+	uint64_t cnt0ena                      : 1;  /**< Performance Counter 0 Enable
+                                                         When this bit is set, the performance counter \#0
+                                                         is enabled. */
+#else
+	uint64_t cnt0ena                      : 1;
+	uint64_t cnt1ena                      : 1;
+	uint64_t cnt2ena                      : 1;
+	uint64_t cnt3ena                      : 1;
+	uint64_t cnt0wclr                     : 1;
+	uint64_t cnt1wclr                     : 1;
+	uint64_t cnt2wclr                     : 1;
+	uint64_t cnt3wclr                     : 1;
+	uint64_t cnt0rclr                     : 1;
+	uint64_t cnt1rclr                     : 1;
+	uint64_t cnt2rclr                     : 1;
+	uint64_t cnt3rclr                     : 1;
+	uint64_t snode                        : 3;
+	uint64_t enode                        : 3;
+	uint64_t ednode                       : 2;
+	uint64_t pmode                        : 1;
+	uint64_t vgid                         : 8;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_dfa_pfc_gctl_s            cn63xx;
+	struct cvmx_dfa_pfc_gctl_s            cn63xxp1;
+};
+typedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t;
+
+/**
+ * cvmx_dfa_rodt_comp_ctl
+ *
+ * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination")
+ *
+ */
+union cvmx_dfa_rodt_comp_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfa_rodt_comp_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t enable                       : 1;  /**< Read On Die Termination Enable
+                                                         (0=disable, 1=enable) */
+	uint64_t reserved_12_15               : 4;
+	uint64_t nctl                         : 4;  /**< Compensation control bits */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;  /**< Compensation control bits */
+#else
+	uint64_t pctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t enable                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_dfa_rodt_comp_ctl_s       cn58xx;
+	struct cvmx_dfa_rodt_comp_ctl_s       cn58xxp1;
+};
+typedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t;
+
+/**
+ * cvmx_dfa_sbd_dbg0
+ *
+ * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register
+ *
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_sbd_dbg0
+{
+	uint64_t u64;
+	struct cvmx_dfa_sbd_dbg0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd0                         : 64; /**< DFA ScoreBoard \#0 Data
+                                                         For internal use only! (DFA Scoreboard Debug)
+                                                         [63:40] rptr[26:3]: Result Base Pointer
+                                                         [39:24] rwcnt[15:0] Cumulative Result Write Counter
+                                                         [23]    lastgrdrsp: Last Gather-Rd Response
+                                                         [22]    wtgrdrsp: Waiting Gather-Rd Response
+                                                         [21]    wtgrdreq: Waiting for Gather-Rd Issue
+                                                         [20]    glvld: GLPTR/GLCNT Valid
+                                                         [19]    cmpmark: Completion Marked Node Detected
+                                                         [18:17] cmpcode[1:0]: Completion Code
+                                                                       [0=PDGONE/1=PERR/2=RFULL/3=TERM]
+                                                         [16]    cmpdet: Completion Detected
+                                                         [15]    wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp
+                                                         [14]    wtlastwrcmtrsp: Waiting for LAST RESULT
+                                                                       RWrCmtRsp
+                                                         [13]    hdrwrreq: Waiting for HDR RWrReq
+                                                         [12]    wtrwrreq: Waiting for RWrReq
+                                                         [11]    wtwqwrreq: Waiting for WQWrReq issue
+                                                         [10]    lastprdrspeot: Last Packet-Rd Response
+                                                         [9]     lastprdrsp: Last Packet-Rd Response
+                                                         [8]     wtprdrsp:  Waiting for PRdRsp EOT
+                                                         [7]     wtprdreq: Waiting for PRdReq Issue
+                                                         [6]     lastpdvld: PDPTR/PDLEN Valid
+                                                         [5]     pdvld: Packet Data Valid
+                                                         [4]     wqvld: WQVLD
+                                                         [3]     wqdone: WorkQueue Done condition
+                                                                       a) WQWrReq issued(for WQPTR<>0) OR
+                                                                       b) HDR RWrCmtRsp completed)
+                                                         [2]     rwstf: Resultant write STF/P Mode
+                                                         [1]     pdldt: Packet-Data LDT mode
+                                                         [0]     gmode: Gather-Mode */
+#else
+	uint64_t sbd0                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_sbd_dbg0_s            cn31xx;
+	struct cvmx_dfa_sbd_dbg0_s            cn38xx;
+	struct cvmx_dfa_sbd_dbg0_s            cn38xxp2;
+	struct cvmx_dfa_sbd_dbg0_s            cn58xx;
+	struct cvmx_dfa_sbd_dbg0_s            cn58xxp1;
+};
+typedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t;
+
+/**
+ * cvmx_dfa_sbd_dbg1
+ *
+ * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register
+ *
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_sbd_dbg1
+{
+	uint64_t u64;
+	struct cvmx_dfa_sbd_dbg1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd1                         : 64; /**< DFA ScoreBoard \#1 Data
+                                                         For internal use only! (DFA Scoreboard Debug)
+                                                         [63:61] wqptr[35:33]: Work Queue Pointer
+                                                         [60:52] rptr[35:27]: Result Base Pointer
+                                                         [51:16] pdptr[35:0]: Packet Data Pointer
+                                                         [15:0]  pdcnt[15:0]: Packet Data Counter */
+#else
+	uint64_t sbd1                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_sbd_dbg1_s            cn31xx;
+	struct cvmx_dfa_sbd_dbg1_s            cn38xx;
+	struct cvmx_dfa_sbd_dbg1_s            cn38xxp2;
+	struct cvmx_dfa_sbd_dbg1_s            cn58xx;
+	struct cvmx_dfa_sbd_dbg1_s            cn58xxp1;
+};
+typedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t;
+
+/**
+ * cvmx_dfa_sbd_dbg2
+ *
+ * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register
+ *
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_sbd_dbg2
+{
+	uint64_t u64;
+	struct cvmx_dfa_sbd_dbg2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd2                         : 64; /**< DFA ScoreBoard \#2 Data
+                                                         [63:49] wqptr[17:3]: Work Queue Pointer
+                                                         [48:16] rwptr[35:3]: Result Write Pointer
+                                                         [15:0]  prwcnt[15:0]: Pending Result Write Counter */
+#else
+	uint64_t sbd2                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_sbd_dbg2_s            cn31xx;
+	struct cvmx_dfa_sbd_dbg2_s            cn38xx;
+	struct cvmx_dfa_sbd_dbg2_s            cn38xxp2;
+	struct cvmx_dfa_sbd_dbg2_s            cn58xx;
+	struct cvmx_dfa_sbd_dbg2_s            cn58xxp1;
+};
+typedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t;
+
+/**
+ * cvmx_dfa_sbd_dbg3
+ *
+ * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register
+ *
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+union cvmx_dfa_sbd_dbg3
+{
+	uint64_t u64;
+	struct cvmx_dfa_sbd_dbg3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t sbd3                         : 64; /**< DFA ScoreBoard \#3 Data
+                                                         [63:49] wqptr[32:18]: Work Queue Pointer
+                                                         [48:16] glptr[35:3]: Gather List Pointer
+                                                         [15:0]  glcnt[15:0]: Gather List Counter */
+#else
+	uint64_t sbd3                         : 64;
+#endif
+	} s;
+	struct cvmx_dfa_sbd_dbg3_s            cn31xx;
+	struct cvmx_dfa_sbd_dbg3_s            cn38xx;
+	struct cvmx_dfa_sbd_dbg3_s            cn38xxp2;
+	struct cvmx_dfa_sbd_dbg3_s            cn58xx;
+	struct cvmx_dfa_sbd_dbg3_s            cn58xxp1;
+};
+typedef union cvmx_dfa_sbd_dbg3 cvmx_dfa_sbd_dbg3_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa.c b/sys/contrib/octeon-sdk/cvmx-dfa.c
index 9658c9e..8b2847b 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfa.c
+++ b/sys/contrib/octeon-sdk/cvmx-dfa.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
- * Support library for the hardware DFA engine.
+ * Support library for the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #include "executive-config.h"
 #ifdef CVMX_ENABLE_DFA_FUNCTIONS
diff --git a/sys/contrib/octeon-sdk/cvmx-dfa.h b/sys/contrib/octeon-sdk/cvmx-dfa.h
index 2b943c3..d1a3b14 100644
--- a/sys/contrib/octeon-sdk/cvmx-dfa.h
+++ b/sys/contrib/octeon-sdk/cvmx-dfa.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
- * Interface to the hardware DFA engine.
+ * Interface to the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_DFA_H__
@@ -517,7 +519,7 @@ typedef union
     } s2;
 } cvmx_dfa_state_t;
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-dfa-defs.h */
 
 /**
  * Write a small node edge to LLM.
diff --git a/sys/contrib/octeon-sdk/cvmx-dfm-defs.h b/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
new file mode 100644
index 0000000..bb324ad
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
@@ -0,0 +1,3224 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-dfm-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dfm.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_DFM_TYPEDEFS_H__
+#define __CVMX_DFM_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CHAR_CTL CVMX_DFM_CHAR_CTL_FUNC()
+static inline uint64_t CVMX_DFM_CHAR_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CHAR_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000220ull);
+}
+#else
+#define CVMX_DFM_CHAR_CTL (CVMX_ADD_IO_SEG(0x00011800D4000220ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CHAR_MASK0 CVMX_DFM_CHAR_MASK0_FUNC()
+static inline uint64_t CVMX_DFM_CHAR_MASK0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CHAR_MASK0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000228ull);
+}
+#else
+#define CVMX_DFM_CHAR_MASK0 (CVMX_ADD_IO_SEG(0x00011800D4000228ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CHAR_MASK2 CVMX_DFM_CHAR_MASK2_FUNC()
+static inline uint64_t CVMX_DFM_CHAR_MASK2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CHAR_MASK2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000238ull);
+}
+#else
+#define CVMX_DFM_CHAR_MASK2 (CVMX_ADD_IO_SEG(0x00011800D4000238ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CHAR_MASK4 CVMX_DFM_CHAR_MASK4_FUNC()
+static inline uint64_t CVMX_DFM_CHAR_MASK4_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CHAR_MASK4 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000318ull);
+}
+#else
+#define CVMX_DFM_CHAR_MASK4 (CVMX_ADD_IO_SEG(0x00011800D4000318ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_COMP_CTL2 CVMX_DFM_COMP_CTL2_FUNC()
+static inline uint64_t CVMX_DFM_COMP_CTL2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_COMP_CTL2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001B8ull);
+}
+#else
+#define CVMX_DFM_COMP_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CONFIG CVMX_DFM_CONFIG_FUNC()
+static inline uint64_t CVMX_DFM_CONFIG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CONFIG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000188ull);
+}
+#else
+#define CVMX_DFM_CONFIG (CVMX_ADD_IO_SEG(0x00011800D4000188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_CONTROL CVMX_DFM_CONTROL_FUNC()
+static inline uint64_t CVMX_DFM_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000190ull);
+}
+#else
+#define CVMX_DFM_CONTROL (CVMX_ADD_IO_SEG(0x00011800D4000190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_DLL_CTL2 CVMX_DFM_DLL_CTL2_FUNC()
+static inline uint64_t CVMX_DFM_DLL_CTL2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_DLL_CTL2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001C8ull);
+}
+#else
+#define CVMX_DFM_DLL_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_DLL_CTL3 CVMX_DFM_DLL_CTL3_FUNC()
+static inline uint64_t CVMX_DFM_DLL_CTL3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_DLL_CTL3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000218ull);
+}
+#else
+#define CVMX_DFM_DLL_CTL3 (CVMX_ADD_IO_SEG(0x00011800D4000218ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FCLK_CNT CVMX_DFM_FCLK_CNT_FUNC()
+static inline uint64_t CVMX_DFM_FCLK_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FCLK_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001E0ull);
+}
+#else
+#define CVMX_DFM_FCLK_CNT (CVMX_ADD_IO_SEG(0x00011800D40001E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FNT_BIST CVMX_DFM_FNT_BIST_FUNC()
+static inline uint64_t CVMX_DFM_FNT_BIST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FNT_BIST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40007F8ull);
+}
+#else
+#define CVMX_DFM_FNT_BIST (CVMX_ADD_IO_SEG(0x00011800D40007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FNT_CTL CVMX_DFM_FNT_CTL_FUNC()
+static inline uint64_t CVMX_DFM_FNT_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FNT_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000400ull);
+}
+#else
+#define CVMX_DFM_FNT_CTL (CVMX_ADD_IO_SEG(0x00011800D4000400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FNT_IENA CVMX_DFM_FNT_IENA_FUNC()
+static inline uint64_t CVMX_DFM_FNT_IENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FNT_IENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000410ull);
+}
+#else
+#define CVMX_DFM_FNT_IENA (CVMX_ADD_IO_SEG(0x00011800D4000410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FNT_SCLK CVMX_DFM_FNT_SCLK_FUNC()
+static inline uint64_t CVMX_DFM_FNT_SCLK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FNT_SCLK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000418ull);
+}
+#else
+#define CVMX_DFM_FNT_SCLK (CVMX_ADD_IO_SEG(0x00011800D4000418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_FNT_STAT CVMX_DFM_FNT_STAT_FUNC()
+static inline uint64_t CVMX_DFM_FNT_STAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_FNT_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000408ull);
+}
+#else
+#define CVMX_DFM_FNT_STAT (CVMX_ADD_IO_SEG(0x00011800D4000408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_IFB_CNT CVMX_DFM_IFB_CNT_FUNC()
+static inline uint64_t CVMX_DFM_IFB_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_IFB_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001D0ull);
+}
+#else
+#define CVMX_DFM_IFB_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_MODEREG_PARAMS0 CVMX_DFM_MODEREG_PARAMS0_FUNC()
+static inline uint64_t CVMX_DFM_MODEREG_PARAMS0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_MODEREG_PARAMS0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001A8ull);
+}
+#else
+#define CVMX_DFM_MODEREG_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D40001A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_MODEREG_PARAMS1 CVMX_DFM_MODEREG_PARAMS1_FUNC()
+static inline uint64_t CVMX_DFM_MODEREG_PARAMS1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_MODEREG_PARAMS1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000260ull);
+}
+#else
+#define CVMX_DFM_MODEREG_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D4000260ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_OPS_CNT CVMX_DFM_OPS_CNT_FUNC()
+static inline uint64_t CVMX_DFM_OPS_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_OPS_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001D8ull);
+}
+#else
+#define CVMX_DFM_OPS_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_PHY_CTL CVMX_DFM_PHY_CTL_FUNC()
+static inline uint64_t CVMX_DFM_PHY_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_PHY_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000210ull);
+}
+#else
+#define CVMX_DFM_PHY_CTL (CVMX_ADD_IO_SEG(0x00011800D4000210ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_RESET_CTL CVMX_DFM_RESET_CTL_FUNC()
+static inline uint64_t CVMX_DFM_RESET_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_RESET_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000180ull);
+}
+#else
+#define CVMX_DFM_RESET_CTL (CVMX_ADD_IO_SEG(0x00011800D4000180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_RLEVEL_CTL CVMX_DFM_RLEVEL_CTL_FUNC()
+static inline uint64_t CVMX_DFM_RLEVEL_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_RLEVEL_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40002A0ull);
+}
+#else
+#define CVMX_DFM_RLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D40002A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_RLEVEL_DBG CVMX_DFM_RLEVEL_DBG_FUNC()
+static inline uint64_t CVMX_DFM_RLEVEL_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_RLEVEL_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40002A8ull);
+}
+#else
+#define CVMX_DFM_RLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D40002A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DFM_RLEVEL_RANKX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_DFM_RLEVEL_RANKX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_DFM_RLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_RODT_MASK CVMX_DFM_RODT_MASK_FUNC()
+static inline uint64_t CVMX_DFM_RODT_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_RODT_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000268ull);
+}
+#else
+#define CVMX_DFM_RODT_MASK (CVMX_ADD_IO_SEG(0x00011800D4000268ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_SLOT_CTL0 CVMX_DFM_SLOT_CTL0_FUNC()
+static inline uint64_t CVMX_DFM_SLOT_CTL0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_SLOT_CTL0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001F8ull);
+}
+#else
+#define CVMX_DFM_SLOT_CTL0 (CVMX_ADD_IO_SEG(0x00011800D40001F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_SLOT_CTL1 CVMX_DFM_SLOT_CTL1_FUNC()
+static inline uint64_t CVMX_DFM_SLOT_CTL1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_SLOT_CTL1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000200ull);
+}
+#else
+#define CVMX_DFM_SLOT_CTL1 (CVMX_ADD_IO_SEG(0x00011800D4000200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_TIMING_PARAMS0 CVMX_DFM_TIMING_PARAMS0_FUNC()
+static inline uint64_t CVMX_DFM_TIMING_PARAMS0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_TIMING_PARAMS0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000198ull);
+}
+#else
+#define CVMX_DFM_TIMING_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D4000198ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_TIMING_PARAMS1 CVMX_DFM_TIMING_PARAMS1_FUNC()
+static inline uint64_t CVMX_DFM_TIMING_PARAMS1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_TIMING_PARAMS1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001A0ull);
+}
+#else
+#define CVMX_DFM_TIMING_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D40001A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_WLEVEL_CTL CVMX_DFM_WLEVEL_CTL_FUNC()
+static inline uint64_t CVMX_DFM_WLEVEL_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_WLEVEL_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000300ull);
+}
+#else
+#define CVMX_DFM_WLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D4000300ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_WLEVEL_DBG CVMX_DFM_WLEVEL_DBG_FUNC()
+static inline uint64_t CVMX_DFM_WLEVEL_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_WLEVEL_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D4000308ull);
+}
+#else
+#define CVMX_DFM_WLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D4000308ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DFM_WLEVEL_RANKX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_DFM_WLEVEL_RANKX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_DFM_WLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DFM_WODT_MASK CVMX_DFM_WODT_MASK_FUNC()
+static inline uint64_t CVMX_DFM_WODT_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DFM_WODT_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800D40001B0ull);
+}
+#else
+#define CVMX_DFM_WODT_MASK (CVMX_ADD_IO_SEG(0x00011800D40001B0ull))
+#endif
+
+/**
+ * cvmx_dfm_char_ctl
+ *
+ * DFM_CHAR_CTL = DFM Characterization Control
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_dfm_char_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_char_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t en                           : 1;  /**< Enable characterization */
+	uint64_t sel                          : 1;  /**< Pattern select
+                                                         0 = PRBS
+                                                         1 = Programmable pattern */
+	uint64_t prog                         : 8;  /**< Programmable pattern */
+	uint64_t prbs                         : 32; /**< PRBS Polynomial */
+#else
+	uint64_t prbs                         : 32;
+	uint64_t prog                         : 8;
+	uint64_t sel                          : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_dfm_char_ctl_s            cn63xx;
+	struct cvmx_dfm_char_ctl_s            cn63xxp1;
+};
+typedef union cvmx_dfm_char_ctl cvmx_dfm_char_ctl_t;
+
+/**
+ * cvmx_dfm_char_mask0
+ *
+ * DFM_CHAR_MASK0 = DFM Characterization Control Mask0
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_dfm_char_mask0
+{
+	uint64_t u64;
+	struct cvmx_dfm_char_mask0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Mask for DQ0[15:0] */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_dfm_char_mask0_s          cn63xx;
+	struct cvmx_dfm_char_mask0_s          cn63xxp1;
+};
+typedef union cvmx_dfm_char_mask0 cvmx_dfm_char_mask0_t;
+
+/**
+ * cvmx_dfm_char_mask2
+ *
+ * DFM_CHAR_MASK2 = DFM Characterization Control Mask2
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_dfm_char_mask2
+{
+	uint64_t u64;
+	struct cvmx_dfm_char_mask2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Mask for DQ1[15:0] */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_dfm_char_mask2_s          cn63xx;
+	struct cvmx_dfm_char_mask2_s          cn63xxp1;
+};
+typedef union cvmx_dfm_char_mask2 cvmx_dfm_char_mask2_t;
+
+/**
+ * cvmx_dfm_char_mask4
+ *
+ * DFM_CHAR_MASK4 = DFM Characterization Mask4
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_dfm_char_mask4
+{
+	uint64_t u64;
+	struct cvmx_dfm_char_mask4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t reset_n_mask                 : 1;  /**< Mask for RESET_N */
+	uint64_t a_mask                       : 16; /**< Mask for A[15:0] */
+	uint64_t ba_mask                      : 3;  /**< Mask for BA[2:0] */
+	uint64_t we_n_mask                    : 1;  /**< Mask for WE_N */
+	uint64_t cas_n_mask                   : 1;  /**< Mask for CAS_N */
+	uint64_t ras_n_mask                   : 1;  /**< Mask for RAS_N */
+	uint64_t odt1_mask                    : 2;  /**< Mask for ODT1
+                                                         For DFM, ODT1 is reserved. */
+	uint64_t odt0_mask                    : 2;  /**< Mask for ODT0 */
+	uint64_t cs1_n_mask                   : 2;  /**< Mask for CS1_N
+                                                         For DFM, CS1_N is reserved. */
+	uint64_t cs0_n_mask                   : 2;  /**< Mask for CS0_N */
+	uint64_t cke_mask                     : 2;  /**< Mask for CKE
+                                                         For DFM, CKE_MASK[1] is reserved. */
+#else
+	uint64_t cke_mask                     : 2;
+	uint64_t cs0_n_mask                   : 2;
+	uint64_t cs1_n_mask                   : 2;
+	uint64_t odt0_mask                    : 2;
+	uint64_t odt1_mask                    : 2;
+	uint64_t ras_n_mask                   : 1;
+	uint64_t cas_n_mask                   : 1;
+	uint64_t we_n_mask                    : 1;
+	uint64_t ba_mask                      : 3;
+	uint64_t a_mask                       : 16;
+	uint64_t reset_n_mask                 : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_dfm_char_mask4_s          cn63xx;
+};
+typedef union cvmx_dfm_char_mask4 cvmx_dfm_char_mask4_t;
+
+/**
+ * cvmx_dfm_comp_ctl2
+ *
+ * DFM_COMP_CTL2 = DFM Compensation control2
+ *
+ */
+union cvmx_dfm_comp_ctl2
+{
+	uint64_t u64;
+	struct cvmx_dfm_comp_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ddr__ptune                   : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value provides debug information for the
+                                                         compensation impedance on P-pullup */
+	uint64_t ddr__ntune                   : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value provides debug information for the
+                                                         compensation impedance on N-pulldown */
+	uint64_t m180                         : 1;  /**< Cap impedance at 180 ohm (instead of 240 ohm) */
+	uint64_t byp                          : 1;  /**< Bypass mode
+                                                         Use compensation setting from PTUNE,NTUNE */
+	uint64_t ptune                        : 4;  /**< PCTL impedance control in bypass mode */
+	uint64_t ntune                        : 4;  /**< NCTL impedance control in bypass mode */
+	uint64_t rodt_ctl                     : 4;  /**< NCTL RODT impedance control bits
+                                                         0000 = No ODT
+                                                         0001 = 20 ohm
+                                                         0010 = 30 ohm
+                                                         0011 = 40 ohm
+                                                         0100 = 60 ohm
+                                                         0101 = 120 ohm
+                                                         0110-1111 = Reserved */
+	uint64_t cmd_ctl                      : 4;  /**< Drive strength control for CMD/A/RESET_N/CKE drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+	uint64_t ck_ctl                       : 4;  /**< Drive strength control for CK/CS_N/ODT drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+	uint64_t dqx_ctl                      : 4;  /**< Drive strength control for DQ/DQS drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+#else
+	uint64_t dqx_ctl                      : 4;
+	uint64_t ck_ctl                       : 4;
+	uint64_t cmd_ctl                      : 4;
+	uint64_t rodt_ctl                     : 4;
+	uint64_t ntune                        : 4;
+	uint64_t ptune                        : 4;
+	uint64_t byp                          : 1;
+	uint64_t m180                         : 1;
+	uint64_t ddr__ntune                   : 4;
+	uint64_t ddr__ptune                   : 4;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_dfm_comp_ctl2_s           cn63xx;
+	struct cvmx_dfm_comp_ctl2_s           cn63xxp1;
+};
+typedef union cvmx_dfm_comp_ctl2 cvmx_dfm_comp_ctl2_t;
+
+/**
+ * cvmx_dfm_config
+ *
+ * DFM_CONFIG = DFM Memory Configuration Register
+ *
+ * This register controls certain parameters of  Memory Configuration
+ *
+ * Notes:
+ * a. The self refresh entry sequence(s) power the DLL up/down (depending on DFM_MODEREG_PARAMS[DLL])
+ * when DFM_CONFIG[SREF_WITH_DLL] is set
+ * b. Prior to the self-refresh exit sequence, DFM_MODEREG_PARAMS should be re-programmed (if needed) to the
+ * appropriate values
+ *
+ * DFM Bringup Sequence:
+ * 1. SW must ensure there are no pending DRAM transactions and that the DDR PLL and the DLL have been initialized.
+ * 2. Write DFM_COMP_CTL2, DFM_CONTROL, DFM_WODT_MASK, DFM_RODT_MASK, DFM_DUAL_MEMCFG, DFM_TIMING_PARAMS0, DFM_TIMING_PARAMS1,
+ *    DFM_MODEREG_PARAMS0, DFM_MODEREG_PARAMS1, DFM_RESET_CTL (with DDR3RST=0), DFM_CONFIG (with INIT_START=0)
+ *    with appropriate values, if necessary.
+ * 3. Wait 200us, then write DFM_RESET_CTL[DDR3RST] = 1.
+ * 4. Initialize all ranks at once by writing DFM_CONFIG[RANKMASK][n] = 1, DFM_CONFIG[INIT_STATUS][n] = 1, and DFM_CONFIG[INIT_START] = 1
+ *    where n is a valid rank index for the specific board configuration.
+ * 5. for each rank n to be write-leveled [
+ *       if auto write-leveling is desired [
+ *           write DFM_CONFIG[RANKMASK][n] = 1, DFM_WLEVEL_CTL appropriately and DFM_CONFIG[INIT_START] = 1
+ *           wait until DFM_WLEVEL_RANKn[STATUS] = 3
+ *       ] else [
+ *           write DFM_WLEVEL_RANKn with appropriate values
+ *       ]
+ *    ]
+ * 6. for each rank n to be read-leveled [
+ *       if auto read-leveling is desired [
+ *           write DFM_CONFIG[RANKMASK][n] = 1, DFM_RLEVEL_CTL appropriately and DFM_CONFIG[INIT_START] = 1
+ *           wait until DFM_RLEVEL_RANKn[STATUS] = 3
+ *       ] else [
+ *           write DFM_RLEVEL_RANKn with appropriate values
+ *       ]
+ *    ]
+ */
+union cvmx_dfm_config
+{
+	uint64_t u64;
+	struct cvmx_dfm_config_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t early_unload_d1_r1           : 1;  /**< Reserved */
+	uint64_t early_unload_d1_r0           : 1;  /**< Reserved */
+	uint64_t early_unload_d0_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 1
+                                                         reads.
+                                                         The recommended EARLY_UNLOAD_D0_R1 value can be calculated
+                                                         after the final DFM_RLEVEL_RANK1[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 1 (i.e. calculate maxset=MAX(DFM_RLEVEL_RANK1[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 0
+                                                         reads.
+                                                         The recommended EARLY_UNLOAD_D0_R0 value can be calculated
+                                                         after the final DFM_RLEVEL_RANK0[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 0 (i.e. calculate maxset=MAX(DFM_RLEVEL_RANK0[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R0
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R0 = (maxset<1:0>!=3)). */
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same DFM_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before DFM initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's.
+                                                         INIT_STATUS<3:2> must be zero. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 1
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         MIRRMASK<3:2> must be zero.
+                                                         When RANK_ENA=0, MIRRMASK<1> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> =    CS0                  CS0 and CS1
+                                                           RANKMASK<1> =    CS1                      MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         RANKMASK<3:2> must be zero.
+                                                         When RANK_ENA=0, RANKMASK<1> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK enable (for use with multiple ranks)
+                                                         The RANK_ENA bit enables
+                                                         the drive of the CS_N[1:0] and ODT_<1:0> pins differently based on the
+                                                         (PBANK_LSB-1) address bit. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Instruction sequence that is run after a 0->1
+                                                         transition on DFM_CONFIG[INIT_START]. Self-refresh entry and
+                                                         precharge power-down entry and exit SEQUENCE's can also
+                                                         be initiated automatically by hardware.
+                                                         0=power-up/init                  (RANKMASK used, MR0, MR1, MR2, and MR3 written)
+                                                         1=read-leveling                  (RANKMASK used, MR3 written)
+                                                         2=self-refresh entry             (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1)
+                                                         3=self-refresh exit,             (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1)
+                                                         4=precharge power-down entry     (all ranks participate)
+                                                         5=precharge power-down exit      (all ranks participate)
+                                                         6=write-leveling                 (RANKMASK used, MR1 written)
+                                                         7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         DFM writes the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 descriptions for more details.
+                                                         The DFR_CKE pin gets activated as part of power-up/init,
+                                                         self-refresh exit, and precharge power-down exit sequences.
+                                                         The DFR_CKE pin gets de-activated as part of self-refresh entry,
+                                                         precharge power-down entry, or DRESET assertion.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, DFM asserts DFR_CKE as part of
+                                                         the first power-up/init, and continues to assert DFR_CKE
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DFR_CKE deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 fclks
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 fclks ~ 335ms for a 1.25 ns clock
+                                                         DFM_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. DFM does not send any refreshes / ZQCS's
+                                                         when DFM_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and DFM_OPS_CNT, DFM_IFB_CNT, and DFM_FCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Must be zero. */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         DFM_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< Physical bank address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the rank(or bunk) bit used to enable 1(of 2)
+                                                         ranks(via chip enables) supported by the DFM DDR3 interface.
+                                                         Reverting to the explanation for ROW_LSB, PBANK_LSB would be ROW_LSB bit +
+                                                         \#rowbits + \#rankbits.
+                                                         PBANK_LSB
+                                                             - 0: rank = mem_adr[24]
+                                                             - 1: rank = mem_adr[25]
+                                                             - 2: rank = mem_adr[26]
+                                                             - 3: rank = mem_adr[27]
+                                                             - 4: rank = mem_adr[28]
+                                                             - 5: rank = mem_adr[29]
+                                                             - 6: rank = mem_adr[30]
+                                                             - 7: rank = mem_adr[31]
+                                                          - 8-15:  RESERVED
+                                                         DESIGN NOTE: The DFM DDR3 memory bus is 16b wide, therefore DOES NOT
+                                                         support standard 64b/72b DDR3 DIMM modules. The board designer should
+                                                         populate the DFM DDR3 interface using either TWO x8bit DDR3 devices
+                                                         (or a single x16bit device if available) to fully populate the 16b
+                                                         DFM DDR3 data bus.
+                                                         The DFM DDR3 memory controller supports either 1(or 2) rank(s) based
+                                                         on how much total memory is desired for the DFA application. See
+                                                         RANK_ENA CSR bit when enabling for dual-ranks.
+                                                         SW NOTE:
+                                                             1) When RANK_ENA=0, SW must properly configure the PBANK_LSB to
+                                                                reference upper unused memory address bits.
+                                                             2) When RANK_ENA=1 (dual ranks), SW must configure PBANK_LSB to
+                                                                reference the upper most address bit based on the total size
+                                                                of the rank.
+                                                         For example, for a DFM DDR3 memory populated using Samsung's k4b1g0846c-f7
+                                                         1Gb(256MB) (16M x 8 bit x 8 bank) DDR3 parts, the column address width = 10 and
+                                                         the device row address width = 14b.  The single x8bit device contains 128MB, and
+                                                         requires TWO such parts to populate the DFM 16b DDR3 interface. This then yields
+                                                         a total rank size = 256MB = 2^28.
+                                                         For a single-rank configuration (RANK_ENA=0), SW would program PBANK_LSB>=3 to
+                                                         select mem_adr[x] bits above the legal DFM address range for mem_adr[27:0]=256MB.
+                                                         For a dual-rank configuration (RANK_ENA=1), SW would program PBANK_LSB=4 to select
+                                                         rank=mem_adr[28] as the bit used to determine which 256MB rank (of 512MB total) to
+                                                         access (via rank chip enables - see: DFM DDR3 CS0[1:0] pins for connection to
+                                                         upper and lower rank). */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The DFM memory address [31:4] which references octawords
+                                                         needs to be translated to DRAM addresses (bnk,row,col,bunk)
+                                                         mem_adr[31:4]:
+                                                           3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+                                                           1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4
+                                                          +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+                                                          |       ROW[m:n]            |     COL[13:3]       | BA
+                                                          +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+                                                         See:
+                                                           BA[2:0]:   mem_adr[6:4]
+                                                           COL[13:0]: [mem_adr[17:7],3'd0]
+                                                               NOTE: The extracted COL address is always 14b fixed size width,
+                                                               and upper unused bits are ignored by the DRAM device.
+                                                           ROW[15:0]: Extraction of ROW starting address bit is programmable,
+                                                           and is dependent on the \#column bits supported by the DRAM device.
+                                                           The actual starting bit of the ROW can actually span into the
+                                                           high order bits of the COL[13:3] field described above.
+                                                                  ROW_LSB    ROW[15:0]
+                                                                --------------------------
+                                                                   - 0:      mem_adr[26:11]
+                                                                   - 1:      mem_adr[27:12]
+                                                                   - 2:      mem_adr[28:13]
+                                                                   - 3:      mem_adr[29:14]
+                                                                   - 4:      mem_adr[30:15]
+                                                                   - 5:      mem_adr[31:16]
+                                                                  6,7:     [1'b0, mem_adr[31:17]]  For current DDR3 Jedec spec - UNSUPPORTED
+                                                         For example, for Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10. Therefore,
+                                                              BA[3:0] = mem_adr[6:4] / COL[9:0] = [mem_adr[13:7],3'd0], and
+                                                         we would want the row starting address to be extracted from mem_adr[14].
+                                                         Therefore, a ROW_LSB=3, will extract the row from mem_adr[29:14]. */
+	uint64_t ecc_ena                      : 1;  /**< Must be zero. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by DFM_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t early_unload_d0_r0           : 1;
+	uint64_t early_unload_d0_r1           : 1;
+	uint64_t early_unload_d1_r0           : 1;
+	uint64_t early_unload_d1_r1           : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_dfm_config_s              cn63xx;
+	struct cvmx_dfm_config_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_55_63               : 9;
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same DFM_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before DFM initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's.
+                                                         INIT_STATUS<3:2> must be zero. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 1
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         MIRRMASK<3:2> must be zero.
+                                                         When RANK_ENA=0, MIRRMASK<1> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> =    CS0                  CS0 and CS1
+                                                           RANKMASK<1> =    CS1                      MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         RANKMASK<3:2> must be zero.
+                                                         When RANK_ENA=0, RANKMASK<1> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK enable (for use with multiple ranks)
+                                                         The RANK_ENA bit enables
+                                                         the drive of the CS_N[1:0] and ODT_<1:0> pins differently based on the
+                                                         (PBANK_LSB-1) address bit. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Instruction sequence that is run after a 0->1
+                                                         transition on DFM_CONFIG[INIT_START]. Self-refresh entry and
+                                                         precharge power-down entry and exit SEQUENCE's can also
+                                                         be initiated automatically by hardware.
+                                                         0=power-up/init                  (RANKMASK used, MR0, MR1, MR2, and MR3 written)
+                                                         1=read-leveling                  (RANKMASK used, MR3 written)
+                                                         2=self-refresh entry             (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1)
+                                                         3=self-refresh exit,             (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1)
+                                                         4=precharge power-down entry     (all ranks participate)
+                                                         5=precharge power-down exit      (all ranks participate)
+                                                         6=write-leveling                 (RANKMASK used, MR1 written)
+                                                         7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         DFM writes the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 descriptions for more details.
+                                                         The DFR_CKE pin gets activated as part of power-up/init,
+                                                         self-refresh exit, and precharge power-down exit sequences.
+                                                         The DFR_CKE pin gets de-activated as part of self-refresh entry,
+                                                         precharge power-down entry, or DRESET assertion.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, DFM asserts DFR_CKE as part of
+                                                         the first power-up/init, and continues to assert DFR_CKE
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DFR_CKE deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 fclks
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 fclks ~ 335ms for a 1.25 ns clock
+                                                         DFM_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. DFM does not send any refreshes / ZQCS's
+                                                         when DFM_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and DFM_OPS_CNT, DFM_IFB_CNT, and DFM_FCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Must be zero. */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         DFM_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< Physical bank address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the rank(or bunk) bit used to enable 1(of 2)
+                                                         ranks(via chip enables) supported by the DFM DDR3 interface.
+                                                         Reverting to the explanation for ROW_LSB, PBANK_LSB would be ROW_LSB bit +
+                                                         \#rowbits + \#rankbits.
+                                                         PBANK_LSB
+                                                             - 0: rank = mem_adr[24]
+                                                             - 1: rank = mem_adr[25]
+                                                             - 2: rank = mem_adr[26]
+                                                             - 3: rank = mem_adr[27]
+                                                             - 4: rank = mem_adr[28]
+                                                             - 5: rank = mem_adr[29]
+                                                             - 6: rank = mem_adr[30]
+                                                             - 7: rank = mem_adr[31]
+                                                          - 8-15:  RESERVED
+                                                         DESIGN NOTE: The DFM DDR3 memory bus is 16b wide, therefore DOES NOT
+                                                         support standard 64b/72b DDR3 DIMM modules. The board designer should
+                                                         populate the DFM DDR3 interface using either TWO x8bit DDR3 devices
+                                                         (or a single x16bit device if available) to fully populate the 16b
+                                                         DFM DDR3 data bus.
+                                                         The DFM DDR3 memory controller supports either 1(or 2) rank(s) based
+                                                         on how much total memory is desired for the DFA application. See
+                                                         RANK_ENA CSR bit when enabling for dual-ranks.
+                                                         SW NOTE:
+                                                             1) When RANK_ENA=0, SW must properly configure the PBANK_LSB to
+                                                                reference upper unused memory address bits.
+                                                             2) When RANK_ENA=1 (dual ranks), SW must configure PBANK_LSB to
+                                                                reference the upper most address bit based on the total size
+                                                                of the rank.
+                                                         For example, for a DFM DDR3 memory populated using Samsung's k4b1g0846c-f7
+                                                         1Gb(256MB) (16M x 8 bit x 8 bank) DDR3 parts, the column address width = 10 and
+                                                         the device row address width = 14b.  The single x8bit device contains 128MB, and
+                                                         requires TWO such parts to populate the DFM 16b DDR3 interface. This then yields
+                                                         a total rank size = 256MB = 2^28.
+                                                         For a single-rank configuration (RANK_ENA=0), SW would program PBANK_LSB>=3 to
+                                                         select mem_adr[x] bits above the legal DFM address range for mem_adr[27:0]=256MB.
+                                                         For a dual-rank configuration (RANK_ENA=1), SW would program PBANK_LSB=4 to select
+                                                         rank=mem_adr[28] as the bit used to determine which 256MB rank (of 512MB total) to
+                                                         access (via rank chip enables - see: DFM DDR3 CS0[1:0] pins for connection to
+                                                         upper and lower rank). */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The DFM memory address [31:4] which references octawords
+                                                         needs to be translated to DRAM addresses (bnk,row,col,bunk)
+                                                         mem_adr[31:4]:
+                                                           3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+                                                           1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4
+                                                          +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+                                                          |       ROW[m:n]            |     COL[13:3]       | BA
+                                                          +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+                                                         See:
+                                                           BA[2:0]:   mem_adr[6:4]
+                                                           COL[13:0]: [mem_adr[17:7],3'd0]
+                                                               NOTE: The extracted COL address is always 14b fixed size width,
+                                                               and upper unused bits are ignored by the DRAM device.
+                                                           ROW[15:0]: Extraction of ROW starting address bit is programmable,
+                                                           and is dependent on the \#column bits supported by the DRAM device.
+                                                           The actual starting bit of the ROW can actually span into the
+                                                           high order bits of the COL[13:3] field described above.
+                                                                  ROW_LSB    ROW[15:0]
+                                                                --------------------------
+                                                                   - 0:      mem_adr[26:11]
+                                                                   - 1:      mem_adr[27:12]
+                                                                   - 2:      mem_adr[28:13]
+                                                                   - 3:      mem_adr[29:14]
+                                                                   - 4:      mem_adr[30:15]
+                                                                   - 5:      mem_adr[31:16]
+                                                                  6,7:     [1'b0, mem_adr[31:17]]  For current DDR3 Jedec spec - UNSUPPORTED
+                                                         For example, for Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10. Therefore,
+                                                              BA[3:0] = mem_adr[6:4] / COL[9:0] = [mem_adr[13:7],3'd0], and
+                                                         we would want the row starting address to be extracted from mem_adr[14].
+                                                         Therefore, a ROW_LSB=3, will extract the row from mem_adr[29:14]. */
+	uint64_t ecc_ena                      : 1;  /**< Must be zero. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by DFM_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_config cvmx_dfm_config_t;
+
+/**
+ * cvmx_dfm_control
+ *
+ * DFM_CONTROL = DFM Control
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+union cvmx_dfm_control
+{
+	uint64_t u64;
+	struct cvmx_dfm_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         RD cmd is delayed an additional DCLK cycle. */
+	uint64_t wodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         WR cmd is delayed an additional DCLK cycle. */
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH FCLK
+                                                         cycles.
+                                                         00 = 0 fclks
+                                                         01 = 1 fclks
+                                                         10 = 2 fclks
+                                                         11 = 3 fclks */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, DFM runs external ZQ calibration */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When counter is re-enabled, ZQCS is run immediately,
+                                                         and then every DFM_CONFIG[REF_ZQCS_INT] fclk cycles. */
+	uint64_t auto_fclkdis                 : 1;  /**< When 1, DFM will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< Must be zero. */
+	uint64_t max_write_batch              : 4;  /**< Must be set to value 8 */
+	uint64_t nxm_write_en                 : 1;  /**< Must be zero. */
+	uint64_t elev_prio_dis                : 1;  /**< Must be zero. */
+	uint64_t inorder_wr                   : 1;  /**< Must be zero. */
+	uint64_t inorder_rd                   : 1;  /**< Must be zero. */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes
+                                                         THROTTLE_RD and THROTTLE_WR must be the same value. */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads
+                                                         THROTTLE_RD and THROTTLE_WR must be the same value. */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 fclks earlier.
+                                                         00 = 0 fclks
+                                                         01 = 1 fclks
+                                                         10 = 2 fclks
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit should be set in conjunction with DFM_MODEREG_PARAMS[AL] */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the DFM_OPS_CNT, DFM_IFB_CNT, and
+                                                         DFM_FCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Must be zero. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_fclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t wodt_bprch                   : 1;
+	uint64_t rodt_bprch                   : 1;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_dfm_control_s             cn63xx;
+	struct cvmx_dfm_control_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH FCLK
+                                                         cycles.
+                                                         00 = 0 fclks
+                                                         01 = 1 fclks
+                                                         10 = 2 fclks
+                                                         11 = 3 fclks */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, DFM runs external ZQ calibration */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When counter is re-enabled, ZQCS is run immediately,
+                                                         and then every DFM_CONFIG[REF_ZQCS_INT] fclk cycles. */
+	uint64_t auto_fclkdis                 : 1;  /**< When 1, DFM will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< Must be zero. */
+	uint64_t max_write_batch              : 4;  /**< Must be set to value 8 */
+	uint64_t nxm_write_en                 : 1;  /**< Must be zero. */
+	uint64_t elev_prio_dis                : 1;  /**< Must be zero. */
+	uint64_t inorder_wr                   : 1;  /**< Must be zero. */
+	uint64_t inorder_rd                   : 1;  /**< Must be zero. */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes
+                                                         THROTTLE_RD and THROTTLE_WR must be the same value. */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads
+                                                         THROTTLE_RD and THROTTLE_WR must be the same value. */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 fclks earlier.
+                                                         00 = 0 fclks
+                                                         01 = 1 fclks
+                                                         10 = 2 fclks
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit should be set in conjunction with DFM_MODEREG_PARAMS[AL] */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the DFM_OPS_CNT, DFM_IFB_CNT, and
+                                                         DFM_FCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Must be zero. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_fclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_control cvmx_dfm_control_t;
+
+/**
+ * cvmx_dfm_dll_ctl2
+ *
+ * DFM_DLL_CTL2 = DFM (Octeon) DLL control and FCLK reset
+ *
+ *
+ * Notes:
+ * DLL Bringup sequence:
+ * 1. If not done already, set DFM_DLL_CTL2 = 0, except when DFM_DLL_CTL2[DRESET] = 1.
+ * 2. Write 1 to DFM_DLL_CTL2[DLL_BRINGUP]
+ * 3. Wait for 10 FCLK cycles, then write 1 to DFM_DLL_CTL2[QUAD_DLL_ENA]. It may not be feasible to count 10 FCLK cycles, but the
+ *    idea is to configure the delay line into DLL mode by asserting DLL_BRING_UP earlier than [QUAD_DLL_ENA], even if it is one
+ *    cycle early. DFM_DLL_CTL2[QUAD_DLL_ENA] must not change after this point without restarting the DFM and/or DRESET initialization
+ *    sequence.
+ * 4. Read L2D_BST0 and wait for the result. (L2D_BST0 is subject to change depending on how it called in o63. It is still ok to go
+ *    without step 4, since step 5 has enough time)
+ * 5. Wait 10 us.
+ * 6. Write 0 to DFM_DLL_CTL2[DLL_BRINGUP]. DFM_DLL_CTL2[DLL_BRINGUP] must not change after this point without restarting the DFM
+ *    and/or DRESET initialization sequence.
+ * 7. Read L2D_BST0 and wait for the result. (same as step 4, but the idea here is the wait some time before going to step 8, even it
+ *    is one cycle is fine)
+ * 8. Write 0 to DFM_DLL_CTL2[DRESET].  DFM_DLL_CTL2[DRESET] must not change after this point without restarting the DFM and/or
+ *    DRESET initialization sequence.
+ */
+union cvmx_dfm_dll_ctl2
+{
+	uint64_t u64;
+	struct cvmx_dfm_dll_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t dll_bringup                  : 1;  /**< DLL Bringup */
+	uint64_t dreset                       : 1;  /**< Fclk domain reset.  The reset signal that is used by the
+                                                         Fclk domain is (DRESET || ECLK_RESET). */
+	uint64_t quad_dll_ena                 : 1;  /**< DLL Enable */
+	uint64_t byp_sel                      : 4;  /**< Bypass select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t byp_setting                  : 8;  /**< Bypass setting
+                                                         DDR3-1600: 00100010
+                                                         DDR3-1333: 00110010
+                                                         DDR3-1066: 01001011
+                                                         DDR3-800 : 01110101
+                                                         DDR3-667 : 10010110
+                                                         DDR3-600 : 10101100 */
+#else
+	uint64_t byp_setting                  : 8;
+	uint64_t byp_sel                      : 4;
+	uint64_t quad_dll_ena                 : 1;
+	uint64_t dreset                       : 1;
+	uint64_t dll_bringup                  : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_dfm_dll_ctl2_s            cn63xx;
+	struct cvmx_dfm_dll_ctl2_s            cn63xxp1;
+};
+typedef union cvmx_dfm_dll_ctl2 cvmx_dfm_dll_ctl2_t;
+
+/**
+ * cvmx_dfm_dll_ctl3
+ *
+ * DFM_DLL_CTL3 = DFM DLL control and FCLK reset
+ *
+ */
+union cvmx_dfm_dll_ctl3
+{
+	uint64_t u64;
+	struct cvmx_dfm_dll_ctl3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t dll_fast                     : 1;  /**< DLL lock
+                                                         0 = DLL locked */
+	uint64_t dll90_setting                : 8;  /**< Encoded DLL settings. Works in conjuction with
+                                                         DLL90_BYTE_SEL */
+	uint64_t fine_tune_mode               : 1;  /**< Fine Tune Mode */
+	uint64_t dll_mode                     : 1;  /**< DLL Mode */
+	uint64_t dll90_byte_sel               : 4;  /**< Observe DLL settings for selected byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         0000,1010-1111 : Reserved */
+	uint64_t offset_ena                   : 1;  /**< Offset enable
+                                                         0 = disable
+                                                         1 = enable */
+	uint64_t load_offset                  : 1;  /**< Load offset
+                                                         0 : disable
+                                                         1 : load (generates a 1 cycle pulse to the PHY)
+                                                         This register is oneshot and clears itself each time
+                                                         it is set */
+	uint64_t mode_sel                     : 2;  /**< Mode select
+                                                         00 : reset
+                                                         01 : write
+                                                         10 : read
+                                                         11 : write & read */
+	uint64_t byte_sel                     : 4;  /**< Byte select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t offset                       : 6;  /**< Write/read offset setting
+                                                         [4:0] : offset
+                                                         [5]   : 0 = increment, 1 = decrement
+                                                         Not a 2's complement value */
+#else
+	uint64_t offset                       : 6;
+	uint64_t byte_sel                     : 4;
+	uint64_t mode_sel                     : 2;
+	uint64_t load_offset                  : 1;
+	uint64_t offset_ena                   : 1;
+	uint64_t dll90_byte_sel               : 4;
+	uint64_t dll_mode                     : 1;
+	uint64_t fine_tune_mode               : 1;
+	uint64_t dll90_setting                : 8;
+	uint64_t dll_fast                     : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_dfm_dll_ctl3_s            cn63xx;
+	struct cvmx_dfm_dll_ctl3_s            cn63xxp1;
+};
+typedef union cvmx_dfm_dll_ctl3 cvmx_dfm_dll_ctl3_t;
+
+/**
+ * cvmx_dfm_fclk_cnt
+ *
+ * DFM_FCLK_CNT  = Performance Counters
+ *
+ */
+union cvmx_dfm_fclk_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfm_fclk_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fclkcnt                      : 64; /**< Performance Counter that counts fclks
+                                                         64-bit counter. */
+#else
+	uint64_t fclkcnt                      : 64;
+#endif
+	} s;
+	struct cvmx_dfm_fclk_cnt_s            cn63xx;
+	struct cvmx_dfm_fclk_cnt_s            cn63xxp1;
+};
+typedef union cvmx_dfm_fclk_cnt cvmx_dfm_fclk_cnt_t;
+
+/**
+ * cvmx_dfm_fnt_bist
+ *
+ * DFM_FNT_BIST = DFM Front BIST Status
+ *
+ * This register contains Bist Status for DFM Front
+ */
+union cvmx_dfm_fnt_bist
+{
+	uint64_t u64;
+	struct cvmx_dfm_fnt_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t cab                          : 1;  /**< Bist Results for CAB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mrq                          : 1;  /**< Bist Results for MRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mff                          : 1;  /**< Bist Results for MFF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rpb                          : 1;  /**< Bist Results for RPB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mwb                          : 1;  /**< Bist Results for MWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t mwb                          : 1;
+	uint64_t rpb                          : 1;
+	uint64_t mff                          : 1;
+	uint64_t mrq                          : 1;
+	uint64_t cab                          : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_dfm_fnt_bist_s            cn63xx;
+	struct cvmx_dfm_fnt_bist_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t mrq                          : 1;  /**< Bist Results for MRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mff                          : 1;  /**< Bist Results for MFF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rpb                          : 1;  /**< Bist Results for RPB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mwb                          : 1;  /**< Bist Results for MWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t mwb                          : 1;
+	uint64_t rpb                          : 1;
+	uint64_t mff                          : 1;
+	uint64_t mrq                          : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_fnt_bist cvmx_dfm_fnt_bist_t;
+
+/**
+ * cvmx_dfm_fnt_ctl
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  DFM_FNT_CTL = DFM Front Control Register
+ *
+ * This register contains control registers for the DFM Front Section of Logic.
+ */
+union cvmx_dfm_fnt_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_fnt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t sbe_ena                      : 1;  /**< If SBE_ENA=1 & RECC_ENA=1 then all single bit errors
+                                                         which have been detected/corrected during GWALK reads,
+                                                         will be reported through RWORD0[REA]=ERR code in system
+                                                         memory at the conclusion of the DFA instruction.
+                                                         SWNOTE: The application user may wish to report single
+                                                         bit errors that were corrected through the
+                                                         RWORD0[REA]=ERR codeword.
+                                                         NOTE: This DOES NOT effect the reporting of SBEs in
+                                                         DFM_FNT_STAT[SBE] (which were corrected if RECC_ENA=1).
+                                                         This bit is only here for applications which 'MAY' want
+                                                         to be alerted with an ERR completion code if there were
+                                                         SBEs that were auto-corrected during GWALK instructions.
+                                                         Recap: If there is a SBE and SBE_ENA==1, the "err" field
+                                                         in the data returned to DFA will be set.  If SBE_ENA==0,
+                                                         the "err" is always 0 when there is a SBE; however,
+                                                         regardless of SBE_ENA, DBE will cause "err" to be 1. */
+	uint64_t wecc_ena                     : 1;  /**< If WECC_ENA=1, HW will auto-generate(overwrite) the 10b
+                                                         OWECC codeword during Memory Writes sourced by
+                                                         1) DFA MLOAD instructions, or by 2) NCB-Direct CSR
+                                                         mode writes to DFA memory space. The HW will insert
+                                                         the 10b OWECC inband into OW-DATA[127:118].
+                                                         If WECC_ENA=0, SW is responsible for generating the
+                                                         10b OWECC codeword inband in the upper OW-data[127:118]
+                                                         during Memory writes (to provide SEC/DED coverage for
+                                                         the data during subsequent Memory reads-see RECC_ENA). */
+	uint64_t recc_ena                     : 1;  /**< If RECC_ENA=1, all DFA memory reads sourced by 1) DFA
+                                                         GWALK instructions or by 2) NCB-Direct CSR mode reads
+                                                         to DFA memory space, will be protected by an inband 10b
+                                                         OWECC SEC/DED codeword. The inband OW-DATA[127:118]
+                                                         represents the inband OWECC codeword which offers single
+                                                         bit error correction(SEC)/double bit error detection(DED).
+                                                         [see also DFM_FNT_STAT[SBE,DBE,FADR,FSYN] status fields].
+                                                         The FSYN field contains an encoded value which determines
+                                                         which bit was corrected(for SBE) or detected(for DBE) to
+                                                         help in bit isolation of the error.
+                                                         SW NOTE: If RECC_ENA=1: An NCB-Direct CSR mode read of the
+                                                         upper QW in memory will return ZEROES in the upper 10b of the
+                                                         data word.
+                                                         If RECC_ENA=0: An NCB-Direct CSR mode read of the upper QW in
+                                                         memory will return the RAW 64bits from memory. During memory
+                                                         debug, writing RECC_ENA=0 provides visibility into the raw ECC
+                                                         stored in memory at that time. */
+	uint64_t dfr_ena                      : 1;  /**< DFM Memory Interface Enable
+                                                         The DFM powers up with the DDR3 interface disabled.
+                                                         If the DFA function is required, then after poweron
+                                                         software configures a stable DFM DDR3 memory clock
+                                                         (see: LMCx_DDR_PLL_CTL[DFM_PS_EN, DFM_DIV_RESET]),
+                                                         the DFM DDR3 memory interface can be enabled.
+                                                         When disabled (DFR_ENA=0), all DFM DDR3 memory
+                                                         output and bidirectional pins will be tristated.
+                                                         SW NOTE: The DFR_ENA=1 write MUST occur sometime after
+                                                         the DFM is brought out of reset (ie: after the
+                                                         DFM_DLL_CTL2[DRESET]=0 write). */
+#else
+	uint64_t dfr_ena                      : 1;
+	uint64_t recc_ena                     : 1;
+	uint64_t wecc_ena                     : 1;
+	uint64_t sbe_ena                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_dfm_fnt_ctl_s             cn63xx;
+	struct cvmx_dfm_fnt_ctl_s             cn63xxp1;
+};
+typedef union cvmx_dfm_fnt_ctl cvmx_dfm_fnt_ctl_t;
+
+/**
+ * cvmx_dfm_fnt_iena
+ *
+ * DFM_FNT_IENA = DFM Front Interrupt Enable Mask
+ *
+ * This register contains error interrupt enable information for the DFM Front Section of Logic.
+ */
+union cvmx_dfm_fnt_iena
+{
+	uint64_t u64;
+	struct cvmx_dfm_fnt_iena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dbe_intena                   : 1;  /**< OWECC Double Error Detected(DED) Interrupt Enable
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting an uncorrectable double bit
+                                                         OWECC during a memory read. */
+	uint64_t sbe_intena                   : 1;  /**< OWECC Single Error Corrected(SEC) Interrupt Enable
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting a correctable single bit
+                                                         OWECC error which was corrected during a memory
+                                                         read. */
+#else
+	uint64_t sbe_intena                   : 1;
+	uint64_t dbe_intena                   : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_dfm_fnt_iena_s            cn63xx;
+	struct cvmx_dfm_fnt_iena_s            cn63xxp1;
+};
+typedef union cvmx_dfm_fnt_iena cvmx_dfm_fnt_iena_t;
+
+/**
+ * cvmx_dfm_fnt_sclk
+ *
+ * DFM_FNT_SCLK = DFM Front SCLK Control Register
+ *
+ * This register contains control registers for the DFM Front Section of Logic.
+ * NOTE: This register is in USCLK domain and is ised to enable the conditional SCLK grid, as well as
+ * to start a software BiST sequence for the DFM sub-block. (note: the DFM has conditional clocks which
+ * prevent BiST to run under reset automatically).
+ */
+union cvmx_dfm_fnt_sclk
+{
+	uint64_t u64;
+	struct cvmx_dfm_fnt_sclk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t clear_bist                   : 1;  /**< When START_BIST is written 0->1, if CLEAR_BIST=1, all
+                                                         previous BiST state is cleared.
+                                                         NOTES:
+                                                         1) CLEAR_BIST must be written to 1 before START_BIST
+                                                         is written to 1 using a separate CSR write.
+                                                         2) CLEAR_BIST must not be changed after writing START_BIST
+                                                         0->1 until the BIST operation completes. */
+	uint64_t bist_start                   : 1;  /**< When software writes BIST_START=0->1, a BiST is executed
+                                                         for the DFM sub-block.
+                                                         NOTES:
+                                                         1) This bit should only be written after BOTH sclk
+                                                         and fclk have been enabled by software and are stable
+                                                         (see: DFM_FNT_SCLK[SCLKDIS] and instructions on how to
+                                                         enable the DFM DDR3 memory (fclk) - which requires LMC
+                                                         PLL init, DFM clock divider and proper DFM DLL
+                                                         initialization sequence). */
+	uint64_t sclkdis                      : 1;  /**< DFM sclk disable Source
+                                                         When SET, the DFM sclk are disabled (to conserve overall
+                                                         chip clocking power when the DFM function is not used).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+	uint64_t sclkdis                      : 1;
+	uint64_t bist_start                   : 1;
+	uint64_t clear_bist                   : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_dfm_fnt_sclk_s            cn63xx;
+	struct cvmx_dfm_fnt_sclk_s            cn63xxp1;
+};
+typedef union cvmx_dfm_fnt_sclk cvmx_dfm_fnt_sclk_t;
+
+/**
+ * cvmx_dfm_fnt_stat
+ *
+ * DFM_FNT_STAT = DFM Front Status Register
+ *
+ * This register contains error status information for the DFM Front Section of Logic.
+ */
+union cvmx_dfm_fnt_stat
+{
+	uint64_t u64;
+	struct cvmx_dfm_fnt_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t fsyn                         : 10; /**< Failing Syndrome
+                                                         If SBE_ERR=1, the FSYN code determines which bit was
+                                                         corrected during the OWECC check/correct.
+                                                         NOTE: If both DBE_ERR/SBE_ERR are set, the DBE_ERR has
+                                                         higher priority and FSYN captured will always be for the
+                                                         DBE_ERR detected.
+                                                         The FSYN is "locked down" when either DBE_ERR/SBE_ERR
+                                                         are detected (until these bits are cleared (W1C)).
+                                                         However, if an SBE_ERR occurs first, followed by a
+                                                         DBE_ERR, the higher priority DBE_ERR will re-capture
+                                                         the FSYN for the higher priority error case. */
+	uint64_t fadr                         : 28; /**< Failing Memory octaword address
+                                                         If either SBE_ERR or DBE_ERR are set, the FADR
+                                                         represents the failing octaword address.
+                                                         NOTE: If both DBE_ERR/SBE_ERR are set, the DBE_ERR has
+                                                         higher priority and the FADR captured will always be
+                                                         with the DBE_ERR detected.
+                                                         The FADR is "locked down" when either DBE_ERR/SBE_ERR
+                                                         are detected (until these bits are cleared (W1C)).
+                                                         However, if an SBE_ERR occurs first, followed by a
+                                                         DBE_ERR, the higher priority DBE_ERR will re-capture
+                                                         the FADR for the higher priority error case. */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t dbe_err                      : 1;  /**< Double bit error detected(uncorrectable) during
+                                                         Memory Read.
+                                                         Write of 1 will clear the corresponding error bit */
+	uint64_t sbe_err                      : 1;  /**< Single bit error detected(corrected) during
+                                                         Memory Read.
+                                                         Write of 1 will clear the corresponding error bit */
+#else
+	uint64_t sbe_err                      : 1;
+	uint64_t dbe_err                      : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t fadr                         : 28;
+	uint64_t fsyn                         : 10;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_dfm_fnt_stat_s            cn63xx;
+	struct cvmx_dfm_fnt_stat_s            cn63xxp1;
+};
+typedef union cvmx_dfm_fnt_stat cvmx_dfm_fnt_stat_t;
+
+/**
+ * cvmx_dfm_ifb_cnt
+ *
+ * DFM_IFB_CNT  = Performance Counters
+ *
+ */
+union cvmx_dfm_ifb_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfm_ifb_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t ifbcnt                       : 64; /**< Performance Counter
+                                                         64-bit counter that increments every
+                                                         cycle there is something in the in-flight buffer. */
+#else
+	uint64_t ifbcnt                       : 64;
+#endif
+	} s;
+	struct cvmx_dfm_ifb_cnt_s             cn63xx;
+	struct cvmx_dfm_ifb_cnt_s             cn63xxp1;
+};
+typedef union cvmx_dfm_ifb_cnt cvmx_dfm_ifb_cnt_t;
+
+/**
+ * cvmx_dfm_modereg_params0
+ *
+ * Notes:
+ * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
+ *
+ */
+union cvmx_dfm_modereg_params0
+{
+	uint64_t u64;
+	struct cvmx_dfm_modereg_params0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t ppd                          : 1;  /**< DLL Control for precharge powerdown
+                                                         0 = Slow exit (DLL off)
+                                                         1 = Fast exit (DLL on)
+                                                         DFM writes this value to MR0[PPD] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[PPD] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t wrp                          : 3;  /**< Write recovery for auto precharge
+                                                         Should be programmed to be equal to or greater than
+                                                         RNDUP[tWR(ns)/tCYC(ns)]
+                                                         000 = Reserved
+                                                         001 = 5
+                                                         010 = 6
+                                                         011 = 7
+                                                         100 = 8
+                                                         101 = 10
+                                                         110 = 12
+                                                         111 = Reserved
+                                                         DFM writes this value to MR0[WR] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[WR] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t dllr                         : 1;  /**< DLL Reset
+                                                         DFM writes this value to MR0[DLL] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[DLL] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t tm                           : 1;  /**< Test Mode
+                                                         DFM writes this value to MR0[TM] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[TM] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t rbt                          : 1;  /**< Read Burst Type
+                                                         1 = interleaved (fixed)
+                                                         DFM writes this value to MR0[RBT] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[RBT] value must be 1 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t cl                           : 4;  /**< CAS Latency
+                                                         0010 = 5
+                                                         0100 = 6
+                                                         0110 = 7
+                                                         1000 = 8
+                                                         1010 = 9
+                                                         1100 = 10
+                                                         1110 = 11
+                                                         0000, ???1 = Reserved
+                                                         DFM writes this value to MR0[CAS Latency / CL] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[CAS Latency / CL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t bl                           : 2;  /**< Burst Length
+                                                         0 = 8 (fixed)
+                                                         DFM writes this value to MR0[BL] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[BL] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t qoff                         : 1;  /**< Qoff Enable
+                                                         0 = enable
+                                                         DFM writes this value to MR1[Qoff] in the selected DDR3 parts
+                                                         during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[Qoff] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         The MR1[Qoff] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t tdqs                         : 1;  /**< TDQS Enable
+                                                         0 = disable
+                                                         DFM writes this value to MR1[TDQS] in the selected DDR3 parts
+                                                         during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[TDQS] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t wlev                         : 1;  /**< Write Leveling Enable
+                                                         0 = disable
+                                                         DFM writes MR1[Level]=0 in the selected DDR3 parts
+                                                         during power-up/init and write-leveling instruction sequencing.
+                                                         (DFM also writes MR1[Level]=1 at the beginning of a
+                                                         write-leveling instruction sequence. Write-leveling can only be initiated via the
+                                                         write-leveling instruction sequence.)
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         MR1[Level]=0 in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t al                           : 2;  /**< Additive Latency
+                                                         00 = 0
+                                                         01 = CL-1
+                                                         10 = CL-2
+                                                         11 = Reserved
+                                                         DFM writes this value to MR1[AL] in the selected DDR3 parts
+                                                         during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[AL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR1[AL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation.
+                                                         See also DFM_CONTROL[POCAS]. */
+	uint64_t dll                          : 1;  /**< DLL Enable
+                                                         0 = enable
+                                                         1 = disable
+                                                         DFM writes this value to MR1[DLL] in the selected DDR3 parts
+                                                         during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[DLL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR1[DLL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation.
+                                                         In dll-off mode, CL/CWL must be programmed
+                                                         equal to 6/6, respectively, as per the DDR3 specifications. */
+	uint64_t mpr                          : 1;  /**< MPR
+                                                         DFM writes this value to MR3[MPR] in the selected DDR3 parts
+                                                         during power-up/init and read-leveling instruction sequencing.
+                                                         (DFM also writes MR3[MPR]=1 at the beginning of a
+                                                         read-leveling instruction sequence. Read-leveling can only be initiated via the
+                                                         read-leveling instruction sequence.)
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR3[MPR] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t mprloc                       : 2;  /**< MPR Location
+                                                         DFM writes this value to MR3[MPRLoc] in the selected DDR3 parts
+                                                         during power-up/init and read-leveling instruction sequencing.
+                                                         (DFM also writes MR3[MPRLoc]=0 at the beginning of the
+                                                         read-leveling instruction sequence.)
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR3[MPRLoc] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t cwl                          : 3;  /**< CAS Write Latency
+                                                         - 000: 5
+                                                         - 001: 6
+                                                         - 010: 7
+                                                         - 011: 8
+                                                         1xx: Reserved
+                                                         DFM writes this value to MR2[CWL] in the selected DDR3 parts
+                                                         during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[CWL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh
+                                                         entry and exit instruction sequences.
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR2[CWL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+#else
+	uint64_t cwl                          : 3;
+	uint64_t mprloc                       : 2;
+	uint64_t mpr                          : 1;
+	uint64_t dll                          : 1;
+	uint64_t al                           : 2;
+	uint64_t wlev                         : 1;
+	uint64_t tdqs                         : 1;
+	uint64_t qoff                         : 1;
+	uint64_t bl                           : 2;
+	uint64_t cl                           : 4;
+	uint64_t rbt                          : 1;
+	uint64_t tm                           : 1;
+	uint64_t dllr                         : 1;
+	uint64_t wrp                          : 3;
+	uint64_t ppd                          : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_dfm_modereg_params0_s     cn63xx;
+	struct cvmx_dfm_modereg_params0_s     cn63xxp1;
+};
+typedef union cvmx_dfm_modereg_params0 cvmx_dfm_modereg_params0_t;
+
+/**
+ * cvmx_dfm_modereg_params1
+ *
+ * Notes:
+ * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
+ *
+ */
+union cvmx_dfm_modereg_params1
+{
+	uint64_t u64;
+	struct cvmx_dfm_modereg_params1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t rtt_nom_11                   : 3;  /**< Must be zero */
+	uint64_t dic_11                       : 2;  /**< Must be zero */
+	uint64_t rtt_wr_11                    : 2;  /**< Must be zero */
+	uint64_t srt_11                       : 1;  /**< Must be zero */
+	uint64_t asr_11                       : 1;  /**< Must be zero */
+	uint64_t pasr_11                      : 3;  /**< Must be zero */
+	uint64_t rtt_nom_10                   : 3;  /**< Must be zero */
+	uint64_t dic_10                       : 2;  /**< Must be zero */
+	uint64_t rtt_wr_10                    : 2;  /**< Must be zero */
+	uint64_t srt_10                       : 1;  /**< Must be zero */
+	uint64_t asr_10                       : 1;  /**< Must be zero */
+	uint64_t pasr_10                      : 3;  /**< Must be zero */
+	uint64_t rtt_nom_01                   : 3;  /**< RTT_NOM Rank 1
+                                                         DFM writes this value to MR1[Rtt_Nom] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[Rtt_Nom] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t dic_01                       : 2;  /**< Output Driver Impedance Control Rank 1
+                                                         DFM writes this value to MR1[D.I.C.] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[D.I.C.] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_01                    : 2;  /**< RTT_WR Rank 1
+                                                         DFM writes this value to MR2[Rtt_WR] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[Rtt_WR] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_01                       : 1;  /**< Self-refresh temperature range Rank 1
+                                                         DFM writes this value to MR2[SRT] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[SRT] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_01                       : 1;  /**< Auto self-refresh Rank 1
+                                                         DFM writes this value to MR2[ASR] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[ASR] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_01                      : 3;  /**< Partial array self-refresh Rank 1
+                                                         DFM writes this value to MR2[PASR] in the rank 1 (i.e. CS1) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[PASR] in all DRAM parts in rank 1 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_nom_00                   : 3;  /**< RTT_NOM Rank 0
+                                                         DFM writes this value to MR1[Rtt_Nom] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[Rtt_Nom] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t dic_00                       : 2;  /**< Output Driver Impedance Control Rank 0
+                                                         DFM writes this value to MR1[D.I.C.] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init and write-leveling instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR1[D.I.C.] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_00                    : 2;  /**< RTT_WR Rank 0
+                                                         DFM writes this value to MR2[Rtt_WR] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[Rtt_WR] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_00                       : 1;  /**< Self-refresh temperature range Rank 0
+                                                         DFM writes this value to MR2[SRT] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[SRT] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_00                       : 1;  /**< Auto self-refresh Rank 0
+                                                         DFM writes this value to MR2[ASR] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[ASR] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_00                      : 3;  /**< Partial array self-refresh Rank 0
+                                                         DFM writes this value to MR2[PASR] in the rank 0 (i.e. CS0) DDR3 parts
+                                                         when selected during power-up/init instruction sequencing.
+                                                         If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes
+                                                         this value to MR2[PASR] in all DRAM parts in rank 0 during self-refresh
+                                                         entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1).
+                                                         See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+#else
+	uint64_t pasr_00                      : 3;
+	uint64_t asr_00                       : 1;
+	uint64_t srt_00                       : 1;
+	uint64_t rtt_wr_00                    : 2;
+	uint64_t dic_00                       : 2;
+	uint64_t rtt_nom_00                   : 3;
+	uint64_t pasr_01                      : 3;
+	uint64_t asr_01                       : 1;
+	uint64_t srt_01                       : 1;
+	uint64_t rtt_wr_01                    : 2;
+	uint64_t dic_01                       : 2;
+	uint64_t rtt_nom_01                   : 3;
+	uint64_t pasr_10                      : 3;
+	uint64_t asr_10                       : 1;
+	uint64_t srt_10                       : 1;
+	uint64_t rtt_wr_10                    : 2;
+	uint64_t dic_10                       : 2;
+	uint64_t rtt_nom_10                   : 3;
+	uint64_t pasr_11                      : 3;
+	uint64_t asr_11                       : 1;
+	uint64_t srt_11                       : 1;
+	uint64_t rtt_wr_11                    : 2;
+	uint64_t dic_11                       : 2;
+	uint64_t rtt_nom_11                   : 3;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_dfm_modereg_params1_s     cn63xx;
+	struct cvmx_dfm_modereg_params1_s     cn63xxp1;
+};
+typedef union cvmx_dfm_modereg_params1 cvmx_dfm_modereg_params1_t;
+
+/**
+ * cvmx_dfm_ops_cnt
+ *
+ * DFM_OPS_CNT  = Performance Counters
+ *
+ */
+union cvmx_dfm_ops_cnt
+{
+	uint64_t u64;
+	struct cvmx_dfm_ops_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t opscnt                       : 64; /**< Performance Counter
+                                                         64-bit counter that increments when the DDR3 data bus
+                                                         is being used.
+                                                           DRAM bus utilization = DFM_OPS_CNT/DFM_FCLK_CNT */
+#else
+	uint64_t opscnt                       : 64;
+#endif
+	} s;
+	struct cvmx_dfm_ops_cnt_s             cn63xx;
+	struct cvmx_dfm_ops_cnt_s             cn63xxp1;
+};
+typedef union cvmx_dfm_ops_cnt cvmx_dfm_ops_cnt_t;
+
+/**
+ * cvmx_dfm_phy_ctl
+ *
+ * DFM_PHY_CTL = DFM PHY Control
+ *
+ */
+union cvmx_dfm_phy_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_phy_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t rx_always_on                 : 1;  /**< Disable dynamic DDR3 IO Rx power gating */
+	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
+	uint64_t ck_tune1                     : 1;  /**< Clock Tune
+
+                                                         NOTE: DFM UNUSED */
+	uint64_t ck_dlyout1                   : 4;  /**< Clock delay out setting
+
+                                                         NOTE: DFM UNUSED */
+	uint64_t ck_tune0                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout0                   : 4;  /**< Clock delay out setting */
+	uint64_t loopback                     : 1;  /**< Loopback enable */
+	uint64_t loopback_pos                 : 1;  /**< Loopback pos mode */
+	uint64_t ts_stagger                   : 1;  /**< TS Staggermode
+                                                         This mode configures output drivers with 2-stage drive
+                                                         strength to avoid undershoot issues on the bus when strong
+                                                         drivers are suddenly turned on. When this mode is asserted,
+                                                         Octeon will configure output drivers to be weak drivers
+                                                         (60 ohm output impedance) at the first FCLK cycle, and
+                                                         change drivers to the designated drive strengths specified
+                                                         in DFM_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting
+                                                         at the following cycle */
+#else
+	uint64_t ts_stagger                   : 1;
+	uint64_t loopback_pos                 : 1;
+	uint64_t loopback                     : 1;
+	uint64_t ck_dlyout0                   : 4;
+	uint64_t ck_tune0                     : 1;
+	uint64_t ck_dlyout1                   : 4;
+	uint64_t ck_tune1                     : 1;
+	uint64_t lv_mode                      : 1;
+	uint64_t rx_always_on                 : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_dfm_phy_ctl_s             cn63xx;
+	struct cvmx_dfm_phy_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
+	uint64_t ck_tune1                     : 1;  /**< Clock Tune
+
+                                                         NOTE: DFM UNUSED */
+	uint64_t ck_dlyout1                   : 4;  /**< Clock delay out setting
+
+                                                         NOTE: DFM UNUSED */
+	uint64_t ck_tune0                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout0                   : 4;  /**< Clock delay out setting */
+	uint64_t loopback                     : 1;  /**< Loopback enable */
+	uint64_t loopback_pos                 : 1;  /**< Loopback pos mode */
+	uint64_t ts_stagger                   : 1;  /**< TS Staggermode
+                                                         This mode configures output drivers with 2-stage drive
+                                                         strength to avoid undershoot issues on the bus when strong
+                                                         drivers are suddenly turned on. When this mode is asserted,
+                                                         Octeon will configure output drivers to be weak drivers
+                                                         (60 ohm output impedance) at the first FCLK cycle, and
+                                                         change drivers to the designated drive strengths specified
+                                                         in DFM_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting
+                                                         at the following cycle */
+#else
+	uint64_t ts_stagger                   : 1;
+	uint64_t loopback_pos                 : 1;
+	uint64_t loopback                     : 1;
+	uint64_t ck_dlyout0                   : 4;
+	uint64_t ck_tune0                     : 1;
+	uint64_t ck_dlyout1                   : 4;
+	uint64_t ck_tune1                     : 1;
+	uint64_t lv_mode                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_phy_ctl cvmx_dfm_phy_ctl_t;
+
+/**
+ * cvmx_dfm_reset_ctl
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *
+ * Notes:
+ * DDR3RST - DDR3 DRAM parts have a new RESET#
+ * pin that wasn't present in DDR2 parts. The
+ * DDR3RST CSR field controls the assertion of
+ * the new 63xx pin that attaches to RESET#.
+ * When DDR3RST is set, 63xx asserts RESET#.
+ * When DDR3RST is clear, 63xx de-asserts
+ * RESET#.
+ *
+ * DDR3RST is set on a cold reset. Warm and
+ * soft chip resets do not affect the DDR3RST
+ * value. Outside of cold reset, only software
+ * CSR writes change the DDR3RST value.
+ */
+union cvmx_dfm_reset_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_reset_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ddr3psv                      : 1;  /**< Must be zero */
+	uint64_t ddr3psoft                    : 1;  /**< Must be zero */
+	uint64_t ddr3pwarm                    : 1;  /**< Must be zero */
+	uint64_t ddr3rst                      : 1;  /**< Memory Reset
+                                                         0 = Reset asserted
+                                                         1 = Reset de-asserted */
+#else
+	uint64_t ddr3rst                      : 1;
+	uint64_t ddr3pwarm                    : 1;
+	uint64_t ddr3psoft                    : 1;
+	uint64_t ddr3psv                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_dfm_reset_ctl_s           cn63xx;
+	struct cvmx_dfm_reset_ctl_s           cn63xxp1;
+};
+typedef union cvmx_dfm_reset_ctl cvmx_dfm_reset_ctl_t;
+
+/**
+ * cvmx_dfm_rlevel_ctl
+ */
+union cvmx_dfm_rlevel_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_rlevel_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t delay_unload_3               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 3
+                                                         DELAY_UNLOAD_3 should normally be set, particularly at higher speeds. */
+	uint64_t delay_unload_2               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 2
+                                                         DELAY_UNLOAD_2 should normally not be set. */
+	uint64_t delay_unload_1               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 1
+                                                         DELAY_UNLOAD_1 should normally not be set. */
+	uint64_t delay_unload_0               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 0
+                                                         DELAY_UNLOAD_0 should normally not be set. */
+	uint64_t bitmask                      : 8;  /**< Mask to select bit lanes on which read-leveling
+                                                         feedback is returned when OR_DIS is set to 1 */
+	uint64_t or_dis                       : 1;  /**< Disable or'ing of bits in a byte lane when computing
+                                                         the read-leveling bitmask
+                                                         OR_DIS should normally not be set. */
+	uint64_t offset_en                    : 1;  /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read
+                                                         level dskew settings */
+	uint64_t offset                       : 4;  /**< Pick final_setting-offset (if set) for the read level
+                                                         deskew setting instead of the middle of the largest
+                                                         contiguous sequence of 1's in the bitmask */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 1
+                                                         Byte index for which bitmask results are saved
+                                                         in DFM_RLEVEL_DBG */
+#else
+	uint64_t byte                         : 4;
+	uint64_t offset                       : 4;
+	uint64_t offset_en                    : 1;
+	uint64_t or_dis                       : 1;
+	uint64_t bitmask                      : 8;
+	uint64_t delay_unload_0               : 1;
+	uint64_t delay_unload_1               : 1;
+	uint64_t delay_unload_2               : 1;
+	uint64_t delay_unload_3               : 1;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_dfm_rlevel_ctl_s          cn63xx;
+	struct cvmx_dfm_rlevel_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t offset_en                    : 1;  /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read
+                                                         level dskew settings */
+	uint64_t offset                       : 4;  /**< Pick final_setting-offset (if set) for the read level
+                                                         deskew setting instead of the middle of the largest
+                                                         contiguous sequence of 1's in the bitmask */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 1
+                                                         Byte index for which bitmask results are saved
+                                                         in DFM_RLEVEL_DBG */
+#else
+	uint64_t byte                         : 4;
+	uint64_t offset                       : 4;
+	uint64_t offset_en                    : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_rlevel_ctl cvmx_dfm_rlevel_ctl_t;
+
+/**
+ * cvmx_dfm_rlevel_dbg
+ *
+ * Notes:
+ * A given read of DFM_RLEVEL_DBG returns the read-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled.
+ * DFM_RLEVEL_CTL[BYTE] selects the particular byte.
+ * To get these pass/fail results for another different rank, you must run the hardware read-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run read-leveling separately for each rank, probing DFM_RLEVEL_DBG between each
+ * read-leveling.
+ */
+union cvmx_dfm_rlevel_dbg
+{
+	uint64_t u64;
+	struct cvmx_dfm_rlevel_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bitmask                      : 64; /**< Bitmask generated during deskew settings sweep
+                                                         BITMASK[n]=0 means deskew setting n failed
+                                                         BITMASK[n]=1 means deskew setting n passed
+                                                         for 0 <= n <= 63 */
+#else
+	uint64_t bitmask                      : 64;
+#endif
+	} s;
+	struct cvmx_dfm_rlevel_dbg_s          cn63xx;
+	struct cvmx_dfm_rlevel_dbg_s          cn63xxp1;
+};
+typedef union cvmx_dfm_rlevel_dbg cvmx_dfm_rlevel_dbg_t;
+
+/**
+ * cvmx_dfm_rlevel_rank#
+ *
+ * Notes:
+ * This is TWO CSRs per DFM, one per each rank.
+ *
+ * Deskew setting is measured in units of 1/4 FCLK, so the above BYTE* values can range over 16 FCLKs.
+ *
+ * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.)
+ * If HW is unable to find a match per DFM_RLEVEL_CTL[OFFSET_EN] and DFM_RLEVEL_CTL[OFFSET], then HW will set DFM_RLEVEL_RANKn[BYTE*<5:0>]
+ * to 0.
+ *
+ * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ *
+ * SW initiates a HW read-leveling sequence by programming DFM_RLEVEL_CTL and writing INIT_START=1 with SEQUENCE=1 in DFM_CONFIG.
+ * See DFM_RLEVEL_CTL.
+ */
+union cvmx_dfm_rlevel_rankx
+{
+	uint64_t u64;
+	struct cvmx_dfm_rlevel_rankx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
+                                                         the BYTE* programmings in <35:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = read-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete read-leveling sequence */
+	uint64_t reserved_12_53               : 42;
+	uint64_t byte1                        : 6;  /**< Deskew setting */
+	uint64_t byte0                        : 6;  /**< Deskew setting */
+#else
+	uint64_t byte0                        : 6;
+	uint64_t byte1                        : 6;
+	uint64_t reserved_12_53               : 42;
+	uint64_t status                       : 2;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_dfm_rlevel_rankx_s        cn63xx;
+	struct cvmx_dfm_rlevel_rankx_s        cn63xxp1;
+};
+typedef union cvmx_dfm_rlevel_rankx cvmx_dfm_rlevel_rankx_t;
+
+/**
+ * cvmx_dfm_rodt_mask
+ *
+ * DFM_RODT_MASK = DFM Read OnDieTermination mask
+ * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations
+ * especially on a multi-rank system. DDR3 DQ/DM/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that rank. System designers may prefer different combinations of ODT ON's for reads
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a read to that rank, it sets the 4 ODT pins to the MASK pins below.
+ * For eg., When doing a read into Rank0, a system designer may desire to terminate the lines
+ * with the resistor on Dimm0/Rank1. The mask RODT_D0_R0 would then be [00000010].
+ * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not
+ * required, write 0 in this register. Note that, as per the DDR3 specifications, the ODT pin
+ * for the rank that is being read should always be 0.
+ *
+ * Notes:
+ * - Notice that when there is only one rank, all valid fields must be zero.  This is because there is no
+ * "other" rank to terminate lines for.  Read ODT is meant for multirank systems.
+ * - For a two rank system and a read op to rank0: use RODT_D0_R0<1> to terminate lines on rank1.
+ * - For a two rank system and a read op to rank1: use RODT_D0_R1<0> to terminate lines on rank0.
+ * - Therefore, when a given RANK is selected, the RODT mask for that RANK is used.
+ *
+ * DFM always reads 128-bit words independently via one read CAS operation per word.
+ * When a RODT mask bit is set, DFM asserts the OCTEON ODT output
+ * pin(s) starting (CL - CWL) CK's after the read CAS operation. Then, OCTEON
+ * normally continues to assert the ODT output pin(s) for 5+DFM_CONTROL[RODT_BPRCH] more CK's
+ * - for a total of 6+DFM_CONTROL[RODT_BPRCH] CK's for the entire 128-bit read -
+ * satisfying the 6 CK DDR3 ODTH8 requirements.
+ *
+ * But it is possible for OCTEON to issue two 128-bit reads separated by as few as
+ * RtR = 4 or 5 (6 if DFM_CONTROL[RODT_BPRCH]=1) CK's. In that case, OCTEON asserts the ODT output pin(s)
+ * for the RODT mask of the first 128-bit read for RtR CK's, then asserts
+ * the ODT output pin(s) for the RODT mask of the second 128-bit read for 6+DFM_CONTROL[RODT_BPRCH] CK's
+ * (or less if a third 128-bit read follows within 4 or 5 (or 6) CK's of this second 128-bit read).
+ * Note that it may be necessary to force DFM to space back-to-back 128-bit reads
+ * to different ranks apart by at least 6+DFM_CONTROL[RODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
+ */
+union cvmx_dfm_rodt_mask
+{
+	uint64_t u64;
+	struct cvmx_dfm_rodt_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rodt_d3_r1                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d3_r0                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d2_r1                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d2_r0                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d1_r1                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d1_r0                   : 8;  /**< Must be zero. */
+	uint64_t rodt_d0_r1                   : 8;  /**< Read ODT mask RANK1
+                                                         RODT_D0_R1<7:1> must be zero in all cases.
+                                                         RODT_D0_R1<0> must also be zero if RANK_ENA is not set. */
+	uint64_t rodt_d0_r0                   : 8;  /**< Read ODT mask RANK0
+                                                         RODT_D0_R0<7:2,0> must be zero in all cases.
+                                                         RODT_D0_R0<1> must also be zero if RANK_ENA is not set. */
+#else
+	uint64_t rodt_d0_r0                   : 8;
+	uint64_t rodt_d0_r1                   : 8;
+	uint64_t rodt_d1_r0                   : 8;
+	uint64_t rodt_d1_r1                   : 8;
+	uint64_t rodt_d2_r0                   : 8;
+	uint64_t rodt_d2_r1                   : 8;
+	uint64_t rodt_d3_r0                   : 8;
+	uint64_t rodt_d3_r1                   : 8;
+#endif
+	} s;
+	struct cvmx_dfm_rodt_mask_s           cn63xx;
+	struct cvmx_dfm_rodt_mask_s           cn63xxp1;
+};
+typedef union cvmx_dfm_rodt_mask cvmx_dfm_rodt_mask_t;
+
+/**
+ * cvmx_dfm_slot_ctl0
+ *
+ * DFM_SLOT_CTL0 = DFM Slot Control0
+ * This register is an assortment of various control fields needed by the memory controller
+ *
+ * Notes:
+ * HW will update this register if SW has not previously written to it and when any of DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn, DFM_CONTROL and
+ * DFM_MODEREG_PARAMS0 change.Ideally, this register should only be read after DFM has been initialized and DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn
+ * have valid data.
+ * R2W_INIT has 1 extra CK cycle built in for odt settling/channel turnaround time.
+ */
+union cvmx_dfm_slot_ctl0
+{
+	uint64_t u64;
+	struct cvmx_dfm_slot_ctl0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t w2w_init                     : 6;  /**< Write-to-write spacing control
+                                                         for back to back accesses to the same rank and dimm */
+	uint64_t w2r_init                     : 6;  /**< Write-to-read spacing control
+                                                         for back to back accesses to the same rank and dimm */
+	uint64_t r2w_init                     : 6;  /**< Read-to-write spacing control
+                                                         for back to back accesses to the same rank and dimm */
+	uint64_t r2r_init                     : 6;  /**< Read-to-read spacing control
+                                                         for back to back accesses to the same rank and dimm */
+#else
+	uint64_t r2r_init                     : 6;
+	uint64_t r2w_init                     : 6;
+	uint64_t w2r_init                     : 6;
+	uint64_t w2w_init                     : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_dfm_slot_ctl0_s           cn63xx;
+	struct cvmx_dfm_slot_ctl0_s           cn63xxp1;
+};
+typedef union cvmx_dfm_slot_ctl0 cvmx_dfm_slot_ctl0_t;
+
+/**
+ * cvmx_dfm_slot_ctl1
+ *
+ * DFM_SLOT_CTL1 = DFM Slot Control1
+ * This register is an assortment of various control fields needed by the memory controller
+ *
+ * Notes:
+ * HW will update this register if SW has not previously written to it and when any of DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn, DFM_CONTROL and
+ * DFM_MODEREG_PARAMS0 change.Ideally, this register should only be read after DFM has been initialized and DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn
+ * have valid data.
+ * R2W_XRANK_INIT, W2R_XRANK_INIT have 1 extra CK cycle built in for odt settling/channel turnaround time.
+ */
+union cvmx_dfm_slot_ctl1
+{
+	uint64_t u64;
+	struct cvmx_dfm_slot_ctl1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t w2w_xrank_init               : 6;  /**< Write-to-write spacing control
+                                                         for back to back accesses across ranks of the same dimm */
+	uint64_t w2r_xrank_init               : 6;  /**< Write-to-read spacing control
+                                                         for back to back accesses across ranks of the same dimm */
+	uint64_t r2w_xrank_init               : 6;  /**< Read-to-write spacing control
+                                                         for back to back accesses across ranks of the same dimm */
+	uint64_t r2r_xrank_init               : 6;  /**< Read-to-read spacing control
+                                                         for back to back accesses across ranks of the same dimm */
+#else
+	uint64_t r2r_xrank_init               : 6;
+	uint64_t r2w_xrank_init               : 6;
+	uint64_t w2r_xrank_init               : 6;
+	uint64_t w2w_xrank_init               : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_dfm_slot_ctl1_s           cn63xx;
+	struct cvmx_dfm_slot_ctl1_s           cn63xxp1;
+};
+typedef union cvmx_dfm_slot_ctl1 cvmx_dfm_slot_ctl1_t;
+
+/**
+ * cvmx_dfm_timing_params0
+ */
+union cvmx_dfm_timing_params0
+{
+	uint64_t u64;
+	struct cvmx_dfm_timing_params0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLk constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))],
+                                                         where tDLLk is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t tckeon                       : 10; /**< Reserved. Should be written to zero. */
+#else
+	uint64_t tckeon                       : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t trp_ext                      : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfm_timing_params0_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLk constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))],
+                                                         where tDLLk is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t reserved_0_9                 : 10;
+#else
+	uint64_t reserved_0_9                 : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t trp_ext                      : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} cn63xx;
+	struct cvmx_dfm_timing_params0_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLk constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))],
+                                                         where tDLLk is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t tckeon                       : 10; /**< Reserved. Should be written to zero. */
+#else
+	uint64_t tckeon                       : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_timing_params0 cvmx_dfm_timing_params0_t;
+
+/**
+ * cvmx_dfm_timing_params1
+ */
+union cvmx_dfm_timing_params1
+{
+	uint64_t u64;
+	struct cvmx_dfm_timing_params1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t tras_ext                     : 1;  /**< Indicates tRAS constraints.
+                                                         Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 000000: RESERVED
+                                                             - 000001: 2 tCYC
+                                                             - 000010: 3 tCYC
+                                                             - ...
+                                                             - 111111: 64 tCYC */
+	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
+                                                         Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
+                                                         where tXPDLL is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(10nCK, 24ns) */
+	uint64_t tfaw                         : 5;  /**< Indicates tFAW constraints.
+                                                         Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))],
+                                                         where tFAW is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=30-40ns */
+	uint64_t twldqsen                     : 4;  /**< Indicates tWLDQSEN constraints.
+                                                         Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))],
+                                                         where tWLDQSEN is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(25nCK) */
+	uint64_t twlmrd                       : 4;  /**< Indicates tWLMRD constraints.
+                                                         Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))],
+                                                         where tWLMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(40nCK) */
+	uint64_t txp                          : 3;  /**< Indicates tXP constraints.
+                                                         Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1,
+                                                         where tXP is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5ns) */
+	uint64_t trrd                         : 3;  /**< Indicates tRRD constraints.
+                                                         Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2,
+                                                         where tRRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 10ns)
+                                                            - 000: RESERVED
+                                                            - 001: 3 tCYC
+                                                            - ...
+                                                            - 110: 8 tCYC
+                                                            - 111: 9 tCYC */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))],
+                                                         where tRFC is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=90-350ns
+                                                              - 00000: RESERVED
+                                                              - 00001: 8 tCYC
+                                                              - 00010: 16 tCYC
+                                                              - 00011: 24 tCYC
+                                                              - 00100: 32 tCYC
+                                                              - ...
+                                                              - 11110: 240 tCYC
+                                                              - 11111: 248 tCYC */
+	uint64_t twtr                         : 4;  /**< Indicates tWTR constraints.
+                                                         Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1,
+                                                         where tWTR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 7.5ns)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2
+                                                             - ...
+                                                             - 0111: 8
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< Indicates tRCD constraints.
+                                                         Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)],
+                                                         where tRCD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=10-15ns
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
+                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 00000: RESERVED
+                                                             - 00001: 2 tCYC
+                                                             - 00010: 3 tCYC
+                                                             - ...
+                                                             - 11111: 32 tCYC */
+	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
+                                                         Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
+                                                         where tMPRR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=1nCK */
+#else
+	uint64_t tmprr                        : 4;
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trfc                         : 5;
+	uint64_t trrd                         : 3;
+	uint64_t txp                          : 3;
+	uint64_t twlmrd                       : 4;
+	uint64_t twldqsen                     : 4;
+	uint64_t tfaw                         : 5;
+	uint64_t txpdll                       : 5;
+	uint64_t tras_ext                     : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfm_timing_params1_s      cn63xx;
+	struct cvmx_dfm_timing_params1_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
+                                                         Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
+                                                         where tXPDLL is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(10nCK, 24ns) */
+	uint64_t tfaw                         : 5;  /**< Indicates tFAW constraints.
+                                                         Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))],
+                                                         where tFAW is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=30-40ns */
+	uint64_t twldqsen                     : 4;  /**< Indicates tWLDQSEN constraints.
+                                                         Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))],
+                                                         where tWLDQSEN is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(25nCK) */
+	uint64_t twlmrd                       : 4;  /**< Indicates tWLMRD constraints.
+                                                         Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))],
+                                                         where tWLMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(40nCK) */
+	uint64_t txp                          : 3;  /**< Indicates tXP constraints.
+                                                         Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1,
+                                                         where tXP is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5ns) */
+	uint64_t trrd                         : 3;  /**< Indicates tRRD constraints.
+                                                         Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2,
+                                                         where tRRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 10ns)
+                                                            - 000: RESERVED
+                                                            - 001: 3 tCYC
+                                                            - ...
+                                                            - 110: 8 tCYC
+                                                            - 111: 9 tCYC */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))],
+                                                         where tRFC is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=90-350ns
+                                                              - 00000: RESERVED
+                                                              - 00001: 8 tCYC
+                                                              - 00010: 16 tCYC
+                                                              - 00011: 24 tCYC
+                                                              - 00100: 32 tCYC
+                                                              - ...
+                                                              - 11110: 240 tCYC
+                                                              - 11111: 248 tCYC */
+	uint64_t twtr                         : 4;  /**< Indicates tWTR constraints.
+                                                         Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1,
+                                                         where tWTR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 7.5ns)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2
+                                                             - ...
+                                                             - 0111: 8
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< Indicates tRCD constraints.
+                                                         Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)],
+                                                         where tRCD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=10-15ns
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
+                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 00000: RESERVED
+                                                             - 00001: 2 tCYC
+                                                             - 00010: 3 tCYC
+                                                             - ...
+                                                             - 11111: 32 tCYC */
+	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
+                                                         Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
+                                                         where tMPRR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=1nCK */
+#else
+	uint64_t tmprr                        : 4;
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trfc                         : 5;
+	uint64_t trrd                         : 3;
+	uint64_t txp                          : 3;
+	uint64_t twlmrd                       : 4;
+	uint64_t twldqsen                     : 4;
+	uint64_t tfaw                         : 5;
+	uint64_t txpdll                       : 5;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_timing_params1 cvmx_dfm_timing_params1_t;
+
+/**
+ * cvmx_dfm_wlevel_ctl
+ */
+union cvmx_dfm_wlevel_ctl
+{
+	uint64_t u64;
+	struct cvmx_dfm_wlevel_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t rtt_nom                      : 3;  /**< RTT_NOM
+                                                         DFM writes a decoded value to MR1[Rtt_Nom] of the rank during
+                                                         write leveling. Per JEDEC DDR3 specifications,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6)
+                                                         are allowed during write leveling with output buffer enabled.
+                                                         000 : DFM writes 001 (RZQ/4)   to MR1[Rtt_Nom]
+                                                         001 : DFM writes 010 (RZQ/2)   to MR1[Rtt_Nom]
+                                                         010 : DFM writes 011 (RZQ/6)   to MR1[Rtt_Nom]
+                                                         011 : DFM writes 100 (RZQ/12)  to MR1[Rtt_Nom]
+                                                         100 : DFM writes 101 (RZQ/8)   to MR1[Rtt_Nom]
+                                                         101 : DFM writes 110 (Rsvd)    to MR1[Rtt_Nom]
+                                                         110 : DFM writes 111 (Rsvd)    to  MR1[Rtt_Nom]
+                                                         111 : DFM writes 000 (Disabled) to MR1[Rtt_Nom] */
+	uint64_t bitmask                      : 8;  /**< Mask to select bit lanes on which write-leveling
+                                                         feedback is returned when OR_DIS is set to 1 */
+	uint64_t or_dis                       : 1;  /**< Disable or'ing of bits in a byte lane when computing
+                                                         the write-leveling bitmask */
+	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
+	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
+                                                         the write-leveling sequence
+                                                         Used with x16 parts where the upper and lower byte
+                                                         lanes need to be leveled independently
+                                                         LANEMASK<8:2> must be zero. */
+#else
+	uint64_t lanemask                     : 9;
+	uint64_t sset                         : 1;
+	uint64_t or_dis                       : 1;
+	uint64_t bitmask                      : 8;
+	uint64_t rtt_nom                      : 3;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_dfm_wlevel_ctl_s          cn63xx;
+	struct cvmx_dfm_wlevel_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
+	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
+                                                         the write-leveling sequence
+                                                         Used with x16 parts where the upper and lower byte
+                                                         lanes need to be leveled independently
+                                                         LANEMASK<8:2> must be zero. */
+#else
+	uint64_t lanemask                     : 9;
+	uint64_t sset                         : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dfm_wlevel_ctl cvmx_dfm_wlevel_ctl_t;
+
+/**
+ * cvmx_dfm_wlevel_dbg
+ *
+ * Notes:
+ * A given write of DFM_WLEVEL_DBG returns the write-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW write-leveled.
+ * DFM_WLEVEL_DBG[BYTE] selects the particular byte.
+ * To get these pass/fail results for another different rank, you must run the hardware write-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run write-leveling separately for each rank, probing DFM_WLEVEL_DBG between each
+ * write-leveling.
+ */
+union cvmx_dfm_wlevel_dbg
+{
+	uint64_t u64;
+	struct cvmx_dfm_wlevel_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t bitmask                      : 8;  /**< Bitmask generated during deskew settings sweep
+                                                         if DFM_WLEVEL_CTL[SSET]=0
+                                                           BITMASK[n]=0 means deskew setting n failed
+                                                           BITMASK[n]=1 means deskew setting n passed
+                                                           for 0 <= n <= 7
+                                                           BITMASK contains the first 8 results of the total 16
+                                                           collected by DFM during the write-leveling sequence
+                                                         else if DFM_WLEVEL_CTL[SSET]=1
+                                                           BITMASK[0]=0 means curr deskew setting failed
+                                                           BITMASK[0]=1 means curr deskew setting passed */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 8 */
+#else
+	uint64_t byte                         : 4;
+	uint64_t bitmask                      : 8;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_dfm_wlevel_dbg_s          cn63xx;
+	struct cvmx_dfm_wlevel_dbg_s          cn63xxp1;
+};
+typedef union cvmx_dfm_wlevel_dbg cvmx_dfm_wlevel_dbg_t;
+
+/**
+ * cvmx_dfm_wlevel_rank#
+ *
+ * Notes:
+ * This is TWO CSRs per DFM, one per each rank. (front bunk/back bunk)
+ *
+ * Deskew setting is measured in units of 1/8 FCLK, so the above BYTE* values can range over 4 FCLKs.
+ *
+ * Assuming DFM_WLEVEL_CTL[SSET]=0, the BYTE*<2:0> values are not used during write-leveling, and
+ * they are over-written by the hardware as part of the write-leveling sequence. (HW sets STATUS==3
+ * after HW write-leveling completes for the rank). SW needs to set BYTE*<4:3> bits.
+ *
+ * Each CSR may also be written by SW, but not while a write-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ *
+ * SW initiates a HW write-leveling sequence by programming DFM_WLEVEL_CTL and writing RANKMASK and INIT_START=1 with SEQUENCE=6 in DFM_CONFIG.
+ * DFM will then step through and accumulate write leveling results for 8 unique delay settings (twice), starting at a delay of
+ * DFM_WLEVEL_RANKn[BYTE*<4:3>]*8 CK increasing by 1/8 CK each setting. HW will then set DFM_WLEVEL_RANKn[BYTE*<2:0>] to indicate the
+ * first write leveling result of '1' that followed a reslt of '0' during the sequence by searching for a '1100' pattern in the generated
+ * bitmask, except that DFM will always write DFM_WLEVEL_RANKn[BYTE*<0>]=0. If HW is unable to find a match for a '1100' pattern, then HW will
+ * set DFM_WLEVEL_RANKn[BYTE*<2:0>] to 4.
+ * See DFM_WLEVEL_CTL.
+ */
+union cvmx_dfm_wlevel_rankx
+{
+	uint64_t u64;
+	struct cvmx_dfm_wlevel_rankx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t status                       : 2;  /**< Indicates status of the write-leveling and where
+                                                         the BYTE* programmings in <44:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = write-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete write-leveling sequence, irrespective of
+                                                             which lanes are masked via DFM_WLEVEL_CTL[LANEMASK] */
+	uint64_t reserved_10_44               : 35;
+	uint64_t byte1                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE1 must be zero during normal operation */
+	uint64_t byte0                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE0 must be zero during normal operation */
+#else
+	uint64_t byte0                        : 5;
+	uint64_t byte1                        : 5;
+	uint64_t reserved_10_44               : 35;
+	uint64_t status                       : 2;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_dfm_wlevel_rankx_s        cn63xx;
+	struct cvmx_dfm_wlevel_rankx_s        cn63xxp1;
+};
+typedef union cvmx_dfm_wlevel_rankx cvmx_dfm_wlevel_rankx_t;
+
+/**
+ * cvmx_dfm_wodt_mask
+ *
+ * DFM_WODT_MASK = DFM Write OnDieTermination mask
+ * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations
+ * especially on a multi-rank system. DDR3 DQ/DM/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that rank. System designers may prefer different combinations of ODT ON's for writes
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a write to that rank, it sets the 4 ODT pins to the MASK pins below.
+ * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines
+ * with the resistor on Dimm0/Rank1. The mask WODT_D0_R0 would then be [00000010].
+ * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not
+ * required, write 0 in this register.
+ *
+ * Notes:
+ * - DFM_WODT_MASK functions a little differently than DFM_RODT_MASK.  While, in DFM_RODT_MASK, the other
+ * rank(s) are ODT-ed, in DFM_WODT_MASK, the rank in which the write CAS is issued can be ODT-ed as well.
+ * - For a two rank system and a write op to rank0: use RODT_D0_R0<1:0> to terminate lines on rank1 and/or rank0.
+ * - For a two rank system and a write op to rank1: use RODT_D0_R1<1:0> to terminate lines on rank1 and/or rank0.
+ * - When a given RANK is selected, the WODT mask for that RANK is used.
+ *
+ * DFM always writes 128-bit words independently via one write CAS operation per word.
+ * When a WODT mask bit is set, DFM asserts the OCTEON ODT output pin(s) starting the same cycle
+ * as the write CAS operation. Then, OCTEON normally continues to assert the ODT output pin(s) for five
+ * more cycles - for a total of 6 cycles for the entire word write - satisfying the 6 cycle DDR3
+ * ODTH8 requirements. But it is possible for DFM to issue two word writes  separated by as few
+ * as WtW = 4 or 5 cycles. In that case, DFM asserts the ODT output pin(s) for the WODT mask of the
+ * first word write for WtW cycles, then asserts the ODT output pin(s) for the WODT mask of the
+ * second write for 6 cycles (or less if a third word write follows within 4 or 5
+ * cycles of this second word write). Note that it may be necessary to force DFM to space back-to-back
+ * word writes to different ranks apart by at least 6 cycles to prevent DDR3 ODTH8 violations.
+ */
+union cvmx_dfm_wodt_mask
+{
+	uint64_t u64;
+	struct cvmx_dfm_wodt_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wodt_d3_r1                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d3_r0                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d2_r1                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d2_r0                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d1_r1                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d1_r0                   : 8;  /**< Not used by DFM. */
+	uint64_t wodt_d0_r1                   : 8;  /**< Write ODT mask RANK1
+                                                         WODT_D0_R1<7:2> not used by DFM.
+                                                         WODT_D0_R1<1:0> is also not used by DFM when RANK_ENA is not set. */
+	uint64_t wodt_d0_r0                   : 8;  /**< Write ODT mask RANK0
+                                                         WODT_D0_R0<7:2> not used by DFM. */
+#else
+	uint64_t wodt_d0_r0                   : 8;
+	uint64_t wodt_d0_r1                   : 8;
+	uint64_t wodt_d1_r0                   : 8;
+	uint64_t wodt_d1_r1                   : 8;
+	uint64_t wodt_d2_r0                   : 8;
+	uint64_t wodt_d2_r1                   : 8;
+	uint64_t wodt_d3_r0                   : 8;
+	uint64_t wodt_d3_r1                   : 8;
+#endif
+	} s;
+	struct cvmx_dfm_wodt_mask_s           cn63xx;
+	struct cvmx_dfm_wodt_mask_s           cn63xxp1;
+};
+typedef union cvmx_dfm_wodt_mask cvmx_dfm_wodt_mask_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-dma-engine.c b/sys/contrib/octeon-sdk/cvmx-dma-engine.c
index ad793ea..a3718bd 100644
--- a/sys/contrib/octeon-sdk/cvmx-dma-engine.c
+++ b/sys/contrib/octeon-sdk/cvmx-dma-engine.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 50126 $<hr>
  */
 #include "executive-config.h"
 #include "cvmx-config.h"
@@ -64,13 +66,15 @@
  */
 int cvmx_dma_engine_get_num(void)
 {
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
             return 4;
         else
             return 5;
     }
+    else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        return 8;
     else
         return 2;
 }
@@ -82,7 +86,6 @@ int cvmx_dma_engine_get_num(void)
  */
 int cvmx_dma_engine_initialize(void)
 {
-    cvmx_npei_dmax_ibuff_saddr_t dmax_ibuff_saddr;
     int engine;
 
     for (engine=0; engine < cvmx_dma_engine_get_num(); engine++)
@@ -93,20 +96,32 @@ int cvmx_dma_engine_initialize(void)
                                            CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
         if (result != CVMX_CMD_QUEUE_SUCCESS)
             return -1;
-        dmax_ibuff_saddr.u64 = 0;
-        dmax_ibuff_saddr.s.saddr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DMA(engine))) >> 7;
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+        {
+            cvmx_npei_dmax_ibuff_saddr_t dmax_ibuff_saddr;
+            dmax_ibuff_saddr.u64 = 0;
+            dmax_ibuff_saddr.s.saddr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DMA(engine))) >> 7;
             cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), dmax_ibuff_saddr.u64);
+        }
+        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        {
+            cvmx_dpi_dmax_ibuff_saddr_t dpi_dmax_ibuff_saddr;
+            dpi_dmax_ibuff_saddr.u64 = 0;
+            dpi_dmax_ibuff_saddr.s.csize = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+            dpi_dmax_ibuff_saddr.s.saddr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DMA(engine))) >> 7;
+            cvmx_write_csr(CVMX_DPI_DMAX_IBUFF_SADDR(engine), dpi_dmax_ibuff_saddr.u64);
+        }
         else
         {
+            uint64_t address = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DMA(engine)));
             if (engine)
-                cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, dmax_ibuff_saddr.u64);
+                cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, address);
             else
-                cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, dmax_ibuff_saddr.u64);
+                cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, address);
         }
     }
 
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
         cvmx_npei_dma_control_t dma_control;
         dma_control.u64 = 0;
@@ -135,6 +150,37 @@ int cvmx_dma_engine_initialize(void)
             cvmx_write_csr(CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM, pcie_req_num.u64);
         }
     }
+    else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        cvmx_dpi_engx_buf_t dpi_engx_buf;
+        cvmx_dpi_dma_control_t dma_control;
+        cvmx_dpi_ctl_t dpi_ctl;
+
+        /* Give engine 0-4 1KB, and 5 3KB. This gives the packet engines better
+            performance. Total must not exceed 8KB */
+        dpi_engx_buf.u64 = 0;
+        dpi_engx_buf.s.blks = 2;
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(0), dpi_engx_buf.u64);
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(1), dpi_engx_buf.u64);
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(2), dpi_engx_buf.u64);
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(3), dpi_engx_buf.u64);
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(4), dpi_engx_buf.u64);
+        dpi_engx_buf.s.blks = 6;
+        cvmx_write_csr(CVMX_DPI_ENGX_BUF(5), dpi_engx_buf.u64);
+
+        dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
+        dma_control.s.pkt_hp = 1;
+        dma_control.s.pkt_en = 1;
+        dma_control.s.dma_enb = 0x1f;
+        dma_control.s.dwb_denb = 1;
+        dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+        dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
+        dma_control.s.o_mode = 1;
+        cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
+        dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
+        dpi_ctl.s.en = 1;
+        cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
+    }
     else
     {
         cvmx_npi_dma_control_t dma_control;
@@ -172,7 +218,7 @@ int cvmx_dma_engine_shutdown(void)
         }
     }
 
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
         cvmx_npei_dma_control_t dma_control;
         dma_control.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMA_CONTROL);
@@ -186,6 +232,15 @@ int cvmx_dma_engine_shutdown(void)
         /* Make sure the disable completes */
         cvmx_read_csr(CVMX_PEXP_NPEI_DMA_CONTROL);
     }
+    else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        cvmx_dpi_dma_control_t dma_control;
+        dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
+        dma_control.s.dma_enb = 0;
+        cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
+        /* Make sure the disable completes */
+        cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
+    }
     else
     {
         cvmx_npi_dma_control_t dma_control;
@@ -200,8 +255,10 @@ int cvmx_dma_engine_shutdown(void)
     for (engine=0; engine < cvmx_dma_engine_get_num(); engine++)
     {
         cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_DMA(engine));
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
             cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), 0);
+        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+            cvmx_write_csr(CVMX_DPI_DMAX_IBUFF_SADDR(engine), 0);
         else
         {
             if (engine)
@@ -218,7 +275,7 @@ int cvmx_dma_engine_shutdown(void)
 /**
  * Submit a series of DMA comamnd to the DMA engines.
  *
- * @param engine  Engine to submit to (0-4)
+ * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
@@ -262,11 +319,13 @@ int cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_
     /* A syncw isn't needed here since the command queue did one as part of the queue unlock */
     if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
     {
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
         {
             /* DMA doorbells are 32bit writes in little endian space. This means we need to xor the address with 4 */
             cvmx_write64_uint32(CVMX_PEXP_NPEI_DMAX_DBELL(engine)^4, cmd_count);
         }
+        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+            cvmx_write_csr(CVMX_DPI_DMAX_DBELL(engine), cmd_count);
         else
         {
             if (engine)
@@ -414,7 +473,7 @@ static inline int __cvmx_dma_engine_build_external_pointers(cvmx_dma_engine_buff
  * or PCI / PCIe address list. This function does not support gather lists,
  * so you will need to build your own lists in that case.
  *
- * @param engine Engine to submit to (0-4)
+ * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header DMA Command header. Note that the nfst and nlst fields do not
  *               need to be filled in. All other fields must be set properly.
  * @param first_address
diff --git a/sys/contrib/octeon-sdk/cvmx-dma-engine.h b/sys/contrib/octeon-sdk/cvmx-dma-engine.h
index d17c790..c83b7c1 100644
--- a/sys/contrib/octeon-sdk/cvmx-dma-engine.h
+++ b/sys/contrib/octeon-sdk/cvmx-dma-engine.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_DMA_ENGINES_H__
@@ -264,7 +266,7 @@ int cvmx_dma_engine_get_num(void);
 /**
  * Submit a series of DMA comamnd to the DMA engines.
  *
- * @param engine  Engine to submit to (0-4)
+ * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
@@ -282,7 +284,7 @@ int cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_
  * or PCI / PCIe address list. This function does not support gather lists,
  * so you will need to build your own lists in that case.
  *
- * @param engine Engine to submit to (0-4)
+ * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header DMA Command header. Note that the nfst and nlst fields do not
  *               need to be filled in. All other fields must be set properly.
  * @param first_address
@@ -304,7 +306,7 @@ int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
 /**
  * Simplified interface to the DMA engines to emulate memcpy()
  *
- * @param engine Engine to submit to (0-4)
+ * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param dest   Pointer to the destination memory. cvmx_ptr_to_phys() will be
  *               used to turn this into a physical address. It cannot be a local
  *               or CVMX_SHARED block.
diff --git a/sys/contrib/octeon-sdk/cvmx-dpi-defs.h b/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
new file mode 100644
index 0000000..564f9b0
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
@@ -0,0 +1,1305 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-dpi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dpi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_DPI_TYPEDEFS_H__
+#define __CVMX_DPI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000000ull);
+}
+#else
+#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC()
+static inline uint64_t CVMX_DPI_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000040ull);
+}
+#else
+#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000048ull);
+}
+#else
+#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC()
+static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000980ull);
+}
+#else
+#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC()
+static inline uint64_t CVMX_DPI_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000010ull);
+}
+#else
+#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC()
+static inline uint64_t CVMX_DPI_INT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000008ull);
+}
+#else
+#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC()
+static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000830ull);
+}
+#else
+#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC()
+static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000078ull);
+}
+#else
+#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC()
+static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000058ull);
+}
+#else
+#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC()
+static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000068ull);
+}
+#else
+#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC()
+static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000060ull);
+}
+#else
+#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC()
+static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000070ull);
+}
+#else
+#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC()
+static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001DF0000000050ull);
+}
+#else
+#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_DPI_SLI_PRTX_ERR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_DPI_SLI_PRTX_ERR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8)
+#endif
+
+/**
+ * cvmx_dpi_bist_status
+ */
+union cvmx_dpi_bist_status
+{
+	uint64_t u64;
+	struct cvmx_dpi_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t bist                         : 37; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 37;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_dpi_bist_status_s         cn63xx;
+	struct cvmx_dpi_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t;
+
+/**
+ * cvmx_dpi_ctl
+ */
+union cvmx_dpi_ctl
+{
+	uint64_t u64;
+	struct cvmx_dpi_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t clk                          : 1;  /**< Status bit that indicates that the clks are running */
+	uint64_t en                           : 1;  /**< Turns on the DMA and Packet state machines */
+#else
+	uint64_t en                           : 1;
+	uint64_t clk                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_dpi_ctl_s                 cn63xx;
+	struct cvmx_dpi_ctl_s                 cn63xxp1;
+};
+typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t;
+
+/**
+ * cvmx_dpi_dma#_counts
+ *
+ * DPI_DMA[0..7]_COUNTS = DMA Instruction Counts
+ *
+ * Values for determing the number of instructions for DMA[0..7] in the DPI.
+ */
+union cvmx_dpi_dmax_counts
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO locally
+                                                         cached within DPI. */
+	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t fcnt                         : 7;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_counts_s         cn63xx;
+	struct cvmx_dpi_dmax_counts_s         cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t;
+
+/**
+ * cvmx_dpi_dma#_dbell
+ *
+ * DPI_DMA_DBELL[0..7] = DMA Door Bell
+ *
+ * The door bell register for DMA[0..7] queue.
+ */
+union cvmx_dpi_dmax_dbell
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dbell                        : 16; /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the low priority dma queue. */
+#else
+	uint64_t dbell                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_dbell_s          cn63xx;
+	struct cvmx_dpi_dmax_dbell_s          cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t;
+
+/**
+ * cvmx_dpi_dma#_ibuff_saddr
+ *
+ * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
+ *
+ * The address to start reading Instructions from for DMA[0..7].
+ */
+union cvmx_dpi_dmax_ibuff_saddr
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_ibuff_saddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t csize                        : 14; /**< The size in 8B words of the DMA Instruction Chunk.
+                                                         This value should only be written at known times
+                                                         in order to prevent corruption of the instruction
+                                                         queue.  The minimum CSIZE is 16 (one cacheblock). */
+	uint64_t reserved_41_47               : 7;
+	uint64_t idle                         : 1;  /**< DMA Request Queue is IDLE */
+	uint64_t reserved_36_39               : 4;
+	uint64_t saddr                        : 29; /**< The 128 byte aligned starting or chunk address.
+                                                         SADDR is address bit 35:7 of the starting
+                                                         instructions address. When new chunks are fetched
+                                                         by the HW, SADDR will be updated to reflect the
+                                                         address of the current chunk.
+                                                         A write to SADDR resets both the queue's doorbell
+                                                         (DPI_DMAx_COUNTS[DBELL) and its tail pointer
+                                                         (DPI_DMAx_NADDR[ADDR]). */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t saddr                        : 29;
+	uint64_t reserved_36_39               : 4;
+	uint64_t idle                         : 1;
+	uint64_t reserved_41_47               : 7;
+	uint64_t csize                        : 14;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_ibuff_saddr_s    cn63xx;
+	struct cvmx_dpi_dmax_ibuff_saddr_s    cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t;
+
+/**
+ * cvmx_dpi_dma#_naddr
+ *
+ * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address
+ *
+ * Place DPI will read the next Ichunk data from.
+ */
+union cvmx_dpi_dmax_naddr
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_naddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< The next L2C address to read DMA# instructions
+                                                         from. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_naddr_s          cn63xx;
+	struct cvmx_dpi_dmax_naddr_s          cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t;
+
+/**
+ * cvmx_dpi_dma#_reqbnk0
+ *
+ * DPI_DMA[0..7]_REQBNK0 = DMA Request State Bank0
+ *
+ * Current contents of the request state machine - bank0
+ */
+union cvmx_dpi_dmax_reqbnk0
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_reqbnk0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t state                        : 64; /**< State */
+#else
+	uint64_t state                        : 64;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn63xx;
+	struct cvmx_dpi_dmax_reqbnk0_s        cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t;
+
+/**
+ * cvmx_dpi_dma#_reqbnk1
+ *
+ * DPI_DMA[0..7]_REQBNK1 = DMA Request State Bank1
+ *
+ * Current contents of the request state machine - bank1
+ */
+union cvmx_dpi_dmax_reqbnk1
+{
+	uint64_t u64;
+	struct cvmx_dpi_dmax_reqbnk1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t state                        : 64; /**< State */
+#else
+	uint64_t state                        : 64;
+#endif
+	} s;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn63xx;
+	struct cvmx_dpi_dmax_reqbnk1_s        cn63xxp1;
+};
+typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t;
+
+/**
+ * cvmx_dpi_dma_control
+ *
+ * DPI_DMA_CONTROL = DMA Control Register
+ *
+ * Controls operation of the DMA IN/OUT.
+ */
+union cvmx_dpi_dma_control
+{
+	uint64_t u64;
+	struct cvmx_dpi_dma_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t pkt_en1                      : 1;  /**< Enables the 2nd packet interface.
+                                                         When the packet interface is enabled, engine 4
+                                                         is used for packets and is not available for DMA.
+                                                         The packet interfaces must be enabled in order.
+                                                         When PKT_EN1=1, then PKT_EN=1.
+                                                         When PKT_EN1=1, then DMA_ENB<4>=0. */
+	uint64_t ffp_dis                      : 1;  /**< Force forward progress disable
+                                                         The DMA engines will compete for shared resources.
+                                                         If the HW detects that particular engines are not
+                                                         able to make requests to an interface, the HW
+                                                         will periodically trade-off throughput for
+                                                         fairness. */
+	uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
+
+                                                         When COMMIT_MODE=0, DPI considers an instruction
+                                                         complete when the HW internally generates the
+                                                         final write for the current instruction.
+
+                                                         When COMMIT_MODE=1, DPI additionally waits for
+                                                         the final write to reach the interface coherency
+                                                         point to declare the instructions complete.
+
+                                                         Please note: when COMMIT_MODE == 0, DPI may not
+                                                         follow the HRM ordering rules.
+
+                                                         DPI hardware performance may be better with
+                                                         COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
+                                                         to the relaxed ordering rules.
+
+                                                         If the HRM ordering rules are required, set
+                                                         COMMIT_MODE == 1. */
+	uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
+                                                         Engine 5 will be serviced more frequently to
+                                                         deliver more bandwidth to packet interface.
+                                                         When PKT_EN=0, then PKT_HP=0. */
+	uint64_t pkt_en                       : 1;  /**< Enables the packet interface.
+                                                         When the packet interface is enabled, engine 5
+                                                         is used for packets and is not available for DMA.
+                                                         When PKT_EN=1, then DMA_ENB<5>=0.
+                                                         When PKT_EN=0, then PKT_HP=0. */
+	uint64_t reserved_54_55               : 2;
+	uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
+                                                         DMA engine. After being enabled an engine should
+                                                         not be disabled while processing instructions.
+                                                         When PKT_EN=1, then DMA_ENB<5>=0. */
+	uint64_t reserved_34_47               : 14;
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
+                                                         freed this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma
+                                                         transfer will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         0=DPTR format 1 is used
+                                                           use register values for address and pointer
+                                                           values for ES, NS, RO
+                                                         1=DPTR format 0 is used
+                                                           use pointer values for address and register
+                                                           values for ES, NS, RO */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t reserved_34_47               : 14;
+	uint64_t dma_enb                      : 6;
+	uint64_t reserved_54_55               : 2;
+	uint64_t pkt_en                       : 1;
+	uint64_t pkt_hp                       : 1;
+	uint64_t commit_mode                  : 1;
+	uint64_t ffp_dis                      : 1;
+	uint64_t pkt_en1                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_dpi_dma_control_s         cn63xx;
+	struct cvmx_dpi_dma_control_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
+
+                                                         When COMMIT_MODE=0, DPI considers an instruction
+                                                         complete when the HW internally generates the
+                                                         final write for the current instruction.
+
+                                                         When COMMIT_MODE=1, DPI additionally waits for
+                                                         the final write to reach the interface coherency
+                                                         point to declare the instructions complete.
+
+                                                         Please note: when COMMIT_MODE == 0, DPI may not
+                                                         follow the HRM ordering rules.
+
+                                                         DPI hardware performance may be better with
+                                                         COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
+                                                         to the relaxed ordering rules.
+
+                                                         If the HRM ordering rules are required, set
+                                                         COMMIT_MODE == 1. */
+	uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
+                                                         Engine 5 will be serviced more frequently to
+                                                         deliver more bandwidth to packet interface.
+                                                         When PKT_EN=0, then PKT_HP=0. */
+	uint64_t pkt_en                       : 1;  /**< Enables the packet interface.
+                                                         When the packet interface is enabled, engine 5
+                                                         is used for packets and is not available for DMA.
+                                                         When PKT_EN=1, then DMA_ENB<5>=0.
+                                                         When PKT_EN=0, then PKT_HP=0. */
+	uint64_t reserved_54_55               : 2;
+	uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
+                                                         DMA engine. After being enabled an engine should
+                                                         not be disabled while processing instructions.
+                                                         When PKT_EN=1, then DMA_ENB<5>=0. */
+	uint64_t reserved_34_47               : 14;
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
+                                                         freed this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma
+                                                         transfer will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         0=DPTR format 1 is used
+                                                           use register values for address and pointer
+                                                           values for ES, NS, RO
+                                                         1=DPTR format 0 is used
+                                                           use pointer values for address and register
+                                                           values for ES, NS, RO */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t reserved_34_47               : 14;
+	uint64_t dma_enb                      : 6;
+	uint64_t reserved_54_55               : 2;
+	uint64_t pkt_en                       : 1;
+	uint64_t pkt_hp                       : 1;
+	uint64_t commit_mode                  : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t;
+
+/**
+ * cvmx_dpi_dma_eng#_en
+ */
+union cvmx_dpi_dma_engx_en
+{
+	uint64_t u64;
+	struct cvmx_dpi_dma_engx_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t qen                          : 8;  /**< Controls which logical instruction queues can be
+                                                         serviced by the DMA engine. Setting QEN==0
+                                                         effectively disables the engine.
+                                                         When DPI_DMA_CONTROL[PKT_EN] = 1, then
+                                                         DPI_DMA_ENG5_EN[QEN] must be zero. */
+#else
+	uint64_t qen                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_dma_engx_en_s         cn63xx;
+	struct cvmx_dpi_dma_engx_en_s         cn63xxp1;
+};
+typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t;
+
+/**
+ * cvmx_dpi_eng#_buf
+ *
+ * Notes:
+ * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB.
+ *
+ */
+union cvmx_dpi_engx_buf
+{
+	uint64_t u64;
+	struct cvmx_dpi_engx_buf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t base                         : 4;  /**< The base address in 512B blocks of the engine fifo */
+	uint64_t blks                         : 4;  /**< The size in 512B blocks of the engine fifo
+                                                         Legal values are 0-8.
+                                                         0 = Engine is disabled
+                                                         1 = 0.5KB buffer
+                                                         2 = 1.0KB buffer
+                                                         3 = 1.5KB buffer
+                                                         4 = 2.0KB buffer
+                                                         5 = 2.5KB buffer
+                                                         6 = 3.0KB buffer
+                                                         7 = 3.5KB buffer
+                                                         8 = 4.0KB buffer */
+#else
+	uint64_t blks                         : 4;
+	uint64_t base                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_engx_buf_s            cn63xx;
+	struct cvmx_dpi_engx_buf_s            cn63xxp1;
+};
+typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t;
+
+/**
+ * cvmx_dpi_info_reg
+ */
+union cvmx_dpi_info_reg
+{
+	uint64_t u64;
+	struct cvmx_dpi_info_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ffp                          : 4;  /**< Force Forward Progress Indicator */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ncb                          : 1;  /**< NCB Register Access
+                                                         This interrupt will fire in normal operation
+                                                         when SW reads a DPI register through the NCB
+                                                         interface. */
+	uint64_t rsl                          : 1;  /**< RSL Register Access
+                                                         This interrupt will fire in normal operation
+                                                         when SW reads a DPI register through the RSL
+                                                         interface. */
+#else
+	uint64_t rsl                          : 1;
+	uint64_t ncb                          : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ffp                          : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_info_reg_s            cn63xx;
+	struct cvmx_dpi_info_reg_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t ncb                          : 1;  /**< NCB Register Access
+                                                         This interrupt will fire in normal operation
+                                                         when SW reads a DPI register through the NCB
+                                                         interface. */
+	uint64_t rsl                          : 1;  /**< RSL Register Access
+                                                         This interrupt will fire in normal operation
+                                                         when SW reads a DPI register through the RSL
+                                                         interface. */
+#else
+	uint64_t rsl                          : 1;
+	uint64_t ncb                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t;
+
+/**
+ * cvmx_dpi_int_en
+ */
+union cvmx_dpi_int_en
+{
+	uint64_t u64;
+	struct cvmx_dpi_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t reserved_23_23               : 1;
+	uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill */
+	uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer */
+	uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction */
+	uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow */
+	uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow */
+	uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length */
+	uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer */
+	uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow */
+	uint64_t nderr                        : 1;  /**< NCB Decode Error */
+#else
+	uint64_t nderr                        : 1;
+	uint64_t nfovr                        : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dmadbo                       : 8;
+	uint64_t req_badadr                   : 1;
+	uint64_t req_badlen                   : 1;
+	uint64_t req_ovrflw                   : 1;
+	uint64_t req_undflw                   : 1;
+	uint64_t req_anull                    : 1;
+	uint64_t req_inull                    : 1;
+	uint64_t req_badfil                   : 1;
+	uint64_t reserved_23_23               : 1;
+	uint64_t sprt0_rst                    : 1;
+	uint64_t sprt1_rst                    : 1;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_dpi_int_en_s              cn63xx;
+	struct cvmx_dpi_int_en_s              cn63xxp1;
+};
+typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t;
+
+/**
+ * cvmx_dpi_int_reg
+ */
+union cvmx_dpi_int_reg
+{
+	uint64_t u64;
+	struct cvmx_dpi_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
+                                                          destination port was in reset.
+                                                         this bit is set. */
+	uint64_t reserved_23_23               : 1;
+	uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill
+                                                         Instruction fill when none outstanding. */
+	uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer
+                                                         Next pointer was NULL. */
+	uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction
+                                                         Fetched instruction word was 0. */
+	uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow
+                                                         DPI tracks outstanding instructions fetches.
+                                                         Interrupt will fire when FIFO underflows. */
+	uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow
+                                                         DPI tracks outstanding instructions fetches.
+                                                         Interrupt will fire when FIFO overflows. */
+	uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length
+                                                         Interrupt will fire if DPI forms an instruction
+                                                         fetch with length of zero. */
+	uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer
+                                                         Interrupt will fire if DPI forms an instruction
+                                                         fetch to the NULL pointer. */
+	uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow.
+                                                         DPI has a 32-bit counter for each request's queue
+                                                         outstanding doorbell counts. Interrupt will fire
+                                                         if the count overflows. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow
+                                                         DPI can store upto 16 CSR request.  The FIFO will
+                                                         overflow if that number is exceeded. */
+	uint64_t nderr                        : 1;  /**< NCB Decode Error
+                                                         DPI received a NCB transaction on the outbound
+                                                         bus to the DPI deviceID, but the command was not
+                                                         recognized. */
+#else
+	uint64_t nderr                        : 1;
+	uint64_t nfovr                        : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dmadbo                       : 8;
+	uint64_t req_badadr                   : 1;
+	uint64_t req_badlen                   : 1;
+	uint64_t req_ovrflw                   : 1;
+	uint64_t req_undflw                   : 1;
+	uint64_t req_anull                    : 1;
+	uint64_t req_inull                    : 1;
+	uint64_t req_badfil                   : 1;
+	uint64_t reserved_23_23               : 1;
+	uint64_t sprt0_rst                    : 1;
+	uint64_t sprt1_rst                    : 1;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_dpi_int_reg_s             cn63xx;
+	struct cvmx_dpi_int_reg_s             cn63xxp1;
+};
+typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t;
+
+/**
+ * cvmx_dpi_pint_info
+ *
+ * DPI_PINT_INFO = DPI Packet Interrupt Info
+ *
+ * DPI Packet Interrupt Info.
+ */
+union cvmx_dpi_pint_info
+{
+	uint64_t u64;
+	struct cvmx_dpi_pint_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t iinfo                        : 6;  /**< Packet Instruction Doorbell count overflow info */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t sinfo                        : 6;  /**< Packet Scatterlist Doorbell count overflow info */
+#else
+	uint64_t sinfo                        : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t iinfo                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_dpi_pint_info_s           cn63xx;
+	struct cvmx_dpi_pint_info_s           cn63xxp1;
+};
+typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t;
+
+/**
+ * cvmx_dpi_pkt_err_rsp
+ */
+union cvmx_dpi_pkt_err_rsp
+{
+	uint64_t u64;
+	struct cvmx_dpi_pkt_err_rsp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t pkterr                       : 1;  /**< Indicates that an ErrorResponse was received from
+                                                         the I/O subsystem. */
+#else
+	uint64_t pkterr                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_dpi_pkt_err_rsp_s         cn63xx;
+	struct cvmx_dpi_pkt_err_rsp_s         cn63xxp1;
+};
+typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t;
+
+/**
+ * cvmx_dpi_req_err_rsp
+ */
+union cvmx_dpi_req_err_rsp
+{
+	uint64_t u64;
+	struct cvmx_dpi_req_err_rsp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t qerr                         : 8;  /**< Indicates which instruction queue received an
+                                                         ErrorResponse from the I/O subsystem.
+                                                         SW must clear the bit before the the cooresponding
+                                                         instruction queue will continue processing
+                                                         instructions if DPI_REQ_ERR_RSP_EN[EN] is set. */
+#else
+	uint64_t qerr                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_req_err_rsp_s         cn63xx;
+	struct cvmx_dpi_req_err_rsp_s         cn63xxp1;
+};
+typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t;
+
+/**
+ * cvmx_dpi_req_err_rsp_en
+ */
+union cvmx_dpi_req_err_rsp_en
+{
+	uint64_t u64;
+	struct cvmx_dpi_req_err_rsp_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
+                                                         dispatching instructions when an  ErrorResponse
+                                                         is received from the I/O subsystem. */
+#else
+	uint64_t en                           : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_req_err_rsp_en_s      cn63xx;
+	struct cvmx_dpi_req_err_rsp_en_s      cn63xxp1;
+};
+typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t;
+
+/**
+ * cvmx_dpi_req_err_rst
+ */
+union cvmx_dpi_req_err_rst
+{
+	uint64_t u64;
+	struct cvmx_dpi_req_err_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t qerr                         : 8;  /**< Indicates which instruction queue dropped an
+                                                         instruction because the source or destination
+                                                         was in reset.
+                                                         SW must clear the bit before the the cooresponding
+                                                         instruction queue will continue processing
+                                                         instructions if DPI_REQ_ERR_RST_EN[EN] is set. */
+#else
+	uint64_t qerr                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_req_err_rst_s         cn63xx;
+	struct cvmx_dpi_req_err_rst_s         cn63xxp1;
+};
+typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t;
+
+/**
+ * cvmx_dpi_req_err_rst_en
+ */
+union cvmx_dpi_req_err_rst_en
+{
+	uint64_t u64;
+	struct cvmx_dpi_req_err_rst_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
+                                                         dispatching instructions when an instruction
+                                                         is dropped because the source or destination port
+                                                         is in reset. */
+#else
+	uint64_t en                           : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_req_err_rst_en_s      cn63xx;
+	struct cvmx_dpi_req_err_rst_en_s      cn63xxp1;
+};
+typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t;
+
+/**
+ * cvmx_dpi_req_gbl_en
+ */
+union cvmx_dpi_req_gbl_en
+{
+	uint64_t u64;
+	struct cvmx_dpi_req_gbl_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t qen                          : 8;  /**< Indicates which instruction queues are enabled and
+                                                         can dispatch instructions to a requesting engine. */
+#else
+	uint64_t qen                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_dpi_req_gbl_en_s          cn63xx;
+	struct cvmx_dpi_req_gbl_en_s          cn63xxp1;
+};
+typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t;
+
+/**
+ * cvmx_dpi_sli_prt#_cfg
+ *
+ * DPI_SLI_PRTx_CFG = DPI SLI Port Configuration
+ *
+ * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use
+ */
+union cvmx_dpi_sli_prtx_cfg
+{
+	uint64_t u64;
+	struct cvmx_dpi_sli_prtx_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t halt                         : 1;  /**< When set, HALT indicates that the MAC has detected
+                                                         a reset condition. No further instructions that
+                                                         reference the MAC from any instruction Q will be
+                                                         issued until the MAC comes out of reset and HALT
+                                                         is cleared in SLI_CTL_PORTx[DIS_PORT]. */
+	uint64_t reserved_21_23               : 3;
+	uint64_t qlm_cfg                      : 1;  /**< Read only copy of the QLM CFG pin
+                                                         0= MAC is PCIe
+                                                         1= MAC is SRIO */
+	uint64_t reserved_17_19               : 3;
+	uint64_t rd_mode                      : 1;  /**< Read Mode
+                                                         0=Exact Read Mode
+                                                           If the port is a PCIe port, the HW reads on a
+                                                           4B granularity.  In this mode, the HW may break
+                                                           a given read into 3 operations to satisify
+                                                           PCIe rules.
+                                                           If the port is a SRIO port, the HW follows the
+                                                           SRIO read rules from the SRIO specification and
+                                                            only issues 32*n, 16, and 8 byte  operations
+                                                            on the SRIO bus.
+                                                         1=Block Mode
+                                                           The HW will read more data than requested in
+                                                           order to minimize the number of operations
+                                                           necessary to complete the operation.
+                                                           The memory region must be memory like. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
+                                                         Limits the number of oustanding load requests on
+                                                         the port by restricting the number of tags
+                                                         used by the SLI to track load responses.  This
+                                                         value can range from 1 to 32. Setting a value of
+                                                         0 will halt all read traffic to the port.  There
+                                                         are no restrictions on when this value
+                                                         can be changed. */
+	uint64_t mps_lim                      : 1;  /**< MAC memory space write requests cannot cross the
+                                                         (naturally-aligned) MPS boundary.
+                                                         When clear, DPI is allowed to issue a MAC memory
+                                                         space read that crosses the naturally-aligned
+                                                         boundary of size defined by MPS. (DPI will still
+                                                         only cross the boundary when it would eliminate a
+                                                         write by doing so.)
+                                                         When set, DPI will never issue a MAC memory space
+                                                         write that crosses the naturally-aligned boundary
+                                                         of size defined by MPS. */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t mps                          : 1;  /**< Max Payload Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                         For PCIe MACs, this MPS size must not exceed
+                                                               the size selected by PCIE*_CFG030[MPS].
+                                                         For sRIO MACs, all MPS values are allowed. */
+	uint64_t mrrs_lim                     : 1;  /**< MAC memory space read requests cannot cross the
+                                                         (naturally-aligned) MRRS boundary.
+                                                         When clear, DPI is allowed to issue a MAC memory
+                                                         space read that crosses the naturally-aligned
+                                                         boundary of size defined by MRRS. (DPI will still
+                                                         only cross the boundary when it would eliminate a
+                                                         read by doing so.)
+                                                         When set, DPI will never issue a MAC memory space
+                                                         read that crosses the naturally-aligned boundary
+                                                         of size defined by MRRS. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mrrs                         : 2;  /**< Max Read Request Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                                 2 = 512B
+                                                                 3 = 1024B
+                                                         For PCIe MACs, this MRRS size must not exceed
+                                                               the size selected by PCIE*_CFG030[MRRS].
+                                                         For sRIO MACs, this MRRS size must be <= 256B. */
+#else
+	uint64_t mrrs                         : 2;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t mrrs_lim                     : 1;
+	uint64_t mps                          : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t mps_lim                      : 1;
+	uint64_t molr                         : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t rd_mode                      : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t qlm_cfg                      : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t halt                         : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_dpi_sli_prtx_cfg_s        cn63xx;
+	struct cvmx_dpi_sli_prtx_cfg_s        cn63xxp1;
+};
+typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t;
+
+/**
+ * cvmx_dpi_sli_prt#_err
+ *
+ * DPI_SLI_PRTx_ERR = DPI SLI Port Error Info
+ *
+ * Logs the Address and Request Queue associated with the reported SLI error response
+ */
+union cvmx_dpi_sli_prtx_err
+{
+	uint64_t u64;
+	struct cvmx_dpi_sli_prtx_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 61; /**< Address of the failed load request. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t addr                         : 61;
+#endif
+	} s;
+	struct cvmx_dpi_sli_prtx_err_s        cn63xx;
+	struct cvmx_dpi_sli_prtx_err_s        cn63xxp1;
+};
+typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t;
+
+/**
+ * cvmx_dpi_sli_prt#_err_info
+ *
+ * DPI_SLI_PRTx_ERR_INFO = DPI SLI Port Error Info
+ *
+ * Logs the Address and Request Queue associated with the reported SLI error response
+ */
+union cvmx_dpi_sli_prtx_err_info
+{
+	uint64_t u64;
+	struct cvmx_dpi_sli_prtx_err_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t lock                         : 1;  /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have
+                                                         captured and locked contents. */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t type                         : 1;  /**< Type of transaction that caused the ErrorResponse.
+                                                         0=DMA Instruction
+                                                         1=PKT Instruction */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t reqq                         : 3;  /**< Request queue that made the failed load request. */
+#else
+	uint64_t reqq                         : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t type                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t lock                         : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn63xx;
+	struct cvmx_dpi_sli_prtx_err_info_s   cn63xxp1;
+};
+typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ebt3000.c b/sys/contrib/octeon-sdk/cvmx-ebt3000.c
index c3f2e97..5763fda 100644
--- a/sys/contrib/octeon-sdk/cvmx-ebt3000.c
+++ b/sys/contrib/octeon-sdk/cvmx-ebt3000.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-ebt3000.h b/sys/contrib/octeon-sdk/cvmx-ebt3000.h
index 7e51959..60be6ce 100644
--- a/sys/contrib/octeon-sdk/cvmx-ebt3000.h
+++ b/sys/contrib/octeon-sdk/cvmx-ebt3000.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 #ifndef __CVMX_EBT3000_H__
 #define __CVMX_EBT3000_H__
 
@@ -49,7 +51,7 @@
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.c b/sys/contrib/octeon-sdk/cvmx-error-custom.c
new file mode 100644
index 0000000..3aeaa0d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-custom.c
@@ -0,0 +1,624 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Prototypes for custom error handler function not handled by the default
+ * message display error function.
+ *
+ * <hr>$Revision: 44252 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-l2c.h>
+#include <asm/octeon/cvmx-pcie.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-dfa-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-lmcx-defs.h>
+#include <asm/octeon/cvmx-pemx-defs.h>
+#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#include "cvmx-helper.h"
+#include "cvmx-l2c.h"
+#include "cvmx-pcie.h"
+#include "cvmx-interrupt.h"
+#endif
+
+/**
+ * @INTERNAL
+ * XAUI interfaces need to be reset whenever a local or remote fault
+ * is detected. Calling autoconf takes the link through a reset.
+ *
+ * @param info
+ *
+ * @return
+ */
+static int __cvmx_error_handle_gmxx_rxx_int_reg(const struct cvmx_error_info *info)
+{
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+    int ipd_port = info->group_index;
+    cvmx_helper_link_autoconf(ipd_port);
+#endif
+    cvmx_write_csr(info->status_addr, info->status_mask);
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * When NPEI_INT_SUM[C0_LDWN] is set, the PCIe block requires a shutdown and
+ * initialization to bring the link back up. This handler does this for port 0.
+ * Note that config space is not enumerated again, so the devices will still be
+ * unusable.
+ *
+ * @param info
+ *
+ * @return
+ */
+static int __cvmx_error_handle_npei_int_sum_c0_ldwn(const struct cvmx_error_info *info)
+{
+    cvmx_ciu_soft_prst_t ciu_soft_prst;
+    PRINT_ERROR("NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n");
+    ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+    if (!ciu_soft_prst.s.soft_prst)
+    {
+        /* Attempt to automatically bring the link back up */
+        cvmx_pcie_rc_shutdown(0);
+        cvmx_pcie_rc_initialize(0);
+    }
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * When NPEI_INT_SUM[C1_LDWN] is set, the PCIe block requires a shutdown and
+ * initialization to bring the link back up. This handler does this for port 1.
+ * Note that config space is not enumerated again, so the devices will still be
+ * unusable.
+ *
+ * @param info
+ *
+ * @return
+ */
+static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info *info)
+{
+    cvmx_ciu_soft_prst_t ciu_soft_prst;
+    PRINT_ERROR("NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n");
+    ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+    if (!ciu_soft_prst.s.soft_prst)
+    {
+        /* Attempt to automatically bring the link back up */
+        cvmx_pcie_rc_shutdown(1);
+        cvmx_pcie_rc_initialize(1);
+    }
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * Some errors require more complicated error handing functions than the
+ * automatically generated functions in cvmx-error-init-*.c. This function
+ * replaces these handers with hand coded functions for these special cases.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int __cvmx_error_custom_initialize(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<21 /* rem_fault */,
+                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<20 /* loc_fault */,
+                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<21 /* rem_fault */,
+                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<20 /* loc_fault */,
+                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+    }
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    {
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_PEXP_NPEI_INT_SUM, 1ull<<59 /* c0_ldwn */,
+                            __cvmx_error_handle_npei_int_sum_c0_ldwn, 0, NULL, NULL);
+        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_PEXP_NPEI_INT_SUM, 1ull<<60 /* c1_ldwn */,
+                            __cvmx_error_handle_npei_int_sum_c1_ldwn, 0, NULL, NULL);
+    }
+
+    /* CN63XX pass 1.x has a bug where the PCIe config CRS counter does not
+        stop. Disable reporting errors from CRS */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(0),
+            1ull<<12);
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(0),
+            1ull<<13);
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
+            1ull<<12);
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
+            1ull<<13);
+    }
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_cp2dbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_cp2perr(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_cp2sbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_dblovf(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[DBLOVF]: Doorbell Overflow detected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_dtedbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_dteperr(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[DTEPERR]: DTE Parity Error Detected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_dfa_err_dtesbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
+    PRINT_ERROR("DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2D_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2d_err_ded_err(const struct cvmx_error_info *info)
+{
+    cvmx_l2d_err_t derr;
+    cvmx_l2d_fadr_t fadr;
+    uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
+    uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
+    derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
+    fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
+
+    PRINT_ERROR("L2D_ERR[DED_ERR] ECC double: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
+        (unsigned long long)fadr.u64, (unsigned long long)syn0, (unsigned long long)syn1);
+    /* Flush the line that had the error */
+    cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
+    cvmx_write_csr(CVMX_L2D_ERR, derr.u64);
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2D_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2d_err_sec_err(const struct cvmx_error_info *info)
+{
+    cvmx_l2d_err_t derr;
+    cvmx_l2d_fadr_t fadr;
+    uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
+    uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
+    derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
+    fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
+
+    PRINT_ERROR("L2D_ERR[SEC_ERR] ECC single: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
+        (unsigned long long)fadr.u64, (unsigned long long)syn0, (unsigned long long)syn1);
+    /* Flush the line that had the error */
+    cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
+    cvmx_write_csr(CVMX_L2D_ERR, derr.u64);
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2t_err_ded_err(const struct cvmx_error_info *info)
+{
+    cvmx_l2t_err_t terr;
+    terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
+    PRINT_ERROR("L2T_ERR[DED_ERR]: double bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
+                     terr.s.fadr, terr.s.fset, terr.s.fsyn);
+    if (!terr.s.fsyn)
+    {
+        /* Syndrome is zero, which means error was in non-hit line,
+            so flush all associations */
+        int i;
+        int l2_assoc = cvmx_l2c_get_num_assoc();
+
+        for (i = 0; i < l2_assoc; i++)
+            cvmx_l2c_flush_line(i, terr.s.fadr);
+    }
+    else
+        cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2t_err_lckerr2(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_L2T_ERR, cvmx_read_csr(CVMX_L2T_ERR));
+    PRINT_ERROR("L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2t_err_lckerr(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_L2T_ERR, cvmx_read_csr(CVMX_L2T_ERR));
+    PRINT_ERROR("L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
+ * special handling instead of the normal __cvmx_error_display() function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_l2t_err_sec_err(const struct cvmx_error_info *info)
+{
+    cvmx_l2t_err_t terr;
+    terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
+    PRINT_ERROR("L2T_ERR[SEC_ERR]: single bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
+                 terr.s.fadr, terr.s.fset, terr.s.fsyn);
+    if (!terr.s.fsyn)
+    {
+        /* Syndrome is zero, which means error was in non-hit line,
+            so flush all associations */
+        int i;
+        int l2_assoc = cvmx_l2c_get_num_assoc();
+
+        for (i = 0; i < l2_assoc; i++)
+            cvmx_l2c_flush_line(i, terr.s.fadr);
+    }
+    else
+        cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
+    return 1;
+}
+
+
+/**
+ * @INTERNAL
+ * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+static int __cvmx_error_handle_lmcx_mem_cfg0(const struct cvmx_error_info *info)
+{
+    int ddr_controller = info->group_index;
+    cvmx_lmcx_mem_cfg0_t mem_cfg0;
+    cvmx_lmcx_fadr_t fadr;
+    int sec_err;
+    int ded_err;
+
+    mem_cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
+    fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(ddr_controller));
+    cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller),mem_cfg0.u64);
+
+    sec_err = cvmx_dpop(mem_cfg0.s.sec_err);
+    ded_err = cvmx_dpop(mem_cfg0.s.ded_err);
+
+    if (ded_err || sec_err)
+    {
+        PRINT_ERROR("DDR%d ECC: %d Single bit corrections, %d Double bit errors\n"
+                     "DDR%d ECC:\tFailing dimm:   %u\n"
+                     "DDR%d ECC:\tFailing rank:   %u\n"
+                     "DDR%d ECC:\tFailing bank:   %u\n"
+                     "DDR%d ECC:\tFailing row:    0x%x\n"
+                     "DDR%d ECC:\tFailing column: 0x%x\n",
+                     ddr_controller, sec_err, ded_err,
+                     ddr_controller, fadr.cn38xx.fdimm,
+                     ddr_controller, fadr.cn38xx.fbunk,
+                     ddr_controller, fadr.cn38xx.fbank,
+                     ddr_controller, fadr.cn38xx.frow,
+                     ddr_controller, fadr.cn38xx.fcol);
+    }
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_lmcx_mem_cfg0_ded_err(const struct cvmx_error_info *info)
+{
+    return __cvmx_error_handle_lmcx_mem_cfg0(info);
+}
+
+/**
+ * @INTERNAL
+ * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_lmcx_mem_cfg0_sec_err(const struct cvmx_error_info *info)
+{
+    return __cvmx_error_handle_lmcx_mem_cfg0(info);
+}
+
+/**
+ * @INTERNAL
+ * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
+    PRINT_ERROR("POW_ECC_ERR[DBE]: POW double bit error\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info)
+{
+    cvmx_pow_ecc_err_t err;
+    err.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
+    cvmx_write_csr(CVMX_POW_ECC_ERR, err.u64);
+    if (err.s.iop & (1 << 0))
+        PRINT_ERROR("POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state\n");
+    if (err.s.iop & (1 << 1))
+        PRINT_ERROR("POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state\n");
+    if (err.s.iop & (1 << 2))
+        PRINT_ERROR("POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC\n");
+    if (err.s.iop & (1 << 3))
+        PRINT_ERROR("POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL\n");
+    if (err.s.iop & (1 << 4))
+        PRINT_ERROR("POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL\n");
+    if (err.s.iop & (1 << 5))
+        PRINT_ERROR("POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending\n");
+    if (err.s.iop & (1 << 6))
+        PRINT_ERROR("POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending\n");
+    if (err.s.iop & (1 << 7))
+        PRINT_ERROR("POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n");
+    if (err.s.iop & (1 << 8))
+        PRINT_ERROR("POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending\n");
+    if (err.s.iop & (1 << 9))
+        PRINT_ERROR("POW_ECC_ERR[IOP9]: Received illegal opcode\n");
+    if (err.s.iop & (1 << 10))
+        PRINT_ERROR("POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL\n");
+    if (err.s.iop & (1 << 11))
+        PRINT_ERROR("POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending\n");
+    if (err.s.iop & (1 << 12))
+        PRINT_ERROR("POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
+    PRINT_ERROR("POW_ECC_ERR[RPE]: Remote pointer error\n");
+    return 1;
+}
+
+/**
+ * @INTERNAL
+ * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
+ * requires special handling instead of the normal __cvmx_error_display()
+ * function.
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info)
+{
+    cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
+    PRINT_ERROR("POW_ECC_ERR[SBE]: POW single bit error\n");
+    return 1;
+}
+
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.h b/sys/contrib/octeon-sdk/cvmx-error-custom.h
new file mode 100644
index 0000000..e6a13f0
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-custom.h
@@ -0,0 +1,91 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Prototypes for custom error handler function not handled by the default
+ * message display error function.
+ *
+ * <hr>$Revision: 44252 $<hr>
+ */
+#ifndef __CVMX_ERROR_CUSTOM_H__
+#define __CVMX_ERROR_CUSTOM_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * @INTERNAL
+ * Some errors require more complicated error handing functions
+ * than the automatically generated functions in cvmx-error-init-*.c.
+ * This function replaces these handers with hand coded functions
+ * for these special cases.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int __cvmx_error_custom_initialize(void);
+
+int __cvmx_error_handle_dfa_err_cp2dbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_cp2perr(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_cp2sbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_dblovf(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_dtedbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_dteperr(const struct cvmx_error_info *info);
+int __cvmx_error_handle_dfa_err_dtesbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2d_err_ded_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2d_err_sec_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2t_err_ded_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2t_err_lckerr2(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2t_err_lckerr(const struct cvmx_error_info *info);
+int __cvmx_error_handle_l2t_err_sec_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_lmcx_mem_cfg0_ded_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_lmcx_mem_cfg0_sec_err(const struct cvmx_error_info *info);
+int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info);
+int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
new file mode 100644
index 0000000..79371dd
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
@@ -0,0 +1,3504 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn30xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN30XX</h2>
+ * @dot
+ * digraph cn30xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
+ *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
+ *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
+ *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
+ *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<i0_rtout>i0_rtout|<i0_overf>i0_overf|<p0_rtout>p0_rtout|<p0_perr>p0_perr|<g0_rtout>g0_rtout|<p0_pperr>p0_pperr|<p0_ptout>p0_ptout|<i0_pperr>i0_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn30xx(void);
+
+int cvmx_error_initialize_cn30xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is\n"
+        "    completed successfully, however the address is NOT\n"
+        "    locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
+        "    (not used in O2P)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0x7ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
+        "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
+        "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
+        "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
+        "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
+        "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
+        "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
+        "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
+        "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
+        "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
+        "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
+        "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
+        "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
+        "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
+        "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<26 /* n2u_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<26 /* n2u_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<27 /* n2u_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<27 /* n2u_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<28 /* u2n_d_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<28 /* u2n_d_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<29 /* u2n_d_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<29 /* u2n_d_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<30 /* u2n_c_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<30 /* u2n_c_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<31 /* u2n_c_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<31 /* u2n_c_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
new file mode 100644
index 0000000..7d3f531
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
@@ -0,0 +1,3835 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn31xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN31XX</h2>
+ * @dot
+ * digraph cn31xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
+ *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
+ *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
+ *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
+ *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<zip>zip|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<usb>usb"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
+ *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn31xx(void);
+
+int cvmx_error_initialize_cn31xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0x7ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
+        "    (not used in O2P)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<1 /* cp2sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a PP-generated QW Mode read\n"
+        "    transaction.\n"
+        "    If the CP2DBE=0, then the CP2SYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2SBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<2 /* cp2dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a PP-generated QW Mode read transaction.\n"
+        "    The CP2SYN contains the failing syndrome.\n"
+        "     NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2DBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<14 /* dtesbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtesbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTESBE]: DTE 25b Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a DTE-generated 32b SIMPLE Mode read\n"
+        "    transaction.\n"
+        "    If the DTEDBE=0, then the DTESYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    NOTE: DTE-generated 16b SIMPLE Mode Read\n"
+        "    transactions do not participate in ECC check/correct).\n"
+        "    If the DTESBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<15 /* dtedbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtedbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEDBE]: DTE 25b Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a DTE-generated 32b SIMPLE Mode read transaction.\n"
+        "    The DTESYN contains the failing syndrome.\n"
+        "    If the DTEDBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: DTE-generated 16b SIMPLE Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<26 /* dteperr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dteperr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 16b SIMPLE mode ONLY)\n"
+        "    When set, all DTE-generated 16b SIMPLE Mode read\n"
+        "    transactions which encounter a parity error (across\n"
+        "    the 17b of data) are reported.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<29 /* cp2perr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2perr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
+        "    When set, a parity error had been detected for a\n"
+        "    PP-generated LW Mode read transaction.\n"
+        "    If the CP2PINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<31 /* dblovf */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dblovf;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<26 /* n2u_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<26 /* n2u_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<27 /* n2u_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<27 /* n2u_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<28 /* u2n_d_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<28 /* u2n_d_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<29 /* u2n_d_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<29 /* u2n_d_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<30 /* u2n_c_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<30 /* u2n_c_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<31 /* u2n_c_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<31 /* u2n_c_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
new file mode 100644
index 0000000..41582de
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
@@ -0,0 +1,4866 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn38xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN38XX</h2>
+ * @dot
+ * digraph cn38xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
+ *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
+ *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
+ *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
+ *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn38xx(void);
+
+int cvmx_error_initialize_cn38xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* po2_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* po2_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* po3_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* po3_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* i2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* i2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* i3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* i3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* i2_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* i2_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* i3_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* i3_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<17 /* p2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* p2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<18 /* p3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* p3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* p2_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* p2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* p3_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* p3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* g2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* g2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* g3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* g3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* p2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* p2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* p3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* p3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* p2_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* p2_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* p3_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* p3_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* i2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* i2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* i3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* i3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0\n"
+        "    [22] corresponds to DQ[127:64], Phase0\n"
+        "    [23] corresponds to DQ[63:0], Phase1\n"
+        "    [24] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0\n"
+        "    [26] corresponds to DQ[127:64], Phase0\n"
+        "    [27] corresponds to DQ[63:0], Phase1\n"
+        "    [28] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<1 /* cp2sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a PP-generated QW Mode read\n"
+        "    transaction.\n"
+        "    If the CP2DBE=0, then the CP2SYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2SBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<2 /* cp2dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a PP-generated QW Mode read transaction.\n"
+        "    The CP2SYN contains the failing syndrome.\n"
+        "     NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2DBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<14 /* dtesbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtesbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
+        "    transaction.\n"
+        "    If the DTEDBE=0, then the DTESYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
+        "    transactions do not participate in ECC check/correct).\n"
+        "    If the DTESBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<15 /* dtedbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtedbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
+        "    The DTESYN contains the failing syndrome.\n"
+        "    If the DTEDBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<26 /* dteperr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dteperr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
+        "    When set, all DTE-generated 18b SIMPLE Mode read\n"
+        "    transactions which encounter a parity error (across\n"
+        "    the 17b of data) are reported.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<29 /* cp2perr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2perr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
+        "    When set, a parity error had been detected for a\n"
+        "    PP-generated LW Mode read transaction.\n"
+        "    If the CP2PINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<31 /* dblovf */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dblovf;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
new file mode 100644
index 0000000..7d7c10c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
@@ -0,0 +1,4423 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn38xxp2.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN38XXP2</h2>
+ * @dot
+ * digraph cn38xxp2
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
+ *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
+ *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
+ *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
+ *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn38xxp2(void);
+
+int cvmx_error_initialize_cn38xxp2(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* po2_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* po2_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* po3_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* po3_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* i2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* i2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* i3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* i3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* i2_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* i2_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* i3_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* i3_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<17 /* p2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* p2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<18 /* p3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* p3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* p2_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* p2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* p3_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* p3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* g2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* g2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* g3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* g3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* p2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* p2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* p3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* p3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* p2_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* p2_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* p3_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* p3_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* i2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* i2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* i3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* i3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0\n"
+        "    [22] corresponds to DQ[127:64], Phase0\n"
+        "    [23] corresponds to DQ[63:0], Phase1\n"
+        "    [24] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0\n"
+        "    [26] corresponds to DQ[127:64], Phase0\n"
+        "    [27] corresponds to DQ[63:0], Phase1\n"
+        "    [28] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<1 /* cp2sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a PP-generated QW Mode read\n"
+        "    transaction.\n"
+        "    If the CP2DBE=0, then the CP2SYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2SBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<2 /* cp2dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a PP-generated QW Mode read transaction.\n"
+        "    The CP2SYN contains the failing syndrome.\n"
+        "     NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2DBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<14 /* dtesbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtesbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
+        "    transaction.\n"
+        "    If the DTEDBE=0, then the DTESYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
+        "    transactions do not participate in ECC check/correct).\n"
+        "    If the DTESBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<15 /* dtedbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtedbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
+        "    The DTESYN contains the failing syndrome.\n"
+        "    If the DTEDBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<26 /* dteperr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dteperr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
+        "    When set, all DTE-generated 18b SIMPLE Mode read\n"
+        "    transactions which encounter a parity error (across\n"
+        "    the 17b of data) are reported.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<29 /* cp2perr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2perr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
+        "    When set, a parity error had been detected for a\n"
+        "    PP-generated LW Mode read transaction.\n"
+        "    If the CP2PINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<31 /* dblovf */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dblovf;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
new file mode 100644
index 0000000..ecd0ca1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
@@ -0,0 +1,3606 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn50xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN50XX</h2>
+ * @dot
+ * digraph cn50xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
+ *     cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
+ *     cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
+ *     cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
+ *     cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
+ *     cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn50xx(void);
+
+int cvmx_error_initialize_cn50xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(1);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(2) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(2);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(2);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCMX_INT_SUM(3) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<0 /* fsyncmissed */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<0 /* fsyncmissed */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<1 /* fsyncextra */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<1 /* fsyncextra */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<6 /* txempty */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<6 /* txempty */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCMX_INT_SUM(3);
+    info.status_mask        = 1ull<<7 /* rxovf */;
+    info.enable_addr        = CVMX_PCMX_INT_ENA(3);
+    info.enable_mask        = 1ull<<7 /* rxovf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<57 /* pcm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0x7ull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0x7ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0x7ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0x7ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
+        "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
+        "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
+        "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
+        "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
+        "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
+        "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
+        "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "    In 16b mode, ecc is calculated on 8 cycle worth of data\n"
+        "    [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
+        "                        DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
+        "                        DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
+        "    [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
+        "                        DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
+        "    [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
+        "                        DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [3:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
new file mode 100644
index 0000000..9743995
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
@@ -0,0 +1,6681 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn52xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN52XX</h2>
+ * @dot
+ * digraph cn52xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
+ *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
+ *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
+ *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn52xx(void);
+
+int cvmx_error_initialize_cn52xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<3 /* l2tsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<3 /* l2tsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<5 /* l2dsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<5 /* l2dsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<0 /* oob1 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<0 /* oob1en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<1 /* oob2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<1 /* oob2en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<2 /* oob3 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<2 /* oob3en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<4 /* l2tded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<4 /* l2tdeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<6 /* l2dded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<6 /* l2ddeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<7 /* lck */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<7 /* lckena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<8 /* lck2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<8 /* lck2ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* c0_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* c0_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<21 /* c0_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 0. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* c0_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<42 /* c0_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* c0_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<53 /* c0_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* c0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<41 /* c0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* c0_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<37 /* c0_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* c0_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<55 /* c0_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* c0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<36 /* c0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* c0_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<23 /* c0_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 0. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* crs0_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<22 /* crs0_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* crs0_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<20 /* crs0_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* c1_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* c1_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<28 /* c1_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 1. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* c1_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<52 /* c1_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* c1_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<54 /* c1_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* c1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<51 /* c1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* c1_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<47 /* c1_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* c1_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<56 /* c1_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* c1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<46 /* c1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* c1_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<30 /* c1_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 1. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* crs1_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<29 /* crs1_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* crs1_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<27 /* crs1_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* dma0dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* dma0dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dma1dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* dma1dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* dma2dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* dma2dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* dma3dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* dma3dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* dma4dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* dma4dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
new file mode 100644
index 0000000..a0f24b3
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
@@ -0,0 +1,6580 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn52xxp1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN52XXP1</h2>
+ * @dot
+ * digraph cn52xxp1
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
+ *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
+ *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
+ *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn52xxp1(void);
+
+int cvmx_error_initialize_cn52xxp1(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<3 /* l2tsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<3 /* l2tsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<5 /* l2dsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<5 /* l2dsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<0 /* oob1 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<0 /* oob1en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<1 /* oob2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<1 /* oob2en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<2 /* oob3 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<2 /* oob3en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<4 /* l2tded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<4 /* l2tdeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<6 /* l2dded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<6 /* l2ddeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<7 /* lck */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<7 /* lckena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<8 /* lck2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<8 /* lck2ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(1);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(1);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<15 /* usb1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* c0_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* c0_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<21 /* c0_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 0. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* c0_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<42 /* c0_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* c0_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<53 /* c0_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* c0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<41 /* c0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* c0_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<37 /* c0_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* c0_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<55 /* c0_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* c0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<36 /* c0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* c0_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<23 /* c0_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 0. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* crs0_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<22 /* crs0_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* crs0_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<20 /* crs0_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* c1_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* c1_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<28 /* c1_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 1. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* c1_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<52 /* c1_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* c1_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<54 /* c1_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* c1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<51 /* c1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* c1_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<47 /* c1_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* c1_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<56 /* c1_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* c1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<46 /* c1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* c1_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<30 /* c1_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 1. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* crs1_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<29 /* crs1_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* crs1_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<27 /* crs1_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* dma0dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* dma0dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell count overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dma1dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* dma1dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell count overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* dma2dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* dma2dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell count overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* dma3dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* dma3dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell count overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
new file mode 100644
index 0000000..75be2ce
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
@@ -0,0 +1,7627 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn56xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN56XX</h2>
+ * @dot
+ * digraph cn56xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
+ *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
+ *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
+ *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
+ *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
+ *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
+ *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn56xx(void);
+
+int cvmx_error_initialize_cn56xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<3 /* l2tsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<3 /* l2tsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<5 /* l2dsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<5 /* l2dsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<0 /* oob1 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<0 /* oob1en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<1 /* oob2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<1 /* oob2en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<2 /* oob3 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<2 /* oob3en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<4 /* l2tded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<4 /* l2tdeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<6 /* l2dded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<6 /* l2ddeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<7 /* lck */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<7 /* lckena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<8 /* lck2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<8 /* lck2ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* c0_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* c0_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<21 /* c0_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 0. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* c0_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<42 /* c0_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* c0_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<53 /* c0_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* c0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<41 /* c0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* c0_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<37 /* c0_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* c0_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<55 /* c0_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* c0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<36 /* c0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* c0_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<23 /* c0_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 0. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* crs0_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<22 /* crs0_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* crs0_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<20 /* crs0_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* c1_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* c1_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<28 /* c1_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 1. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* c1_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<52 /* c1_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* c1_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<54 /* c1_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* c1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<51 /* c1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* c1_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<47 /* c1_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* c1_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<56 /* c1_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* c1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<46 /* c1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* c1_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<30 /* c1_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 1. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* crs1_dr */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<29 /* crs1_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* crs1_er */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<27 /* crs1_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* dma0dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* dma0dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dma1dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* dma1dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* dma2dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* dma2dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* dma3dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* dma3dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* dma4dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* dma4dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<29 /* lmc1 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<29 /* lmc1 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
new file mode 100644
index 0000000..58c2671
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
@@ -0,0 +1,7178 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn56xxp1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN56XXP1</h2>
+ * @dot
+ * digraph cn56xxp1
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
+ *     cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
+ *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
+ *     cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
+ *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
+ *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
+ *     cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
+ *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
+ *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
+ *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn56xxp1(void);
+
+int cvmx_error_initialize_cn56xxp1(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<3 /* l2tsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<3 /* l2tsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<5 /* l2dsec */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<5 /* l2dsecen */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<0 /* oob1 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<0 /* oob1en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<1 /* oob2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<1 /* oob2en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<2 /* oob3 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<2 /* oob3en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<4 /* l2tded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<4 /* l2tdeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<6 /* l2dded */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<6 /* l2ddeden */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
+        "    NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<7 /* lck */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<7 /* lckena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_STAT;
+    info.status_mask        = 1ull<<8 /* lck2 */;
+    info.enable_addr        = CVMX_L2C_INT_EN;
+    info.enable_mask        = 1ull<<8 /* lck2ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n"
+        "    NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_NPEI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* c0_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* c0_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<21 /* c0_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 0. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<38 /* c0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<39 /* c0_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<40 /* c0_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* c0_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<42 /* c0_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* c0_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<53 /* c0_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* c0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<41 /* c0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* c0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<34 /* c0_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<35 /* c0_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* c0_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<37 /* c0_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* c0_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<55 /* c0_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* c0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<36 /* c0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* c0_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<23 /* c0_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 0. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* c1_ldwn */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* c1_se */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<28 /* c1_se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
+        "    Pcie Core 1. (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<48 /* c1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<49 /* c1_un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<50 /* c1_un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* c1_un_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<52 /* c1_un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* c1_un_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<54 /* c1_un_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* c1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<51 /* c1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<43 /* c1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<44 /* c1_up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<45 /* c1_up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* c1_up_bx */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<47 /* c1_up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* c1_up_wf */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<56 /* c1_up_wf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+        "    register. Core1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* c1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<46 /* c1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+        "    Core 1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* c1_wake */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<30 /* c1_wake */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
+        "    Pcie Core 1. (wake_n)\n"
+        "    Octeon will never generate this interrupt.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* dma0dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* dma0dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dma1dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* dma1dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* dma2dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* dma2dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* dma3dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* dma3dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* dma4dbo */;
+    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* dma4dbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
+        "    Bit[32] of the doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npei */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<57 /* c0_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PESCX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PESCX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PESCX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
+    info.parent.status_mask = 1ull<<58 /* c1_exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<29 /* lmc1 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(1);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<29 /* lmc1 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    In 32b mode, ecc is calculated on 4 cycle worth of data\n"
+        "    [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
+        "    [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
+        "    [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
+        "    [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
+        "      where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_USBNX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<0 /* pr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<0 /* pr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP  Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* pr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* pr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP  Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<2 /* nr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<2 /* nr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<3 /* nr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<3 /* nr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* lr_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* lr_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* lr_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* lr_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* pt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* pt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* pt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* pt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* nt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* nt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* nt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* nt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<10 /* lt_po_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<10 /* lt_po_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* lt_pu_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* lt_pu_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* dcred_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* dcred_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* dcred_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* dcred_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<14 /* l2c_s_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<14 /* l2c_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<15 /* l2c_a_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<15 /* l2c_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<16 /* lt_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<16 /* l2_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<17 /* lt_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<17 /* l2_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<18 /* rg_fi_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<18 /* rg_fi_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<19 /* rg_fi_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<19 /* rg_fi_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<20 /* rq_q2_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<20 /* rq_q2_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<21 /* rq_q2_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<21 /* rq_q2_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<22 /* rq_q3_f */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<22 /* rq_q3_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<23 /* rq_q3_e */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<23 /* rq_q3_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<24 /* uod_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<24 /* uod_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<25 /* uod_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<25 /* uod_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<32 /* ltl_f_pe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<33 /* ltl_f_pf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<34 /* nd4o_rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<35 /* nd4o_rpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<36 /* nd4o_dpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_USBNX_INT_SUM(0);
+    info.status_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.enable_addr        = CVMX_USBNX_INT_ENB(0);
+    info.enable_mask        = 1ull<<37 /* nd4o_dpf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
new file mode 100644
index 0000000..67db154
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
@@ -0,0 +1,4939 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn58xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN58XX</h2>
+ * @dot
+ * digraph cn58xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
+ *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
+ *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
+ *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
+ *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn58xx(void);
+
+int cvmx_error_initialize_cn58xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* po2_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* po2_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* po3_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* po3_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* i2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* i2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* i3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* i3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* i2_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* i2_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* i3_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* i3_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<17 /* p2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* p2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<18 /* p3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* p3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* p2_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* p2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* p3_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* p3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* g2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* g2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* g3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* g3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* p2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* p2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* p3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* p3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* p2_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* p2_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* p3_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* p3_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* i2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* i2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* i3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* i3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0\n"
+        "    [22] corresponds to DQ[127:64], Phase0\n"
+        "    [23] corresponds to DQ[63:0], Phase1\n"
+        "    [24] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0\n"
+        "    [26] corresponds to DQ[127:64], Phase0\n"
+        "    [27] corresponds to DQ[63:0], Phase1\n"
+        "    [28] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<1 /* cp2sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a PP-generated QW Mode read\n"
+        "    transaction.\n"
+        "    If the CP2DBE=0, then the CP2SYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2SBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<2 /* cp2dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a PP-generated QW Mode read transaction.\n"
+        "    The CP2SYN contains the failing syndrome.\n"
+        "     NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2DBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<14 /* dtesbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtesbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
+        "    transaction.\n"
+        "    If the DTEDBE=0, then the DTESYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
+        "    transactions do not participate in ECC check/correct).\n"
+        "    If the DTESBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<15 /* dtedbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtedbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
+        "    The DTESYN contains the failing syndrome.\n"
+        "    If the DTEDBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<26 /* dteperr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dteperr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
+        "    When set, all DTE-generated 18b SIMPLE Mode read\n"
+        "    transactions which encounter a parity error (across\n"
+        "    the 17b of data) are reported.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<29 /* cp2perr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2perr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
+        "    When set, a parity error had been detected for a\n"
+        "    PP-generated LW Mode read transaction.\n"
+        "    If the CP2PINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<31 /* dblovf */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dblovf;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
new file mode 100644
index 0000000..a754c11
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
@@ -0,0 +1,4922 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn58xxp1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN58XXP1</h2>
+ * @dot
+ * digraph cn58xxp1
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
+ *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
+ *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
+ *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
+ *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
+ *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
+ *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
+ *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
+ *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
+ *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
+ *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
+ *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
+ *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
+ *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
+ *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
+ *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
+ *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
+ *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
+ *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
+ *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
+ *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
+ *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
+ *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
+ *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
+ *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
+ *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
+ *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
+ *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
+ *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn58xxp1(void);
+
+int cvmx_error_initialize_cn58xxp1(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    /* CVMX_CIU_INT_SUM1 */
+    /* CVMX_NPI_RSL_INT_BLOCKS */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2D_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2D_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2D_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2d_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2T_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<3 /* sec_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<1 /* sec_intena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_sec_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for single bit errors(SBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains an SBE.\n"
+        "    SBEs are auto corrected in HW and generate an\n"
+        "    interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<4 /* ded_err */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<2 /* ded_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_ded_err;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
+        "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
+        "    given index) are checked for double bit errors(DBEs).\n"
+        "    This bit is set if ANY of the 8 sets contains a DBE.\n"
+        "    DBEs also generated an interrupt(if enabled).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<24 /* lckerr */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<25 /* lck_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
+        "    the INDEX (which is ignored by HW - but reported to SW).\n"
+        "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
+        "    successfully, however the address is NOT locked.\n"
+        "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
+        "    into account. For example, if diagnostic PPx has\n"
+        "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
+        "    been previously LOCKED, then an attempt to LOCK the\n"
+        "    last available SET0 would result in a LCKERR. (This\n"
+        "    is to ensure that at least 1 SET at each INDEX is\n"
+        "    not LOCKED for general use by other PPs).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2T_ERR;
+    info.status_mask        = 1ull<<26 /* lckerr2 */;
+    info.enable_addr        = CVMX_L2T_ERR;
+    info.enable_mask        = 1ull<<27 /* lck_intena2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_handle_l2t_err_lckerr2;
+    info.user_info          = (long)
+        "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
+        "    could not find an available/unlocked set (for\n"
+        "    replacement).\n"
+        "    Most likely, this is a result of SW mixing SET\n"
+        "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
+        "    another PP to LOCKDOWN all SETs available to PP#n,\n"
+        "    then a Rd/Wr Miss from PP#n will be unable\n"
+        "    to determine a 'valid' replacement set (since LOCKED\n"
+        "    addresses should NEVER be replaced).\n"
+        "    If such an event occurs, the HW will select the smallest\n"
+        "    available SET(specified by UMSK'x)' as the replacement\n"
+        "    set, and the address is unlocked.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* rml_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+        "    back from a RSL after sending a read command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* rml_wto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* rml_wto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+        "    back from a RSL after sending a write command to\n"
+        "    a RSL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* po0_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* po0_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<4 /* po1_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* po1_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<5 /* po2_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* po2_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<6 /* po3_2sml */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* po3_2sml */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
+        "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<7 /* i0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* i0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* i1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* i1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* i2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* i2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* i3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* i3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read instructions.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* i0_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* i0_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* i1_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* i1_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* i2_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* i2_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* i3_overf */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* i3_overf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
+        "    doorbell count was set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* p0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* p0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<16 /* p1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* p1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<17 /* p2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* p2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<18 /* p3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* p3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read packet data.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<19 /* p0_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* p0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<20 /* p1_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* p1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<21 /* p2_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* p2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<22 /* p3_perr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* p3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
+        "    data this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<23 /* g0_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* g0_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<24 /* g1_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* g1_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<25 /* g2_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* g2_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<26 /* g3_rtout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* g3_rtout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+        "    read a gather list.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<27 /* p0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* p0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<28 /* p1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* p1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<29 /* p2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* p2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<30 /* p3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* p3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
+        "    pointer-pair, this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<31 /* p0_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* p0_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<32 /* p1_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* p1_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<33 /* p2_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* p2_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<34 /* p3_ptout */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* p3_ptout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
+        "    pair.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<35 /* i0_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* i0_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<36 /* i1_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* i1_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<37 /* i2_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* i2_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<38 /* i3_pperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* i3_pperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
+        "    this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<39 /* win_rto */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* win_rto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<40 /* p_dperr */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* p_dperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+        "    from the PCI this bit may be set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<41 /* iobdma */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* iobdma */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<42 /* fcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* fcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<43 /* fcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* fcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<44 /* pcr_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<44 /* pcr_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<45 /* pcr_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<45 /* pcr_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<46 /* q2_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<46 /* q2_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<47 /* q2_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<47 /* q2_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* q3_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<48 /* q3_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* q3_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<49 /* q3_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* com_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<50 /* com_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* com_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<51 /* com_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pnc_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<52 /* pnc_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pnc_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<53 /* pnc_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* rwx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<54 /* rwx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* rdx_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<55 /* rdx_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* pcf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<56 /* pcf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* pcf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<57 /* pcf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<58 /* pdf_p_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<58 /* pdf_p_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<59 /* pdf_p_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<59 /* pdf_p_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* q1_s_e */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<60 /* q1_s_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 1ull<<61 /* q1_a_f */;
+    info.enable_addr        = CVMX_NPI_INT_ENB;
+    info.enable_mask        = 1ull<<61 /* q1_a_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
+        "    PASS3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_INT_SUM;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<3 /* npi */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NPI_PCI_INT_SUM2 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<0 /* tr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<0 /* rtr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<1 /* mr_wabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<1 /* rmr_wabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<2 /* mr_wtto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<2 /* rmr_wtto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<3 /* tr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<3 /* rtr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<4 /* mr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<4 /* rmr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<5 /* mr_tto */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<5 /* rmr_tto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<6 /* msi_per */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<6 /* rmsi_per */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<7 /* msi_tabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<7 /* rmsi_tabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<8 /* msi_mabt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<8 /* rmsi_mabt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<9 /* msc_msg */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<9 /* rmsc_msg */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<10 /* tsr_abt */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<10 /* rtsr_abt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<11 /* serr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<11 /* rserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<12 /* aperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<12 /* raperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<13 /* dperr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<13 /* rdperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<14 /* ill_rwr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<14 /* ill_rwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<15 /* ill_rrd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<15 /* ill_rrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<31 /* win_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<31 /* win_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+        "    Read-Address Register took place.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<32 /* ill_wr */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<32 /* ill_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NPI_PCI_INT_SUM2;
+    info.status_mask        = 1ull<<33 /* ill_rd */;
+    info.enable_addr        = CVMX_NPI_PCI_INT_ENB2;
+    info.enable_mask        = 1ull<<33 /* ill_rd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_INT_SUM;
+    info.parent.status_mask = 1ull<<2 /* pci_rsl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+        "    when the mem area is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<0 /* out_col */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xffffull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(1);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 17;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 18;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<2 /* maxerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<2 /* maxerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<5 /* alnerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<5 /* alnerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<6 /* lenerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<6 /* lenerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<9 /* niberr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<9 /* niberr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 19;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* ncb_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 1ull<<1 /* ncb_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<2 /* gmx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
+        "    This is a PASS-3 Field.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(0);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(0);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<18 /* spx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SPXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* prtnxa */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* abnorm */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* abnorm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* spiovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* spiovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* clserr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* clserr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* drwnng */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* drwnng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* rsverr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* rsverr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* tpaovr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<8 /* tpaovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* diperr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<9 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* syncerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<10 /* syncerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+        "    SPX_ERR_CTL[ERRCNT]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SPXX_INT_REG(1);
+    info.status_mask        = 1ull<<11 /* calerr */;
+    info.enable_addr        = CVMX_SPXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<11 /* calerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_STXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<0 /* calpar0 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<0 /* calpar0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<1 /* calpar1 */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<1 /* calpar1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<2 /* ovrbst */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<2 /* ovrbst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* datovr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<3 /* datovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* diperr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<4 /* diperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* nosync */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<5 /* nosync */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* unxfrm */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<6 /* unxfrm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_STXX_INT_REG(1);
+    info.status_mask        = 1ull<<7 /* frmerr */;
+    info.enable_addr        = CVMX_STXX_INT_MSK(1);
+    info.enable_mask        = 1ull<<7 /* frmerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<19 /* spx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(0);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(0);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ASXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<8 /* txpsh */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<8 /* txpsh */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<4 /* txpop */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<4 /* txpop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ASXX_INT_REG(1);
+    info.status_mask        = 0xfull<<0 /* ovrflw */;
+    info.enable_addr        = CVMX_ASXX_INT_EN(1);
+    info.enable_mask        = 0xfull<<0 /* ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asx1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_MEM_CFG0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<21 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<19 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0\n"
+        "    [22] corresponds to DQ[127:64], Phase0\n"
+        "    [23] corresponds to DQ[63:0], Phase1\n"
+        "    [24] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [21] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [22] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [23] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [24] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.status_mask        = 0xfull<<25 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_MEM_CFG0(0);
+    info.enable_mask        = 1ull<<20 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<17 /* lmc */;
+    info.func               = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
+    info.user_info          = (long)
+        "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    In 128b mode, ecc is calulated on 1 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0\n"
+        "    [26] corresponds to DQ[127:64], Phase0\n"
+        "    [27] corresponds to DQ[63:0], Phase1\n"
+        "    [28] corresponds to DQ[127:64], Phase1\n"
+        "    In 64b mode, ecc is calculated on 2 cycle worth of data\n"
+        "    [25] corresponds to DQ[63:0], Phase0, cycle0\n"
+        "    [26] corresponds to DQ[63:0], Phase0, cycle1\n"
+        "    [27] corresponds to DQ[63:0], Phase1, cycle0\n"
+        "    [28] corresponds to DQ[63:0], Phase1, cycle1\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<1 /* cp2sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2sbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a PP-generated QW Mode read\n"
+        "    transaction.\n"
+        "    If the CP2DBE=0, then the CP2SYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2SBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<2 /* cp2dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2dbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a PP-generated QW Mode read transaction.\n"
+        "    The CP2SYN contains the failing syndrome.\n"
+        "     NOTE: PP-generated LW Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n"
+        "    Refer to CP2ECCENA.\n"
+        "    If the CP2DBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<14 /* dtesbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtesbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
+        "    When set, a single bit error had been detected and\n"
+        "    corrected for a DTE-generated 36b SIMPLE Mode read\n"
+        "    transaction.\n"
+        "    If the DTEDBE=0, then the DTESYN contains the\n"
+        "    failing syndrome (used during correction).\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read\n"
+        "    transactions do not participate in ECC check/correct).\n"
+        "    If the DTESBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<15 /* dtedbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dtedbe;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
+        "    When set, a double bit error had been detected\n"
+        "    for a DTE-generated 36b SIMPLE Mode read transaction.\n"
+        "    The DTESYN contains the failing syndrome.\n"
+        "    If the DTEDBINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n"
+        "    NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
+        "    do not participate in ECC check/correct).\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<26 /* dteperr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dteperr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
+        "    When set, all DTE-generated 18b SIMPLE Mode read\n"
+        "    transactions which encounter a parity error (across\n"
+        "    the 17b of data) are reported.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<29 /* cp2perr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_cp2perr;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
+        "    When set, a parity error had been detected for a\n"
+        "    PP-generated LW Mode read transaction.\n"
+        "    If the CP2PINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    See also: DFA_MEMFADR CSR which contains more data\n"
+        "    about the memory address/control to help isolate\n"
+        "    the failure.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERR;
+    info.status_mask        = 1ull<<31 /* dblovf */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_handle_dfa_err_dblovf;
+    info.user_info          = (long)
+        "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
new file mode 100644
index 0000000..8370325
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
@@ -0,0 +1,7185 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn63xx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN63XX</h2>
+ * @dot
+ * digraph cn63xx
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
+ *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7"];
+ *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
+ *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
+ *     cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
+ *     cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
+ *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
+ *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
+ *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn63xx(void);
+
+int cvmx_error_initialize_cn63xx(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_BLOCK_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_BLOCK_INT;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<6 /* bigwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<6 /* bigwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<7 /* bigrd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<7 /* bigrd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<28 /* pool0th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<28 /* pool0th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
+        "    FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<29 /* pool1th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<29 /* pool1th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
+        "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<30 /* pool2th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<30 /* pool2th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
+        "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<31 /* pool3th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<31 /* pool3th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
+        "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<32 /* pool4th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<32 /* pool4th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
+        "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<33 /* pool5th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<33 /* pool5th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
+        "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<34 /* pool6th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<34 /* pool6th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
+        "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<35 /* pool7th */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<35 /* pool7th */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
+        "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
+        "    allocated or de-allocated.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<36 /* free0 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<36 /* free0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<37 /* free1 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<37 /* free1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<38 /* free2 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<38 /* free2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<39 /* free3 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<39 /* free3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<40 /* free4 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<40 /* free4 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<41 /* free5 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<41 /* free5 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<42 /* free6 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<42 /* free6 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<43 /* free7 */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<43 /* free7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_UCTLX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pp_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* pp_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* er_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* er_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* or_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<2 /* or_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* cf_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<3 /* cf_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* wb_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<4 /* wb_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* wb_pop_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<5 /* wb_pop_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFM_FNT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<0 /* sbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<0 /* sbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<1 /* dbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<1 /* dbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In MII/RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SRIOX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* bar_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<4 /* bar_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* deny_wr */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<5 /* deny_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* sli_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<6 /* sli_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
+        "    See SRIO(0..1)_INT_INFO[1:0]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* mce_rx */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<9 /* mce_rx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<12 /* log_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<12 /* log_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
+        "    See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<13 /* phy_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<13 /* phy_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
+        "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<18 /* omsg_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<18 /* omsg_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
+        "    See SRIO(0..1)_INT_INFO2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<19 /* pko_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<19 /* pko_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<20 /* rtry_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<20 /* rtry_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
+        "    See SRIO(0..1)_INT_INFO3\n"
+        "    When one or more of the segments in an outgoing\n"
+        "    message have a RTRY_ERR, SRIO will not set\n"
+        "    OMSG* after the message \"transfer\".\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<21 /* f_error */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<21 /* f_error */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<22 /* mac_buf */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<22 /* mac_buf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
+        "    See SRIO(0..1)_MAC_BUFFERS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<23 /* degrad */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<23 /* degrade */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<24 /* fail */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<24 /* fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<25 /* ttl_tout */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<25 /* ttl_tout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_DROP_PACKET\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SRIOX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* bar_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<4 /* bar_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* deny_wr */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<5 /* deny_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* sli_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<6 /* sli_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
+        "    See SRIO(0..1)_INT_INFO[1:0]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* mce_rx */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<9 /* mce_rx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<12 /* log_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<12 /* log_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
+        "    See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<13 /* phy_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<13 /* phy_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
+        "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<18 /* omsg_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<18 /* omsg_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
+        "    See SRIO(0..1)_INT_INFO2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<19 /* pko_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<19 /* pko_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<20 /* rtry_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<20 /* rtry_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
+        "    See SRIO(0..1)_INT_INFO3\n"
+        "    When one or more of the segments in an outgoing\n"
+        "    message have a RTRY_ERR, SRIO will not set\n"
+        "    OMSG* after the message \"transfer\".\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<21 /* f_error */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<21 /* f_error */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<22 /* mac_buf */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<22 /* mac_buf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
+        "    See SRIO(0..1)_MAC_BUFFERS\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<23 /* degrad */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<23 /* degrade */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<24 /* fail */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<24 /* fail */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<25 /* ttl_tout */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<25 /* ttl_tout */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
+        "    See SRIOMAINT(0..1)_DROP_PACKET\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* pin_bp */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<51 /* pin_bp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
+        "    See SLI_PKT_IN_BP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
new file mode 100644
index 0000000..ce80164
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
@@ -0,0 +1,6745 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Automatically generated error messages for cn63xxp1.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ * <hr><h2>Error tree for CN63XXP1</h2>
+ * @dot
+ * digraph cn63xxp1
+ * {
+ *     rankdir=LR;
+ *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
+ *     edge [fontsize=7, font=helvitica];
+ *     cvmx_root [label="ROOT|<root>root"];
+ *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
+ *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
+ *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
+ *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
+ *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
+ *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
+ *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
+ *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
+ *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
+ *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
+ *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<tad0>tad0"];
+ *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
+ *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
+ *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
+ *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
+ *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
+ *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
+ *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
+ *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
+ *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
+ *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
+ *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
+ *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
+ *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
+ *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
+ *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
+ *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
+ *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
+ *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
+ *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
+ *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
+ *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
+ *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
+ *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
+ *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
+ *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
+ *     cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
+ *     cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
+ *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
+ *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
+ *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
+ *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
+ *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
+ *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
+ *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
+ *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
+ *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
+ *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
+ *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
+ *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
+ *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
+ *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
+ *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
+ *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
+ *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
+ *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
+ *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
+ *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
+ *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
+ *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
+ *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
+ *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
+ *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
+ *     cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
+ *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
+ *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
+ *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
+ *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
+ *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
+ *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
+ *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
+ *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
+ *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
+ *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
+ *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
+ *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
+ *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
+ *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
+ *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
+ *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
+ *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
+ *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
+ *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
+ *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
+ *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
+ *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
+ * }
+ * @enddot
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-csr-typedefs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#endif
+
+int cvmx_error_initialize_cn63xxp1(void);
+
+int cvmx_error_initialize_cn63xxp1(void)
+{
+    cvmx_error_info_t info;
+    int fail = 0;
+
+    /* CVMX_CIU_INTX_SUM0(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INTX_SUM0(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(0);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(0);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
+    info.parent.status_mask = 1ull<<62 /* mii */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_INT_SUM1 */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_INT_SUM1;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIXX_ISR(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<0 /* odblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<0 /* ovfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(OVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
+        "    future ODBELL writes don't exceed the size of the\n"
+        "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
+        "    SW must reclaim O-Ring Entries by writing to the\n"
+        "    MIX_ORCNT[ORCNT]. .\n"
+        "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the O-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<1 /* idblovf */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<1 /* ivfena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
+        "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
+        "    with a value greater than the remaining #of\n"
+        "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
+        "    the following occurs:\n"
+        "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
+        "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
+        "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(IVFENA) is set, than an\n"
+        "    interrupt is reported for this event.\n"
+        "    SW should keep track of the #I-Ring Entries in use\n"
+        "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
+        "    future IDBELL writes don't exceed the size of the\n"
+        "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
+        "    SW must reclaim I-Ring Entries by keeping track of the\n"
+        "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
+        "    total #packets(not IRing Entries) and SW must further\n"
+        "    keep track of the # of I-Ring Entries associated with\n"
+        "    each packet as they are processed.\n"
+        "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
+        "    If it occurs, it's an indication that SW has\n"
+        "    overwritten the I-Ring buffer, and the only recourse\n"
+        "    is a HW reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<4 /* data_drp */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<4 /* data_drpena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
+        "    If this does occur, the DATA_DRP is set and the\n"
+        "    CIU_INTx_SUM0,4[MII] bits are set.\n"
+        "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
+        "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
+        "    interrupt is reported for this event.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<5 /* irun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<5 /* irunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
+        "    NOTE: If an IRUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIXX_ISR(1);
+    info.status_mask        = 1ull<<6 /* orun */;
+    info.enable_addr        = CVMX_MIXX_INTENA(1);
+    info.enable_mask        = 1ull<<6 /* orunena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<18 /* mii1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
+        "    If SW writes a larger value than what is currently\n"
+        "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
+        "    underflow condition.\n"
+        "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
+        "    NOTE: If an ORUN underflow condition is detected,\n"
+        "    the integrity of the MIX/AGL HW state has\n"
+        "    been compromised. To recover, SW must issue a\n"
+        "    software reset sequence (see: MIX_CTL[RESET]\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_NDF_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<2 /* wdog */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<2 /* wdog */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<3 /* sm_bad */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<3 /* sm_bad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<4 /* ecc_1bit */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<4 /* ecc_1bit */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<5 /* ecc_mult */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<5 /* ecc_mult */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_NDF_INT;
+    info.status_mask        = 1ull<<6 /* ovrf */;
+    info.enable_addr        = CVMX_NDF_INT_EN;
+    info.enable_mask        = 1ull<<6 /* ovrf */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_INT_SUM1;
+    info.parent.status_mask = 1ull<<19 /* nand */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
+        "    fatal error.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_CIU_BLOCK_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_CIU_BLOCK_INT;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
+    info.parent.status_addr = 0;
+    info.parent.status_mask = 0;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<0 /* holerd */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<0 /* holerd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<1 /* holewr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<1 /* holewr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<2 /* vrtwr */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<2 /* vrtwr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
+        "    Set when L2C_VRT_MEM blocked a store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<3 /* vrtidrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<3 /* vrtidrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
+        "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
+        "    store.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<4 /* vrtadrng */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<4 /* vrtadrng */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
+        "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
+        "    store.\n"
+        "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 1ull<<5 /* vrtpe */;
+    info.enable_addr        = CVMX_L2C_INT_ENA;
+    info.enable_mask        = 1ull<<5 /* vrtpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
+        "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
+        "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
+        "    Software should correct the error.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_INT_REG;
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<16 /* l2c */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TDTX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<60 /* vsbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<61 /* vdbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_L2C_ERR_TTGX(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<61 /* noway */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
+        "    L2C sets NOWAY during its processing of a\n"
+        "    transaction whenever it needed/wanted to allocate\n"
+        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
+        "    is (generally) not an indication that L2C failed to\n"
+        "    complete transactions. Rather, it is a hint of\n"
+        "    possible performance degradation. (For example, L2C\n"
+        "    must read-modify-write DRAM for every transaction\n"
+        "    that updates some, but not all, of the bytes in a\n"
+        "    cache block, misses in the L2 cache, and cannot\n"
+        "    allocate a WAY.) There is one \"failure\" case where\n"
+        "    L2C will set NOWAY: when it cannot leave a block\n"
+        "    locked in the L2 cache as part of a LCKL2\n"
+        "    transaction.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<62 /* sbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
+    info.status_mask        = 1ull<<63 /* dbe */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IPD_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<0 /* prc_par0 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* prc_par0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+        "    [31:0] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<1 /* prc_par1 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* prc_par1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+        "    [63:32] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<2 /* prc_par2 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* prc_par2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+        "    [95:64] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<3 /* prc_par3 */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* prc_par3 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+        "    [127:96] of the PBM memory.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<4 /* bp_sub */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* bp_sub */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+        "    supplied illegal value.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<5 /* dc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* dc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<6 /* cc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* cc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<7 /* c_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* c_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<8 /* d_coll */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* d_coll */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+        "    collides.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IPD_INT_SUM;
+    info.status_mask        = 1ull<<9 /* bc_ovr */;
+    info.enable_addr        = CVMX_IPD_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* bc_ovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<9 /* ipd */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_POW_ECC_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<0 /* sbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<2 /* sbe_ie */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<1 /* dbe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<3 /* dbe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 1ull<<12 /* rpe */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 1ull<<13 /* rpe_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_POW_ECC_ERR;
+    info.status_mask        = 0x1fffull<<16 /* iop */;
+    info.enable_addr        = CVMX_POW_ECC_ERR;
+    info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<12 /* pow */;
+    info.func               = __cvmx_error_handle_pow_ecc_err_iop;
+    info.user_info          = (long)
+        "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_RAD_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_RAD_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_RAD_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<14 /* rad */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSX_INTX_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<2 /* an_err */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<2 /* an_err_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<3 /* txfifu */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<3 /* txfifu_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<4 /* txfifo */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<4 /* txfifo_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+        "    condition\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<5 /* txbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<5 /* txbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<7 /* rxbad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<7 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<8 /* rxlock */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<8 /* rxlock_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+        "    failure occurs\n"
+        "    Cannot fire in loopback1 mode\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<9 /* an_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<9 /* an_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<10 /* sync_bad */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<10 /* sync_bad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+        "    state. Should never be set during normal operation\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
+    info.status_mask        = 1ull<<12 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
+    info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PCSXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* txflt */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<0 /* txflt_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* rxbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<1 /* rxbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* rxsynbad */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+        "    in one of the 4 xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* synlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<4 /* synlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* algnlos */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<5 /* algnlos_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* dbg_sync */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PIP_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<3 /* prtnxa */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<3 /* prtnxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<4 /* badtag */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<4 /* badtag */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<5 /* skprunt */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<5 /* skprunt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+        "    This interrupt can occur with received PARTIAL\n"
+        "    packets that are truncated to SKIP bytes or\n"
+        "    smaller.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<6 /* todoovr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<6 /* todoovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<7 /* feperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<7 /* feperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<8 /* beperr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<8 /* beperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PIP_INT_REG;
+    info.status_mask        = 1ull<<12 /* punyerr */;
+    info.enable_addr        = CVMX_PIP_INT_EN;
+    info.enable_mask        = 1ull<<12 /* punyerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<20 /* pip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+        "    stripping in IPD is enable\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PKO_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<0 /* parity */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* parity */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<1 /* doorbell */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<1 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PKO_REG_ERROR;
+    info.status_mask        = 1ull<<2 /* currzero */;
+    info.enable_addr        = CVMX_PKO_REG_INT_MASK;
+    info.enable_mask        = 1ull<<2 /* currzero */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<10 /* pko */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(0);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(0);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<25 /* pem0 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(0);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_INT_SUM(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<1 /* se */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<1 /* se */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
+        "    (cfg_sys_err_rc)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<4 /* up_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<4 /* up_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<5 /* up_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<5 /* up_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<6 /* up_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<6 /* up_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<7 /* un_b1 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<7 /* un_b1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
+        "    is not set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<8 /* un_b2 */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<8 /* un_b2 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<9 /* un_bx */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<9 /* un_bx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<11 /* rdlk */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<11 /* rdlk */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<12 /* crs_er */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<12 /* crs_er */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 1ull<<13 /* crs_dr */;
+    info.enable_addr        = CVMX_PEMX_INT_ENB(1);
+    info.enable_mask        = 1ull<<13 /* crs_dr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_INT_SUM(1);
+    info.status_mask        = 0;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<26 /* pem1 */;
+    info.func               = __cvmx_error_decode;
+    info.user_info          = 0;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEMX_DBG_INFO(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<0 /* spoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<0 /* spoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
+        "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<2 /* rtlplle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<2 /* rtlplle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
+        "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<3 /* recrce */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<3 /* recrce */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
+        "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<4 /* rpoison */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<4 /* rpoison */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
+        "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<5 /* rcemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<5 /* rcemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+        "    pedc_radm_correctable_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<6 /* rnfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<6 /* rnfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_nonfatal_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<7 /* rfemrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<7 /* rfemrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+        "    pedc_radm_fatal_err\n"
+        "    Bit set when a message with ERR_FATAL is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<8 /* rpmerc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<8 /* rpmerc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
+        "    pedc_radm_pm_pme\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<9 /* rptamrc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<9 /* rptamrc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+        "    (RC Mode only)\n"
+        "    pedc_radm_pm_to_ack\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<10 /* rumep */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<10 /* rumep */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+        "    pedc_radm_msg_unlock\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<11 /* rvdm */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<11 /* rvdm */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
+        "    pedc_radm_vendor_msg\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<12 /* acto */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<12 /* acto */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
+        "    pedc_radm_cpl_timeout\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<13 /* rte */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<13 /* rte */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
+        "    xdlh_replay_timeout_err\n"
+        "    This bit is set when the REPLAY_TIMER expires in\n"
+        "    the PCIE core. The probability of this bit being\n"
+        "    set will increase with the traffic load.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<14 /* mre */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<14 /* mre */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
+        "    xdlh_replay_num_rlover_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<15 /* rdwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<15 /* rdwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+        "    rdlh_bad_dllp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<16 /* rtwdle */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<16 /* rtwdle */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
+        "    rdlh_bad_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<17 /* dpeoosd */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<17 /* dpeoosd */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+        "    rdlh_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<18 /* fcpvwt */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<18 /* fcpvwt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+        "    rtlh_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<19 /* rpe */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<19 /* rpe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
+        "    (RxStatus = 3b100) or disparity error\n"
+        "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+        "    be asserted.\n"
+        "    rmlh_rcvd_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<20 /* fcuv */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<20 /* fcuv */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
+        "    int_xadm_fc_prot_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<21 /* rqo */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<21 /* rqo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
+        "    flow control advertisements are ignored\n"
+        "    radm_qoverflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<22 /* rauc */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<22 /* rauc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
+        "    radm_unexp_cpl_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<23 /* racur */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<23 /* racur */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
+        "    radm_rcvd_cpl_ur\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<24 /* racca */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<24 /* racca */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
+        "    radm_rcvd_cpl_ca\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<25 /* caar */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<25 /* caar */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
+        "    radm_rcvd_ca_req\n"
+        "    This bit will never be set because Octeon does\n"
+        "    not generate Completer Aborts.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<26 /* rarwdns */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<26 /* rarwdns */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
+        "    radm_rcvd_ur_req\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<27 /* ramtlp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<27 /* ramtlp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
+        "    radm_mlf_tlp_err\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<28 /* racpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<28 /* racpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
+        "    radm_rcvd_cpl_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<29 /* rawwpp */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<29 /* rawwpp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
+        "    radm_rcvd_wreq_poisoned\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEMX_DBG_INFO(1);
+    info.status_mask        = 1ull<<30 /* ecrc_e */;
+    info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
+    info.enable_mask        = 1ull<<30 /* ecrc_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_PCI;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
+    info.parent.status_mask = 1ull<<10 /* exc */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
+        "    radm_ecrc_err\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_FPA_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<0 /* fed0_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* fed0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<1 /* fed0_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* fed0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<2 /* fed1_sbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* fed1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<3 /* fed1_dbe */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* fed1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<4 /* q0_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* q0_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<5 /* q0_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* q0_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<6 /* q0_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<6 /* q0_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<7 /* q1_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<7 /* q1_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<8 /* q1_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<8 /* q1_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<9 /* q1_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<9 /* q1_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<10 /* q2_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<10 /* q2_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<11 /* q2_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<11 /* q2_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<12 /* q2_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<12 /* q2_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<13 /* q3_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<13 /* q3_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<14 /* q3_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<14 /* q3_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<15 /* q3_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<15 /* q3_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<16 /* q4_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<16 /* q4_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<17 /* q4_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<17 /* q4_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<18 /* q4_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<18 /* q4_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<19 /* q5_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<19 /* q5_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<20 /* q5_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<20 /* q5_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<21 /* q5_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<21 /* q5_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<22 /* q6_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<22 /* q6_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<23 /* q6_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<23 /* q6_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<24 /* q6_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<24 /* q6_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<25 /* q7_und */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<25 /* q7_und */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+        "    negative.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<26 /* q7_coff */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<26 /* q7_coff */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+        "    the count available is greater than than pointers\n"
+        "    present in the FPA.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_FPA_INT_SUM;
+    info.status_mask        = 1ull<<27 /* q7_perr */;
+    info.enable_addr        = CVMX_FPA_INT_ENB;
+    info.enable_mask        = 1ull<<27 /* q7_perr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<5 /* fpa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+        "    the L2C does not have the FPA owner ship bit set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_UCTLX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pp_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<0 /* pp_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<1 /* er_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<1 /* er_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<2 /* or_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<2 /* or_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* cf_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<3 /* cf_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* wb_psh_f */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<4 /* wb_psh_f */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* wb_pop_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<5 /* wb_pop_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_UCTLX_INT_REG(0);
+    info.status_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
+    info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_USB;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<13 /* usb */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
+        "    When the error happenes, the whole NCB system needs\n"
+        "    to be reset.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_BOOT_ERR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<0 /* adr_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<0 /* adr_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_BOOT_ERR;
+    info.status_mask        = 1ull<<1 /* wait_err */;
+    info.enable_addr        = CVMX_MIO_BOOT_INT;
+    info.enable_mask        = 1ull<<1 /* wait_int */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_MIO_RST_INT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<0 /* rst_link0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<0 /* rst_link0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL0[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<1 /* rst_link1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<1 /* rst_link1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
+        "    MIO_RST_CTL1[RST_LINK]=0.  Software must assert\n"
+        "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<8 /* perst0 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<8 /* perst0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
+        "    and MIO_RST_CTL0[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_MIO_RST_INT;
+    info.status_mask        = 1ull<<9 /* perst1 */;
+    info.enable_addr        = CVMX_MIO_RST_INT_EN;
+    info.enable_mask        = 1ull<<9 /* perst1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<0 /* mio */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
+        "    and MIO_RST_CTL1[RST_CHIP]=0\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFM_FNT_STAT */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<0 /* sbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<0 /* sbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFM_FNT_STAT;
+    info.status_mask        = 1ull<<1 /* dbe_err */;
+    info.enable_addr        = CVMX_DFM_FNT_IENA;
+    info.enable_mask        = 1ull<<1 /* dbe_intena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<40 /* dfm */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
+        "    Memory Read.\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_TIM_REG_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_TIM_REG_ERROR;
+    info.status_mask        = 0xffffull<<0 /* mask */;
+    info.enable_addr        = CVMX_TIM_REG_INT_MASK;
+    info.enable_mask        = 0xffffull<<0 /* mask */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<11 /* tim */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_LMCX_INT(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<1 /* sec_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
+    info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 1ull<<0 /* nxm_wr_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_LMCX_INT(0);
+    info.status_mask        = 0xfull<<5 /* ded_err */;
+    info.enable_addr        = CVMX_LMCX_INT_EN(0);
+    info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_LMC;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<17 /* lmc0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
+        "    [0] corresponds to DQ[63:0]_c0_p0\n"
+        "    [1] corresponds to DQ[63:0]_c0_p1\n"
+        "    [2] corresponds to DQ[63:0]_c1_p0\n"
+        "    [3] corresponds to DQ[63:0]_c1_p1\n"
+        "    where _cC_pP denotes cycle C and phase P\n"
+        "    Write of 1 will clear the corresponding error bit\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_KEY_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<0 /* ked0_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* ked0_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<1 /* ked0_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* ked0_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<2 /* ked1_sbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* ked1_sbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_KEY_INT_SUM;
+    info.status_mask        = 1ull<<3 /* ked1_dbe */;
+    info.enable_addr        = CVMX_KEY_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* ked1_dbe */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<4 /* key */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_BAD_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In SGMII, one bit per port\n"
+        "    In XAUI, only port0 is used\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 1ull<<26 /* statovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
+        "    The common FIFO to SGMII and XAUI had an overflow\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_BAD_REG(0);
+    info.status_mask        = 0xfull<<27 /* inb_nxa */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(0,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(1,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(2,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 2;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_RXX_INT_REG(3,0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<1 /* carext */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<1 /* carext */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n"
+        "    (SGMII/1000Base-X only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<20 /* loc_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<20 /* loc_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<21 /* rem_fault */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<21 /* rem_fault */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<22 /* bad_seq */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<22 /* bad_seq */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<23 /* bad_term */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<23 /* bad_term */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
+        "    than /T/.  The error propagation control\n"
+        "    character /E/ will be included as part of the\n"
+        "    frame and does not cause a frame termination.\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<24 /* unsop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<24 /* unsop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<25 /* uneop */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<25 /* uneop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<26 /* undat */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<26 /* undat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
+        "    (XAUI Mode only)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<27 /* hg2fld */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<27 /* hg2fld */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
+        "    1) MSG_TYPE field not 6'b00_0000\n"
+        "       i.e. it is not a FLOW CONTROL message, which\n"
+        "       is the only defined type for HiGig2\n"
+        "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+        "       which is the only defined type for HiGig2\n"
+        "    3) FC_OBJECT field is neither 4'b0000 for\n"
+        "       Physical Link nor 4'b0010 for Logical Link.\n"
+        "       Those are the only two defined types in HiGig2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
+    info.status_mask        = 1ull<<28 /* hg2cc */;
+    info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
+    info.enable_mask        = 1ull<<28 /* hg2cc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 3;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+        "    Set when either CRC8 error detected or when\n"
+        "    a Control Character is found in the message\n"
+        "    bytes after the K.SOM\n"
+        "    NOTE: HG2CC has higher priority than HG2FLD\n"
+        "          i.e. a HiGig2 message that results in HG2CC\n"
+        "          getting set, will never set HG2FLD.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_GMXX_TX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<2 /* undflw */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
+    info.status_mask        = 0xfull<<20 /* ptp_lost */;
+    info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
+    info.enable_mask        = 0xfull<<20 /* ptp_lost */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<1 /* gmx0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
+        "    sent due to XSCOL\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_IOB_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<0 /* np_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<0 /* np_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<1 /* np_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<1 /* np_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<2 /* p_sop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<2 /* p_sop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<3 /* p_eop */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<3 /* p_eop */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<4 /* np_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<4 /* np_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a non-passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_IOB_INT_SUM;
+    info.status_mask        = 1ull<<5 /* p_dat */;
+    info.enable_addr        = CVMX_IOB_INT_ENB;
+    info.enable_mask        = 1ull<<5 /* p_dat */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<30 /* iob */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+        "    port for a passthrough packet.\n"
+        "    The first detected error associated with bits [5:0]\n"
+        "    of this register will only be set here. A new bit\n"
+        "    can be set when the previous reported bit is cleared.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_BAD_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<32 /* ovrflw */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<33 /* txpop */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<34 /* txpsh */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<35 /* ovrflw1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<36 /* txpop1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 1ull<<37 /* txpsh1 */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<2 /* out_ovr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_BAD_REG;
+    info.status_mask        = 0x3ull<<22 /* loststat */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
+        "    In MII/RGMII, one bit per port\n"
+        "    TX Stats are corrupted\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_RXX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<8 /* skperr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<8 /* skperr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
+    info.status_mask        = 1ull<<10 /* ovrerr */;
+    info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
+    info.enable_mask        = 1ull<<10 /* ovrerr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
+        "    This interrupt should never assert\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_AGL_GMX_TX_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 1ull<<0 /* pko_nxa */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 1ull<<0 /* pko_nxa */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
+    info.status_mask        = 0x3ull<<2 /* undflw */;
+    info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
+    info.enable_mask        = 0x3ull<<2 /* undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<28 /* agl */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_ZIP_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_ZIP_ERROR;
+    info.status_mask        = 1ull<<0 /* doorbell */;
+    info.enable_addr        = CVMX_ZIP_INT_MASK;
+    info.enable_mask        = 1ull<<0 /* doorbell */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<7 /* zip */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DFA_ERROR */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 1ull<<0 /* dblovf */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 1ull<<0 /* dblina */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
+        "    When set, the 20b accumulated doorbell register\n"
+        "    had overflowed (SW wrote too many doorbell requests).\n"
+        "    If the DBLINA had previously been enabled(set),\n"
+        "    an interrupt will be posted. Software can clear\n"
+        "    the interrupt by writing a 1 to this register bit.\n"
+        "    NOTE: Detection of a Doorbell Register overflow\n"
+        "    is a catastrophic error which may leave the DFA\n"
+        "    HW in an unrecoverable state.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DFA_ERROR;
+    info.status_mask        = 0x7ull<<1 /* dc0perr */;
+    info.enable_addr        = CVMX_DFA_INTMSK;
+    info.enable_mask        = 0x7ull<<1 /* dc0pena */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<6 /* dfa */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
+        "    See also DFA_DTCFADR register which contains the\n"
+        "    failing addresses for the internal node cache RAMs.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SRIOX_INT_REG(0) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<4 /* bar_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<4 /* bar_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<5 /* deny_wr */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<5 /* deny_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<6 /* sli_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<6 /* sli_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
+        "    See SRIO(0..1)_INT_INFO[1:0]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<9 /* mce_rx */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<9 /* mce_rx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<12 /* log_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<12 /* log_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
+        "    See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<13 /* phy_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<13 /* phy_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
+        "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<18 /* omsg_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<18 /* omsg_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
+        "    See SRIO(0..1)_INT_INFO2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<19 /* pko_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<19 /* pko_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<20 /* rtry_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<20 /* rtry_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
+        "    See SRIO(0..1)_INT_INFO3\n"
+        "    When one or more of the segments in an outgoing\n"
+        "    message have a RTRY_ERR, SRIO will not set\n"
+        "    OMSG* after the message \"transfer\".\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<21 /* f_error */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<21 /* f_error */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_SRIOX_INT_REG(1) */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<4 /* bar_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<4 /* bar_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<5 /* deny_wr */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<5 /* deny_wr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<6 /* sli_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<6 /* sli_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
+        "    See SRIO(0..1)_INT_INFO[1:0]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<9 /* mce_rx */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<9 /* mce_rx */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<12 /* log_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<12 /* log_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
+        "    See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<13 /* phy_erb */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<13 /* phy_erb */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
+        "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<18 /* omsg_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<18 /* omsg_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
+        "    See SRIO(0..1)_INT_INFO2\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<19 /* pko_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<19 /* pko_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<20 /* rtry_err */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<20 /* rtry_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
+        "    See SRIO(0..1)_INT_INFO3\n"
+        "    When one or more of the segments in an outgoing\n"
+        "    message have a RTRY_ERR, SRIO will not set\n"
+        "    OMSG* after the message \"transfer\".\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<21 /* f_error */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<21 /* f_error */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_PEXP_SLI_INT_SUM */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<0 /* rml_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<0 /* rml_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
+        "    within 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<2 /* bar0_to */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<2 /* bar0_to */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+        "    read-data/commit in 0xffff core clocks.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<3 /* iob2big */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<3 /* iob2big */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
+;
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<9 /* m0_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<9 /* m0_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<11 /* m0_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<11 /* m0_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 0. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<13 /* m1_up_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<13 /* m1_up_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
+        "    This occurs when the BAR 0 address space is\n"
+        "    disabeled.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<15 /* m1_un_wi */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<15 /* m1_un_wi */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
+        "    from MAC 1. This occurs when the window registers\n"
+        "    are disabeld and a window register access occurs.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<48 /* pidbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<48 /* pidbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<49 /* psldbof */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<49 /* psldbof */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+        "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<50 /* pout_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<50 /* pout_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
+        "    set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<51 /* pin_bp */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<51 /* pin_bp */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
+        "    See SLI_PKT_IN_BP\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<52 /* pgl_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<52 /* pgl_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
+        "    read this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<53 /* pdi_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<53 /* pdi_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<54 /* pop_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<54 /* pop_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
+        "    pointer pair this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<55 /* pins_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<55 /* pins_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<56 /* sprt0_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<56 /* sprt0_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<57 /* sprt1_err */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<57 /* sprt1_err */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
+    info.status_mask        = 1ull<<60 /* ill_pad */;
+    info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
+    info.enable_mask        = 1ull<<60 /* ill_pad */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<3 /* sli */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
+        "    range of the Packet-CSR, but for an unused\n"
+        "    address.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_INT_REG */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<0 /* nderr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<0 /* nderr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
+        "    DPI received a NCB transaction on the outbound\n"
+        "    bus to the DPI deviceID, but the command was not\n"
+        "    recognized.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<1 /* nfovr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<1 /* nfovr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
+        "    DPI can store upto 16 CSR request.  The FIFO will\n"
+        "    overflow if that number is exceeded.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 0xffull<<8 /* dmadbo */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 0xffull<<8 /* dmadbo */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
+        "    DPI has a 32-bit counter for each request's queue\n"
+        "    outstanding doorbell counts. Interrupt will fire\n"
+        "    if the count overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<16 /* req_badadr */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<16 /* req_badadr */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch to the NULL pointer.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<17 /* req_badlen */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<17 /* req_badlen */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
+        "    Interrupt will fire if DPI forms an instruction\n"
+        "    fetch with length of zero.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<18 /* req_ovrflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<18 /* req_ovrflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO overflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<19 /* req_undflw */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<19 /* req_undflw */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
+        "    DPI tracks outstanding instructions fetches.\n"
+        "    Interrupt will fire when FIFO underflows.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<20 /* req_anull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<20 /* req_anull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
+        "    Fetched instruction word was 0.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<21 /* req_inull */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<21 /* req_inull */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
+        "    Next pointer was NULL.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<22 /* req_badfil */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<22 /* req_badfil */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
+        "    Instruction fill when none outstanding.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<24 /* sprt0_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<24 /* sprt0_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_INT_REG;
+    info.status_mask        = 1ull<<25 /* sprt1_rst */;
+    info.enable_addr        = CVMX_DPI_INT_EN;
+    info.enable_mask        = 1ull<<25 /* sprt1_rst */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
+        "     destination port was in reset.\n"
+        "    this bit is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_PKT_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
+    info.status_mask        = 1ull<<0 /* pkterr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
+        "    the I/O subsystem.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RSP */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
+        "    ErrorResponse from the I/O subsystem.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    /* CVMX_DPI_REQ_ERR_RST */
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_DPI_REQ_ERR_RST;
+    info.status_mask        = 0xffull<<0 /* qerr */;
+    info.enable_addr        = 0;
+    info.enable_mask        = 0;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<41 /* dpi */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
+        "    instruction because the source or destination\n"
+        "    was in reset.\n"
+        "    SW must clear the bit before the the cooresponding\n"
+        "    instruction queue will continue processing\n"
+        "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
+    fail |= cvmx_error_add(&info);
+
+    return fail;
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error.c b/sys/contrib/octeon-sdk/cvmx-error.c
new file mode 100644
index 0000000..7b33b37
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error.c
@@ -0,0 +1,643 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Interface to the Octeon extended error status.
+ *
+ * <hr>$Revision: 44252 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-error.h>
+#include <asm/octeon/cvmx-error-custom.h>
+#include <asm/octeon/cvmx-pcie.h>
+#include <asm/octeon/cvmx-srio.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#else
+#include "cvmx.h"
+#include "cvmx-error.h"
+#include "cvmx-error-custom.h"
+#include "cvmx-pcie.h"
+#include "cvmx-srio.h"
+#include "cvmx-interrupt.h"
+#endif
+
+#define MAX_TABLE_SIZE 1024   /* Max number of error status bits we can support */
+
+extern int cvmx_error_initialize_cn63xx(void);
+extern int cvmx_error_initialize_cn63xxp1(void);
+extern int cvmx_error_initialize_cn58xxp1(void);
+extern int cvmx_error_initialize_cn58xx(void);
+extern int cvmx_error_initialize_cn56xxp1(void);
+extern int cvmx_error_initialize_cn56xx(void);
+extern int cvmx_error_initialize_cn50xx(void);
+extern int cvmx_error_initialize_cn52xxp1(void);
+extern int cvmx_error_initialize_cn52xx(void);
+extern int cvmx_error_initialize_cn38xxp2(void);
+extern int cvmx_error_initialize_cn38xx(void);
+extern int cvmx_error_initialize_cn31xx(void);
+extern int cvmx_error_initialize_cn30xx(void);
+
+/* Each entry in this array represents a status bit function or chain */
+static CVMX_SHARED cvmx_error_info_t __cvmx_error_table[MAX_TABLE_SIZE];
+static CVMX_SHARED int __cvmx_error_table_size = 0;
+static CVMX_SHARED cvmx_error_flags_t __cvmx_error_flags;
+
+#define REG_MATCH(h, reg_type, status_addr, status_mask) \
+    ((h->reg_type == reg_type) && (h->status_addr == status_addr) && (h->status_mask == status_mask))
+
+/**
+ * @INTERNAL
+ * Read a status or enable register from the hardware
+ *
+ * @param reg_type Register type to read
+ * @param addr     Address to read
+ *
+ * @return Result of the read
+ */
+static uint64_t __cvmx_error_read_hw(cvmx_error_register_t reg_type, uint64_t addr)
+{
+    switch (reg_type)
+    {
+        case __CVMX_ERROR_REGISTER_NONE:
+            return 0;
+        case CVMX_ERROR_REGISTER_IO64:
+            return cvmx_read_csr(addr);
+        case CVMX_ERROR_REGISTER_IO32:
+            return cvmx_read64_uint32(addr ^ 4);
+        case CVMX_ERROR_REGISTER_PCICONFIG:
+            return cvmx_pcie_cfgx_read(addr>>32, addr&0xffffffffull);
+        case CVMX_ERROR_REGISTER_SRIOMAINT:
+        {
+            uint32_t r;
+            if (cvmx_srio_config_read32(addr>>32, 0, -1, 0, 0, addr&0xffffffffull, &r))
+                return 0;
+            else
+                return r;
+        }
+    }
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Write a status or enable register to the hardware
+ *
+ * @param reg_type Register type to write
+ * @param addr     Address to write
+ * @param value    Value to write
+ */
+static void __cvmx_error_write_hw(cvmx_error_register_t reg_type, uint64_t addr, uint64_t value)
+{
+    switch (reg_type)
+    {
+        case __CVMX_ERROR_REGISTER_NONE:
+            return;
+        case CVMX_ERROR_REGISTER_IO64:
+            cvmx_write_csr(addr, value);
+            return;
+        case CVMX_ERROR_REGISTER_IO32:
+            cvmx_write64_uint32(addr ^ 4, value);
+            return;
+        case CVMX_ERROR_REGISTER_PCICONFIG:
+            cvmx_pcie_cfgx_write(addr>>32, addr&0xffffffffull, value);
+            return;
+        case CVMX_ERROR_REGISTER_SRIOMAINT:
+        {
+            cvmx_srio_config_write32(addr>>32, 0, -1, 0, 0, addr&0xffffffffull, value);
+            return;
+        }
+    }
+}
+
+/**
+ * @INTERNAL
+ * Function for processing non leaf error status registers. This function
+ * calls all handlers for this passed register and all children linked
+ * to it.
+ *
+ * @param info   Error register to check
+ *
+ * @return Number of error status bits found or zero if no bits were set.
+ */
+int __cvmx_error_decode(const cvmx_error_info_t *info)
+{
+    uint64_t status;
+    uint64_t enable;
+    int i;
+    int handled = 0;
+
+    /* Read the status and enable state */
+    status = __cvmx_error_read_hw(info->reg_type, info->status_addr);
+    if (info->enable_addr)
+        enable = __cvmx_error_read_hw(info->reg_type, info->enable_addr);
+    else
+        enable = 0;
+
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        const cvmx_error_info_t *h = &__cvmx_error_table[i];
+        uint64_t masked_status = status;
+
+        /* If this is a child of the current register then recurse and process
+            the child */
+        if ((h->parent.reg_type == info->reg_type) &&
+            (h->parent.status_addr == info->status_addr) &&
+            (status & h->parent.status_mask))
+            handled += __cvmx_error_decode(h);
+
+        if ((h->reg_type != info->reg_type) || (h->status_addr != info->status_addr))
+            continue;
+
+        /* If the corresponding enable bit is not set then we have nothing to do */
+        if (h->enable_addr && h->enable_mask)
+        {
+            if (!(enable & h->enable_mask))
+                continue;
+        }
+
+        /* Apply the mask to eliminate irrelevant bits */
+        if (h->status_mask)
+            masked_status &= h->status_mask;
+
+        /* Finally call the handler function unless it is this function */
+        if (masked_status && h->func && (h->func != __cvmx_error_decode))
+            handled += h->func(h);
+    }
+    /* Ths should be the total errors found */
+    return handled;
+}
+
+/**
+ * @INTERNAL
+ * This error bit handler simply prints a message and clears the status bit
+ *
+ * @param info   Error register to check
+ *
+ * @return
+ */
+int __cvmx_error_display(const cvmx_error_info_t *info)
+{
+    const char *message = (const char *)(long)info->user_info;
+    /* This assumes that all bits in the status register are RO or R/W1C */
+    __cvmx_error_write_hw(info->reg_type, info->status_addr, info->status_mask);
+    cvmx_safe_printf("%s", message);
+    return 1;
+}
+
+/**
+ * Initalize the error status system. This should be called once
+ * before any other functions are called. This function adds default
+ * handlers for most all error events but does not enable them. Later
+ * calls to cvmx_error_enable() are needed.
+ *
+ * @param flags  Optional flags.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_initialize(cvmx_error_flags_t flags)
+{
+    __cvmx_error_flags = flags;
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+    {
+        if (cvmx_error_initialize_cn63xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn63xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn58xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        if (cvmx_error_initialize_cn58xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn56xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        if (cvmx_error_initialize_cn56xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        if (cvmx_error_initialize_cn50xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn52xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        if (cvmx_error_initialize_cn52xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+    {
+        if (cvmx_error_initialize_cn38xxp2())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        if (cvmx_error_initialize_cn38xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        if (cvmx_error_initialize_cn31xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        if (cvmx_error_initialize_cn30xx())
+            return -1;
+    }
+    else
+    {
+        cvmx_warn("cvmx_error_initialize() needs update for this Octeon model\n");
+        return -1;
+    }
+
+    if (__cvmx_error_custom_initialize())
+        return -1;
+
+    /* Enable all of the purely internal error sources by default */
+    cvmx_error_enable_group(CVMX_ERROR_GROUP_INTERNAL, 0);
+
+    /* Enable DDR error reporting based on the memory controllers */
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        cvmx_l2c_cfg_t l2c_cfg;
+        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        if (l2c_cfg.s.dpres0)
+            cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
+        if (l2c_cfg.s.dpres1)
+            cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 1);
+    }
+    else
+        cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
+
+    /* Old PCI parts don't have a common PCI init, so enable error
+        reporting if the bootloader told us we are a PCI host. PCIe
+        is handled when cvmx_pcie_rc_initialize is called */
+    if (!octeon_has_feature(OCTEON_FEATURE_PCIE) &&
+        (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST))
+        cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, 0);
+
+    /* FIXME: Why is this needed for CN63XX? */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+
+    return 0;
+}
+
+/**
+ * Poll the error status registers and call the appropriate error
+ * handlers. This should be called in the RSL interrupt handler
+ * for your application or operating system.
+ *
+ * @return Number of error handlers called. Zero means this call
+ *         found no errors and was spurious.
+ */
+int cvmx_error_poll(void)
+{
+    int i;
+    int count = 0;
+    /* Call all handlers that don't have a parent */
+    for (i = 0; i < __cvmx_error_table_size; i++)
+        if (__cvmx_error_table[i].parent.reg_type == __CVMX_ERROR_REGISTER_NONE)
+            count += __cvmx_error_decode(&__cvmx_error_table[i]);
+    return count;
+}
+
+/**
+ * Register to be called when an error status bit is set. Most users
+ * will not need to call this function as cvmx_error_initialize()
+ * registers default handlers for most error conditions. This function
+ * is normally used to add more handlers without changing the existing
+ * handlers.
+ *
+ * @param new_info Information about the handler for a error register. The
+ *                 structure passed is copied and can be destroyed after the
+ *                 call. All members of the structure must be populated, even the
+ *                 parent information.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_add(const cvmx_error_info_t *new_info)
+{
+    if (__cvmx_error_table_size >= MAX_TABLE_SIZE)
+    {
+        cvmx_warn("cvmx-error table full\n");
+        return -1;
+    }
+    __cvmx_error_table[__cvmx_error_table_size] = *new_info;
+    __cvmx_error_table_size++;
+    return 0;
+}
+
+/**
+ * Remove all handlers for a status register and mask. Normally
+ * this function should not be called. Instead a new handler should be
+ * installed to replace the existing handler. In the even that all
+ * reporting of a error bit should be removed, then use this
+ * function.
+ *
+ * @param reg_type Type of the status register to remove
+ * @param status_addr
+ *                 Status register to remove.
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 removed.
+ * @param old_info If not NULL, this is filled with information about the handler
+ *                 that was removed.
+ *
+ * @return Zero on success, negative on failure (not found).
+ */
+int cvmx_error_remove(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask,
+                        cvmx_error_info_t *old_info)
+{
+    int found = 0;
+    int i;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        cvmx_error_info_t *h = &__cvmx_error_table[i];
+        if (!REG_MATCH(h, reg_type, status_addr, status_mask))
+            continue;
+        if (old_info)
+            *old_info = *h;
+        memset(h, 0, sizeof(*h));
+        found = 1;
+    }
+    if (found)
+        return 0;
+    else
+    {
+        cvmx_warn("cvmx-error remove couldn't find requested register\n");
+        return -1;
+    }
+}
+
+/**
+ * Change the function and user_info for an existing error status
+ * register. This function should be used to replace the default
+ * handler with an application specific version as needed.
+ *
+ * @param reg_type Type of the status register to change
+ * @param status_addr
+ *                 Status register to change.
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 changed.
+ * @param new_func New function to use to handle the error status
+ * @param new_user_info
+ *                 New user info parameter for the function
+ * @param old_func If not NULL, the old function is returned. Useful for restoring
+ *                 the old handler.
+ * @param old_user_info
+ *                 If not NULL, the old user info parameter.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_error_change_handler(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask,
+                        cvmx_error_func_t new_func, uint64_t new_user_info,
+                        cvmx_error_func_t *old_func, uint64_t *old_user_info)
+{
+    int found = 0;
+    int i;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        cvmx_error_info_t *h = &__cvmx_error_table[i];
+        if (!REG_MATCH(h, reg_type, status_addr, status_mask))
+            continue;
+        if (old_func)
+            *old_func = h->func;
+        if (old_user_info)
+            *old_user_info = h->user_info;
+        h->func = new_func;
+        h->user_info = new_user_info;
+        found = 1;
+    }
+    if (found)
+        return 0;
+    else
+    {
+        cvmx_warn("cvmx-error change couldn't find requested register\n");
+        return -1;
+    }
+}
+
+/**
+ * Enable all error registers for a logical group. This should be
+ * called whenever a logical group is brought online.
+ *
+ * @param group  Logical group to enable
+ * @param group_index
+ *               Index for the group as defined in the cvmx_error_group_t
+ *               comments.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
+{
+    int i;
+    uint64_t enable;
+
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return 0;
+
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        const cvmx_error_info_t *h = &__cvmx_error_table[i];
+        /* Skip entries that have a different group or group index. We
+            also skip entries that don't have an enable */
+        if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
+            continue;
+        /* Skip entries that have flags that don't match the user's
+            selected flags */
+        if (h->flags && (h->flags != (h->flags & __cvmx_error_flags)))
+            continue;
+        /* Update the enables for this entry */
+        enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
+        if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
+            enable &= ~h->enable_mask; /* PCI bits have reversed polarity */
+        else
+            enable |= h->enable_mask;
+        __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
+    }
+    return 0;
+}
+
+/**
+ * Disable all error registers for a logical group. This should be
+ * called whenever a logical group is brought offline. Many blocks
+ * will report spurious errors when offline unless this function
+ * is called.
+ *
+ * @param group  Logical group to disable
+ * @param group_index
+ *               Index for the group as defined in the cvmx_error_group_t
+ *               comments.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
+{
+    int i;
+    uint64_t enable;
+
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return 0;
+
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        const cvmx_error_info_t *h = &__cvmx_error_table[i];
+        /* Skip entries that have a different group or group index. We
+            also skip entries that don't have an enable */
+        if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
+            continue;
+        /* Update the enables for this entry */
+        enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
+        if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
+            enable |= h->enable_mask; /* PCI bits have reversed polarity */
+        else
+            enable &= ~h->enable_mask;
+        __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
+    }
+    return 0;
+}
+
+/**
+ * Enable all handlers for a specific status register mask.
+ *
+ * @param reg_type Type of the status register
+ * @param status_addr
+ *                 Status register address
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 enabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_enable(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask)
+{
+    int found = 0;
+    int i;
+    uint64_t enable;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        cvmx_error_info_t *h = &__cvmx_error_table[i];
+        if (!REG_MATCH(h, reg_type, status_addr, status_mask) || !h->enable_addr)
+            continue;
+        enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
+        if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
+            enable &= ~h->enable_mask; /* PCI bits have reversed polarity */
+        else
+            enable |= h->enable_mask;
+        __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
+        h->flags &= ~CVMX_ERROR_FLAGS_DISABLED;
+        found = 1;
+    }
+    if (found)
+        return 0;
+    else
+    {
+        cvmx_warn("cvmx-error enable couldn't find requested register\n");
+        return -1;
+    }
+}
+
+/**
+ * Disable all handlers for a specific status register and mask.
+ *
+ * @param reg_type Type of the status register
+ * @param status_addr
+ *                 Status register address
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 disabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_disable(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask)
+{
+    int found = 0;
+    int i;
+    uint64_t enable;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        cvmx_error_info_t *h = &__cvmx_error_table[i];
+        if (!REG_MATCH(h, reg_type, status_addr, status_mask) || !h->enable_addr)
+            continue;
+        enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
+        if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
+            enable |= h->enable_mask; /* PCI bits have reversed polarity */
+        else
+            enable &= ~h->enable_mask;
+        __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
+        h->flags |= CVMX_ERROR_FLAGS_DISABLED;
+        found = 1;
+    }
+    if (found)
+        return 0;
+    else
+    {
+        cvmx_warn("cvmx-error disable couldn't find requested register\n");
+        return -1;
+    }
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-error.h b/sys/contrib/octeon-sdk/cvmx-error.h
new file mode 100644
index 0000000..2c1415d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-error.h
@@ -0,0 +1,318 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Interface to the Octeon extended error status.
+ *
+ * <hr>$Revision: 44252 $<hr>
+ */
+#ifndef __CVMX_ERROR_H__
+#define __CVMX_ERROR_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * There are generally many error status bits associated with a
+ * single logical group. The enumeration below is used to
+ * communicate high level groups to the error infastructure so
+ * error status bits can be enable or disabled in large groups.
+ */
+typedef enum
+{
+    CVMX_ERROR_GROUP_INTERNAL,  /* All internal blocks that can always be enabled */
+    CVMX_ERROR_GROUP_ETHERNET,  /* All errors related to network traffic that should be enabled when a port is up. Indexed by IPD number */
+    CVMX_ERROR_GROUP_MGMT_PORT, /* All errors related to the management ethernet ports that should be enabled when a port is up. Indexed by port number (0-1) */
+    CVMX_ERROR_GROUP_PCI,       /* All errors related to PCI/PCIe when the bus is up. Index by port number (0-1) */
+    CVMX_ERROR_GROUP_SRIO,      /* All errors related to SRIO when the bus is up. Index by port number (0-1) */
+    CVMX_ERROR_GROUP_USB,       /* All errors related to USB when the port is enabled. Index by port number (0-1) */
+    CVMX_ERROR_GROUP_LMC,       /* All errors related to LMC when the controller is enabled. Index by controller number (0-1) */
+} cvmx_error_group_t;
+
+/**
+ * When registering for interest in an error status register, the
+ * type of the register needs to be known by cvmx-error. Most
+ * registers are either IO64 or IO32, but some blocks contain
+ * registers that can't be directly accessed. A good example of
+ * would be PCIe extended error state stored in config space.
+ */
+typedef enum
+{
+    __CVMX_ERROR_REGISTER_NONE,     /* Used internally */
+    CVMX_ERROR_REGISTER_IO64,       /* Status and enable registers are Octeon 64bit CSRs */
+    CVMX_ERROR_REGISTER_IO32,       /* Status and enable registers are Octeon 32bit CSRs */
+    CVMX_ERROR_REGISTER_PCICONFIG,  /* Status and enable registers are in PCI config space */
+    CVMX_ERROR_REGISTER_SRIOMAINT,  /* Status and enable registers are in SRIO maintenance space */
+} cvmx_error_register_t;
+
+/**
+ * Flags representing special handling for some error registers.
+ * These flags are passed to cvmx_error_initialize() to control
+ * the handling of bits where the same flags were passed to the
+ * added cvmx_error_info_t.
+ */
+typedef enum
+{
+    CVMX_ERROR_FLAGS_ECC_SINGLE_BIT = 1<<0, /* This is a ECC single bit error. Normally these can be ignored */
+    CVMX_ERROR_FLAGS_CORRECTABLE = 1<<1,    /* Some blocks have errors that can be silently corrected. This flags reports these */
+    CVMX_ERROR_FLAGS_DISABLED = 1<<2,       /* Flag used to signal a register should not be enable as part of the groups */
+} cvmx_error_flags_t;
+
+struct cvmx_error_info;
+/**
+ * Error handling functions must have the following prototype.
+ */
+typedef int (*cvmx_error_func_t)(const struct cvmx_error_info *info);
+
+/**
+ * This structure is passed to all error handling functions.
+ */
+typedef struct cvmx_error_info
+{
+    cvmx_error_register_t   reg_type;       /* Type of registers used for the error */
+    uint64_t                status_addr;    /* The address of the status register */
+    uint64_t                status_mask;    /* Mask to apply to status register to detect asserted error */
+    uint64_t                enable_addr;    /* The address of the enable register */
+    uint64_t                enable_mask;    /* Mask to apply to enable register to allow error detection */
+    cvmx_error_flags_t      flags;          /* Flags indicating special handling of this error */
+    cvmx_error_group_t      group;          /* Group to associate this error register with */
+    int                     group_index;    /* Group index to associate this error register with */
+    cvmx_error_func_t       func;           /* Function to call when the error is detected */
+    uint64_t                user_info;      /* User supplied information for the error handler */
+    struct
+    {
+        cvmx_error_register_t reg_type;     /* Type of parent's register */
+        uint64_t            status_addr;    /* The address of the parent's register */
+        uint64_t            status_mask;    /* Mask to apply to parent's register */
+    } parent;
+} cvmx_error_info_t;
+
+/**
+ * Initalize the error status system. This should be called once
+ * before any other functions are called. This function adds default
+ * handlers for most all error events but does not enable them. Later
+ * calls to cvmx_error_enable() are needed.
+ *
+ * @param flags  Optional flags.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_initialize(cvmx_error_flags_t flags);
+
+/**
+ * Poll the error status registers and call the appropriate error
+ * handlers. This should be called in the RSL interrupt handler
+ * for your application or operating system.
+ *
+ * @return Number of error handlers called. Zero means this call
+ *         found no errors and was spurious.
+ */
+int cvmx_error_poll(void);
+
+/**
+ * Register to be called when an error status bit is set. Most users
+ * will not need to call this function as cvmx_error_initialize()
+ * registers default handlers for most error conditions. This function
+ * is normally used to add more handlers without changing the existing
+ * handlers.
+ *
+ * @param new_info Information about the handler for a error register. The
+ *                 structure passed is copied and can be destroyed after the
+ *                 call. All members of the structure must be populated, even the
+ *                 parent information.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_add(const cvmx_error_info_t *new_info);
+
+/**
+ * Remove all handlers for a status register and mask. Normally
+ * this function should not be called. Instead a new handler should be
+ * installed to replace the existing handler. In the even that all
+ * reporting of a error bit should be removed, then use this
+ * function.
+ *
+ * @param reg_type Type of the status register to remove
+ * @param status_addr
+ *                 Status register to remove.
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 removed.
+ * @param old_info If not NULL, this is filled with information about the handler
+ *                 that was removed.
+ *
+ * @return Zero on success, negative on failure (not found).
+ */
+int cvmx_error_remove(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask,
+                        cvmx_error_info_t *old_info);
+
+/**
+ * Change the function and user_info for an existing error status
+ * register. This function should be used to replace the default
+ * handler with an application specific version as needed.
+ *
+ * @param reg_type Type of the status register to change
+ * @param status_addr
+ *                 Status register to change.
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 changed.
+ * @param new_func New function to use to handle the error status
+ * @param new_user_info
+ *                 New user info parameter for the function
+ * @param old_func If not NULL, the old function is returned. Useful for restoring
+ *                 the old handler.
+ * @param old_user_info
+ *                 If not NULL, the old user info parameter.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_error_change_handler(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask,
+                        cvmx_error_func_t new_func, uint64_t new_user_info,
+                        cvmx_error_func_t *old_func, uint64_t *old_user_info);
+
+/**
+ * Enable all error registers for a logical group. This should be
+ * called whenever a logical group is brought online.
+ *
+ * @param group  Logical group to enable
+ * @param group_index
+ *               Index for the group as defined in the cvmx_error_group_t
+ *               comments.
+ *
+ * @return Zero on success, negative on failure.
+ */
+#ifndef CVMX_BUILD_FOR_UBOOT
+int cvmx_error_enable_group(cvmx_error_group_t group, int group_index);
+#else
+/* Rather than conditionalize the calls throughout the executive to not enable
+    interrupts in Uboot, simply make the enable function do nothing */
+static inline int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
+{
+    return 0;
+}
+#endif
+
+/**
+ * Disable all error registers for a logical group. This should be
+ * called whenever a logical group is brought offline. Many blocks
+ * will report spurious errors when offline unless this function
+ * is called.
+ *
+ * @param group  Logical group to disable
+ * @param group_index
+ *               Index for the group as defined in the cvmx_error_group_t
+ *               comments.
+ *
+ * @return Zero on success, negative on failure.
+ */
+#ifndef CVMX_BUILD_FOR_UBOOT
+int cvmx_error_disable_group(cvmx_error_group_t group, int group_index);
+#else
+/* Rather than conditionalize the calls throughout the executive to not disable
+    interrupts in Uboot, simply make the enable function do nothing */
+static inline int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
+{
+    return 0;
+}
+#endif
+
+/**
+ * Enable all handlers for a specific status register mask.
+ *
+ * @param reg_type Type of the status register
+ * @param status_addr
+ *                 Status register address
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 enabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_enable(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask);
+
+/**
+ * Disable all handlers for a specific status register and mask.
+ *
+ * @param reg_type Type of the status register
+ * @param status_addr
+ *                 Status register address
+ * @param status_mask
+ *                 All handlers for this status register with this mask will be
+ *                 disabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_error_disable(cvmx_error_register_t reg_type,
+                        uint64_t status_addr, uint64_t status_mask);
+
+/**
+ * @INTERNAL
+ * Function for processing non leaf error status registers. This function
+ * calls all handlers for this passed register and all children linked
+ * to it.
+ *
+ * @param info   Error register to check
+ *
+ * @return Number of error status bits found or zero if no bits were set.
+ */
+int __cvmx_error_decode(const cvmx_error_info_t *info);
+
+/**
+ * @INTERNAL
+ * This error bit handler simply prints a message and clears the status bit
+ *
+ * @param info   Error register to check
+ *
+ * @return
+ */
+int __cvmx_error_display(const cvmx_error_info_t *info);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-fau.h b/sys/contrib/octeon-sdk/cvmx-fau.h
index 4e3e420..a8d0234 100644
--- a/sys/contrib/octeon-sdk/cvmx-fau.h
+++ b/sys/contrib/octeon-sdk/cvmx-fau.h
@@ -1,52 +1,49 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
  * Interface to the hardware Fetch and Add Unit.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_FAU_H__
@@ -139,11 +136,10 @@ typedef union {
    uint64_t        u64;
    struct {
       uint64_t     invalid: 1;
-      uint64_t     data   :63; // unpredictable if invalid is set
+     uint64_t     data   :63; /* unpredictable if invalid is set */
    } s;
 } cvmx_fau_async_tagwait_result_t;
 
-
 /**
  * @INTERNAL
  * Builds a store I/O address for writing to the FAU
@@ -163,7 +159,6 @@ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
             cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
 }
 
-
 /**
  * @INTERNAL
  * Builds a I/O address for accessing the FAU
@@ -189,7 +184,6 @@ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
             cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
 }
 
-
 /**
  * Perform an atomic 64 bit add
  *
@@ -204,7 +198,6 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t va
     return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
 }
 
-
 /**
  * Perform an atomic 32 bit add
  *
@@ -219,7 +212,6 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t va
     return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
 }
 
-
 /**
  * Perform an atomic 16 bit add
  *
@@ -233,7 +225,6 @@ static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t va
     return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
 }
 
-
 /**
  * Perform an atomic 8 bit add
  *
@@ -246,7 +237,6 @@ static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
     return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
 }
 
-
 /**
  * Perform an atomic 64 bit add after the current tag switch
  * completes
@@ -270,7 +260,6 @@ static inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg
     return result.t;
 }
 
-
 /**
  * Perform an atomic 32 bit add after the current tag switch
  * completes
@@ -294,7 +283,6 @@ static inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg
     return result.t;
 }
 
-
 /**
  * Perform an atomic 16 bit add after the current tag switch
  * completes
@@ -317,7 +305,6 @@ static inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg
     return result.t;
 }
 
-
 /**
  * Perform an atomic 8 bit add after the current tag switch
  * completes
@@ -339,7 +326,6 @@ static inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8
     return result.t;
 }
 
-
 /**
  * @INTERNAL
  * Builds I/O data for async operations
@@ -375,7 +361,6 @@ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, u
                       cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
 }
 
-
 /**
  * Perform an async atomic 64 bit add. The old value is
  * placed in the scratch memory at byte address scraddr.
@@ -393,7 +378,6 @@ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
 }
 
-
 /**
  * Perform an async atomic 32 bit add. The old value is
  * placed in the scratch memory at byte address scraddr.
@@ -411,7 +395,6 @@ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
 }
 
-
 /**
  * Perform an async atomic 16 bit add. The old value is
  * placed in the scratch memory at byte address scraddr.
@@ -428,7 +411,6 @@ static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
 }
 
-
 /**
  * Perform an async atomic 8 bit add. The old value is
  * placed in the scratch memory at byte address scraddr.
@@ -444,7 +426,6 @@ static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
 }
 
-
 /**
  * Perform an async atomic 64 bit add after the current tag
  * switch completes.
@@ -465,7 +446,6 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
 }
 
-
 /**
  * Perform an async atomic 32 bit add after the current tag
  * switch completes.
@@ -486,7 +466,6 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
 }
 
-
 /**
  * Perform an async atomic 16 bit add after the current tag
  * switch completes.
@@ -506,7 +485,6 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
 }
 
-
 /**
  * Perform an async atomic 8 bit add after the current tag
  * switch completes.
@@ -525,9 +503,6 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_
     cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
 }
 
-
-
-
 /**
  * Perform an atomic 64 bit add
  *
@@ -540,7 +515,6 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
     cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
 }
 
-
 /**
  * Perform an atomic 32 bit add
  *
@@ -553,7 +527,6 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
     cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
 }
 
-
 /**
  * Perform an atomic 16 bit add
  *
@@ -566,7 +539,6 @@ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
     cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
 }
 
-
 /**
  * Perform an atomic 8 bit add
  *
@@ -578,7 +550,6 @@ static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
     cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
 }
 
-
 /**
  * Perform an atomic 64 bit write
  *
@@ -591,7 +562,6 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
     cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
 }
 
-
 /**
  * Perform an atomic 32 bit write
  *
@@ -604,7 +574,6 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
     cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
 }
 
-
 /**
  * Perform an atomic 16 bit write
  *
@@ -617,7 +586,6 @@ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
     cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
 }
 
-
 /**
  * Perform an atomic 8 bit write
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-flash.c b/sys/contrib/octeon-sdk/cvmx-flash.c
index 2c4ea04..bba7948 100644
--- a/sys/contrib/octeon-sdk/cvmx-flash.c
+++ b/sys/contrib/octeon-sdk/cvmx-flash.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
@@ -247,8 +249,8 @@ static int __cvmx_flash_queury_cfi(int chip_id, void *base_ptr)
     }
 
     /* Convert the timeouts to cycles */
-    flash->write_timeout *= cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
-    flash->erase_timeout *= cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    flash->write_timeout *= cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
+    flash->erase_timeout *= cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
 
 #if DEBUG
     /* Print the information about the chip */
diff --git a/sys/contrib/octeon-sdk/cvmx-flash.h b/sys/contrib/octeon-sdk/cvmx-flash.h
index 6bac116..e187fff 100644
--- a/sys/contrib/octeon-sdk/cvmx-flash.h
+++ b/sys/contrib/octeon-sdk/cvmx-flash.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa-defs.h b/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
new file mode 100644
index 0000000..e9d2764
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
@@ -0,0 +1,1423 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-fpa-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon fpa.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_FPA_TYPEDEFS_H__
+#define __CVMX_FPA_TYPEDEFS_H__
+
+#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
+#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000000ull);
+}
+#else
+#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000058ull);
+}
+#else
+#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
+#endif
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7))))))
+		cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1;
+}
+#else
+#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7))))))
+		cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1;
+}
+#else
+#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
+#endif
+#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
+#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC()
+static inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000460ull);
+}
+#else
+#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
+#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
+#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
+#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
+#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
+#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
+#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
+#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
+#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC()
+static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_FPA_WART_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800280000D8ull);
+}
+#else
+#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_FPA_WART_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800280000E0ull);
+}
+#else
+#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC()
+static inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180028000468ull);
+}
+#else
+#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
+#endif
+
+/**
+ * cvmx_fpa_bist_status
+ *
+ * FPA_BIST_STATUS = BIST Status of FPA Memories
+ *
+ * The result of the BIST run on the FPA memories.
+ */
+union cvmx_fpa_bist_status
+{
+	uint64_t u64;
+	struct cvmx_fpa_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t frd                          : 1;  /**< fpa_frd  memory bist status. */
+	uint64_t fpf0                         : 1;  /**< fpa_fpf0 memory bist status. */
+	uint64_t fpf1                         : 1;  /**< fpa_fpf1 memory bist status. */
+	uint64_t ffr                          : 1;  /**< fpa_ffr  memory bist status. */
+	uint64_t fdr                          : 1;  /**< fpa_fdr  memory bist status. */
+#else
+	uint64_t fdr                          : 1;
+	uint64_t ffr                          : 1;
+	uint64_t fpf1                         : 1;
+	uint64_t fpf0                         : 1;
+	uint64_t frd                          : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_fpa_bist_status_s         cn30xx;
+	struct cvmx_fpa_bist_status_s         cn31xx;
+	struct cvmx_fpa_bist_status_s         cn38xx;
+	struct cvmx_fpa_bist_status_s         cn38xxp2;
+	struct cvmx_fpa_bist_status_s         cn50xx;
+	struct cvmx_fpa_bist_status_s         cn52xx;
+	struct cvmx_fpa_bist_status_s         cn52xxp1;
+	struct cvmx_fpa_bist_status_s         cn56xx;
+	struct cvmx_fpa_bist_status_s         cn56xxp1;
+	struct cvmx_fpa_bist_status_s         cn58xx;
+	struct cvmx_fpa_bist_status_s         cn58xxp1;
+	struct cvmx_fpa_bist_status_s         cn63xx;
+	struct cvmx_fpa_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t;
+
+/**
+ * cvmx_fpa_ctl_status
+ *
+ * FPA_CTL_STATUS = FPA's Control/Status Register
+ *
+ * The FPA's interrupt enable register.
+ */
+union cvmx_fpa_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_fpa_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t free_en                      : 1;  /**< Enables the setting of the INT_SUM_[FREE*] bits. */
+	uint64_t ret_off                      : 1;  /**< When set NCB devices returning pointer will be
+                                                         stalled. */
+	uint64_t req_off                      : 1;  /**< When set NCB devices requesting pointers will be
+                                                         stalled. */
+	uint64_t reset                        : 1;  /**< When set causes a reset of the FPA with the
+                                                         exception of the RSL. This is a PASS-2 field. */
+	uint64_t use_ldt                      : 1;  /**< When clear '0' the FPA will use LDT to load
+                                                         pointers from the L2C. This is a PASS-2 field. */
+	uint64_t use_stt                      : 1;  /**< When clear '0' the FPA will use STT to store
+                                                         pointers to the L2C. This is a PASS-2 field. */
+	uint64_t enb                          : 1;  /**< Must be set to 1 AFTER writing all config registers
+                                                         and 10 cycles have past. If any of the config
+                                                         register are written after writing this bit the
+                                                         FPA may begin to operate incorrectly. */
+	uint64_t mem1_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 1. */
+	uint64_t mem0_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 0. */
+#else
+	uint64_t mem0_err                     : 7;
+	uint64_t mem1_err                     : 7;
+	uint64_t enb                          : 1;
+	uint64_t use_stt                      : 1;
+	uint64_t use_ldt                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t req_off                      : 1;
+	uint64_t ret_off                      : 1;
+	uint64_t free_en                      : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_fpa_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t reset                        : 1;  /**< When set causes a reset of the FPA with the
+                                                         exception of the RSL. */
+	uint64_t use_ldt                      : 1;  /**< When clear '0' the FPA will use LDT to load
+                                                         pointers from the L2C. */
+	uint64_t use_stt                      : 1;  /**< When clear '0' the FPA will use STT to store
+                                                         pointers to the L2C. */
+	uint64_t enb                          : 1;  /**< Must be set to 1 AFTER writing all config registers
+                                                         and 10 cycles have past. If any of the config
+                                                         register are written after writing this bit the
+                                                         FPA may begin to operate incorrectly. */
+	uint64_t mem1_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 1. */
+	uint64_t mem0_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 0. */
+#else
+	uint64_t mem0_err                     : 7;
+	uint64_t mem1_err                     : 7;
+	uint64_t enb                          : 1;
+	uint64_t use_stt                      : 1;
+	uint64_t use_ldt                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn30xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn31xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn38xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn38xxp2;
+	struct cvmx_fpa_ctl_status_cn30xx     cn50xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn52xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn52xxp1;
+	struct cvmx_fpa_ctl_status_cn30xx     cn56xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn56xxp1;
+	struct cvmx_fpa_ctl_status_cn30xx     cn58xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn58xxp1;
+	struct cvmx_fpa_ctl_status_s          cn63xx;
+	struct cvmx_fpa_ctl_status_cn30xx     cn63xxp1;
+};
+typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t;
+
+/**
+ * cvmx_fpa_fpf#_marks
+ *
+ * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks
+ *
+ * The high and low watermark register that determines when we write and read free pages from L2C
+ * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value
+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
+ */
+union cvmx_fpa_fpfx_marks
+{
+	uint64_t u64;
+	struct cvmx_fpa_fpfx_marks_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t fpf_wr                       : 11; /**< When the number of free-page-pointers in a
+                                                          queue exceeds this value the FPA will write
+                                                          32-page-pointers of that queue to DRAM.
+                                                         The MAX value for this field should be
+                                                         FPA_FPF1_SIZE[FPF_SIZ]-2. */
+	uint64_t fpf_rd                       : 11; /**< When the number of free-page-pointers in a
+                                                          queue drops below this value and there are
+                                                          free-page-pointers in DRAM, the FPA will
+                                                          read one page (32 pointers) from DRAM.
+                                                         This maximum value for this field should be
+                                                         FPA_FPF1_SIZE[FPF_SIZ]-34. The min number
+                                                         for this would be 16. */
+#else
+	uint64_t fpf_rd                       : 11;
+	uint64_t fpf_wr                       : 11;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_fpa_fpfx_marks_s          cn38xx;
+	struct cvmx_fpa_fpfx_marks_s          cn38xxp2;
+	struct cvmx_fpa_fpfx_marks_s          cn56xx;
+	struct cvmx_fpa_fpfx_marks_s          cn56xxp1;
+	struct cvmx_fpa_fpfx_marks_s          cn58xx;
+	struct cvmx_fpa_fpfx_marks_s          cn58xxp1;
+	struct cvmx_fpa_fpfx_marks_s          cn63xx;
+	struct cvmx_fpa_fpfx_marks_s          cn63xxp1;
+};
+typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t;
+
+/**
+ * cvmx_fpa_fpf#_size
+ *
+ * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size
+ *
+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
+ */
+union cvmx_fpa_fpfx_size
+{
+	uint64_t u64;
+	struct cvmx_fpa_fpfx_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t fpf_siz                      : 11; /**< The number of entries assigned in the FPA FIFO
+                                                         (used to hold page-pointers) for this Queue.
+                                                         The value of this register must divisable by 2,
+                                                         and the FPA will ignore bit [0] of this register.
+                                                         The total of the FPF_SIZ field of the 8 (0-7)
+                                                         FPA_FPF#_SIZE registers must not exceed 2048.
+                                                         After writing this field the FPA will need 10
+                                                         core clock cycles to be ready for operation. The
+                                                         assignment of location in the FPA FIFO must
+                                                         start with Queue 0, then 1, 2, etc.
+                                                         The number of useable entries will be FPF_SIZ-2. */
+#else
+	uint64_t fpf_siz                      : 11;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_fpa_fpfx_size_s           cn38xx;
+	struct cvmx_fpa_fpfx_size_s           cn38xxp2;
+	struct cvmx_fpa_fpfx_size_s           cn56xx;
+	struct cvmx_fpa_fpfx_size_s           cn56xxp1;
+	struct cvmx_fpa_fpfx_size_s           cn58xx;
+	struct cvmx_fpa_fpfx_size_s           cn58xxp1;
+	struct cvmx_fpa_fpfx_size_s           cn63xx;
+	struct cvmx_fpa_fpfx_size_s           cn63xxp1;
+};
+typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t;
+
+/**
+ * cvmx_fpa_fpf0_marks
+ *
+ * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks
+ *
+ * The high and low watermark register that determines when we write and read free pages from L2C
+ * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value
+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
+ */
+union cvmx_fpa_fpf0_marks
+{
+	uint64_t u64;
+	struct cvmx_fpa_fpf0_marks_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t fpf_wr                       : 12; /**< When the number of free-page-pointers in a
+                                                          queue exceeds this value the FPA will write
+                                                          32-page-pointers of that queue to DRAM.
+                                                         The MAX value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
+	uint64_t fpf_rd                       : 12; /**< When the number of free-page-pointers in a
+                                                         queue drops below this value and there are
+                                                         free-page-pointers in DRAM, the FPA will
+                                                         read one page (32 pointers) from DRAM.
+                                                         This maximum value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
+                                                         for this would be 16. */
+#else
+	uint64_t fpf_rd                       : 12;
+	uint64_t fpf_wr                       : 12;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_fpa_fpf0_marks_s          cn38xx;
+	struct cvmx_fpa_fpf0_marks_s          cn38xxp2;
+	struct cvmx_fpa_fpf0_marks_s          cn56xx;
+	struct cvmx_fpa_fpf0_marks_s          cn56xxp1;
+	struct cvmx_fpa_fpf0_marks_s          cn58xx;
+	struct cvmx_fpa_fpf0_marks_s          cn58xxp1;
+	struct cvmx_fpa_fpf0_marks_s          cn63xx;
+	struct cvmx_fpa_fpf0_marks_s          cn63xxp1;
+};
+typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t;
+
+/**
+ * cvmx_fpa_fpf0_size
+ *
+ * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size
+ *
+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
+ */
+union cvmx_fpa_fpf0_size
+{
+	uint64_t u64;
+	struct cvmx_fpa_fpf0_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t fpf_siz                      : 12; /**< The number of entries assigned in the FPA FIFO
+                                                         (used to hold page-pointers) for this Queue.
+                                                         The value of this register must divisable by 2,
+                                                         and the FPA will ignore bit [0] of this register.
+                                                         The total of the FPF_SIZ field of the 8 (0-7)
+                                                         FPA_FPF#_SIZE registers must not exceed 2048.
+                                                         After writing this field the FPA will need 10
+                                                         core clock cycles to be ready for operation. The
+                                                         assignment of location in the FPA FIFO must
+                                                         start with Queue 0, then 1, 2, etc.
+                                                         The number of useable entries will be FPF_SIZ-2. */
+#else
+	uint64_t fpf_siz                      : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_fpa_fpf0_size_s           cn38xx;
+	struct cvmx_fpa_fpf0_size_s           cn38xxp2;
+	struct cvmx_fpa_fpf0_size_s           cn56xx;
+	struct cvmx_fpa_fpf0_size_s           cn56xxp1;
+	struct cvmx_fpa_fpf0_size_s           cn58xx;
+	struct cvmx_fpa_fpf0_size_s           cn58xxp1;
+	struct cvmx_fpa_fpf0_size_s           cn63xx;
+	struct cvmx_fpa_fpf0_size_s           cn63xxp1;
+};
+typedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t;
+
+/**
+ * cvmx_fpa_int_enb
+ *
+ * FPA_INT_ENB = FPA's Interrupt Enable
+ *
+ * The FPA's interrupt enable register.
+ */
+union cvmx_fpa_int_enb
+{
+	uint64_t u64;
+	struct cvmx_fpa_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t free7                        : 1;  /**< When set (1) and bit 43 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free6                        : 1;  /**< When set (1) and bit 42 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free5                        : 1;  /**< When set (1) and bit 41 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free4                        : 1;  /**< When set (1) and bit 40 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free3                        : 1;  /**< When set (1) and bit 39 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free2                        : 1;  /**< When set (1) and bit 38 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free1                        : 1;  /**< When set (1) and bit 37 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t free0                        : 1;  /**< When set (1) and bit 36 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool7th                      : 1;  /**< When set (1) and bit 35 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool6th                      : 1;  /**< When set (1) and bit 34 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool5th                      : 1;  /**< When set (1) and bit 33 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool4th                      : 1;  /**< When set (1) and bit 32 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool3th                      : 1;  /**< When set (1) and bit 31 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool2th                      : 1;  /**< When set (1) and bit 30 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool1th                      : 1;  /**< When set (1) and bit 29 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t pool0th                      : 1;  /**< When set (1) and bit 28 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_coff                      : 1;  /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_und                       : 1;  /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_perr                      : 1;  /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_coff                      : 1;  /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_und                       : 1;  /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_perr                      : 1;  /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_coff                      : 1;  /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_und                       : 1;  /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_perr                      : 1;  /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_coff                      : 1;  /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_und                       : 1;  /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_perr                      : 1;  /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_coff                      : 1;  /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_und                       : 1;  /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_perr                      : 1;  /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_coff                      : 1;  /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_und                       : 1;  /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_perr                      : 1;  /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_coff                      : 1;  /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_und                       : 1;  /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_perr                      : 1;  /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_coff                      : 1;  /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_und                       : 1;  /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_dbe                     : 1;  /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_sbe                     : 1;  /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_dbe                     : 1;  /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_sbe                     : 1;  /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_fpa_int_enb_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t q7_perr                      : 1;  /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_coff                      : 1;  /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q7_und                       : 1;  /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_perr                      : 1;  /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_coff                      : 1;  /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q6_und                       : 1;  /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_perr                      : 1;  /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_coff                      : 1;  /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q5_und                       : 1;  /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_perr                      : 1;  /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_coff                      : 1;  /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q4_und                       : 1;  /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_perr                      : 1;  /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_coff                      : 1;  /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q3_und                       : 1;  /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_perr                      : 1;  /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_coff                      : 1;  /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q2_und                       : 1;  /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_perr                      : 1;  /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_coff                      : 1;  /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q1_und                       : 1;  /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_perr                      : 1;  /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_coff                      : 1;  /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t q0_und                       : 1;  /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_dbe                     : 1;  /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed1_sbe                     : 1;  /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_dbe                     : 1;  /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+	uint64_t fed0_sbe                     : 1;  /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn30xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn31xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn38xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn38xxp2;
+	struct cvmx_fpa_int_enb_cn30xx        cn50xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn52xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn52xxp1;
+	struct cvmx_fpa_int_enb_cn30xx        cn56xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn56xxp1;
+	struct cvmx_fpa_int_enb_cn30xx        cn58xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn58xxp1;
+	struct cvmx_fpa_int_enb_s             cn63xx;
+	struct cvmx_fpa_int_enb_cn30xx        cn63xxp1;
+};
+typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t;
+
+/**
+ * cvmx_fpa_int_sum
+ *
+ * FPA_INT_SUM = FPA's Interrupt Summary Register
+ *
+ * Contains the different interrupt summary bits of the FPA.
+ */
+union cvmx_fpa_int_sum
+{
+	uint64_t u64;
+	struct cvmx_fpa_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t free7                        : 1;  /**< When a pointer for POOL7 is freed bit is set. */
+	uint64_t free6                        : 1;  /**< When a pointer for POOL6 is freed bit is set. */
+	uint64_t free5                        : 1;  /**< When a pointer for POOL5 is freed bit is set. */
+	uint64_t free4                        : 1;  /**< When a pointer for POOL4 is freed bit is set. */
+	uint64_t free3                        : 1;  /**< When a pointer for POOL3 is freed bit is set. */
+	uint64_t free2                        : 1;  /**< When a pointer for POOL2 is freed bit is set. */
+	uint64_t free1                        : 1;  /**< When a pointer for POOL1 is freed bit is set. */
+	uint64_t free0                        : 1;  /**< When a pointer for POOL0 is freed bit is set. */
+	uint64_t pool7th                      : 1;  /**< Set when FPA_QUE7_AVAILABLE is equal to
+                                                         FPA_POOL7_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool6th                      : 1;  /**< Set when FPA_QUE6_AVAILABLE is equal to
+                                                         FPA_POOL6_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool5th                      : 1;  /**< Set when FPA_QUE5_AVAILABLE is equal to
+                                                         FPA_POOL5_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool4th                      : 1;  /**< Set when FPA_QUE4_AVAILABLE is equal to
+                                                         FPA_POOL4_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool3th                      : 1;  /**< Set when FPA_QUE3_AVAILABLE is equal to
+                                                         FPA_POOL3_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool2th                      : 1;  /**< Set when FPA_QUE2_AVAILABLE is equal to
+                                                         FPA_POOL2_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool1th                      : 1;  /**< Set when FPA_QUE1_AVAILABLE is equal to
+                                                         FPA_POOL1_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t pool0th                      : 1;  /**< Set when FPA_QUE0_AVAILABLE is equal to
+                                                         FPA_POOL`_THRESHOLD[THRESH] and a pointer is
+                                                         allocated or de-allocated. */
+	uint64_t q7_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q7_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q7_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q6_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q6_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q6_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q5_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q5_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q5_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q4_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q4_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q4_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q3_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q3_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q3_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q2_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q2_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q2_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q1_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q1_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q1_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q0_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q0_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q0_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t fed1_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF1. */
+	uint64_t fed1_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF1. */
+	uint64_t fed0_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF0. */
+	uint64_t fed0_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF0. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t pool0th                      : 1;
+	uint64_t pool1th                      : 1;
+	uint64_t pool2th                      : 1;
+	uint64_t pool3th                      : 1;
+	uint64_t pool4th                      : 1;
+	uint64_t pool5th                      : 1;
+	uint64_t pool6th                      : 1;
+	uint64_t pool7th                      : 1;
+	uint64_t free0                        : 1;
+	uint64_t free1                        : 1;
+	uint64_t free2                        : 1;
+	uint64_t free3                        : 1;
+	uint64_t free4                        : 1;
+	uint64_t free5                        : 1;
+	uint64_t free6                        : 1;
+	uint64_t free7                        : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_fpa_int_sum_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t q7_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q7_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q7_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q6_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q6_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q6_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q5_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q5_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q5_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q4_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q4_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q4_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q3_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q3_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q3_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q2_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q2_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+	uint64_t q2_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q1_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q1_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q1_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t q0_perr                      : 1;  /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+	uint64_t q0_coff                      : 1;  /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+	uint64_t q0_und                       : 1;  /**< Set when a Queue0 page count available goes
+                                                         negative. */
+	uint64_t fed1_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF1. */
+	uint64_t fed1_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF1. */
+	uint64_t fed0_dbe                     : 1;  /**< Set when a Double Bit Error is detected in FPF0. */
+	uint64_t fed0_sbe                     : 1;  /**< Set when a Single Bit Error is detected in FPF0. */
+#else
+	uint64_t fed0_sbe                     : 1;
+	uint64_t fed0_dbe                     : 1;
+	uint64_t fed1_sbe                     : 1;
+	uint64_t fed1_dbe                     : 1;
+	uint64_t q0_und                       : 1;
+	uint64_t q0_coff                      : 1;
+	uint64_t q0_perr                      : 1;
+	uint64_t q1_und                       : 1;
+	uint64_t q1_coff                      : 1;
+	uint64_t q1_perr                      : 1;
+	uint64_t q2_und                       : 1;
+	uint64_t q2_coff                      : 1;
+	uint64_t q2_perr                      : 1;
+	uint64_t q3_und                       : 1;
+	uint64_t q3_coff                      : 1;
+	uint64_t q3_perr                      : 1;
+	uint64_t q4_und                       : 1;
+	uint64_t q4_coff                      : 1;
+	uint64_t q4_perr                      : 1;
+	uint64_t q5_und                       : 1;
+	uint64_t q5_coff                      : 1;
+	uint64_t q5_perr                      : 1;
+	uint64_t q6_und                       : 1;
+	uint64_t q6_coff                      : 1;
+	uint64_t q6_perr                      : 1;
+	uint64_t q7_und                       : 1;
+	uint64_t q7_coff                      : 1;
+	uint64_t q7_perr                      : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn30xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn31xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn38xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn38xxp2;
+	struct cvmx_fpa_int_sum_cn30xx        cn50xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn52xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn52xxp1;
+	struct cvmx_fpa_int_sum_cn30xx        cn56xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn56xxp1;
+	struct cvmx_fpa_int_sum_cn30xx        cn58xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn58xxp1;
+	struct cvmx_fpa_int_sum_s             cn63xx;
+	struct cvmx_fpa_int_sum_cn30xx        cn63xxp1;
+};
+typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t;
+
+/**
+ * cvmx_fpa_packet_threshold
+ *
+ * FPA_PACKET_THRESHOLD = FPA's Packet Threshold
+ *
+ * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low pool count signal is sent to the
+ * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants
+ * to packets MAC with the exception of the PCIe MAC.
+ */
+union cvmx_fpa_packet_threshold
+{
+	uint64_t u64;
+	struct cvmx_fpa_packet_threshold_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t thresh                       : 32; /**< Packet Threshold. */
+#else
+	uint64_t thresh                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_fpa_packet_threshold_s    cn63xx;
+};
+typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t;
+
+/**
+ * cvmx_fpa_pool#_threshold
+ *
+ * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold
+ *
+ * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated
+ * or deallocated, set interrupt FPA_INT_SUM[POOLXTH].
+ */
+union cvmx_fpa_poolx_threshold
+{
+	uint64_t u64;
+	struct cvmx_fpa_poolx_threshold_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t thresh                       : 29; /**< The Threshold. */
+#else
+	uint64_t thresh                       : 29;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_fpa_poolx_threshold_s     cn63xx;
+};
+typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t;
+
+/**
+ * cvmx_fpa_que#_available
+ *
+ * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register
+ *
+ * The number of page pointers that are available in the FPA and local DRAM.
+ */
+union cvmx_fpa_quex_available
+{
+	uint64_t u64;
+	struct cvmx_fpa_quex_available_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t que_siz                      : 29; /**< The number of free pages available in this Queue.
+                                                         In PASS-1 this field was [25:0]. */
+#else
+	uint64_t que_siz                      : 29;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_fpa_quex_available_s      cn30xx;
+	struct cvmx_fpa_quex_available_s      cn31xx;
+	struct cvmx_fpa_quex_available_s      cn38xx;
+	struct cvmx_fpa_quex_available_s      cn38xxp2;
+	struct cvmx_fpa_quex_available_s      cn50xx;
+	struct cvmx_fpa_quex_available_s      cn52xx;
+	struct cvmx_fpa_quex_available_s      cn52xxp1;
+	struct cvmx_fpa_quex_available_s      cn56xx;
+	struct cvmx_fpa_quex_available_s      cn56xxp1;
+	struct cvmx_fpa_quex_available_s      cn58xx;
+	struct cvmx_fpa_quex_available_s      cn58xxp1;
+	struct cvmx_fpa_quex_available_s      cn63xx;
+	struct cvmx_fpa_quex_available_s      cn63xxp1;
+};
+typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t;
+
+/**
+ * cvmx_fpa_que#_page_index
+ *
+ * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index
+ *
+ * The present index page for queue 0 of the FPA, this is a PASS-2 register.
+ * This number reflects the number of pages of pointers that have been written to memory
+ * for this queue.
+ */
+union cvmx_fpa_quex_page_index
+{
+	uint64_t u64;
+	struct cvmx_fpa_quex_page_index_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t pg_num                       : 25; /**< Page number. */
+#else
+	uint64_t pg_num                       : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_fpa_quex_page_index_s     cn30xx;
+	struct cvmx_fpa_quex_page_index_s     cn31xx;
+	struct cvmx_fpa_quex_page_index_s     cn38xx;
+	struct cvmx_fpa_quex_page_index_s     cn38xxp2;
+	struct cvmx_fpa_quex_page_index_s     cn50xx;
+	struct cvmx_fpa_quex_page_index_s     cn52xx;
+	struct cvmx_fpa_quex_page_index_s     cn52xxp1;
+	struct cvmx_fpa_quex_page_index_s     cn56xx;
+	struct cvmx_fpa_quex_page_index_s     cn56xxp1;
+	struct cvmx_fpa_quex_page_index_s     cn58xx;
+	struct cvmx_fpa_quex_page_index_s     cn58xxp1;
+	struct cvmx_fpa_quex_page_index_s     cn63xx;
+	struct cvmx_fpa_quex_page_index_s     cn63xxp1;
+};
+typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t;
+
+/**
+ * cvmx_fpa_que_act
+ *
+ * FPA_QUE_ACT = FPA's Queue# Actual Page Index
+ *
+ * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register.
+ * This is latched on the first error and will not latch again unitl all errors are cleared.
+ */
+union cvmx_fpa_que_act
+{
+	uint64_t u64;
+	struct cvmx_fpa_que_act_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t act_que                      : 3;  /**< FPA-queue-number read from memory. */
+	uint64_t act_indx                     : 26; /**< Page number read from memory. */
+#else
+	uint64_t act_indx                     : 26;
+	uint64_t act_que                      : 3;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_fpa_que_act_s             cn30xx;
+	struct cvmx_fpa_que_act_s             cn31xx;
+	struct cvmx_fpa_que_act_s             cn38xx;
+	struct cvmx_fpa_que_act_s             cn38xxp2;
+	struct cvmx_fpa_que_act_s             cn50xx;
+	struct cvmx_fpa_que_act_s             cn52xx;
+	struct cvmx_fpa_que_act_s             cn52xxp1;
+	struct cvmx_fpa_que_act_s             cn56xx;
+	struct cvmx_fpa_que_act_s             cn56xxp1;
+	struct cvmx_fpa_que_act_s             cn58xx;
+	struct cvmx_fpa_que_act_s             cn58xxp1;
+	struct cvmx_fpa_que_act_s             cn63xx;
+	struct cvmx_fpa_que_act_s             cn63xxp1;
+};
+typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t;
+
+/**
+ * cvmx_fpa_que_exp
+ *
+ * FPA_QUE_EXP = FPA's Queue# Expected Page Index
+ *
+ * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register.
+ * This is latched on the first error and will not latch again unitl all errors are cleared.
+ */
+union cvmx_fpa_que_exp
+{
+	uint64_t u64;
+	struct cvmx_fpa_que_exp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t exp_que                      : 3;  /**< Expected fpa-queue-number read from memory. */
+	uint64_t exp_indx                     : 26; /**< Expected page number read from memory. */
+#else
+	uint64_t exp_indx                     : 26;
+	uint64_t exp_que                      : 3;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_fpa_que_exp_s             cn30xx;
+	struct cvmx_fpa_que_exp_s             cn31xx;
+	struct cvmx_fpa_que_exp_s             cn38xx;
+	struct cvmx_fpa_que_exp_s             cn38xxp2;
+	struct cvmx_fpa_que_exp_s             cn50xx;
+	struct cvmx_fpa_que_exp_s             cn52xx;
+	struct cvmx_fpa_que_exp_s             cn52xxp1;
+	struct cvmx_fpa_que_exp_s             cn56xx;
+	struct cvmx_fpa_que_exp_s             cn56xxp1;
+	struct cvmx_fpa_que_exp_s             cn58xx;
+	struct cvmx_fpa_que_exp_s             cn58xxp1;
+	struct cvmx_fpa_que_exp_s             cn63xx;
+	struct cvmx_fpa_que_exp_s             cn63xxp1;
+};
+typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t;
+
+/**
+ * cvmx_fpa_wart_ctl
+ *
+ * FPA_WART_CTL = FPA's WART Control
+ *
+ * Control and status for the WART block.
+ */
+union cvmx_fpa_wart_ctl
+{
+	uint64_t u64;
+	struct cvmx_fpa_wart_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ctl                          : 16; /**< Control information. */
+#else
+	uint64_t ctl                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_fpa_wart_ctl_s            cn30xx;
+	struct cvmx_fpa_wart_ctl_s            cn31xx;
+	struct cvmx_fpa_wart_ctl_s            cn38xx;
+	struct cvmx_fpa_wart_ctl_s            cn38xxp2;
+	struct cvmx_fpa_wart_ctl_s            cn50xx;
+	struct cvmx_fpa_wart_ctl_s            cn52xx;
+	struct cvmx_fpa_wart_ctl_s            cn52xxp1;
+	struct cvmx_fpa_wart_ctl_s            cn56xx;
+	struct cvmx_fpa_wart_ctl_s            cn56xxp1;
+	struct cvmx_fpa_wart_ctl_s            cn58xx;
+	struct cvmx_fpa_wart_ctl_s            cn58xxp1;
+};
+typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t;
+
+/**
+ * cvmx_fpa_wart_status
+ *
+ * FPA_WART_STATUS = FPA's WART Status
+ *
+ * Control and status for the WART block.
+ */
+union cvmx_fpa_wart_status
+{
+	uint64_t u64;
+	struct cvmx_fpa_wart_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t status                       : 32; /**< Status information. */
+#else
+	uint64_t status                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_fpa_wart_status_s         cn30xx;
+	struct cvmx_fpa_wart_status_s         cn31xx;
+	struct cvmx_fpa_wart_status_s         cn38xx;
+	struct cvmx_fpa_wart_status_s         cn38xxp2;
+	struct cvmx_fpa_wart_status_s         cn50xx;
+	struct cvmx_fpa_wart_status_s         cn52xx;
+	struct cvmx_fpa_wart_status_s         cn52xxp1;
+	struct cvmx_fpa_wart_status_s         cn56xx;
+	struct cvmx_fpa_wart_status_s         cn56xxp1;
+	struct cvmx_fpa_wart_status_s         cn58xx;
+	struct cvmx_fpa_wart_status_s         cn58xxp1;
+};
+typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t;
+
+/**
+ * cvmx_fpa_wqe_threshold
+ *
+ * FPA_WQE_THRESHOLD = FPA's WQE Threshold
+ *
+ * When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of IPD_WQE_FPA_QUEUE) is Less than the value of this
+ * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the
+ * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC.
+ */
+union cvmx_fpa_wqe_threshold
+{
+	uint64_t u64;
+	struct cvmx_fpa_wqe_threshold_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t thresh                       : 32; /**< WQE Threshold. */
+#else
+	uint64_t thresh                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_fpa_wqe_threshold_s       cn63xx;
+};
+typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa.c b/sys/contrib/octeon-sdk/cvmx-fpa.c
index a14e992..22afc79 100644
--- a/sys/contrib/octeon-sdk/cvmx-fpa.c
+++ b/sys/contrib/octeon-sdk/cvmx-fpa.c
@@ -1,52 +1,49 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
  * Support library for the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -84,24 +81,24 @@ int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
     if (!buffer)
     {
         cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
-        return(-1);
+        return -1;
     }
     if (pool >= CVMX_FPA_NUM_POOLS)
     {
         cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
-        return(-1);
+        return -1;
     }
 
     if (block_size < CVMX_FPA_MIN_BLOCK_SIZE)
     {
         cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
-        return(-1);
+        return -1;
     }
 
     if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT-1)) != 0)
     {
         cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
-        return(-1);
+        return -1;
     }
 
     cvmx_fpa_pool_info[pool].name = name;
@@ -115,78 +112,96 @@ int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
         cvmx_fpa_free(ptr, pool, 0);
         ptr += block_size;
     }
-    return(0);
+    return 0;
 }
 
 /**
  * Shutdown a Memory pool and validate that it had all of
- * the buffers originally placed in it.
+ * the buffers originally placed in it. This should only be
+ * called by one processor after all hardware has finished
+ * using the pool. Most like you will want to have called
+ * cvmx_helper_shutdown_packet_io_global() before this
+ * function to make sure all FPA buffers are out of the packet
+ * IO hardware.
  *
  * @param pool   Pool to shutdown
+ *
  * @return Zero on success
  *         - Positive is count of missing buffers
  *         - Negative is too many buffers or corrupted pointers
  */
 uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
 {
-    uint64_t errors = 0;
-    uint64_t count  = 0;
+    int errors = 0;
+    int count  = 0;
+    int expected_count = cvmx_fpa_pool_info[pool].starting_element_count;
     uint64_t base   = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
-    uint64_t finish = base + cvmx_fpa_pool_info[pool].size * cvmx_fpa_pool_info[pool].starting_element_count;
-    void *ptr;
-    uint64_t address;
+    uint64_t finish = base + cvmx_fpa_pool_info[pool].size * expected_count;
 
     count = 0;
-    do
+    while (1)
     {
-        ptr = cvmx_fpa_alloc(pool);
-        if (ptr)
-            address = cvmx_ptr_to_phys(ptr);
+        uint64_t address;
+        void *ptr = cvmx_fpa_alloc(pool);
+        if (!ptr)
+            break;
+
+        address = cvmx_ptr_to_phys(ptr);
+        if ((address >= base) && (address < finish) &&
+            (((address - base) % cvmx_fpa_pool_info[pool].size) == 0))
+        {
+            count++;
+        }
         else
-            address = 0;
-        if (address)
         {
-            if ((address >= base) && (address < finish) &&
-                (((address - base) % cvmx_fpa_pool_info[pool].size) == 0))
-            {
-                count++;
-            }
-            else
-            {
-                cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
-                       (unsigned long long)address, cvmx_fpa_pool_info[pool].name, (int)pool);
-                errors++;
-            }
+            cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
+                   (unsigned long long)address, cvmx_fpa_pool_info[pool].name, (int)pool);
+            errors++;
         }
-    } while (address);
+    }
 
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
-    if (pool == 0)
-	cvmx_ipd_free_ptr();
-#endif
+    if (count < expected_count)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) missing %d buffers\n",
+               cvmx_fpa_pool_info[pool].name, (int)pool, expected_count - count);
+    }
+    else if (count > expected_count)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) had %d duplicate buffers\n",
+               cvmx_fpa_pool_info[pool].name, (int)pool, count - expected_count);
+    }
 
     if (errors)
     {
-        cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
-               cvmx_fpa_pool_info[pool].name, (int)pool, (unsigned long long)base, (unsigned long long)finish, (unsigned long long)cvmx_fpa_pool_info[pool].size);
+        cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%x\n",
+               cvmx_fpa_pool_info[pool].name, (int)pool, (unsigned long long)base, (unsigned long long)finish, (int)cvmx_fpa_pool_info[pool].size);
         return -errors;
     }
     else
-        return 0;
+        return expected_count - count;
 }
 
 uint64_t cvmx_fpa_get_block_size(uint64_t pool)
 {
     switch (pool)
     {
-        case 0: return(CVMX_FPA_POOL_0_SIZE);
-        case 1: return(CVMX_FPA_POOL_1_SIZE);
-        case 2: return(CVMX_FPA_POOL_2_SIZE);
-        case 3: return(CVMX_FPA_POOL_3_SIZE);
-        case 4: return(CVMX_FPA_POOL_4_SIZE);
-        case 5: return(CVMX_FPA_POOL_5_SIZE);
-        case 6: return(CVMX_FPA_POOL_6_SIZE);
-        case 7: return(CVMX_FPA_POOL_7_SIZE);
-        default: return(0);
+        case 0:
+	    return CVMX_FPA_POOL_0_SIZE;
+        case 1:
+	    return CVMX_FPA_POOL_1_SIZE;
+        case 2:
+	    return CVMX_FPA_POOL_2_SIZE;
+        case 3:
+	    return CVMX_FPA_POOL_3_SIZE;
+        case 4:
+	    return CVMX_FPA_POOL_4_SIZE;
+        case 5:
+	    return CVMX_FPA_POOL_5_SIZE;
+        case 6:
+	    return CVMX_FPA_POOL_6_SIZE;
+        case 7:
+	    return CVMX_FPA_POOL_7_SIZE;
+        default:
+	    return 0;
     }
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-fpa.h b/sys/contrib/octeon-sdk/cvmx-fpa.h
index b172116..88de805 100644
--- a/sys/contrib/octeon-sdk/cvmx-fpa.h
+++ b/sys/contrib/octeon-sdk/cvmx-fpa.h
@@ -1,58 +1,61 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
  * Interface to the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 50048 $<hr>
  *
  */
 
 #ifndef __CVMX_FPA_H__
 #define __CVMX_FPA_H__
 
+#include "cvmx-scratch.h"
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-fpa-defs.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -92,7 +95,7 @@ typedef struct
  */
 extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-fpa-defs.h */
 
 /**
  * Return the name of the pool
@@ -131,8 +134,6 @@ static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
             ((char*)ptr < ((char*)(cvmx_fpa_pool_info[pool].base)) + cvmx_fpa_pool_info[pool].size * cvmx_fpa_pool_info[pool].starting_element_count));
 }
 
-
-
 /**
  * Enable the FPA for use. Must be performed after any CSR
  * configuration but before any other FPA functions.
@@ -147,28 +148,11 @@ static inline void cvmx_fpa_enable(void)
         cvmx_dprintf("Warning: Enabling FPA when FPA already enabled.\n");
     }
 
-    /* Do runtime check as we allow pass1 compiled code to run on pass2 chips */
-    if (cvmx_octeon_is_pass1())
-    {
-        cvmx_fpa_fpf_marks_t marks;
-        int i;
-        for (i=1; i<8; i++)
-        {
-            marks.u64 = cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i-1)*8ull);
-            marks.s.fpf_wr = 0xe0;
-            cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i-1)*8ull, marks.u64);
-        }
-
-        /* Enforce a 10 cycle delay between config and enable */
-        cvmx_wait(10);
-    }
-
-    status.u64 = 0; /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
+    status.u64 = 0;
     status.s.enb = 1;
     cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
 }
 
-
 /**
  * Get a new block from the FPA
  *
@@ -177,17 +161,28 @@ static inline void cvmx_fpa_enable(void)
  */
 static inline void *cvmx_fpa_alloc(uint64_t pool)
 {
-    uint64_t address = cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool)));
-    if (address)
-        return cvmx_phys_to_ptr(address);
-    else
-        return NULL;
+    uint64_t address;
+
+    for (;;) {
+        address = cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool)));
+        if (cvmx_likely(address)) {
+            return cvmx_phys_to_ptr(address);
+        } else {
+	   /* If pointers are available, continuously retry.  */
+           if (cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)) > 0)
+               cvmx_wait(50);
+           else
+               return NULL;
+	}
+    }
 }
 
-
 /**
  * Asynchronously get a new block from the FPA
  *
+ * The result of cvmx_fpa_async_alloc() may be retrieved using
+ * cvmx_fpa_async_alloc_finish().
+ *
  * @param scr_addr Local scratch address to put response in.  This is a byte address,
  *                  but must be 8 byte aligned.
  * @param pool      Pool to get the block from
@@ -206,6 +201,29 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
    cvmx_send_single(data.u64);
 }
 
+/**
+ * Retrieve the result of cvmx_fpa_async_alloc
+ *
+ * @param scr_addr The Local scratch address.  Must be the same value
+ * passed to cvmx_fpa_async_alloc().
+ *
+ * @param pool Pool the block came from.  Must be the same value
+ * passed to cvmx_fpa_async_alloc.
+ *
+ * @return Pointer to the block or NULL on failure
+ */
+static inline void *cvmx_fpa_async_alloc_finish(uint64_t scr_addr, uint64_t pool)
+{
+    uint64_t address;
+
+    CVMX_SYNCIOBDMA;
+
+    address = cvmx_scratch_read64(scr_addr);
+    if (cvmx_likely(address))
+        return cvmx_phys_to_ptr(address);
+    else
+        return cvmx_fpa_alloc(pool);
+}
 
 /**
  * Free a block allocated with a FPA pool.
@@ -248,7 +266,6 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, uint64_t num_cache_li
     cvmx_write_io(newptr.u64, num_cache_lines);
 }
 
-
 /**
  * Setup a FPA pool to control a new block of memory.
  * This can only be called once per pool. Make sure proper
@@ -269,21 +286,23 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, uint64_t num_cache_li
 extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
                                 uint64_t block_size, uint64_t num_blocks);
 
-
 /**
  * Shutdown a Memory pool and validate that it had all of
  * the buffers originally placed in it. This should only be
  * called by one processor after all hardware has finished
- * using the pool.
+ * using the pool. Most like you will want to have called
+ * cvmx_helper_shutdown_packet_io_global() before this
+ * function to make sure all FPA buffers are out of the packet
+ * IO hardware.
  *
  * @param pool   Pool to shutdown
+ *
  * @return Zero on success
  *         - Positive is count of missing buffers
  *         - Negative is too many buffers or corrupted pointers
  */
 extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
 
-
 /**
  * Get the size of blocks controlled by the pool
  * This is resolved to a constant at compile time.
@@ -297,4 +316,4 @@ uint64_t cvmx_fpa_get_block_size(uint64_t pool);
 }
 #endif
 
-#endif //  __CVM_FPA_H__
+#endif /*  __CVM_FPA_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-gmx.h b/sys/contrib/octeon-sdk/cvmx-gmx.h
index e2e4d1c..e9ad751 100644
--- a/sys/contrib/octeon-sdk/cvmx-gmx.h
+++ b/sys/contrib/octeon-sdk/cvmx-gmx.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the GMX hardware.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_GMX_H__
@@ -56,7 +58,7 @@
 extern "C" {
 #endif
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-gmx-defs.h */
 
 /**
  * Disables the sending of flow control (pause) frames on the specified
diff --git a/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h b/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
new file mode 100644
index 0000000..e7e5cea
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
@@ -0,0 +1,8057 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-gmxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon gmxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_GMXX_TYPEDEFS_H__
+#define __CVMX_GMXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_BAD_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_BIST(block_id) (CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_CLK_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_HG2_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_INF_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_NXA_ADR(block_id) (CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_PRTX_CFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_DECISION(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_IFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_INT_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_INT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_JABBER(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_GMXX_RX_BP_ONX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_HG2_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_PRT_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007E8ull);
+}
+#else
+#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_RX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_SMACX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_SOFT_BIST(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080007E8ull);
+}
+#else
+#define CVMX_GMXX_SOFT_BIST(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_STAT_BP(block_id) (CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_APPEND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_BURST(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_SLOT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT6(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT7(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT8(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STAT9(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+}
+#else
+#define CVMX_GMXX_TXX_THRESH(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
+}
+#else
+#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) (CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_CORRUPT(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_HG2_REG1(block_id) (CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_HG2_REG2(block_id) (CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_IFG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_JAM(block_id) (CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_LFSR(block_id) (CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_OVR_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_TX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_gmx#_bad_reg
+ *
+ * GMX_BAD_REG = A collection of things that have gone very, very wrong
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
+ *
+ */
+union cvmx_gmxx_bad_reg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_bad_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow
+                                                         The common FIFO to SGMII and XAUI had an overflow
+                                                         TX Stats are corrupted */
+	uint64_t loststat                     : 4;  /**< TX Statistics data was over-written
+                                                         In SGMII, one bit per port
+                                                         In XAUI, only port0 is used
+                                                         TX Stats are corrupted */
+	uint64_t reserved_18_21               : 4;
+	uint64_t out_ovr                      : 16; /**< Outbound data FIFO overflow (per port) */
+	uint64_t ncb_ovr                      : 1;  /**< Outbound NCB FIFO Overflow */
+	uint64_t out_col                      : 1;  /**< Outbound collision occured between PKO and NCB */
+#else
+	uint64_t out_col                      : 1;
+	uint64_t ncb_ovr                      : 1;
+	uint64_t out_ovr                      : 16;
+	uint64_t reserved_18_21               : 4;
+	uint64_t loststat                     : 4;
+	uint64_t statovr                      : 1;
+	uint64_t inb_nxa                      : 4;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_gmxx_bad_reg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow */
+	uint64_t reserved_25_25               : 1;
+	uint64_t loststat                     : 3;  /**< TX Statistics data was over-written (per RGM port)
+                                                         TX Stats are corrupted */
+	uint64_t reserved_5_21                : 17;
+	uint64_t out_ovr                      : 3;  /**< Outbound data FIFO overflow (per port) */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t out_ovr                      : 3;
+	uint64_t reserved_5_21                : 17;
+	uint64_t loststat                     : 3;
+	uint64_t reserved_25_25               : 1;
+	uint64_t statovr                      : 1;
+	uint64_t inb_nxa                      : 4;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_bad_reg_cn30xx       cn31xx;
+	struct cvmx_gmxx_bad_reg_s            cn38xx;
+	struct cvmx_gmxx_bad_reg_s            cn38xxp2;
+	struct cvmx_gmxx_bad_reg_cn30xx       cn50xx;
+	struct cvmx_gmxx_bad_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t inb_nxa                      : 4;  /**< Inbound port > GMX_RX_PRTS */
+	uint64_t statovr                      : 1;  /**< TX Statistics overflow
+                                                         The common FIFO to SGMII and XAUI had an overflow
+                                                         TX Stats are corrupted */
+	uint64_t loststat                     : 4;  /**< TX Statistics data was over-written
+                                                         In SGMII, one bit per port
+                                                         In XAUI, only port0 is used
+                                                         TX Stats are corrupted */
+	uint64_t reserved_6_21                : 16;
+	uint64_t out_ovr                      : 4;  /**< Outbound data FIFO overflow (per port) */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t out_ovr                      : 4;
+	uint64_t reserved_6_21                : 16;
+	uint64_t loststat                     : 4;
+	uint64_t statovr                      : 1;
+	uint64_t inb_nxa                      : 4;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn52xxp1;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn56xx;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn56xxp1;
+	struct cvmx_gmxx_bad_reg_s            cn58xx;
+	struct cvmx_gmxx_bad_reg_s            cn58xxp1;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn63xx;
+	struct cvmx_gmxx_bad_reg_cn52xx       cn63xxp1;
+};
+typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
+
+/**
+ * cvmx_gmx#_bist
+ *
+ * GMX_BIST = GMX BIST Results
+ *
+ */
+union cvmx_gmxx_bist
+{
+	uint64_t u64;
+	struct cvmx_gmxx_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t status                       : 25; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.inb.fif_bnk_ext0
+                                                         - 5: gmx#.inb.fif_bnk_ext1
+                                                         - 6: gmx#.inb.fif_bnk_ext2
+                                                         - 7: gmx#.inb.fif_bnk_ext3
+                                                         - 8: gmx#.outb.fif.fif_bnk0
+                                                         - 9: gmx#.outb.fif.fif_bnk1
+                                                         - 10: gmx#.outb.fif.fif_bnk2
+                                                         - 11: gmx#.outb.fif.fif_bnk3
+                                                         - 12: gmx#.outb.fif.fif_bnk_ext0
+                                                         - 13: gmx#.outb.fif.fif_bnk_ext1
+                                                         - 14: gmx#.outb.fif.fif_bnk_ext2
+                                                         - 15: gmx#.outb.fif.fif_bnk_ext3
+                                                         - 16: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 17: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 18: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 19: gmx#.csr.gmi3.srf8x64m1_bist
+                                                         - 20: gmx#.csr.drf20x32m2_bist
+                                                         - 21: gmx#.csr.drf20x48m2_bist
+                                                         - 22: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 23: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 24: xgmii.tx.drf16x38m1_async_bist */
+#else
+	uint64_t status                       : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_gmxx_bist_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t status                       : 10; /**< BIST Results.
+                                                          HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.dpr512x78m4_bist
+                                                         - 1: gmx#.outb.fif.dpr512x71m4_bist
+                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 3: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 4: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 5: 0
+                                                         - 6: gmx#.csr.drf20x80m1_bist
+                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 9: 0 */
+#else
+	uint64_t status                       : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_bist_cn30xx          cn31xx;
+	struct cvmx_gmxx_bist_cn30xx          cn38xx;
+	struct cvmx_gmxx_bist_cn30xx          cn38xxp2;
+	struct cvmx_gmxx_bist_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t status                       : 12; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails */
+#else
+	uint64_t status                       : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn50xx;
+	struct cvmx_gmxx_bist_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t status                       : 16; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.outb.fif.fif_bnk0
+                                                         - 5: gmx#.outb.fif.fif_bnk1
+                                                         - 6: gmx#.outb.fif.fif_bnk2
+                                                         - 7: gmx#.outb.fif.fif_bnk3
+                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
+                                                         - 12: gmx#.csr.drf20x80m1_bist
+                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 15: xgmii.tx.drf16x38m1_async_bist */
+#else
+	uint64_t status                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_bist_cn52xx          cn52xxp1;
+	struct cvmx_gmxx_bist_cn52xx          cn56xx;
+	struct cvmx_gmxx_bist_cn52xx          cn56xxp1;
+	struct cvmx_gmxx_bist_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t status                       : 17; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.outb.fif.fif_bnk0
+                                                         - 5: gmx#.outb.fif.fif_bnk1
+                                                         - 6: gmx#.outb.fif.fif_bnk2
+                                                         - 7: gmx#.outb.fif.fif_bnk3
+                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
+                                                         - 12: gmx#.csr.drf20x80m1_bist
+                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 15: gmx#.outb.ncb.drf16x76m1_bist
+                                                         - 16: gmx#.outb.fif.srf32x16m2_bist */
+#else
+	uint64_t status                       : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn58xx;
+	struct cvmx_gmxx_bist_cn58xx          cn58xxp1;
+	struct cvmx_gmxx_bist_s               cn63xx;
+	struct cvmx_gmxx_bist_s               cn63xxp1;
+};
+typedef union cvmx_gmxx_bist cvmx_gmxx_bist_t;
+
+/**
+ * cvmx_gmx#_clk_en
+ *
+ * DO NOT DOCUMENT THIS REGISTER - IT IS NOT OFFICIAL
+ *
+ */
+union cvmx_gmxx_clk_en
+{
+	uint64_t u64;
+	struct cvmx_gmxx_clk_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t clk_en                       : 1;  /**< Force the clock enables on */
+#else
+	uint64_t clk_en                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_clk_en_s             cn52xx;
+	struct cvmx_gmxx_clk_en_s             cn52xxp1;
+	struct cvmx_gmxx_clk_en_s             cn56xx;
+	struct cvmx_gmxx_clk_en_s             cn56xxp1;
+	struct cvmx_gmxx_clk_en_s             cn63xx;
+	struct cvmx_gmxx_clk_en_s             cn63xxp1;
+};
+typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
+
+/**
+ * cvmx_gmx#_hg2_control
+ *
+ * Notes:
+ * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However
+ * setting just the TX or RX bit will result in only the HG2 message transmit or the receive
+ * capability.
+ * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received
+ * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages
+ * are disabled.
+ *
+ * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN
+ * are set.
+ *
+ * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN
+ * are set.
+ *
+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when
+ * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1
+ * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
+ * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
+ */
+union cvmx_gmxx_hg2_control
+{
+	uint64_t u64;
+	struct cvmx_gmxx_hg2_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t hg2tx_en                     : 1;  /**< Enable Transmission of HG2 phys and logl messages
+                                                         When set, also disables HW auto-generated (802.3
+                                                         and CBFC) pause frames. (OCTEON cannot generate
+                                                         proper 802.3 or CBFC pause frames in HiGig2 mode.) */
+	uint64_t hg2rx_en                     : 1;  /**< Enable extraction and processing of HG2 message
+                                                         packet from RX flow. Physical logical pause info
+                                                         is used to pause physical link, back pressure PKO
+                                                         HG2RX_EN must be set when HiGig2 messages are
+                                                         present in the receive stream. */
+	uint64_t phys_en                      : 1;  /**< 1 bit physical link pause enable for recevied
+                                                         HiGig2 physical pause message */
+	uint64_t logl_en                      : 16; /**< 16 bit xof enables for recevied HiGig2 messages
+                                                         or CBFC packets */
+#else
+	uint64_t logl_en                      : 16;
+	uint64_t phys_en                      : 1;
+	uint64_t hg2rx_en                     : 1;
+	uint64_t hg2tx_en                     : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_gmxx_hg2_control_s        cn52xx;
+	struct cvmx_gmxx_hg2_control_s        cn52xxp1;
+	struct cvmx_gmxx_hg2_control_s        cn56xx;
+	struct cvmx_gmxx_hg2_control_s        cn63xx;
+	struct cvmx_gmxx_hg2_control_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
+
+/**
+ * cvmx_gmx#_inf_mode
+ *
+ * GMX_INF_MODE = Interface Mode
+ *
+ */
+union cvmx_gmxx_inf_mode
+{
+	uint64_t u64;
+	struct cvmx_gmxx_inf_mode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t speed                        : 4;  /**< Interface Speed */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t mode                         : 2;  /**< Interface Electrical Operating Mode
+                                                         - 0: SGMII (v1.8)
+                                                         - 1: XAUI (IEEE 802.3-2005) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t p0mii                        : 1;  /**< Port 0 Interface Mode
+                                                         - 0: Port 0 is RGMII
+                                                         - 1: Port 0 is MII */
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t p0mii                        : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t mode                         : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t speed                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_gmxx_inf_mode_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t p0mii                        : 1;  /**< Port 0 Interface Mode
+                                                         - 0: Port 0 is RGMII
+                                                         - 1: Port 0 is MII */
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Port 1/2 Interface Mode
+                                                         - 0: Ports 1 and 2 are RGMII
+                                                         - 1: Port  1 is GMII/MII, Port 2 is unused
+                                                             GMII/MII is selected by GMX_PRT1_CFG[SPEED] */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t p0mii                        : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_inf_mode_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Mode
+                                                         - 0: All three ports are RGMII ports
+                                                         - 1: prt0 is RGMII, prt1 is GMII, and prt2 is unused */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn31xx;
+	struct cvmx_gmxx_inf_mode_cn31xx      cn38xx;
+	struct cvmx_gmxx_inf_mode_cn31xx      cn38xxp2;
+	struct cvmx_gmxx_inf_mode_cn30xx      cn50xx;
+	struct cvmx_gmxx_inf_mode_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t speed                        : 2;  /**< Interface Speed
+                                                         - 0: 1.250GHz
+                                                         - 1: 2.500GHz
+                                                         - 2: 3.125GHz
+                                                         - 3: 3.750GHz */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t mode                         : 2;  /**< Interface Electrical Operating Mode
+                                                         - 0: Disabled (PCIe)
+                                                         - 1: XAUI (IEEE 802.3-2005)
+                                                         - 2: SGMII (v1.8)
+                                                         - 3: PICMG3.1 */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t mode                         : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t speed                        : 2;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_inf_mode_cn52xx      cn52xxp1;
+	struct cvmx_gmxx_inf_mode_cn52xx      cn56xx;
+	struct cvmx_gmxx_inf_mode_cn52xx      cn56xxp1;
+	struct cvmx_gmxx_inf_mode_cn31xx      cn58xx;
+	struct cvmx_gmxx_inf_mode_cn31xx      cn58xxp1;
+	struct cvmx_gmxx_inf_mode_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t speed                        : 4;  /**< Interface Speed */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t mode                         : 1;  /**< Interface Electrical Operating Mode
+                                                         - 0: SGMII (v1.8)
+                                                         - 1: XAUI (IEEE 802.3-2005) */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t en                           : 1;  /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+	uint64_t type                         : 1;  /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI */
+#else
+	uint64_t type                         : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t mode                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t speed                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_inf_mode_cn63xx      cn63xxp1;
+};
+typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
+
+/**
+ * cvmx_gmx#_nxa_adr
+ *
+ * GMX_NXA_ADR = NXA Port Address
+ *
+ */
+union cvmx_gmxx_nxa_adr
+{
+	uint64_t u64;
+	struct cvmx_gmxx_nxa_adr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t prt                          : 6;  /**< Logged address for NXA exceptions
+                                                         The logged address will be from the first
+                                                         exception that caused the problem.  NCB has
+                                                         higher priority than PKO and will win.
+                                                         (only PRT[3:0]) */
+#else
+	uint64_t prt                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_gmxx_nxa_adr_s            cn30xx;
+	struct cvmx_gmxx_nxa_adr_s            cn31xx;
+	struct cvmx_gmxx_nxa_adr_s            cn38xx;
+	struct cvmx_gmxx_nxa_adr_s            cn38xxp2;
+	struct cvmx_gmxx_nxa_adr_s            cn50xx;
+	struct cvmx_gmxx_nxa_adr_s            cn52xx;
+	struct cvmx_gmxx_nxa_adr_s            cn52xxp1;
+	struct cvmx_gmxx_nxa_adr_s            cn56xx;
+	struct cvmx_gmxx_nxa_adr_s            cn56xxp1;
+	struct cvmx_gmxx_nxa_adr_s            cn58xx;
+	struct cvmx_gmxx_nxa_adr_s            cn58xxp1;
+	struct cvmx_gmxx_nxa_adr_s            cn63xx;
+	struct cvmx_gmxx_nxa_adr_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
+
+/**
+ * cvmx_gmx#_prt#_cbfc_ctl
+ *
+ * ** HG2 message CSRs end
+ *
+ *
+ * Notes:
+ * XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>)
+ *
+ */
+union cvmx_gmxx_prtx_cbfc_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t phys_en                      : 16; /**< Determines which ports will have physical
+                                                         backpressure pause packets.
+                                                         The value pplaced in the Class Enable Vector
+                                                         field of the CBFC pause packet will be
+                                                         PHYS_EN | LOGL_EN */
+	uint64_t logl_en                      : 16; /**< Determines which ports will have logical
+                                                         backpressure pause packets.
+                                                         The value pplaced in the Class Enable Vector
+                                                         field of the CBFC pause packet will be
+                                                         PHYS_EN | LOGL_EN */
+	uint64_t phys_bp                      : 16; /**< When RX_EN is set and the HW is backpressuring any
+                                                         ports (from either CBFC pause packets or the
+                                                         GMX_TX_OVR_BP[TX_PRT_BP] register) and all ports
+                                                         indiciated by PHYS_BP are backpressured, simulate
+                                                         physical backpressure by defering all packets on
+                                                         the transmitter. */
+	uint64_t reserved_4_15                : 12;
+	uint64_t bck_en                       : 1;  /**< Forward CBFC Pause information to BP block */
+	uint64_t drp_en                       : 1;  /**< Drop Control CBFC Pause Frames */
+	uint64_t tx_en                        : 1;  /**< When set, allow for CBFC Pause Packets
+                                                         Must be clear in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+	uint64_t rx_en                        : 1;  /**< When set, allow for CBFC Pause Packets
+                                                         Must be clear in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+	uint64_t rx_en                        : 1;
+	uint64_t tx_en                        : 1;
+	uint64_t drp_en                       : 1;
+	uint64_t bck_en                       : 1;
+	uint64_t reserved_4_15                : 12;
+	uint64_t phys_bp                      : 16;
+	uint64_t logl_en                      : 16;
+	uint64_t phys_en                      : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn52xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn56xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn63xx;
+	struct cvmx_gmxx_prtx_cbfc_ctl_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
+
+/**
+ * cvmx_gmx#_prt#_cfg
+ *
+ * GMX_PRT_CFG = Port description
+ *
+ */
+union cvmx_gmxx_prtx_cfg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_prtx_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t tx_idle                      : 1;  /**< TX Machine is idle */
+	uint64_t rx_idle                      : 1;  /**< RX Machine is idle */
+	uint64_t reserved_9_11                : 3;
+	uint64_t speed_msb                    : 1;  /**< Link Speed MSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation)
+                                                         (SGMII/1000Base-X only) */
+	uint64_t duplex                       : 1;  /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex
+                                                         (SGMII/1000Base-X only) */
+	uint64_t speed                        : 1;  /**< Link Speed LSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved
+                                                         (SGMII/1000Base-X only) */
+	uint64_t en                           : 1;  /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+	uint64_t en                           : 1;
+	uint64_t speed                        : 1;
+	uint64_t duplex                       : 1;
+	uint64_t slottime                     : 1;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t speed_msb                    : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rx_idle                      : 1;
+	uint64_t tx_idle                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_gmxx_prtx_cfg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t slottime                     : 1;  /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation) */
+	uint64_t duplex                       : 1;  /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+	uint64_t speed                        : 1;  /**< Link Speed
+                                                         0 = 10/100Mbs operation
+                                                             (in RGMII mode, GMX_TX_CLK[CLK_CNT] >  1)
+                                                             (in MII   mode, GMX_TX_CLK[CLK_CNT] == 1)
+                                                         1 = 1000Mbs operation */
+	uint64_t en                           : 1;  /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+	uint64_t en                           : 1;
+	uint64_t speed                        : 1;
+	uint64_t duplex                       : 1;
+	uint64_t slottime                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn31xx;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn38xx;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn38xxp2;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn50xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn52xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn52xxp1;
+	struct cvmx_gmxx_prtx_cfg_s           cn56xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn56xxp1;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn58xx;
+	struct cvmx_gmxx_prtx_cfg_cn30xx      cn58xxp1;
+	struct cvmx_gmxx_prtx_cfg_s           cn63xx;
+	struct cvmx_gmxx_prtx_cfg_s           cn63xxp1;
+};
+typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam0
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam0
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam0_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam1
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam1
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam1_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam2
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam2
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam2_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam3
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam3
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam3_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam4
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam4
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam4_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam5
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam5
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t adr                          : 64; /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses.
+                                                         In XAUI mode, all ports will reflect the data
+                                                         written to port0. */
+#else
+	uint64_t adr                          : 64;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam5_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_cam_en
+ *
+ * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam_en
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_cam_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t en                           : 8;  /**< CAM Entry Enables */
+#else
+	uint64_t en                           : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn30xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn31xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn38xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn50xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn52xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn56xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn58xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn63xx;
+	struct cvmx_gmxx_rxx_adr_cam_en_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
+
+/**
+ * cvmx_gmx#_rx#_adr_ctl
+ *
+ * GMX_RX_ADR_CTL = Address Filtering Control
+ *
+ *
+ * Notes:
+ * * ALGORITHM
+ * Here is some pseudo code that represents the address filter behavior.
+ *
+ *    @verbatim
+ *    bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ *      ASSERT(prt >= 0 && prt <= 3);
+ *      if (is_bcst(dmac))                               // broadcast accept
+ *        return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
+ *        return REJECT;
+ *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
+ *        return ACCEPT;
+ *
+ *      cam_hit = 0;
+ *
+ *      for (i=0; i<8; i++) [
+ *        if (GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
+ *          continue;
+ *        uint48 unswizzled_mac_adr = 0x0;
+ *        for (j=5; j>=0; j--) [
+ *           unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
+ *        ]
+ *        if (unswizzled_mac_adr == dmac) [
+ *          cam_hit = 1;
+ *          break;
+ *        ]
+ *      ]
+ *
+ *      if (cam_hit)
+ *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ *      else
+ *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
+ *    ]
+ *    @endverbatim
+ */
+union cvmx_gmxx_rxx_adr_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_adr_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t cam_mode                     : 1;  /**< Allow or deny DMAC address filter
+                                                         0 = reject the packet on DMAC address match
+                                                         1 = accept the packet on DMAC address match */
+	uint64_t mcst                         : 2;  /**< Multicast Mode
+                                                         0 = Use the Address Filter CAM
+                                                         1 = Force reject all multicast packets
+                                                         2 = Force accept all multicast packets
+                                                         3 = Reserved */
+	uint64_t bcst                         : 1;  /**< Accept All Broadcast Packets */
+#else
+	uint64_t bcst                         : 1;
+	uint64_t mcst                         : 2;
+	uint64_t cam_mode                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn30xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn31xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn38xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn38xxp2;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn50xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn52xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn52xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn56xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn56xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn58xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn58xxp1;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn63xx;
+	struct cvmx_gmxx_rxx_adr_ctl_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
+
+/**
+ * cvmx_gmx#_rx#_decision
+ *
+ * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
+ *
+ *
+ * Notes:
+ * As each byte in a packet is received by GMX, the L2 byte count is compared
+ * against the GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
+ * from the beginning of the L2 header (DMAC).  In normal operation, the L2
+ * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any
+ * optional UDD skip data (GMX_RX_UDD_SKP[LEN]).
+ *
+ * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
+ * packet and would require UDD skip length to account for them.
+ *
+ *                                                 L2 Size
+ * Port Mode             <GMX_RX_DECISION bytes (default=24)       >=GMX_RX_DECISION bytes (default=24)
+ *
+ * Full Duplex           accept packet                             apply filters
+ *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
+ *
+ * Half Duplex           drop packet                               apply filters
+ *                       packet is unconditionally dropped         accept packet based on DMAC
+ *
+ * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
+ */
+union cvmx_gmxx_rxx_decision
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_decision_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t cnt                          : 5;  /**< The byte count to decide when to accept or filter
+                                                         a packet. */
+#else
+	uint64_t cnt                          : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_decision_s       cn30xx;
+	struct cvmx_gmxx_rxx_decision_s       cn31xx;
+	struct cvmx_gmxx_rxx_decision_s       cn38xx;
+	struct cvmx_gmxx_rxx_decision_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_decision_s       cn50xx;
+	struct cvmx_gmxx_rxx_decision_s       cn52xx;
+	struct cvmx_gmxx_rxx_decision_s       cn52xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cn56xx;
+	struct cvmx_gmxx_rxx_decision_s       cn56xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cn58xx;
+	struct cvmx_gmxx_rxx_decision_s       cn58xxp1;
+	struct cvmx_gmxx_rxx_decision_s       cn63xx;
+	struct cvmx_gmxx_rxx_decision_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
+
+/**
+ * cvmx_gmx#_rx#_frm_chk
+ *
+ * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
+ *
+ *
+ * Notes:
+ * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
+ *
+ * In XAUI mode prt0 is used for checking.
+ */
+union cvmx_gmxx_rxx_frm_chk
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_frm_chk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn30xx;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn31xx;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn38xx;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn38xxp2;
+	struct cvmx_gmxx_rxx_frm_chk_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn50xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn52xx   cn52xxp1;
+	struct cvmx_gmxx_rxx_frm_chk_cn52xx   cn56xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn52xx   cn56xxp1;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn58xx;
+	struct cvmx_gmxx_rxx_frm_chk_s        cn58xxp1;
+	struct cvmx_gmxx_rxx_frm_chk_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_rxx_frm_chk_cn63xx   cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
+
+/**
+ * cvmx_gmx#_rx#_frm_ctl
+ *
+ * GMX_RX_FRM_CTL = Frame Control
+ *
+ *
+ * Notes:
+ * * PRE_STRP
+ *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
+ *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
+ *   core as part of the packet.
+ *
+ *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
+ *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
+ *   are skipped when locating the start of the L2 header for DMAC and Control
+ *   frame recognition.
+ *
+ * * CTL_BCK/CTL_DRP
+ *   These bits control how the HW handles incoming PAUSE packets.  Here are
+ *   the most common modes of operation:
+ *     CTL_BCK=1,CTL_DRP=1   - HW does it all
+ *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
+ *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
+ *
+ *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
+ *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
+ *   would constitute an exception which should be handled by the processing
+ *   cores.  PAUSE packets should not be forwarded.
+ */
+union cvmx_gmxx_rxx_frm_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_frm_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
+                                                         When PTP_MODE is set, a 64-bit timestamp will be
+                                                         prepended to every incoming packet. The timestamp
+                                                         bytes are added to the packet in such a way as to
+                                                         not modify the packet's receive byte count.  This
+                                                         implies that the GMX_RX_JABBER, MINERR,
+                                                         GMX_RX_DECISION, GMX_RX_UDD_SKP, and the
+                                                         GMX_RX_STATS_* do not require any adjustment as
+                                                         they operate on the received packet size.
+                                                         When the packet reaches PKI, its size will
+                                                         reflect the additional bytes and is subject to
+                                                         the restrictions below.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1.
+                                                         If PTP_MODE=1,
+                                                          PIP_PRT_CFGx[SKIP] should be increased by 8.
+                                                          PIP_PRT_CFGx[HIGIG_EN] should be 0.
+                                                          PIP_FRM_CHKx[MAXLEN] should be increased by 8.
+                                                          PIP_FRM_CHKx[MINLEN] should be increased by 8.
+                                                          PIP_TAG_INCx[EN] should be adjusted. */
+	uint64_t reserved_11_11               : 1;
+	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets */
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PRE_STRP should be set to
+                                                         account for the variable nature of the PREAMBLE.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII at 10/100Mbs only) */
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data
+                                                         (PASS3 Only) */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is  less strict.
+                                                         GMX will begin the frame at the first SFD.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII/1000Base-X only) */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send a valid 802.3
+                                                         PREAMBLE to begin every frame. GMX checks that a
+                                                         valid PREAMBLE is received (based on PRE_FREE).
+                                                         When a problem does occur within the PREAMBLE
+                                                         seqeunce, the frame is marked as bad and not sent
+                                                         into the core.  The GMX_GMX_RX_INT_REG[PCTERR]
+                                                         interrupt is also raised.
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK
+                                                         must be zero.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t pre_align                    : 1;
+	uint64_t null_dis                     : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t ptp_mode                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_frm_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< Allows for less strict PREAMBLE checking.
+                                                         0-7 cycles of PREAMBLE followed by SFD (pass 1.0)
+                                                         0-254 cycles of PREAMBLE followed by SFD (else) */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< Allows for less strict PREAMBLE checking.
+                                                         0 - 7 cycles of PREAMBLE followed by SFD (pass1.0)
+                                                         0 - 254 cycles of PREAMBLE followed by SFD (else) */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn31xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn30xx   cn38xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn31xx   cn38xxp2;
+	struct cvmx_gmxx_rxx_frm_ctl_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets */
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_free                     : 1;  /**< Allows for less strict PREAMBLE checking.
+                                                         0-254 cycles of PREAMBLE followed by SFD */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_align                    : 1;
+	uint64_t null_dis                     : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn50xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn52xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn52xxp1;
+	struct cvmx_gmxx_rxx_frm_ctl_cn50xx   cn56xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PRE_STRP should be set to
+                                                         account for the variable nature of the PREAMBLE.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII at 10/100Mbs only) */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII/1000Base-X only) */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly.
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK
+                                                         must be zero. */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_align                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn56xxp1;
+	struct cvmx_gmxx_rxx_frm_ctl_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets
+                                                         In spi4 mode, all ports use prt0 for checking. */
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data
+                                                         (PASS3 Only) */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t pre_align                    : 1;
+	uint64_t null_dis                     : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn58xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn30xx   cn58xxp1;
+	struct cvmx_gmxx_rxx_frm_ctl_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t ptp_mode                     : 1;  /**< Timestamp mode
+                                                         When PTP_MODE is set, a 64-bit timestamp will be
+                                                         prepended to every incoming packet. The timestamp
+                                                         bytes are added to the packet in such a way as to
+                                                         not modify the packet's receive byte count.  This
+                                                         implies that the GMX_RX_JABBER, MINERR,
+                                                         GMX_RX_DECISION, GMX_RX_UDD_SKP, and the
+                                                         GMX_RX_STATS_* do not require any adjustment as
+                                                         they operate on the received packet size.
+                                                         When the packet reaches PKI, its size will
+                                                         reflect the additional bytes and is subject to
+                                                         the restrictions below.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1.
+                                                         If PTP_MODE=1,
+                                                          PIP_PRT_CFGx[SKIP] should be increased by 8.
+                                                          PIP_PRT_CFGx[HIGIG_EN] should be 0.
+                                                          PIP_FRM_CHKx[MAXLEN] should be increased by 8.
+                                                          PIP_FRM_CHKx[MINLEN] should be increased by 8.
+                                                          PIP_TAG_INCx[EN] should be adjusted. */
+	uint64_t reserved_11_11               : 1;
+	uint64_t null_dis                     : 1;  /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets */
+	uint64_t pre_align                    : 1;  /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PRE_STRP should be set to
+                                                         account for the variable nature of the PREAMBLE.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII at 10/100Mbs only) */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_free                     : 1;  /**< When set, PREAMBLE checking is  less strict.
+                                                         GMX will begin the frame at the first SFD.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII/1000Base-X only) */
+	uint64_t ctl_smac                     : 1;  /**< Control Pause Frames can match station SMAC */
+	uint64_t ctl_mcst                     : 1;  /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+	uint64_t ctl_bck                      : 1;  /**< Forward pause information to TX block */
+	uint64_t ctl_drp                      : 1;  /**< Drop Control Pause Frames */
+	uint64_t pre_strp                     : 1;  /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */
+	uint64_t pre_chk                      : 1;  /**< This port is configured to send a valid 802.3
+                                                         PREAMBLE to begin every frame. GMX checks that a
+                                                         valid PREAMBLE is received (based on PRE_FREE).
+                                                         When a problem does occur within the PREAMBLE
+                                                         seqeunce, the frame is marked as bad and not sent
+                                                         into the core.  The GMX_GMX_RX_INT_REG[PCTERR]
+                                                         interrupt is also raised.
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK
+                                                         must be zero.
+                                                         If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */
+#else
+	uint64_t pre_chk                      : 1;
+	uint64_t pre_strp                     : 1;
+	uint64_t ctl_drp                      : 1;
+	uint64_t ctl_bck                      : 1;
+	uint64_t ctl_mcst                     : 1;
+	uint64_t ctl_smac                     : 1;
+	uint64_t pre_free                     : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t pre_align                    : 1;
+	uint64_t null_dis                     : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t ptp_mode                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_rxx_frm_ctl_cn63xx   cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
+
+/**
+ * cvmx_gmx#_rx#_frm_max
+ *
+ * GMX_RX_FRM_MAX = Frame Max length
+ *
+ *
+ * Notes:
+ * In spi4 mode, all spi4 ports use prt0 for checking.
+ *
+ * When changing the LEN field, be sure that LEN does not exceed
+ * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
+ * are within the maximum length parameter to be rejected because they exceed
+ * the GMX_RX_JABBER[CNT] limit.
+ */
+union cvmx_gmxx_rxx_frm_max
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_frm_max_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t len                          : 16; /**< Byte count for Max-sized frame check
+                                                         GMX_RXn_FRM_CHK[MAXERR] enables the check for
+                                                         port n.
+                                                         If enabled, failing packets set the MAXERR
+                                                         interrupt and work-queue entry WORD2[opcode] is
+                                                         set to OVER_FCS (0x3, if packet has bad FCS) or
+                                                         OVER_ERR (0x4, if packet has good FCS).
+                                                         LEN =< GMX_RX_JABBER[CNT] */
+#else
+	uint64_t len                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_frm_max_s        cn30xx;
+	struct cvmx_gmxx_rxx_frm_max_s        cn31xx;
+	struct cvmx_gmxx_rxx_frm_max_s        cn38xx;
+	struct cvmx_gmxx_rxx_frm_max_s        cn38xxp2;
+	struct cvmx_gmxx_rxx_frm_max_s        cn58xx;
+	struct cvmx_gmxx_rxx_frm_max_s        cn58xxp1;
+};
+typedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t;
+
+/**
+ * cvmx_gmx#_rx#_frm_min
+ *
+ * GMX_RX_FRM_MIN = Frame Min length
+ *
+ *
+ * Notes:
+ * In spi4 mode, all spi4 ports use prt0 for checking.
+ *
+ */
+union cvmx_gmxx_rxx_frm_min
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_frm_min_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t len                          : 16; /**< Byte count for Min-sized frame check
+                                                         GMX_RXn_FRM_CHK[MINERR] enables the check for
+                                                         port n.
+                                                         If enabled, failing packets set the MINERR
+                                                         interrupt and work-queue entry WORD2[opcode] is
+                                                         set to UNDER_FCS (0x6, if packet has bad FCS) or
+                                                         UNDER_ERR (0x8, if packet has good FCS). */
+#else
+	uint64_t len                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_frm_min_s        cn30xx;
+	struct cvmx_gmxx_rxx_frm_min_s        cn31xx;
+	struct cvmx_gmxx_rxx_frm_min_s        cn38xx;
+	struct cvmx_gmxx_rxx_frm_min_s        cn38xxp2;
+	struct cvmx_gmxx_rxx_frm_min_s        cn58xx;
+	struct cvmx_gmxx_rxx_frm_min_s        cn58xxp1;
+};
+typedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t;
+
+/**
+ * cvmx_gmx#_rx#_ifg
+ *
+ * GMX_RX_IFG = RX Min IFG
+ *
+ */
+union cvmx_gmxx_rxx_ifg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_ifg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ifg                          : 4;  /**< Min IFG (in IFG*8 bits) between packets used to
+                                                         determine IFGERR. Normally IFG is 96 bits.
+                                                         Note in some operating modes, IFG cycles can be
+                                                         inserted or removed in order to achieve clock rate
+                                                         adaptation. For these reasons, the default value
+                                                         is slightly conservative and does not check upto
+                                                         the full 96 bits of IFG.
+                                                         (SGMII/1000Base-X only) */
+#else
+	uint64_t ifg                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_ifg_s            cn30xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn31xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn38xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn38xxp2;
+	struct cvmx_gmxx_rxx_ifg_s            cn50xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn52xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn52xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cn56xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn56xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cn58xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn58xxp1;
+	struct cvmx_gmxx_rxx_ifg_s            cn63xx;
+	struct cvmx_gmxx_rxx_ifg_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
+
+/**
+ * cvmx_gmx#_rx#_int_en
+ *
+ * GMX_RX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * In XAUI mode prt0 is used for checking.
+ *
+ */
+union cvmx_gmxx_rxx_int_en
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_int_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_rxx_int_en_cn30xx    cn31xx;
+	struct cvmx_gmxx_rxx_int_en_cn30xx    cn38xx;
+	struct cvmx_gmxx_rxx_int_en_cn30xx    cn38xxp2;
+	struct cvmx_gmxx_rxx_int_en_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn50xx;
+	struct cvmx_gmxx_rxx_int_en_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_rxx_int_en_cn52xx    cn52xxp1;
+	struct cvmx_gmxx_rxx_int_en_cn52xx    cn56xx;
+	struct cvmx_gmxx_rxx_int_en_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn56xxp1;
+	struct cvmx_gmxx_rxx_int_en_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn58xx;
+	struct cvmx_gmxx_rxx_int_en_cn58xx    cn58xxp1;
+	struct cvmx_gmxx_rxx_int_en_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 CRC8 or Control char error interrupt enable */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 Bad field error interrupt enable */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_rxx_int_en_cn63xx    cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
+
+/**
+ * cvmx_gmx#_rx#_int_reg
+ *
+ * GMX_RX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * (1) exceptions will only be raised to the control processor if the
+ *     corresponding bit in the GMX_RX_INT_EN register is set.
+ *
+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received
+ *     packet's workQ entry.  The GMX_RX_FRM_CHK register provides a bit mask
+ *     for configuring which conditions set the error.
+ *
+ * (3) in half duplex operation, the expectation is that collisions will appear
+ *     as either MINERR o r CAREXT errors.
+ *
+ * (4) JABBER - An RX Jabber error indicates that a packet was received which
+ *              is longer than the maximum allowed packet as defined by the
+ *              system.  GMX will truncate the packet at the JABBER count.
+ *              Failure to do so could lead to system instabilty.
+ *
+ * (5) NIBERR - This error is illegal at 1000Mbs speeds
+ *              (GMX_RX_PRT_CFG[SPEED]==0) and will never assert.
+ *
+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
+ *              GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
+ *              > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
+ *
+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < 64
+ *
+ * (8) ALNERR - Indicates that the packet received was not an integer number of
+ *              bytes.  If FCS checking is enabled, ALNERR will only assert if
+ *              the FCS is bad.  If FCS checking is disabled, ALNERR will
+ *              assert in all non-integer frame cases.
+ *
+ * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
+ *                  is assumed by the receiver when the slottime
+ *                  (GMX_PRT_CFG[SLOTTIME]) is not satisfied.  In 10/100 mode,
+ *                  this will result in a frame < SLOTTIME.  In 1000 mode, it
+ *                  could result either in frame < SLOTTIME or a carrier extend
+ *                  error with the SLOTTIME.  These conditions are visible by...
+ *
+ *                  . transfer ended before slottime - COLDET
+ *                  . carrier extend error           - CAREXT
+ *
+ * (A) LENERR - Length errors occur when the received packet does not match the
+ *              length field.  LENERR is only checked for packets between 64
+ *              and 1500 bytes.  For untagged frames, the length must exact
+ *              match.  For tagged frames the length or length+4 must match.
+ *
+ * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
+ *              Does not check the number of PREAMBLE cycles.
+ *
+ * (C) OVRERR - Not to be included in the HRM
+ *
+ *              OVRERR is an architectural assertion check internal to GMX to
+ *              make sure no assumption was violated.  In a correctly operating
+ *              system, this interrupt can never fire.
+ *
+ *              GMX has an internal arbiter which selects which of 4 ports to
+ *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
+ *              then each port will typically push a tick every 8 cycles - if
+ *              the packet interface is going as fast as possible.  If there
+ *              are four ports, they push every two cycles.  So that's the
+ *              assumption.  That the inbound module will always be able to
+ *              consume the tick before another is produced.  If that doesn't
+ *              happen - that's when OVRERR will assert.
+ *
+ * (D) In XAUI mode prt0 is used for interrupt logging.
+ */
+union cvmx_gmxx_rxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
+                                                         Set when either CRC8 error detected or when
+                                                         a Control Character is found in the message
+                                                         bytes after the K.SOM
+                                                         NOTE: HG2CC has higher priority than HG2FLD
+                                                               i.e. a HiGig2 message that results in HG2CC
+                                                               getting set, will never set HG2FLD. */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 received message field error, as below
+                                                         1) MSG_TYPE field not 6'b00_0000
+                                                            i.e. it is not a FLOW CONTROL message, which
+                                                            is the only defined type for HiGig2
+                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
+                                                            which is the only defined type for HiGig2
+                                                         3) FC_OBJECT field is neither 4'b0000 for
+                                                            Physical Link nor 4'b0010 for Logical Link.
+                                                            Those are the only two defined types in HiGig2 */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize
+                                                         Frame length checks are typically handled in PIP
+                                                         (PIP_INT_REG[MINERR]), but pause frames are
+                                                         normally discarded before being inspected by PIP. */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_int_reg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn31xx;
+	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn38xx;
+	struct cvmx_gmxx_rxx_int_reg_cn30xx   cn38xxp2;
+	struct cvmx_gmxx_rxx_int_reg_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn50xx;
+	struct cvmx_gmxx_rxx_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
+                                                         Set when either CRC8 error detected or when
+                                                         a Control Character is found in the message
+                                                         bytes after the K.SOM
+                                                         NOTE: HG2CC has higher priority than HG2FLD
+                                                               i.e. a HiGig2 message that results in HG2CC
+                                                               getting set, will never set HG2FLD. */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 received message field error, as below
+                                                         1) MSG_TYPE field not 6'b00_0000
+                                                            i.e. it is not a FLOW CONTROL message, which
+                                                            is the only defined type for HiGig2
+                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
+                                                            which is the only defined type for HiGig2
+                                                         3) FC_OBJECT field is neither 4'b0000 for
+                                                            Physical Link nor 4'b0010 for Logical Link.
+                                                            Those are the only two defined types in HiGig2 */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_rxx_int_reg_cn52xx   cn52xxp1;
+	struct cvmx_gmxx_rxx_int_reg_cn52xx   cn56xx;
+	struct cvmx_gmxx_rxx_int_reg_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn56xxp1;
+	struct cvmx_gmxx_rxx_int_reg_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t phy_dupx                     : 1;  /**< Change in the RMGII inbound LinkDuplex */
+	uint64_t phy_spd                      : 1;  /**< Change in the RMGII inbound LinkSpeed */
+	uint64_t phy_link                     : 1;  /**< Change in the RMGII inbound LinkStatus */
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+	uint64_t coldet                       : 1;  /**< Collision Detection */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime */
+	uint64_t rsverr                       : 1;  /**< RGMII reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+	uint64_t niberr                       : 1;  /**< Nibble error (hi_nibble != lo_nibble) */
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with RMGII Data reception error */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t alnerr                       : 1;  /**< Frame was received with an alignment error */
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t carext                       : 1;  /**< RGMII carrier extend error */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t alnerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t niberr                       : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t phy_link                     : 1;
+	uint64_t phy_spd                      : 1;
+	uint64_t phy_dupx                     : 1;
+	uint64_t pause_drp                    : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn58xx;
+	struct cvmx_gmxx_rxx_int_reg_cn58xx   cn58xxp1;
+	struct cvmx_gmxx_rxx_int_reg_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t hg2cc                        : 1;  /**< HiGig2 received message CRC or Control char  error
+                                                         Set when either CRC8 error detected or when
+                                                         a Control Character is found in the message
+                                                         bytes after the K.SOM
+                                                         NOTE: HG2CC has higher priority than HG2FLD
+                                                               i.e. a HiGig2 message that results in HG2CC
+                                                               getting set, will never set HG2FLD. */
+	uint64_t hg2fld                       : 1;  /**< HiGig2 received message field error, as below
+                                                         1) MSG_TYPE field not 6'b00_0000
+                                                            i.e. it is not a FLOW CONTROL message, which
+                                                            is the only defined type for HiGig2
+                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
+                                                            which is the only defined type for HiGig2
+                                                         3) FC_OBJECT field is neither 4'b0000 for
+                                                            Physical Link nor 4'b0010 for Logical Link.
+                                                            Those are the only two defined types in HiGig2 */
+	uint64_t undat                        : 1;  /**< Unexpected Data
+                                                         (XAUI Mode only) */
+	uint64_t uneop                        : 1;  /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+	uint64_t unsop                        : 1;  /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+	uint64_t bad_term                     : 1;  /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+	uint64_t bad_seq                      : 1;  /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t rem_fault                    : 1;  /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t loc_fault                    : 1;  /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+	uint64_t pause_drp                    : 1;  /**< Pause packet was dropped due to full GMX RX FIFO */
+	uint64_t reserved_16_18               : 3;
+	uint64_t ifgerr                       : 1;  /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+	uint64_t coldet                       : 1;  /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t falerr                       : 1;  /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+	uint64_t rsverr                       : 1;  /**< Reserved opcodes */
+	uint64_t pcterr                       : 1;  /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+	uint64_t ovrerr                       : 1;  /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t skperr                       : 1;  /**< Skipper error */
+	uint64_t rcverr                       : 1;  /**< Frame was received with Data reception error */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t fcserr                       : 1;  /**< Frame was received with FCS/CRC error */
+	uint64_t jabber                       : 1;  /**< Frame was received with length > sys_length */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t carext                       : 1;  /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+	uint64_t minerr                       : 1;  /**< Pause Frame was received with length<minFrameSize
+                                                         Frame length checks are typically handled in PIP
+                                                         (PIP_INT_REG[MINERR]), but pause frames are
+                                                         normally discarded before being inspected by PIP. */
+#else
+	uint64_t minerr                       : 1;
+	uint64_t carext                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t jabber                       : 1;
+	uint64_t fcserr                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t rcverr                       : 1;
+	uint64_t skperr                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t ovrerr                       : 1;
+	uint64_t pcterr                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t falerr                       : 1;
+	uint64_t coldet                       : 1;
+	uint64_t ifgerr                       : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t pause_drp                    : 1;
+	uint64_t loc_fault                    : 1;
+	uint64_t rem_fault                    : 1;
+	uint64_t bad_seq                      : 1;
+	uint64_t bad_term                     : 1;
+	uint64_t unsop                        : 1;
+	uint64_t uneop                        : 1;
+	uint64_t undat                        : 1;
+	uint64_t hg2fld                       : 1;
+	uint64_t hg2cc                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_rxx_int_reg_cn63xx   cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
+
+/**
+ * cvmx_gmx#_rx#_jabber
+ *
+ * GMX_RX_JABBER = The max size packet after which GMX will truncate
+ *
+ *
+ * Notes:
+ * CNT must be 8-byte aligned such that CNT[2:0] == 0
+ *
+ * The packet that will be sent to the packet input logic will have an
+ * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and
+ * GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
+ * defined as...
+ *
+ *      max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8)
+ *
+ * In XAUI mode prt0 is used for checking.
+ */
+union cvmx_gmxx_rxx_jabber
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_jabber_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Byte count for jabber check
+                                                         Failing packets set the JABBER interrupt and are
+                                                         optionally sent with opcode==JABBER
+                                                         GMX will truncate the packet to CNT bytes */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_jabber_s         cn30xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn31xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn38xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn38xxp2;
+	struct cvmx_gmxx_rxx_jabber_s         cn50xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn52xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn52xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cn56xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn56xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cn58xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn58xxp1;
+	struct cvmx_gmxx_rxx_jabber_s         cn63xx;
+	struct cvmx_gmxx_rxx_jabber_s         cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
+
+/**
+ * cvmx_gmx#_rx#_pause_drop_time
+ *
+ * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
+ *
+ */
+union cvmx_gmxx_rxx_pause_drop_time
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_pause_drop_time_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t status                       : 16; /**< Time extracted from the dropped PAUSE packet */
+#else
+	uint64_t status                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
+	struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
+
+/**
+ * cvmx_gmx#_rx#_rx_inbnd
+ *
+ * GMX_RX_INBND = RGMII InBand Link Status
+ *
+ *
+ * Notes:
+ * These fields are only valid if the attached PHY is operating in RGMII mode
+ * and supports the optional in-band status (see section 3.4.1 of the RGMII
+ * specification, version 1.3 for more information).
+ */
+union cvmx_gmxx_rxx_rx_inbnd
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_rx_inbnd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t duplex                       : 1;  /**< RGMII Inbound LinkDuplex
+                                                         0=half-duplex
+                                                         1=full-duplex */
+	uint64_t speed                        : 2;  /**< RGMII Inbound LinkSpeed
+                                                         00=2.5MHz
+                                                         01=25MHz
+                                                         10=125MHz
+                                                         11=Reserved */
+	uint64_t status                       : 1;  /**< RGMII Inbound LinkStatus
+                                                         0=down
+                                                         1=up */
+#else
+	uint64_t status                       : 1;
+	uint64_t speed                        : 2;
+	uint64_t duplex                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn30xx;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn31xx;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn38xx;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn38xxp2;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn50xx;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn58xx;
+	struct cvmx_gmxx_rxx_rx_inbnd_s       cn58xxp1;
+};
+typedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_ctl
+ *
+ * GMX_RX_STATS_CTL = RX Stats Control register
+ *
+ */
+union cvmx_gmxx_rxx_stats_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rd_clr                       : 1;  /**< RX Stats registers will clear on reads */
+#else
+	uint64_t rd_clr                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn30xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn31xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn38xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn50xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn52xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn56xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn58xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn63xx;
+	struct cvmx_gmxx_rxx_stats_ctl_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_octs
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_octs
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_octs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of received good packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn30xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn31xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn38xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn50xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn52xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn56xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn58xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn63xx;
+	struct cvmx_gmxx_rxx_stats_octs_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_ctl
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_octs_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of received pause packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_dmac
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_octs_dmac
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of filtered dmac packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_drp
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_octs_drp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t cnt                          : 48; /**< Octet count of dropped packets */
+#else
+	uint64_t cnt                          : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts
+ *
+ * GMX_RX_STATS_PKTS
+ *
+ * Count of good received packets - packets that are not recognized as PAUSE
+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or
+ * have any other OPCODE (FCS, Length, etc).
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_pkts
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_pkts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of received good packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn30xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn31xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn38xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn50xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn52xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn56xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn58xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn63xx;
+	struct cvmx_gmxx_rxx_stats_pkts_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_bad
+ *
+ * GMX_RX_STATS_PKTS_BAD
+ *
+ * Count of all packets received with some error that were not dropped
+ * either due to the dmac filter or lack of room in the receive FIFO.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_pkts_bad
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of bad packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_ctl
+ *
+ * GMX_RX_STATS_PKTS_CTL
+ *
+ * Count of all packets received that were recognized as Flow Control or
+ * PAUSE packets.  PAUSE packets with any kind of error are counted in
+ * GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
+ * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
+ * increments regardless of whether the packet is dropped.  Pause packets
+ * will never be counted in GMX_RX_STATS_PKTS.  Packets dropped due the dmac
+ * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_pkts_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of received pause packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_dmac
+ *
+ * GMX_RX_STATS_PKTS_DMAC
+ *
+ * Count of all packets received that were dropped by the dmac filter.
+ * Packets that match the DMAC will be dropped and counted here regardless
+ * of if they were bad packets.  These packets will never be counted in
+ * GMX_RX_STATS_PKTS.
+ *
+ * Some packets that were not able to satisify the DECISION_CNT may not
+ * actually be dropped by Octeon, but they will be counted here as if they
+ * were dropped.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_pkts_dmac
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of filtered dmac packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_drp
+ *
+ * GMX_RX_STATS_PKTS_DRP
+ *
+ * Count of all packets received that were dropped due to a full receive
+ * FIFO.  This counts good and bad packets received - all packets dropped by
+ * the FIFO.  It does not count packets dropped by the dmac or pause packet
+ * filters.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_rxx_stats_pkts_drp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Count of dropped packets */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
+	struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
+
+/**
+ * cvmx_gmx#_rx#_udd_skp
+ *
+ * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
+ *
+ *
+ * Notes:
+ * (1) The skip bytes are part of the packet and will be sent down the NCB
+ *     packet interface and will be handled by PKI.
+ *
+ * (2) The system can determine if the UDD bytes are included in the FCS check
+ *     by using the FCSSEL field - if the FCS check is enabled.
+ *
+ * (3) Assume that the preamble/sfd is always at the start of the frame - even
+ *     before UDD bytes.  In most cases, there will be no preamble in these
+ *     cases since it will be packet interface in direct communication to
+ *     another packet interface (MAC to MAC) without a PHY involved.
+ *
+ * (4) We can still do address filtering and control packet filtering is the
+ *     user desires.
+ *
+ * (5) UDD_SKP must be 0 in half-duplex operation unless
+ *     GMX_RX_FRM_CTL[PRE_CHK] is clear.  If GMX_RX_FRM_CTL[PRE_CHK] is clear,
+ *     then UDD_SKP will normally be 8.
+ *
+ * (6) In all cases, the UDD bytes will be sent down the packet interface as
+ *     part of the packet.  The UDD bytes are never stripped from the actual
+ *     packet.
+ *
+ * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
+ */
+union cvmx_gmxx_rxx_udd_skp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rxx_udd_skp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t fcssel                       : 1;  /**< Include the skip bytes in the FCS calculation
+                                                         0 = all skip bytes are included in FCS
+                                                         1 = the skip bytes are not included in FCS
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, FCSSEL must
+                                                         be zero. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t len                          : 7;  /**< Amount of User-defined data before the start of
+                                                         the L2 data.  Zero means L2 comes first.
+                                                         Max value is 64.
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, LEN must be
+                                                         set to 12 or 16 (depending on HiGig header size)
+                                                         to account for the HiGig header. LEN=12 selects
+                                                         HiGig/HiGig+, and LEN=16 selects HiGig2. */
+#else
+	uint64_t len                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t fcssel                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn30xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn31xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn38xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn38xxp2;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn50xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn52xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn52xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn56xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn56xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn58xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn58xxp1;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn63xx;
+	struct cvmx_gmxx_rxx_udd_skp_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
+
+/**
+ * cvmx_gmx#_rx_bp_drop#
+ *
+ * GMX_RX_BP_DROP = FIFO mark for packet drop
+ *
+ *
+ * Notes:
+ * The actual watermark is dynamic with respect to the GMX_RX_PRTS
+ * register.  The GMX_RX_PRTS controls the depth of the port's
+ * FIFO so as ports are added or removed, the drop point may change.
+ *
+ * In XAUI mode prt0 is used for checking.
+ */
+union cvmx_gmxx_rx_bp_dropx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_bp_dropx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mark                         : 6;  /**< Number of 8B ticks to reserve in the RX FIFO.
+                                                         When the FIFO exceeds this count, packets will
+                                                         be dropped and not buffered.
+                                                         MARK should typically be programmed to ports+1.
+                                                         Failure to program correctly can lead to system
+                                                         instability. */
+#else
+	uint64_t mark                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn30xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn31xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn38xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn38xxp2;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn50xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn52xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn52xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn56xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn56xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn58xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn58xxp1;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn63xx;
+	struct cvmx_gmxx_rx_bp_dropx_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
+
+/**
+ * cvmx_gmx#_rx_bp_off#
+ *
+ * GMX_RX_BP_OFF = Lowater mark for packet drop
+ *
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.
+ *
+ */
+union cvmx_gmxx_rx_bp_offx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_bp_offx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mark                         : 6;  /**< Water mark (8B ticks) to deassert backpressure */
+#else
+	uint64_t mark                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_bp_offx_s         cn30xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn31xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn38xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn38xxp2;
+	struct cvmx_gmxx_rx_bp_offx_s         cn50xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn52xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn52xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cn56xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn56xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cn58xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn58xxp1;
+	struct cvmx_gmxx_rx_bp_offx_s         cn63xx;
+	struct cvmx_gmxx_rx_bp_offx_s         cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
+
+/**
+ * cvmx_gmx#_rx_bp_on#
+ *
+ * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
+ *
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.
+ *
+ */
+union cvmx_gmxx_rx_bp_onx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_bp_onx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t mark                         : 9;  /**< Hiwater mark (8B ticks) for backpressure.
+                                                         Each register is for an individual port.  In XAUI
+                                                         mode, prt0 is used for the unified RX FIFO
+                                                         GMX_RX_BP_ON must satisfy
+                                                         BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP)
+                                                         A value of zero will immediately assert back
+                                                         pressure. */
+#else
+	uint64_t mark                         : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_bp_onx_s          cn30xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn31xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn38xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn38xxp2;
+	struct cvmx_gmxx_rx_bp_onx_s          cn50xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn52xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn52xxp1;
+	struct cvmx_gmxx_rx_bp_onx_s          cn56xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn56xxp1;
+	struct cvmx_gmxx_rx_bp_onx_s          cn58xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn58xxp1;
+	struct cvmx_gmxx_rx_bp_onx_s          cn63xx;
+	struct cvmx_gmxx_rx_bp_onx_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
+
+/**
+ * cvmx_gmx#_rx_hg2_status
+ *
+ * ** HG2 message CSRs
+ *
+ */
+union cvmx_gmxx_rx_hg2_status
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_hg2_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t phtim2go                     : 16; /**< Physical time to go for removal of physical link
+                                                         pause. Initial value from received HiGig2 msg pkt
+                                                         Non-zero only when physical back pressure active */
+	uint64_t xof                          : 16; /**< 16 bit xof back pressure vector from HiGig2 msg pkt
+                                                         or from CBFC packets.
+                                                         Non-zero only when logical back pressure is active
+                                                         All bits will be 0 when LGTIM2GO=0 */
+	uint64_t lgtim2go                     : 16; /**< Logical packet flow back pressure time remaining
+                                                         Initial value set from xof time field of HiGig2
+                                                         message packet received or a function of the
+                                                         enabled and current timers for CBFC packets.
+                                                         Non-zero only when logical back pressure is active */
+#else
+	uint64_t lgtim2go                     : 16;
+	uint64_t xof                          : 16;
+	uint64_t phtim2go                     : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_hg2_status_s      cn52xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn52xxp1;
+	struct cvmx_gmxx_rx_hg2_status_s      cn56xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn63xx;
+	struct cvmx_gmxx_rx_hg2_status_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
+
+/**
+ * cvmx_gmx#_rx_pass_en
+ *
+ * GMX_RX_PASS_EN = Packet pass through mode enable
+ *
+ * When both Octane ports are running in Spi4 mode, packets can be directly
+ * passed from one SPX interface to the other without being processed by the
+ * core or PP's.  The register has one bit for each port to enable the pass
+ * through feature.
+ *
+ * Notes:
+ * (1) Can only be used in dual Spi4 configs
+ *
+ * (2) The mapped pass through output port cannot be the destination port for
+ *     any Octane core traffic.
+ */
+union cvmx_gmxx_rx_pass_en
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_pass_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t en                           : 16; /**< Which ports to configure in pass through mode */
+#else
+	uint64_t en                           : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_pass_en_s         cn38xx;
+	struct cvmx_gmxx_rx_pass_en_s         cn38xxp2;
+	struct cvmx_gmxx_rx_pass_en_s         cn58xx;
+	struct cvmx_gmxx_rx_pass_en_s         cn58xxp1;
+};
+typedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t;
+
+/**
+ * cvmx_gmx#_rx_pass_map#
+ *
+ * GMX_RX_PASS_MAP = Packet pass through port map
+ *
+ */
+union cvmx_gmxx_rx_pass_mapx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_pass_mapx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t dprt                         : 4;  /**< Destination port to map Spi pass through traffic */
+#else
+	uint64_t dprt                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_pass_mapx_s       cn38xx;
+	struct cvmx_gmxx_rx_pass_mapx_s       cn38xxp2;
+	struct cvmx_gmxx_rx_pass_mapx_s       cn58xx;
+	struct cvmx_gmxx_rx_pass_mapx_s       cn58xxp1;
+};
+typedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t;
+
+/**
+ * cvmx_gmx#_rx_prt_info
+ *
+ * GMX_RX_PRT_INFO = Report the RX status for port
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
+ *
+ */
+union cvmx_gmxx_rx_prt_info
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_prt_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t drop                         : 16; /**< Per port indication that data was dropped */
+	uint64_t commit                       : 16; /**< Per port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 16;
+	uint64_t drop                         : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_prt_info_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t drop                         : 3;  /**< Per port indication that data was dropped */
+	uint64_t reserved_3_15                : 13;
+	uint64_t commit                       : 3;  /**< Per port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 3;
+	uint64_t reserved_3_15                : 13;
+	uint64_t drop                         : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_rx_prt_info_cn30xx   cn31xx;
+	struct cvmx_gmxx_rx_prt_info_s        cn38xx;
+	struct cvmx_gmxx_rx_prt_info_cn30xx   cn50xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t drop                         : 4;  /**< Per port indication that data was dropped */
+	uint64_t reserved_4_15                : 12;
+	uint64_t commit                       : 4;  /**< Per port indication that SOP was accepted */
+#else
+	uint64_t commit                       : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t drop                         : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn52xxp1;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn56xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn56xxp1;
+	struct cvmx_gmxx_rx_prt_info_s        cn58xx;
+	struct cvmx_gmxx_rx_prt_info_s        cn58xxp1;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn63xx;
+	struct cvmx_gmxx_rx_prt_info_cn52xx   cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
+
+/**
+ * cvmx_gmx#_rx_prts
+ *
+ * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into
+ *
+ *
+ * Notes:
+ * GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode.
+ *
+ */
+union cvmx_gmxx_rx_prts
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_prts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t prts                         : 3;  /**< In SGMII/1000Base-X mode, the RX buffer can be
+                                                         carved into several logical buffers depending on
+                                                         the number or implemented ports.
+                                                         0 or 1 port  = 512ticks / 4096bytes
+                                                         2 ports      = 256ticks / 2048bytes
+                                                         3 or 4 ports = 128ticks / 1024bytes */
+#else
+	uint64_t prts                         : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_prts_s            cn30xx;
+	struct cvmx_gmxx_rx_prts_s            cn31xx;
+	struct cvmx_gmxx_rx_prts_s            cn38xx;
+	struct cvmx_gmxx_rx_prts_s            cn38xxp2;
+	struct cvmx_gmxx_rx_prts_s            cn50xx;
+	struct cvmx_gmxx_rx_prts_s            cn52xx;
+	struct cvmx_gmxx_rx_prts_s            cn52xxp1;
+	struct cvmx_gmxx_rx_prts_s            cn56xx;
+	struct cvmx_gmxx_rx_prts_s            cn56xxp1;
+	struct cvmx_gmxx_rx_prts_s            cn58xx;
+	struct cvmx_gmxx_rx_prts_s            cn58xxp1;
+	struct cvmx_gmxx_rx_prts_s            cn63xx;
+	struct cvmx_gmxx_rx_prts_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
+
+/**
+ * cvmx_gmx#_rx_tx_status
+ *
+ * GMX_RX_TX_STATUS = GMX RX/TX Status
+ *
+ */
+union cvmx_gmxx_rx_tx_status
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_tx_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t tx                           : 3;  /**< Transmit data since last read */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t rx                           : 3;  /**< Receive data since last read */
+#else
+	uint64_t rx                           : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t tx                           : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_tx_status_s       cn30xx;
+	struct cvmx_gmxx_rx_tx_status_s       cn31xx;
+	struct cvmx_gmxx_rx_tx_status_s       cn50xx;
+};
+typedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t;
+
+/**
+ * cvmx_gmx#_rx_xaui_bad_col
+ */
+union cvmx_gmxx_rx_xaui_bad_col
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_xaui_bad_col_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t val                          : 1;  /**< Set when GMX_RX_INT_REG[PCTERR] is set.
+                                                         (XAUI mode only) */
+	uint64_t state                        : 3;  /**< When GMX_RX_INT_REG[PCTERR] is set, STATE will
+                                                         conatin the receive state at the time of the
+                                                         error.
+                                                         (XAUI mode only) */
+	uint64_t lane_rxc                     : 4;  /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXC will
+                                                         conatin the XAUI column at the time of the error.
+                                                         (XAUI mode only) */
+	uint64_t lane_rxd                     : 32; /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXD will
+                                                         conatin the XAUI column at the time of the error.
+                                                         (XAUI mode only) */
+#else
+	uint64_t lane_rxd                     : 32;
+	uint64_t lane_rxc                     : 4;
+	uint64_t state                        : 3;
+	uint64_t val                          : 1;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn52xx;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn52xxp1;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn56xx;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn56xxp1;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn63xx;
+	struct cvmx_gmxx_rx_xaui_bad_col_s    cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t;
+
+/**
+ * cvmx_gmx#_rx_xaui_ctl
+ */
+union cvmx_gmxx_rx_xaui_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_rx_xaui_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t status                       : 2;  /**< Link Status
+                                                         0=Link OK
+                                                         1=Local Fault
+                                                         2=Remote Fault
+                                                         3=Reserved
+                                                         (XAUI mode only) */
+#else
+	uint64_t status                       : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn52xx;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn52xxp1;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn56xx;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn56xxp1;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn63xx;
+	struct cvmx_gmxx_rx_xaui_ctl_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t;
+
+/**
+ * cvmx_gmx#_smac#
+ *
+ * GMX_SMAC = Packet SMAC
+ *
+ */
+union cvmx_gmxx_smacx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_smacx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t smac                         : 48; /**< The SMAC field is used for generating and
+                                                         accepting Control Pause packets */
+#else
+	uint64_t smac                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_smacx_s              cn30xx;
+	struct cvmx_gmxx_smacx_s              cn31xx;
+	struct cvmx_gmxx_smacx_s              cn38xx;
+	struct cvmx_gmxx_smacx_s              cn38xxp2;
+	struct cvmx_gmxx_smacx_s              cn50xx;
+	struct cvmx_gmxx_smacx_s              cn52xx;
+	struct cvmx_gmxx_smacx_s              cn52xxp1;
+	struct cvmx_gmxx_smacx_s              cn56xx;
+	struct cvmx_gmxx_smacx_s              cn56xxp1;
+	struct cvmx_gmxx_smacx_s              cn58xx;
+	struct cvmx_gmxx_smacx_s              cn58xxp1;
+	struct cvmx_gmxx_smacx_s              cn63xx;
+	struct cvmx_gmxx_smacx_s              cn63xxp1;
+};
+typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
+
+/**
+ * cvmx_gmx#_soft_bist
+ *
+ * GMX_SOFT_BIST = Software BIST Control
+ *
+ */
+union cvmx_gmxx_soft_bist
+{
+	uint64_t u64;
+	struct cvmx_gmxx_soft_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t start_bist                   : 1;  /**< Run BIST on all memories in the XAUI CLK domain */
+	uint64_t clear_bist                   : 1;  /**< Choose between full BIST and CLEAR bist
+                                                         0=Run full BIST
+                                                         1=Only run clear BIST */
+#else
+	uint64_t clear_bist                   : 1;
+	uint64_t start_bist                   : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_gmxx_soft_bist_s          cn63xx;
+	struct cvmx_gmxx_soft_bist_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
+
+/**
+ * cvmx_gmx#_stat_bp
+ *
+ * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
+ *
+ */
+union cvmx_gmxx_stat_bp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_stat_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t bp                           : 1;  /**< Current BP state */
+	uint64_t cnt                          : 16; /**< Number of cycles that BP has been asserted
+                                                         Saturating counter */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t bp                           : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_gmxx_stat_bp_s            cn30xx;
+	struct cvmx_gmxx_stat_bp_s            cn31xx;
+	struct cvmx_gmxx_stat_bp_s            cn38xx;
+	struct cvmx_gmxx_stat_bp_s            cn38xxp2;
+	struct cvmx_gmxx_stat_bp_s            cn50xx;
+	struct cvmx_gmxx_stat_bp_s            cn52xx;
+	struct cvmx_gmxx_stat_bp_s            cn52xxp1;
+	struct cvmx_gmxx_stat_bp_s            cn56xx;
+	struct cvmx_gmxx_stat_bp_s            cn56xxp1;
+	struct cvmx_gmxx_stat_bp_s            cn58xx;
+	struct cvmx_gmxx_stat_bp_s            cn58xxp1;
+	struct cvmx_gmxx_stat_bp_s            cn63xx;
+	struct cvmx_gmxx_stat_bp_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t;
+
+/**
+ * cvmx_gmx#_tx#_append
+ *
+ * GMX_TX_APPEND = Packet TX Append Control
+ *
+ */
+union cvmx_gmxx_txx_append
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_append_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t force_fcs                    : 1;  /**< Append the Ethernet FCS on each pause packet
+                                                         when FCS is clear.  Pause packets are normally
+                                                         padded to 60 bytes.  If GMX_TX_MIN_PKT[MIN_SIZE]
+                                                         exceeds 59, then FORCE_FCS will not be used. */
+	uint64_t fcs                          : 1;  /**< Append the Ethernet FCS on each packet */
+	uint64_t pad                          : 1;  /**< Append PAD bytes such that min sized */
+	uint64_t preamble                     : 1;  /**< Prepend the Ethernet preamble on each transfer
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PREAMBLE
+                                                         must be zero. */
+#else
+	uint64_t preamble                     : 1;
+	uint64_t pad                          : 1;
+	uint64_t fcs                          : 1;
+	uint64_t force_fcs                    : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_append_s         cn30xx;
+	struct cvmx_gmxx_txx_append_s         cn31xx;
+	struct cvmx_gmxx_txx_append_s         cn38xx;
+	struct cvmx_gmxx_txx_append_s         cn38xxp2;
+	struct cvmx_gmxx_txx_append_s         cn50xx;
+	struct cvmx_gmxx_txx_append_s         cn52xx;
+	struct cvmx_gmxx_txx_append_s         cn52xxp1;
+	struct cvmx_gmxx_txx_append_s         cn56xx;
+	struct cvmx_gmxx_txx_append_s         cn56xxp1;
+	struct cvmx_gmxx_txx_append_s         cn58xx;
+	struct cvmx_gmxx_txx_append_s         cn58xxp1;
+	struct cvmx_gmxx_txx_append_s         cn63xx;
+	struct cvmx_gmxx_txx_append_s         cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
+
+/**
+ * cvmx_gmx#_tx#_burst
+ *
+ * GMX_TX_BURST = Packet TX Burst Counter
+ *
+ */
+union cvmx_gmxx_txx_burst
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_burst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t burst                        : 16; /**< Burst (refer to 802.3 to set correctly)
+                                                         Only valid for 1000Mbs half-duplex operation
+                                                          halfdup / 1000Mbs: 0x2000
+                                                          all other modes:   0x0
+                                                         (SGMII/1000Base-X only) */
+#else
+	uint64_t burst                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_burst_s          cn30xx;
+	struct cvmx_gmxx_txx_burst_s          cn31xx;
+	struct cvmx_gmxx_txx_burst_s          cn38xx;
+	struct cvmx_gmxx_txx_burst_s          cn38xxp2;
+	struct cvmx_gmxx_txx_burst_s          cn50xx;
+	struct cvmx_gmxx_txx_burst_s          cn52xx;
+	struct cvmx_gmxx_txx_burst_s          cn52xxp1;
+	struct cvmx_gmxx_txx_burst_s          cn56xx;
+	struct cvmx_gmxx_txx_burst_s          cn56xxp1;
+	struct cvmx_gmxx_txx_burst_s          cn58xx;
+	struct cvmx_gmxx_txx_burst_s          cn58xxp1;
+	struct cvmx_gmxx_txx_burst_s          cn63xx;
+	struct cvmx_gmxx_txx_burst_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t;
+
+/**
+ * cvmx_gmx#_tx#_cbfc_xoff
+ */
+union cvmx_gmxx_txx_cbfc_xoff
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_cbfc_xoff_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t xoff                         : 16; /**< Which ports to backpressure
+                                                         Do not write in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+	uint64_t xoff                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn52xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn56xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn63xx;
+	struct cvmx_gmxx_txx_cbfc_xoff_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t;
+
+/**
+ * cvmx_gmx#_tx#_cbfc_xon
+ */
+union cvmx_gmxx_txx_cbfc_xon
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_cbfc_xon_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t xon                          : 16; /**< Which ports to stop backpressure
+                                                         Do not write in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+	uint64_t xon                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn52xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn56xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn63xx;
+	struct cvmx_gmxx_txx_cbfc_xon_s       cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
+
+/**
+ * cvmx_gmx#_tx#_clk
+ *
+ * Per Port
+ *
+ *
+ * GMX_TX_CLK = RGMII TX Clock Generation Register
+ *
+ * Notes:
+ * Programming Restrictions:
+ *  (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1.
+ *  (2) In MII mode, CLK_CNT == 1
+ *  (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock.
+ *
+ * RGMII Example:
+ *  Given a 125MHz PLL reference clock...
+ *   CLK_CNT ==  1 ==> 125.0MHz TXC clock period (8ns* 1)
+ *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)
+ *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)
+ */
+union cvmx_gmxx_txx_clk
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_clk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t clk_cnt                      : 6;  /**< Controls the RGMII TXC frequency
+                                                         When PLL is used, TXC(phase) =
+                                                          spi4_tx_pll_ref_clk(period)/2*CLK_CNT
+                                                         When PLL bypass is used, TXC(phase) =
+                                                          spi4_tx_pll_ref_clk(period)*2*CLK_CNT
+                                                         NOTE: CLK_CNT==0 will not generate any clock
+                                                         if CLK_CNT > 1 if GMX_PRT_CFG[SPEED]==0 */
+#else
+	uint64_t clk_cnt                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_clk_s            cn30xx;
+	struct cvmx_gmxx_txx_clk_s            cn31xx;
+	struct cvmx_gmxx_txx_clk_s            cn38xx;
+	struct cvmx_gmxx_txx_clk_s            cn38xxp2;
+	struct cvmx_gmxx_txx_clk_s            cn50xx;
+	struct cvmx_gmxx_txx_clk_s            cn58xx;
+	struct cvmx_gmxx_txx_clk_s            cn58xxp1;
+};
+typedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t;
+
+/**
+ * cvmx_gmx#_tx#_ctl
+ *
+ * GMX_TX_CTL = TX Control register
+ *
+ */
+union cvmx_gmxx_txx_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t xsdef_en                     : 1;  /**< Enables the excessive deferral check for stats
+                                                         and interrupts
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol_en                     : 1;  /**< Enables the excessive collision check for stats
+                                                         and interrupts
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t xscol_en                     : 1;
+	uint64_t xsdef_en                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_ctl_s            cn30xx;
+	struct cvmx_gmxx_txx_ctl_s            cn31xx;
+	struct cvmx_gmxx_txx_ctl_s            cn38xx;
+	struct cvmx_gmxx_txx_ctl_s            cn38xxp2;
+	struct cvmx_gmxx_txx_ctl_s            cn50xx;
+	struct cvmx_gmxx_txx_ctl_s            cn52xx;
+	struct cvmx_gmxx_txx_ctl_s            cn52xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cn56xx;
+	struct cvmx_gmxx_txx_ctl_s            cn56xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cn58xx;
+	struct cvmx_gmxx_txx_ctl_s            cn58xxp1;
+	struct cvmx_gmxx_txx_ctl_s            cn63xx;
+	struct cvmx_gmxx_txx_ctl_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
+
+/**
+ * cvmx_gmx#_tx#_min_pkt
+ *
+ * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
+ *
+ */
+union cvmx_gmxx_txx_min_pkt
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_min_pkt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t min_size                     : 8;  /**< Min frame in bytes before the FCS is applied
+                                                         Padding is only appened when GMX_TX_APPEND[PAD]
+                                                         for the coresponding port is set.
+                                                         In SGMII mode, packets will be padded to
+                                                          MIN_SIZE+1. The reset value will pad to 60 bytes.
+                                                         In XAUI mode, packets will be padded to
+                                                          MIN(252,(MIN_SIZE+1 & ~0x3))
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, the HiGig
+                                                          header (12B or 16B) is normally added to the
+                                                          packet, so MIN_SIZE should be 59+12=71B for
+                                                          HiGig or 59+16=75B for HiGig2. */
+#else
+	uint64_t min_size                     : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_min_pkt_s        cn30xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn31xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn38xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn38xxp2;
+	struct cvmx_gmxx_txx_min_pkt_s        cn50xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn52xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn52xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cn56xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn56xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cn58xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn58xxp1;
+	struct cvmx_gmxx_txx_min_pkt_s        cn63xx;
+	struct cvmx_gmxx_txx_min_pkt_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
+
+/**
+ * cvmx_gmx#_tx#_pause_pkt_interval
+ *
+ * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent
+ *
+ *
+ * Notes:
+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ *
+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ *
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ *
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ */
+union cvmx_gmxx_txx_pause_pkt_interval
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t interval                     : 16; /**< Arbitrate for a 802.3 pause packet, HiGig2 message,
+                                                         or CBFC pause packet every (INTERVAL*512)
+                                                         bit-times.
+                                                         Normally, 0 < INTERVAL < GMX_TX_PAUSE_PKT_TIME
+                                                         INTERVAL=0, will only send a single PAUSE packet
+                                                         for each backpressure event */
+#else
+	uint64_t interval                     : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
+	struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t;
+
+/**
+ * cvmx_gmx#_tx#_pause_pkt_time
+ *
+ * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field
+ *
+ *
+ * Notes:
+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ *
+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ *
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ *
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ */
+union cvmx_gmxx_txx_pause_pkt_time
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_pause_pkt_time_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< The pause_time field placed in outbnd 802.3 pause
+                                                         packets, HiGig2 messages, or CBFC pause packets.
+                                                         pause_time is in 512 bit-times
+                                                         Normally, TIME > GMX_TX_PAUSE_PKT_INTERVAL */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
+	struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
+
+/**
+ * cvmx_gmx#_tx#_pause_togo
+ *
+ * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
+ *
+ */
+union cvmx_gmxx_txx_pause_togo
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_pause_togo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t msg_time                     : 16; /**< Amount of time remaining to backpressure
+                                                         From the higig2 physical message pause timer
+                                                         (only valid on port0) */
+	uint64_t time                         : 16; /**< Amount of time remaining to backpressure
+                                                         From the standard 802.3 pause timer */
+#else
+	uint64_t time                         : 16;
+	uint64_t msg_time                     : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< Amount of time remaining to backpressure */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
+	struct cvmx_gmxx_txx_pause_togo_s     cn52xx;
+	struct cvmx_gmxx_txx_pause_togo_s     cn52xxp1;
+	struct cvmx_gmxx_txx_pause_togo_s     cn56xx;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
+	struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+	struct cvmx_gmxx_txx_pause_togo_s     cn63xx;
+	struct cvmx_gmxx_txx_pause_togo_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
+
+/**
+ * cvmx_gmx#_tx#_pause_zero
+ *
+ * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
+ *
+ */
+union cvmx_gmxx_txx_pause_zero
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_pause_zero_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t send                         : 1;  /**< When backpressure condition clear, send PAUSE
+                                                         packet with pause_time of zero to enable the
+                                                         channel */
+#else
+	uint64_t send                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_pause_zero_s     cn30xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn31xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn38xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn38xxp2;
+	struct cvmx_gmxx_txx_pause_zero_s     cn50xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn52xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn52xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cn56xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn56xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cn58xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn58xxp1;
+	struct cvmx_gmxx_txx_pause_zero_s     cn63xx;
+	struct cvmx_gmxx_txx_pause_zero_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t;
+
+/**
+ * cvmx_gmx#_tx#_sgmii_ctl
+ */
+union cvmx_gmxx_txx_sgmii_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_sgmii_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t align                        : 1;  /**< Align the transmission to even cycles
+                                                         0 = Data can be sent on any cycle
+                                                             Possible to for the TX PCS machine to drop
+                                                             first byte of preamble
+                                                         1 = Data will only be sent on even cycles
+                                                             There will be no loss of data
+                                                         (SGMII/1000Base-X only) */
+#else
+	uint64_t align                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn52xx;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn52xxp1;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn56xx;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn56xxp1;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn63xx;
+	struct cvmx_gmxx_txx_sgmii_ctl_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
+
+/**
+ * cvmx_gmx#_tx#_slot
+ *
+ * GMX_TX_SLOT = Packet TX Slottime Counter
+ *
+ */
+union cvmx_gmxx_txx_slot
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_slot_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t slot                         : 10; /**< Slottime (refer to 802.3 to set correctly)
+                                                         10/100Mbs: 0x40
+                                                         1000Mbs:   0x200
+                                                         (SGMII/1000Base-X only) */
+#else
+	uint64_t slot                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_slot_s           cn30xx;
+	struct cvmx_gmxx_txx_slot_s           cn31xx;
+	struct cvmx_gmxx_txx_slot_s           cn38xx;
+	struct cvmx_gmxx_txx_slot_s           cn38xxp2;
+	struct cvmx_gmxx_txx_slot_s           cn50xx;
+	struct cvmx_gmxx_txx_slot_s           cn52xx;
+	struct cvmx_gmxx_txx_slot_s           cn52xxp1;
+	struct cvmx_gmxx_txx_slot_s           cn56xx;
+	struct cvmx_gmxx_txx_slot_s           cn56xxp1;
+	struct cvmx_gmxx_txx_slot_s           cn58xx;
+	struct cvmx_gmxx_txx_slot_s           cn58xxp1;
+	struct cvmx_gmxx_txx_slot_s           cn63xx;
+	struct cvmx_gmxx_txx_slot_s           cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
+
+/**
+ * cvmx_gmx#_tx#_soft_pause
+ *
+ * GMX_TX_SOFT_PAUSE = Packet TX Software Pause
+ *
+ */
+union cvmx_gmxx_txx_soft_pause
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_soft_pause_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t time                         : 16; /**< Back off the TX bus for (TIME*512) bit-times */
+#else
+	uint64_t time                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_soft_pause_s     cn30xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn31xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn38xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn38xxp2;
+	struct cvmx_gmxx_txx_soft_pause_s     cn50xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn52xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn52xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cn56xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn56xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cn58xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn58xxp1;
+	struct cvmx_gmxx_txx_soft_pause_s     cn63xx;
+	struct cvmx_gmxx_txx_soft_pause_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
+
+/**
+ * cvmx_gmx#_tx#_stat0
+ *
+ * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat0
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t xsdef                        : 32; /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive deferal
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 32; /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive collision.  Defined by
+                                                         GMX_TX_COL_ATTEMPT[LIMIT].
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t xscol                        : 32;
+	uint64_t xsdef                        : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat0_s          cn30xx;
+	struct cvmx_gmxx_txx_stat0_s          cn31xx;
+	struct cvmx_gmxx_txx_stat0_s          cn38xx;
+	struct cvmx_gmxx_txx_stat0_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat0_s          cn50xx;
+	struct cvmx_gmxx_txx_stat0_s          cn52xx;
+	struct cvmx_gmxx_txx_stat0_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cn56xx;
+	struct cvmx_gmxx_txx_stat0_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cn58xx;
+	struct cvmx_gmxx_txx_stat0_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat0_s          cn63xx;
+	struct cvmx_gmxx_txx_stat0_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
+
+/**
+ * cvmx_gmx#_tx#_stat1
+ *
+ * GMX_TX_STAT1 = GMX_TX_STATS_SCOL  / GMX_TX_STATS_MCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat1
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t scol                         : 32; /**< Number of packets sent with a single collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t mcol                         : 32; /**< Number of packets sent with multiple collisions
+                                                         but < GMX_TX_COL_ATTEMPT[LIMIT].
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t mcol                         : 32;
+	uint64_t scol                         : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat1_s          cn30xx;
+	struct cvmx_gmxx_txx_stat1_s          cn31xx;
+	struct cvmx_gmxx_txx_stat1_s          cn38xx;
+	struct cvmx_gmxx_txx_stat1_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat1_s          cn50xx;
+	struct cvmx_gmxx_txx_stat1_s          cn52xx;
+	struct cvmx_gmxx_txx_stat1_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cn56xx;
+	struct cvmx_gmxx_txx_stat1_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cn58xx;
+	struct cvmx_gmxx_txx_stat1_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat1_s          cn63xx;
+	struct cvmx_gmxx_txx_stat1_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
+
+/**
+ * cvmx_gmx#_tx#_stat2
+ *
+ * GMX_TX_STAT2 = GMX_TX_STATS_OCTS
+ *
+ *
+ * Notes:
+ * - Octect counts are the sum of all data transmitted on the wire including
+ *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
+ *   counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat2
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Number of total octets sent on the interface.
+                                                         Does not count octets from frames that were
+                                                         truncated due to collisions in halfdup mode. */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat2_s          cn30xx;
+	struct cvmx_gmxx_txx_stat2_s          cn31xx;
+	struct cvmx_gmxx_txx_stat2_s          cn38xx;
+	struct cvmx_gmxx_txx_stat2_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat2_s          cn50xx;
+	struct cvmx_gmxx_txx_stat2_s          cn52xx;
+	struct cvmx_gmxx_txx_stat2_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cn56xx;
+	struct cvmx_gmxx_txx_stat2_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cn58xx;
+	struct cvmx_gmxx_txx_stat2_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat2_s          cn63xx;
+	struct cvmx_gmxx_txx_stat2_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
+
+/**
+ * cvmx_gmx#_tx#_stat3
+ *
+ * GMX_TX_STAT3 = GMX_TX_STATS_PKTS
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat3
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pkts                         : 32; /**< Number of total frames sent on the interface.
+                                                         Does not count frames that were truncated due to
+                                                          collisions in halfdup mode. */
+#else
+	uint64_t pkts                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat3_s          cn30xx;
+	struct cvmx_gmxx_txx_stat3_s          cn31xx;
+	struct cvmx_gmxx_txx_stat3_s          cn38xx;
+	struct cvmx_gmxx_txx_stat3_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat3_s          cn50xx;
+	struct cvmx_gmxx_txx_stat3_s          cn52xx;
+	struct cvmx_gmxx_txx_stat3_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cn56xx;
+	struct cvmx_gmxx_txx_stat3_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cn58xx;
+	struct cvmx_gmxx_txx_stat3_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat3_s          cn63xx;
+	struct cvmx_gmxx_txx_stat3_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
+
+/**
+ * cvmx_gmx#_tx#_stat4
+ *
+ * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat4
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist1                        : 32; /**< Number of packets sent with an octet count of 64. */
+	uint64_t hist0                        : 32; /**< Number of packets sent with an octet count
+                                                         of < 64. */
+#else
+	uint64_t hist0                        : 32;
+	uint64_t hist1                        : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat4_s          cn30xx;
+	struct cvmx_gmxx_txx_stat4_s          cn31xx;
+	struct cvmx_gmxx_txx_stat4_s          cn38xx;
+	struct cvmx_gmxx_txx_stat4_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat4_s          cn50xx;
+	struct cvmx_gmxx_txx_stat4_s          cn52xx;
+	struct cvmx_gmxx_txx_stat4_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cn56xx;
+	struct cvmx_gmxx_txx_stat4_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cn58xx;
+	struct cvmx_gmxx_txx_stat4_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat4_s          cn63xx;
+	struct cvmx_gmxx_txx_stat4_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
+
+/**
+ * cvmx_gmx#_tx#_stat5
+ *
+ * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat5
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist3                        : 32; /**< Number of packets sent with an octet count of
+                                                         128 - 255. */
+	uint64_t hist2                        : 32; /**< Number of packets sent with an octet count of
+                                                         65 - 127. */
+#else
+	uint64_t hist2                        : 32;
+	uint64_t hist3                        : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat5_s          cn30xx;
+	struct cvmx_gmxx_txx_stat5_s          cn31xx;
+	struct cvmx_gmxx_txx_stat5_s          cn38xx;
+	struct cvmx_gmxx_txx_stat5_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat5_s          cn50xx;
+	struct cvmx_gmxx_txx_stat5_s          cn52xx;
+	struct cvmx_gmxx_txx_stat5_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cn56xx;
+	struct cvmx_gmxx_txx_stat5_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cn58xx;
+	struct cvmx_gmxx_txx_stat5_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat5_s          cn63xx;
+	struct cvmx_gmxx_txx_stat5_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
+
+/**
+ * cvmx_gmx#_tx#_stat6
+ *
+ * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat6
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist5                        : 32; /**< Number of packets sent with an octet count of
+                                                         512 - 1023. */
+	uint64_t hist4                        : 32; /**< Number of packets sent with an octet count of
+                                                         256 - 511. */
+#else
+	uint64_t hist4                        : 32;
+	uint64_t hist5                        : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat6_s          cn30xx;
+	struct cvmx_gmxx_txx_stat6_s          cn31xx;
+	struct cvmx_gmxx_txx_stat6_s          cn38xx;
+	struct cvmx_gmxx_txx_stat6_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat6_s          cn50xx;
+	struct cvmx_gmxx_txx_stat6_s          cn52xx;
+	struct cvmx_gmxx_txx_stat6_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cn56xx;
+	struct cvmx_gmxx_txx_stat6_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cn58xx;
+	struct cvmx_gmxx_txx_stat6_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat6_s          cn63xx;
+	struct cvmx_gmxx_txx_stat6_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
+
+/**
+ * cvmx_gmx#_tx#_stat7
+ *
+ * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat7
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t hist7                        : 32; /**< Number of packets sent with an octet count
+                                                         of > 1518. */
+	uint64_t hist6                        : 32; /**< Number of packets sent with an octet count of
+                                                         1024 - 1518. */
+#else
+	uint64_t hist6                        : 32;
+	uint64_t hist7                        : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat7_s          cn30xx;
+	struct cvmx_gmxx_txx_stat7_s          cn31xx;
+	struct cvmx_gmxx_txx_stat7_s          cn38xx;
+	struct cvmx_gmxx_txx_stat7_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat7_s          cn50xx;
+	struct cvmx_gmxx_txx_stat7_s          cn52xx;
+	struct cvmx_gmxx_txx_stat7_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cn56xx;
+	struct cvmx_gmxx_txx_stat7_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cn58xx;
+	struct cvmx_gmxx_txx_stat7_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat7_s          cn63xx;
+	struct cvmx_gmxx_txx_stat7_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
+
+/**
+ * cvmx_gmx#_tx#_stat8
+ *
+ * GMX_TX_STAT8 = GMX_TX_STATS_MCST  / GMX_TX_STATS_BCST
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
+ *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
+ *   as per the 802.3 frame definition.  If the system requires additional data
+ *   before the L2 header, then the MCST and BCST counters may not reflect
+ *   reality and should be ignored by software.
+ */
+union cvmx_gmxx_txx_stat8
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat8_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mcst                         : 32; /**< Number of packets sent to multicast DMAC.
+                                                         Does not include BCST packets. */
+	uint64_t bcst                         : 32; /**< Number of packets sent to broadcast DMAC.
+                                                         Does not include MCST packets. */
+#else
+	uint64_t bcst                         : 32;
+	uint64_t mcst                         : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat8_s          cn30xx;
+	struct cvmx_gmxx_txx_stat8_s          cn31xx;
+	struct cvmx_gmxx_txx_stat8_s          cn38xx;
+	struct cvmx_gmxx_txx_stat8_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat8_s          cn50xx;
+	struct cvmx_gmxx_txx_stat8_s          cn52xx;
+	struct cvmx_gmxx_txx_stat8_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cn56xx;
+	struct cvmx_gmxx_txx_stat8_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cn58xx;
+	struct cvmx_gmxx_txx_stat8_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat8_s          cn63xx;
+	struct cvmx_gmxx_txx_stat8_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
+
+/**
+ * cvmx_gmx#_tx#_stat9
+ *
+ * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+union cvmx_gmxx_txx_stat9
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stat9_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t undflw                       : 32; /**< Number of underflow packets */
+	uint64_t ctl                          : 32; /**< Number of Control packets (PAUSE flow control)
+                                                         generated by GMX.  It does not include control
+                                                         packets forwarded or generated by the PP's. */
+#else
+	uint64_t ctl                          : 32;
+	uint64_t undflw                       : 32;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stat9_s          cn30xx;
+	struct cvmx_gmxx_txx_stat9_s          cn31xx;
+	struct cvmx_gmxx_txx_stat9_s          cn38xx;
+	struct cvmx_gmxx_txx_stat9_s          cn38xxp2;
+	struct cvmx_gmxx_txx_stat9_s          cn50xx;
+	struct cvmx_gmxx_txx_stat9_s          cn52xx;
+	struct cvmx_gmxx_txx_stat9_s          cn52xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cn56xx;
+	struct cvmx_gmxx_txx_stat9_s          cn56xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cn58xx;
+	struct cvmx_gmxx_txx_stat9_s          cn58xxp1;
+	struct cvmx_gmxx_txx_stat9_s          cn63xx;
+	struct cvmx_gmxx_txx_stat9_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
+
+/**
+ * cvmx_gmx#_tx#_stats_ctl
+ *
+ * GMX_TX_STATS_CTL = TX Stats Control register
+ *
+ */
+union cvmx_gmxx_txx_stats_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_stats_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rd_clr                       : 1;  /**< Stats registers will clear on reads */
+#else
+	uint64_t rd_clr                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn30xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn31xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn38xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn38xxp2;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn50xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn52xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn52xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn56xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn56xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn58xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn58xxp1;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn63xx;
+	struct cvmx_gmxx_txx_stats_ctl_s      cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
+
+/**
+ * cvmx_gmx#_tx#_thresh
+ *
+ * Per Port
+ *
+ *
+ * GMX_TX_THRESH = Packet TX Threshold
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.  Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x100.
+ *
+ */
+union cvmx_gmxx_txx_thresh
+{
+	uint64_t u64;
+	struct cvmx_gmxx_txx_thresh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t cnt                          : 9;  /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the packet interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the packet interface and must never
+                                                         be set to zero.  This register cannot exceed the
+                                                         the TX FIFO depth which is...
+                                                          GMX_TX_PRTS==0,1:  CNT MAX = 0x100
+                                                          GMX_TX_PRTS==2  :  CNT MAX = 0x080
+                                                          GMX_TX_PRTS==3,4:  CNT MAX = 0x040 */
+#else
+	uint64_t cnt                          : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_gmxx_txx_thresh_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t cnt                          : 7;  /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the RGMII interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the RGMII interface and must never
+                                                         be set below 4.  This register cannot exceed the
+                                                         the TX FIFO depth which is 64 16B entries. */
+#else
+	uint64_t cnt                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_txx_thresh_cn30xx    cn31xx;
+	struct cvmx_gmxx_txx_thresh_s         cn38xx;
+	struct cvmx_gmxx_txx_thresh_s         cn38xxp2;
+	struct cvmx_gmxx_txx_thresh_cn30xx    cn50xx;
+	struct cvmx_gmxx_txx_thresh_s         cn52xx;
+	struct cvmx_gmxx_txx_thresh_s         cn52xxp1;
+	struct cvmx_gmxx_txx_thresh_s         cn56xx;
+	struct cvmx_gmxx_txx_thresh_s         cn56xxp1;
+	struct cvmx_gmxx_txx_thresh_s         cn58xx;
+	struct cvmx_gmxx_txx_thresh_s         cn58xxp1;
+	struct cvmx_gmxx_txx_thresh_s         cn63xx;
+	struct cvmx_gmxx_txx_thresh_s         cn63xxp1;
+};
+typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
+
+/**
+ * cvmx_gmx#_tx_bp
+ *
+ * GMX_TX_BP = Packet Interface TX BackPressure Register
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of BP is used.
+ *
+ */
+union cvmx_gmxx_tx_bp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t bp                           : 4;  /**< Per port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+	uint64_t bp                           : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_bp_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t bp                           : 3;  /**< Per port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+	uint64_t bp                           : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_tx_bp_cn30xx         cn31xx;
+	struct cvmx_gmxx_tx_bp_s              cn38xx;
+	struct cvmx_gmxx_tx_bp_s              cn38xxp2;
+	struct cvmx_gmxx_tx_bp_cn30xx         cn50xx;
+	struct cvmx_gmxx_tx_bp_s              cn52xx;
+	struct cvmx_gmxx_tx_bp_s              cn52xxp1;
+	struct cvmx_gmxx_tx_bp_s              cn56xx;
+	struct cvmx_gmxx_tx_bp_s              cn56xxp1;
+	struct cvmx_gmxx_tx_bp_s              cn58xx;
+	struct cvmx_gmxx_tx_bp_s              cn58xxp1;
+	struct cvmx_gmxx_tx_bp_s              cn63xx;
+	struct cvmx_gmxx_tx_bp_s              cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
+
+/**
+ * cvmx_gmx#_tx_clk_msk#
+ *
+ * GMX_TX_CLK_MSK = GMX Clock Select
+ *
+ */
+union cvmx_gmxx_tx_clk_mskx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_clk_mskx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t msk                          : 1;  /**< Write this bit to a 1 when switching clks */
+#else
+	uint64_t msk                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_clk_mskx_s        cn30xx;
+	struct cvmx_gmxx_tx_clk_mskx_s        cn50xx;
+};
+typedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t;
+
+/**
+ * cvmx_gmx#_tx_col_attempt
+ *
+ * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
+ *
+ */
+union cvmx_gmxx_tx_col_attempt
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_col_attempt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t limit                        : 5;  /**< Collision Attempts
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t limit                        : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_col_attempt_s     cn30xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn31xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn38xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn38xxp2;
+	struct cvmx_gmxx_tx_col_attempt_s     cn50xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn52xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn52xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cn56xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn56xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cn58xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn58xxp1;
+	struct cvmx_gmxx_tx_col_attempt_s     cn63xx;
+	struct cvmx_gmxx_tx_col_attempt_s     cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
+
+/**
+ * cvmx_gmx#_tx_corrupt
+ *
+ * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set
+ *
+ *
+ * Notes:
+ * Packets sent from PKO with the ERR wire asserted will be corrupted by
+ * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0).
+ *
+ * Corruption means that GMX will send a bad FCS value.  If GMX_TX_APPEND[FCS]
+ * is clear then no FCS is sent and the GMX cannot corrupt it.  The corrupt FCS
+ * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
+ * propagation code in XAUI mode.
+ */
+union cvmx_gmxx_tx_corrupt
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_corrupt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t corrupt                      : 4;  /**< Per port error propagation
+                                                         0=Never corrupt packets
+                                                         1=Corrupt packets with ERR */
+#else
+	uint64_t corrupt                      : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_corrupt_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t corrupt                      : 3;  /**< Per port error propagation
+                                                         0=Never corrupt packets
+                                                         1=Corrupt packets with ERR */
+#else
+	uint64_t corrupt                      : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_tx_corrupt_cn30xx    cn31xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn38xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn38xxp2;
+	struct cvmx_gmxx_tx_corrupt_cn30xx    cn50xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn52xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn52xxp1;
+	struct cvmx_gmxx_tx_corrupt_s         cn56xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn56xxp1;
+	struct cvmx_gmxx_tx_corrupt_s         cn58xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn58xxp1;
+	struct cvmx_gmxx_tx_corrupt_s         cn63xx;
+	struct cvmx_gmxx_tx_corrupt_s         cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
+
+/**
+ * cvmx_gmx#_tx_hg2_reg1
+ *
+ * Notes:
+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of
+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
+ */
+union cvmx_gmxx_tx_hg2_reg1
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_hg2_reg1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t tx_xof                       : 16; /**< TX HiGig2 message for logical link pause when any
+                                                         bit value changes
+                                                          Only write in HiGig2 mode i.e. when
+                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                          GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+	uint64_t tx_xof                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn52xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn52xxp1;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn56xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn63xx;
+	struct cvmx_gmxx_tx_hg2_reg1_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
+
+/**
+ * cvmx_gmx#_tx_hg2_reg2
+ *
+ * Notes:
+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address  of
+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
+ */
+union cvmx_gmxx_tx_hg2_reg2
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_hg2_reg2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t tx_xon                       : 16; /**< TX HiGig2 message for logical link pause when any
+                                                         bit value changes
+                                                          Only write in HiGig2 mode i.e. when
+                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                          GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+	uint64_t tx_xon                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn52xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn52xxp1;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn56xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn63xx;
+	struct cvmx_gmxx_tx_hg2_reg2_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
+
+/**
+ * cvmx_gmx#_tx_ifg
+ *
+ * GMX_TX_IFG = Packet TX Interframe Gap
+ *
+ *
+ * Notes:
+ * * Programming IFG1 and IFG2.
+ *
+ * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3
+ * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range
+ * of 4-12, and the IFG1+IFG2 sum must be 12.
+ *
+ * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3
+ * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range
+ * of 1-11, and the IFG1+IFG2 sum must be 12.
+ *
+ * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the
+ * IFG1+IFG2 sum must be 12.  IFG1[1:0] and IFG2[1:0] must be zero.
+ *
+ * For all other systems, IFG1 and IFG2 can be any value in the range of
+ * 1-15.  Allowing for a total possible IFG sum of 2-30.
+ */
+union cvmx_gmxx_tx_ifg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_ifg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ifg2                         : 4;  /**< 1/3 of the interframe gap timing (in IFG2*8 bits)
+                                                         If CRS is detected during IFG2, then the
+                                                         interFrameSpacing timer is not reset and a frame
+                                                         is transmited once the timer expires. */
+	uint64_t ifg1                         : 4;  /**< 2/3 of the interframe gap timing (in IFG1*8 bits)
+                                                         If CRS is detected during IFG1, then the
+                                                         interFrameSpacing timer is reset and a frame is
+                                                         not transmited. */
+#else
+	uint64_t ifg1                         : 4;
+	uint64_t ifg2                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_ifg_s             cn30xx;
+	struct cvmx_gmxx_tx_ifg_s             cn31xx;
+	struct cvmx_gmxx_tx_ifg_s             cn38xx;
+	struct cvmx_gmxx_tx_ifg_s             cn38xxp2;
+	struct cvmx_gmxx_tx_ifg_s             cn50xx;
+	struct cvmx_gmxx_tx_ifg_s             cn52xx;
+	struct cvmx_gmxx_tx_ifg_s             cn52xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cn56xx;
+	struct cvmx_gmxx_tx_ifg_s             cn56xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cn58xx;
+	struct cvmx_gmxx_tx_ifg_s             cn58xxp1;
+	struct cvmx_gmxx_tx_ifg_s             cn63xx;
+	struct cvmx_gmxx_tx_ifg_s             cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
+
+/**
+ * cvmx_gmx#_tx_int_en
+ *
+ * GMX_TX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
+ *
+ */
+union cvmx_gmxx_tx_int_en
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_int_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t late_col                     : 3;  /**< TX Late Collision */
+	uint64_t reserved_15_15               : 1;
+	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t reserved_11_11               : 1;
+	uint64_t xscol                        : 3;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t undflw                       : 3;  /**< TX Underflow (RGMII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 3;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t xscol                        : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t xsdef                        : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t late_col                     : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_tx_int_en_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t reserved_11_11               : 1;
+	uint64_t xscol                        : 3;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t undflw                       : 3;  /**< TX Underflow (RGMII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 3;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t xscol                        : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t xsdef                        : 3;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn31xx;
+	struct cvmx_gmxx_tx_int_en_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (PASS3 only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow (RGMII mode only) */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn38xx;
+	struct cvmx_gmxx_tx_int_en_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow (RGMII mode only) */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xxp2;
+	struct cvmx_gmxx_tx_int_en_cn30xx     cn50xx;
+	struct cvmx_gmxx_tx_int_en_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_tx_int_en_cn52xx     cn52xxp1;
+	struct cvmx_gmxx_tx_int_en_cn52xx     cn56xx;
+	struct cvmx_gmxx_tx_int_en_cn52xx     cn56xxp1;
+	struct cvmx_gmxx_tx_int_en_cn38xx     cn58xx;
+	struct cvmx_gmxx_tx_int_en_cn38xx     cn58xxp1;
+	struct cvmx_gmxx_tx_int_en_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_tx_int_en_cn63xx     cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
+
+/**
+ * cvmx_gmx#_tx_int_reg
+ *
+ * GMX_TX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
+ *
+ */
+union cvmx_gmxx_tx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_int_reg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t late_col                     : 3;  /**< TX Late Collision */
+	uint64_t reserved_15_15               : 1;
+	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t reserved_11_11               : 1;
+	uint64_t xscol                        : 3;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t undflw                       : 3;  /**< TX Underflow (RGMII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 3;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t xscol                        : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t xsdef                        : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t late_col                     : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_tx_int_reg_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t xsdef                        : 3;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t reserved_11_11               : 1;
+	uint64_t xscol                        : 3;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t undflw                       : 3;  /**< TX Underflow (RGMII mode only) */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 3;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t xscol                        : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t xsdef                        : 3;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn31xx;
+	struct cvmx_gmxx_tx_int_reg_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (PASS3 only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow (RGMII mode only) */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn38xx;
+	struct cvmx_gmxx_tx_int_reg_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral (RGMII/halfdup mode only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions (RGMII/halfdup mode only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow (RGMII mode only) */
+	uint64_t ncb_nxa                      : 1;  /**< Port address out-of-range from NCB Interface */
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t ncb_nxa                      : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xxp2;
+	struct cvmx_gmxx_tx_int_reg_cn30xx    cn50xx;
+	struct cvmx_gmxx_tx_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_gmxx_tx_int_reg_cn52xx    cn52xxp1;
+	struct cvmx_gmxx_tx_int_reg_cn52xx    cn56xx;
+	struct cvmx_gmxx_tx_int_reg_cn52xx    cn56xxp1;
+	struct cvmx_gmxx_tx_int_reg_cn38xx    cn58xx;
+	struct cvmx_gmxx_tx_int_reg_cn38xx    cn58xxp1;
+	struct cvmx_gmxx_tx_int_reg_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t ptp_lost                     : 4;  /**< A packet with a PTP request was not able to be
+                                                         sent due to XSCOL */
+	uint64_t late_col                     : 4;  /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xsdef                        : 4;  /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t xscol                        : 4;  /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t undflw                       : 4;  /**< TX Underflow */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pko_nxa                      : 1;  /**< Port address out-of-range from PKO Interface */
+#else
+	uint64_t pko_nxa                      : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t undflw                       : 4;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t xscol                        : 4;
+	uint64_t xsdef                        : 4;
+	uint64_t late_col                     : 4;
+	uint64_t ptp_lost                     : 4;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn63xx;
+	struct cvmx_gmxx_tx_int_reg_cn63xx    cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
+
+/**
+ * cvmx_gmx#_tx_jam
+ *
+ * GMX_TX_JAM = Packet TX Jam Pattern
+ *
+ */
+union cvmx_gmxx_tx_jam
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_jam_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t jam                          : 8;  /**< Jam pattern
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t jam                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_jam_s             cn30xx;
+	struct cvmx_gmxx_tx_jam_s             cn31xx;
+	struct cvmx_gmxx_tx_jam_s             cn38xx;
+	struct cvmx_gmxx_tx_jam_s             cn38xxp2;
+	struct cvmx_gmxx_tx_jam_s             cn50xx;
+	struct cvmx_gmxx_tx_jam_s             cn52xx;
+	struct cvmx_gmxx_tx_jam_s             cn52xxp1;
+	struct cvmx_gmxx_tx_jam_s             cn56xx;
+	struct cvmx_gmxx_tx_jam_s             cn56xxp1;
+	struct cvmx_gmxx_tx_jam_s             cn58xx;
+	struct cvmx_gmxx_tx_jam_s             cn58xxp1;
+	struct cvmx_gmxx_tx_jam_s             cn63xx;
+	struct cvmx_gmxx_tx_jam_s             cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
+
+/**
+ * cvmx_gmx#_tx_lfsr
+ *
+ * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
+ *
+ */
+union cvmx_gmxx_tx_lfsr
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_lfsr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t lfsr                         : 16; /**< The current state of the LFSR used to feed random
+                                                         numbers to compute truncated binary exponential
+                                                         backoff.
+                                                         (SGMII/1000Base-X half-duplex only) */
+#else
+	uint64_t lfsr                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_lfsr_s            cn30xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn31xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn38xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn38xxp2;
+	struct cvmx_gmxx_tx_lfsr_s            cn50xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn52xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn52xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cn56xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn56xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cn58xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn58xxp1;
+	struct cvmx_gmxx_tx_lfsr_s            cn63xx;
+	struct cvmx_gmxx_tx_lfsr_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
+
+/**
+ * cvmx_gmx#_tx_ovr_bp
+ *
+ * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used.
+ *
+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol
+ * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by
+ * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure
+ * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
+ * protocol.
+ */
+union cvmx_gmxx_tx_ovr_bp
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_ovr_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t tx_prt_bp                    : 16; /**< Per port BP sent to PKO
+                                                         0=Port is available
+                                                         1=Port should be back pressured
+                                                         TX_PRT_BP should not be set until
+                                                         GMX_INF_MODE[EN] has been enabled */
+	uint64_t reserved_12_31               : 20;
+	uint64_t en                           : 4;  /**< Per port Enable back pressure override */
+	uint64_t bp                           : 4;  /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t ign_full                     : 4;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 4;
+	uint64_t bp                           : 4;
+	uint64_t en                           : 4;
+	uint64_t reserved_12_31               : 20;
+	uint64_t tx_prt_bp                    : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_ovr_bp_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t en                           : 3;  /**< Per port Enable back pressure override */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t bp                           : 3;  /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t ign_full                     : 3;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t bp                           : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t en                           : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn30xx;
+	struct cvmx_gmxx_tx_ovr_bp_cn30xx     cn31xx;
+	struct cvmx_gmxx_tx_ovr_bp_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t en                           : 4;  /**< Per port Enable back pressure override */
+	uint64_t bp                           : 4;  /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+	uint64_t ign_full                     : 4;  /**< Ignore the RX FIFO full when computing BP */
+#else
+	uint64_t ign_full                     : 4;
+	uint64_t bp                           : 4;
+	uint64_t en                           : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn38xx;
+	struct cvmx_gmxx_tx_ovr_bp_cn38xx     cn38xxp2;
+	struct cvmx_gmxx_tx_ovr_bp_cn30xx     cn50xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn52xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn52xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn56xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn56xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_cn38xx     cn58xx;
+	struct cvmx_gmxx_tx_ovr_bp_cn38xx     cn58xxp1;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn63xx;
+	struct cvmx_gmxx_tx_ovr_bp_s          cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
+
+/**
+ * cvmx_gmx#_tx_pause_pkt_dmac
+ *
+ * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
+ *
+ */
+union cvmx_gmxx_tx_pause_pkt_dmac
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t dmac                         : 48; /**< The DMAC field placed is outbnd pause pkts */
+#else
+	uint64_t dmac                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn30xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn31xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn38xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn38xxp2;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn50xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn52xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn52xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn56xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn56xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn58xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn58xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn63xx;
+	struct cvmx_gmxx_tx_pause_pkt_dmac_s  cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
+
+/**
+ * cvmx_gmx#_tx_pause_pkt_type
+ *
+ * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
+ *
+ */
+union cvmx_gmxx_tx_pause_pkt_type
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_pause_pkt_type_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t type                         : 16; /**< The TYPE field placed is outbnd pause pkts */
+#else
+	uint64_t type                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn30xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn31xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn38xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn38xxp2;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn50xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn52xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn52xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn56xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn56xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn58xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn58xxp1;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn63xx;
+	struct cvmx_gmxx_tx_pause_pkt_type_s  cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
+
+/**
+ * cvmx_gmx#_tx_prts
+ *
+ * Common
+ *
+ *
+ * GMX_TX_PRTS = TX Ports
+ *
+ * Notes:
+ * * The value programmed for PRTS is the number of the highest architected
+ * port number on the interface, plus 1.  For example, if port 2 is the
+ * highest architected port, then the programmed value should be 3 since
+ * there are 3 ports in the system - 0, 1, and 2.
+ */
+union cvmx_gmxx_tx_prts
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_prts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t prts                         : 5;  /**< Number of ports allowed on the interface
+                                                         (SGMII/1000Base-X only) */
+#else
+	uint64_t prts                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_prts_s            cn30xx;
+	struct cvmx_gmxx_tx_prts_s            cn31xx;
+	struct cvmx_gmxx_tx_prts_s            cn38xx;
+	struct cvmx_gmxx_tx_prts_s            cn38xxp2;
+	struct cvmx_gmxx_tx_prts_s            cn50xx;
+	struct cvmx_gmxx_tx_prts_s            cn52xx;
+	struct cvmx_gmxx_tx_prts_s            cn52xxp1;
+	struct cvmx_gmxx_tx_prts_s            cn56xx;
+	struct cvmx_gmxx_tx_prts_s            cn56xxp1;
+	struct cvmx_gmxx_tx_prts_s            cn58xx;
+	struct cvmx_gmxx_tx_prts_s            cn58xxp1;
+	struct cvmx_gmxx_tx_prts_s            cn63xx;
+	struct cvmx_gmxx_tx_prts_s            cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
+
+/**
+ * cvmx_gmx#_tx_spi_ctl
+ *
+ * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
+ *
+ */
+union cvmx_gmxx_tx_spi_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_spi_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t tpa_clr                      : 1;  /**< TPA Clear Mode
+                                                         Clear credit counter when satisifed status */
+	uint64_t cont_pkt                     : 1;  /**< Contiguous Packet Mode
+                                                         Finish one packet before switching to another
+                                                         Cannot be set in Spi4 pass-through mode */
+#else
+	uint64_t cont_pkt                     : 1;
+	uint64_t tpa_clr                      : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_spi_ctl_s         cn38xx;
+	struct cvmx_gmxx_tx_spi_ctl_s         cn38xxp2;
+	struct cvmx_gmxx_tx_spi_ctl_s         cn58xx;
+	struct cvmx_gmxx_tx_spi_ctl_s         cn58xxp1;
+};
+typedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t;
+
+/**
+ * cvmx_gmx#_tx_spi_drain
+ *
+ * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
+ *
+ */
+union cvmx_gmxx_tx_spi_drain
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_spi_drain_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t drain                        : 16; /**< Per port drain control
+                                                         0=Normal operation
+                                                         1=GMX TX will be popped, but no valid data will
+                                                           be sent to SPX.  Credits are correctly returned
+                                                           to PKO.  STX_IGN_CAL should be set to ignore
+                                                           TPA and not stall due to back-pressure.
+                                                         (PASS3 only) */
+#else
+	uint64_t drain                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_spi_drain_s       cn38xx;
+	struct cvmx_gmxx_tx_spi_drain_s       cn58xx;
+	struct cvmx_gmxx_tx_spi_drain_s       cn58xxp1;
+};
+typedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t;
+
+/**
+ * cvmx_gmx#_tx_spi_max
+ *
+ * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
+ *
+ */
+union cvmx_gmxx_tx_spi_max
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_spi_max_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t slice                        : 7;  /**< Number of 16B blocks to transmit in a burst before
+                                                         switching to the next port. SLICE does not always
+                                                         limit the burst length transmitted by OCTEON.
+                                                         Depending on the traffic pattern and
+                                                         GMX_TX_SPI_ROUND programming, the next port could
+                                                         be the same as the current port. In this case,
+                                                         OCTEON may merge multiple sub-SLICE bursts into
+                                                         one contiguous burst that is longer than SLICE
+                                                         (as long as the burst does not cross a packet
+                                                         boundary).
+                                                         SLICE must be programmed to be >=
+                                                           GMX_TX_SPI_THRESH[THRESH]
+                                                         If SLICE==0, then the transmitter will tend to
+                                                         send the complete packet. The port will only
+                                                         switch if credits are exhausted or PKO cannot
+                                                         keep up.
+                                                         (90nm ONLY) */
+	uint64_t max2                         : 8;  /**< MAX2 (per Spi4.2 spec) */
+	uint64_t max1                         : 8;  /**< MAX1 (per Spi4.2 spec)
+                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
+#else
+	uint64_t max1                         : 8;
+	uint64_t max2                         : 8;
+	uint64_t slice                        : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_spi_max_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t max2                         : 8;  /**< MAX2 (per Spi4.2 spec) */
+	uint64_t max1                         : 8;  /**< MAX1 (per Spi4.2 spec)
+                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
+#else
+	uint64_t max1                         : 8;
+	uint64_t max2                         : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_gmxx_tx_spi_max_cn38xx    cn38xxp2;
+	struct cvmx_gmxx_tx_spi_max_s         cn58xx;
+	struct cvmx_gmxx_tx_spi_max_s         cn58xxp1;
+};
+typedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t;
+
+/**
+ * cvmx_gmx#_tx_spi_round#
+ *
+ * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
+ *
+ */
+union cvmx_gmxx_tx_spi_roundx
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_spi_roundx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t round                        : 16; /**< Which Spi ports participate in each arbitration
+                                                          round.  Each bit corresponds to a spi port
+                                                         - 0: this port will arb in this round
+                                                         - 1: this port will not arb in this round
+                                                          (90nm ONLY) */
+#else
+	uint64_t round                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_spi_roundx_s      cn58xx;
+	struct cvmx_gmxx_tx_spi_roundx_s      cn58xxp1;
+};
+typedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t;
+
+/**
+ * cvmx_gmx#_tx_spi_thresh
+ *
+ * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold
+ *
+ *
+ * Notes:
+ * Note: zero will map to 0x20
+ *
+ * This will normally creates Spi4 traffic bursts at least THRESH in length.
+ * If dclk > eclk, then this rule may not always hold and Octeon may split
+ * transfers into smaller bursts - some of which could be as short as 16B.
+ * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
+ * not a multiple of 16B.
+ */
+union cvmx_gmxx_tx_spi_thresh
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_spi_thresh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t thresh                       : 6;  /**< Transmit threshold in 16B blocks - cannot be zero
+                                                         THRESH <= TX_FIFO size   (in non-passthrough mode)
+                                                         THRESH <= TX_FIFO size-2 (in passthrough mode)
+                                                         THRESH <= GMX_TX_SPI_MAX[MAX1]
+                                                         THRESH <= GMX_TX_SPI_MAX[MAX2], if not then is it
+                                                          possible for Octeon to send a Spi4 data burst of
+                                                          MAX2 <= burst <= THRESH 16B ticks
+                                                         GMX_TX_SPI_MAX[SLICE] must be programmed to be >=
+                                                           THRESH */
+#else
+	uint64_t thresh                       : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_spi_thresh_s      cn38xx;
+	struct cvmx_gmxx_tx_spi_thresh_s      cn38xxp2;
+	struct cvmx_gmxx_tx_spi_thresh_s      cn58xx;
+	struct cvmx_gmxx_tx_spi_thresh_s      cn58xxp1;
+};
+typedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t;
+
+/**
+ * cvmx_gmx#_tx_xaui_ctl
+ */
+union cvmx_gmxx_tx_xaui_ctl
+{
+	uint64_t u64;
+	struct cvmx_gmxx_tx_xaui_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t hg_pause_hgi                 : 2;  /**< HGI Field for HW generated HiGig pause packets
+                                                         (XAUI mode only) */
+	uint64_t hg_en                        : 1;  /**< Enable HiGig Mode
+                                                         When HG_EN is set and GMX_RX_UDD_SKP[SKIP]=12
+                                                          the interface is in HiGig/HiGig+ mode and the
+                                                          following must be set:
+                                                          GMX_RX_FRM_CTL[PRE_CHK] == 0
+                                                          GMX_RX_UDD_SKP[FCSSEL] == 0
+                                                          GMX_RX_UDD_SKP[SKIP] == 12
+                                                          GMX_TX_APPEND[PREAMBLE] == 0
+                                                         When HG_EN is set and GMX_RX_UDD_SKP[SKIP]=16
+                                                          the interface is in HiGig2 mode and the
+                                                          following must be set:
+                                                          GMX_RX_FRM_CTL[PRE_CHK] == 0
+                                                          GMX_RX_UDD_SKP[FCSSEL] == 0
+                                                          GMX_RX_UDD_SKP[SKIP] == 16
+                                                          GMX_TX_APPEND[PREAMBLE] == 0
+                                                          GMX_PRT0_CBFC_CTL[RX_EN] == 0
+                                                          GMX_PRT0_CBFC_CTL[TX_EN] == 0
+                                                         (XAUI mode only) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t ls_byp                       : 1;  /**< Bypass the link status as determined by the XGMII
+                                                         receiver and set the link status of the
+                                                         transmitter to LS.
+                                                         (XAUI mode only) */
+	uint64_t ls                           : 2;  /**< Link Status
+                                                         0 = Link Ok
+                                                             Link runs normally. RS passes MAC data to PCS
+                                                         1 = Local Fault
+                                                             RS layer sends continuous remote fault
+                                                              sequences.
+                                                         2 = Remote Fault
+                                                             RS layer sends continuous idles sequences
+                                                         3 = Link Drain
+                                                             RS layer drops full packets to allow GMX and
+                                                              PKO to drain their FIFOs
+                                                         (XAUI mode only) */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t uni_en                       : 1;  /**< Enable Unidirectional Mode (IEEE Clause 66)
+                                                         (XAUI mode only) */
+	uint64_t dic_en                       : 1;  /**< Enable the deficit idle counter for IFG averaging
+                                                         (XAUI mode only) */
+#else
+	uint64_t dic_en                       : 1;
+	uint64_t uni_en                       : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t ls                           : 2;
+	uint64_t ls_byp                       : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t hg_en                        : 1;
+	uint64_t hg_pause_hgi                 : 2;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn52xx;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn52xxp1;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn56xx;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn56xxp1;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn63xx;
+	struct cvmx_gmxx_tx_xaui_ctl_s        cn63xxp1;
+};
+typedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t;
+
+/**
+ * cvmx_gmx#_xaui_ext_loopback
+ */
+union cvmx_gmxx_xaui_ext_loopback
+{
+	uint64_t u64;
+	struct cvmx_gmxx_xaui_ext_loopback_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t en                           : 1;  /**< Loopback enable
+                                                         Puts the packet interface in external loopback
+                                                         mode on the XAUI bus in which the RX lines are
+                                                         reflected on the TX lines.
+                                                         (XAUI mode only) */
+	uint64_t thresh                       : 4;  /**< Threshhold on the TX FIFO
+                                                         SW must only write the typical value.  Any other
+                                                         value will cause loopback mode not to function
+                                                         correctly.
+                                                         (XAUI mode only) */
+#else
+	uint64_t thresh                       : 4;
+	uint64_t en                           : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn52xx;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn52xxp1;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn56xx;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn56xxp1;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn63xx;
+	struct cvmx_gmxx_xaui_ext_loopback_s  cn63xxp1;
+};
+typedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-gpio-defs.h b/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
new file mode 100644
index 0000000..d0e700f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
@@ -0,0 +1,542 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-gpio-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon gpio.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_GPIO_TYPEDEFS_H__
+#define __CVMX_GPIO_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+		cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
+}
+#else
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
+}
+#else
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#endif
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
+		cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
+}
+#else
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
+#endif
+
+/**
+ * cvmx_gpio_bit_cfg#
+ */
+union cvmx_gpio_bit_cfgx
+{
+	uint64_t u64;
+	struct cvmx_gpio_bit_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t synce_sel                    : 2;  /**< Selects the QLM clock output
+                                                         x0=Normal GPIO output
+                                                         01=GPIO QLM clock selected by GPIO_CLK_QLM0
+                                                         11=GPIO QLM clock selected by GPIO_CLK_QLM1 */
+	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
+	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t int_type                     : 1;  /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+	uint64_t int_en                       : 1;  /**< Bit mask to indicate which bits to raise interrupt */
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t int_en                       : 1;
+	uint64_t int_type                     : 1;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t clk_sel                      : 2;
+	uint64_t clk_gen                      : 1;
+	uint64_t synce_sel                    : 2;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_gpio_bit_cfgx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t int_type                     : 1;  /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+	uint64_t int_en                       : 1;  /**< Bit mask to indicate which bits to raise interrupt */
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t int_en                       : 1;
+	uint64_t int_type                     : 1;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn30xx;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn31xx;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xx;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xxp2;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn50xx;
+	struct cvmx_gpio_bit_cfgx_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
+	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t int_type                     : 1;  /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+	uint64_t int_en                       : 1;  /**< Bit mask to indicate which bits to raise interrupt */
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t int_en                       : 1;
+	uint64_t int_type                     : 1;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t clk_sel                      : 2;
+	uint64_t clk_gen                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn52xx;
+	struct cvmx_gpio_bit_cfgx_cn52xx      cn52xxp1;
+	struct cvmx_gpio_bit_cfgx_cn52xx      cn56xx;
+	struct cvmx_gpio_bit_cfgx_cn52xx      cn56xxp1;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xx;
+	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cn63xx;
+	struct cvmx_gpio_bit_cfgx_s           cn63xxp1;
+};
+typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
+
+/**
+ * cvmx_gpio_boot_ena
+ */
+union cvmx_gpio_boot_ena
+{
+	uint64_t u64;
+	struct cvmx_gpio_boot_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t boot_ena                     : 4;  /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t boot_ena                     : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_gpio_boot_ena_s           cn30xx;
+	struct cvmx_gpio_boot_ena_s           cn31xx;
+	struct cvmx_gpio_boot_ena_s           cn50xx;
+};
+typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
+
+/**
+ * cvmx_gpio_clk_gen#
+ */
+union cvmx_gpio_clk_genx
+{
+	uint64_t u64;
+	struct cvmx_gpio_clk_genx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t n                            : 32; /**< Determines the frequency of the GPIO clk generator
+                                                         NOTE: Fgpio_clk = Feclk * N / 2^32
+                                                               N = (Fgpio_clk / Feclk) * 2^32
+                                                         NOTE: writing N == 0 stops the clock generator
+                                                         N  should be <= 2^31-1. */
+#else
+	uint64_t n                            : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_gpio_clk_genx_s           cn52xx;
+	struct cvmx_gpio_clk_genx_s           cn52xxp1;
+	struct cvmx_gpio_clk_genx_s           cn56xx;
+	struct cvmx_gpio_clk_genx_s           cn56xxp1;
+	struct cvmx_gpio_clk_genx_s           cn63xx;
+	struct cvmx_gpio_clk_genx_s           cn63xxp1;
+};
+typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
+
+/**
+ * cvmx_gpio_clk_qlm#
+ *
+ * Notes:
+ * Clock speed output for different modes ...
+ *
+ *                        Speed With      Speed with
+ * SERDES speed (Gbaud)   DIV=0 (MHz)     DIV=1 (MHz)
+ * **********************************************************
+ *      1.25                 62.5            31.25
+ *      2.5                 125              62.5
+ *      3.125               156.25           78.125
+ *      5.0                 250             125
+ *      6.25                312.5           156.25
+ */
+union cvmx_gpio_clk_qlmx
+{
+	uint64_t u64;
+	struct cvmx_gpio_clk_qlmx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t div                          : 1;  /**< Internal clock divider
+                                                         0=DIV2
+                                                         1=DIV4 */
+	uint64_t lane_sel                     : 2;  /**< Selects which RX lane clock from QLM2 to use as
+                                                         the GPIO internal QLMx clock.  The GPIO block can
+                                                         support upto two unique clocks to send out any
+                                                         GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
+                                                         The clock can either be a divided by 2 or divide
+                                                         by 4 of the selected RX lane clock. */
+#else
+	uint64_t lane_sel                     : 2;
+	uint64_t div                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_gpio_clk_qlmx_s           cn63xx;
+	struct cvmx_gpio_clk_qlmx_s           cn63xxp1;
+};
+typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
+
+/**
+ * cvmx_gpio_dbg_ena
+ */
+union cvmx_gpio_dbg_ena
+{
+	uint64_t u64;
+	struct cvmx_gpio_dbg_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t dbg_ena                      : 21; /**< Enable the debug port to be driven on the gpio */
+#else
+	uint64_t dbg_ena                      : 21;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_gpio_dbg_ena_s            cn30xx;
+	struct cvmx_gpio_dbg_ena_s            cn31xx;
+	struct cvmx_gpio_dbg_ena_s            cn50xx;
+};
+typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
+
+/**
+ * cvmx_gpio_int_clr
+ */
+union cvmx_gpio_int_clr
+{
+	uint64_t u64;
+	struct cvmx_gpio_int_clr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t type                         : 16; /**< Clear the interrupt rising edge detector */
+#else
+	uint64_t type                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_gpio_int_clr_s            cn30xx;
+	struct cvmx_gpio_int_clr_s            cn31xx;
+	struct cvmx_gpio_int_clr_s            cn38xx;
+	struct cvmx_gpio_int_clr_s            cn38xxp2;
+	struct cvmx_gpio_int_clr_s            cn50xx;
+	struct cvmx_gpio_int_clr_s            cn52xx;
+	struct cvmx_gpio_int_clr_s            cn52xxp1;
+	struct cvmx_gpio_int_clr_s            cn56xx;
+	struct cvmx_gpio_int_clr_s            cn56xxp1;
+	struct cvmx_gpio_int_clr_s            cn58xx;
+	struct cvmx_gpio_int_clr_s            cn58xxp1;
+	struct cvmx_gpio_int_clr_s            cn63xx;
+	struct cvmx_gpio_int_clr_s            cn63xxp1;
+};
+typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
+
+/**
+ * cvmx_gpio_rx_dat
+ */
+union cvmx_gpio_rx_dat
+{
+	uint64_t u64;
+	struct cvmx_gpio_rx_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t dat                          : 24; /**< GPIO Read Data */
+#else
+	uint64_t dat                          : 24;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_gpio_rx_dat_s             cn30xx;
+	struct cvmx_gpio_rx_dat_s             cn31xx;
+	struct cvmx_gpio_rx_dat_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dat                          : 16; /**< GPIO Read Data */
+#else
+	uint64_t dat                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn38xxp2;
+	struct cvmx_gpio_rx_dat_s             cn50xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn52xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn52xxp1;
+	struct cvmx_gpio_rx_dat_cn38xx        cn56xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn56xxp1;
+	struct cvmx_gpio_rx_dat_cn38xx        cn58xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn58xxp1;
+	struct cvmx_gpio_rx_dat_cn38xx        cn63xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn63xxp1;
+};
+typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
+
+/**
+ * cvmx_gpio_tx_clr
+ */
+union cvmx_gpio_tx_clr
+{
+	uint64_t u64;
+	struct cvmx_gpio_tx_clr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t clr                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '0'. When read, CLR returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t clr                          : 24;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_gpio_tx_clr_s             cn30xx;
+	struct cvmx_gpio_tx_clr_s             cn31xx;
+	struct cvmx_gpio_tx_clr_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t clr                          : 16; /**< Bit mask to indicate which bits to drive to '0'. */
+#else
+	uint64_t clr                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn38xxp2;
+	struct cvmx_gpio_tx_clr_s             cn50xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn52xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn52xxp1;
+	struct cvmx_gpio_tx_clr_cn38xx        cn56xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn56xxp1;
+	struct cvmx_gpio_tx_clr_cn38xx        cn58xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_clr_cn38xx        cn63xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn63xxp1;
+};
+typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
+
+/**
+ * cvmx_gpio_tx_set
+ */
+union cvmx_gpio_tx_set
+{
+	uint64_t u64;
+	struct cvmx_gpio_tx_set_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t set                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '1'. When read, SET returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t set                          : 24;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_gpio_tx_set_s             cn30xx;
+	struct cvmx_gpio_tx_set_s             cn31xx;
+	struct cvmx_gpio_tx_set_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t set                          : 16; /**< Bit mask to indicate which bits to drive to '1'. */
+#else
+	uint64_t set                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn38xxp2;
+	struct cvmx_gpio_tx_set_s             cn50xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn52xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn52xxp1;
+	struct cvmx_gpio_tx_set_cn38xx        cn56xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn56xxp1;
+	struct cvmx_gpio_tx_set_cn38xx        cn58xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_set_cn38xx        cn63xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn63xxp1;
+};
+typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
+
+/**
+ * cvmx_gpio_xbit_cfg#
+ */
+union cvmx_gpio_xbit_cfgx
+{
+	uint64_t u64;
+	struct cvmx_gpio_xbit_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_gpio_xbit_cfgx_s          cn30xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn31xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn50xx;
+};
+typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-gpio.h b/sys/contrib/octeon-sdk/cvmx-gpio.h
index ffbd815..f728933 100644
--- a/sys/contrib/octeon-sdk/cvmx-gpio.h
+++ b/sys/contrib/octeon-sdk/cvmx-gpio.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * General Purpose IO interface.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_GPIO_H__
@@ -56,7 +58,7 @@
 extern "C" {
 #endif
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-gpio-defs.h */
 
 /**
  * Clear the interrupt rising edge detector for the supplied
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.c b/sys/contrib/octeon-sdk/cvmx-helper-board.c
index 4efc825..bbac3e7 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-board.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-board.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,21 +42,37 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 41946 $<hr>
+ * <hr>$Revision: 49627 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-bootinfo.h>
+#include <asm/octeon/cvmx-smix-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-mdio.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#include <asm/octeon/cvmx-twsi.h>
+#else
 #include "cvmx.h"
 #include "cvmx-app-init.h"
-#include "cvmx-mdio.h"
 #include "cvmx-sysinfo.h"
+#include "cvmx-twsi.h"
+#include "cvmx-mdio.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-util.h"
 #include "cvmx-helper-board.h"
+#endif
 
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
@@ -119,6 +136,17 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return ipd_port - 16;
             else
                 return -1;
+        case CVMX_BOARD_TYPE_LANAI2_A:
+            if (ipd_port == 0)
+                return 0;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_LANAI2_U:
+        case CVMX_BOARD_TYPE_LANAI2_G:
+            if (ipd_port == 0)
+                return 0x1c;
+            else
+                return -1;
         case CVMX_BOARD_TYPE_KODAMA:
         case CVMX_BOARD_TYPE_EBH3100:
         case CVMX_BOARD_TYPE_HIKARI:
@@ -144,9 +172,17 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBH3000:
             /* Board has dual SPI4 and no PHYs */
             return -1;
+        case CVMX_BOARD_TYPE_EBT5810:
+            /* Board has 10g PHYs hooked up to the MII controller on the
+            ** IXF18201 MAC.  The 10G PHYS use clause 45 MDIO which the CN58XX
+            ** does not support. All MII accesses go through the IXF part. */
+            return -1;
         case CVMX_BOARD_TYPE_EBH5200:
         case CVMX_BOARD_TYPE_EBH5201:
         case CVMX_BOARD_TYPE_EBT5200:
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
             /* Board has 4 SGMII ports. The PHYs start right after the MII
                 ports MII0 = 0, MII1 = 1, SGMII = 2-5 */
             if ((ipd_port >= 0) && (ipd_port < 4))
@@ -155,12 +191,56 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return -1;
         case CVMX_BOARD_TYPE_EBH5600:
         case CVMX_BOARD_TYPE_EBH5601:
+        case CVMX_BOARD_TYPE_EBH5610:
+            /* Board has 1 management port */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 0;
             /* Board has 8 SGMII ports. 4 connect out, two connect to a switch,
                 and 2 loop to each other */
             if ((ipd_port >= 0) && (ipd_port < 4))
                 return ipd_port+1;
             else
                 return -1;
+        case CVMX_BOARD_TYPE_EBB5600:
+            {
+                static unsigned char qlm_switch_addr = 0;
+
+                /* Board has 1 management port */
+                if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                    return 0;
+
+                /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */
+                if ((ipd_port >= 0) && (ipd_port < 4))
+                {
+                    if (qlm_switch_addr != 0x3)
+                    {
+                        qlm_switch_addr = 0x3;  /* QLM1 */
+                        cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                        cvmx_wait_usec(11000); /* Let the write complete */
+                    }
+                    return ipd_port+1 + (1<<8);
+                }
+                else if ((ipd_port >= 16) && (ipd_port < 20))
+                {
+                    if (qlm_switch_addr != 0xC)
+                    {
+                        qlm_switch_addr = 0xC;  /* QLM3 */
+                        cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                        cvmx_wait_usec(11000); /* Let the write complete */
+                    }
+                    return ipd_port-16+1 + (1<<8);
+                }
+                else
+                    return -1;
+            }
+        case CVMX_BOARD_TYPE_EBB6300:
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
+            if ((ipd_port >= 0) && (ipd_port < 4))
+                return ipd_port + 1 + (1<<8);
+            else
+                return -1;
         case CVMX_BOARD_TYPE_CUST_NB5:
             if (ipd_port == 2)
                 return 4;
@@ -172,8 +252,17 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return ipd_port - 16 + 1;
             else
                 return -1;
+        case CVMX_BOARD_TYPE_NIC_XLE_10G:
+            return -1;  /* We don't use clause 45 MDIO for anything */
         case CVMX_BOARD_TYPE_BBGW_REF:
             return -1;  /* No PHYs are connected to Octeon, everything is through switch */
+	case CVMX_BOARD_TYPE_CUST_WSX16:
+		if (ipd_port >= 0 && ipd_port <= 3)
+			return ipd_port;
+		else if (ipd_port >= 16 && ipd_port <= 19)
+			return ipd_port - 16 + 4;
+		else
+			return -1;
 
 	/* Private vendor-defined boards.  */
 #if defined(OCTEON_VENDOR_LANNER)
@@ -203,10 +292,13 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
     }
 
     /* Some unknown board. Somebody forgot to update this function... */
-    cvmx_dprintf("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
-                 cvmx_sysinfo_get()->board_type);
+    cvmx_dprintf("%s: Unknown board type %d\n",
+                 __FUNCTION__, cvmx_sysinfo_get()->board_type);
     return -1;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_board_get_mii_address);
+#endif
 
 
 /**
@@ -252,6 +344,10 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
             result.s.full_duplex = 1;
             result.s.speed = 1000;
             return result;
+        case CVMX_BOARD_TYPE_LANAI2_A:
+        case CVMX_BOARD_TYPE_LANAI2_U:
+        case CVMX_BOARD_TYPE_LANAI2_G:
+            break;
         case CVMX_BOARD_TYPE_EBH3100:
         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
@@ -266,6 +362,25 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
             }
             /* Fall through to the generic code below */
             break;
+        case CVMX_BOARD_TYPE_EBH5600:
+        case CVMX_BOARD_TYPE_EBH5601:
+        case CVMX_BOARD_TYPE_EBH5610:
+            /* Board has 1 management ports */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                is_broadcom_phy = 1;
+            break;
+        case CVMX_BOARD_TYPE_EBH5200:
+        case CVMX_BOARD_TYPE_EBH5201:
+        case CVMX_BOARD_TYPE_EBT5200:
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                is_broadcom_phy = 1;
+            break;
+        case CVMX_BOARD_TYPE_EBB6300:   /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))
+                && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1)
+                is_broadcom_phy = 1;
+            break;
         case CVMX_BOARD_TYPE_CUST_NB5:
             /* Port 1 on these boards is always Gigabit */
             if (ipd_port == 1)
@@ -281,7 +396,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
         case CVMX_BOARD_TYPE_BBGW_REF:
             /* Port 1 on these boards is always Gigabit */
             if (ipd_port == 2)
-            {   
+            {
                 /* Port 2 is not hooked up */
                 result.u64 = 0;
                 return result;
@@ -457,14 +572,15 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 
 /**
  * This function as a board specific method of changing the PHY
- * speed, duplex, and auto-negotiation. This programs the PHY and
+ * speed, duplex, and autonegotiation. This programs the PHY and
  * not Octeon. This can be used to force Octeon's links to
  * specific settings.
  *
  * @param phy_addr  The address of the PHY to program
- * @param enable_autoneg
- *                  Non zero if you want to enable auto-negotiation.
- * @param link_info Link speed to program. If the speed is zero and auto-negotiation
+ * @param link_flags
+ *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
+ *                  enable/disable to maintain backward compatibility.
+ * @param link_info Link speed to program. If the speed is zero and autonegotiation
  *                  is enabled, all possible negotiation speeds are advertised.
  *
  * @return Zero on success, negative on failure
@@ -595,9 +711,9 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
  * support and should return the number of actual ports on the
  * board.
  *
- * This function must be modifed for every new Octeon board.
+ * This function must be modified for every new Octeon board.
  * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
+ * data to determine board types and revisions. It relies on the
  * fact that every Octeon board receives a unique board type
  * enumeration from the bootloader.
  *
@@ -613,6 +729,9 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+        case CVMX_BOARD_TYPE_LANAI2_A:
+        case CVMX_BOARD_TYPE_LANAI2_U:
+        case CVMX_BOARD_TYPE_LANAI2_G:
             if (interface == 0)
                 return 2;
 	    break;
@@ -630,6 +749,15 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
             if (interface == 1)
                 return 0;
 	    break;
+        case CVMX_BOARD_TYPE_EBB5600:
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+            if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_PICMG)
+                return 0;
+#endif
+	    break;
+        case CVMX_BOARD_TYPE_EBT5810:
+            return 1;  /* Two ports on each SPI: 1 hooked to MAC, 1 loopback
+                       ** Loopback disabled by default. */
 #if defined(OCTEON_VENDOR_LANNER)
 	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
 	    if (interface == 1)
@@ -671,9 +799,17 @@ int __cvmx_helper_board_hardware_enable(int interface)
             cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0xc);
         }
     }
+    else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_LANAI2_U)
+    {
+        if (interface == 0)
+        {
+            cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 16);
+            cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 16);
+        }
+    }
     else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3010_EVB_HS5)
     {
-        /* Broadcom PHYs require differnet ASX clocks. Unfortunately
+        /* Broadcom PHYs require different ASX clocks. Unfortunately
             many customer don't define a new board Id and simply
             mangle the CN3010_EVB_HS5 */
         if (interface == 0)
@@ -706,10 +842,22 @@ int __cvmx_helper_board_hardware_enable(int interface)
     return 0;
 }
 
+
+/**
+ * @INTERNAL
+ * Gets the clock type used for the USB block based on board type.
+ * Used by the USB code for auto configuration of clock type.
+ *
+ * @return USB clock type enumeration
+ */
 cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 {
-    switch (cvmx_sysinfo_get()->board_type) {
-    case CVMX_BOARD_TYPE_BBGW_REF:
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_BBGW_REF:
+        case CVMX_BOARD_TYPE_LANAI2_A:
+        case CVMX_BOARD_TYPE_LANAI2_U:
+        case CVMX_BOARD_TYPE_LANAI2_G:
 #if defined(OCTEON_VENDOR_LANNER)
     case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
 #endif
@@ -718,9 +866,23 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
     return USB_CLOCK_TYPE_REF_48;
 }
 
+
+/**
+ * @INTERNAL
+ * Adjusts the number of available USB ports on Octeon based on board
+ * specifics.
+ *
+ * @param supported_ports expected number of ports based on chip type;
+ *
+ *
+ * @return number of available usb ports, based on board specifics.
+ *         Return value is supported_ports if function does not
+ *         override.
+ */
 int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
 {
-    switch (cvmx_sysinfo_get()->board_type) {
+    switch (cvmx_sysinfo_get()->board_type)
+    {
         case CVMX_BOARD_TYPE_NIC_XLE_4G:
             return 0;
     }
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.h b/sys/contrib/octeon-sdk/cvmx-helper-board.h
index fd07fc7..2e7dc31 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-board.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-board.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 41946 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_BOARD_H__
 #define __CVMX_HELPER_BOARD_H__
@@ -73,6 +75,10 @@ typedef enum {
 } cvmx_helper_board_set_phy_link_flags_types_t;
 
 
+/* Fake IPD port, the RGMII/MII interface may use different PHY, use this
+   macro to return appropriate MIX address to read the PHY. */
+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
+
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
  * pointer. It is meant to allow customization of the process of
@@ -89,9 +95,9 @@ extern cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port);
  * connected to this port. On chips supporting multiple MII
  * busses the bus number is encoded in bits <15:8>.
  *
- * This function must be modifed for every new Octeon board.
+ * This function must be modified for every new Octeon board.
  * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
+ * data to determine board types and revisions. It relies on the
  * fact that every Octeon board receives a unique board type
  * enumeration from the bootloader.
  *
@@ -110,7 +116,7 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port);
  * @param phy_addr  The address of the PHY to program
  * @param link_flags
  *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
- *                  enable/disable to maintain backware compatability.
+ *                  enable/disable to maintain backward compatibility.
  * @param link_info Link speed to program. If the speed is zero and autonegotiation
  *                  is enabled, all possible negotiation speeds are advertised.
  *
@@ -126,9 +132,9 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
  * and are handled by the fall through case. This function must be
  * updated for boards that don't have the normal Marvell PHYs.
  *
- * This function must be modifed for every new Octeon board.
+ * This function must be modified for every new Octeon board.
  * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
+ * data to determine board types and revisions. It relies on the
  * fact that every Octeon board receives a unique board type
  * enumeration from the bootloader.
  *
@@ -149,9 +155,9 @@ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
  * support and should return the number of actual ports on the
  * board.
  *
- * This function must be modifed for every new Octeon board.
+ * This function must be modified for every new Octeon board.
  * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
+ * data to determine board types and revisions. It relies on the
  * fact that every Octeon board receives a unique board type
  * enumeration from the bootloader.
  *
@@ -194,9 +200,9 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
  * @INTERNAL
  * Adjusts the number of available USB ports on Octeon based on board
  * specifics.
- * 
+ *
  * @param supported_ports expected number of ports based on chip type;
- * 
+ *
  *
  * @return number of available usb ports, based on board specifics.
  *         Return value is supported_ports if function does not
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h b/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
index 7fd976b..70a2ca0 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -49,7 +51,7 @@
  * function properly. It either supplies a default or fails
  * compile if a define is incorrect.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_CHECK_DEFINES_H__
 #define __CVMX_HELPER_CHECK_DEFINES_H__
@@ -68,13 +70,6 @@
 #warning WARNING: default CVMX_HELPER_NOT_FIRST_MBUFF_SKIP used.  Defaults deprecated, please set in executive-config.h
 #endif
 
-/* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
-    for all input ports. Override in executive-config.h */
-#ifndef CVMX_HELPER_ENABLE_BACK_PRESSURE
-#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
-#warning WARNING: default CVMX_HELPER_ENABLE_BACK_PRESSURE used.  Defaults deprecated, please set in executive-config.h
-#endif
-
 /* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
     function. Once it is enabled the hardware starts accepting packets. You
     might want to skip the IPD enable if configuration changes are need
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-errata.c b/sys/contrib/octeon-sdk/cvmx-helper-errata.c
index 10bcd08..d226acd 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-errata.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-errata.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -49,20 +51,35 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 42150 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#endif
+
 #include "cvmx.h"
+
 #include "cvmx-fpa.h"
 #include "cvmx-pip.h"
 #include "cvmx-pko.h"
 #include "cvmx-ipd.h"
-#include "cvmx-asx.h"
 #include "cvmx-gmx.h"
 #include "cvmx-spi.h"
 #include "cvmx-pow.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-helper.h"
-#include "cvmx-helper-util.h"
+#include "cvmx-helper-jtag.h"
+#endif
+
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
@@ -193,7 +210,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
         } while ((work == NULL) && (retry_cnt > 0));
 
         if (!retry_cnt)
-            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occured.\n");
+            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred.\n");
 
 
         /* Free packet */
@@ -226,34 +243,6 @@ fix_ipd_exit:
 
 
 /**
- * @INTERNAL
- * Workaround ASX setup errata with CN38XX pass1
- *
- * @param interface Interface to setup
- * @param port      Port to setup (0..3)
- * @param cpu_clock_hz
- *                  Chip frequency in Hertz
- *
- * @return Zero on success, negative on failure
- */
-int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
-{
-    /* Set hi water mark as per errata GMX-4 */
-    if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
-        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
-    else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
-        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
-    else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
-        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
-    else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
-        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
-    else
-        cvmx_dprintf("Illegal clock frequency (%d). CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
-    return 0;
-}
-
-
-/**
  * This function needs to be called on all Octeon chips with
  * errata PKI-100.
  *
@@ -334,4 +323,3 @@ void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
     }
     cvmx_helper_qlm_jtag_update(qlm);
 }
-
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-errata.h b/sys/contrib/octeon-sdk/cvmx-helper-errata.h
index 9982dd8..3d94d1a 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-errata.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-errata.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -49,7 +51,7 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
 #ifndef __CVMX_HELPER_ERRATA_H__
 #define __CVMX_HELPER_ERRATA_H__
@@ -64,19 +66,6 @@
 extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
 
 /**
- * @INTERNAL
- * Workaround ASX setup errata with CN38XX pass1
- *
- * @param interface Interface to setup
- * @param port      Port to setup (0..3)
- * @param cpu_clock_hz
- *                  Chip frequency in Hertz
- *
- * @return Zero on success, negative on failure
- */
-extern int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz);
-
-/**
  * This function needs to be called on all Octeon chips with
  * errata PKI-100.
  *
@@ -101,5 +90,4 @@ extern int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);
  * @param qlm    QLM to disable 2nd order CDR for.
  */
 extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
-
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-fpa.c b/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
index 4df6ecc..18bcdb6 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-bootmem.h"
@@ -122,7 +124,7 @@ static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
  * @param tim_size Should always be CVMX_FPA_TIMER_POOL_SIZE
  * @param tim_buffers
  *                 TIM ring buffer command queues. At least two per timer bucket
- *                 is recommened.
+ *                 is recommended.
  * @param dfa_pool Should always be CVMX_FPA_DFA_POOL
  * @param dfa_size Should always be CVMX_FPA_DFA_POOL_SIZE
  * @param dfa_buffers
@@ -205,7 +207,7 @@ static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, int pip_buff
  *               each PKO queue.
  * @param tim_buffers
  *               TIM ring buffer command queues. At least two per timer bucket
- *               is recommened.
+ *               is recommended.
  * @param dfa_buffers
  *               DFA command buffer. A relatively small (32 for example)
  *               number should work.
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-fpa.h b/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
index 24f622a..f7fd583 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_H_FPA__
 #define __CVMX_HELPER_H_FPA__
@@ -68,7 +70,7 @@
  *               each PKO queue.
  * @param tim_buffers
  *               TIM ring buffer command queues. At least two per timer bucket
- *               is recommened.
+ *               is recommended.
  * @param dfa_buffers
  *               DFA command buffer. A relatively small (32 for example)
  *               number should work.
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-jtag.c b/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
new file mode 100644
index 0000000..57971f6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
@@ -0,0 +1,225 @@
+
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper utilities for qlm_jtag.
+ *
+ * <hr>$Revision: 42480 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#endif
+#include "cvmx.h"
+#if defined(__FreeBSD__) && defined(_KERNEL)
+#include "cvmx-helper-jtag.h"
+#endif
+#endif
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+void cvmx_helper_qlm_jtag_init(void)
+{
+    cvmx_ciu_qlm_jtgc_t jtgc;
+    int clock_div = 0;
+    int divisor = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / (25 * 1000000);
+    divisor = (divisor-1)>>2;
+    /* Convert the divisor into a power of 2 shift */
+    while (divisor)
+    {
+        clock_div++;
+        divisor>>=1;
+    }
+
+    /* Clock divider for QLM JTAG operations.  sclk is divided by 2^(CLK_DIV + 2) */
+    jtgc.u64 = 0;
+    jtgc.s.clk_div = clock_div;
+    jtgc.s.mux_sel = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        jtgc.s.bypass = 0x3;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        jtgc.s.bypass = 0x7;
+    else
+        jtgc.s.bypass = 0xf;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+}
+
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain for
+ * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain
+ * for CN63XX is 4 * 300 bits long, or 1200.
+ *
+ * @param qlm    QLM to shift value into
+ * @param bits   Number of bits to shift in (1-32).
+ * @param data   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * @return The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
+{
+    cvmx_ciu_qlm_jtgc_t jtgc;
+    cvmx_ciu_qlm_jtgd_t jtgd;
+
+    jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+    jtgc.s.mux_sel = qlm;
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+        jtgc.s.bypass = 1<<qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+
+    jtgd.u64 = 0;
+    jtgd.s.shift = 1;
+    jtgd.s.shft_cnt = bits-1;
+    jtgd.s.shft_reg = data;
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        jtgd.s.select = 1 << qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+    do
+    {
+        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    } while (jtgd.s.shift);
+    return jtgd.s.shft_reg >> (32-bits);
+}
+
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @param qlm    QLM to shift zeros into
+ * @param bits
+ */
+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
+{
+    while (bits > 0)
+    {
+        int n = bits;
+        if (n > 32)
+            n = 32;
+        cvmx_helper_qlm_jtag_shift(qlm, n, 0);
+        bits -= n;
+    }
+}
+
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in the proper number of bits into the
+ * JTAG chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @param qlm    QLM to program
+ */
+void cvmx_helper_qlm_jtag_update(int qlm)
+{
+    cvmx_ciu_qlm_jtgc_t jtgc;
+    cvmx_ciu_qlm_jtgd_t jtgd;
+
+    jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+    jtgc.s.mux_sel = qlm;
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+        jtgc.s.bypass = 1<<qlm;
+
+    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+
+    /* Update the new data */
+    jtgd.u64 = 0;
+    jtgd.s.update = 1;
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        jtgd.s.select = 1 << qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+    do
+    {
+        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    } while (jtgd.s.update);
+}
+
+
+/**
+ * Load the QLM JTAG chain with data from all lanes of the QLM.
+ *
+ * @param qlm    QLM to program
+ */
+void cvmx_helper_qlm_jtag_capture(int qlm)
+{
+    cvmx_ciu_qlm_jtgc_t jtgc;
+    cvmx_ciu_qlm_jtgd_t jtgd;
+
+    jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+    jtgc.s.mux_sel = qlm;
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+        jtgc.s.bypass = 1<<qlm;
+
+    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+
+    jtgd.u64 = 0;
+    jtgd.s.capture = 1;
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        jtgd.s.select = 1 << qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+    do
+    {
+        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    } while (jtgd.s.capture);
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-jtag.h b/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
new file mode 100644
index 0000000..dae1c38
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
@@ -0,0 +1,106 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ *  Helper utilities for qlm_jtag.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_HELPER_JTAG_H__
+#define __CVMX_HELPER_JTAG_H__
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+extern void cvmx_helper_qlm_jtag_init(void);
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain for
+ * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain
+ * for CN63XX is 4 * 300 bits long, or 1200.
+ *
+ * @param qlm    QLM to shift value into
+ * @param bits   Number of bits to shift in (1-32).
+ * @param data   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * @return The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @param qlm    QLM to shift zeros into
+ * @param bits
+ */
+extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in the proper number of bits into the
+ * JTAG chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @param qlm    QLM to program
+ */
+extern void cvmx_helper_qlm_jtag_update(int qlm);
+
+/**
+ * Load the QLM JTAG chain with data from all lanes of the QLM.
+ *
+ * @param qlm    QLM to program
+ */
+extern void cvmx_helper_qlm_jtag_capture(int qlm);
+
+#endif  /* __CVMX_HELPER_JTAG_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-loop.c b/sys/contrib/octeon-sdk/cvmx-helper-loop.c
index 7a8c667..c12ec59 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-loop.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-loop.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,19 +42,38 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for LOOP initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-helper.h>
+#endif
+#include <asm/octeon/cvmx-pip-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 #include "cvmx.h"
 #include "cvmx-helper.h"
-
-
+#endif
+#else
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#endif
+#endif
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 /**
  * @INTERNAL
  * Probe a LOOP interface and determine the number of ports
@@ -74,7 +94,7 @@ int __cvmx_helper_loop_probe(int interface)
         frames don't get errors */
     for (port=0; port<num_ports; port++)
     {
-        cvmx_pip_port_cfg_t port_cfg;
+        cvmx_pip_prt_cfgx_t port_cfg;
         int ipd_port = cvmx_helper_get_ipd_port(interface, port);
         port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
         port_cfg.s.maxerr_en = 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-loop.h b/sys/contrib/octeon-sdk/cvmx-helper-loop.h
index 42b2e15..30acdb6 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-loop.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-loop.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for LOOP initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_LOOP_H__
 #define __CVMX_HELPER_LOOP_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-npi.c b/sys/contrib/octeon-sdk/cvmx-helper-npi.c
index bfdcf40..72629bb 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-npi.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-npi.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,39 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for NPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-helper.h>
+#endif
+#include <asm/octeon/cvmx-pip-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#endif
+#else
 #include "cvmx.h"
 #include "cvmx-helper.h"
+#endif
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 /**
  * @INTERNAL
  * Probe a NPI interface and determine the number of ports
@@ -72,6 +94,8 @@ int __cvmx_helper_npi_probe(int interface)
         return 4; /* The packet engines didn't exist before pass 2 */
     else if (OCTEON_IS_MODEL(OCTEON_CN52XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
         return 4; /* The packet engines didn't exist before pass 2 */
+    else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        return 4;
 #if 0
     /* Technically CN30XX, CN31XX, and CN50XX contain packet engines, but
         nobody ever uses them. Since this is the case, we disable them here */
@@ -105,7 +129,7 @@ int __cvmx_helper_npi_enable(int interface)
         int port;
         for (port=0; port<num_ports; port++)
         {
-            cvmx_pip_port_cfg_t port_cfg;
+            cvmx_pip_prt_cfgx_t port_cfg;
             int ipd_port = cvmx_helper_get_ipd_port(interface, port);
             port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
             port_cfg.s.maxerr_en = 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-npi.h b/sys/contrib/octeon-sdk/cvmx-helper-npi.h
index c249e07..3f43ad4 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-npi.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-npi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for NPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_NPI_H__
 #define __CVMX_HELPER_NPI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
index 81a790a..e62c46f 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,22 +42,54 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for RGMII/GMII/MII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 42417 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#endif
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
+
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 #include "cvmx.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-mdio.h"
 #include "cvmx-pko.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
+#endif
+#else
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-mdio.h"
+#include "cvmx-pko.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+#endif
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 /**
  * @INTERNAL
  * Probe RGMII ports and determine the number present
@@ -153,7 +186,6 @@ int __cvmx_helper_rgmii_enable(int interface)
 {
     int num_ports = cvmx_helper_ports_on_interface(interface);
     int port;
-    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     cvmx_gmxx_inf_mode_t mode;
     cvmx_asxx_tx_prt_en_t asx_tx;
     cvmx_asxx_rx_prt_en_t asx_rx;
@@ -180,17 +212,12 @@ int __cvmx_helper_rgmii_enable(int interface)
         /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
             __cvmx_helper_setup_gmx() */
 
-        if (cvmx_octeon_is_pass1())
-            __cvmx_helper_errata_asx_pass1(interface, port, sys_info_ptr->cpu_clock_hz);
-        else
-        {
-            /* Configure more flexible RGMII preamble checking. Pass 1 doesn't
-                support this feature. */
-            cvmx_gmxx_rxx_frm_ctl_t frm_ctl;
-            frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface));
-            frm_ctl.s.pre_free = 1;  /* New field, so must be compile time */
-            cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
-        }
+        /* Configure more flexible RGMII preamble checking. Pass 1 doesn't
+           support this feature. */
+        cvmx_gmxx_rxx_frm_ctl_t frm_ctl;
+        frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface));
+        frm_ctl.s.pre_free = 1;  /* New field, so must be compile time */
+        cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
 
         /* Each pause frame transmitted will ask for about 10M bit times
             before resume.  If buffer space comes available before that time
@@ -249,7 +276,6 @@ int __cvmx_helper_rgmii_enable(int interface)
         gmx_cfg.s.en = 1;
         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64);
     }
-
     return 0;
 }
 
@@ -360,9 +386,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info
     cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 
     /* Set full/half duplex */
-    if (cvmx_octeon_is_pass1())
-        new_gmx_cfg.s.duplex = 1;   /* Half duplex is broken for 38XX Pass 1 */
-    else if (!link_info.s.link_up)
+    if (!link_info.s.link_up)
         new_gmx_cfg.s.duplex = 1;   /* Force full duplex on down links */
     else
         new_gmx_cfg.s.duplex = link_info.s.full_duplex;
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
index 2560adc..5526370 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for RGMII/GMII/MII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_RGMII_H__
 #define __CVMX_HELPER_RGMII_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
index 3ca5662..a3a8b16 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,21 +42,49 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for SGMII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 42417 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-clock.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#endif
+#include <asm/octeon/cvmx-pcsx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-ciu-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-mdio.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+#endif
+#else
 #include "cvmx.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-mdio.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
+#endif
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 /**
  * @INTERNAL
  * Perform initialization required only once for an SGMII port.
@@ -67,8 +96,8 @@
  */
 static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
 {
-    const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
-    cvmx_pcsx_miscx_ctl_reg_t pcs_misc_ctl_reg;
+    const uint64_t clock_mhz = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / 1000000;
+    cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
     cvmx_pcsx_linkx_timer_count_reg_t pcsx_linkx_timer_count_reg;
     cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
 
@@ -80,9 +109,9 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
     /* Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the appropriate
         value. 1000BASE-X specifies a 10ms interval. SGMII specifies a 1.6ms
         interval. */
-    pcs_misc_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+    pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
     pcsx_linkx_timer_count_reg.u64 = cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
-    if (pcs_misc_ctl_reg.s.mode)
+    if (pcsx_miscx_ctl_reg.s.mode)
     {
         /* 1000BASE-X */
         pcsx_linkx_timer_count_reg.s.count = (10000ull * clock_mhz) >> 10;
@@ -100,7 +129,7 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
         In SGMII PHY mode, tx_Config_Reg<D15:D0> is PCS*_SGM*_AN_ADV_REG.
         In SGMII MAC mode, tx_Config_Reg<D15:D0> is the fixed value 0x4001, so
         this step can be skipped. */
-    if (pcs_misc_ctl_reg.s.mode)
+    if (pcsx_miscx_ctl_reg.s.mode)
     {
         /* 1000BASE-X */
         cvmx_pcsx_anx_adv_reg_t pcsx_anx_adv_reg;
@@ -113,8 +142,6 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
     }
     else
     {
-        cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
-        pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
         if (pcsx_miscx_ctl_reg.s.mac_phy)
         {
             /* PHY Mode */
@@ -253,7 +280,10 @@ static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index
             gmxx_prtx_cfg.s.slottime = 1;
             pcsx_miscx_ctl_reg.s.samp_pt = 1;
             cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
-            cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
+	    if (gmxx_prtx_cfg.s.duplex)
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); // full duplex
+	    else
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); // half duplex
             break;
         default:
             break;
@@ -291,6 +321,17 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
 {
     int index;
 
+    /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
+    {
+        cvmx_ciu_qlm2_t ciu_qlm;
+        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
+        ciu_qlm.s.txbypass = 1;
+        ciu_qlm.s.txdeemph = 0xf;
+        ciu_qlm.s.txmargin = 0xd;
+        cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
+    }
+
     __cvmx_helper_setup_gmx(interface, num_ports);
 
     for (index=0; index<num_ports; index++)
@@ -371,7 +412,7 @@ int __cvmx_helper_sgmii_enable(int interface)
 cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
 {
     cvmx_helper_link_info_t result;
-    cvmx_pcsx_miscx_ctl_reg_t pcs_misc_ctl_reg;
+    cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
     int interface = cvmx_helper_get_interface_num(ipd_port);
     int index = cvmx_helper_get_interface_index_num(ipd_port);
     cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg;
@@ -398,16 +439,14 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
     }
 
 
-    pcs_misc_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
-    if (pcs_misc_ctl_reg.s.mode)
+    pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+    if (pcsx_miscx_ctl_reg.s.mode)
     {
         /* 1000BASE-X */
         // FIXME
     }
     else
     {
-        cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
-        pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
         if (pcsx_miscx_ctl_reg.s.mac_phy)
         {
             /* PHY Mode */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
index 3ff1672..4eb9863 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for SGMII initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_SGMII_H__
 #define __CVMX_HELPER_SGMII_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-spi.c b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
index bc05662..54c768b 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
@@ -1,60 +1,84 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
-
 /**
  * @file
  *
  * Functions for SPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 42417 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-helper.h>
+#endif
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 #include "cvmx.h"
 #include "cvmx-spi.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-helper.h"
+#endif
+#else
+#include "cvmx.h"
+#include "cvmx-spi.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+#endif
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
 /* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
     routines wait for SPI training. You can override the value using
     executive-config.h if necessary */
@@ -132,7 +156,7 @@ int __cvmx_helper_spi_enable(int interface)
     int ipd_port;
     for (ipd_port=interface*16; ipd_port<interface*16+num_ports; ipd_port++)
     {
-        cvmx_pip_port_cfg_t port_config;
+        cvmx_pip_prt_cfgx_t port_config;
         port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
         port_config.s.crc_en = 1;
         cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-spi.h b/sys/contrib/octeon-sdk/cvmx-helper-spi.h
index 7f2f82f..d34da55 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-spi.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-spi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for SPI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_SPI_H__
 #define __CVMX_HELPER_SPI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-srio.c b/sys/contrib/octeon-sdk/cvmx-helper-srio.c
new file mode 100644
index 0000000..bf5e297
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-srio.c
@@ -0,0 +1,323 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SRIO initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-srio.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
+#include <asm/octeon/cvmx-sriomaintx-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#include "cvmx-srio.h"
+#endif
+#else
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#include "cvmx-srio.h"
+#endif
+#endif
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * @INTERNAL
+ * Probe a SRIO interface and determine the number of ports
+ * connected to it. The SRIO interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_srio_probe(int interface)
+{
+    cvmx_sriox_status_reg_t srio0_status_reg;
+    cvmx_sriox_status_reg_t srio1_status_reg;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return 0;
+
+    srio0_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
+    srio1_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
+    if (srio0_status_reg.s.srio || srio1_status_reg.s.srio)
+        return 2;
+    else
+        return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable SRIO interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_srio_enable(int interface)
+{
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+    int index;
+    cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
+    cvmx_sriox_imsg_ctrl_t sriox_imsg_ctrl;
+    cvmx_dpi_ctl_t dpi_ctl;
+
+    /* All SRIO ports have a cvmx_srio_rx_message_header_t header
+        on them that must be skipped by IPD */
+    for (index=0; index<num_ports; index++)
+    {
+        cvmx_pip_prt_cfgx_t port_config;
+        cvmx_sriox_omsg_portx_t sriox_omsg_portx;
+        cvmx_sriox_omsg_sp_mrx_t sriox_omsg_sp_mrx;
+        cvmx_sriox_omsg_fmp_mrx_t sriox_omsg_fmp_mrx;
+        cvmx_sriox_omsg_nmp_mrx_t sriox_omsg_nmp_mrx;
+        int ipd_port = cvmx_helper_get_ipd_port(interface, index);
+        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+        /* Only change the skip if the user hasn't already set it */
+        if (!port_config.s.skip)
+        {
+            port_config.s.skip = sizeof(cvmx_srio_rx_message_header_t);
+            cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
+        }
+
+        /* Enable TX with PKO */
+        sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4));
+        sriox_omsg_portx.s.port = (interface - 4) * 2 + index;
+        sriox_omsg_portx.s.enable = 1;
+        cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4), sriox_omsg_portx.u64);
+
+        /* Allow OMSG controller to send regardless of the state of any other
+            controller. Allow messages to different IDs and MBOXes to go in
+            parallel */
+        sriox_omsg_sp_mrx.u64 = 0;
+        sriox_omsg_sp_mrx.s.xmbox_sp = 1;
+        sriox_omsg_sp_mrx.s.ctlr_sp = 1;
+        sriox_omsg_sp_mrx.s.ctlr_fmp = 1;
+        sriox_omsg_sp_mrx.s.ctlr_nmp = 1;
+        sriox_omsg_sp_mrx.s.id_sp = 1;
+        sriox_omsg_sp_mrx.s.id_fmp = 1;
+        sriox_omsg_sp_mrx.s.id_nmp = 1;
+        sriox_omsg_sp_mrx.s.mbox_sp = 1;
+        sriox_omsg_sp_mrx.s.mbox_fmp = 1;
+        sriox_omsg_sp_mrx.s.mbox_nmp = 1;
+        sriox_omsg_sp_mrx.s.all_psd = 1;
+        cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, interface-4), sriox_omsg_sp_mrx.u64);
+
+        /* Allow OMSG controller to send regardless of the state of any other
+            controller. Allow messages to different IDs and MBOXes to go in
+            parallel */
+        sriox_omsg_fmp_mrx.u64 = 0;
+        sriox_omsg_fmp_mrx.s.ctlr_sp = 1;
+        sriox_omsg_fmp_mrx.s.ctlr_fmp = 1;
+        sriox_omsg_fmp_mrx.s.ctlr_nmp = 1;
+        sriox_omsg_fmp_mrx.s.id_sp = 1;
+        sriox_omsg_fmp_mrx.s.id_fmp = 1;
+        sriox_omsg_fmp_mrx.s.id_nmp = 1;
+        sriox_omsg_fmp_mrx.s.mbox_sp = 1;
+        sriox_omsg_fmp_mrx.s.mbox_fmp = 1;
+        sriox_omsg_fmp_mrx.s.mbox_nmp = 1;
+        sriox_omsg_fmp_mrx.s.all_psd = 1;
+        cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, interface-4), sriox_omsg_fmp_mrx.u64);
+
+        /* Once the first part of a message is accepted, always acept the rest
+            of the message */
+        sriox_omsg_nmp_mrx.u64 = 0;
+        sriox_omsg_nmp_mrx.s.all_sp = 1;
+        sriox_omsg_nmp_mrx.s.all_fmp = 1;
+        sriox_omsg_nmp_mrx.s.all_nmp = 1;
+        cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, interface-4), sriox_omsg_nmp_mrx.u64);
+
+    }
+
+    /* Choose the receive controller based on the mailbox */
+    sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4));
+    sriox_imsg_ctrl.s.prt_sel = 0;
+    sriox_imsg_ctrl.s.mbox = 0xa;
+    cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4), sriox_imsg_ctrl.u64);
+
+    /* DPI must be enabled for us to RX messages */
+    dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
+    dpi_ctl.s.clk = 1;
+    dpi_ctl.s.en = 1;
+    cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
+
+    /* Enable RX */
+    if (!cvmx_srio_config_read32(interface - 4, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), &sriomaintx_core_enables.u32))
+    {
+        sriomaintx_core_enables.s.imsg0 = 1;
+        sriomaintx_core_enables.s.imsg1 = 1;
+        cvmx_srio_config_write32(interface - 4, 0, -1, 0, 0,
+            CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), sriomaintx_core_enables.u32);
+    }
+
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by SRIO link status.
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int srio_port = interface - 4;
+    cvmx_helper_link_info_t result;
+    cvmx_sriox_status_reg_t srio_status_reg;
+    cvmx_sriomaintx_port_0_err_stat_t sriomaintx_port_0_err_stat;
+    cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
+    cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
+
+    result.u64 = 0;
+
+    /* Make sure register access is allowed */
+    srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
+    if (!srio_status_reg.s.access)
+        return result;
+
+    /* Read the port link status */
+    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_PORT_0_ERR_STAT(srio_port),
+        &sriomaintx_port_0_err_stat.u32))
+        return result;
+
+    /* Return if link is down */
+    if (!sriomaintx_port_0_err_stat.s.pt_ok)
+        return result;
+
+    /* Read the port link width and speed */
+    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_PORT_0_CTL(srio_port),
+        &sriomaintx_port_0_ctl.u32))
+        return result;
+    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
+        CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port),
+        &sriomaintx_port_0_ctl2.u32))
+        return result;
+
+    /* Link is up */
+    result.s.full_duplex = 1;
+    result.s.link_up = 1;
+    switch (sriomaintx_port_0_ctl2.s.sel_baud)
+    {
+        case 1:
+            result.s.speed = 1250;
+            break;
+        case 2:
+            result.s.speed = 2500;
+            break;
+        case 3:
+            result.s.speed = 3125;
+            break;
+        case 4:
+            result.s.speed = 5000;
+            break;
+        case 5:
+            result.s.speed = 6250;
+            break;
+        default:
+            result.s.speed = 0;
+            break;
+    }
+    switch (sriomaintx_port_0_ctl.s.it_width)
+    {
+        case 2: /* Four lanes */
+            result.s.speed += 40000;
+            break;
+        case 3: /* Two lanes */
+            result.s.speed += 20000;
+            break;
+        default: /* One lane */
+            result.s.speed += 10000;
+            break;
+    }
+    return result;
+}
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_srio_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-srio.h b/sys/contrib/octeon-sdk/cvmx-helper-srio.h
new file mode 100644
index 0000000..1f9e62c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-helper-srio.h
@@ -0,0 +1,107 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SRIO initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_SRIO_H__
+#define __CVMX_HELPER_SRIO_H__
+
+/**
+ * @INTERNAL
+ * Probe a SRIO interface and determine the number of ports
+ * connected to it. The SRIO interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_srio_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a SRIO interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_srio_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by SRIO link status.
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_srio_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+#endif
+
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-util.c b/sys/contrib/octeon-sdk/cvmx-helper-util.c
index bbdbf08..47250df 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-util.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-util.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,29 +42,46 @@
 
 
 
+
 /**
  * @file
  *
  * Small helper utilities.
  *
- * <hr>$Revision: 42493 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#endif
 #include "cvmx.h"
 #include "cvmx-bootmem.h"
 #include "cvmx-fpa.h"
 #include "cvmx-pip.h"
 #include "cvmx-pko.h"
 #include "cvmx-ipd.h"
-#include "cvmx-asx.h"
 #include "cvmx-gmx.h"
 #include "cvmx-spi.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-util.h"
 #include "cvmx-version.h"
+#endif
 
 #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 /**
  * Get the version of the CVMX libraries.
  *
@@ -74,7 +92,7 @@ const char *cvmx_helper_get_version(void)
 {
     return OCTEON_SDK_VERSION_STRING;
 }
-
+#endif
 
 /**
  * Convert a interface mode into a human readable string
@@ -97,6 +115,7 @@ const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mo
         case CVMX_HELPER_INTERFACE_MODE_PICMG:      return "PICMG";
         case CVMX_HELPER_INTERFACE_MODE_NPI:        return "NPI";
         case CVMX_HELPER_INTERFACE_MODE_LOOP:       return "LOOP";
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:       return "SRIO";
     }
     return "UNKNOWN";
 }
@@ -204,7 +223,7 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
  */
 int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
 {
-    cvmx_ipd_qos_red_marks_t red_marks;
+    cvmx_ipd_qosx_red_marks_t red_marks;
     cvmx_ipd_red_quex_param_t red_param;
 
     /* Set RED to begin dropping packets when there are pass_thresh buffers
@@ -271,8 +290,20 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
     red_port_enable.s.prb_dly = 10000;
     cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
 
+    /* Shutoff the dropping of packets based on RED for SRIO ports */
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_ipd_red_port_enable2_t red_port_enable2;
+        red_port_enable2.u64 = 0;
+        red_port_enable2.s.prt_enb = 0xf0;
+        cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE2, red_port_enable2.u64);
+    }
+
     return 0;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_setup_red);
+#endif
 
 
 /**
@@ -383,7 +414,7 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports)
 
 
 /**
- * Returns the IPD/PKO port number for a port on teh given
+ * Returns the IPD/PKO port number for a port on the given
  * interface.
  *
  * @param interface Interface to use
@@ -399,9 +430,14 @@ int cvmx_helper_get_ipd_port(int interface, int port)
         case 1: return port + 16;
         case 2: return port + 32;
         case 3: return port + 36;
+        case 4: return port + 40;
+        case 5: return port + 42;
     }
     return -1;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_ipd_port);
+#endif
 
 #endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
 
@@ -423,11 +459,18 @@ int cvmx_helper_get_interface_num(int ipd_port)
         return 2;
     else if (ipd_port < 40)
         return 3;
+    else if (ipd_port < 42)
+	return 4;
+    else if (ipd_port < 44)
+	return 5;
     else
         cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n");
 
     return -1;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_interface_num);
+#endif
 
 
 /**
@@ -442,121 +485,15 @@ int cvmx_helper_get_interface_index_num(int ipd_port)
 {
     if (ipd_port < 32)
         return ipd_port & 15;
-    else if (ipd_port < 36)
-        return ipd_port & 3;
     else if (ipd_port < 40)
         return ipd_port & 3;
+    else if (ipd_port < 44)
+	return ipd_port & 1;
     else
         cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n");
 
     return -1;
 }
-
-/**
- * Initialize the internal QLM JTAG logic to allow programming
- * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
- * These functions should only be used at the direction of Cavium
- * Networks. Programming incorrect values into the JTAG chain
- * can cause chip damage.
- */
-void cvmx_helper_qlm_jtag_init(void)
-{
-    cvmx_ciu_qlm_jtgc_t jtgc;
-    int clock_div = 0;
-    int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
-    divisor = (divisor-1)>>2;
-    /* Convert the divisor into a power of 2 shift */
-    CVMX_CLZ(clock_div, divisor);
-    clock_div = 32 - clock_div;
-
-    /* Clock divider for QLM JTAG operations.  eclk is divided by 2^(CLK_DIV + 2) */
-    jtgc.u64 = 0;
-    jtgc.s.clk_div = clock_div;
-    jtgc.s.mux_sel = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-        jtgc.s.bypass = 0x3;
-    else
-        jtgc.s.bypass = 0xf;
-    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
-    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
-}
-
-
-/**
- * Write up to 32bits into the QLM jtag chain. Bits are shifted
- * into the MSB and out the LSB, so you should shift in the low
- * order bits followed by the high order bits. The JTAG chain is
- * 4 * 268 bits long, or 1072.
- *
- * @param qlm    QLM to shift value into
- * @param bits   Number of bits to shift in (1-32).
- * @param data   Data to shift in. Bit 0 enters the chain first, followed by
- *               bit 1, etc.
- *
- * @return The low order bits of the JTAG chain that shifted out of the
- *         circle.
- */
-uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
-{
-    cvmx_ciu_qlm_jtgd_t jtgd;
-    jtgd.u64 = 0;
-    jtgd.s.shift = 1;
-    jtgd.s.shft_cnt = bits-1;
-    jtgd.s.shft_reg = data;
-    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
-        jtgd.s.select = 1 << qlm;
-    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
-    do
-    {
-        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
-    } while (jtgd.s.shift);
-    return jtgd.s.shft_reg >> (32-bits);
-}
-
-
-/**
- * Shift long sequences of zeros into the QLM JTAG chain. It is
- * common to need to shift more than 32 bits of zeros into the
- * chain. This function is a convience wrapper around
- * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
- * zeros at a time.
- *
- * @param qlm    QLM to shift zeros into
- * @param bits
- */
-void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
-{
-    while (bits > 0)
-    {
-        int n = bits;
-        if (n > 32)
-            n = 32;
-        cvmx_helper_qlm_jtag_shift(qlm, n, 0);
-        bits -= n;
-    }
-}
-
-
-/**
- * Program the QLM JTAG chain into all lanes of the QLM. You must
- * have already shifted in 268*4, or 1072 bits into the JTAG
- * chain. Updating invalid values can possibly cause chip damage.
- *
- * @param qlm    QLM to program
- */
-void cvmx_helper_qlm_jtag_update(int qlm)
-{
-    cvmx_ciu_qlm_jtgd_t jtgd;
-
-    /* Update the new data */
-    jtgd.u64 = 0;
-    jtgd.s.update = 1;
-    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
-        jtgd.s.select = 1 << qlm;
-    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
-    do
-    {
-        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
-    } while (jtgd.s.update);
-}
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_interface_index_num);
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-util.h b/sys/contrib/octeon-sdk/cvmx-helper-util.h
index 210f815..fdbc84e 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-util.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-util.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Small helper utilities.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_HELPER_UTIL_H__
@@ -226,50 +228,4 @@ extern int cvmx_helper_get_interface_num(int ipd_port);
  */
 extern int cvmx_helper_get_interface_index_num(int ipd_port);
 
-/**
- * Initialize the internal QLM JTAG logic to allow programming
- * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
- * These functions should only be used at the direction of Cavium
- * Networks. Programming incorrect values into the JTAG chain
- * can cause chip damage.
- */
-extern void cvmx_helper_qlm_jtag_init(void);
-
-/**
- * Write up to 32bits into the QLM jtag chain. Bits are shifted
- * into the MSB and out the LSB, so you should shift in the low
- * order bits followed by the high order bits. The JTAG chain is
- * 4 * 268 bits long, or 1072.
- *
- * @param qlm    QLM to shift value into
- * @param bits   Number of bits to shift in (1-32).
- * @param data   Data to shift in. Bit 0 enters the chain first, followed by
- *               bit 1, etc.
- *
- * @return The low order bits of the JTAG chain that shifted out of the
- *         circle.
- */
-extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
-
-/**
- * Shift long sequences of zeros into the QLM JTAG chain. It is
- * common to need to shift more than 32 bits of zeros into the
- * chain. This function is a convience wrapper around
- * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
- * zeros at a time.
- *
- * @param qlm    QLM to shift zeros into
- * @param bits
- */
-extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
-
-/**
- * Program the QLM JTAG chain into all lanes of the QLM. You must
- * have already shifted in 268*4, or 1072 bits into the JTAG
- * chain. Updating invalid values can possibly cause chip damage.
- *
- * @param qlm    QLM to program
- */
-extern void cvmx_helper_qlm_jtag_update(int qlm);
-
 #endif  /* __CVMX_HELPER_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-xaui.c b/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
index 1968499..2616f32 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,44 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for XAUI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 42417 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include <asm/octeon/cvmx-helper.h>
+#endif
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-pcsxx-defs.h>
+#include <asm/octeon/cvmx-ciu-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#endif
+#else
 #include "cvmx.h"
 #include "cvmx-helper.h"
+#endif
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+
 /**
  * @INTERNAL
  * Probe a XAUI interface and determine the number of ports
@@ -69,6 +96,17 @@ int __cvmx_helper_xaui_probe(int interface)
     cvmx_gmxx_hg2_control_t gmx_hg2_control;
     cvmx_gmxx_inf_mode_t mode;
 
+    /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
+    {
+        cvmx_ciu_qlm2_t ciu_qlm;
+        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
+        ciu_qlm.s.txbypass = 1;
+        ciu_qlm.s.txdeemph = 0x5;
+        ciu_qlm.s.txmargin = 0x1a;
+        cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
+    }
+
     /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
         needs to be enabled before IPD otherwise per port backpressure
         may not work properly */
@@ -120,9 +158,7 @@ int __cvmx_helper_xaui_enable(int interface)
     cvmx_pcsxx_control1_reg_t     xauiCtl;
     cvmx_pcsxx_misc_ctl_reg_t     xauiMiscCtl;
     cvmx_gmxx_tx_xaui_ctl_t       gmxXauiTxCtl;
-    cvmx_gmxx_rxx_int_en_t        gmx_rx_int_en;
-    cvmx_gmxx_tx_int_en_t         gmx_tx_int_en;
-    cvmx_pcsxx_int_en_reg_t       pcsx_int_en_reg;
+    cvmx_helper_link_info_t       link_info;
 
     /* (1) Interface has already been enabled. */
 
@@ -132,11 +168,8 @@ int __cvmx_helper_xaui_enable(int interface)
     cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
 
     /* (3) Disable GMX and PCSX interrupts. */
-    gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0,interface));
     cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
-    gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
     cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
-    pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
     cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
 
     /* (4) Bring up the PCSX and GMX reconciliation layer. */
@@ -185,11 +218,6 @@ int __cvmx_helper_xaui_enable(int interface)
     cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
 
-    /* (7) Clear out any error state */
-    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0,interface)));
-    cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
-    cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
-
     /* Wait for receive link */
     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface), cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1, 10000))
         return -1;
@@ -198,12 +226,6 @@ int __cvmx_helper_xaui_enable(int interface)
     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0, 10000))
         return -1;
 
-    cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), gmx_rx_int_en.u64);
-    cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
-    cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
-
-    cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
-
     /* (8) Enable packet reception */
     xauiMiscCtl.s.gmxeno = 0;
     cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
@@ -211,6 +233,11 @@ int __cvmx_helper_xaui_enable(int interface)
     gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
     gmx_cfg.s.en = 1;
     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+    link_info = cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
+    if (!link_info.s.link_up)
+        return -1;
+
     return 0;
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-xaui.h b/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
index 4bea0c2..14c2659 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for XAUI initialization, configuration,
  * and monitoring.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_HELPER_XAUI_H__
 #define __CVMX_HELPER_XAUI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-helper.c b/sys/contrib/octeon-sdk/cvmx-helper.c
index fbb1316..c5e9054 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,28 +42,64 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions for common, but complicated tasks.
  *
- * <hr>$Revision: 42150 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-smix-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
+
+#include <asm/octeon/cvmx-gmx.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#include <asm/octeon/cvmx-helper-errata.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#endif
 #include "cvmx.h"
+#include "cvmx-sysinfo.h"
 #include "cvmx-bootmem.h"
+#include "cvmx-version.h"
+#include "cvmx-helper-check-defines.h"
+#include "cvmx-gmx.h"
+#include "cvmx-error.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
+
 #include "cvmx-fpa.h"
 #include "cvmx-pip.h"
 #include "cvmx-pko.h"
 #include "cvmx-ipd.h"
-#include "cvmx-asx.h"
-#include "cvmx-gmx.h"
 #include "cvmx-spi.h"
-#include "cvmx-sysinfo.h"
 #include "cvmx-helper.h"
-#include "cvmx-version.h"
-#include "cvmx-helper-check-defines.h"
 #include "cvmx-helper-board.h"
 #include "cvmx-helper-errata.h"
+#endif
+
+
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
@@ -74,6 +111,9 @@
  * calling any cvmx-helper operations.
  */
 CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]) = NULL;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_override_pko_queue_priority);
+#endif
 
 /**
  * cvmx_override_ipd_port_setup(int ipd_port) is a function
@@ -86,7 +126,7 @@ CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t prio
 CVMX_SHARED void (*cvmx_override_ipd_port_setup)(int ipd_port) = NULL;
 
 /* Port count per interface */
-static CVMX_SHARED int interface_port_count[4] = {0,0,0,0};
+static CVMX_SHARED int interface_port_count[6] = {0,};
 /* Port last configured link info index by IPD/PKO port */
 static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
 
@@ -112,11 +152,16 @@ int cvmx_helper_get_number_of_interfaces(void)
 	    break;
     }
 
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+	return 6;
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
         return 4;
     else
         return 3;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_get_number_of_interfaces);
+#endif
 
 
 /**
@@ -132,6 +177,9 @@ int cvmx_helper_ports_on_interface(int interface)
 {
     return interface_port_count[interface];
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_ports_on_interface);
+#endif
 
 
 /**
@@ -152,12 +200,22 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
 
     if (interface == 3)
     {
-        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX))
             return CVMX_HELPER_INTERFACE_MODE_LOOP;
         else
             return CVMX_HELPER_INTERFACE_MODE_DISABLED;
     }
 
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && (interface == 4 || interface == 5))
+    {
+        cvmx_sriox_status_reg_t sriox_status_reg;
+        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(interface-4));
+        if (sriox_status_reg.s.srio)
+            return CVMX_HELPER_INTERFACE_MODE_SRIO;
+        else
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+    }
+
     if (interface == 0 && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 && cvmx_sysinfo_get()->board_rev_major == 1)
     {
         /* Lie about interface type of CN3005 board.  This board has a switch on port 1 like
@@ -169,7 +227,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
     }
 
     /* Interface 1 is always disabled on CN31XX and CN30XX */
-    if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)))
+    if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
         return CVMX_HELPER_INTERFACE_MODE_DISABLED;
 
     mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
@@ -185,6 +243,15 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
             default:return CVMX_HELPER_INTERFACE_MODE_DISABLED;
         }
     }
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+	switch(mode.cn63xx.mode)
+	{
+	    case 0: return CVMX_HELPER_INTERFACE_MODE_SGMII;
+	    case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
+	    default: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+	}
+    }
     else
     {
         if (!mode.s.en)
@@ -201,7 +268,9 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
             return CVMX_HELPER_INTERFACE_MODE_RGMII;
     }
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_interface_get_mode);
+#endif
 
 /**
  * @INTERNAL
@@ -217,8 +286,8 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
  */
 static int __cvmx_helper_port_setup_ipd(int ipd_port)
 {
-    cvmx_pip_port_cfg_t port_config;
-    cvmx_pip_port_tag_cfg_t tag_config;
+    cvmx_pip_prt_cfgx_t port_config;
+    cvmx_pip_prt_tagx_t tag_config;
 
     port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
     tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
@@ -309,6 +378,10 @@ int cvmx_helper_interface_probe(int interface)
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             interface_port_count[interface] = __cvmx_helper_loop_probe(interface);
             break;
+	/* SRIO has 2^N ports, where N is number of interfaces */
+	case CVMX_HELPER_INTERFACE_MODE_SRIO:
+	    interface_port_count[interface] = __cvmx_helper_srio_probe(interface);
+	    break;
     }
 
     interface_port_count[interface] = __cvmx_helper_board_interface_probe(interface, interface_port_count[interface]);
@@ -354,6 +427,9 @@ static int __cvmx_helper_interface_setup_ipd(int interface)
  */
 static int __cvmx_helper_global_setup_ipd(void)
 {
+#ifndef CVMX_HELPER_IPD_DRAM_MODE
+#define CVMX_HELPER_IPD_DRAM_MODE   CVMX_IPD_OPC_MODE_STT
+#endif
     /* Setup the global packet input options */
     cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE/8,
                     CVMX_HELPER_FIRST_MBUFF_SKIP/8,
@@ -361,8 +437,8 @@ static int __cvmx_helper_global_setup_ipd(void)
                     (CVMX_HELPER_FIRST_MBUFF_SKIP+8) / 128, /* The +8 is to account for the next ptr */
                     (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP+8) / 128, /* The +8 is to account for the next ptr */
                     CVMX_FPA_WQE_POOL,
-                    CVMX_IPD_OPC_MODE_STT,
-                    CVMX_HELPER_ENABLE_BACK_PRESSURE);
+                    CVMX_HELPER_IPD_DRAM_MODE,
+                    1);
     return 0;
 }
 
@@ -448,6 +524,7 @@ static int __cvmx_helper_global_setup_backpressure(void)
         {
             case CVMX_HELPER_INTERFACE_MODE_DISABLED:
             case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            case CVMX_HELPER_INTERFACE_MODE_SRIO:
             case CVMX_HELPER_INTERFACE_MODE_NPI:
             case CVMX_HELPER_INTERFACE_MODE_LOOP:
             case CVMX_HELPER_INTERFACE_MODE_XAUI:
@@ -467,6 +544,119 @@ static int __cvmx_helper_global_setup_backpressure(void)
     return 0;
 }
 
+/**
+ * @INTERNAL
+ * Verify the per port IPD backpressure is aligned properly.
+ * @return Zero if working, non zero if misaligned
+ */
+static int __cvmx_helper_backpressure_is_misaligned(void)
+{
+    uint64_t ipd_int_enb;
+    cvmx_ipd_ctl_status_t ipd_reg;
+    uint64_t bp_status0;
+    uint64_t bp_status1;
+    const int port0 = 0;
+    const int port1 = 16;
+    cvmx_helper_interface_mode_t mode0 = cvmx_helper_interface_get_mode(0);
+    cvmx_helper_interface_mode_t mode1 = cvmx_helper_interface_get_mode(1);
+
+    /* Disable error interrupts while we check backpressure */
+    ipd_int_enb = cvmx_read_csr(CVMX_IPD_INT_ENB);
+    cvmx_write_csr(CVMX_IPD_INT_ENB, 0);
+
+    /* Enable per port backpressure */
+    ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+    ipd_reg.s.pbp_en = 1;
+    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+
+    if (mode0 != CVMX_HELPER_INTERFACE_MODE_DISABLED)
+    {
+        /* Enable backpressure for port with a zero threshold */
+        cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port0), 1<<17);
+        /* Add 1000 to the page count to simulate packets coming in */
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_BP_PAGE_CNT, (port0<<25) | 1000);
+    }
+
+    if (mode1 != CVMX_HELPER_INTERFACE_MODE_DISABLED)
+    {
+        /* Enable backpressure for port with a zero threshold */
+        cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port1), 1<<17);
+        /* Add 1000 to the page count to simulate packets coming in */
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_BP_PAGE_CNT, (port1<<25) | 1000);
+    }
+
+    /* Wait 500 cycles for the BP to update */
+    cvmx_wait(500);
+
+    /* Read the BP state from the debug select register */
+    switch (mode0)
+    {
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            cvmx_write_csr(CVMX_NPI_DBG_SELECT, 0x9004);
+            bp_status0 = cvmx_read_csr(CVMX_DBG_DATA);
+            bp_status0 = 0xffff & ~bp_status0;
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            cvmx_write_csr(CVMX_NPI_DBG_SELECT, 0x0e00);
+            bp_status0 = 0xffff & cvmx_read_csr(CVMX_DBG_DATA);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, 0x0e00);
+            bp_status0 = 0xffff & cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+            break;
+        default:
+            bp_status0 = 1<<port0;
+            break;
+    }
+
+    /* Read the BP state from the debug select register */
+    switch (mode1)
+    {
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            cvmx_write_csr(CVMX_NPI_DBG_SELECT, 0x9804);
+            bp_status1 = cvmx_read_csr(CVMX_DBG_DATA);
+            bp_status1 = 0xffff & ~bp_status1;
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            cvmx_write_csr(CVMX_NPI_DBG_SELECT, 0x1600);
+            bp_status1 = 0xffff & cvmx_read_csr(CVMX_DBG_DATA);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, 0x1600);
+            bp_status1 = 0xffff & cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+            break;
+        default:
+            bp_status1 = 1<<(port1-16);
+            break;
+    }
+
+    if (mode0 != CVMX_HELPER_INTERFACE_MODE_DISABLED)
+    {
+        /* Shutdown BP */
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_BP_PAGE_CNT, (port0<<25) | (0x1ffffff & -1000));
+        cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port0), 0);
+    }
+
+    if (mode1 != CVMX_HELPER_INTERFACE_MODE_DISABLED)
+    {
+        /* Shutdown BP */
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_BP_PAGE_CNT, (port1<<25) | (0x1ffffff & -1000));
+        cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port1), 0);
+    }
+
+    /* Clear any error interrupts that might have been set */
+    cvmx_write_csr(CVMX_IPD_INT_SUM, 0x1f);
+    cvmx_write_csr(CVMX_IPD_INT_ENB, ipd_int_enb);
+
+    return ((bp_status0 != 1ull<<port0) || (bp_status1 != 1ull<<(port1-16)));
+}
+
 
 /**
  * @INTERNAL
@@ -518,6 +708,10 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             result = __cvmx_helper_loop_enable(interface);
             break;
+	/* SRIO has 2^N ports, where N is number of interfaces */
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
+	    result = __cvmx_helper_srio_enable(interface);
+	    break;
     }
     result |= __cvmx_helper_board_hardware_enable(interface);
     return result;
@@ -558,7 +752,9 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
         __cvmx_helper_errata_fix_ipd_ptr_alignment();
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_ipd_and_packet_input_enable);
+#endif
 
 /**
  * Initialize the PIP, IPD, and PKO hardware to support
@@ -584,36 +780,52 @@ int cvmx_helper_initialize_packet_io_global(void)
     /* Tell L2 to give the IOB statically higher priority compared to the
         cores. This avoids conditions where IO blocks might be starved under
         very high L2 loads */
-    l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
-    l2c_cfg.s.lrf_arb_mode = 0;
-    l2c_cfg.s.rfb_arb_mode = 0;
-    cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
-
-    /* Make sure SMI/MDIO is enabled so we can query PHYs */
-    smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
-    if (!smix_en.s.en)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_l2c_ctl_t l2c_ctl;
+        l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+        l2c_ctl.s.rsp_arb_mode = 1;
+        l2c_ctl.s.xmc_arb_mode = 0;
+        cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64);
+    }
+    else
     {
-        smix_en.s.en = 1;
-        cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
+        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        l2c_cfg.s.lrf_arb_mode = 0;
+        l2c_cfg.s.rfb_arb_mode = 0;
+        cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
     }
 
-    /* Newer chips actually have two SMI/MDIO interfaces */
-    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
-        !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
-        !OCTEON_IS_MODEL(OCTEON_CN50XX))
+    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
     {
-        smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+        /* Make sure SMI/MDIO is enabled so we can query PHYs */
+        smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
         if (!smix_en.s.en)
         {
             smix_en.s.en = 1;
-            cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+            cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
+        }
+
+        /* Newer chips actually have two SMI/MDIO interfaces */
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
+            !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
+            !OCTEON_IS_MODEL(OCTEON_CN50XX))
+        {
+            smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+            if (!smix_en.s.en)
+            {
+                smix_en.s.en = 1;
+                cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+            }
         }
     }
 
+    for (interface=0; interface<num_interfaces; interface++)
+        result |= cvmx_helper_interface_probe(interface);
+
     cvmx_pko_initialize_global();
     for (interface=0; interface<num_interfaces; interface++)
     {
-        result |= cvmx_helper_interface_probe(interface);
         if (cvmx_helper_ports_on_interface(interface) > 0)
             cvmx_dprintf("Interface %d has %d ports (%s)\n",
                      interface, cvmx_helper_ports_on_interface(interface),
@@ -633,6 +845,9 @@ int cvmx_helper_initialize_packet_io_global(void)
 #endif
     return result;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_initialize_packet_io_global);
+#endif
 
 
 /**
@@ -647,6 +862,359 @@ int cvmx_helper_initialize_packet_io_local(void)
 
 
 /**
+ * Undo the initialization performed in
+ * cvmx_helper_initialize_packet_io_global(). After calling this routine and the
+ * local version on each core, packet IO for Octeon will be disabled and placed
+ * in the initial reset state. It will then be safe to call the initialize
+ * later on. Note that this routine does not empty the FPA pools. It frees all
+ * buffers used by the packet IO hardware to the FPA so a function emptying the
+ * FPA after shutdown should find all packet buffers in the FPA.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_helper_shutdown_packet_io_global(void)
+{
+    const int timeout = 5; /* Wait up to 5 seconds for timeouts */
+    int result = 0;
+    int num_interfaces;
+    int interface;
+    int num_ports;
+    int index;
+    int pool0_count;
+    cvmx_wqe_t *work;
+
+    /* Step 1: Disable all backpressure */
+    for (interface=0; interface<2; interface++)
+        if (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_DISABLED)
+            cvmx_gmx_set_backpressure_override(interface, 0xf);
+
+step2:
+    /* Step 2: Wait for the PKO queues to drain */
+    num_interfaces = cvmx_helper_get_number_of_interfaces();
+    for (interface=0; interface<num_interfaces; interface++)
+    {
+        num_ports = cvmx_helper_ports_on_interface(interface);
+        for (index=0; index<num_ports; index++)
+        {
+            int pko_port = cvmx_helper_get_ipd_port(interface, index);
+            int queue = cvmx_pko_get_base_queue(pko_port);
+            int max_queue = queue + cvmx_pko_get_num_queues(pko_port);
+            while (queue < max_queue)
+            {
+                int count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+                uint64_t start_cycle = cvmx_get_cycle();
+                uint64_t stop_cycle = start_cycle +
+                    cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
+                while (count && (cvmx_get_cycle() < stop_cycle))
+                {
+                    cvmx_wait(10000);
+                    count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+                }
+                if (count)
+                {
+                    cvmx_dprintf("PKO port %d, queue %d, timeout waiting for idle\n",
+                        pko_port, queue);
+                    result = -1;
+                }
+                queue++;
+            }
+        }
+    }
+
+    /* Step 3: Disable TX and RX on all ports */
+    for (interface=0; interface<2; interface++)
+    {
+        switch (cvmx_helper_interface_get_mode(interface))
+        {
+            case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+            case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                /* Not a packet interface */
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_NPI:
+            case CVMX_HELPER_INTERFACE_MODE_SRIO:
+                /* We don't handle the NPI/NPEI/SRIO packet engines. The caller
+                    must know these are idle */
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                /* Nothing needed. Once PKO is idle, the loopback devices
+                    must be idle */
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_SPI:
+                /* SPI cannot be disabled from Octeon. It is the responsibility
+                    of the caller to make sure SPI is idle before doing
+                    shutdown */
+                /* Fall through and do the same processing as RGMII/GMII */
+            case CVMX_HELPER_INTERFACE_MODE_GMII:
+            case CVMX_HELPER_INTERFACE_MODE_RGMII:
+                /* Disable outermost RX at the ASX block */
+                cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), 0);
+                num_ports = cvmx_helper_ports_on_interface(interface);
+                if (num_ports > 4)
+                    num_ports = 4;
+                for (index=0; index<num_ports; index++)
+                {
+                    cvmx_gmxx_prtx_cfg_t gmx_cfg;
+                    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                    gmx_cfg.s.en = 0;
+                    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+                    /* Poll the GMX state machine waiting for it to become idle */
+                    cvmx_write_csr(CVMX_NPI_DBG_SELECT, interface*0x800 + index*0x100 + 0x880);
+                    if (CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, cvmx_dbg_data_t, data&7, ==, 0, timeout*1000000))
+                    {
+                        cvmx_dprintf("GMX RX path timeout waiting for idle\n");
+                        result = -1;
+                    }
+                    if (CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, cvmx_dbg_data_t, data&0xf, ==, 0, timeout*1000000))
+                    {
+                        cvmx_dprintf("GMX TX path timeout waiting for idle\n");
+                        result = -1;
+                    }
+                }
+                /* Disable outermost TX at the ASX block */
+                cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), 0);
+                /* Disable interrupts for interface */
+                cvmx_write_csr(CVMX_ASXX_INT_EN(interface), 0);
+                cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0);
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            case CVMX_HELPER_INTERFACE_MODE_SGMII:
+            case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                num_ports = cvmx_helper_ports_on_interface(interface);
+                if (num_ports > 4)
+                    num_ports = 4;
+                for (index=0; index<num_ports; index++)
+                {
+                    cvmx_gmxx_prtx_cfg_t gmx_cfg;
+                    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                    gmx_cfg.s.en = 0;
+                    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+                    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, timeout*1000000))
+                    {
+                        cvmx_dprintf("GMX RX path timeout waiting for idle\n");
+                        result = -1;
+                    }
+                    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, timeout*1000000))
+                    {
+                        cvmx_dprintf("GMX TX path timeout waiting for idle\n");
+                        result = -1;
+                    }
+                }
+                break;
+        }
+    }
+
+    /* Step 4: Retrieve all packets from the POW and free them */
+    while ((work = cvmx_pow_work_request_sync(CVMX_POW_WAIT)))
+    {
+        cvmx_helper_free_packet_data(work);
+        cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, 0);
+    }
+
+    /* Step 4b: Special workaround for pass 2 errata */
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+    {
+        cvmx_ipd_ptr_count_t ipd_cnt;
+        int to_add;
+        ipd_cnt.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+        to_add = (ipd_cnt.s.wqev_cnt + ipd_cnt.s.wqe_pcnt) & 0x7;
+        if (to_add)
+        {
+            int port = -1;
+            cvmx_dprintf("Aligning CN38XX pass 2 IPD counters\n");
+            if (cvmx_helper_interface_get_mode(0) == CVMX_HELPER_INTERFACE_MODE_RGMII)
+                port = 0;
+            else if (cvmx_helper_interface_get_mode(1) == CVMX_HELPER_INTERFACE_MODE_RGMII)
+                port = 16;
+
+            if (port != -1)
+            {
+                char *buffer = cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL);
+                if (buffer)
+                {
+                    int queue = cvmx_pko_get_base_queue(port);
+                    cvmx_pko_command_word0_t pko_command;
+                    cvmx_buf_ptr_t packet;
+                    uint64_t start_cycle;
+                    uint64_t stop_cycle;
+
+                    /* Populate a minimal packet */
+                    memset(buffer, 0xff, 6);
+                    memset(buffer+6, 0, 54);
+                    pko_command.u64 = 0;
+                    pko_command.s.dontfree = 1;
+                    pko_command.s.total_bytes = 60;
+                    pko_command.s.segs = 1;
+                    packet.u64 = 0;
+                    packet.s.addr = cvmx_ptr_to_phys(buffer);
+                    packet.s.size = CVMX_FPA_PACKET_POOL_SIZE;
+                    __cvmx_helper_rgmii_configure_loopback(port, 1, 0);
+                    while (to_add--)
+                    {
+                        cvmx_pko_send_packet_prepare(port, queue, CVMX_PKO_LOCK_CMD_QUEUE);
+                        if (cvmx_pko_send_packet_finish(port, queue, pko_command, packet, CVMX_PKO_LOCK_CMD_QUEUE))
+                        {
+                            cvmx_dprintf("ERROR: Unable to align IPD counters (PKO failed)\n");
+                            break;
+                        }
+                    }
+                    cvmx_fpa_free(buffer, CVMX_FPA_PACKET_POOL, 0);
+
+                    /* Wait for the packets to loop back */
+                    start_cycle = cvmx_get_cycle();
+                    stop_cycle = start_cycle + cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
+                    while (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue)) &&
+                           (cvmx_get_cycle() < stop_cycle))
+                    {
+                        cvmx_wait(1000);
+                    }
+                    cvmx_wait(1000);
+                    __cvmx_helper_rgmii_configure_loopback(port, 0, 0);
+                    if (to_add == -1)
+                        goto step2;
+                }
+                else
+                    cvmx_dprintf("ERROR: Unable to align IPD counters (Packet pool empty)\n");
+            }
+            else
+                cvmx_dprintf("ERROR: Unable to align IPD counters\n");
+        }
+    }
+
+    /* Step 5: Disable IPD and PKO. PIP is taken care of in the next step */
+    cvmx_ipd_disable();
+    cvmx_pko_disable();
+
+    /* Step 6: Drain all prefetched buffers from IPD/PIP. Note that IPD/PIP
+        have not been reset yet */
+    __cvmx_ipd_free_ptr();
+
+    /* Step 7: Free the PKO command buffers and put PKO in reset */
+    cvmx_pko_shutdown();
+
+    /* Step 8: Disable MAC address filtering */
+    for (interface=0; interface<2; interface++)
+    {
+        switch (cvmx_helper_interface_get_mode(interface))
+        {
+            case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+            case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            case CVMX_HELPER_INTERFACE_MODE_NPI:
+            case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            case CVMX_HELPER_INTERFACE_MODE_GMII:
+            case CVMX_HELPER_INTERFACE_MODE_RGMII:
+            case CVMX_HELPER_INTERFACE_MODE_SPI:
+            case CVMX_HELPER_INTERFACE_MODE_SGMII:
+            case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                num_ports = cvmx_helper_ports_on_interface(interface);
+                if (num_ports > 4)
+                    num_ports = 4;
+                for (index=0; index<num_ports; index++)
+                {
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), 1);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), 0);
+                    cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), 0);
+                }
+                break;
+        }
+    }
+
+    /* Step 9: Drain all FPA buffers out of pool 0 before we reset IPD/PIP.
+        This is needed to keep IPD_QUE0_FREE_PAGE_CNT in sync. We use pool 1
+        for temporary storage */
+    pool0_count = 0;
+    while (1)
+    {
+        void *buffer = cvmx_fpa_alloc(0);
+        if (buffer)
+        {
+            cvmx_fpa_free(buffer, 1, 0);
+            pool0_count++;
+        }
+        else
+            break;
+    }
+
+
+    /* Step 10: Reset IPD and PIP */
+    {
+        cvmx_ipd_ctl_status_t ipd_ctl_status;
+        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        ipd_ctl_status.s.reset = 1;
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+
+        if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+            (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+        {
+            /* only try 1000 times.  Normally if this works it will happen in
+            ** the first 50 loops. */
+            int max_loops = 1000;
+            int loop = 0;
+            /* Per port backpressure counters can get misaligned after an
+               IPD reset. This code realigns them by performing repeated
+               resets. See IPD-13473 */
+            cvmx_wait(100);
+            if (__cvmx_helper_backpressure_is_misaligned())
+            {
+                cvmx_dprintf("Starting to align per port backpressure counters.\n");
+                while (__cvmx_helper_backpressure_is_misaligned() && (loop++ < max_loops))
+                {
+                    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+                    cvmx_wait(123);
+                }
+                if (loop < max_loops)
+                    cvmx_dprintf("Completed aligning per port backpressure counters (%d loops).\n", loop);
+                else
+                {
+                    cvmx_dprintf("ERROR: unable to align per port backpressure counters.\n");
+                    /* For now, don't hang.... */
+                }
+            }
+        }
+
+        /* PIP_SFT_RST not present in CN38XXp{1,2} */
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+        {
+            cvmx_pip_sft_rst_t pip_sft_rst;
+            pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
+            pip_sft_rst.s.rst = 1;
+            cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
+        }
+    }
+
+    /* Step 11: Restore the FPA buffers into pool 0 */
+    while (pool0_count--)
+        cvmx_fpa_free(cvmx_fpa_alloc(1), 0, 0);
+
+    return result;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_shutdown_packet_io_global);
+#endif
+
+
+/**
+ * Does core local shutdown of packet io
+ *
+ * @return Zero on success, non-zero on failure
+ */
+int cvmx_helper_shutdown_packet_io_local(void)
+{
+    /* Currently there is nothing to do per core. This may change in
+        the future */
+    return 0;
+}
+
+
+
+/**
  * Auto configure an IPD/PKO port link state and speed. This
  * function basically does the equivalent of:
  * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
@@ -671,14 +1239,26 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
     if (link_info.u64 ==  port_link_info[ipd_port].u64)
         return link_info;
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
+    if (!link_info.s.link_up)
+        cvmx_error_disable_group(CVMX_ERROR_GROUP_ETHERNET, ipd_port);
+#endif
+
     /* If we fail to set the link speed, port_link_info will not change */
     cvmx_helper_link_set(ipd_port, link_info);
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
+    if (link_info.s.link_up)
+        cvmx_error_enable_group(CVMX_ERROR_GROUP_ETHERNET, ipd_port);
+#endif
+
     /* port_link_info should be the current value, which will be different
         than expect if cvmx_helper_link_set() failed */
     return port_link_info[ipd_port];
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_link_autoconf);
+#endif
 
 /**
  * Return the link state of an IPD/PKO port as returned by
@@ -732,6 +1312,9 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
         case CVMX_HELPER_INTERFACE_MODE_PICMG:
             result = __cvmx_helper_sgmii_link_get(ipd_port);
             break;
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            result = __cvmx_helper_srio_link_get(ipd_port);
+            break;
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             /* Network links are not supported */
@@ -739,6 +1322,9 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
     }
     return result;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_link_get);
+#endif
 
 
 /**
@@ -783,6 +1369,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
         case CVMX_HELPER_INTERFACE_MODE_PICMG:
             result = __cvmx_helper_sgmii_link_set(ipd_port, link_info);
             break;
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
+            result = __cvmx_helper_srio_link_set(ipd_port, link_info);
+            break;
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
             break;
@@ -794,6 +1383,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
         port_link_info[ipd_port].u64 = link_info.u64;
     return result;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_helper_link_set);
+#endif
 
 
 /**
@@ -822,6 +1414,7 @@ int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable
     {
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
         case CVMX_HELPER_INTERFACE_MODE_PCIE:
+        case CVMX_HELPER_INTERFACE_MODE_SRIO:
         case CVMX_HELPER_INTERFACE_MODE_SPI:
         case CVMX_HELPER_INTERFACE_MODE_NPI:
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
diff --git a/sys/contrib/octeon-sdk/cvmx-helper.h b/sys/contrib/octeon-sdk/cvmx-helper.h
index ecc59f0..82d34e1 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper.h
+++ b/sys/contrib/octeon-sdk/cvmx-helper.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,21 +42,26 @@
 
 
 
+
 /**
  * @file
  *
  * Helper functions for common, but complicated tasks.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_HELPER_H__
 #define __CVMX_HELPER_H__
 
-#ifndef CVMX_DONT_INCLUDE_CONFIG
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#elif !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 #include "executive-config.h"
 #include "cvmx-config.h"
 #endif
+
 #include "cvmx-fpa.h"
 #include "cvmx-wqe.h"
 
@@ -75,6 +81,7 @@ typedef enum
     CVMX_HELPER_INTERFACE_MODE_PICMG,
     CVMX_HELPER_INTERFACE_MODE_NPI,
     CVMX_HELPER_INTERFACE_MODE_LOOP,
+    CVMX_HELPER_INTERFACE_MODE_SRIO,
 } cvmx_helper_interface_mode_t;
 
 typedef union
@@ -99,6 +106,7 @@ typedef union
 #include "cvmx-helper-rgmii.h"
 #include "cvmx-helper-sgmii.h"
 #include "cvmx-helper-spi.h"
+#include "cvmx-helper-srio.h"
 #include "cvmx-helper-xaui.h"
 
 /**
@@ -151,6 +159,26 @@ extern int cvmx_helper_initialize_packet_io_global(void);
 extern int cvmx_helper_initialize_packet_io_local(void);
 
 /**
+ * Undo the initialization performed in
+ * cvmx_helper_initialize_packet_io_global(). After calling this routine and the
+ * local version on each core, packet IO for Octeon will be disabled and placed
+ * in the initial reset state. It will then be safe to call the initialize
+ * later on. Note that this routine does not empty the FPA pools. It frees all
+ * buffers used by the packet IO hardware to the FPA so a function emptying the
+ * FPA after shutdown should find all packet buffers in the FPA.
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int cvmx_helper_shutdown_packet_io_global(void);
+
+/**
+ * Does core local shutdown of packet io
+ *
+ * @return Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_shutdown_packet_io_local(void);
+
+/**
  * Returns the number of ports on the given interface.
  * The interface must be initialized before the port count
  * can be returned.
diff --git a/sys/contrib/octeon-sdk/cvmx-higig.h b/sys/contrib/octeon-sdk/cvmx-higig.h
index 02eeda2..87dd754 100644
--- a/sys/contrib/octeon-sdk/cvmx-higig.h
+++ b/sys/contrib/octeon-sdk/cvmx-higig.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
  * XAUI.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_HIGIG_H__
@@ -177,6 +179,129 @@ typedef struct
     } dw2;
 } cvmx_higig_header_t;
 
+typedef struct
+{
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t k_sop          : 8;  /**< The delimiter indicating the start of a packet transmission */
+            uint32_t reserved_21_23 : 3;
+            uint32_t mcst           : 1;  /**< MCST indicates whether the packet should be unicast or
+                                            multicast forwarded through the XGS switching fabric
+                                            - 0: Unicast
+                                            - 1: Mulitcast */
+            uint32_t tc             : 4;  /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS)
+                                            the switching fabric will provide when forwarding the packet
+                                            through the fabric */
+            uint32_t dst_modid_mgid : 8;  /**< When MCST=0, this field indicates the destination XGS module to
+                                            which the packet will be delivered. When MCST=1, this field indicates
+                                            higher order bits of the Multicast Group ID. */
+            uint32_t dst_pid_mgid   : 8;  /**< When MCST=0, this field indicates a port associated with the
+                                            module indicated by the DST_MODID, through which the packet
+                                            will exit the system. When MCST=1, this field indicates lower order
+                                            bits of the Multicast Group ID */
+        } s;
+    } dw0;
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t src_modid      : 8;  /**< Source Module ID indicates the source XGS module from which
+                                            the packet is originated. (It can also be used for the fabric multicast
+                                            load balancing purpose.) */
+            uint32_t src_pid        : 8;  /**< Source Port ID indicates a port associated with the module
+                                            indicated by the SRC_MODID, through which the packet has
+                                            entered the system */
+            uint32_t lbid           : 8;  /**< Load Balancing ID indicates a packet flow hashing index
+                                            computed by the ingress XGS module for statistical distribution of
+                                            packet flows through a multipath fabric */
+            uint32_t dp             : 2;  /**< Drop Precedence indicates the traffic rate violation status of the
+                                            packet measured by the ingress module.
+                                            - 00: GREEN
+                                            - 01: RED
+                                            - 10: Reserved
+                                            - 11: Yellow */
+            uint32_t reserved_3_5   : 3;
+            uint32_t ppd_type       : 3;  /**< Packet Processing Descriptor Type
+                                            - 000: PPD Overlay1
+                                            - 001: PPD Overlay2
+                                            - 010~111: Reserved */
+        } s;
+    } dw1;
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t dst_t          : 1;  /**< Destination Trunk: Indicates that the destination port is a member of a trunk
+                                            group. */
+            uint32_t dst_tgid       : 3;  /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
+                                            DO_NOT_LEARN bit is overlaid on the second bit of this field. */
+            uint32_t ingress_tagged : 1;  /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
+                                            ingressed the system. */
+            uint32_t mirror_only    : 1;  /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
+                                            needs to be mirrored. */
+            uint32_t mirror_done    : 1;  /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
+                                            may still need to be switched. */
+            uint32_t mirror         : 1;  /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
+                                            packet was switched and only needs to be mirrored. */
+            uint32_t reserved_22_23 : 2;
+            uint32_t l3             : 1;  /**< L3: Indicates that the packet is L3 switched */
+            uint32_t label_present  : 1;  /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
+                                            added field. */
+            uint32_t vc_label       : 20; /**< Refer to the HiGig+ Architecture Specification */
+        } o1;
+        struct
+        {
+            uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
+            uint32_t reserved_0_15  : 16;
+        } o2;
+    } dw2;
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t vid            : 16; /**< VLAN tag information */
+            uint32_t pfm            : 2;  /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
+                                            multicast (unknown L2 multicast and IPMC) packets. This field is used
+                                            when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
+                                            For registered L2 multicast packets:
+                                                PFM= 0 ­ Flood to VLAN
+                                                PFM= 1 or 2 ­ Send to group members in the L2MC table
+                                            For unregistered L2 multicast packets:
+                                                PFM= 0 or 1 ­ Flood to VLAN
+                                                PFM= 2 ­ Drop the packet */
+            uint32_t src_t          : 1;  /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
+                                            on, else it represents the physical port the packet ingressed on. */
+            uint32_t reserved_11_12 : 2;
+            uint32_t opcode         : 3;  /**< XGS HiGig op-code, indicating the type of packet
+                                            000 =     Control frames used for CPU to CPU communications
+                                            001 =     Unicast packet with destination resolved; The packet can be
+                                                      either Layer 2 unicast packet or L3 unicast packet that was
+                                                      routed in the ingress chip.
+                                            010 =     Broadcast or unknown Unicast packet or unknown multicast,
+                                                      destined to all members of the VLAN
+                                            011 =     L2 Multicast packet, destined to all ports of the group indicated
+                                                      in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
+                                            100 =     IP Multicast packet, destined to all ports of the group indicated
+                                                      in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
+                                            101 =     Reserved
+                                            110 =     Reserved
+                                            111 =     Reserved */
+            uint32_t hdr_ext_len    : 3;  /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
+                                            to the standard 12-bytes of XGS HiGig header. Each unit represents 4
+                                            bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
+                                            and b'111' are reserved. For HGI field value of b'01' this field should be
+                                            b'01'. For all other values of HGI it is don't care. */
+            uint32_t reserved_0_4   : 5;
+        } s;
+    } dw3;
+} cvmx_higig2_header_t;
+
 
 /**
  * Initialize the HiGig aspects of a XAUI interface. This function
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt-decodes.c b/sys/contrib/octeon-sdk/cvmx-interrupt-decodes.c
deleted file mode 100644
index 0902492..0000000
--- a/sys/contrib/octeon-sdk/cvmx-interrupt-decodes.c
+++ /dev/null
@@ -1,3584 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Automatically generated functions useful for enabling
- * and decoding RSL_INT_BLOCKS interrupts.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- */
-
-#include "cvmx.h"
-#include "cvmx-interrupt.h"
-#include "cvmx-pcie.h"
-
-#ifndef PRINT_ERROR
-#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
-#endif
-
-void __cvmx_interrupt_pci_int_enb2_enable(void);
-void __cvmx_interrupt_pci_int_sum2_decode(void);
-void __cvmx_interrupt_pescx_dbg_info_en_enable(int index);
-void __cvmx_interrupt_pescx_dbg_info_decode(int index);
-
-/**
- * __cvmx_interrupt_agl_gmx_rxx_int_en_enable enables all interrupt bits in cvmx_agl_gmx_rxx_int_en_t
- */
-void __cvmx_interrupt_agl_gmx_rxx_int_en_enable(int index)
-{
-    cvmx_agl_gmx_rxx_int_en_t agl_gmx_rx_int_en;
-    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index)));
-    agl_gmx_rx_int_en.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping agl_gmx_rx_int_en.s.reserved_20_63
-        agl_gmx_rx_int_en.s.pause_drp = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_16_18
-        agl_gmx_rx_int_en.s.ifgerr = 1;
-        //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        agl_gmx_rx_int_en.s.ovrerr = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_9_9
-        agl_gmx_rx_int_en.s.skperr = 1;
-        agl_gmx_rx_int_en.s.rcverr = 1;
-        agl_gmx_rx_int_en.s.lenerr = 1;
-        agl_gmx_rx_int_en.s.alnerr = 1;
-        agl_gmx_rx_int_en.s.fcserr = 1;
-        agl_gmx_rx_int_en.s.jabber = 1;
-        agl_gmx_rx_int_en.s.maxerr = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_1_1
-        agl_gmx_rx_int_en.s.minerr = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping agl_gmx_rx_int_en.s.reserved_20_63
-        agl_gmx_rx_int_en.s.pause_drp = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_16_18
-        agl_gmx_rx_int_en.s.ifgerr = 1;
-        //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        agl_gmx_rx_int_en.s.ovrerr = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_9_9
-        agl_gmx_rx_int_en.s.skperr = 1;
-        agl_gmx_rx_int_en.s.rcverr = 1;
-        agl_gmx_rx_int_en.s.lenerr = 1;
-        agl_gmx_rx_int_en.s.alnerr = 1;
-        agl_gmx_rx_int_en.s.fcserr = 1;
-        agl_gmx_rx_int_en.s.jabber = 1;
-        agl_gmx_rx_int_en.s.maxerr = 1;
-        // Skipping agl_gmx_rx_int_en.s.reserved_1_1
-        agl_gmx_rx_int_en.s.minerr = 1;
-    }
-    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_EN(index), agl_gmx_rx_int_en.u64);
-}
-
-
-/**
- * __cvmx_interrupt_agl_gmx_rxx_int_reg_decode decodes all interrupt bits in cvmx_agl_gmx_rxx_int_reg_t
- */
-void __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(int index)
-{
-    cvmx_agl_gmx_rxx_int_reg_t agl_gmx_rx_int_reg;
-    agl_gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index));
-    agl_gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_EN(index));
-    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), agl_gmx_rx_int_reg.u64);
-    // Skipping agl_gmx_rx_int_reg.s.reserved_20_63
-    if (agl_gmx_rx_int_reg.s.pause_drp)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", index);
-    // Skipping agl_gmx_rx_int_reg.s.reserved_16_18
-    if (agl_gmx_rx_int_reg.s.ifgerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
-                    "    Does not necessarily indicate a failure\n", index);
-    if (agl_gmx_rx_int_reg.s.coldet)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[COLDET]: Collision Detection\n", index);
-    if (agl_gmx_rx_int_reg.s.falerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", index);
-    if (agl_gmx_rx_int_reg.s.rsverr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RSVERR]: MII reserved opcodes\n", index);
-    if (agl_gmx_rx_int_reg.s.pcterr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", index);
-    if (agl_gmx_rx_int_reg.s.ovrerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
-                    "    This interrupt should never assert\n", index);
-    // Skipping agl_gmx_rx_int_reg.s.reserved_9_9
-    if (agl_gmx_rx_int_reg.s.skperr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[SKPERR]: Skipper error\n", index);
-    if (agl_gmx_rx_int_reg.s.rcverr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RCVERR]: Frame was received with MII Data reception error\n", index);
-    if (agl_gmx_rx_int_reg.s.lenerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[LENERR]: Frame was received with length error\n", index);
-    if (agl_gmx_rx_int_reg.s.alnerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", index);
-    if (agl_gmx_rx_int_reg.s.fcserr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", index);
-    if (agl_gmx_rx_int_reg.s.jabber)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", index);
-    if (agl_gmx_rx_int_reg.s.maxerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", index);
-    // Skipping agl_gmx_rx_int_reg.s.reserved_1_1
-    if (agl_gmx_rx_int_reg.s.minerr)
-        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_fpa_int_enb_enable enables all interrupt bits in cvmx_fpa_int_enb_t
- */
-void __cvmx_interrupt_fpa_int_enb_enable(void)
-{
-    cvmx_fpa_int_enb_t fpa_int_enb;
-    cvmx_write_csr(CVMX_FPA_INT_SUM, cvmx_read_csr(CVMX_FPA_INT_SUM));
-    fpa_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping fpa_int_enb.s.reserved_28_63
-        fpa_int_enb.s.q7_perr = 1;
-        fpa_int_enb.s.q7_coff = 1;
-        fpa_int_enb.s.q7_und = 1;
-        fpa_int_enb.s.q6_perr = 1;
-        fpa_int_enb.s.q6_coff = 1;
-        fpa_int_enb.s.q6_und = 1;
-        fpa_int_enb.s.q5_perr = 1;
-        fpa_int_enb.s.q5_coff = 1;
-        fpa_int_enb.s.q5_und = 1;
-        fpa_int_enb.s.q4_perr = 1;
-        fpa_int_enb.s.q4_coff = 1;
-        fpa_int_enb.s.q4_und = 1;
-        fpa_int_enb.s.q3_perr = 1;
-        fpa_int_enb.s.q3_coff = 1;
-        fpa_int_enb.s.q3_und = 1;
-        fpa_int_enb.s.q2_perr = 1;
-        fpa_int_enb.s.q2_coff = 1;
-        fpa_int_enb.s.q2_und = 1;
-        fpa_int_enb.s.q1_perr = 1;
-        fpa_int_enb.s.q1_coff = 1;
-        fpa_int_enb.s.q1_und = 1;
-        fpa_int_enb.s.q0_perr = 1;
-        fpa_int_enb.s.q0_coff = 1;
-        fpa_int_enb.s.q0_und = 1;
-        fpa_int_enb.s.fed1_dbe = 1;
-        fpa_int_enb.s.fed1_sbe = 1;
-        fpa_int_enb.s.fed0_dbe = 1;
-        fpa_int_enb.s.fed0_sbe = 1;
-    }
-    cvmx_write_csr(CVMX_FPA_INT_ENB, fpa_int_enb.u64);
-}
-
-
-/**
- * __cvmx_interrupt_fpa_int_sum_decode decodes all interrupt bits in cvmx_fpa_int_sum_t
- */
-void __cvmx_interrupt_fpa_int_sum_decode(void)
-{
-    cvmx_fpa_int_sum_t fpa_int_sum;
-    fpa_int_sum.u64 = cvmx_read_csr(CVMX_FPA_INT_SUM);
-    fpa_int_sum.u64 &= cvmx_read_csr(CVMX_FPA_INT_ENB);
-    cvmx_write_csr(CVMX_FPA_INT_SUM, fpa_int_sum.u64);
-    // Skipping fpa_int_sum.s.reserved_28_63
-    if (fpa_int_sum.s.q7_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q7_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q7_und)
-        PRINT_ERROR("FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q6_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q6_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q6_und)
-        PRINT_ERROR("FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q5_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q5_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q5_und)
-        PRINT_ERROR("FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q4_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q4_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q4_und)
-        PRINT_ERROR("FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q3_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q3_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q3_und)
-        PRINT_ERROR("FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q2_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q2_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q2_und)
-        PRINT_ERROR("FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q1_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q1_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q1_und)
-        PRINT_ERROR("FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.q0_perr)
-        PRINT_ERROR("FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
-                    "    the L2C does not have the FPA owner ship bit set.\n");
-    if (fpa_int_sum.s.q0_coff)
-        PRINT_ERROR("FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
-                    "    the count available is greater than pointers\n"
-                    "    present in the FPA.\n");
-    if (fpa_int_sum.s.q0_und)
-        PRINT_ERROR("FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
-                    "    negative.\n");
-    if (fpa_int_sum.s.fed1_dbe)
-        PRINT_ERROR("FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n");
-    if (fpa_int_sum.s.fed1_sbe)
-        PRINT_ERROR("FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n");
-    if (fpa_int_sum.s.fed0_dbe)
-        PRINT_ERROR("FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n");
-    if (fpa_int_sum.s.fed0_sbe)
-        PRINT_ERROR("FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n");
-}
-
-
-/**
- * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
- */
-void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
-{
-    cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
-    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
-    gmx_rx_int_en.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_29_63
-        gmx_rx_int_en.s.hg2cc = 1;
-        gmx_rx_int_en.s.hg2fld = 1;
-        gmx_rx_int_en.s.undat = 1;
-        gmx_rx_int_en.s.uneop = 1;
-        gmx_rx_int_en.s.unsop = 1;
-        gmx_rx_int_en.s.bad_term = 1;
-        gmx_rx_int_en.s.bad_seq = 1;
-        gmx_rx_int_en.s.rem_fault = 1;
-        gmx_rx_int_en.s.loc_fault = 1;
-        gmx_rx_int_en.s.pause_drp = 1;
-        // Skipping gmx_rx_int_en.s.reserved_16_18
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        // Skipping gmx_rx_int_en.s.reserved_9_9
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        // Skipping gmx_rx_int_en.s.reserved_5_6
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        // Skipping gmx_rx_int_en.s.reserved_2_2
-        gmx_rx_int_en.s.carext = 1;
-        // Skipping gmx_rx_int_en.s.reserved_0_0
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_19_63
-        //gmx_rx_int_en.s.phy_dupx = 1;
-        //gmx_rx_int_en.s.phy_spd = 1;
-        //gmx_rx_int_en.s.phy_link = 1;
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        gmx_rx_int_en.s.niberr = 1;
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
-        gmx_rx_int_en.s.alnerr = 1;
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        gmx_rx_int_en.s.maxerr = 1;
-        gmx_rx_int_en.s.carext = 1;
-        gmx_rx_int_en.s.minerr = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_20_63
-        gmx_rx_int_en.s.pause_drp = 1;
-        //gmx_rx_int_en.s.phy_dupx = 1;
-        //gmx_rx_int_en.s.phy_spd = 1;
-        //gmx_rx_int_en.s.phy_link = 1;
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        gmx_rx_int_en.s.niberr = 1;
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        // Skipping gmx_rx_int_en.s.reserved_6_6
-        gmx_rx_int_en.s.alnerr = 1;
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        // Skipping gmx_rx_int_en.s.reserved_2_2
-        gmx_rx_int_en.s.carext = 1;
-        // Skipping gmx_rx_int_en.s.reserved_0_0
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_19_63
-        //gmx_rx_int_en.s.phy_dupx = 1;
-        //gmx_rx_int_en.s.phy_spd = 1;
-        //gmx_rx_int_en.s.phy_link = 1;
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        gmx_rx_int_en.s.niberr = 1;
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
-        gmx_rx_int_en.s.alnerr = 1;
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        gmx_rx_int_en.s.maxerr = 1;
-        gmx_rx_int_en.s.carext = 1;
-        gmx_rx_int_en.s.minerr = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_19_63
-        //gmx_rx_int_en.s.phy_dupx = 1;
-        //gmx_rx_int_en.s.phy_spd = 1;
-        //gmx_rx_int_en.s.phy_link = 1;
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        gmx_rx_int_en.s.niberr = 1;
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
-        gmx_rx_int_en.s.alnerr = 1;
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        gmx_rx_int_en.s.maxerr = 1;
-        gmx_rx_int_en.s.carext = 1;
-        gmx_rx_int_en.s.minerr = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_20_63
-        gmx_rx_int_en.s.pause_drp = 1;
-        //gmx_rx_int_en.s.phy_dupx = 1;
-        //gmx_rx_int_en.s.phy_spd = 1;
-        //gmx_rx_int_en.s.phy_link = 1;
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        gmx_rx_int_en.s.niberr = 1;
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
-        gmx_rx_int_en.s.alnerr = 1;
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        gmx_rx_int_en.s.maxerr = 1;
-        gmx_rx_int_en.s.carext = 1;
-        gmx_rx_int_en.s.minerr = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping gmx_rx_int_en.s.reserved_29_63
-        gmx_rx_int_en.s.hg2cc = 1;
-        gmx_rx_int_en.s.hg2fld = 1;
-        gmx_rx_int_en.s.undat = 1;
-        gmx_rx_int_en.s.uneop = 1;
-        gmx_rx_int_en.s.unsop = 1;
-        gmx_rx_int_en.s.bad_term = 1;
-        gmx_rx_int_en.s.bad_seq = 0;
-        gmx_rx_int_en.s.rem_fault = 1;
-        gmx_rx_int_en.s.loc_fault = 0;
-        gmx_rx_int_en.s.pause_drp = 1;
-        // Skipping gmx_rx_int_en.s.reserved_16_18
-        //gmx_rx_int_en.s.ifgerr = 1;
-        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
-        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
-        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
-        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
-        gmx_rx_int_en.s.ovrerr = 1;
-        // Skipping gmx_rx_int_en.s.reserved_9_9
-        gmx_rx_int_en.s.skperr = 1;
-        gmx_rx_int_en.s.rcverr = 1;
-        // Skipping gmx_rx_int_en.s.reserved_5_6
-        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
-        gmx_rx_int_en.s.jabber = 1;
-        // Skipping gmx_rx_int_en.s.reserved_2_2
-        gmx_rx_int_en.s.carext = 1;
-        // Skipping gmx_rx_int_en.s.reserved_0_0
-    }
-    cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
-}
-
-
-/**
- * __cvmx_interrupt_gmxx_rxx_int_reg_decode decodes all interrupt bits in cvmx_gmxx_rxx_int_reg_t
- */
-void __cvmx_interrupt_gmxx_rxx_int_reg_decode(int index, int block)
-{
-    cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
-    gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block));
-    /* Don't clear inband status bits so someone else can use them */
-    gmx_rx_int_reg.s.phy_dupx = 0;
-    gmx_rx_int_reg.s.phy_spd = 0;
-    gmx_rx_int_reg.s.phy_link = 0;
-    gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, block));
-    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), gmx_rx_int_reg.u64);
-    // Skipping gmx_rx_int_reg.s.reserved_29_63
-    if (gmx_rx_int_reg.s.hg2cc)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2CC]: HiGig2 received message CRC or Control char  error\n"
-                    "    Set when either CRC8 error detected or when\n"
-                    "    a Control Character is found in the message\n"
-                    "    bytes after the K.SOM\n"
-                    "    NOTE: HG2CC has higher priority than HG2FLD\n"
-                    "          i.e. a HiGig2 message that results in HG2CC\n"
-                    "          getting set, will never set HG2FLD.\n", block, index);
-    if (gmx_rx_int_reg.s.hg2fld)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2FLD]: HiGig2 received message field error, as below\n"
-                    "    1) MSG_TYPE field not 6'b00_0000\n"
-                    "       i.e. it is not a FLOW CONTROL message, which\n"
-                    "       is the only defined type for HiGig2\n"
-                    "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
-                    "       which is the only defined type for HiGig2\n"
-                    "    3) FC_OBJECT field is neither 4'b0000 for\n"
-                    "       Physical Link nor 4'b0010 for Logical Link.\n"
-                    "       Those are the only two defined types in HiGig2\n", block, index);
-    if (gmx_rx_int_reg.s.undat)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNDAT]: Unexpected Data\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.uneop)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNEOP]: Unexpected EOP\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.unsop)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNSOP]: Unexpected SOP\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.bad_term)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_TERM]: Frame is terminated by control character other\n"
-                    "    than /T/.  The error propagation control\n"
-                    "    character /E/ will be included as part of the\n"
-                    "    frame and does not cause a frame termination.\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.bad_seq)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_SEQ]: Reserved Sequence Deteted\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.rem_fault)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[REM_FAULT]: Remote Fault Sequence Deteted\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.loc_fault)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[LOC_FAULT]: Local Fault Sequence Deteted\n"
-                    "    (XAUI Mode only)\n", block, index);
-    if (gmx_rx_int_reg.s.pause_drp)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", block, index);
-#if 0
-    if (gmx_rx_int_reg.s.phy_dupx)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_DUPX]: Change in the RMGII inbound LinkDuplex\n", block, index);
-    if (gmx_rx_int_reg.s.phy_spd)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_SPD]: Change in the RMGII inbound LinkSpeed\n", block, index);
-    if (gmx_rx_int_reg.s.phy_link)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_LINK]: Change in the RMGII inbound LinkStatus\n", block, index);
-#endif
-    if (gmx_rx_int_reg.s.ifgerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
-                    "    Does not necessarily indicate a failure\n", block, index);
-    if (gmx_rx_int_reg.s.coldet)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[COLDET]: Collision Detection\n", block, index);
-    if (gmx_rx_int_reg.s.falerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", block, index);
-    if (gmx_rx_int_reg.s.rsverr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[RSVERR]: RGMII reserved opcodes\n", block, index);
-    if (gmx_rx_int_reg.s.pcterr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", block, index);
-    if (gmx_rx_int_reg.s.ovrerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
-                    "    This interrupt should never assert\n", block, index);
-    if (gmx_rx_int_reg.s.niberr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n", block, index);
-    if (gmx_rx_int_reg.s.skperr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[SKPERR]: Skipper error\n", block, index);
-    if (gmx_rx_int_reg.s.rcverr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[RCVERR]: Frame was received with RMGII Data reception error\n", block, index);
-    if (gmx_rx_int_reg.s.lenerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[LENERR]: Frame was received with length error\n", block, index);
-    if (gmx_rx_int_reg.s.alnerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", block, index);
-    if (gmx_rx_int_reg.s.fcserr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", block, index);
-    if (gmx_rx_int_reg.s.jabber)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", block, index);
-    if (gmx_rx_int_reg.s.maxerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", block, index);
-    if (gmx_rx_int_reg.s.carext)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[CAREXT]: RGMII carrier extend error\n", block, index);
-    if (gmx_rx_int_reg.s.minerr)
-        PRINT_ERROR("GMX%d_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", block, index);
-}
-
-
-/**
- * __cvmx_interrupt_iob_int_enb_enable enables all interrupt bits in cvmx_iob_int_enb_t
- */
-void __cvmx_interrupt_iob_int_enb_enable(void)
-{
-    cvmx_iob_int_enb_t iob_int_enb;
-    cvmx_write_csr(CVMX_IOB_INT_SUM, cvmx_read_csr(CVMX_IOB_INT_SUM));
-    iob_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping iob_int_enb.s.reserved_6_63
-        iob_int_enb.s.p_dat = 1;
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        /* These interrupts are disabled on CN56XXp2.X due to errata IOB-800 */
-        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X))
-        {
-            iob_int_enb.s.np_dat = 1;
-            iob_int_enb.s.np_eop = 1;
-            iob_int_enb.s.np_sop = 1;
-        }
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping iob_int_enb.s.reserved_4_63
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        iob_int_enb.s.np_eop = 1;
-        iob_int_enb.s.np_sop = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping iob_int_enb.s.reserved_6_63
-        iob_int_enb.s.p_dat = 1;
-        iob_int_enb.s.np_dat = 1;
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        iob_int_enb.s.np_eop = 1;
-        iob_int_enb.s.np_sop = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping iob_int_enb.s.reserved_4_63
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        iob_int_enb.s.np_eop = 1;
-        iob_int_enb.s.np_sop = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping iob_int_enb.s.reserved_4_63
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        iob_int_enb.s.np_eop = 1;
-        iob_int_enb.s.np_sop = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping iob_int_enb.s.reserved_6_63
-        iob_int_enb.s.p_dat = 1;
-        iob_int_enb.s.np_dat = 1;
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        iob_int_enb.s.np_eop = 1;
-        iob_int_enb.s.np_sop = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping iob_int_enb.s.reserved_6_63
-        iob_int_enb.s.p_dat = 1;
-        iob_int_enb.s.p_eop = 1;
-        iob_int_enb.s.p_sop = 1;
-        /* These interrupts are disabled on CN52XXp2.X due to errata IOB-800 */
-        if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X))
-        {
-            iob_int_enb.s.np_dat = 1;
-            iob_int_enb.s.np_eop = 1;
-            iob_int_enb.s.np_sop = 1;
-        }
-    }
-    cvmx_write_csr(CVMX_IOB_INT_ENB, iob_int_enb.u64);
-}
-
-
-/**
- * __cvmx_interrupt_iob_int_sum_decode decodes all interrupt bits in cvmx_iob_int_sum_t
- */
-void __cvmx_interrupt_iob_int_sum_decode(void)
-{
-    cvmx_iob_int_sum_t iob_int_sum;
-    iob_int_sum.u64 = cvmx_read_csr(CVMX_IOB_INT_SUM);
-    iob_int_sum.u64 &= cvmx_read_csr(CVMX_IOB_INT_ENB);
-    cvmx_write_csr(CVMX_IOB_INT_SUM, iob_int_sum.u64);
-    // Skipping iob_int_sum.s.reserved_6_63
-    if (iob_int_sum.s.p_dat)
-        PRINT_ERROR("IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
-                    "    port for a passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-    if (iob_int_sum.s.np_dat)
-        PRINT_ERROR("IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
-                    "    port for a non-passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-    if (iob_int_sum.s.p_eop)
-        PRINT_ERROR("IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
-                    "    port for a passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-    if (iob_int_sum.s.p_sop)
-        PRINT_ERROR("IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
-                    "    port for a passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-    if (iob_int_sum.s.np_eop)
-        PRINT_ERROR("IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
-                    "    port for a non-passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-    if (iob_int_sum.s.np_sop)
-        PRINT_ERROR("IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
-                    "    port for a non-passthrough packet.\n"
-                    "    The first detected error associated with bits [5:0]\n"
-                    "    of this register will only be set here. A new bit\n"
-                    "    can be set when the previous reported bit is cleared.\n");
-}
-
-
-/**
- * __cvmx_interrupt_ipd_int_enb_enable enables all interrupt bits in cvmx_ipd_int_enb_t
- */
-void __cvmx_interrupt_ipd_int_enb_enable(void)
-{
-    cvmx_ipd_int_enb_t ipd_int_enb;
-    cvmx_write_csr(CVMX_IPD_INT_SUM, cvmx_read_csr(CVMX_IPD_INT_SUM));
-    ipd_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_12_63
-        //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
-        //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
-        ipd_int_enb.s.bc_ovr = 1;
-        ipd_int_enb.s.d_coll = 1;
-        ipd_int_enb.s.c_coll = 1;
-        ipd_int_enb.s.cc_ovr = 1;
-        ipd_int_enb.s.dc_ovr = 1;
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_5_63
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_10_63
-        ipd_int_enb.s.bc_ovr = 1;
-        ipd_int_enb.s.d_coll = 1;
-        ipd_int_enb.s.c_coll = 1;
-        ipd_int_enb.s.cc_ovr = 1;
-        ipd_int_enb.s.dc_ovr = 1;
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_10_63
-        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
-        {
-            ipd_int_enb.s.bc_ovr = 1;
-            ipd_int_enb.s.d_coll = 1;
-            ipd_int_enb.s.c_coll = 1;
-            ipd_int_enb.s.cc_ovr = 1;
-            ipd_int_enb.s.dc_ovr = 1;
-        }
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_5_63
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_10_63
-        ipd_int_enb.s.bc_ovr = 1;
-        ipd_int_enb.s.d_coll = 1;
-        ipd_int_enb.s.c_coll = 1;
-        ipd_int_enb.s.cc_ovr = 1;
-        ipd_int_enb.s.dc_ovr = 1;
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping ipd_int_enb.s.reserved_12_63
-        //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
-        //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
-        ipd_int_enb.s.bc_ovr = 1;
-        ipd_int_enb.s.d_coll = 1;
-        ipd_int_enb.s.c_coll = 1;
-        ipd_int_enb.s.cc_ovr = 1;
-        ipd_int_enb.s.dc_ovr = 1;
-        ipd_int_enb.s.bp_sub = 1;
-        ipd_int_enb.s.prc_par3 = 1;
-        ipd_int_enb.s.prc_par2 = 1;
-        ipd_int_enb.s.prc_par1 = 1;
-        ipd_int_enb.s.prc_par0 = 1;
-    }
-    cvmx_write_csr(CVMX_IPD_INT_ENB, ipd_int_enb.u64);
-}
-
-
-/**
- * __cvmx_interrupt_ipd_int_sum_decode decodes all interrupt bits in cvmx_ipd_int_sum_t
- */
-void __cvmx_interrupt_ipd_int_sum_decode(void)
-{
-    cvmx_ipd_int_sum_t ipd_int_sum;
-    ipd_int_sum.u64 = cvmx_read_csr(CVMX_IPD_INT_SUM);
-    ipd_int_sum.u64 &= cvmx_read_csr(CVMX_IPD_INT_ENB);
-    cvmx_write_csr(CVMX_IPD_INT_SUM, ipd_int_sum.u64);
-    // Skipping ipd_int_sum.s.reserved_12_63
-    if (ipd_int_sum.s.pq_sub)
-        PRINT_ERROR("IPD_INT_SUM[PQ_SUB]: Set when a port-qos does an sub to the count\n"
-                    "    that causes the counter to wrap.\n");
-    if (ipd_int_sum.s.pq_add)
-        PRINT_ERROR("IPD_INT_SUM[PQ_ADD]: Set when a port-qos does an add to the count\n"
-                    "    that causes the counter to wrap.\n");
-    if (ipd_int_sum.s.bc_ovr)
-        PRINT_ERROR("IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
-                    "    This is a PASS-3 Field.\n");
-    if (ipd_int_sum.s.d_coll)
-        PRINT_ERROR("IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
-                    "    collides.\n"
-                    "    This is a PASS-3 Field.\n");
-    if (ipd_int_sum.s.c_coll)
-        PRINT_ERROR("IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
-                    "    collides.\n"
-                    "    This is a PASS-3 Field.\n");
-    if (ipd_int_sum.s.cc_ovr)
-        PRINT_ERROR("IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
-                    "    This is a PASS-3 Field.\n");
-    if (ipd_int_sum.s.dc_ovr)
-        PRINT_ERROR("IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
-                    "    This is a PASS-3 Field.\n");
-    if (ipd_int_sum.s.bp_sub)
-        PRINT_ERROR("IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
-                    "    supplied illegal value.\n");
-    if (ipd_int_sum.s.prc_par3)
-        PRINT_ERROR("IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
-                    "    [127:96] of the PBM memory.\n");
-    if (ipd_int_sum.s.prc_par2)
-        PRINT_ERROR("IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
-                    "    [95:64] of the PBM memory.\n");
-    if (ipd_int_sum.s.prc_par1)
-        PRINT_ERROR("IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
-                    "    [63:32] of the PBM memory.\n");
-    if (ipd_int_sum.s.prc_par0)
-        PRINT_ERROR("IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
-                    "    [31:0] of the PBM memory.\n");
-}
-
-
-/**
- * __cvmx_interrupt_key_int_enb_enable enables all interrupt bits in cvmx_key_int_enb_t
- */
-void __cvmx_interrupt_key_int_enb_enable(void)
-{
-    cvmx_key_int_enb_t key_int_enb;
-    cvmx_write_csr(CVMX_KEY_INT_SUM, cvmx_read_csr(CVMX_KEY_INT_SUM));
-    key_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping key_int_enb.s.reserved_4_63
-        key_int_enb.s.ked1_dbe = 1;
-        key_int_enb.s.ked1_sbe = 1;
-        key_int_enb.s.ked0_dbe = 1;
-        key_int_enb.s.ked0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping key_int_enb.s.reserved_4_63
-        key_int_enb.s.ked1_dbe = 1;
-        key_int_enb.s.ked1_sbe = 1;
-        key_int_enb.s.ked0_dbe = 1;
-        key_int_enb.s.ked0_sbe = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping key_int_enb.s.reserved_4_63
-        key_int_enb.s.ked1_dbe = 1;
-        key_int_enb.s.ked1_sbe = 1;
-        key_int_enb.s.ked0_dbe = 1;
-        key_int_enb.s.ked0_sbe = 1;
-    }
-    cvmx_write_csr(CVMX_KEY_INT_ENB, key_int_enb.u64);
-}
-
-
-/**
- * __cvmx_interrupt_key_int_sum_decode decodes all interrupt bits in cvmx_key_int_sum_t
- */
-void __cvmx_interrupt_key_int_sum_decode(void)
-{
-    cvmx_key_int_sum_t key_int_sum;
-    key_int_sum.u64 = cvmx_read_csr(CVMX_KEY_INT_SUM);
-    key_int_sum.u64 &= cvmx_read_csr(CVMX_KEY_INT_ENB);
-    cvmx_write_csr(CVMX_KEY_INT_SUM, key_int_sum.u64);
-    // Skipping key_int_sum.s.reserved_4_63
-    if (key_int_sum.s.ked1_dbe)
-        PRINT_ERROR("KEY_INT_SUM[KED1_DBE]: Error bit\n");
-    if (key_int_sum.s.ked1_sbe)
-        PRINT_ERROR("KEY_INT_SUM[KED1_SBE]: Error bit\n");
-    if (key_int_sum.s.ked0_dbe)
-        PRINT_ERROR("KEY_INT_SUM[KED0_DBE]: Error bit\n");
-    if (key_int_sum.s.ked0_sbe)
-        PRINT_ERROR("KEY_INT_SUM[KED0_SBE]: Error bit\n");
-}
-
-
-/**
- * __cvmx_interrupt_mio_boot_int_enable enables all interrupt bits in cvmx_mio_boot_int_t
- */
-void __cvmx_interrupt_mio_boot_int_enable(void)
-{
-    cvmx_mio_boot_int_t mio_boot_int;
-    cvmx_write_csr(CVMX_MIO_BOOT_ERR, cvmx_read_csr(CVMX_MIO_BOOT_ERR));
-    mio_boot_int.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping mio_boot_int.s.reserved_2_63
-        mio_boot_int.s.wait_int = 1;
-        mio_boot_int.s.adr_int = 1;
-    }
-    cvmx_write_csr(CVMX_MIO_BOOT_INT, mio_boot_int.u64);
-}
-
-
-/**
- * __cvmx_interrupt_mio_boot_err_decode decodes all interrupt bits in cvmx_mio_boot_err_t
- */
-void __cvmx_interrupt_mio_boot_err_decode(void)
-{
-    cvmx_mio_boot_err_t mio_boot_err;
-    mio_boot_err.u64 = cvmx_read_csr(CVMX_MIO_BOOT_ERR);
-    mio_boot_err.u64 &= cvmx_read_csr(CVMX_MIO_BOOT_INT);
-    cvmx_write_csr(CVMX_MIO_BOOT_ERR, mio_boot_err.u64);
-    // Skipping mio_boot_err.s.reserved_2_63
-    if (mio_boot_err.s.wait_err)
-        PRINT_ERROR("MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n");
-    if (mio_boot_err.s.adr_err)
-        PRINT_ERROR("MIO_BOOT_ERR[ADR_ERR]: Address decode error\n");
-}
-
-
-/**
- * __cvmx_interrupt_npei_int_sum_decode decodes all interrupt bits in cvmx_npei_int_sum_t
- */
-void __cvmx_interrupt_npei_int_sum_decode(void)
-{
-    cvmx_npei_int_sum_t npei_int_sum;
-    npei_int_sum.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM);
-    /* Note that NPEI_INT_ENB2 controls the internal RSL interrupts.
-        NPEI_INT_ENB controls external forwarding which is not what we
-        want. It is a little strange that we are using NPEI_INT_SUM with
-        NPEI_INT_ENB2, but we need the R/W version of NPEI_INT_SUM2 and
-        internal RSL interrupts */
-    npei_int_sum.u64 &= cvmx_read_csr(CVMX_PEXP_NPEI_INT_ENB2);
-    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, npei_int_sum.u64);
-    if (npei_int_sum.s.mio_inta)
-        PRINT_ERROR("NPEI_INT_SUM[MIO_INTA]: Interrupt from MIO.\n");
-    // Skipping npei_int_sum.s.reserved_62_62
-    if (npei_int_sum.s.int_a)
-        PRINT_ERROR("NPEI_INT_SUM[INT_A]: Set when a bit in the NPEI_INT_A_SUM register and\n"
-                    "    the cooresponding bit in the NPEI_INT_A_ENB\n"
-                    "    register is set.\n");
-    if (npei_int_sum.s.c1_ldwn)
-    {
-        cvmx_ciu_soft_prst_t ciu_soft_prst;
-        PRINT_ERROR("NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n");
-        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
-        if (!ciu_soft_prst.s.soft_prst)
-        {
-            /* Attempt to automatically bring the link back up */
-            cvmx_pcie_rc_shutdown(1);
-            cvmx_pcie_rc_initialize(1);
-        }
-        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
-    }
-    if (npei_int_sum.s.c0_ldwn)
-    {
-        cvmx_ciu_soft_prst_t ciu_soft_prst;
-        PRINT_ERROR("NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n");
-        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
-        if (!ciu_soft_prst.s.soft_prst)
-        {
-            /* Attempt to automatically bring the link back up */
-            cvmx_pcie_rc_shutdown(0);
-            cvmx_pcie_rc_initialize(0);
-        }
-        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
-    }
-    if (npei_int_sum.s.c1_exc)
-    {
-#if 0
-        PRINT_ERROR("NPEI_INT_SUM[C1_EXC]: Set when the PESC1_DBG_INFO register has a bit\n"
-                    "    set and its cooresponding PESC1_DBG_INFO_EN bit\n"
-                    "    is set.\n");
-#endif
-        __cvmx_interrupt_pescx_dbg_info_decode(1);
-    }
-    if (npei_int_sum.s.c0_exc)
-    {
-#if 0
-        PRINT_ERROR("NPEI_INT_SUM[C0_EXC]: Set when the PESC0_DBG_INFO register has a bit\n"
-                    "    set and its cooresponding PESC0_DBG_INFO_EN bit\n"
-                    "    is set.\n");
-#endif
-        __cvmx_interrupt_pescx_dbg_info_decode(0);
-    }
-    if (npei_int_sum.s.c1_up_wf)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
-                    "    register. Core1.\n");
-    if (npei_int_sum.s.c0_up_wf)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
-                    "    register. Core0.\n");
-    if (npei_int_sum.s.c1_un_wf)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
-                    "    register. Core1.\n");
-    if (npei_int_sum.s.c0_un_wf)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
-                    "    register. Core0.\n");
-    if (npei_int_sum.s.c1_un_bx)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_un_wi)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_un_b2)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_un_b1)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_un_b0)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_up_bx)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_up_wi)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_up_b2)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_up_b1)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c1_up_b0)
-        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
-                    "    Core 1.\n");
-    if (npei_int_sum.s.c0_un_bx)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_un_wi)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_un_b2)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_un_b1)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_un_b0)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_up_bx)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_up_wi)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_up_b2)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_up_b1)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c0_up_b0)
-        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
-                    "    Core 0.\n");
-    if (npei_int_sum.s.c1_hpint)
-        PRINT_ERROR("NPEI_INT_SUM[C1_HPINT]: Hot-Plug Interrupt.\n"
-                    "    Pcie Core 1 (hp_int).\n"
-                    "    This interrupt will only be generated when\n"
-                    "    PCIERC1_CFG034[DLLS_C] is generated. Hot plug is\n"
-                    "    not supported.\n");
-    if (npei_int_sum.s.c1_pmei)
-        PRINT_ERROR("NPEI_INT_SUM[C1_PMEI]: PME Interrupt.\n"
-                    "    Pcie Core 1. (cfg_pme_int)\n");
-    if (npei_int_sum.s.c1_wake)
-        PRINT_ERROR("NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
-                    "    Pcie Core 1. (wake_n)\n"
-                    "    Octeon will never generate this interrupt.\n");
-    if (npei_int_sum.s.crs1_dr)
-        PRINT_ERROR("NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n");
-    if (npei_int_sum.s.c1_se)
-        PRINT_ERROR("NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
-                    "    Pcie Core 1. (cfg_sys_err_rc)\n");
-    if (npei_int_sum.s.crs1_er)
-        PRINT_ERROR("NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n");
-    if (npei_int_sum.s.c1_aeri)
-        PRINT_ERROR("NPEI_INT_SUM[C1_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
-                    "    Pcie Core 1.\n");
-    if (npei_int_sum.s.c0_hpint)
-        PRINT_ERROR("NPEI_INT_SUM[C0_HPINT]: Hot-Plug Interrupt.\n"
-                    "    Pcie Core 0 (hp_int).\n"
-                    "    This interrupt will only be generated when\n"
-                    "    PCIERC0_CFG034[DLLS_C] is generated. Hot plug is\n"
-                    "    not supported.\n");
-    if (npei_int_sum.s.c0_pmei)
-        PRINT_ERROR("NPEI_INT_SUM[C0_PMEI]: PME Interrupt.\n"
-                    "    Pcie Core 0. (cfg_pme_int)\n");
-    if (npei_int_sum.s.c0_wake)
-        PRINT_ERROR("NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
-                    "    Pcie Core 0. (wake_n)\n"
-                    "    Octeon will never generate this interrupt.\n");
-    if (npei_int_sum.s.crs0_dr)
-        PRINT_ERROR("NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n");
-    if (npei_int_sum.s.c0_se)
-        PRINT_ERROR("NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
-                    "    Pcie Core 0. (cfg_sys_err_rc)\n");
-    if (npei_int_sum.s.crs0_er)
-        PRINT_ERROR("NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n");
-    if (npei_int_sum.s.c0_aeri)
-        PRINT_ERROR("NPEI_INT_SUM[C0_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
-                    "    Pcie Core 0 (cfg_aer_rc_err_int).\n");
-    if (npei_int_sum.s.ptime)
-        PRINT_ERROR("NPEI_INT_SUM[PTIME]: Packet Timer has an interrupt. Which rings can\n"
-                    "    be found in NPEI_PKT_TIME_INT.\n");
-    if (npei_int_sum.s.pcnt)
-        PRINT_ERROR("NPEI_INT_SUM[PCNT]: Packet Counter has an interrupt. Which rings can\n"
-                    "    be found in NPEI_PKT_CNT_INT.\n");
-    if (npei_int_sum.s.pidbof)
-        PRINT_ERROR("NPEI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
-                    "    doorbell can be found in NPEI_INT_INFO[PIDBOF]\n");
-    if (npei_int_sum.s.psldbof)
-        PRINT_ERROR("NPEI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
-                    "    doorbell can be found in NPEI_INT_INFO[PSLDBOF]\n");
-    if (npei_int_sum.s.dtime1)
-        PRINT_ERROR("NPEI_INT_SUM[DTIME1]: Whenever NPEI_DMA_CNTS[DMA1] is not 0, the\n"
-                    "    DMA_CNT1 timer increments every core clock. When\n"
-                    "    DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],\n"
-                    "    this bit is set. Writing a '1' to this bit also\n"
-                    "    clears the DMA_CNT1 timer.\n");
-    if (npei_int_sum.s.dtime0)
-        PRINT_ERROR("NPEI_INT_SUM[DTIME0]: Whenever NPEI_DMA_CNTS[DMA0] is not 0, the\n"
-                    "    DMA_CNT0 timer increments every core clock. When\n"
-                    "    DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],\n"
-                    "    this bit is set. Writing a '1' to this bit also\n"
-                    "    clears the DMA_CNT0 timer.\n");
-    if (npei_int_sum.s.dcnt1)
-        PRINT_ERROR("NPEI_INT_SUM[DCNT1]: This bit indicates that NPEI_DMA_CNTS[DMA1] was/is\n"
-                    "    greater than NPEI_DMA1_INT_LEVEL[CNT].\n");
-    if (npei_int_sum.s.dcnt0)
-        PRINT_ERROR("NPEI_INT_SUM[DCNT0]: This bit indicates that NPEI_DMA_CNTS[DMA0] was/is\n"
-                    "    greater than NPEI_DMA0_INT_LEVEL[CNT].\n");
-    if (npei_int_sum.s.dma1fi)
-        PRINT_ERROR("NPEI_INT_SUM[DMA1FI]: DMA0 set Forced Interrupt.\n");
-    if (npei_int_sum.s.dma0fi)
-        PRINT_ERROR("NPEI_INT_SUM[DMA0FI]: DMA0 set Forced Interrupt.\n");
-    if (npei_int_sum.s.dma4dbo)
-        PRINT_ERROR("NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
-                    "    Bit[32] of the doorbell count was set.\n");
-    if (npei_int_sum.s.dma3dbo)
-        PRINT_ERROR("NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
-                    "    Bit[32] of the doorbell count was set.\n");
-    if (npei_int_sum.s.dma2dbo)
-        PRINT_ERROR("NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
-                    "    Bit[32] of the doorbell count was set.\n");
-    if (npei_int_sum.s.dma1dbo)
-        PRINT_ERROR("NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
-                    "    Bit[32] of the doorbell count was set.\n");
-    if (npei_int_sum.s.dma0dbo)
-        PRINT_ERROR("NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
-                    "    Bit[32] of the doorbell count was set.\n");
-    if (npei_int_sum.s.iob2big)
-        PRINT_ERROR("NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n");
-    if (npei_int_sum.s.bar0_to)
-        PRINT_ERROR("NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
-                    "    read-data/commit in 0xffff core clocks.\n");
-    if (npei_int_sum.s.rml_wto)
-        PRINT_ERROR("NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n");
-    if (npei_int_sum.s.rml_rto)
-        PRINT_ERROR("NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n");
-}
-
-
-/**
- * __cvmx_interrupt_npei_int_enb2_enable enables all interrupt bits in cvmx_npei_int_enb2_t
- */
-void __cvmx_interrupt_npei_int_enb2_enable(void)
-{
-    int enable_pcie0 = 0;
-    int enable_pcie1 = 0;
-    cvmx_npei_int_enb2_t npei_int_enb2;
-    /* Reset NPEI_INT_SUM, as NPEI_INT_SUM2 is a read-only copy of NPEI_INT_SUM. */
-    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
-    npei_int_enb2.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        cvmx_pescx_ctl_status2_t pescx_ctl_status2;
-        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
-        enable_pcie0 = !pescx_ctl_status2.s.pcierst;
-        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
-        enable_pcie1 = !pescx_ctl_status2.s.pcierst;
-
-        // Skipping npei_int_enb2.s.reserved_62_63
-        npei_int_enb2.s.int_a = 1;
-        npei_int_enb2.s.c1_ldwn = enable_pcie1;
-        npei_int_enb2.s.c0_ldwn = enable_pcie0;
-        npei_int_enb2.s.c1_exc = enable_pcie1;
-        npei_int_enb2.s.c0_exc = enable_pcie0;
-        npei_int_enb2.s.c1_up_wf = enable_pcie1;
-        npei_int_enb2.s.c0_up_wf = enable_pcie0;
-        npei_int_enb2.s.c1_un_wf = enable_pcie1;
-        npei_int_enb2.s.c0_un_wf = enable_pcie0;
-        npei_int_enb2.s.c1_un_bx = enable_pcie1;
-        npei_int_enb2.s.c1_un_wi = enable_pcie1;
-        npei_int_enb2.s.c1_un_b2 = enable_pcie1;
-        npei_int_enb2.s.c1_un_b1 = enable_pcie1;
-        npei_int_enb2.s.c1_un_b0 = enable_pcie1;
-        npei_int_enb2.s.c1_up_bx = enable_pcie1;
-        npei_int_enb2.s.c1_up_wi = enable_pcie1;
-        npei_int_enb2.s.c1_up_b2 = enable_pcie1;
-        npei_int_enb2.s.c1_up_b1 = enable_pcie1;
-        npei_int_enb2.s.c1_up_b0 = enable_pcie1;
-        npei_int_enb2.s.c0_un_bx = enable_pcie0;
-        npei_int_enb2.s.c0_un_wi = enable_pcie0;
-        npei_int_enb2.s.c0_un_b2 = enable_pcie0;
-        npei_int_enb2.s.c0_un_b1 = enable_pcie0;
-        npei_int_enb2.s.c0_un_b0 = enable_pcie0;
-        npei_int_enb2.s.c0_up_bx = enable_pcie0;
-        npei_int_enb2.s.c0_up_wi = enable_pcie0;
-        npei_int_enb2.s.c0_up_b2 = enable_pcie0;
-        npei_int_enb2.s.c0_up_b1 = enable_pcie0;
-        npei_int_enb2.s.c0_up_b0 = enable_pcie0;
-        npei_int_enb2.s.c1_hpint = enable_pcie1;
-        npei_int_enb2.s.c1_pmei = enable_pcie1;
-        npei_int_enb2.s.c1_wake = enable_pcie1;
-        npei_int_enb2.s.crs1_dr = enable_pcie1;
-        npei_int_enb2.s.c1_se = enable_pcie1;
-        npei_int_enb2.s.crs1_er = enable_pcie1;
-        npei_int_enb2.s.c1_aeri = enable_pcie1;
-        npei_int_enb2.s.c0_hpint = enable_pcie0;
-        npei_int_enb2.s.c0_pmei = enable_pcie0;
-        npei_int_enb2.s.c0_wake = enable_pcie0;
-        npei_int_enb2.s.crs0_dr = enable_pcie0;
-        npei_int_enb2.s.c0_se = enable_pcie0;
-        npei_int_enb2.s.crs0_er = enable_pcie0;
-        npei_int_enb2.s.c0_aeri = enable_pcie0;
-        npei_int_enb2.s.ptime = 1;
-        npei_int_enb2.s.pcnt = 1;
-        npei_int_enb2.s.pidbof = 1;
-        npei_int_enb2.s.psldbof = 1;
-        npei_int_enb2.s.dtime1 = 1;
-        npei_int_enb2.s.dtime0 = 1;
-        npei_int_enb2.s.dcnt1 = 1;
-        npei_int_enb2.s.dcnt0 = 1;
-        npei_int_enb2.s.dma1fi = 1;
-        npei_int_enb2.s.dma0fi = 1;
-        npei_int_enb2.s.dma4dbo = 1;
-        npei_int_enb2.s.dma3dbo = 1;
-        npei_int_enb2.s.dma2dbo = 1;
-        npei_int_enb2.s.dma1dbo = 1;
-        npei_int_enb2.s.dma0dbo = 1;
-        npei_int_enb2.s.iob2big = 1;
-        npei_int_enb2.s.bar0_to = 1;
-        npei_int_enb2.s.rml_wto = 1;
-        npei_int_enb2.s.rml_rto = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        cvmx_pescx_ctl_status2_t pescx_ctl_status2;
-        cvmx_npei_dbg_data_t npei_dbg_data;
-        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
-        enable_pcie0 = !pescx_ctl_status2.s.pcierst;
-        npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
-        if (!npei_dbg_data.cn52xx.qlm0_link_width)
-        {
-            pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
-            enable_pcie1 = !pescx_ctl_status2.s.pcierst;
-        }
-
-        // Skipping npei_int_enb2.s.reserved_62_63
-        npei_int_enb2.s.int_a = 1;
-        npei_int_enb2.s.c1_ldwn = enable_pcie1;
-        npei_int_enb2.s.c0_ldwn = enable_pcie0;
-        npei_int_enb2.s.c1_exc = enable_pcie1;
-        npei_int_enb2.s.c0_exc = enable_pcie0;
-        npei_int_enb2.s.c1_up_wf = enable_pcie1;
-        npei_int_enb2.s.c0_up_wf = enable_pcie0;
-        npei_int_enb2.s.c1_un_wf = enable_pcie1;
-        npei_int_enb2.s.c0_un_wf = enable_pcie0;
-        npei_int_enb2.s.c1_un_bx = enable_pcie1;
-        npei_int_enb2.s.c1_un_wi = enable_pcie1;
-        npei_int_enb2.s.c1_un_b2 = enable_pcie1;
-        npei_int_enb2.s.c1_un_b1 = enable_pcie1;
-        npei_int_enb2.s.c1_un_b0 = enable_pcie1;
-        npei_int_enb2.s.c1_up_bx = enable_pcie1;
-        npei_int_enb2.s.c1_up_wi = enable_pcie1;
-        npei_int_enb2.s.c1_up_b2 = enable_pcie1;
-        npei_int_enb2.s.c1_up_b1 = enable_pcie1;
-        npei_int_enb2.s.c1_up_b0 = enable_pcie1;
-        npei_int_enb2.s.c0_un_bx = enable_pcie0;
-        npei_int_enb2.s.c0_un_wi = enable_pcie0;
-        npei_int_enb2.s.c0_un_b2 = enable_pcie0;
-        npei_int_enb2.s.c0_un_b1 = enable_pcie0;
-        npei_int_enb2.s.c0_un_b0 = enable_pcie0;
-        npei_int_enb2.s.c0_up_bx = enable_pcie0;
-        npei_int_enb2.s.c0_up_wi = enable_pcie0;
-        npei_int_enb2.s.c0_up_b2 = enable_pcie0;
-        npei_int_enb2.s.c0_up_b1 = enable_pcie0;
-        npei_int_enb2.s.c0_up_b0 = enable_pcie0;
-        npei_int_enb2.s.c1_hpint = enable_pcie1;
-        npei_int_enb2.s.c1_pmei = enable_pcie1;
-        npei_int_enb2.s.c1_wake = enable_pcie1;
-        npei_int_enb2.s.crs1_dr = enable_pcie1;
-        npei_int_enb2.s.c1_se = enable_pcie1;
-        npei_int_enb2.s.crs1_er = enable_pcie1;
-        npei_int_enb2.s.c1_aeri = enable_pcie1;
-        npei_int_enb2.s.c0_hpint = enable_pcie0;
-        npei_int_enb2.s.c0_pmei = enable_pcie0;
-        npei_int_enb2.s.c0_wake = enable_pcie0;
-        npei_int_enb2.s.crs0_dr = enable_pcie0;
-        npei_int_enb2.s.c0_se = enable_pcie0;
-        npei_int_enb2.s.crs0_er = enable_pcie0;
-        npei_int_enb2.s.c0_aeri = enable_pcie0;
-        npei_int_enb2.s.ptime = 1;
-        npei_int_enb2.s.pcnt = 1;
-        npei_int_enb2.s.pidbof = 1;
-        npei_int_enb2.s.psldbof = 1;
-        npei_int_enb2.s.dtime1 = 1;
-        npei_int_enb2.s.dtime0 = 1;
-        npei_int_enb2.s.dcnt1 = 1;
-        npei_int_enb2.s.dcnt0 = 1;
-        npei_int_enb2.s.dma1fi = 1;
-        npei_int_enb2.s.dma0fi = 1;
-        if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
-            npei_int_enb2.s.dma4dbo = 1;
-        npei_int_enb2.s.dma3dbo = 1;
-        npei_int_enb2.s.dma2dbo = 1;
-        npei_int_enb2.s.dma1dbo = 1;
-        npei_int_enb2.s.dma0dbo = 1;
-        npei_int_enb2.s.iob2big = 1;
-        npei_int_enb2.s.bar0_to = 1;
-        npei_int_enb2.s.rml_wto = 1;
-        npei_int_enb2.s.rml_rto = 1;
-    }
-    cvmx_write_csr(CVMX_PEXP_NPEI_INT_ENB2, npei_int_enb2.u64);
-    if (enable_pcie0)
-        __cvmx_interrupt_pescx_dbg_info_en_enable(0);
-    if (enable_pcie1)
-        __cvmx_interrupt_pescx_dbg_info_en_enable(1);
-}
-
-
-/**
- * __cvmx_interrupt_npi_int_enb_enable enables all interrupt bits in cvmx_npi_int_enb_t
- */
-void __cvmx_interrupt_npi_int_enb_enable(void)
-{
-    cvmx_npi_int_enb_t npi_int_enb;
-    cvmx_write_csr(CVMX_NPI_INT_SUM, cvmx_read_csr(CVMX_NPI_INT_SUM));
-    npi_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping npi_int_enb.s.reserved_62_63
-        npi_int_enb.s.q1_a_f = 1;
-        npi_int_enb.s.q1_s_e = 1;
-        npi_int_enb.s.pdf_p_f = 1;
-        npi_int_enb.s.pdf_p_e = 1;
-        npi_int_enb.s.pcf_p_f = 1;
-        npi_int_enb.s.pcf_p_e = 1;
-        npi_int_enb.s.rdx_s_e = 1;
-        npi_int_enb.s.rwx_s_e = 1;
-        npi_int_enb.s.pnc_a_f = 1;
-        npi_int_enb.s.pnc_s_e = 1;
-        npi_int_enb.s.com_a_f = 1;
-        npi_int_enb.s.com_s_e = 1;
-        npi_int_enb.s.q3_a_f = 1;
-        npi_int_enb.s.q3_s_e = 1;
-        npi_int_enb.s.q2_a_f = 1;
-        npi_int_enb.s.q2_s_e = 1;
-        npi_int_enb.s.pcr_a_f = 1;
-        npi_int_enb.s.pcr_s_e = 1;
-        npi_int_enb.s.fcr_a_f = 1;
-        npi_int_enb.s.fcr_s_e = 1;
-        npi_int_enb.s.iobdma = 1;
-        npi_int_enb.s.p_dperr = 1;
-        npi_int_enb.s.win_rto = 1;
-        // Skipping npi_int_enb.s.reserved_36_38
-        npi_int_enb.s.i0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_32_34
-        npi_int_enb.s.p0_ptout = 1;
-        // Skipping npi_int_enb.s.reserved_28_30
-        npi_int_enb.s.p0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_24_26
-        npi_int_enb.s.g0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_20_22
-        npi_int_enb.s.p0_perr = 1;
-        // Skipping npi_int_enb.s.reserved_16_18
-        npi_int_enb.s.p0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_12_14
-        npi_int_enb.s.i0_overf = 1;
-        // Skipping npi_int_enb.s.reserved_8_10
-        npi_int_enb.s.i0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_4_6
-        npi_int_enb.s.po0_2sml = 1;
-        npi_int_enb.s.pci_rsl = 1;
-        npi_int_enb.s.rml_wto = 1;
-        npi_int_enb.s.rml_rto = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping npi_int_enb.s.reserved_62_63
-        npi_int_enb.s.q1_a_f = 1;
-        npi_int_enb.s.q1_s_e = 1;
-        npi_int_enb.s.pdf_p_f = 1;
-        npi_int_enb.s.pdf_p_e = 1;
-        npi_int_enb.s.pcf_p_f = 1;
-        npi_int_enb.s.pcf_p_e = 1;
-        npi_int_enb.s.rdx_s_e = 1;
-        npi_int_enb.s.rwx_s_e = 1;
-        npi_int_enb.s.pnc_a_f = 1;
-        npi_int_enb.s.pnc_s_e = 1;
-        npi_int_enb.s.com_a_f = 1;
-        npi_int_enb.s.com_s_e = 1;
-        npi_int_enb.s.q3_a_f = 1;
-        npi_int_enb.s.q3_s_e = 1;
-        npi_int_enb.s.q2_a_f = 1;
-        npi_int_enb.s.q2_s_e = 1;
-        npi_int_enb.s.pcr_a_f = 1;
-        npi_int_enb.s.pcr_s_e = 1;
-        npi_int_enb.s.fcr_a_f = 1;
-        npi_int_enb.s.fcr_s_e = 1;
-        npi_int_enb.s.iobdma = 1;
-        npi_int_enb.s.p_dperr = 1;
-        npi_int_enb.s.win_rto = 1;
-        // Skipping npi_int_enb.s.reserved_37_38
-        npi_int_enb.s.i1_pperr = 1;
-        npi_int_enb.s.i0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_33_34
-        npi_int_enb.s.p1_ptout = 1;
-        npi_int_enb.s.p0_ptout = 1;
-        // Skipping npi_int_enb.s.reserved_29_30
-        npi_int_enb.s.p1_pperr = 1;
-        npi_int_enb.s.p0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_25_26
-        npi_int_enb.s.g1_rtout = 1;
-        npi_int_enb.s.g0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_21_22
-        npi_int_enb.s.p1_perr = 1;
-        npi_int_enb.s.p0_perr = 1;
-        // Skipping npi_int_enb.s.reserved_17_18
-        npi_int_enb.s.p1_rtout = 1;
-        npi_int_enb.s.p0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_13_14
-        npi_int_enb.s.i1_overf = 1;
-        npi_int_enb.s.i0_overf = 1;
-        // Skipping npi_int_enb.s.reserved_9_10
-        npi_int_enb.s.i1_rtout = 1;
-        npi_int_enb.s.i0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_5_6
-        npi_int_enb.s.po1_2sml = 1;
-        npi_int_enb.s.po0_2sml = 1;
-        npi_int_enb.s.pci_rsl = 1;
-        npi_int_enb.s.rml_wto = 1;
-        npi_int_enb.s.rml_rto = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping npi_int_enb.s.reserved_62_63
-        npi_int_enb.s.q1_a_f = 1;
-        npi_int_enb.s.q1_s_e = 1;
-        npi_int_enb.s.pdf_p_f = 1;
-        npi_int_enb.s.pdf_p_e = 1;
-        npi_int_enb.s.pcf_p_f = 1;
-        npi_int_enb.s.pcf_p_e = 1;
-        npi_int_enb.s.rdx_s_e = 1;
-        npi_int_enb.s.rwx_s_e = 1;
-        npi_int_enb.s.pnc_a_f = 1;
-        npi_int_enb.s.pnc_s_e = 1;
-        npi_int_enb.s.com_a_f = 1;
-        npi_int_enb.s.com_s_e = 1;
-        npi_int_enb.s.q3_a_f = 1;
-        npi_int_enb.s.q3_s_e = 1;
-        npi_int_enb.s.q2_a_f = 1;
-        npi_int_enb.s.q2_s_e = 1;
-        npi_int_enb.s.pcr_a_f = 1;
-        npi_int_enb.s.pcr_s_e = 1;
-        npi_int_enb.s.fcr_a_f = 1;
-        npi_int_enb.s.fcr_s_e = 1;
-        npi_int_enb.s.iobdma = 1;
-        npi_int_enb.s.p_dperr = 1;
-        npi_int_enb.s.win_rto = 1;
-        npi_int_enb.s.i3_pperr = 1;
-        npi_int_enb.s.i2_pperr = 1;
-        npi_int_enb.s.i1_pperr = 1;
-        npi_int_enb.s.i0_pperr = 1;
-        npi_int_enb.s.p3_ptout = 1;
-        npi_int_enb.s.p2_ptout = 1;
-        npi_int_enb.s.p1_ptout = 1;
-        npi_int_enb.s.p0_ptout = 1;
-        npi_int_enb.s.p3_pperr = 1;
-        npi_int_enb.s.p2_pperr = 1;
-        npi_int_enb.s.p1_pperr = 1;
-        npi_int_enb.s.p0_pperr = 1;
-        npi_int_enb.s.g3_rtout = 1;
-        npi_int_enb.s.g2_rtout = 1;
-        npi_int_enb.s.g1_rtout = 1;
-        npi_int_enb.s.g0_rtout = 1;
-        npi_int_enb.s.p3_perr = 1;
-        npi_int_enb.s.p2_perr = 1;
-        npi_int_enb.s.p1_perr = 1;
-        npi_int_enb.s.p0_perr = 1;
-        npi_int_enb.s.p3_rtout = 1;
-        npi_int_enb.s.p2_rtout = 1;
-        npi_int_enb.s.p1_rtout = 1;
-        npi_int_enb.s.p0_rtout = 1;
-        npi_int_enb.s.i3_overf = 1;
-        npi_int_enb.s.i2_overf = 1;
-        npi_int_enb.s.i1_overf = 1;
-        npi_int_enb.s.i0_overf = 1;
-        npi_int_enb.s.i3_rtout = 1;
-        npi_int_enb.s.i2_rtout = 1;
-        npi_int_enb.s.i1_rtout = 1;
-        npi_int_enb.s.i0_rtout = 1;
-        npi_int_enb.s.po3_2sml = 1;
-        npi_int_enb.s.po2_2sml = 1;
-        npi_int_enb.s.po1_2sml = 1;
-        npi_int_enb.s.po0_2sml = 1;
-        npi_int_enb.s.pci_rsl = 1;
-        npi_int_enb.s.rml_wto = 1;
-        npi_int_enb.s.rml_rto = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping npi_int_enb.s.reserved_62_63
-        npi_int_enb.s.q1_a_f = 1;
-        npi_int_enb.s.q1_s_e = 1;
-        npi_int_enb.s.pdf_p_f = 1;
-        npi_int_enb.s.pdf_p_e = 1;
-        npi_int_enb.s.pcf_p_f = 1;
-        npi_int_enb.s.pcf_p_e = 1;
-        npi_int_enb.s.rdx_s_e = 1;
-        npi_int_enb.s.rwx_s_e = 1;
-        npi_int_enb.s.pnc_a_f = 1;
-        npi_int_enb.s.pnc_s_e = 1;
-        npi_int_enb.s.com_a_f = 1;
-        npi_int_enb.s.com_s_e = 1;
-        npi_int_enb.s.q3_a_f = 1;
-        npi_int_enb.s.q3_s_e = 1;
-        npi_int_enb.s.q2_a_f = 1;
-        npi_int_enb.s.q2_s_e = 1;
-        npi_int_enb.s.pcr_a_f = 1;
-        npi_int_enb.s.pcr_s_e = 1;
-        npi_int_enb.s.fcr_a_f = 1;
-        npi_int_enb.s.fcr_s_e = 1;
-        npi_int_enb.s.iobdma = 1;
-        npi_int_enb.s.p_dperr = 1;
-        npi_int_enb.s.win_rto = 1;
-        // Skipping npi_int_enb.s.reserved_37_38
-        npi_int_enb.s.i1_pperr = 1;
-        npi_int_enb.s.i0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_33_34
-        npi_int_enb.s.p1_ptout = 1;
-        npi_int_enb.s.p0_ptout = 1;
-        // Skipping npi_int_enb.s.reserved_29_30
-        npi_int_enb.s.p1_pperr = 1;
-        npi_int_enb.s.p0_pperr = 1;
-        // Skipping npi_int_enb.s.reserved_25_26
-        npi_int_enb.s.g1_rtout = 1;
-        npi_int_enb.s.g0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_21_22
-        npi_int_enb.s.p1_perr = 1;
-        npi_int_enb.s.p0_perr = 1;
-        // Skipping npi_int_enb.s.reserved_17_18
-        npi_int_enb.s.p1_rtout = 1;
-        npi_int_enb.s.p0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_13_14
-        npi_int_enb.s.i1_overf = 1;
-        npi_int_enb.s.i0_overf = 1;
-        // Skipping npi_int_enb.s.reserved_9_10
-        npi_int_enb.s.i1_rtout = 1;
-        npi_int_enb.s.i0_rtout = 1;
-        // Skipping npi_int_enb.s.reserved_5_6
-        npi_int_enb.s.po1_2sml = 1;
-        npi_int_enb.s.po0_2sml = 1;
-        npi_int_enb.s.pci_rsl = 1;
-        npi_int_enb.s.rml_wto = 1;
-        npi_int_enb.s.rml_rto = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping npi_int_enb.s.reserved_62_63
-        npi_int_enb.s.q1_a_f = 1;
-        npi_int_enb.s.q1_s_e = 1;
-        npi_int_enb.s.pdf_p_f = 1;
-        npi_int_enb.s.pdf_p_e = 1;
-        npi_int_enb.s.pcf_p_f = 1;
-        npi_int_enb.s.pcf_p_e = 1;
-        npi_int_enb.s.rdx_s_e = 1;
-        npi_int_enb.s.rwx_s_e = 1;
-        npi_int_enb.s.pnc_a_f = 1;
-        npi_int_enb.s.pnc_s_e = 1;
-        npi_int_enb.s.com_a_f = 1;
-        npi_int_enb.s.com_s_e = 1;
-        npi_int_enb.s.q3_a_f = 1;
-        npi_int_enb.s.q3_s_e = 1;
-        npi_int_enb.s.q2_a_f = 1;
-        npi_int_enb.s.q2_s_e = 1;
-        npi_int_enb.s.pcr_a_f = 1;
-        npi_int_enb.s.pcr_s_e = 1;
-        npi_int_enb.s.fcr_a_f = 1;
-        npi_int_enb.s.fcr_s_e = 1;
-        npi_int_enb.s.iobdma = 1;
-        npi_int_enb.s.p_dperr = 1;
-        npi_int_enb.s.win_rto = 1;
-        npi_int_enb.s.i3_pperr = 1;
-        npi_int_enb.s.i2_pperr = 1;
-        npi_int_enb.s.i1_pperr = 1;
-        npi_int_enb.s.i0_pperr = 1;
-        npi_int_enb.s.p3_ptout = 1;
-        npi_int_enb.s.p2_ptout = 1;
-        npi_int_enb.s.p1_ptout = 1;
-        npi_int_enb.s.p0_ptout = 1;
-        npi_int_enb.s.p3_pperr = 1;
-        npi_int_enb.s.p2_pperr = 1;
-        npi_int_enb.s.p1_pperr = 1;
-        npi_int_enb.s.p0_pperr = 1;
-        npi_int_enb.s.g3_rtout = 1;
-        npi_int_enb.s.g2_rtout = 1;
-        npi_int_enb.s.g1_rtout = 1;
-        npi_int_enb.s.g0_rtout = 1;
-        npi_int_enb.s.p3_perr = 1;
-        npi_int_enb.s.p2_perr = 1;
-        npi_int_enb.s.p1_perr = 1;
-        npi_int_enb.s.p0_perr = 1;
-        npi_int_enb.s.p3_rtout = 1;
-        npi_int_enb.s.p2_rtout = 1;
-        npi_int_enb.s.p1_rtout = 1;
-        npi_int_enb.s.p0_rtout = 1;
-        npi_int_enb.s.i3_overf = 1;
-        npi_int_enb.s.i2_overf = 1;
-        npi_int_enb.s.i1_overf = 1;
-        npi_int_enb.s.i0_overf = 1;
-        npi_int_enb.s.i3_rtout = 1;
-        npi_int_enb.s.i2_rtout = 1;
-        npi_int_enb.s.i1_rtout = 1;
-        npi_int_enb.s.i0_rtout = 1;
-        npi_int_enb.s.po3_2sml = 1;
-        npi_int_enb.s.po2_2sml = 1;
-        npi_int_enb.s.po1_2sml = 1;
-        npi_int_enb.s.po0_2sml = 1;
-        npi_int_enb.s.pci_rsl = 1;
-        npi_int_enb.s.rml_wto = 1;
-        npi_int_enb.s.rml_rto = 1;
-    }
-    cvmx_write_csr(CVMX_NPI_INT_ENB, npi_int_enb.u64);
-    __cvmx_interrupt_pci_int_enb2_enable();
-}
-
-
-/**
- * __cvmx_interrupt_npi_int_sum_decode decodes all interrupt bits in cvmx_npi_int_sum_t
- */
-void __cvmx_interrupt_npi_int_sum_decode(void)
-{
-    cvmx_npi_int_sum_t npi_int_sum;
-    npi_int_sum.u64 = cvmx_read_csr(CVMX_NPI_INT_SUM);
-    npi_int_sum.u64 &= cvmx_read_csr(CVMX_NPI_INT_ENB);
-    cvmx_write_csr(CVMX_NPI_INT_SUM, npi_int_sum.u64);
-    // Skipping npi_int_sum.s.reserved_62_63
-    if (npi_int_sum.s.q1_a_f)
-        PRINT_ERROR("NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.q1_s_e)
-        PRINT_ERROR("NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pdf_p_f)
-        PRINT_ERROR("NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pdf_p_e)
-        PRINT_ERROR("NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pcf_p_f)
-        PRINT_ERROR("NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pcf_p_e)
-        PRINT_ERROR("NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.rdx_s_e)
-        PRINT_ERROR("NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.rwx_s_e)
-        PRINT_ERROR("NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pnc_a_f)
-        PRINT_ERROR("NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pnc_s_e)
-        PRINT_ERROR("NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.com_a_f)
-        PRINT_ERROR("NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.com_s_e)
-        PRINT_ERROR("NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.q3_a_f)
-        PRINT_ERROR("NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.q3_s_e)
-        PRINT_ERROR("NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.q2_a_f)
-        PRINT_ERROR("NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.q2_s_e)
-        PRINT_ERROR("NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pcr_a_f)
-        PRINT_ERROR("NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.pcr_s_e)
-        PRINT_ERROR("NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.fcr_a_f)
-        PRINT_ERROR("NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.fcr_s_e)
-        PRINT_ERROR("NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
-                    "    PASS3 Field.\n");
-    if (npi_int_sum.s.iobdma)
-        PRINT_ERROR("NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n");
-    if (npi_int_sum.s.p_dperr)
-        PRINT_ERROR("NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
-                    "    from the PCI this bit may be set.\n");
-    if (npi_int_sum.s.win_rto)
-        PRINT_ERROR("NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n");
-    if (npi_int_sum.s.i3_pperr)
-        PRINT_ERROR("NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
-                    "    this bit may be set.\n");
-    if (npi_int_sum.s.i2_pperr)
-        PRINT_ERROR("NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
-                    "    this bit may be set.\n");
-    if (npi_int_sum.s.i1_pperr)
-        PRINT_ERROR("NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
-                    "    this bit may be set.\n");
-    if (npi_int_sum.s.i0_pperr)
-        PRINT_ERROR("NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
-                    "    this bit may be set.\n");
-    if (npi_int_sum.s.p3_ptout)
-        PRINT_ERROR("NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
-                    "    pair.\n");
-    if (npi_int_sum.s.p2_ptout)
-        PRINT_ERROR("NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
-                    "    pair.\n");
-    if (npi_int_sum.s.p1_ptout)
-        PRINT_ERROR("NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
-                    "    pair.\n");
-    if (npi_int_sum.s.p0_ptout)
-        PRINT_ERROR("NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
-                    "    pair.\n");
-    if (npi_int_sum.s.p3_pperr)
-        PRINT_ERROR("NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
-                    "    pointer-pair, this bit may be set.\n");
-    if (npi_int_sum.s.p2_pperr)
-        PRINT_ERROR("NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
-                    "    pointer-pair, this bit may be set.\n");
-    if (npi_int_sum.s.p1_pperr)
-        PRINT_ERROR("NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
-                    "    pointer-pair, this bit may be set.\n");
-    if (npi_int_sum.s.p0_pperr)
-        PRINT_ERROR("NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
-                    "    pointer-pair, this bit may be set.\n");
-    if (npi_int_sum.s.g3_rtout)
-        PRINT_ERROR("NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
-                    "    read a gather list.\n");
-    if (npi_int_sum.s.g2_rtout)
-        PRINT_ERROR("NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
-                    "    read a gather list.\n");
-    if (npi_int_sum.s.g1_rtout)
-        PRINT_ERROR("NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
-                    "    read a gather list.\n");
-    if (npi_int_sum.s.g0_rtout)
-        PRINT_ERROR("NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
-                    "    read a gather list.\n");
-    if (npi_int_sum.s.p3_perr)
-        PRINT_ERROR("NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
-                    "    data this bit may be set.\n");
-    if (npi_int_sum.s.p2_perr)
-        PRINT_ERROR("NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
-                    "    data this bit may be set.\n");
-    if (npi_int_sum.s.p1_perr)
-        PRINT_ERROR("NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
-                    "    data this bit may be set.\n");
-    if (npi_int_sum.s.p0_perr)
-        PRINT_ERROR("NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
-                    "    data this bit may be set.\n");
-    if (npi_int_sum.s.p3_rtout)
-        PRINT_ERROR("NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
-                    "    read packet data.\n");
-    if (npi_int_sum.s.p2_rtout)
-        PRINT_ERROR("NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
-                    "    read packet data.\n");
-    if (npi_int_sum.s.p1_rtout)
-        PRINT_ERROR("NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
-                    "    read packet data.\n");
-    if (npi_int_sum.s.p0_rtout)
-        PRINT_ERROR("NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
-                    "    read packet data.\n");
-    if (npi_int_sum.s.i3_overf)
-        PRINT_ERROR("NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
-                    "    doorbell count was set.\n");
-    if (npi_int_sum.s.i2_overf)
-        PRINT_ERROR("NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
-                    "    doorbell count was set.\n");
-    if (npi_int_sum.s.i1_overf)
-        PRINT_ERROR("NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
-                    "    doorbell count was set.\n");
-    if (npi_int_sum.s.i0_overf)
-        PRINT_ERROR("NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
-                    "    doorbell count was set.\n");
-    if (npi_int_sum.s.i3_rtout)
-        PRINT_ERROR("NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
-                    "    read instructions.\n");
-    if (npi_int_sum.s.i2_rtout)
-        PRINT_ERROR("NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
-                    "    read instructions.\n");
-    if (npi_int_sum.s.i1_rtout)
-        PRINT_ERROR("NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
-                    "    read instructions.\n");
-    if (npi_int_sum.s.i0_rtout)
-        PRINT_ERROR("NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
-                    "    read instructions.\n");
-    if (npi_int_sum.s.po3_2sml)
-        PRINT_ERROR("NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
-                    "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n");
-    if (npi_int_sum.s.po2_2sml)
-        PRINT_ERROR("NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
-                    "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n");
-    if (npi_int_sum.s.po1_2sml)
-        PRINT_ERROR("NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
-                    "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n");
-    if (npi_int_sum.s.po0_2sml)
-        PRINT_ERROR("NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
-                    "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n");
-    if (npi_int_sum.s.pci_rsl)
-    {
-#if 0
-        PRINT_ERROR("NPI_INT_SUM[PCI_RSL]: This '1' when a bit in PCI_INT_SUM2 is SET and the\n"
-                    "    corresponding bit in the PCI_INT_ENB2 is SET.\n");
-#endif
-        __cvmx_interrupt_pci_int_sum2_decode();
-    }
-    if (npi_int_sum.s.rml_wto)
-        PRINT_ERROR("NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
-                    "    back from a RSL after sending a write command to\n"
-                    "    a RSL.\n");
-    if (npi_int_sum.s.rml_rto)
-        PRINT_ERROR("NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
-                    "    back from a RSL after sending a read command to\n"
-                    "    a RSL.\n");
-}
-
-
-/**
- * __cvmx_interrupt_pci_int_enb2_enable enables all interrupt bits in cvmx_pci_int_enb2_t
- */
-void __cvmx_interrupt_pci_int_enb2_enable(void)
-{
-    cvmx_pci_int_enb2_t pci_int_enb2;
-    cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2));
-    pci_int_enb2.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping pci_int_enb2.s.reserved_34_63
-        pci_int_enb2.s.ill_rd = 1;
-        pci_int_enb2.s.ill_wr = 1;
-        pci_int_enb2.s.win_wr = 1;
-        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
-        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_22_24
-        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_18_20
-        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
-        pci_int_enb2.s.ill_rrd = 1;
-        pci_int_enb2.s.ill_rwr = 1;
-        pci_int_enb2.s.rdperr = 1;
-        pci_int_enb2.s.raperr = 1;
-        pci_int_enb2.s.rserr = 1;
-        pci_int_enb2.s.rtsr_abt = 1;
-        pci_int_enb2.s.rmsc_msg = 1;
-        pci_int_enb2.s.rmsi_mabt = 1;
-        pci_int_enb2.s.rmsi_tabt = 1;
-        pci_int_enb2.s.rmsi_per = 1;
-        pci_int_enb2.s.rmr_tto = 1;
-        pci_int_enb2.s.rmr_abt = 1;
-        pci_int_enb2.s.rtr_abt = 1;
-        pci_int_enb2.s.rmr_wtto = 1;
-        pci_int_enb2.s.rmr_wabt = 1;
-        pci_int_enb2.s.rtr_wabt = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping pci_int_enb2.s.reserved_34_63
-        pci_int_enb2.s.ill_rd = 1;
-        pci_int_enb2.s.ill_wr = 1;
-        pci_int_enb2.s.win_wr = 1;
-        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
-        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_23_24
-        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_19_20
-        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
-        pci_int_enb2.s.ill_rrd = 1;
-        pci_int_enb2.s.ill_rwr = 1;
-        pci_int_enb2.s.rdperr = 1;
-        pci_int_enb2.s.raperr = 1;
-        pci_int_enb2.s.rserr = 1;
-        pci_int_enb2.s.rtsr_abt = 1;
-        pci_int_enb2.s.rmsc_msg = 1;
-        pci_int_enb2.s.rmsi_mabt = 1;
-        pci_int_enb2.s.rmsi_tabt = 1;
-        pci_int_enb2.s.rmsi_per = 1;
-        pci_int_enb2.s.rmr_tto = 1;
-        pci_int_enb2.s.rmr_abt = 1;
-        pci_int_enb2.s.rtr_abt = 1;
-        pci_int_enb2.s.rmr_wtto = 1;
-        pci_int_enb2.s.rmr_wabt = 1;
-        pci_int_enb2.s.rtr_wabt = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping pci_int_enb2.s.reserved_34_63
-        pci_int_enb2.s.ill_rd = 1;
-        pci_int_enb2.s.ill_wr = 1;
-        pci_int_enb2.s.win_wr = 1;
-        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
-        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime3 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime2 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
-        pci_int_enb2.s.ill_rrd = 1;
-        pci_int_enb2.s.ill_rwr = 1;
-        pci_int_enb2.s.rdperr = 1;
-        pci_int_enb2.s.raperr = 1;
-        pci_int_enb2.s.rserr = 1;
-        pci_int_enb2.s.rtsr_abt = 1;
-        pci_int_enb2.s.rmsc_msg = 1;
-        pci_int_enb2.s.rmsi_mabt = 1;
-        pci_int_enb2.s.rmsi_tabt = 1;
-        pci_int_enb2.s.rmsi_per = 1;
-        pci_int_enb2.s.rmr_tto = 1;
-        pci_int_enb2.s.rmr_abt = 1;
-        pci_int_enb2.s.rtr_abt = 1;
-        pci_int_enb2.s.rmr_wtto = 1;
-        pci_int_enb2.s.rmr_wabt = 1;
-        pci_int_enb2.s.rtr_wabt = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping pci_int_enb2.s.reserved_34_63
-        pci_int_enb2.s.ill_rd = 1;
-        pci_int_enb2.s.ill_wr = 1;
-        pci_int_enb2.s.win_wr = 1;
-        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
-        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_23_24
-        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
-        // Skipping pci_int_enb2.s.reserved_19_20
-        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
-        pci_int_enb2.s.ill_rrd = 1;
-        pci_int_enb2.s.ill_rwr = 1;
-        pci_int_enb2.s.rdperr = 1;
-        pci_int_enb2.s.raperr = 1;
-        pci_int_enb2.s.rserr = 1;
-        pci_int_enb2.s.rtsr_abt = 1;
-        pci_int_enb2.s.rmsc_msg = 1;
-        pci_int_enb2.s.rmsi_mabt = 1;
-        pci_int_enb2.s.rmsi_tabt = 1;
-        pci_int_enb2.s.rmsi_per = 1;
-        pci_int_enb2.s.rmr_tto = 1;
-        pci_int_enb2.s.rmr_abt = 1;
-        pci_int_enb2.s.rtr_abt = 1;
-        pci_int_enb2.s.rmr_wtto = 1;
-        pci_int_enb2.s.rmr_wabt = 1;
-        pci_int_enb2.s.rtr_wabt = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping pci_int_enb2.s.reserved_34_63
-        pci_int_enb2.s.ill_rd = 1;
-        pci_int_enb2.s.ill_wr = 1;
-        pci_int_enb2.s.win_wr = 1;
-        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
-        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime3 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime2 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
-        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
-        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
-        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
-        pci_int_enb2.s.ill_rrd = 1;
-        pci_int_enb2.s.ill_rwr = 1;
-        pci_int_enb2.s.rdperr = 1;
-        pci_int_enb2.s.raperr = 1;
-        pci_int_enb2.s.rserr = 1;
-        pci_int_enb2.s.rtsr_abt = 1;
-        pci_int_enb2.s.rmsc_msg = 1;
-        pci_int_enb2.s.rmsi_mabt = 1;
-        pci_int_enb2.s.rmsi_tabt = 1;
-        pci_int_enb2.s.rmsi_per = 1;
-        pci_int_enb2.s.rmr_tto = 1;
-        pci_int_enb2.s.rmr_abt = 1;
-        pci_int_enb2.s.rtr_abt = 1;
-        pci_int_enb2.s.rmr_wtto = 1;
-        pci_int_enb2.s.rmr_wabt = 1;
-        pci_int_enb2.s.rtr_wabt = 1;
-    }
-    cvmx_write_csr(CVMX_NPI_PCI_INT_ENB2, pci_int_enb2.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pci_int_sum2_decode decodes all interrupt bits in cvmx_pci_int_sum2_t
- */
-void __cvmx_interrupt_pci_int_sum2_decode(void)
-{
-    cvmx_pci_int_sum2_t pci_int_sum2;
-    pci_int_sum2.u64 = cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2);
-    pci_int_sum2.u64 &= cvmx_read_csr(CVMX_NPI_PCI_INT_ENB2);
-    cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, pci_int_sum2.u64);
-    // Skipping pci_int_sum2.s.reserved_34_63
-    if (pci_int_sum2.s.ill_rd)
-        PRINT_ERROR("PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
-                    "    when the mem area is disabled.\n");
-    if (pci_int_sum2.s.ill_wr)
-        PRINT_ERROR("PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
-                    "    when the mem area is disabled.\n");
-    if (pci_int_sum2.s.win_wr)
-        PRINT_ERROR("PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
-                    "    Read-Address Register took place.\n");
-    if (pci_int_sum2.s.dma1_fi)
-        PRINT_ERROR("PCI_INT_SUM2[DMA1_FI]: A DMA operation operation finished that was\n"
-                    "    required to set the FORCE-INT bit for counter 1.\n");
-    if (pci_int_sum2.s.dma0_fi)
-        PRINT_ERROR("PCI_INT_SUM2[DMA0_FI]: A DMA operation operation finished that was\n"
-                    "    required to set the FORCE-INT bit for counter 0.\n");
-    if (pci_int_sum2.s.dtime1)
-        PRINT_ERROR("PCI_INT_SUM2[DTIME1]: When the value in the PCI_DMA_CNT1\n"
-                    "    register is not 0 the DMA_CNT1 timer counts.\n"
-                    "    When the DMA1_CNT timer has a value greater\n"
-                    "    than the PCI_DMA_TIME1 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.dtime0)
-        PRINT_ERROR("PCI_INT_SUM2[DTIME0]: When the value in the PCI_DMA_CNT0\n"
-                    "    register is not 0 the DMA_CNT0 timer counts.\n"
-                    "    When the DMA0_CNT timer has a value greater\n"
-                    "    than the PCI_DMA_TIME0 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.dcnt1)
-        PRINT_ERROR("PCI_INT_SUM2[DCNT1]: This bit indicates that PCI_DMA_CNT1\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_DMA_INT_LEV1 register.\n");
-    if (pci_int_sum2.s.dcnt0)
-        PRINT_ERROR("PCI_INT_SUM2[DCNT0]: This bit indicates that PCI_DMA_CNT0\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_DMA_INT_LEV0 register.\n");
-    if (pci_int_sum2.s.ptime3)
-        PRINT_ERROR("PCI_INT_SUM2[PTIME3]: When the value in the PCI_PKTS_SENT3\n"
-                    "    register is not 0 the Sent-3 timer counts.\n"
-                    "    When the Sent-3 timer has a value greater\n"
-                    "    than the PCI_PKTS_SENT_TIME3 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.ptime2)
-        PRINT_ERROR("PCI_INT_SUM2[PTIME2]: When the value in the PCI_PKTS_SENT2\n"
-                    "    register is not 0 the Sent-2 timer counts.\n"
-                    "    When the Sent-2 timer has a value greater\n"
-                    "    than the PCI_PKTS_SENT_TIME2 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.ptime1)
-        PRINT_ERROR("PCI_INT_SUM2[PTIME1]: When the value in the PCI_PKTS_SENT1\n"
-                    "    register is not 0 the Sent-1 timer counts.\n"
-                    "    When the Sent-1 timer has a value greater\n"
-                    "    than the PCI_PKTS_SENT_TIME1 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.ptime0)
-        PRINT_ERROR("PCI_INT_SUM2[PTIME0]: When the value in the PCI_PKTS_SENT0\n"
-                    "    register is not 0 the Sent-0 timer counts.\n"
-                    "    When the Sent-0 timer has a value greater\n"
-                    "    than the PCI_PKTS_SENT_TIME0 register this\n"
-                    "    bit is set. The timer is reset when bit is\n"
-                    "    written with a one.\n");
-    if (pci_int_sum2.s.pcnt3)
-        PRINT_ERROR("PCI_INT_SUM2[PCNT3]: This bit indicates that PCI_PKTS_SENT3\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_PKTS_SENT_INT_LEV3 register.\n");
-    if (pci_int_sum2.s.pcnt2)
-        PRINT_ERROR("PCI_INT_SUM2[PCNT2]: This bit indicates that PCI_PKTS_SENT2\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_PKTS_SENT_INT_LEV2 register.\n");
-    if (pci_int_sum2.s.pcnt1)
-        PRINT_ERROR("PCI_INT_SUM2[PCNT1]: This bit indicates that PCI_PKTS_SENT1\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_PKTS_SENT_INT_LEV1 register.\n");
-    if (pci_int_sum2.s.pcnt0)
-        PRINT_ERROR("PCI_INT_SUM2[PCNT0]: This bit indicates that PCI_PKTS_SENT0\n"
-                    "    value is greater than the value\n"
-                    "    in the PCI_PKTS_SENT_INT_LEV0 register.\n");
-    if (pci_int_sum2.s.rsl_int)
-        PRINT_ERROR("PCI_INT_SUM2[RSL_INT]: This bit is set when the RSL Chain has\n"
-                    "    generated an interrupt.\n");
-    if (pci_int_sum2.s.ill_rrd)
-        PRINT_ERROR("PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n");
-    if (pci_int_sum2.s.ill_rwr)
-        PRINT_ERROR("PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n");
-    if (pci_int_sum2.s.dperr)
-        PRINT_ERROR("PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n");
-    if (pci_int_sum2.s.aperr)
-        PRINT_ERROR("PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n");
-    if (pci_int_sum2.s.serr)
-        PRINT_ERROR("PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n");
-    if (pci_int_sum2.s.tsr_abt)
-        PRINT_ERROR("PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n");
-    if (pci_int_sum2.s.msc_msg)
-        PRINT_ERROR("PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n");
-    if (pci_int_sum2.s.msi_mabt)
-        PRINT_ERROR("PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n");
-    if (pci_int_sum2.s.msi_tabt)
-        PRINT_ERROR("PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n");
-    if (pci_int_sum2.s.msi_per)
-        PRINT_ERROR("PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n");
-    if (pci_int_sum2.s.mr_tto)
-        PRINT_ERROR("PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n");
-    if (pci_int_sum2.s.mr_abt)
-        PRINT_ERROR("PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n");
-    if (pci_int_sum2.s.tr_abt)
-        PRINT_ERROR("PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n");
-    if (pci_int_sum2.s.mr_wtto)
-        PRINT_ERROR("PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n");
-    if (pci_int_sum2.s.mr_wabt)
-        PRINT_ERROR("PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n");
-    if (pci_int_sum2.s.tr_wabt)
-        PRINT_ERROR("PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n");
-}
-
-
-/**
- * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
- */
-void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
-{
-    cvmx_pcsx_intx_en_reg_t pcs_int_en_reg;
-    cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
-    pcs_int_en_reg.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping pcs_int_en_reg.s.reserved_12_63
-        //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
-        pcs_int_en_reg.s.sync_bad_en = 1;
-        pcs_int_en_reg.s.an_bad_en = 1;
-        pcs_int_en_reg.s.rxlock_en = 1;
-        pcs_int_en_reg.s.rxbad_en = 1;
-        //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
-        pcs_int_en_reg.s.txbad_en = 1;
-        pcs_int_en_reg.s.txfifo_en = 1;
-        pcs_int_en_reg.s.txfifu_en = 1;
-        pcs_int_en_reg.s.an_err_en = 1;
-        //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
-        //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping pcs_int_en_reg.s.reserved_12_63
-        //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
-        pcs_int_en_reg.s.sync_bad_en = 1;
-        pcs_int_en_reg.s.an_bad_en = 1;
-        pcs_int_en_reg.s.rxlock_en = 1;
-        pcs_int_en_reg.s.rxbad_en = 1;
-        //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
-        pcs_int_en_reg.s.txbad_en = 1;
-        pcs_int_en_reg.s.txfifo_en = 1;
-        pcs_int_en_reg.s.txfifu_en = 1;
-        pcs_int_en_reg.s.an_err_en = 1;
-        //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
-        //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
-    }
-    cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pcsx_intx_reg_decode decodes all interrupt bits in cvmx_pcsx_intx_reg_t
- */
-void __cvmx_interrupt_pcsx_intx_reg_decode(int index, int block)
-{
-    cvmx_pcsx_intx_reg_t pcs_int_reg;
-    pcs_int_reg.u64 = cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block));
-    pcs_int_reg.u64 &= cvmx_read_csr(CVMX_PCSX_INTX_EN_REG(index, block));
-    cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), pcs_int_reg.u64);
-    // Skipping pcs_int_reg.s.reserved_12_63
-    if (pcs_int_reg.s.dup)
-        PRINT_ERROR("PCS%d_INT%d_REG[DUP]: Set whenever Duplex mode changes on the link\n", block, index);
-    if (pcs_int_reg.s.sync_bad)
-        PRINT_ERROR("PCS%d_INT%d_REG[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
-                    "    state. Should never be set during normal operation\n", block, index);
-    if (pcs_int_reg.s.an_bad)
-        PRINT_ERROR("PCS%d_INT%d_REG[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
-                    "    state. Should never be set during normal operation\n", block, index);
-    if (pcs_int_reg.s.rxlock)
-        PRINT_ERROR("PCS%d_INT%d_REG[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
-                    "    failure occurs\n"
-                    "    Cannot fire in loopback1 mode\n", block, index);
-    if (pcs_int_reg.s.rxbad)
-        PRINT_ERROR("PCS%d_INT%d_REG[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
-                    "    state. Should never be set during normal operation\n", block, index);
-    if (pcs_int_reg.s.rxerr)
-        PRINT_ERROR("PCS%d_INT%d_REG[RXERR]: Set whenever RX receives a code group error in\n"
-                    "    10 bit to 8 bit decode logic\n"
-                    "    Cannot fire in loopback1 mode\n", block, index);
-    if (pcs_int_reg.s.txbad)
-        PRINT_ERROR("PCS%d_INT%d_REG[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
-                    "    state. Should never be set during normal operation\n", block, index);
-    if (pcs_int_reg.s.txfifo)
-        PRINT_ERROR("PCS%d_INT%d_REG[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
-                    "    condition\n", block, index);
-    if (pcs_int_reg.s.txfifu)
-        PRINT_ERROR("PCS%d_INT%d_REG[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
-                    "    condition\n", block, index);
-    if (pcs_int_reg.s.an_err)
-        PRINT_ERROR("PCS%d_INT%d_REG[AN_ERR]: AN Error, AN resolution function failed\n", block, index);
-    if (pcs_int_reg.s.xmit)
-        PRINT_ERROR("PCS%d_INT%d_REG[XMIT]: Set whenever HW detects a change in the XMIT\n"
-                    "    variable. XMIT variable states are IDLE, CONFIG and\n"
-                    "    DATA\n", block, index);
-    if (pcs_int_reg.s.lnkspd)
-        PRINT_ERROR("PCS%d_INT%d_REG[LNKSPD]: Set by HW whenever Link Speed has changed\n", block, index);
-}
-
-
-/**
- * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
- */
-void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
-{
-    cvmx_pcsxx_int_en_reg_t pcsx_int_en_reg;
-    cvmx_write_csr(CVMX_PCSXX_INT_REG(index), cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
-    pcsx_int_en_reg.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping pcsx_int_en_reg.s.reserved_6_63
-        pcsx_int_en_reg.s.algnlos_en = 1;
-        pcsx_int_en_reg.s.synlos_en = 1;
-        pcsx_int_en_reg.s.bitlckls_en = 1;
-        pcsx_int_en_reg.s.rxsynbad_en = 1;
-        pcsx_int_en_reg.s.rxbad_en = 1;
-        pcsx_int_en_reg.s.txflt_en = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping pcsx_int_en_reg.s.reserved_6_63
-        pcsx_int_en_reg.s.algnlos_en = 1;
-        pcsx_int_en_reg.s.synlos_en = 1;
-        pcsx_int_en_reg.s.bitlckls_en = 0;  // Happens if XAUI module is not installed
-        pcsx_int_en_reg.s.rxsynbad_en = 1;
-        pcsx_int_en_reg.s.rxbad_en = 1;
-        pcsx_int_en_reg.s.txflt_en = 1;
-    }
-    cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pcsxx_int_reg_decode decodes all interrupt bits in cvmx_pcsxx_int_reg_t
- */
-void __cvmx_interrupt_pcsxx_int_reg_decode(int index)
-{
-    cvmx_pcsxx_int_reg_t pcsx_int_reg;
-    pcsx_int_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_REG(index));
-    pcsx_int_reg.u64 &= cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(index));
-    cvmx_write_csr(CVMX_PCSXX_INT_REG(index), pcsx_int_reg.u64);
-    // Skipping pcsx_int_reg.s.reserved_6_63
-    if (pcsx_int_reg.s.algnlos)
-        PRINT_ERROR("PCSX%d_INT_REG[ALGNLOS]: Set when XAUI lanes lose alignment\n", index);
-    if (pcsx_int_reg.s.synlos)
-        PRINT_ERROR("PCSX%d_INT_REG[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n", index);
-    if (pcsx_int_reg.s.bitlckls)
-        PRINT_ERROR("PCSX%d_INT_REG[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n", index);
-    if (pcsx_int_reg.s.rxsynbad)
-        PRINT_ERROR("PCSX%d_INT_REG[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
-                    "    in one of the 4 xaui lanes\n", index);
-    if (pcsx_int_reg.s.rxbad)
-        PRINT_ERROR("PCSX%d_INT_REG[RXBAD]: Set when RX state machine in bad state\n", index);
-    if (pcsx_int_reg.s.txflt)
-        PRINT_ERROR("PCSX%d_INT_REG[TXFLT]: None defined at this time, always 0x0\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_pescx_dbg_info_en_enable enables all interrupt bits in cvmx_pescx_dbg_info_en_t
- */
-void __cvmx_interrupt_pescx_dbg_info_en_enable(int index)
-{
-    cvmx_pescx_dbg_info_en_t pesc_dbg_info_en;
-    cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), cvmx_read_csr(CVMX_PESCX_DBG_INFO(index)));
-    pesc_dbg_info_en.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping pesc_dbg_info_en.s.reserved_31_63
-        pesc_dbg_info_en.s.ecrc_e = 1;
-        pesc_dbg_info_en.s.rawwpp = 1;
-        pesc_dbg_info_en.s.racpp = 1;
-        pesc_dbg_info_en.s.ramtlp = 1;
-        pesc_dbg_info_en.s.rarwdns = 1;
-        pesc_dbg_info_en.s.caar = 1;
-        pesc_dbg_info_en.s.racca = 1;
-        pesc_dbg_info_en.s.racur = 1;
-        pesc_dbg_info_en.s.rauc = 1;
-        pesc_dbg_info_en.s.rqo = 1;
-        pesc_dbg_info_en.s.fcuv = 1;
-        pesc_dbg_info_en.s.rpe = 1;
-        pesc_dbg_info_en.s.fcpvwt = 1;
-        pesc_dbg_info_en.s.dpeoosd = 1;
-        pesc_dbg_info_en.s.rtwdle = 1;
-        pesc_dbg_info_en.s.rdwdle = 1;
-        pesc_dbg_info_en.s.mre = 1;
-        pesc_dbg_info_en.s.rte = 1;
-        pesc_dbg_info_en.s.acto = 1;
-        pesc_dbg_info_en.s.rvdm = 1;
-        pesc_dbg_info_en.s.rumep = 1;
-        pesc_dbg_info_en.s.rptamrc = 1;
-        pesc_dbg_info_en.s.rpmerc = 1;
-        pesc_dbg_info_en.s.rfemrc = 1;
-        pesc_dbg_info_en.s.rnfemrc = 1;
-        pesc_dbg_info_en.s.rcemrc = 1;
-        pesc_dbg_info_en.s.rpoison = 1;
-        pesc_dbg_info_en.s.recrce = 1;
-        pesc_dbg_info_en.s.rtlplle = 1;
-#if 0
-    /* RTLPMAL is disabled since it will be generated under normal conditions,
-        like devices causing legacy PCI interrupts */
-        pesc_dbg_info_en.s.rtlpmal = 1;
-#endif
-        pesc_dbg_info_en.s.spoison = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping pesc_dbg_info_en.s.reserved_31_63
-        pesc_dbg_info_en.s.ecrc_e = 1;
-        pesc_dbg_info_en.s.rawwpp = 1;
-        pesc_dbg_info_en.s.racpp = 1;
-        pesc_dbg_info_en.s.ramtlp = 1;
-        pesc_dbg_info_en.s.rarwdns = 1;
-        pesc_dbg_info_en.s.caar = 1;
-        pesc_dbg_info_en.s.racca = 1;
-        pesc_dbg_info_en.s.racur = 1;
-        pesc_dbg_info_en.s.rauc = 1;
-        pesc_dbg_info_en.s.rqo = 1;
-        pesc_dbg_info_en.s.fcuv = 1;
-        pesc_dbg_info_en.s.rpe = 1;
-        pesc_dbg_info_en.s.fcpvwt = 1;
-        pesc_dbg_info_en.s.dpeoosd = 1;
-        pesc_dbg_info_en.s.rtwdle = 1;
-        pesc_dbg_info_en.s.rdwdle = 1;
-        pesc_dbg_info_en.s.mre = 1;
-        pesc_dbg_info_en.s.rte = 1;
-        pesc_dbg_info_en.s.acto = 1;
-        pesc_dbg_info_en.s.rvdm = 1;
-        pesc_dbg_info_en.s.rumep = 1;
-        pesc_dbg_info_en.s.rptamrc = 1;
-        pesc_dbg_info_en.s.rpmerc = 1;
-        pesc_dbg_info_en.s.rfemrc = 1;
-        pesc_dbg_info_en.s.rnfemrc = 1;
-        pesc_dbg_info_en.s.rcemrc = 1;
-        pesc_dbg_info_en.s.rpoison = 1;
-        pesc_dbg_info_en.s.recrce = 1;
-        pesc_dbg_info_en.s.rtlplle = 1;
-#if 0
-    /* RTLPMAL is disabled since it will be generated under normal conditions,
-        like devices causing legacy PCI interrupts */
-        pesc_dbg_info_en.s.rtlpmal = 1;
-#endif
-        pesc_dbg_info_en.s.spoison = 1;
-    }
-    cvmx_write_csr(CVMX_PESCX_DBG_INFO_EN(index), pesc_dbg_info_en.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pescx_dbg_info_decode decodes all interrupt bits in cvmx_pescx_dbg_info_t
- */
-void __cvmx_interrupt_pescx_dbg_info_decode(int index)
-{
-    cvmx_pescx_dbg_info_t pesc_dbg_info;
-    pesc_dbg_info.u64 = cvmx_read_csr(CVMX_PESCX_DBG_INFO(index));
-    pesc_dbg_info.u64 &= cvmx_read_csr(CVMX_PESCX_DBG_INFO_EN(index));
-    cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), pesc_dbg_info.u64);
-    // Skipping pesc_dbg_info.s.reserved_31_63
-    if (pesc_dbg_info.s.ecrc_e)
-        PRINT_ERROR("PESC%d_DBG_INFO[ECRC_E]: Received a ECRC error.\n"
-                    "    radm_ecrc_err\n", index);
-    if (pesc_dbg_info.s.rawwpp)
-        PRINT_ERROR("PESC%d_DBG_INFO[RAWWPP]: Received a write with poisoned payload\n"
-                    "    radm_rcvd_wreq_poisoned\n", index);
-    if (pesc_dbg_info.s.racpp)
-        PRINT_ERROR("PESC%d_DBG_INFO[RACPP]: Received a completion with poisoned payload\n"
-                    "    radm_rcvd_cpl_poisoned\n", index);
-    if (pesc_dbg_info.s.ramtlp)
-        PRINT_ERROR("PESC%d_DBG_INFO[RAMTLP]: Received a malformed TLP\n"
-                    "    radm_mlf_tlp_err\n", index);
-    if (pesc_dbg_info.s.rarwdns)
-        PRINT_ERROR("PESC%d_DBG_INFO[RARWDNS]: Recieved a request which device does not support\n"
-                    "    radm_rcvd_ur_req\n", index);
-    if (pesc_dbg_info.s.caar)
-        PRINT_ERROR("PESC%d_DBG_INFO[CAAR]: Completer aborted a request\n"
-                    "    radm_rcvd_ca_req\n"
-                    "    This bit will never be set because Octeon does\n"
-                    "    not generate Completer Aborts.\n", index);
-    if (pesc_dbg_info.s.racca)
-        PRINT_ERROR("PESC%d_DBG_INFO[RACCA]: Received a completion with CA status\n"
-                    "    radm_rcvd_cpl_ca\n", index);
-    if (pesc_dbg_info.s.racur)
-        PRINT_ERROR("PESC%d_DBG_INFO[RACUR]: Received a completion with UR status\n"
-                    "    radm_rcvd_cpl_ur\n", index);
-    if (pesc_dbg_info.s.rauc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RAUC]: Received an unexpected completion\n"
-                    "    radm_unexp_cpl_err\n", index);
-    if (pesc_dbg_info.s.rqo)
-        PRINT_ERROR("PESC%d_DBG_INFO[RQO]: Receive queue overflow. Normally happens only when\n"
-                    "    flow control advertisements are ignored\n"
-                    "    radm_qoverflow\n", index);
-    if (pesc_dbg_info.s.fcuv)
-        PRINT_ERROR("PESC%d_DBG_INFO[FCUV]: Flow Control Update Violation (opt. checks)\n"
-                    "    int_xadm_fc_prot_err\n", index);
-    if (pesc_dbg_info.s.rpe)
-        PRINT_ERROR("PESC%d_DBG_INFO[RPE]: When the PHY reports 8B/10B decode error\n"
-                    "    (RxStatus = 3b100) or disparity error\n"
-                    "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
-                    "    be asserted.\n"
-                    "    rmlh_rcvd_err\n", index);
-    if (pesc_dbg_info.s.fcpvwt)
-        PRINT_ERROR("PESC%d_DBG_INFO[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
-                    "    rtlh_fc_prot_err\n", index);
-    if (pesc_dbg_info.s.dpeoosd)
-        PRINT_ERROR("PESC%d_DBG_INFO[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
-                    "    rdlh_prot_err\n", index);
-    if (pesc_dbg_info.s.rtwdle)
-        PRINT_ERROR("PESC%d_DBG_INFO[RTWDLE]: Received TLP with DataLink Layer Error\n"
-                    "    rdlh_bad_tlp_err\n", index);
-    if (pesc_dbg_info.s.rdwdle)
-        PRINT_ERROR("PESC%d_DBG_INFO[RDWDLE]: Received DLLP with DataLink Layer Error\n"
-                    "    rdlh_bad_dllp_err\n", index);
-    if (pesc_dbg_info.s.mre)
-        PRINT_ERROR("PESC%d_DBG_INFO[MRE]: Max Retries Exceeded\n"
-                    "    xdlh_replay_num_rlover_err\n", index);
-    if (pesc_dbg_info.s.rte)
-        PRINT_ERROR("PESC%d_DBG_INFO[RTE]: Replay Timer Expired\n"
-                    "    xdlh_replay_timeout_err\n"
-                    "    This bit is set when the REPLAY_TIMER expires in\n"
-                    "    the PCIE core. The probability of this bit being\n"
-                    "    set will increase with the traffic load.\n", index);
-    if (pesc_dbg_info.s.acto)
-        PRINT_ERROR("PESC%d_DBG_INFO[ACTO]: A Completion Timeout Occured\n"
-                    "    pedc_radm_cpl_timeout\n", index);
-    if (pesc_dbg_info.s.rvdm)
-        PRINT_ERROR("PESC%d_DBG_INFO[RVDM]: Received Vendor-Defined Message\n"
-                    "    pedc_radm_vendor_msg\n", index);
-    if (pesc_dbg_info.s.rumep)
-        PRINT_ERROR("PESC%d_DBG_INFO[RUMEP]: Received Unlock Message (EP Mode Only)\n"
-                    "    pedc_radm_msg_unlock\n", index);
-    if (pesc_dbg_info.s.rptamrc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
-                    "    (RC Mode only)\n"
-                    "    pedc_radm_pm_to_ack\n", index);
-    if (pesc_dbg_info.s.rpmerc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RPMERC]: Received PME Message (RC Mode only)\n"
-                    "    pedc_radm_pm_pme\n", index);
-    if (pesc_dbg_info.s.rfemrc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
-                    "    pedc_radm_fatal_err\n"
-                    "    Bit set when a message with ERR_FATAL is set.\n", index);
-    if (pesc_dbg_info.s.rnfemrc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
-                    "    pedc_radm_nonfatal_err\n", index);
-    if (pesc_dbg_info.s.rcemrc)
-        PRINT_ERROR("PESC%d_DBG_INFO[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
-                    "    pedc_radm_correctable_err\n", index);
-    if (pesc_dbg_info.s.rpoison)
-        PRINT_ERROR("PESC%d_DBG_INFO[RPOISON]: Received Poisoned TLP\n"
-                    "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n", index);
-    if (pesc_dbg_info.s.recrce)
-        PRINT_ERROR("PESC%d_DBG_INFO[RECRCE]: Received ECRC Error\n"
-                    "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n", index);
-    if (pesc_dbg_info.s.rtlplle)
-        PRINT_ERROR("PESC%d_DBG_INFO[RTLPLLE]: Received TLP has link layer error\n"
-                    "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n", index);
-    if (pesc_dbg_info.s.rtlpmal)
-        PRINT_ERROR("PESC%d_DBG_INFO[RTLPMAL]: Received TLP is malformed or a message.\n"
-                    "    pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot\n"
-                    "    If the core receives a MSG (or Vendor Message)\n"
-                    "    this bit will be set.\n", index);
-    if (pesc_dbg_info.s.spoison)
-        PRINT_ERROR("PESC%d_DBG_INFO[SPOISON]: Poisoned TLP sent\n"
-                    "    peai__client0_tlp_ep & peai__client0_tlp_hv\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_pip_int_en_enable enables all interrupt bits in cvmx_pip_int_en_t
- */
-void __cvmx_interrupt_pip_int_en_enable(void)
-{
-    cvmx_pip_int_en_t pip_int_en;
-    cvmx_write_csr(CVMX_PIP_INT_REG, cvmx_read_csr(CVMX_PIP_INT_REG));
-    pip_int_en.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping pip_int_en.s.reserved_13_63
-        pip_int_en.s.punyerr = 1;
-        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping pip_int_en.s.reserved_9_63
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping pip_int_en.s.reserved_12_63
-        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        // Skipping pip_int_en.s.reserved_1_1
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping pip_int_en.s.reserved_9_63
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping pip_int_en.s.reserved_9_63
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping pip_int_en.s.reserved_13_63
-        pip_int_en.s.punyerr = 1;
-        // Skipping pip_int_en.s.reserved_9_11
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping pip_int_en.s.reserved_13_63
-        pip_int_en.s.punyerr = 1;
-        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
-        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
-        pip_int_en.s.beperr = 1;
-        pip_int_en.s.feperr = 1;
-        pip_int_en.s.todoovr = 1;
-        pip_int_en.s.skprunt = 1;
-        pip_int_en.s.badtag = 1;
-        pip_int_en.s.prtnxa = 1;
-        //pip_int_en.s.bckprs = 1; // Don't care
-        // Skipping pip_int_en.s.reserved_1_1
-        //pip_int_en.s.pktdrp = 1; // Don't care
-    }
-    cvmx_write_csr(CVMX_PIP_INT_EN, pip_int_en.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pip_int_reg_decode decodes all interrupt bits in cvmx_pip_int_reg_t
- */
-void __cvmx_interrupt_pip_int_reg_decode(void)
-{
-    cvmx_pip_int_reg_t pip_int_reg;
-    pip_int_reg.u64 = cvmx_read_csr(CVMX_PIP_INT_REG);
-    pip_int_reg.u64 &= cvmx_read_csr(CVMX_PIP_INT_EN);
-    cvmx_write_csr(CVMX_PIP_INT_REG, pip_int_reg.u64);
-    // Skipping pip_int_reg.s.reserved_13_63
-    if (pip_int_reg.s.punyerr)
-        PRINT_ERROR("PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
-                    "    stripping in IPD is enable\n");
-    if (pip_int_reg.s.lenerr)
-        PRINT_ERROR("PIP_INT_REG[LENERR]: Frame was received with length error\n");
-    if (pip_int_reg.s.maxerr)
-        PRINT_ERROR("PIP_INT_REG[MAXERR]: Frame was received with length > max_length\n");
-    if (pip_int_reg.s.minerr)
-        PRINT_ERROR("PIP_INT_REG[MINERR]: Frame was received with length < min_length\n");
-    if (pip_int_reg.s.beperr)
-        PRINT_ERROR("PIP_INT_REG[BEPERR]: Parity Error in back end memory\n");
-    if (pip_int_reg.s.feperr)
-        PRINT_ERROR("PIP_INT_REG[FEPERR]: Parity Error in front end memory\n");
-    if (pip_int_reg.s.todoovr)
-        PRINT_ERROR("PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n");
-    if (pip_int_reg.s.skprunt)
-        PRINT_ERROR("PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
-                    "    This interrupt can occur with received PARTIAL\n"
-                    "    packets that are truncated to SKIP bytes or\n"
-                    "    smaller.\n");
-    if (pip_int_reg.s.badtag)
-        PRINT_ERROR("PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n");
-    if (pip_int_reg.s.prtnxa)
-        PRINT_ERROR("PIP_INT_REG[PRTNXA]: Non-existent port\n");
-    if (pip_int_reg.s.bckprs)
-        PRINT_ERROR("PIP_INT_REG[BCKPRS]: PIP asserted backpressure\n");
-    if (pip_int_reg.s.crcerr)
-        PRINT_ERROR("PIP_INT_REG[CRCERR]: PIP calculated bad CRC\n");
-    if (pip_int_reg.s.pktdrp)
-        PRINT_ERROR("PIP_INT_REG[PKTDRP]: Packet Dropped due to QOS\n");
-}
-
-
-/**
- * __cvmx_interrupt_pko_reg_int_mask_enable enables all interrupt bits in cvmx_pko_reg_int_mask_t
- */
-void __cvmx_interrupt_pko_reg_int_mask_enable(void)
-{
-    cvmx_pko_reg_int_mask_t pko_reg_int_mask;
-    cvmx_write_csr(CVMX_PKO_REG_ERROR, cvmx_read_csr(CVMX_PKO_REG_ERROR));
-    pko_reg_int_mask.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_3_63
-        pko_reg_int_mask.s.currzero = 1;
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_2_63
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_3_63
-        pko_reg_int_mask.s.currzero = 1;
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_2_63
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_2_63
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_3_63
-        pko_reg_int_mask.s.currzero = 1;
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping pko_reg_int_mask.s.reserved_3_63
-        pko_reg_int_mask.s.currzero = 1;
-        pko_reg_int_mask.s.doorbell = 1;
-        pko_reg_int_mask.s.parity = 1;
-    }
-    cvmx_write_csr(CVMX_PKO_REG_INT_MASK, pko_reg_int_mask.u64);
-}
-
-
-/**
- * __cvmx_interrupt_pko_reg_error_decode decodes all interrupt bits in cvmx_pko_reg_error_t
- */
-void __cvmx_interrupt_pko_reg_error_decode(void)
-{
-    cvmx_pko_reg_error_t pko_reg_error;
-    pko_reg_error.u64 = cvmx_read_csr(CVMX_PKO_REG_ERROR);
-    pko_reg_error.u64 &= cvmx_read_csr(CVMX_PKO_REG_INT_MASK);
-    cvmx_write_csr(CVMX_PKO_REG_ERROR, pko_reg_error.u64);
-    // Skipping pko_reg_error.s.reserved_3_63
-    if (pko_reg_error.s.currzero)
-        PRINT_ERROR("PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n");
-    if (pko_reg_error.s.doorbell)
-        PRINT_ERROR("PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
-    if (pko_reg_error.s.parity)
-        PRINT_ERROR("PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n");
-}
-
-
-/**
- * __cvmx_interrupt_rad_reg_int_mask_enable enables all interrupt bits in cvmx_rad_reg_int_mask_t
- */
-void __cvmx_interrupt_rad_reg_int_mask_enable(void)
-{
-    cvmx_rad_reg_int_mask_t rad_reg_int_mask;
-    cvmx_write_csr(CVMX_RAD_REG_ERROR, cvmx_read_csr(CVMX_RAD_REG_ERROR));
-    rad_reg_int_mask.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping rad_reg_int_mask.s.reserved_1_63
-        rad_reg_int_mask.s.doorbell = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping rad_reg_int_mask.s.reserved_1_63
-        rad_reg_int_mask.s.doorbell = 1;
-    }
-    cvmx_write_csr(CVMX_RAD_REG_INT_MASK, rad_reg_int_mask.u64);
-}
-
-
-/**
- * __cvmx_interrupt_rad_reg_error_decode decodes all interrupt bits in cvmx_rad_reg_error_t
- */
-void __cvmx_interrupt_rad_reg_error_decode(void)
-{
-    cvmx_rad_reg_error_t rad_reg_error;
-    rad_reg_error.u64 = cvmx_read_csr(CVMX_RAD_REG_ERROR);
-    rad_reg_error.u64 &= cvmx_read_csr(CVMX_RAD_REG_INT_MASK);
-    cvmx_write_csr(CVMX_RAD_REG_ERROR, rad_reg_error.u64);
-    // Skipping rad_reg_error.s.reserved_1_63
-    if (rad_reg_error.s.doorbell)
-        PRINT_ERROR("RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
-}
-
-
-/**
- * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
- */
-void __cvmx_interrupt_spxx_int_msk_enable(int index)
-{
-    cvmx_spxx_int_msk_t spx_int_msk;
-    cvmx_write_csr(CVMX_SPXX_INT_REG(index), cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
-    spx_int_msk.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping spx_int_msk.s.reserved_12_63
-        spx_int_msk.s.calerr = 1;
-        spx_int_msk.s.syncerr = 1;
-        spx_int_msk.s.diperr = 1;
-        spx_int_msk.s.tpaovr = 1;
-        spx_int_msk.s.rsverr = 1;
-        spx_int_msk.s.drwnng = 1;
-        spx_int_msk.s.clserr = 1;
-        spx_int_msk.s.spiovr = 1;
-        // Skipping spx_int_msk.s.reserved_2_3
-        spx_int_msk.s.abnorm = 1;
-        spx_int_msk.s.prtnxa = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping spx_int_msk.s.reserved_12_63
-        spx_int_msk.s.calerr = 1;
-        spx_int_msk.s.syncerr = 1;
-        spx_int_msk.s.diperr = 1;
-        spx_int_msk.s.tpaovr = 1;
-        spx_int_msk.s.rsverr = 1;
-        spx_int_msk.s.drwnng = 1;
-        spx_int_msk.s.clserr = 1;
-        spx_int_msk.s.spiovr = 1;
-        // Skipping spx_int_msk.s.reserved_2_3
-        spx_int_msk.s.abnorm = 1;
-        spx_int_msk.s.prtnxa = 1;
-    }
-    cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
-}
-
-
-/**
- * __cvmx_interrupt_spxx_int_reg_decode decodes all interrupt bits in cvmx_spxx_int_reg_t
- */
-void __cvmx_interrupt_spxx_int_reg_decode(int index)
-{
-    cvmx_spxx_int_reg_t spx_int_reg;
-    spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));
-    spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));
-    cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);
-    // Skipping spx_int_reg.s.reserved_32_63
-    if (spx_int_reg.s.spf)
-        PRINT_ERROR("SPX%d_INT_REG[SPF]: Spi interface down\n", index);
-    // Skipping spx_int_reg.s.reserved_12_30
-    if (spx_int_reg.s.calerr)
-        PRINT_ERROR("SPX%d_INT_REG[CALERR]: Spi4 Calendar table parity error\n", index);
-    if (spx_int_reg.s.syncerr)
-        PRINT_ERROR("SPX%d_INT_REG[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
-                    "    SPX_ERR_CTL[ERRCNT]\n", index);
-    if (spx_int_reg.s.diperr)
-        PRINT_ERROR("SPX%d_INT_REG[DIPERR]: Spi4 DIP4 error\n", index);
-    if (spx_int_reg.s.tpaovr)
-        PRINT_ERROR("SPX%d_INT_REG[TPAOVR]: Selected port has hit TPA overflow\n", index);
-    if (spx_int_reg.s.rsverr)
-        PRINT_ERROR("SPX%d_INT_REG[RSVERR]: Spi4 reserved control word detected\n", index);
-    if (spx_int_reg.s.drwnng)
-        PRINT_ERROR("SPX%d_INT_REG[DRWNNG]: Spi4 receive FIFO drowning/overflow\n", index);
-    if (spx_int_reg.s.clserr)
-        PRINT_ERROR("SPX%d_INT_REG[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n", index);
-    if (spx_int_reg.s.spiovr)
-        PRINT_ERROR("SPX%d_INT_REG[SPIOVR]: Spi async FIFO overflow\n", index);
-    // Skipping spx_int_reg.s.reserved_2_3
-    if (spx_int_reg.s.abnorm)
-        PRINT_ERROR("SPX%d_INT_REG[ABNORM]: Abnormal packet termination (ERR bit)\n", index);
-    if (spx_int_reg.s.prtnxa)
-        PRINT_ERROR("SPX%d_INT_REG[PRTNXA]: Port out of range\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
- */
-void __cvmx_interrupt_stxx_int_msk_enable(int index)
-{
-    cvmx_stxx_int_msk_t stx_int_msk;
-    cvmx_write_csr(CVMX_STXX_INT_REG(index), cvmx_read_csr(CVMX_STXX_INT_REG(index)));
-    stx_int_msk.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping stx_int_msk.s.reserved_8_63
-        stx_int_msk.s.frmerr = 1;
-        stx_int_msk.s.unxfrm = 1;
-        stx_int_msk.s.nosync = 1;
-        stx_int_msk.s.diperr = 1;
-        stx_int_msk.s.datovr = 1;
-        stx_int_msk.s.ovrbst = 1;
-        stx_int_msk.s.calpar1 = 1;
-        stx_int_msk.s.calpar0 = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping stx_int_msk.s.reserved_8_63
-        stx_int_msk.s.frmerr = 1;
-        stx_int_msk.s.unxfrm = 1;
-        stx_int_msk.s.nosync = 1;
-        stx_int_msk.s.diperr = 1;
-        stx_int_msk.s.datovr = 1;
-        stx_int_msk.s.ovrbst = 1;
-        stx_int_msk.s.calpar1 = 1;
-        stx_int_msk.s.calpar0 = 1;
-    }
-    cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
-}
-
-
-/**
- * __cvmx_interrupt_stxx_int_reg_decode decodes all interrupt bits in cvmx_stxx_int_reg_t
- */
-void __cvmx_interrupt_stxx_int_reg_decode(int index)
-{
-    cvmx_stxx_int_reg_t stx_int_reg;
-    stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));
-    stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));
-    cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);
-    // Skipping stx_int_reg.s.reserved_9_63
-    if (stx_int_reg.s.syncerr)
-        PRINT_ERROR("STX%d_INT_REG[SYNCERR]: Interface encountered a fatal error\n", index);
-    if (stx_int_reg.s.frmerr)
-        PRINT_ERROR("STX%d_INT_REG[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n", index);
-    if (stx_int_reg.s.unxfrm)
-        PRINT_ERROR("STX%d_INT_REG[UNXFRM]: Unexpected framing sequence\n", index);
-    if (stx_int_reg.s.nosync)
-        PRINT_ERROR("STX%d_INT_REG[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n", index);
-    if (stx_int_reg.s.diperr)
-        PRINT_ERROR("STX%d_INT_REG[DIPERR]: DIP2 error on the Spi4 Status channel\n", index);
-    if (stx_int_reg.s.datovr)
-        PRINT_ERROR("STX%d_INT_REG[DATOVR]: Spi4 FIFO overflow error\n", index);
-    if (stx_int_reg.s.ovrbst)
-        PRINT_ERROR("STX%d_INT_REG[OVRBST]: Transmit packet burst too big\n", index);
-    if (stx_int_reg.s.calpar1)
-        PRINT_ERROR("STX%d_INT_REG[CALPAR1]: STX Calendar Table Parity Error Bank1\n", index);
-    if (stx_int_reg.s.calpar0)
-        PRINT_ERROR("STX%d_INT_REG[CALPAR0]: STX Calendar Table Parity Error Bank0\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_usbnx_int_enb_enable enables all interrupt bits in cvmx_usbnx_int_enb_t
- */
-void __cvmx_interrupt_usbnx_int_enb_enable(int index)
-{
-    cvmx_usbnx_int_enb_t usbn_int_enb;
-    cvmx_write_csr(CVMX_USBNX_INT_SUM(index), cvmx_read_csr(CVMX_USBNX_INT_SUM(index)));
-    usbn_int_enb.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        // Skipping usbn_int_enb.s.reserved_38_63
-        usbn_int_enb.s.nd4o_dpf = 1;
-        usbn_int_enb.s.nd4o_dpe = 1;
-        usbn_int_enb.s.nd4o_rpf = 1;
-        usbn_int_enb.s.nd4o_rpe = 1;
-        usbn_int_enb.s.ltl_f_pf = 1;
-        usbn_int_enb.s.ltl_f_pe = 1;
-        usbn_int_enb.s.u2n_c_pe = 1;
-        usbn_int_enb.s.u2n_c_pf = 1;
-        usbn_int_enb.s.u2n_d_pf = 1;
-        usbn_int_enb.s.u2n_d_pe = 1;
-        usbn_int_enb.s.n2u_pe = 1;
-        usbn_int_enb.s.n2u_pf = 1;
-        usbn_int_enb.s.uod_pf = 1;
-        usbn_int_enb.s.uod_pe = 1;
-        usbn_int_enb.s.rq_q3_e = 1;
-        usbn_int_enb.s.rq_q3_f = 1;
-        usbn_int_enb.s.rq_q2_e = 1;
-        usbn_int_enb.s.rq_q2_f = 1;
-        usbn_int_enb.s.rg_fi_f = 1;
-        usbn_int_enb.s.rg_fi_e = 1;
-        usbn_int_enb.s.l2_fi_f = 1;
-        usbn_int_enb.s.l2_fi_e = 1;
-        usbn_int_enb.s.l2c_a_f = 1;
-        usbn_int_enb.s.l2c_s_e = 1;
-        usbn_int_enb.s.dcred_f = 1;
-        usbn_int_enb.s.dcred_e = 1;
-        usbn_int_enb.s.lt_pu_f = 1;
-        usbn_int_enb.s.lt_po_e = 1;
-        usbn_int_enb.s.nt_pu_f = 1;
-        usbn_int_enb.s.nt_po_e = 1;
-        usbn_int_enb.s.pt_pu_f = 1;
-        usbn_int_enb.s.pt_po_e = 1;
-        usbn_int_enb.s.lr_pu_f = 1;
-        usbn_int_enb.s.lr_po_e = 1;
-        usbn_int_enb.s.nr_pu_f = 1;
-        usbn_int_enb.s.nr_po_e = 1;
-        usbn_int_enb.s.pr_pu_f = 1;
-        usbn_int_enb.s.pr_po_e = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
-    {
-        // Skipping usbn_int_enb.s.reserved_38_63
-        usbn_int_enb.s.nd4o_dpf = 1;
-        usbn_int_enb.s.nd4o_dpe = 1;
-        usbn_int_enb.s.nd4o_rpf = 1;
-        usbn_int_enb.s.nd4o_rpe = 1;
-        usbn_int_enb.s.ltl_f_pf = 1;
-        usbn_int_enb.s.ltl_f_pe = 1;
-        // Skipping usbn_int_enb.s.reserved_26_31
-        usbn_int_enb.s.uod_pf = 1;
-        usbn_int_enb.s.uod_pe = 1;
-        usbn_int_enb.s.rq_q3_e = 1;
-        usbn_int_enb.s.rq_q3_f = 1;
-        usbn_int_enb.s.rq_q2_e = 1;
-        usbn_int_enb.s.rq_q2_f = 1;
-        usbn_int_enb.s.rg_fi_f = 1;
-        usbn_int_enb.s.rg_fi_e = 1;
-        usbn_int_enb.s.l2_fi_f = 1;
-        usbn_int_enb.s.l2_fi_e = 1;
-        usbn_int_enb.s.l2c_a_f = 1;
-        usbn_int_enb.s.l2c_s_e = 1;
-        usbn_int_enb.s.dcred_f = 1;
-        usbn_int_enb.s.dcred_e = 1;
-        usbn_int_enb.s.lt_pu_f = 1;
-        usbn_int_enb.s.lt_po_e = 1;
-        usbn_int_enb.s.nt_pu_f = 1;
-        usbn_int_enb.s.nt_po_e = 1;
-        usbn_int_enb.s.pt_pu_f = 1;
-        usbn_int_enb.s.pt_po_e = 1;
-        usbn_int_enb.s.lr_pu_f = 1;
-        usbn_int_enb.s.lr_po_e = 1;
-        usbn_int_enb.s.nr_pu_f = 1;
-        usbn_int_enb.s.nr_po_e = 1;
-        usbn_int_enb.s.pr_pu_f = 1;
-        usbn_int_enb.s.pr_po_e = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping usbn_int_enb.s.reserved_38_63
-        usbn_int_enb.s.nd4o_dpf = 1;
-        usbn_int_enb.s.nd4o_dpe = 1;
-        usbn_int_enb.s.nd4o_rpf = 1;
-        usbn_int_enb.s.nd4o_rpe = 1;
-        usbn_int_enb.s.ltl_f_pf = 1;
-        usbn_int_enb.s.ltl_f_pe = 1;
-        usbn_int_enb.s.u2n_c_pe = 1;
-        usbn_int_enb.s.u2n_c_pf = 1;
-        usbn_int_enb.s.u2n_d_pf = 1;
-        usbn_int_enb.s.u2n_d_pe = 1;
-        usbn_int_enb.s.n2u_pe = 1;
-        usbn_int_enb.s.n2u_pf = 1;
-        usbn_int_enb.s.uod_pf = 1;
-        usbn_int_enb.s.uod_pe = 1;
-        usbn_int_enb.s.rq_q3_e = 1;
-        usbn_int_enb.s.rq_q3_f = 1;
-        usbn_int_enb.s.rq_q2_e = 1;
-        usbn_int_enb.s.rq_q2_f = 1;
-        usbn_int_enb.s.rg_fi_f = 1;
-        usbn_int_enb.s.rg_fi_e = 1;
-        usbn_int_enb.s.l2_fi_f = 1;
-        usbn_int_enb.s.l2_fi_e = 1;
-        usbn_int_enb.s.l2c_a_f = 1;
-        usbn_int_enb.s.l2c_s_e = 1;
-        usbn_int_enb.s.dcred_f = 1;
-        usbn_int_enb.s.dcred_e = 1;
-        usbn_int_enb.s.lt_pu_f = 1;
-        usbn_int_enb.s.lt_po_e = 1;
-        usbn_int_enb.s.nt_pu_f = 1;
-        usbn_int_enb.s.nt_po_e = 1;
-        usbn_int_enb.s.pt_pu_f = 1;
-        usbn_int_enb.s.pt_po_e = 1;
-        usbn_int_enb.s.lr_pu_f = 1;
-        usbn_int_enb.s.lr_po_e = 1;
-        usbn_int_enb.s.nr_pu_f = 1;
-        usbn_int_enb.s.nr_po_e = 1;
-        usbn_int_enb.s.pr_pu_f = 1;
-        usbn_int_enb.s.pr_po_e = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping usbn_int_enb.s.reserved_38_63
-        usbn_int_enb.s.nd4o_dpf = 1;
-        usbn_int_enb.s.nd4o_dpe = 1;
-        usbn_int_enb.s.nd4o_rpf = 1;
-        usbn_int_enb.s.nd4o_rpe = 1;
-        usbn_int_enb.s.ltl_f_pf = 1;
-        usbn_int_enb.s.ltl_f_pe = 1;
-        // Skipping usbn_int_enb.s.reserved_26_31
-        usbn_int_enb.s.uod_pf = 1;
-        usbn_int_enb.s.uod_pe = 1;
-        usbn_int_enb.s.rq_q3_e = 1;
-        usbn_int_enb.s.rq_q3_f = 1;
-        usbn_int_enb.s.rq_q2_e = 1;
-        usbn_int_enb.s.rq_q2_f = 1;
-        usbn_int_enb.s.rg_fi_f = 1;
-        usbn_int_enb.s.rg_fi_e = 1;
-        usbn_int_enb.s.l2_fi_f = 1;
-        usbn_int_enb.s.l2_fi_e = 1;
-        usbn_int_enb.s.l2c_a_f = 1;
-        usbn_int_enb.s.l2c_s_e = 1;
-        usbn_int_enb.s.dcred_f = 1;
-        usbn_int_enb.s.dcred_e = 1;
-        usbn_int_enb.s.lt_pu_f = 1;
-        usbn_int_enb.s.lt_po_e = 1;
-        usbn_int_enb.s.nt_pu_f = 1;
-        usbn_int_enb.s.nt_po_e = 1;
-        usbn_int_enb.s.pt_pu_f = 1;
-        usbn_int_enb.s.pt_po_e = 1;
-        usbn_int_enb.s.lr_pu_f = 1;
-        usbn_int_enb.s.lr_po_e = 1;
-        usbn_int_enb.s.nr_pu_f = 1;
-        usbn_int_enb.s.nr_po_e = 1;
-        usbn_int_enb.s.pr_pu_f = 1;
-        usbn_int_enb.s.pr_po_e = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        // Skipping usbn_int_enb.s.reserved_38_63
-        usbn_int_enb.s.nd4o_dpf = 1;
-        usbn_int_enb.s.nd4o_dpe = 1;
-        usbn_int_enb.s.nd4o_rpf = 1;
-        usbn_int_enb.s.nd4o_rpe = 1;
-        usbn_int_enb.s.ltl_f_pf = 1;
-        usbn_int_enb.s.ltl_f_pe = 1;
-        // Skipping usbn_int_enb.s.reserved_26_31
-        usbn_int_enb.s.uod_pf = 1;
-        usbn_int_enb.s.uod_pe = 1;
-        usbn_int_enb.s.rq_q3_e = 1;
-        usbn_int_enb.s.rq_q3_f = 1;
-        usbn_int_enb.s.rq_q2_e = 1;
-        usbn_int_enb.s.rq_q2_f = 1;
-        usbn_int_enb.s.rg_fi_f = 1;
-        usbn_int_enb.s.rg_fi_e = 1;
-        usbn_int_enb.s.l2_fi_f = 1;
-        usbn_int_enb.s.l2_fi_e = 1;
-        usbn_int_enb.s.l2c_a_f = 1;
-        usbn_int_enb.s.l2c_s_e = 1;
-        usbn_int_enb.s.dcred_f = 1;
-        usbn_int_enb.s.dcred_e = 1;
-        usbn_int_enb.s.lt_pu_f = 1;
-        usbn_int_enb.s.lt_po_e = 1;
-        usbn_int_enb.s.nt_pu_f = 1;
-        usbn_int_enb.s.nt_po_e = 1;
-        usbn_int_enb.s.pt_pu_f = 1;
-        usbn_int_enb.s.pt_po_e = 1;
-        usbn_int_enb.s.lr_pu_f = 1;
-        usbn_int_enb.s.lr_po_e = 1;
-        usbn_int_enb.s.nr_pu_f = 1;
-        usbn_int_enb.s.nr_po_e = 1;
-        usbn_int_enb.s.pr_pu_f = 1;
-        usbn_int_enb.s.pr_po_e = 1;
-    }
-    cvmx_write_csr(CVMX_USBNX_INT_ENB(index), usbn_int_enb.u64);
-}
-
-
-/**
- * __cvmx_interrupt_usbnx_int_sum_decode decodes all interrupt bits in cvmx_usbnx_int_sum_t
- */
-void __cvmx_interrupt_usbnx_int_sum_decode(int index)
-{
-    cvmx_usbnx_int_sum_t usbn_int_sum;
-    usbn_int_sum.u64 = cvmx_read_csr(CVMX_USBNX_INT_SUM(index));
-    usbn_int_sum.u64 &= cvmx_read_csr(CVMX_USBNX_INT_ENB(index));
-    cvmx_write_csr(CVMX_USBNX_INT_SUM(index), usbn_int_sum.u64);
-    // Skipping usbn_int_sum.s.reserved_38_63
-    if (usbn_int_sum.s.nd4o_dpf)
-        PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.nd4o_dpe)
-        PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.nd4o_rpf)
-        PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.nd4o_rpe)
-        PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.ltl_f_pf)
-        PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.ltl_f_pe)
-        PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.u2n_c_pe)
-        PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PE]: U2N Control Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.u2n_c_pf)
-        PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PF]: U2N Control Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.u2n_d_pf)
-        PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PF]: U2N Data Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.u2n_d_pe)
-        PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PE]: U2N Data Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.n2u_pe)
-        PRINT_ERROR("USBN%d_INT_SUM[N2U_PE]: N2U Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.n2u_pf)
-        PRINT_ERROR("USBN%d_INT_SUM[N2U_PF]: N2U Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.uod_pf)
-        PRINT_ERROR("USBN%d_INT_SUM[UOD_PF]: UOD Fifo Push Full.\n", index);
-    if (usbn_int_sum.s.uod_pe)
-        PRINT_ERROR("USBN%d_INT_SUM[UOD_PE]: UOD Fifo Pop Empty.\n", index);
-    if (usbn_int_sum.s.rq_q3_e)
-        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.rq_q3_f)
-        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.rq_q2_e)
-        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.rq_q2_f)
-        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.rg_fi_f)
-        PRINT_ERROR("USBN%d_INT_SUM[RG_FI_F]: Register Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.rg_fi_e)
-        PRINT_ERROR("USBN%d_INT_SUM[RG_FI_E]: Register Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.lt_fi_f)
-        PRINT_ERROR("USBN%d_INT_SUM[LT_FI_F]: L2C Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.lt_fi_e)
-        PRINT_ERROR("USBN%d_INT_SUM[LT_FI_E]: L2C Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.l2c_a_f)
-        PRINT_ERROR("USBN%d_INT_SUM[L2C_A_F]: L2C Credit Count Added When Full.\n", index);
-    if (usbn_int_sum.s.l2c_s_e)
-        PRINT_ERROR("USBN%d_INT_SUM[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n", index);
-    if (usbn_int_sum.s.dcred_f)
-        PRINT_ERROR("USBN%d_INT_SUM[DCRED_F]: Data CreditFifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.dcred_e)
-        PRINT_ERROR("USBN%d_INT_SUM[DCRED_E]: Data Credit Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.lt_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.lt_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n", index);
-    if (usbn_int_sum.s.nt_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.nt_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n", index);
-    if (usbn_int_sum.s.pt_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.pt_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n", index);
-    if (usbn_int_sum.s.lr_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[LR_PU_F]: L2C Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.lr_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[LR_PO_E]: L2C Request Fifo Popped When Empty.\n", index);
-    if (usbn_int_sum.s.nr_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[NR_PU_F]: NPI Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.nr_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[NR_PO_E]: NPI Request Fifo Popped When Empty.\n", index);
-    if (usbn_int_sum.s.pr_pu_f)
-        PRINT_ERROR("USBN%d_INT_SUM[PR_PU_F]: PP  Request Fifo Pushed When Full.\n", index);
-    if (usbn_int_sum.s.pr_po_e)
-        PRINT_ERROR("USBN%d_INT_SUM[PR_PO_E]: PP  Request Fifo Popped When Empty.\n", index);
-}
-
-
-/**
- * __cvmx_interrupt_zip_int_mask_enable enables all interrupt bits in cvmx_zip_int_mask_t
- */
-void __cvmx_interrupt_zip_int_mask_enable(void)
-{
-    cvmx_zip_int_mask_t zip_int_mask;
-    cvmx_write_csr(CVMX_ZIP_ERROR, cvmx_read_csr(CVMX_ZIP_ERROR));
-    zip_int_mask.u64 = 0;
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        // Skipping zip_int_mask.s.reserved_1_63
-        zip_int_mask.s.doorbell = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        // Skipping zip_int_mask.s.reserved_1_63
-        zip_int_mask.s.doorbell = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-        // Skipping zip_int_mask.s.reserved_1_63
-        zip_int_mask.s.doorbell = 1;
-    }
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        // Skipping zip_int_mask.s.reserved_1_63
-        zip_int_mask.s.doorbell = 1;
-    }
-    cvmx_write_csr(CVMX_ZIP_INT_MASK, zip_int_mask.u64);
-}
-
-
-/**
- * __cvmx_interrupt_zip_error_decode decodes all interrupt bits in cvmx_zip_error_t
- */
-void __cvmx_interrupt_zip_error_decode(void)
-{
-    cvmx_zip_error_t zip_error;
-    zip_error.u64 = cvmx_read_csr(CVMX_ZIP_ERROR);
-    zip_error.u64 &= cvmx_read_csr(CVMX_ZIP_INT_MASK);
-    cvmx_write_csr(CVMX_ZIP_ERROR, zip_error.u64);
-    // Skipping zip_error.s.reserved_1_63
-    if (zip_error.s.doorbell)
-        PRINT_ERROR("ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n");
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S b/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
index af47cbc..fc45622 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -7,33 +7,34 @@
  * modification, are permitted provided that the following conditions are
  * met:
  *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -44,6 +45,7 @@
 
 
 
+
 #include <machine/asm.h>
 #include <machine/regdef.h>
 
@@ -105,10 +107,17 @@ LEAF(cvmx_interrupt_stage2)
         dmfc0   k0, $14
         sd      k0, 280(sp)
 
+	dla	k0, cvmx_interrupt_in_isr
+	li	k1, 1
+	sw	k1, 0(k0)
+
 	dla     k0, cvmx_interrupt_do_irq
 	jal 	k0
 	dadd	a0, sp, 0	// First argument is array of registers
 
+	dla	k0, cvmx_interrupt_in_isr
+	sw	$0, 0(k0)
+
 	ld	k0, 256(sp)	// read hi
 	ld	k1, 264(sp)	// read lo
 	mthi	k0		// restore hi
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt-rsl.c b/sys/contrib/octeon-sdk/cvmx-interrupt-rsl.c
deleted file mode 100644
index aaafc30..0000000
--- a/sys/contrib/octeon-sdk/cvmx-interrupt-rsl.c
+++ /dev/null
@@ -1,762 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Utility functions to decode Octeon's RSL_INT_BLOCKS
- * interrupts into error messages.
- *
- * <hr>$Revision: 32636 $<hr>
- */
-#include "cvmx.h"
-#include "cvmx-interrupt.h"
-#include "cvmx-l2c.h"
-
-#ifndef PRINT_ERROR
-#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
-#endif
-
-/* Change this to a 1 before calling cvmx_interrupt_rsl_enable() to report
-    single bit ecc errors and other correctable errors */
-CVMX_SHARED int __cvmx_interrupt_ecc_report_single_bit_errors = 0;
-
-void __cvmx_interrupt_agl_gmx_rxx_int_en_enable(int index);
-void __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(int index);
-void __cvmx_interrupt_fpa_int_enb_enable(void);
-void __cvmx_interrupt_fpa_int_sum_decode(void);
-void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
-void __cvmx_interrupt_gmxx_rxx_int_reg_decode(int index, int block);
-void __cvmx_interrupt_iob_int_enb_enable(void);
-void __cvmx_interrupt_iob_int_sum_decode(void);
-void __cvmx_interrupt_ipd_int_enb_enable(void);
-void __cvmx_interrupt_ipd_int_sum_decode(void);
-void __cvmx_interrupt_key_int_enb_enable(void);
-void __cvmx_interrupt_key_int_sum_decode(void);
-void __cvmx_interrupt_mio_boot_int_enable(void);
-void __cvmx_interrupt_mio_boot_err_decode(void);
-void __cvmx_interrupt_npei_int_sum_decode(void);
-void __cvmx_interrupt_npei_int_enb2_enable(void);
-void __cvmx_interrupt_npi_int_enb_enable(void);
-void __cvmx_interrupt_npi_int_sum_decode(void);
-void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
-void __cvmx_interrupt_pcsx_intx_reg_decode(int index, int block);
-void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
-void __cvmx_interrupt_pcsxx_int_reg_decode(int index);
-void __cvmx_interrupt_pescx_dbg_info_en_enable(int index);
-void __cvmx_interrupt_pescx_dbg_info_decode(int index);
-void __cvmx_interrupt_pip_int_en_enable(void);
-void __cvmx_interrupt_pip_int_reg_decode(void);
-void __cvmx_interrupt_pko_reg_int_mask_enable(void);
-void __cvmx_interrupt_pko_reg_error_decode(void);
-void __cvmx_interrupt_rad_reg_int_mask_enable(void);
-void __cvmx_interrupt_rad_reg_error_decode(void);
-void __cvmx_interrupt_spxx_int_msk_enable(int index);
-void __cvmx_interrupt_spxx_int_reg_decode(int index);
-void __cvmx_interrupt_stxx_int_msk_enable(int index);
-void __cvmx_interrupt_stxx_int_reg_decode(int index);
-void __cvmx_interrupt_usbnx_int_enb_enable(int index);
-void __cvmx_interrupt_usbnx_int_sum_decode(int index);
-void __cvmx_interrupt_zip_int_mask_enable(void);
-void __cvmx_interrupt_zip_error_decode(void);
-
-
-/**
- * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
- * CN58XX.
- *
- * @param block  Interface to enable 0-1
- */
-static void __cvmx_interrupt_asxx_enable(int block)
-{
-    int mask;
-    cvmx_asxx_int_en_t csr;
-    /* CN38XX and CN58XX have two interfaces with 4 ports per interface. All
-        other chips have a max of 3 ports on interface 0 */
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-        mask = 0xf; /* Set enables for 4 ports */
-    else
-        mask = 0x7; /* Set enables for 3 ports */
-
-    /* Enable interface interrupts */
-    csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
-    csr.s.txpsh = mask;
-    csr.s.txpop = mask;
-    csr.s.ovrflw = mask;
-    cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
-}
-
-
-/**
- * Decode ASX error interrupts for CN3XXX, CN50XX, and CN58XX
- *
- * @param block  Interface to decode 0-1
- */
-static void __cvmx_interrupt_asxx_decode(int block)
-{
-    cvmx_asxx_int_reg_t err;
-    err.u64 = cvmx_read_csr(CVMX_ASXX_INT_REG(block));
-    cvmx_write_csr(CVMX_ASXX_INT_REG(block), err.u64);
-    if (err.u64)
-    {
-        int port;
-        for (port = 0; port < 4; port++)
-        {
-            if (err.s.ovrflw & (1 << port))
-                PRINT_ERROR("ASX%d_INT_REG[OVRFLW]: RX FIFO overflow on RMGII port %d\n",
-                             block, port + block*16);
-            if (err.s.txpop & (1 << port))
-                PRINT_ERROR("ASX%d_INT_REG[TXPOP]: TX FIFO underflow on RMGII port %d\n",
-                             block, port + block*16);
-            if (err.s.txpsh & (1 << port))
-                PRINT_ERROR("ASX%d_INT_REG[TXPSH]: TX FIFO overflow on RMGII port %d\n",
-                             block, port + block*16);
-        }
-    }
-}
-
-
-/**
- * Enable DFA errors for CN38XX, CN58XX, and CN31XX
- */
-static void __cvmx_interrupt_dfa_enable(void)
-{
-    cvmx_dfa_err_t csr;
-    csr.u64 = cvmx_read_csr(CVMX_DFA_ERR);
-    csr.s.dblina = 1;
-    csr.s.cp2pina = 1;
-    csr.s.cp2parena = 0;
-    csr.s.dtepina = 1;
-    csr.s.dteparena = 1;
-    csr.s.dtedbina = 1;
-    csr.s.dtesbina = __cvmx_interrupt_ecc_report_single_bit_errors;
-    csr.s.dteeccena = 1;
-    csr.s.cp2dbina = 1;
-    csr.s.cp2sbina = __cvmx_interrupt_ecc_report_single_bit_errors;
-    csr.s.cp2eccena = 1;
-    cvmx_write_csr(CVMX_DFA_ERR, csr.u64);
-}
-
-
-/**
- * Decode DFA errors for CN38XX, CN58XX, and CN31XX
- */
-static void __cvmx_interrupt_dfa_decode(void)
-{
-    cvmx_dfa_err_t err;
-
-    err.u64 = cvmx_read_csr(CVMX_DFA_ERR);
-    cvmx_write_csr(CVMX_DFA_ERR, err.u64);
-    if (err.u64)
-    {
-        if (err.s.dblovf)
-            PRINT_ERROR("DFA_ERR[DBLOVF]: Doorbell Overflow detected\n");
-        if (err.s.cp2perr)
-            PRINT_ERROR("DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected\n");
-        if (err.s.dteperr)
-            PRINT_ERROR("DFA_ERR[DTEPERR]: DTE Parity Error Detected\n");
-
-        if (err.s.dtedbe)
-            PRINT_ERROR("DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected\n");
-        if (err.s.dtesbe && __cvmx_interrupt_ecc_report_single_bit_errors)
-            PRINT_ERROR("DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected\n");
-        if (err.s.dtedbe || (err.s.dtesbe && __cvmx_interrupt_ecc_report_single_bit_errors))
-            PRINT_ERROR("DFA_ERR[DTESYN]: Failing syndrome %u\n", err.s.dtesyn);
-
-        if (err.s.cp2dbe)
-            PRINT_ERROR("DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected\n");
-        if (err.s.cp2sbe && __cvmx_interrupt_ecc_report_single_bit_errors)
-            PRINT_ERROR("DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected\n");
-        if (err.s.cp2dbe || (err.s.cp2sbe && __cvmx_interrupt_ecc_report_single_bit_errors))
-            PRINT_ERROR("DFA_ERR[CP2SYN]: Failing syndrome %u\n", err.s.cp2syn);
-    }
-}
-
-
-/**
- * Enable L2 error interrupts for all chips
- */
-static void __cvmx_interrupt_l2_enable(void)
-{
-    cvmx_l2t_err_t csr;
-    cvmx_l2d_err_t csr2;
-
-    /* Enable ECC Interrupts for double bit errors from L2C Tags */
-    csr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-    csr.s.lck_intena2 = 1;
-    csr.s.lck_intena = 1;
-    csr.s.ded_intena = 1;
-    csr.s.sec_intena = __cvmx_interrupt_ecc_report_single_bit_errors;
-    csr.s.ecc_ena = 1;
-    cvmx_write_csr(CVMX_L2T_ERR, csr.u64);
-
-    /* Enable ECC Interrupts for double bit errors from L2D Errors */
-    csr2.u64 = cvmx_read_csr(CVMX_L2D_ERR);
-    csr2.s.ded_intena = 1;
-    csr2.s.sec_intena = __cvmx_interrupt_ecc_report_single_bit_errors;
-    csr2.s.ecc_ena = 1;
-    cvmx_write_csr(CVMX_L2D_ERR, csr2.u64);
-}
-
-
-/**
- * Decode L2 error interrupts for all chips
- */
-static void __cvmx_interrupt_l2_decode(void)
-{
-    cvmx_l2t_err_t terr;
-    cvmx_l2d_err_t derr;
-    uint64_t clr_val;
-
-    terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-    cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
-    if (terr.u64)
-    {
-        if (terr.s.ded_err)
-            PRINT_ERROR("L2T_ERR[DED_ERR]: double bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
-                         terr.s.fadr, terr.s.fset, terr.s.fsyn);
-        if (terr.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors)
-            PRINT_ERROR("L2T_ERR[SEC_ERR]: single bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
-                         terr.s.fadr, terr.s.fset, terr.s.fsyn);
-        if (terr.s.ded_err || terr.s.sec_err)
-        {
-            if (!terr.s.fsyn)
-            {
-                /* Syndrome is zero, which means error was in non-hit line,
-                    so flush all associations */
-                int i;
-                int l2_assoc = cvmx_l2c_get_num_assoc();
-
-                for (i = 0; i < l2_assoc; i++)
-                    cvmx_l2c_flush_line(i, terr.s.fadr);
-            }
-            else
-                cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
-
-        }
-        if (terr.s.lckerr2)
-            PRINT_ERROR("L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).\n");
-        if (terr.s.lckerr)
-            PRINT_ERROR("L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).\n");
-    }
-
-    clr_val = derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
-    if (derr.u64)
-    {
-        cvmx_l2d_fadr_t fadr;
-
-        if (derr.s.ded_err || (derr.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors))
-        {
-            const int coreid = (int) cvmx_get_core_num();
-            uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
-            uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
-            fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
-            if (derr.s.ded_err)
-                PRINT_ERROR("L2D_ERR[DED_ERR] ECC double (core %d): fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
-                             coreid, (unsigned long long) fadr.u64, (unsigned long long) syn0, (unsigned long long) syn1);
-            else
-                PRINT_ERROR("L2D_ERR[SEC_ERR] ECC single (core %d): fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
-                             coreid, (unsigned long long) fadr.u64, (unsigned long long) syn0, (unsigned long long) syn1);
-            /* Flush the line that had the error */
-            if (derr.s.ded_err || derr.s.sec_err)
-                cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
-        }
-    }
-    cvmx_write_csr(CVMX_L2D_ERR, clr_val);
-}
-
-
-/**
- * Enable LMC (DDR controller) interrupts for all chips
- *
- * @param ddr_controller
- *               Which controller to enable for 0-1
- */
-static void __cvmx_interrupt_lmcx_enable(int ddr_controller)
-{
-    cvmx_lmc_mem_cfg0_t csr;
-
-    /* The LMC controllers can be independently enabled/disabled on CN56XX.
-        If a controller is disabled it can't be accessed at all since it
-        isn't clocked */
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        cvmx_l2c_cfg_t l2c_cfg;
-        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
-        if (!l2c_cfg.s.dpres0 && (ddr_controller == 0))
-            return;
-        if (!l2c_cfg.s.dpres1 && (ddr_controller == 1))
-            return;
-    }
-
-    csr.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
-    csr.s.intr_ded_ena = 1;
-    csr.s.intr_sec_ena = __cvmx_interrupt_ecc_report_single_bit_errors;
-    cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller), csr.u64);
-}
-
-
-/**
- * Decode LMC (DDR controller) interrupts for all chips
- *
- * @param ddr_controller
- *               Which controller to decode 0-1
- */
-static void __cvmx_interrupt_lmcx_decode(int ddr_controller)
-{
-    /* These static counters are used to track ECC error counts */
-    static CVMX_SHARED unsigned long single_bit_errors[2] = {0, 0};
-    static CVMX_SHARED unsigned long double_bit_errors[2] = {0, 0};
-    cvmx_lmcx_mem_cfg0_t mem_cfg0;
-    cvmx_lmc_fadr_t fadr;
-
-    mem_cfg0.u64 =cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
-    fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR (ddr_controller));
-    cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller),mem_cfg0.u64);
-    if (mem_cfg0.s.sec_err || mem_cfg0.s.ded_err)
-    {
-        int pop_count;
-        CVMX_DPOP(pop_count, mem_cfg0.s.sec_err);
-        single_bit_errors[ddr_controller] += pop_count;
-        CVMX_DPOP(pop_count, mem_cfg0.s.ded_err);
-        double_bit_errors[ddr_controller] += pop_count;
-        if (mem_cfg0.s.ded_err || (mem_cfg0.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors))
-        {
-            PRINT_ERROR("DDR%d ECC: %lu Single bit corrections, %lu Double bit errors\n"
-                         "DDR%d ECC:\tFailing dimm:   %u\n"
-                         "DDR%d ECC:\tFailing rank:   %u\n"
-                         "DDR%d ECC:\tFailing bank:   %u\n"
-                         "DDR%d ECC:\tFailing row:    0x%x\n"
-                         "DDR%d ECC:\tFailing column: 0x%x\n",
-                         ddr_controller, single_bit_errors[ddr_controller], double_bit_errors[ddr_controller],
-                         ddr_controller, fadr.s.fdimm,
-                         ddr_controller, fadr.s.fbunk,
-                         ddr_controller, fadr.s.fbank,
-                         ddr_controller, fadr.s.frow,
-                         ddr_controller, fadr.s.fcol);
-        }
-    }
-}
-
-
-/**
- * Decode GMX error interrupts
- *
- * @param block  GMX interface to decode
- */
-static void __cvmx_interrupt_gmxx_decode(int block)
-{
-    int index;
-    cvmx_gmxx_tx_int_reg_t csr;
-
-    csr.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_REG(block)) & cvmx_read_csr(CVMX_GMXX_TX_INT_EN(block));
-    cvmx_write_csr(CVMX_GMXX_TX_INT_REG(block), csr.u64);
-
-    for (index=0; index<4; index++)
-    {
-        if (csr.s.late_col & (1<<index))
-            PRINT_ERROR("GMX%d_TX%d_INT_REG[LATE_COL]: TX Late Collision\n", block, index);
-        if (csr.s.xsdef & (1<<index))
-            PRINT_ERROR("GMX%d_TX%d_INT_REG[XSDEF]: TX Excessive deferral\n", block, index);
-        if (csr.s.xscol & (1<<index))
-            PRINT_ERROR("GMX%d_TX%d_INT_REG[XSCOL]: TX Excessive collisions\n", block, index);
-        if (csr.s.undflw & (1<<index))
-            PRINT_ERROR("GMX%d_TX%d_INT_REG[UNDFLW]: TX Underflow\n", block, index);
-    }
-    if (csr.s.ncb_nxa)
-        PRINT_ERROR("GMX%d_TX_INT_REG[NCB_NXA]: Port address out-of-range from NCB Interface\n", block);
-    if (csr.s.pko_nxa)
-        PRINT_ERROR("GMX%d_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n", block);
-
-    __cvmx_interrupt_gmxx_rxx_int_reg_decode(0, block);
-    __cvmx_interrupt_gmxx_rxx_int_reg_decode(1, block);
-    __cvmx_interrupt_gmxx_rxx_int_reg_decode(2, block);
-    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
-        __cvmx_interrupt_gmxx_rxx_int_reg_decode(3, block);
-}
-
-
-/**
- * Enable POW error interrupts for all chips
- */
-static void __cvmx_interrupt_pow_enable(void)
-{
-    cvmx_pow_ecc_err_t csr;
-    csr.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
-    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) && !OCTEON_IS_MODEL(OCTEON_CN31XX))
-    {
-            /* These doesn't exist for chips CN31XX and CN38XXp2 */
-            csr.s.iop_ie = 0x1fff;
-    }
-    csr.s.rpe_ie = 1;
-    csr.s.dbe_ie = 1;
-    csr.s.sbe_ie = __cvmx_interrupt_ecc_report_single_bit_errors;
-    cvmx_write_csr(CVMX_POW_ECC_ERR, csr.u64);
-}
-
-
-/**
- * Decode POW error interrupts for all chips
- */
-static void __cvmx_interrupt_pow_decode(void)
-{
-    cvmx_pow_ecc_err_t err;
-
-    err.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
-    cvmx_write_csr(CVMX_POW_ECC_ERR, err.u64);
-    if (err.u64)
-    {
-        if (err.s.sbe && __cvmx_interrupt_ecc_report_single_bit_errors)
-            PRINT_ERROR("POW_ECC_ERR[SBE]: POW single bit error\n");
-        if (err.s.dbe)
-            PRINT_ERROR("POW_ECC_ERR[DBE]: POW double bit error\n");
-        if (err.s.dbe || (err.s.sbe && __cvmx_interrupt_ecc_report_single_bit_errors))
-            PRINT_ERROR("POW_ECC_ERR[SYN]: Failing syndrome %u\n", err.s.syn);
-        if (err.s.rpe)
-            PRINT_ERROR("POW_ECC_ERR[RPE]: Remote pointer error\n");
-        if (err.s.iop & (1 << 0))
-            PRINT_ERROR("POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state\n");
-        if (err.s.iop & (1 << 1))
-            PRINT_ERROR("POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state\n");
-        if (err.s.iop & (1 << 2))
-            PRINT_ERROR("POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC\n");
-        if (err.s.iop & (1 << 3))
-            PRINT_ERROR("POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL\n");
-        if (err.s.iop & (1 << 4))
-            PRINT_ERROR("POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL\n");
-        if (err.s.iop & (1 << 5))
-            PRINT_ERROR("POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending\n");
-        if (err.s.iop & (1 << 6))
-            PRINT_ERROR("POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending\n");
-        if (err.s.iop & (1 << 7))
-            PRINT_ERROR("POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n");
-        if (err.s.iop & (1 << 8))
-            PRINT_ERROR("POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending\n");
-        if (err.s.iop & (1 << 9))
-            PRINT_ERROR("POW_ECC_ERR[IOP9]: Received illegal opcode\n");
-        if (err.s.iop & (1 << 10))
-            PRINT_ERROR("POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL\n");
-        if (err.s.iop & (1 << 11))
-            PRINT_ERROR("POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending\n");
-        if (err.s.iop & (1 << 12))
-            PRINT_ERROR("POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending\n");
-    }
-}
-
-
-/**
- * Enable TIM tiemr wheel interrupts for all chips
- */
-static void __cvmx_interrupt_tim_enable(void)
-{
-    cvmx_tim_reg_int_mask_t csr;
-    csr.u64 = cvmx_read_csr(CVMX_TIM_REG_INT_MASK);
-    csr.s.mask = 0xffff;
-    cvmx_write_csr(CVMX_TIM_REG_INT_MASK, csr.u64);
-}
-
-
-/**
- * Decode TIM timer wheel interrupts
- */
-static void __cvmx_interrupt_tim_decode(void)
-{
-    cvmx_tim_reg_error_t err;
-
-    err.u64 = cvmx_read_csr(CVMX_TIM_REG_ERROR);
-    cvmx_write_csr(CVMX_TIM_REG_ERROR, err.u64);
-    if (err.u64)
-    {
-        int i;
-        for (i = 0; i < 16; i++)
-            if (err.s.mask & (1 << i))
-                PRINT_ERROR("TIM_REG_ERROR[MASK]: Timer wheel %d error\n", i);
-    }
-}
-
-
-/**
- * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
- * into error messages.
- */
-void cvmx_interrupt_rsl_decode(void)
-{
-    uint64_t rsl_int_blocks;
-
-    /* Reading the RSL interrupts is different between PCI and PCIe chips */
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-        rsl_int_blocks = cvmx_read_csr(CVMX_PEXP_NPEI_RSL_INT_BLOCKS);
-    else
-        rsl_int_blocks = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
-
-    /* Not all chips support all error interrupts. This code assumes
-        that unsupported interrupts always are zero */
-
-    /* Bits 63-31 are unused on all chips */
-    if (rsl_int_blocks & (1ull<<30)) __cvmx_interrupt_iob_int_sum_decode();
-    if (rsl_int_blocks & (1ull<<29)) __cvmx_interrupt_lmcx_decode(1);
-    if (rsl_int_blocks & (1ull<<28))
-    {
-        __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(0);
-        if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-            __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(1);
-    }
-    /* Bit 27-24 are unused on all chips */
-    if (rsl_int_blocks & (1ull<<23))
-    {
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-        {
-            __cvmx_interrupt_pcsx_intx_reg_decode(0, 1);
-            __cvmx_interrupt_pcsx_intx_reg_decode(1, 1);
-            __cvmx_interrupt_pcsx_intx_reg_decode(2, 1);
-            __cvmx_interrupt_pcsx_intx_reg_decode(3, 1);
-            __cvmx_interrupt_pcsxx_int_reg_decode(1);
-        }
-        else
-            __cvmx_interrupt_asxx_decode(1);
-    }
-    if (rsl_int_blocks & (1ull<<22))
-    {
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-        {
-            __cvmx_interrupt_pcsx_intx_reg_decode(0, 0);
-            __cvmx_interrupt_pcsx_intx_reg_decode(1, 0);
-            __cvmx_interrupt_pcsx_intx_reg_decode(2, 0);
-            __cvmx_interrupt_pcsx_intx_reg_decode(3, 0);
-            __cvmx_interrupt_pcsxx_int_reg_decode(0);
-        }
-        else
-            __cvmx_interrupt_asxx_decode(0);
-    }
-    /* Bit 21 is unsed on all chips */
-    if (rsl_int_blocks & (1ull<<20)) __cvmx_interrupt_pip_int_reg_decode();
-    if (rsl_int_blocks & (1ull<<19))
-    {
-        __cvmx_interrupt_spxx_int_reg_decode(1);
-        __cvmx_interrupt_stxx_int_reg_decode(1);
-    }
-    if (rsl_int_blocks & (1ull<<18))
-    {
-        __cvmx_interrupt_spxx_int_reg_decode(0);
-        __cvmx_interrupt_stxx_int_reg_decode(0);
-    }
-    if (rsl_int_blocks & (1ull<<17)) __cvmx_interrupt_lmcx_decode(0);
-    if (rsl_int_blocks & (1ull<<16)) __cvmx_interrupt_l2_decode();
-    if (rsl_int_blocks & (1ull<<15)) __cvmx_interrupt_usbnx_int_sum_decode(1);
-    if (rsl_int_blocks & (1ull<<14)) __cvmx_interrupt_rad_reg_error_decode();
-    if (rsl_int_blocks & (1ull<<13)) __cvmx_interrupt_usbnx_int_sum_decode(0);
-    if (rsl_int_blocks & (1ull<<12)) __cvmx_interrupt_pow_decode();
-    if (rsl_int_blocks & (1ull<<11)) __cvmx_interrupt_tim_decode();
-    if (rsl_int_blocks & (1ull<<10)) __cvmx_interrupt_pko_reg_error_decode();
-    if (rsl_int_blocks & (1ull<< 9)) __cvmx_interrupt_ipd_int_sum_decode();
-    /* Bit 8 is unused on all chips */
-    if (rsl_int_blocks & (1ull<< 7)) __cvmx_interrupt_zip_error_decode();
-    if (rsl_int_blocks & (1ull<< 6)) __cvmx_interrupt_dfa_decode();
-    if (rsl_int_blocks & (1ull<< 5)) __cvmx_interrupt_fpa_int_sum_decode();
-    if (rsl_int_blocks & (1ull<< 4)) __cvmx_interrupt_key_int_sum_decode();
-    if (rsl_int_blocks & (1ull<< 3))
-    {
-        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-            __cvmx_interrupt_npei_int_sum_decode();
-        else
-            __cvmx_interrupt_npi_int_sum_decode();
-    }
-    if (rsl_int_blocks & (1ull<< 2)) __cvmx_interrupt_gmxx_decode(1);
-    if (rsl_int_blocks & (1ull<< 1)) __cvmx_interrupt_gmxx_decode(0);
-    if (rsl_int_blocks & (1ull<< 0)) __cvmx_interrupt_mio_boot_err_decode();
-}
-
-
-/**
- * Enable GMX error reporting for the supplied interface
- *
- * @param interface Interface to enable
- */
-static void __cvmx_interrupt_gmxx_enable(int interface)
-{
-    cvmx_gmxx_inf_mode_t mode;
-    cvmx_gmxx_tx_int_en_t gmx_tx_int_en;
-    int num_ports;
-    int index;
-
-    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
-
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        if (mode.s.en)
-        {
-            switch(mode.cn56xx.mode)
-            {
-                case 1: /* XAUI */
-                    num_ports = 1;
-                    break;
-                case 2: /* SGMII */
-                case 3: /* PICMG */
-                    num_ports = 4;
-                    break;
-                default: /* Disabled */
-                    num_ports = 0;
-                    break;
-            }
-        }
-        else
-            num_ports = 0;
-    }
-    else
-    {
-        if (mode.s.en)
-        {
-            if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-            {
-                /* SPI on CN38XX and CN58XX report all errors through port 0.
-                    RGMII needs to check all 4 ports */
-                if (mode.s.type)
-                    num_ports = 1;
-                else
-                    num_ports = 4;
-            }
-            else
-            {
-                /* CN30XX, CN31XX, and CN50XX have two or three ports. GMII
-                    and MII has 2, RGMII has three */
-                if (mode.s.type)
-                    num_ports = 2;
-                else
-                    num_ports = 3;
-            }
-        }
-        else
-            num_ports = 0;
-    }
-
-    gmx_tx_int_en.u64 = 0;
-    if (num_ports)
-    {
-        gmx_tx_int_en.s.ncb_nxa = 1;
-        gmx_tx_int_en.s.pko_nxa = 1;
-    }
-    gmx_tx_int_en.s.undflw = (1<<num_ports)-1;
-    cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
-    for (index=0; index<num_ports;index++)
-        __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
-}
-
-
-/**
- * Utility function to enable all RSL error interupts
- */
-void cvmx_interrupt_rsl_enable(void)
-{
-    /* Bits 63-31 are unused on all chips */
-    __cvmx_interrupt_iob_int_enb_enable();
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-        __cvmx_interrupt_lmcx_enable(1);
-    if (octeon_has_feature(OCTEON_FEATURE_MGMT_PORT))
-    {
-        // FIXME __cvmx_interrupt_agl_gmx_rxx_int_en_enable(0);
-        //if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-        //    __cvmx_interrupt_agl_gmx_rxx_int_en_enable(1);
-    }
-    /* Bit 27-24 are unused on all chips */
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-        __cvmx_interrupt_asxx_enable(1);
-    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(0, 1);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(1, 1);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(2, 1);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(3, 1);
-        __cvmx_interrupt_pcsxx_int_en_reg_enable(1);
-    }
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-    {
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(0, 0);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(1, 0);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(2, 0);
-        __cvmx_interrupt_pcsx_intx_en_reg_enable(3, 0);
-        __cvmx_interrupt_pcsxx_int_en_reg_enable(0);
-    }
-    else
-        __cvmx_interrupt_asxx_enable(0);
-    /* Bit 21 is unsed on all chips */
-    __cvmx_interrupt_pip_int_en_enable();
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-    {
-        __cvmx_interrupt_spxx_int_msk_enable(1);
-        __cvmx_interrupt_stxx_int_msk_enable(1);
-        __cvmx_interrupt_spxx_int_msk_enable(0);
-        __cvmx_interrupt_stxx_int_msk_enable(0);
-    }
-    __cvmx_interrupt_lmcx_enable(0);
-    __cvmx_interrupt_l2_enable();
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
-        __cvmx_interrupt_usbnx_int_enb_enable(1);
-    if (octeon_has_feature(OCTEON_FEATURE_RAID))
-        __cvmx_interrupt_rad_reg_int_mask_enable();
-    if (octeon_has_feature(OCTEON_FEATURE_USB))
-        __cvmx_interrupt_usbnx_int_enb_enable(0);
-    __cvmx_interrupt_pow_enable();
-    __cvmx_interrupt_tim_enable();
-    __cvmx_interrupt_pko_reg_int_mask_enable();
-    __cvmx_interrupt_ipd_int_enb_enable();
-    /* Bit 8 is unused on all chips */
-    if (octeon_has_feature(OCTEON_FEATURE_ZIP))
-        __cvmx_interrupt_zip_int_mask_enable();
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-        __cvmx_interrupt_dfa_enable();
-    __cvmx_interrupt_fpa_int_enb_enable();
-    if (octeon_has_feature(OCTEON_FEATURE_KEY_MEMORY))
-        __cvmx_interrupt_key_int_enb_enable();
-    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
-    {
-        cvmx_ciu_soft_prst_t ciu_soft_prst;
-        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
-        if (ciu_soft_prst.s.soft_prst == 0)
-            __cvmx_interrupt_npei_int_enb2_enable();
-    }
-    else if (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST)
-        __cvmx_interrupt_npi_int_enb_enable();
-
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) ||
-        OCTEON_IS_MODEL(OCTEON_CN56XX))
-        __cvmx_interrupt_gmxx_enable(1);
-    __cvmx_interrupt_gmxx_enable(0);
-
-    __cvmx_interrupt_mio_boot_int_enable();
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt.c b/sys/contrib/octeon-sdk/cvmx-interrupt.c
index fdf3645..9280e8d 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt.c
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,20 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the Mips interrupts.
  *
- * <hr>$Revision: 42264 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifndef __U_BOOT__
 #if __GNUC__ >= 4
 /* Backtrace is only available with the new toolchain.  */
 #include <execinfo.h>
 #endif
+#endif  /* __U_BOOT__ */
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-interrupt.h"
@@ -62,10 +66,15 @@
 #include "cvmx-coremask.h"
 #include "cvmx-spinlock.h"
 #include "cvmx-app-init.h"
+#include "cvmx-error.h"
+#include "../../bootloader/u-boot/include/octeon_mem_map.h"
 
 EXTERN_ASM void cvmx_interrupt_stage1(void);
+EXTERN_ASM void cvmx_debug_handler_stage1(void);
 EXTERN_ASM void cvmx_interrupt_cache_error(void);
 
+int cvmx_interrupt_in_isr = 0;
+
 /**
  * Internal status the interrupt registration
  */
@@ -79,17 +88,108 @@ typedef struct
 /**
  * Internal state the interrupt registration
  */
+#ifndef __U_BOOT__
 static CVMX_SHARED cvmx_interrupt_state_t cvmx_interrupt_state;
 static CVMX_SHARED cvmx_spinlock_t cvmx_interrupt_default_lock;
+#endif  /* __U_BOOT__ */
 
-#define COP0_CAUSE      "$13,0"
-#define COP0_STATUS     "$12,0"
-#define COP0_BADVADDR   "$8,0"
-#define COP0_EPC        "$14,0"
-#define READ_COP0(dest, R) asm volatile ("dmfc0 %[rt]," R : [rt] "=r" (dest))
 #define ULL unsigned long long
 
+#define HI32(data64)	((uint32_t)(data64 >> 32))
+#define LO32(data64)	((uint32_t)(data64 & 0xFFFFFFFF))
 
+static const char reg_names[][32] = { "r0","at","v0","v1","a0","a1","a2","a3",
+                                      "t0","t1","t2","t3","t4","t5","t6","t7",
+                                      "s0","s1","s2","s3","s4","s5", "s6","s7",
+                                      "t8","t9", "k0","k1","gp","sp","s8","ra" };
+
+/**
+ * version of printf that works better in exception context.
+ *
+ * @param format
+ */
+void cvmx_safe_printf(const char *format, ...)
+{
+    char buffer[256];
+    char *ptr = buffer;
+    int count;
+    va_list args;
+
+    va_start(args, format);
+#ifndef __U_BOOT__
+    count = vsnprintf(buffer, sizeof(buffer), format, args);
+#else
+    count = vsprintf(buffer, format, args);
+#endif
+    va_end(args);
+
+    while (count-- > 0)
+    {
+        cvmx_uart_lsr_t lsrval;
+
+        /* Spin until there is room */
+        do
+        {
+            lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
+#if !defined(CONFIG_OCTEON_SIM_SPEED)
+            if (lsrval.s.temt == 0)
+                cvmx_wait(10000);   /* Just to reduce the load on the system */
+#endif
+        }
+        while (lsrval.s.temt == 0);
+
+        if (*ptr == '\n')
+            cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
+        cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
+    }
+}
+
+/* Textual descriptions of cause codes */
+static const char cause_names[][128] = {
+        /*  0 */ "Interrupt",
+        /*  1 */ "TLB modification",
+        /*  2 */ "tlb load/fetch",
+        /*  3 */ "tlb store",
+        /*  4 */ "address exc, load/fetch",
+        /*  5 */ "address exc, store",
+        /*  6 */ "bus error, instruction fetch",
+        /*  7 */ "bus error, load/store",
+        /*  8 */ "syscall",
+        /*  9 */ "breakpoint",
+        /* 10 */ "reserved instruction",
+        /* 11 */ "cop unusable",
+        /* 12 */ "arithmetic overflow",
+        /* 13 */ "trap",
+        /* 14 */ "",
+        /* 15 */ "floating point exc",
+        /* 16 */ "",
+        /* 17 */ "",
+        /* 18 */ "cop2 exception",
+        /* 19 */ "",
+        /* 20 */ "",
+        /* 21 */ "",
+        /* 22 */ "mdmx unusable",
+        /* 23 */ "watch",
+        /* 24 */ "machine check",
+        /* 25 */ "",
+        /* 26 */ "",
+        /* 27 */ "",
+        /* 28 */ "",
+        /* 29 */ "",
+        /* 30 */ "cache error",
+        /* 31 */ ""
+};
+
+/**
+ * @INTERNAL
+ * print_reg64
+ * @param name   Name of the value to print
+ * @param reg    Value to print
+ */
+static inline void print_reg64(const char *name, uint64_t reg)
+{
+    cvmx_safe_printf("%16s: 0x%08x%08x\n", name, (unsigned int)HI32(reg),(unsigned int)LO32(reg));
+}
 
 /**
  * @INTERNAL
@@ -99,26 +199,25 @@ static CVMX_SHARED cvmx_spinlock_t cvmx_interrupt_default_lock;
  */
 static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
 {
-    static const char *name[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
-        "t0","t1","t2","t3","t4","t5","t6","t7","s0","s1","s2","s3","s4","s5",
-        "s6","s7", "t8","t9", "k0","k1","gp","sp","s8","ra"};
-    uint64_t reg;
+    uint64_t r1, r2;
+    int reg;
     for (reg=0; reg<16; reg++)
     {
-        cvmx_safe_printf("%3s ($%02d): 0x%016llx \t %3s ($%02d): 0x%016llx\n",
-               name[reg], (int)reg, (ULL)registers[reg], name[reg+16], (int)reg+16, (ULL)registers[reg+16]);
+        r1 = registers[reg]; r2 = registers[reg+16];
+        cvmx_safe_printf("%3s ($%02d): 0x%08x%08x \t %3s ($%02d): 0x%08x%08x\n",
+                           reg_names[reg], reg, (unsigned int)HI32(r1), (unsigned int)LO32(r1),
+                           reg_names[reg+16], reg+16, (unsigned int)HI32(r2), (unsigned int)LO32(r2));
     }
-    READ_COP0(reg, COP0_CAUSE);
-    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_CAUSE", (ULL)reg);
-    READ_COP0(reg, COP0_STATUS);
-    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_STATUS", (ULL)reg);
-    READ_COP0(reg, COP0_BADVADDR);
-    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_BADVADDR", (ULL)reg);
-    READ_COP0(reg, COP0_EPC);
-    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_EPC", (ULL)reg);
+    CVMX_MF_COP0 (r1, COP0_CAUSE);
+    print_reg64 ("COP0_CAUSE", r1);
+    CVMX_MF_COP0 (r2, COP0_STATUS);
+    print_reg64 ("COP0_STATUS", r2);
+    CVMX_MF_COP0 (r1, COP0_BADVADDR);
+    print_reg64 ("COP0_BADVADDR", r1);
+    CVMX_MF_COP0 (r2, COP0_EPC);
+    print_reg64 ("COP0_EPC", r2);
 }
 
-
 /**
  * @INTERNAL
  * Default exception handler. Prints out the exception
@@ -126,87 +225,27 @@ static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
  *
  * @param registers Registers at time of the exception
  */
-static void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
+#ifndef __U_BOOT__
+static
+#endif  /* __U_BOOT__ */
+void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
 {
     uint64_t trap_print_cause;
+    const char *str;
 
+#ifndef __U_BOOT__
     ebt3000_str_write("Trap");
     cvmx_spinlock_lock(&cvmx_interrupt_default_lock);
+#endif
+    CVMX_MF_COP0 (trap_print_cause, COP0_CAUSE);
+    str = cause_names [(trap_print_cause >> 2) & 0x1f];
+    cvmx_safe_printf("Core %d: Unhandled Exception. Cause register decodes to:\n%s\n", (int)cvmx_get_core_num(), str && *str ? str : "Reserved exception cause");
     cvmx_safe_printf("******************************************************************\n");
-    cvmx_safe_printf("Core %d: Unhandled Exception. Cause register decodes to:\n", (int)cvmx_get_core_num());
-    READ_COP0(trap_print_cause, COP0_CAUSE);
-    switch ((trap_print_cause >> 2) & 0x1f)
-    {
-        case 0x0:
-            cvmx_safe_printf("Interrupt\n");
-            break;
-        case 0x1:
-            cvmx_safe_printf("TLB Mod\n");
-            break;
-        case 0x2:
-            cvmx_safe_printf("tlb load/fetch\n");
-            break;
-        case 0x3:
-            cvmx_safe_printf("tlb store\n");
-            break;
-        case 0x4:
-            cvmx_safe_printf("address exc, load/fetch\n");
-            break;
-        case 0x5:
-            cvmx_safe_printf("address exc, store\n");
-            break;
-        case 0x6:
-            cvmx_safe_printf("bus error, inst. fetch\n");
-            break;
-        case 0x7:
-            cvmx_safe_printf("bus error, load/store\n");
-            break;
-        case 0x8:
-            cvmx_safe_printf("syscall\n");
-            break;
-        case 0x9:
-            cvmx_safe_printf("breakpoint \n");
-            break;
-        case 0xa:
-            cvmx_safe_printf("reserved instruction\n");
-            break;
-        case 0xb:
-            cvmx_safe_printf("cop unusable\n");
-            break;
-        case 0xc:
-            cvmx_safe_printf("arithmetic overflow\n");
-            break;
-        case 0xd:
-            cvmx_safe_printf("trap\n");
-            break;
-        case 0xf:
-            cvmx_safe_printf("floating point exc\n");
-            break;
-        case 0x12:
-            cvmx_safe_printf("cop2 exception\n");
-            break;
-        case 0x16:
-            cvmx_safe_printf("mdmx unusable\n");
-            break;
-        case 0x17:
-            cvmx_safe_printf("watch\n");
-            break;
-        case 0x18:
-            cvmx_safe_printf("machine check\n");
-            break;
-        case 0x1e:
-            cvmx_safe_printf("cache error\n");
-            break;
-        default:
-            cvmx_safe_printf("Reserved exception cause.\n");
-            break;
+    __cvmx_interrupt_dump_registers(registers);
 
-    }
+#ifndef __U_BOOT__
 
     cvmx_safe_printf("******************************************************************\n");
-    __cvmx_interrupt_dump_registers(registers);
-    cvmx_safe_printf("******************************************************************\n");
-
 #if __GNUC__ >= 4 && !defined(OCTEON_DISABLE_BACKTRACE)
     cvmx_safe_printf("Backtrace:\n\n");
     __octeon_print_backtrace_func ((__octeon_backtrace_printf_t)cvmx_safe_printf);
@@ -216,7 +255,7 @@ static void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
     cvmx_spinlock_unlock(&cvmx_interrupt_default_lock);
 
     if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
-      CVMX_BREAK;
+	CVMX_BREAK;
 
     while (1)
     {
@@ -230,19 +269,20 @@ static void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
 	    uint64_t tmp;
 	    /* Pulse the MCD0 signal. */
 	    asm volatile (
-		".set push\n"
-		".set noreorder\n"
-		".set mips64\n"
-		"dmfc0 %0, $22\n"
-		"ori   %0, %0, 0x10\n"
-		"dmtc0 %0, $22\n"
-		".set pop\n"
-		: "=r" (tmp));
+	    ".set push\n"
+	    ".set noreorder\n"
+	    ".set mips64\n"
+	    "dmfc0 %0, $22\n"
+	    "ori   %0, %0, 0x10\n"
+	    "dmtc0 %0, $22\n"
+	    ".set pop\n"
+	    : "=r" (tmp));
 	}
     }
+#endif /* __U_BOOT__ */
 }
 
-
+#ifndef __U_BOOT__
 /**
  * @INTERNAL
  * Default interrupt handler if the user doesn't register one.
@@ -313,7 +353,7 @@ static void __cvmx_interrupt_ciu(int irq_number, uint64_t registers[32], void *u
  */
 static void __cvmx_interrupt_ecc(int irq_number, uint64_t registers[32], void *user_arg)
 {
-    cvmx_interrupt_rsl_decode();
+    cvmx_error_poll();
 }
 
 
@@ -333,11 +373,15 @@ void cvmx_interrupt_do_irq(uint64_t registers[35])
     uint64_t        cache_err;
     int             i;
     uint32_t exc_vec;
-
     /* Determine the cause of the interrupt */
     asm volatile ("dmfc0 %0,$13,0" : "=r" (cause));
     asm volatile ("dmfc0 %0,$12,0" : "=r" (status));
-
+    /* In case of exception, clear all interrupts to avoid recursive interrupts.
+       Also clear EXL bit to display the correct PC value. */
+    if ((cause & 0x7c) == 0)
+    {
+        asm volatile ("dmtc0 %0, $12, 0" : : "r" (status & ~(0xff02)));
+    }
     /* The assembly stub at each exception vector saves its address in k1 when
     ** it calls the stage 2 handler.  We use this to compute the exception vector
     ** that brought us here */
@@ -371,25 +415,31 @@ void cvmx_interrupt_do_irq(uint64_t registers[35])
     if ((cause & 0x7c) != 0)
     {
         cvmx_interrupt_state.exception_handler(registers);
-        return;
+        goto return_from_interrupt;
     }
 
     /* Convert the cause into an active mask */
     mask = ((cause & status) >> 8) & 0xff;
     if (mask == 0)
-        return; /* Spurious interrupt */
+    {
+        goto return_from_interrupt; /* Spurious interrupt */
+    }
 
     for (i=0; i<8; i++)
     {
         if (mask & (1<<i))
         {
             cvmx_interrupt_state.handlers[i](i, registers, cvmx_interrupt_state.data[i]);
-            return;
+            goto return_from_interrupt;
         }
     }
 
     /* We should never get here */
     __cvmx_interrupt_default_exception_handler(registers);
+
+return_from_interrupt:
+    /* Restore Status register before returning from exception. */
+    asm volatile ("dmtc0 %0, $12, 0" : : "r" (status));
 }
 
 
@@ -425,6 +475,7 @@ void cvmx_interrupt_initialize(void)
         memcpy(low_level_loc + 0x100, (void*)cvmx_interrupt_cache_error, 0x80);
         memcpy(low_level_loc + 0x180, (void*)cvmx_interrupt_stage1, 0x80);
         memcpy(low_level_loc + 0x200, (void*)cvmx_interrupt_stage1, 0x80);
+
         /* Make sure the locations used to count Icache and Dcache exceptions
             starts out as zero */
         cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 8), 0);
@@ -439,7 +490,8 @@ void cvmx_interrupt_initialize(void)
         /* Add an interrupt handler for ECC failures */
         cvmx_interrupt_register(CVMX_IRQ_RML, __cvmx_interrupt_ecc, NULL);
 
-        cvmx_interrupt_rsl_enable();
+        if (cvmx_error_initialize(0 /* || CVMX_ERROR_FLAGS_ECC_SINGLE_BIT */))
+            cvmx_warn("cvmx_error_initialize() failed\n");
         cvmx_interrupt_unmask_irq(CVMX_IRQ_RML);
     }
 
@@ -486,43 +538,6 @@ cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception
     CVMX_SYNCWS;
     return result;
 }
-
-
-/**
- * version of printf that works better in exception context.
- *
- * @param format
- */
-void cvmx_safe_printf(const char *format, ...)
-{
-    static char buffer[256];
-    va_list args;
-    va_start(args, format);
-    int count = vsnprintf(buffer, sizeof(buffer), format, args);
-    va_end(args);
-
-    char *ptr = buffer;
-    while (count-- > 0)
-    {
-        cvmx_uart_lsr_t lsrval;
-
-        /* Spin until there is room */
-        do
-        {
-            lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
-            if (lsrval.s.temt == 0)
-                cvmx_wait(10000);   /* Just to reduce the load on the system */
-        }
-        while (lsrval.s.temt == 0);
-
-        if (*ptr == '\n')
-            cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
-        cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
-    }
-}
-
-
-
-
+#endif /* !__U_BOOT__ */
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-interrupt.h b/sys/contrib/octeon-sdk/cvmx-interrupt.h
index 0683d6e..c3275c3 100644
--- a/sys/contrib/octeon-sdk/cvmx-interrupt.h
+++ b/sys/contrib/octeon-sdk/cvmx-interrupt.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the Mips interrupts.
  *
- * <hr>$Revision: 42203 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #ifndef __CVMX_INTERRUPT_H__
 #define __CVMX_INTERRUPT_H__
@@ -120,16 +122,16 @@ typedef enum
     CVMX_IRQ_RML        = 54,
     CVMX_IRQ_TRACE      = 55,
     CVMX_IRQ_GMX_DRP0   = 56,
-    CVMX_IRQ_GMX_DRP1   = 57,
+    CVMX_IRQ_GMX_DRP1   = 57,   /* Doesn't apply on CN52XX or CN63XX */
     CVMX_IRQ_IPD_DRP    = 58,
-    CVMX_IRQ_KEY_ZERO   = 59,
+    CVMX_IRQ_KEY_ZERO   = 59,   /* Doesn't apply on CN52XX or CN63XX */
     CVMX_IRQ_TIMER0     = 60,
     CVMX_IRQ_TIMER1     = 61,
     CVMX_IRQ_TIMER2     = 62,
     CVMX_IRQ_TIMER3     = 63,
-    CVMX_IRQ_USB        = 64,   /* Doesn't apply on CN38XX or CN58XX */
-    CVMX_IRQ_PCM        = 65,
-    CVMX_IRQ_MPI        = 66,
+    CVMX_IRQ_USB0       = 64,   /* Doesn't apply on CN38XX or CN58XX */
+    CVMX_IRQ_PCM        = 65,   /* Doesn't apply on CN52XX or CN63XX */
+    CVMX_IRQ_MPI        = 66,   /* Doesn't apply on CN52XX or CN63XX */
     CVMX_IRQ_TWSI2      = 67,   /* Added in CN56XX */
     CVMX_IRQ_POWIQ      = 68,   /* Added in CN56XX */
     CVMX_IRQ_IPDPPTHR   = 69,   /* Added in CN56XX */
@@ -152,8 +154,39 @@ typedef enum
     CVMX_IRQ_WDOG12= 84,
     CVMX_IRQ_WDOG13= 85,
     CVMX_IRQ_WDOG14= 86,
-    CVMX_IRQ_WDOG15= 87
-    /* numbers 88 - 135 are reserved */
+    CVMX_IRQ_WDOG15= 87,
+    CVMX_IRQ_UART2 = 88,           /* Added in CN52XX */
+    CVMX_IRQ_USB1  = 89,           /* Added in CN52XX */
+    CVMX_IRQ_MII1  = 90,           /* Added in CN52XX */
+    CVMX_IRQ_NAND  = 91,           /* Added in CN52XX */
+    CVMX_IRQ_MIO   = 92,           /* Added in CN63XX */
+    CVMX_IRQ_IOB   = 93,           /* Added in CN63XX */
+    CVMX_IRQ_FPA   = 94,           /* Added in CN63XX */
+    CVMX_IRQ_POW   = 95,           /* Added in CN63XX */
+    CVMX_IRQ_L2C   = 96,           /* Added in CN63XX */
+    CVMX_IRQ_IPD   = 97,           /* Added in CN63XX */
+    CVMX_IRQ_PIP   = 98,           /* Added in CN63XX */
+    CVMX_IRQ_PKO   = 99,           /* Added in CN63XX */
+    CVMX_IRQ_ZIP   = 100,          /* Added in CN63XX */
+    CVMX_IRQ_TIM   = 101,          /* Added in CN63XX */
+    CVMX_IRQ_RAD   = 102,          /* Added in CN63XX */
+    CVMX_IRQ_KEY   = 103,          /* Added in CN63XX */
+    CVMX_IRQ_DFA   = 104,          /* Added in CN63XX */
+    CVMX_IRQ_USB   = 105,          /* Added in CN63XX */
+    CVMX_IRQ_SLI   = 106,          /* Added in CN63XX */
+    CVMX_IRQ_DPI   = 107,          /* Added in CN63XX */
+    CVMX_IRQ_AGX0  = 108,          /* Added in CN63XX */
+    /* 109 - 117 are reserved */
+    CVMX_IRQ_AGL   = 118,          /* Added in CN63XX */
+    CVMX_IRQ_PTP   = 119,          /* Added in CN63XX */
+    CVMX_IRQ_PEM0  = 120,          /* Added in CN63XX */
+    CVMX_IRQ_PEM1  = 121,          /* Added in CN63XX */
+    CVMX_IRQ_SRIO0 = 122,          /* Added in CN63XX */
+    CVMX_IRQ_SRIO1 = 123,          /* Added in CN63XX */
+    CVMX_IRQ_LMC0  = 124,          /* Added in CN63XX */
+    /* Interrupts 125 - 127 are reserved */
+    CVMX_IRQ_DFM   = 128,          /* Added in CN63XX */
+    /* Interrupts 129 - 135 are reserved */
 } cvmx_irq_t;
 
 /**
@@ -278,19 +311,11 @@ static inline void cvmx_interrupt_restore(uint32_t flags)
     }
 }
 
-/**
- * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
- * into error messages.
- */
-extern void cvmx_interrupt_rsl_decode(void);
-
-/**
- * Utility function to enable all RSL error interupts
- */
-extern void cvmx_interrupt_rsl_enable(void);
+#define cvmx_local_irq_save(x) ({x = cvmx_interrupt_disable_save();})
+#define cvmx_local_irq_restore(x) cvmx_interrupt_restore(x)
 
 /**
- * Utility function to do interrupt safe printf 
+ * Utility function to do interrupt safe printf
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 	#define cvmx_safe_printf printk
@@ -298,7 +323,10 @@ extern void cvmx_interrupt_rsl_enable(void);
 	#define cvmx_safe_printf printf
 #else
 	extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
-#endif 
+#endif
+
+#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-iob-defs.h b/sys/contrib/octeon-sdk/cvmx-iob-defs.h
new file mode 100644
index 0000000..bb669f8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-iob-defs.h
@@ -0,0 +1,1307 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-iob-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon iob.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_IOB_TYPEDEFS_H__
+#define __CVMX_IOB_TYPEDEFS_H__
+
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
+}
+#else
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#endif
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
+}
+#else
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#endif
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
+}
+#else
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
+}
+#else
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
+}
+#else
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#endif
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
+}
+#else
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
+}
+#else
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
+}
+#else
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#endif
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
+}
+#else
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
+#endif
+
+/**
+ * cvmx_iob_bist_status
+ *
+ * IOB_BIST_STATUS = BIST Status of IOB Memories
+ *
+ * The result of the BIST run on the IOB memories.
+ */
+union cvmx_iob_bist_status
+{
+	uint64_t u64;
+	struct cvmx_iob_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t xmdfif                       : 1;  /**< xmdfif_bist_status */
+	uint64_t xmcfif                       : 1;  /**< xmcfif_bist_status */
+	uint64_t iorfif                       : 1;  /**< iorfif_bist_status */
+	uint64_t rsdfif                       : 1;  /**< rsdfif_bist_status */
+	uint64_t iocfif                       : 1;  /**< iocfif_bist_status */
+	uint64_t icnrcb                       : 1;  /**< icnr_cb_reg_fifo_bist_status */
+	uint64_t icr0                         : 1;  /**< icr_bist_req_fifo0_status */
+	uint64_t icr1                         : 1;  /**< icr_bist_req_fifo1_status */
+	uint64_t icnr1                        : 1;  /**< Reserved */
+	uint64_t icnr0                        : 1;  /**< icnr_reg_mem0_bist_status */
+	uint64_t ibdr0                        : 1;  /**< ibdr_bist_req_fifo0_status */
+	uint64_t ibdr1                        : 1;  /**< ibdr_bist_req_fifo1_status */
+	uint64_t ibr0                         : 1;  /**< ibr_bist_rsp_fifo0_status */
+	uint64_t ibr1                         : 1;  /**< ibr_bist_rsp_fifo1_status */
+	uint64_t icnrt                        : 1;  /**< icnr_tag_cb_reg_fifo_bist_status */
+	uint64_t ibrq0                        : 1;  /**< ibrq_bist_req_fifo0_status */
+	uint64_t ibrq1                        : 1;  /**< ibrq_bist_req_fifo1_status */
+	uint64_t icrn0                        : 1;  /**< icr_ncb_bist_mem0_status */
+	uint64_t icrn1                        : 1;  /**< icr_ncb_bist_mem1_status */
+	uint64_t icrp0                        : 1;  /**< icr_pko_bist_mem0_status */
+	uint64_t icrp1                        : 1;  /**< icr_pko_bist_mem1_status */
+	uint64_t ibd                          : 1;  /**< ibd_bist_mem0_status */
+	uint64_t icd                          : 1;  /**< icd_ncb_fifo_bist_status */
+#else
+	uint64_t icd                          : 1;
+	uint64_t ibd                          : 1;
+	uint64_t icrp1                        : 1;
+	uint64_t icrp0                        : 1;
+	uint64_t icrn1                        : 1;
+	uint64_t icrn0                        : 1;
+	uint64_t ibrq1                        : 1;
+	uint64_t ibrq0                        : 1;
+	uint64_t icnrt                        : 1;
+	uint64_t ibr1                         : 1;
+	uint64_t ibr0                         : 1;
+	uint64_t ibdr1                        : 1;
+	uint64_t ibdr0                        : 1;
+	uint64_t icnr0                        : 1;
+	uint64_t icnr1                        : 1;
+	uint64_t icr1                         : 1;
+	uint64_t icr0                         : 1;
+	uint64_t icnrcb                       : 1;
+	uint64_t iocfif                       : 1;
+	uint64_t rsdfif                       : 1;
+	uint64_t iorfif                       : 1;
+	uint64_t xmcfif                       : 1;
+	uint64_t xmdfif                       : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_iob_bist_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t icnrcb                       : 1;  /**< Reserved */
+	uint64_t icr0                         : 1;  /**< Reserved */
+	uint64_t icr1                         : 1;  /**< Reserved */
+	uint64_t icnr1                        : 1;  /**< Reserved */
+	uint64_t icnr0                        : 1;  /**< icnr_reg_mem0_bist_status */
+	uint64_t ibdr0                        : 1;  /**< ibdr_bist_req_fifo0_status */
+	uint64_t ibdr1                        : 1;  /**< ibdr_bist_req_fifo1_status */
+	uint64_t ibr0                         : 1;  /**< ibr_bist_rsp_fifo0_status */
+	uint64_t ibr1                         : 1;  /**< ibr_bist_rsp_fifo1_status */
+	uint64_t icnrt                        : 1;  /**< Reserved */
+	uint64_t ibrq0                        : 1;  /**< ibrq_bist_req_fifo0_status */
+	uint64_t ibrq1                        : 1;  /**< ibrq_bist_req_fifo1_status */
+	uint64_t icrn0                        : 1;  /**< icr_ncb_bist_mem0_status */
+	uint64_t icrn1                        : 1;  /**< icr_ncb_bist_mem1_status */
+	uint64_t icrp0                        : 1;  /**< icr_pko_bist_mem0_status */
+	uint64_t icrp1                        : 1;  /**< icr_pko_bist_mem1_status */
+	uint64_t ibd                          : 1;  /**< ibd_bist_mem0_status */
+	uint64_t icd                          : 1;  /**< icd_ncb_fifo_bist_status */
+#else
+	uint64_t icd                          : 1;
+	uint64_t ibd                          : 1;
+	uint64_t icrp1                        : 1;
+	uint64_t icrp0                        : 1;
+	uint64_t icrn1                        : 1;
+	uint64_t icrn0                        : 1;
+	uint64_t ibrq1                        : 1;
+	uint64_t ibrq0                        : 1;
+	uint64_t icnrt                        : 1;
+	uint64_t ibr1                         : 1;
+	uint64_t ibr0                         : 1;
+	uint64_t ibdr1                        : 1;
+	uint64_t ibdr0                        : 1;
+	uint64_t icnr0                        : 1;
+	uint64_t icnr1                        : 1;
+	uint64_t icr1                         : 1;
+	uint64_t icr0                         : 1;
+	uint64_t icnrcb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn30xx;
+	struct cvmx_iob_bist_status_cn30xx    cn31xx;
+	struct cvmx_iob_bist_status_cn30xx    cn38xx;
+	struct cvmx_iob_bist_status_cn30xx    cn38xxp2;
+	struct cvmx_iob_bist_status_cn30xx    cn50xx;
+	struct cvmx_iob_bist_status_cn30xx    cn52xx;
+	struct cvmx_iob_bist_status_cn30xx    cn52xxp1;
+	struct cvmx_iob_bist_status_cn30xx    cn56xx;
+	struct cvmx_iob_bist_status_cn30xx    cn56xxp1;
+	struct cvmx_iob_bist_status_cn30xx    cn58xx;
+	struct cvmx_iob_bist_status_cn30xx    cn58xxp1;
+	struct cvmx_iob_bist_status_s         cn63xx;
+	struct cvmx_iob_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_iob_bist_status cvmx_iob_bist_status_t;
+
+/**
+ * cvmx_iob_ctl_status
+ *
+ * IOB Control Status = IOB Control and Status Register
+ *
+ * Provides control for IOB functions.
+ */
+union cvmx_iob_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_iob_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t xmc_per                      : 4;  /**< IBC XMC PUSH EARLY */
+	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
+                                                         transaction that could arbitrate for the XMB. */
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t rr_mode                      : 1;
+	uint64_t xmc_per                      : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_iob_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn30xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn31xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn38xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn38xxp2;
+	struct cvmx_iob_ctl_status_cn30xx     cn50xx;
+	struct cvmx_iob_ctl_status_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t rr_mode                      : 1;  /**< When set to '1' will enable Round-Robin mode of next
+                                                         transaction that could arbitrate for the XMB. */
+	uint64_t outb_mat                     : 1;  /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t inb_mat                      : 1;  /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+	uint64_t pko_enb                      : 1;  /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+	uint64_t dwb_enb                      : 1;  /**< Enables the DWB function of the IOB. */
+	uint64_t fau_end                      : 1;  /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+	uint64_t fau_end                      : 1;
+	uint64_t dwb_enb                      : 1;
+	uint64_t pko_enb                      : 1;
+	uint64_t inb_mat                      : 1;
+	uint64_t outb_mat                     : 1;
+	uint64_t rr_mode                      : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn52xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn52xxp1;
+	struct cvmx_iob_ctl_status_cn30xx     cn56xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn56xxp1;
+	struct cvmx_iob_ctl_status_cn30xx     cn58xx;
+	struct cvmx_iob_ctl_status_cn30xx     cn58xxp1;
+	struct cvmx_iob_ctl_status_s          cn63xx;
+	struct cvmx_iob_ctl_status_s          cn63xxp1;
+};
+typedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t;
+
+/**
+ * cvmx_iob_dwb_pri_cnt
+ *
+ * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
+ */
+union cvmx_iob_dwb_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_dwb_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_dwb_pri_cnt_s         cn38xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cn38xxp2;
+	struct cvmx_iob_dwb_pri_cnt_s         cn52xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cn52xxp1;
+	struct cvmx_iob_dwb_pri_cnt_s         cn56xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cn56xxp1;
+	struct cvmx_iob_dwb_pri_cnt_s         cn58xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cn58xxp1;
+	struct cvmx_iob_dwb_pri_cnt_s         cn63xx;
+	struct cvmx_iob_dwb_pri_cnt_s         cn63xxp1;
+};
+typedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t;
+
+/**
+ * cvmx_iob_fau_timeout
+ *
+ * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout
+ *
+ * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
+ * for Queue 0.
+ */
+union cvmx_iob_fau_timeout
+{
+	uint64_t u64;
+	struct cvmx_iob_fau_timeout_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t tout_enb                     : 1;  /**< The enable for the FAU timeout feature.
+                                                         '1' will enable the timeout, '0' will disable. */
+	uint64_t tout_val                     : 12; /**< When a tag request arrives from the PP a timer is
+                                                         started associate with that PP. The timer which
+                                                         increments every 256 eclks is compared to TOUT_VAL.
+                                                         When the two are equal the IOB will flag the tag
+                                                         request to complete as a time-out tag operation.
+                                                         The 256 count timer used to increment the PP
+                                                         associated timer is always running so the first
+                                                         increment of the PP associated timer may occur any
+                                                         where within the first 256 eclks.  Note that '0'
+                                                         is an illegal value. */
+#else
+	uint64_t tout_val                     : 12;
+	uint64_t tout_enb                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_iob_fau_timeout_s         cn30xx;
+	struct cvmx_iob_fau_timeout_s         cn31xx;
+	struct cvmx_iob_fau_timeout_s         cn38xx;
+	struct cvmx_iob_fau_timeout_s         cn38xxp2;
+	struct cvmx_iob_fau_timeout_s         cn50xx;
+	struct cvmx_iob_fau_timeout_s         cn52xx;
+	struct cvmx_iob_fau_timeout_s         cn52xxp1;
+	struct cvmx_iob_fau_timeout_s         cn56xx;
+	struct cvmx_iob_fau_timeout_s         cn56xxp1;
+	struct cvmx_iob_fau_timeout_s         cn58xx;
+	struct cvmx_iob_fau_timeout_s         cn58xxp1;
+	struct cvmx_iob_fau_timeout_s         cn63xx;
+	struct cvmx_iob_fau_timeout_s         cn63xxp1;
+};
+typedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t;
+
+/**
+ * cvmx_iob_i2c_pri_cnt
+ *
+ * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
+ */
+union cvmx_iob_i2c_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_i2c_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_i2c_pri_cnt_s         cn38xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cn38xxp2;
+	struct cvmx_iob_i2c_pri_cnt_s         cn52xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cn52xxp1;
+	struct cvmx_iob_i2c_pri_cnt_s         cn56xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cn56xxp1;
+	struct cvmx_iob_i2c_pri_cnt_s         cn58xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cn58xxp1;
+	struct cvmx_iob_i2c_pri_cnt_s         cn63xx;
+	struct cvmx_iob_i2c_pri_cnt_s         cn63xxp1;
+};
+typedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t;
+
+/**
+ * cvmx_iob_inb_control_match
+ *
+ * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match
+ *
+ * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
+ */
+union cvmx_iob_inb_control_match
+{
+	uint64_t u64;
+	struct cvmx_iob_inb_control_match_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t mask                         : 8;  /**< Pattern to match on the inbound NCB. */
+	uint64_t opc                          : 4;  /**< Pattern to match on the inbound NCB. */
+	uint64_t dst                          : 9;  /**< Pattern to match on the inbound NCB. */
+	uint64_t src                          : 8;  /**< Pattern to match on the inbound NCB. */
+#else
+	uint64_t src                          : 8;
+	uint64_t dst                          : 9;
+	uint64_t opc                          : 4;
+	uint64_t mask                         : 8;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_iob_inb_control_match_s   cn30xx;
+	struct cvmx_iob_inb_control_match_s   cn31xx;
+	struct cvmx_iob_inb_control_match_s   cn38xx;
+	struct cvmx_iob_inb_control_match_s   cn38xxp2;
+	struct cvmx_iob_inb_control_match_s   cn50xx;
+	struct cvmx_iob_inb_control_match_s   cn52xx;
+	struct cvmx_iob_inb_control_match_s   cn52xxp1;
+	struct cvmx_iob_inb_control_match_s   cn56xx;
+	struct cvmx_iob_inb_control_match_s   cn56xxp1;
+	struct cvmx_iob_inb_control_match_s   cn58xx;
+	struct cvmx_iob_inb_control_match_s   cn58xxp1;
+	struct cvmx_iob_inb_control_match_s   cn63xx;
+	struct cvmx_iob_inb_control_match_s   cn63xxp1;
+};
+typedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t;
+
+/**
+ * cvmx_iob_inb_control_match_enb
+ *
+ * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable
+ *
+ * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
+ */
+union cvmx_iob_inb_control_match_enb
+{
+	uint64_t u64;
+	struct cvmx_iob_inb_control_match_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t mask                         : 8;  /**< Pattern to match on the inbound NCB. */
+	uint64_t opc                          : 4;  /**< Pattern to match on the inbound NCB. */
+	uint64_t dst                          : 9;  /**< Pattern to match on the inbound NCB. */
+	uint64_t src                          : 8;  /**< Pattern to match on the inbound NCB. */
+#else
+	uint64_t src                          : 8;
+	uint64_t dst                          : 9;
+	uint64_t opc                          : 4;
+	uint64_t mask                         : 8;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_iob_inb_control_match_enb_s cn30xx;
+	struct cvmx_iob_inb_control_match_enb_s cn31xx;
+	struct cvmx_iob_inb_control_match_enb_s cn38xx;
+	struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
+	struct cvmx_iob_inb_control_match_enb_s cn50xx;
+	struct cvmx_iob_inb_control_match_enb_s cn52xx;
+	struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cn56xx;
+	struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cn58xx;
+	struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+	struct cvmx_iob_inb_control_match_enb_s cn63xx;
+	struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
+};
+typedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t;
+
+/**
+ * cvmx_iob_inb_data_match
+ *
+ * IOB_INB_DATA_MATCH = IOB Inbound Data Match
+ *
+ * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
+ */
+union cvmx_iob_inb_data_match
+{
+	uint64_t u64;
+	struct cvmx_iob_inb_data_match_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Pattern to match on the inbound NCB. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_iob_inb_data_match_s      cn30xx;
+	struct cvmx_iob_inb_data_match_s      cn31xx;
+	struct cvmx_iob_inb_data_match_s      cn38xx;
+	struct cvmx_iob_inb_data_match_s      cn38xxp2;
+	struct cvmx_iob_inb_data_match_s      cn50xx;
+	struct cvmx_iob_inb_data_match_s      cn52xx;
+	struct cvmx_iob_inb_data_match_s      cn52xxp1;
+	struct cvmx_iob_inb_data_match_s      cn56xx;
+	struct cvmx_iob_inb_data_match_s      cn56xxp1;
+	struct cvmx_iob_inb_data_match_s      cn58xx;
+	struct cvmx_iob_inb_data_match_s      cn58xxp1;
+	struct cvmx_iob_inb_data_match_s      cn63xx;
+	struct cvmx_iob_inb_data_match_s      cn63xxp1;
+};
+typedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t;
+
+/**
+ * cvmx_iob_inb_data_match_enb
+ *
+ * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable
+ *
+ * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
+ */
+union cvmx_iob_inb_data_match_enb
+{
+	uint64_t u64;
+	struct cvmx_iob_inb_data_match_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Bit to enable match of. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_iob_inb_data_match_enb_s  cn30xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn31xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn38xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn38xxp2;
+	struct cvmx_iob_inb_data_match_enb_s  cn50xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn52xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn52xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cn56xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn56xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cn58xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn58xxp1;
+	struct cvmx_iob_inb_data_match_enb_s  cn63xx;
+	struct cvmx_iob_inb_data_match_enb_s  cn63xxp1;
+};
+typedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t;
+
+/**
+ * cvmx_iob_int_enb
+ *
+ * IOB_INT_ENB = IOB's Interrupt Enable
+ *
+ * The IOB's interrupt enable register. This is a PASS-2 register.
+ */
+union cvmx_iob_int_enb
+{
+	uint64_t u64;
+	struct cvmx_iob_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t p_dat                        : 1;  /**< When set (1) and bit 5 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t np_dat                       : 1;  /**< When set (1) and bit 4 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t p_eop                        : 1;  /**< When set (1) and bit 3 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t p_sop                        : 1;  /**< When set (1) and bit 2 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t np_eop                       : 1;  /**< When set (1) and bit 1 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t np_sop                       : 1;  /**< When set (1) and bit 0 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+#else
+	uint64_t np_sop                       : 1;
+	uint64_t np_eop                       : 1;
+	uint64_t p_sop                        : 1;
+	uint64_t p_eop                        : 1;
+	uint64_t np_dat                       : 1;
+	uint64_t p_dat                        : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_iob_int_enb_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t p_eop                        : 1;  /**< When set (1) and bit 3 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t p_sop                        : 1;  /**< When set (1) and bit 2 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t np_eop                       : 1;  /**< When set (1) and bit 1 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+	uint64_t np_sop                       : 1;  /**< When set (1) and bit 0 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+#else
+	uint64_t np_sop                       : 1;
+	uint64_t np_eop                       : 1;
+	uint64_t p_sop                        : 1;
+	uint64_t p_eop                        : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_iob_int_enb_cn30xx        cn31xx;
+	struct cvmx_iob_int_enb_cn30xx        cn38xx;
+	struct cvmx_iob_int_enb_cn30xx        cn38xxp2;
+	struct cvmx_iob_int_enb_s             cn50xx;
+	struct cvmx_iob_int_enb_s             cn52xx;
+	struct cvmx_iob_int_enb_s             cn52xxp1;
+	struct cvmx_iob_int_enb_s             cn56xx;
+	struct cvmx_iob_int_enb_s             cn56xxp1;
+	struct cvmx_iob_int_enb_s             cn58xx;
+	struct cvmx_iob_int_enb_s             cn58xxp1;
+	struct cvmx_iob_int_enb_s             cn63xx;
+	struct cvmx_iob_int_enb_s             cn63xxp1;
+};
+typedef union cvmx_iob_int_enb cvmx_iob_int_enb_t;
+
+/**
+ * cvmx_iob_int_sum
+ *
+ * IOB_INT_SUM = IOB's Interrupt Summary Register
+ *
+ * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
+ */
+union cvmx_iob_int_sum
+{
+	uint64_t u64;
+	struct cvmx_iob_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t p_dat                        : 1;  /**< Set when a data arrives before a SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t np_dat                       : 1;  /**< Set when a data arrives before a SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t p_eop                        : 1;  /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t p_sop                        : 1;  /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t np_eop                       : 1;  /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t np_sop                       : 1;  /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+#else
+	uint64_t np_sop                       : 1;
+	uint64_t np_eop                       : 1;
+	uint64_t p_sop                        : 1;
+	uint64_t p_eop                        : 1;
+	uint64_t np_dat                       : 1;
+	uint64_t p_dat                        : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_iob_int_sum_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t p_eop                        : 1;  /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t p_sop                        : 1;  /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t np_eop                       : 1;  /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+	uint64_t np_sop                       : 1;  /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+#else
+	uint64_t np_sop                       : 1;
+	uint64_t np_eop                       : 1;
+	uint64_t p_sop                        : 1;
+	uint64_t p_eop                        : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_iob_int_sum_cn30xx        cn31xx;
+	struct cvmx_iob_int_sum_cn30xx        cn38xx;
+	struct cvmx_iob_int_sum_cn30xx        cn38xxp2;
+	struct cvmx_iob_int_sum_s             cn50xx;
+	struct cvmx_iob_int_sum_s             cn52xx;
+	struct cvmx_iob_int_sum_s             cn52xxp1;
+	struct cvmx_iob_int_sum_s             cn56xx;
+	struct cvmx_iob_int_sum_s             cn56xxp1;
+	struct cvmx_iob_int_sum_s             cn58xx;
+	struct cvmx_iob_int_sum_s             cn58xxp1;
+	struct cvmx_iob_int_sum_s             cn63xx;
+	struct cvmx_iob_int_sum_s             cn63xxp1;
+};
+typedef union cvmx_iob_int_sum cvmx_iob_int_sum_t;
+
+/**
+ * cvmx_iob_n2c_l2c_pri_cnt
+ *
+ * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
+ */
+union cvmx_iob_n2c_l2c_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn38xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn38xxp2;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn52xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn52xxp1;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn56xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn56xxp1;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn58xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn63xx;
+	struct cvmx_iob_n2c_l2c_pri_cnt_s     cn63xxp1;
+};
+typedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t;
+
+/**
+ * cvmx_iob_n2c_rsp_pri_cnt
+ *
+ * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
+ */
+union cvmx_iob_n2c_rsp_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn38xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn38xxp2;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn52xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn52xxp1;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn56xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn56xxp1;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn58xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn63xx;
+	struct cvmx_iob_n2c_rsp_pri_cnt_s     cn63xxp1;
+};
+typedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t;
+
+/**
+ * cvmx_iob_outb_com_pri_cnt
+ *
+ * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
+ */
+union cvmx_iob_outb_com_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_com_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn38xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn38xxp2;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn52xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn52xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn56xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn56xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn58xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn63xx;
+	struct cvmx_iob_outb_com_pri_cnt_s    cn63xxp1;
+};
+typedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t;
+
+/**
+ * cvmx_iob_outb_control_match
+ *
+ * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match
+ *
+ * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
+ */
+union cvmx_iob_outb_control_match
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_control_match_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t mask                         : 8;  /**< Pattern to match on the outbound NCB. */
+	uint64_t eot                          : 1;  /**< Pattern to match on the outbound NCB. */
+	uint64_t dst                          : 8;  /**< Pattern to match on the outbound NCB. */
+	uint64_t src                          : 9;  /**< Pattern to match on the outbound NCB. */
+#else
+	uint64_t src                          : 9;
+	uint64_t dst                          : 8;
+	uint64_t eot                          : 1;
+	uint64_t mask                         : 8;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_iob_outb_control_match_s  cn30xx;
+	struct cvmx_iob_outb_control_match_s  cn31xx;
+	struct cvmx_iob_outb_control_match_s  cn38xx;
+	struct cvmx_iob_outb_control_match_s  cn38xxp2;
+	struct cvmx_iob_outb_control_match_s  cn50xx;
+	struct cvmx_iob_outb_control_match_s  cn52xx;
+	struct cvmx_iob_outb_control_match_s  cn52xxp1;
+	struct cvmx_iob_outb_control_match_s  cn56xx;
+	struct cvmx_iob_outb_control_match_s  cn56xxp1;
+	struct cvmx_iob_outb_control_match_s  cn58xx;
+	struct cvmx_iob_outb_control_match_s  cn58xxp1;
+	struct cvmx_iob_outb_control_match_s  cn63xx;
+	struct cvmx_iob_outb_control_match_s  cn63xxp1;
+};
+typedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t;
+
+/**
+ * cvmx_iob_outb_control_match_enb
+ *
+ * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable
+ *
+ * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
+ */
+union cvmx_iob_outb_control_match_enb
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_control_match_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t mask                         : 8;  /**< Pattern to match on the outbound NCB. */
+	uint64_t eot                          : 1;  /**< Pattern to match on the outbound NCB. */
+	uint64_t dst                          : 8;  /**< Pattern to match on the outbound NCB. */
+	uint64_t src                          : 9;  /**< Pattern to match on the outbound NCB. */
+#else
+	uint64_t src                          : 9;
+	uint64_t dst                          : 8;
+	uint64_t eot                          : 1;
+	uint64_t mask                         : 8;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_iob_outb_control_match_enb_s cn30xx;
+	struct cvmx_iob_outb_control_match_enb_s cn31xx;
+	struct cvmx_iob_outb_control_match_enb_s cn38xx;
+	struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
+	struct cvmx_iob_outb_control_match_enb_s cn50xx;
+	struct cvmx_iob_outb_control_match_enb_s cn52xx;
+	struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cn56xx;
+	struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cn58xx;
+	struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+	struct cvmx_iob_outb_control_match_enb_s cn63xx;
+	struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
+};
+typedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t;
+
+/**
+ * cvmx_iob_outb_data_match
+ *
+ * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match
+ *
+ * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
+ */
+union cvmx_iob_outb_data_match
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_data_match_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Pattern to match on the outbound NCB. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_iob_outb_data_match_s     cn30xx;
+	struct cvmx_iob_outb_data_match_s     cn31xx;
+	struct cvmx_iob_outb_data_match_s     cn38xx;
+	struct cvmx_iob_outb_data_match_s     cn38xxp2;
+	struct cvmx_iob_outb_data_match_s     cn50xx;
+	struct cvmx_iob_outb_data_match_s     cn52xx;
+	struct cvmx_iob_outb_data_match_s     cn52xxp1;
+	struct cvmx_iob_outb_data_match_s     cn56xx;
+	struct cvmx_iob_outb_data_match_s     cn56xxp1;
+	struct cvmx_iob_outb_data_match_s     cn58xx;
+	struct cvmx_iob_outb_data_match_s     cn58xxp1;
+	struct cvmx_iob_outb_data_match_s     cn63xx;
+	struct cvmx_iob_outb_data_match_s     cn63xxp1;
+};
+typedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t;
+
+/**
+ * cvmx_iob_outb_data_match_enb
+ *
+ * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable
+ *
+ * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
+ */
+union cvmx_iob_outb_data_match_enb
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_data_match_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Bit to enable match of. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_iob_outb_data_match_enb_s cn30xx;
+	struct cvmx_iob_outb_data_match_enb_s cn31xx;
+	struct cvmx_iob_outb_data_match_enb_s cn38xx;
+	struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
+	struct cvmx_iob_outb_data_match_enb_s cn50xx;
+	struct cvmx_iob_outb_data_match_enb_s cn52xx;
+	struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cn56xx;
+	struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cn58xx;
+	struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+	struct cvmx_iob_outb_data_match_enb_s cn63xx;
+	struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
+};
+typedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t;
+
+/**
+ * cvmx_iob_outb_fpa_pri_cnt
+ *
+ * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
+ */
+union cvmx_iob_outb_fpa_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_fpa_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn38xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn38xxp2;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn52xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn52xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn56xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn56xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn58xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn63xx;
+	struct cvmx_iob_outb_fpa_pri_cnt_s    cn63xxp1;
+};
+typedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t;
+
+/**
+ * cvmx_iob_outb_req_pri_cnt
+ *
+ * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
+ */
+union cvmx_iob_outb_req_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_outb_req_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn38xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn38xxp2;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn52xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn52xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn56xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn56xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn58xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn58xxp1;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn63xx;
+	struct cvmx_iob_outb_req_pri_cnt_s    cn63xxp1;
+};
+typedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t;
+
+/**
+ * cvmx_iob_p2c_req_pri_cnt
+ *
+ * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value
+ *
+ * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
+ */
+union cvmx_iob_p2c_req_pri_cnt
+{
+	uint64_t u64;
+	struct cvmx_iob_p2c_req_pri_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt_enb                      : 1;  /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+	uint64_t cnt_val                      : 15; /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+	uint64_t cnt_val                      : 15;
+	uint64_t cnt_enb                      : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn38xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn38xxp2;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn52xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn52xxp1;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn56xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn56xxp1;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn58xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn58xxp1;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn63xx;
+	struct cvmx_iob_p2c_req_pri_cnt_s     cn63xxp1;
+};
+typedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t;
+
+/**
+ * cvmx_iob_pkt_err
+ *
+ * IOB_PKT_ERR = IOB Packet Error Register
+ *
+ * Provides status about the failing packet recevie error. This is a PASS-2 register.
+ */
+union cvmx_iob_pkt_err
+{
+	uint64_t u64;
+	struct cvmx_iob_pkt_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t vport                        : 6;  /**< When IOB_INT_SUM[3:0] bit is set, this field
+                                                         latches the failing vport associate with the
+                                                         IOB_INT_SUM[3:0] bit set. */
+	uint64_t port                         : 6;  /**< When IOB_INT_SUM[3:0] bit is set, this field
+                                                         latches the failing port associate with the
+                                                         IOB_INT_SUM[3:0] bit set. */
+#else
+	uint64_t port                         : 6;
+	uint64_t vport                        : 6;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_iob_pkt_err_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t port                         : 6;  /**< When IOB_INT_SUM[3:0] bit is set, this field
+                                                         latches the failing port associate with the
+                                                         IOB_INT_SUM[3:0] bit set. */
+#else
+	uint64_t port                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn30xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn31xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn38xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn38xxp2;
+	struct cvmx_iob_pkt_err_cn30xx        cn50xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn52xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn52xxp1;
+	struct cvmx_iob_pkt_err_cn30xx        cn56xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn56xxp1;
+	struct cvmx_iob_pkt_err_cn30xx        cn58xx;
+	struct cvmx_iob_pkt_err_cn30xx        cn58xxp1;
+	struct cvmx_iob_pkt_err_s             cn63xx;
+	struct cvmx_iob_pkt_err_s             cn63xxp1;
+};
+typedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t;
+
+/**
+ * cvmx_iob_to_cmb_credits
+ *
+ * IOB_TO_CMB_CREDITS = IOB To CMB Credits
+ *
+ * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
+ */
+union cvmx_iob_to_cmb_credits
+{
+	uint64_t u64;
+	struct cvmx_iob_to_cmb_credits_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t pko_rd                       : 3;  /**< Number of PKO reads that can be out to L2C where
+                                                         0 == 8-credits. */
+	uint64_t ncb_rd                       : 3;  /**< Number of NCB reads that can be out to L2C where
+                                                         0 == 8-credits. */
+	uint64_t ncb_wr                       : 3;  /**< Number of NCB/PKI writes that can be out to L2C
+                                                         where 0 == 8-credits. */
+#else
+	uint64_t ncb_wr                       : 3;
+	uint64_t ncb_rd                       : 3;
+	uint64_t pko_rd                       : 3;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_iob_to_cmb_credits_s      cn52xx;
+	struct cvmx_iob_to_cmb_credits_s      cn63xx;
+	struct cvmx_iob_to_cmb_credits_s      cn63xxp1;
+};
+typedef union cvmx_iob_to_cmb_credits cvmx_iob_to_cmb_credits_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-iob.h b/sys/contrib/octeon-sdk/cvmx-iob.h
deleted file mode 100644
index 7f89711..0000000
--- a/sys/contrib/octeon-sdk/cvmx-iob.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * This file contains defines for the IO bridge
-
- * <hr>$Revision: 41586 $<hr>
- *
- *
- */
-#ifndef __CVMX_IOB_H__
-#define __CVMX_IOB_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif  /* __CVMX_IOB_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-ipd-defs.h b/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
new file mode 100644
index 0000000..a0a4a3e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
@@ -0,0 +1,2458 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-ipd-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon ipd.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_IPD_TYPEDEFS_H__
+#define __CVMX_IPD_TYPEDEFS_H__
+
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36;
+}
+#else
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40;
+}
+#else
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36;
+}
+#else
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40;
+}
+#else
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5)))))
+		cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5)))))
+		cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351))))))
+		cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8;
+}
+#else
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#endif
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
+}
+#else
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#endif
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
+}
+#else
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#endif
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
+
+/**
+ * cvmx_ipd_1st_mbuff_skip
+ *
+ * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size
+ *
+ * The number of words that the IPD will skip when writing the first MBUFF.
+ */
+union cvmx_ipd_1st_mbuff_skip
+{
+	uint64_t u64;
+	struct cvmx_ipd_1st_mbuff_skip_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t skip_sz                      : 6;  /**< The number of 8-byte words from the top of the
+                                                         1st MBUFF that the IPD will store the next-pointer.
+                                                         Legal values are 0 to 32, where the MAX value
+                                                         is also limited to:
+                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18.
+                                                         Must be at least 16 when IPD_CTL_STATUS[NO_WPTR]
+                                                         is set. */
+#else
+	uint64_t skip_sz                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn30xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn31xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn38xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn38xxp2;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn50xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn52xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn52xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn56xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn56xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn58xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn58xxp1;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn63xx;
+	struct cvmx_ipd_1st_mbuff_skip_s      cn63xxp1;
+};
+typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t;
+
+/**
+ * cvmx_ipd_1st_next_ptr_back
+ *
+ * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values
+ *
+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
+ */
+union cvmx_ipd_1st_next_ptr_back
+{
+	uint64_t u64;
+	struct cvmx_ipd_1st_next_ptr_back_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t back                         : 4;  /**< Used to find head of buffer from the nxt-hdr-ptr. */
+#else
+	uint64_t back                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn30xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn31xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn38xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn38xxp2;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn50xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn52xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn52xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn56xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn56xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn58xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn58xxp1;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn63xx;
+	struct cvmx_ipd_1st_next_ptr_back_s   cn63xxp1;
+};
+typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t;
+
+/**
+ * cvmx_ipd_2nd_next_ptr_back
+ *
+ * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value
+ *
+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
+ */
+union cvmx_ipd_2nd_next_ptr_back
+{
+	uint64_t u64;
+	struct cvmx_ipd_2nd_next_ptr_back_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t back                         : 4;  /**< Used to find head of buffer from the nxt-hdr-ptr. */
+#else
+	uint64_t back                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn30xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn31xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn38xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn38xxp2;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn50xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn52xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn52xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn56xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn56xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn58xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn58xxp1;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn63xx;
+	struct cvmx_ipd_2nd_next_ptr_back_s   cn63xxp1;
+};
+typedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t;
+
+/**
+ * cvmx_ipd_bist_status
+ *
+ * IPD_BIST_STATUS = IPD BIST STATUS
+ *
+ * BIST Status for IPD's Memories.
+ */
+union cvmx_ipd_bist_status
+{
+	uint64_t u64;
+	struct cvmx_ipd_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t csr_mem                      : 1;  /**< CSR Register Memory Bist Status. */
+	uint64_t csr_ncmd                     : 1;  /**< CSR NCB Commands Memory Bist Status. */
+	uint64_t pwq_wqed                     : 1;  /**< PWQ PIP WQE DONE Memory Bist Status. */
+	uint64_t pwq_wp1                      : 1;  /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
+	uint64_t pwq_pow                      : 1;  /**< PWQ POW MEM Memory Bist Status. */
+	uint64_t ipq_pbe1                     : 1;  /**< IPQ PBE1 Memory Bist Status. */
+	uint64_t ipq_pbe0                     : 1;  /**< IPQ PBE0 Memory Bist Status. */
+	uint64_t pbm3                         : 1;  /**< PBM3 Memory Bist Status. */
+	uint64_t pbm2                         : 1;  /**< PBM2 Memory Bist Status. */
+	uint64_t pbm1                         : 1;  /**< PBM1 Memory Bist Status. */
+	uint64_t pbm0                         : 1;  /**< PBM0 Memory Bist Status. */
+	uint64_t pbm_word                     : 1;  /**< PBM_WORD Memory Bist Status. */
+	uint64_t pwq1                         : 1;  /**< PWQ1 Memory Bist Status. */
+	uint64_t pwq0                         : 1;  /**< PWQ0 Memory Bist Status. */
+	uint64_t prc_off                      : 1;  /**< PRC_OFF Memory Bist Status. */
+	uint64_t ipd_old                      : 1;  /**< IPD_OLD Memory Bist Status. */
+	uint64_t ipd_new                      : 1;  /**< IPD_NEW Memory Bist Status. */
+	uint64_t pwp                          : 1;  /**< PWP Memory Bist Status. */
+#else
+	uint64_t pwp                          : 1;
+	uint64_t ipd_new                      : 1;
+	uint64_t ipd_old                      : 1;
+	uint64_t prc_off                      : 1;
+	uint64_t pwq0                         : 1;
+	uint64_t pwq1                         : 1;
+	uint64_t pbm_word                     : 1;
+	uint64_t pbm0                         : 1;
+	uint64_t pbm1                         : 1;
+	uint64_t pbm2                         : 1;
+	uint64_t pbm3                         : 1;
+	uint64_t ipq_pbe0                     : 1;
+	uint64_t ipq_pbe1                     : 1;
+	uint64_t pwq_pow                      : 1;
+	uint64_t pwq_wp1                      : 1;
+	uint64_t pwq_wqed                     : 1;
+	uint64_t csr_ncmd                     : 1;
+	uint64_t csr_mem                      : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_bist_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t pwq_wqed                     : 1;  /**< PWQ PIP WQE DONE Memory Bist Status. */
+	uint64_t pwq_wp1                      : 1;  /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
+	uint64_t pwq_pow                      : 1;  /**< PWQ POW MEM Memory Bist Status. */
+	uint64_t ipq_pbe1                     : 1;  /**< IPQ PBE1 Memory Bist Status. */
+	uint64_t ipq_pbe0                     : 1;  /**< IPQ PBE0 Memory Bist Status. */
+	uint64_t pbm3                         : 1;  /**< PBM3 Memory Bist Status. */
+	uint64_t pbm2                         : 1;  /**< PBM2 Memory Bist Status. */
+	uint64_t pbm1                         : 1;  /**< PBM1 Memory Bist Status. */
+	uint64_t pbm0                         : 1;  /**< PBM0 Memory Bist Status. */
+	uint64_t pbm_word                     : 1;  /**< PBM_WORD Memory Bist Status. */
+	uint64_t pwq1                         : 1;  /**< PWQ1 Memory Bist Status. */
+	uint64_t pwq0                         : 1;  /**< PWQ0 Memory Bist Status. */
+	uint64_t prc_off                      : 1;  /**< PRC_OFF Memory Bist Status. */
+	uint64_t ipd_old                      : 1;  /**< IPD_OLD Memory Bist Status. */
+	uint64_t ipd_new                      : 1;  /**< IPD_NEW Memory Bist Status. */
+	uint64_t pwp                          : 1;  /**< PWP Memory Bist Status. */
+#else
+	uint64_t pwp                          : 1;
+	uint64_t ipd_new                      : 1;
+	uint64_t ipd_old                      : 1;
+	uint64_t prc_off                      : 1;
+	uint64_t pwq0                         : 1;
+	uint64_t pwq1                         : 1;
+	uint64_t pbm_word                     : 1;
+	uint64_t pbm0                         : 1;
+	uint64_t pbm1                         : 1;
+	uint64_t pbm2                         : 1;
+	uint64_t pbm3                         : 1;
+	uint64_t ipq_pbe0                     : 1;
+	uint64_t ipq_pbe1                     : 1;
+	uint64_t pwq_pow                      : 1;
+	uint64_t pwq_wp1                      : 1;
+	uint64_t pwq_wqed                     : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_bist_status_cn30xx    cn31xx;
+	struct cvmx_ipd_bist_status_cn30xx    cn38xx;
+	struct cvmx_ipd_bist_status_cn30xx    cn38xxp2;
+	struct cvmx_ipd_bist_status_cn30xx    cn50xx;
+	struct cvmx_ipd_bist_status_s         cn52xx;
+	struct cvmx_ipd_bist_status_s         cn52xxp1;
+	struct cvmx_ipd_bist_status_s         cn56xx;
+	struct cvmx_ipd_bist_status_s         cn56xxp1;
+	struct cvmx_ipd_bist_status_cn30xx    cn58xx;
+	struct cvmx_ipd_bist_status_cn30xx    cn58xxp1;
+	struct cvmx_ipd_bist_status_s         cn63xx;
+	struct cvmx_ipd_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t;
+
+/**
+ * cvmx_ipd_bp_prt_red_end
+ *
+ * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable
+ *
+ * When IPD applies backpressure to a PORT and the corresponding bit in this register is set,
+ * the RED Unit will drop packets for that port.
+ */
+union cvmx_ipd_bp_prt_red_end
+{
+	uint64_t u64;
+	struct cvmx_ipd_bp_prt_red_end_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t prt_enb                      : 44; /**< The port corresponding to the bit position in this
+                                                         field will drop all NON-RAW packets to that port
+                                                         when port level backpressure is applied to that
+                                                         port.  The applying of port-level backpressure for
+                                                         this dropping does not take into consideration the
+                                                         value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor
+                                                         IPD_RED_PORT_ENABLE[PRT_ENB]. */
+#else
+	uint64_t prt_enb                      : 44;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t prt_enb                      : 36; /**< The port corresponding to the bit position in this
+                                                         field, will allow RED to drop back when port level
+                                                         backpressure is applied to the port. The applying
+                                                         of port-level backpressure for this RED dropping
+                                                         does not take into consideration the value of
+                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
+#else
+	uint64_t prt_enb                      : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
+	struct cvmx_ipd_bp_prt_red_end_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t prt_enb                      : 40; /**< The port corresponding to the bit position in this
+                                                         field, will allow RED to drop back when port level
+                                                         backpressure is applied to the port. The applying
+                                                         of port-level backpressure for this RED dropping
+                                                         does not take into consideration the value of
+                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
+#else
+	uint64_t prt_enb                      : 40;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn52xx;
+	struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
+	struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
+	struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
+	struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+	struct cvmx_ipd_bp_prt_red_end_s      cn63xx;
+	struct cvmx_ipd_bp_prt_red_end_s      cn63xxp1;
+};
+typedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t;
+
+/**
+ * cvmx_ipd_clk_count
+ *
+ * IPD_CLK_COUNT = IPD Clock Count
+ *
+ * Counts the number of core clocks periods since the de-asserition of reset.
+ */
+union cvmx_ipd_clk_count
+{
+	uint64_t u64;
+	struct cvmx_ipd_clk_count_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clk_cnt                      : 64; /**< This counter will be zeroed when reset is applied
+                                                         and will increment every rising edge of the
+                                                         core-clock. */
+#else
+	uint64_t clk_cnt                      : 64;
+#endif
+	} s;
+	struct cvmx_ipd_clk_count_s           cn30xx;
+	struct cvmx_ipd_clk_count_s           cn31xx;
+	struct cvmx_ipd_clk_count_s           cn38xx;
+	struct cvmx_ipd_clk_count_s           cn38xxp2;
+	struct cvmx_ipd_clk_count_s           cn50xx;
+	struct cvmx_ipd_clk_count_s           cn52xx;
+	struct cvmx_ipd_clk_count_s           cn52xxp1;
+	struct cvmx_ipd_clk_count_s           cn56xx;
+	struct cvmx_ipd_clk_count_s           cn56xxp1;
+	struct cvmx_ipd_clk_count_s           cn58xx;
+	struct cvmx_ipd_clk_count_s           cn58xxp1;
+	struct cvmx_ipd_clk_count_s           cn63xx;
+	struct cvmx_ipd_clk_count_s           cn63xxp1;
+};
+typedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t;
+
+/**
+ * cvmx_ipd_ctl_status
+ *
+ * IPD_CTL_STATUS = IPD's Control Status Register
+ *
+ * The number of words in a MBUFF used for packet data store.
+ */
+union cvmx_ipd_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_ipd_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t use_sop                      : 1;  /**< When '1' the SOP sent by the MAC will be used in
+                                                         place of the SOP generated by the IPD. */
+	uint64_t rst_done                     : 1;  /**< When '0' IPD has finished reset. No access
+                                                         except the reading of this bit should occur to the
+                                                         IPD until this is asserted. Or a 1000 core clock
+                                                         cycles has passed after the de-assertion of reset. */
+	uint64_t clken                        : 1;  /**< Controls the conditional clocking within IPD
+                                                         0=Allow HW to control the clocks
+                                                         1=Force the clocks to be always on */
+	uint64_t no_wptr                      : 1;  /**< When set '1' the WQE pointers will not be used and
+                                                         the WQE will be located at the front of the packet.
+                                                         When set:
+                                                           - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used
+                                                           - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16
+                                                           - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then
+                                                             the WQE will be written into the first 128B
+                                                             cache block in the first buffer that contains
+                                                             the packet.
+                                                           - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then
+                                                             the WQE will be written into the second 128B
+                                                             cache block in the first buffer that contains
+                                                             the packet. */
+	uint64_t pq_apkt                      : 1;  /**< When set IPD_PORT_QOS_X_CNT WILL be incremented
+                                                         by one for every work queue entry that is sent to
+                                                         POW. */
+	uint64_t pq_nabuf                     : 1;  /**< When set IPD_PORT_QOS_X_CNT WILL NOT be
+                                                         incremented when IPD allocates a buffer for a
+                                                         packet. */
+	uint64_t ipd_full                     : 1;  /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+	uint64_t pkt_off                      : 1;  /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written to the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL],
+                                                         IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and
+                                                         IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL],
+                                                         IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and
+                                                         IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. The application should NOT
+                                                         de-assert this bit after asserting it. The
+                                                         receivers of this bit may have been put into
+                                                         backpressure mode and can only be released by
+                                                         IPD informing them that the backpressure has
+                                                         been released.
+                                                         GMXX_INF_MODE[EN] must be set to '1' for each
+                                                         packet interface which requires port back pressure
+                                                         prior to setting PBP_EN to '1'. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t len_m8                       : 1;
+	uint64_t pkt_off                      : 1;
+	uint64_t ipd_full                     : 1;
+	uint64_t pq_nabuf                     : 1;
+	uint64_t pq_apkt                      : 1;
+	uint64_t no_wptr                      : 1;
+	uint64_t clken                        : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t use_sop                      : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit.
+                                                         GMXX_INF_MODE[EN] must be set to '1' for each
+                                                         packet interface which requires port back pressure
+                                                         prior to setting PBP_EN to '1'. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t len_m8                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_ctl_status_cn30xx     cn31xx;
+	struct cvmx_ipd_ctl_status_cn30xx     cn38xx;
+	struct cvmx_ipd_ctl_status_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW.
+                                                         PASS-2 Field. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port.
+                                                         PASS-2 Field. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn38xxp2;
+	struct cvmx_ipd_ctl_status_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t no_wptr                      : 1;  /**< When set '1' the WQE pointers will not be used and
+                                                         the WQE will be located at the front of the packet. */
+	uint64_t pq_apkt                      : 1;  /**< Reserved. */
+	uint64_t pq_nabuf                     : 1;  /**< Reserved. */
+	uint64_t ipd_full                     : 1;  /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+	uint64_t pkt_off                      : 1;  /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit.
+                                                         GMXX_INF_MODE[EN] must be set to '1' for each
+                                                         packet interface which requires port back pressure
+                                                         prior to setting PBP_EN to '1'. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t len_m8                       : 1;
+	uint64_t pkt_off                      : 1;
+	uint64_t ipd_full                     : 1;
+	uint64_t pq_nabuf                     : 1;
+	uint64_t pq_apkt                      : 1;
+	uint64_t no_wptr                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn50xx;
+	struct cvmx_ipd_ctl_status_cn50xx     cn52xx;
+	struct cvmx_ipd_ctl_status_cn50xx     cn52xxp1;
+	struct cvmx_ipd_ctl_status_cn50xx     cn56xx;
+	struct cvmx_ipd_ctl_status_cn50xx     cn56xxp1;
+	struct cvmx_ipd_ctl_status_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t ipd_full                     : 1;  /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+	uint64_t pkt_off                      : 1;  /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN PASS2 generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW.
+                                                         PASS-2 Field. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port.
+                                                         PASS-2 Field. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t len_m8                       : 1;
+	uint64_t pkt_off                      : 1;
+	uint64_t ipd_full                     : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn58xx;
+	struct cvmx_ipd_ctl_status_cn58xx     cn58xxp1;
+	struct cvmx_ipd_ctl_status_s          cn63xx;
+	struct cvmx_ipd_ctl_status_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t clken                        : 1;  /**< Controls the conditional clocking within IPD
+                                                         0=Allow HW to control the clocks
+                                                         1=Force the clocks to be always on */
+	uint64_t no_wptr                      : 1;  /**< When set '1' the WQE pointers will not be used and
+                                                         the WQE will be located at the front of the packet.
+                                                         When set:
+                                                           - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used
+                                                           - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16
+                                                           - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then
+                                                             the WQE will be written into the first 128B
+                                                             cache block in the first buffer that contains
+                                                             the packet.
+                                                           - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then
+                                                             the WQE will be written into the second 128B
+                                                             cache block in the first buffer that contains
+                                                             the packet. */
+	uint64_t pq_apkt                      : 1;  /**< When set IPD_PORT_QOS_X_CNT WILL be incremented
+                                                         by one for every work queue entry that is sent to
+                                                         POW. */
+	uint64_t pq_nabuf                     : 1;  /**< When set IPD_PORT_QOS_X_CNT WILL NOT be
+                                                         incremented when IPD allocates a buffer for a
+                                                         packet. */
+	uint64_t ipd_full                     : 1;  /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+	uint64_t pkt_off                      : 1;  /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+	uint64_t len_m8                       : 1;  /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written to the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+	uint64_t reset                        : 1;  /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+	uint64_t addpkt                       : 1;  /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL],
+                                                         IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and
+                                                         IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW. */
+	uint64_t naddbuf                      : 1;  /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL],
+                                                         IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and
+                                                         IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port. */
+	uint64_t pkt_lend                     : 1;  /**< Changes PKT to little endian writes to L2C */
+	uint64_t wqe_lend                     : 1;  /**< Changes WQE to little endian writes to L2C */
+	uint64_t pbp_en                       : 1;  /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. The application should NOT
+                                                         de-assert this bit after asserting it. The
+                                                         receivers of this bit may have been put into
+                                                         backpressure mode and can only be released by
+                                                         IPD informing them that the backpressure has
+                                                         been released.
+                                                         GMXX_INF_MODE[EN] must be set to '1' for each
+                                                         packet interface which requires port back pressure
+                                                         prior to setting PBP_EN to '1'. */
+	cvmx_ipd_mode_t opc_mode              : 2;  /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+	uint64_t ipd_en                       : 1;  /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+	uint64_t ipd_en                       : 1;
+	cvmx_ipd_mode_t opc_mode              : 2;
+	uint64_t pbp_en                       : 1;
+	uint64_t wqe_lend                     : 1;
+	uint64_t pkt_lend                     : 1;
+	uint64_t naddbuf                      : 1;
+	uint64_t addpkt                       : 1;
+	uint64_t reset                        : 1;
+	uint64_t len_m8                       : 1;
+	uint64_t pkt_off                      : 1;
+	uint64_t ipd_full                     : 1;
+	uint64_t pq_nabuf                     : 1;
+	uint64_t pq_apkt                      : 1;
+	uint64_t no_wptr                      : 1;
+	uint64_t clken                        : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t;
+
+/**
+ * cvmx_ipd_int_enb
+ *
+ * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register
+ *
+ * Used to enable the various interrupting conditions of IPD
+ */
+union cvmx_ipd_int_enb
+{
+	uint64_t u64;
+	struct cvmx_ipd_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t pq_sub                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t pq_add                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t bc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t d_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t c_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t cc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t dc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+	uint64_t bp_sub                       : 1;  /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t pq_add                       : 1;
+	uint64_t pq_sub                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_ipd_int_enb_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bp_sub                       : 1;  /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_int_enb_cn30xx        cn31xx;
+	struct cvmx_ipd_int_enb_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t bc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+	uint64_t d_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+	uint64_t c_coll                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+	uint64_t cc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+	uint64_t dc_ovr                       : 1;  /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+	uint64_t bp_sub                       : 1;  /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn38xx;
+	struct cvmx_ipd_int_enb_cn30xx        cn38xxp2;
+	struct cvmx_ipd_int_enb_cn38xx        cn50xx;
+	struct cvmx_ipd_int_enb_s             cn52xx;
+	struct cvmx_ipd_int_enb_s             cn52xxp1;
+	struct cvmx_ipd_int_enb_s             cn56xx;
+	struct cvmx_ipd_int_enb_s             cn56xxp1;
+	struct cvmx_ipd_int_enb_cn38xx        cn58xx;
+	struct cvmx_ipd_int_enb_cn38xx        cn58xxp1;
+	struct cvmx_ipd_int_enb_s             cn63xx;
+	struct cvmx_ipd_int_enb_s             cn63xxp1;
+};
+typedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t;
+
+/**
+ * cvmx_ipd_int_sum
+ *
+ * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register
+ *
+ * Set when an interrupt condition occurs, write '1' to clear.
+ */
+union cvmx_ipd_int_sum
+{
+	uint64_t u64;
+	struct cvmx_ipd_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t pq_sub                       : 1;  /**< Set when a port-qos does an sub to the count
+                                                         that causes the counter to wrap. */
+	uint64_t pq_add                       : 1;  /**< Set when a port-qos does an add to the count
+                                                         that causes the counter to wrap. */
+	uint64_t bc_ovr                       : 1;  /**< Set when the byte-count to send to IOB overflows. */
+	uint64_t d_coll                       : 1;  /**< Set when the packet/WQE data to be sent to IOB
+                                                         collides. */
+	uint64_t c_coll                       : 1;  /**< Set when the packet/WQE commands to be sent to IOB
+                                                         collides. */
+	uint64_t cc_ovr                       : 1;  /**< Set when the command credits to the IOB overflow. */
+	uint64_t dc_ovr                       : 1;  /**< Set when the data credits to the IOB overflow. */
+	uint64_t bp_sub                       : 1;  /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t pq_add                       : 1;
+	uint64_t pq_sub                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_ipd_int_sum_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bp_sub                       : 1;  /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_int_sum_cn30xx        cn31xx;
+	struct cvmx_ipd_int_sum_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t bc_ovr                       : 1;  /**< Set when the byte-count to send to IOB overflows.
+                                                         This is a PASS-3 Field. */
+	uint64_t d_coll                       : 1;  /**< Set when the packet/WQE data to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+	uint64_t c_coll                       : 1;  /**< Set when the packet/WQE commands to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+	uint64_t cc_ovr                       : 1;  /**< Set when the command credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+	uint64_t dc_ovr                       : 1;  /**< Set when the data credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+	uint64_t bp_sub                       : 1;  /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+	uint64_t prc_par3                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+	uint64_t prc_par2                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+	uint64_t prc_par1                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+	uint64_t prc_par0                     : 1;  /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+	uint64_t prc_par0                     : 1;
+	uint64_t prc_par1                     : 1;
+	uint64_t prc_par2                     : 1;
+	uint64_t prc_par3                     : 1;
+	uint64_t bp_sub                       : 1;
+	uint64_t dc_ovr                       : 1;
+	uint64_t cc_ovr                       : 1;
+	uint64_t c_coll                       : 1;
+	uint64_t d_coll                       : 1;
+	uint64_t bc_ovr                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn38xx;
+	struct cvmx_ipd_int_sum_cn30xx        cn38xxp2;
+	struct cvmx_ipd_int_sum_cn38xx        cn50xx;
+	struct cvmx_ipd_int_sum_s             cn52xx;
+	struct cvmx_ipd_int_sum_s             cn52xxp1;
+	struct cvmx_ipd_int_sum_s             cn56xx;
+	struct cvmx_ipd_int_sum_s             cn56xxp1;
+	struct cvmx_ipd_int_sum_cn38xx        cn58xx;
+	struct cvmx_ipd_int_sum_cn38xx        cn58xxp1;
+	struct cvmx_ipd_int_sum_s             cn63xx;
+	struct cvmx_ipd_int_sum_s             cn63xxp1;
+};
+typedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t;
+
+/**
+ * cvmx_ipd_not_1st_mbuff_skip
+ *
+ * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size
+ *
+ * The number of words that the IPD will skip when writing any MBUFF that is not the first.
+ */
+union cvmx_ipd_not_1st_mbuff_skip
+{
+	uint64_t u64;
+	struct cvmx_ipd_not_1st_mbuff_skip_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t skip_sz                      : 6;  /**< The number of 8-byte words from the top of any
+                                                         MBUFF, that is not the 1st MBUFF, that the IPD
+                                                         will write the next-pointer.
+                                                         Legal values are 0 to 32, where the MAX value
+                                                         is also limited to:
+                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */
+#else
+	uint64_t skip_sz                      : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn30xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn31xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn38xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn38xxp2;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn50xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn52xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn52xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn56xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn56xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn58xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn58xxp1;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn63xx;
+	struct cvmx_ipd_not_1st_mbuff_skip_s  cn63xxp1;
+};
+typedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t;
+
+/**
+ * cvmx_ipd_packet_mbuff_size
+ *
+ * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words
+ *
+ * The number of words in a MBUFF used for packet data store.
+ */
+union cvmx_ipd_packet_mbuff_size
+{
+	uint64_t u64;
+	struct cvmx_ipd_packet_mbuff_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t mb_size                      : 12; /**< The number of 8-byte words in a MBUF.
+                                                         This must be a number in the range of 32 to
+                                                         2048.
+                                                         This is also the size of the FPA's
+                                                         Queue-0 Free-Page. */
+#else
+	uint64_t mb_size                      : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_ipd_packet_mbuff_size_s   cn30xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn31xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn38xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn38xxp2;
+	struct cvmx_ipd_packet_mbuff_size_s   cn50xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn52xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn52xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cn56xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn56xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cn58xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn58xxp1;
+	struct cvmx_ipd_packet_mbuff_size_s   cn63xx;
+	struct cvmx_ipd_packet_mbuff_size_s   cn63xxp1;
+};
+typedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t;
+
+/**
+ * cvmx_ipd_pkt_ptr_valid
+ *
+ * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid
+ *
+ * The value of the packet-pointer fetched and in the valid register.
+ */
+union cvmx_ipd_pkt_ptr_valid
+{
+	uint64_t u64;
+	struct cvmx_ipd_pkt_ptr_valid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t ptr                          : 29; /**< Pointer value. */
+#else
+	uint64_t ptr                          : 29;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn30xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn31xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn38xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn50xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn52xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn52xxp1;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn56xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn56xxp1;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn58xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn58xxp1;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn63xx;
+	struct cvmx_ipd_pkt_ptr_valid_s       cn63xxp1;
+};
+typedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t;
+
+/**
+ * cvmx_ipd_port#_bp_page_cnt
+ *
+ * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count
+ *
+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
+ * See also IPD_PORTX_BP_PAGE_CNT2
+ * See also IPD_PORTX_BP_PAGE_CNT3
+ */
+union cvmx_ipd_portx_bp_page_cnt
+{
+	uint64_t u64;
+	struct cvmx_ipd_portx_bp_page_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to port. */
+	uint64_t page_cnt                     : 17; /**< The number of page pointers assigned to
+                                                         the port, that when exceeded will cause
+                                                         back-pressure to be applied to the port.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+	uint64_t page_cnt                     : 17;
+	uint64_t bp_enb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn30xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn31xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn38xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn38xxp2;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn50xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn52xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn52xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn56xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn56xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn58xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn58xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn63xx;
+	struct cvmx_ipd_portx_bp_page_cnt_s   cn63xxp1;
+};
+typedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t;
+
+/**
+ * cvmx_ipd_port#_bp_page_cnt2
+ *
+ * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count
+ *
+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
+ * See also IPD_PORTX_BP_PAGE_CNT
+ * See also IPD_PORTX_BP_PAGE_CNT3
+ */
+union cvmx_ipd_portx_bp_page_cnt2
+{
+	uint64_t u64;
+	struct cvmx_ipd_portx_bp_page_cnt2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to port. */
+	uint64_t page_cnt                     : 17; /**< The number of page pointers assigned to
+                                                         the port, that when exceeded will cause
+                                                         back-pressure to be applied to the port.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+	uint64_t page_cnt                     : 17;
+	uint64_t bp_enb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn52xx;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn52xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn56xx;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn56xxp1;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn63xx;
+	struct cvmx_ipd_portx_bp_page_cnt2_s  cn63xxp1;
+};
+typedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t;
+
+/**
+ * cvmx_ipd_port#_bp_page_cnt3
+ *
+ * IPD_PORTX_BP_PAGE_CNT3 = IPD Port Backpressure Page Count
+ *
+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
+ * See also IPD_PORTX_BP_PAGE_CNT
+ * See also IPD_PORTX_BP_PAGE_CNT2
+ */
+union cvmx_ipd_portx_bp_page_cnt3
+{
+	uint64_t u64;
+	struct cvmx_ipd_portx_bp_page_cnt3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t bp_enb                       : 1;  /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to port. */
+	uint64_t page_cnt                     : 17; /**< The number of page pointers assigned to
+                                                         the port, that when exceeded will cause
+                                                         back-pressure to be applied to the port.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+	uint64_t page_cnt                     : 17;
+	uint64_t bp_enb                       : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_ipd_portx_bp_page_cnt3_s  cn63xx;
+	struct cvmx_ipd_portx_bp_page_cnt3_s  cn63xxp1;
+};
+typedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t;
+
+/**
+ * cvmx_ipd_port_bp_counters2_pair#
+ *
+ * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ * See also IPD_PORT_BP_COUNTERS_PAIRX
+ * See also IPD_PORT_BP_COUNTERS3_PAIRX
+ */
+union cvmx_ipd_port_bp_counters2_pairx
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_bp_counters2_pairx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
+#else
+	uint64_t cnt_val                      : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
+	struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+};
+typedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t;
+
+/**
+ * cvmx_ipd_port_bp_counters3_pair#
+ *
+ * IPD_PORT_BP_COUNTERS3_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ * See also IPD_PORT_BP_COUNTERS_PAIRX
+ * See also IPD_PORT_BP_COUNTERS2_PAIRX
+ */
+union cvmx_ipd_port_bp_counters3_pairx
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_bp_counters3_pairx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
+#else
+	uint64_t cnt_val                      : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
+	struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
+};
+typedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t;
+
+/**
+ * cvmx_ipd_port_bp_counters_pair#
+ *
+ * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ * See also IPD_PORT_BP_COUNTERS2_PAIRX
+ * See also IPD_PORT_BP_COUNTERS3_PAIRX
+ */
+union cvmx_ipd_port_bp_counters_pairx
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_bp_counters_pairx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t cnt_val                      : 25; /**< Number of MBUFs being used by data on this port. */
+#else
+	uint64_t cnt_val                      : 25;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
+	struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
+};
+typedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t;
+
+/**
+ * cvmx_ipd_port_qos_#_cnt
+ *
+ * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count
+ *
+ * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0
+ * QOS 0-7 respectively followed by port 1 at (8-15), etc
+ * Ports 0-3, 32-43
+ */
+union cvmx_ipd_port_qos_x_cnt
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_qos_x_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wmark                        : 32; /**< When the field CNT after being modified is equal to
+                                                         or crosses this value (i.e. value was greater than
+                                                         then becomes less then, or value was less than and
+                                                         becomes greater than) the corresponding bit in
+                                                         IPD_PORT_QOS_INTX is set. */
+	uint64_t cnt                          : 32; /**< The packet related count that is incremented as
+                                                         specified by IPD_SUB_PORT_QOS_CNT. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t wmark                        : 32;
+#endif
+	} s;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn52xx;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn52xxp1;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn56xx;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn56xxp1;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn63xx;
+	struct cvmx_ipd_port_qos_x_cnt_s      cn63xxp1;
+};
+typedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t;
+
+/**
+ * cvmx_ipd_port_qos_int#
+ *
+ * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt
+ *
+ * See the description for IPD_PORT_QOS_X_CNT
+ *
+ * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63
+ *
+ * Only ports used are: P0-3, P32-39, and P40-43. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4,
+ * and IPD_PORT_QOS_INT5 exist and, furthermore:  <63:32> of IPD_PORT_QOS_INT0 and IPD_PORT_QOS_INT5,
+ * are reserved.
+ */
+union cvmx_ipd_port_qos_intx
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_qos_intx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Interrupt bits. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_ipd_port_qos_intx_s       cn52xx;
+	struct cvmx_ipd_port_qos_intx_s       cn52xxp1;
+	struct cvmx_ipd_port_qos_intx_s       cn56xx;
+	struct cvmx_ipd_port_qos_intx_s       cn56xxp1;
+	struct cvmx_ipd_port_qos_intx_s       cn63xx;
+	struct cvmx_ipd_port_qos_intx_s       cn63xxp1;
+};
+typedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t;
+
+/**
+ * cvmx_ipd_port_qos_int_enb#
+ *
+ * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable
+ *
+ * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated.
+ */
+union cvmx_ipd_port_qos_int_enbx
+{
+	uint64_t u64;
+	struct cvmx_ipd_port_qos_int_enbx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enable bits. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn52xx;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn52xxp1;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn56xx;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn56xxp1;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn63xx;
+	struct cvmx_ipd_port_qos_int_enbx_s   cn63xxp1;
+};
+typedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t;
+
+/**
+ * cvmx_ipd_prc_hold_ptr_fifo_ctl
+ *
+ * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo.
+ */
+union cvmx_ipd_prc_hold_ptr_fifo_ctl
+{
+	uint64_t u64;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t max_pkt                      : 3;  /**< Maximum number of Packet-Pointers that COULD be
+                                                         in the FIFO. */
+	uint64_t praddr                       : 3;  /**< Present Packet-Pointer read address. */
+	uint64_t ptr                          : 29; /**< The output of the prc-holding-fifo. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable that controls the
+                                                         MUX-select that steers [RADDR] to the fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 3;  /**< Sets the address to read from in the holding.
+                                                         fifo in the PRC. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+	uint64_t raddr                        : 3;
+	uint64_t cena                         : 1;
+	uint64_t ptr                          : 29;
+	uint64_t praddr                       : 3;
+	uint64_t max_pkt                      : 3;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
+	struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
+};
+typedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
+
+/**
+ * cvmx_ipd_prc_port_ptr_fifo_ctl
+ *
+ * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo.
+ */
+union cvmx_ipd_prc_port_ptr_fifo_ctl
+{
+	uint64_t u64;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t max_pkt                      : 7;  /**< Maximum number of Packet-Pointers that are in
+                                                         in the FIFO. */
+	uint64_t ptr                          : 29; /**< The output of the prc-port-ptr-fifo. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable to the read port of the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 7;  /**< Sets the address to read from in the port
+                                                         fifo in the PRC. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+	uint64_t raddr                        : 7;
+	uint64_t cena                         : 1;
+	uint64_t ptr                          : 29;
+	uint64_t max_pkt                      : 7;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
+	struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
+};
+typedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t;
+
+/**
+ * cvmx_ipd_ptr_count
+ *
+ * IPD_PTR_COUNT = IPD Page Pointer Count
+ *
+ * Shows the number of WQE and Packet Page Pointers stored in the IPD.
+ */
+union cvmx_ipd_ptr_count
+{
+	uint64_t u64;
+	struct cvmx_ipd_ptr_count_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t pktv_cnt                     : 1;  /**< PKT Ptr Valid. */
+	uint64_t wqev_cnt                     : 1;  /**< WQE Ptr Valid. This value is '1' when a WQE
+                                                         is being for use by the IPD. The value of this
+                                                         field should be added to tha value of the
+                                                         WQE_PCNT field, of this register, for a total
+                                                         count of the WQE Page Pointers being held by IPD.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
+                                                         represents a Packet-Pointer NOT a WQE pointer. */
+	uint64_t pfif_cnt                     : 3;  /**< See PKT_PCNT. */
+	uint64_t pkt_pcnt                     : 7;  /**< This value plus PFIF_CNT plus
+                                                         IPD_PRC_PORT_PTR_FIFO_CTL[MAX_PKT] is the number
+                                                         of PKT Page Pointers in IPD. */
+	uint64_t wqe_pcnt                     : 7;  /**< Number of page pointers for WQE storage that are
+                                                         buffered in the IPD. The total count is the value
+                                                         of this buffer plus the field [WQEV_CNT]. For
+                                                         PASS-1 (which does not have the WQEV_CNT field)
+                                                         when the value of this register is '0' there still
+                                                         may be 1 pointer being held by IPD. */
+#else
+	uint64_t wqe_pcnt                     : 7;
+	uint64_t pkt_pcnt                     : 7;
+	uint64_t pfif_cnt                     : 3;
+	uint64_t wqev_cnt                     : 1;
+	uint64_t pktv_cnt                     : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_ipd_ptr_count_s           cn30xx;
+	struct cvmx_ipd_ptr_count_s           cn31xx;
+	struct cvmx_ipd_ptr_count_s           cn38xx;
+	struct cvmx_ipd_ptr_count_s           cn38xxp2;
+	struct cvmx_ipd_ptr_count_s           cn50xx;
+	struct cvmx_ipd_ptr_count_s           cn52xx;
+	struct cvmx_ipd_ptr_count_s           cn52xxp1;
+	struct cvmx_ipd_ptr_count_s           cn56xx;
+	struct cvmx_ipd_ptr_count_s           cn56xxp1;
+	struct cvmx_ipd_ptr_count_s           cn58xx;
+	struct cvmx_ipd_ptr_count_s           cn58xxp1;
+	struct cvmx_ipd_ptr_count_s           cn63xx;
+	struct cvmx_ipd_ptr_count_s           cn63xxp1;
+};
+typedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t;
+
+/**
+ * cvmx_ipd_pwp_ptr_fifo_ctl
+ *
+ * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control
+ *
+ * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo.
+ */
+union cvmx_ipd_pwp_ptr_fifo_ctl
+{
+	uint64_t u64;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t max_cnts                     : 7;  /**< Maximum number of Packet-Pointers or WQE-Pointers
+                                                         that COULD be in the FIFO.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
+                                                         only represents the Max number of Packet-Pointers,
+                                                         WQE-Pointers are not used in this mode. */
+	uint64_t wraddr                       : 8;  /**< Present FIFO WQE Read address. */
+	uint64_t praddr                       : 8;  /**< Present FIFO Packet Read address. */
+	uint64_t ptr                          : 29; /**< The output of the pwp_fifo. */
+	uint64_t cena                         : 1;  /**< Active low Chip Enable to the read port of the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+	uint64_t raddr                        : 8;  /**< Sets the address to read from in the pwp_fifo.
+                                                         Addresses 0 through 63 contain Packet-Pointers and
+                                                         addresses 64 through 127 contain WQE-Pointers.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses
+                                                         64 through 127 are not valid. */
+#else
+	uint64_t raddr                        : 8;
+	uint64_t cena                         : 1;
+	uint64_t ptr                          : 29;
+	uint64_t praddr                       : 8;
+	uint64_t wraddr                       : 8;
+	uint64_t max_cnts                     : 7;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn30xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn31xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn38xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn50xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn52xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn52xxp1;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn56xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn56xxp1;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn58xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn58xxp1;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn63xx;
+	struct cvmx_ipd_pwp_ptr_fifo_ctl_s    cn63xxp1;
+};
+typedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t;
+
+/**
+ * cvmx_ipd_qos#_red_marks
+ *
+ * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low
+ *
+ * Set the pass-drop marks for qos level.
+ */
+union cvmx_ipd_qosx_red_marks
+{
+	uint64_t u64;
+	struct cvmx_ipd_qosx_red_marks_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t drop                         : 32; /**< Packets will be dropped when the average value of
+                                                         IPD_QUE0_FREE_PAGE_CNT is equal to or less than
+                                                         this value. */
+	uint64_t pass                         : 32; /**< Packets will be passed when the average value of
+                                                         IPD_QUE0_FREE_PAGE_CNT is larger than this value. */
+#else
+	uint64_t pass                         : 32;
+	uint64_t drop                         : 32;
+#endif
+	} s;
+	struct cvmx_ipd_qosx_red_marks_s      cn30xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn31xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn38xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn38xxp2;
+	struct cvmx_ipd_qosx_red_marks_s      cn50xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn52xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn52xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cn56xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn56xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cn58xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn58xxp1;
+	struct cvmx_ipd_qosx_red_marks_s      cn63xx;
+	struct cvmx_ipd_qosx_red_marks_s      cn63xxp1;
+};
+typedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t;
+
+/**
+ * cvmx_ipd_que0_free_page_cnt
+ *
+ * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count
+ *
+ * Number of Free-Page Pointer that are available for use in the FPA for Queue-0.
+ */
+union cvmx_ipd_que0_free_page_cnt
+{
+	uint64_t u64;
+	struct cvmx_ipd_que0_free_page_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t q0_pcnt                      : 32; /**< Number of Queue-0 Page Pointers Available. */
+#else
+	uint64_t q0_pcnt                      : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn30xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn31xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn38xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn38xxp2;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn50xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn52xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn52xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn56xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn56xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn58xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn58xxp1;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn63xx;
+	struct cvmx_ipd_que0_free_page_cnt_s  cn63xxp1;
+};
+typedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t;
+
+/**
+ * cvmx_ipd_red_port_enable
+ *
+ * IPD_RED_PORT_ENABLE = IPD RED Port Enable
+ *
+ * Set the pass-drop marks for qos level.
+ */
+union cvmx_ipd_red_port_enable
+{
+	uint64_t u64;
+	struct cvmx_ipd_red_port_enable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t prb_dly                      : 14; /**< Number (core clocks periods + 68) * 8 to wait
+                                                         before calculating the new packet drop
+                                                         probability for each QOS level. */
+	uint64_t avg_dly                      : 14; /**< Number (core clocks periods + 10) * 8 to wait
+                                                         before calculating the moving average for each
+                                                         QOS level.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+	uint64_t prt_enb                      : 36; /**< The bit position will enable the corresponding
+                                                         Ports ability to have packets dropped by RED
+                                                         probability. */
+#else
+	uint64_t prt_enb                      : 36;
+	uint64_t avg_dly                      : 14;
+	uint64_t prb_dly                      : 14;
+#endif
+	} s;
+	struct cvmx_ipd_red_port_enable_s     cn30xx;
+	struct cvmx_ipd_red_port_enable_s     cn31xx;
+	struct cvmx_ipd_red_port_enable_s     cn38xx;
+	struct cvmx_ipd_red_port_enable_s     cn38xxp2;
+	struct cvmx_ipd_red_port_enable_s     cn50xx;
+	struct cvmx_ipd_red_port_enable_s     cn52xx;
+	struct cvmx_ipd_red_port_enable_s     cn52xxp1;
+	struct cvmx_ipd_red_port_enable_s     cn56xx;
+	struct cvmx_ipd_red_port_enable_s     cn56xxp1;
+	struct cvmx_ipd_red_port_enable_s     cn58xx;
+	struct cvmx_ipd_red_port_enable_s     cn58xxp1;
+	struct cvmx_ipd_red_port_enable_s     cn63xx;
+	struct cvmx_ipd_red_port_enable_s     cn63xxp1;
+};
+typedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t;
+
+/**
+ * cvmx_ipd_red_port_enable2
+ *
+ * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2
+ *
+ * Set the pass-drop marks for qos level.
+ */
+union cvmx_ipd_red_port_enable2
+{
+	uint64_t u64;
+	struct cvmx_ipd_red_port_enable2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t prt_enb                      : 8;  /**< Bits 7-0 corresponds to ports 43-36. These bits
+                                                         have the same meaning as the PRT_ENB field of
+                                                         IPD_RED_PORT_ENABLE. */
+#else
+	uint64_t prt_enb                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_ipd_red_port_enable2_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t prt_enb                      : 4;  /**< Bits 3-0 cooresponds to ports 39-36. These bits
+                                                         have the same meaning as the PRT_ENB field of
+                                                         IPD_RED_PORT_ENABLE. */
+#else
+	uint64_t prt_enb                      : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
+	struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
+	struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
+	struct cvmx_ipd_red_port_enable2_s    cn63xx;
+	struct cvmx_ipd_red_port_enable2_s    cn63xxp1;
+};
+typedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t;
+
+/**
+ * cvmx_ipd_red_que#_param
+ *
+ * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters
+ *
+ * Value control the Passing and Dropping of packets by the red engine for QOS Level-0.
+ */
+union cvmx_ipd_red_quex_param
+{
+	uint64_t u64;
+	struct cvmx_ipd_red_quex_param_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t use_pcnt                     : 1;  /**< When set '1' red will use the actual Packet-Page
+                                                         Count in place of the Average for RED calculations. */
+	uint64_t new_con                      : 8;  /**< This value is used control how much of the present
+                                                         Actual Queue Size is used to calculate the new
+                                                         Average Queue Size. The value is a number from 0
+                                                         256, which represents NEW_CON/256 of the Actual
+                                                         Queue Size that will be used in the calculation.
+                                                         The number in this field plus the value of
+                                                         AVG_CON must be equal to 256.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+	uint64_t avg_con                      : 8;  /**< This value is used control how much of the present
+                                                         Average Queue Size is used to calculate the new
+                                                         Average Queue Size. The value is a number from 0
+                                                         256, which represents AVG_CON/256 of the Average
+                                                         Queue Size that will be used in the calculation.
+                                                         The number in this field plus the value of
+                                                         NEW_CON must be equal to 256.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+	uint64_t prb_con                      : 32; /**< Used in computing the probability of a packet being
+                                                         passed or drop by the WRED engine. The field is
+                                                         calculated to be (255 * 2^24)/(PASS-DROP). Where
+                                                         PASS and DROP are the field from the
+                                                         IPD_QOS0_RED_MARKS CSR. */
+#else
+	uint64_t prb_con                      : 32;
+	uint64_t avg_con                      : 8;
+	uint64_t new_con                      : 8;
+	uint64_t use_pcnt                     : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_ipd_red_quex_param_s      cn30xx;
+	struct cvmx_ipd_red_quex_param_s      cn31xx;
+	struct cvmx_ipd_red_quex_param_s      cn38xx;
+	struct cvmx_ipd_red_quex_param_s      cn38xxp2;
+	struct cvmx_ipd_red_quex_param_s      cn50xx;
+	struct cvmx_ipd_red_quex_param_s      cn52xx;
+	struct cvmx_ipd_red_quex_param_s      cn52xxp1;
+	struct cvmx_ipd_red_quex_param_s      cn56xx;
+	struct cvmx_ipd_red_quex_param_s      cn56xxp1;
+	struct cvmx_ipd_red_quex_param_s      cn58xx;
+	struct cvmx_ipd_red_quex_param_s      cn58xxp1;
+	struct cvmx_ipd_red_quex_param_s      cn63xx;
+	struct cvmx_ipd_red_quex_param_s      cn63xxp1;
+};
+typedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t;
+
+/**
+ * cvmx_ipd_sub_port_bp_page_cnt
+ *
+ * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count
+ *
+ * Will add the value to the indicated port count register, the number of pages supplied. The value added should
+ * be the 2's complement of the value that needs to be subtracted. Users add 2's complement values to the
+ * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level
+ * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the
+ * value in the IPD_PORTX_BP_PAGE_CNT, IPD_PORTX_BP_PAGE_CNT2, and IPD_PORTX_BP_PAGE_CNT3.
+ *
+ * This register can't be written from the PCI via a window write.
+ */
+union cvmx_ipd_sub_port_bp_page_cnt
+{
+	uint64_t u64;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t port                         : 6;  /**< The port to add the PAGE_CNT field to. */
+	uint64_t page_cnt                     : 25; /**< The number of page pointers to add to
+                                                         the port counter pointed to by the
+                                                         PORT Field. */
+#else
+	uint64_t page_cnt                     : 25;
+	uint64_t port                         : 6;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
+	struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
+};
+typedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t;
+
+/**
+ * cvmx_ipd_sub_port_fcs
+ *
+ * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register
+ *
+ * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of
+ * the packet.
+ */
+union cvmx_ipd_sub_port_fcs
+{
+	uint64_t u64;
+	struct cvmx_ipd_sub_port_fcs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t port_bit2                    : 4;  /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+	uint64_t reserved_32_35               : 4;
+	uint64_t port_bit                     : 32; /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+	uint64_t port_bit                     : 32;
+	uint64_t reserved_32_35               : 4;
+	uint64_t port_bit2                    : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_ipd_sub_port_fcs_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t port_bit                     : 3;  /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+	uint64_t port_bit                     : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_ipd_sub_port_fcs_cn30xx   cn31xx;
+	struct cvmx_ipd_sub_port_fcs_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port_bit                     : 32; /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+	uint64_t port_bit                     : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_ipd_sub_port_fcs_cn38xx   cn38xxp2;
+	struct cvmx_ipd_sub_port_fcs_cn30xx   cn50xx;
+	struct cvmx_ipd_sub_port_fcs_s        cn52xx;
+	struct cvmx_ipd_sub_port_fcs_s        cn52xxp1;
+	struct cvmx_ipd_sub_port_fcs_s        cn56xx;
+	struct cvmx_ipd_sub_port_fcs_s        cn56xxp1;
+	struct cvmx_ipd_sub_port_fcs_cn38xx   cn58xx;
+	struct cvmx_ipd_sub_port_fcs_cn38xx   cn58xxp1;
+	struct cvmx_ipd_sub_port_fcs_s        cn63xx;
+	struct cvmx_ipd_sub_port_fcs_s        cn63xxp1;
+};
+typedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t;
+
+/**
+ * cvmx_ipd_sub_port_qos_cnt
+ *
+ * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count
+ *
+ * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be
+ * be the 2's complement of the value that needs to be subtracted.
+ */
+union cvmx_ipd_sub_port_qos_cnt
+{
+	uint64_t u64;
+	struct cvmx_ipd_sub_port_qos_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_41_63               : 23;
+	uint64_t port_qos                     : 9;  /**< The port to add the CNT field to. */
+	uint64_t cnt                          : 32; /**< The value to be added to the register selected
+                                                         in the PORT_QOS field. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t port_qos                     : 9;
+	uint64_t reserved_41_63               : 23;
+#endif
+	} s;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn52xx;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn52xxp1;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn56xx;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn56xxp1;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn63xx;
+	struct cvmx_ipd_sub_port_qos_cnt_s    cn63xxp1;
+};
+typedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t;
+
+/**
+ * cvmx_ipd_wqe_fpa_queue
+ *
+ * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size
+ *
+ * Which FPA Queue (0-7) to fetch page-pointers from for WQE's
+ */
+union cvmx_ipd_wqe_fpa_queue
+{
+	uint64_t u64;
+	struct cvmx_ipd_wqe_fpa_queue_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t wqe_pool                     : 3;  /**< Which FPA Queue to fetch page-pointers
+                                                         from for WQE's.
+                                                         Not used when IPD_CTL_STATUS[NO_WPTR] is set. */
+#else
+	uint64_t wqe_pool                     : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn30xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn31xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn38xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn38xxp2;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn50xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn52xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn52xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn56xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn56xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn58xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn58xxp1;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn63xx;
+	struct cvmx_ipd_wqe_fpa_queue_s       cn63xxp1;
+};
+typedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t;
+
+/**
+ * cvmx_ipd_wqe_ptr_valid
+ *
+ * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid
+ *
+ * The value of the WQE-pointer fetched and in the valid register.
+ */
+union cvmx_ipd_wqe_ptr_valid
+{
+	uint64_t u64;
+	struct cvmx_ipd_wqe_ptr_valid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t ptr                          : 29; /**< Pointer value.
+                                                         When IPD_CTL_STATUS[NO_WPTR] is set '1' this field
+                                                         represents a Packet-Pointer NOT a WQE pointer. */
+#else
+	uint64_t ptr                          : 29;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn30xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn31xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn38xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn50xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn52xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn52xxp1;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn56xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn56xxp1;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn58xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn58xxp1;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn63xx;
+	struct cvmx_ipd_wqe_ptr_valid_s       cn63xxp1;
+};
+typedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ipd.h b/sys/contrib/octeon-sdk/cvmx-ipd.h
index 2c3b177..c6c7bf9 100644
--- a/sys/contrib/octeon-sdk/cvmx-ipd.h
+++ b/sys/contrib/octeon-sdk/cvmx-ipd.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,23 +42,30 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the hardware Input Packet Data unit.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 
 #ifndef __CVMX_IPD_H__
 #define __CVMX_IPD_H__
 
-#ifndef CVMX_DONT_INCLUDE_CONFIG
-#include "executive-config.h"
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
-#include "cvmx-config.h"
-#endif
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-ipd-defs.h>
+#else
+# ifndef CVMX_DONT_INCLUDE_CONFIG
+#  include "executive-config.h"
+#   ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#    include "cvmx-config.h"
+#   endif
+# endif
 #endif
 
 #ifdef	__cplusplus
@@ -68,10 +76,10 @@ extern "C" {
 #define CVMX_ENABLE_LEN_M8_FIX 0
 #endif
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-ipd-defs.h */
 
-typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
-typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
+typedef cvmx_ipd_1st_mbuff_skip_t cvmx_ipd_mbuff_not_first_skip_t;
+typedef cvmx_ipd_1st_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
 
 
 /**
@@ -89,7 +97,9 @@ typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
  *                   FPA pool to get work entries from
  * @param cache_mode
  * @param back_pres_enable_flag
- *                   Enable or disable port back pressure
+ *                   Enable or disable port back pressure at a global level.
+ *                   This should always be 1 as more accurate control can be
+ *                   found in IPD_PORTX_BP_PAGE_CNT[BP_ENB].
  */
 static inline void cvmx_ipd_config(uint64_t mbuff_size,
                                    uint64_t first_mbuff_skip,
@@ -101,12 +111,12 @@ static inline void cvmx_ipd_config(uint64_t mbuff_size,
                                    uint64_t back_pres_enable_flag
                                   )
 {
-    cvmx_ipd_mbuff_first_skip_t first_skip;
+    cvmx_ipd_1st_mbuff_skip_t first_skip;
     cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
-    cvmx_ipd_mbuff_size_t size;
-    cvmx_ipd_first_next_ptr_back_t first_back_struct;
+    cvmx_ipd_packet_mbuff_size_t size;
+    cvmx_ipd_1st_next_ptr_back_t first_back_struct;
     cvmx_ipd_second_next_ptr_back_t second_back_struct;
-    cvmx_ipd_wqe_fpa_pool_t wqe_pool;
+    cvmx_ipd_wqe_fpa_queue_t wqe_pool;
     cvmx_ipd_ctl_status_t ipd_ctl_reg;
 
     first_skip.u64 = 0;
@@ -154,10 +164,10 @@ static inline void cvmx_ipd_enable(void)
     {
         cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
     }
-    ipd_reg.s.ipd_en = TRUE;
+    ipd_reg.s.ipd_en = 1;
     #if  CVMX_ENABLE_LEN_M8_FIX
     if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
-        ipd_reg.s.len_m8 = TRUE;
+        ipd_reg.s.len_m8 = 1;
     }
     #endif
     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
@@ -171,18 +181,25 @@ static inline void cvmx_ipd_disable(void)
 {
     cvmx_ipd_ctl_status_t ipd_reg;
     ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-    ipd_reg.s.ipd_en = FALSE;
+    ipd_reg.s.ipd_en = 0;
     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
 }
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 /**
- * Supportive function for cvmx_fpa_shutdown_pool.
+ * @INTERNAL
+ * This function is called by cvmx_helper_shutdown() to extract
+ * all FPA buffers out of the IPD and PIP. After this function
+ * completes, all FPA buffers that were prefetched by IPD and PIP
+ * wil be in the apropriate FPA pool. This functions does not reset
+ * PIP or IPD as FPA pool zero must be empty before the reset can
+ * be performed. WARNING: It is very important that IPD and PIP be
+ * reset soon after a call to this function.
  */
-static inline void cvmx_ipd_free_ptr(void)
+static inline void __cvmx_ipd_free_ptr(void)
 {
     /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
-    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
 	int no_wptr = 0;
 	cvmx_ipd_ptr_count_t ipd_ptr_count;
 	ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
@@ -191,7 +208,7 @@ static inline void cvmx_ipd_free_ptr(void)
 	if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
 	    cvmx_ipd_ctl_status_t ipd_ctl_status;
 	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-	    if (ipd_ctl_status.s.no_wptr) 
+	    if (ipd_ctl_status.s.no_wptr)
 		no_wptr = 1;
 	}
 
@@ -228,7 +245,7 @@ static inline void cvmx_ipd_free_ptr(void)
 	if (ipd_ptr_count.s.pktv_cnt) {
 	    cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
 	    ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
-	    cvmx_fpa_free(cvmx_phys_to_ptr(ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 	}
 
 	/* Free the per port prefetched packets */
@@ -282,22 +299,6 @@ static inline void cvmx_ipd_free_ptr(void)
 	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
 	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
 	}
-
-	/* Reset the IPD to get all buffers out of it */
-	{
-	    cvmx_ipd_ctl_status_t ipd_ctl_status;
-	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-	    ipd_ctl_status.s.reset = 1;
-	    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
-	}
-
-	/* Reset the PIP */
-	{
-	    cvmx_pip_sft_rst_t pip_sft_rst;
-	    pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
-	    pip_sft_rst.s.rst = 1;
-	    cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
-	}
     }
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-ixf18201.c b/sys/contrib/octeon-sdk/cvmx-ixf18201.c
new file mode 100644
index 0000000..8f423d8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ixf18201.c
@@ -0,0 +1,362 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+/* This file contains support functions for the Cortina IXF18201 SPI->XAUI dual
+** MAC.  The IXF18201 has dual SPI and dual XAUI interfaces to provide 2 10 gigabit
+** interfaces.
+** This file supports the EBT5810 evaluation board.  To support a different board,
+** the 16 bit read/write functions would need to be customized for that board, and the
+** IXF18201 may need to be initialized differently as well.
+**
+** The IXF18201 and Octeon are configured for 2 SPI channels per interface (ports 0/1, and 16/17).
+** Ports 0 and 16 are the ports that are connected to the XAUI MACs (which are connected to the SFP+ modules)
+** Ports 1 and 17 are connected to the hairpin loopback port on the IXF SPI interface.  All packets sent out
+** of these ports are looped back the same port they were sent on.  The loopback ports are always enabled.
+**
+** The MAC address filtering on the IXF is not enabled.  Link up/down events are not detected, only SPI status
+** is monitored by default, which is independent of the XAUI/SFP+ link status.
+**
+**
+*/
+#include "cvmx.h"
+#include "cvmx-swap.h"
+
+
+
+
+
+#define PAL_BASE            (1ull << 63 | 0x1d030000)
+#define IXF_ADDR_HI         (PAL_BASE + 0xa)
+#define IXF_ADDR_LO         (PAL_BASE + 0xb)
+#define IXF_ADDR_16         IXF_ADDR_HI         /* 16 bit access */
+
+#define IXF_WR_DATA_HI      (PAL_BASE + 0xc)
+#define IXF_WR_DATA_LO      (PAL_BASE + 0xd)
+#define IXF_WR_DATA_16      IXF_WR_DATA_HI
+
+#define IXF_RD_DATA_HI      (PAL_BASE + 0x10)
+#define IXF_RD_DATA_LO      (PAL_BASE + 0x11)
+#define IXF_RD_DATA_16      IXF_RD_DATA_HI
+
+#define IXF_TRANS_TYPE      (PAL_BASE + 0xe)
+#define IXF_TRANS_STATUS    (PAL_BASE + 0xf)
+
+
+uint16_t cvmx_ixf18201_read16(uint16_t reg_addr)
+{
+    cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
+    cvmx_write64_uint8(IXF_TRANS_TYPE, 1);  // Do read
+    cvmx_wait(800000);
+
+    /* Read result */
+    return(cvmx_read64_uint16(IXF_RD_DATA_16));
+}
+
+void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data)
+{
+    cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
+    cvmx_write64_uint16(IXF_WR_DATA_16, data);
+    cvmx_write64_uint8(IXF_TRANS_TYPE, 0);
+    cvmx_wait(800000);
+}
+
+
+
+uint32_t cvmx_ixf18201_read32(uint16_t reg_addr)
+{
+    uint32_t hi, lo;
+
+    if (reg_addr & 0x1)
+    {
+        return(0xdeadbeef);
+    }
+    lo = cvmx_ixf18201_read16(reg_addr);
+    hi = cvmx_ixf18201_read16(reg_addr + 1);
+    return((hi << 16) | lo);
+}
+void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data)
+{
+    uint16_t hi, lo;
+
+    if (reg_addr & 0x1)
+    {
+        return;
+    }
+    lo = data & 0xFFFF;
+    hi = data >> 16;
+    cvmx_ixf18201_write16(reg_addr, lo);
+    cvmx_ixf18201_write16(reg_addr + 1, hi);
+
+}
+
+
+#define IXF_REG_MDI_CMD_ADDR1   0x310E
+#define IXF_REG_MDI_RD_WR1      0x3110
+void cvmx_ixf18201_mii_write(int mii_addr, int mmd, uint16_t reg, uint16_t val)
+{
+    uint32_t cmd_val = 0;
+
+
+    cmd_val = reg;
+    cmd_val |= 0x0 << 26;  // Set address operation
+    cmd_val |= (mii_addr & 0x1f) << 21;  // Set PHY addr
+    cmd_val |= (mmd & 0x1f) << 16;  // Set MMD
+    cmd_val |= 1 << 30;   // Do operation
+    cmd_val |= 1 << 31;   // enable in progress bit
+
+
+
+    /* Set up address */
+    cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
+
+    while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
+        ;  /* Wait for operation to complete */
+
+
+    cvmx_ixf18201_write32(IXF_REG_MDI_RD_WR1, val);
+
+    /* Do read operation */
+    cmd_val = 0;
+    cmd_val |= 0x1 << 26;  // Set write operation
+    cmd_val |= (mii_addr & 0x1f) << 21;  // Set PHY addr
+    cmd_val |= (mmd & 0x1f) << 16;  // Set MMD
+    cmd_val |= 1 << 30;   // Do operation
+    cmd_val |= 1 << 31;   // enable in progress bit
+    cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
+
+    while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
+        ;  /* Wait for operation to complete */
+
+
+}
+
+
+int cvmx_ixf18201_mii_read(int mii_addr, int mmd, uint16_t reg)
+{
+    uint32_t cmd_val = 0;
+
+
+    cmd_val = reg;
+    cmd_val |= 0x0 << 26;  // Set address operation
+    cmd_val |= (mii_addr & 0x1f) << 21;  // Set PHY addr
+    cmd_val |= (mmd & 0x1f) << 16;  // Set MMD
+    cmd_val |= 1 << 30;   // Do operation
+    cmd_val |= 1 << 31;   // enable in progress bit
+
+
+
+    /* Set up address */
+    cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
+
+    while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
+        ;  /* Wait for operation to complete */
+
+    /* Do read operation */
+    cmd_val = 0;
+    cmd_val |= 0x3 << 26;  // Set read operation
+    cmd_val |= (mii_addr & 0x1f) << 21;  // Set PHY addr
+    cmd_val |= (mmd & 0x1f) << 16;  // Set MMD
+    cmd_val |= 1 << 30;   // Do operation
+    cmd_val |= 1 << 31;   // enable in progress bit
+    cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
+
+    while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
+        ;  /* Wait for operation to complete */
+
+    cmd_val = cvmx_ixf18201_read32(IXF_REG_MDI_RD_WR1);
+
+    return(cmd_val >> 16);
+
+}
+
+
+
+int cvmx_ixf18201_init(void)
+{
+    int index;  /* For indexing the two 'ports' on ixf */
+    int offset;
+
+    /* Reset IXF, and take all blocks out of reset */
+
+/*
+Initializing...
+PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
+PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
+PP0:~CONSOLE->  **** LLM201(Lochlomond) Driver loaded ****
+PP0:~CONSOLE->  LLM201 Driver - Released on Tue Aug 28 09:51:30 2007.
+PP0:~CONSOLE-> retval is: 0
+PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
+PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
+PP0:~CONSOLE-> Brought all blocks out of reset
+PP0:~CONSOLE-> Getting default config.
+*/
+
+
+    cvmx_ixf18201_write16(0x0003, 0x0001);
+    cvmx_ixf18201_write16(0x0003, 0);
+
+    /*
+PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4014, new: 0x4010
+PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4010, new: 0x4014
+PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x01ff, new: 0x0140
+PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x007f, new: 0x0000
+    */
+    cvmx_ixf18201_write16(0x0000, 0x4010);
+    cvmx_ixf18201_write16(0x0000, 0x4014);
+    cvmx_ixf18201_write16(0x0004, 0x0140);
+    cvmx_ixf18201_write16(0x0009, 0);
+
+
+    /*
+PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x0000, new: 0x000f
+PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0000, new: 0x0004
+PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0004, new: 0x0006
+PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x000f, new: 0x00f0
+PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0006, new: 0x0040
+PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0040, new: 0x0060
+    */
+    // skip GPIO, 0xe/0xf
+
+
+    /*
+PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x57fb, new: 0x7f7b
+PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x57fb, new: 0x7f7b
+PP0:~CONSOLE-> Changing register value, addr 0x3005, old: 0x8010, new: 0x0040
+PP0:~CONSOLE-> Changing register value, addr 0x3006, old: 0x061a, new: 0x0000
+PP0:~CONSOLE-> Changing register value, addr 0x3505, old: 0x8010, new: 0x0040
+PP0:~CONSOLE-> Changing register value, addr 0x3506, old: 0x061a, new: 0x0000
+    */
+    for (index = 0; index < 2;index++ )
+    {
+        offset = 0x500 * index;
+        cvmx_ixf18201_write32(0x3100 + offset, 0x47f7b);
+        cvmx_ixf18201_write16(0x3005 + offset, 0x0040);
+        cvmx_ixf18201_write16(0x3006 + offset, 0);
+    }
+
+    /*PP0:~CONSOLE->   *** SPI soft reset ***, block id: 0
+PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf980, new: 0xf9c0
+PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0xa6f0, new: 0x36f0
+PP0:~CONSOLE-> Changing register value, addr 0x3000, old: 0x0080, new: 0x0060
+PP0:~CONSOLE-> Changing register value, addr 0x3002, old: 0x0200, new: 0x0040
+PP0:~CONSOLE-> Changing register value, addr 0x3003, old: 0x0100, new: 0x0000
+PP0:~CONSOLE-> Changing register value, addr 0x30c2, old: 0x0080, new: 0x0060
+PP0:~CONSOLE-> Changing register value, addr 0x300a, old: 0x0800, new: 0x0000
+PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf9c0, new: 0x89c0
+PP0:~CONSOLE-> Changing register value, addr 0x3016, old: 0x0000, new: 0x0010
+PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x36f0, new: 0x3610
+PP0:~CONSOLE-> Changing register value, addr 0x3012, old: 0x0000, new: 0x0010
+PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0x89c0, new: 0x8980
+PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x3610, new: 0xa210
+PP0:~CONSOLE->
+
+    */
+
+
+    for (index = 0; index < 2;index++ )
+    {
+        offset = 0x500 * index;
+        int cal_len_min_1 = 0;  /* Calendar length -1.  Must match number
+                                ** of ports configured for interface.*/
+        cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
+        cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
+        cvmx_ixf18201_write16(0x3000 + offset, 0x0060);
+        cvmx_ixf18201_write16(0x3002 + offset, 0x0040);
+        cvmx_ixf18201_write16(0x3003 + offset, 0x0000);
+        cvmx_ixf18201_write16(0x30c2 + offset, 0x0060);
+        cvmx_ixf18201_write16(0x300a + offset, 0x0000);
+        cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
+        cvmx_ixf18201_write16(0x3016 + offset, 0x0010);
+        cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
+        cvmx_ixf18201_write16(0x3012 + offset, 0x0010);
+        cvmx_ixf18201_write16(0x3007 + offset, 0x8180 | (cal_len_min_1 << 11));
+        cvmx_ixf18201_write16(0x3008 + offset, 0xa200 | (cal_len_min_1 << 4));
+
+        cvmx_ixf18201_write16(0x3090 + offset, 0x0301);  /* Enable hairpin loopback */
+    }
+
+
+
+    /*
+PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x0140, new: 0x1fff
+PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x0000, new: 0x007f
+PP0:~CONSOLE-> Changing register value, addr 0x310b, old: 0x0004, new: 0xffff
+PP0:~CONSOLE-> Changing register value, addr 0x310a, old: 0x7f7b, new: 0xffff
+
+    */
+
+    cvmx_ixf18201_write16(0x0004, 0x1fff);
+    cvmx_ixf18201_write16(0x0009, 0x007f);
+#if 0
+    /* MDI autoscan */
+    cvmx_ixf18201_write16(0x310b, 0xffff);
+    cvmx_ixf18201_write16(0x310a, 0xffff);
+#endif
+
+
+    /*
+    *** 32 bit register, trace only captures part of it...
+PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x7f7b, new: 0x7f78
+PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x7f7b, new: 0x7f78
+    */
+
+    for (index = 0; index < 2;index++ )
+    {
+        offset = 0x500 * index;
+        cvmx_ixf18201_write32(0x3100 + offset, 0x47f7c); /* Also enable jumbo frames */
+        /* Set max packet size to 9600 bytes, max supported by IXF18201 */
+        cvmx_ixf18201_write32(0x3114 + offset, 0x25800000);
+    }
+
+
+    cvmx_wait(100000000);
+
+    /* Now reset the PCS blocks in the phy.  This seems to be required after
+    ** bringing up the Cortina. */
+    cvmx_ixf18201_mii_write(1, 3, 0, 0x8000);
+    cvmx_ixf18201_mii_write(5, 3, 0, 0x8000);
+
+
+    return 1;
+
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-ixf18201.h b/sys/contrib/octeon-sdk/cvmx-ixf18201.h
new file mode 100644
index 0000000..d387f5e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ixf18201.h
@@ -0,0 +1,112 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+#ifndef __CVMX_IXF18201_H__
+#define __CVMX_IXF18201_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize the IXF18201 SPI<->XAUI MAC.
+ * @return 1 on success
+ *         0 on failure
+ */
+int cvmx_ixf18201_init(void);
+
+/**
+ * Read a 16 bit register from the IXF18201
+ *
+ * @param reg_addr Register address
+ *
+ * @return 16 bit register value
+ */
+uint16_t cvmx_ixf18201_read16(uint16_t reg_addr);
+/**
+ * Write a 16 bit IXF18201 register
+ *
+ * @param reg_addr Register address
+ * @param data Value to write
+ *
+ */
+void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data);
+/**
+ * Write a 16 bit IXF18201 register
+ *
+ * @param reg_addr Register address (must be 4 byte aligned)
+ *
+ * @return 32 bit register value
+ */
+uint32_t cvmx_ixf18201_read32(uint16_t reg_addr);
+/**
+ * Write a 32 bit IXF18201 register
+ *
+ * @param reg_addr Register address (must be 4 byte aligned)
+ * @param data Value to write
+ *
+ */
+void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data);
+
+/**
+ * Performs an MII clause 45 write using the MII block in IXF18201.
+ *
+ * @param mii_addr Device MII address
+ * @param mmd      MMD address (block within device)
+ * @param reg      Register address
+ * @param val      Value to write
+ */
+void cvmx_ixf18201_mii_write(int mii_addr, int mmd, uint16_t reg, uint16_t val);
+/**
+ * Performs an MII clause 45 read using the MII block in IXF18201.
+ *
+ * @param mii_addr Device MII address
+ * @param mmd      MMD address (block within device)
+ * @param reg      Register address
+ * @return  register value read from device
+ */
+int cvmx_ixf18201_mii_read(int mii_addr, int mmd, uint16_t reg);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /*  __CVMX_IXF18201_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-key-defs.h b/sys/contrib/octeon-sdk/cvmx-key-defs.h
new file mode 100644
index 0000000..cf22a0c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-key-defs.h
@@ -0,0 +1,254 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-key-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon key.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_KEY_TYPEDEFS_H__
+#define __CVMX_KEY_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
+static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180020000018ull);
+}
+#else
+#define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180020000010ull);
+}
+#else
+#define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
+static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180020000008ull);
+}
+#else
+#define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
+static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180020000000ull);
+}
+#else
+#define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
+#endif
+
+/**
+ * cvmx_key_bist_reg
+ *
+ * KEY_BIST_REG = KEY's BIST Status Register
+ *
+ * The KEY's BIST status for memories.
+ */
+union cvmx_key_bist_reg
+{
+	uint64_t u64;
+	struct cvmx_key_bist_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t rrc                          : 1;  /**< RRC bist status. */
+	uint64_t mem1                         : 1;  /**< MEM - 1 bist status. */
+	uint64_t mem0                         : 1;  /**< MEM - 0 bist status. */
+#else
+	uint64_t mem0                         : 1;
+	uint64_t mem1                         : 1;
+	uint64_t rrc                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_key_bist_reg_s            cn38xx;
+	struct cvmx_key_bist_reg_s            cn38xxp2;
+	struct cvmx_key_bist_reg_s            cn56xx;
+	struct cvmx_key_bist_reg_s            cn56xxp1;
+	struct cvmx_key_bist_reg_s            cn58xx;
+	struct cvmx_key_bist_reg_s            cn58xxp1;
+	struct cvmx_key_bist_reg_s            cn63xx;
+	struct cvmx_key_bist_reg_s            cn63xxp1;
+};
+typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
+
+/**
+ * cvmx_key_ctl_status
+ *
+ * KEY_CTL_STATUS = KEY's Control/Status Register
+ *
+ * The KEY's interrupt enable register.
+ */
+union cvmx_key_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_key_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t mem1_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 13:7 of this field, for FPF
+                                                         FIFO 1. */
+	uint64_t mem0_err                     : 7;  /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 0. */
+#else
+	uint64_t mem0_err                     : 7;
+	uint64_t mem1_err                     : 7;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_key_ctl_status_s          cn38xx;
+	struct cvmx_key_ctl_status_s          cn38xxp2;
+	struct cvmx_key_ctl_status_s          cn56xx;
+	struct cvmx_key_ctl_status_s          cn56xxp1;
+	struct cvmx_key_ctl_status_s          cn58xx;
+	struct cvmx_key_ctl_status_s          cn58xxp1;
+	struct cvmx_key_ctl_status_s          cn63xx;
+	struct cvmx_key_ctl_status_s          cn63xxp1;
+};
+typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
+
+/**
+ * cvmx_key_int_enb
+ *
+ * KEY_INT_ENB = KEY's Interrupt Enable
+ *
+ * The KEY's interrupt enable register.
+ */
+union cvmx_key_int_enb
+{
+	uint64_t u64;
+	struct cvmx_key_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ked1_dbe                     : 1;  /**< When set (1) and bit 3 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+	uint64_t ked1_sbe                     : 1;  /**< When set (1) and bit 2 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+	uint64_t ked0_dbe                     : 1;  /**< When set (1) and bit 1 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+	uint64_t ked0_sbe                     : 1;  /**< When set (1) and bit 0 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+#else
+	uint64_t ked0_sbe                     : 1;
+	uint64_t ked0_dbe                     : 1;
+	uint64_t ked1_sbe                     : 1;
+	uint64_t ked1_dbe                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_key_int_enb_s             cn38xx;
+	struct cvmx_key_int_enb_s             cn38xxp2;
+	struct cvmx_key_int_enb_s             cn56xx;
+	struct cvmx_key_int_enb_s             cn56xxp1;
+	struct cvmx_key_int_enb_s             cn58xx;
+	struct cvmx_key_int_enb_s             cn58xxp1;
+	struct cvmx_key_int_enb_s             cn63xx;
+	struct cvmx_key_int_enb_s             cn63xxp1;
+};
+typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
+
+/**
+ * cvmx_key_int_sum
+ *
+ * KEY_INT_SUM = KEY's Interrupt Summary Register
+ *
+ * Contains the diffrent interrupt summary bits of the KEY.
+ */
+union cvmx_key_int_sum
+{
+	uint64_t u64;
+	struct cvmx_key_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ked1_dbe                     : 1;
+	uint64_t ked1_sbe                     : 1;
+	uint64_t ked0_dbe                     : 1;
+	uint64_t ked0_sbe                     : 1;
+#else
+	uint64_t ked0_sbe                     : 1;
+	uint64_t ked0_dbe                     : 1;
+	uint64_t ked1_sbe                     : 1;
+	uint64_t ked1_dbe                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_key_int_sum_s             cn38xx;
+	struct cvmx_key_int_sum_s             cn38xxp2;
+	struct cvmx_key_int_sum_s             cn56xx;
+	struct cvmx_key_int_sum_s             cn56xxp1;
+	struct cvmx_key_int_sum_s             cn58xx;
+	struct cvmx_key_int_sum_s             cn58xxp1;
+	struct cvmx_key_int_sum_s             cn63xx;
+	struct cvmx_key_int_sum_s             cn63xxp1;
+};
+typedef union cvmx_key_int_sum cvmx_key_int_sum_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-key.h b/sys/contrib/octeon-sdk/cvmx-key.h
index 791006e..c4754d8 100644
--- a/sys/contrib/octeon-sdk/cvmx-key.h
+++ b/sys/contrib/octeon-sdk/cvmx-key.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -48,7 +50,7 @@
  * 8k on chip that is inaccessible from off chip. It can
  * also be cleared using an external hardware pin.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -104,7 +106,7 @@ static inline void cvmx_key_write(uint64_t address, uint64_t value)
 }
 
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-key-defs.h */
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c-defs.h b/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
new file mode 100644
index 0000000..f0dd6d4
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
@@ -0,0 +1,5889 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-l2c-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon l2c.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_L2C_TYPEDEFS_H__
+#define __CVMX_L2C_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_BIG_CTL CVMX_L2C_BIG_CTL_FUNC()
+static inline uint64_t CVMX_L2C_BIG_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_BIG_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800030ull);
+}
+#else
+#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_BST CVMX_L2C_BST_FUNC()
+static inline uint64_t CVMX_L2C_BST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_BST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007F8ull);
+}
+#else
+#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC()
+static inline uint64_t CVMX_L2C_BST0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_BST0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
+}
+#else
+#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC()
+static inline uint64_t CVMX_L2C_BST1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_BST1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
+}
+#else
+#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC()
+static inline uint64_t CVMX_L2C_BST2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_BST2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
+}
+#else
+#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_BST_MEMX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_BST_MEMX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080C007F8ull);
+}
+#else
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_BST_TDTX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_BST_TDTX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A007F0ull);
+}
+#else
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_BST_TTGX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_BST_TTGX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A007F8ull);
+}
+#else
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
+static inline uint64_t CVMX_L2C_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000000ull);
+}
+#else
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_COP0_MAPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535) || ((offset >= 16128) && (offset <= 16383))))))
+		cvmx_warn("CVMX_L2C_COP0_MAPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8;
+}
+#else
+#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_CTL CVMX_L2C_CTL_FUNC()
+static inline uint64_t CVMX_L2C_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800000ull);
+}
+#else
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC()
+static inline uint64_t CVMX_L2C_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000030ull);
+}
+#else
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC()
+static inline uint64_t CVMX_L2C_DUT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_DUT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000050ull);
+}
+#else
+#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_DUT_MAPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535)))))
+		cvmx_warn("CVMX_L2C_DUT_MAPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8;
+}
+#else
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_ERR_TDTX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_ERR_TDTX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A007E0ull);
+}
+#else
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_ERR_TTGX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_ERR_TTGX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A007E8ull);
+}
+#else
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_ERR_VBFX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_ERR_VBFX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080C007F0ull);
+}
+#else
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_ERR_XMC CVMX_L2C_ERR_XMC_FUNC()
+static inline uint64_t CVMX_L2C_ERR_XMC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_ERR_XMC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007D8ull);
+}
+#else
+#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000C8ull);
+}
+#else
+#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000D0ull);
+}
+#else
+#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC()
+static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000100ull);
+}
+#else
+#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_INT_ENA CVMX_L2C_INT_ENA_FUNC()
+static inline uint64_t CVMX_L2C_INT_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_INT_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800020ull);
+}
+#else
+#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_INT_REG CVMX_L2C_INT_REG_FUNC()
+static inline uint64_t CVMX_L2C_INT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_INT_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800018ull);
+}
+#else
+#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC()
+static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000F8ull);
+}
+#else
+#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_IOCX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_IOCX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800420ull);
+}
+#else
+#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_IORX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_IORX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800428ull);
+}
+#else
+#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC()
+static inline uint64_t CVMX_L2C_LCKBASE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LCKBASE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000058ull);
+}
+#else
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC()
+static inline uint64_t CVMX_L2C_LCKOFF_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LCKOFF not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000060ull);
+}
+#else
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC()
+static inline uint64_t CVMX_L2C_LFB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LFB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000038ull);
+}
+#else
+#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC()
+static inline uint64_t CVMX_L2C_LFB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LFB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000040ull);
+}
+#else
+#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC()
+static inline uint64_t CVMX_L2C_LFB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LFB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000048ull);
+}
+#else
+#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC()
+static inline uint64_t CVMX_L2C_LFB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_LFB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000B8ull);
+}
+#else
+#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC()
+static inline uint64_t CVMX_L2C_OOB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_OOB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000D8ull);
+}
+#else
+#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC()
+static inline uint64_t CVMX_L2C_OOB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000E0ull);
+}
+#else
+#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC()
+static inline uint64_t CVMX_L2C_OOB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000E8ull);
+}
+#else
+#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC()
+static inline uint64_t CVMX_L2C_OOB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000F0ull);
+}
+#else
+#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
+#endif
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC()
+static inline uint64_t CVMX_L2C_PFCTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_PFCTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000090ull);
+}
+#else
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_PFCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC()
+static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800000C0ull);
+}
+#else
+#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_QOS_IOBX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_QOS_IOBX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080880200ull);
+}
+#else
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_QOS_PPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_L2C_QOS_PPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_QOS_WGT CVMX_L2C_QOS_WGT_FUNC()
+static inline uint64_t CVMX_L2C_QOS_WGT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_QOS_WGT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800008ull);
+}
+#else
+#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_RSCX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_RSCX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800410ull);
+}
+#else
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_RSDX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_RSDX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800418ull);
+}
+#else
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
+static inline uint64_t CVMX_L2C_SPAR0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_SPAR0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000068ull);
+}
+#else
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC()
+static inline uint64_t CVMX_L2C_SPAR1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000070ull);
+}
+#else
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC()
+static inline uint64_t CVMX_L2C_SPAR2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000078ull);
+}
+#else
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC()
+static inline uint64_t CVMX_L2C_SPAR3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000080ull);
+}
+#else
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC()
+static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2C_SPAR4 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000088ull);
+}
+#else
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_ECC0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_ECC0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00018ull);
+}
+#else
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_ECC1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_ECC1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00020ull);
+}
+#else
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_IEN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_IEN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00000ull);
+}
+#else
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_INT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_INT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00028ull);
+}
+#else
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_PFC0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_PFC0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00400ull);
+}
+#else
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_PFC1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_PFC1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00408ull);
+}
+#else
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_PFC2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_PFC2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00410ull);
+}
+#else
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_PFC3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_PFC3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00418ull);
+}
+#else
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_PRF(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_PRF(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00008ull);
+}
+#else
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_TADX_TAG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_TADX_TAG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080A00010ull);
+}
+#else
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_VER_ID CVMX_L2C_VER_ID_FUNC()
+static inline uint64_t CVMX_L2C_VER_ID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_VER_ID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007E0ull);
+}
+#else
+#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_VER_IOB CVMX_L2C_VER_IOB_FUNC()
+static inline uint64_t CVMX_L2C_VER_IOB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_VER_IOB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007F0ull);
+}
+#else
+#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_VER_MSC CVMX_L2C_VER_MSC_FUNC()
+static inline uint64_t CVMX_L2C_VER_MSC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_VER_MSC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007D0ull);
+}
+#else
+#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_VER_PP CVMX_L2C_VER_PP_FUNC()
+static inline uint64_t CVMX_L2C_VER_PP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_VER_PP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800808007E8ull);
+}
+#else
+#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_VIRTID_IOBX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_VIRTID_IOBX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800808C0200ull);
+}
+#else
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_VIRTID_PPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_L2C_VIRTID_PPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_VRT_CTL CVMX_L2C_VRT_CTL_FUNC()
+static inline uint64_t CVMX_L2C_VRT_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_VRT_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800010ull);
+}
+#else
+#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_VRT_MEMX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1023)))))
+		cvmx_warn("CVMX_L2C_VRT_MEMX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8;
+}
+#else
+#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_WPAR_IOBX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_WPAR_IOBX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080840200ull);
+}
+#else
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_WPAR_PPX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_L2C_WPAR_PPX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_XMCX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_XMCX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800400ull);
+}
+#else
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2C_XMC_CMD CVMX_L2C_XMC_CMD_FUNC()
+static inline uint64_t CVMX_L2C_XMC_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_L2C_XMC_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080800028ull);
+}
+#else
+#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_L2C_XMDX_PFC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_L2C_XMDX_PFC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180080800408ull);
+}
+#else
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+#endif
+
+/**
+ * cvmx_l2c_big_ctl
+ *
+ * L2C_BIG_CTL = L2C Big memory control register
+ *
+ *
+ * Notes:
+ * (1) BIGRD interrupts can occur during normal operation as the PP's are allowed to prefetch to
+ *     non-existent memory locations.  Therefore, BIGRD is for informational purposes only.
+ *
+ * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB, and L2C_VER_MSC will be
+ *     loaded just like a store which is blocked by VRTWR.  Additionally, L2C_ERR_XMC will be loaded.
+ */
+union cvmx_l2c_big_ctl
+{
+	uint64_t u64;
+	struct cvmx_l2c_big_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t maxdram                      : 4;  /**< Amount of configured DRAM
+                                                             0 = reserved
+                                                             1 = 512MB
+                                                             2 = 1GB
+                                                             3 = 2GB
+                                                             4 = 4GB
+                                                             5 = 8GB
+                                                             6 = 16GB
+                                                             7 = 32GB
+                                                             8 = 64GB     (**reserved in 63xx**)
+                                                             9 = 128GB    (**reserved in 63xx**)
+                                                             10-15 reserved
+                                                         Violations of this limit causes
+                                                         L2C to set L2C_INT_REG[BIGRD/BIGWR]. */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t disable                      : 1;  /**< When set, disables the BIGWR/BIGRD logic completely
+                                                         and reverts HOLEWR to 63xx pass 1.x behavior.
+                                                         When clear, BIGWR and HOLEWR block stores in the same
+                                                         same manner as the VRT logic, and BIGRD is reported. */
+#else
+	uint64_t disable                      : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t maxdram                      : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_l2c_big_ctl_s             cn63xx;
+};
+typedef union cvmx_l2c_big_ctl cvmx_l2c_big_ctl_t;
+
+/**
+ * cvmx_l2c_bst
+ *
+ * L2C_BST = L2C BIST Status
+ *
+ */
+union cvmx_l2c_bst
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t dutfl                        : 6;  /**< BIST failure status for PP0-5 DUT */
+	uint64_t reserved_17_31               : 15;
+	uint64_t ioccmdfl                     : 1;  /**< BIST failure status for IOCCMD */
+	uint64_t reserved_13_15               : 3;
+	uint64_t iocdatfl                     : 1;  /**< BIST failure status for IOCDAT */
+	uint64_t reserved_9_11                : 3;
+	uint64_t dutresfl                     : 1;  /**< BIST failure status for DUTRES */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t vrtfl                        : 1;  /**< BIST failure status for VRT0 */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t tdffl                        : 1;  /**< BIST failure status for TDF0 */
+#else
+	uint64_t tdffl                        : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t vrtfl                        : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dutresfl                     : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t iocdatfl                     : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t ioccmdfl                     : 1;
+	uint64_t reserved_17_31               : 15;
+	uint64_t dutfl                        : 6;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_l2c_bst_s                 cn63xx;
+	struct cvmx_l2c_bst_s                 cn63xxp1;
+};
+typedef union cvmx_l2c_bst cvmx_l2c_bst_t;
+
+/**
+ * cvmx_l2c_bst0
+ *
+ * L2C_BST0 = L2C BIST 0 CTL/STAT
+ *
+ */
+union cvmx_l2c_bst0
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t dtbnk                        : 1;  /**< DuTag Bank#
+                                                         When DT=1(BAD), this field provides additional information
+                                                         about which DuTag Bank (0/1) failed. */
+	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t dtcnt                        : 13; /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
+                                                         [11:10]: j (Pattern# 1 of 4)
+                                                         [9:4]:   k (DT Index 1 of 64)
+                                                         [3:0]:   l (DT# 1 of 16 DTs) */
+	uint64_t dt                           : 1;  /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stin_msk                     : 1;  /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t wlb_dat                      : 4;  /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t wlb_dat                      : 4;
+	uint64_t stin_msk                     : 1;
+	uint64_t dt                           : 1;
+	uint64_t dtcnt                        : 13;
+	uint64_t wlb_msk                      : 4;
+	uint64_t dtbnk                        : 1;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_l2c_bst0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_15_18               : 4;
+	uint64_t dtcnt                        : 9;  /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [8]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [7:6]: j (Pattern# 1 of 4)
+                                                         [5:0]: k (DT Index 1 of 64) */
+	uint64_t dt                           : 1;  /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_4_4                 : 1;
+	uint64_t wlb_dat                      : 4;  /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t wlb_dat                      : 4;
+	uint64_t reserved_4_4                 : 1;
+	uint64_t dt                           : 1;
+	uint64_t dtcnt                        : 9;
+	uint64_t reserved_15_18               : 4;
+	uint64_t wlb_msk                      : 4;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_bst0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_16_18               : 3;
+	uint64_t dtcnt                        : 10; /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [8:7]: j (Pattern# 1 of 4)
+                                                         [6:1]: k (DT Index 1 of 64)
+                                                         [0]:   l (DT# 1 of 2 DTs) */
+	uint64_t dt                           : 1;  /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stin_msk                     : 1;  /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t wlb_dat                      : 4;  /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t wlb_dat                      : 4;
+	uint64_t stin_msk                     : 1;
+	uint64_t dt                           : 1;
+	uint64_t dtcnt                        : 10;
+	uint64_t reserved_16_18               : 3;
+	uint64_t wlb_msk                      : 4;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_bst0_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t dtcnt                        : 13; /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
+                                                         [11:10]: j (Pattern# 1 of 4)
+                                                         [9:4]:   k (DT Index 1 of 64)
+                                                         [3:0]:   l (DT# 1 of 16 DTs) */
+	uint64_t dt                           : 1;  /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stin_msk                     : 1;  /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t wlb_dat                      : 4;  /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t wlb_dat                      : 4;
+	uint64_t stin_msk                     : 1;
+	uint64_t dt                           : 1;
+	uint64_t dtcnt                        : 13;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn38xx;
+	struct cvmx_l2c_bst0_cn38xx           cn38xxp2;
+	struct cvmx_l2c_bst0_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t dtbnk                        : 1;  /**< DuTag Bank#
+                                                         When DT=1(BAD), this field provides additional information
+                                                         about which DuTag Bank (0/1) failed. */
+	uint64_t wlb_msk                      : 4;  /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_16_18               : 3;
+	uint64_t dtcnt                        : 10; /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [8:7]: j (Pattern# 1 of 4)
+                                                         [6:1]: k (DT Index 1 of 64)
+                                                         [0]:   l (DT# 1 of 2 DTs) */
+	uint64_t dt                           : 1;  /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t stin_msk                     : 1;  /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t wlb_dat                      : 4;  /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t wlb_dat                      : 4;
+	uint64_t stin_msk                     : 1;
+	uint64_t dt                           : 1;
+	uint64_t dtcnt                        : 10;
+	uint64_t reserved_16_18               : 3;
+	uint64_t wlb_msk                      : 4;
+	uint64_t dtbnk                        : 1;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_bst0_cn50xx           cn52xx;
+	struct cvmx_l2c_bst0_cn50xx           cn52xxp1;
+	struct cvmx_l2c_bst0_s                cn56xx;
+	struct cvmx_l2c_bst0_s                cn56xxp1;
+	struct cvmx_l2c_bst0_s                cn58xx;
+	struct cvmx_l2c_bst0_s                cn58xxp1;
+};
+typedef union cvmx_l2c_bst0 cvmx_l2c_bst0_t;
+
+/**
+ * cvmx_l2c_bst1
+ *
+ * L2C_BST1 = L2C BIST 1 CTL/STAT
+ *
+ */
+union cvmx_l2c_bst1
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t l2t                          : 9;  /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t l2t                          : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_bst1_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t vwdf                         : 4;  /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t lrf                          : 2;  /**< Bist Results for LRF RAMs (PLC+ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vab_vwcf                     : 1;  /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_5_8                 : 4;
+	uint64_t l2t                          : 5;  /**< Bist Results for L2T (USE+4SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t l2t                          : 5;
+	uint64_t reserved_5_8                 : 4;
+	uint64_t vab_vwcf                     : 1;
+	uint64_t lrf                          : 2;
+	uint64_t vwdf                         : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_bst1_cn30xx           cn31xx;
+	struct cvmx_l2c_bst1_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t vwdf                         : 4;  /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t lrf                          : 2;  /**< Bist Results for LRF RAMs (PLC+ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vab_vwcf                     : 1;  /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t l2t                          : 9;  /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t l2t                          : 9;
+	uint64_t vab_vwcf                     : 1;
+	uint64_t lrf                          : 2;
+	uint64_t vwdf                         : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_l2c_bst1_cn38xx           cn38xxp2;
+	struct cvmx_l2c_bst1_cn38xx           cn50xx;
+	struct cvmx_l2c_bst1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t plc2                         : 1;  /**< Bist Results for PLC2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t plc1                         : 1;  /**< Bist Results for PLC1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t plc0                         : 1;  /**< Bist Results for PLC0 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vwdf                         : 4;  /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_11_11               : 1;
+	uint64_t ilc                          : 1;  /**< Bist Results for ILC RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vab_vwcf                     : 1;  /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t l2t                          : 9;  /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t l2t                          : 9;
+	uint64_t vab_vwcf                     : 1;
+	uint64_t ilc                          : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t vwdf                         : 4;
+	uint64_t plc0                         : 1;
+	uint64_t plc1                         : 1;
+	uint64_t plc2                         : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn52xx;
+	struct cvmx_l2c_bst1_cn52xx           cn52xxp1;
+	struct cvmx_l2c_bst1_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t plc2                         : 1;  /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t plc1                         : 1;  /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t plc0                         : 1;  /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ilc                          : 1;  /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vwdf1                        : 4;  /**< Bist Results for VWDF1 RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vwdf0                        : 4;  /**< Bist Results for VWDF0 RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t vab_vwcf1                    : 1;  /**< Bist Results for VAB VWCF1_MEM */
+	uint64_t reserved_10_10               : 1;
+	uint64_t vab_vwcf0                    : 1;  /**< Bist Results for VAB VWCF0_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t l2t                          : 9;  /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t l2t                          : 9;
+	uint64_t vab_vwcf0                    : 1;
+	uint64_t reserved_10_10               : 1;
+	uint64_t vab_vwcf1                    : 1;
+	uint64_t vwdf0                        : 4;
+	uint64_t vwdf1                        : 4;
+	uint64_t ilc                          : 1;
+	uint64_t plc0                         : 1;
+	uint64_t plc1                         : 1;
+	uint64_t plc2                         : 1;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn56xx;
+	struct cvmx_l2c_bst1_cn56xx           cn56xxp1;
+	struct cvmx_l2c_bst1_cn38xx           cn58xx;
+	struct cvmx_l2c_bst1_cn38xx           cn58xxp1;
+};
+typedef union cvmx_l2c_bst1 cvmx_l2c_bst1_t;
+
+/**
+ * cvmx_l2c_bst2
+ *
+ * L2C_BST2 = L2C BIST 2 CTL/STAT
+ *
+ */
+union cvmx_l2c_bst2
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_4_11                : 8;
+	uint64_t ipcbst                       : 1;  /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+	uint64_t picbst                       : 1;  /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+	uint64_t xrdmsk                       : 1;  /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t xrddat                       : 1;  /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t xrddat                       : 1;
+	uint64_t xrdmsk                       : 1;
+	uint64_t picbst                       : 1;
+	uint64_t ipcbst                       : 1;
+	uint64_t reserved_4_11                : 8;
+	uint64_t mrb                          : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_l2c_bst2_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rmdf                         : 4;  /**< Bist Results for RMDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t ipcbst                       : 1;  /**< Bist Results for RFB IPC RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t xrdmsk                       : 1;  /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t xrddat                       : 1;  /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t xrddat                       : 1;
+	uint64_t xrdmsk                       : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ipcbst                       : 1;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t rmdf                         : 4;
+	uint64_t mrb                          : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_bst2_cn30xx           cn31xx;
+	struct cvmx_l2c_bst2_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rmdf                         : 4;  /**< Bist Results for RMDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rhdf                         : 4;  /**< Bist Results for RHDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ipcbst                       : 1;  /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+	uint64_t picbst                       : 1;  /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+	uint64_t xrdmsk                       : 1;  /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t xrddat                       : 1;  /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t xrddat                       : 1;
+	uint64_t xrdmsk                       : 1;
+	uint64_t picbst                       : 1;
+	uint64_t ipcbst                       : 1;
+	uint64_t rhdf                         : 4;
+	uint64_t rmdf                         : 4;
+	uint64_t mrb                          : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_l2c_bst2_cn38xx           cn38xxp2;
+	struct cvmx_l2c_bst2_cn30xx           cn50xx;
+	struct cvmx_l2c_bst2_cn30xx           cn52xx;
+	struct cvmx_l2c_bst2_cn30xx           cn52xxp1;
+	struct cvmx_l2c_bst2_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mrb                          : 4;  /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rmdb                         : 4;  /**< Bist Results for RMDB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t rhdb                         : 4;  /**< Bist Results for RHDB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ipcbst                       : 1;  /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+	uint64_t picbst                       : 1;  /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+	uint64_t xrdmsk                       : 1;  /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t xrddat                       : 1;  /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t xrddat                       : 1;
+	uint64_t xrdmsk                       : 1;
+	uint64_t picbst                       : 1;
+	uint64_t ipcbst                       : 1;
+	uint64_t rhdb                         : 4;
+	uint64_t rmdb                         : 4;
+	uint64_t mrb                          : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn56xx;
+	struct cvmx_l2c_bst2_cn56xx           cn56xxp1;
+	struct cvmx_l2c_bst2_cn56xx           cn58xx;
+	struct cvmx_l2c_bst2_cn56xx           cn58xxp1;
+};
+typedef union cvmx_l2c_bst2 cvmx_l2c_bst2_t;
+
+/**
+ * cvmx_l2c_bst_mem#
+ *
+ * L2C_BST_MEM = L2C MEM BIST Status
+ *
+ *
+ * Notes:
+ * (1) CLEAR_BIST must be written to 1 before START_BIST is written to 1 using a separate CSR write.
+ *
+ * (2) CLEAR_BIST must not be changed after writing START_BIST to 1 until the BIST operation completes
+ *     (indicated by START_BIST returning to 0) or operation is undefined.
+ */
+union cvmx_l2c_bst_memx
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst_memx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t start_bist                   : 1;  /**< When written to 1, starts BIST.  Will read 1 until
+                                                         BIST is complete (see Note). */
+	uint64_t clear_bist                   : 1;  /**< When BIST is triggered, run clear BIST (see Note) */
+	uint64_t reserved_5_61                : 57;
+	uint64_t rdffl                        : 1;  /**< BIST failure status for RDF */
+	uint64_t vbffl                        : 4;  /**< BIST failure status for VBF0-3 */
+#else
+	uint64_t vbffl                        : 4;
+	uint64_t rdffl                        : 1;
+	uint64_t reserved_5_61                : 57;
+	uint64_t clear_bist                   : 1;
+	uint64_t start_bist                   : 1;
+#endif
+	} s;
+	struct cvmx_l2c_bst_memx_s            cn63xx;
+	struct cvmx_l2c_bst_memx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_bst_memx cvmx_l2c_bst_memx_t;
+
+/**
+ * cvmx_l2c_bst_tdt#
+ *
+ * L2C_BST_TDT = L2C TAD DaTa BIST Status
+ *
+ */
+union cvmx_l2c_bst_tdtx
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst_tdtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t fbfrspfl                     : 8;  /**< BIST failure status for quad 0-7 FBF RSP read port */
+	uint64_t sbffl                        : 8;  /**< BIST failure status for quad 0-7 SBF */
+	uint64_t fbffl                        : 8;  /**< BIST failure status for quad 0-7 FBF */
+	uint64_t l2dfl                        : 8;  /**< BIST failure status for quad 0-7 L2D */
+#else
+	uint64_t l2dfl                        : 8;
+	uint64_t fbffl                        : 8;
+	uint64_t sbffl                        : 8;
+	uint64_t fbfrspfl                     : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_bst_tdtx_s            cn63xx;
+	struct cvmx_l2c_bst_tdtx_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t sbffl                        : 8;  /**< BIST failure status for quad 0-7 SBF */
+	uint64_t fbffl                        : 8;  /**< BIST failure status for quad 0-7 FBF */
+	uint64_t l2dfl                        : 8;  /**< BIST failure status for quad 0-7 L2D */
+#else
+	uint64_t l2dfl                        : 8;
+	uint64_t fbffl                        : 8;
+	uint64_t sbffl                        : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_l2c_bst_tdtx cvmx_l2c_bst_tdtx_t;
+
+/**
+ * cvmx_l2c_bst_ttg#
+ *
+ * L2C_BST_TTG = L2C TAD TaG BIST Status
+ *
+ */
+union cvmx_l2c_bst_ttgx
+{
+	uint64_t u64;
+	struct cvmx_l2c_bst_ttgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t lrufl                        : 1;  /**< BIST failure status for tag LRU */
+	uint64_t tagfl                        : 16; /**< BIST failure status for tag ways 0-15 */
+#else
+	uint64_t tagfl                        : 16;
+	uint64_t lrufl                        : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_l2c_bst_ttgx_s            cn63xx;
+	struct cvmx_l2c_bst_ttgx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_bst_ttgx cvmx_l2c_bst_ttgx_t;
+
+/**
+ * cvmx_l2c_cfg
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  L2C_CFG = L2C Configuration
+ *
+ * Description:
+ */
+union cvmx_l2c_cfg
+{
+	uint64_t u64;
+	struct cvmx_l2c_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state] */
+	uint64_t lbist                        : 1;  /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0).
+                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
+                                                         Fuse is blown. */
+	uint64_t xor_bank                     : 1;  /**< L2C XOR Bank Bit
+                                                         When both LMC's are enabled(DPRES1=1/DPRES0=1), this
+                                                         bit determines how addresses are assigned to
+                                                         LMC port(s).
+                                                            XOR_BANK|  LMC#
+                                                          ----------+---------------------------------
+                                                              0     |   byte address[7]
+                                                              1     |   byte address[7] XOR byte address[12]
+                                                         Example: If both LMC ports are enabled (DPRES1=1/DPRES0=1)
+                                                         and XOR_BANK=1, then addr[7] XOR addr[12] is used to determine
+                                                         which LMC Port# a reference is directed to. */
+	uint64_t dpres1                       : 1;  /**< DDR1 Present/LMC1 Enable
+                                                         When DPRES1 is set, LMC#1 is enabled(DDR1 pins at
+                                                         the BOTTOM of the chip are active).
+                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
+                                                         see XOR_BANK bit to determine how a reference is
+                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
+                                                         the address sent to the targeted LMC port is the
+                                                         address shifted right by one).
+                                                         NOTE: For power-savings, the DPRES1 is also used to
+                                                         disable DDR1/LMC1 clocks. */
+	uint64_t dpres0                       : 1;  /**< DDR0 Present/LMC0 Enable
+                                                         When DPRES0 is set, LMC#0 is enabled(DDR0 pins at
+                                                         the BOTTOM of the chip are active).
+                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
+                                                         see XOR_BANK bit to determine how a reference is
+                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
+                                                         the address sent to the targeted LMC port is the
+                                                         address shifted right by one).
+                                                         NOTE: For power-savings, the DPRES0 is also used to
+                                                         disable DDR0/LMC0 clocks. */
+	uint64_t dfill_dis                    : 1;  /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero. */
+	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+	uint64_t fpempty                      : 1;  /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+	uint64_t fpen                         : 1;  /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+	uint64_t idxalias                     : 1;  /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+	uint64_t mwf_crd                      : 4;  /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+	uint64_t rsp_arb_mode                 : 1;  /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+	uint64_t rfb_arb_mode                 : 1;  /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+	uint64_t lrf_arb_mode                 : 1;  /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+	uint64_t lrf_arb_mode                 : 1;
+	uint64_t rfb_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t mwf_crd                      : 4;
+	uint64_t idxalias                     : 1;
+	uint64_t fpen                         : 1;
+	uint64_t fpempty                      : 1;
+	uint64_t fpexp                        : 4;
+	uint64_t dfill_dis                    : 1;
+	uint64_t dpres0                       : 1;
+	uint64_t dpres1                       : 1;
+	uint64_t xor_bank                     : 1;
+	uint64_t lbist                        : 1;
+	uint64_t bstrun                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_l2c_cfg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+	uint64_t fpempty                      : 1;  /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+	uint64_t fpen                         : 1;  /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+	uint64_t idxalias                     : 1;  /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 8-bit
+                                                         index with the low order 8-bits of the tag.
+                                                            index[14:7] =  (tag[22:15] ^ index[14:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+	uint64_t mwf_crd                      : 4;  /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+	uint64_t rsp_arb_mode                 : 1;  /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+	uint64_t rfb_arb_mode                 : 1;  /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+	uint64_t lrf_arb_mode                 : 1;  /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+	uint64_t lrf_arb_mode                 : 1;
+	uint64_t rfb_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t mwf_crd                      : 4;
+	uint64_t idxalias                     : 1;
+	uint64_t fpen                         : 1;
+	uint64_t fpempty                      : 1;
+	uint64_t fpexp                        : 4;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_cfg_cn30xx            cn31xx;
+	struct cvmx_l2c_cfg_cn30xx            cn38xx;
+	struct cvmx_l2c_cfg_cn30xx            cn38xxp2;
+	struct cvmx_l2c_cfg_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state] */
+	uint64_t lbist                        : 1;  /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0). */
+	uint64_t reserved_14_17               : 4;
+	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+	uint64_t fpempty                      : 1;  /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+	uint64_t fpen                         : 1;  /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+	uint64_t idxalias                     : 1;  /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 7-bit
+                                                         index with the low order 7-bits of the tag.
+                                                            index[13:7] =  (tag[20:14] ^ index[13:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+	uint64_t mwf_crd                      : 4;  /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+	uint64_t rsp_arb_mode                 : 1;  /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+	uint64_t rfb_arb_mode                 : 1;  /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+	uint64_t lrf_arb_mode                 : 1;  /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+	uint64_t lrf_arb_mode                 : 1;
+	uint64_t rfb_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t mwf_crd                      : 4;
+	uint64_t idxalias                     : 1;
+	uint64_t fpen                         : 1;
+	uint64_t fpempty                      : 1;
+	uint64_t fpexp                        : 4;
+	uint64_t reserved_14_17               : 4;
+	uint64_t lbist                        : 1;
+	uint64_t bstrun                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_cfg_cn50xx            cn52xx;
+	struct cvmx_l2c_cfg_cn50xx            cn52xxp1;
+	struct cvmx_l2c_cfg_s                 cn56xx;
+	struct cvmx_l2c_cfg_s                 cn56xxp1;
+	struct cvmx_l2c_cfg_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t bstrun                       : 1;  /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state] */
+	uint64_t lbist                        : 1;  /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0).
+                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
+                                                         Fuse is blown. */
+	uint64_t reserved_15_17               : 3;
+	uint64_t dfill_dis                    : 1;  /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero. */
+	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+	uint64_t fpempty                      : 1;  /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+	uint64_t fpen                         : 1;  /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+	uint64_t idxalias                     : 1;  /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+	uint64_t mwf_crd                      : 4;  /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+	uint64_t rsp_arb_mode                 : 1;  /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+	uint64_t rfb_arb_mode                 : 1;  /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+	uint64_t lrf_arb_mode                 : 1;  /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+	uint64_t lrf_arb_mode                 : 1;
+	uint64_t rfb_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t mwf_crd                      : 4;
+	uint64_t idxalias                     : 1;
+	uint64_t fpen                         : 1;
+	uint64_t fpempty                      : 1;
+	uint64_t fpexp                        : 4;
+	uint64_t dfill_dis                    : 1;
+	uint64_t reserved_15_17               : 3;
+	uint64_t lbist                        : 1;
+	uint64_t bstrun                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn58xx;
+	struct cvmx_l2c_cfg_cn58xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t dfill_dis                    : 1;  /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero. */
+	uint64_t fpexp                        : 4;  /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+	uint64_t fpempty                      : 1;  /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+	uint64_t fpen                         : 1;  /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+	uint64_t idxalias                     : 1;  /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+	uint64_t mwf_crd                      : 4;  /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+	uint64_t rsp_arb_mode                 : 1;  /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+	uint64_t rfb_arb_mode                 : 1;  /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+	uint64_t lrf_arb_mode                 : 1;  /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+	uint64_t lrf_arb_mode                 : 1;
+	uint64_t rfb_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t mwf_crd                      : 4;
+	uint64_t idxalias                     : 1;
+	uint64_t fpen                         : 1;
+	uint64_t fpempty                      : 1;
+	uint64_t fpexp                        : 4;
+	uint64_t dfill_dis                    : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn58xxp1;
+};
+typedef union cvmx_l2c_cfg cvmx_l2c_cfg_t;
+
+/**
+ * cvmx_l2c_cop0_map#
+ *
+ * L2C_COP0_MAP = PP COP0 register memory mapped region
+ *
+ * Description: PP COP0 register mapped region.
+ *
+ * NOTE: for 63xx, if the PPID is outside the range of 0-5,63 the write will be ignored and reads
+ * will return 0x2bad2bad2bad2bad
+ *
+ * Notes:
+ * (1) There are 256 COP0 registers per PP.  Registers 0-255 map to PP0's COP0 registers, 256-511 are
+ *     mapped to PP1's, etc.  A special set X PP63 (registers 16128-16383) are for broadcast writes.
+ *     Any write done to these registers will take effect in ALL PPs.  Note the means the L2C_COP0_MAP
+ *     register to access can be gotten by:
+ *
+ *         REGNUM = [ PPID[5:0], rd[4:0], sel[2:0] ]
+ *
+ *     where rd and sel are as defined in the HRM description of Core Coprocessor 0 registers
+ *     and note 4 below.
+ *
+ * (2) if a COP0 register cannot be accessed by this mechanism the write be silently ignored and the
+ *     read data will be 0xBADDEED.
+ *
+ * (3) for 63xx, if the PPID is outside the range of 0-5,63 or if the PP in question is in reset a
+ *     write will be ignored and reads will timeout the RSL bus.
+ *
+ * (4) Referring to note (1) above, the following rd/sel values are supported:
+ *
+ *     NOTE: Put only the "Customer type" in HRM. do not put the "Real type" in HRM.
+ *
+ *                    Customer                                                    Real
+ *        rd     sel     type         Description                                 type
+ *     ======+=======+==========+==============================================+=========
+ *        4      2       RO          COP0 UserLocal                                RW
+ *        7      0       RO          COP0 HWREna                                   RW
+ *        9      0       RO          COP0 Count                                    RW
+ *        9      6       RO          COP0 CvmCount                                 RW
+ *        9      7       RO          COP0 CvmCtl                                   RW
+ *       11      0       RO          COP0 Compare                                  RW
+ *       11      6       RW          COP0 PowThrottle                              RW
+ *       12      0       RO          COP0 Status                                   RW
+ *       12      1       RO          COP0 IntCtl                                   RO
+ *       12      2       RO          COP0 SRSCtl                                   RO
+ *       13      0       RO          COP0 Cause                                    RW
+ *       14      0       RO          COP0 EPC                                      RW
+ *       15      0       RO          COP0 PrID                                     RO
+ *       15      1       RO          COP0 EBase                                    RW
+ *       16      0       RO          PC Issue Debug Info (see details below)       RO
+ *       16      1       RO          PC Fetch Debug Info (see details below)       RO
+ *       16      2       RO          PC Fill Debug Info (see details below)        RO
+ *       16      3       RO          PC Misc Debug Info (see details below)        RO
+ *       18      0       RO          COP0 WatchLo0                                 RW
+ *       19      0       RO          COP0 WatchHi0                                 RW
+ *       22      0       RO          COP0 MultiCoreDebug                           RW
+ *       23      0       RO          COP0 Debug                                    RW
+ *       23      6       RO          COP0 Debug2                                   RO
+ *       24      0       RO          COP0 DEPC                                     RW
+ *       25      0       RO          COP0 PerfCnt Control0                         RW
+ *       25      1       RO          COP0 PerfCnt Counter0                         RW
+ *       25      2       RO          COP0 PerfCnt Control1                         RW
+ *       25      3       RO          COP0 PerfCnt Counter1                         RW
+ *       27      0       RO          COP0 CacheErr (icache)                        RW
+ *       28      0       RO          COP0 TagLo (icache)                           RW
+ *       28      1       RO          COP0 DataLo (icache)                          RW
+ *       29      1       RO          COP0 DataHi (icache)                          RW
+ *       30      0       RO          COP0 ErrorEPC                                 RW
+ *       31      0       RO          COP0 DESAVE                                   RW
+ *       31      2       RO          COP0 Scratch                                  RW
+ *       31      3       RO          COP0 Scratch1                                 RW
+ *       31      4       RO          COP0 Scratch2                                 RW
+ *
+ *     - PC Issue Debug Info
+ *
+ *       - 63:2 pc0_5a<63:2> // often VA<63:2> of the next instruction to issue
+ *                           //    but can also be the VA of an instruction executing/replaying on pipe 0
+ *                           //    or can also be a VA being filled into the instruction cache
+ *                           //    or can also be unpredictable
+ *                           // <61:49> RAZ
+ *       1    illegal      // set when illegal VA
+ *       0    delayslot    // set when VA is delayslot (prior branch may be either taken or not taken)
+ *
+ *     - PC Fetch Debug Info
+ *
+ *       - 63:0 fetch_address_3a // VA being fetched from the instruction cache
+ *                               // <61:49>, <1:0> RAZ
+ *
+ *     - PC Fill Debug Info
+ *
+ *       - 63:0 fill_address_4a<63:2> // VA<63:2> being filled into instruction cache
+ *                                    // valid when waiting_for_ifill_4a is set (see PC Misc Debug Info below)
+ *                                    // <61:49> RAZ
+ *          1 illegal               // set when illegal VA
+ *          0 RAZ
+ *
+ *     - PC Misc Debug Info
+ *
+ *       - 63:3 RAZ
+ *          2 mem_stall_3a         // stall term from L1 memory system
+ *          1 waiting_for_pfill_4a // when waiting_for_ifill_4a is set, indicates whether instruction cache fill is due to a prefetch
+ *          0 waiting_for_ifill_4a // set when there is an outstanding instruction cache fill
+ */
+union cvmx_l2c_cop0_mapx
+{
+	uint64_t u64;
+	struct cvmx_l2c_cop0_mapx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Data to write to/read from designated PP's COP0
+                                                         register. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_l2c_cop0_mapx_s           cn63xx;
+	struct cvmx_l2c_cop0_mapx_s           cn63xxp1;
+};
+typedef union cvmx_l2c_cop0_mapx cvmx_l2c_cop0_mapx_t;
+
+/**
+ * cvmx_l2c_ctl
+ *
+ * L2C_CTL = L2C Control
+ *
+ *
+ * Notes:
+ * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.
+ *
+ * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE, and VBFDBE errors for
+ *     the purposes of testing error handling code.  When one (or both) of these bits are set a PL2
+ *     which misses in the L2 will fill with the appropriate error in the first 2 OWs of the fill.
+ *     Software can determine which OW pair gets the error by choosing the desired fill order
+ *     (address<6:5>).  A PL2 which hits in the L2 will not inject any errors.  Therefore sending a
+ *     WBIL2 prior to the PL2 is recommended to make a miss likely (if multiple processors are involved
+ *     software must be careful to be sure no other processor or IO device can bring the block into the
+ *     L2).
+ *
+ *     To generate a VBFSBE or VBFDBE, software must first get the cache block into the cache with an
+ *     error using a PL2 which misses the L2.  Then a store partial to a portion of the cache block
+ *     without the error must change the block to dirty.  Then, a subsequent WBL2/WBIL2/victim will
+ *     trigger the VBFSBE/VBFDBE error.
+ */
+union cvmx_l2c_ctl
+{
+	uint64_t u64;
+	struct cvmx_l2c_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t disstgl2i                    : 1;  /**< Disable STGL2I's from changing the tags */
+	uint64_t l2dfsbe                      : 1;  /**< Force single bit ECC error on PL2 allocates (2) */
+	uint64_t l2dfdbe                      : 1;  /**< Force double bit ECC error on PL2 allocates (2) */
+	uint64_t discclk                      : 1;  /**< Disable conditional clocking in L2C PNR blocks */
+	uint64_t maxvab                       : 4;  /**< Maximum VABs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t maxlfb                       : 4;  /**< Maximum LFBs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t rsp_arb_mode                 : 1;  /**< Arbitration mode for RSC/RSD bus
+                                                         == 0, round-robin
+                                                         == 1, static priority
+                                                             1. IOR data
+                                                             2. STIN/FILLs
+                                                             3. STDN/SCDN/SCFL */
+	uint64_t xmc_arb_mode                 : 1;  /**< Arbitration mode for XMC QOS queues
+                                                         == 0, fully determined through QOS
+                                                         == 1, QOS0 highest priority, QOS1-3 use normal mode */
+	uint64_t ef_ena                       : 1;  /**< LMC early fill enable */
+	uint64_t ef_cnt                       : 7;  /**< LMC early fill count
+                                                         Specifies the number of cycles after the first LMC
+                                                         fill cycle to wait before requesting a fill on the
+                                                         RSC/RSD bus.
+                                                           // 7 dclks (we've received 1st out of 8
+                                                           // by the time we start counting)
+                                                           ef_cnt = (7 * dclk0_period) / rclk_period;
+                                                           // + 1 rclk if the dclk and rclk edges don't
+                                                           // stay in the same position
+                                                           if ((dclk0_gen.period % rclk_gen.period) != 0)
+                                                              ef_cnt = ef_cnt + 1;
+                                                           // + 2 rclk synchronization uncertainty
+                                                           ef_cnt = ef_cnt + 2;
+                                                           // - 3 rclks to recognize first write
+                                                           ef_cnt = ef_cnt - 3;
+                                                           // + 3 rclks to perform first write
+                                                           ef_cnt = ef_cnt + 3;
+                                                           // - 9 rclks minimum latency from counter expire
+                                                           // to final fbf read
+                                                           ef_cnt = ef_cnt - 9; */
+	uint64_t vab_thresh                   : 4;  /**< VAB Threshold
+                                                         When the number of valid VABs exceeds this number the
+                                                         L2C increases the priority of all writes in the LMC. */
+	uint64_t disecc                       : 1;  /**< Tag and Data ECC Disable */
+	uint64_t disidxalias                  : 1;  /**< Index Alias Disable */
+#else
+	uint64_t disidxalias                  : 1;
+	uint64_t disecc                       : 1;
+	uint64_t vab_thresh                   : 4;
+	uint64_t ef_cnt                       : 7;
+	uint64_t ef_ena                       : 1;
+	uint64_t xmc_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t maxlfb                       : 4;
+	uint64_t maxvab                       : 4;
+	uint64_t discclk                      : 1;
+	uint64_t l2dfdbe                      : 1;
+	uint64_t l2dfsbe                      : 1;
+	uint64_t disstgl2i                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_l2c_ctl_s                 cn63xx;
+	struct cvmx_l2c_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t discclk                      : 1;  /**< Disable conditional clocking in L2C PNR blocks */
+	uint64_t maxvab                       : 4;  /**< Maximum VABs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t maxlfb                       : 4;  /**< Maximum LFBs in use at once
+                                                         (0 means 16, 1-15 as expected) */
+	uint64_t rsp_arb_mode                 : 1;  /**< Arbitration mode for RSC/RSD bus
+                                                         == 0, round-robin
+                                                         == 1, static priority
+                                                             1. IOR data
+                                                             2. STIN/FILLs
+                                                             3. STDN/SCDN/SCFL */
+	uint64_t xmc_arb_mode                 : 1;  /**< Arbitration mode for XMC QOS queues
+                                                         == 0, fully determined through QOS
+                                                         == 1, QOS0 highest priority, QOS1-3 use normal mode */
+	uint64_t ef_ena                       : 1;  /**< LMC early fill enable */
+	uint64_t ef_cnt                       : 7;  /**< LMC early fill count
+                                                         Specifies the number of cycles after the first LMC
+                                                         fill cycle to wait before requesting a fill on the
+                                                         RSC/RSD bus.
+                                                           // 7 dclks (we've received 1st out of 8
+                                                           // by the time we start counting)
+                                                           ef_cnt = (7 * dclk0_period) / rclk_period;
+                                                           // + 1 rclk if the dclk and rclk edges don't
+                                                           // stay in the same position
+                                                           if ((dclk0_gen.period % rclk_gen.period) != 0)
+                                                              ef_cnt = ef_cnt + 1;
+                                                           // + 2 rclk synchronization uncertainty
+                                                           ef_cnt = ef_cnt + 2;
+                                                           // - 3 rclks to recognize first write
+                                                           ef_cnt = ef_cnt - 3;
+                                                           // + 3 rclks to perform first write
+                                                           ef_cnt = ef_cnt + 3;
+                                                           // - 9 rclks minimum latency from counter expire
+                                                           // to final fbf read
+                                                           ef_cnt = ef_cnt - 9; */
+	uint64_t vab_thresh                   : 4;  /**< VAB Threshold
+                                                         When the number of valid VABs exceeds this number the
+                                                         L2C increases the priority of all writes in the LMC. */
+	uint64_t disecc                       : 1;  /**< Tag and Data ECC Disable */
+	uint64_t disidxalias                  : 1;  /**< Index Alias Disable */
+#else
+	uint64_t disidxalias                  : 1;
+	uint64_t disecc                       : 1;
+	uint64_t vab_thresh                   : 4;
+	uint64_t ef_cnt                       : 7;
+	uint64_t ef_ena                       : 1;
+	uint64_t xmc_arb_mode                 : 1;
+	uint64_t rsp_arb_mode                 : 1;
+	uint64_t maxlfb                       : 4;
+	uint64_t maxvab                       : 4;
+	uint64_t discclk                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_l2c_ctl cvmx_l2c_ctl_t;
+
+/**
+ * cvmx_l2c_dbg
+ *
+ * L2C_DBG = L2C DEBUG Register
+ *
+ * Description: L2C Tag/Data Store Debug Register
+ *
+ * Notes:
+ * (1) When using the L2T, L2D or FINV Debug probe feature, the LDD command WILL NOT update the DuTags.
+ * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one set)
+ * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
+ *     dirty data to memory to maintain coherency.
+ * (4) L2 Cache Lock Down feature MUST BE disabled (L2C_LCKBASE[LCK_ENA]=0) if ANY of the L2C debug
+ *     features (L2T, L2D, FINV) are enabled.
+ */
+union cvmx_l2c_dbg
+{
+	uint64_t u64;
+	struct cvmx_l2c_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t lfb_enum                     : 4;  /**< Specifies the LFB Entry# which is to be captured. */
+	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[3:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+	uint64_t ppnum                        : 4;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which one-of-16
+                                                         PPs is selected as the diagnostic PP. */
+	uint64_t set                          : 3;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+	uint64_t finv                         : 1;  /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[17:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[17:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+	uint64_t l2d                          : 1;  /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[17:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+	uint64_t l2t                          : 1;  /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:18]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[17:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: N3K-Pass2 modification. (This bit's functionality
+                                                         has changed since Pass1-in the following way).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+	uint64_t l2t                          : 1;
+	uint64_t l2d                          : 1;
+	uint64_t finv                         : 1;
+	uint64_t set                          : 3;
+	uint64_t ppnum                        : 4;
+	uint64_t lfb_dmp                      : 1;
+	uint64_t lfb_enum                     : 4;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_l2c_dbg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t lfb_enum                     : 2;  /**< Specifies the LFB Entry# which is to be captured. */
+	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+	uint64_t reserved_7_9                 : 3;
+	uint64_t ppnum                        : 1;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which
+                                                         PP is selected as the diagnostic PP.
+                                                         NOTE: For CN30XX single core PPNUM=0 (MBZ) */
+	uint64_t reserved_5_5                 : 1;
+	uint64_t set                          : 2;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+	uint64_t finv                         : 1;  /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the PP will invalidate
+                                                         the specified set(L2C_DBG[SET]) at the index specified
+                                                         in the STF address[14:7]. If a dirty block is detected(D=1),
+                                                         it is written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[14:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The PP can generate STF(L1 store-miss)
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+	uint64_t l2d                          : 1;  /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
+                                                         command is issued from the PP.
+                                                         The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[14:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+	uint64_t l2t                          : 1;  /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:15]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from the PP.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[14:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD(L1 load-miss) is detected. */
+#else
+	uint64_t l2t                          : 1;
+	uint64_t l2d                          : 1;
+	uint64_t finv                         : 1;
+	uint64_t set                          : 2;
+	uint64_t reserved_5_5                 : 1;
+	uint64_t ppnum                        : 1;
+	uint64_t reserved_7_9                 : 3;
+	uint64_t lfb_dmp                      : 1;
+	uint64_t lfb_enum                     : 2;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_dbg_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
+	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+	uint64_t reserved_7_9                 : 3;
+	uint64_t ppnum                        : 1;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which
+                                                         PP is selected as the diagnostic PP. */
+	uint64_t reserved_5_5                 : 1;
+	uint64_t set                          : 2;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+	uint64_t finv                         : 1;  /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[15:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[15:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF(L1 store-miss)
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+	uint64_t l2d                          : 1;  /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
+                                                         command is issued from a PP determined by the
+                                                         L2C_DBG[PPNUM] field. The selected set# is determined
+                                                         by the L2C_DBG[SET] field, and the index is determined
+                                                         from the address[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+	uint64_t l2t                          : 1;  /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD(L1 load-miss) is detected from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]). */
+#else
+	uint64_t l2t                          : 1;
+	uint64_t l2d                          : 1;
+	uint64_t finv                         : 1;
+	uint64_t set                          : 2;
+	uint64_t reserved_5_5                 : 1;
+	uint64_t ppnum                        : 1;
+	uint64_t reserved_7_9                 : 3;
+	uint64_t lfb_dmp                      : 1;
+	uint64_t lfb_enum                     : 3;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_dbg_s                 cn38xx;
+	struct cvmx_l2c_dbg_s                 cn38xxp2;
+	struct cvmx_l2c_dbg_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
+	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[2:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+	uint64_t reserved_7_9                 : 3;
+	uint64_t ppnum                        : 1;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which 1-of-2
+                                                         PPs is selected as the diagnostic PP. */
+	uint64_t set                          : 3;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+	uint64_t finv                         : 1;  /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[13:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[13:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+	uint64_t l2d                          : 1;  /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[13:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+	uint64_t l2t                          : 1;  /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:14]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[13:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+	uint64_t l2t                          : 1;
+	uint64_t l2d                          : 1;
+	uint64_t finv                         : 1;
+	uint64_t set                          : 3;
+	uint64_t ppnum                        : 1;
+	uint64_t reserved_7_9                 : 3;
+	uint64_t lfb_dmp                      : 1;
+	uint64_t lfb_enum                     : 3;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_dbg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t lfb_enum                     : 3;  /**< Specifies the LFB Entry# which is to be captured. */
+	uint64_t lfb_dmp                      : 1;  /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[2:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+	uint64_t reserved_8_9                 : 2;
+	uint64_t ppnum                        : 2;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which 1-of-4
+                                                         PPs is selected as the diagnostic PP. */
+	uint64_t set                          : 3;  /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+	uint64_t finv                         : 1;  /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[15:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[15:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+	uint64_t l2d                          : 1;  /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[15:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+	uint64_t l2t                          : 1;  /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+	uint64_t l2t                          : 1;
+	uint64_t l2d                          : 1;
+	uint64_t finv                         : 1;
+	uint64_t set                          : 3;
+	uint64_t ppnum                        : 2;
+	uint64_t reserved_8_9                 : 2;
+	uint64_t lfb_dmp                      : 1;
+	uint64_t lfb_enum                     : 3;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn52xx;
+	struct cvmx_l2c_dbg_cn52xx            cn52xxp1;
+	struct cvmx_l2c_dbg_s                 cn56xx;
+	struct cvmx_l2c_dbg_s                 cn56xxp1;
+	struct cvmx_l2c_dbg_s                 cn58xx;
+	struct cvmx_l2c_dbg_s                 cn58xxp1;
+};
+typedef union cvmx_l2c_dbg cvmx_l2c_dbg_t;
+
+/**
+ * cvmx_l2c_dut
+ *
+ * L2C_DUT = L2C DUTAG Register
+ *
+ * Description: L2C Duplicate Tag State Register
+ *
+ * Notes:
+ * (1) When using the L2T, L2D or FINV Debug probe feature, an LDD command issued by the diagnostic PP
+ *     WILL NOT update the DuTags.
+ * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one enabled at a time).
+ * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
+ *     dirty data to memory to maintain coherency. (A side effect of FINV is that an LDD L2 fill is
+ *     launched which fills data into the L2 DS).
+ */
+union cvmx_l2c_dut
+{
+	uint64_t u64;
+	struct cvmx_l2c_dut_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dtena                        : 1;  /**< DuTag Diagnostic read enable.
+                                                         When L2C_DUT[DTENA]=1, all LDD(L1 load-miss)
+                                                         commands issued from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will capture the DuTag state (V|L1TAG)
+                                                         of the PP#(specified in the LDD address[29:26] into
+                                                         the L2C_DUT CSR register. This allows the diagPP to
+                                                         read ALL DuTags (from any PP).
+                                                         The DuTag Set# to capture is extracted from the LDD
+                                                         address[25:20]. The diagnostic PP would issue the
+                                                         LDD then read the L2C_DUT register (one at a time).
+                                                         This LDD 'L2 force-hit' will NOT alter the current L2
+                                                         Tag State OR the DuTag state.
+                                                         NOTE: For CN58XX the DuTag SIZE has doubled (to 16KB)
+                                                         where each DuTag is organized as 2x 64-way entries.
+                                                         The LDD address[7] determines which 1(of-2) internal
+                                                         64-ways to select.
+                                                         The fill data is returned directly from the L2 Data
+                                                         Store(regardless of hit/miss) when an LDD command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected L2 Set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[17:7] associated with the LDD
+                                                         command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: In order for the DiagPP to generate an LDD command
+                                                         to the L2C, it must first force an L1 Dcache flush. */
+	uint64_t reserved_30_30               : 1;
+	uint64_t dt_vld                       : 1;  /**< Duplicate L1 Tag Valid bit latched in for previous
+                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
+	uint64_t dt_tag                       : 29; /**< Duplicate L1 Tag[35:7] latched in for previous
+                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
+#else
+	uint64_t dt_tag                       : 29;
+	uint64_t dt_vld                       : 1;
+	uint64_t reserved_30_30               : 1;
+	uint64_t dtena                        : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_dut_s                 cn30xx;
+	struct cvmx_l2c_dut_s                 cn31xx;
+	struct cvmx_l2c_dut_s                 cn38xx;
+	struct cvmx_l2c_dut_s                 cn38xxp2;
+	struct cvmx_l2c_dut_s                 cn50xx;
+	struct cvmx_l2c_dut_s                 cn52xx;
+	struct cvmx_l2c_dut_s                 cn52xxp1;
+	struct cvmx_l2c_dut_s                 cn56xx;
+	struct cvmx_l2c_dut_s                 cn56xxp1;
+	struct cvmx_l2c_dut_s                 cn58xx;
+	struct cvmx_l2c_dut_s                 cn58xxp1;
+};
+typedef union cvmx_l2c_dut cvmx_l2c_dut_t;
+
+/**
+ * cvmx_l2c_dut_map#
+ *
+ * L2C_DUT_MAP = L2C DUT memory map region
+ *
+ * Description: Address of the start of the region mapped to the duplicate tag.  Can be used to read
+ * and write the raw duplicate tag CAM.  Writes should be used only with great care as they can easily
+ * destroy the coherency of the memory system.  In any case this region is expected to only be used
+ * for debug.
+ *
+ * This base address should be combined with PP virtual ID, L1 way and L1 set to produce the final
+ * address as follows:
+ *     addr<63:14>      L2C_DUT_MAP<63:14>
+ *     addr<13:11>      PP VID
+ *     addr<10:6>       L1 way
+ *     addr<5:3>        L1 set
+ *     addr<2:0>        UNUSED
+ *
+ * Notes:
+ * (1) The tag is 37:10 from the 38-bit OCTEON physical address after hole removal. (The hole is between DR0
+ * and DR1. Remove the hole by subtracting 256MB from 38-bit OCTEON L2/DRAM physical addresses >= 512 MB.)
+ */
+union cvmx_l2c_dut_mapx
+{
+	uint64_t u64;
+	struct cvmx_l2c_dut_mapx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t tag                          : 28; /**< The tag value (see Note 1) */
+	uint64_t reserved_1_9                 : 9;
+	uint64_t valid                        : 1;  /**< The valid bit */
+#else
+	uint64_t valid                        : 1;
+	uint64_t reserved_1_9                 : 9;
+	uint64_t tag                          : 28;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_l2c_dut_mapx_s            cn63xx;
+	struct cvmx_l2c_dut_mapx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_dut_mapx cvmx_l2c_dut_mapx_t;
+
+/**
+ * cvmx_l2c_err_tdt#
+ *
+ * L2C_ERR_TDT = L2C TAD DaTa Error Info
+ *
+ *
+ * Notes:
+ * (1) If the status bit corresponding to the value of the TYPE field is not set the WAYIDX/SYN fields
+ *     are not associated with the errors currently logged by the status bits and should be ignored.
+ *     This can occur, for example, because of a race between a write to clear a DBE and a new, lower
+ *     priority, SBE error occuring.  If the SBE arrives prior to the DBE clear the WAYIDX/SYN fields
+ *     will still be locked, but the new SBE error status bit will still be set.
+ *
+ * (2) The four types of errors have differing priorities.  Priority (from lowest to highest) is SBE,
+ *     VSBE, DBE, VDBE.  A error will lock the WAYIDX, and SYN fields for other errors of equal or
+ *     lower priority until cleared by software.  This means that the error information is always
+ *     (assuming the TYPE field matches) for the highest priority error logged in the status bits.
+ *
+ * (3) If VSBE or VDBE are set (and the TYPE field matches), the WAYIDX fields are valid and the
+ *     syndrome can be found in L2C_ERR_VBF.
+ *
+ * (4) The syndrome is recorded for DBE errors, though the utility of the value is not clear.
+ */
+union cvmx_l2c_err_tdtx
+{
+	uint64_t u64;
+	struct cvmx_l2c_err_tdtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dbe                          : 1;  /**< L2D Double-Bit error has occurred */
+	uint64_t sbe                          : 1;  /**< L2D Single-Bit error has occurred */
+	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
+	uint64_t vsbe                         : 1;  /**< VBF Single-Bit error has occurred */
+	uint64_t syn                          : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */
+	uint64_t reserved_21_49               : 29;
+	uint64_t wayidx                       : 17; /**< Way, index, OW of the L2 block containing the error */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - VSBE
+                                                         1 - VDBE
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t wayidx                       : 17;
+	uint64_t reserved_21_49               : 29;
+	uint64_t syn                          : 10;
+	uint64_t vsbe                         : 1;
+	uint64_t vdbe                         : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} s;
+	struct cvmx_l2c_err_tdtx_s            cn63xx;
+	struct cvmx_l2c_err_tdtx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_err_tdtx cvmx_l2c_err_tdtx_t;
+
+/**
+ * cvmx_l2c_err_ttg#
+ *
+ * L2C_ERR_TTG = L2C TAD TaG Error Info
+ *
+ *
+ * Notes:
+ * (1) The priority of errors (highest to lowest) is DBE, SBE, NOWAY.  An error will lock the SYN, and
+ *     WAYIDX fields for equal or lower priority errors until cleared by software.
+ *
+ * (2) The syndrome is recorded for DBE errors, though the utility of the value is not clear.
+ *
+ * (3) A NOWAY error does not change the value of the SYN field, and leaves WAYIDX[20:17]
+ *     unpredictable.  WAYIDX[16:7] is the L2 block index associated with the command which had no way
+ *     to allocate.
+ *
+ * (4) If the status bit corresponding to the value of the TYPE field is not set the WAYIDX/SYN fields
+ *     are not associated with the errors currently logged by the status bits and should be ignored.
+ *     This can occur, for example, because of a race between a write to clear a DBE and a new, lower
+ *     priority, SBE error occuring.  If the SBE arrives prior to the DBE clear the WAYIDX/SYN fields
+ *     will still be locked, but the new SBE error status bit will still be set.
+ */
+union cvmx_l2c_err_ttgx
+{
+	uint64_t u64;
+	struct cvmx_l2c_err_ttgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dbe                          : 1;  /**< Double-Bit ECC error */
+	uint64_t sbe                          : 1;  /**< Single-Bit ECC error */
+	uint64_t noway                        : 1;  /**< No way was available for allocation.
+                                                         L2C sets NOWAY during its processing of a
+                                                         transaction whenever it needed/wanted to allocate
+                                                         a WAY in the L2 cache, but was unable to. NOWAY==1
+                                                         is (generally) not an indication that L2C failed to
+                                                         complete transactions. Rather, it is a hint of
+                                                         possible performance degradation. (For example, L2C
+                                                         must read-modify-write DRAM for every transaction
+                                                         that updates some, but not all, of the bytes in a
+                                                         cache block, misses in the L2 cache, and cannot
+                                                         allocate a WAY.) There is one "failure" case where
+                                                         L2C will set NOWAY: when it cannot leave a block
+                                                         locked in the L2 cache as part of a LCKL2
+                                                         transaction. */
+	uint64_t reserved_56_60               : 5;
+	uint64_t syn                          : 6;  /**< Syndrome for the single-bit error */
+	uint64_t reserved_21_49               : 29;
+	uint64_t wayidx                       : 14; /**< Way and index of the L2 block containing the error */
+	uint64_t reserved_2_6                 : 5;
+	uint64_t type                         : 2;  /**< The type of error the WAYIDX,SYN were latched for.
+                                                         0 - not valid
+                                                         1 - NOWAY
+                                                         2 - SBE
+                                                         3 - DBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_6                 : 5;
+	uint64_t wayidx                       : 14;
+	uint64_t reserved_21_49               : 29;
+	uint64_t syn                          : 6;
+	uint64_t reserved_56_60               : 5;
+	uint64_t noway                        : 1;
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+#endif
+	} s;
+	struct cvmx_l2c_err_ttgx_s            cn63xx;
+	struct cvmx_l2c_err_ttgx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_err_ttgx cvmx_l2c_err_ttgx_t;
+
+/**
+ * cvmx_l2c_err_vbf#
+ *
+ * L2C_ERR_VBF = L2C VBF Error Info
+ *
+ *
+ * Notes:
+ * (1) The way/index information is stored in L2C_ERR_TDT, assuming no later interrupt occurred to
+ *     overwrite the information.  See the notes associated with L2C_ERR_TDT for full details.
+ *
+ * (2) The first VSBE will lock the register for other VSBE's.  A VDBE, however, will overwrite a
+ *     previously logged VSBE.  Once a VDBE has been logged all later errors will not be logged.  This
+ *     means that if VDBE is set the information in the register is for the VDBE, if VDBE is clear and
+ *     VSBE is set the register contains information about the VSBE.
+ *
+ * (3) The syndrome is recorded for VDBE errors, though the utility of the value is not clear.
+ *
+ * (4) If the status bit corresponding to the value of the TYPE field is not set the SYN field is not
+ *     associated with the errors currently logged by the status bits and should be ignored.  This can
+ *     occur, for example, because of a race between a write to clear a VDBE and a new, lower priority,
+ *     VSBE error occuring.  If the VSBE arrives prior to the VDBE clear the SYN field will still be
+ *     locked, but the new VSBE error status bit will still be set.
+ */
+union cvmx_l2c_err_vbfx
+{
+	uint64_t u64;
+	struct cvmx_l2c_err_vbfx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t vdbe                         : 1;  /**< VBF Double-Bit error has occurred */
+	uint64_t vsbe                         : 1;  /**< VBF Single-Bit error has occurred */
+	uint64_t vsyn                         : 10; /**< VBF syndrome (valid only if VSBE/VDBE is set) */
+	uint64_t reserved_2_49                : 48;
+	uint64_t type                         : 2;  /**< The type of error the SYN were latched for.
+                                                         0 - VSBE
+                                                         1 - VDBE */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_49                : 48;
+	uint64_t vsyn                         : 10;
+	uint64_t vsbe                         : 1;
+	uint64_t vdbe                         : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_l2c_err_vbfx_s            cn63xx;
+	struct cvmx_l2c_err_vbfx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_err_vbfx cvmx_l2c_err_vbfx_t;
+
+/**
+ * cvmx_l2c_err_xmc
+ *
+ * L2C_ERR_XMC = L2C XMC request error
+ *
+ * Description: records error information for HOLE*, BIG* and VRT* interrupts.
+ *
+ * Notes:
+ * (1) The first BIGWR/HOLEWR/VRT* interrupt will lock the register until L2C_INT_REG[6:1] are
+ *     cleared.
+ *
+ * (2) ADDR<15:0> will always be zero for VRT* interrupts.
+ *
+ * (3) ADDR is the 38-bit OCTEON physical address after hole removal. (The hole is between DR0
+ *     and DR1. Remove the hole by subtracting 256MB from all 38-bit OCTEON L2/DRAM physical addresses
+ *     >= 512 MB.)
+ *
+ * (4) For 63xx pass 2.0 and all 68xx ADDR<15:0> will ALWAYS be zero.
+ */
+union cvmx_l2c_err_xmc
+{
+	uint64_t u64;
+	struct cvmx_l2c_err_xmc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cmd                          : 6;  /**< XMC command or request causing error */
+	uint64_t reserved_52_57               : 6;
+	uint64_t sid                          : 4;  /**< XMC sid of request causing error */
+	uint64_t reserved_38_47               : 10;
+	uint64_t addr                         : 38; /**< XMC address causing the error (see Notes 2 and 3) */
+#else
+	uint64_t addr                         : 38;
+	uint64_t reserved_38_47               : 10;
+	uint64_t sid                          : 4;
+	uint64_t reserved_52_57               : 6;
+	uint64_t cmd                          : 6;
+#endif
+	} s;
+	struct cvmx_l2c_err_xmc_s             cn63xx;
+	struct cvmx_l2c_err_xmc_s             cn63xxp1;
+};
+typedef union cvmx_l2c_err_xmc cvmx_l2c_err_xmc_t;
+
+/**
+ * cvmx_l2c_grpwrr0
+ *
+ * L2C_GRPWRR0 = L2C PP Weighted Round \#0 Register
+ *
+ * Description: Defines Weighted rounds(32) for Group PLC0,PLC1
+ *
+ * Notes:
+ * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
+ * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
+ */
+union cvmx_l2c_grpwrr0
+{
+	uint64_t u64;
+	struct cvmx_l2c_grpwrr0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t plc1rmsk                     : 32; /**< PLC1 Group#1 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#1's participation. When a 'round' bit is
+                                                         set, Group#1 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#1 WILL
+                                                         participate in the arbitration for this round. */
+	uint64_t plc0rmsk                     : 32; /**< PLC Group#0 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#0's participation. When a 'round' bit is
+                                                         set, Group#0 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#0 WILL
+                                                         participate in the arbitration for this round. */
+#else
+	uint64_t plc0rmsk                     : 32;
+	uint64_t plc1rmsk                     : 32;
+#endif
+	} s;
+	struct cvmx_l2c_grpwrr0_s             cn52xx;
+	struct cvmx_l2c_grpwrr0_s             cn52xxp1;
+	struct cvmx_l2c_grpwrr0_s             cn56xx;
+	struct cvmx_l2c_grpwrr0_s             cn56xxp1;
+};
+typedef union cvmx_l2c_grpwrr0 cvmx_l2c_grpwrr0_t;
+
+/**
+ * cvmx_l2c_grpwrr1
+ *
+ * L2C_GRPWRR1 = L2C PP Weighted Round \#1 Register
+ *
+ * Description: Defines Weighted Rounds(32) for Group PLC2,ILC
+ *
+ * Notes:
+ * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
+ * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
+ */
+union cvmx_l2c_grpwrr1
+{
+	uint64_t u64;
+	struct cvmx_l2c_grpwrr1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t ilcrmsk                      : 32; /**< ILC (IOB) Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for IOB participation. When a 'round' bit is
+                                                         set, IOB is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, IOB WILL
+                                                         participate in the arbitration for this round. */
+	uint64_t plc2rmsk                     : 32; /**< PLC Group#2 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#2's participation. When a 'round' bit is
+                                                         set, Group#2 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#2 WILL
+                                                         participate in the arbitration for this round. */
+#else
+	uint64_t plc2rmsk                     : 32;
+	uint64_t ilcrmsk                      : 32;
+#endif
+	} s;
+	struct cvmx_l2c_grpwrr1_s             cn52xx;
+	struct cvmx_l2c_grpwrr1_s             cn52xxp1;
+	struct cvmx_l2c_grpwrr1_s             cn56xx;
+	struct cvmx_l2c_grpwrr1_s             cn56xxp1;
+};
+typedef union cvmx_l2c_grpwrr1 cvmx_l2c_grpwrr1_t;
+
+/**
+ * cvmx_l2c_int_en
+ *
+ * L2C_INT_EN = L2C Global Interrupt Enable Register
+ *
+ * Description:
+ */
+union cvmx_l2c_int_en
+{
+	uint64_t u64;
+	struct cvmx_l2c_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t lck2ena                      : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA2] */
+	uint64_t lckena                       : 1;  /**< L2 Tag Lock Error Interrupt Enable bit
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA] */
+	uint64_t l2ddeden                     : 1;  /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on double bit
+                                                         (uncorrectable) errors from the L2 Data Arrays.
+                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_INTENA] */
+	uint64_t l2dsecen                     : 1;  /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on single bit
+                                                         (correctable) errors from the L2 Data Arrays.
+                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_INTENA] */
+	uint64_t l2tdeden                     : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_INTENA] */
+	uint64_t l2tsecen                     : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays.
+                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_INTENA] */
+	uint64_t oob3en                       : 1;  /**< DMA Out of Bounds Interrupt Enable Range#3 */
+	uint64_t oob2en                       : 1;  /**< DMA Out of Bounds Interrupt Enable Range#2 */
+	uint64_t oob1en                       : 1;  /**< DMA Out of Bounds Interrupt Enable Range#1 */
+#else
+	uint64_t oob1en                       : 1;
+	uint64_t oob2en                       : 1;
+	uint64_t oob3en                       : 1;
+	uint64_t l2tsecen                     : 1;
+	uint64_t l2tdeden                     : 1;
+	uint64_t l2dsecen                     : 1;
+	uint64_t l2ddeden                     : 1;
+	uint64_t lckena                       : 1;
+	uint64_t lck2ena                      : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_int_en_s              cn52xx;
+	struct cvmx_l2c_int_en_s              cn52xxp1;
+	struct cvmx_l2c_int_en_s              cn56xx;
+	struct cvmx_l2c_int_en_s              cn56xxp1;
+};
+typedef union cvmx_l2c_int_en cvmx_l2c_int_en_t;
+
+/**
+ * cvmx_l2c_int_ena
+ *
+ * L2C_INT_ENA = L2C Interrupt Enable
+ *
+ */
+union cvmx_l2c_int_ena
+{
+	uint64_t u64;
+	struct cvmx_l2c_int_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t bigrd                        : 1;  /**< Read reference past MAXDRAM enable */
+	uint64_t bigwr                        : 1;  /**< Write reference past MAXDRAM enable */
+	uint64_t vrtpe                        : 1;  /**< Virtualization memory parity error */
+	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range enable */
+	uint64_t vrtidrng                     : 1;  /**< Virtualization ID out of range enable */
+	uint64_t vrtwr                        : 1;  /**< Virtualization ID prevented a write enable */
+	uint64_t holewr                       : 1;  /**< Write reference to 256MB hole enable */
+	uint64_t holerd                       : 1;  /**< Read reference to 256MB hole enable */
+#else
+	uint64_t holerd                       : 1;
+	uint64_t holewr                       : 1;
+	uint64_t vrtwr                        : 1;
+	uint64_t vrtidrng                     : 1;
+	uint64_t vrtadrng                     : 1;
+	uint64_t vrtpe                        : 1;
+	uint64_t bigwr                        : 1;
+	uint64_t bigrd                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_l2c_int_ena_s             cn63xx;
+	struct cvmx_l2c_int_ena_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t vrtpe                        : 1;  /**< Virtualization memory parity error */
+	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range enable */
+	uint64_t vrtidrng                     : 1;  /**< Virtualization ID out of range enable */
+	uint64_t vrtwr                        : 1;  /**< Virtualization ID prevented a write enable */
+	uint64_t holewr                       : 1;  /**< Write reference to 256MB hole enable */
+	uint64_t holerd                       : 1;  /**< Read reference to 256MB hole enable */
+#else
+	uint64_t holerd                       : 1;
+	uint64_t holewr                       : 1;
+	uint64_t vrtwr                        : 1;
+	uint64_t vrtidrng                     : 1;
+	uint64_t vrtadrng                     : 1;
+	uint64_t vrtpe                        : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_l2c_int_ena cvmx_l2c_int_ena_t;
+
+/**
+ * cvmx_l2c_int_reg
+ *
+ * L2C_INT_REG = L2C Interrupt Register
+ *
+ */
+union cvmx_l2c_int_reg
+{
+	uint64_t u64;
+	struct cvmx_l2c_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in either
+                                                         the L2C_ERR_TDT0 or L2C_ERR_TTG0 CSR */
+	uint64_t reserved_8_15                : 8;
+	uint64_t bigrd                        : 1;  /**< Read reference past L2C_BIG_CTL[MAXDRAM] occurred */
+	uint64_t bigwr                        : 1;  /**< Write reference past L2C_BIG_CTL[MAXDRAM] occurred */
+	uint64_t vrtpe                        : 1;  /**< L2C_VRT_MEM read found a parity error
+                                                         Whenever an L2C_VRT_MEM read finds a parity error,
+                                                         that L2C_VRT_MEM cannot cause stores to be blocked.
+                                                         Software should correct the error. */
+	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range
+                                                         Set when a L2C_VRT_CTL[MEMSZ] violation blocked a
+                                                         store.
+                                                         L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */
+	uint64_t vrtidrng                     : 1;  /**< Virtualization ID out of range
+                                                         Set when a L2C_VRT_CTL[NUMID] violation blocked a
+                                                         store. */
+	uint64_t vrtwr                        : 1;  /**< Virtualization ID prevented a write
+                                                         Set when L2C_VRT_MEM blocked a store. */
+	uint64_t holewr                       : 1;  /**< Write reference to 256MB hole occurred */
+	uint64_t holerd                       : 1;  /**< Read reference to 256MB hole occurred */
+#else
+	uint64_t holerd                       : 1;
+	uint64_t holewr                       : 1;
+	uint64_t vrtwr                        : 1;
+	uint64_t vrtidrng                     : 1;
+	uint64_t vrtadrng                     : 1;
+	uint64_t vrtpe                        : 1;
+	uint64_t bigwr                        : 1;
+	uint64_t bigrd                        : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t tad0                         : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_l2c_int_reg_s             cn63xx;
+	struct cvmx_l2c_int_reg_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t tad0                         : 1;  /**< When set, the enabled interrupt is in either
+                                                         the L2C_ERR_TDT0 or L2C_ERR_TTG0 CSR */
+	uint64_t reserved_6_15                : 10;
+	uint64_t vrtpe                        : 1;  /**< L2C_VRT_MEM read found a parity error
+                                                         Whenever an L2C_VRT_MEM read finds a parity error,
+                                                         that L2C_VRT_MEM cannot cause stores to be blocked.
+                                                         Software should correct the error. */
+	uint64_t vrtadrng                     : 1;  /**< Address outside of virtualization range
+                                                         Set when a L2C_VRT_CTL[MEMSZ] violation blocked a
+                                                         store.
+                                                         L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */
+	uint64_t vrtidrng                     : 1;  /**< Virtualization ID out of range
+                                                         Set when a L2C_VRT_CTL[NUMID] violation blocked a
+                                                         store. */
+	uint64_t vrtwr                        : 1;  /**< Virtualization ID prevented a write
+                                                         Set when L2C_VRT_MEM blocked a store. */
+	uint64_t holewr                       : 1;  /**< Write reference to 256MB hole occurred */
+	uint64_t holerd                       : 1;  /**< Read reference to 256MB hole occurred */
+#else
+	uint64_t holerd                       : 1;
+	uint64_t holewr                       : 1;
+	uint64_t vrtwr                        : 1;
+	uint64_t vrtidrng                     : 1;
+	uint64_t vrtadrng                     : 1;
+	uint64_t vrtpe                        : 1;
+	uint64_t reserved_6_15                : 10;
+	uint64_t tad0                         : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_l2c_int_reg cvmx_l2c_int_reg_t;
+
+/**
+ * cvmx_l2c_int_stat
+ *
+ * L2C_INT_STAT = L2C Global Interrupt Status Register
+ *
+ * Description:
+ */
+union cvmx_l2c_int_stat
+{
+	uint64_t u64;
+	struct cvmx_l2c_int_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t lck2                         : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked.
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR2] */
+	uint64_t lck                          : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR] */
+	uint64_t l2dded                       : 1;  /**< L2D Double Error detected (DED)
+                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_ERR] */
+	uint64_t l2dsec                       : 1;  /**< L2D Single Error corrected (SEC)
+                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR] */
+	uint64_t l2tded                       : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_ERR] */
+	uint64_t l2tsec                       : 1;  /**< L2T Single Bit Error corrected (SEC) status
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR] */
+	uint64_t oob3                         : 1;  /**< DMA Out of Bounds Interrupt Status Range#3 */
+	uint64_t oob2                         : 1;  /**< DMA Out of Bounds Interrupt Status Range#2 */
+	uint64_t oob1                         : 1;  /**< DMA Out of Bounds Interrupt Status Range#1 */
+#else
+	uint64_t oob1                         : 1;
+	uint64_t oob2                         : 1;
+	uint64_t oob3                         : 1;
+	uint64_t l2tsec                       : 1;
+	uint64_t l2tded                       : 1;
+	uint64_t l2dsec                       : 1;
+	uint64_t l2dded                       : 1;
+	uint64_t lck                          : 1;
+	uint64_t lck2                         : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_int_stat_s            cn52xx;
+	struct cvmx_l2c_int_stat_s            cn52xxp1;
+	struct cvmx_l2c_int_stat_s            cn56xx;
+	struct cvmx_l2c_int_stat_s            cn56xxp1;
+};
+typedef union cvmx_l2c_int_stat cvmx_l2c_int_stat_t;
+
+/**
+ * cvmx_l2c_ioc#_pfc
+ *
+ * L2C_IOC_PFC = L2C IOC Performance Counter(s)
+ *
+ */
+union cvmx_l2c_iocx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_iocx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_iocx_pfc_s            cn63xx;
+	struct cvmx_l2c_iocx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_iocx_pfc cvmx_l2c_iocx_pfc_t;
+
+/**
+ * cvmx_l2c_ior#_pfc
+ *
+ * L2C_IOR_PFC = L2C IOR Performance Counter(s)
+ *
+ */
+union cvmx_l2c_iorx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_iorx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_iorx_pfc_s            cn63xx;
+	struct cvmx_l2c_iorx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_iorx_pfc cvmx_l2c_iorx_pfc_t;
+
+/**
+ * cvmx_l2c_lckbase
+ *
+ * L2C_LCKBASE = L2C LockDown Base Register
+ *
+ * Description: L2C LockDown Base Register
+ *
+ * Notes:
+ * (1) SW RESTRICTION \#1: SW must manage the L2 Data Store lockdown space such that at least 1
+ *     set per cache line remains in the 'unlocked' (normal) state to allow general caching operations.
+ *     If SW violates this restriction, a status bit is set (LCK_ERR) and an interrupt is posted.
+ *     [this limits the total lockdown space to 7/8ths of the total L2 data store = 896KB]
+ * (2) IOB initiated LDI commands are ignored (only PP initiated LDI/LDD commands are considered
+ *     for lockdown).
+ * (3) To 'unlock' a locked cache line, SW can use the FLUSH-INVAL CSR mechanism (see L2C_DBG[FINV]).
+ * (4) LCK_ENA MUST only be activated when debug modes are disabled (L2C_DBG[L2T], L2C_DBG[L2D], L2C_DBG[FINV]).
+ */
+union cvmx_l2c_lckbase
+{
+	uint64_t u64;
+	struct cvmx_l2c_lckbase_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t lck_base                     : 27; /**< Base Memory block address[33:7]. Specifies the
+                                                         starting address of the lockdown region. */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t lck_ena                      : 1;  /**< L2 Cache Lock Enable
+                                                         When the LCK_ENA=1, all LDI(I-stream Load) or
+                                                         LDD(L1 load-miss) commands issued from the
+                                                         diagnostic PP (specified by the L2C_DBG[PPNUM]),
+                                                         which fall within a predefined lockdown address
+                                                         range (specified by: [lck_base:lck_base+lck_offset])
+                                                         are LOCKED in the L2 cache. The LOCKED state is
+                                                         denoted using an explicit L2 Tag bit (L=1).
+                                                         If the LOCK request L2-Hits (on ANY SET), then data is
+                                                         returned from the L2 and the hit set is updated to the
+                                                         LOCKED state. NOTE: If the Hit Set# is outside the
+                                                         available sets for a given PP (see UMSK'x'), the
+                                                         the LOCK bit is still SET. If the programmer's intent
+                                                         is to explicitly LOCK addresses into 'available' sets,
+                                                         care must be taken to flush-invalidate the cache first
+                                                         (to avoid such situations). Not following this procedure
+                                                         can lead to LCKERR2 interrupts.
+                                                         If the LOCK request L2-Misses, a replacment set is
+                                                         chosen(from the available sets (UMSK'x').
+                                                         If the replacement set contains a dirty-victim it is
+                                                         written back to memory. Memory read data is then written
+                                                         into the replacement set, and the replacment SET is
+                                                         updated to the LOCKED state(L=1).
+                                                         NOTE: SETs that contain LOCKED addresses are
+                                                         excluded from the replacement set selection algorithm.
+                                                         NOTE: The LDD command will allocate the DuTag as normal.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the address is 'aliased' first
+                                                         before being checked against the lockdown address
+                                                         range. To ensure an 'aliased' address is properly locked,
+                                                         it is recommmended that SW preload the 'aliased' locked adddress
+                                                         into the L2C_LCKBASE[LCK_BASE] register (while keeping
+                                                         L2C_LCKOFF[LCK_OFFSET]=0).
+                                                         NOTE: The OCTEON(N3) implementation only supports 16GB(MAX) of
+                                                         physical memory. Therefore, only byte address[33:0] are used
+                                                         (ie: address[35:34] are ignored). */
+#else
+	uint64_t lck_ena                      : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t lck_base                     : 27;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_l2c_lckbase_s             cn30xx;
+	struct cvmx_l2c_lckbase_s             cn31xx;
+	struct cvmx_l2c_lckbase_s             cn38xx;
+	struct cvmx_l2c_lckbase_s             cn38xxp2;
+	struct cvmx_l2c_lckbase_s             cn50xx;
+	struct cvmx_l2c_lckbase_s             cn52xx;
+	struct cvmx_l2c_lckbase_s             cn52xxp1;
+	struct cvmx_l2c_lckbase_s             cn56xx;
+	struct cvmx_l2c_lckbase_s             cn56xxp1;
+	struct cvmx_l2c_lckbase_s             cn58xx;
+	struct cvmx_l2c_lckbase_s             cn58xxp1;
+};
+typedef union cvmx_l2c_lckbase cvmx_l2c_lckbase_t;
+
+/**
+ * cvmx_l2c_lckoff
+ *
+ * L2C_LCKOFF = L2C LockDown OFFSET Register
+ *
+ * Description: L2C LockDown OFFSET Register
+ *
+ * Notes:
+ * (1) The generation of the end lockdown block address will 'wrap'.
+ * (2) The minimum granularity for lockdown is 1 cache line (= 128B block)
+ */
+union cvmx_l2c_lckoff
+{
+	uint64_t u64;
+	struct cvmx_l2c_lckoff_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t lck_offset                   : 10; /**< LockDown block Offset. Used in determining
+                                                         the ending block address of the lockdown
+                                                         region:
+                                                         End Lockdown block Address[33:7] =
+                                                         LCK_BASE[33:7]+LCK_OFFSET[9:0] */
+#else
+	uint64_t lck_offset                   : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_l2c_lckoff_s              cn30xx;
+	struct cvmx_l2c_lckoff_s              cn31xx;
+	struct cvmx_l2c_lckoff_s              cn38xx;
+	struct cvmx_l2c_lckoff_s              cn38xxp2;
+	struct cvmx_l2c_lckoff_s              cn50xx;
+	struct cvmx_l2c_lckoff_s              cn52xx;
+	struct cvmx_l2c_lckoff_s              cn52xxp1;
+	struct cvmx_l2c_lckoff_s              cn56xx;
+	struct cvmx_l2c_lckoff_s              cn56xxp1;
+	struct cvmx_l2c_lckoff_s              cn58xx;
+	struct cvmx_l2c_lckoff_s              cn58xxp1;
+};
+typedef union cvmx_l2c_lckoff cvmx_l2c_lckoff_t;
+
+/**
+ * cvmx_l2c_lfb0
+ *
+ * L2C_LFB0 = L2C LFB DEBUG 0 Register
+ *
+ * Description: L2C LFB Contents (Status Bits)
+ */
+union cvmx_l2c_lfb0
+{
+	uint64_t u64;
+	struct cvmx_l2c_lfb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
+	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
+	uint64_t stinv                        : 1;  /**< LFB ST* Invalidate Status */
+	uint64_t stcfl                        : 1;  /**< LFB STC=FAIL Status */
+	uint64_t vam                          : 1;  /**< Valid Full Address Match Status */
+	uint64_t inxt                         : 4;  /**< Next LFB Pointer(invalid if ITL=1) */
+	uint64_t itl                          : 1;  /**< LFB Tail of List Indicator */
+	uint64_t ihd                          : 1;  /**< LFB Head of List Indicator */
+	uint64_t set                          : 3;  /**< SET# used for DS-OP (hit=hset/miss=rset) */
+	uint64_t vabnum                       : 4;  /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+	uint64_t sid                          : 9;  /**< LFB Source ID */
+	uint64_t cmd                          : 4;  /**< LFB Command */
+	uint64_t vld                          : 1;  /**< LFB Valid */
+#else
+	uint64_t vld                          : 1;
+	uint64_t cmd                          : 4;
+	uint64_t sid                          : 9;
+	uint64_t vabnum                       : 4;
+	uint64_t set                          : 3;
+	uint64_t ihd                          : 1;
+	uint64_t itl                          : 1;
+	uint64_t inxt                         : 4;
+	uint64_t vam                          : 1;
+	uint64_t stcfl                        : 1;
+	uint64_t stinv                        : 1;
+	uint64_t stpnd                        : 1;
+	uint64_t stcpnd                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_lfb0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
+	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
+	uint64_t stinv                        : 1;  /**< LFB ST* Invalidate Status */
+	uint64_t stcfl                        : 1;  /**< LFB STC=FAIL Status */
+	uint64_t vam                          : 1;  /**< Valid Full Address Match Status */
+	uint64_t reserved_25_26               : 2;
+	uint64_t inxt                         : 2;  /**< Next LFB Pointer(invalid if ITL=1) */
+	uint64_t itl                          : 1;  /**< LFB Tail of List Indicator */
+	uint64_t ihd                          : 1;  /**< LFB Head of List Indicator */
+	uint64_t reserved_20_20               : 1;
+	uint64_t set                          : 2;  /**< SET# used for DS-OP (hit=hset/miss=rset) */
+	uint64_t reserved_16_17               : 2;
+	uint64_t vabnum                       : 2;  /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+	uint64_t sid                          : 9;  /**< LFB Source ID */
+	uint64_t cmd                          : 4;  /**< LFB Command */
+	uint64_t vld                          : 1;  /**< LFB Valid */
+#else
+	uint64_t vld                          : 1;
+	uint64_t cmd                          : 4;
+	uint64_t sid                          : 9;
+	uint64_t vabnum                       : 2;
+	uint64_t reserved_16_17               : 2;
+	uint64_t set                          : 2;
+	uint64_t reserved_20_20               : 1;
+	uint64_t ihd                          : 1;
+	uint64_t itl                          : 1;
+	uint64_t inxt                         : 2;
+	uint64_t reserved_25_26               : 2;
+	uint64_t vam                          : 1;
+	uint64_t stcfl                        : 1;
+	uint64_t stinv                        : 1;
+	uint64_t stpnd                        : 1;
+	uint64_t stcpnd                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_lfb0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
+	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
+	uint64_t stinv                        : 1;  /**< LFB ST* Invalidate Status */
+	uint64_t stcfl                        : 1;  /**< LFB STC=FAIL Status */
+	uint64_t vam                          : 1;  /**< Valid Full Address Match Status */
+	uint64_t reserved_26_26               : 1;
+	uint64_t inxt                         : 3;  /**< Next LFB Pointer(invalid if ITL=1) */
+	uint64_t itl                          : 1;  /**< LFB Tail of List Indicator */
+	uint64_t ihd                          : 1;  /**< LFB Head of List Indicator */
+	uint64_t reserved_20_20               : 1;
+	uint64_t set                          : 2;  /**< SET# used for DS-OP (hit=hset/miss=rset) */
+	uint64_t reserved_17_17               : 1;
+	uint64_t vabnum                       : 3;  /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+	uint64_t sid                          : 9;  /**< LFB Source ID */
+	uint64_t cmd                          : 4;  /**< LFB Command */
+	uint64_t vld                          : 1;  /**< LFB Valid */
+#else
+	uint64_t vld                          : 1;
+	uint64_t cmd                          : 4;
+	uint64_t sid                          : 9;
+	uint64_t vabnum                       : 3;
+	uint64_t reserved_17_17               : 1;
+	uint64_t set                          : 2;
+	uint64_t reserved_20_20               : 1;
+	uint64_t ihd                          : 1;
+	uint64_t itl                          : 1;
+	uint64_t inxt                         : 3;
+	uint64_t reserved_26_26               : 1;
+	uint64_t vam                          : 1;
+	uint64_t stcfl                        : 1;
+	uint64_t stinv                        : 1;
+	uint64_t stpnd                        : 1;
+	uint64_t stcpnd                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_lfb0_s                cn38xx;
+	struct cvmx_l2c_lfb0_s                cn38xxp2;
+	struct cvmx_l2c_lfb0_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t stcpnd                       : 1;  /**< LFB STC Pending Status */
+	uint64_t stpnd                        : 1;  /**< LFB ST* Pending Status */
+	uint64_t stinv                        : 1;  /**< LFB ST* Invalidate Status */
+	uint64_t stcfl                        : 1;  /**< LFB STC=FAIL Status */
+	uint64_t vam                          : 1;  /**< Valid Full Address Match Status */
+	uint64_t reserved_26_26               : 1;
+	uint64_t inxt                         : 3;  /**< Next LFB Pointer(invalid if ITL=1) */
+	uint64_t itl                          : 1;  /**< LFB Tail of List Indicator */
+	uint64_t ihd                          : 1;  /**< LFB Head of List Indicator */
+	uint64_t set                          : 3;  /**< SET# used for DS-OP (hit=hset/miss=rset) */
+	uint64_t reserved_17_17               : 1;
+	uint64_t vabnum                       : 3;  /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+	uint64_t sid                          : 9;  /**< LFB Source ID */
+	uint64_t cmd                          : 4;  /**< LFB Command */
+	uint64_t vld                          : 1;  /**< LFB Valid */
+#else
+	uint64_t vld                          : 1;
+	uint64_t cmd                          : 4;
+	uint64_t sid                          : 9;
+	uint64_t vabnum                       : 3;
+	uint64_t reserved_17_17               : 1;
+	uint64_t set                          : 3;
+	uint64_t ihd                          : 1;
+	uint64_t itl                          : 1;
+	uint64_t inxt                         : 3;
+	uint64_t reserved_26_26               : 1;
+	uint64_t vam                          : 1;
+	uint64_t stcfl                        : 1;
+	uint64_t stinv                        : 1;
+	uint64_t stpnd                        : 1;
+	uint64_t stcpnd                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_lfb0_cn50xx           cn52xx;
+	struct cvmx_l2c_lfb0_cn50xx           cn52xxp1;
+	struct cvmx_l2c_lfb0_s                cn56xx;
+	struct cvmx_l2c_lfb0_s                cn56xxp1;
+	struct cvmx_l2c_lfb0_s                cn58xx;
+	struct cvmx_l2c_lfb0_s                cn58xxp1;
+};
+typedef union cvmx_l2c_lfb0 cvmx_l2c_lfb0_t;
+
+/**
+ * cvmx_l2c_lfb1
+ *
+ * L2C_LFB1 = L2C LFB DEBUG 1 Register
+ *
+ * Description: L2C LFB Contents (Wait Bits)
+ */
+union cvmx_l2c_lfb1
+{
+	uint64_t u64;
+	struct cvmx_l2c_lfb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t dsgoing                      : 1;  /**< LFB DS Going (in flight) */
+	uint64_t bid                          : 2;  /**< LFB DS Bid# */
+	uint64_t wtrsp                        : 1;  /**< LFB Waiting for RSC Response [FILL,STRSP] completion */
+	uint64_t wtdw                         : 1;  /**< LFB Waiting for DS-WR completion */
+	uint64_t wtdq                         : 1;  /**< LFB Waiting for LFB-DQ */
+	uint64_t wtwhp                        : 1;  /**< LFB Waiting for Write-Hit Partial L2 DS-WR completion */
+	uint64_t wtwhf                        : 1;  /**< LFB Waiting for Write-Hit Full L2 DS-WR completion */
+	uint64_t wtwrm                        : 1;  /**< LFB Waiting for Write-Miss L2 DS-WR completion */
+	uint64_t wtstm                        : 1;  /**< LFB Waiting for Write-Miss L2 DS-WR completion */
+	uint64_t wtrda                        : 1;  /**< LFB Waiting for Read-Miss L2 DS-WR completion */
+	uint64_t wtstdt                       : 1;  /**< LFB Waiting for all ST write Data to arrive on XMD bus */
+	uint64_t wtstrsp                      : 1;  /**< LFB Waiting for ST RSC/RSD to be issued on RSP
+                                                         (with invalidates) */
+	uint64_t wtstrsc                      : 1;  /**< LFB Waiting for ST RSC-Only to be issued on RSP
+                                                         (no-invalidates) */
+	uint64_t wtvtm                        : 1;  /**< LFB Waiting for Victim Read L2 DS-RD completion */
+	uint64_t wtmfl                        : 1;  /**< LFB Waiting for Memory Fill completion to MRB */
+	uint64_t prbrty                       : 1;  /**< Probe-Retry Detected - waiting for probe completion */
+	uint64_t wtprb                        : 1;  /**< LFB Waiting for Probe */
+	uint64_t vld                          : 1;  /**< LFB Valid */
+#else
+	uint64_t vld                          : 1;
+	uint64_t wtprb                        : 1;
+	uint64_t prbrty                       : 1;
+	uint64_t wtmfl                        : 1;
+	uint64_t wtvtm                        : 1;
+	uint64_t wtstrsc                      : 1;
+	uint64_t wtstrsp                      : 1;
+	uint64_t wtstdt                       : 1;
+	uint64_t wtrda                        : 1;
+	uint64_t wtstm                        : 1;
+	uint64_t wtwrm                        : 1;
+	uint64_t wtwhf                        : 1;
+	uint64_t wtwhp                        : 1;
+	uint64_t wtdq                         : 1;
+	uint64_t wtdw                         : 1;
+	uint64_t wtrsp                        : 1;
+	uint64_t bid                          : 2;
+	uint64_t dsgoing                      : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_l2c_lfb1_s                cn30xx;
+	struct cvmx_l2c_lfb1_s                cn31xx;
+	struct cvmx_l2c_lfb1_s                cn38xx;
+	struct cvmx_l2c_lfb1_s                cn38xxp2;
+	struct cvmx_l2c_lfb1_s                cn50xx;
+	struct cvmx_l2c_lfb1_s                cn52xx;
+	struct cvmx_l2c_lfb1_s                cn52xxp1;
+	struct cvmx_l2c_lfb1_s                cn56xx;
+	struct cvmx_l2c_lfb1_s                cn56xxp1;
+	struct cvmx_l2c_lfb1_s                cn58xx;
+	struct cvmx_l2c_lfb1_s                cn58xxp1;
+};
+typedef union cvmx_l2c_lfb1 cvmx_l2c_lfb1_t;
+
+/**
+ * cvmx_l2c_lfb2
+ *
+ * L2C_LFB2 = L2C LFB DEBUG 2 Register
+ *
+ * Description: L2C LFB Contents Tag/Index
+ */
+union cvmx_l2c_lfb2
+{
+	uint64_t u64;
+	struct cvmx_l2c_lfb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_l2c_lfb2_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t lfb_tag                      : 19; /**< LFB TAG[33:15] */
+	uint64_t lfb_idx                      : 8;  /**< LFB IDX[14:7] */
+#else
+	uint64_t lfb_idx                      : 8;
+	uint64_t lfb_tag                      : 19;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_lfb2_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t lfb_tag                      : 17; /**< LFB TAG[33:16] */
+	uint64_t lfb_idx                      : 10; /**< LFB IDX[15:7] */
+#else
+	uint64_t lfb_idx                      : 10;
+	uint64_t lfb_tag                      : 17;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_lfb2_cn31xx           cn38xx;
+	struct cvmx_l2c_lfb2_cn31xx           cn38xxp2;
+	struct cvmx_l2c_lfb2_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t lfb_tag                      : 20; /**< LFB TAG[33:14] */
+	uint64_t lfb_idx                      : 7;  /**< LFB IDX[13:7] */
+#else
+	uint64_t lfb_idx                      : 7;
+	uint64_t lfb_tag                      : 20;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_lfb2_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t lfb_tag                      : 18; /**< LFB TAG[33:16] */
+	uint64_t lfb_idx                      : 9;  /**< LFB IDX[15:7] */
+#else
+	uint64_t lfb_idx                      : 9;
+	uint64_t lfb_tag                      : 18;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn52xx;
+	struct cvmx_l2c_lfb2_cn52xx           cn52xxp1;
+	struct cvmx_l2c_lfb2_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t lfb_tag                      : 16; /**< LFB TAG[33:18] */
+	uint64_t lfb_idx                      : 11; /**< LFB IDX[17:7] */
+#else
+	uint64_t lfb_idx                      : 11;
+	uint64_t lfb_tag                      : 16;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn56xx;
+	struct cvmx_l2c_lfb2_cn56xx           cn56xxp1;
+	struct cvmx_l2c_lfb2_cn56xx           cn58xx;
+	struct cvmx_l2c_lfb2_cn56xx           cn58xxp1;
+};
+typedef union cvmx_l2c_lfb2 cvmx_l2c_lfb2_t;
+
+/**
+ * cvmx_l2c_lfb3
+ *
+ * L2C_LFB3 = L2C LFB DEBUG 3 Register
+ *
+ * Description: LFB High Water Mark Register
+ */
+union cvmx_l2c_lfb3
+{
+	uint64_t u64;
+	struct cvmx_l2c_lfb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
+	uint64_t lfb_hwm                      : 4;  /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=15: 16 LFB Entries available */
+#else
+	uint64_t lfb_hwm                      : 4;
+	uint64_t stpartdis                    : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_l2c_lfb3_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t lfb_hwm                      : 2;  /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=3:   4 LFB Entries available */
+#else
+	uint64_t lfb_hwm                      : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t stpartdis                    : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_lfb3_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t stpartdis                    : 1;  /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t lfb_hwm                      : 3;  /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=7:   8 LFB Entries available */
+#else
+	uint64_t lfb_hwm                      : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t stpartdis                    : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_lfb3_s                cn38xx;
+	struct cvmx_l2c_lfb3_s                cn38xxp2;
+	struct cvmx_l2c_lfb3_cn31xx           cn50xx;
+	struct cvmx_l2c_lfb3_cn31xx           cn52xx;
+	struct cvmx_l2c_lfb3_cn31xx           cn52xxp1;
+	struct cvmx_l2c_lfb3_s                cn56xx;
+	struct cvmx_l2c_lfb3_s                cn56xxp1;
+	struct cvmx_l2c_lfb3_s                cn58xx;
+	struct cvmx_l2c_lfb3_s                cn58xxp1;
+};
+typedef union cvmx_l2c_lfb3 cvmx_l2c_lfb3_t;
+
+/**
+ * cvmx_l2c_oob
+ *
+ * L2C_OOB = L2C Out of Bounds Global Enables
+ *
+ * Description: Defines DMA "Out of Bounds" global enables.
+ */
+union cvmx_l2c_oob
+{
+	uint64_t u64;
+	struct cvmx_l2c_oob_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dwbena                       : 1;  /**< DMA Out of Bounds Range Checker for DMA DWB
+                                                         commands (Don't WriteBack).
+                                                         When enabled, any DMA DWB commands which hit 1-of-3
+                                                         out of bounds regions will be logged into
+                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
+                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
+                                                         is enabled, an interrupt will also be reported. */
+	uint64_t stena                        : 1;  /**< DMA Out of Bounds Range Checker for DMA store
+                                                         commands (STF/P/T).
+                                                         When enabled, any DMA store commands (STF/P/T) which
+                                                         hit 1-of-3 out of bounds regions will be logged into
+                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
+                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
+                                                         is enabled, an interrupt will also be reported. */
+#else
+	uint64_t stena                        : 1;
+	uint64_t dwbena                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_l2c_oob_s                 cn52xx;
+	struct cvmx_l2c_oob_s                 cn52xxp1;
+	struct cvmx_l2c_oob_s                 cn56xx;
+	struct cvmx_l2c_oob_s                 cn56xxp1;
+};
+typedef union cvmx_l2c_oob cvmx_l2c_oob_t;
+
+/**
+ * cvmx_l2c_oob1
+ *
+ * L2C_OOB1 = L2C Out of Bounds Range Checker
+ *
+ * Description: Defines DMA "Out of Bounds" region \#1. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+union cvmx_l2c_oob1
+{
+	uint64_t u64;
+	struct cvmx_l2c_oob1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB1]
+                                                         is cleared. */
+	uint64_t fsrc                         : 1;  /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB1]
+                                                         is cleared. */
+	uint64_t reserved_34_35               : 2;
+	uint64_t sadr                         : 14; /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+	uint64_t reserved_14_19               : 6;
+	uint64_t size                         : 14; /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+	uint64_t size                         : 14;
+	uint64_t reserved_14_19               : 6;
+	uint64_t sadr                         : 14;
+	uint64_t reserved_34_35               : 2;
+	uint64_t fsrc                         : 1;
+	uint64_t fadr                         : 27;
+#endif
+	} s;
+	struct cvmx_l2c_oob1_s                cn52xx;
+	struct cvmx_l2c_oob1_s                cn52xxp1;
+	struct cvmx_l2c_oob1_s                cn56xx;
+	struct cvmx_l2c_oob1_s                cn56xxp1;
+};
+typedef union cvmx_l2c_oob1 cvmx_l2c_oob1_t;
+
+/**
+ * cvmx_l2c_oob2
+ *
+ * L2C_OOB2 = L2C Out of Bounds Range Checker
+ *
+ * Description: Defines DMA "Out of Bounds" region \#2. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+union cvmx_l2c_oob2
+{
+	uint64_t u64;
+	struct cvmx_l2c_oob2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB2]
+                                                         is cleared. */
+	uint64_t fsrc                         : 1;  /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB2]
+                                                         is cleared. */
+	uint64_t reserved_34_35               : 2;
+	uint64_t sadr                         : 14; /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+	uint64_t reserved_14_19               : 6;
+	uint64_t size                         : 14; /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+	uint64_t size                         : 14;
+	uint64_t reserved_14_19               : 6;
+	uint64_t sadr                         : 14;
+	uint64_t reserved_34_35               : 2;
+	uint64_t fsrc                         : 1;
+	uint64_t fadr                         : 27;
+#endif
+	} s;
+	struct cvmx_l2c_oob2_s                cn52xx;
+	struct cvmx_l2c_oob2_s                cn52xxp1;
+	struct cvmx_l2c_oob2_s                cn56xx;
+	struct cvmx_l2c_oob2_s                cn56xxp1;
+};
+typedef union cvmx_l2c_oob2 cvmx_l2c_oob2_t;
+
+/**
+ * cvmx_l2c_oob3
+ *
+ * L2C_OOB3 = L2C Out of Bounds Range Checker
+ *
+ * Description: Defines DMA "Out of Bounds" region \#3. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+union cvmx_l2c_oob3
+{
+	uint64_t u64;
+	struct cvmx_l2c_oob3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fadr                         : 27; /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[00B3]
+                                                         is cleared. */
+	uint64_t fsrc                         : 1;  /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[00B3]
+                                                         is cleared. */
+	uint64_t reserved_34_35               : 2;
+	uint64_t sadr                         : 14; /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+	uint64_t reserved_14_19               : 6;
+	uint64_t size                         : 14; /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+	uint64_t size                         : 14;
+	uint64_t reserved_14_19               : 6;
+	uint64_t sadr                         : 14;
+	uint64_t reserved_34_35               : 2;
+	uint64_t fsrc                         : 1;
+	uint64_t fadr                         : 27;
+#endif
+	} s;
+	struct cvmx_l2c_oob3_s                cn52xx;
+	struct cvmx_l2c_oob3_s                cn52xxp1;
+	struct cvmx_l2c_oob3_s                cn56xx;
+	struct cvmx_l2c_oob3_s                cn56xxp1;
+};
+typedef union cvmx_l2c_oob3 cvmx_l2c_oob3_t;
+
+/**
+ * cvmx_l2c_pfc#
+ *
+ * L2C_PFC0 = L2 Performance Counter \#0
+ *
+ * Description:
+ */
+union cvmx_l2c_pfcx
+{
+	uint64_t u64;
+	struct cvmx_l2c_pfcx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t pfcnt0                       : 36; /**< Performance Counter \#0 */
+#else
+	uint64_t pfcnt0                       : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_l2c_pfcx_s                cn30xx;
+	struct cvmx_l2c_pfcx_s                cn31xx;
+	struct cvmx_l2c_pfcx_s                cn38xx;
+	struct cvmx_l2c_pfcx_s                cn38xxp2;
+	struct cvmx_l2c_pfcx_s                cn50xx;
+	struct cvmx_l2c_pfcx_s                cn52xx;
+	struct cvmx_l2c_pfcx_s                cn52xxp1;
+	struct cvmx_l2c_pfcx_s                cn56xx;
+	struct cvmx_l2c_pfcx_s                cn56xxp1;
+	struct cvmx_l2c_pfcx_s                cn58xx;
+	struct cvmx_l2c_pfcx_s                cn58xxp1;
+};
+typedef union cvmx_l2c_pfcx cvmx_l2c_pfcx_t;
+
+/**
+ * cvmx_l2c_pfctl
+ *
+ * L2C_PFCTL = L2 Performance Counter Control Register
+ *
+ * Description: Controls the actions of the 4 Performance Counters
+ *
+ * Notes:
+ * - There are four 36b performance counter registers which can simultaneously count events.
+ * Each Counter's event is programmably selected via the corresponding CNTxSEL field:
+ *       CNTxSEL[5:0]    Event
+ *    -----------------+-----------------------
+ *             0       | Cycles
+ *             1       | L2 LDI Command Miss (NOTE: Both PP and IOB are cabable of generating LDI)
+ *             2       | L2 LDI Command Hit  (NOTE: Both PP and IOB are cabable of generating LDI)
+ *             3       | L2 non-LDI Command Miss
+ *             4       | L2 non-LDI Command Hit
+ *             5       | L2 Miss (total)
+ *             6       | L2 Hit (total)
+ *             7       | L2 Victim Buffer Hit (Retry Probe)
+ *             8       | LFB-NQ Index Conflict
+ *             9       | L2 Tag Probe (issued - could be VB-Retried)
+ *            10       | L2 Tag Update (completed - note: some CMD types do not update)
+ *            11       | L2 Tag Probe Completed (beyond VB-RTY window)
+ *            12       | L2 Tag Dirty Victim
+ *            13       | L2 Data Store NOP
+ *            14       | L2 Data Store READ
+ *            15       | L2 Data Store WRITE
+ *            16       | Memory Fill Data valid (1 strobe/32B)
+ *            17       | Memory Write Request
+ *            18       | Memory Read Request
+ *            19       | Memory Write Data valid (1 strobe/32B)
+ *            20       | XMC NOP (XMC Bus Idle)
+ *            21       | XMC LDT (Load-Through Request)
+ *            22       | XMC LDI (L2 Load I-Stream Request)
+ *            23       | XMC LDD (L2 Load D-stream Request)
+ *            24       | XMC STF (L2 Store Full cacheline Request)
+ *            25       | XMC STT (L2 Store Through Request)
+ *            26       | XMC STP (L2 Store Partial Request)
+ *            27       | XMC STC (L2 Store Conditional Request)
+ *            28       | XMC DWB (L2 Don't WriteBack Request)
+ *            29       | XMC PL2 (L2 Prefetch Request)
+ *            30       | XMC PSL1 (L1 Prefetch Request)
+ *            31       | XMC IOBLD
+ *            32       | XMC IOBST
+ *            33       | XMC IOBDMA
+ *            34       | XMC IOBRSP
+ *            35       | XMD Bus valid (all)
+ *            36       | XMD Bus valid (DST=L2C) Memory Data
+ *            37       | XMD Bus valid (DST=IOB) REFL Data
+ *            38       | XMD Bus valid (DST=PP) IOBRSP Data
+ *            39       | RSC NOP
+ *            40       | RSC STDN
+ *            41       | RSC FILL
+ *            42       | RSC REFL
+ *            43       | RSC STIN
+ *            44       | RSC SCIN
+ *            45       | RSC SCFL
+ *            46       | RSC SCDN
+ *            47       | RSD Data Valid
+ *            48       | RSD Data Valid (FILL)
+ *            49       | RSD Data Valid (STRSP)
+ *            50       | RSD Data Valid (REFL)
+ *            51       | LRF-REQ (LFB-NQ)
+ *            52       | DT RD-ALLOC (LDD/PSL1 Commands)
+ *            53       | DT WR-INVAL (ST* Commands)
+ */
+union cvmx_l2c_pfctl
+{
+	uint64_t u64;
+	struct cvmx_l2c_pfctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t cnt3rdclr                    : 1;  /**< Performance Counter 3 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC3
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event. */
+	uint64_t cnt2rdclr                    : 1;  /**< Performance Counter 2 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC2
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event. */
+	uint64_t cnt1rdclr                    : 1;  /**< Performance Counter 1 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC1
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event. */
+	uint64_t cnt0rdclr                    : 1;  /**< Performance Counter 0 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC0
+                                                         register will 'auto-clear' the counter. This allows
+                                                         SW to maintain accurate 'cumulative' counters.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event. */
+	uint64_t cnt3ena                      : 1;  /**< Performance Counter 3 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+	uint64_t cnt3clr                      : 1;  /**< Performance Counter 3 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+	uint64_t cnt3sel                      : 6;  /**< Performance Counter 3 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+	uint64_t cnt2ena                      : 1;  /**< Performance Counter 2 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+	uint64_t cnt2clr                      : 1;  /**< Performance Counter 2 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+	uint64_t cnt2sel                      : 6;  /**< Performance Counter 2 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+	uint64_t cnt1ena                      : 1;  /**< Performance Counter 1 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+	uint64_t cnt1clr                      : 1;  /**< Performance Counter 1 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+	uint64_t cnt1sel                      : 6;  /**< Performance Counter 1 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+	uint64_t cnt0ena                      : 1;  /**< Performance Counter 0 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+	uint64_t cnt0clr                      : 1;  /**< Performance Counter 0 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+	uint64_t cnt0sel                      : 6;  /**< Performance Counter 0 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+#else
+	uint64_t cnt0sel                      : 6;
+	uint64_t cnt0clr                      : 1;
+	uint64_t cnt0ena                      : 1;
+	uint64_t cnt1sel                      : 6;
+	uint64_t cnt1clr                      : 1;
+	uint64_t cnt1ena                      : 1;
+	uint64_t cnt2sel                      : 6;
+	uint64_t cnt2clr                      : 1;
+	uint64_t cnt2ena                      : 1;
+	uint64_t cnt3sel                      : 6;
+	uint64_t cnt3clr                      : 1;
+	uint64_t cnt3ena                      : 1;
+	uint64_t cnt0rdclr                    : 1;
+	uint64_t cnt1rdclr                    : 1;
+	uint64_t cnt2rdclr                    : 1;
+	uint64_t cnt3rdclr                    : 1;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_l2c_pfctl_s               cn30xx;
+	struct cvmx_l2c_pfctl_s               cn31xx;
+	struct cvmx_l2c_pfctl_s               cn38xx;
+	struct cvmx_l2c_pfctl_s               cn38xxp2;
+	struct cvmx_l2c_pfctl_s               cn50xx;
+	struct cvmx_l2c_pfctl_s               cn52xx;
+	struct cvmx_l2c_pfctl_s               cn52xxp1;
+	struct cvmx_l2c_pfctl_s               cn56xx;
+	struct cvmx_l2c_pfctl_s               cn56xxp1;
+	struct cvmx_l2c_pfctl_s               cn58xx;
+	struct cvmx_l2c_pfctl_s               cn58xxp1;
+};
+typedef union cvmx_l2c_pfctl cvmx_l2c_pfctl_t;
+
+/**
+ * cvmx_l2c_ppgrp
+ *
+ * L2C_PPGRP = L2C PP Group Number
+ *
+ * Description: Defines the PP(Packet Processor) PLC Group \# (0,1,2)
+ */
+union cvmx_l2c_ppgrp
+{
+	uint64_t u64;
+	struct cvmx_l2c_ppgrp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t pp11grp                      : 2;  /**< PP11 PLC Group# (0,1,2) */
+	uint64_t pp10grp                      : 2;  /**< PP10 PLC Group# (0,1,2) */
+	uint64_t pp9grp                       : 2;  /**< PP9 PLC Group# (0,1,2) */
+	uint64_t pp8grp                       : 2;  /**< PP8 PLC Group# (0,1,2) */
+	uint64_t pp7grp                       : 2;  /**< PP7 PLC Group# (0,1,2) */
+	uint64_t pp6grp                       : 2;  /**< PP6 PLC Group# (0,1,2) */
+	uint64_t pp5grp                       : 2;  /**< PP5 PLC Group# (0,1,2) */
+	uint64_t pp4grp                       : 2;  /**< PP4 PLC Group# (0,1,2) */
+	uint64_t pp3grp                       : 2;  /**< PP3 PLC Group# (0,1,2) */
+	uint64_t pp2grp                       : 2;  /**< PP2 PLC Group# (0,1,2) */
+	uint64_t pp1grp                       : 2;  /**< PP1 PLC Group# (0,1,2) */
+	uint64_t pp0grp                       : 2;  /**< PP0 PLC Group# (0,1,2) */
+#else
+	uint64_t pp0grp                       : 2;
+	uint64_t pp1grp                       : 2;
+	uint64_t pp2grp                       : 2;
+	uint64_t pp3grp                       : 2;
+	uint64_t pp4grp                       : 2;
+	uint64_t pp5grp                       : 2;
+	uint64_t pp6grp                       : 2;
+	uint64_t pp7grp                       : 2;
+	uint64_t pp8grp                       : 2;
+	uint64_t pp9grp                       : 2;
+	uint64_t pp10grp                      : 2;
+	uint64_t pp11grp                      : 2;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_l2c_ppgrp_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t pp3grp                       : 2;  /**< PP3 PLC Group# (0,1,2) */
+	uint64_t pp2grp                       : 2;  /**< PP2 PLC Group# (0,1,2) */
+	uint64_t pp1grp                       : 2;  /**< PP1 PLC Group# (0,1,2) */
+	uint64_t pp0grp                       : 2;  /**< PP0 PLC Group# (0,1,2) */
+#else
+	uint64_t pp0grp                       : 2;
+	uint64_t pp1grp                       : 2;
+	uint64_t pp2grp                       : 2;
+	uint64_t pp3grp                       : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn52xx;
+	struct cvmx_l2c_ppgrp_cn52xx          cn52xxp1;
+	struct cvmx_l2c_ppgrp_s               cn56xx;
+	struct cvmx_l2c_ppgrp_s               cn56xxp1;
+};
+typedef union cvmx_l2c_ppgrp cvmx_l2c_ppgrp_t;
+
+/**
+ * cvmx_l2c_qos_iob#
+ *
+ * L2C_QOS_IOB = L2C IOB QOS level
+ *
+ * Description:
+ */
+union cvmx_l2c_qos_iobx
+{
+	uint64_t u64;
+	struct cvmx_l2c_qos_iobx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t dwblvl                       : 2;  /**< QOS level for DWB commands. */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t lvl                          : 2;  /**< QOS level for non-DWB commands. */
+#else
+	uint64_t lvl                          : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t dwblvl                       : 2;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_l2c_qos_iobx_s            cn63xx;
+	struct cvmx_l2c_qos_iobx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_qos_iobx cvmx_l2c_qos_iobx_t;
+
+/**
+ * cvmx_l2c_qos_pp#
+ *
+ * L2C_QOS_PP = L2C PP QOS level
+ *
+ * Description:
+ */
+union cvmx_l2c_qos_ppx
+{
+	uint64_t u64;
+	struct cvmx_l2c_qos_ppx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t lvl                          : 2;  /**< QOS level to use for this PP. */
+#else
+	uint64_t lvl                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_l2c_qos_ppx_s             cn63xx;
+	struct cvmx_l2c_qos_ppx_s             cn63xxp1;
+};
+typedef union cvmx_l2c_qos_ppx cvmx_l2c_qos_ppx_t;
+
+/**
+ * cvmx_l2c_qos_wgt
+ *
+ * L2C_QOS_WGT = L2C QOS weights
+ *
+ */
+union cvmx_l2c_qos_wgt
+{
+	uint64_t u64;
+	struct cvmx_l2c_qos_wgt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wgt3                         : 8;  /**< Weight for QOS level 3 */
+	uint64_t wgt2                         : 8;  /**< Weight for QOS level 2 */
+	uint64_t wgt1                         : 8;  /**< Weight for QOS level 1 */
+	uint64_t wgt0                         : 8;  /**< Weight for QOS level 0 */
+#else
+	uint64_t wgt0                         : 8;
+	uint64_t wgt1                         : 8;
+	uint64_t wgt2                         : 8;
+	uint64_t wgt3                         : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_qos_wgt_s             cn63xx;
+	struct cvmx_l2c_qos_wgt_s             cn63xxp1;
+};
+typedef union cvmx_l2c_qos_wgt cvmx_l2c_qos_wgt_t;
+
+/**
+ * cvmx_l2c_rsc#_pfc
+ *
+ * L2C_RSC_PFC = L2C RSC Performance Counter(s)
+ *
+ */
+union cvmx_l2c_rscx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_rscx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_rscx_pfc_s            cn63xx;
+	struct cvmx_l2c_rscx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_rscx_pfc cvmx_l2c_rscx_pfc_t;
+
+/**
+ * cvmx_l2c_rsd#_pfc
+ *
+ * L2C_RSD_PFC = L2C RSD Performance Counter(s)
+ *
+ */
+union cvmx_l2c_rsdx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_rsdx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_rsdx_pfc_s            cn63xx;
+	struct cvmx_l2c_rsdx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_rsdx_pfc cvmx_l2c_rsdx_pfc_t;
+
+/**
+ * cvmx_l2c_spar0
+ *
+ * L2C_SPAR0 = L2 Set Partitioning Register (PP0-3)
+ *
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There MUST ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+union cvmx_l2c_spar0
+{
+	uint64_t u64;
+	struct cvmx_l2c_spar0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t umsk3                        : 8;  /**< PP[3] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk2                        : 8;  /**< PP[2] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk1                        : 8;  /**< PP[1] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk0                        : 8;  /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk0                        : 8;
+	uint64_t umsk1                        : 8;
+	uint64_t umsk2                        : 8;
+	uint64_t umsk3                        : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_spar0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t umsk0                        : 4;  /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk0                        : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_spar0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t umsk1                        : 4;  /**< PP[1] L2 'DO NOT USE' set partition mask */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t umsk0                        : 4;  /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk0                        : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t umsk1                        : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn31xx;
+	struct cvmx_l2c_spar0_s               cn38xx;
+	struct cvmx_l2c_spar0_s               cn38xxp2;
+	struct cvmx_l2c_spar0_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t umsk1                        : 8;  /**< PP[1] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk0                        : 8;  /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk0                        : 8;
+	uint64_t umsk1                        : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn50xx;
+	struct cvmx_l2c_spar0_s               cn52xx;
+	struct cvmx_l2c_spar0_s               cn52xxp1;
+	struct cvmx_l2c_spar0_s               cn56xx;
+	struct cvmx_l2c_spar0_s               cn56xxp1;
+	struct cvmx_l2c_spar0_s               cn58xx;
+	struct cvmx_l2c_spar0_s               cn58xxp1;
+};
+typedef union cvmx_l2c_spar0 cvmx_l2c_spar0_t;
+
+/**
+ * cvmx_l2c_spar1
+ *
+ * L2C_SPAR1 = L2 Set Partitioning Register (PP4-7)
+ *
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+union cvmx_l2c_spar1
+{
+	uint64_t u64;
+	struct cvmx_l2c_spar1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t umsk7                        : 8;  /**< PP[7] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk6                        : 8;  /**< PP[6] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk5                        : 8;  /**< PP[5] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk4                        : 8;  /**< PP[4] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk4                        : 8;
+	uint64_t umsk5                        : 8;
+	uint64_t umsk6                        : 8;
+	uint64_t umsk7                        : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_spar1_s               cn38xx;
+	struct cvmx_l2c_spar1_s               cn38xxp2;
+	struct cvmx_l2c_spar1_s               cn56xx;
+	struct cvmx_l2c_spar1_s               cn56xxp1;
+	struct cvmx_l2c_spar1_s               cn58xx;
+	struct cvmx_l2c_spar1_s               cn58xxp1;
+};
+typedef union cvmx_l2c_spar1 cvmx_l2c_spar1_t;
+
+/**
+ * cvmx_l2c_spar2
+ *
+ * L2C_SPAR2 = L2 Set Partitioning Register (PP8-11)
+ *
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+union cvmx_l2c_spar2
+{
+	uint64_t u64;
+	struct cvmx_l2c_spar2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t umsk11                       : 8;  /**< PP[11] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk10                       : 8;  /**< PP[10] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk9                        : 8;  /**< PP[9] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk8                        : 8;  /**< PP[8] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk8                        : 8;
+	uint64_t umsk9                        : 8;
+	uint64_t umsk10                       : 8;
+	uint64_t umsk11                       : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_spar2_s               cn38xx;
+	struct cvmx_l2c_spar2_s               cn38xxp2;
+	struct cvmx_l2c_spar2_s               cn56xx;
+	struct cvmx_l2c_spar2_s               cn56xxp1;
+	struct cvmx_l2c_spar2_s               cn58xx;
+	struct cvmx_l2c_spar2_s               cn58xxp1;
+};
+typedef union cvmx_l2c_spar2 cvmx_l2c_spar2_t;
+
+/**
+ * cvmx_l2c_spar3
+ *
+ * L2C_SPAR3 = L2 Set Partitioning Register (PP12-15)
+ *
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+union cvmx_l2c_spar3
+{
+	uint64_t u64;
+	struct cvmx_l2c_spar3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t umsk15                       : 8;  /**< PP[15] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk14                       : 8;  /**< PP[14] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk13                       : 8;  /**< PP[13] L2 'DO NOT USE' set partition mask */
+	uint64_t umsk12                       : 8;  /**< PP[12] L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umsk12                       : 8;
+	uint64_t umsk13                       : 8;
+	uint64_t umsk14                       : 8;
+	uint64_t umsk15                       : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_spar3_s               cn38xx;
+	struct cvmx_l2c_spar3_s               cn38xxp2;
+	struct cvmx_l2c_spar3_s               cn58xx;
+	struct cvmx_l2c_spar3_s               cn58xxp1;
+};
+typedef union cvmx_l2c_spar3 cvmx_l2c_spar3_t;
+
+/**
+ * cvmx_l2c_spar4
+ *
+ * L2C_SPAR4 = L2 Set Partitioning Register (IOB)
+ *
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+union cvmx_l2c_spar4
+{
+	uint64_t u64;
+	struct cvmx_l2c_spar4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t umskiob                      : 8;  /**< IOB L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umskiob                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_l2c_spar4_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t umskiob                      : 4;  /**< IOB L2 'DO NOT USE' set partition mask */
+#else
+	uint64_t umskiob                      : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_l2c_spar4_cn30xx          cn31xx;
+	struct cvmx_l2c_spar4_s               cn38xx;
+	struct cvmx_l2c_spar4_s               cn38xxp2;
+	struct cvmx_l2c_spar4_s               cn50xx;
+	struct cvmx_l2c_spar4_s               cn52xx;
+	struct cvmx_l2c_spar4_s               cn52xxp1;
+	struct cvmx_l2c_spar4_s               cn56xx;
+	struct cvmx_l2c_spar4_s               cn56xxp1;
+	struct cvmx_l2c_spar4_s               cn58xx;
+	struct cvmx_l2c_spar4_s               cn58xxp1;
+};
+typedef union cvmx_l2c_spar4 cvmx_l2c_spar4_t;
+
+/**
+ * cvmx_l2c_tad#_ecc0
+ *
+ * L2C_TAD_ECC0 = L2C ECC logging
+ *
+ * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD
+ */
+union cvmx_l2c_tadx_ecc0
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_ecc0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t ow3ecc                       : 10; /**< ECC for OW3 of cache block */
+	uint64_t reserved_42_47               : 6;
+	uint64_t ow2ecc                       : 10; /**< ECC for OW2 of cache block */
+	uint64_t reserved_26_31               : 6;
+	uint64_t ow1ecc                       : 10; /**< ECC for OW1 of cache block */
+	uint64_t reserved_10_15               : 6;
+	uint64_t ow0ecc                       : 10; /**< ECC for OW0 of cache block */
+#else
+	uint64_t ow0ecc                       : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t ow1ecc                       : 10;
+	uint64_t reserved_26_31               : 6;
+	uint64_t ow2ecc                       : 10;
+	uint64_t reserved_42_47               : 6;
+	uint64_t ow3ecc                       : 10;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_ecc0_s           cn63xx;
+	struct cvmx_l2c_tadx_ecc0_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_ecc0 cvmx_l2c_tadx_ecc0_t;
+
+/**
+ * cvmx_l2c_tad#_ecc1
+ *
+ * L2C_TAD_ECC1 = L2C ECC logging
+ *
+ * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD
+ */
+union cvmx_l2c_tadx_ecc1
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_ecc1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t ow7ecc                       : 10; /**< ECC for OW7 of cache block */
+	uint64_t reserved_42_47               : 6;
+	uint64_t ow6ecc                       : 10; /**< ECC for OW6 of cache block */
+	uint64_t reserved_26_31               : 6;
+	uint64_t ow5ecc                       : 10; /**< ECC for OW5 of cache block */
+	uint64_t reserved_10_15               : 6;
+	uint64_t ow4ecc                       : 10; /**< ECC for OW4 of cache block */
+#else
+	uint64_t ow4ecc                       : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t ow5ecc                       : 10;
+	uint64_t reserved_26_31               : 6;
+	uint64_t ow6ecc                       : 10;
+	uint64_t reserved_42_47               : 6;
+	uint64_t ow7ecc                       : 10;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_ecc1_s           cn63xx;
+	struct cvmx_l2c_tadx_ecc1_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_ecc1 cvmx_l2c_tadx_ecc1_t;
+
+/**
+ * cvmx_l2c_tad#_ien
+ *
+ * L2C_TAD_IEN = L2C TAD Interrupt Enable
+ *
+ */
+union cvmx_l2c_tadx_ien
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_ien_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t wrdislmc                     : 1;  /**< Illegal Write to Disabled LMC Error enable
+                                                         Enables L2C_TADX_INT[WRDISLMC] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t rddislmc                     : 1;  /**< Illegal Read  to Disabled LMC Error enable
+                                                         Enables L2C_TADX_INT[RDDISLMC] to
+                                                         assert L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t noway                        : 1;  /**< No way available interrupt enable
+                                                         Enables L2C_ERR_TTGX[NOWAY] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t vbfdbe                       : 1;  /**< VBF Double-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[VSBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t vbfsbe                       : 1;  /**< VBF Single-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[VSBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t tagdbe                       : 1;  /**< TAG Double-Bit Error enable
+                                                         Enables L2C_ERR_TTGX[DBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t tagsbe                       : 1;  /**< TAG Single-Bit Error enable
+                                                         Enables L2C_ERR_TTGX[SBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t l2ddbe                       : 1;  /**< L2D Double-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[DBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t l2dsbe                       : 1;  /**< L2D Single-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[SBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+#else
+	uint64_t l2dsbe                       : 1;
+	uint64_t l2ddbe                       : 1;
+	uint64_t tagsbe                       : 1;
+	uint64_t tagdbe                       : 1;
+	uint64_t vbfsbe                       : 1;
+	uint64_t vbfdbe                       : 1;
+	uint64_t noway                        : 1;
+	uint64_t rddislmc                     : 1;
+	uint64_t wrdislmc                     : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_ien_s            cn63xx;
+	struct cvmx_l2c_tadx_ien_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t noway                        : 1;  /**< No way available interrupt enable
+                                                         Enables L2C_ERR_TTGX[NOWAY] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t vbfdbe                       : 1;  /**< VBF Double-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[VSBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t vbfsbe                       : 1;  /**< VBF Single-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[VSBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t tagdbe                       : 1;  /**< TAG Double-Bit Error enable
+                                                         Enables L2C_ERR_TTGX[DBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t tagsbe                       : 1;  /**< TAG Single-Bit Error enable
+                                                         Enables L2C_ERR_TTGX[SBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t l2ddbe                       : 1;  /**< L2D Double-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[DBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+	uint64_t l2dsbe                       : 1;  /**< L2D Single-Bit Error enable
+                                                         Enables L2C_ERR_TDTX[SBE] to assert
+                                                         L2C_INT_REG[TADX] (and cause an interrupt) */
+#else
+	uint64_t l2dsbe                       : 1;
+	uint64_t l2ddbe                       : 1;
+	uint64_t tagsbe                       : 1;
+	uint64_t tagdbe                       : 1;
+	uint64_t vbfsbe                       : 1;
+	uint64_t vbfdbe                       : 1;
+	uint64_t noway                        : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_ien cvmx_l2c_tadx_ien_t;
+
+/**
+ * cvmx_l2c_tad#_int
+ *
+ * L2C_TAD_INT = L2C TAD Interrupt Register (not present in pass 1 O63)
+ *
+ *
+ * Notes:
+ * L2C_TAD_IEN is the interrupt enable register corresponding to this register.
+ *
+ */
+union cvmx_l2c_tadx_int
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t wrdislmc                     : 1;  /**< Illegal Write to Disabled LMC Error
+                                                         A DRAM write arrived before the LMC(s) were enabled */
+	uint64_t rddislmc                     : 1;  /**< Illegal Read  to Disabled LMC Error
+                                                         A DRAM read  arrived before the LMC(s) were enabled */
+	uint64_t noway                        : 1;  /**< No way available interrupt
+                                                         Shadow copy of L2C_ERR_TTGX[NOWAY]
+                                                         Writes of 1 also clear L2C_ERR_TTGX[NOWAY] */
+	uint64_t vbfdbe                       : 1;  /**< VBF Double-Bit Error
+                                                         Shadow copy of L2C_ERR_TDTX[VDBE]
+                                                         Writes of 1 also clear L2C_ERR_TDTX[VDBE] */
+	uint64_t vbfsbe                       : 1;  /**< VBF Single-Bit Error
+                                                         Shadow copy of L2C_ERR_TDTX[VSBE]
+                                                         Writes of 1 also clear L2C_ERR_TDTX[VSBE] */
+	uint64_t tagdbe                       : 1;  /**< TAG Double-Bit Error
+                                                         Shadow copy of L2C_ERR_TTGX[DBE]
+                                                         Writes of 1 also clear L2C_ERR_TTGX[DBE] */
+	uint64_t tagsbe                       : 1;  /**< TAG Single-Bit Error
+                                                         Shadow copy of L2C_ERR_TTGX[SBE]
+                                                         Writes of 1 also clear L2C_ERR_TTGX[SBE] */
+	uint64_t l2ddbe                       : 1;  /**< L2D Double-Bit Error
+                                                         Shadow copy of L2C_ERR_TDTX[DBE]
+                                                         Writes of 1 also clear L2C_ERR_TDTX[DBE] */
+	uint64_t l2dsbe                       : 1;  /**< L2D Single-Bit Error
+                                                         Shadow copy of L2C_ERR_TDTX[SBE]
+                                                         Writes of 1 also clear L2C_ERR_TDTX[SBE] */
+#else
+	uint64_t l2dsbe                       : 1;
+	uint64_t l2ddbe                       : 1;
+	uint64_t tagsbe                       : 1;
+	uint64_t tagdbe                       : 1;
+	uint64_t vbfsbe                       : 1;
+	uint64_t vbfdbe                       : 1;
+	uint64_t noway                        : 1;
+	uint64_t rddislmc                     : 1;
+	uint64_t wrdislmc                     : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_int_s            cn63xx;
+};
+typedef union cvmx_l2c_tadx_int cvmx_l2c_tadx_int_t;
+
+/**
+ * cvmx_l2c_tad#_pfc0
+ *
+ * L2C_TAD_PFC0 = L2C TAD Performance Counter 0
+ *
+ */
+union cvmx_l2c_tadx_pfc0
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_pfc0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_pfc0_s           cn63xx;
+	struct cvmx_l2c_tadx_pfc0_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_pfc0 cvmx_l2c_tadx_pfc0_t;
+
+/**
+ * cvmx_l2c_tad#_pfc1
+ *
+ * L2C_TAD_PFC1 = L2C TAD Performance Counter 1
+ *
+ */
+union cvmx_l2c_tadx_pfc1
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_pfc1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_pfc1_s           cn63xx;
+	struct cvmx_l2c_tadx_pfc1_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_pfc1 cvmx_l2c_tadx_pfc1_t;
+
+/**
+ * cvmx_l2c_tad#_pfc2
+ *
+ * L2C_TAD_PFC2 = L2C TAD Performance Counter 2
+ *
+ */
+union cvmx_l2c_tadx_pfc2
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_pfc2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_pfc2_s           cn63xx;
+	struct cvmx_l2c_tadx_pfc2_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_pfc2 cvmx_l2c_tadx_pfc2_t;
+
+/**
+ * cvmx_l2c_tad#_pfc3
+ *
+ * L2C_TAD_PFC3 = L2C TAD Performance Counter 3
+ *
+ */
+union cvmx_l2c_tadx_pfc3
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_pfc3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_pfc3_s           cn63xx;
+	struct cvmx_l2c_tadx_pfc3_s           cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_pfc3 cvmx_l2c_tadx_pfc3_t;
+
+/**
+ * cvmx_l2c_tad#_prf
+ *
+ * L2C_TAD_PRF = L2C TAD Performance Counter Control
+ *
+ *
+ * Notes:
+ * (1) All four counters are equivalent and can use any of the defined selects.
+ *
+ * (2) the CNTnSEL legal values are:
+ *         0x00 -- Nothing (disabled)
+ *         0x01 -- L2 Tag Hit
+ *         0x02 -- L2 Tag Miss
+ *         0x03 -- L2 Tag NoAlloc (forced no-allocate)
+ *         0x04 -- L2 Victim
+ *         0x05 -- SC Fail
+ *         0x06 -- SC Pass
+ *         0x07 -- LFB Occupancy (each cycle adds \# of LFBs valid)
+ *         0x08 -- LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs)
+ *         0x09 -- LFB Wait VAB (each cycle adds \# LFBs waiting for VAB)
+ *         0x80 -- Quad 0 index bus inuse
+ *         0x81 -- Quad 0 read data bus inuse
+ *         0x82 -- Quad 0 \# banks inuse (0-4/cycle)
+ *         0x83 -- Quad 0 wdat flops inuse (0-4/cycle)
+ *         0x90 -- Quad 1 index bus inuse
+ *         0x91 -- Quad 1 read data bus inuse
+ *         0x92 -- Quad 1 \# banks inuse (0-4/cycle)
+ *         0x93 -- Quad 1 wdat flops inuse (0-4/cycle)
+ *         0xA0 -- Quad 2 index bus inuse
+ *         0xA1 -- Quad 2 read data bus inuse
+ *         0xA2 -- Quad 2 \# banks inuse (0-4/cycle)
+ *         0xA3 -- Quad 2 wdat flops inuse (0-4/cycle)
+ *         0xB0 -- Quad 3 index bus inuse
+ *         0xB1 -- Quad 3 read data bus inuse
+ *         0xB2 -- Quad 3 \# banks inuse (0-4/cycle)
+ *         0xB3 -- Quad 3 wdat flops inuse (0-4/cycle)
+ */
+union cvmx_l2c_tadx_prf
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_prf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt3sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC3 */
+	uint64_t cnt2sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC2 */
+	uint64_t cnt1sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC1 */
+	uint64_t cnt0sel                      : 8;  /**< Selects event to count for L2C_TAD_PFC0 */
+#else
+	uint64_t cnt0sel                      : 8;
+	uint64_t cnt1sel                      : 8;
+	uint64_t cnt2sel                      : 8;
+	uint64_t cnt3sel                      : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_prf_s            cn63xx;
+	struct cvmx_l2c_tadx_prf_s            cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_prf cvmx_l2c_tadx_prf_t;
+
+/**
+ * cvmx_l2c_tad#_tag
+ *
+ * L2C_TAD_TAG = L2C tag data
+ *
+ * Description: holds the tag information for LTGL2I and STGL2I commands
+ *
+ * Notes:
+ * (1) For 63xx TAG[35] must be written zero for STGL2I's or operation is undefined.  During normal
+ *     operation, TAG[35] will also read 0.
+ *
+ * (2) If setting the LOCK bit, the USE bit should also be set or operation is undefined.
+ *
+ * (3) The tag is the corresponding bits from the L2C+LMC internal L2/DRAM byte address.
+ */
+union cvmx_l2c_tadx_tag
+{
+	uint64_t u64;
+	struct cvmx_l2c_tadx_tag_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t ecc                          : 6;  /**< The tag ECC */
+	uint64_t reserved_36_39               : 4;
+	uint64_t tag                          : 19; /**< The tag (see notes 1 and 3) */
+	uint64_t reserved_4_16                : 13;
+	uint64_t use                          : 1;  /**< The LRU use bit */
+	uint64_t valid                        : 1;  /**< The valid bit */
+	uint64_t dirty                        : 1;  /**< The dirty bit */
+	uint64_t lock                         : 1;  /**< The lock bit */
+#else
+	uint64_t lock                         : 1;
+	uint64_t dirty                        : 1;
+	uint64_t valid                        : 1;
+	uint64_t use                          : 1;
+	uint64_t reserved_4_16                : 13;
+	uint64_t tag                          : 19;
+	uint64_t reserved_36_39               : 4;
+	uint64_t ecc                          : 6;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} s;
+	struct cvmx_l2c_tadx_tag_s            cn63xx;
+	struct cvmx_l2c_tadx_tag_s            cn63xxp1;
+};
+typedef union cvmx_l2c_tadx_tag cvmx_l2c_tadx_tag_t;
+
+/**
+ * cvmx_l2c_ver_id
+ *
+ * L2C_VER_ID = L2C Virtualization ID Error Register
+ *
+ * Description: records virtualization IDs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
+ */
+union cvmx_l2c_ver_id
+{
+	uint64_t u64;
+	struct cvmx_l2c_ver_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Mask of virtualization IDs which had an error */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_l2c_ver_id_s              cn63xx;
+	struct cvmx_l2c_ver_id_s              cn63xxp1;
+};
+typedef union cvmx_l2c_ver_id cvmx_l2c_ver_id_t;
+
+/**
+ * cvmx_l2c_ver_iob
+ *
+ * L2C_VER_IOB = L2C Virtualization ID IOB Error Register
+ *
+ * Description: records IOBs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
+ */
+union cvmx_l2c_ver_iob
+{
+	uint64_t u64;
+	struct cvmx_l2c_ver_iob_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t mask                         : 1;  /**< Mask of IOBs which had a virtualization error */
+#else
+	uint64_t mask                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_l2c_ver_iob_s             cn63xx;
+	struct cvmx_l2c_ver_iob_s             cn63xxp1;
+};
+typedef union cvmx_l2c_ver_iob cvmx_l2c_ver_iob_t;
+
+/**
+ * cvmx_l2c_ver_msc
+ *
+ * L2C_VER_MSC = L2C Virtualization Miscellaneous Error Register (not in 63xx pass 1.x)
+ *
+ * Description: records type of command associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts
+ */
+union cvmx_l2c_ver_msc
+{
+	uint64_t u64;
+	struct cvmx_l2c_ver_msc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t invl2                        : 1;  /**< If set, a INVL2 caused HOLEWR/BIGWR/VRT* to set */
+	uint64_t dwb                          : 1;  /**< If set, a DWB caused HOLEWR/BIGWR/VRT* to set */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t invl2                        : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_l2c_ver_msc_s             cn63xx;
+};
+typedef union cvmx_l2c_ver_msc cvmx_l2c_ver_msc_t;
+
+/**
+ * cvmx_l2c_ver_pp
+ *
+ * L2C_VER_PP = L2C Virtualization ID PP Error Register
+ *
+ * Description: records PPs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts.
+ */
+union cvmx_l2c_ver_pp
+{
+	uint64_t u64;
+	struct cvmx_l2c_ver_pp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mask                         : 6;  /**< Mask of PPs which had a virtualization error */
+#else
+	uint64_t mask                         : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_l2c_ver_pp_s              cn63xx;
+	struct cvmx_l2c_ver_pp_s              cn63xxp1;
+};
+typedef union cvmx_l2c_ver_pp cvmx_l2c_ver_pp_t;
+
+/**
+ * cvmx_l2c_virtid_iob#
+ *
+ * L2C_VIRTID_IOB = L2C IOB virtualization ID
+ *
+ * Description:
+ */
+union cvmx_l2c_virtid_iobx
+{
+	uint64_t u64;
+	struct cvmx_l2c_virtid_iobx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t dwbid                        : 6;  /**< Virtualization ID to use for DWB commands */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t id                           : 6;  /**< Virtualization ID to use for non-DWB commands */
+#else
+	uint64_t id                           : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwbid                        : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_l2c_virtid_iobx_s         cn63xx;
+	struct cvmx_l2c_virtid_iobx_s         cn63xxp1;
+};
+typedef union cvmx_l2c_virtid_iobx cvmx_l2c_virtid_iobx_t;
+
+/**
+ * cvmx_l2c_virtid_pp#
+ *
+ * L2C_VIRTID_PP = L2C PP virtualization ID
+ *
+ * Description:
+ */
+union cvmx_l2c_virtid_ppx
+{
+	uint64_t u64;
+	struct cvmx_l2c_virtid_ppx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t id                           : 6;  /**< Virtualization ID to use for this PP. */
+#else
+	uint64_t id                           : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_l2c_virtid_ppx_s          cn63xx;
+	struct cvmx_l2c_virtid_ppx_s          cn63xxp1;
+};
+typedef union cvmx_l2c_virtid_ppx cvmx_l2c_virtid_ppx_t;
+
+/**
+ * cvmx_l2c_vrt_ctl
+ *
+ * L2C_VRT_CTL = L2C Virtualization control register
+ *
+ */
+union cvmx_l2c_vrt_ctl
+{
+	uint64_t u64;
+	struct cvmx_l2c_vrt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t ooberr                       : 1;  /**< Whether out of bounds writes are an error
+                                                         Determines virtualization hardware behavior for
+                                                         a store to an L2/DRAM address larger than
+                                                         indicated by MEMSZ. If OOBERR is set, all these
+                                                         stores (from any virtualization ID) are blocked. If
+                                                         OOBERR is clear, none of these stores are blocked. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t memsz                        : 3;  /**< Memory space coverage of L2C_VRT_MEM (encoded)
+                                                         0 = 1GB
+                                                         1 = 2GB
+                                                         2 = 4GB
+                                                         3 = 8GB
+                                                         4 = 16GB
+                                                         5 = 32GB
+                                                         6 = 64GB (**reserved in 63xx**)
+                                                         7 = 128GB (**reserved in 63xx**) */
+	uint64_t numid                        : 3;  /**< Number of allowed virtualization IDs (encoded)
+                                                             0 = 2
+                                                             1 = 4
+                                                             2 = 8
+                                                             3 = 16
+                                                             4 = 32
+                                                             5 = 64
+                                                             6,7 illegal
+                                                         Violations of this limit causes
+                                                         L2C to set L2C_INT_REG[VRTIDRNG]. */
+	uint64_t enable                       : 1;  /**< Global virtualization enable
+                                                         When ENABLE is clear, stores are never blocked by
+                                                         the L2C virtualization hardware and none of NUMID,
+                                                         MEMSZ, OOBERR are used. */
+#else
+	uint64_t enable                       : 1;
+	uint64_t numid                        : 3;
+	uint64_t memsz                        : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t ooberr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_l2c_vrt_ctl_s             cn63xx;
+	struct cvmx_l2c_vrt_ctl_s             cn63xxp1;
+};
+typedef union cvmx_l2c_vrt_ctl cvmx_l2c_vrt_ctl_t;
+
+/**
+ * cvmx_l2c_vrt_mem#
+ *
+ * L2C_VRT_MEM = L2C Virtualization Memory
+ *
+ * Description: Virtualization memory mapped region.  There are 1024 32b
+ * byte-parity protected entries.
+ *
+ * Notes:
+ * When a DATA bit is set in L2C_VRT_MEM when L2C virtualization is enabled, L2C
+ * prevents the selected virtual machine from storing to the selected L2/DRAM region.
+ * L2C uses L2C_VRT_MEM to block stores when:
+ *  - L2C_VRT_CTL[ENABLE] is set, and
+ *  - the address of the store exists in L2C+LMC internal L2/DRAM Address space
+ *    and is within the L2C_VRT_CTL[MEMSZ] bounds, and
+ *  - the virtID of the store is within the L2C_VRT_CTL[NUMID] bounds
+ *
+ * L2C_VRT_MEM is never used for these L2C transactions which are always allowed:
+ *   - L2C CMI L2/DRAM transactions that cannot modify L2/DRAM, and
+ *   - any L2/DRAM transaction originated from L2C_XMC_CMD
+ *
+ * L2C_VRT_MEM contains one DATA bit per L2C+LMC internal L2/DRAM region and virtID indicating whether the store
+ * to the region is allowed. The granularity of the checking is the region size, which is:
+ *       2 ^^ (L2C_VRT_CTL[NUMID]+L2C_VRT_CTL[MEMSZ]+16)
+ * which ranges from a minimum of 64KB to a maximum of 256MB, depending on the size
+ * of L2/DRAM that is protected and the number of virtual machines.
+ *
+ * The L2C_VRT_MEM DATA bit that L2C uses is:
+ *
+ *   l2c_vrt_mem_bit_index = address >> (L2C_VRT_CTL[MEMSZ]+L2C_VRT_CTL[NUMID]+16); // address is a byte address
+ *   l2c_vrt_mem_bit_index = l2c_vrt_mem_bit_index | (virtID << (14-L2C_VRT_CTL[NUMID]));
+ *
+ *   L2C_VRT_MEM(l2c_vrt_mem_bit_index >> 5)[DATA<l2c_vrt_mem_bit_index & 0x1F>] is used
+ *
+ * A specific example:
+ *
+ *   L2C_VRT_CTL[NUMID]=2 (i.e. 8 virtual machine ID's used)
+ *   L2C_VRT_CTL[MEMSZ]=4 (i.e. L2C_VRT_MEM covers 16 GB)
+ *
+ *   L2/DRAM region size (granularity) is 4MB
+ *
+ *   l2c_vrt_mem_bit_index<14:12> = virtID<2:0>
+ *   l2c_vrt_mem_bit_index<11:0> = address<33:22>
+ *
+ *   For L2/DRAM physical address 0x51000000 with virtID=5:
+ *      L2C_VRT_MEM648[DATA<4>] determines when the store is allowed (648 is decimal, not hex)
+ */
+union cvmx_l2c_vrt_memx
+{
+	uint64_t u64;
+	struct cvmx_l2c_vrt_memx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t parity                       : 4;  /**< Parity to write into (or read from) the
+                                                         virtualization memory.
+                                                         PARITY<i> is the even parity of DATA<(i*8)+7:i*8> */
+	uint64_t data                         : 32; /**< Data to write into (or read from) the
+                                                         virtualization memory. */
+#else
+	uint64_t data                         : 32;
+	uint64_t parity                       : 4;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_l2c_vrt_memx_s            cn63xx;
+	struct cvmx_l2c_vrt_memx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_vrt_memx cvmx_l2c_vrt_memx_t;
+
+/**
+ * cvmx_l2c_wpar_iob#
+ *
+ * L2C_WPAR_IOB = L2C IOB way partitioning
+ *
+ *
+ * Notes:
+ * (1) The read value of MASK will include bits set because of the L2C cripple fuses.
+ *
+ */
+union cvmx_l2c_wpar_iobx
+{
+	uint64_t u64;
+	struct cvmx_l2c_wpar_iobx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Way partitioning mask. (1 means do not use) */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_l2c_wpar_iobx_s           cn63xx;
+	struct cvmx_l2c_wpar_iobx_s           cn63xxp1;
+};
+typedef union cvmx_l2c_wpar_iobx cvmx_l2c_wpar_iobx_t;
+
+/**
+ * cvmx_l2c_wpar_pp#
+ *
+ * L2C_WPAR_PP = L2C PP way partitioning
+ *
+ *
+ * Notes:
+ * (1) The read value of MASK will include bits set because of the L2C cripple fuses.
+ *
+ */
+union cvmx_l2c_wpar_ppx
+{
+	uint64_t u64;
+	struct cvmx_l2c_wpar_ppx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Way partitioning mask. (1 means do not use) */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_l2c_wpar_ppx_s            cn63xx;
+	struct cvmx_l2c_wpar_ppx_s            cn63xxp1;
+};
+typedef union cvmx_l2c_wpar_ppx cvmx_l2c_wpar_ppx_t;
+
+/**
+ * cvmx_l2c_xmc#_pfc
+ *
+ * L2C_XMC_PFC = L2C XMC Performance Counter(s)
+ *
+ */
+union cvmx_l2c_xmcx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_xmcx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_xmcx_pfc_s            cn63xx;
+	struct cvmx_l2c_xmcx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_xmcx_pfc cvmx_l2c_xmcx_pfc_t;
+
+/**
+ * cvmx_l2c_xmc_cmd
+ *
+ * L2C_XMC_CMD = L2C XMC command register
+ *
+ *
+ * Notes:
+ * (1) the XMC command chosen MUST NOT be a IOB destined command or operation is UNDEFINED.
+ *
+ * (2) the XMC command will have sid forced to IOB, did forced to L2C, no virtualization checks
+ *     performed (always pass), and xmdmsk forced to 0.  Note that this implies that commands which
+ *     REQUIRE an XMD cycle (STP,STC,SAA,FAA,FAS) should not be used or the results are unpredictable.
+ *     The sid=IOB means that the way partitioning used for the command is L2C_WPAR_IOB.
+ *     None of L2C_QOS_IOB, L2C_QOS_PP, L2C_VIRTID_IOB, L2C_VIRTID_PP are used for these commands.
+ *
+ * (3) any responses generated by the XMC command will be forced to PP7 (a non-existant PP) effectively
+ *     causing them to be ignored.  Generated STINs, however, will correctly invalidate the required
+ *     PPs.
+ *
+ * (4) any L2D read generated by the XMC command will record the syndrome information in
+ *     L2C_TAD_ECC0/1.  If ECC is disabled prior to the CSR write this provides the ability to read the
+ *     ECC bits directly.  If ECC is not disabled this should log 0's (assuming no ECC errors were
+ *     found in the block).
+ *
+ * (5) A write which arrives while the INUSE bit is set will block until the INUSE bit clears.  This
+ *     gives software 2 options when needing to issue a stream of writes to L2C_XMC_CMD: polling on the
+ *     INUSE bit, or allowing HW to handle the interlock -- at the expense of locking up the RSL bus
+ *     for potentially tens of cycles at a time while waiting for an available LFB/VAB entry.
+ *
+ * (6) The address written to L2C_XMC_CMD is a 38-bit OCTEON physical address.  L2C performs hole removal and
+ *     index aliasing (if enabled) on the written address and uses that for the command. This hole
+ *     removed/index aliased 38-bit address is what is returned on a read of the L2C_XMC_CMD register.
+ */
+union cvmx_l2c_xmc_cmd
+{
+	uint64_t u64;
+	struct cvmx_l2c_xmc_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t inuse                        : 1;  /**< Set to 1 by HW upon receiving a write, cleared when
+                                                         command has issued (not necessarily completed, but
+                                                         ordered relative to other traffic) and HW can accept
+                                                         another command. */
+	uint64_t cmd                          : 6;  /**< Command to use for simulated XMC request
+                                                         a new request can be accepted */
+	uint64_t reserved_38_56               : 19;
+	uint64_t addr                         : 38; /**< Address to use for simulated XMC request (see Note 6) */
+#else
+	uint64_t addr                         : 38;
+	uint64_t reserved_38_56               : 19;
+	uint64_t cmd                          : 6;
+	uint64_t inuse                        : 1;
+#endif
+	} s;
+	struct cvmx_l2c_xmc_cmd_s             cn63xx;
+	struct cvmx_l2c_xmc_cmd_s             cn63xxp1;
+};
+typedef union cvmx_l2c_xmc_cmd cvmx_l2c_xmc_cmd_t;
+
+/**
+ * cvmx_l2c_xmd#_pfc
+ *
+ * L2C_XMD_PFC = L2C XMD Performance Counter(s)
+ *
+ */
+union cvmx_l2c_xmdx_pfc
+{
+	uint64_t u64;
+	struct cvmx_l2c_xmdx_pfc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t count                        : 64; /**< Current counter value */
+#else
+	uint64_t count                        : 64;
+#endif
+	} s;
+	struct cvmx_l2c_xmdx_pfc_s            cn63xx;
+	struct cvmx_l2c_xmdx_pfc_s            cn63xxp1;
+};
+typedef union cvmx_l2c_xmdx_pfc cvmx_l2c_xmdx_pfc_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c.c b/sys/contrib/octeon-sdk/cvmx-l2c.c
index c1a3320..fab7141 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2c.c
+++ b/sys/contrib/octeon-sdk/cvmx-l2c.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,21 +42,29 @@
 
 
 
+
 /**
  * @file
  *
  * Implementation of the Level 2 Cache (L2C) control,
  * measurement, and debugging facilities.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-l2c.h>
+#include <asm/octeon/cvmx-spinlock.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
 #include "cvmx-config.h"
+#endif
 #include "cvmx.h"
 #include "cvmx-l2c.h"
 #include "cvmx-spinlock.h"
 #include "cvmx-interrupt.h"
-
+#endif
 
 #ifndef CVMX_BUILD_FOR_LINUX_HOST
 /* This spinlock is used internally to ensure that only one core is performing
@@ -67,11 +76,8 @@
 CVMX_SHARED cvmx_spinlock_t cvmx_l2c_spinlock;
 #endif
 
-static inline int l2_size_half(void)
-{
-    uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
-    return !!(val & (1ull << 34));
-}
+CVMX_SHARED cvmx_spinlock_t cvmx_l2c_vrt_spinlock;
+
 int cvmx_l2c_get_core_way_partition(uint32_t core)
 {
     uint32_t    field;
@@ -80,6 +86,9 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
     if (core >= cvmx_octeon_num_cores())
         return -1;
 
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return (cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff);
+
     /* Use the lower two bits of the coreNumber to determine the bit offset
      * of the UMSK[] field in the L2C_SPAR register.
      */
@@ -112,18 +121,19 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
 
     mask &= valid_mask;
 
-    /* A UMSK setting which blocks all L2C Ways is an error. */
-    if (mask == valid_mask)
+    /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+    if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
         return -1;
 
     /* Validate the core number */
     if (core >= cvmx_octeon_num_cores())
         return -1;
 
-    /* Check to make sure current mask & new mask don't block all ways */
-    if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) == valid_mask)
-        return -1;
-
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+       cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+       return 0;
+    }
 
     /* Use the lower two bits of core to determine the bit offset of the
      * UMSK[] field in the L2C_SPAR register.
@@ -168,59 +178,92 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
     valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
     mask &= valid_mask;
 
-    /* A UMSK setting which blocks all L2C Ways is an error. */
-    if (mask == valid_mask)
-        return -1;
-    /* Check to make sure current mask & new mask don't block all ways */
-    if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) == valid_mask)
+    /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+    if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))
         return -1;
 
-    cvmx_write_csr(CVMX_L2C_SPAR4, (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
+    else
+        cvmx_write_csr(CVMX_L2C_SPAR4, (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
     return 0;
 }
 
 int cvmx_l2c_get_hw_way_partition(void)
 {
-    return(cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF));
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        return(cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff);
+    else
+        return(cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF));
 }
 
-
 void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event,
                           uint32_t clear_on_read)
-{   cvmx_l2c_pfctl_t pfctl;
-
-    pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+{
 
-    switch (counter)
+    if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
     {
-        case 0:
-            pfctl.s.cnt0sel = event;
-            pfctl.s.cnt0ena = 1;
-            if (!cvmx_octeon_is_pass1())
+        cvmx_l2c_pfctl_t pfctl;
+
+        pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+
+        switch (counter)
+        {
+            case 0:
+                pfctl.s.cnt0sel = event;
+                pfctl.s.cnt0ena = 1;
                 pfctl.s.cnt0rdclr = clear_on_read;
-            break;
-        case 1:
-            pfctl.s.cnt1sel = event;
-            pfctl.s.cnt1ena = 1;
-            if (!cvmx_octeon_is_pass1())
+                break;
+            case 1:
+                pfctl.s.cnt1sel = event;
+                pfctl.s.cnt1ena = 1;
                 pfctl.s.cnt1rdclr = clear_on_read;
-            break;
-        case 2:
-            pfctl.s.cnt2sel = event;
-            pfctl.s.cnt2ena = 1;
-            if (!cvmx_octeon_is_pass1())
+                break;
+            case 2:
+                pfctl.s.cnt2sel = event;
+                pfctl.s.cnt2ena = 1;
                 pfctl.s.cnt2rdclr = clear_on_read;
-            break;
-        case 3:
-        default:
-            pfctl.s.cnt3sel = event;
-            pfctl.s.cnt3ena = 1;
-            if (!cvmx_octeon_is_pass1())
+                break;
+            case 3:
+            default:
+                pfctl.s.cnt3sel = event;
+                pfctl.s.cnt3ena = 1;
                 pfctl.s.cnt3rdclr = clear_on_read;
-            break;
+                break;
+        }
+
+        cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
     }
+    else
+    {
+        cvmx_l2c_tadx_prf_t l2c_tadx_prf;
+        int tad;
+
+        cvmx_warn("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
+
+        cvmx_warn_if(clear_on_read, "L2C counters don't support clear on read for this chip\n");
+
+        l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
 
-    cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+        switch (counter)
+        {
+            case 0:
+                l2c_tadx_prf.s.cnt0sel = event;
+                break;
+            case 1:
+                l2c_tadx_prf.s.cnt1sel = event;
+                break;
+            case 2:
+                l2c_tadx_prf.s.cnt2sel = event;
+                break;
+            default:
+            case 3:
+                l2c_tadx_prf.s.cnt3sel = event;
+                break;
+        }
+        for (tad=0; tad<CVMX_L2C_TADS; tad++)
+            cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), l2c_tadx_prf.u64);
+    }
 }
 
 uint64_t cvmx_l2c_read_perf(uint32_t counter)
@@ -228,14 +271,50 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
     switch (counter)
     {
         case 0:
-            return(cvmx_read_csr(CVMX_L2C_PFC0));
+            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                return(cvmx_read_csr(CVMX_L2C_PFC0));
+            else
+            {
+                uint64_t counter = 0;
+                int tad;
+                for (tad=0; tad<CVMX_L2C_TADS; tad++)
+                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+                return counter;
+            }
         case 1:
-            return(cvmx_read_csr(CVMX_L2C_PFC1));
+            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                return(cvmx_read_csr(CVMX_L2C_PFC1));
+            else
+            {
+                uint64_t counter = 0;
+                int tad;
+                for (tad=0; tad<CVMX_L2C_TADS; tad++)
+                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+                return counter;
+            }
         case 2:
-            return(cvmx_read_csr(CVMX_L2C_PFC2));
+            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                return(cvmx_read_csr(CVMX_L2C_PFC2));
+            else
+            {
+                uint64_t counter = 0;
+                int tad;
+                for (tad=0; tad<CVMX_L2C_TADS; tad++)
+                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+                return counter;
+            }
         case 3:
         default:
-            return(cvmx_read_csr(CVMX_L2C_PFC3));
+            if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                return(cvmx_read_csr(CVMX_L2C_PFC3));
+            else
+            {
+                uint64_t counter = 0;
+                int tad;
+                for (tad=0; tad<CVMX_L2C_TADS; tad++)
+                    counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+                return counter;
+            }
     }
 }
 
@@ -267,67 +346,107 @@ static void fault_in(uint64_t addr, int len)
 
 int cvmx_l2c_lock_line(uint64_t addr)
 {
-    int retval = 0;
-    cvmx_l2c_dbg_t l2cdbg;
-    cvmx_l2c_lckbase_t lckbase;
-    cvmx_l2c_lckoff_t lckoff;
-    cvmx_l2t_err_t l2t_err;
-    l2cdbg.u64 = 0;
-    lckbase.u64 = 0;
-    lckoff.u64 = 0;
-
-    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-
-    /* Clear l2t error bits if set */
-    l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-    l2t_err.s.lckerr = 1;
-    l2t_err.s.lckerr2 = 1;
-    cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+        uint64_t assoc = cvmx_l2c_get_num_assoc();
+        uint64_t tag = addr >> shift;
+        uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+        uint64_t way;
+        cvmx_l2c_tadx_tag_t l2c_tadx_tag;
 
-    addr &= ~CVMX_CACHE_LINE_MASK;
+        CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
 
-    /* Set this core as debug core */
-    l2cdbg.s.ppnum = cvmx_get_core_num();
-    CVMX_SYNC;
-    cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-    cvmx_read_csr(CVMX_L2C_DBG);
+        /* Make sure we were able to lock the line */
+        for (way = 0; way < assoc; way++)
+        {
+            CVMX_CACHE_LTGL2I(index | (way << shift), 0);
+            CVMX_SYNC;   // make sure CVMX_L2C_TADX_TAG is updated
+            l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+            if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
+                break;
+        }
 
-    lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
-    cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
-    cvmx_read_csr(CVMX_L2C_LCKOFF);
+        /* Check if a valid line is found */
+        if (way >= assoc)
+        {
+            //cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr);
+            return -1;
+        }
 
-    if (((cvmx_l2c_cfg_t)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias)
-    {
-        int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
-        uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
-        lckbase.s.lck_base = addr_tmp >> 7;
+        /* Check if lock bit is not set */
+        if (!l2c_tadx_tag.s.lock)
+        {
+            //cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr);
+            return -1;
+        }
+
+        return way;
     }
     else
     {
-        lckbase.s.lck_base = addr >> 7;
-    }
+        int retval = 0;
+        cvmx_l2c_dbg_t l2cdbg;
+        cvmx_l2c_lckbase_t lckbase;
+        cvmx_l2c_lckoff_t lckoff;
+        cvmx_l2t_err_t l2t_err;
 
-    lckbase.s.lck_ena = 1;
-    cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-    cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
-    fault_in(addr, CVMX_CACHE_LINE_SIZE);
+        l2cdbg.u64 = 0;
+        lckbase.u64 = 0;
+        lckoff.u64 = 0;
 
-    lckbase.s.lck_ena = 0;
-    cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-    cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+        /* Clear l2t error bits if set */
+        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+        l2t_err.s.lckerr = 1;
+        l2t_err.s.lckerr2 = 1;
+        cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
 
-    /* Stop being debug core */
-    cvmx_write_csr(CVMX_L2C_DBG, 0);
-    cvmx_read_csr(CVMX_L2C_DBG);
+        addr &= ~CVMX_CACHE_LINE_MASK;
 
-    l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-    if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
-        retval = 1;  /* We were unable to lock the line */
+        /* Set this core as debug core */
+        l2cdbg.s.ppnum = cvmx_get_core_num();
+        CVMX_SYNC;
+        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+        cvmx_read_csr(CVMX_L2C_DBG);
 
-    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+        lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+        cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+        cvmx_read_csr(CVMX_L2C_LCKOFF);
 
-    return(retval);
+        if (((cvmx_l2c_cfg_t)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias)
+        {
+            int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+            uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+            lckbase.s.lck_base = addr_tmp >> 7;
+        }
+        else
+        {
+            lckbase.s.lck_base = addr >> 7;
+        }
+
+        lckbase.s.lck_ena = 1;
+        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+        cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+
+        fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+        lckbase.s.lck_ena = 0;
+        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+        cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+
+        /* Stop being debug core */
+        cvmx_write_csr(CVMX_L2C_DBG, 0);
+        cvmx_read_csr(CVMX_L2C_DBG);
+
+        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+        if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+            retval = 1;  /* We were unable to lock the line */
+
+        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+        return(retval);
+    }
 }
 
 
@@ -355,77 +474,83 @@ void cvmx_l2c_flush(void)
 {
     uint64_t assoc, set;
     uint64_t n_assoc, n_set;
-    cvmx_l2c_dbg_t l2cdbg;
 
-    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+    n_set = cvmx_l2c_get_num_sets();
+    n_assoc = cvmx_l2c_get_num_assoc();
 
-    l2cdbg.u64 = 0;
-    if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
-        l2cdbg.s.ppnum = cvmx_get_core_num();
-    l2cdbg.s.finv = 1;
-    n_set = CVMX_L2_SETS;
-    n_assoc = l2_size_half() ? (CVMX_L2_ASSOC/2) : CVMX_L2_ASSOC ;
-    for(set=0; set < n_set; set++)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
     {
-        for(assoc = 0; assoc < n_assoc; assoc++)
+        uint64_t address;
+        /* These may look like constants, but they aren't... */
+        int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+        int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
+        for (set=0; set < n_set; set++)
         {
-            l2cdbg.s.set = assoc;
-            /* Enter debug mode, and make sure all other writes complete before we
-            ** enter debug mode */
-            CVMX_SYNCW;
-            cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-            cvmx_read_csr(CVMX_L2C_DBG);
-
-            CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, set*CVMX_CACHE_LINE_SIZE), 0);
-            CVMX_SYNCW; /* Push STF out to L2 */
-            /* Exit debug mode */
-            CVMX_SYNC;
-            cvmx_write_csr(CVMX_L2C_DBG, 0);
-            cvmx_read_csr(CVMX_L2C_DBG);
+            for(assoc=0; assoc < n_assoc; assoc++)
+            {
+                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                       (assoc << assoc_shift) |
+                                       (set << set_shift));
+                CVMX_CACHE_WBIL2I(address, 0);
+            }
         }
     }
-
-    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+    else
+    {
+        for (set=0; set < n_set; set++)
+            for(assoc=0; assoc < n_assoc; assoc++)
+                cvmx_l2c_flush_line(assoc, set);
+    }
 }
 
 
 int cvmx_l2c_unlock_line(uint64_t address)
 {
-    int assoc;
-    cvmx_l2c_tag_t tag;
-    cvmx_l2c_dbg_t l2cdbg;
-    uint32_t tag_addr;
-
-    uint32_t index = cvmx_l2c_address_to_index(address);
 
-    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-    /* Compute portion of address that is stored in tag */
-    tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
-    for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
     {
-        tag = cvmx_get_l2c_tag(assoc, index);
+        int assoc;         cvmx_l2c_tag_t tag;
+        uint32_t tag_addr;
+        uint32_t index = cvmx_l2c_address_to_index(address);
 
-        if (tag.s.V && (tag.s.addr == tag_addr))
+        tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+
+        /* For 63XX, we can flush a line by using the physical address directly,
+        ** so finding the cache line used by the address is only required to provide
+        ** the proper return value for the function.
+        */
+        for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
         {
-            l2cdbg.u64 = 0;
-            l2cdbg.s.ppnum = cvmx_get_core_num();
-            l2cdbg.s.set = assoc;
-            l2cdbg.s.finv = 1;
+            tag = cvmx_l2c_get_tag(assoc, index);
+
+            if (tag.s.V && (tag.s.addr == tag_addr))
+            {
+                CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+                return tag.s.L;
+            }
+        }
+    }
+    else
+    {
+        int assoc;
+        cvmx_l2c_tag_t tag;
+        uint32_t tag_addr;
 
-            CVMX_SYNC;
-            cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); /* Enter debug mode */
-            cvmx_read_csr(CVMX_L2C_DBG);
+        uint32_t index = cvmx_l2c_address_to_index(address);
 
-            CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
-            CVMX_SYNC;
-            /* Exit debug mode */
-            cvmx_write_csr(CVMX_L2C_DBG, 0);
-            cvmx_read_csr(CVMX_L2C_DBG);
-            cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
-            return tag.s.L;
+        /* Compute portion of address that is stored in tag */
+        tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+        for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
+        {
+            tag = cvmx_l2c_get_tag(assoc, index);
+
+            if (tag.s.V && (tag.s.addr == tag_addr))
+            {
+                cvmx_l2c_flush_line(assoc, index);
+                return tag.s.L;
+            }
         }
     }
-    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
     return 0;
 }
 
@@ -519,11 +644,11 @@ typedef union
 static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
 {
 
-    uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+    uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
     uint64_t core = cvmx_get_core_num();
     __cvmx_l2c_tag_t tag_val;
     uint64_t dbg_addr = CVMX_L2C_DBG;
-    uint32_t flags;
+    unsigned long flags;
 
     cvmx_l2c_dbg_t debug_val;
     debug_val.u64 = 0;
@@ -536,7 +661,7 @@ static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
     CVMX_SYNC;  /* Make sure core is quiet (no prefetches, etc.) before entering debug mode */
     CVMX_DCACHE_INVALIDATE;  /* Flush L1 to make sure debug load misses L1 */
 
-    flags = cvmx_interrupt_disable_save();
+    cvmx_local_irq_save(flags);
 
     /* The following must be done in assembly as when in debug mode all data loads from
     ** L2 return special debug data, not normal memory contents.  Also, interrupts must be disabled,
@@ -556,7 +681,7 @@ static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
     "        .set pop             \n"
     :[tag_val] "=r" (tag_val):  [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr) : "memory");
 
-    cvmx_interrupt_restore(flags);
+    cvmx_local_irq_restore(flags);
 
     return(tag_val);
 
@@ -565,67 +690,89 @@ static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
 
 cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
 {
-    __cvmx_l2c_tag_t tmp_tag;
     cvmx_l2c_tag_t tag;
     tag.u64 = 0;
 
     if ((int)association >= cvmx_l2c_get_num_assoc())
     {
-        cvmx_dprintf("ERROR: cvmx_get_l2c_tag association out of range\n");
+        cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
         return(tag);
     }
     if ((int)index >= cvmx_l2c_get_num_sets())
     {
-        cvmx_dprintf("ERROR: cvmx_get_l2c_tag index out of range (arg: %d, max: %d)\n", (int)index, cvmx_l2c_get_num_sets());
+        cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n", (int)index, cvmx_l2c_get_num_sets());
         return(tag);
     }
-    /* __read_l2_tag is intended for internal use only */
-    tmp_tag = __read_l2_tag(association, index);
-
-    /* Convert all tag structure types to generic version, as it can represent all models */
-    if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        tag.s.V    = tmp_tag.cn58xx.V;
-        tag.s.D    = tmp_tag.cn58xx.D;
-        tag.s.L    = tmp_tag.cn58xx.L;
-        tag.s.U    = tmp_tag.cn58xx.U;
-        tag.s.addr = tmp_tag.cn58xx.addr;
-    }
-    else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
-    {
-        tag.s.V    = tmp_tag.cn38xx.V;
-        tag.s.D    = tmp_tag.cn38xx.D;
-        tag.s.L    = tmp_tag.cn38xx.L;
-        tag.s.U    = tmp_tag.cn38xx.U;
-        tag.s.addr = tmp_tag.cn38xx.addr;
-    }
-    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
-    {
-        tag.s.V    = tmp_tag.cn31xx.V;
-        tag.s.D    = tmp_tag.cn31xx.D;
-        tag.s.L    = tmp_tag.cn31xx.L;
-        tag.s.U    = tmp_tag.cn31xx.U;
-        tag.s.addr = tmp_tag.cn31xx.addr;
-    }
-    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
-    {
-        tag.s.V    = tmp_tag.cn30xx.V;
-        tag.s.D    = tmp_tag.cn30xx.D;
-        tag.s.L    = tmp_tag.cn30xx.L;
-        tag.s.U    = tmp_tag.cn30xx.U;
-        tag.s.addr = tmp_tag.cn30xx.addr;
-    }
-    else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
     {
-        tag.s.V    = tmp_tag.cn50xx.V;
-        tag.s.D    = tmp_tag.cn50xx.D;
-        tag.s.L    = tmp_tag.cn50xx.L;
-        tag.s.U    = tmp_tag.cn50xx.U;
-        tag.s.addr = tmp_tag.cn50xx.addr;
+        cvmx_l2c_tadx_tag_t l2c_tadx_tag;
+        uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                        (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                                        (index << CVMX_L2C_IDX_ADDR_SHIFT));
+        /* Use L2 cache Index load tag cache instruction, as hardware loads
+           the virtual tag for the L2 cache block with the contents of
+           L2C_TAD0_TAG register. */
+        CVMX_CACHE_LTGL2I(address, 0);
+        CVMX_SYNC;   // make sure CVMX_L2C_TADX_TAG is updated
+        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+        tag.s.V     = l2c_tadx_tag.s.valid;
+        tag.s.D     = l2c_tadx_tag.s.dirty;
+        tag.s.L     = l2c_tadx_tag.s.lock;
+        tag.s.U     = l2c_tadx_tag.s.use;
+        tag.s.addr  = l2c_tadx_tag.s.tag;
     }
     else
     {
-        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+        __cvmx_l2c_tag_t tmp_tag;
+        /* __read_l2_tag is intended for internal use only */
+        tmp_tag = __read_l2_tag(association, index);
+
+        /* Convert all tag structure types to generic version, as it can represent all models */
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))
+        {
+            tag.s.V    = tmp_tag.cn58xx.V;
+            tag.s.D    = tmp_tag.cn58xx.D;
+            tag.s.L    = tmp_tag.cn58xx.L;
+            tag.s.U    = tmp_tag.cn58xx.U;
+            tag.s.addr = tmp_tag.cn58xx.addr;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+        {
+            tag.s.V    = tmp_tag.cn38xx.V;
+            tag.s.D    = tmp_tag.cn38xx.D;
+            tag.s.L    = tmp_tag.cn38xx.L;
+            tag.s.U    = tmp_tag.cn38xx.U;
+            tag.s.addr = tmp_tag.cn38xx.addr;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        {
+            tag.s.V    = tmp_tag.cn31xx.V;
+            tag.s.D    = tmp_tag.cn31xx.D;
+            tag.s.L    = tmp_tag.cn31xx.L;
+            tag.s.U    = tmp_tag.cn31xx.U;
+            tag.s.addr = tmp_tag.cn31xx.addr;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+        {
+            tag.s.V    = tmp_tag.cn30xx.V;
+            tag.s.D    = tmp_tag.cn30xx.D;
+            tag.s.L    = tmp_tag.cn30xx.L;
+            tag.s.U    = tmp_tag.cn30xx.U;
+            tag.s.addr = tmp_tag.cn30xx.addr;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+        {
+            tag.s.V    = tmp_tag.cn50xx.V;
+            tag.s.D    = tmp_tag.cn50xx.D;
+            tag.s.L    = tmp_tag.cn50xx.L;
+            tag.s.U    = tmp_tag.cn50xx.U;
+            tag.s.addr = tmp_tag.cn50xx.addr;
+        }
+        else
+        {
+            cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+        }
     }
 
     return tag;
@@ -636,12 +783,33 @@ cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
 uint32_t cvmx_l2c_address_to_index (uint64_t addr)
 {
     uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
-    cvmx_l2c_cfg_t l2c_cfg;
-    l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+    int indxalias = 0;
 
-    if (l2c_cfg.s.idxalias)
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
     {
-        idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+        cvmx_l2c_ctl_t l2c_ctl;
+        l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+        indxalias = !l2c_ctl.s.disidxalias;
+    }
+    else
+    {
+        cvmx_l2c_cfg_t l2c_cfg;
+        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        indxalias = l2c_cfg.s.idxalias;
+    }
+
+    if (indxalias)
+    {
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        {
+            uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
+            idx ^= idx / cvmx_l2c_get_num_sets();
+            idx ^= a_14_12;
+        }
+        else
+        {
+            idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+        }
     }
     idx &= CVMX_L2C_IDX_MASK;
     return(idx);
@@ -662,7 +830,7 @@ int cvmx_l2c_get_set_bits(void)
     if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
         OCTEON_IS_MODEL(OCTEON_CN58XX))
         l2_set_bits =  11; /* 2048 sets */
-    else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
         l2_set_bits =  10; /* 1024 sets */
     else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
         l2_set_bits =  9; /* 512 sets */
@@ -695,7 +863,9 @@ int cvmx_l2c_get_num_assoc(void)
         OCTEON_IS_MODEL(OCTEON_CN50XX) ||
         OCTEON_IS_MODEL(OCTEON_CN38XX))
         l2_assoc =  8;
-    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || 
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+        l2_assoc =  16;
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
              OCTEON_IS_MODEL(OCTEON_CN30XX))
         l2_assoc =  4;
     else
@@ -705,10 +875,40 @@ int cvmx_l2c_get_num_assoc(void)
     }
 
     /* Check to see if part of the cache is disabled */
-    if (cvmx_fuse_read(265))
-        l2_assoc = l2_assoc >> 2;
-    else if (cvmx_fuse_read(264))
-        l2_assoc = l2_assoc >> 1;
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        cvmx_mio_fus_dat3_t mio_fus_dat3;
+
+        mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+        /* cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+           <2> will be not used for 63xx
+           <1> disables 1/2 ways
+           <0> disables 1/4 ways
+           They are cumulative, so for 63xx:
+           <1> <0>
+           0 0 16-way 2MB cache
+           0 1 12-way 1.5MB cache
+           1 0 8-way 1MB cache
+           1 1 4-way 512KB cache */
+
+        if (mio_fus_dat3.s.l2c_crip == 3)
+            l2_assoc = 4;
+        else if (mio_fus_dat3.s.l2c_crip == 2)
+            l2_assoc = 8;
+        else if (mio_fus_dat3.s.l2c_crip == 1)
+            l2_assoc = 12;
+    }
+    else
+    {
+        cvmx_l2d_fus3_t val;
+        val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+        /* Using shifts here, as bit position names are different for
+           each model but they all mean the same. */
+        if ((val.u64 >> 35) & 0x1)
+            l2_assoc = l2_assoc >> 2;
+        else if ((val.u64 >> 34) & 0x1)
+            l2_assoc = l2_assoc >> 1;
+    }
 
     return(l2_assoc);
 }
@@ -725,23 +925,492 @@ int cvmx_l2c_get_num_assoc(void)
  */
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 {
-    cvmx_l2c_dbg_t l2cdbg;
+    /* Check the range of the index. */
+    if (index > (uint32_t)cvmx_l2c_get_num_sets())
+    {
+        cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
+        return;
+    }
 
-    l2cdbg.u64 = 0;
-    l2cdbg.s.ppnum = cvmx_get_core_num();
-    l2cdbg.s.finv = 1;
+    /* Check the range of association. */
+    if (assoc > (uint32_t)cvmx_l2c_get_num_assoc())
+    {
+        cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
+        return;
+    }
 
-    l2cdbg.s.set = assoc;
-    /* Enter debug mode, and make sure all other writes complete before we
-    ** enter debug mode */
-    asm volatile ("sync \n"::: "memory");
-    cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-    cvmx_read_csr(CVMX_L2C_DBG);
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        uint64_t address;
+        /* Create the address based on index and association.
+           Bits<20:17> select the way of the cache block involved in
+                       the operation
+           Bits<16:7> of the effect address select the index */
+        address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                               (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                               (index << CVMX_L2C_IDX_ADDR_SHIFT));
+        CVMX_CACHE_WBIL2I(address, 0);
+    }
+    else
+    {
+        cvmx_l2c_dbg_t l2cdbg;
 
-    CVMX_PREPARE_FOR_STORE (((1ULL << 63) + (index)*128), 0);
-    /* Exit debug mode */
-    asm volatile ("sync \n"::: "memory");
-    cvmx_write_csr(CVMX_L2C_DBG, 0);
-    cvmx_read_csr(CVMX_L2C_DBG);
+        l2cdbg.u64 = 0;
+        if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+            l2cdbg.s.ppnum = cvmx_get_core_num();
+        l2cdbg.s.finv = 1;
+
+        l2cdbg.s.set = assoc;
+        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+        /* Enter debug mode, and make sure all other writes complete before we
+        ** enter debug mode */
+        CVMX_SYNC;
+        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+        cvmx_read_csr(CVMX_L2C_DBG);
+
+        CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, index*CVMX_CACHE_LINE_SIZE), 0);
+        /* Exit debug mode */
+        CVMX_SYNC;
+        cvmx_write_csr(CVMX_L2C_DBG, 0);
+        cvmx_read_csr(CVMX_L2C_DBG);
+        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+    }
 }
 #endif
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+
+/* L2C Virtualization APIs. These APIs are based on Octeon II documentation. */
+
+/**
+ * @INTERNAL
+ * Helper function to decode VALUE to number of allowed virtualization IDS.
+ * Returns L2C_VRT_CTL[NUMID].
+ * 
+ * @param nvid     Number of virtual Ids.
+ * @return         On success decode to NUMID, or to -1 on failure.
+ */
+static inline int __cvmx_l2c_vrt_decode_numid(int nvid)
+{
+    int bits = -1;
+    int zero_bits = -1;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
+        {
+            cvmx_dprintf("WARNING: Invalid number of virtual ids(%d) requested, should be <= 64\n", nvid);
+            return bits;
+        }
+
+        while (nvid)
+        {
+           if ((nvid & 1) == 0)
+              zero_bits++;
+
+            bits++;
+            nvid >>= 1;
+        }
+
+        if (bits == 1 || (zero_bits && ((bits - zero_bits) == 1)))
+            return zero_bits;
+    }
+    return -1;
+}
+
+/**
+ * Set maxium number of Virtual IDs allowed in a machine. 
+ *
+ * @param nvid   Number of virtial ids allowed in a machine.
+ * @return       Return 0 on success or -1 on failure.
+ */
+int cvmx_l2c_vrt_set_max_virtids(int nvid)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+    {
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+
+        if (l2c_vrt_ctl.s.enable)
+        {
+            cvmx_dprintf("WARNING: Changing number of Virtual Machine IDs is not allowed after Virtualization is enabled\n");
+            return -1;
+        }
+
+        if (nvid < 1 || nvid > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_max_virtids: Invalid number of Virtual Machine IDs(%d) requested, max allowed %d\n", nvid, CVMX_L2C_VRT_MAX_VIRTID_ALLOWED);
+            return -1;
+        }
+
+        /* Calculate the numid based on nvid */
+        l2c_vrt_ctl.s.numid = __cvmx_l2c_vrt_decode_numid(nvid);
+        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    }
+    return 0;
+}
+
+/**
+ * Get maxium number of virtual IDs allowed in a machine.
+ *
+ * @return  Return number of virtual machine IDs or -1 on failure.
+ */
+int cvmx_l2c_vrt_get_max_virtids(void)
+{
+    int virtids = -1;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+        virtids = 1 << (l2c_vrt_ctl.s.numid + 1);
+        if (virtids > CVMX_L2C_VRT_MAX_VIRTID_ALLOWED)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_get_max_virtids: Invalid number of Virtual IDs initialized (%d)\n", virtids);
+            return -1;
+        }
+    }
+    return virtids;
+}
+
+/**
+ * @INTERNAL
+ * Helper function to decode VALUE to memory space coverage of L2C_VRT_MEM.
+ * Returns L2C_VRT_CTL[MEMSZ].
+ * 
+ * @param memsz    Memory in GB.
+ * @return         On success, decode to MEMSZ, or on failure return -1.
+ */
+static inline int __cvmx_l2c_vrt_decode_memsize(int memsz)
+{
+    int bits = 0;
+    int zero_bits = 0;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        if (memsz == 0 || memsz > CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED)
+        {
+            cvmx_dprintf("WARNING: Invalid virtual memory size(%d) requested, should be <= %d\n", memsz, CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED);
+            return -1;
+        }
+
+        while (memsz)
+        {
+           if ((memsz & 1) == 0)
+              zero_bits++;
+
+            bits++;
+            memsz >>= 1;
+        }
+
+        if (bits == 1 || (bits - zero_bits) == 1)
+            return zero_bits;
+    }
+    return -1;
+}
+
+/**
+ * Set the maxium size of memory space to be allocated for virtualization.
+ *
+ * @param memsz  Size of the virtual memory in GB
+ * @return       Return 0 on success or -1 on failure.
+ */
+int cvmx_l2c_vrt_set_max_memsz(int memsz)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+        int decode = 0;
+
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+
+        if (l2c_vrt_ctl.s.enable)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Changing the size of the memory after Virtualization is enabled is not allowed.\n");
+            return -1;
+        }
+
+        if (memsz >= (int)(cvmx_sysinfo_get()->system_dram_size / 1000000))
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), greater than available on the chip\n", memsz);
+            return -1;
+        }
+        
+        decode = __cvmx_l2c_vrt_decode_memsize(memsz);
+        if (decode == -1)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_set_memsz: Invalid memory size (%d GB), refer to L2C_VRT_CTL[MEMSZ] for more information\n", memsz);
+            return -1;
+        }
+
+        l2c_vrt_ctl.s.memsz = decode;
+        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    }
+    return 0;
+}
+
+/**
+ * Set a Virtual ID to a set of cores.
+ *
+ * @param virtid    Assign virtid to a set of cores.
+ * @param coremask  The group of cores to assign a unique virtual id.
+ * @return          Return 0 on success, otherwise -1.
+ */
+int cvmx_l2c_vrt_assign_virtid(int virtid, uint32_t coremask)
+{
+    uint32_t core = 0;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        int found = 0;
+        int max_virtid = cvmx_l2c_vrt_get_max_virtids();
+        
+        if (virtid > max_virtid)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Max %d number of virtids are allowed, passed %d.\n", max_virtid, virtid);
+            return -1;
+        }
+
+        while (core < cvmx_octeon_num_cores())
+        {
+            if ((coremask >> core) & 1)
+            {
+                cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+                cvmx_l2c_virtid_iobx_t l2c_virtid_iobx;
+                l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+
+                /* Check if the core already has a virtid assigned. */
+                if (l2c_virtid_ppx.s.id)
+                {
+                    cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Changing virtid of core #%d to %d from %d.\n", 
+                        (unsigned int)core, virtid, l2c_virtid_ppx.s.id);
+
+                    /* Flush L2 cache to avoid write errors */
+                    cvmx_l2c_flush();
+                }
+                cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), virtid & 0x3f);
+
+                /* Set the IOB to normal mode. */
+                l2c_virtid_iobx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_IOBX(core));
+                l2c_virtid_iobx.s.id = 1;
+                l2c_virtid_iobx.s.dwbid = 0;
+                cvmx_write_csr(CVMX_L2C_VIRTID_IOBX(core), l2c_virtid_iobx.u64); 
+                found = 1;
+            }
+            core++;
+        } 
+
+        /* Invalid coremask passed. */
+        if (!found)
+        {
+           cvmx_dprintf("WARNING: cvmx_l2c_vrt_assign_virt_id: Invalid coremask(0x%x) passed\n", (unsigned int)coremask);
+           return -1;
+        }
+    }
+    return 0;
+}
+
+/**
+ * Remove a virt id assigned to a set of cores. Update the virtid mask and
+ * virtid stored for each core. 
+ *
+ * @param virtid  Remove the specified Virtualization machine ID.
+ */
+void cvmx_l2c_vrt_remove_virtid(int virtid)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint32_t core;
+        cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+
+        for (core = 0; core < cvmx_octeon_num_cores(); core++)
+        {
+            l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+            if (virtid == l2c_virtid_ppx.s.id)
+                cvmx_write_csr(CVMX_L2C_VIRTID_PPX(core), 0);
+        }
+    }
+}
+
+/**
+ * Helper function to protect the memory region based on the granularity.
+ */
+static uint64_t __cvmx_l2c_vrt_get_granularity(void)
+{
+    uint64_t gran = 0;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        int nvid;
+        uint64_t szd;
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+        nvid = cvmx_l2c_vrt_get_max_virtids();
+        szd = (1ull << l2c_vrt_ctl.s.memsz) * 1024 * 1024 * 1024;
+        gran = (unsigned long long)(szd * nvid)/(32ull * 1024);
+    }
+    return gran;
+}
+
+/**
+ * Block a memory region to be updated for a given virtual id.
+ *
+ * @param start_addr   Starting address of memory region
+ * @param size         Size of the memory to protect
+ * @param virtid       Virtual ID to use
+ * @param mode         Allow/Disallow write access
+ *                        = 0,  Allow write access by virtid
+ *                        = 1,  Disallow write access by virtid
+ */
+int cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        /* Check the alignment of start address, should be aligned to the
+           granularity. */
+        uint64_t gran = __cvmx_l2c_vrt_get_granularity();
+        uint64_t end_addr = start_addr + size;
+        int byte_offset, virtid_offset;
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+        cvmx_l2c_vrt_memx_t l2c_vrt_mem;
+
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+
+        /* No need to protect if virtualization is not enabled */
+        if (!l2c_vrt_ctl.s.enable)
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization is not enabled.\n");
+            return -1;
+        }
+
+        if (virtid > cvmx_l2c_vrt_get_max_virtids())
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id is greater than max allowed\n");
+            return -1;
+        }
+
+        /* No need to protect if virtid is not assigned to a core */
+        {
+            cvmx_l2c_virtid_ppx_t l2c_virtid_ppx;
+            int found = 0;
+            uint32_t core;
+
+            for (core = 0; core < cvmx_octeon_num_cores(); core++)
+            {
+                l2c_virtid_ppx.u64 = cvmx_read_csr(CVMX_L2C_VIRTID_PPX(core));
+                if (l2c_virtid_ppx.s.id == virtid)
+                {
+                    found = 1;
+                    break;
+                }
+            }
+            if (found == 0)
+            {
+                cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Virtualization id (%d) is not assigned to any core.\n", virtid);
+                return -1;
+            }
+        }
+
+        /* Make sure previous stores are through before protecting the memory. */
+        CVMX_SYNCW;
+
+        /* If the L2/DRAM physical address is >= 512 MB, subtract 256 MB
+           to get the address to use. This is because L2C removes the 256MB 
+           "hole" between DR0 and DR1. */
+        if (start_addr >= (512 * 1024 * 1024))
+            start_addr -= 256 * 1024 * 1024;
+
+        if (start_addr != ((start_addr + (gran - 1)) & ~(gran - 1)))
+        {
+            cvmx_dprintf("WARNING: cvmx_l2c_vrt_memprotect: Start address is not aligned\n");
+            return -1;
+        } 
+
+        /* Check the size of the memory to protect, should be aligned to the
+           granularity. */
+        if (end_addr != ((end_addr + (gran - 1)) & ~(gran - 1)))
+        {
+            end_addr = (start_addr + (gran - 1)) & ~(gran - 1);
+            size = start_addr - end_addr;
+        }
+
+        byte_offset = l2c_vrt_ctl.s.memsz + l2c_vrt_ctl.s.numid + 16;
+        virtid_offset = 14 - l2c_vrt_ctl.s.numid;
+        
+        cvmx_spinlock_lock(&cvmx_l2c_vrt_spinlock);
+
+        /* Enable memory protection for each virtid for the specified range. */
+        while (start_addr < end_addr)
+        {
+            /* When L2C virtualization is enabled and a bit is set in 
+               L2C_VRT_MEM(0..1023), then L2C prevents the selected virtual 
+               machine from storing to the selected L2C/DRAM region. */ 
+            int offset, position, i;
+            int l2c_vrt_mem_bit_index = start_addr >> byte_offset;
+            l2c_vrt_mem_bit_index |= (virtid << virtid_offset);
+
+            offset = l2c_vrt_mem_bit_index >> 5;
+            position = l2c_vrt_mem_bit_index & 0x1f;
+
+            l2c_vrt_mem.u64 = cvmx_read_csr(CVMX_L2C_VRT_MEMX(offset));
+            /* Allow/Disallow write access to memory. */
+            if (mode == 0)
+                l2c_vrt_mem.s.data &= ~(1 << position);
+            else
+                l2c_vrt_mem.s.data |= 1 << position;
+            l2c_vrt_mem.s.parity = 0;
+            /* PARITY<i> is the even parity of DATA<i*8+7:i*8>, which means
+               that each bit<i> in PARITY[0..3], is the XOR of all the bits
+               in the corresponding byte in DATA. */
+            for (i = 0; i <= 4; i++)
+            {
+               uint64_t mask = 0xffull << (i*8);
+               if ((cvmx_pop(l2c_vrt_mem.s.data & mask) & 0x1))
+                   l2c_vrt_mem.s.parity |= (1ull << i);
+            }
+            cvmx_write_csr(CVMX_L2C_VRT_MEMX(offset), l2c_vrt_mem.u64);
+            start_addr += gran;
+        }
+
+        cvmx_spinlock_unlock(&cvmx_l2c_vrt_spinlock);
+    }
+    return 0;
+}
+#endif
+
+/**
+ * Enable virtualization.
+ *
+ * @param mode   Whether out of bound writes are an error.
+ */
+void cvmx_l2c_vrt_enable(int mode)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+
+        /* Enable global virtualization */
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+        l2c_vrt_ctl.s.ooberr = mode;
+        l2c_vrt_ctl.s.enable = 1;
+        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    }
+}
+
+/**
+ * Disable virtualization.
+ */
+void cvmx_l2c_vrt_disable(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_l2c_vrt_ctl_t l2c_vrt_ctl;
+
+        /* Disable global virtualization */
+        l2c_vrt_ctl.u64 = cvmx_read_csr(CVMX_L2C_VRT_CTL);
+        l2c_vrt_ctl.s.enable = 0;
+        cvmx_write_csr(CVMX_L2C_VRT_CTL, l2c_vrt_ctl.u64);
+    }
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-l2c.h b/sys/contrib/octeon-sdk/cvmx-l2c.h
index bd049c0c..775f26f 100644
--- a/sys/contrib/octeon-sdk/cvmx-l2c.h
+++ b/sys/contrib/octeon-sdk/cvmx-l2c.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
  * facilities.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 
@@ -65,24 +67,15 @@
 /* Defines for index aliasing computations */
 #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
 #define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE  4096
 
+/* Defines for Virtualizations, valid only from Octeon II onwards. */
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
+#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
 
   /*------------*/
   /*  TYPEDEFS  */
   /*------------*/
-typedef union {        // L2C Tag/Data Store Debug Register
-  uint64_t    u64;
-  struct {
-    uint64_t  reserved: 32,
-	      lfb_enum:  4,
-	      lfb_dmp:   1,
-	      ppnum:     4,
-	      set:       3,
-	      finv:      1,
-	      l2d:       1,
-	      l2t:       1;
-  };
-} cvmx_l2c_dbg;
 
 typedef union
 {
@@ -100,66 +93,101 @@ typedef union
 #endif
 } cvmx_l2c_tag_t;
 
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS  1
 
   /* L2C Performance Counter events. */
 typedef enum
 {
-    CVMX_L2C_EVENT_CYCLES           =  0,
-    CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
-    CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
-    CVMX_L2C_EVENT_DATA_MISS        =  3,
-    CVMX_L2C_EVENT_DATA_HIT         =  4,
-    CVMX_L2C_EVENT_MISS             =  5,
-    CVMX_L2C_EVENT_HIT              =  6,
-    CVMX_L2C_EVENT_VICTIM_HIT       =  7,
-    CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
-    CVMX_L2C_EVENT_TAG_PROBE        =  9,
-    CVMX_L2C_EVENT_TAG_UPDATE       = 10,
-    CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
-    CVMX_L2C_EVENT_TAG_DIRTY        = 12,
-    CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
-    CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
-    CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
-    CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
-    CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
-    CVMX_L2C_EVENT_READ_REQUEST     = 18,
-    CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
-    CVMX_L2C_EVENT_XMC_NOP          = 20,
-    CVMX_L2C_EVENT_XMC_LDT          = 21,
-    CVMX_L2C_EVENT_XMC_LDI          = 22,
-    CVMX_L2C_EVENT_XMC_LDD          = 23,
-    CVMX_L2C_EVENT_XMC_STF          = 24,
-    CVMX_L2C_EVENT_XMC_STT          = 25,
-    CVMX_L2C_EVENT_XMC_STP          = 26,
-    CVMX_L2C_EVENT_XMC_STC          = 27,
-    CVMX_L2C_EVENT_XMC_DWB          = 28,
-    CVMX_L2C_EVENT_XMC_PL2          = 29,
-    CVMX_L2C_EVENT_XMC_PSL1         = 30,
-    CVMX_L2C_EVENT_XMC_IOBLD        = 31,
-    CVMX_L2C_EVENT_XMC_IOBST        = 32,
-    CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
-    CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
-    CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
-    CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
-    CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
-    CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
-    CVMX_L2C_EVENT_RSC_NOP          = 39,
-    CVMX_L2C_EVENT_RSC_STDN         = 40,
-    CVMX_L2C_EVENT_RSC_FILL         = 41,
-    CVMX_L2C_EVENT_RSC_REFL         = 42,
-    CVMX_L2C_EVENT_RSC_STIN         = 43,
-    CVMX_L2C_EVENT_RSC_SCIN         = 44,
-    CVMX_L2C_EVENT_RSC_SCFL         = 45,
-    CVMX_L2C_EVENT_RSC_SCDN         = 46,
-    CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
-    CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
-    CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
-    CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
-    CVMX_L2C_EVENT_LRF_REQ          = 51,
-    CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
-    CVMX_L2C_EVENT_DT_WR_INVAL      = 53
+    CVMX_L2C_EVENT_CYCLES           =  0,    /**< Cycles */
+    CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,    /**< L2 Instruction Miss */
+    CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,    /**< L2 Instruction Hit */
+    CVMX_L2C_EVENT_DATA_MISS        =  3,    /**< L2 Data Miss */
+    CVMX_L2C_EVENT_DATA_HIT         =  4,    /**< L2 Data Hit */
+    CVMX_L2C_EVENT_MISS             =  5,    /**< L2 Miss (I/D) */
+    CVMX_L2C_EVENT_HIT              =  6,    /**< L2 Hit (I/D) */
+    CVMX_L2C_EVENT_VICTIM_HIT       =  7,    /**< L2 Victim Buffer Hit (Retry Probe) */
+    CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,    /**< LFB-NQ Index Conflict */
+    CVMX_L2C_EVENT_TAG_PROBE        =  9,    /**< L2 Tag Probe (issued - could be VB-Retried) */
+    CVMX_L2C_EVENT_TAG_UPDATE       = 10,    /**< L2 Tag Update (completed). Note: Some CMD types do not update */
+    CVMX_L2C_EVENT_TAG_COMPLETE     = 11,    /**< L2 Tag Probe Completed (beyond VB-RTY window) */
+    CVMX_L2C_EVENT_TAG_DIRTY        = 12,    /**< L2 Tag Dirty Victim */
+    CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,    /**< L2 Data Store NOP */
+    CVMX_L2C_EVENT_DATA_STORE_READ  = 14,    /**< L2 Data Store READ */
+    CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,    /**< L2 Data Store WRITE */
+    CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,    /**< Memory Fill Data valid */
+    CVMX_L2C_EVENT_WRITE_REQUEST    = 17,    /**< Memory Write Request */
+    CVMX_L2C_EVENT_READ_REQUEST     = 18,    /**< Memory Read Request */
+    CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,    /**< Memory Write Data valid */
+    CVMX_L2C_EVENT_XMC_NOP          = 20,    /**< XMC NOP */
+    CVMX_L2C_EVENT_XMC_LDT          = 21,    /**< XMC LDT */
+    CVMX_L2C_EVENT_XMC_LDI          = 22,    /**< XMC LDI */
+    CVMX_L2C_EVENT_XMC_LDD          = 23,    /**< XMC LDD */
+    CVMX_L2C_EVENT_XMC_STF          = 24,    /**< XMC STF */
+    CVMX_L2C_EVENT_XMC_STT          = 25,    /**< XMC STT */
+    CVMX_L2C_EVENT_XMC_STP          = 26,    /**< XMC STP */
+    CVMX_L2C_EVENT_XMC_STC          = 27,    /**< XMC STC */
+    CVMX_L2C_EVENT_XMC_DWB          = 28,    /**< XMC DWB */
+    CVMX_L2C_EVENT_XMC_PL2          = 29,    /**< XMC PL2 */
+    CVMX_L2C_EVENT_XMC_PSL1         = 30,    /**< XMC PSL1 */
+    CVMX_L2C_EVENT_XMC_IOBLD        = 31,    /**< XMC IOBLD */
+    CVMX_L2C_EVENT_XMC_IOBST        = 32,    /**< XMC IOBST */
+    CVMX_L2C_EVENT_XMC_IOBDMA       = 33,    /**< XMC IOBDMA */
+    CVMX_L2C_EVENT_XMC_IOBRSP       = 34,    /**< XMC IOBRSP */
+    CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,    /**< XMC Bus valid (all) */
+    CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,    /**< XMC Bus valid (DST=L2C) Memory */
+    CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,    /**< XMC Bus valid (DST=IOB) REFL Data */
+    CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,    /**< XMC Bus valid (DST=PP) IOBRSP Data */
+    CVMX_L2C_EVENT_RSC_NOP          = 39,    /**< RSC NOP */
+    CVMX_L2C_EVENT_RSC_STDN         = 40,    /**< RSC STDN */
+    CVMX_L2C_EVENT_RSC_FILL         = 41,    /**< RSC FILL */
+    CVMX_L2C_EVENT_RSC_REFL         = 42,    /**< RSC REFL */
+    CVMX_L2C_EVENT_RSC_STIN         = 43,    /**< RSC STIN */
+    CVMX_L2C_EVENT_RSC_SCIN         = 44,    /**< RSC SCIN */
+    CVMX_L2C_EVENT_RSC_SCFL         = 45,    /**< RSC SCFL */
+    CVMX_L2C_EVENT_RSC_SCDN         = 46,    /**< RSC SCDN */
+    CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,    /**< RSC Data Valid */
+    CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,    /**< RSC Data Valid (FILL) */
+    CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,    /**< RSC Data Valid (STRSP) */
+    CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,    /**< RSC Data Valid (REFL) */
+    CVMX_L2C_EVENT_LRF_REQ          = 51,    /**< LRF-REQ (LFB-NQ) */
+    CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,    /**< DT RD-ALLOC */
+    CVMX_L2C_EVENT_DT_WR_INVAL      = 53,    /**< DT WR-INVAL */
+    CVMX_L2C_EVENT_MAX
 } cvmx_l2c_event_t;
 
+/* L2C Performance Counter events for Octeon2. */
+typedef enum
+{
+     CVMX_L2C_TAD_EVENT_NONE          = 0,     /* None */
+     CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,     /* L2 Tag Hit */
+     CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,     /* L2 Tag Miss */
+     CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,     /* L2 Tag NoAlloc (forced no-allocate) */
+     CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,     /* L2 Tag Victim */
+     CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,     /* SC Fail */
+     CVMX_L2C_TAD_EVENT_SC_PASS       = 6,     /* SC Pass */
+     CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,     /* LFB Occupancy (each cycle adds \# of LFBs valid) */
+     CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,     /* LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) */
+     CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,     /* LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) */
+     CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,   /* Quad 0 index bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,   /* Quad 0 read data bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,   /* Quad 0 \# banks inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,   /* Quad 0 wdat flops inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,   /* Quad 1 index bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,   /* Quad 1 read data bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,   /* Quad 1 \# banks inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,   /* Quad 1 wdat flops inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,   /* Quad 2 index bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,   /* Quad 2 read data bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,   /* Quad 2 \# banks inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,   /* Quad 2 wdat flops inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,   /* Quad 3 index bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,   /* Quad 3 read data bus inuse */
+     CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,   /* Quad 3 \# banks inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,   /* Quad 3 wdat flops inuse (0-4/cycle) */
+     CVMX_L2C_TAD_EVENT_MAX
+} cvmx_l2c_tad_event_t;
+
 /**
  * Configure one of the four L2 Cache performance counters to capture event
  * occurences.
@@ -171,9 +199,8 @@ typedef enum
  *
  * @note The routine does not clear the counter.
  */
-void cvmx_l2c_config_perf(uint32_t         counter,
-                               cvmx_l2c_event_t event,
-                               uint32_t         clear_on_read);
+void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event, uint32_t clear_on_read);
+
 /**
  * Read the given L2 Cache performance counter. The counter must be configured
  * before reading, but this routine does not enforce this requirement.
@@ -299,7 +326,8 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
  */
 cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index);
 
-/* Wrapper around deprecated old function name */
+/* Wrapper providing a deprecated old function name */
+static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
 static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index)
 {
     return cvmx_l2c_get_tag(association, index);
@@ -361,4 +389,66 @@ int cvmx_l2c_get_num_assoc(void);
  */
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
 
+/*
+ * Set maxium number of Virtual IDS allowed in a machine.
+ *
+ * @param nvid  Number of virtial ids allowed in a machine.
+ * @return      Return 0 on success or -1 on failure.
+ */
+int cvmx_l2c_vrt_set_max_virtids(int nvid);
+
+/**
+ * Get maxium number of virtual IDs allowed in a machine.
+ *
+ * @return  Return number of virtual machine IDs. Return -1 on failure.
+ */
+int cvmx_l2c_vrt_get_max_virtids(void);
+
+/**
+ * Set the maxium size of memory space to be allocated for virtualization.
+ *
+ * @param memsz     Size of the virtual memory in GB
+ * @return          Return 0 on success or -1 on failure.
+ */
+int cvmx_l2c_vrt_set_max_memsz(int memsz);
+
+/**
+ * Set a Virtual ID to a set of cores.
+ *
+ * @param virtid    Assign virtid to a set of cores.
+ * @param coremask  The group of cores to assign a unique virtual id.
+ * @return          Return 0 on success, otherwise -1.
+ */
+int cvmx_l2c_vrt_assign_virtid(int virtid, uint32_t coremask);
+
+/**
+ * Remove a virt id assigned to a set of cores. Update the virtid mask and
+ * virtid stored for each core.
+ *
+ * @param coremask  the group of cores whose virtual id is removed.
+ */
+void cvmx_l2c_vrt_remove_virtid(int virtid);
+
+/**
+ * Block a memory region to be updated by a set of virtids.
+ *
+ * @param start_addr   Starting address of memory region
+ * @param size         Size of the memory to protect
+ * @param virtid_mask  Virtual ID to use
+ * @param mode         Allow/Disallow write access
+ *                        = 0,  Allow write access by virtid
+ *                        = 1,  Disallow write access by virtid
+ */
+int cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode);
+
+/**
+ * Enable virtualization.
+ */
+void cvmx_l2c_vrt_enable(int mode);
+
+/**
+ * Disable virtualization.
+ */
+void cvmx_l2c_vrt_disable(void);
+
 #endif /* __CVMX_L2C_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-l2d-defs.h b/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
new file mode 100644
index 0000000..402edd0
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
@@ -0,0 +1,1172 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-l2d-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon l2d.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_L2D_TYPEDEFS_H__
+#define __CVMX_L2D_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
+static inline uint64_t CVMX_L2D_BST0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000780ull);
+}
+#else
+#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
+static inline uint64_t CVMX_L2D_BST1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000788ull);
+}
+#else
+#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
+static inline uint64_t CVMX_L2D_BST2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000790ull);
+}
+#else
+#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
+static inline uint64_t CVMX_L2D_BST3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000798ull);
+}
+#else
+#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
+static inline uint64_t CVMX_L2D_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000010ull);
+}
+#else
+#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
+static inline uint64_t CVMX_L2D_FADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000018ull);
+}
+#else
+#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
+static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000020ull);
+}
+#else
+#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
+static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000028ull);
+}
+#else
+#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
+static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
+}
+#else
+#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
+static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
+}
+#else
+#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
+static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
+}
+#else
+#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
+static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
+}
+#else
+#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
+#endif
+
+/**
+ * cvmx_l2d_bst0
+ *
+ * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
+ *
+ */
+union cvmx_l2d_bst0
+{
+	uint64_t u64;
+	struct cvmx_l2d_bst0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t ftl                          : 1;  /**< L2C Data Store Fatal Defect(across all QUADs)
+                                                         2 or more columns were detected bad across all
+                                                         QUADs[0-3]. Please refer to individual quad failures
+                                                         for bad column = 0x7e to determine which QUAD was in
+                                                         error. */
+	uint64_t q0stat                       : 34; /**< Bist Results for QUAD0
+                                                         Failure \#1 Status
+                                                           [16:14] bad bank
+                                                           [13:7] bad high column
+                                                           [6:0] bad low column
+                                                         Failure \#2 Status
+                                                           [33:31] bad bank
+                                                           [30:24] bad high column
+                                                           [23:17] bad low column
+                                                         NOTES: For bad high/low column reporting:
+                                                            0x7f:   No failure
+                                                            0x7e:   Fatal Defect: 2 or more bad columns
+                                                            0-0x45: Bad column
+                                                         NOTE: If there are less than 2 failures then the
+                                                            bad bank will be 0x7. */
+#else
+	uint64_t q0stat                       : 34;
+	uint64_t ftl                          : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} s;
+	struct cvmx_l2d_bst0_s                cn30xx;
+	struct cvmx_l2d_bst0_s                cn31xx;
+	struct cvmx_l2d_bst0_s                cn38xx;
+	struct cvmx_l2d_bst0_s                cn38xxp2;
+	struct cvmx_l2d_bst0_s                cn50xx;
+	struct cvmx_l2d_bst0_s                cn52xx;
+	struct cvmx_l2d_bst0_s                cn52xxp1;
+	struct cvmx_l2d_bst0_s                cn56xx;
+	struct cvmx_l2d_bst0_s                cn56xxp1;
+	struct cvmx_l2d_bst0_s                cn58xx;
+	struct cvmx_l2d_bst0_s                cn58xxp1;
+};
+typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;
+
+/**
+ * cvmx_l2d_bst1
+ *
+ * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
+ *
+ */
+union cvmx_l2d_bst1
+{
+	uint64_t u64;
+	struct cvmx_l2d_bst1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q1stat                       : 34; /**< Bist Results for QUAD1
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+	uint64_t q1stat                       : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_bst1_s                cn30xx;
+	struct cvmx_l2d_bst1_s                cn31xx;
+	struct cvmx_l2d_bst1_s                cn38xx;
+	struct cvmx_l2d_bst1_s                cn38xxp2;
+	struct cvmx_l2d_bst1_s                cn50xx;
+	struct cvmx_l2d_bst1_s                cn52xx;
+	struct cvmx_l2d_bst1_s                cn52xxp1;
+	struct cvmx_l2d_bst1_s                cn56xx;
+	struct cvmx_l2d_bst1_s                cn56xxp1;
+	struct cvmx_l2d_bst1_s                cn58xx;
+	struct cvmx_l2d_bst1_s                cn58xxp1;
+};
+typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;
+
+/**
+ * cvmx_l2d_bst2
+ *
+ * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
+ *
+ */
+union cvmx_l2d_bst2
+{
+	uint64_t u64;
+	struct cvmx_l2d_bst2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q2stat                       : 34; /**< Bist Results for QUAD2
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+	uint64_t q2stat                       : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_bst2_s                cn30xx;
+	struct cvmx_l2d_bst2_s                cn31xx;
+	struct cvmx_l2d_bst2_s                cn38xx;
+	struct cvmx_l2d_bst2_s                cn38xxp2;
+	struct cvmx_l2d_bst2_s                cn50xx;
+	struct cvmx_l2d_bst2_s                cn52xx;
+	struct cvmx_l2d_bst2_s                cn52xxp1;
+	struct cvmx_l2d_bst2_s                cn56xx;
+	struct cvmx_l2d_bst2_s                cn56xxp1;
+	struct cvmx_l2d_bst2_s                cn58xx;
+	struct cvmx_l2d_bst2_s                cn58xxp1;
+};
+typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;
+
+/**
+ * cvmx_l2d_bst3
+ *
+ * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
+ *
+ */
+union cvmx_l2d_bst3
+{
+	uint64_t u64;
+	struct cvmx_l2d_bst3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q3stat                       : 34; /**< Bist Results for QUAD3
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+	uint64_t q3stat                       : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_bst3_s                cn30xx;
+	struct cvmx_l2d_bst3_s                cn31xx;
+	struct cvmx_l2d_bst3_s                cn38xx;
+	struct cvmx_l2d_bst3_s                cn38xxp2;
+	struct cvmx_l2d_bst3_s                cn50xx;
+	struct cvmx_l2d_bst3_s                cn52xx;
+	struct cvmx_l2d_bst3_s                cn52xxp1;
+	struct cvmx_l2d_bst3_s                cn56xx;
+	struct cvmx_l2d_bst3_s                cn56xxp1;
+	struct cvmx_l2d_bst3_s                cn58xx;
+	struct cvmx_l2d_bst3_s                cn58xxp1;
+};
+typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;
+
+/**
+ * cvmx_l2d_err
+ *
+ * L2D_ERR = L2 Data Errors
+ *
+ * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
+ */
+union cvmx_l2d_err
+{
+	uint64_t u64;
+	struct cvmx_l2d_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t bmhclsel                     : 1;  /**< L2 Bit Map Half CacheLine ECC Selector
+
+                                                          When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
+                                                          which half cacheline to conditionally latch into
+                                                          the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
+                                                          is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
+                                                         - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
+                                                             be conditionally latched into the L2D_FSYN0/1 CSRs.
+                                                         - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
+                                                             be conditionally latched into
+                                                             the L2D_FSYN0/1 CSRs. */
+	uint64_t ded_err                      : 1;  /**< L2D Double Error detected (DED) */
+	uint64_t sec_err                      : 1;  /**< L2D Single Error corrected (SEC) */
+	uint64_t ded_intena                   : 1;  /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on double bit
+                                                         (uncorrectable) errors from the L2 Data Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on single bit
+                                                         (correctable) errors from the L2 Data Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Data ECC Enable
+                                                         When set, enables 10-bit SEC/DED codeword for 128bit L2
+                                                         Data Arrays. */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t bmhclsel                     : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_l2d_err_s                 cn30xx;
+	struct cvmx_l2d_err_s                 cn31xx;
+	struct cvmx_l2d_err_s                 cn38xx;
+	struct cvmx_l2d_err_s                 cn38xxp2;
+	struct cvmx_l2d_err_s                 cn50xx;
+	struct cvmx_l2d_err_s                 cn52xx;
+	struct cvmx_l2d_err_s                 cn52xxp1;
+	struct cvmx_l2d_err_s                 cn56xx;
+	struct cvmx_l2d_err_s                 cn56xxp1;
+	struct cvmx_l2d_err_s                 cn58xx;
+	struct cvmx_l2d_err_s                 cn58xxp1;
+};
+typedef union cvmx_l2d_err cvmx_l2d_err_t;
+
+/**
+ * cvmx_l2d_fadr
+ *
+ * L2D_FADR = L2 Failing Address
+ *
+ * Description: L2 Data ECC SEC/DED Failing Address
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+union cvmx_l2d_fadr
+{
+	uint64_t u64;
+	struct cvmx_l2d_fadr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t fadru                        : 1;  /**< Failing L2 Data Store Upper Index bit(MSB) */
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t fset                         : 3;  /**< Failing SET# */
+	uint64_t fadr                         : 11; /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            [FADRU, FADR[10:1]]: cacheline index[17:7]
+                                                            FADR[0]: 1/2 cacheline index
+                                                         NOTE: FADR[1] is used to select between upper/lower 1MB
+                                                         physical L2 Data Store banks. */
+#else
+	uint64_t fadr                         : 11;
+	uint64_t fset                         : 3;
+	uint64_t fowmsk                       : 4;
+	uint64_t fadru                        : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_l2d_fadr_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t reserved_13_13               : 1;
+	uint64_t fset                         : 2;  /**< Failing SET# */
+	uint64_t reserved_9_10                : 2;
+	uint64_t fadr                         : 9;  /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
+#else
+	uint64_t fadr                         : 9;
+	uint64_t reserved_9_10                : 2;
+	uint64_t fset                         : 2;
+	uint64_t reserved_13_13               : 1;
+	uint64_t fowmsk                       : 4;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn30xx;
+	struct cvmx_l2d_fadr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t reserved_13_13               : 1;
+	uint64_t fset                         : 2;  /**< Failing SET# */
+	uint64_t reserved_10_10               : 1;
+	uint64_t fadr                         : 10; /**< Failing L2 Data Store Index
+                                                         (1 of 1024 = half cacheline indices) */
+#else
+	uint64_t fadr                         : 10;
+	uint64_t reserved_10_10               : 1;
+	uint64_t fset                         : 2;
+	uint64_t reserved_13_13               : 1;
+	uint64_t fowmsk                       : 4;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn31xx;
+	struct cvmx_l2d_fadr_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t fset                         : 3;  /**< Failing SET# */
+	uint64_t fadr                         : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
+#else
+	uint64_t fadr                         : 11;
+	uint64_t fset                         : 3;
+	uint64_t fowmsk                       : 4;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn38xx;
+	struct cvmx_l2d_fadr_cn38xx           cn38xxp2;
+	struct cvmx_l2d_fadr_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t fset                         : 3;  /**< Failing SET# */
+	uint64_t reserved_8_10                : 3;
+	uint64_t fadr                         : 8;  /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            FADR[7:1]: cacheline index[13:7]
+                                                            FADR[0]: 1/2 cacheline index */
+#else
+	uint64_t fadr                         : 8;
+	uint64_t reserved_8_10                : 3;
+	uint64_t fset                         : 3;
+	uint64_t fowmsk                       : 4;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn50xx;
+	struct cvmx_l2d_fadr_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+	uint64_t fset                         : 3;  /**< Failing SET# */
+	uint64_t reserved_10_10               : 1;
+	uint64_t fadr                         : 10; /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            FADR[9:1]: cacheline index[15:7]
+                                                            FADR[0]: 1/2 cacheline index */
+#else
+	uint64_t fadr                         : 10;
+	uint64_t reserved_10_10               : 1;
+	uint64_t fset                         : 3;
+	uint64_t fowmsk                       : 4;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn52xx;
+	struct cvmx_l2d_fadr_cn52xx           cn52xxp1;
+	struct cvmx_l2d_fadr_s                cn56xx;
+	struct cvmx_l2d_fadr_s                cn56xxp1;
+	struct cvmx_l2d_fadr_s                cn58xx;
+	struct cvmx_l2d_fadr_s                cn58xxp1;
+};
+typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;
+
+/**
+ * cvmx_l2d_fsyn0
+ *
+ * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
+ *
+ * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+union cvmx_l2d_fsyn0
+{
+	uint64_t u64;
+	struct cvmx_l2d_fsyn0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t fsyn_ow1                     : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
+                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
+                                                         or L2D_ERR[DED_ERR] are set, this field represents
+                                                         the failing OWECC syndrome for the half cacheline
+                                                         indexed by L2D_FADR[FADR].
+                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
+                                                         OW lane(1of4) detected the error.
+                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
+                                                         command from the diagnostic PP will conditionally latch
+                                                         the raw OWECC for the selected half cacheline.
+                                                         (see: L2D_ERR[BMHCLSEL] */
+	uint64_t fsyn_ow0                     : 10; /**< Failing L2 Data Store SYNDROME OW[0,4]
+                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
+                                                         or L2D_ERR[DED_ERR] are set, this field represents
+                                                         the failing OWECC syndrome for the half cacheline
+                                                         indexed by L2D_FADR[FADR].
+                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
+                                                         OW lane(1of4) detected the error.
+                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
+                                                         (L1 load-miss) from the diagnostic PP will conditionally
+                                                         latch the raw OWECC for the selected half cacheline.
+                                                         (see: L2D_ERR[BMHCLSEL] */
+#else
+	uint64_t fsyn_ow0                     : 10;
+	uint64_t fsyn_ow1                     : 10;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_l2d_fsyn0_s               cn30xx;
+	struct cvmx_l2d_fsyn0_s               cn31xx;
+	struct cvmx_l2d_fsyn0_s               cn38xx;
+	struct cvmx_l2d_fsyn0_s               cn38xxp2;
+	struct cvmx_l2d_fsyn0_s               cn50xx;
+	struct cvmx_l2d_fsyn0_s               cn52xx;
+	struct cvmx_l2d_fsyn0_s               cn52xxp1;
+	struct cvmx_l2d_fsyn0_s               cn56xx;
+	struct cvmx_l2d_fsyn0_s               cn56xxp1;
+	struct cvmx_l2d_fsyn0_s               cn58xx;
+	struct cvmx_l2d_fsyn0_s               cn58xxp1;
+};
+typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;
+
+/**
+ * cvmx_l2d_fsyn1
+ *
+ * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
+ *
+ * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+union cvmx_l2d_fsyn1
+{
+	uint64_t u64;
+	struct cvmx_l2d_fsyn1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t fsyn_ow3                     : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
+	uint64_t fsyn_ow2                     : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
+#else
+	uint64_t fsyn_ow2                     : 10;
+	uint64_t fsyn_ow3                     : 10;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_l2d_fsyn1_s               cn30xx;
+	struct cvmx_l2d_fsyn1_s               cn31xx;
+	struct cvmx_l2d_fsyn1_s               cn38xx;
+	struct cvmx_l2d_fsyn1_s               cn38xxp2;
+	struct cvmx_l2d_fsyn1_s               cn50xx;
+	struct cvmx_l2d_fsyn1_s               cn52xx;
+	struct cvmx_l2d_fsyn1_s               cn52xxp1;
+	struct cvmx_l2d_fsyn1_s               cn56xx;
+	struct cvmx_l2d_fsyn1_s               cn56xxp1;
+	struct cvmx_l2d_fsyn1_s               cn58xx;
+	struct cvmx_l2d_fsyn1_s               cn58xxp1;
+};
+typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;
+
+/**
+ * cvmx_l2d_fus0
+ *
+ * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
+ *
+ */
+union cvmx_l2d_fus0
+{
+	uint64_t u64;
+	struct cvmx_l2d_fus0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q0fus                        : 34; /**< Fuse Register for QUAD0
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q0fus                        : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_fus0_s                cn30xx;
+	struct cvmx_l2d_fus0_s                cn31xx;
+	struct cvmx_l2d_fus0_s                cn38xx;
+	struct cvmx_l2d_fus0_s                cn38xxp2;
+	struct cvmx_l2d_fus0_s                cn50xx;
+	struct cvmx_l2d_fus0_s                cn52xx;
+	struct cvmx_l2d_fus0_s                cn52xxp1;
+	struct cvmx_l2d_fus0_s                cn56xx;
+	struct cvmx_l2d_fus0_s                cn56xxp1;
+	struct cvmx_l2d_fus0_s                cn58xx;
+	struct cvmx_l2d_fus0_s                cn58xxp1;
+};
+typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;
+
+/**
+ * cvmx_l2d_fus1
+ *
+ * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
+ *
+ */
+union cvmx_l2d_fus1
+{
+	uint64_t u64;
+	struct cvmx_l2d_fus1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q1fus                        : 34; /**< Fuse Register for QUAD1
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q1fus                        : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_fus1_s                cn30xx;
+	struct cvmx_l2d_fus1_s                cn31xx;
+	struct cvmx_l2d_fus1_s                cn38xx;
+	struct cvmx_l2d_fus1_s                cn38xxp2;
+	struct cvmx_l2d_fus1_s                cn50xx;
+	struct cvmx_l2d_fus1_s                cn52xx;
+	struct cvmx_l2d_fus1_s                cn52xxp1;
+	struct cvmx_l2d_fus1_s                cn56xx;
+	struct cvmx_l2d_fus1_s                cn56xxp1;
+	struct cvmx_l2d_fus1_s                cn58xx;
+	struct cvmx_l2d_fus1_s                cn58xxp1;
+};
+typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;
+
+/**
+ * cvmx_l2d_fus2
+ *
+ * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
+ *
+ */
+union cvmx_l2d_fus2
+{
+	uint64_t u64;
+	struct cvmx_l2d_fus2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t q2fus                        : 34; /**< Fuse Register for QUAD2
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q2fus                        : 34;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_l2d_fus2_s                cn30xx;
+	struct cvmx_l2d_fus2_s                cn31xx;
+	struct cvmx_l2d_fus2_s                cn38xx;
+	struct cvmx_l2d_fus2_s                cn38xxp2;
+	struct cvmx_l2d_fus2_s                cn50xx;
+	struct cvmx_l2d_fus2_s                cn52xx;
+	struct cvmx_l2d_fus2_s                cn52xxp1;
+	struct cvmx_l2d_fus2_s                cn56xx;
+	struct cvmx_l2d_fus2_s                cn56xxp1;
+	struct cvmx_l2d_fus2_s                cn58xx;
+	struct cvmx_l2d_fus2_s                cn58xxp1;
+};
+typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;
+
+/**
+ * cvmx_l2d_fus3
+ *
+ * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
+ *
+ */
+union cvmx_l2d_fus3
+{
+	uint64_t u64;
+	struct cvmx_l2d_fus3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[1:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+	uint64_t reserved_34_36               : 3;
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t reserved_34_36               : 3;
+	uint64_t ema_ctl                      : 3;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_l2d_fus3_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t crip_64k                     : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:15] UNUSED
+                                                             [14]    bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:32] UNUSED
+                                                             [31]    bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_64k                     : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn30xx;
+	struct cvmx_l2d_fus3_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t crip_128k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:15] UNUSED
+                                                             [14]    bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:32] UNUSED
+                                                             [31]    bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_128k                    : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn31xx;
+	struct cvmx_l2d_fus3_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t crip_256k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_512k                    : 1;
+	uint64_t crip_256k                    : 1;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn38xx;
+	struct cvmx_l2d_fus3_cn38xx           cn38xxp2;
+	struct cvmx_l2d_fus3_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+	uint64_t reserved_36_36               : 1;
+	uint64_t crip_32k                     : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t crip_64k                     : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_64k                     : 1;
+	uint64_t crip_32k                     : 1;
+	uint64_t reserved_36_36               : 1;
+	uint64_t ema_ctl                      : 3;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn50xx;
+	struct cvmx_l2d_fus3_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+	uint64_t reserved_36_36               : 1;
+	uint64_t crip_128k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t crip_256k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_256k                    : 1;
+	uint64_t crip_128k                    : 1;
+	uint64_t reserved_36_36               : 1;
+	uint64_t ema_ctl                      : 3;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn52xx;
+	struct cvmx_l2d_fus3_cn52xx           cn52xxp1;
+	struct cvmx_l2d_fus3_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+	uint64_t reserved_36_36               : 1;
+	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t crip_1024k                   : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_1024k                   : 1;
+	uint64_t crip_512k                    : 1;
+	uint64_t reserved_36_36               : 1;
+	uint64_t ema_ctl                      : 3;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn56xx;
+	struct cvmx_l2d_fus3_cn56xx           cn56xxp1;
+	struct cvmx_l2d_fus3_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t ema_ctl                      : 2;  /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[1:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+	uint64_t reserved_36_36               : 1;
+	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t crip_1024k                   : 1;  /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+	uint64_t q3fus                        : 34;
+	uint64_t crip_1024k                   : 1;
+	uint64_t crip_512k                    : 1;
+	uint64_t reserved_36_36               : 1;
+	uint64_t ema_ctl                      : 2;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} cn58xx;
+	struct cvmx_l2d_fus3_cn58xx           cn58xxp1;
+};
+typedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-l2t-defs.h b/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
new file mode 100644
index 0000000..d56b811
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
@@ -0,0 +1,656 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-l2t-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon l2t.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_L2T_TYPEDEFS_H__
+#define __CVMX_L2T_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
+static inline uint64_t CVMX_L2T_ERR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
+		cvmx_warn("CVMX_L2T_ERR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180080000008ull);
+}
+#else
+#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
+#endif
+
+/**
+ * cvmx_l2t_err
+ *
+ * L2T_ERR = L2 Tag Errors
+ *
+ * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
+ */
+union cvmx_l2t_err
+{
+	uint64_t u64;
+	struct cvmx_l2t_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t fadru                        : 1;  /**< Failing L2 Tag Upper Address Bit (Index[10])
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADRU contains the upper(MSB bit) cacheline index
+                                                         into the L2 Tag Store. */
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t fset                         : 3;  /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t fadr                         : 10; /**< Failing L2 Tag Address (10-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 10bit cacheline index
+                                                         into the L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 19-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:18]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 10;
+	uint64_t fset                         : 3;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t fadru                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_l2t_err_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is
+                                                         completed successfully, however the address is NOT
+                                                         locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t reserved_23_23               : 1;
+	uint64_t fset                         : 2;  /**< Failing L2 Tag Hit Set# (1-of-4)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t reserved_19_20               : 2;
+	uint64_t fadr                         : 8;  /**< Failing L2 Tag Store Index (8-bit)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 8bit cacheline index into the
+                                                         L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 22-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:15]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 8;
+	uint64_t reserved_19_20               : 2;
+	uint64_t fset                         : 2;
+	uint64_t reserved_23_23               : 1;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn30xx;
+	struct cvmx_l2t_err_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t reserved_23_23               : 1;
+	uint64_t fset                         : 2;  /**< Failing L2 Tag Hit Set# (1-of-4)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t reserved_20_20               : 1;
+	uint64_t fadr                         : 9;  /**< Failing L2 Tag Address (9-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 9-bit cacheline index into the
+                                                         L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 9;
+	uint64_t reserved_20_20               : 1;
+	uint64_t fset                         : 2;
+	uint64_t reserved_23_23               : 1;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn31xx;
+	struct cvmx_l2t_err_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t fset                         : 3;  /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t fadr                         : 10; /**< Failing L2 Tag Address (10-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 10bit cacheline index into the
+                                                         L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 20-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:17]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 10;
+	uint64_t fset                         : 3;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn38xx;
+	struct cvmx_l2t_err_cn38xx            cn38xxp2;
+	struct cvmx_l2t_err_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t fset                         : 3;  /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t reserved_18_20               : 3;
+	uint64_t fadr                         : 7;  /**< Failing L2 Tag Address (7-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 7bit cacheline index
+                                                         into the L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 23-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:14]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 7;
+	uint64_t reserved_18_20               : 3;
+	uint64_t fset                         : 3;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn50xx;
+	struct cvmx_l2t_err_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t lck_intena2                  : 1;  /**< L2 Tag Lock Error2 Interrupt Enable bit */
+	uint64_t lckerr2                      : 1;  /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+	uint64_t lck_intena                   : 1;  /**< L2 Tag Lock Error Interrupt Enable bit */
+	uint64_t lckerr                       : 1;  /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+	uint64_t fset                         : 3;  /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+	uint64_t reserved_20_20               : 1;
+	uint64_t fadr                         : 9;  /**< Failing L2 Tag Address (9-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 9bit cacheline index
+                                                         into the L2 Tag Store. */
+	uint64_t fsyn                         : 6;  /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+	uint64_t ded_err                      : 1;  /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+	uint64_t sec_err                      : 1;  /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+	uint64_t ded_intena                   : 1;  /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t sec_intena                   : 1;  /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+	uint64_t ecc_ena                      : 1;  /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
+#else
+	uint64_t ecc_ena                      : 1;
+	uint64_t sec_intena                   : 1;
+	uint64_t ded_intena                   : 1;
+	uint64_t sec_err                      : 1;
+	uint64_t ded_err                      : 1;
+	uint64_t fsyn                         : 6;
+	uint64_t fadr                         : 9;
+	uint64_t reserved_20_20               : 1;
+	uint64_t fset                         : 3;
+	uint64_t lckerr                       : 1;
+	uint64_t lck_intena                   : 1;
+	uint64_t lckerr2                      : 1;
+	uint64_t lck_intena2                  : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn52xx;
+	struct cvmx_l2t_err_cn52xx            cn52xxp1;
+	struct cvmx_l2t_err_s                 cn56xx;
+	struct cvmx_l2t_err_s                 cn56xxp1;
+	struct cvmx_l2t_err_s                 cn58xx;
+	struct cvmx_l2t_err_s                 cn58xxp1;
+};
+typedef union cvmx_l2t_err cvmx_l2t_err_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-led-defs.h b/sys/contrib/octeon-sdk/cvmx-led-defs.h
new file mode 100644
index 0000000..b32c670
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-led-defs.h
@@ -0,0 +1,656 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-led-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon led.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_LED_TYPEDEFS_H__
+#define __CVMX_LED_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
+static inline uint64_t CVMX_LED_BLINK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
+}
+#else
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
+static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
+}
+#else
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
+static inline uint64_t CVMX_LED_CYLON_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
+}
+#else
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
+static inline uint64_t CVMX_LED_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
+}
+#else
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_EN CVMX_LED_EN_FUNC()
+static inline uint64_t CVMX_LED_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
+}
+#else
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
+static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
+}
+#else
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
+}
+#else
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
+}
+#else
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
+#endif
+
+/**
+ * cvmx_led_blink
+ *
+ * LED_BLINK = LED Blink Rate (in led_clks)
+ *
+ */
+union cvmx_led_blink
+{
+	uint64_t u64;
+	struct cvmx_led_blink_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rate                         : 8;  /**< LED Blink rate in led_latch clks
+                                                         RATE must be > 0 */
+#else
+	uint64_t rate                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_led_blink_s               cn38xx;
+	struct cvmx_led_blink_s               cn38xxp2;
+	struct cvmx_led_blink_s               cn56xx;
+	struct cvmx_led_blink_s               cn56xxp1;
+	struct cvmx_led_blink_s               cn58xx;
+	struct cvmx_led_blink_s               cn58xxp1;
+};
+typedef union cvmx_led_blink cvmx_led_blink_t;
+
+/**
+ * cvmx_led_clk_phase
+ *
+ * LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
+ *
+ *
+ * Notes:
+ * Example:
+ * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
+ * led_clk phase is 64 eclks, or 128ns.  The led_clk period is 2*phase,
+ * or 256ns which is 3.9MHz.  The default value of 4, yields an led_clk
+ * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
+ */
+union cvmx_led_clk_phase
+{
+	uint64_t u64;
+	struct cvmx_led_clk_phase_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t phase                        : 7;  /**< Number of 64 eclks in order to create the led_clk */
+#else
+	uint64_t phase                        : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_led_clk_phase_s           cn38xx;
+	struct cvmx_led_clk_phase_s           cn38xxp2;
+	struct cvmx_led_clk_phase_s           cn56xx;
+	struct cvmx_led_clk_phase_s           cn56xxp1;
+	struct cvmx_led_clk_phase_s           cn58xx;
+	struct cvmx_led_clk_phase_s           cn58xxp1;
+};
+typedef union cvmx_led_clk_phase cvmx_led_clk_phase_t;
+
+/**
+ * cvmx_led_cylon
+ *
+ * LED_CYLON = LED CYLON Effect (should remain undocumented)
+ *
+ */
+union cvmx_led_cylon
+{
+	uint64_t u64;
+	struct cvmx_led_cylon_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t rate                         : 16; /**< LED Cylon Effect when RATE!=0
+                                                         Changes at RATE*LATCH period */
+#else
+	uint64_t rate                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_led_cylon_s               cn38xx;
+	struct cvmx_led_cylon_s               cn38xxp2;
+	struct cvmx_led_cylon_s               cn56xx;
+	struct cvmx_led_cylon_s               cn56xxp1;
+	struct cvmx_led_cylon_s               cn58xx;
+	struct cvmx_led_cylon_s               cn58xxp1;
+};
+typedef union cvmx_led_cylon cvmx_led_cylon_t;
+
+/**
+ * cvmx_led_dbg
+ *
+ * LED_DBG = LED Debug Port information
+ *
+ */
+union cvmx_led_dbg
+{
+	uint64_t u64;
+	struct cvmx_led_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t dbg_en                       : 1;  /**< Add Debug Port Data to the LED shift chain
+                                                         Debug Data is shifted out LSB to MSB */
+#else
+	uint64_t dbg_en                       : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_led_dbg_s                 cn38xx;
+	struct cvmx_led_dbg_s                 cn38xxp2;
+	struct cvmx_led_dbg_s                 cn56xx;
+	struct cvmx_led_dbg_s                 cn56xxp1;
+	struct cvmx_led_dbg_s                 cn58xx;
+	struct cvmx_led_dbg_s                 cn58xxp1;
+};
+typedef union cvmx_led_dbg cvmx_led_dbg_t;
+
+/**
+ * cvmx_led_en
+ *
+ * LED_EN = LED Interface Enable
+ *
+ *
+ * Notes:
+ * The LED interface is comprised of a shift chain with a parallel latch.  LED
+ * data is shifted out on each fallingg edge of led_clk and then captured by
+ * led_lat.
+ *
+ * The LED shift chain is comprised of the following...
+ *
+ *      32  - UDD header
+ *      6x8 - per port status
+ *      17  - debug port
+ *      32  - UDD trailer
+ *
+ * for a total of 129 bits.
+ *
+ * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
+ * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
+ * ... LED_UDD_DAT0[LED_UDD_CNT0].
+ *
+ * The per port status is also variable.  Systems can control which ports send
+ * data (LED_PRT) as well as the status content (LED_PRT_FMT and
+ * LED_PRT_STATUS*).  When multiple ports are enabled, they come out in lowest
+ * port to highest port (prt0, prt1, ...).
+ *
+ * The debug port data can also be added to the LED chain (LED_DBG).  When
+ * enabled, the debug data shifts out LSB to MSB.
+ *
+ * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
+ * and LED_UDD_DAT1.
+ */
+union cvmx_led_en
+{
+	uint64_t u64;
+	struct cvmx_led_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Enable the LED interface shift-chain */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_led_en_s                  cn38xx;
+	struct cvmx_led_en_s                  cn38xxp2;
+	struct cvmx_led_en_s                  cn56xx;
+	struct cvmx_led_en_s                  cn56xxp1;
+	struct cvmx_led_en_s                  cn58xx;
+	struct cvmx_led_en_s                  cn58xxp1;
+};
+typedef union cvmx_led_en cvmx_led_en_t;
+
+/**
+ * cvmx_led_polarity
+ *
+ * LED_POLARITY = LED Polarity
+ *
+ */
+union cvmx_led_polarity
+{
+	uint64_t u64;
+	struct cvmx_led_polarity_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t polarity                     : 1;  /**< LED active polarity
+                                                         0 = active HIGH LED
+                                                         1 = active LOW LED (invert led_dat) */
+#else
+	uint64_t polarity                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_led_polarity_s            cn38xx;
+	struct cvmx_led_polarity_s            cn38xxp2;
+	struct cvmx_led_polarity_s            cn56xx;
+	struct cvmx_led_polarity_s            cn56xxp1;
+	struct cvmx_led_polarity_s            cn58xx;
+	struct cvmx_led_polarity_s            cn58xxp1;
+};
+typedef union cvmx_led_polarity cvmx_led_polarity_t;
+
+/**
+ * cvmx_led_prt
+ *
+ * LED_PRT = LED Port status information
+ *
+ *
+ * Notes:
+ * Note:
+ * the PRT vector enables information of the 8 RGMII ports connected to
+ * Octane.  It does not reflect the actual programmed PHY addresses.
+ */
+union cvmx_led_prt
+{
+	uint64_t u64;
+	struct cvmx_led_prt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t prt_en                       : 8;  /**< Which ports are enabled to display status
+                                                         PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
+                                                         PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
+                                                         Only applies when interface is in RGMII mode
+                                                         The status format is defined by LED_PRT_FMT */
+#else
+	uint64_t prt_en                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_led_prt_s                 cn38xx;
+	struct cvmx_led_prt_s                 cn38xxp2;
+	struct cvmx_led_prt_s                 cn56xx;
+	struct cvmx_led_prt_s                 cn56xxp1;
+	struct cvmx_led_prt_s                 cn58xx;
+	struct cvmx_led_prt_s                 cn58xxp1;
+};
+typedef union cvmx_led_prt cvmx_led_prt_t;
+
+/**
+ * cvmx_led_prt_fmt
+ *
+ * LED_PRT_FMT = LED Port Status Infomation Format
+ *
+ *
+ * Notes:
+ * TX: RGMII TX block is sending packet data or extends on the port
+ * RX: RGMII RX block has received non-idle cycle
+ *
+ * For short transfers, LEDs will remain on for at least one blink cycle
+ */
+union cvmx_led_prt_fmt
+{
+	uint64_t u64;
+	struct cvmx_led_prt_fmt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t format                       : 4;  /**< Port Status Information for each enabled port in
+                                                         LED_PRT.  The formats are below
+                                                         0x0: [ LED_PRT_STATUS[0]            ]
+                                                         0x1: [ LED_PRT_STATUS[1:0]          ]
+                                                         0x2: [ LED_PRT_STATUS[3:0]          ]
+                                                         0x3: [ LED_PRT_STATUS[5:0]          ]
+                                                         0x4: [ (RX|TX), LED_PRT_STATUS[0]   ]
+                                                         0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
+                                                         0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
+                                                         0x8: [ Tx, Rx, LED_PRT_STATUS[0]    ]
+                                                         0x9: [ Tx, Rx, LED_PRT_STATUS[1:0]  ]
+                                                         0xa: [ Tx, Rx, LED_PRT_STATUS[3:0]  ] */
+#else
+	uint64_t format                       : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_led_prt_fmt_s             cn38xx;
+	struct cvmx_led_prt_fmt_s             cn38xxp2;
+	struct cvmx_led_prt_fmt_s             cn56xx;
+	struct cvmx_led_prt_fmt_s             cn56xxp1;
+	struct cvmx_led_prt_fmt_s             cn58xx;
+	struct cvmx_led_prt_fmt_s             cn58xxp1;
+};
+typedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t;
+
+/**
+ * cvmx_led_prt_status#
+ *
+ * LED_PRT_STATUS = LED Port Status information
+ *
+ */
+union cvmx_led_prt_statusx
+{
+	uint64_t u64;
+	struct cvmx_led_prt_statusx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t status                       : 6;  /**< Bits that software can set to be added to the
+                                                         LED shift chain - depending on LED_PRT_FMT
+                                                         LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
+                                                          on interface0
+                                                         LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
+                                                          on interface1
+                                                         Only applies when interface is in RGMII mode */
+#else
+	uint64_t status                       : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_led_prt_statusx_s         cn38xx;
+	struct cvmx_led_prt_statusx_s         cn38xxp2;
+	struct cvmx_led_prt_statusx_s         cn56xx;
+	struct cvmx_led_prt_statusx_s         cn56xxp1;
+	struct cvmx_led_prt_statusx_s         cn58xx;
+	struct cvmx_led_prt_statusx_s         cn58xxp1;
+};
+typedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t;
+
+/**
+ * cvmx_led_udd_cnt#
+ *
+ * LED_UDD_CNT = LED UDD Counts
+ *
+ */
+union cvmx_led_udd_cntx
+{
+	uint64_t u64;
+	struct cvmx_led_udd_cntx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t cnt                          : 6;  /**< Number of bits of user-defined data to include in
+                                                         the LED shift chain.  Legal values: 0-32. */
+#else
+	uint64_t cnt                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_led_udd_cntx_s            cn38xx;
+	struct cvmx_led_udd_cntx_s            cn38xxp2;
+	struct cvmx_led_udd_cntx_s            cn56xx;
+	struct cvmx_led_udd_cntx_s            cn56xxp1;
+	struct cvmx_led_udd_cntx_s            cn58xx;
+	struct cvmx_led_udd_cntx_s            cn58xxp1;
+};
+typedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t;
+
+/**
+ * cvmx_led_udd_dat#
+ *
+ * LED_UDD_DAT = User defined data (header or trailer)
+ *
+ *
+ * Notes:
+ * Bits come out LSB to MSB on the shift chain.  If LED_UDD_CNT is set to 4
+ * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
+ * LED_UDD_DAT[3].
+ */
+union cvmx_led_udd_datx
+{
+	uint64_t u64;
+	struct cvmx_led_udd_datx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dat                          : 32; /**< Header or trailer UDD data to be displayed on
+                                                         the LED shift chain.  Number of bits to include
+                                                         is controled by LED_UDD_CNT */
+#else
+	uint64_t dat                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_led_udd_datx_s            cn38xx;
+	struct cvmx_led_udd_datx_s            cn38xxp2;
+	struct cvmx_led_udd_datx_s            cn56xx;
+	struct cvmx_led_udd_datx_s            cn56xxp1;
+	struct cvmx_led_udd_datx_s            cn58xx;
+	struct cvmx_led_udd_datx_s            cn58xxp1;
+};
+typedef union cvmx_led_udd_datx cvmx_led_udd_datx_t;
+
+/**
+ * cvmx_led_udd_dat_clr#
+ *
+ * LED_UDD_DAT_CLR = User defined data (header or trailer)
+ *
+ */
+union cvmx_led_udd_dat_clrx
+{
+	uint64_t u64;
+	struct cvmx_led_udd_dat_clrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t clr                          : 32; /**< Bitwise clear for the Header or trailer UDD data to
+                                                         be displayed on the LED shift chain. */
+#else
+	uint64_t clr                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_led_udd_dat_clrx_s        cn38xx;
+	struct cvmx_led_udd_dat_clrx_s        cn38xxp2;
+	struct cvmx_led_udd_dat_clrx_s        cn56xx;
+	struct cvmx_led_udd_dat_clrx_s        cn56xxp1;
+	struct cvmx_led_udd_dat_clrx_s        cn58xx;
+	struct cvmx_led_udd_dat_clrx_s        cn58xxp1;
+};
+typedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t;
+
+/**
+ * cvmx_led_udd_dat_set#
+ *
+ * LED_UDD_DAT_SET = User defined data (header or trailer)
+ *
+ */
+union cvmx_led_udd_dat_setx
+{
+	uint64_t u64;
+	struct cvmx_led_udd_dat_setx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t set                          : 32; /**< Bitwise set for the Header or trailer UDD data to
+                                                         be displayed on the LED shift chain. */
+#else
+	uint64_t set                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_led_udd_dat_setx_s        cn38xx;
+	struct cvmx_led_udd_dat_setx_s        cn38xxp2;
+	struct cvmx_led_udd_dat_setx_s        cn56xx;
+	struct cvmx_led_udd_dat_setx_s        cn56xxp1;
+	struct cvmx_led_udd_dat_setx_s        cn58xx;
+	struct cvmx_led_udd_dat_setx_s        cn58xxp1;
+};
+typedef union cvmx_led_udd_dat_setx cvmx_led_udd_dat_setx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-llm.c b/sys/contrib/octeon-sdk/cvmx-llm.c
index fb058c8..3d19670 100644
--- a/sys/contrib/octeon-sdk/cvmx-llm.c
+++ b/sys/contrib/octeon-sdk/cvmx-llm.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Configuration functions for low latency memory.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52372 $<hr>
  */
 #include "cvmx-config.h"
 #include "cvmx.h"
@@ -113,7 +115,7 @@ int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr)
 
     memset(llm_desc_ptr, 0, sizeof(llm_descriptor_t));
 
-    llm_desc_ptr->cpu_hz = sys_ptr->cpu_clock_hz;
+    llm_desc_ptr->cpu_hz = cvmx_clock_get_rate(CVMX_CLOCK_CORE);
 
     if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBT3000)
     { // N3K->RLD0 Address Swizzle
@@ -461,7 +463,7 @@ int rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t
             sil_lat = 2;
 
         /* Increment tskw for high clock speeds */
-        if ((unsigned long)eclk_mhz/clkdiv > 375)
+        if ((unsigned long)eclk_mhz/clkdiv >= 375)
             tskw_cyc += 1;
     }
 
@@ -577,10 +579,6 @@ int rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t
     }
     else if (membunk == 512)
     { // 512MB/bunk
-        if (cvmx_octeon_is_pass1() == 1)
-        {
-            goto TERMINATE;
-        }
     }
     //=======================================================================
     //=======================================================================
diff --git a/sys/contrib/octeon-sdk/cvmx-llm.h b/sys/contrib/octeon-sdk/cvmx-llm.h
index b1d1e1f..1abec09 100644
--- a/sys/contrib/octeon-sdk/cvmx-llm.h
+++ b/sys/contrib/octeon-sdk/cvmx-llm.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * interface to the low latency DRAM
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -223,10 +225,7 @@ static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t va
     cvmx_llm_data_t data;
     data.s.mbz = 0;
 
-    if (cvmx_octeon_is_pass1())
-        data.s.dat = ((value & 0x3ffff) << 18) | ((value >> 18) & 0x3ffff);
-    else
-        data.s.dat = value;
+    data.s.dat = value;
 
     data.s.xxor = 0;
 
@@ -256,24 +255,15 @@ static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t va
  */
 static inline void cvmx_llm_write_wide(cvmx_llm_address_t address, uint64_t value, int set)
 {
-    if (cvmx_octeon_is_pass1())
+    if (set)
     {
-        cvmx_llm_write36(address, value & 0xfffffffffull, set);
-        address.s.address+=4;
-        cvmx_llm_write36(address, ((value>>36) & 0xfffffff) | (cvmx_llm_ecc(value) << 28), set);
+        CVMX_MT_LLM_DATA(1, value);
+        CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
     }
     else
     {
-        if (set)
-        {
-            CVMX_MT_LLM_DATA(1, value);
-            CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
-        }
-        else
-        {
-            CVMX_MT_LLM_DATA(0, value);
-            CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
-        }
+        CVMX_MT_LLM_DATA(0, value);
+        CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
     }
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-lmc.h b/sys/contrib/octeon-sdk/cvmx-lmc.h
deleted file mode 100644
index 54cda6a..0000000
--- a/sys/contrib/octeon-sdk/cvmx-lmc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * Memory controller interface.
- *
- * <hr>$Revision: 41586 $<hr>
- */
-
-#ifndef __CVMX_ASX_H__
-#define __CVMX_ASX_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif
-
diff --git a/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h b/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
new file mode 100644
index 0000000..dbc45eb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
@@ -0,0 +1,7061 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-lmcx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon lmcx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_LMCX_TYPEDEFS_H__
+#define __CVMX_LMCX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000220ull);
+}
+#else
+#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_MASK0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_MASK0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000228ull);
+}
+#else
+#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_MASK1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_MASK1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000230ull);
+}
+#else
+#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_MASK2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_MASK2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000238ull);
+}
+#else
+#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_MASK3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_MASK3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000240ull);
+}
+#else
+#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CHAR_MASK4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CHAR_MASK4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000318ull);
+}
+#else
+#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_COMP_CTL2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_COMP_CTL2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001B8ull);
+}
+#else
+#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CONFIG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CONFIG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000188ull);
+}
+#else
+#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CONTROL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CONTROL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000190ull);
+}
+#else
+#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DCLK_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DCLK_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001E0ull);
+}
+#else
+#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DDR_PLL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DDR_PLL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000258ull);
+}
+#else
+#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DIMMX_PARAMS(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_LMCX_DIMMX_PARAMS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
+}
+#else
+#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DIMM_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DIMM_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000310ull);
+}
+#else
+#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DLL_CTL2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DLL_CTL2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001C8ull);
+}
+#else
+#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DLL_CTL3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DLL_CTL3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000218ull);
+}
+#else
+#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_DUAL_MEMCFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_ECC_SYND(block_id) (CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_IFB_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_IFB_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001D0ull);
+}
+#else
+#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_INT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_INT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001F0ull);
+}
+#else
+#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_INT_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_INT_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001E8ull);
+}
+#else
+#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_MODEREG_PARAMS0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_MODEREG_PARAMS0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001A8ull);
+}
+#else
+#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_MODEREG_PARAMS1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_MODEREG_PARAMS1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000260ull);
+}
+#else
+#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_NXM(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_OPS_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_OPS_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001D8ull);
+}
+#else
+#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_PHY_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_PHY_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000210ull);
+}
+#else
+#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000040ull);
+}
+#else
+#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8;
+}
+#else
+#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RESET_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RESET_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000180ull);
+}
+#else
+#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RLEVEL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880002A0ull);
+}
+#else
+#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RLEVEL_DBG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880002A8ull);
+}
+#else
+#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RLEVEL_RANKX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_LMCX_RLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+}
+#else
+#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_RODT_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_RODT_MASK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000268ull);
+}
+#else
+#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SLOT_CTL0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SLOT_CTL0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001F8ull);
+}
+#else
+#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SLOT_CTL1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SLOT_CTL1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000200ull);
+}
+#else
+#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_SLOT_CTL2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_SLOT_CTL2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000208ull);
+}
+#else
+#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_TIMING_PARAMS0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_TIMING_PARAMS0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000198ull);
+}
+#else
+#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_TIMING_PARAMS1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_TIMING_PARAMS1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001A0ull);
+}
+#else
+#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_TRO_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_TRO_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000248ull);
+}
+#else
+#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_TRO_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_TRO_STAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000250ull);
+}
+#else
+#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WLEVEL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_WLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000300ull);
+}
+#else
+#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WLEVEL_DBG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_WLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000308ull);
+}
+#else
+#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WLEVEL_RANKX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_LMCX_WLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+}
+#else
+#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull;
+}
+#else
+#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_LMCX_WODT_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_LMCX_WODT_MASK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800880001B0ull);
+}
+#else
+#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull))
+#endif
+
+/**
+ * cvmx_lmc#_bist_ctl
+ *
+ * Notes:
+ * This controls BiST only for the memories that operate on DCLK.  The normal, chip-wide BiST flow
+ * controls BiST for the memories that operate on ECLK.
+ */
+union cvmx_lmcx_bist_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_bist_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t start                        : 1;  /**< A 0->1 transition causes BiST to run. */
+#else
+	uint64_t start                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_lmcx_bist_ctl_s           cn50xx;
+	struct cvmx_lmcx_bist_ctl_s           cn52xx;
+	struct cvmx_lmcx_bist_ctl_s           cn52xxp1;
+	struct cvmx_lmcx_bist_ctl_s           cn56xx;
+	struct cvmx_lmcx_bist_ctl_s           cn56xxp1;
+};
+typedef union cvmx_lmcx_bist_ctl cvmx_lmcx_bist_ctl_t;
+
+/**
+ * cvmx_lmc#_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_lmcx_bist_result
+{
+	uint64_t u64;
+	struct cvmx_lmcx_bist_result_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t csrd2e                       : 1;  /**< BiST result of CSRD2E memory (0=pass, !0=fail) */
+	uint64_t csre2d                       : 1;  /**< BiST result of CSRE2D memory (0=pass, !0=fail) */
+	uint64_t mwf                          : 1;  /**< BiST result of MWF memories (0=pass, !0=fail) */
+	uint64_t mwd                          : 3;  /**< BiST result of MWD memories (0=pass, !0=fail) */
+	uint64_t mwc                          : 1;  /**< BiST result of MWC memories (0=pass, !0=fail) */
+	uint64_t mrf                          : 1;  /**< BiST result of MRF memories (0=pass, !0=fail) */
+	uint64_t mrd                          : 3;  /**< BiST result of MRD memories (0=pass, !0=fail) */
+#else
+	uint64_t mrd                          : 3;
+	uint64_t mrf                          : 1;
+	uint64_t mwc                          : 1;
+	uint64_t mwd                          : 3;
+	uint64_t mwf                          : 1;
+	uint64_t csre2d                       : 1;
+	uint64_t csrd2e                       : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_lmcx_bist_result_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t mwf                          : 1;  /**< BiST result of MWF memories (0=pass, !0=fail) */
+	uint64_t mwd                          : 3;  /**< BiST result of MWD memories (0=pass, !0=fail) */
+	uint64_t mwc                          : 1;  /**< BiST result of MWC memories (0=pass, !0=fail) */
+	uint64_t mrf                          : 1;  /**< BiST result of MRF memories (0=pass, !0=fail) */
+	uint64_t mrd                          : 3;  /**< BiST result of MRD memories (0=pass, !0=fail) */
+#else
+	uint64_t mrd                          : 3;
+	uint64_t mrf                          : 1;
+	uint64_t mwc                          : 1;
+	uint64_t mwd                          : 3;
+	uint64_t mwf                          : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn50xx;
+	struct cvmx_lmcx_bist_result_s        cn52xx;
+	struct cvmx_lmcx_bist_result_s        cn52xxp1;
+	struct cvmx_lmcx_bist_result_s        cn56xx;
+	struct cvmx_lmcx_bist_result_s        cn56xxp1;
+};
+typedef union cvmx_lmcx_bist_result cvmx_lmcx_bist_result_t;
+
+/**
+ * cvmx_lmc#_char_ctl
+ *
+ * LMC_CHAR_CTL = LMC Characterization Control
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t en                           : 1;  /**< Enable characterization */
+	uint64_t sel                          : 1;  /**< Pattern select
+                                                         0 = PRBS
+                                                         1 = Programmable pattern */
+	uint64_t prog                         : 8;  /**< Programmable pattern */
+	uint64_t prbs                         : 32; /**< PRBS Polynomial */
+#else
+	uint64_t prbs                         : 32;
+	uint64_t prog                         : 8;
+	uint64_t sel                          : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_lmcx_char_ctl_s           cn63xx;
+	struct cvmx_lmcx_char_ctl_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_char_ctl cvmx_lmcx_char_ctl_t;
+
+/**
+ * cvmx_lmc#_char_mask0
+ *
+ * LMC_CHAR_MASK0 = LMC Characterization Mask0
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_mask0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_mask0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Mask for DQ0[63:0] */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_char_mask0_s         cn63xx;
+	struct cvmx_lmcx_char_mask0_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_char_mask0 cvmx_lmcx_char_mask0_t;
+
+/**
+ * cvmx_lmc#_char_mask1
+ *
+ * LMC_CHAR_MASK1 = LMC Characterization Mask1
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_mask1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_mask1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t mask                         : 8;  /**< Mask for DQ0[71:64] */
+#else
+	uint64_t mask                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_lmcx_char_mask1_s         cn63xx;
+	struct cvmx_lmcx_char_mask1_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_char_mask1 cvmx_lmcx_char_mask1_t;
+
+/**
+ * cvmx_lmc#_char_mask2
+ *
+ * LMC_CHAR_MASK2 = LMC Characterization Mask2
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_mask2
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_mask2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Mask for DQ1[63:0] */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_char_mask2_s         cn63xx;
+	struct cvmx_lmcx_char_mask2_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_char_mask2 cvmx_lmcx_char_mask2_t;
+
+/**
+ * cvmx_lmc#_char_mask3
+ *
+ * LMC_CHAR_MASK3 = LMC Characterization Mask3
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_mask3
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_mask3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t mask                         : 8;  /**< Mask for DQ1[71:64] */
+#else
+	uint64_t mask                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_lmcx_char_mask3_s         cn63xx;
+	struct cvmx_lmcx_char_mask3_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_char_mask3 cvmx_lmcx_char_mask3_t;
+
+/**
+ * cvmx_lmc#_char_mask4
+ *
+ * LMC_CHAR_MASK4 = LMC Characterization Mask4
+ * This register is an assortment of various control fields needed to charecterize the DDR3 interface
+ */
+union cvmx_lmcx_char_mask4
+{
+	uint64_t u64;
+	struct cvmx_lmcx_char_mask4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t reset_n_mask                 : 1;  /**< Mask for RESET_L */
+	uint64_t a_mask                       : 16; /**< Mask for A[15:0] */
+	uint64_t ba_mask                      : 3;  /**< Mask for BA[2:0] */
+	uint64_t we_n_mask                    : 1;  /**< Mask for WE_N */
+	uint64_t cas_n_mask                   : 1;  /**< Mask for CAS_N */
+	uint64_t ras_n_mask                   : 1;  /**< Mask for RAS_N */
+	uint64_t odt1_mask                    : 2;  /**< Mask for ODT1 */
+	uint64_t odt0_mask                    : 2;  /**< Mask for ODT0 */
+	uint64_t cs1_n_mask                   : 2;  /**< Mask for CS1_N */
+	uint64_t cs0_n_mask                   : 2;  /**< Mask for CS0_N */
+	uint64_t cke_mask                     : 2;  /**< Mask for CKE* */
+#else
+	uint64_t cke_mask                     : 2;
+	uint64_t cs0_n_mask                   : 2;
+	uint64_t cs1_n_mask                   : 2;
+	uint64_t odt0_mask                    : 2;
+	uint64_t odt1_mask                    : 2;
+	uint64_t ras_n_mask                   : 1;
+	uint64_t cas_n_mask                   : 1;
+	uint64_t we_n_mask                    : 1;
+	uint64_t ba_mask                      : 3;
+	uint64_t a_mask                       : 16;
+	uint64_t reset_n_mask                 : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_lmcx_char_mask4_s         cn63xx;
+	struct cvmx_lmcx_char_mask4_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_char_mask4 cvmx_lmcx_char_mask4_t;
+
+/**
+ * cvmx_lmc#_comp_ctl
+ *
+ * LMC_COMP_CTL = LMC Compensation control
+ *
+ */
+union cvmx_lmcx_comp_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_comp_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_clk                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_cmd                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_dat                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_clk                     : 4;  /**< Compensation control bits */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t pctl_clk                     : 4;
+	uint64_t pctl_csr                     : 4;
+	uint64_t nctl_dat                     : 4;
+	uint64_t nctl_cmd                     : 4;
+	uint64_t nctl_clk                     : 4;
+	uint64_t nctl_csr                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_comp_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_clk                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_cmd                     : 4;  /**< Compensation control bits */
+	uint64_t nctl_dat                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_clk                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_cmd                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_dat                     : 4;  /**< Compensation control bits */
+#else
+	uint64_t pctl_dat                     : 4;
+	uint64_t pctl_cmd                     : 4;
+	uint64_t pctl_clk                     : 4;
+	uint64_t pctl_csr                     : 4;
+	uint64_t nctl_dat                     : 4;
+	uint64_t nctl_cmd                     : 4;
+	uint64_t nctl_clk                     : 4;
+	uint64_t nctl_csr                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_comp_ctl_cn30xx      cn31xx;
+	struct cvmx_lmcx_comp_ctl_cn30xx      cn38xx;
+	struct cvmx_lmcx_comp_ctl_cn30xx      cn38xxp2;
+	struct cvmx_lmcx_comp_ctl_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t reserved_20_27               : 8;
+	uint64_t nctl_dat                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t reserved_5_11                : 7;
+	uint64_t pctl_dat                     : 5;  /**< Compensation control bits */
+#else
+	uint64_t pctl_dat                     : 5;
+	uint64_t reserved_5_11                : 7;
+	uint64_t pctl_csr                     : 4;
+	uint64_t nctl_dat                     : 4;
+	uint64_t reserved_20_27               : 8;
+	uint64_t nctl_csr                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn50xx;
+	struct cvmx_lmcx_comp_ctl_cn50xx      cn52xx;
+	struct cvmx_lmcx_comp_ctl_cn50xx      cn52xxp1;
+	struct cvmx_lmcx_comp_ctl_cn50xx      cn56xx;
+	struct cvmx_lmcx_comp_ctl_cn50xx      cn56xxp1;
+	struct cvmx_lmcx_comp_ctl_cn50xx      cn58xx;
+	struct cvmx_lmcx_comp_ctl_cn58xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t reserved_20_27               : 8;
+	uint64_t nctl_dat                     : 4;  /**< Compensation control bits */
+	uint64_t pctl_csr                     : 4;  /**< Compensation control bits */
+	uint64_t reserved_4_11                : 8;
+	uint64_t pctl_dat                     : 4;  /**< Compensation control bits */
+#else
+	uint64_t pctl_dat                     : 4;
+	uint64_t reserved_4_11                : 8;
+	uint64_t pctl_csr                     : 4;
+	uint64_t nctl_dat                     : 4;
+	uint64_t reserved_20_27               : 8;
+	uint64_t nctl_csr                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn58xxp1;
+};
+typedef union cvmx_lmcx_comp_ctl cvmx_lmcx_comp_ctl_t;
+
+/**
+ * cvmx_lmc#_comp_ctl2
+ *
+ * LMC_COMP_CTL2 = LMC Compensation control
+ *
+ */
+union cvmx_lmcx_comp_ctl2
+{
+	uint64_t u64;
+	struct cvmx_lmcx_comp_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ddr__ptune                   : 4;  /**< DDR PCTL from compensation circuit
+                                                         The encoded value provides debug information for the
+                                                         compensation impedance on P-pullup */
+	uint64_t ddr__ntune                   : 4;  /**< DDR NCTL from compensation circuit
+                                                         The encoded value provides debug information for the
+                                                         compensation impedance on N-pulldown */
+	uint64_t m180                         : 1;  /**< Cap impedance at 180 Ohm (instead of 240 Ohm) */
+	uint64_t byp                          : 1;  /**< Bypass mode
+                                                         When set, PTUNE,NTUNE are the compensation setting.
+                                                         When clear, DDR_PTUNE,DDR_NTUNE are the compensation setting. */
+	uint64_t ptune                        : 4;  /**< PCTL impedance control in bypass mode */
+	uint64_t ntune                        : 4;  /**< NCTL impedance control in bypass mode */
+	uint64_t rodt_ctl                     : 4;  /**< NCTL RODT impedance control bits
+                                                         This field controls ODT values during a memory read
+                                                         on the Octeon side
+                                                         0000 = No ODT
+                                                         0001 = 20 ohm
+                                                         0010 = 30 ohm
+                                                         0011 = 40 ohm
+                                                         0100 = 60 ohm
+                                                         0101 = 120 ohm
+                                                         0110-1111 = Reserved */
+	uint64_t cmd_ctl                      : 4;  /**< Drive strength control for CMD/A/RESET_L/CKE* drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+	uint64_t ck_ctl                       : 4;  /**< Drive strength control for CK/CS*_L/ODT drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+	uint64_t dqx_ctl                      : 4;  /**< Drive strength control for DQ/DQS drivers
+                                                         0001 = 24 ohm
+                                                         0010 = 26.67 ohm
+                                                         0011 = 30 ohm
+                                                         0100 = 34.3 ohm
+                                                         0101 = 40 ohm
+                                                         0110 = 48 ohm
+                                                         0111 = 60 ohm
+                                                         0000,1000-1111 = Reserved */
+#else
+	uint64_t dqx_ctl                      : 4;
+	uint64_t ck_ctl                       : 4;
+	uint64_t cmd_ctl                      : 4;
+	uint64_t rodt_ctl                     : 4;
+	uint64_t ntune                        : 4;
+	uint64_t ptune                        : 4;
+	uint64_t byp                          : 1;
+	uint64_t m180                         : 1;
+	uint64_t ddr__ntune                   : 4;
+	uint64_t ddr__ptune                   : 4;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_lmcx_comp_ctl2_s          cn63xx;
+	struct cvmx_lmcx_comp_ctl2_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_comp_ctl2 cvmx_lmcx_comp_ctl2_t;
+
+/**
+ * cvmx_lmc#_config
+ *
+ * LMC_CONFIG = LMC Configuration Register
+ *
+ * This register controls certain parameters of  Memory Configuration
+ *
+ * Notes:
+ * a. Priority order for hardware writes to LMC*_CONFIG/LMC*_FADR/LMC*_ECC_SYND: DED error >= NXM error > SEC error
+ * b. The self refresh entry sequence(s) power the DLL up/down (depending on LMC*_MODEREG_PARAMS0[DLL])
+ * when LMC*_CONFIG[SREF_WITH_DLL] is set
+ * c. Prior to the self-refresh exit sequence, LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 should be re-programmed (if needed) to the
+ * appropriate values
+ *
+ * LMC Bringup Sequence:
+ * 1. SW must ensure there are no pending DRAM transactions and that the DDR PLL and the DLL have been initialized.
+ * 2. Write LMC*_COMP_CTL2, LMC*_CONTROL, LMC*_WODT_MASK, LMC*_DUAL_MEMCFG, LMC*_TIMING_PARAMS0, LMC*_TIMING_PARAMS1,
+ *    LMC*_MODEREG_PARAMS0, LMC*_MODEREG_PARAMS1, LMC*_RESET_CTL (with DDR3RST=0), LMC*_CONFIG (with INIT_START=0)
+ *    with appropriate values, if necessary.
+ * 3. Wait 200us, then write LMC*_RESET_CTL[DDR3RST] = 1.
+ * 4. Initialize all ranks at once by writing LMC*_CONFIG[RANKMASK][n] = 1, LMC*_CONFIG[INIT_STATUS][n] = 1, and LMC*_CONFIG[INIT_START] = 1
+ *    where n is a valid rank index for the specific board configuration.
+ * 5. for each rank n to be write-leveled [
+ *       if auto write-leveling is desired [
+ *           write LMC*_CONFIG[RANKMASK][n] = 1, LMC*_WLEVEL_CTL appropriately and LMC*_CONFIG[INIT_START] = 1
+ *           wait until LMC*_WLEVEL_RANKn[STATUS] = 3
+ *       ] else [
+ *           write LMC*_WLEVEL_RANKn with appropriate values
+ *       ]
+ *    ]
+ * 6. for each rank n to be read-leveled [
+ *       if auto read-leveling is desired [
+ *           write LMC*_CONFIG[RANKMASK][n] = 1, LMC*_RLEVEL_CTL appropriately and LMC*_CONFIG[INIT_START] = 1
+ *           wait until LMC*_RLEVEL_RANKn[STATUS] = 3
+ *       ] else [
+ *           write LMC*_RLEVEL_RANKn with appropriate values
+ *       ]
+ *    ]
+ */
+union cvmx_lmcx_config
+{
+	uint64_t u64;
+	struct cvmx_lmcx_config_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t early_unload_d1_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 3
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK3[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 3 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK3[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d1_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 2
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D1_RO value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK2[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 2 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK2[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D1_RO
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D1_RO = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r1           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 1
+                                                         reads
+                                                         The recommended EARLY_UNLOAD_D0_R1 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK1[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 1 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK1[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R1
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R1 = (maxset<1:0>!=3)). */
+	uint64_t early_unload_d0_r0           : 1;  /**< When set, unload the PHY silo one cycle early for Rank 0
+                                                         reads.
+                                                         The recommended EARLY_UNLOAD_D0_R0 value can be calculated
+                                                         after the final LMC*_RLEVEL_RANK0[BYTE*] values are
+                                                         selected (as part of read-leveling initialization).
+                                                         Then, determine the largest read-leveling setting
+                                                         for rank 0 (i.e. calculate maxset=MAX(LMC*_RLEVEL_RANK0[BYTEi])
+                                                         across all i), then set EARLY_UNLOAD_D0_R0
+                                                         when the low two bits of this largest setting is not
+                                                         3 (i.e. EARLY_UNLOAD_D0_R0 = (maxset<1:0>!=3)). */
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same LMC*_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before LMC initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 3
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         When RANK_ENA=0, MIRRMASK<1> and MIRRMASK<3> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> = DIMM0_CS0                DIMM0_CS0
+                                                           RANKMASK<1> = DIMM0_CS1                  MBZ
+                                                           RANKMASK<2> = DIMM1_CS0                DIMM1_CS0
+                                                           RANKMASK<3> = DIMM1_CS1                  MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         When RANK_ENA=0, RANKMASK<1> and RANKMASK<3> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the rank_ena bit will enable
+                                                         the drive of the CS*_L[1:0] and ODT_<1:0> pins differently based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Selects the sequence that LMC runs after a 0->1
+                                                         transition on LMC*_CONFIG[INIT_START].
+                                                         SEQUENCE=0=power-up/init:
+                                                           - RANKMASK selects participating ranks (should be all ranks with attached DRAM)
+                                                           - INIT_STATUS must equal RANKMASK
+                                                           - DDR_CKE* signals activated (if they weren't already active)
+                                                           - RDIMM register control words 0-15 will be written to RANKMASK-selected
+                                                               RDIMM's when LMC(0)_CONTROL[RDIMM_ENA]=1 and corresponding
+                                                               LMC*_DIMM_CTL[DIMM*_WMASK] bits are set. (Refer to LMC*_DIMM*_PARAMS and
+                                                               LMC*_DIMM_CTL descriptions below for more details.)
+                                                           - MR0, MR1, MR2, and MR3 will be written to selected ranks
+                                                         SEQUENCE=1=read-leveling:
+                                                           - RANKMASK selects the rank to be read-leveled
+                                                           - MR3 written to selected rank
+                                                         SEQUENCE=2=self-refresh entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - MR1 and MR2 will be written to selected ranks if SREF_WITH_DLL=1
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=3=self-refresh exit:
+                                                           - INIT_STATUS must be set to indicate participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                           - MR0, MR1, MR2, and MR3 will be written to participating ranks if SREF_WITH_DLL=1
+                                                         SEQUENCE=4=precharge power-down entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=5=precharge power-down exit:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                         SEQUENCE=6=write-leveling:
+                                                           - RANKMASK selects the rank to be write-leveled
+                                                           - INIT_STATUS must indicate all ranks with attached DRAM
+                                                           - MR1 and MR2 written to INIT_STATUS-selected ranks
+                                                         SEQUENCE=7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may also
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may also be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         LMC writes the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (i.e. MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 descriptions for more details.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, LMC asserts DDR_CKE* as part of
+                                                         the first power-up/init, and continues to assert DDR_CKE*
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DDR_CKE* deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 CK cycle
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 CKs
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 CKs ~ 335ms for a 800 MHz CK
+                                                         LMC*_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. LMC does not send any refreshes / ZQCS's
+                                                         when LMC*_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC*_OPS_CNT, LMC*_IFB_CNT, and LMC*_DCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE CK cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) CK cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         LMC*_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< DIMM address bit select
+                                                         Reverting to the explanation for ROW_LSB,
+                                                         PBank_LSB would be Row_LSB bit + \#rowbits + \#rankbits
+                                                         Decoding for pbank_lsb
+                                                              - 0000:DIMM = mem_adr[28]    / rank = mem_adr[27] (if RANK_ENA)
+                                                              - 0001:DIMM = mem_adr[29]    / rank = mem_adr[28]      "
+                                                              - 0010:DIMM = mem_adr[30]    / rank = mem_adr[29]      "
+                                                              - 0011:DIMM = mem_adr[31]    / rank = mem_adr[30]      "
+                                                              - 0100:DIMM = mem_adr[32]    / rank = mem_adr[31]      "
+                                                              - 0101:DIMM = mem_adr[33]    / rank = mem_adr[32]      "
+                                                              - 0110:DIMM = mem_adr[34]    / rank = mem_adr[33]      "
+                                                              - 0111:DIMM = 0              / rank = mem_adr[34]      "
+                                                              - 1000-1111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16]
+                                                         With rank_ena = 0, pbank_lsb = 2
+                                                         With rank_ena = 1, pbank_lsb = 3 */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[34:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and DIMM)
+                                                         and that is a function of the following:
+                                                         1. Datapath Width (64)
+                                                         2. \# Banks (8)
+                                                         3. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         4. \# Row Bits of the memory part - spec'd indirectly
+                                                         5. \# Ranks in a DIMM - spec'd by RANK_ENA
+                                                         6. \# DIMM's in the system by the register below (PBANK_LSB).
+                                                         Decoding for row_lsb
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101: row_lsb = mem_adr[19]
+                                                              - 110: row_lsb = mem_adr[20]
+                                                              - 111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16] */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64]
+                                                         on writes, will contain the ECC code generated for
+                                                         the 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC*_FADR, and LMC*_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by LMC*_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t early_unload_d0_r0           : 1;
+	uint64_t early_unload_d0_r1           : 1;
+	uint64_t early_unload_d1_r0           : 1;
+	uint64_t early_unload_d1_r1           : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_lmcx_config_s             cn63xx;
+	struct cvmx_lmcx_config_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_55_63               : 9;
+	uint64_t init_status                  : 4;  /**< Indicates status of initialization
+                                                         INIT_STATUS[n] = 1 implies rank n has been initialized
+                                                         SW must set necessary INIT_STATUS bits with the
+                                                         same LMC*_CONFIG write that initiates
+                                                         power-up/init and self-refresh exit sequences
+                                                         (if the required INIT_STATUS bits are not already
+                                                         set before LMC initiates the sequence).
+                                                         INIT_STATUS determines the chip-selects that assert
+                                                         during refresh, ZQCS, and precharge power-down and
+                                                         self-refresh entry/exit SEQUENCE's. */
+	uint64_t mirrmask                     : 4;  /**< Mask determining which ranks are address-mirrored.
+                                                         MIRRMASK<n> = 1 means Rank n addresses are mirrored
+                                                         for 0 <= n <= 3
+                                                         A mirrored read/write has these differences:
+                                                          - DDR_BA<1> is swapped with DDR_BA<0>
+                                                          - DDR_A<8> is swapped with DDR_A<7>
+                                                          - DDR_A<6> is swapped with DDR_A<5>
+                                                          - DDR_A<4> is swapped with DDR_A<3>
+                                                         When RANK_ENA=0, MIRRMASK<1> and MIRRMASK<3> MBZ */
+	uint64_t rankmask                     : 4;  /**< Mask to select rank to be leveled/initialized.
+                                                         To write-level/read-level/initialize rank i, set RANKMASK<i>
+                                                                         RANK_ENA=1               RANK_ENA=0
+                                                           RANKMASK<0> = DIMM0_CS0                DIMM0_CS0
+                                                           RANKMASK<1> = DIMM0_CS1                  MBZ
+                                                           RANKMASK<2> = DIMM1_CS0                DIMM1_CS0
+                                                           RANKMASK<3> = DIMM1_CS1                  MBZ
+                                                         For read/write leveling, each rank has to be leveled separately,
+                                                         so RANKMASK should only have one bit set.
+                                                         RANKMASK is not used during self-refresh entry/exit and
+                                                         precharge power-down entry/exit instruction sequences.
+                                                         When RANK_ENA=0, RANKMASK<1> and RANKMASK<3> MBZ */
+	uint64_t rank_ena                     : 1;  /**< RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the rank_ena bit will enable
+                                                         the drive of the CS*_L[1:0] and ODT_<1:0> pins differently based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+	uint64_t sref_with_dll                : 1;  /**< Self-refresh entry/exit write MR1 and MR2
+                                                         When set, self-refresh entry and exit instruction sequences
+                                                         write MR1 and MR2 (in all ranks). (The writes occur before
+                                                         self-refresh entry, and after self-refresh exit.)
+                                                         When clear, self-refresh entry and exit instruction sequences
+                                                         do not write any registers in the DDR3 parts. */
+	uint64_t early_dqx                    : 1;  /**< Send DQx signals one CK cycle earlier for the case when
+                                                         the shortest DQx lines have a larger delay than the CK line */
+	uint64_t sequence                     : 3;  /**< Selects the sequence that LMC runs after a 0->1
+                                                         transition on LMC*_CONFIG[INIT_START].
+                                                         SEQUENCE=0=power-up/init:
+                                                           - RANKMASK selects participating ranks (should be all ranks with attached DRAM)
+                                                           - INIT_STATUS must equal RANKMASK
+                                                           - DDR_CKE* signals activated (if they weren't already active)
+                                                           - RDIMM register control words 0-15 will be written to RANKMASK-selected
+                                                               RDIMM's when LMC(0)_CONTROL[RDIMM_ENA]=1 and corresponding
+                                                               LMC*_DIMM_CTL[DIMM*_WMASK] bits are set. (Refer to LMC*_DIMM*_PARAMS and
+                                                               LMC*_DIMM_CTL descriptions below for more details.)
+                                                           - MR0, MR1, MR2, and MR3 will be written to selected ranks
+                                                         SEQUENCE=1=read-leveling:
+                                                           - RANKMASK selects the rank to be read-leveled
+                                                           - MR3 written to selected rank
+                                                         SEQUENCE=2=self-refresh entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - MR1 and MR2 will be written to selected ranks if SREF_WITH_DLL=1
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=3=self-refresh exit:
+                                                           - INIT_STATUS must be set to indicate participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                           - MR0, MR1, MR2, and MR3 will be written to participating ranks if SREF_WITH_DLL=1
+                                                         SEQUENCE=4=precharge power-down entry:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals de-activated
+                                                         SEQUENCE=5=precharge power-down exit:
+                                                           - INIT_STATUS selects participating ranks (should be all ranks with attached DRAM)
+                                                           - DDR_CKE* signals activated
+                                                         SEQUENCE=6=write-leveling:
+                                                           - RANKMASK selects the rank to be write-leveled
+                                                           - INIT_STATUS must indicate all ranks with attached DRAM
+                                                           - MR1 and MR2 written to INIT_STATUS-selected ranks
+                                                         SEQUENCE=7=illegal
+                                                         Precharge power-down entry and exit SEQUENCE's may also
+                                                         be automatically generated by the HW when IDLEPOWER!=0.
+                                                         Self-refresh entry SEQUENCE's may also be automatically
+                                                         generated by hardware upon a chip warm or soft reset
+                                                         sequence when LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set.
+                                                         LMC writes the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 CSR field values
+                                                         to the Mode registers in the DRAM parts (i.e. MR0, MR1, MR2, and MR3) as part of some of these sequences.
+                                                         Refer to the LMC*_MODEREG_PARAMS0 and LMC*_MODEREG_PARAMS1 descriptions for more details.
+                                                         If there are two consecutive power-up/init's without
+                                                         a DRESET assertion between them, LMC asserts DDR_CKE* as part of
+                                                         the first power-up/init, and continues to assert DDR_CKE*
+                                                         through the remainder of the first and the second power-up/init.
+                                                         If DDR_CKE* deactivation and reactivation is needed for
+                                                         a second power-up/init, a DRESET assertion is required
+                                                         between the first and the second. */
+	uint64_t ref_zqcs_int                 : 19; /**< Refresh & ZQCS interval represented in \#of 512 CK cycle
+                                                         increments. A Refresh sequence is triggered when bits
+                                                         [24:18] are equal to 0, and a ZQCS sequence is triggered
+                                                         when [36:18] are equal to 0.
+                                                         Program [24:18] to RND-DN(tREFI/clkPeriod/512)
+                                                         Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note
+                                                         that this value should always be greater than 32, to account for
+                                                         resistor calibration delays.
+                                                         000_00000000_00000000: RESERVED
+                                                         Max Refresh interval = 127 * 512           = 65024 CKs
+                                                         Max ZQCS interval    = (8*256*256-1) * 512 = 268434944 CKs ~ 335ms for a 800 MHz CK
+                                                         LMC*_CONFIG[INIT_STATUS] determines which ranks receive
+                                                         the REF / ZQCS. LMC does not send any refreshes / ZQCS's
+                                                         when LMC*_CONFIG[INIT_STATUS]=0. */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC*_OPS_CNT, LMC*_IFB_CNT, and LMC*_DCLK_CNT
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE CK cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter precharge power-down mode after the memory
+                                                         controller has been idle for 2^(2+IDLEPOWER) CK cycles.
+                                                         0=disabled.
+                                                         This field should only be programmed after initialization.
+                                                         LMC*_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL
+                                                         is disabled during the precharge power-down. */
+	uint64_t pbank_lsb                    : 4;  /**< DIMM address bit select
+                                                         Reverting to the explanation for ROW_LSB,
+                                                         PBank_LSB would be Row_LSB bit + \#rowbits + \#rankbits
+                                                         Decoding for pbank_lsb
+                                                              - 0000:DIMM = mem_adr[28]    / rank = mem_adr[27] (if RANK_ENA)
+                                                              - 0001:DIMM = mem_adr[29]    / rank = mem_adr[28]      "
+                                                              - 0010:DIMM = mem_adr[30]    / rank = mem_adr[29]      "
+                                                              - 0011:DIMM = mem_adr[31]    / rank = mem_adr[30]      "
+                                                              - 0100:DIMM = mem_adr[32]    / rank = mem_adr[31]      "
+                                                              - 0101:DIMM = mem_adr[33]    / rank = mem_adr[32]      "
+                                                              - 0110:DIMM = mem_adr[34]    / rank = mem_adr[33]      "
+                                                              - 0111:DIMM = 0              / rank = mem_adr[34]      "
+                                                              - 1000-1111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16]
+                                                         With rank_ena = 0, pbank_lsb = 2
+                                                         With rank_ena = 1, pbank_lsb = 3 */
+	uint64_t row_lsb                      : 3;  /**< Row Address bit select
+                                                         Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[34:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and DIMM)
+                                                         and that is a function of the following:
+                                                         1. Datapath Width (64)
+                                                         2. \# Banks (8)
+                                                         3. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         4. \# Row Bits of the memory part - spec'd indirectly
+                                                         5. \# Ranks in a DIMM - spec'd by RANK_ENA
+                                                         6. \# DIMM's in the system by the register below (PBANK_LSB).
+                                                         Decoding for row_lsb
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101: row_lsb = mem_adr[19]
+                                                              - 110: row_lsb = mem_adr[20]
+                                                              - 111: RESERVED
+                                                         For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+                                                         DDR3 parts, the column address width = 10, so with
+                                                         10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16] */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64]
+                                                         on writes, will contain the ECC code generated for
+                                                         the 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC*_FADR, and LMC*_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory sequence that is
+                                                         selected by LMC*_CONFIG[SEQUENCE].  This register is a
+                                                         oneshot and clears itself each time it is set. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t ref_zqcs_int                 : 19;
+	uint64_t sequence                     : 3;
+	uint64_t early_dqx                    : 1;
+	uint64_t sref_with_dll                : 1;
+	uint64_t rank_ena                     : 1;
+	uint64_t rankmask                     : 4;
+	uint64_t mirrmask                     : 4;
+	uint64_t init_status                  : 4;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_config cvmx_lmcx_config_t;
+
+/**
+ * cvmx_lmc#_control
+ *
+ * LMC_CONTROL = LMC Control
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+union cvmx_lmcx_control
+{
+	uint64_t u64;
+	struct cvmx_lmcx_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t rodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         RD cmd is delayed an additional CK cycle. */
+	uint64_t wodt_bprch                   : 1;  /**< When set, the turn-off time for the ODT pin during a
+                                                         WR cmd is delayed an additional CK cycle. */
+	uint64_t bprch                        : 2;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the default DDR_DQ/DQS drivers is delayed an additional BPRCH
+                                                         CK cycles.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = 3 CKs */
+	uint64_t ext_zqcs_dis                 : 1;  /**< Disable (external) auto-zqcs calibration
+                                                         When clear, LMC runs external ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t int_zqcs_dis                 : 1;  /**< Disable (internal) auto-zqcs calibration
+                                                         When clear, LMC runs internal ZQ calibration
+                                                         every LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t auto_dclkdis                 : 1;  /**< When 1, LMC will automatically shut off its internal
+                                                         clock to conserve power when there is no traffic. Note
+                                                         that this has no effect on the DDR3 PHY and pads clocks. */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                          bank[2:0]=address[9:7] ^ address[14:12]
+                                                         else
+                                                          bank[2:0]=address[9:7] */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         forcing reads to interrupt. */
+	uint64_t nxm_write_en                 : 1;  /**< NXM Write mode
+                                                         When clear, LMC discards writes to addresses that don't
+                                                         exist in the DRAM (as defined by LMC*_NXM configuration).
+                                                         When set, LMC completes writes to addresses that don't
+                                                         exist in the DRAM at an aliased address. */
+	uint64_t elev_prio_dis                : 1;  /**< Disable elevate priority logic.
+                                                         When set, writes are sent in
+                                                         regardless of priority information from L2C. */
+	uint64_t inorder_wr                   : 1;  /**< Send writes in order(regardless of priority) */
+	uint64_t inorder_rd                   : 1;  /**< Send reads in order (regardless of priority) */
+	uint64_t throttle_wr                  : 1;  /**< When set, use at most one IFB for writes */
+	uint64_t throttle_rd                  : 1;  /**< When set, use at most one IFB for reads */
+	uint64_t fprch2                       : 2;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
+                                                         00 = 0 CKs
+                                                         01 = 1 CKs
+                                                         10 = 2 CKs
+                                                         11 = RESERVED */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR3.
+                                                         This bit must be set whenever LMC*_MODEREG_PARAMS0[AL]!=0,
+                                                         and clear otherwise. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 CK cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC*_OPS_CNT, LMC*_IFB_CNT, and
+                                                         LMC*_DCLK_CNT registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require address and
+                                                         control bits to be registered in the controller. */
+#else
+	uint64_t rdimm_ena                    : 1;
+	uint64_t bwcnt                        : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t fprch2                       : 2;
+	uint64_t throttle_rd                  : 1;
+	uint64_t throttle_wr                  : 1;
+	uint64_t inorder_rd                   : 1;
+	uint64_t inorder_wr                   : 1;
+	uint64_t elev_prio_dis                : 1;
+	uint64_t nxm_write_en                 : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t auto_dclkdis                 : 1;
+	uint64_t int_zqcs_dis                 : 1;
+	uint64_t ext_zqcs_dis                 : 1;
+	uint64_t bprch                        : 2;
+	uint64_t wodt_bprch                   : 1;
+	uint64_t rodt_bprch                   : 1;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_lmcx_control_s            cn63xx;
+	struct cvmx_lmcx_control_s            cn63xxp1;
+};
+typedef union cvmx_lmcx_control cvmx_lmcx_control_t;
+
+/**
+ * cvmx_lmc#_ctl
+ *
+ * LMC_CTL = LMC Control
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+union cvmx_lmcx_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< Should be cleared to zero */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t pll_div2                     : 1;  /**< PLL Div2. */
+	uint64_t pll_bypass                   : 1;  /**< PLL Bypass. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< Reads as zero */
+	uint64_t inorder_mrf                  : 1;  /**< Always clear to zero */
+	uint64_t reserved_10_11               : 2;
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+	uint64_t qs_dic                       : 2;  /**< DDR2 Termination Resistor Setting
+                                                         A non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t reserved_10_11               : 2;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t pll_bypass                   : 1;
+	uint64_t pll_div2                     : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
+                                                         when compared to pass1 */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t pll_div2                     : 1;  /**< PLL Div2. */
+	uint64_t pll_bypass                   : 1;  /**< PLL Bypass. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< Reads as zero */
+	uint64_t inorder_mrf                  : 1;  /**< Always set to zero */
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t mode32b                      : 1;  /**< 32b data Path Mode
+                                                         Set to 1 if we use only 32 DQ pins
+                                                         0 for 16b DQ mode. */
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+	uint64_t qs_dic                       : 2;  /**< QS Drive Strength Control (DDR1):
+                                                         & DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 8 ODT
+                                                         pins based on what the masks (LMC_WODT_CTL1 & 2)
+                                                         are programmed to. LMC_DDR2_CTL->ODT_ENA
+                                                         enables Octeon to drive ODT pins for READS.
+                                                         LMC_RODT_CTL needs to be programmed based on
+                                                         the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t mode32b                      : 1;
+	uint64_t dreset                       : 1;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t pll_bypass                   : 1;
+	uint64_t pll_div2                     : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_ctl_cn30xx           cn31xx;
+	struct cvmx_lmcx_ctl_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
+                                                         when compared to pass1
+                                                         NOTE - This bit has NO effect in PASS1 */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t reserved_16_17               : 2;
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< When set, forces LMC_MWF (writes) into strict, in-order
+                                                         mode.  When clear, writes may be serviced out of order
+                                                         (optimized to keep multiple banks active).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use.
+                                                         NOTE: For PASS1, set as follows:
+                                                             DDR-I -> 1
+                                                             DDR-II -> 0
+                                                         For Pass2, this bit is RA0, write ignore (this feature
+                                                         is permanently disabled) */
+	uint64_t inorder_mrf                  : 1;  /**< When set, forces LMC_MRF (reads) into strict, in-order
+                                                         mode.  When clear, reads may be serviced out of order
+                                                         (optimized to keep multiple banks active).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use.
+                                                         NOTE: For PASS1, set as follows:
+                                                             DDR-I -> 1
+                                                             DDR-II -> 0
+                                                         For Pass2, this bit should be written ZERO for
+                                                         DDR I & II */
+	uint64_t set_zero                     : 1;  /**< Reserved. Always Set this Bit to Zero */
+	uint64_t mode128b                     : 1;  /**< 128b data Path Mode
+                                                         Set to 1 if we use all 128 DQ pins
+                                                         0 for 64b DQ mode. */
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+	uint64_t qs_dic                       : 2;  /**< QS Drive Strength Control (DDR1):
+                                                         & DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t mode128b                     : 1;
+	uint64_t set_zero                     : 1;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t reserved_16_17               : 2;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_lmcx_ctl_cn38xx           cn38xxp2;
+	struct cvmx_lmcx_ctl_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< Should be cleared to zero */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t reserved_17_17               : 1;
+	uint64_t pll_bypass                   : 1;  /**< PLL Bypass. */
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< Reads as zero */
+	uint64_t inorder_mrf                  : 1;  /**< Always clear to zero */
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t mode32b                      : 1;  /**< 32b data Path Mode
+                                                         Set to 1 if we use 32 DQ pins
+                                                         0 for 16b DQ mode. */
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+	uint64_t qs_dic                       : 2;  /**< DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the ODT
+                                                         pins based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t mode32b                      : 1;
+	uint64_t dreset                       : 1;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t pll_bypass                   : 1;
+	uint64_t reserved_17_17               : 1;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn50xx;
+	struct cvmx_lmcx_ctl_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< Always clear to zero */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t reserved_16_17               : 2;
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< Reads as zero */
+	uint64_t inorder_mrf                  : 1;  /**< Always set to zero */
+	uint64_t dreset                       : 1;  /**< MBZ
+                                                         THIS IS OBSOLETE.  Use LMC_DLL_CTL[DRESET] instead. */
+	uint64_t mode32b                      : 1;  /**< 32b data Path Mode
+                                                         Set to 1 if we use only 32 DQ pins
+                                                         0 for 64b DQ mode. */
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1.
+                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks
+                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
+	uint64_t qs_dic                       : 2;  /**< DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL0 & 1) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t mode32b                      : 1;
+	uint64_t dreset                       : 1;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t reserved_16_17               : 2;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn52xx;
+	struct cvmx_lmcx_ctl_cn52xx           cn52xxp1;
+	struct cvmx_lmcx_ctl_cn52xx           cn56xx;
+	struct cvmx_lmcx_ctl_cn52xx           cn56xxp1;
+	struct cvmx_lmcx_ctl_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 4;  /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+	uint64_t ddr__pctl                    : 4;  /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+	uint64_t slow_scf                     : 1;  /**< Should be cleared to zero */
+	uint64_t xor_bank                     : 1;  /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+	uint64_t max_write_batch              : 4;  /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+	uint64_t reserved_16_17               : 2;
+	uint64_t rdimm_ena                    : 1;  /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+	uint64_t r2r_slot                     : 1;  /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+	uint64_t inorder_mwf                  : 1;  /**< Reads as zero */
+	uint64_t inorder_mrf                  : 1;  /**< Always clear to zero */
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t mode128b                     : 1;  /**< 128b data Path Mode
+                                                         Set to 1 if we use all 128 DQ pins
+                                                         0 for 64b DQ mode. */
+	uint64_t fprch2                       : 1;  /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+	uint64_t bprch                        : 1;  /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+	uint64_t sil_lat                      : 2;  /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+	uint64_t tskw                         : 2;  /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+	uint64_t qs_dic                       : 2;  /**< DDR2 Termination Resistor Setting
+                                                         A non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+	uint64_t dic                          : 2;  /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+	uint64_t dic                          : 2;
+	uint64_t qs_dic                       : 2;
+	uint64_t tskw                         : 2;
+	uint64_t sil_lat                      : 2;
+	uint64_t bprch                        : 1;
+	uint64_t fprch2                       : 1;
+	uint64_t mode128b                     : 1;
+	uint64_t dreset                       : 1;
+	uint64_t inorder_mrf                  : 1;
+	uint64_t inorder_mwf                  : 1;
+	uint64_t r2r_slot                     : 1;
+	uint64_t rdimm_ena                    : 1;
+	uint64_t reserved_16_17               : 2;
+	uint64_t max_write_batch              : 4;
+	uint64_t xor_bank                     : 1;
+	uint64_t slow_scf                     : 1;
+	uint64_t ddr__pctl                    : 4;
+	uint64_t ddr__nctl                    : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn58xx;
+	struct cvmx_lmcx_ctl_cn58xx           cn58xxp1;
+};
+typedef union cvmx_lmcx_ctl cvmx_lmcx_ctl_t;
+
+/**
+ * cvmx_lmc#_ctl1
+ *
+ * LMC_CTL1 = LMC Control1
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+union cvmx_lmcx_ctl1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ctl1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter power-down mode after the memory controller has
+                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
+	uint64_t sequence                     : 3;  /**< Instruction sequence that is run after a 0->1 transition
+                                                         on LMC_MEM_CFG0[INIT_START].
+                                                         0=DDR2 power-up/init, 1=read-leveling
+                                                         2=self-refresh entry, 3=self-refresh exit,
+                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
+	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
+	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t data_layout                  : 2;  /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+	uint64_t data_layout                  : 2;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dcc_enable                   : 1;
+	uint64_t sil_mode                     : 1;
+	uint64_t sequence                     : 3;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_lmcx_ctl1_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t data_layout                  : 2;  /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+	uint64_t data_layout                  : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_ctl1_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
+	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t data_layout                  : 2;  /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+	uint64_t data_layout                  : 2;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t dcc_enable                   : 1;
+	uint64_t sil_mode                     : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn50xx;
+	struct cvmx_lmcx_ctl1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t ecc_adr                      : 1;  /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+	uint64_t forcewrite                   : 4;  /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+	uint64_t idlepower                    : 3;  /**< Enter power-down mode after the memory controller has
+                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
+	uint64_t sequence                     : 3;  /**< Instruction sequence that is run after a 0->1 transition
+                                                         on LMC_MEM_CFG0[INIT_START].
+                                                         0=DDR2 power-up/init, 1=read-leveling
+                                                         2=self-refresh entry, 3=self-refresh exit,
+                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
+	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
+	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t dcc_enable                   : 1;
+	uint64_t sil_mode                     : 1;
+	uint64_t sequence                     : 3;
+	uint64_t idlepower                    : 3;
+	uint64_t forcewrite                   : 4;
+	uint64_t ecc_adr                      : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} cn52xx;
+	struct cvmx_lmcx_ctl1_cn52xx          cn52xxp1;
+	struct cvmx_lmcx_ctl1_cn52xx          cn56xx;
+	struct cvmx_lmcx_ctl1_cn52xx          cn56xxp1;
+	struct cvmx_lmcx_ctl1_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sil_mode                     : 1;  /**< Read Silo mode.  0=envelope, 1=self-timed. */
+	uint64_t dcc_enable                   : 1;  /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t dcc_enable                   : 1;
+	uint64_t sil_mode                     : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn58xx;
+	struct cvmx_lmcx_ctl1_cn58xx          cn58xxp1;
+};
+typedef union cvmx_lmcx_ctl1 cvmx_lmcx_ctl1_t;
+
+/**
+ * cvmx_lmc#_dclk_cnt
+ *
+ * LMC_DCLK_CNT  = Performance Counters
+ *
+ */
+union cvmx_lmcx_dclk_cnt
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dclk_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dclkcnt                      : 64; /**< Performance Counter
+                                                         64-bit counter that increments every CK cycle */
+#else
+	uint64_t dclkcnt                      : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_dclk_cnt_s           cn63xx;
+	struct cvmx_lmcx_dclk_cnt_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_dclk_cnt cvmx_lmcx_dclk_cnt_t;
+
+/**
+ * cvmx_lmc#_dclk_cnt_hi
+ *
+ * LMC_DCLK_CNT_HI  = Performance Counters
+ *
+ */
+union cvmx_lmcx_dclk_cnt_hi
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dclk_cnt_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dclkcnt_hi                   : 32; /**< Performance Counter that counts dclks
+                                                         Upper 32-bits of a 64-bit counter. */
+#else
+	uint64_t dclkcnt_hi                   : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn30xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn31xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn38xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn38xxp2;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn50xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn52xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn52xxp1;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn56xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn56xxp1;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn58xx;
+	struct cvmx_lmcx_dclk_cnt_hi_s        cn58xxp1;
+};
+typedef union cvmx_lmcx_dclk_cnt_hi cvmx_lmcx_dclk_cnt_hi_t;
+
+/**
+ * cvmx_lmc#_dclk_cnt_lo
+ *
+ * LMC_DCLK_CNT_LO  = Performance Counters
+ *
+ */
+union cvmx_lmcx_dclk_cnt_lo
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dclk_cnt_lo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dclkcnt_lo                   : 32; /**< Performance Counter that counts dclks
+                                                         Lower 32-bits of a 64-bit counter. */
+#else
+	uint64_t dclkcnt_lo                   : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn30xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn31xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn38xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn38xxp2;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn50xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn52xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn52xxp1;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn56xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn56xxp1;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn58xx;
+	struct cvmx_lmcx_dclk_cnt_lo_s        cn58xxp1;
+};
+typedef union cvmx_lmcx_dclk_cnt_lo cvmx_lmcx_dclk_cnt_lo_t;
+
+/**
+ * cvmx_lmc#_dclk_ctl
+ *
+ * LMC_DCLK_CTL = LMC DCLK generation control
+ *
+ *
+ * Notes:
+ * This CSR is only relevant for LMC1. LMC0_DCLK_CTL is not used.
+ *
+ */
+union cvmx_lmcx_dclk_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dclk_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t off90_ena                    : 1;  /**< 0=use global DCLK (i.e. the PLL) directly for LMC1
+                                                         1=use the 90 degree DCLK DLL to offset LMC1 DCLK */
+	uint64_t dclk90_byp                   : 1;  /**< 0=90 degree DCLK DLL uses sampled delay from LMC0
+                                                         1=90 degree DCLK DLL uses DCLK90_VLU
+                                                         See DCLK90_VLU. */
+	uint64_t dclk90_ld                    : 1;  /**< The 90 degree DCLK DLL samples the delay setting
+                                                         from LMC0's DLL when this field transitions 0->1 */
+	uint64_t dclk90_vlu                   : 5;  /**< Manual open-loop delay setting.
+                                                         The LMC1 90 degree DCLK DLL uses DCLK90_VLU rather
+                                                         than the delay setting sampled from LMC0 when
+                                                         DCLK90_BYP=1. */
+#else
+	uint64_t dclk90_vlu                   : 5;
+	uint64_t dclk90_ld                    : 1;
+	uint64_t dclk90_byp                   : 1;
+	uint64_t off90_ena                    : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_lmcx_dclk_ctl_s           cn56xx;
+	struct cvmx_lmcx_dclk_ctl_s           cn56xxp1;
+};
+typedef union cvmx_lmcx_dclk_ctl cvmx_lmcx_dclk_ctl_t;
+
+/**
+ * cvmx_lmc#_ddr2_ctl
+ *
+ * LMC_DDR2_CTL = LMC DDR2 & DLL Control Register
+ *
+ */
+union cvmx_lmcx_ddr2_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ddr2_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bank8                        : 1;  /**< For 8 bank DDR2 parts
+                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
+                                                         wide).
+                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
+                                                         wide). */
+	uint64_t burst8                       : 1;  /**< 8-burst mode.
+                                                         1 - DDR data transfer happens in burst of 8
+                                                         0 - DDR data transfer happens in burst of 4
+                                                         BURST8 should be set when DDR2T is set
+                                                         to minimize the command bandwidth loss. */
+	uint64_t addlat                       : 3;  /**< Additional Latency for posted CAS
+                                                         When Posted CAS is on, this configures the additional
+                                                         latency. This should be set to
+                                                                1 .. LMC_MEM_CFG1[TRCD]-2
+                                                         (Note the implication that posted CAS should not
+                                                         be used when tRCD is two.) */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR2. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
+                                                         LMC_DCLK_CNT_* registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t twr                          : 3;  /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
+                                                          TYP=15ns
+                                                             - 000: RESERVED
+                                                             - 001: 2
+                                                             - 010: 3
+                                                             - 011: 4
+                                                             - 100: 5
+                                                             - 101: 6
+                                                             - 110: 7
+                                                             - 111: 8 */
+	uint64_t silo_hc                      : 1;  /**< Delays the read sample window by a Half Cycle. */
+	uint64_t ddr_eof                      : 4;  /**< Early Fill Counter Init.
+                                                         L2 needs to know a few cycle before a fill completes so
+                                                         it can get its Control pipe started (for better overall
+                                                         performance). This counter contains  an init value which
+                                                         is a function of Eclk/Dclk ratio to account for the
+                                                         asynchronous boundary between L2 cache and the DRAM
+                                                         controller. This init value will
+                                                         determine when to safely let the L2 know that a fill
+                                                         termination is coming up.
+                                                         Set DDR_EOF according to the following rule:
+                                                         eclkFreq/dclkFreq = dclkPeriod/eclkPeriod = RATIO
+                                                                RATIO < 6/6  -> illegal
+                                                         6/6 <= RATIO < 6/5  -> DDR_EOF=3
+                                                         6/5 <= RATIO < 6/4  -> DDR_EOF=3
+                                                         6/4 <= RATIO < 6/3  -> DDR_EOF=2
+                                                         6/3 <= RATIO < 6/2  -> DDR_EOF=1
+                                                         6/2 <= RATIO < 6/1  -> DDR_EOF=0
+                                                         6/1 <= RATIO        -> DDR_EOF=0 */
+	uint64_t tfaw                         : 5;  /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in DDR2 AND in
+                                                         8-bank parts.
+                                                             tFAW = 5'b0 in DDR2-4bank
+                                                             tFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                                      in DDR2-8bank */
+	uint64_t crip_mode                    : 1;  /**< Cripple Mode - When set, the LMC allows only
+                                                         1 inflight transaction (.vs. 8 in normal mode).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details.
+                                                         BURST8 should be set when DDR2T is set to minimize
+                                                         add/cmd loss. */
+	uint64_t odt_ena                      : 1;  /**< Enable Obsolete ODT on Reads
+                                                         Obsolete Read ODT wiggles DDR_ODT_* pins on reads.
+                                                         Should normally be cleared to zero.
+                                                         When this is on, the following fields must also be
+                                                         programmed:
+                                                             LMC_CTL->QS_DIC - programs the termination value
+                                                             LMC_RODT_CTL - programs the ODT I/O mask for Reads */
+	uint64_t qdll_ena                     : 1;  /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         DCLK init sequence will reset the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR.
+                                                         DRESET should be asserted before and for 10 usec
+                                                         following the 0->1 transition on QDLL_ENA. */
+	uint64_t dll90_vlu                    : 5;  /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+	uint64_t dll90_byp                    : 1;  /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+	uint64_t rdqs                         : 1;  /**< DDR2 RDQS mode. When set, configures memory subsystem to
+                                                         use unidirectional DQS pins. RDQS/DM - Rcv & DQS - Xmit */
+	uint64_t ddr2                         : 1;  /**< Should be set */
+#else
+	uint64_t ddr2                         : 1;
+	uint64_t rdqs                         : 1;
+	uint64_t dll90_byp                    : 1;
+	uint64_t dll90_vlu                    : 5;
+	uint64_t qdll_ena                     : 1;
+	uint64_t odt_ena                      : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t crip_mode                    : 1;
+	uint64_t tfaw                         : 5;
+	uint64_t ddr_eof                      : 4;
+	uint64_t silo_hc                      : 1;
+	uint64_t twr                          : 3;
+	uint64_t bwcnt                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t addlat                       : 3;
+	uint64_t burst8                       : 1;
+	uint64_t bank8                        : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ddr2_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bank8                        : 1;  /**< For 8 bank DDR2 parts
+                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
+                                                         wide).
+                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
+                                                         wide). */
+	uint64_t burst8                       : 1;  /**< 8-burst mode.
+                                                         1 - DDR data transfer happens in burst of 8
+                                                         0 - DDR data transfer happens in burst of 4
+                                                         BURST8 should be set when DDR2T is set to minimize
+                                                         add/cmd bandwidth loss. */
+	uint64_t addlat                       : 3;  /**< Additional Latency for posted CAS
+                                                         When Posted CAS is on, this configures the additional
+                                                         latency. This should be set to
+                                                                1 .. LMC_MEM_CFG1[TRCD]-2
+                                                         (Note the implication that posted CAS should not
+                                                         be used when tRCD is two.) */
+	uint64_t pocas                        : 1;  /**< Enable the Posted CAS feature of DDR2. */
+	uint64_t bwcnt                        : 1;  /**< Bus utilization counter Clear.
+                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
+                                                         LMC_DCLK_CNT_* registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+	uint64_t twr                          : 3;  /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
+                                                          TYP=15ns
+                                                             - 000: RESERVED
+                                                             - 001: 2
+                                                             - 010: 3
+                                                             - 011: 4
+                                                             - 100: 5
+                                                             - 101: 6
+                                                             - 110-111: RESERVED */
+	uint64_t silo_hc                      : 1;  /**< Delays the read sample window by a Half Cycle. */
+	uint64_t ddr_eof                      : 4;  /**< Early Fill Counter Init.
+                                                         L2 needs to know a few cycle before a fill completes so
+                                                         it can get its Control pipe started (for better overall
+                                                         performance). This counter contains  an init value which
+                                                         is a function of Eclk/Dclk ratio to account for the
+                                                         asynchronous boundary between L2 cache and the DRAM
+                                                         controller. This init value will
+                                                         determine when to safely let the L2 know that a fill
+                                                         termination is coming up.
+                                                         DDR_EOF = RNDUP (DCLK period/Eclk Period). If the ratio
+                                                         is above 3, set DDR_EOF to 3.
+                                                             DCLK/ECLK period         DDR_EOF
+                                                                Less than 1            1
+                                                                Less than 2            2
+                                                                More than 2            3 */
+	uint64_t tfaw                         : 5;  /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in
+                                                         8-bank parts.
+                                                             TFAW = 5'b0 for DDR2-4bank
+                                                             TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
+	uint64_t crip_mode                    : 1;  /**< Cripple Mode - When set, the LMC allows only
+                                                         1 inflight transaction (.vs. 8 in normal mode).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use. */
+	uint64_t ddr2t                        : 1;  /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details.
+                                                         BURST8 should be used when DDR2T is set to minimize
+                                                         add/cmd bandwidth loss. */
+	uint64_t odt_ena                      : 1;  /**< Enable ODT for DDR2 on Reads
+                                                         When this is on, the following fields must also be
+                                                         programmed:
+                                                             LMC_CTL->QS_DIC - programs the termination value
+                                                             LMC_RODT_CTL - programs the ODT I/O mask for writes
+                                                         Program as 0 for DDR1 mode and ODT needs to be off
+                                                         on Octeon Reads */
+	uint64_t qdll_ena                     : 1;  /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         erst deassertion will reset the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR. */
+	uint64_t dll90_vlu                    : 5;  /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+	uint64_t dll90_byp                    : 1;  /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t ddr2                         : 1;  /**< DDR2 Enable: When set, configures memory subsystem for
+                                                         DDR-II SDRAMs. */
+#else
+	uint64_t ddr2                         : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t dll90_byp                    : 1;
+	uint64_t dll90_vlu                    : 5;
+	uint64_t qdll_ena                     : 1;
+	uint64_t odt_ena                      : 1;
+	uint64_t ddr2t                        : 1;
+	uint64_t crip_mode                    : 1;
+	uint64_t tfaw                         : 5;
+	uint64_t ddr_eof                      : 4;
+	uint64_t silo_hc                      : 1;
+	uint64_t twr                          : 3;
+	uint64_t bwcnt                        : 1;
+	uint64_t pocas                        : 1;
+	uint64_t addlat                       : 3;
+	uint64_t burst8                       : 1;
+	uint64_t bank8                        : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_ddr2_ctl_cn30xx      cn31xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn38xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn38xxp2;
+	struct cvmx_lmcx_ddr2_ctl_s           cn50xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn52xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn52xxp1;
+	struct cvmx_lmcx_ddr2_ctl_s           cn56xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn56xxp1;
+	struct cvmx_lmcx_ddr2_ctl_s           cn58xx;
+	struct cvmx_lmcx_ddr2_ctl_s           cn58xxp1;
+};
+typedef union cvmx_lmcx_ddr2_ctl cvmx_lmcx_ddr2_ctl_t;
+
+/**
+ * cvmx_lmc#_ddr_pll_ctl
+ *
+ * LMC_DDR_PLL_CTL = LMC DDR PLL control
+ *
+ *
+ * Notes:
+ * DDR PLL Bringup sequence:
+ * 1.  Write CLKF, DDR_PS_EN, DFM_PS_EN, DIFFAMP, CPS, CPB.
+ *     If test mode is going to be activated, then also write jtg__ddr_pll_tm_en1, jtg__ddr_pll_tm_en2, jtg__ddr_pll_tm_en3,
+ *     jtg__ddr_pll_tm_en4, jtg__dfa_pll_tm_en1, jtg__dfa_pll_tm_en2, jtg__dfa_pll_tm_en3, jtg__dfa_pll_tm_en4, JTAG_TEST_MODE
+ * 2.  Wait 128 ref clock cycles (7680 rclk cycles)
+ * 3.  Write 1 to RESET_N
+ * 4.  Wait 1152 ref clocks (1152*16 rclk cycles)
+ * 5.  Write 0 to  DDR_DIV_RESET and DFM_DIV_RESET
+ * 6.  Wait 10 ref clock cycles (160 rclk cycles) before bringing up the DDR interface
+ *     If test mode is going to be activated, wait an additional 8191 ref clocks (8191*16 rclk cycles) to allow PLL
+ *     clock alignment
+ */
+union cvmx_lmcx_ddr_pll_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ddr_pll_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t jtg_test_mode                : 1;  /**< JTAG Test Mode
+                                                         Clock alignment between DCLK & REFCLK as well as FCLK &
+                                                         REFCLK can only be performed after the ddr_pll_divider_reset
+                                                         is deasserted. SW need to wait atleast 10 reference clock
+                                                         cycles after deasserting pll_divider_reset before asserting
+                                                         LMC(0)_DDR_PLL_CTL[JTG_TEST_MODE]. During alignment (which can
+                                                         take upto 160 microseconds) DCLK and FCLK can exhibit some
+                                                         high frequency pulses. Therefore, all bring up activities in
+                                                         that clock domain need to be delayed (when the chip operates
+                                                         in jtg_test_mode) by about 160 microseconds to ensure that
+                                                         lock is achieved. */
+	uint64_t dfm_div_reset                : 1;  /**< DFM postscalar divider reset */
+	uint64_t dfm_ps_en                    : 3;  /**< DFM postscalar divide ratio
+                                                         Determines the DFM CK speed.
+                                                         0x0 : Divide LMC+DFM PLL output by 1
+                                                         0x1 : Divide LMC+DFM PLL output by 2
+                                                         0x2 : Divide LMC+DFM PLL output by 3
+                                                         0x3 : Divide LMC+DFM PLL output by 4
+                                                         0x4 : Divide LMC+DFM PLL output by 6
+                                                         0x5 : Divide LMC+DFM PLL output by 8
+                                                         0x6 : Divide LMC+DFM PLL output by 12
+                                                         0x7 : Divide LMC+DFM PLL output by 12
+                                                         DFM_PS_EN is not used when DFM_DIV_RESET = 1 */
+	uint64_t ddr_div_reset                : 1;  /**< DDR postscalar divider reset */
+	uint64_t ddr_ps_en                    : 3;  /**< DDR postscalar divide ratio
+                                                         Determines the LMC CK speed.
+                                                         0x0 : Divide LMC+DFM PLL output by 1
+                                                         0x1 : Divide LMC+DFM PLL output by 2
+                                                         0x2 : Divide LMC+DFM PLL output by 3
+                                                         0x3 : Divide LMC+DFM PLL output by 4
+                                                         0x4 : Divide LMC+DFM PLL output by 6
+                                                         0x5 : Divide LMC+DFM PLL output by 8
+                                                         0x6 : Divide LMC+DFM PLL output by 12
+                                                         0x7 : Divide LMC+DFM PLL output by 12
+                                                         DDR_PS_EN is not used when DDR_DIV_RESET = 1 */
+	uint64_t diffamp                      : 4;  /**< PLL diffamp input transconductance */
+	uint64_t cps                          : 3;  /**< PLL charge-pump current */
+	uint64_t cpb                          : 3;  /**< PLL charge-pump current */
+	uint64_t reset_n                      : 1;  /**< PLL reset */
+	uint64_t clkf                         : 7;  /**< Multiply reference by CLKF
+                                                         32 <= CLKF <= 64
+                                                         LMC+DFM PLL frequency = 50 * CLKF
+                                                         min = 1.6 GHz, max = 3.2 GHz */
+#else
+	uint64_t clkf                         : 7;
+	uint64_t reset_n                      : 1;
+	uint64_t cpb                          : 3;
+	uint64_t cps                          : 3;
+	uint64_t diffamp                      : 4;
+	uint64_t ddr_ps_en                    : 3;
+	uint64_t ddr_div_reset                : 1;
+	uint64_t dfm_ps_en                    : 3;
+	uint64_t dfm_div_reset                : 1;
+	uint64_t jtg_test_mode                : 1;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} s;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn63xx;
+	struct cvmx_lmcx_ddr_pll_ctl_s        cn63xxp1;
+};
+typedef union cvmx_lmcx_ddr_pll_ctl cvmx_lmcx_ddr_pll_ctl_t;
+
+/**
+ * cvmx_lmc#_delay_cfg
+ *
+ * LMC_DELAY_CFG = Open-loop delay line settings
+ *
+ *
+ * Notes:
+ * The DQ bits add OUTGOING delay only to dq, dqs_[p,n], cb, cbs_[p,n], dqm.  Delay is approximately
+ * 50-80ps per setting depending on process/voltage.  There is no need to add incoming delay since by
+ * default all strobe bits are delayed internally by 90 degrees (as was always the case in previous
+ * passes and past chips.
+ *
+ * The CMD add delay to all command bits DDR_RAS, DDR_CAS, DDR_A<15:0>, DDR_BA<2:0>, DDR_n_CS<1:0>_L,
+ * DDR_WE, DDR_CKE and DDR_ODT_<7:0>. Again, delay is 50-80ps per tap.
+ *
+ * The CLK bits add delay to all clock signals DDR_CK_<5:0>_P and DDR_CK_<5:0>_N.  Again, delay is
+ * 50-80ps per tap.
+ *
+ * The usage scenario is the following: There is too much delay on command signals and setup on command
+ * is not met. The user can then delay the clock until setup is met.
+ *
+ * At the same time though, dq/dqs should be delayed because there is also a DDR spec tying dqs with
+ * clock. If clock is too much delayed with respect to dqs, writes will start to fail.
+ *
+ * This scheme should eliminate the board need of adding routing delay to clock signals to make high
+ * frequencies work.
+ */
+union cvmx_lmcx_delay_cfg
+{
+	uint64_t u64;
+	struct cvmx_lmcx_delay_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t dq                           : 5;  /**< Setting for DQ  delay line */
+	uint64_t cmd                          : 5;  /**< Setting for CMD delay line */
+	uint64_t clk                          : 5;  /**< Setting for CLK delay line */
+#else
+	uint64_t clk                          : 5;
+	uint64_t cmd                          : 5;
+	uint64_t dq                           : 5;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_lmcx_delay_cfg_s          cn30xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t dq                           : 4;  /**< Setting for DQ  delay line */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t cmd                          : 4;  /**< Setting for CMD delay line */
+	uint64_t reserved_4_4                 : 1;
+	uint64_t clk                          : 4;  /**< Setting for CLK delay line */
+#else
+	uint64_t clk                          : 4;
+	uint64_t reserved_4_4                 : 1;
+	uint64_t cmd                          : 4;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t dq                           : 4;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn38xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn50xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn52xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn52xxp1;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn56xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn56xxp1;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn58xx;
+	struct cvmx_lmcx_delay_cfg_cn38xx     cn58xxp1;
+};
+typedef union cvmx_lmcx_delay_cfg cvmx_lmcx_delay_cfg_t;
+
+/**
+ * cvmx_lmc#_dimm#_params
+ *
+ * LMC_DIMMX_PARAMS = LMC DIMMX Params
+ * This register contains values to be programmed into each control word in the corresponding (registered) DIMM. The control words allow
+ * optimization of the device properties for different raw card designs.
+ *
+ * Notes:
+ * LMC only uses this CSR when LMC*_CONTROL[RDIMM_ENA]=1. During a power-up/init sequence, LMC writes
+ * these fields into the control words in the JEDEC standard SSTE32882 registering clock driver on an
+ * RDIMM when corresponding LMC*_DIMM_CTL[DIMM*_WMASK] bits are set.
+ */
+union cvmx_lmcx_dimmx_params
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dimmx_params_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rc15                         : 4;  /**< RC15, Reserved */
+	uint64_t rc14                         : 4;  /**< RC14, Reserved */
+	uint64_t rc13                         : 4;  /**< RC13, Reserved */
+	uint64_t rc12                         : 4;  /**< RC12, Reserved */
+	uint64_t rc11                         : 4;  /**< RC11, Encoding for RDIMM Operating VDD */
+	uint64_t rc10                         : 4;  /**< RC10, Encoding for RDIMM Operating Speed */
+	uint64_t rc9                          : 4;  /**< RC9 , Power Savings Settings Control Word */
+	uint64_t rc8                          : 4;  /**< RC8 , Additional IBT Settings Control Word */
+	uint64_t rc7                          : 4;  /**< RC7 , Reserved */
+	uint64_t rc6                          : 4;  /**< RC6 , Reserved */
+	uint64_t rc5                          : 4;  /**< RC5 , CK Driver Characterstics Control Word */
+	uint64_t rc4                          : 4;  /**< RC4 , Control Signals Driver Characteristics Control Word */
+	uint64_t rc3                          : 4;  /**< RC3 , CA Signals Driver Characterstics Control Word */
+	uint64_t rc2                          : 4;  /**< RC2 , Timing Control Word */
+	uint64_t rc1                          : 4;  /**< RC1 , Clock Driver Enable Control Word */
+	uint64_t rc0                          : 4;  /**< RC0 , Global Features Control Word */
+#else
+	uint64_t rc0                          : 4;
+	uint64_t rc1                          : 4;
+	uint64_t rc2                          : 4;
+	uint64_t rc3                          : 4;
+	uint64_t rc4                          : 4;
+	uint64_t rc5                          : 4;
+	uint64_t rc6                          : 4;
+	uint64_t rc7                          : 4;
+	uint64_t rc8                          : 4;
+	uint64_t rc9                          : 4;
+	uint64_t rc10                         : 4;
+	uint64_t rc11                         : 4;
+	uint64_t rc12                         : 4;
+	uint64_t rc13                         : 4;
+	uint64_t rc14                         : 4;
+	uint64_t rc15                         : 4;
+#endif
+	} s;
+	struct cvmx_lmcx_dimmx_params_s       cn63xx;
+	struct cvmx_lmcx_dimmx_params_s       cn63xxp1;
+};
+typedef union cvmx_lmcx_dimmx_params cvmx_lmcx_dimmx_params_t;
+
+/**
+ * cvmx_lmc#_dimm_ctl
+ *
+ * LMC_DIMM_CTL = LMC DIMM Control
+ *
+ *
+ * Notes:
+ * This CSR is only used when LMC*_CONTROL[RDIMM_ENA]=1. During a power-up/init sequence, this CSR
+ * controls LMC's writes to the control words in the JEDEC standard SSTE32882 registering clock driver
+ * on an RDIMM.
+ */
+union cvmx_lmcx_dimm_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dimm_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t parity                       : 1;  /**< Parity */
+	uint64_t tcws                         : 13; /**< LMC waits for this time period before and after a RDIMM
+                                                         Control Word Access during a power-up/init SEQUENCE.
+                                                         TCWS is in multiples of 8 CK cycles.
+                                                         Set TCWS (CSR field) = RNDUP[tcws(ns)/(8*tCYC(ns))],
+                                                         where tCWS is the desired time (ns), and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=0x4e0 (equivalent to 15us) when changing
+                                                         clock timing (RC2.DBA1, RC6.DA4, RC10.DA3, RC10.DA4,
+                                                         RC11.DA3, and RC11.DA4)
+                                                         TYP=0x8, otherwise
+                                                         0x0 = Reserved */
+	uint64_t dimm1_wmask                  : 16; /**< DIMM1 Write Mask
+                                                         if (DIMM1_WMASK[n] = 1)
+                                                             Write DIMM1.RCn */
+	uint64_t dimm0_wmask                  : 16; /**< DIMM0 Write Mask
+                                                         if (DIMM0_WMASK[n] = 1)
+                                                             Write DIMM0.RCn */
+#else
+	uint64_t dimm0_wmask                  : 16;
+	uint64_t dimm1_wmask                  : 16;
+	uint64_t tcws                         : 13;
+	uint64_t parity                       : 1;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} s;
+	struct cvmx_lmcx_dimm_ctl_s           cn63xx;
+	struct cvmx_lmcx_dimm_ctl_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_dimm_ctl cvmx_lmcx_dimm_ctl_t;
+
+/**
+ * cvmx_lmc#_dll_ctl
+ *
+ * LMC_DLL_CTL = LMC DLL control and DCLK reset
+ *
+ */
+union cvmx_lmcx_dll_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dll_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t dll90_byp                    : 1;  /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+	uint64_t dll90_ena                    : 1;  /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         DCLK init sequence resets the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR. QDLL_ENA
+                                                         must not transition 1->0 outside of a DRESET sequence
+                                                         (i.e. it must remain 1 until the next DRESET).
+                                                         DRESET should be asserted before and for 10 usec
+                                                         following the 0->1 transition on QDLL_ENA. */
+	uint64_t dll90_vlu                    : 5;  /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+#else
+	uint64_t dll90_vlu                    : 5;
+	uint64_t dll90_ena                    : 1;
+	uint64_t dll90_byp                    : 1;
+	uint64_t dreset                       : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_lmcx_dll_ctl_s            cn52xx;
+	struct cvmx_lmcx_dll_ctl_s            cn52xxp1;
+	struct cvmx_lmcx_dll_ctl_s            cn56xx;
+	struct cvmx_lmcx_dll_ctl_s            cn56xxp1;
+};
+typedef union cvmx_lmcx_dll_ctl cvmx_lmcx_dll_ctl_t;
+
+/**
+ * cvmx_lmc#_dll_ctl2
+ *
+ * LMC_DLL_CTL2 = LMC (Octeon) DLL control and DCLK reset
+ *
+ *
+ * Notes:
+ * DLL Bringup sequence:
+ * 1. If not done already, set LMC*_DLL_CTL2 = 0, except when LMC*_DLL_CTL2[DRESET] = 1.
+ * 2. Write 1 to LMC*_DLL_CTL2[DLL_BRINGUP]
+ * 3. Wait for 10 CK cycles, then write 1 to LMC*_DLL_CTL2[QUAD_DLL_ENA]. It may not be feasible to count 10 CK cycles, but the
+ *    idea is to configure the delay line into DLL mode by asserting DLL_BRING_UP earlier than [QUAD_DLL_ENA], even if it is one
+ *    cycle early. LMC*_DLL_CTL2[QUAD_DLL_ENA] must not change after this point without restarting the LMC and/or DRESET initialization
+ *    sequence.
+ * 4. Read L2D_BST0 and wait for the result. (L2D_BST0 is subject to change depending on how it called in o63. It is still ok to go
+ *    without step 4, since step 5 has enough time)
+ * 5. Wait 10 us.
+ * 6. Write 0 to LMC*_DLL_CTL2[DLL_BRINGUP]. LMC*_DLL_CTL2[DLL_BRINGUP] must not change after this point without restarting the LMC
+ *    and/or DRESET initialization sequence.
+ * 7. Read L2D_BST0 and wait for the result. (same as step 4, but the idea here is the wait some time before going to step 8, even it
+ *    is one cycle is fine)
+ * 8. Write 0 to LMC*_DLL_CTL2[DRESET].  LMC*_DLL_CTL2[DRESET] must not change after this point without restarting the LMC and/or
+ *    DRESET initialization sequence.
+ */
+union cvmx_lmcx_dll_ctl2
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dll_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t dll_bringup                  : 1;  /**< DLL Bringup */
+	uint64_t dreset                       : 1;  /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+	uint64_t quad_dll_ena                 : 1;  /**< DLL Enable */
+	uint64_t byp_sel                      : 4;  /**< Bypass select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t byp_setting                  : 8;  /**< Bypass setting
+                                                         DDR3-1600: 00100010
+                                                         DDR3-1333: 00110010
+                                                         DDR3-1066: 01001011
+                                                         DDR3-800 : 01110101
+                                                         DDR3-667 : 10010110
+                                                         DDR3-600 : 10101100 */
+#else
+	uint64_t byp_setting                  : 8;
+	uint64_t byp_sel                      : 4;
+	uint64_t quad_dll_ena                 : 1;
+	uint64_t dreset                       : 1;
+	uint64_t dll_bringup                  : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_lmcx_dll_ctl2_s           cn63xx;
+	struct cvmx_lmcx_dll_ctl2_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_dll_ctl2 cvmx_lmcx_dll_ctl2_t;
+
+/**
+ * cvmx_lmc#_dll_ctl3
+ *
+ * LMC_DLL_CTL3 = LMC DLL control and DCLK reset
+ *
+ */
+union cvmx_lmcx_dll_ctl3
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dll_ctl3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t dll_fast                     : 1;  /**< DLL lock
+                                                         0 = DLL locked */
+	uint64_t dll90_setting                : 8;  /**< Encoded DLL settings. Works in conjuction with
+                                                         DLL90_BYTE_SEL */
+	uint64_t fine_tune_mode               : 1;  /**< DLL Fine Tune Mode
+                                                         0 = disabled
+                                                         1 = enable.
+                                                         When enabled, calibrate internal PHY DLL every
+                                                         LMC*_CONFIG[REF_ZQCS_INT] CK cycles. */
+	uint64_t dll_mode                     : 1;  /**< DLL Mode */
+	uint64_t dll90_byte_sel               : 4;  /**< Observe DLL settings for selected byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         0000,1010-1111 : Reserved */
+	uint64_t offset_ena                   : 1;  /**< Offset enable
+                                                         0 = disable
+                                                         1 = enable */
+	uint64_t load_offset                  : 1;  /**< Load offset
+                                                         0 : disable
+                                                         1 : load (generates a 1 cycle pulse to the PHY)
+                                                         This register is oneshot and clears itself each time
+                                                         it is set */
+	uint64_t mode_sel                     : 2;  /**< Mode select
+                                                         00 : reset
+                                                         01 : write
+                                                         10 : read
+                                                         11 : write & read */
+	uint64_t byte_sel                     : 4;  /**< Byte select
+                                                         0000 : no byte
+                                                         0001 : byte 0
+                                                         - ...
+                                                         1001 : byte 8
+                                                         1010 : all bytes
+                                                         1011-1111 : Reserved */
+	uint64_t offset                       : 6;  /**< Write/read offset setting
+                                                         [4:0] : offset
+                                                         [5]   : 0 = increment, 1 = decrement
+                                                         Not a 2's complement value */
+#else
+	uint64_t offset                       : 6;
+	uint64_t byte_sel                     : 4;
+	uint64_t mode_sel                     : 2;
+	uint64_t load_offset                  : 1;
+	uint64_t offset_ena                   : 1;
+	uint64_t dll90_byte_sel               : 4;
+	uint64_t dll_mode                     : 1;
+	uint64_t fine_tune_mode               : 1;
+	uint64_t dll90_setting                : 8;
+	uint64_t dll_fast                     : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_lmcx_dll_ctl3_s           cn63xx;
+	struct cvmx_lmcx_dll_ctl3_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_dll_ctl3 cvmx_lmcx_dll_ctl3_t;
+
+/**
+ * cvmx_lmc#_dual_memcfg
+ *
+ * LMC_DUAL_MEMCFG = LMC Dual Memory Configuration Register
+ *
+ * This register controls certain parameters of Dual Memory Configuration
+ *
+ * Notes:
+ * This register enables the design to have two, separate memory configurations, selected dynamically
+ * by the reference address.  Note however, that both configurations share
+ * LMC*_CONTROL[XOR_BANK], LMC*_CONFIG[PBANK_LSB], LMC*_CONFIG[RANK_ENA], and all timing parameters.
+ * In this description, "config0" refers to the normal memory configuration that is defined by the
+ * LMC*_CONFIG[ROW_LSB] parameters and "config1" refers to the dual (or second)
+ * memory configuration that is defined by this register.
+ *
+ * Enable mask to chip select mapping is shown below:
+ *   CS_MASK[3] -> DIMM1_CS_<1>
+ *   CS_MASK[2] -> DIMM1_CS_<0>
+ *
+ *   CS_MASK[1] -> DIMM0_CS_<1>
+ *   CS_MASK[0] -> DIMM0_CS_<0>
+ *
+ *  DIMM n uses the pair of chip selects DIMMn_CS_<1:0>.
+ *
+ *  Programming restrictions for CS_MASK:
+ *    when LMC*_CONFIG[RANK_ENA] == 0, CS_MASK[2n + 1] = CS_MASK[2n]
+ */
+union cvmx_lmcx_dual_memcfg
+{
+	uint64_t u64;
+	struct cvmx_lmcx_dual_memcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t bank8                        : 1;  /**< See LMC_DDR2_CTL[BANK8] */
+	uint64_t row_lsb                      : 3;  /**< See LMC*_CONFIG[ROW_LSB] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t cs_mask                      : 8;  /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  Each reference address will assert one of
+                                                         the chip selects.  If that chip select has its
+                                                         corresponding CS_MASK bit set, then the "config1"
+                                                         parameters are used, otherwise the "config0" parameters
+                                                         are used.  See additional notes below.
+                                                         [7:4] */
+#else
+	uint64_t cs_mask                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t row_lsb                      : 3;
+	uint64_t bank8                        : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_lmcx_dual_memcfg_s        cn50xx;
+	struct cvmx_lmcx_dual_memcfg_s        cn52xx;
+	struct cvmx_lmcx_dual_memcfg_s        cn52xxp1;
+	struct cvmx_lmcx_dual_memcfg_s        cn56xx;
+	struct cvmx_lmcx_dual_memcfg_s        cn56xxp1;
+	struct cvmx_lmcx_dual_memcfg_s        cn58xx;
+	struct cvmx_lmcx_dual_memcfg_s        cn58xxp1;
+	struct cvmx_lmcx_dual_memcfg_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t row_lsb                      : 3;  /**< See LMC*_CONFIG[ROW_LSB] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t cs_mask                      : 8;  /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  Each reference address will assert one of
+                                                         the chip selects.  If that chip select has its
+                                                         corresponding CS_MASK bit set, then the "config1"
+                                                         parameters are used, otherwise the "config0" parameters
+                                                         are used.  See additional notes below.
+                                                         [7:4] */
+#else
+	uint64_t cs_mask                      : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t row_lsb                      : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} cn63xx;
+	struct cvmx_lmcx_dual_memcfg_cn63xx   cn63xxp1;
+};
+typedef union cvmx_lmcx_dual_memcfg cvmx_lmcx_dual_memcfg_t;
+
+/**
+ * cvmx_lmc#_ecc_synd
+ *
+ * LMC_ECC_SYND = MRD ECC Syndromes
+ *
+ */
+union cvmx_lmcx_ecc_synd
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ecc_synd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t mrdsyn3                      : 8;  /**< MRD ECC Syndrome Quad3
+                                                         MRDSYN3 corresponds to DQ[63:0]_c1_p1
+                                                           where _cC_pP denotes cycle C and phase P */
+	uint64_t mrdsyn2                      : 8;  /**< MRD ECC Syndrome Quad2
+                                                         MRDSYN2 corresponds to DQ[63:0]_c1_p0
+                                                           where _cC_pP denotes cycle C and phase P */
+	uint64_t mrdsyn1                      : 8;  /**< MRD ECC Syndrome Quad1
+                                                         MRDSYN1 corresponds to DQ[63:0]_c0_p1
+                                                           where _cC_pP denotes cycle C and phase P */
+	uint64_t mrdsyn0                      : 8;  /**< MRD ECC Syndrome Quad0
+                                                         MRDSYN0 corresponds to DQ[63:0]_c0_p0
+                                                           where _cC_pP denotes cycle C and phase P */
+#else
+	uint64_t mrdsyn0                      : 8;
+	uint64_t mrdsyn1                      : 8;
+	uint64_t mrdsyn2                      : 8;
+	uint64_t mrdsyn3                      : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ecc_synd_s           cn30xx;
+	struct cvmx_lmcx_ecc_synd_s           cn31xx;
+	struct cvmx_lmcx_ecc_synd_s           cn38xx;
+	struct cvmx_lmcx_ecc_synd_s           cn38xxp2;
+	struct cvmx_lmcx_ecc_synd_s           cn50xx;
+	struct cvmx_lmcx_ecc_synd_s           cn52xx;
+	struct cvmx_lmcx_ecc_synd_s           cn52xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cn56xx;
+	struct cvmx_lmcx_ecc_synd_s           cn56xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cn58xx;
+	struct cvmx_lmcx_ecc_synd_s           cn58xxp1;
+	struct cvmx_lmcx_ecc_synd_s           cn63xx;
+	struct cvmx_lmcx_ecc_synd_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_ecc_synd cvmx_lmcx_ecc_synd_t;
+
+/**
+ * cvmx_lmc#_fadr
+ *
+ * LMC_FADR = LMC Failing Address Register (SEC/DED/NXM)
+ *
+ * This register only captures the first transaction with ecc/nxm errors. A DED/NXM error can
+ * over-write this register with its failing addresses if the first error was a SEC. If you write
+ * LMC*_CONFIG->SEC_ERR/DED_ERR/NXM_ERR then it will clear the error bits and capture the
+ * next failing address.
+ *
+ * If FDIMM is 2 that means the error is in the higher bits DIMM.
+ */
+union cvmx_lmcx_fadr
+{
+	uint64_t u64;
+	struct cvmx_lmcx_fadr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_fadr_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t fdimm                        : 2;  /**< Failing DIMM# */
+	uint64_t fbunk                        : 1;  /**< Failing Rank */
+	uint64_t fbank                        : 3;  /**< Failing Bank[2:0] */
+	uint64_t frow                         : 14; /**< Failing Row Address[13:0] */
+	uint64_t fcol                         : 12; /**< Failing Column Start Address[11:0]
+                                                         Represents the Failing read's starting column address
+                                                         (and not the exact column address in which the SEC/DED
+                                                         was detected) */
+#else
+	uint64_t fcol                         : 12;
+	uint64_t frow                         : 14;
+	uint64_t fbank                        : 3;
+	uint64_t fbunk                        : 1;
+	uint64_t fdimm                        : 2;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn31xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn38xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn38xxp2;
+	struct cvmx_lmcx_fadr_cn30xx          cn50xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn52xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn52xxp1;
+	struct cvmx_lmcx_fadr_cn30xx          cn56xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn56xxp1;
+	struct cvmx_lmcx_fadr_cn30xx          cn58xx;
+	struct cvmx_lmcx_fadr_cn30xx          cn58xxp1;
+	struct cvmx_lmcx_fadr_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t fdimm                        : 2;  /**< Failing DIMM# */
+	uint64_t fbunk                        : 1;  /**< Failing Rank */
+	uint64_t fbank                        : 3;  /**< Failing Bank[2:0] */
+	uint64_t frow                         : 16; /**< Failing Row Address[15:0] */
+	uint64_t fcol                         : 14; /**< Failing Column Address[13:0]
+                                                         Technically, represents the address of the 128b data
+                                                         that had an ecc error, i.e., fcol[0] is always 0. Can
+                                                         be used in conjuction with LMC*_CONFIG[DED_ERR] to
+                                                         isolate the 64b chunk of data in error */
+#else
+	uint64_t fcol                         : 14;
+	uint64_t frow                         : 16;
+	uint64_t fbank                        : 3;
+	uint64_t fbunk                        : 1;
+	uint64_t fdimm                        : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn63xx;
+	struct cvmx_lmcx_fadr_cn63xx          cn63xxp1;
+};
+typedef union cvmx_lmcx_fadr cvmx_lmcx_fadr_t;
+
+/**
+ * cvmx_lmc#_ifb_cnt
+ *
+ * LMC_IFB_CNT  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ifb_cnt
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ifb_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t ifbcnt                       : 64; /**< Performance Counter
+                                                         64-bit counter that increments every
+                                                         CK cycle there is something in the in-flight buffer. */
+#else
+	uint64_t ifbcnt                       : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_ifb_cnt_s            cn63xx;
+	struct cvmx_lmcx_ifb_cnt_s            cn63xxp1;
+};
+typedef union cvmx_lmcx_ifb_cnt cvmx_lmcx_ifb_cnt_t;
+
+/**
+ * cvmx_lmc#_ifb_cnt_hi
+ *
+ * LMC_IFB_CNT_HI  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ifb_cnt_hi
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ifb_cnt_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ifbcnt_hi                    : 32; /**< Performance Counter to measure Bus Utilization
+                                                         Upper 32-bits of 64-bit counter that increments every
+                                                         cycle there is something in the in-flight buffer. */
+#else
+	uint64_t ifbcnt_hi                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn30xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn31xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn38xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn38xxp2;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn50xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn52xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn52xxp1;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn56xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn56xxp1;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn58xx;
+	struct cvmx_lmcx_ifb_cnt_hi_s         cn58xxp1;
+};
+typedef union cvmx_lmcx_ifb_cnt_hi cvmx_lmcx_ifb_cnt_hi_t;
+
+/**
+ * cvmx_lmc#_ifb_cnt_lo
+ *
+ * LMC_IFB_CNT_LO  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ifb_cnt_lo
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ifb_cnt_lo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ifbcnt_lo                    : 32; /**< Performance Counter
+                                                         Low 32-bits of 64-bit counter that increments every
+                                                         cycle there is something in the in-flight buffer. */
+#else
+	uint64_t ifbcnt_lo                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn30xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn31xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn38xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn38xxp2;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn50xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn52xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn52xxp1;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn56xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn56xxp1;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn58xx;
+	struct cvmx_lmcx_ifb_cnt_lo_s         cn58xxp1;
+};
+typedef union cvmx_lmcx_ifb_cnt_lo cvmx_lmcx_ifb_cnt_lo_t;
+
+/**
+ * cvmx_lmc#_int
+ *
+ * LMC_INT = LMC Interrupt Register
+ *
+ */
+union cvmx_lmcx_int
+{
+	uint64_t u64;
+	struct cvmx_lmcx_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t ded_err                      : 4;  /**< Double Error detected (DED) of Rd Data
+                                                         [0] corresponds to DQ[63:0]_c0_p0
+                                                         [1] corresponds to DQ[63:0]_c0_p1
+                                                         [2] corresponds to DQ[63:0]_c1_p0
+                                                         [3] corresponds to DQ[63:0]_c1_p1
+                                                         where _cC_pP denotes cycle C and phase P
+                                                         Write of 1 will clear the corresponding error bit */
+	uint64_t sec_err                      : 4;  /**< Single Error (corrected) of Rd Data
+                                                         [0] corresponds to DQ[63:0]_c0_p0
+                                                         [1] corresponds to DQ[63:0]_c0_p1
+                                                         [2] corresponds to DQ[63:0]_c1_p0
+                                                         [3] corresponds to DQ[63:0]_c1_p1
+                                                         where _cC_pP denotes cycle C and phase P
+                                                         Write of 1 will clear the corresponding error bit */
+	uint64_t nxm_wr_err                   : 1;  /**< Write to non-existent memory
+                                                         Write of 1 will clear the corresponding error bit */
+#else
+	uint64_t nxm_wr_err                   : 1;
+	uint64_t sec_err                      : 4;
+	uint64_t ded_err                      : 4;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_lmcx_int_s                cn63xx;
+	struct cvmx_lmcx_int_s                cn63xxp1;
+};
+typedef union cvmx_lmcx_int cvmx_lmcx_int_t;
+
+/**
+ * cvmx_lmc#_int_en
+ *
+ * LMC_INT_EN = LMC Interrupt Enable Register
+ *
+ */
+union cvmx_lmcx_int_en
+{
+	uint64_t u64;
+	struct cvmx_lmcx_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t intr_ded_ena                 : 1;  /**< ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting an uncorrectable Dbl Bit ECC
+                                                         error. */
+	uint64_t intr_sec_ena                 : 1;  /**< ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting a correctable Single Bit ECC
+                                                         error. */
+	uint64_t intr_nxm_wr_ena              : 1;  /**< Non Write Error Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting an non-existent memory write */
+#else
+	uint64_t intr_nxm_wr_ena              : 1;
+	uint64_t intr_sec_ena                 : 1;
+	uint64_t intr_ded_ena                 : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_lmcx_int_en_s             cn63xx;
+	struct cvmx_lmcx_int_en_s             cn63xxp1;
+};
+typedef union cvmx_lmcx_int_en cvmx_lmcx_int_en_t;
+
+/**
+ * cvmx_lmc#_mem_cfg0
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *                  LMC_MEM_CFG0 = LMC Memory Configuration Register0
+ *
+ * This register controls certain parameters of  Memory Configuration
+ */
+union cvmx_lmcx_mem_cfg0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_mem_cfg0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC_OPS_CNT_*, LMC_IFB_CNT_*, and LMC_DCLK_CNT_*
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+	uint64_t silo_qc                      : 1;  /**< Adds a Quarter Cycle granularity to generate
+                                                         dqs pulse generation for silo.
+                                                         Combination of Silo_HC and Silo_QC gives the
+                                                         ability to position the read enable with quarter
+                                                         cycle resolution. This is applied on all the bytes
+                                                         uniformly. */
+	uint64_t bunk_ena                     : 1;  /**< Bunk Enable aka RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the bunk_ena bit will enable
+                                                         the drive of the CS_N[1:0] pins based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+	uint64_t ded_err                      : 4;  /**< Double Error detected (DED) of Rd Data
+                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
+                                                         [25] corresponds to DQ[63:0], Phase0
+                                                         [26] corresponds to DQ[127:64], Phase0
+                                                         [27] corresponds to DQ[63:0], Phase1
+                                                         [28] corresponds to DQ[127:64], Phase1
+                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
+                                                         [25] corresponds to DQ[63:0], Phase0, cycle0
+                                                         [26] corresponds to DQ[63:0], Phase0, cycle1
+                                                         [27] corresponds to DQ[63:0], Phase1, cycle0
+                                                         [28] corresponds to DQ[63:0], Phase1, cycle1
+                                                         Write of 1 will clear the corresponding error bit */
+	uint64_t sec_err                      : 4;  /**< Single Error (corrected) of Rd Data
+                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
+                                                         [21] corresponds to DQ[63:0], Phase0
+                                                         [22] corresponds to DQ[127:64], Phase0
+                                                         [23] corresponds to DQ[63:0], Phase1
+                                                         [24] corresponds to DQ[127:64], Phase1
+                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
+                                                         [21] corresponds to DQ[63:0], Phase0, cycle0
+                                                         [22] corresponds to DQ[63:0], Phase0, cycle1
+                                                         [23] corresponds to DQ[63:0], Phase1, cycle0
+                                                         [24] corresponds to DQ[63:0], Phase1, cycle1
+                                                         Write of 1 will clear the corresponding error bit */
+	uint64_t intr_ded_ena                 : 1;  /**< ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting an uncorrectable Dbl Bit ECC
+                                                         error. */
+	uint64_t intr_sec_ena                 : 1;  /**< ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting a correctable Single Bit ECC
+                                                         error. */
+	uint64_t tcl                          : 4;  /**< This register is not used */
+	uint64_t ref_int                      : 6;  /**< Refresh interval represented in \#of 512 dclk increments.
+                                                         Program this to RND-DN(tREFI/clkPeriod/512)
+                                                            - 000000: RESERVED
+                                                            - 000001: 1 * 512  = 512 dclks
+                                                             - ...
+                                                            - 111111: 63 * 512 = 32256 dclks */
+	uint64_t pbank_lsb                    : 4;  /**< Physical Bank address select
+                                                                                 Reverting to the explanation for ROW_LSB,
+                                                                                 PBank_LSB would be Row_LSB bit + \#rowbits
+                                                                                 + \#rankbits
+                                                                                 In the 512MB DIMM Example, assuming no rank bits:
+                                                                                 pbank_lsb=mem_addr[15+13] for 64 b mode
+                                                                                          =mem_addr[16+13] for 128b mode
+                                                                                 Hence the parameter
+                                                         0000:pbank[1:0] = mem_adr[28:27]    / rank = mem_adr[26] (if bunk_ena)
+                                                         0001:pbank[1:0] = mem_adr[29:28]    / rank = mem_adr[27]      "
+                                                         0010:pbank[1:0] = mem_adr[30:29]    / rank = mem_adr[28]      "
+                                                         0011:pbank[1:0] = mem_adr[31:30]    / rank = mem_adr[29]      "
+                                                         0100:pbank[1:0] = mem_adr[32:31]    / rank = mem_adr[30]      "
+                                                         0101:pbank[1:0] = mem_adr[33:32]    / rank = mem_adr[31]      "
+                                                         0110:pbank[1:0] =[1'b0,mem_adr[33]] / rank = mem_adr[32]      "
+                                                         0111:pbank[1:0] =[2'b0]             / rank = mem_adr[33]      "
+                                                         1000-1111: RESERVED */
+	uint64_t row_lsb                      : 3;  /**< Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[33:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and dimm)
+                                                         and that is a function of the following:
+                                                         1. \# Banks (4 or 8) - spec'd by BANK8
+                                                         2. Datapath Width(64 or 128) - MODE128b
+                                                         3. \# Ranks in a DIMM - spec'd by BUNK_ENA
+                                                         4. \# DIMM's in the system
+                                                         5. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         6. \# Row Bits of the memory part - spec'd indirectly
+                                                         by the register below (PBANK_LSB).
+                                                         Illustration: For Micron's MT18HTF6472A,512MB DDR2
+                                                         Unbuffered DIMM which uses 256Mb parts (8M x 8 x 4),
+                                                         \# Banks = 4 -> 2 bits of BA
+                                                         \# Columns = 1K -> 10 bits of Col
+                                                         \# Rows = 8K -> 13 bits of Row
+                                                         Assuming that the total Data width is 128, this is how
+                                                         we arrive at row_lsb:
+                                                         Col Address starts from mem_addr[4] for 128b (16Bytes)
+                                                         dq width or from mem_addr[3] for 64b (8Bytes) dq width
+                                                         \# col + \# bank = 12. Hence row_lsb is mem_adr[15] for
+                                                         64bmode or mem_adr[16] for 128b mode. Hence row_lsb
+                                                         parameter should be set to 001 (64b) or 010 (128b).
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101-111:row_lsb = RESERVED */
+	uint64_t ecc_ena                      : 1;  /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64] and DQ[143:137]
+                                                         on writes, will contain the ECC code generated for
+                                                         the lower 64 and upper 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64] and DQ[143:137]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC_FADR, and LMC_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+	uint64_t init_start                   : 1;  /**< A 0->1 transition starts the DDR memory initialization
+                                                         sequence. */
+#else
+	uint64_t init_start                   : 1;
+	uint64_t ecc_ena                      : 1;
+	uint64_t row_lsb                      : 3;
+	uint64_t pbank_lsb                    : 4;
+	uint64_t ref_int                      : 6;
+	uint64_t tcl                          : 4;
+	uint64_t intr_sec_ena                 : 1;
+	uint64_t intr_ded_ena                 : 1;
+	uint64_t sec_err                      : 4;
+	uint64_t ded_err                      : 4;
+	uint64_t bunk_ena                     : 1;
+	uint64_t silo_qc                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_mem_cfg0_s           cn30xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn31xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn38xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn38xxp2;
+	struct cvmx_lmcx_mem_cfg0_s           cn50xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn52xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn52xxp1;
+	struct cvmx_lmcx_mem_cfg0_s           cn56xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn56xxp1;
+	struct cvmx_lmcx_mem_cfg0_s           cn58xx;
+	struct cvmx_lmcx_mem_cfg0_s           cn58xxp1;
+};
+typedef union cvmx_lmcx_mem_cfg0 cvmx_lmcx_mem_cfg0_t;
+
+/**
+ * cvmx_lmc#_mem_cfg1
+ *
+ * LMC_MEM_CFG1 = LMC Memory Configuration Register1
+ *
+ * This register controls the External Memory Configuration Timing Parameters. Please refer to the
+ * appropriate DDR part spec from your memory vendor for the various values in this CSR.
+ * The details of each of these timing parameters can be found in the JEDEC spec or the vendor
+ * spec of the memory parts.
+ */
+union cvmx_lmcx_mem_cfg1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_mem_cfg1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t comp_bypass                  : 1;  /**< Compensation bypass. */
+	uint64_t trrd                         : 3;  /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
+                                                         For DDR2, TYP=7.5ns
+                                                            - 000: RESERVED
+                                                            - 001: 1 tCYC
+                                                            - 010: 2 tCYC
+                                                            - 011: 3 tCYC
+                                                            - 100: 4 tCYC
+                                                            - 101: 5 tCYC
+                                                            - 110: 6 tCYC
+                                                            - 111: 7 tCYC */
+	uint64_t caslat                       : 3;  /**< CAS Latency Encoding which is loaded into each DDR
+                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
+                                                         (Represented in tCYC cycles == 1 dclks)
+                                                            000 RESERVED
+                                                            001 RESERVED
+                                                            010 2.0 tCYC
+                                                            011 3.0 tCYC
+                                                            100 4.0 tCYC
+                                                            101 5.0 tCYC
+                                                            110 6.0 tCYC
+                                                            111 RESERVED
+                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
+                                                         account for 1/4 cycle granularity in board/etch delays. */
+	uint64_t tmrd                         : 3;  /**< tMRD Cycles
+                                                         (Represented in dclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3
+                                                             - 100: 4
+                                                             - 101-111: RESERVED */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/4*tcyc(ns)],
+                                                         where tRFC is from the DDR2 spec, and tcyc(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         For example, with 2Gb, DDR2-667 parts,
+                                                         typ tRFC=195ns, so TRFC (CSR field) = 0x11.
+                                                             TRFC (binary): Corresponding tRFC Cycles
+                                                             ----------------------------------------
+                                                             - 00000-00001: RESERVED
+                                                             - 00010: 0-8
+                                                             - 00011: 9-12
+                                                             - 00100: 13-16
+                                                             - ...
+                                                             - 11110: 117-120
+                                                             - 11111: 121-124 */
+	uint64_t trp                          : 4;  /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
+                                                         is 1), load tRP cycles + 1 into this register. */
+	uint64_t twtr                         : 4;  /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1 dclk)
+                                                             - 00000-0001: RESERVED
+                                                             - 00010: 2
+                                                             - ...
+                                                             - 11111: 31 */
+#else
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trp                          : 4;
+	uint64_t trfc                         : 5;
+	uint64_t tmrd                         : 3;
+	uint64_t caslat                       : 3;
+	uint64_t trrd                         : 3;
+	uint64_t comp_bypass                  : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_mem_cfg1_s           cn30xx;
+	struct cvmx_lmcx_mem_cfg1_s           cn31xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t trrd                         : 3;  /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
+                                                         For DDR2, TYP=7.5ns
+                                                            - 000: RESERVED
+                                                            - 001: 1 tCYC
+                                                            - 010: 2 tCYC
+                                                            - 011: 3 tCYC
+                                                            - 100: 4 tCYC
+                                                            - 101: 5 tCYC
+                                                            - 110-111: RESERVED */
+	uint64_t caslat                       : 3;  /**< CAS Latency Encoding which is loaded into each DDR
+                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
+                                                         (Represented in tCYC cycles == 1 dclks)
+                                                            000 RESERVED
+                                                            001 RESERVED
+                                                            010 2.0 tCYC
+                                                            011 3.0 tCYC
+                                                            100 4.0 tCYC
+                                                            101 5.0 tCYC
+                                                            110 6.0 tCYC (DDR2)
+                                                                2.5 tCYC (DDR1)
+                                                            111 RESERVED
+                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
+                                                         account for 1/4 cycle granularity in board/etch delays. */
+	uint64_t tmrd                         : 3;  /**< tMRD Cycles
+                                                         (Represented in dclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3
+                                                             - 100: 4
+                                                             - 101-111: RESERVED */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/4*tcyc(ns)],
+                                                         where tRFC is from the DDR2 spec, and tcyc(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         For example, with 2Gb, DDR2-667 parts,
+                                                         typ tRFC=195ns, so TRFC (CSR field) = 0x11.
+                                                             TRFC (binary): Corresponding tRFC Cycles
+                                                             ----------------------------------------
+                                                             - 00000-00001: RESERVED
+                                                             - 00010: 0-8
+                                                             - 00011: 9-12
+                                                             - 00100: 13-16
+                                                             - ...
+                                                             - 11110: 117-120
+                                                             - 11111: 121-124 */
+	uint64_t trp                          : 4;  /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED
+                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
+                                                         is 1), load tRP cycles + 1 into this register. */
+	uint64_t twtr                         : 4;  /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1110-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1 dclk)
+                                                         For DDR-I mode:
+                                                         TYP=45ns (66MHz=3,167MHz=8,400MHz=18
+                                                             - 00000-0001: RESERVED
+                                                             - 00010: 2
+                                                             - ...
+                                                             - 10100: 20
+                                                             - 10101-11111: RESERVED */
+#else
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trp                          : 4;
+	uint64_t trfc                         : 5;
+	uint64_t tmrd                         : 3;
+	uint64_t caslat                       : 3;
+	uint64_t trrd                         : 3;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn38xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn38xxp2;
+	struct cvmx_lmcx_mem_cfg1_s           cn50xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn52xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn52xxp1;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn56xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn56xxp1;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn58xx;
+	struct cvmx_lmcx_mem_cfg1_cn38xx      cn58xxp1;
+};
+typedef union cvmx_lmcx_mem_cfg1 cvmx_lmcx_mem_cfg1_t;
+
+/**
+ * cvmx_lmc#_modereg_params0
+ *
+ * Notes:
+ * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
+ *
+ */
+union cvmx_lmcx_modereg_params0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_modereg_params0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t ppd                          : 1;  /**< DLL Control for precharge powerdown
+                                                         0 = Slow exit (DLL off)
+                                                         1 = Fast exit (DLL on)
+                                                         LMC writes this value to MR0[PPD] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[PPD] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t wrp                          : 3;  /**< Write recovery for auto precharge
+                                                         Should be programmed to be equal to or greater than
+                                                         RNDUP[tWR(ns)/tCYC(ns)]
+                                                         000 = Reserved
+                                                         001 = 5
+                                                         010 = 6
+                                                         011 = 7
+                                                         100 = 8
+                                                         101 = 10
+                                                         110 = 12
+                                                         111 = Reserved
+                                                         LMC writes this value to MR0[WR] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[WR] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t dllr                         : 1;  /**< DLL Reset
+                                                         LMC writes this value to MR0[DLL] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[DLL] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t tm                           : 1;  /**< Test Mode
+                                                         LMC writes this value to MR0[TM] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[TM] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t rbt                          : 1;  /**< Read Burst Type
+                                                         1 = interleaved (fixed)
+                                                         LMC writes this value to MR0[RBT] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[RBT] value must be 1 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t cl                           : 4;  /**< CAS Latency
+                                                         0010 = 5
+                                                         0100 = 6
+                                                         0110 = 7
+                                                         1000 = 8
+                                                         1010 = 9
+                                                         1100 = 10
+                                                         1110 = 11
+                                                         0000, ???1 = Reserved
+                                                         LMC writes this value to MR0[CAS Latency / CL] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         This value must equal the MR0[CAS Latency / CL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t bl                           : 2;  /**< Burst Length
+                                                         0 = 8 (fixed)
+                                                         LMC writes this value to MR0[BL] in the selected DDR3 parts
+                                                         during power-up/init and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR0[BL] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t qoff                         : 1;  /**< Qoff Enable
+                                                         0 = enable
+                                                         1 = disable
+                                                         LMC writes this value to MR1[Qoff] in the DDR3 parts in the selected ranks
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK,INIT_STATUS] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         The MR1[Qoff] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t tdqs                         : 1;  /**< TDQS Enable
+                                                         0 = disable
+                                                         LMC writes this value to MR1[TDQS] in the DDR3 parts in the selected ranks
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK,INIT_STATUS] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t wlev                         : 1;  /**< Write Leveling Enable
+                                                         0 = disable
+                                                         LMC writes MR1[Level]=0 in the DDR3 parts in the selected ranks
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         (Write-leveling can only be initiated via the
+                                                         write-leveling instruction sequence.)
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK,INIT_STATUS] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t al                           : 2;  /**< Additive Latency
+                                                         00 = 0
+                                                         01 = CL-1
+                                                         10 = CL-2
+                                                         11 = Reserved
+                                                         LMC writes this value to MR1[AL] in the selected DDR3 parts
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR1[AL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation.
+                                                         See also LMC*_CONTROL[POCAS]. */
+	uint64_t dll                          : 1;  /**< DLL Enable
+                                                         0 = enable
+                                                         1 = disable.
+                                                         LMC writes this value to MR1[DLL] in the selected DDR3 parts
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR1[DLL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation.
+                                                         In dll-off mode, CL/CWL must be programmed
+                                                         equal to 6/6, respectively, as per the DDR3 specifications. */
+	uint64_t mpr                          : 1;  /**< MPR
+                                                         LMC writes this value to MR3[MPR] in the selected DDR3 parts
+                                                         during power-up/init, read-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         (LMC also writes MR3[MPR]=1 at the beginning of the
+                                                         read-leveling instruction sequence. Read-leveling should only be initiated via the
+                                                         read-leveling instruction sequence.)
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR3[MPR] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t mprloc                       : 2;  /**< MPR Location
+                                                         LMC writes this value to MR3[MPRLoc] in the selected DDR3 parts
+                                                         during power-up/init, read-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh exit instruction sequences.
+                                                         (LMC also writes MR3[MPRLoc]=0 at the beginning of the
+                                                         read-leveling instruction sequence.)
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK].
+                                                         The MR3[MPRLoc] value must be 0 in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+	uint64_t cwl                          : 3;  /**< CAS Write Latency
+                                                         - 000: 5
+                                                         - 001: 6
+                                                         - 010: 7
+                                                         - 011: 8
+                                                         1xx: Reserved
+                                                         LMC writes this value to MR2[CWL] in the selected DDR3 parts
+                                                         during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         This value must equal the MR2[CWL] value in all the DDR3
+                                                         parts attached to all ranks during normal operation. */
+#else
+	uint64_t cwl                          : 3;
+	uint64_t mprloc                       : 2;
+	uint64_t mpr                          : 1;
+	uint64_t dll                          : 1;
+	uint64_t al                           : 2;
+	uint64_t wlev                         : 1;
+	uint64_t tdqs                         : 1;
+	uint64_t qoff                         : 1;
+	uint64_t bl                           : 2;
+	uint64_t cl                           : 4;
+	uint64_t rbt                          : 1;
+	uint64_t tm                           : 1;
+	uint64_t dllr                         : 1;
+	uint64_t wrp                          : 3;
+	uint64_t ppd                          : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_lmcx_modereg_params0_s    cn63xx;
+	struct cvmx_lmcx_modereg_params0_s    cn63xxp1;
+};
+typedef union cvmx_lmcx_modereg_params0 cvmx_lmcx_modereg_params0_t;
+
+/**
+ * cvmx_lmc#_modereg_params1
+ *
+ * Notes:
+ * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers.
+ *
+ */
+union cvmx_lmcx_modereg_params1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_modereg_params1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t rtt_nom_11                   : 3;  /**< RTT_NOM Rank 3
+                                                         LMC writes this value to MR1[Rtt_Nom] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         Per JEDEC DDR3 specifications, if RTT_Nom is used during writes,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6) are allowed.
+                                                         Otherwise, values MR1[Rtt_Nom] = 4 (RQZ/12) and 5 (RQZ/8) are also allowed. */
+	uint64_t dic_11                       : 2;  /**< Output Driver Impedance Control Rank 3
+                                                         LMC writes this value to MR1[D.I.C.] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_11                    : 2;  /**< RTT_WR Rank 3
+                                                         LMC writes this value to MR2[Rtt_WR] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_11                       : 1;  /**< Self-refresh temperature range Rank 3
+                                                         LMC writes this value to MR2[SRT] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_11                       : 1;  /**< Auto self-refresh Rank 3
+                                                         LMC writes this value to MR2[ASR] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_11                      : 3;  /**< Partial array self-refresh Rank 3
+                                                         LMC writes this value to MR2[PASR] in the rank 3 (i.e. DIMM1_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_nom_10                   : 3;  /**< RTT_NOM Rank 2
+                                                         LMC writes this value to MR1[Rtt_Nom] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         Per JEDEC DDR3 specifications, if RTT_Nom is used during writes,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6) are allowed.
+                                                         Otherwise, values MR1[Rtt_Nom] = 4 (RQZ/12) and 5 (RQZ/8) are also allowed. */
+	uint64_t dic_10                       : 2;  /**< Output Driver Impedance Control Rank 2
+                                                         LMC writes this value to MR1[D.I.C.] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_10                    : 2;  /**< RTT_WR Rank 2
+                                                         LMC writes this value to MR2[Rtt_WR] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_10                       : 1;  /**< Self-refresh temperature range Rank 2
+                                                         LMC writes this value to MR2[SRT] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_10                       : 1;  /**< Auto self-refresh Rank 2
+                                                         LMC writes this value to MR2[ASR] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_10                      : 3;  /**< Partial array self-refresh Rank 2
+                                                         LMC writes this value to MR2[PASR] in the rank 2 (i.e. DIMM1_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_nom_01                   : 3;  /**< RTT_NOM Rank 1
+                                                         LMC writes this value to MR1[Rtt_Nom] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         Per JEDEC DDR3 specifications, if RTT_Nom is used during writes,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6) are allowed.
+                                                         Otherwise, values MR1[Rtt_Nom] = 4 (RQZ/12) and 5 (RQZ/8) are also allowed. */
+	uint64_t dic_01                       : 2;  /**< Output Driver Impedance Control Rank 1
+                                                         LMC writes this value to MR1[D.I.C.] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_01                    : 2;  /**< RTT_WR Rank 1
+                                                         LMC writes this value to MR2[Rtt_WR] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_01                       : 1;  /**< Self-refresh temperature range Rank 1
+                                                         LMC writes this value to MR2[SRT] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_01                       : 1;  /**< Auto self-refresh Rank 1
+                                                         LMC writes this value to MR2[ASR] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_01                      : 3;  /**< Partial array self-refresh Rank 1
+                                                         LMC writes this value to MR2[PASR] in the rank 1 (i.e. DIMM0_CS1) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_nom_00                   : 3;  /**< RTT_NOM Rank 0
+                                                         LMC writes this value to MR1[Rtt_Nom] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT].
+                                                         Per JEDEC DDR3 specifications, if RTT_Nom is used during writes,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6) are allowed.
+                                                         Otherwise, values MR1[Rtt_Nom] = 4 (RQZ/12) and 5 (RQZ/8) are also allowed. */
+	uint64_t dic_00                       : 2;  /**< Output Driver Impedance Control Rank 0
+                                                         LMC writes this value to MR1[D.I.C.] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t rtt_wr_00                    : 2;  /**< RTT_WR Rank 0
+                                                         LMC writes this value to MR2[Rtt_WR] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t srt_00                       : 1;  /**< Self-refresh temperature range Rank 0
+                                                         LMC writes this value to MR2[SRT] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t asr_00                       : 1;  /**< Auto self-refresh Rank 0
+                                                         LMC writes this value to MR2[ASR] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+	uint64_t pasr_00                      : 3;  /**< Partial array self-refresh Rank 0
+                                                         LMC writes this value to MR2[PASR] in the rank 0 (i.e. DIMM0_CS0) DDR3 parts
+                                                         when selected during power-up/init, write-leveling, and, if LMC*_CONFIG[SREF_WITH_DLL] is set,
+                                                         self-refresh entry and exit instruction sequences.
+                                                         See LMC*_CONFIG[SEQUENCE,INIT_START,RANKMASK] and
+                                                         LMC*_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */
+#else
+	uint64_t pasr_00                      : 3;
+	uint64_t asr_00                       : 1;
+	uint64_t srt_00                       : 1;
+	uint64_t rtt_wr_00                    : 2;
+	uint64_t dic_00                       : 2;
+	uint64_t rtt_nom_00                   : 3;
+	uint64_t pasr_01                      : 3;
+	uint64_t asr_01                       : 1;
+	uint64_t srt_01                       : 1;
+	uint64_t rtt_wr_01                    : 2;
+	uint64_t dic_01                       : 2;
+	uint64_t rtt_nom_01                   : 3;
+	uint64_t pasr_10                      : 3;
+	uint64_t asr_10                       : 1;
+	uint64_t srt_10                       : 1;
+	uint64_t rtt_wr_10                    : 2;
+	uint64_t dic_10                       : 2;
+	uint64_t rtt_nom_10                   : 3;
+	uint64_t pasr_11                      : 3;
+	uint64_t asr_11                       : 1;
+	uint64_t srt_11                       : 1;
+	uint64_t rtt_wr_11                    : 2;
+	uint64_t dic_11                       : 2;
+	uint64_t rtt_nom_11                   : 3;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_lmcx_modereg_params1_s    cn63xx;
+	struct cvmx_lmcx_modereg_params1_s    cn63xxp1;
+};
+typedef union cvmx_lmcx_modereg_params1 cvmx_lmcx_modereg_params1_t;
+
+/**
+ * cvmx_lmc#_nxm
+ *
+ * LMC_NXM = LMC non-existent memory
+ *
+ *
+ * Notes:
+ * Decoding for mem_msb/rank
+ *      - 0000: mem_msb = mem_adr[25]
+ *      - 0001: mem_msb = mem_adr[26]
+ *      - 0010: mem_msb = mem_adr[27]
+ *      - 0011: mem_msb = mem_adr[28]
+ *      - 0100: mem_msb = mem_adr[29]
+ *      - 0101: mem_msb = mem_adr[30]
+ *      - 0110: mem_msb = mem_adr[31]
+ *      - 0111: mem_msb = mem_adr[32]
+ *      - 1000: mem_msb = mem_adr[33]
+ *      - 1001: mem_msb = mem_adr[34]
+ *      1010-1111 = Reserved
+ * For example, for a DIMM made of Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank)
+ * DDR3 parts, the column address width = 10, so with
+ * 10b of col, 3b of bus, 3b of bank, row_lsb = 16. So, row = mem_adr[29:16] and
+ * mem_msb = 4
+ *
+ * Note also that addresses greater the max defined space (pbank_msb) are also treated
+ * as NXM accesses
+ */
+union cvmx_lmcx_nxm
+{
+	uint64_t u64;
+	struct cvmx_lmcx_nxm_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t mem_msb_d3_r1                : 4;  /**< Max Row MSB for DIMM3, RANK1/DIMM3 in Single Ranked */
+	uint64_t mem_msb_d3_r0                : 4;  /**< Max Row MSB for DIMM3, RANK0 */
+	uint64_t mem_msb_d2_r1                : 4;  /**< Max Row MSB for DIMM2, RANK1/DIMM2 in Single Ranked */
+	uint64_t mem_msb_d2_r0                : 4;  /**< Max Row MSB for DIMM2, RANK0 */
+	uint64_t mem_msb_d1_r1                : 4;  /**< Max Row MSB for DIMM1, RANK1/DIMM1 in Single Ranked */
+	uint64_t mem_msb_d1_r0                : 4;  /**< Max Row MSB for DIMM1, RANK0 */
+	uint64_t mem_msb_d0_r1                : 4;  /**< Max Row MSB for DIMM0, RANK1/DIMM0 in Single Ranked */
+	uint64_t mem_msb_d0_r0                : 4;  /**< Max Row MSB for DIMM0, RANK0 */
+	uint64_t cs_mask                      : 8;  /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  If LMC*_CONFIG[RANK_ENA]==0 then this
+                                                         mask must be set in pairs because each reference address
+                                                         will assert a pair of chip selects.  If the chip
+                                                         select(s) have a corresponding CS_MASK bit set, then the
+                                                         reference is to non-existent memory (NXM).  LMC will alias a
+                                                         NXM read reference to use the lowest, legal chip select(s)
+                                                         and return 0's. LMC normally discards NXM writes, but will
+                                                         also alias them when LMC*_CONTROL[NXM_WRITE_EN]=1.
+                                                         CS_MASK<7:4> MBZ in 63xx */
+#else
+	uint64_t cs_mask                      : 8;
+	uint64_t mem_msb_d0_r0                : 4;
+	uint64_t mem_msb_d0_r1                : 4;
+	uint64_t mem_msb_d1_r0                : 4;
+	uint64_t mem_msb_d1_r1                : 4;
+	uint64_t mem_msb_d2_r0                : 4;
+	uint64_t mem_msb_d2_r1                : 4;
+	uint64_t mem_msb_d3_r0                : 4;
+	uint64_t mem_msb_d3_r1                : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_lmcx_nxm_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t cs_mask                      : 8;  /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  If LMC_MEM_CFG0[BUNK_ENA]==0 then this
+                                                         mask must be set in pairs because each reference address
+                                                         will assert a pair of chip selects.  If the chip
+                                                         select(s) have a corresponding CS_MASK bit set, then the
+                                                         reference is to non-existent memory.  LMC will alias the
+                                                         reference to use the lowest, legal chip select(s) in
+                                                         that case. */
+#else
+	uint64_t cs_mask                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn52xx;
+	struct cvmx_lmcx_nxm_cn52xx           cn56xx;
+	struct cvmx_lmcx_nxm_cn52xx           cn58xx;
+	struct cvmx_lmcx_nxm_s                cn63xx;
+	struct cvmx_lmcx_nxm_s                cn63xxp1;
+};
+typedef union cvmx_lmcx_nxm cvmx_lmcx_nxm_t;
+
+/**
+ * cvmx_lmc#_ops_cnt
+ *
+ * LMC_OPS_CNT  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ops_cnt
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ops_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t opscnt                       : 64; /**< Performance Counter
+                                                         64-bit counter that increments when the DDR3 data bus
+                                                         is being used
+                                                         DRAM bus utilization = LMC*_OPS_CNT/LMC*_DCLK_CNT */
+#else
+	uint64_t opscnt                       : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_ops_cnt_s            cn63xx;
+	struct cvmx_lmcx_ops_cnt_s            cn63xxp1;
+};
+typedef union cvmx_lmcx_ops_cnt cvmx_lmcx_ops_cnt_t;
+
+/**
+ * cvmx_lmc#_ops_cnt_hi
+ *
+ * LMC_OPS_CNT_HI  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ops_cnt_hi
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ops_cnt_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t opscnt_hi                    : 32; /**< Performance Counter to measure Bus Utilization
+                                                         Upper 32-bits of 64-bit counter
+                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
+#else
+	uint64_t opscnt_hi                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn30xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn31xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn38xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn38xxp2;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn50xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn52xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn52xxp1;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn56xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn56xxp1;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn58xx;
+	struct cvmx_lmcx_ops_cnt_hi_s         cn58xxp1;
+};
+typedef union cvmx_lmcx_ops_cnt_hi cvmx_lmcx_ops_cnt_hi_t;
+
+/**
+ * cvmx_lmc#_ops_cnt_lo
+ *
+ * LMC_OPS_CNT_LO  = Performance Counters
+ *
+ */
+union cvmx_lmcx_ops_cnt_lo
+{
+	uint64_t u64;
+	struct cvmx_lmcx_ops_cnt_lo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t opscnt_lo                    : 32; /**< Performance Counter
+                                                         Low 32-bits of 64-bit counter
+                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
+#else
+	uint64_t opscnt_lo                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn30xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn31xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn38xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn38xxp2;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn50xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn52xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn52xxp1;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn56xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn56xxp1;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn58xx;
+	struct cvmx_lmcx_ops_cnt_lo_s         cn58xxp1;
+};
+typedef union cvmx_lmcx_ops_cnt_lo cvmx_lmcx_ops_cnt_lo_t;
+
+/**
+ * cvmx_lmc#_phy_ctl
+ *
+ * LMC_PHY_CTL = LMC PHY Control
+ *
+ */
+union cvmx_lmcx_phy_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_phy_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t rx_always_on                 : 1;  /**< Disable dynamic DDR3 IO Rx power gating */
+	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
+	uint64_t ck_tune1                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout1                   : 4;  /**< Clock delay out setting */
+	uint64_t ck_tune0                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout0                   : 4;  /**< Clock delay out setting */
+	uint64_t loopback                     : 1;  /**< Loopback enable */
+	uint64_t loopback_pos                 : 1;  /**< Loopback pos mode */
+	uint64_t ts_stagger                   : 1;  /**< TS Staggermode
+                                                         This mode configures output drivers with 2-stage drive
+                                                         strength to avoid undershoot issues on the bus when strong
+                                                         drivers are suddenly turned on. When this mode is asserted,
+                                                         Octeon will configure output drivers to be weak drivers
+                                                         (60 ohm output impedance) at the first CK cycle, and
+                                                         change drivers to the designated drive strengths specified
+                                                         in $LMC(0)_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting
+                                                         at the following cycle */
+#else
+	uint64_t ts_stagger                   : 1;
+	uint64_t loopback_pos                 : 1;
+	uint64_t loopback                     : 1;
+	uint64_t ck_dlyout0                   : 4;
+	uint64_t ck_tune0                     : 1;
+	uint64_t ck_dlyout1                   : 4;
+	uint64_t ck_tune1                     : 1;
+	uint64_t lv_mode                      : 1;
+	uint64_t rx_always_on                 : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_lmcx_phy_ctl_s            cn63xx;
+	struct cvmx_lmcx_phy_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t lv_mode                      : 1;  /**< Low Voltage Mode (1.35V) */
+	uint64_t ck_tune1                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout1                   : 4;  /**< Clock delay out setting */
+	uint64_t ck_tune0                     : 1;  /**< Clock Tune */
+	uint64_t ck_dlyout0                   : 4;  /**< Clock delay out setting */
+	uint64_t loopback                     : 1;  /**< Loopback enable */
+	uint64_t loopback_pos                 : 1;  /**< Loopback pos mode */
+	uint64_t ts_stagger                   : 1;  /**< TS Staggermode
+                                                         This mode configures output drivers with 2-stage drive
+                                                         strength to avoid undershoot issues on the bus when strong
+                                                         drivers are suddenly turned on. When this mode is asserted,
+                                                         Octeon will configure output drivers to be weak drivers
+                                                         (60 ohm output impedance) at the first CK cycle, and
+                                                         change drivers to the designated drive strengths specified
+                                                         in $LMC(0)_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting
+                                                         at the following cycle */
+#else
+	uint64_t ts_stagger                   : 1;
+	uint64_t loopback_pos                 : 1;
+	uint64_t loopback                     : 1;
+	uint64_t ck_dlyout0                   : 4;
+	uint64_t ck_tune0                     : 1;
+	uint64_t ck_dlyout1                   : 4;
+	uint64_t ck_tune1                     : 1;
+	uint64_t lv_mode                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_phy_ctl cvmx_lmcx_phy_ctl_t;
+
+/**
+ * cvmx_lmc#_pll_bwctl
+ *
+ * LMC_PLL_BWCTL  = DDR PLL Bandwidth Control Register
+ *
+ */
+union cvmx_lmcx_pll_bwctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_pll_bwctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bwupd                        : 1;  /**< Load this Bandwidth Register value into the PLL */
+	uint64_t bwctl                        : 4;  /**< Bandwidth Control Register for DDR PLL */
+#else
+	uint64_t bwctl                        : 4;
+	uint64_t bwupd                        : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_lmcx_pll_bwctl_s          cn30xx;
+	struct cvmx_lmcx_pll_bwctl_s          cn31xx;
+	struct cvmx_lmcx_pll_bwctl_s          cn38xx;
+	struct cvmx_lmcx_pll_bwctl_s          cn38xxp2;
+};
+typedef union cvmx_lmcx_pll_bwctl cvmx_lmcx_pll_bwctl_t;
+
+/**
+ * cvmx_lmc#_pll_ctl
+ *
+ * LMC_PLL_CTL = LMC pll control
+ *
+ *
+ * Notes:
+ * This CSR is only relevant for LMC0. LMC1_PLL_CTL is not used.
+ *
+ * Exactly one of EN2, EN4, EN6, EN8, EN12, EN16 must be set.
+ *
+ * The resultant DDR_CK frequency is the DDR2_REF_CLK
+ * frequency multiplied by:
+ *
+ *     (CLKF + 1) / ((CLKR + 1) * EN(2,4,6,8,12,16))
+ *
+ * The PLL frequency, which is:
+ *
+ *     (DDR2_REF_CLK freq) * ((CLKF + 1) / (CLKR + 1))
+ *
+ * must reside between 1.2 and 2.5 GHz. A faster PLL frequency is desirable if there is a choice.
+ */
+union cvmx_lmcx_pll_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_pll_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_30_63               : 34;
+	uint64_t bypass                       : 1;  /**< PLL Bypass */
+	uint64_t fasten_n                     : 1;  /**< Should be set, especially when CLKF > ~80 */
+	uint64_t div_reset                    : 1;  /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+	uint64_t reset_n                      : 1;  /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+	uint64_t clkf                         : 12; /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 128 */
+	uint64_t clkr                         : 6;  /**< Divide reference by CLKR + 1 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t en16                         : 1;  /**< Divide output by 16 */
+	uint64_t en12                         : 1;  /**< Divide output by 12 */
+	uint64_t en8                          : 1;  /**< Divide output by 8 */
+	uint64_t en6                          : 1;  /**< Divide output by 6 */
+	uint64_t en4                          : 1;  /**< Divide output by 4 */
+	uint64_t en2                          : 1;  /**< Divide output by 2 */
+#else
+	uint64_t en2                          : 1;
+	uint64_t en4                          : 1;
+	uint64_t en6                          : 1;
+	uint64_t en8                          : 1;
+	uint64_t en12                         : 1;
+	uint64_t en16                         : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clkr                         : 6;
+	uint64_t clkf                         : 12;
+	uint64_t reset_n                      : 1;
+	uint64_t div_reset                    : 1;
+	uint64_t fasten_n                     : 1;
+	uint64_t bypass                       : 1;
+	uint64_t reserved_30_63               : 34;
+#endif
+	} s;
+	struct cvmx_lmcx_pll_ctl_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t fasten_n                     : 1;  /**< Should be set, especially when CLKF > ~80 */
+	uint64_t div_reset                    : 1;  /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+	uint64_t reset_n                      : 1;  /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+	uint64_t clkf                         : 12; /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 256 */
+	uint64_t clkr                         : 6;  /**< Divide reference by CLKR + 1 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t en16                         : 1;  /**< Divide output by 16 */
+	uint64_t en12                         : 1;  /**< Divide output by 12 */
+	uint64_t en8                          : 1;  /**< Divide output by 8 */
+	uint64_t en6                          : 1;  /**< Divide output by 6 */
+	uint64_t en4                          : 1;  /**< Divide output by 4 */
+	uint64_t en2                          : 1;  /**< Divide output by 2 */
+#else
+	uint64_t en2                          : 1;
+	uint64_t en4                          : 1;
+	uint64_t en6                          : 1;
+	uint64_t en8                          : 1;
+	uint64_t en12                         : 1;
+	uint64_t en16                         : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clkr                         : 6;
+	uint64_t clkf                         : 12;
+	uint64_t reset_n                      : 1;
+	uint64_t div_reset                    : 1;
+	uint64_t fasten_n                     : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn50xx;
+	struct cvmx_lmcx_pll_ctl_s            cn52xx;
+	struct cvmx_lmcx_pll_ctl_s            cn52xxp1;
+	struct cvmx_lmcx_pll_ctl_cn50xx       cn56xx;
+	struct cvmx_lmcx_pll_ctl_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t div_reset                    : 1;  /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+	uint64_t reset_n                      : 1;  /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+	uint64_t clkf                         : 12; /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 128 */
+	uint64_t clkr                         : 6;  /**< Divide reference by CLKR + 1 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t en16                         : 1;  /**< Divide output by 16 */
+	uint64_t en12                         : 1;  /**< Divide output by 12 */
+	uint64_t en8                          : 1;  /**< Divide output by 8 */
+	uint64_t en6                          : 1;  /**< Divide output by 6 */
+	uint64_t en4                          : 1;  /**< Divide output by 4 */
+	uint64_t en2                          : 1;  /**< Divide output by 2 */
+#else
+	uint64_t en2                          : 1;
+	uint64_t en4                          : 1;
+	uint64_t en6                          : 1;
+	uint64_t en8                          : 1;
+	uint64_t en12                         : 1;
+	uint64_t en16                         : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t clkr                         : 6;
+	uint64_t clkf                         : 12;
+	uint64_t reset_n                      : 1;
+	uint64_t div_reset                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn56xxp1;
+	struct cvmx_lmcx_pll_ctl_cn56xxp1     cn58xx;
+	struct cvmx_lmcx_pll_ctl_cn56xxp1     cn58xxp1;
+};
+typedef union cvmx_lmcx_pll_ctl cvmx_lmcx_pll_ctl_t;
+
+/**
+ * cvmx_lmc#_pll_status
+ *
+ * LMC_PLL_STATUS = LMC pll status
+ *
+ */
+union cvmx_lmcx_pll_status
+{
+	uint64_t u64;
+	struct cvmx_lmcx_pll_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ddr__nctl                    : 5;  /**< DDR nctl from compensation circuit */
+	uint64_t ddr__pctl                    : 5;  /**< DDR pctl from compensation circuit */
+	uint64_t reserved_2_21                : 20;
+	uint64_t rfslip                       : 1;  /**< Reference clock slip */
+	uint64_t fbslip                       : 1;  /**< Feedback clock slip */
+#else
+	uint64_t fbslip                       : 1;
+	uint64_t rfslip                       : 1;
+	uint64_t reserved_2_21                : 20;
+	uint64_t ddr__pctl                    : 5;
+	uint64_t ddr__nctl                    : 5;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_pll_status_s         cn50xx;
+	struct cvmx_lmcx_pll_status_s         cn52xx;
+	struct cvmx_lmcx_pll_status_s         cn52xxp1;
+	struct cvmx_lmcx_pll_status_s         cn56xx;
+	struct cvmx_lmcx_pll_status_s         cn56xxp1;
+	struct cvmx_lmcx_pll_status_s         cn58xx;
+	struct cvmx_lmcx_pll_status_cn58xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t rfslip                       : 1;  /**< Reference clock slip */
+	uint64_t fbslip                       : 1;  /**< Feedback clock slip */
+#else
+	uint64_t fbslip                       : 1;
+	uint64_t rfslip                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn58xxp1;
+};
+typedef union cvmx_lmcx_pll_status cvmx_lmcx_pll_status_t;
+
+/**
+ * cvmx_lmc#_read_level_ctl
+ *
+ * Notes:
+ * The HW writes and reads the cache block selected by ROW, COL, BNK and the rank as part of a read-leveling sequence for a rank.
+ * A cache block write is 16 72-bit words. PATTERN selects the write value. For the first 8
+ * words, the write value is the bit PATTERN<i> duplicated into a 72-bit vector. The write value of
+ * the last 8 words is the inverse of the write value of the first 8 words.
+ * See LMC*_READ_LEVEL_RANK*.
+ */
+union cvmx_lmcx_read_level_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_read_level_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t rankmask                     : 4;  /**< Selects ranks to be leveled
+                                                         to read-level rank i, set RANKMASK<i> */
+	uint64_t pattern                      : 8;  /**< All DQ driven to PATTERN[burst], 0 <= burst <= 7
+                                                         All DQ driven to ~PATTERN[burst-8], 8 <= burst <= 15 */
+	uint64_t row                          : 16; /**< Row    address used to write/read data pattern */
+	uint64_t col                          : 12; /**< Column address used to write/read data pattern */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t bnk                          : 3;  /**< Bank   address used to write/read data pattern */
+#else
+	uint64_t bnk                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t col                          : 12;
+	uint64_t row                          : 16;
+	uint64_t pattern                      : 8;
+	uint64_t rankmask                     : 4;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_lmcx_read_level_ctl_s     cn52xx;
+	struct cvmx_lmcx_read_level_ctl_s     cn52xxp1;
+	struct cvmx_lmcx_read_level_ctl_s     cn56xx;
+	struct cvmx_lmcx_read_level_ctl_s     cn56xxp1;
+};
+typedef union cvmx_lmcx_read_level_ctl cvmx_lmcx_read_level_ctl_t;
+
+/**
+ * cvmx_lmc#_read_level_dbg
+ *
+ * Notes:
+ * A given read of LMC*_READ_LEVEL_DBG returns the read-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled.
+ * LMC*_READ_LEVEL_DBG[BYTE] selects the particular byte.
+ * To get these pass/fail results for another different rank, you must run the hardware read-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run read-leveling separately for each rank, probing LMC*_READ_LEVEL_DBG between each
+ * read-leveling.
+ */
+union cvmx_lmcx_read_level_dbg
+{
+	uint64_t u64;
+	struct cvmx_lmcx_read_level_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bitmask                      : 16; /**< Bitmask generated during deskew settings sweep
+                                                         BITMASK[n]=0 means deskew setting n failed
+                                                         BITMASK[n]=1 means deskew setting n passed
+                                                         for 0 <= n <= 15 */
+	uint64_t reserved_4_15                : 12;
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 8 */
+#else
+	uint64_t byte                         : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t bitmask                      : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_read_level_dbg_s     cn52xx;
+	struct cvmx_lmcx_read_level_dbg_s     cn52xxp1;
+	struct cvmx_lmcx_read_level_dbg_s     cn56xx;
+	struct cvmx_lmcx_read_level_dbg_s     cn56xxp1;
+};
+typedef union cvmx_lmcx_read_level_dbg cvmx_lmcx_read_level_dbg_t;
+
+/**
+ * cvmx_lmc#_read_level_rank#
+ *
+ * Notes:
+ * This is four CSRs per LMC, one per each rank.
+ * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.)
+ * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ * Deskew setting is measured in units of 1/4 DCLK, so the above BYTE* values can range over 4 DCLKs.
+ * SW initiates a HW read-leveling sequence by programming LMC*_READ_LEVEL_CTL and writing INIT_START=1 with SEQUENCE=1.
+ * See LMC*_READ_LEVEL_CTL.
+ */
+union cvmx_lmcx_read_level_rankx
+{
+	uint64_t u64;
+	struct cvmx_lmcx_read_level_rankx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
+                                                         the BYTE* programmings in <35:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = read-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete read-leveling sequence */
+	uint64_t byte8                        : 4;  /**< Deskew setting */
+	uint64_t byte7                        : 4;  /**< Deskew setting */
+	uint64_t byte6                        : 4;  /**< Deskew setting */
+	uint64_t byte5                        : 4;  /**< Deskew setting */
+	uint64_t byte4                        : 4;  /**< Deskew setting */
+	uint64_t byte3                        : 4;  /**< Deskew setting */
+	uint64_t byte2                        : 4;  /**< Deskew setting */
+	uint64_t byte1                        : 4;  /**< Deskew setting */
+	uint64_t byte0                        : 4;  /**< Deskew setting */
+#else
+	uint64_t byte0                        : 4;
+	uint64_t byte1                        : 4;
+	uint64_t byte2                        : 4;
+	uint64_t byte3                        : 4;
+	uint64_t byte4                        : 4;
+	uint64_t byte5                        : 4;
+	uint64_t byte6                        : 4;
+	uint64_t byte7                        : 4;
+	uint64_t byte8                        : 4;
+	uint64_t status                       : 2;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_lmcx_read_level_rankx_s   cn52xx;
+	struct cvmx_lmcx_read_level_rankx_s   cn52xxp1;
+	struct cvmx_lmcx_read_level_rankx_s   cn56xx;
+	struct cvmx_lmcx_read_level_rankx_s   cn56xxp1;
+};
+typedef union cvmx_lmcx_read_level_rankx cvmx_lmcx_read_level_rankx_t;
+
+/**
+ * cvmx_lmc#_reset_ctl
+ *
+ * Specify the RSL base addresses for the block
+ *
+ *
+ * Notes:
+ * DDR3RST - DDR3 DRAM parts have a new RESET#
+ *   pin that wasn't present in DDR2 parts. The
+ *   DDR3RST CSR field controls the assertion of
+ *   the new 63xx pin that attaches to RESET#.
+ *   When DDR3RST is set, 63xx asserts RESET#.
+ *   When DDR3RST is clear, 63xx de-asserts
+ *   RESET#.
+ *
+ *   DDR3RST is set on a cold reset. Warm and
+ *   soft chip resets do not affect the DDR3RST
+ *   value. Outside of cold reset, only software
+ *   CSR writes change the DDR3RST value.
+ *
+ * DDR3PWARM - Enables preserve mode during a warm
+ *   reset. When set, the DDR3 controller hardware
+ *   automatically puts the attached DDR3 DRAM parts
+ *   into self refresh (see LMC*CONFIG[SEQUENCE] below) at the beginning of a warm
+ *   reset sequence, provided that the DDR3 controller
+ *   is up. When clear, the DDR3 controller hardware
+ *   does not put the attached DDR3 DRAM parts into
+ *   self-refresh during a warm reset sequence.
+ *
+ *   DDR3PWARM is cleared on a cold reset. Warm and
+ *   soft chip resets do not affect the DDR3PWARM
+ *   value. Outside of cold reset, only software
+ *   CSR writes change the DDR3PWARM value.
+ *
+ *   Note that if a warm reset follows a soft reset,
+ *   DDR3PWARM has no effect, as the DDR3 controller
+ *   is no longer up after any cold/warm/soft
+ *   reset sequence.
+ *
+ * DDR3PSOFT - Enables preserve mode during a soft
+ *   reset. When set, the DDR3 controller hardware
+ *   automatically puts the attached DDR3 DRAM parts
+ *   into self refresh (see LMC*CONFIG[SEQUENCE] below) at the beginning of a soft
+ *   reset sequence, provided that the DDR3 controller
+ *   is up. When clear, the DDR3 controller hardware
+ *   does not put the attached DDR3 DRAM parts into
+ *   self-refresh during a soft reset sequence.
+ *
+ *   DDR3PSOFT is cleared on a cold reset. Warm and
+ *   soft chip resets do not affect the DDR3PSOFT
+ *   value. Outside of cold reset, only software
+ *   CSR writes change the DDR3PSOFT value.
+ *
+ * DDR3PSV - May be useful for system software to
+ *   determine when the DDR3 contents have been
+ *   preserved.
+ *
+ *   Cleared by hardware during a cold reset. Never
+ *   cleared by hardware during a warm/soft reset.
+ *   Set by hardware during a warm/soft reset if
+ *   the hardware automatically put the DDR3 DRAM
+ *   into self-refresh during the reset sequence.
+ *
+ *   Can also be written by software (to any value).
+ */
+union cvmx_lmcx_reset_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_reset_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ddr3psv                      : 1;  /**< Memory Reset
+                                                         1 = DDR contents preserved */
+	uint64_t ddr3psoft                    : 1;  /**< Memory Reset
+                                                         1 = Enable Preserve mode during soft reset */
+	uint64_t ddr3pwarm                    : 1;  /**< Memory Reset
+                                                         1 = Enable Preserve mode during warm reset */
+	uint64_t ddr3rst                      : 1;  /**< Memory Reset
+                                                         0 = Reset asserted
+                                                         1 = Reset de-asserted */
+#else
+	uint64_t ddr3rst                      : 1;
+	uint64_t ddr3pwarm                    : 1;
+	uint64_t ddr3psoft                    : 1;
+	uint64_t ddr3psv                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_lmcx_reset_ctl_s          cn63xx;
+	struct cvmx_lmcx_reset_ctl_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_reset_ctl cvmx_lmcx_reset_ctl_t;
+
+/**
+ * cvmx_lmc#_rlevel_ctl
+ */
+union cvmx_lmcx_rlevel_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rlevel_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t delay_unload_3               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if LMC*_RLEVEL_RANKi[BYTE*<1:0>] = 3
+                                                         DELAY_UNLOAD_3 should normally be set, particularly at higher speeds. */
+	uint64_t delay_unload_2               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if LMC*_RLEVEL_RANKi[BYTE*<1:0>] = 2
+                                                         DELAY_UNLOAD_2 should normally not be set. */
+	uint64_t delay_unload_1               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if LMC*_RLEVEL_RANKi[BYTE*<1:0>] = 1
+                                                         DELAY_UNLOAD_1 should normally not be set. */
+	uint64_t delay_unload_0               : 1;  /**< When set, unload the PHY silo one cycle later
+                                                         during read-leveling if LMC*_RLEVEL_RANKi[BYTE*<1:0>] = 0
+                                                         DELAY_UNLOAD_0 should normally not be set. */
+	uint64_t bitmask                      : 8;  /**< Mask to select bit lanes on which read-leveling
+                                                         feedback is returned when OR_DIS is set to 1 */
+	uint64_t or_dis                       : 1;  /**< Disable or'ing of bits in a byte lane when computing
+                                                         the read-leveling bitmask
+                                                         OR_DIS should normally not be set. */
+	uint64_t offset_en                    : 1;  /**< When set, LMC attempts to select the read-leveling
+                                                         setting that is LMC*RLEVEL_CTL[OFFSET] settings earlier than the
+                                                         last passing read-leveling setting in the largest
+                                                         contiguous sequence of passing settings.
+                                                         When clear, or if the setting selected by LMC*RLEVEL_CTL[OFFSET]
+                                                         did not pass, LMC selects the middle setting in the
+                                                         largest contiguous sequence of passing settings,
+                                                         rounding earlier when necessary. */
+	uint64_t offset                       : 4;  /**< The offset used when LMC*RLEVEL_CTL[OFFSET] is set */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 8
+                                                         Byte index for which bitmask results are saved
+                                                         in LMC*_RLEVEL_DBG */
+#else
+	uint64_t byte                         : 4;
+	uint64_t offset                       : 4;
+	uint64_t offset_en                    : 1;
+	uint64_t or_dis                       : 1;
+	uint64_t bitmask                      : 8;
+	uint64_t delay_unload_0               : 1;
+	uint64_t delay_unload_1               : 1;
+	uint64_t delay_unload_2               : 1;
+	uint64_t delay_unload_3               : 1;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_lmcx_rlevel_ctl_s         cn63xx;
+	struct cvmx_lmcx_rlevel_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t offset_en                    : 1;  /**< When set, LMC attempts to select the read-leveling
+                                                         setting that is LMC*RLEVEL_CTL[OFFSET] settings earlier than the
+                                                         last passing read-leveling setting in the largest
+                                                         contiguous sequence of passing settings.
+                                                         When clear, or if the setting selected by LMC*RLEVEL_CTL[OFFSET]
+                                                         did not pass, LMC selects the middle setting in the
+                                                         largest contiguous sequence of passing settings,
+                                                         rounding earlier when necessary. */
+	uint64_t offset                       : 4;  /**< The offset used when LMC*RLEVEL_CTL[OFFSET] is set */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 8
+                                                         Byte index for which bitmask results are saved
+                                                         in LMC*_RLEVEL_DBG */
+#else
+	uint64_t byte                         : 4;
+	uint64_t offset                       : 4;
+	uint64_t offset_en                    : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_rlevel_ctl cvmx_lmcx_rlevel_ctl_t;
+
+/**
+ * cvmx_lmc#_rlevel_dbg
+ *
+ * Notes:
+ * A given read of LMC*_RLEVEL_DBG returns the read-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled.
+ * LMC*_RLEVEL_CTL[BYTE] selects the particular byte.
+ *
+ * To get these pass/fail results for another different rank, you must run the hardware read-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run read-leveling separately for each rank, probing LMC*_RLEVEL_DBG between each
+ * read-leveling.
+ */
+union cvmx_lmcx_rlevel_dbg
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rlevel_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bitmask                      : 64; /**< Bitmask generated during deskew settings sweep
+                                                         BITMASK[n]=0 means deskew setting n failed
+                                                         BITMASK[n]=1 means deskew setting n passed
+                                                         for 0 <= n <= 63 */
+#else
+	uint64_t bitmask                      : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_rlevel_dbg_s         cn63xx;
+	struct cvmx_lmcx_rlevel_dbg_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_rlevel_dbg cvmx_lmcx_rlevel_dbg_t;
+
+/**
+ * cvmx_lmc#_rlevel_rank#
+ *
+ * Notes:
+ * This is four CSRs per LMC, one per each rank.
+ *
+ * Deskew setting is measured in units of 1/4 CK, so the above BYTE* values can range over 16 CKs.
+ *
+ * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.)
+ * If HW is unable to find a match per LMC*_RLEVEL_CTL[OFFSET_ENA] and LMC*_RLEVEL_CTL[OFFSET], then HW will set LMC*_RLEVEL_RANKi[BYTE*<5:0>]
+ * to  0.
+ *
+ * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ *
+ * SW initiates a HW read-leveling sequence by programming LMC*_RLEVEL_CTL and writing INIT_START=1 with SEQUENCE=1.
+ * See LMC*_RLEVEL_CTL.
+ *
+ * LMC*_RLEVEL_RANKi values for ranks i without attached DRAM should be set such that
+ * they do not increase the range of possible BYTE values for any byte
+ * lane. The easiest way to do this is to set
+ *     LMC*_RLEVEL_RANKi = LMC*_RLEVEL_RANKj,
+ * where j is some rank with attached DRAM whose LMC*_RLEVEL_RANKj is already fully initialized.
+ */
+union cvmx_lmcx_rlevel_rankx
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rlevel_rankx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t status                       : 2;  /**< Indicates status of the read-levelling and where
+                                                         the BYTE* programmings in <35:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = read-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete read-leveling sequence */
+	uint64_t byte8                        : 6;  /**< Deskew setting
+                                                         When ECC DRAM is not present (i.e. when DRAM is not
+                                                         attached to chip signals DDR_CBS_0_* and DDR_CB[7:0]),
+                                                         SW should write BYTE8 to a value that does
+                                                         not increase the range of possible BYTE* values. The
+                                                         easiest way to do this is to set
+                                                         LMC*_RLEVEL_RANK*[BYTE8] = LMC*_RLEVEL_RANK*[BYTE0]
+                                                         when there is no ECC DRAM, using the final BYTE0 value. */
+	uint64_t byte7                        : 6;  /**< Deskew setting */
+	uint64_t byte6                        : 6;  /**< Deskew setting */
+	uint64_t byte5                        : 6;  /**< Deskew setting */
+	uint64_t byte4                        : 6;  /**< Deskew setting */
+	uint64_t byte3                        : 6;  /**< Deskew setting */
+	uint64_t byte2                        : 6;  /**< Deskew setting */
+	uint64_t byte1                        : 6;  /**< Deskew setting */
+	uint64_t byte0                        : 6;  /**< Deskew setting */
+#else
+	uint64_t byte0                        : 6;
+	uint64_t byte1                        : 6;
+	uint64_t byte2                        : 6;
+	uint64_t byte3                        : 6;
+	uint64_t byte4                        : 6;
+	uint64_t byte5                        : 6;
+	uint64_t byte6                        : 6;
+	uint64_t byte7                        : 6;
+	uint64_t byte8                        : 6;
+	uint64_t status                       : 2;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_lmcx_rlevel_rankx_s       cn63xx;
+	struct cvmx_lmcx_rlevel_rankx_s       cn63xxp1;
+};
+typedef union cvmx_lmcx_rlevel_rankx cvmx_lmcx_rlevel_rankx_t;
+
+/**
+ * cvmx_lmc#_rodt_comp_ctl
+ *
+ * LMC_RODT_COMP_CTL = LMC Compensation control
+ *
+ */
+union cvmx_lmcx_rodt_comp_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rodt_comp_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t enable                       : 1;  /**< 0=not enabled, 1=enable */
+	uint64_t reserved_12_15               : 4;
+	uint64_t nctl                         : 4;  /**< Compensation control bits */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pctl                         : 5;  /**< Compensation control bits */
+#else
+	uint64_t pctl                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t nctl                         : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t enable                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn50xx;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn52xx;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn52xxp1;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn56xx;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn56xxp1;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn58xx;
+	struct cvmx_lmcx_rodt_comp_ctl_s      cn58xxp1;
+};
+typedef union cvmx_lmcx_rodt_comp_ctl cvmx_lmcx_rodt_comp_ctl_t;
+
+/**
+ * cvmx_lmc#_rodt_ctl
+ *
+ * LMC_RODT_CTL = Obsolete LMC Read OnDieTermination control
+ * See the description in LMC_WODT_CTL1. On Reads, Octeon only supports turning on ODT's in
+ * the lower 2 DIMM's with the masks as below.
+ *
+ * Notes:
+ * When a given RANK in position N is selected, the RODT _HI and _LO masks for that position are used.
+ * Mask[3:0] is used for RODT control of the RANKs in positions 3, 2, 1, and 0, respectively.
+ * In  64b mode, DIMMs are assumed to be ordered in the following order:
+ *  position 3: [unused        , DIMM1_RANK1_LO]
+ *  position 2: [unused        , DIMM1_RANK0_LO]
+ *  position 1: [unused        , DIMM0_RANK1_LO]
+ *  position 0: [unused        , DIMM0_RANK0_LO]
+ * In 128b mode, DIMMs are assumed to be ordered in the following order:
+ *  position 3: [DIMM3_RANK1_HI, DIMM1_RANK1_LO]
+ *  position 2: [DIMM3_RANK0_HI, DIMM1_RANK0_LO]
+ *  position 1: [DIMM2_RANK1_HI, DIMM0_RANK1_LO]
+ *  position 0: [DIMM2_RANK0_HI, DIMM0_RANK0_LO]
+ */
+union cvmx_lmcx_rodt_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rodt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rodt_hi3                     : 4;  /**< Read ODT mask for position 3, data[127:64] */
+	uint64_t rodt_hi2                     : 4;  /**< Read ODT mask for position 2, data[127:64] */
+	uint64_t rodt_hi1                     : 4;  /**< Read ODT mask for position 1, data[127:64] */
+	uint64_t rodt_hi0                     : 4;  /**< Read ODT mask for position 0, data[127:64] */
+	uint64_t rodt_lo3                     : 4;  /**< Read ODT mask for position 3, data[ 63: 0] */
+	uint64_t rodt_lo2                     : 4;  /**< Read ODT mask for position 2, data[ 63: 0] */
+	uint64_t rodt_lo1                     : 4;  /**< Read ODT mask for position 1, data[ 63: 0] */
+	uint64_t rodt_lo0                     : 4;  /**< Read ODT mask for position 0, data[ 63: 0] */
+#else
+	uint64_t rodt_lo0                     : 4;
+	uint64_t rodt_lo1                     : 4;
+	uint64_t rodt_lo2                     : 4;
+	uint64_t rodt_lo3                     : 4;
+	uint64_t rodt_hi0                     : 4;
+	uint64_t rodt_hi1                     : 4;
+	uint64_t rodt_hi2                     : 4;
+	uint64_t rodt_hi3                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_rodt_ctl_s           cn30xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn31xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn38xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn38xxp2;
+	struct cvmx_lmcx_rodt_ctl_s           cn50xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn52xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn52xxp1;
+	struct cvmx_lmcx_rodt_ctl_s           cn56xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn56xxp1;
+	struct cvmx_lmcx_rodt_ctl_s           cn58xx;
+	struct cvmx_lmcx_rodt_ctl_s           cn58xxp1;
+};
+typedef union cvmx_lmcx_rodt_ctl cvmx_lmcx_rodt_ctl_t;
+
+/**
+ * cvmx_lmc#_rodt_mask
+ *
+ * LMC_RODT_MASK = LMC Read OnDieTermination mask
+ * System designers may desire to terminate DQ/DQS lines for higher frequency DDR operations
+ * especially on a multi-rank system. DDR3 DQ/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that DIMM. System designers may prefer different combinations of ODT ON's for reads
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a read to that rank, it sets the 4 ODT pins to the MASK pins below.
+ * For eg., When doing a read from Rank0, a system designer may desire to terminate the lines
+ * with the resistor on DIMM0/Rank1. The mask RODT_D0_R0 would then be [00000010].
+ * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not
+ * required, write 0 in this register. Note that, as per the DDR3 specifications, the ODT pin
+ * for the rank that is being read should always be 0.
+ *
+ * Notes:
+ * When a given RANK is selected, the RODT mask for that RANK is used.  The resulting RODT mask is
+ * driven to the DIMMs in the following manner:
+ *             RANK_ENA=1                    RANK_ENA=0
+ * Mask[3] -> DIMM1_ODT_1                    MBZ
+ * Mask[2] -> DIMM1_ODT_0                    DIMM1_ODT_0
+ * Mask[1] -> DIMM0_ODT_1                    MBZ
+ * Mask[0] -> DIMM0_ODT_0                    DIMM0_ODT_0
+ *
+ * LMC always reads entire cache blocks and always reads them via two consecutive
+ * read CAS operations to the same rank+bank+row spaced exactly 4 CK's apart.
+ * When a RODT mask bit is set, LMC asserts the OCTEON ODT output
+ * pin(s) starting (CL - CWL) CK's after the first read CAS operation. Then, OCTEON
+ * normally continues to assert the ODT output pin(s) for 9+LMC*_CONTROL[RODT_BPRCH] more CK's
+ * - for a total of 10+LMC*_CONTROL[RODT_BPRCH] CK's for the entire cache block read -
+ * through the second read CAS operation of the cache block,
+ * satisfying the 6 CK DDR3 ODTH8 requirements.
+ * But it is possible for OCTEON to issue two cache block reads separated by as few as
+ * RtR = 8 or 9 (10 if LMC*_CONTROL[RODT_BPRCH]=1) CK's. In that case, OCTEON asserts the ODT output pin(s)
+ * for the RODT mask of the first cache block read for RtR CK's, then asserts
+ * the ODT output pin(s) for the RODT mask of the second cache block read for 10+LMC*_CONTROL[RODT_BPRCH] CK's
+ * (or less if a third cache block read follows within 8 or 9 (or 10) CK's of this second cache block read).
+ * Note that it may be necessary to force LMC to space back-to-back cache block reads
+ * to different ranks apart by at least 10+LMC*_CONTROL[RODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
+ */
+union cvmx_lmcx_rodt_mask
+{
+	uint64_t u64;
+	struct cvmx_lmcx_rodt_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rodt_d3_r1                   : 8;  /**< Read ODT mask DIMM3, RANK1/DIMM3 in SingleRanked
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d3_r0                   : 8;  /**< Read ODT mask DIMM3, RANK0
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d2_r1                   : 8;  /**< Read ODT mask DIMM2, RANK1/DIMM2 in SingleRanked
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d2_r0                   : 8;  /**< Read ODT mask DIMM2, RANK0
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d1_r1                   : 8;  /**< Read ODT mask DIMM1, RANK1/DIMM1 in SingleRanked
+                                                         if (RANK_ENA) then
+                                                             RODT_D1_R1[3] must be 0
+                                                         else
+                                                             RODT_D1_R1[3:0] is not used and MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d1_r0                   : 8;  /**< Read ODT mask DIMM1, RANK0
+                                                         if (RANK_ENA) then
+                                                             RODT_D1_RO[2] must be 0
+                                                         else
+                                                             RODT_D1_RO[3:2,1] must be 0
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d0_r1                   : 8;  /**< Read ODT mask DIMM0, RANK1/DIMM0 in SingleRanked
+                                                         if (RANK_ENA) then
+                                                             RODT_D0_R1[1] must be 0
+                                                         else
+                                                             RODT_D0_R1[3:0] is not used and MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t rodt_d0_r0                   : 8;  /**< Read ODT mask DIMM0, RANK0
+                                                         if (RANK_ENA) then
+                                                             RODT_D0_RO[0] must be 0
+                                                         else
+                                                             RODT_D0_RO[1:0,3] must be 0
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+#else
+	uint64_t rodt_d0_r0                   : 8;
+	uint64_t rodt_d0_r1                   : 8;
+	uint64_t rodt_d1_r0                   : 8;
+	uint64_t rodt_d1_r1                   : 8;
+	uint64_t rodt_d2_r0                   : 8;
+	uint64_t rodt_d2_r1                   : 8;
+	uint64_t rodt_d3_r0                   : 8;
+	uint64_t rodt_d3_r1                   : 8;
+#endif
+	} s;
+	struct cvmx_lmcx_rodt_mask_s          cn63xx;
+	struct cvmx_lmcx_rodt_mask_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_rodt_mask cvmx_lmcx_rodt_mask_t;
+
+/**
+ * cvmx_lmc#_slot_ctl0
+ *
+ * LMC_SLOT_CTL0 = LMC Slot Control0
+ * This register is an assortment of various control fields needed by the memory controller
+ *
+ * Notes:
+ * If SW has not previously written to this register (since the last DRESET),
+ * HW updates the fields in this register to the minimum allowed value
+ * when any of LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn, LMC*_CONTROL and
+ * LMC*_MODEREG_PARAMS0 CSR's change. Ideally, only read this register
+ * after LMC has been initialized and LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn
+ * have valid data.
+ *
+ * The interpretation of the fields in this CSR depends on LMC*_CONFIG[DDR2T]:
+ *  - If LMC*_CONFIG[DDR2T]=1, (FieldValue + 4) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks.
+ *  - If LMC*_CONFIG[DDR2T]=0, (FieldValue + 3) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks. FieldValue = 0 is always illegal in this
+ *    case.
+ *
+ * The hardware-calculated minimums are:
+ *
+ * min R2R_INIT = 1 - LMC*_CONFIG[DDR2T]
+ * min R2W_INIT = 5 - LMC*_CONFIG[DDR2T] + (RL + MaxRdSkew) - (WL + MinWrSkew) + LMC*_CONTROL[BPRCH]
+ * min W2R_INIT = 2 - LMC*_CONFIG[DDR2T] + LMC*_TIMING_PARAMS1[TWTR] + WL
+ * min W2W_INIT = 1 - LMC*_CONFIG[DDR2T]
+ *
+ * where
+ *
+ * RL        = CL  + AL (LMC*_MODEREG_PARAMS0[CL] selects CL, LMC*_MODEREG_PARAMS0[AL] selects AL)
+ * WL        = CWL + AL (LMC*_MODEREG_PARAMS0[CWL] selects CWL)
+ * MaxRdSkew = max(LMC*_RLEVEL_RANKi[BYTEj]/4) + 1                          (max is across all ranks i (0..3) and bytes j (0..8))
+ * MinWrSkew = min(LMC*_WLEVEL_RANKi[BYTEj]/8) - LMC*_CONFIG[EARLY_DQX]     (min is across all ranks i (0..3) and bytes j (0..8))
+ *
+ * R2W_INIT has 1 CK cycle built in for OCTEON-internal ODT settling/channel turnaround time.
+ */
+union cvmx_lmcx_slot_ctl0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_slot_ctl0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t w2w_init                     : 6;  /**< Write-to-write spacing control
+                                                         for back to back accesses to the same rank and DIMM */
+	uint64_t w2r_init                     : 6;  /**< Write-to-read spacing control
+                                                         for back to back accesses to the same rank and DIMM */
+	uint64_t r2w_init                     : 6;  /**< Read-to-write spacing control
+                                                         for back to back accesses to the same rank and DIMM */
+	uint64_t r2r_init                     : 6;  /**< Read-to-read spacing control
+                                                         for back to back accesses to the same rank and DIMM */
+#else
+	uint64_t r2r_init                     : 6;
+	uint64_t r2w_init                     : 6;
+	uint64_t w2r_init                     : 6;
+	uint64_t w2w_init                     : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_lmcx_slot_ctl0_s          cn63xx;
+	struct cvmx_lmcx_slot_ctl0_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_slot_ctl0 cvmx_lmcx_slot_ctl0_t;
+
+/**
+ * cvmx_lmc#_slot_ctl1
+ *
+ * LMC_SLOT_CTL1 = LMC Slot Control1
+ * This register is an assortment of various control fields needed by the memory controller
+ *
+ * Notes:
+ * If SW has not previously written to this register (since the last DRESET),
+ * HW updates the fields in this register to the minimum allowed value
+ * when any of LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn, LMC*_CONTROL and
+ * LMC*_MODEREG_PARAMS0 CSR's change. Ideally, only read this register
+ * after LMC has been initialized and LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn
+ * have valid data.
+ *
+ * The interpretation of the fields in this CSR depends on LMC*_CONFIG[DDR2T]:
+ *  - If LMC*_CONFIG[DDR2T]=1, (FieldValue + 4) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks.
+ *  - If LMC*_CONFIG[DDR2T]=0, (FieldValue + 3) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks. FieldValue = 0 is always illegal in this
+ *    case.
+ *
+ * The hardware-calculated minimums are:
+ *
+ * min R2R_XRANK_INIT = 2 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew
+ * min R2W_XRANK_INIT = 5 - LMC*_CONFIG[DDR2T] + (RL + MaxRdSkew) - (WL + MinWrSkew) + LMC*_CONTROL[BPRCH]
+ * min W2R_XRANK_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxWrSkew + LMC*_CONTROL[FPRCH2]
+ * min W2W_XRANK_INIT = 4 - LMC*_CONFIG[DDR2T] + MaxWrSkew - MinWrSkew
+ *
+ * where
+ *
+ * RL        = CL  + AL (LMC*_MODEREG_PARAMS0[CL] selects CL, LMC*_MODEREG_PARAMS0[AL] selects AL)
+ * WL        = CWL + AL (LMC*_MODEREG_PARAMS0[CWL] selects CWL)
+ * MinRdSkew = min(LMC*_RLEVEL_RANKi[BYTEj]/4)                              (min is across all ranks i (0..3) and bytes j (0..8))
+ * MaxRdSkew = max(LMC*_RLEVEL_RANKi[BYTEj]/4) + 1                          (max is across all ranks i (0..3) and bytes j (0..8))
+ * MinWrSkew = min(LMC*_WLEVEL_RANKi[BYTEj]/8) - LMC*_CONFIG[EARLY_DQX]     (min is across all ranks i (0..3) and bytes j (0..8))
+ * MaxWrSkew = max(LMC*_WLEVEL_RANKi[BYTEj]/8) - LMC*_CONFIG[EARLY_DQX] + 1 (max is across all ranks i (0..3) and bytes j (0..8))
+ *
+ * R2W_XRANK_INIT has 1 extra CK cycle built in for OCTEON-internal ODT settling/channel turnaround time.
+ *
+ * W2R_XRANK_INIT has 1 extra CK cycle built in for channel turnaround time.
+ */
+union cvmx_lmcx_slot_ctl1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_slot_ctl1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t w2w_xrank_init               : 6;  /**< Write-to-write spacing control
+                                                         for back to back accesses across ranks of the same DIMM */
+	uint64_t w2r_xrank_init               : 6;  /**< Write-to-read spacing control
+                                                         for back to back accesses across ranks of the same DIMM */
+	uint64_t r2w_xrank_init               : 6;  /**< Read-to-write spacing control
+                                                         for back to back accesses across ranks of the same DIMM */
+	uint64_t r2r_xrank_init               : 6;  /**< Read-to-read spacing control
+                                                         for back to back accesses across ranks of the same DIMM */
+#else
+	uint64_t r2r_xrank_init               : 6;
+	uint64_t r2w_xrank_init               : 6;
+	uint64_t w2r_xrank_init               : 6;
+	uint64_t w2w_xrank_init               : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_lmcx_slot_ctl1_s          cn63xx;
+	struct cvmx_lmcx_slot_ctl1_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_slot_ctl1 cvmx_lmcx_slot_ctl1_t;
+
+/**
+ * cvmx_lmc#_slot_ctl2
+ *
+ * LMC_SLOT_CTL2 = LMC Slot Control2
+ * This register is an assortment of various control fields needed by the memory controller
+ *
+ * Notes:
+ * If SW has not previously written to this register (since the last DRESET),
+ * HW updates the fields in this register to the minimum allowed value
+ * when any of LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn, LMC*_CONTROL and
+ * LMC*_MODEREG_PARAMS0 CSR's change. Ideally, only read this register
+ * after LMC has been initialized and LMC*_RLEVEL_RANKn, LMC*_WLEVEL_RANKn
+ * have valid data.
+ *
+ * The interpretation of the fields in this CSR depends on LMC*_CONFIG[DDR2T]:
+ *  - If LMC*_CONFIG[DDR2T]=1, (FieldValue + 4) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks.
+ *  - If LMC*_CONFIG[DDR2T]=0, (FieldValue + 3) is the minimum CK cycles
+ *    between when the DRAM part registers CAS commands of the 1st and 2nd types
+ *    from different cache blocks. FieldValue = 0 is always illegal in this
+ *    case.
+ *
+ * The hardware-calculated minimums are:
+ *
+ * min R2R_XDIMM_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxRdSkew - MinRdSkew
+ * min R2W_XDIMM_INIT = 6 - LMC*_CONFIG[DDR2T] + (RL + MaxRdSkew) - (WL + MinWrSkew) + LMC*_CONTROL[BPRCH]
+ * min W2R_XDIMM_INIT = 3 - LMC*_CONFIG[DDR2T] + MaxWrSkew + LMC*_CONTROL[FPRCH2]
+ * min W2W_XDIMM_INIT = 5 - LMC*_CONFIG[DDR2T] + MaxWrSkew - MinWrSkew
+ *
+ * where
+ *
+ * RL        = CL  + AL (LMC*_MODEREG_PARAMS0[CL] selects CL, LMC*_MODEREG_PARAMS0[AL] selects AL)
+ * WL        = CWL + AL (LMC*_MODEREG_PARAMS0[CWL] selects CWL)
+ * MinRdSkew = min(LMC*_RLEVEL_RANKi[BYTEj]/4)                              (min is across all ranks i (0..3) and bytes j (0..8))
+ * MaxRdSkew = max(LMC*_RLEVEL_RANKi[BYTEj]/4) + 1                          (max is across all ranks i (0..3) and bytes j (0..8))
+ * MinWrSkew = min(LMC*_WLEVEL_RANKi[BYTEj]/8) - LMC*_CONFIG[EARLY_DQX]     (min is across all ranks i (0..3) and bytes j (0..8))
+ * MaxWrSkew = max(LMC*_WLEVEL_RANKi[BYTEj]/8) - LMC*_CONFIG[EARLY_DQX] + 1 (max is across all ranks i (0..3) and bytes j (0..8))
+ *
+ * R2W_XDIMM_INIT has 2 extra CK cycles built in for OCTEON-internal ODT settling/channel turnaround time.
+ *
+ * R2R_XDIMM_INIT, W2R_XRANK_INIT, W2W_XDIMM_INIT have 1 extra CK cycle built in for channel turnaround time.
+ */
+union cvmx_lmcx_slot_ctl2
+{
+	uint64_t u64;
+	struct cvmx_lmcx_slot_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t w2w_xdimm_init               : 6;  /**< Write-to-write spacing control
+                                                         for back to back accesses across DIMMs */
+	uint64_t w2r_xdimm_init               : 6;  /**< Write-to-read spacing control
+                                                         for back to back accesses across DIMMs */
+	uint64_t r2w_xdimm_init               : 6;  /**< Read-to-write spacing control
+                                                         for back to back accesses across DIMMs */
+	uint64_t r2r_xdimm_init               : 6;  /**< Read-to-read spacing control
+                                                         for back to back accesses across DIMMs */
+#else
+	uint64_t r2r_xdimm_init               : 6;
+	uint64_t r2w_xdimm_init               : 6;
+	uint64_t w2r_xdimm_init               : 6;
+	uint64_t w2w_xdimm_init               : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_lmcx_slot_ctl2_s          cn63xx;
+	struct cvmx_lmcx_slot_ctl2_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_slot_ctl2 cvmx_lmcx_slot_ctl2_t;
+
+/**
+ * cvmx_lmc#_timing_params0
+ */
+union cvmx_lmcx_timing_params0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_timing_params0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)]-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLK constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLK(ns)/(256*tCYC(ns))],
+                                                         where tDLLK is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t tckeon                       : 10; /**< Reserved. Should be written to zero. */
+#else
+	uint64_t tckeon                       : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t trp_ext                      : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_lmcx_timing_params0_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t trp_ext                      : 1;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)]-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLK constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLK(ns)/(256*tCYC(ns))],
+                                                         where tDLLK is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t reserved_0_9                 : 10;
+#else
+	uint64_t reserved_0_9                 : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t trp_ext                      : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} cn63xx;
+	struct cvmx_lmcx_timing_params0_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t tcksre                       : 4;  /**< Indicates tCKSRE constraints.
+                                                         Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1,
+                                                         where tCKSRE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, 10ns) */
+	uint64_t trp                          : 4;  /**< Indicates tRP constraints.
+                                                         Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)]
+                                                         + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1,
+                                                         where tRP, tRTP are from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP tRP=10-15ns
+                                                         TYP tRTP=max(4nCK, 7.5ns) */
+	uint64_t tzqinit                      : 4;  /**< Indicates tZQINIT constraints.
+                                                         Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))],
+                                                         where tZQINIT is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512) */
+	uint64_t tdllk                        : 4;  /**< Indicates tDLLK constraints.
+                                                         Set TDLLK (CSR field) = RNDUP[tDLLK(ns)/(256*tCYC(ns))],
+                                                         where tDLLK is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=2 (equivalent to 512)
+                                                         This parameter is used in self-refresh exit
+                                                         and assumed to be greater than tRFC */
+	uint64_t tmod                         : 4;  /**< Indicates tMOD constraints.
+                                                         Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1,
+                                                         where tMOD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(12nCK, 15ns) */
+	uint64_t tmrd                         : 4;  /**< Indicates tMRD constraints.
+                                                         Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1,
+                                                         where tMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4nCK */
+	uint64_t txpr                         : 4;  /**< Indicates tXPR constraints.
+                                                         Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))],
+                                                         where tXPR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(5nCK, tRFC+10ns) */
+	uint64_t tcke                         : 4;  /**< Indicates tCKE constraints.
+                                                         Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1,
+                                                         where tCKE is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5/5.625/5.625/5ns) */
+	uint64_t tzqcs                        : 4;  /**< Indicates tZQCS constraints.
+                                                         Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))],
+                                                         where tZQCS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=4 (equivalent to 64) */
+	uint64_t tckeon                       : 10; /**< Reserved. Should be written to zero. */
+#else
+	uint64_t tckeon                       : 10;
+	uint64_t tzqcs                        : 4;
+	uint64_t tcke                         : 4;
+	uint64_t txpr                         : 4;
+	uint64_t tmrd                         : 4;
+	uint64_t tmod                         : 4;
+	uint64_t tdllk                        : 4;
+	uint64_t tzqinit                      : 4;
+	uint64_t trp                          : 4;
+	uint64_t tcksre                       : 4;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_timing_params0 cvmx_lmcx_timing_params0_t;
+
+/**
+ * cvmx_lmc#_timing_params1
+ */
+union cvmx_lmcx_timing_params1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_timing_params1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t tras_ext                     : 1;  /**< Indicates tRAS constraints.
+                                                         Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 000000: RESERVED
+                                                             - 000001: 2 tCYC
+                                                             - 000010: 3 tCYC
+                                                             - ...
+                                                             - 111111: 64 tCYC */
+	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
+                                                         Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
+                                                         where tXPDLL is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(10nCK, 24ns) */
+	uint64_t tfaw                         : 5;  /**< Indicates tFAW constraints.
+                                                         Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))],
+                                                         where tFAW is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=30-40ns */
+	uint64_t twldqsen                     : 4;  /**< Indicates tWLDQSEN constraints.
+                                                         Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))],
+                                                         where tWLDQSEN is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(25nCK) */
+	uint64_t twlmrd                       : 4;  /**< Indicates tWLMRD constraints.
+                                                         Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))],
+                                                         where tWLMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(40nCK) */
+	uint64_t txp                          : 3;  /**< Indicates tXP constraints.
+                                                         Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1,
+                                                         where tXP is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5ns) */
+	uint64_t trrd                         : 3;  /**< Indicates tRRD constraints.
+                                                         Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2,
+                                                         where tRRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 10ns)
+                                                            - 000: RESERVED
+                                                            - 001: 3 tCYC
+                                                            - ...
+                                                            - 110: 8 tCYC
+                                                            - 111: 9 tCYC */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))],
+                                                         where tRFC is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=90-350ns
+                                                              - 00000: RESERVED
+                                                              - 00001: 8 tCYC
+                                                              - 00010: 16 tCYC
+                                                              - 00011: 24 tCYC
+                                                              - 00100: 32 tCYC
+                                                              - ...
+                                                              - 11110: 240 tCYC
+                                                              - 11111: 248 tCYC */
+	uint64_t twtr                         : 4;  /**< Indicates tWTR constraints.
+                                                         Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1,
+                                                         where tWTR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 7.5ns)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2
+                                                             - ...
+                                                             - 0111: 8
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< Indicates tRCD constraints.
+                                                         Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)],
+                                                         where tRCD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=10-15ns
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
+                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 00000: RESERVED
+                                                             - 00001: 2 tCYC
+                                                             - 00010: 3 tCYC
+                                                             - ...
+                                                             - 11111: 32 tCYC */
+	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
+                                                         Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
+                                                         where tMPRR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=1nCK */
+#else
+	uint64_t tmprr                        : 4;
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trfc                         : 5;
+	uint64_t trrd                         : 3;
+	uint64_t txp                          : 3;
+	uint64_t twlmrd                       : 4;
+	uint64_t twldqsen                     : 4;
+	uint64_t tfaw                         : 5;
+	uint64_t txpdll                       : 5;
+	uint64_t tras_ext                     : 1;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_lmcx_timing_params1_s     cn63xx;
+	struct cvmx_lmcx_timing_params1_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t txpdll                       : 5;  /**< Indicates tXPDLL constraints.
+                                                         Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1,
+                                                         where tXPDLL is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(10nCK, 24ns) */
+	uint64_t tfaw                         : 5;  /**< Indicates tFAW constraints.
+                                                         Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))],
+                                                         where tFAW is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=30-40ns */
+	uint64_t twldqsen                     : 4;  /**< Indicates tWLDQSEN constraints.
+                                                         Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))],
+                                                         where tWLDQSEN is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(25nCK) */
+	uint64_t twlmrd                       : 4;  /**< Indicates tWLMRD constraints.
+                                                         Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))],
+                                                         where tWLMRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(40nCK) */
+	uint64_t txp                          : 3;  /**< Indicates tXP constraints.
+                                                         Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1,
+                                                         where tXP is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(3nCK, 7.5ns) */
+	uint64_t trrd                         : 3;  /**< Indicates tRRD constraints.
+                                                         Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2,
+                                                         where tRRD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 10ns)
+                                                            - 000: RESERVED
+                                                            - 001: 3 tCYC
+                                                            - ...
+                                                            - 110: 8 tCYC
+                                                            - 111: 9 tCYC */
+	uint64_t trfc                         : 5;  /**< Indicates tRFC constraints.
+                                                         Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))],
+                                                         where tRFC is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=90-350ns
+                                                              - 00000: RESERVED
+                                                              - 00001: 8 tCYC
+                                                              - 00010: 16 tCYC
+                                                              - 00011: 24 tCYC
+                                                              - 00100: 32 tCYC
+                                                              - ...
+                                                              - 11110: 240 tCYC
+                                                              - 11111: 248 tCYC */
+	uint64_t twtr                         : 4;  /**< Indicates tWTR constraints.
+                                                         Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1,
+                                                         where tWTR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=max(4nCK, 7.5ns)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2
+                                                             - ...
+                                                             - 0111: 8
+                                                             - 1000-1111: RESERVED */
+	uint64_t trcd                         : 4;  /**< Indicates tRCD constraints.
+                                                         Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)],
+                                                         where tRCD is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=10-15ns
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+	uint64_t tras                         : 5;  /**< Indicates tRAS constraints.
+                                                         Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1,
+                                                         where tRAS is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=35ns-9*tREFI
+                                                             - 00000: RESERVED
+                                                             - 00001: 2 tCYC
+                                                             - 00010: 3 tCYC
+                                                             - ...
+                                                             - 11111: 32 tCYC */
+	uint64_t tmprr                        : 4;  /**< Indicates tMPRR constraints.
+                                                         Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1,
+                                                         where tMPRR is from the DDR3 spec, and tCYC(ns)
+                                                         is the DDR clock frequency (not data rate).
+                                                         TYP=1nCK */
+#else
+	uint64_t tmprr                        : 4;
+	uint64_t tras                         : 5;
+	uint64_t trcd                         : 4;
+	uint64_t twtr                         : 4;
+	uint64_t trfc                         : 5;
+	uint64_t trrd                         : 3;
+	uint64_t txp                          : 3;
+	uint64_t twlmrd                       : 4;
+	uint64_t twldqsen                     : 4;
+	uint64_t tfaw                         : 5;
+	uint64_t txpdll                       : 5;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_timing_params1 cvmx_lmcx_timing_params1_t;
+
+/**
+ * cvmx_lmc#_tro_ctl
+ *
+ * LMC_TRO_CTL = LMC Temperature Ring Osc Control
+ * This register is an assortment of various control fields needed to control the temperature ring oscillator
+ *
+ * Notes:
+ * To bring up the temperature ring oscillator, write TRESET to 0, and follow by initializing RCLK_CNT to desired
+ * value
+ */
+union cvmx_lmcx_tro_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_tro_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t rclk_cnt                     : 32; /**< rclk counter */
+	uint64_t treset                       : 1;  /**< Reset ring oscillator */
+#else
+	uint64_t treset                       : 1;
+	uint64_t rclk_cnt                     : 32;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_lmcx_tro_ctl_s            cn63xx;
+	struct cvmx_lmcx_tro_ctl_s            cn63xxp1;
+};
+typedef union cvmx_lmcx_tro_ctl cvmx_lmcx_tro_ctl_t;
+
+/**
+ * cvmx_lmc#_tro_stat
+ *
+ * LMC_TRO_STAT = LMC Temperature Ring Osc Status
+ * This register is an assortment of various control fields needed to control the temperature ring oscillator
+ */
+union cvmx_lmcx_tro_stat
+{
+	uint64_t u64;
+	struct cvmx_lmcx_tro_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ring_cnt                     : 32; /**< ring counter */
+#else
+	uint64_t ring_cnt                     : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_tro_stat_s           cn63xx;
+	struct cvmx_lmcx_tro_stat_s           cn63xxp1;
+};
+typedef union cvmx_lmcx_tro_stat cvmx_lmcx_tro_stat_t;
+
+/**
+ * cvmx_lmc#_wlevel_ctl
+ */
+union cvmx_lmcx_wlevel_ctl
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wlevel_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t rtt_nom                      : 3;  /**< RTT_NOM
+                                                         LMC writes a decoded value to MR1[Rtt_Nom] of the rank during
+                                                         write leveling. Per JEDEC DDR3 specifications,
+                                                         only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6)
+                                                         are allowed during write leveling with output buffer enabled.
+                                                         000 : LMC writes 001 (RZQ/4)   to MR1[Rtt_Nom]
+                                                         001 : LMC writes 010 (RZQ/2)   to MR1[Rtt_Nom]
+                                                         010 : LMC writes 011 (RZQ/6)   to MR1[Rtt_Nom]
+                                                         011 : LMC writes 100 (RZQ/12)  to MR1[Rtt_Nom]
+                                                         100 : LMC writes 101 (RZQ/8)   to MR1[Rtt_Nom]
+                                                         101 : LMC writes 110 (Rsvd)    to MR1[Rtt_Nom]
+                                                         110 : LMC writes 111 (Rsvd)    to  MR1[Rtt_Nom]
+                                                         111 : LMC writes 000 (Disabled) to MR1[Rtt_Nom] */
+	uint64_t bitmask                      : 8;  /**< Mask to select bit lanes on which write-leveling
+                                                         feedback is returned when OR_DIS is set to 1 */
+	uint64_t or_dis                       : 1;  /**< Disable or'ing of bits in a byte lane when computing
+                                                         the write-leveling bitmask */
+	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
+	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
+                                                         the write-leveling sequence
+                                                         Used with x16 parts where the upper and lower byte
+                                                         lanes need to be leveled independently */
+#else
+	uint64_t lanemask                     : 9;
+	uint64_t sset                         : 1;
+	uint64_t or_dis                       : 1;
+	uint64_t bitmask                      : 8;
+	uint64_t rtt_nom                      : 3;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_lmcx_wlevel_ctl_s         cn63xx;
+	struct cvmx_lmcx_wlevel_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t sset                         : 1;  /**< Run write-leveling on the current setting only. */
+	uint64_t lanemask                     : 9;  /**< One-hot mask to select byte lane to be leveled by
+                                                         the write-leveling sequence
+                                                         Used with x16 parts where the upper and lower byte
+                                                         lanes need to be leveled independently */
+#else
+	uint64_t lanemask                     : 9;
+	uint64_t sset                         : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_lmcx_wlevel_ctl cvmx_lmcx_wlevel_ctl_t;
+
+/**
+ * cvmx_lmc#_wlevel_dbg
+ *
+ * Notes:
+ * A given write of LMC*_WLEVEL_DBG returns the write-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW write-leveled.
+ * LMC*_WLEVEL_DBG[BYTE] selects the particular byte.
+ * To get these pass/fail results for another different rank, you must run the hardware write-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run write-leveling separately for each rank, probing LMC*_WLEVEL_DBG between each
+ * write-leveling.
+ */
+union cvmx_lmcx_wlevel_dbg
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wlevel_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t bitmask                      : 8;  /**< Bitmask generated during deskew settings sweep
+                                                         if LMCX_WLEVEL_CTL[SSET]=0
+                                                           BITMASK[n]=0 means deskew setting n failed
+                                                           BITMASK[n]=1 means deskew setting n passed
+                                                           for 0 <= n <= 7
+                                                           BITMASK contains the first 8 results of the total 16
+                                                           collected by LMC during the write-leveling sequence
+                                                         else if LMCX_WLEVEL_CTL[SSET]=1
+                                                           BITMASK[0]=0 means curr deskew setting failed
+                                                           BITMASK[0]=1 means curr deskew setting passed */
+	uint64_t byte                         : 4;  /**< 0 <= BYTE <= 8 */
+#else
+	uint64_t byte                         : 4;
+	uint64_t bitmask                      : 8;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_lmcx_wlevel_dbg_s         cn63xx;
+	struct cvmx_lmcx_wlevel_dbg_s         cn63xxp1;
+};
+typedef union cvmx_lmcx_wlevel_dbg cvmx_lmcx_wlevel_dbg_t;
+
+/**
+ * cvmx_lmc#_wlevel_rank#
+ *
+ * Notes:
+ * This is four CSRs per LMC, one per each rank.
+ *
+ * Deskew setting is measured in units of 1/8 CK, so the above BYTE* values can range over 4 CKs.
+ *
+ * Assuming LMC*_WLEVEL_CTL[SSET]=0, the BYTE*<2:0> values are not used during write-leveling, and
+ * they are over-written by the hardware as part of the write-leveling sequence. (HW sets STATUS==3
+ * after HW write-leveling completes for the rank). SW needs to set BYTE*<4:3> bits.
+ *
+ * Each CSR may also be written by SW, but not while a write-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ *
+ * SW initiates a HW write-leveling sequence by programming LMC*_WLEVEL_CTL and writing RANKMASK and INIT_START=1 with SEQUENCE=6 in LMC*_CONFIG.
+ * LMC will then step through and accumulate write leveling results for 8 unique delay settings (twice), starting at a delay of
+ * LMC*_WLEVEL_RANKn[BYTE*<4:3>]*8 CK increasing by 1/8 CK each setting. HW will then set LMC*_WLEVEL_RANKi[BYTE*<2:0>] to indicate the
+ * first write leveling result of '1' that followed a reslt of '0' during the sequence by searching for a '1100' pattern in the generated
+ * bitmask, except that LMC will always write LMC*_WLEVEL_RANKi[BYTE*<0>]=0. If HW is unable to find a match for a '1100' pattern, then HW will
+ * set LMC*_WLEVEL_RANKi[BYTE*<2:0>] to 4.
+ * See LMC*_WLEVEL_CTL.
+ *
+ * LMC*_WLEVEL_RANKi values for ranks i without attached DRAM should be set such that
+ * they do not increase the range of possible BYTE values for any byte
+ * lane. The easiest way to do this is to set
+ *     LMC*_WLEVEL_RANKi = LMC*_WLEVEL_RANKj,
+ * where j is some rank with attached DRAM whose LMC*_WLEVEL_RANKj is already fully initialized.
+ */
+union cvmx_lmcx_wlevel_rankx
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wlevel_rankx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_47_63               : 17;
+	uint64_t status                       : 2;  /**< Indicates status of the write-leveling and where
+                                                         the BYTE* programmings in <44:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = write-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete write-leveling sequence, irrespective of
+                                                             which lanes are masked via LMC*WLEVEL_CTL[LANEMASK] */
+	uint64_t byte8                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE8 must be zero during normal operation.
+                                                         When ECC DRAM is not present (i.e. when DRAM is not
+                                                         attached to chip signals DDR_CBS_0_* and DDR_CB[7:0]),
+                                                         SW should write BYTE8 with a value that does
+                                                         not increase the range of possible BYTE* values. The
+                                                         easiest way to do this is to set
+                                                         LMC*_WLEVEL_RANK*[BYTE8] = LMC*_WLEVEL_RANK*[BYTE0]
+                                                         when there is no ECC DRAM, using the final BYTE0 value. */
+	uint64_t byte7                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE7 must be zero during normal operation */
+	uint64_t byte6                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE6 must be zero during normal operation */
+	uint64_t byte5                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE5 must be zero during normal operation */
+	uint64_t byte4                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE4 must be zero during normal operation */
+	uint64_t byte3                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE3 must be zero during normal operation */
+	uint64_t byte2                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE2 must be zero during normal operation */
+	uint64_t byte1                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE1 must be zero during normal operation */
+	uint64_t byte0                        : 5;  /**< Deskew setting
+                                                         Bit 0 of BYTE0 must be zero during normal operation */
+#else
+	uint64_t byte0                        : 5;
+	uint64_t byte1                        : 5;
+	uint64_t byte2                        : 5;
+	uint64_t byte3                        : 5;
+	uint64_t byte4                        : 5;
+	uint64_t byte5                        : 5;
+	uint64_t byte6                        : 5;
+	uint64_t byte7                        : 5;
+	uint64_t byte8                        : 5;
+	uint64_t status                       : 2;
+	uint64_t reserved_47_63               : 17;
+#endif
+	} s;
+	struct cvmx_lmcx_wlevel_rankx_s       cn63xx;
+	struct cvmx_lmcx_wlevel_rankx_s       cn63xxp1;
+};
+typedef union cvmx_lmcx_wlevel_rankx cvmx_lmcx_wlevel_rankx_t;
+
+/**
+ * cvmx_lmc#_wodt_ctl0
+ *
+ * LMC_WODT_CTL0 = LMC Write OnDieTermination control
+ * See the description in LMC_WODT_CTL1.
+ *
+ * Notes:
+ * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.  See LMC_WODT_CTL1.
+ *
+ */
+union cvmx_lmcx_wodt_ctl0
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wodt_ctl0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wodt_d1_r1                   : 8;  /**< Write ODT mask DIMM1, RANK1 */
+	uint64_t wodt_d1_r0                   : 8;  /**< Write ODT mask DIMM1, RANK0 */
+	uint64_t wodt_d0_r1                   : 8;  /**< Write ODT mask DIMM0, RANK1 */
+	uint64_t wodt_d0_r0                   : 8;  /**< Write ODT mask DIMM0, RANK0 */
+#else
+	uint64_t wodt_d0_r0                   : 8;
+	uint64_t wodt_d0_r1                   : 8;
+	uint64_t wodt_d1_r0                   : 8;
+	uint64_t wodt_d1_r1                   : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn31xx;
+	struct cvmx_lmcx_wodt_ctl0_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wodt_hi3                     : 4;  /**< Write ODT mask for position 3, data[127:64] */
+	uint64_t wodt_hi2                     : 4;  /**< Write ODT mask for position 2, data[127:64] */
+	uint64_t wodt_hi1                     : 4;  /**< Write ODT mask for position 1, data[127:64] */
+	uint64_t wodt_hi0                     : 4;  /**< Write ODT mask for position 0, data[127:64] */
+	uint64_t wodt_lo3                     : 4;  /**< Write ODT mask for position 3, data[ 63: 0] */
+	uint64_t wodt_lo2                     : 4;  /**< Write ODT mask for position 2, data[ 63: 0] */
+	uint64_t wodt_lo1                     : 4;  /**< Write ODT mask for position 1, data[ 63: 0] */
+	uint64_t wodt_lo0                     : 4;  /**< Write ODT mask for position 0, data[ 63: 0] */
+#else
+	uint64_t wodt_lo0                     : 4;
+	uint64_t wodt_lo1                     : 4;
+	uint64_t wodt_lo2                     : 4;
+	uint64_t wodt_lo3                     : 4;
+	uint64_t wodt_hi0                     : 4;
+	uint64_t wodt_hi1                     : 4;
+	uint64_t wodt_hi2                     : 4;
+	uint64_t wodt_hi3                     : 4;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_lmcx_wodt_ctl0_cn38xx     cn38xxp2;
+	struct cvmx_lmcx_wodt_ctl0_cn38xx     cn50xx;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn52xx;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn52xxp1;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn56xx;
+	struct cvmx_lmcx_wodt_ctl0_cn30xx     cn56xxp1;
+	struct cvmx_lmcx_wodt_ctl0_cn38xx     cn58xx;
+	struct cvmx_lmcx_wodt_ctl0_cn38xx     cn58xxp1;
+};
+typedef union cvmx_lmcx_wodt_ctl0 cvmx_lmcx_wodt_ctl0_t;
+
+/**
+ * cvmx_lmc#_wodt_ctl1
+ *
+ * LMC_WODT_CTL1 = LMC Write OnDieTermination control
+ * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations
+ * (667MHz and faster), especially on a multi-rank system. DDR2 DQ/DM/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that DIMM. System designers may prefer different combinations of ODT ON's for read and write
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a write to that rank, it sets the 8 ODT pins to the MASK pins below.
+ * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines
+ * with the resistor on Dimm0/Rank1. The mask WODT_D0_R0 would then be [00000010].
+ * If ODT feature is not desired, the DDR parts can be programmed to not look at these pins by
+ * writing 0 in QS_DIC. Octeon drives the appropriate mask values on the ODT pins by default.
+ * If this feature is not required, write 0 in this register.
+ *
+ * Notes:
+ * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.
+ * When a given RANK is selected, the WODT mask for that RANK is used.  The resulting WODT mask is
+ * driven to the DIMMs in the following manner:
+ *            BUNK_ENA=1     BUNK_ENA=0
+ * Mask[7] -> DIMM3, RANK1    DIMM3
+ * Mask[6] -> DIMM3, RANK0
+ * Mask[5] -> DIMM2, RANK1    DIMM2
+ * Mask[4] -> DIMM2, RANK0
+ * Mask[3] -> DIMM1, RANK1    DIMM1
+ * Mask[2] -> DIMM1, RANK0
+ * Mask[1] -> DIMM0, RANK1    DIMM0
+ * Mask[0] -> DIMM0, RANK0
+ */
+union cvmx_lmcx_wodt_ctl1
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wodt_ctl1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wodt_d3_r1                   : 8;  /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked */
+	uint64_t wodt_d3_r0                   : 8;  /**< Write ODT mask DIMM3, RANK0 */
+	uint64_t wodt_d2_r1                   : 8;  /**< Write ODT mask DIMM2, RANK1/DIMM2 in SingleRanked */
+	uint64_t wodt_d2_r0                   : 8;  /**< Write ODT mask DIMM2, RANK0 */
+#else
+	uint64_t wodt_d2_r0                   : 8;
+	uint64_t wodt_d2_r1                   : 8;
+	uint64_t wodt_d3_r0                   : 8;
+	uint64_t wodt_d3_r1                   : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_lmcx_wodt_ctl1_s          cn30xx;
+	struct cvmx_lmcx_wodt_ctl1_s          cn31xx;
+	struct cvmx_lmcx_wodt_ctl1_s          cn52xx;
+	struct cvmx_lmcx_wodt_ctl1_s          cn52xxp1;
+	struct cvmx_lmcx_wodt_ctl1_s          cn56xx;
+	struct cvmx_lmcx_wodt_ctl1_s          cn56xxp1;
+};
+typedef union cvmx_lmcx_wodt_ctl1 cvmx_lmcx_wodt_ctl1_t;
+
+/**
+ * cvmx_lmc#_wodt_mask
+ *
+ * LMC_WODT_MASK = LMC Write OnDieTermination mask
+ * System designers may desire to terminate DQ/DQS lines for higher frequency DDR operations
+ * especially on a multi-rank system. DDR3 DQ/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that DIMM. System designers may prefer different combinations of ODT ON's for writes
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a write to that rank, it sets the 4 ODT pins to the MASK pins below.
+ * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines
+ * with the resistor on DIMM0/Rank1. The mask WODT_D0_R0 would then be [00000010].
+ * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not
+ * required, write 0 in this register.
+ *
+ * Notes:
+ * When a given RANK is selected, the WODT mask for that RANK is used.  The resulting WODT mask is
+ * driven to the DIMMs in the following manner:
+ *             RANK_ENA=1                    RANK_ENA=0
+ * Mask[3] -> DIMM1_ODT_1                     MBZ
+ * Mask[2] -> DIMM1_ODT_0                     DIMM1_ODT_0
+ * Mask[1] -> DIMM0_ODT_1                     MBZ
+ * Mask[0] -> DIMM0_ODT_0                     DIMM0_ODT_0
+ *
+ * LMC always writes entire cache blocks and always writes them via two consecutive
+ * write CAS operations to the same rank+bank+row spaced exactly 4 CK's apart.
+ * When a WODT mask bit is set, LMC asserts the OCTEON ODT output
+ * pin(s) starting the same CK as the first write CAS operation. Then, OCTEON
+ * normally continues to assert the ODT output pin(s) for 9+LMC*_CONTROL[WODT_BPRCH] more CK's
+ * - for a total of 10+LMC*_CONTROL[WODT_BPRCH] CK's for the entire cache block write -
+ * through the second write CAS operation of the cache block,
+ * satisfying the 6 CK DDR3 ODTH8 requirements.
+ * But it is possible for OCTEON to issue two cache block writes separated by as few as
+ * WtW = 8 or 9 (10 if LMC*_CONTROL[WODT_BPRCH]=1) CK's. In that case, OCTEON asserts the ODT output pin(s)
+ * for the WODT mask of the first cache block write for WtW CK's, then asserts
+ * the ODT output pin(s) for the WODT mask of the second cache block write for 10+LMC*_CONTROL[WODT_BPRCH] CK's
+ * (or less if a third cache block write follows within 8 or 9 (or 10) CK's of this second cache block write).
+ * Note that it may be necessary to force LMC to space back-to-back cache block writes
+ * to different ranks apart by at least 10+LMC*_CONTROL[WODT_BPRCH] CK's to prevent DDR3 ODTH8 violations.
+ */
+union cvmx_lmcx_wodt_mask
+{
+	uint64_t u64;
+	struct cvmx_lmcx_wodt_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wodt_d3_r1                   : 8;  /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d3_r0                   : 8;  /**< Write ODT mask DIMM3, RANK0
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d2_r1                   : 8;  /**< Write ODT mask DIMM2, RANK1/DIMM2 in SingleRanked
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d2_r0                   : 8;  /**< Write ODT mask DIMM2, RANK0
+                                                         *UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d1_r1                   : 8;  /**< Write ODT mask DIMM1, RANK1/DIMM1 in SingleRanked
+                                                         if (!RANK_ENA) then WODT_D1_R1[3:0] MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d1_r0                   : 8;  /**< Write ODT mask DIMM1, RANK0
+                                                         if (!RANK_ENA) then WODT_D1_R0[3,1] MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d0_r1                   : 8;  /**< Write ODT mask DIMM0, RANK1/DIMM0 in SingleRanked
+                                                         if (!RANK_ENA) then WODT_D0_R1[3:0] MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+	uint64_t wodt_d0_r0                   : 8;  /**< Write ODT mask DIMM0, RANK0
+                                                         if (!RANK_ENA) then WODT_D0_R0[3,1] MBZ
+                                                         *Upper 4 bits UNUSED IN 63xx, and MBZ* */
+#else
+	uint64_t wodt_d0_r0                   : 8;
+	uint64_t wodt_d0_r1                   : 8;
+	uint64_t wodt_d1_r0                   : 8;
+	uint64_t wodt_d1_r1                   : 8;
+	uint64_t wodt_d2_r0                   : 8;
+	uint64_t wodt_d2_r1                   : 8;
+	uint64_t wodt_d3_r0                   : 8;
+	uint64_t wodt_d3_r1                   : 8;
+#endif
+	} s;
+	struct cvmx_lmcx_wodt_mask_s          cn63xx;
+	struct cvmx_lmcx_wodt_mask_s          cn63xxp1;
+};
+typedef union cvmx_lmcx_wodt_mask cvmx_lmcx_wodt_mask_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-log-arc.S b/sys/contrib/octeon-sdk/cvmx-log-arc.S
index c60462b..f57456a 100644
--- a/sys/contrib/octeon-sdk/cvmx-log-arc.S
+++ b/sys/contrib/octeon-sdk/cvmx-log-arc.S
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -7,33 +7,34 @@
  * modification, are permitted provided that the following conditions are
  * met:
  *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.  
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries. 
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 //
 // The function defined here is called for every function as it is executed.
 // These calls are automatically inserted by GCC when the switch "-pg" is
diff --git a/sys/contrib/octeon-sdk/cvmx-log.c b/sys/contrib/octeon-sdk/cvmx-log.c
index b3aeb90..ea03d99 100644
--- a/sys/contrib/octeon-sdk/cvmx-log.c
+++ b/sys/contrib/octeon-sdk/cvmx-log.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -48,9 +50,10 @@
  * log data to a differnet buffer to avoid synchronization overhead. Function
  * call logging can be turned on with the GCC option "-pg".
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #include "cvmx.h"
+#include "cvmx-core.h"
 #include "cvmx-log.h"
 
 #define CVMX_LOG_BUFFER_SIZE (1<<15)
@@ -382,16 +385,16 @@ void cvmx_log_structure(const char *type, void *data, int size_in_bytes)
  * @param counter1 Event type for counter 1
  * @param counter2 Event type for counter 2
  */
-void cvmx_log_perf_setup(cvmx_log_perf_event_t counter1, cvmx_log_perf_event_t counter2)
+void cvmx_log_perf_setup(cvmx_core_perf_t counter1, cvmx_core_perf_t counter2)
 {
-    cvmx_log_perf_control_t control;
+    cvmx_core_perf_control_t control;
 
     control.u32 = 0;
     control.s.event = counter1;
-    control.s.U = 1;
-    control.s.S = 1;
-    control.s.K = 1;
-    control.s.EX = 1;
+    control.s.u = 1;
+    control.s.s = 1;
+    control.s.k = 1;
+    control.s.ex = 1;
     asm ("mtc0 %0, $25, 0\n" : : "r"(control.u32));
     control.s.event = counter2;
     asm ("mtc0 %0, $25, 2\n" : : "r"(control.u32));
diff --git a/sys/contrib/octeon-sdk/cvmx-log.h b/sys/contrib/octeon-sdk/cvmx-log.h
index 8b6e4c5..87fb61c 100644
--- a/sys/contrib/octeon-sdk/cvmx-log.h
+++ b/sys/contrib/octeon-sdk/cvmx-log.h
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 #ifndef __CVMX_LOG_H__
 #define __CVMX_LOG_H__
 
@@ -50,94 +52,13 @@
  * log data to a differnet buffer to avoid synchronization overhead. Function
  * call logging can be turned on with the GCC option "-pg".
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-/**
- * Enumeration of all supported performance counter types
- */
-typedef enum
-{
-    CVMX_LOG_PERF_CNT_NONE      = 0,    /**< Turn off the performance counter */
-    CVMX_LOG_PERF_CNT_CLK       = 1,    /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */
-    CVMX_LOG_PERF_CNT_ISSUE     = 2,    /**< Instructions issued but not retired */
-    CVMX_LOG_PERF_CNT_RET       = 3,    /**< Instructions retired */
-    CVMX_LOG_PERF_CNT_NISSUE    = 4,    /**< Cycles no issue */
-    CVMX_LOG_PERF_CNT_SISSUE    = 5,    /**< Cycles single issue */
-    CVMX_LOG_PERF_CNT_DISSUE    = 6,    /**< Cycles dual issue */
-    CVMX_LOG_PERF_CNT_IFI       = 7,    /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */
-    CVMX_LOG_PERF_CNT_BR        = 8,    /**< Branches retired */
-    CVMX_LOG_PERF_CNT_BRMIS     = 9,    /**< Branch mispredicts */
-    CVMX_LOG_PERF_CNT_J         = 10,   /**< Jumps retired */
-    CVMX_LOG_PERF_CNT_JMIS      = 11,   /**< Jumps mispredicted */
-    CVMX_LOG_PERF_CNT_REPLAY    = 12,   /**< Mem Replays */
-    CVMX_LOG_PERF_CNT_IUNA      = 13,   /**< Cycles idle due to unaligned_replays */
-    CVMX_LOG_PERF_CNT_TRAP      = 14,   /**< trap_6a signal */
-    CVMX_LOG_PERF_CNT_UULOAD    = 16,   /**< Unexpected unaligned loads (REPUN=1) */
-    CVMX_LOG_PERF_CNT_UUSTORE   = 17,   /**< Unexpected unaligned store (REPUN=1) */
-    CVMX_LOG_PERF_CNT_ULOAD     = 18,   /**< Unaligned loads (REPUN=1 or USEUN=1) */
-    CVMX_LOG_PERF_CNT_USTORE    = 19,   /**< Unaligned store (REPUN=1 or USEUN=1) */
-    CVMX_LOG_PERF_CNT_EC        = 20,   /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */
-    CVMX_LOG_PERF_CNT_MC        = 21,   /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */
-    CVMX_LOG_PERF_CNT_CC        = 22,   /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */
-    CVMX_LOG_PERF_CNT_CSRC      = 23,   /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */
-    CVMX_LOG_PERF_CNT_CFETCH    = 24,   /**< Icache committed fetches (demand+prefetch) */
-    CVMX_LOG_PERF_CNT_CPREF     = 25,   /**< Icache committed prefetches */
-    CVMX_LOG_PERF_CNT_ICA       = 26,   /**< Icache aliases */
-    CVMX_LOG_PERF_CNT_II        = 27,   /**< Icache invalidates */
-    CVMX_LOG_PERF_CNT_IP        = 28,   /**< Icache parity error */
-    CVMX_LOG_PERF_CNT_CIMISS    = 29,   /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */
-    CVMX_LOG_PERF_CNT_WBUF      = 32,   /**< Number of write buffer entries created */
-    CVMX_LOG_PERF_CNT_WDAT      = 33,   /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_WBUFLD    = 34,   /**< Number of write buffer entries forced out by loads */
-    CVMX_LOG_PERF_CNT_WBUFFL    = 35,   /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
-    CVMX_LOG_PERF_CNT_WBUFTR    = 36,   /**< Number of stores that found no available write buffer entries */
-    CVMX_LOG_PERF_CNT_BADD      = 37,   /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_BADDL2    = 38,   /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_BFILL     = 39,   /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_DDIDS     = 40,   /**< Number of Dstream DIDs created */
-    CVMX_LOG_PERF_CNT_IDIDS     = 41,   /**< Number of Istream DIDs created */
-    CVMX_LOG_PERF_CNT_DIDNA     = 42,   /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
-    CVMX_LOG_PERF_CNT_LDS       = 43,   /**< Number of load issues */
-    CVMX_LOG_PERF_CNT_LMLDS     = 44,   /**< Number of local memory load */
-    CVMX_LOG_PERF_CNT_IOLDS     = 45,   /**< Number of I/O load issues */
-    CVMX_LOG_PERF_CNT_DMLDS     = 46,   /**< Number of loads that were not prefetches and missed in the cache */
-    CVMX_LOG_PERF_CNT_STS       = 48,   /**< Number of store issues */
-    CVMX_LOG_PERF_CNT_LMSTS     = 49,   /**< Number of local memory store issues */
-    CVMX_LOG_PERF_CNT_IOSTS     = 50,   /**< Number of I/O store issues */
-    CVMX_LOG_PERF_CNT_IOBDMA    = 51,   /**< Number of IOBDMAs */
-    CVMX_LOG_PERF_CNT_DTLB      = 53,   /**< Number of dstream TLB refill, invalid, or modified exceptions */
-    CVMX_LOG_PERF_CNT_DTLBAD    = 54,   /**< Number of dstream TLB address errors */
-    CVMX_LOG_PERF_CNT_ITLB      = 55,   /**< Number of istream TLB refill, invalid, or address error exceptions */
-    CVMX_LOG_PERF_CNT_SYNC      = 56,   /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_SYNCIOB   = 57,   /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
-    CVMX_LOG_PERF_CNT_SYNCW     = 58,   /**< Number of SYNCWs */
-} cvmx_log_perf_event_t;
-
-/**
- * Structure of the performance counter control register
- */
-typedef union
-{
-    uint32_t u32;
-    struct
-    {
-        uint32_t                M       : 1;
-        uint32_t                W       : 1;
-        uint32_t                reserved: 19;
-        cvmx_log_perf_event_t   event   : 6;
-        uint32_t                IE      : 1;
-        uint32_t                U       : 1;
-        uint32_t                S       : 1;
-        uint32_t                K       : 1;
-        uint32_t                EX      : 1;
-    } s;
-} cvmx_log_perf_control_t;
-
 /*
  * Add CVMX_LOG_DISABLE_PC_LOGGING as an attribute to and function prototype
  * that you don't want logged when the gcc option "-pg" is supplied. We
@@ -193,7 +114,7 @@ void cvmx_log_structure(const char *type, void *data, int size_in_bytes) CVMX_LO
  * @param counter1 Event type for counter 1
  * @param counter2 Event type for counter 2
  */
-void cvmx_log_perf_setup(cvmx_log_perf_event_t counter1, cvmx_log_perf_event_t counter2);
+void cvmx_log_perf_setup(cvmx_core_perf_t counter1, cvmx_core_perf_t counter2);
 
 /**
  * Log the performance counters
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc.h b/sys/contrib/octeon-sdk/cvmx-malloc.h
index bb21a28..5a872bd 100644
--- a/sys/contrib/octeon-sdk/cvmx-malloc.h
+++ b/sys/contrib/octeon-sdk/cvmx-malloc.h
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  *
@@ -48,7 +50,7 @@
  * modified version of ptmalloc2 (used in glibc), and a zone allocator for allocating fixed
  * size memory blocks.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
 
 #ifndef __CVMX_MALLOC_H__
@@ -64,6 +66,7 @@ struct malloc_state; /* forward declaration */
 typedef struct malloc_state *cvmx_arena_list_t;
 
 
+#ifndef CVMX_BUILD_FOR_LINUX_USER
 /**
  * Creates an arena from the memory region specified and adds it
  * to the supplied arena list.
@@ -129,6 +132,7 @@ void *cvmx_memalign(cvmx_arena_list_t arena_list, size_t alignment, size_t bytes
  * @param ptr    pointer of buffer to deallocate
  */
 void cvmx_free(void *ptr);
+#endif
 
 
 
@@ -159,6 +163,7 @@ static inline char *cvmx_zone_name(cvmx_zone_t zone)
 }
 
 
+#ifndef CVMX_BUILD_FOR_LINUX_USER
 /**
  * Creates a memory zone for efficient allocation/deallocation of
  * fixed size memory blocks from a specified memory region.
@@ -195,6 +200,7 @@ cvmx_zone_t cvmx_zone_create_from_addr(char *name, uint32_t elem_size, uint32_t
  */
 cvmx_zone_t cvmx_zone_create_from_arena(char *name, uint32_t elem_size, uint32_t num_elem, uint32_t align,
                              cvmx_arena_list_t arena_list, uint32_t flags);
+#endif
 /**
  * Allocate a buffer from a memory zone
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc b/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc
deleted file mode 100644
index 922a713..0000000
--- a/sys/contrib/octeon-sdk/cvmx-malloc/README-malloc
+++ /dev/null
@@ -1,12 +0,0 @@
-Readme for Octeon shared memory malloc
-
-This malloc is based on ptmalloc2, which is the malloc
-implementation of glibc.  Source code and more information
-on this can be found at http://www.malloc.de/en/index.html.
-Please see the individual files for licensing terms.
-
-The main change to the code modifies the way the malloc
-gets memory from the system.  Under Linux/Unix, malloc
-uses the brk or memmap sytem calls to request more memory.
-In this implementation, memory regions must be explicitly
-given to malloc by the application.
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/arena.c b/sys/contrib/octeon-sdk/cvmx-malloc/arena.c
deleted file mode 100644
index 8e0ce1f..0000000
--- a/sys/contrib/octeon-sdk/cvmx-malloc/arena.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
-Copyright (c) 2001 Wolfram Gloger
-Copyright (c) 2006 Cavium networks
-
-Permission to use, copy, modify, distribute, and sell this software
-and its documentation for any purpose is hereby granted without fee,
-provided that (i) the above copyright notices and this permission
-notice appear in all copies of the software and related documentation,
-and (ii) the name of Wolfram Gloger may not be used in any advertising
-or publicity relating to the software.
-
-THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
-EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
-WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-
-IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
-INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
-DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
-WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
-OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-PERFORMANCE OF THIS SOFTWARE.
-*/
-
-/* $Id: arena.c 30481 2007-12-05 21:46:59Z rfranz $ */
-
-/* Compile-time constants.  */
-
-#define HEAP_MIN_SIZE (4096)   /* Must leave room for struct malloc_state, arena ptrs, etc., totals about 2400 bytes */
-
-#ifndef THREAD_STATS
-#define THREAD_STATS 0
-#endif
-
-/* If THREAD_STATS is non-zero, some statistics on mutex locking are
-   computed.  */
-
-/***************************************************************************/
-
-// made static to avoid conflicts with newlib
-static mstate         _int_new_arena __MALLOC_P ((size_t __ini_size));
-
-/***************************************************************************/
-
-#define top(ar_ptr) ((ar_ptr)->top)
-
-/* A heap is a single contiguous memory region holding (coalesceable)
-   malloc_chunks.    Not used unless compiling with
-   USE_ARENAS. */
-
-typedef struct _heap_info {
-  mstate ar_ptr; /* Arena for this heap. */
-  struct _heap_info *prev; /* Previous heap. */
-  size_t size;   /* Current size in bytes. */
-  size_t pad;    /* Make sure the following data is properly aligned. */
-} heap_info;
-
-/* Thread specific data */
-
-static tsd_key_t arena_key;  // one per PP (thread)
-static CVMX_SHARED mutex_t list_lock;  // shared...
-
-#if THREAD_STATS
-static int stat_n_heaps;
-#define THREAD_STAT(x) x
-#else
-#define THREAD_STAT(x) do ; while(0)
-#endif
-
-/* Mapped memory in non-main arenas (reliable only for NO_THREADS). */
-static unsigned long arena_mem;
-
-/* Already initialized? */
-int CVMX_SHARED cvmx__malloc_initialized = -1;
-
-/**************************************************************************/
-
-#if USE_ARENAS
-
-/* find the heap and corresponding arena for a given ptr */
-
-#define arena_for_chunk(ptr) ((ptr)->arena_ptr)
-#define set_arena_for_chunk(ptr, arena) (ptr)->arena_ptr = (arena)
-
-
-#endif /* USE_ARENAS */
-
-/**************************************************************************/
-
-#ifndef NO_THREADS
-
-/* atfork support.  */
-
-static __malloc_ptr_t (*save_malloc_hook) __MALLOC_P ((size_t __size,
-						       __const __malloc_ptr_t));
-static void           (*save_free_hook) __MALLOC_P ((__malloc_ptr_t __ptr,
-						     __const __malloc_ptr_t));
-static Void_t*        save_arena;
-
-/* Magic value for the thread-specific arena pointer when
-   malloc_atfork() is in use.  */
-
-#define ATFORK_ARENA_PTR ((Void_t*)-1)
-
-/* The following hooks are used while the `atfork' handling mechanism
-   is active. */
-
-static Void_t*
-malloc_atfork(size_t sz, const Void_t *caller)
-{
-return(NULL);
-}
-
-static void
-free_atfork(Void_t* mem, const Void_t *caller)
-{
-  Void_t *vptr = NULL;
-  mstate ar_ptr;
-  mchunkptr p;                          /* chunk corresponding to mem */
-
-  if (mem == 0)                              /* free(0) has no effect */
-    return;
-
-  p = mem2chunk(mem);         /* do not bother to replicate free_check here */
-
-#if HAVE_MMAP
-  if (chunk_is_mmapped(p))                       /* release mmapped memory. */
-  {
-    munmap_chunk(p);
-    return;
-  }
-#endif
-
-  ar_ptr = arena_for_chunk(p);
-  tsd_getspecific(arena_key, vptr);
-  if(vptr != ATFORK_ARENA_PTR)
-    (void)mutex_lock(&ar_ptr->mutex);
-  _int_free(ar_ptr, mem);
-  if(vptr != ATFORK_ARENA_PTR)
-    (void)mutex_unlock(&ar_ptr->mutex);
-}
-
-
-
-#ifdef __linux__
-#error   __linux__defined!
-#endif
-
-#endif /* !defined NO_THREADS */
-
-
-
-/* Initialization routine. */
-#ifdef _LIBC
-#error  _LIBC is defined, and should not be
-#endif /* _LIBC */
-
-static CVMX_SHARED cvmx_spinlock_t malloc_init_spin_lock;
-
-
-
-
-/* Managing heaps and arenas (for concurrent threads) */
-
-#if USE_ARENAS
-
-#if MALLOC_DEBUG > 1
-
-/* Print the complete contents of a single heap to stderr. */
-
-static void
-#if __STD_C
-dump_heap(heap_info *heap)
-#else
-dump_heap(heap) heap_info *heap;
-#endif
-{
-  char *ptr;
-  mchunkptr p;
-
-  fprintf(stderr, "Heap %p, size %10lx:\n", heap, (long)heap->size);
-  ptr = (heap->ar_ptr != (mstate)(heap+1)) ?
-    (char*)(heap + 1) : (char*)(heap + 1) + sizeof(struct malloc_state);
-  p = (mchunkptr)(((unsigned long)ptr + MALLOC_ALIGN_MASK) &
-                  ~MALLOC_ALIGN_MASK);
-  for(;;) {
-    fprintf(stderr, "chunk %p size %10lx", p, (long)p->size);
-    if(p == top(heap->ar_ptr)) {
-      fprintf(stderr, " (top)\n");
-      break;
-    } else if(p->size == (0|PREV_INUSE)) {
-      fprintf(stderr, " (fence)\n");
-      break;
-    }
-    fprintf(stderr, "\n");
-    p = next_chunk(p);
-  }
-}
-
-#endif /* MALLOC_DEBUG > 1 */
-/* Delete a heap. */
-
-
-static mstate cvmx_new_arena(void *addr, size_t size)
-{
-  mstate a;
-  heap_info *h;
-  char *ptr;
-  unsigned long misalign;
-  int page_mask = malloc_getpagesize - 1;
-
-  debug_printf("cvmx_new_arena called, addr: %p, size %ld\n", addr, size);
-  debug_printf("heapinfo size: %ld, mstate size: %d\n", sizeof(heap_info), sizeof(struct malloc_state));
-
-  if (!addr || (size < HEAP_MIN_SIZE))
-  {
-      return(NULL);
-  }
-  /* We must zero out the arena as the malloc code assumes this. */
-  memset(addr, 0, size);
-
-  h = (heap_info *)addr;
-  h->size = size;
-
-  a = h->ar_ptr = (mstate)(h+1);
-  malloc_init_state(a);
-  /*a->next = NULL;*/
-  a->system_mem = a->max_system_mem = h->size;
-  arena_mem += h->size;
-  a->next = a;
-
-  /* Set up the top chunk, with proper alignment. */
-  ptr = (char *)(a + 1);
-  misalign = (unsigned long)chunk2mem(ptr) & MALLOC_ALIGN_MASK;
-  if (misalign > 0)
-    ptr += MALLOC_ALIGNMENT - misalign;
-  top(a) = (mchunkptr)ptr;
-  set_head(top(a), (((char*)h + h->size) - ptr) | PREV_INUSE);
-
-  return a;
-}
-
-
-int cvmx_add_arena(cvmx_arena_list_t *arena_list, void *ptr, size_t size)
-{
-  mstate a;
-
-  /* Enforce required alignement, and adjust size */
-  int misaligned = ((size_t)ptr) & (MALLOC_ALIGNMENT - 1);
-  if (misaligned)
-  {
-      ptr = (char*)ptr + MALLOC_ALIGNMENT - misaligned;
-      size -= MALLOC_ALIGNMENT - misaligned;
-  }
-
-  debug_printf("Adding arena at addr: %p, size %d\n", ptr, size);
-
-  a = cvmx_new_arena(ptr, size);  /* checks ptr and size */
-  if (!a)
-  {
-      return(-1);
-  }
-
-  debug_printf("cmvx_add_arena - arena_list: %p, *arena_list: %p\n", arena_list, *arena_list);
-  debug_printf("cmvx_add_arena - list: %p, new: %p\n", *arena_list, a);
-  mutex_init(&a->mutex);
-  mutex_lock(&a->mutex);
-
-
-  if (*arena_list)
-  {
-      mstate ar_ptr = *arena_list;
-      (void)mutex_lock(&ar_ptr->mutex);
-      a->next = ar_ptr->next;  // lock held on a and ar_ptr
-      ar_ptr->next = a;
-      (void)mutex_unlock(&ar_ptr->mutex);
-  }
-  else
-  {
-      *arena_list = a;
-//      a->next = a;
-  }
-
-  debug_printf("cvmx_add_arena - list: %p, list->next: %p\n", *arena_list, ((mstate)*arena_list)->next);
-
-  // unlock, since it is not going to be used immediately
-  (void)mutex_unlock(&a->mutex);
-
-  return(0);
-}
-
-
-
-#endif /* USE_ARENAS */
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c
deleted file mode 100644
index 222ad5d..0000000
--- a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.c
+++ /dev/null
@@ -1,4106 +0,0 @@
-/*
-Copyright (c) 2001 Wolfram Gloger
-Copyright (c) 2006 Cavium networks
-
-Permission to use, copy, modify, distribute, and sell this software
-and its documentation for any purpose is hereby granted without fee,
-provided that (i) the above copyright notices and this permission
-notice appear in all copies of the software and related documentation,
-and (ii) the name of Wolfram Gloger may not be used in any advertising
-or publicity relating to the software.
-
-THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
-EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
-WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-
-IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
-INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
-DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
-WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
-OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-PERFORMANCE OF THIS SOFTWARE.
-*/
-
-/*
-  This is a version (aka ptmalloc2) of malloc/free/realloc written by
-  Doug Lea and adapted to multiple threads/arenas by Wolfram Gloger.
-
-* Version ptmalloc2-20011215
-  $Id: malloc.c 30481 2007-12-05 21:46:59Z rfranz $
-  based on:
-  VERSION 2.7.1pre1 Sat May 12 07:41:21 2001  Doug Lea  (dl at gee)
-
-   Note: There may be an updated version of this malloc obtainable at
-           http://www.malloc.de/malloc/ptmalloc2.tar.gz
-         Check before installing!
-
-* Quickstart
-
-  In order to compile this implementation, a Makefile is provided with
-  the ptmalloc2 distribution, which has pre-defined targets for some
-  popular systems (e.g. "make posix" for Posix threads).  All that is
-  typically required with regard to compiler flags is the selection of
-  the thread package via defining one out of USE_PTHREADS, USE_THR or
-  USE_SPROC.  Check the thread-m.h file for what effects this has.
-  Many/most systems will additionally require USE_TSD_DATA_HACK to be
-  defined, so this is the default for "make posix".
-
-* Why use this malloc?
-
-  This is not the fastest, most space-conserving, most portable, or
-  most tunable malloc ever written. However it is among the fastest
-  while also being among the most space-conserving, portable and tunable.
-  Consistent balance across these factors results in a good general-purpose
-  allocator for malloc-intensive programs.
-
-  The main properties of the algorithms are:
-  * For large (>= 512 bytes) requests, it is a pure best-fit allocator,
-    with ties normally decided via FIFO (i.e. least recently used).
-  * For small (<= 64 bytes by default) requests, it is a caching
-    allocator, that maintains pools of quickly recycled chunks.
-  * In between, and for combinations of large and small requests, it does
-    the best it can trying to meet both goals at once.
-  * For very large requests (>= 128KB by default), it relies on system
-    memory mapping facilities, if supported.
-
-  For a longer but slightly out of date high-level description, see
-     http://gee.cs.oswego.edu/dl/html/malloc.html
-
-  You may already by default be using a C library containing a malloc
-  that is  based on some version of this malloc (for example in
-  linux). You might still want to use the one in this file in order to
-  customize settings or to avoid overheads associated with library
-  versions.
-
-* Contents, described in more detail in "description of public routines" below.
-
-  Standard (ANSI/SVID/...)  functions:
-    malloc(size_t n);
-    calloc(size_t n_elements, size_t element_size);
-    free(Void_t* p);
-    realloc(Void_t* p, size_t n);
-    memalign(size_t alignment, size_t n);
-    valloc(size_t n);
-    mallinfo()
-    mallopt(int parameter_number, int parameter_value)
-
-  Additional functions:
-    independent_calloc(size_t n_elements, size_t size, Void_t* chunks[]);
-    independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
-    pvalloc(size_t n);
-    cfree(Void_t* p);
-    malloc_trim(size_t pad);
-    malloc_usable_size(Void_t* p);
-    malloc_stats();
-
-* Vital statistics:
-
-  Supported pointer representation:       4 or 8 bytes
-  Supported size_t  representation:       4 or 8 bytes
-       Note that size_t is allowed to be 4 bytes even if pointers are 8.
-       You can adjust this by defining INTERNAL_SIZE_T
-
-  Alignment:                              2 * sizeof(size_t) (default)
-       (i.e., 8 byte alignment with 4byte size_t). This suffices for
-       nearly all current machines and C compilers. However, you can
-       define MALLOC_ALIGNMENT to be wider than this if necessary.
-
-  Minimum overhead per allocated chunk:   4 or 8 bytes
-       Each malloced chunk has a hidden word of overhead holding size
-       and status information.
-
-  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
-                          8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
-
-       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
-       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
-       needed; 4 (8) for a trailing size field and 8 (16) bytes for
-       free list pointers. Thus, the minimum allocatable size is
-       16/24/32 bytes.
-
-       Even a request for zero bytes (i.e., malloc(0)) returns a
-       pointer to something of the minimum allocatable size.
-
-       The maximum overhead wastage (i.e., number of extra bytes
-       allocated than were requested in malloc) is less than or equal
-       to the minimum size, except for requests >= mmap_threshold that
-       are serviced via mmap(), where the worst case wastage is 2 *
-       sizeof(size_t) bytes plus the remainder from a system page (the
-       minimal mmap unit); typically 4096 or 8192 bytes.
-
-  Maximum allocated size:  4-byte size_t: 2^32 minus about two pages
-                           8-byte size_t: 2^64 minus about two pages
-
-       It is assumed that (possibly signed) size_t values suffice to
-       represent chunk sizes. `Possibly signed' is due to the fact
-       that `size_t' may be defined on a system as either a signed or
-       an unsigned type. The ISO C standard says that it must be
-       unsigned, but a few systems are known not to adhere to this.
-       Additionally, even when size_t is unsigned, sbrk (which is by
-       default used to obtain memory from system) accepts signed
-       arguments, and may not be able to handle size_t-wide arguments
-       with negative sign bit.  Generally, values that would
-       appear as negative after accounting for overhead and alignment
-       are supported only via mmap(), which does not have this
-       limitation.
-
-       Requests for sizes outside the allowed range will perform an optional
-       failure action and then return null. (Requests may also
-       also fail because a system is out of memory.)
-
-  Thread-safety: thread-safe unless NO_THREADS is defined
-
-  Compliance: I believe it is compliant with the 1997 Single Unix Specification
-       (See http://www.opennc.org). Also SVID/XPG, ANSI C, and probably
-       others as well.
-
-* Synopsis of compile-time options:
-
-    People have reported using previous versions of this malloc on all
-    versions of Unix, sometimes by tweaking some of the defines
-    below. It has been tested most extensively on Solaris and
-    Linux. It is also reported to work on WIN32 platforms.
-    People also report using it in stand-alone embedded systems.
-
-    The implementation is in straight, hand-tuned ANSI C.  It is not
-    at all modular. (Sorry!)  It uses a lot of macros.  To be at all
-    usable, this code should be compiled using an optimizing compiler
-    (for example gcc -O3) that can simplify expressions and control
-    paths. (FAQ: some macros import variables as arguments rather than
-    declare locals because people reported that some debuggers
-    otherwise get confused.)
-
-    OPTION                     DEFAULT VALUE
-
-    Compilation Environment options:
-
-    __STD_C                    derived from C compiler defines
-    WIN32                      NOT defined
-    HAVE_MEMCPY                defined
-    USE_MEMCPY                 1 if HAVE_MEMCPY is defined
-    HAVE_MMAP                  defined as 1
-    MMAP_CLEARS                1
-    HAVE_MREMAP                0 unless linux defined
-    USE_ARENAS                 the same as HAVE_MMAP
-    malloc_getpagesize         derived from system #includes, or 4096 if not
-    HAVE_USR_INCLUDE_MALLOC_H  NOT defined
-    LACKS_UNISTD_H             NOT defined unless WIN32
-    LACKS_SYS_PARAM_H          NOT defined unless WIN32
-    LACKS_SYS_MMAN_H           NOT defined unless WIN32
-
-    Changing default word sizes:
-
-    INTERNAL_SIZE_T            size_t
-    MALLOC_ALIGNMENT           2 * sizeof(INTERNAL_SIZE_T)
-
-    Configuration and functionality options:
-
-    USE_DL_PREFIX              NOT defined
-    USE_PUBLIC_MALLOC_WRAPPERS NOT defined
-    USE_MALLOC_LOCK            NOT defined
-    MALLOC_DEBUG               NOT defined
-    REALLOC_ZERO_BYTES_FREES   1
-    MALLOC_FAILURE_ACTION      errno = ENOMEM, if __STD_C defined, else no-op
-    TRIM_FASTBINS              0
-    FIRST_SORTED_BIN_SIZE      512
-
-    Options for customizing MORECORE:
-
-    MORECORE                   sbrk
-    MORECORE_FAILURE           -1
-    MORECORE_CONTIGUOUS        1
-    MORECORE_CANNOT_TRIM       NOT defined
-    MORECORE_CLEARS            1
-    MMAP_AS_MORECORE_SIZE      (1024 * 1024)
-
-    Tuning options that are also dynamically changeable via mallopt:
-
-    DEFAULT_MXFAST             64
-    DEFAULT_TRIM_THRESHOLD     128 * 1024
-    DEFAULT_TOP_PAD            0
-    DEFAULT_MMAP_THRESHOLD     128 * 1024
-    DEFAULT_MMAP_MAX           65536
-
-    There are several other #defined constants and macros that you
-    probably don't want to touch unless you are extending or adapting malloc.  */
-
-/*
-  __STD_C should be nonzero if using ANSI-standard C compiler, a C++
-  compiler, or a C compiler sufficiently close to ANSI to get away
-  with it.
-*/
-
-#include "cvmx-config.h"
-#include "cvmx.h"
-#include "cvmx-spinlock.h"
-#include "cvmx-malloc.h"
-
-
-#ifndef __STD_C
-#if defined(__STDC__) || defined(__cplusplus)
-#define __STD_C     1
-#else
-#define __STD_C     0
-#endif
-#endif /*__STD_C*/
-
-
-/*
-  Void_t* is the pointer type that malloc should say it returns
-*/
-
-#ifndef Void_t
-#if 1
-#define Void_t      void
-#else
-#define Void_t      char
-#endif
-#endif /*Void_t*/
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* define LACKS_UNISTD_H if your system does not have a <unistd.h>. */
-
-/* #define  LACKS_UNISTD_H */
-
-#ifndef LACKS_UNISTD_H
-#include <unistd.h>
-#endif
-
-/* define LACKS_SYS_PARAM_H if your system does not have a <sys/param.h>. */
-
-/* #define  LACKS_SYS_PARAM_H */
-
-
-#include <stdio.h>    /* needed for malloc_stats */
-#include <errno.h>    /* needed for optional MALLOC_FAILURE_ACTION */
-
-
-/*
-  Debugging:
-
-  Because freed chunks may be overwritten with bookkeeping fields, this
-  malloc will often die when freed memory is overwritten by user
-  programs.  This can be very effective (albeit in an annoying way)
-  in helping track down dangling pointers.
-
-  If you compile with -DMALLOC_DEBUG, a number of assertion checks are
-  enabled that will catch more memory errors. You probably won't be
-  able to make much sense of the actual assertion errors, but they
-  should help you locate incorrectly overwritten memory.  The checking
-  is fairly extensive, and will slow down execution
-  noticeably. Calling malloc_stats or mallinfo with MALLOC_DEBUG set
-  will attempt to check every non-mmapped allocated and free chunk in
-  the course of computing the summmaries. (By nature, mmapped regions
-  cannot be checked very much automatically.)
-
-  Setting MALLOC_DEBUG may also be helpful if you are trying to modify
-  this code. The assertions in the check routines spell out in more
-  detail the assumptions and invariants underlying the algorithms.
-
-  Setting MALLOC_DEBUG does NOT provide an automated mechanism for
-  checking that all accesses to malloced memory stay within their
-  bounds. However, there are several add-ons and adaptations of this
-  or other mallocs available that do this.
-*/
-
-#define MALLOC_DEBUG 1
-#if MALLOC_DEBUG
-#include <assert.h>
-#else
-#define assert(x) ((void)0)
-#endif
-
-
-/*
-  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
-  of chunk sizes.
-
-  The default version is the same as size_t.
-
-  While not strictly necessary, it is best to define this as an
-  unsigned type, even if size_t is a signed type. This may avoid some
-  artificial size limitations on some systems.
-
-  On a 64-bit machine, you may be able to reduce malloc overhead by
-  defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' at the
-  expense of not being able to handle more than 2^32 of malloced
-  space. If this limitation is acceptable, you are encouraged to set
-  this unless you are on a platform requiring 16byte alignments. In
-  this case the alignment requirements turn out to negate any
-  potential advantages of decreasing size_t word size.
-
-  Implementors: Beware of the possible combinations of:
-     - INTERNAL_SIZE_T might be signed or unsigned, might be 32 or 64 bits,
-       and might be the same width as int or as long
-     - size_t might have different width and signedness as INTERNAL_SIZE_T
-     - int and long might be 32 or 64 bits, and might be the same width
-  To deal with this, most comparisons and difference computations
-  among INTERNAL_SIZE_Ts should cast them to unsigned long, being
-  aware of the fact that casting an unsigned int to a wider long does
-  not sign-extend. (This also makes checking for negative numbers
-  awkward.) Some of these casts result in harmless compiler warnings
-  on some systems.
-*/
-
-#ifndef INTERNAL_SIZE_T
-#define INTERNAL_SIZE_T size_t
-#endif
-
-/* The corresponding word size */
-#define SIZE_SZ                (sizeof(INTERNAL_SIZE_T))
-
-
-/*
-  MALLOC_ALIGNMENT is the minimum alignment for malloc'ed chunks.
-  It must be a power of two at least 2 * SIZE_SZ, even on machines
-  for which smaller alignments would suffice. It may be defined as
-  larger than this though. Note however that code and data structures
-  are optimized for the case of 8-byte alignment.
-*/
-
-
-#ifndef MALLOC_ALIGNMENT
-#define MALLOC_ALIGNMENT       (2 * SIZE_SZ)
-#endif
-
-/* The corresponding bit mask value */
-#define MALLOC_ALIGN_MASK      (MALLOC_ALIGNMENT - 1)
-
-
-
-/*
-  REALLOC_ZERO_BYTES_FREES should be set if a call to
-  realloc with zero bytes should be the same as a call to free.
-  This is required by the C standard. Otherwise, since this malloc
-  returns a unique pointer for malloc(0), so does realloc(p, 0).
-*/
-
-#ifndef REALLOC_ZERO_BYTES_FREES
-#define REALLOC_ZERO_BYTES_FREES 1
-#endif
-
-/*
-  TRIM_FASTBINS controls whether free() of a very small chunk can
-  immediately lead to trimming. Setting to true (1) can reduce memory
-  footprint, but will almost always slow down programs that use a lot
-  of small chunks.
-
-  Define this only if you are willing to give up some speed to more
-  aggressively reduce system-level memory footprint when releasing
-  memory in programs that use many small chunks.  You can get
-  essentially the same effect by setting MXFAST to 0, but this can
-  lead to even greater slowdowns in programs using many small chunks.
-  TRIM_FASTBINS is an in-between compile-time option, that disables
-  only those chunks bordering topmost memory from being placed in
-  fastbins.
-*/
-
-#ifndef TRIM_FASTBINS
-#define TRIM_FASTBINS  0
-#endif
-
-
-/*
-  USE_DL_PREFIX will prefix all public routines with the string 'dl'.
-  This is necessary when you only want to use this malloc in one part
-  of a program, using your regular system malloc elsewhere.
-*/
-
-#define USE_DL_PREFIX
-
-
-/*
-   Two-phase name translation.
-   All of the actual routines are given mangled names.
-   When wrappers are used, they become the public callable versions.
-   When DL_PREFIX is used, the callable names are prefixed.
-*/
-
-#ifdef USE_DL_PREFIX
-#define public_cALLOc    cvmx_calloc
-#define public_fREe      cvmx_free
-#define public_cFREe     dlcfree
-#define public_mALLOc    cvmx_malloc
-#define public_mEMALIGn  cvmx_memalign
-#define public_rEALLOc   cvmx_realloc
-#define public_vALLOc    dlvalloc
-#define public_pVALLOc   dlpvalloc
-#define public_mALLINFo  dlmallinfo
-#define public_mALLOPt   dlmallopt
-#define public_mTRIm     dlmalloc_trim
-#define public_mSTATs    dlmalloc_stats
-#define public_mUSABLe   dlmalloc_usable_size
-#define public_iCALLOc   dlindependent_calloc
-#define public_iCOMALLOc dlindependent_comalloc
-#define public_gET_STATe dlget_state
-#define public_sET_STATe dlset_state
-#else /* USE_DL_PREFIX */
-#ifdef _LIBC
-#error _LIBC defined and should not be
-/* Special defines for the GNU C library.  */
-#define public_cALLOc    __libc_calloc
-#define public_fREe      __libc_free
-#define public_cFREe     __libc_cfree
-#define public_mALLOc    __libc_malloc
-#define public_mEMALIGn  __libc_memalign
-#define public_rEALLOc   __libc_realloc
-#define public_vALLOc    __libc_valloc
-#define public_pVALLOc   __libc_pvalloc
-#define public_mALLINFo  __libc_mallinfo
-#define public_mALLOPt   __libc_mallopt
-#define public_mTRIm     __malloc_trim
-#define public_mSTATs    __malloc_stats
-#define public_mUSABLe   __malloc_usable_size
-#define public_iCALLOc   __libc_independent_calloc
-#define public_iCOMALLOc __libc_independent_comalloc
-#define public_gET_STATe __malloc_get_state
-#define public_sET_STATe __malloc_set_state
-#define malloc_getpagesize __getpagesize()
-#define open             __open
-#define mmap             __mmap
-#define munmap           __munmap
-#define mremap           __mremap
-#define mprotect         __mprotect
-#define MORECORE         (*__morecore)
-#define MORECORE_FAILURE 0
-
-Void_t * __default_morecore (ptrdiff_t);
-Void_t *(*__morecore)(ptrdiff_t) = __default_morecore;
-
-#else /* !_LIBC */
-#define public_cALLOc    calloc
-#define public_fREe      free
-#define public_cFREe     cfree
-#define public_mALLOc    malloc
-#define public_mEMALIGn  memalign
-#define public_rEALLOc   realloc
-#define public_vALLOc    valloc
-#define public_pVALLOc   pvalloc
-#define public_mALLINFo  mallinfo
-#define public_mALLOPt   mallopt
-#define public_mTRIm     malloc_trim
-#define public_mSTATs    malloc_stats
-#define public_mUSABLe   malloc_usable_size
-#define public_iCALLOc   independent_calloc
-#define public_iCOMALLOc independent_comalloc
-#define public_gET_STATe malloc_get_state
-#define public_sET_STATe malloc_set_state
-#endif /* _LIBC */
-#endif /* USE_DL_PREFIX */
-
-
-/*
-  HAVE_MEMCPY should be defined if you are not otherwise using
-  ANSI STD C, but still have memcpy and memset in your C library
-  and want to use them in calloc and realloc. Otherwise simple
-  macro versions are defined below.
-
-  USE_MEMCPY should be defined as 1 if you actually want to
-  have memset and memcpy called. People report that the macro
-  versions are faster than libc versions on some systems.
-
-  Even if USE_MEMCPY is set to 1, loops to copy/clear small chunks
-  (of <= 36 bytes) are manually unrolled in realloc and calloc.
-*/
-
-#define HAVE_MEMCPY
-
-#ifndef USE_MEMCPY
-#ifdef HAVE_MEMCPY
-#define USE_MEMCPY 1
-#else
-#define USE_MEMCPY 0
-#endif
-#endif
-
-
-#if (__STD_C || defined(HAVE_MEMCPY))
-
-#ifdef WIN32
-/* On Win32 memset and memcpy are already declared in windows.h */
-#else
-#if __STD_C
-void* memset(void*, int, size_t);
-void* memcpy(void*, const void*, size_t);
-#else
-Void_t* memset();
-Void_t* memcpy();
-#endif
-#endif
-#endif
-
-/*
-  MALLOC_FAILURE_ACTION is the action to take before "return 0" when
-  malloc fails to be able to return memory, either because memory is
-  exhausted or because of illegal arguments.
-
-  By default, sets errno if running on STD_C platform, else does nothing.
-*/
-
-#ifndef MALLOC_FAILURE_ACTION
-#if __STD_C
-#define MALLOC_FAILURE_ACTION \
-   errno = ENOMEM;
-
-#else
-#define MALLOC_FAILURE_ACTION
-#endif
-#endif
-
-/*
-  MORECORE-related declarations. By default, rely on sbrk
-*/
-
-
-#ifdef LACKS_UNISTD_H
-#if !defined(__FreeBSD__) && !defined(__OpenBSD__) && !defined(__NetBSD__)
-#if __STD_C
-extern Void_t*     sbrk(ptrdiff_t);
-#else
-extern Void_t*     sbrk();
-#endif
-#endif
-#endif
-
-/*
-  MORECORE is the name of the routine to call to obtain more memory
-  from the system.  See below for general guidance on writing
-  alternative MORECORE functions, as well as a version for WIN32 and a
-  sample version for pre-OSX macos.
-*/
-#undef MORECORE  // not supported
-#ifndef MORECORE
-#define MORECORE notsupported
-#endif
-
-/*
-  MORECORE_FAILURE is the value returned upon failure of MORECORE
-  as well as mmap. Since it cannot be an otherwise valid memory address,
-  and must reflect values of standard sys calls, you probably ought not
-  try to redefine it.
-*/
-
-#ifndef MORECORE_FAILURE
-#define MORECORE_FAILURE (-1)
-#endif
-
-/*
-  If MORECORE_CONTIGUOUS is true, take advantage of fact that
-  consecutive calls to MORECORE with positive arguments always return
-  contiguous increasing addresses.  This is true of unix sbrk.  Even
-  if not defined, when regions happen to be contiguous, malloc will
-  permit allocations spanning regions obtained from different
-  calls. But defining this when applicable enables some stronger
-  consistency checks and space efficiencies.
-*/
-
-#ifndef MORECORE_CONTIGUOUS
-#define MORECORE_CONTIGUOUS 0
-#endif
-
-/*
-  Define MORECORE_CANNOT_TRIM if your version of MORECORE
-  cannot release space back to the system when given negative
-  arguments. This is generally necessary only if you are using
-  a hand-crafted MORECORE function that cannot handle negative arguments.
-*/
-
-#define MORECORE_CANNOT_TRIM 1
-
-/*  MORECORE_CLEARS           (default 1)
-     The degree to which the routine mapped to MORECORE zeroes out
-     memory: never (0), only for newly allocated space (1) or always
-     (2).  The distinction between (1) and (2) is necessary because on
-     some systems, if the application first decrements and then
-     increments the break value, the contents of the reallocated space
-     are unspecified.
-*/
-
-#ifndef MORECORE_CLEARS
-#define MORECORE_CLEARS 0
-#endif
-
-
-/*
-  Define HAVE_MMAP as true to optionally make malloc() use mmap() to
-  allocate very large blocks.  These will be returned to the
-  operating system immediately after a free(). Also, if mmap
-  is available, it is used as a backup strategy in cases where
-  MORECORE fails to provide space from system.
-
-  This malloc is best tuned to work with mmap for large requests.
-  If you do not have mmap, operations involving very large chunks (1MB
-  or so) may be slower than you'd like.
-*/
-
-#undef HAVE_MMAP
-#ifndef HAVE_MMAP
-#define HAVE_MMAP 0
-
-/*
-   Standard unix mmap using /dev/zero clears memory so calloc doesn't
-   need to.
-*/
-
-#ifndef MMAP_CLEARS
-#define MMAP_CLEARS 0
-#endif
-
-#else /* no mmap */
-#ifndef MMAP_CLEARS
-#define MMAP_CLEARS 0
-#endif
-#endif
-
-
-/*
-   MMAP_AS_MORECORE_SIZE is the minimum mmap size argument to use if
-   sbrk fails, and mmap is used as a backup (which is done only if
-   HAVE_MMAP).  The value must be a multiple of page size.  This
-   backup strategy generally applies only when systems have "holes" in
-   address space, so sbrk cannot perform contiguous expansion, but
-   there is still space available on system.  On systems for which
-   this is known to be useful (i.e. most linux kernels), this occurs
-   only when programs allocate huge amounts of memory.  Between this,
-   and the fact that mmap regions tend to be limited, the size should
-   be large, to avoid too many mmap calls and thus avoid running out
-   of kernel resources.
-*/
-
-#ifndef MMAP_AS_MORECORE_SIZE
-#define MMAP_AS_MORECORE_SIZE (1024 * 1024)
-#endif
-
-/*
-  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
-  large blocks.  This is currently only possible on Linux with
-  kernel versions newer than 1.3.77.
-*/
-#undef linux
-#ifndef HAVE_MREMAP
-#ifdef linux
-#define HAVE_MREMAP 1
-#else
-#define HAVE_MREMAP 0
-#endif
-
-#endif /* HAVE_MMAP */
-
-/* Define USE_ARENAS to enable support for multiple `arenas'.  These
-   are allocated using mmap(), are necessary for threads and
-   occasionally useful to overcome address space limitations affecting
-   sbrk(). */
-
-#ifndef USE_ARENAS
-#define USE_ARENAS 1  // we 'manually' mmap the arenas.....
-#endif
-
-
-/*
-  The system page size. To the extent possible, this malloc manages
-  memory from the system in page-size units.  Note that this value is
-  cached during initialization into a field of malloc_state. So even
-  if malloc_getpagesize is a function, it is only called once.
-
-  The following mechanics for getpagesize were adapted from bsd/gnu
-  getpagesize.h. If none of the system-probes here apply, a value of
-  4096 is used, which should be OK: If they don't apply, then using
-  the actual value probably doesn't impact performance.
-*/
-
-
-#define malloc_getpagesize (4096)
-#ifndef malloc_getpagesize
-
-#ifndef LACKS_UNISTD_H
-#  include <unistd.h>
-#endif
-
-#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
-#    ifndef _SC_PAGE_SIZE
-#      define _SC_PAGE_SIZE _SC_PAGESIZE
-#    endif
-#  endif
-
-#  ifdef _SC_PAGE_SIZE
-#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
-#  else
-#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
-       extern size_t getpagesize();
-#      define malloc_getpagesize getpagesize()
-#    else
-#      ifdef WIN32 /* use supplied emulation of getpagesize */
-#        define malloc_getpagesize getpagesize()
-#      else
-#        ifndef LACKS_SYS_PARAM_H
-#          include <sys/param.h>
-#        endif
-#        ifdef EXEC_PAGESIZE
-#          define malloc_getpagesize EXEC_PAGESIZE
-#        else
-#          ifdef NBPG
-#            ifndef CLSIZE
-#              define malloc_getpagesize NBPG
-#            else
-#              define malloc_getpagesize (NBPG * CLSIZE)
-#            endif
-#          else
-#            ifdef NBPC
-#              define malloc_getpagesize NBPC
-#            else
-#              ifdef PAGESIZE
-#                define malloc_getpagesize PAGESIZE
-#              else /* just guess */
-#                define malloc_getpagesize (4096)
-#              endif
-#            endif
-#          endif
-#        endif
-#      endif
-#    endif
-#  endif
-#endif
-
-/*
-  This version of malloc supports the standard SVID/XPG mallinfo
-  routine that returns a struct containing usage properties and
-  statistics. It should work on any SVID/XPG compliant system that has
-  a /usr/include/malloc.h defining struct mallinfo. (If you'd like to
-  install such a thing yourself, cut out the preliminary declarations
-  as described above and below and save them in a malloc.h file. But
-  there's no compelling reason to bother to do this.)
-
-  The main declaration needed is the mallinfo struct that is returned
-  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
-  bunch of fields that are not even meaningful in this version of
-  malloc.  These fields are are instead filled by mallinfo() with
-  other numbers that might be of interest.
-
-  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
-  /usr/include/malloc.h file that includes a declaration of struct
-  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
-  version is declared below.  These must be precisely the same for
-  mallinfo() to work.  The original SVID version of this struct,
-  defined on most systems with mallinfo, declares all fields as
-  ints. But some others define as unsigned long. If your system
-  defines the fields using a type of different width than listed here,
-  you must #include your system version and #define
-  HAVE_USR_INCLUDE_MALLOC_H.
-*/
-
-/* #define HAVE_USR_INCLUDE_MALLOC_H */
-
-#ifdef HAVE_USR_INCLUDE_MALLOC_H
-#include "/usr/include/malloc.h"
-#endif
-
-
-/* ---------- description of public routines ------------ */
-
-/*
-  malloc(size_t n)
-  Returns a pointer to a newly allocated chunk of at least n bytes, or null
-  if no space is available. Additionally, on failure, errno is
-  set to ENOMEM on ANSI C systems.
-
-  If n is zero, malloc returns a minumum-sized chunk. (The minimum
-  size is 16 bytes on most 32bit systems, and 24 or 32 bytes on 64bit
-  systems.)  On most systems, size_t is an unsigned type, so calls
-  with negative arguments are interpreted as requests for huge amounts
-  of space, which will often fail. The maximum supported value of n
-  differs across systems, but is in all cases less than the maximum
-  representable value of a size_t.
-*/
-#if __STD_C
-Void_t*  public_mALLOc(cvmx_arena_list_t arena_list, size_t);
-#else
-Void_t*  public_mALLOc();
-#endif
-
-/*
-  free(Void_t* p)
-  Releases the chunk of memory pointed to by p, that had been previously
-  allocated using malloc or a related routine such as realloc.
-  It has no effect if p is null. It can have arbitrary (i.e., bad!)
-  effects if p has already been freed.
-
-  Unless disabled (using mallopt), freeing very large spaces will
-  when possible, automatically trigger operations that give
-  back unused memory to the system, thus reducing program footprint.
-*/
-#if __STD_C
-void     public_fREe(Void_t*);
-#else
-void     public_fREe();
-#endif
-
-/*
-  calloc(size_t n_elements, size_t element_size);
-  Returns a pointer to n_elements * element_size bytes, with all locations
-  set to zero.
-*/
-#if __STD_C
-Void_t*  public_cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
-#else
-Void_t*  public_cALLOc();
-#endif
-
-/*
-  realloc(Void_t* p, size_t n)
-  Returns a pointer to a chunk of size n that contains the same data
-  as does chunk p up to the minimum of (n, p's size) bytes, or null
-  if no space is available.
-
-  The returned pointer may or may not be the same as p. The algorithm
-  prefers extending p when possible, otherwise it employs the
-  equivalent of a malloc-copy-free sequence.
-
-  If p is null, realloc is equivalent to malloc.
-
-  If space is not available, realloc returns null, errno is set (if on
-  ANSI) and p is NOT freed.
-
-  if n is for fewer bytes than already held by p, the newly unused
-  space is lopped off and freed if possible.  Unless the #define
-  REALLOC_ZERO_BYTES_FREES is set, realloc with a size argument of
-  zero (re)allocates a minimum-sized chunk.
-
-  Large chunks that were internally obtained via mmap will always
-  be reallocated using malloc-copy-free sequences unless
-  the system supports MREMAP (currently only linux).
-
-  The old unix realloc convention of allowing the last-free'd chunk
-  to be used as an argument to realloc is not supported.
-*/
-#if __STD_C
-Void_t*  public_rEALLOc(cvmx_arena_list_t arena_list, Void_t*, size_t);
-#else
-Void_t*  public_rEALLOc();
-#endif
-
-/*
-  memalign(size_t alignment, size_t n);
-  Returns a pointer to a newly allocated chunk of n bytes, aligned
-  in accord with the alignment argument.
-
-  The alignment argument should be a power of two. If the argument is
-  not a power of two, the nearest greater power is used.
-  8-byte alignment is guaranteed by normal malloc calls, so don't
-  bother calling memalign with an argument of 8 or less.
-
-  Overreliance on memalign is a sure way to fragment space.
-*/
-#if __STD_C
-Void_t*  public_mEMALIGn(cvmx_arena_list_t arena_list, size_t, size_t);
-#else
-Void_t*  public_mEMALIGn();
-#endif
-
-/*
-  valloc(size_t n);
-  Equivalent to memalign(pagesize, n), where pagesize is the page
-  size of the system. If the pagesize is unknown, 4096 is used.
-*/
-#if __STD_C
-Void_t*  public_vALLOc(size_t);
-#else
-Void_t*  public_vALLOc();
-#endif
-
-
-
-/*
-  mallopt(int parameter_number, int parameter_value)
-  Sets tunable parameters The format is to provide a
-  (parameter-number, parameter-value) pair.  mallopt then sets the
-  corresponding parameter to the argument value if it can (i.e., so
-  long as the value is meaningful), and returns 1 if successful else
-  0.  SVID/XPG/ANSI defines four standard param numbers for mallopt,
-  normally defined in malloc.h.  Only one of these (M_MXFAST) is used
-  in this malloc. The others (M_NLBLKS, M_GRAIN, M_KEEP) don't apply,
-  so setting them has no effect. But this malloc also supports four
-  other options in mallopt. See below for details.  Briefly, supported
-  parameters are as follows (listed defaults are for "typical"
-  configurations).
-
-  Symbol            param #   default    allowed param values
-  M_MXFAST          1         64         0-80  (0 disables fastbins)
-  M_TRIM_THRESHOLD -1         128*1024   any   (-1U disables trimming)
-  M_TOP_PAD        -2         0          any
-  M_MMAP_THRESHOLD -3         128*1024   any   (or 0 if no MMAP support)
-  M_MMAP_MAX       -4         65536      any   (0 disables use of mmap)
-*/
-#if __STD_C
-int      public_mALLOPt(int, int);
-#else
-int      public_mALLOPt();
-#endif
-
-
-/*
-  mallinfo()
-  Returns (by copy) a struct containing various summary statistics:
-
-  arena:     current total non-mmapped bytes allocated from system
-  ordblks:   the number of free chunks
-  smblks:    the number of fastbin blocks (i.e., small chunks that
-               have been freed but not use resused or consolidated)
-  hblks:     current number of mmapped regions
-  hblkhd:    total bytes held in mmapped regions
-  usmblks:   the maximum total allocated space. This will be greater
-                than current total if trimming has occurred.
-  fsmblks:   total bytes held in fastbin blocks
-  uordblks:  current total allocated space (normal or mmapped)
-  fordblks:  total free space
-  keepcost:  the maximum number of bytes that could ideally be released
-               back to system via malloc_trim. ("ideally" means that
-               it ignores page restrictions etc.)
-
-  Because these fields are ints, but internal bookkeeping may
-  be kept as longs, the reported values may wrap around zero and
-  thus be inaccurate.
-*/
-#if __STD_C
-struct mallinfo public_mALLINFo(void);
-#else
-struct mallinfo public_mALLINFo();
-#endif
-
-/*
-  independent_calloc(size_t n_elements, size_t element_size, Void_t* chunks[]);
-
-  independent_calloc is similar to calloc, but instead of returning a
-  single cleared space, it returns an array of pointers to n_elements
-  independent elements that can hold contents of size elem_size, each
-  of which starts out cleared, and can be independently freed,
-  realloc'ed etc. The elements are guaranteed to be adjacently
-  allocated (this is not guaranteed to occur with multiple callocs or
-  mallocs), which may also improve cache locality in some
-  applications.
-
-  The "chunks" argument is optional (i.e., may be null, which is
-  probably the most typical usage). If it is null, the returned array
-  is itself dynamically allocated and should also be freed when it is
-  no longer needed. Otherwise, the chunks array must be of at least
-  n_elements in length. It is filled in with the pointers to the
-  chunks.
-
-  In either case, independent_calloc returns this pointer array, or
-  null if the allocation failed.  If n_elements is zero and "chunks"
-  is null, it returns a chunk representing an array with zero elements
-  (which should be freed if not wanted).
-
-  Each element must be individually freed when it is no longer
-  needed. If you'd like to instead be able to free all at once, you
-  should instead use regular calloc and assign pointers into this
-  space to represent elements.  (In this case though, you cannot
-  independently free elements.)
-
-  independent_calloc simplifies and speeds up implementations of many
-  kinds of pools.  It may also be useful when constructing large data
-  structures that initially have a fixed number of fixed-sized nodes,
-  but the number is not known at compile time, and some of the nodes
-  may later need to be freed. For example:
-
-  struct Node { int item; struct Node* next; };
-
-  struct Node* build_list() {
-    struct Node** pool;
-    int n = read_number_of_nodes_needed();
-    if (n <= 0) return 0;
-    pool = (struct Node**)(independent_calloc(n, sizeof(struct Node), 0);
-    if (pool == 0) die();
-    // organize into a linked list...
-    struct Node* first = pool[0];
-    for (i = 0; i < n-1; ++i)
-      pool[i]->next = pool[i+1];
-    free(pool);     // Can now free the array (or not, if it is needed later)
-    return first;
-  }
-*/
-#if __STD_C
-Void_t** public_iCALLOc(size_t, size_t, Void_t**);
-#else
-Void_t** public_iCALLOc();
-#endif
-
-/*
-  independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
-
-  independent_comalloc allocates, all at once, a set of n_elements
-  chunks with sizes indicated in the "sizes" array.    It returns
-  an array of pointers to these elements, each of which can be
-  independently freed, realloc'ed etc. The elements are guaranteed to
-  be adjacently allocated (this is not guaranteed to occur with
-  multiple callocs or mallocs), which may also improve cache locality
-  in some applications.
-
-  The "chunks" argument is optional (i.e., may be null). If it is null
-  the returned array is itself dynamically allocated and should also
-  be freed when it is no longer needed. Otherwise, the chunks array
-  must be of at least n_elements in length. It is filled in with the
-  pointers to the chunks.
-
-  In either case, independent_comalloc returns this pointer array, or
-  null if the allocation failed.  If n_elements is zero and chunks is
-  null, it returns a chunk representing an array with zero elements
-  (which should be freed if not wanted).
-
-  Each element must be individually freed when it is no longer
-  needed. If you'd like to instead be able to free all at once, you
-  should instead use a single regular malloc, and assign pointers at
-  particular offsets in the aggregate space. (In this case though, you
-  cannot independently free elements.)
-
-  independent_comallac differs from independent_calloc in that each
-  element may have a different size, and also that it does not
-  automatically clear elements.
-
-  independent_comalloc can be used to speed up allocation in cases
-  where several structs or objects must always be allocated at the
-  same time.  For example:
-
-  struct Head { ... }
-  struct Foot { ... }
-
-  void send_message(char* msg) {
-    int msglen = strlen(msg);
-    size_t sizes[3] = { sizeof(struct Head), msglen, sizeof(struct Foot) };
-    void* chunks[3];
-    if (independent_comalloc(3, sizes, chunks) == 0)
-      die();
-    struct Head* head = (struct Head*)(chunks[0]);
-    char*        body = (char*)(chunks[1]);
-    struct Foot* foot = (struct Foot*)(chunks[2]);
-    // ...
-  }
-
-  In general though, independent_comalloc is worth using only for
-  larger values of n_elements. For small values, you probably won't
-  detect enough difference from series of malloc calls to bother.
-
-  Overuse of independent_comalloc can increase overall memory usage,
-  since it cannot reuse existing noncontiguous small chunks that
-  might be available for some of the elements.
-*/
-#if __STD_C
-Void_t** public_iCOMALLOc(size_t, size_t*, Void_t**);
-#else
-Void_t** public_iCOMALLOc();
-#endif
-
-
-/*
-  pvalloc(size_t n);
-  Equivalent to valloc(minimum-page-that-holds(n)), that is,
-  round up n to nearest pagesize.
- */
-#if __STD_C
-Void_t*  public_pVALLOc(size_t);
-#else
-Void_t*  public_pVALLOc();
-#endif
-
-/*
-  cfree(Void_t* p);
-  Equivalent to free(p).
-
-  cfree is needed/defined on some systems that pair it with calloc,
-  for odd historical reasons (such as: cfree is used in example
-  code in the first edition of K&R).
-*/
-#if __STD_C
-void     public_cFREe(Void_t*);
-#else
-void     public_cFREe();
-#endif
-
-/*
-  malloc_trim(size_t pad);
-
-  If possible, gives memory back to the system (via negative
-  arguments to sbrk) if there is unused memory at the `high' end of
-  the malloc pool. You can call this after freeing large blocks of
-  memory to potentially reduce the system-level memory requirements
-  of a program. However, it cannot guarantee to reduce memory. Under
-  some allocation patterns, some large free blocks of memory will be
-  locked between two used chunks, so they cannot be given back to
-  the system.
-
-  The `pad' argument to malloc_trim represents the amount of free
-  trailing space to leave untrimmed. If this argument is zero,
-  only the minimum amount of memory to maintain internal data
-  structures will be left (one page or less). Non-zero arguments
-  can be supplied to maintain enough trailing space to service
-  future expected allocations without having to re-obtain memory
-  from the system.
-
-  Malloc_trim returns 1 if it actually released any memory, else 0.
-  On systems that do not support "negative sbrks", it will always
-  rreturn 0.
-*/
-#if __STD_C
-int      public_mTRIm(size_t);
-#else
-int      public_mTRIm();
-#endif
-
-/*
-  malloc_usable_size(Void_t* p);
-
-  Returns the number of bytes you can actually use in
-  an allocated chunk, which may be more than you requested (although
-  often not) due to alignment and minimum size constraints.
-  You can use this many bytes without worrying about
-  overwriting other allocated objects. This is not a particularly great
-  programming practice. malloc_usable_size can be more useful in
-  debugging and assertions, for example:
-
-  p = malloc(n);
-  assert(malloc_usable_size(p) >= 256);
-
-*/
-#if __STD_C
-size_t   public_mUSABLe(Void_t*);
-#else
-size_t   public_mUSABLe();
-#endif
-
-/*
-  malloc_stats();
-  Prints on stderr the amount of space obtained from the system (both
-  via sbrk and mmap), the maximum amount (which may be more than
-  current if malloc_trim and/or munmap got called), and the current
-  number of bytes allocated via malloc (or realloc, etc) but not yet
-  freed. Note that this is the number of bytes allocated, not the
-  number requested. It will be larger than the number requested
-  because of alignment and bookkeeping overhead. Because it includes
-  alignment wastage as being in use, this figure may be greater than
-  zero even when no user-level chunks are allocated.
-
-  The reported current and maximum system memory can be inaccurate if
-  a program makes other calls to system memory allocation functions
-  (normally sbrk) outside of malloc.
-
-  malloc_stats prints only the most commonly interesting statistics.
-  More information can be obtained by calling mallinfo.
-
-*/
-#if __STD_C
-void     public_mSTATs(void);
-#else
-void     public_mSTATs();
-#endif
-
-/*
-  malloc_get_state(void);
-
-  Returns the state of all malloc variables in an opaque data
-  structure.
-*/
-#if __STD_C
-Void_t*  public_gET_STATe(void);
-#else
-Void_t*  public_gET_STATe();
-#endif
-
-/*
-  malloc_set_state(Void_t* state);
-
-  Restore the state of all malloc variables from data obtained with
-  malloc_get_state().
-*/
-#if __STD_C
-int      public_sET_STATe(Void_t*);
-#else
-int      public_sET_STATe();
-#endif
-
-#ifdef _LIBC
-/*
-  posix_memalign(void **memptr, size_t alignment, size_t size);
-
-  POSIX wrapper like memalign(), checking for validity of size.
-*/
-int      __posix_memalign(void **, size_t, size_t);
-#endif
-
-/* mallopt tuning options */
-
-/*
-  M_MXFAST is the maximum request size used for "fastbins", special bins
-  that hold returned chunks without consolidating their spaces. This
-  enables future requests for chunks of the same size to be handled
-  very quickly, but can increase fragmentation, and thus increase the
-  overall memory footprint of a program.
-
-  This malloc manages fastbins very conservatively yet still
-  efficiently, so fragmentation is rarely a problem for values less
-  than or equal to the default.  The maximum supported value of MXFAST
-  is 80. You wouldn't want it any higher than this anyway.  Fastbins
-  are designed especially for use with many small structs, objects or
-  strings -- the default handles structs/objects/arrays with sizes up
-  to 8 4byte fields, or small strings representing words, tokens,
-  etc. Using fastbins for larger objects normally worsens
-  fragmentation without improving speed.
-
-  M_MXFAST is set in REQUEST size units. It is internally used in
-  chunksize units, which adds padding and alignment.  You can reduce
-  M_MXFAST to 0 to disable all use of fastbins.  This causes the malloc
-  algorithm to be a closer approximation of fifo-best-fit in all cases,
-  not just for larger requests, but will generally cause it to be
-  slower.
-*/
-
-
-/* M_MXFAST is a standard SVID/XPG tuning option, usually listed in malloc.h */
-#ifndef M_MXFAST
-#define M_MXFAST            1
-#endif
-
-#ifndef DEFAULT_MXFAST
-#define DEFAULT_MXFAST     64
-#endif
-
-
-/*
-  M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
-  to keep before releasing via malloc_trim in free().
-
-  Automatic trimming is mainly useful in long-lived programs.
-  Because trimming via sbrk can be slow on some systems, and can
-  sometimes be wasteful (in cases where programs immediately
-  afterward allocate more large chunks) the value should be high
-  enough so that your overall system performance would improve by
-  releasing this much memory.
-
-  The trim threshold and the mmap control parameters (see below)
-  can be traded off with one another. Trimming and mmapping are
-  two different ways of releasing unused memory back to the
-  system. Between these two, it is often possible to keep
-  system-level demands of a long-lived program down to a bare
-  minimum. For example, in one test suite of sessions measuring
-  the XF86 X server on Linux, using a trim threshold of 128K and a
-  mmap threshold of 192K led to near-minimal long term resource
-  consumption.
-
-  If you are using this malloc in a long-lived program, it should
-  pay to experiment with these values.  As a rough guide, you
-  might set to a value close to the average size of a process
-  (program) running on your system.  Releasing this much memory
-  would allow such a process to run in memory.  Generally, it's
-  worth it to tune for trimming rather tham memory mapping when a
-  program undergoes phases where several large chunks are
-  allocated and released in ways that can reuse each other's
-  storage, perhaps mixed with phases where there are no such
-  chunks at all.  And in well-behaved long-lived programs,
-  controlling release of large blocks via trimming versus mapping
-  is usually faster.
-
-  However, in most programs, these parameters serve mainly as
-  protection against the system-level effects of carrying around
-  massive amounts of unneeded memory. Since frequent calls to
-  sbrk, mmap, and munmap otherwise degrade performance, the default
-  parameters are set to relatively high values that serve only as
-  safeguards.
-
-  The trim value It must be greater than page size to have any useful
-  effect.  To disable trimming completely, you can set to
-  (unsigned long)(-1)
-
-  Trim settings interact with fastbin (MXFAST) settings: Unless
-  TRIM_FASTBINS is defined, automatic trimming never takes place upon
-  freeing a chunk with size less than or equal to MXFAST. Trimming is
-  instead delayed until subsequent freeing of larger chunks. However,
-  you can still force an attempted trim by calling malloc_trim.
-
-  Also, trimming is not generally possible in cases where
-  the main arena is obtained via mmap.
-
-  Note that the trick some people use of mallocing a huge space and
-  then freeing it at program startup, in an attempt to reserve system
-  memory, doesn't have the intended effect under automatic trimming,
-  since that memory will immediately be returned to the system.
-*/
-
-#define M_TRIM_THRESHOLD       -1
-
-#ifndef DEFAULT_TRIM_THRESHOLD
-#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
-#endif
-
-/*
-  M_TOP_PAD is the amount of extra `padding' space to allocate or
-  retain whenever sbrk is called. It is used in two ways internally:
-
-  * When sbrk is called to extend the top of the arena to satisfy
-  a new malloc request, this much padding is added to the sbrk
-  request.
-
-  * When malloc_trim is called automatically from free(),
-  it is used as the `pad' argument.
-
-  In both cases, the actual amount of padding is rounded
-  so that the end of the arena is always a system page boundary.
-
-  The main reason for using padding is to avoid calling sbrk so
-  often. Having even a small pad greatly reduces the likelihood
-  that nearly every malloc request during program start-up (or
-  after trimming) will invoke sbrk, which needlessly wastes
-  time.
-
-  Automatic rounding-up to page-size units is normally sufficient
-  to avoid measurable overhead, so the default is 0.  However, in
-  systems where sbrk is relatively slow, it can pay to increase
-  this value, at the expense of carrying around more memory than
-  the program needs.
-*/
-
-#define M_TOP_PAD              -2
-
-#ifndef DEFAULT_TOP_PAD
-#define DEFAULT_TOP_PAD        (0)
-#endif
-
-/*
-  M_MMAP_THRESHOLD is the request size threshold for using mmap()
-  to service a request. Requests of at least this size that cannot
-  be allocated using already-existing space will be serviced via mmap.
-  (If enough normal freed space already exists it is used instead.)
-
-  Using mmap segregates relatively large chunks of memory so that
-  they can be individually obtained and released from the host
-  system. A request serviced through mmap is never reused by any
-  other request (at least not directly; the system may just so
-  happen to remap successive requests to the same locations).
-
-  Segregating space in this way has the benefits that:
-
-   1. Mmapped space can ALWAYS be individually released back
-      to the system, which helps keep the system level memory
-      demands of a long-lived program low.
-   2. Mapped memory can never become `locked' between
-      other chunks, as can happen with normally allocated chunks, which
-      means that even trimming via malloc_trim would not release them.
-   3. On some systems with "holes" in address spaces, mmap can obtain
-      memory that sbrk cannot.
-
-  However, it has the disadvantages that:
-
-   1. The space cannot be reclaimed, consolidated, and then
-      used to service later requests, as happens with normal chunks.
-   2. It can lead to more wastage because of mmap page alignment
-      requirements
-   3. It causes malloc performance to be more dependent on host
-      system memory management support routines which may vary in
-      implementation quality and may impose arbitrary
-      limitations. Generally, servicing a request via normal
-      malloc steps is faster than going through a system's mmap.
-
-  The advantages of mmap nearly always outweigh disadvantages for
-  "large" chunks, but the value of "large" varies across systems.  The
-  default is an empirically derived value that works well in most
-  systems.
-*/
-
-#define M_MMAP_THRESHOLD      -3
-
-#ifndef DEFAULT_MMAP_THRESHOLD
-#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
-#endif
-
-/*
-  M_MMAP_MAX is the maximum number of requests to simultaneously
-  service using mmap. This parameter exists because
-  some systems have a limited number of internal tables for
-  use by mmap, and using more than a few of them may degrade
-  performance.
-
-  The default is set to a value that serves only as a safeguard.
-  Setting to 0 disables use of mmap for servicing large requests.  If
-  HAVE_MMAP is not set, the default value is 0, and attempts to set it
-  to non-zero values in mallopt will fail.
-*/
-
-#define M_MMAP_MAX             -4
-
-#ifndef DEFAULT_MMAP_MAX
-#if HAVE_MMAP
-#define DEFAULT_MMAP_MAX       (65536)
-#else
-#define DEFAULT_MMAP_MAX       (0)
-#endif
-#endif
-
-#ifdef __cplusplus
-};  /* end of extern "C" */
-#endif
-
-#include <cvmx-spinlock.h>
-#include "malloc.h"
-#include "thread-m.h"
-
-#ifdef DEBUG_PRINTS
-#define debug_printf    printf
-#else
-#define debug_printf(format, args...)  
-#endif
-
-#ifndef BOUNDED_N
-#define BOUNDED_N(ptr, sz) (ptr)
-#endif
-#ifndef RETURN_ADDRESS
-#define RETURN_ADDRESS(X_) (NULL)
-#endif
-
-/* On some platforms we can compile internal, not exported functions better.
-   Let the environment provide a macro and define it to be empty if it
-   is not available.  */
-#ifndef internal_function
-# define internal_function
-#endif
-
-/* Forward declarations.  */
-struct malloc_chunk;
-typedef struct malloc_chunk* mchunkptr;
-
-/* Internal routines.  */
-
-#if __STD_C
-
-static Void_t*         _int_malloc(mstate, size_t);
-static void            _int_free(mstate, Void_t*);
-static Void_t*         _int_realloc(mstate, Void_t*, size_t);
-static Void_t*         _int_memalign(mstate, size_t, size_t);
-static Void_t*         _int_valloc(mstate, size_t);
-static Void_t*  _int_pvalloc(mstate, size_t);
-static Void_t*  cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
-static Void_t** _int_icalloc(mstate, size_t, size_t, Void_t**);
-static Void_t** _int_icomalloc(mstate, size_t, size_t*, Void_t**);
-static int      mTRIm(size_t);
-static size_t   mUSABLe(Void_t*);
-static void     mSTATs(void);
-static int      mALLOPt(int, int);
-static struct mallinfo mALLINFo(mstate);
-
-static Void_t* internal_function mem2mem_check(Void_t *p, size_t sz);
-static int internal_function top_check(void);
-static void internal_function munmap_chunk(mchunkptr p);
-#if HAVE_MREMAP
-static mchunkptr internal_function mremap_chunk(mchunkptr p, size_t new_size);
-#endif
-
-static Void_t*   malloc_check(size_t sz, const Void_t *caller);
-static void      free_check(Void_t* mem, const Void_t *caller);
-static Void_t*   realloc_check(Void_t* oldmem, size_t bytes,
-			       const Void_t *caller);
-static Void_t*   memalign_check(size_t alignment, size_t bytes,
-				const Void_t *caller);
-#ifndef NO_THREADS
-static Void_t*   malloc_starter(size_t sz, const Void_t *caller);
-static void      free_starter(Void_t* mem, const Void_t *caller);
-static Void_t*   malloc_atfork(size_t sz, const Void_t *caller);
-static void      free_atfork(Void_t* mem, const Void_t *caller);
-#endif
-
-#else
-
-Void_t*         _int_malloc();
-void            _int_free();
-Void_t*         _int_realloc();
-Void_t*         _int_memalign();
-Void_t*         _int_valloc();
-Void_t*         _int_pvalloc();
-/*static Void_t*  cALLOc();*/
-static Void_t** _int_icalloc();
-static Void_t** _int_icomalloc();
-static int      mTRIm();
-static size_t   mUSABLe();
-static void     mSTATs();
-static int      mALLOPt();
-static struct mallinfo mALLINFo();
-
-#endif
-
-
-
-
-/* ------------- Optional versions of memcopy ---------------- */
-
-
-#if USE_MEMCPY
-
-/*
-  Note: memcpy is ONLY invoked with non-overlapping regions,
-  so the (usually slower) memmove is not needed.
-*/
-
-#define MALLOC_COPY(dest, src, nbytes)  memcpy(dest, src, nbytes)
-#define MALLOC_ZERO(dest, nbytes)       memset(dest, 0,   nbytes)
-
-#else /* !USE_MEMCPY */
-
-/* Use Duff's device for good zeroing/copying performance. */
-
-#define MALLOC_ZERO(charp, nbytes)                                            \
-do {                                                                          \
-  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
-  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
-  long mcn;                                                                   \
-  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
-  switch (mctmp) {                                                            \
-    case 0: for(;;) { *mzp++ = 0;                                             \
-    case 7:           *mzp++ = 0;                                             \
-    case 6:           *mzp++ = 0;                                             \
-    case 5:           *mzp++ = 0;                                             \
-    case 4:           *mzp++ = 0;                                             \
-    case 3:           *mzp++ = 0;                                             \
-    case 2:           *mzp++ = 0;                                             \
-    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
-  }                                                                           \
-} while(0)
-
-#define MALLOC_COPY(dest,src,nbytes)                                          \
-do {                                                                          \
-  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
-  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
-  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
-  long mcn;                                                                   \
-  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
-  switch (mctmp) {                                                            \
-    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
-    case 7:           *mcdst++ = *mcsrc++;                                    \
-    case 6:           *mcdst++ = *mcsrc++;                                    \
-    case 5:           *mcdst++ = *mcsrc++;                                    \
-    case 4:           *mcdst++ = *mcsrc++;                                    \
-    case 3:           *mcdst++ = *mcsrc++;                                    \
-    case 2:           *mcdst++ = *mcsrc++;                                    \
-    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
-  }                                                                           \
-} while(0)
-
-#endif
-
-/* ------------------ MMAP support ------------------  */
-
-
-#if HAVE_MMAP
-
-#include <fcntl.h>
-#ifndef LACKS_SYS_MMAN_H
-#include <sys/mman.h>
-#endif
-
-#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
-# define MAP_ANONYMOUS MAP_ANON
-#endif
-#if !defined(MAP_FAILED)
-# define MAP_FAILED ((char*)-1)
-#endif
-
-#ifndef MAP_NORESERVE
-# ifdef MAP_AUTORESRV
-#  define MAP_NORESERVE MAP_AUTORESRV
-# else
-#  define MAP_NORESERVE 0
-# endif
-#endif
-
-/*
-   Nearly all versions of mmap support MAP_ANONYMOUS,
-   so the following is unlikely to be needed, but is
-   supplied just in case.
-*/
-
-#ifndef MAP_ANONYMOUS
-
-static int dev_zero_fd = -1; /* Cached file descriptor for /dev/zero. */
-
-#define MMAP(addr, size, prot, flags) ((dev_zero_fd < 0) ? \
- (dev_zero_fd = open("/dev/zero", O_RDWR), \
-  mmap((addr), (size), (prot), (flags), dev_zero_fd, 0)) : \
-   mmap((addr), (size), (prot), (flags), dev_zero_fd, 0))
-
-#else
-
-#define MMAP(addr, size, prot, flags) \
- (mmap((addr), (size), (prot), (flags)|MAP_ANONYMOUS, -1, 0))
-
-#endif
-
-
-#endif /* HAVE_MMAP */
-
-
-/*
-  -----------------------  Chunk representations -----------------------
-*/
-
-
-/*
-  This struct declaration is misleading (but accurate and necessary).
-  It declares a "view" into memory allowing access to necessary
-  fields at known offsets from a given base. See explanation below.
-*/
-struct malloc_chunk {
-
-  INTERNAL_SIZE_T      prev_size;  /* Size of previous chunk (if free).  */
-  INTERNAL_SIZE_T      size;       /* Size in bytes, including overhead. */
-  mstate               arena_ptr;  /* ptr to arena chunk belongs to */
-
-  struct malloc_chunk* fd;         /* double links -- used only if free. */
-  struct malloc_chunk* bk;
-};
-
-
-/*
-   malloc_chunk details:
-
-    (The following includes lightly edited explanations by Colin Plumb.)
-
-    Chunks of memory are maintained using a `boundary tag' method as
-    described in e.g., Knuth or Standish.  (See the paper by Paul
-    Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a
-    survey of such techniques.)  Sizes of free chunks are stored both
-    in the front of each chunk and at the end.  This makes
-    consolidating fragmented chunks into bigger chunks very fast.  The
-    size fields also hold bits representing whether chunks are free or
-    in use.
-
-    An allocated chunk looks like this:
-
-
-    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Size of previous chunk, if allocated            | |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Size of chunk, in bytes                         |P|
-      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             User data starts here...                          .
-            .                                                               .
-            .             (malloc_usable_space() bytes)                     .
-            .                                                               |
-nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Size of chunk                                     |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-
-
-    Where "chunk" is the front of the chunk for the purpose of most of
-    the malloc code, but "mem" is the pointer that is returned to the
-    user.  "Nextchunk" is the beginning of the next contiguous chunk.
-
-    Chunks always begin on even word boundries, so the mem portion
-    (which is returned to the user) is also on an even word boundary, and
-    thus at least double-word aligned.
-
-    Free chunks are stored in circular doubly-linked lists, and look like this:
-
-    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Size of previous chunk                            |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-    `head:' |             Size of chunk, in bytes                         |P|
-      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Forward pointer to next chunk in list             |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Back pointer to previous chunk in list            |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-            |             Unused space (may be 0 bytes long)                .
-            .                                                               .
-            .                                                               |
-nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-    `foot:' |             Size of chunk, in bytes                           |
-            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-
-    The P (PREV_INUSE) bit, stored in the unused low-order bit of the
-    chunk size (which is always a multiple of two words), is an in-use
-    bit for the *previous* chunk.  If that bit is *clear*, then the
-    word before the current chunk size contains the previous chunk
-    size, and can be used to find the front of the previous chunk.
-    The very first chunk allocated always has this bit set,
-    preventing access to non-existent (or non-owned) memory. If
-    prev_inuse is set for any given chunk, then you CANNOT determine
-    the size of the previous chunk, and might even get a memory
-    addressing fault when trying to do so.
-
-    Note that the `foot' of the current chunk is actually represented
-    as the prev_size of the NEXT chunk. This makes it easier to
-    deal with alignments etc but can be very confusing when trying
-    to extend or adapt this code.
-
-    The two exceptions to all this are
-
-     1. The special chunk `top' doesn't bother using the
-        trailing size field since there is no next contiguous chunk
-        that would have to index off it. After initialization, `top'
-        is forced to always exist.  If it would become less than
-        MINSIZE bytes long, it is replenished.
-
-     2. Chunks allocated via mmap, which have the second-lowest-order
-        bit (IS_MMAPPED) set in their size fields.  Because they are
-        allocated one-by-one, each must contain its own trailing size field.
-
-*/
-
-/*
-  ---------- Size and alignment checks and conversions ----------
-*/
-
-/* conversion from malloc headers to user pointers, and back */
-/* Added size for pointer to make room for arena_ptr */
-#define chunk2mem(p)   ((Void_t*)((char*)(p) + 2*SIZE_SZ + sizeof(void *)))
-#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ - sizeof(void *)))
-
-/* The smallest possible chunk */
-#define MIN_CHUNK_SIZE        (sizeof(struct malloc_chunk))
-
-/* The smallest size we can malloc is an aligned minimal chunk */
-
-#define MINSIZE  \
-  (unsigned long)(((MIN_CHUNK_SIZE+MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK))
-
-/* Check if m has acceptable alignment */
-
-#define aligned_OK(m)  (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0)
-
-
-/*
-   Check if a request is so large that it would wrap around zero when
-   padded and aligned. To simplify some other code, the bound is made
-   low enough so that adding MINSIZE will also not wrap around zero.
-*/
-
-#define REQUEST_OUT_OF_RANGE(req)                                 \
-  ((unsigned long)(req) >=                                        \
-   (unsigned long)(INTERNAL_SIZE_T)(-2 * MINSIZE))
-
-/* pad request bytes into a usable size -- internal version */
-
-
-/* prev_size field of next chunk is overwritten with data
-** when in use.  NOTE - last SIZE_SZ of arena must be left
-** unused for last chunk to use
-*/
-/* Added sizeof(void *) to make room for arena_ptr */
-#define request2size(req)                                         \
-  (((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK < MINSIZE)  ?             \
-   MINSIZE :                                                      \
-   ((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK)
-
-/*  Same, except also perform argument check */
-
-#define checked_request2size(req, sz)                             \
-  if (REQUEST_OUT_OF_RANGE(req)) {                                \
-    MALLOC_FAILURE_ACTION;                                        \
-    return 0;                                                     \
-  }                                                               \
-  (sz) = request2size(req);
-
-/*
-  --------------- Physical chunk operations ---------------
-*/
-
-
-/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */
-#define PREV_INUSE 0x1
-
-/* extract inuse bit of previous chunk */
-#define prev_inuse(p)       ((p)->size & PREV_INUSE)
-
-
-/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */
-#define IS_MMAPPED 0x2
-
-/* check for mmap()'ed chunk */
-#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
-
-
-
-/*
-  Bits to mask off when extracting size
-
-  Note: IS_MMAPPED is intentionally not masked off from size field in
-  macros for which mmapped chunks should never be seen. This should
-  cause helpful core dumps to occur if it is tried by accident by
-  people extending or adapting this malloc.
-*/
-#define SIZE_BITS (PREV_INUSE|IS_MMAPPED)
-
-/* Get size, ignoring use bits */
-#define chunksize(p)         ((p)->size & ~(SIZE_BITS))
-
-
-/* Ptr to next physical malloc_chunk. */
-#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~SIZE_BITS) ))
-
-/* Ptr to previous physical malloc_chunk */
-#define prev_chunk(p) ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) ))
-
-/* Treat space at ptr + offset as a chunk */
-#define chunk_at_offset(p, s)  ((mchunkptr)(((char*)(p)) + (s)))
-
-/* extract p's inuse bit */
-#define inuse(p)\
-((((mchunkptr)(((char*)(p))+((p)->size & ~SIZE_BITS)))->size) & PREV_INUSE)
-
-/* set/clear chunk as being inuse without otherwise disturbing */
-#define set_inuse(p)\
-((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size |= PREV_INUSE
-
-#define clear_inuse(p)\
-((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size &= ~(PREV_INUSE)
-
-
-/* check/set/clear inuse bits in known places */
-#define inuse_bit_at_offset(p, s)\
- (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE)
-
-#define set_inuse_bit_at_offset(p, s)\
- (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE)
-
-#define clear_inuse_bit_at_offset(p, s)\
- (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE))
-
-
-/* Set size at head, without disturbing its use bit */
-#define set_head_size(p, s)  ((p)->size = (((p)->size & SIZE_BITS) | (s)))
-
-/* Set size/use field */
-#define set_head(p, s)       ((p)->size = (s))
-
-/* Set size at footer (only when chunk is not in use) */
-#define set_foot(p, s)       (((mchunkptr)((char*)(p) + (s)))->prev_size = (s))
-
-
-/*
-  -------------------- Internal data structures --------------------
-
-   All internal state is held in an instance of malloc_state defined
-   below. There are no other static variables, except in two optional
-   cases:
-   * If USE_MALLOC_LOCK is defined, the mALLOC_MUTEx declared above.
-   * If HAVE_MMAP is true, but mmap doesn't support
-     MAP_ANONYMOUS, a dummy file descriptor for mmap.
-
-   Beware of lots of tricks that minimize the total bookkeeping space
-   requirements. The result is a little over 1K bytes (for 4byte
-   pointers and size_t.)
-*/
-
-/*
-  Bins
-
-    An array of bin headers for free chunks. Each bin is doubly
-    linked.  The bins are approximately proportionally (log) spaced.
-    There are a lot of these bins (128). This may look excessive, but
-    works very well in practice.  Most bins hold sizes that are
-    unusual as malloc request sizes, but are more usual for fragments
-    and consolidated sets of chunks, which is what these bins hold, so
-    they can be found quickly.  All procedures maintain the invariant
-    that no consolidated chunk physically borders another one, so each
-    chunk in a list is known to be preceeded and followed by either
-    inuse chunks or the ends of memory.
-
-    Chunks in bins are kept in size order, with ties going to the
-    approximately least recently used chunk. Ordering isn't needed
-    for the small bins, which all contain the same-sized chunks, but
-    facilitates best-fit allocation for larger chunks. These lists
-    are just sequential. Keeping them in order almost never requires
-    enough traversal to warrant using fancier ordered data
-    structures.
-
-    Chunks of the same size are linked with the most
-    recently freed at the front, and allocations are taken from the
-    back.  This results in LRU (FIFO) allocation order, which tends
-    to give each chunk an equal opportunity to be consolidated with
-    adjacent freed chunks, resulting in larger free chunks and less
-    fragmentation.
-
-    To simplify use in double-linked lists, each bin header acts
-    as a malloc_chunk. This avoids special-casing for headers.
-    But to conserve space and improve locality, we allocate
-    only the fd/bk pointers of bins, and then use repositioning tricks
-    to treat these as the fields of a malloc_chunk*.
-*/
-
-typedef struct malloc_chunk* mbinptr;
-
-/* addressing -- note that bin_at(0) does not exist */
-#define bin_at(m, i) ((mbinptr)((char*)&((m)->bins[(i)<<1]) - (SIZE_SZ<<1)))
-
-/* analog of ++bin */
-#define next_bin(b)  ((mbinptr)((char*)(b) + (sizeof(mchunkptr)<<1)))
-
-/* Reminders about list directionality within bins */
-#define first(b)     ((b)->fd)
-#define last(b)      ((b)->bk)
-
-/* Take a chunk off a bin list */
-#define unlink(P, BK, FD) {                                            \
-  FD = P->fd;                                                          \
-  BK = P->bk;                                                          \
-  FD->bk = BK;                                                         \
-  BK->fd = FD;                                                         \
-}
-
-/*
-  Indexing
-
-    Bins for sizes < 512 bytes contain chunks of all the same size, spaced
-    8 bytes apart. Larger bins are approximately logarithmically spaced:
-
-    64 bins of size       8
-    32 bins of size      64
-    16 bins of size     512
-     8 bins of size    4096
-     4 bins of size   32768
-     2 bins of size  262144
-     1 bin  of size what's left
-
-    There is actually a little bit of slop in the numbers in bin_index
-    for the sake of speed. This makes no difference elsewhere.
-
-    The bins top out around 1MB because we expect to service large
-    requests via mmap.
-*/
-
-#define NBINS             128
-#define NSMALLBINS         64
-#define SMALLBIN_WIDTH      8
-#define MIN_LARGE_SIZE    512
-
-#define in_smallbin_range(sz)  \
-  ((unsigned long)(sz) < (unsigned long)MIN_LARGE_SIZE)
-
-#define smallbin_index(sz)     (((unsigned)(sz)) >> 3)
-
-#define largebin_index(sz)                                                   \
-(((((unsigned long)(sz)) >>  6) <= 32)?  56 + (((unsigned long)(sz)) >>  6): \
- ((((unsigned long)(sz)) >>  9) <= 20)?  91 + (((unsigned long)(sz)) >>  9): \
- ((((unsigned long)(sz)) >> 12) <= 10)? 110 + (((unsigned long)(sz)) >> 12): \
- ((((unsigned long)(sz)) >> 15) <=  4)? 119 + (((unsigned long)(sz)) >> 15): \
- ((((unsigned long)(sz)) >> 18) <=  2)? 124 + (((unsigned long)(sz)) >> 18): \
-                                        126)
-
-#define bin_index(sz) \
- ((in_smallbin_range(sz)) ? smallbin_index(sz) : largebin_index(sz))
-
-/*
-  FIRST_SORTED_BIN_SIZE is the chunk size corresponding to the
-  first bin that is maintained in sorted order. This must
-  be the smallest size corresponding to a given bin.
-
-  Normally, this should be MIN_LARGE_SIZE. But you can weaken
-  best fit guarantees to sometimes speed up malloc by increasing value.
-  Doing this means that malloc may choose a chunk that is 
-  non-best-fitting by up to the width of the bin.
-
-  Some useful cutoff values:
-      512 - all bins sorted
-     2560 - leaves bins <=     64 bytes wide unsorted  
-    12288 - leaves bins <=    512 bytes wide unsorted
-    65536 - leaves bins <=   4096 bytes wide unsorted
-   262144 - leaves bins <=  32768 bytes wide unsorted
-       -1 - no bins sorted (not recommended!)
-*/
-
-#define FIRST_SORTED_BIN_SIZE MIN_LARGE_SIZE 
-/* #define FIRST_SORTED_BIN_SIZE 65536 */
-
-/*
-  Unsorted chunks
-
-    All remainders from chunk splits, as well as all returned chunks,
-    are first placed in the "unsorted" bin. They are then placed
-    in regular bins after malloc gives them ONE chance to be used before
-    binning. So, basically, the unsorted_chunks list acts as a queue,
-    with chunks being placed on it in free (and malloc_consolidate),
-    and taken off (to be either used or placed in bins) in malloc.
-
-    The NON_MAIN_ARENA flag is never set for unsorted chunks, so it
-    does not have to be taken into account in size comparisons.
-*/
-
-/* The otherwise unindexable 1-bin is used to hold unsorted chunks. */
-#define unsorted_chunks(M)          (bin_at(M, 1))
-
-/*
-  Top
-
-    The top-most available chunk (i.e., the one bordering the end of
-    available memory) is treated specially. It is never included in
-    any bin, is used only if no other chunk is available, and is
-    released back to the system if it is very large (see
-    M_TRIM_THRESHOLD).  Because top initially
-    points to its own bin with initial zero size, thus forcing
-    extension on the first malloc request, we avoid having any special
-    code in malloc to check whether it even exists yet. But we still
-    need to do so when getting memory from system, so we make
-    initial_top treat the bin as a legal but unusable chunk during the
-    interval between initialization and the first call to
-    sYSMALLOc. (This is somewhat delicate, since it relies on
-    the 2 preceding words to be zero during this interval as well.)
-*/
-
-/* Conveniently, the unsorted bin can be used as dummy top on first call */
-#define initial_top(M)              (unsorted_chunks(M))
-
-/*
-  Binmap
-
-    To help compensate for the large number of bins, a one-level index
-    structure is used for bin-by-bin searching.  `binmap' is a
-    bitvector recording whether bins are definitely empty so they can
-    be skipped over during during traversals.  The bits are NOT always
-    cleared as soon as bins are empty, but instead only
-    when they are noticed to be empty during traversal in malloc.
-*/
-
-/* Conservatively use 32 bits per map word, even if on 64bit system */
-#define BINMAPSHIFT      5
-#define BITSPERMAP       (1U << BINMAPSHIFT)
-#define BINMAPSIZE       (NBINS / BITSPERMAP)
-
-#define idx2block(i)     ((i) >> BINMAPSHIFT)
-#define idx2bit(i)       ((1U << ((i) & ((1U << BINMAPSHIFT)-1))))
-
-#define mark_bin(m,i)    ((m)->binmap[idx2block(i)] |=  idx2bit(i))
-#define unmark_bin(m,i)  ((m)->binmap[idx2block(i)] &= ~(idx2bit(i)))
-#define get_binmap(m,i)  ((m)->binmap[idx2block(i)] &   idx2bit(i))
-
-/*
-  Fastbins
-
-    An array of lists holding recently freed small chunks.  Fastbins
-    are not doubly linked.  It is faster to single-link them, and
-    since chunks are never removed from the middles of these lists,
-    double linking is not necessary. Also, unlike regular bins, they
-    are not even processed in FIFO order (they use faster LIFO) since
-    ordering doesn't much matter in the transient contexts in which
-    fastbins are normally used.
-
-    Chunks in fastbins keep their inuse bit set, so they cannot
-    be consolidated with other free chunks. malloc_consolidate
-    releases all chunks in fastbins and consolidates them with
-    other free chunks.
-*/
-
-typedef struct malloc_chunk* mfastbinptr;
-
-/* offset 2 to use otherwise unindexable first 2 bins */
-#define fastbin_index(sz)        ((int)((((unsigned int)(sz)) >> 3) - 2))
-
-/* The maximum fastbin request size we support */
-#define MAX_FAST_SIZE     80
-
-#define NFASTBINS  (fastbin_index(request2size(MAX_FAST_SIZE))+1)
-
-/*
-  FASTBIN_CONSOLIDATION_THRESHOLD is the size of a chunk in free()
-  that triggers automatic consolidation of possibly-surrounding
-  fastbin chunks. This is a heuristic, so the exact value should not
-  matter too much. It is defined at half the default trim threshold as a
-  compromise heuristic to only attempt consolidation if it is likely
-  to lead to trimming. However, it is not dynamically tunable, since
-  consolidation reduces fragmentation surrounding large chunks even
-  if trimming is not used.
-*/
-
-#define FASTBIN_CONSOLIDATION_THRESHOLD  (65536UL)
-
-/*
-  Since the lowest 2 bits in max_fast don't matter in size comparisons,
-  they are used as flags.
-*/
-
-/*
-  FASTCHUNKS_BIT held in max_fast indicates that there are probably
-  some fastbin chunks. It is set true on entering a chunk into any
-  fastbin, and cleared only in malloc_consolidate.
-
-  The truth value is inverted so that have_fastchunks will be true
-  upon startup (since statics are zero-filled), simplifying
-  initialization checks.
-*/
-
-#define FASTCHUNKS_BIT        (1U)
-
-#define have_fastchunks(M)     (((M)->max_fast &  FASTCHUNKS_BIT) == 0)
-#define clear_fastchunks(M)    ((M)->max_fast |=  FASTCHUNKS_BIT)
-#define set_fastchunks(M)      ((M)->max_fast &= ~FASTCHUNKS_BIT)
-
-/*
-  NONCONTIGUOUS_BIT indicates that MORECORE does not return contiguous
-  regions.  Otherwise, contiguity is exploited in merging together,
-  when possible, results from consecutive MORECORE calls.
-
-  The initial value comes from MORECORE_CONTIGUOUS, but is
-  changed dynamically if mmap is ever used as an sbrk substitute.
-*/
-
-#define NONCONTIGUOUS_BIT     (2U)
-
-#define contiguous(M)          (((M)->max_fast &  NONCONTIGUOUS_BIT) == 0)
-#define noncontiguous(M)       (((M)->max_fast &  NONCONTIGUOUS_BIT) != 0)
-#define set_noncontiguous(M)   ((M)->max_fast |=  NONCONTIGUOUS_BIT)
-#define set_contiguous(M)      ((M)->max_fast &= ~NONCONTIGUOUS_BIT)
-
-/*
-   Set value of max_fast.
-   Use impossibly small value if 0.
-   Precondition: there are no existing fastbin chunks.
-   Setting the value clears fastchunk bit but preserves noncontiguous bit.
-*/
-
-#define set_max_fast(M, s) \
-  (M)->max_fast = (((s) == 0)? SMALLBIN_WIDTH: request2size(s)) | \
-  FASTCHUNKS_BIT | \
-  ((M)->max_fast &  NONCONTIGUOUS_BIT)
-
-
-/*
-   ----------- Internal state representation and initialization -----------
-*/
-
-struct malloc_state {
-  /* Serialize access.  */
-  mutex_t mutex;
-
-  /* Statistics for locking.  Only used if THREAD_STATS is defined.  */
-  long stat_lock_direct, stat_lock_loop, stat_lock_wait;
-  long pad0_[1]; /* try to give the mutex its own cacheline */
-
-  /* The maximum chunk size to be eligible for fastbin */
-  INTERNAL_SIZE_T  max_fast;   /* low 2 bits used as flags */
-
-  /* Fastbins */
-  mfastbinptr      fastbins[NFASTBINS];
-
-  /* Base of the topmost chunk -- not otherwise kept in a bin */
-  mchunkptr        top;
-
-  /* The remainder from the most recent split of a small request */
-  mchunkptr        last_remainder;
-
-  /* Normal bins packed as described above */
-  mchunkptr        bins[NBINS * 2];
-
-  /* Bitmap of bins */
-  unsigned int     binmap[BINMAPSIZE];
-
-  /* Linked list */
-  struct malloc_state *next;
-
-  /* Memory allocated from the system in this arena.  */
-  INTERNAL_SIZE_T system_mem;
-  INTERNAL_SIZE_T max_system_mem;
-};
-
-struct malloc_par {
-  /* Tunable parameters */
-  unsigned long    trim_threshold;
-  INTERNAL_SIZE_T  top_pad;
-  INTERNAL_SIZE_T  mmap_threshold;
-
-  /* Memory map support */
-  int              n_mmaps;
-  int              n_mmaps_max;
-  int              max_n_mmaps;
-
-  /* Cache malloc_getpagesize */
-  unsigned int     pagesize;
-
-  /* Statistics */
-  INTERNAL_SIZE_T  mmapped_mem;
-  /*INTERNAL_SIZE_T  sbrked_mem;*/
-  /*INTERNAL_SIZE_T  max_sbrked_mem;*/
-  INTERNAL_SIZE_T  max_mmapped_mem;
-  INTERNAL_SIZE_T  max_total_mem; /* only kept for NO_THREADS */
-
-  /* First address handed out by MORECORE/sbrk.  */
-  char*            sbrk_base;
-};
-
-/* There are several instances of this struct ("arenas") in this
-   malloc.  If you are adapting this malloc in a way that does NOT use
-   a static or mmapped malloc_state, you MUST explicitly zero-fill it
-   before using. This malloc relies on the property that malloc_state
-   is initialized to all zeroes (as is true of C statics).  */
-
-
-
-/*
-  Initialize a malloc_state struct.
-
-  This is called only from within malloc_consolidate, which needs
-  be called in the same contexts anyway.  It is never called directly
-  outside of malloc_consolidate because some optimizing compilers try
-  to inline it at all call points, which turns out not to be an
-  optimization at all. (Inlining it in malloc_consolidate is fine though.)
-*/
-
-#if __STD_C
-static void malloc_init_state(mstate av)
-#else
-static void malloc_init_state(av) mstate av;
-#endif
-{
-  int     i;
-  mbinptr bin;
-
-  /* Establish circular links for normal bins */
-  for (i = 1; i < NBINS; ++i) {
-    bin = bin_at(av,i);
-    bin->fd = bin->bk = bin;
-  }
-
-  set_noncontiguous(av);
-
-  set_max_fast(av, DEFAULT_MXFAST);
-
-  av->top            = initial_top(av);
-}
-
-/*
-   Other internal utilities operating on mstates
-*/
-
-#if __STD_C
-static Void_t*  sYSMALLOc(INTERNAL_SIZE_T, mstate);
-static void     malloc_consolidate(mstate);
-//static Void_t** iALLOc(mstate, size_t, size_t*, int, Void_t**);
-#else
-static Void_t*  sYSMALLOc();
-static void     malloc_consolidate();
-static Void_t** iALLOc();
-#endif
-
-/* ------------------- Support for multiple arenas -------------------- */
-#include "arena.c"
-
-/*
-  Debugging support
-
-  These routines make a number of assertions about the states
-  of data structures that should be true at all times. If any
-  are not true, it's very likely that a user program has somehow
-  trashed memory. (It's also possible that there is a coding error
-  in malloc. In which case, please report it!)
-*/
-
-#if ! MALLOC_DEBUG
-
-#define check_chunk(A,P)
-#define check_free_chunk(A,P)
-#define check_inuse_chunk(A,P)
-#define check_remalloced_chunk(A,P,N)
-#define check_malloced_chunk(A,P,N)
-#define check_malloc_state(A)
-
-#else
-
-#define check_chunk(A,P)              do_check_chunk(A,P)
-#define check_free_chunk(A,P)         do_check_free_chunk(A,P)
-#define check_inuse_chunk(A,P)        do_check_inuse_chunk(A,P)
-#define check_remalloced_chunk(A,P,N) do_check_remalloced_chunk(A,P,N)
-#define check_malloced_chunk(A,P,N)   do_check_malloced_chunk(A,P,N)
-#define check_malloc_state(A)         do_check_malloc_state(A)
-
-/*
-  Properties of all chunks
-*/
-
-#if __STD_C
-static void do_check_chunk(mstate av, mchunkptr p)
-#else
-static void do_check_chunk(av, p) mstate av; mchunkptr p;
-#endif
-{
-  unsigned long sz = chunksize(p);
-  /* min and max possible addresses assuming contiguous allocation */
-  char* max_address = (char*)(av->top) + chunksize(av->top);
-  char* min_address = max_address - av->system_mem;
-
-  if (!chunk_is_mmapped(p)) {
-
-    /* Has legal address ... */
-    if (p != av->top) {
-      if (contiguous(av)) {
-        assert(((char*)p) >= min_address);
-        assert(((char*)p + sz) <= ((char*)(av->top)));
-      }
-    }
-    else {
-      /* top size is always at least MINSIZE */
-      assert((unsigned long)(sz) >= MINSIZE);
-      /* top predecessor always marked inuse */
-      assert(prev_inuse(p));
-    }
-
-  }
-  else {
-#if HAVE_MMAP
-    /* address is outside main heap  */
-    if (contiguous(av) && av->top != initial_top(av)) {
-      assert(((char*)p) < min_address || ((char*)p) > max_address);
-    }
-    /* chunk is page-aligned */
-    assert(((p->prev_size + sz) & (mp_.pagesize-1)) == 0);
-    /* mem is aligned */
-    assert(aligned_OK(chunk2mem(p)));
-#else
-    /* force an appropriate assert violation if debug set */
-    assert(!chunk_is_mmapped(p));
-#endif
-  }
-}
-
-/*
-  Properties of free chunks
-*/
-
-#if __STD_C
-static void do_check_free_chunk(mstate av, mchunkptr p)
-#else
-static void do_check_free_chunk(av, p) mstate av; mchunkptr p;
-#endif
-{
-  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
-  mchunkptr next = chunk_at_offset(p, sz);
-
-  do_check_chunk(av, p);
-
-  /* Chunk must claim to be free ... */
-  assert(!inuse(p));
-  assert (!chunk_is_mmapped(p));
-
-  /* Unless a special marker, must have OK fields */
-  if ((unsigned long)(sz) >= MINSIZE)
-  {
-    assert((sz & MALLOC_ALIGN_MASK) == 0);
-    assert(aligned_OK(chunk2mem(p)));
-    /* ... matching footer field */
-    assert(next->prev_size == sz);
-    /* ... and is fully consolidated */
-    assert(prev_inuse(p));
-    assert (next == av->top || inuse(next));
-
-    /* ... and has minimally sane links */
-    assert(p->fd->bk == p);
-    assert(p->bk->fd == p);
-  }
-  else /* markers are always of size SIZE_SZ */
-    assert(sz == SIZE_SZ);
-}
-
-/*
-  Properties of inuse chunks
-*/
-
-#if __STD_C
-static void do_check_inuse_chunk(mstate av, mchunkptr p)
-#else
-static void do_check_inuse_chunk(av, p) mstate av; mchunkptr p;
-#endif
-{
-  mchunkptr next;
-
-  do_check_chunk(av, p);
-
-  assert(av == arena_for_chunk(p));
-  if (chunk_is_mmapped(p))
-    return; /* mmapped chunks have no next/prev */
-
-  /* Check whether it claims to be in use ... */
-  assert(inuse(p));
-
-  next = next_chunk(p);
-
-  /* ... and is surrounded by OK chunks.
-    Since more things can be checked with free chunks than inuse ones,
-    if an inuse chunk borders them and debug is on, it's worth doing them.
-  */
-  if (!prev_inuse(p))  {
-    /* Note that we cannot even look at prev unless it is not inuse */
-    mchunkptr prv = prev_chunk(p);
-    assert(next_chunk(prv) == p);
-    do_check_free_chunk(av, prv);
-  }
-
-  if (next == av->top) {
-    assert(prev_inuse(next));
-    assert(chunksize(next) >= MINSIZE);
-  }
-  else if (!inuse(next))
-    do_check_free_chunk(av, next);
-}
-
-/*
-  Properties of chunks recycled from fastbins
-*/
-
-#if __STD_C
-static void do_check_remalloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
-#else
-static void do_check_remalloced_chunk(av, p, s)
-mstate av; mchunkptr p; INTERNAL_SIZE_T s;
-#endif
-{
-  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
-
-  if (!chunk_is_mmapped(p)) {
-    assert(av == arena_for_chunk(p));
-  }
-
-  do_check_inuse_chunk(av, p);
-
-  /* Legal size ... */
-  assert((sz & MALLOC_ALIGN_MASK) == 0);
-  assert((unsigned long)(sz) >= MINSIZE);
-  /* ... and alignment */
-  assert(aligned_OK(chunk2mem(p)));
-  /* chunk is less than MINSIZE more than request */
-  assert((long)(sz) - (long)(s) >= 0);
-  assert((long)(sz) - (long)(s + MINSIZE) < 0);
-}
-
-/*
-  Properties of nonrecycled chunks at the point they are malloced
-*/
-
-#if __STD_C
-static void do_check_malloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
-#else
-static void do_check_malloced_chunk(av, p, s)
-mstate av; mchunkptr p; INTERNAL_SIZE_T s;
-#endif
-{
-  /* same as recycled case ... */
-  do_check_remalloced_chunk(av, p, s);
-
-  /*
-    ... plus,  must obey implementation invariant that prev_inuse is
-    always true of any allocated chunk; i.e., that each allocated
-    chunk borders either a previously allocated and still in-use
-    chunk, or the base of its memory arena. This is ensured
-    by making all allocations from the the `lowest' part of any found
-    chunk.  This does not necessarily hold however for chunks
-    recycled via fastbins.
-  */
-
-  assert(prev_inuse(p));
-}
-
-
-/*
-  Properties of malloc_state.
-
-  This may be useful for debugging malloc, as well as detecting user
-  programmer errors that somehow write into malloc_state.
-
-  If you are extending or experimenting with this malloc, you can
-  probably figure out how to hack this routine to print out or
-  display chunk addresses, sizes, bins, and other instrumentation.
-*/
-
-static void do_check_malloc_state(mstate av)
-{
-  int i;
-  mchunkptr p;
-  mchunkptr q;
-  mbinptr b;
-  unsigned int binbit;
-  int empty;
-  unsigned int idx;
-  INTERNAL_SIZE_T size;
-  unsigned long total = 0;
-  int max_fast_bin;
-
-  /* internal size_t must be no wider than pointer type */
-  assert(sizeof(INTERNAL_SIZE_T) <= sizeof(char*));
-
-  /* alignment is a power of 2 */
-  assert((MALLOC_ALIGNMENT & (MALLOC_ALIGNMENT-1)) == 0);
-
-  /* cannot run remaining checks until fully initialized */
-  if (av->top == 0 || av->top == initial_top(av))
-    return;
-
-
-  /* properties of fastbins */
-
-  /* max_fast is in allowed range */
-  assert((av->max_fast & ~1) <= request2size(MAX_FAST_SIZE));
-
-  max_fast_bin = fastbin_index(av->max_fast);
-
-  for (i = 0; i < NFASTBINS; ++i) {
-    p = av->fastbins[i];
-
-    /* all bins past max_fast are empty */
-    if (i > max_fast_bin)
-      assert(p == 0);
-
-    while (p != 0) {
-      /* each chunk claims to be inuse */
-      do_check_inuse_chunk(av, p);
-      total += chunksize(p);
-      /* chunk belongs in this bin */
-      assert(fastbin_index(chunksize(p)) == i);
-      p = p->fd;
-    }
-  }
-
-  if (total != 0)
-    assert(have_fastchunks(av));
-  else if (!have_fastchunks(av))
-    assert(total == 0);
-
-  /* check normal bins */
-  for (i = 1; i < NBINS; ++i) {
-    b = bin_at(av,i);
-
-    /* binmap is accurate (except for bin 1 == unsorted_chunks) */
-    if (i >= 2) {
-      binbit = get_binmap(av,i);
-      empty = last(b) == b;
-      if (!binbit)
-        assert(empty);
-      else if (!empty)
-        assert(binbit);
-    }
-
-    for (p = last(b); p != b; p = p->bk) {
-      /* each chunk claims to be free */
-      do_check_free_chunk(av, p);
-      size = chunksize(p);
-      total += size;
-      if (i >= 2) {
-        /* chunk belongs in bin */
-        idx = bin_index(size);
-        assert(idx == (unsigned int)i);
-        /* lists are sorted */
-        if ((unsigned long) size >= (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
-	  assert(p->bk == b ||
-		 (unsigned long)chunksize(p->bk) >=
-		 (unsigned long)chunksize(p));
-	}
-      }
-      /* chunk is followed by a legal chain of inuse chunks */
-      for (q = next_chunk(p);
-           (q != av->top && inuse(q) &&
-             (unsigned long)(chunksize(q)) >= MINSIZE);
-           q = next_chunk(q))
-        do_check_inuse_chunk(av, q);
-    }
-  }
-
-  /* top chunk is OK */
-  check_chunk(av, av->top);
-
-  /* sanity checks for statistics */
-
-
-  assert((unsigned long)(av->system_mem) <=
-         (unsigned long)(av->max_system_mem));
-
-
-}
-#endif
-
-
-
-/* ----------- Routines dealing with system allocation -------------- */
-
-/* No system allocation routines supported */
-
-
-/*------------------------ Public wrappers. --------------------------------*/
-
-
-
-#undef DEBUG_MALLOC
-Void_t*
-public_mALLOc(cvmx_arena_list_t arena_list, size_t bytes)
-{
-  mstate ar_ptr, orig_ar_ptr;
-  Void_t *victim = NULL;
-  static mstate debug_prev_ar;  // debug only!
-#ifdef DEBUG_MALLOC
-  int arena_cnt=0;
-#endif
-  
-  ar_ptr = arena_list;
-
-  if (!ar_ptr)
-  {
-     return(NULL);
-  }
-
-  if (debug_prev_ar != ar_ptr)
-  {
-      debug_printf("New arena: %p\n", ar_ptr);
-#ifdef CVMX_SPINLOCK_DEBUG
-      cvmx_dprintf("lock wait count for arena: %p is %ld\n", ar_ptr, ar_ptr->mutex.wait_cnt);
-#endif
-      debug_prev_ar = ar_ptr;
-  }
-  orig_ar_ptr = ar_ptr;
-
-  // try to get an arena without contention
-  do
-  {
-#ifdef DEBUG_MALLOC
-  arena_cnt++;
-#endif
-      if (!mutex_trylock(&ar_ptr->mutex))
-      {
-          // we locked it
-          victim = _int_malloc(ar_ptr, bytes);
-          (void)mutex_unlock(&ar_ptr->mutex);
-          if(victim)
-          {
-              break;
-          }
-      }
-      ar_ptr = ar_ptr->next;
-  } while (ar_ptr != orig_ar_ptr);
-
-  // we couldn't get the memory without contention, so try all
-  // arenas.  SLOW!
-  if (!victim)
-  {
-      ar_ptr = orig_ar_ptr;
-      do
-      {
-#ifdef DEBUG_MALLOC
-  arena_cnt++;
-#endif
-          mutex_lock(&ar_ptr->mutex);
-          victim = _int_malloc(ar_ptr, bytes);
-          (void)mutex_unlock(&ar_ptr->mutex);
-          if(victim)
-          {
-              break;
-          }
-          ar_ptr = ar_ptr->next;
-      } while (ar_ptr != orig_ar_ptr);
-  }
-
-
-  assert(!victim || chunk_is_mmapped(mem2chunk(victim)) ||
-	 ar_ptr == arena_for_chunk(mem2chunk(victim)));
-
-#ifdef DEBUG_MALLOC
-  if (!victim)
-  {
-     cvmx_dprintf("Malloc failed: size: %ld, arena_cnt: %d\n", bytes, arena_cnt);
-  }
-#endif
-
-  debug_printf("cvmx_malloc(%ld) = %p\n", bytes, victim);
-
-  // remember which arena we last used.....
-  tsd_setspecific(arena_key, (Void_t *)ar_ptr);
-  return victim;
-}
-
-
-
-void
-public_fREe(Void_t* mem)
-{
-  mstate ar_ptr;
-  mchunkptr p;                          /* chunk corresponding to mem */
-
-  debug_printf("cvmx_free(%p)\n", mem);
-
-
-  if (mem == 0)                              /* free(0) has no effect */
-    return;
-
-  p = mem2chunk(mem);
-
-
-  ar_ptr = arena_for_chunk(p);
-  assert(ar_ptr);
-#if THREAD_STATS
-  if(!mutex_trylock(&ar_ptr->mutex))
-    ++(ar_ptr->stat_lock_direct);
-  else {
-    (void)mutex_lock(&ar_ptr->mutex);
-    ++(ar_ptr->stat_lock_wait);
-  }
-#else
-  (void)mutex_lock(&ar_ptr->mutex);
-#endif
-  _int_free(ar_ptr, mem);
-  (void)mutex_unlock(&ar_ptr->mutex);
-}
-
-Void_t*
-public_rEALLOc(cvmx_arena_list_t arena_list, Void_t* oldmem, size_t bytes)
-{
-  mstate ar_ptr;
-  INTERNAL_SIZE_T    nb;      /* padded request size */
-
-  mchunkptr oldp;             /* chunk corresponding to oldmem */
-  INTERNAL_SIZE_T    oldsize; /* its size */
-
-  Void_t* newp;             /* chunk to return */
-
-
-#if REALLOC_ZERO_BYTES_FREES
-  if (bytes == 0 && oldmem != NULL) { public_fREe(oldmem); return 0; }
-#endif
-
-  /* realloc of null is supposed to be same as malloc */
-  if (oldmem == 0) return public_mALLOc(arena_list, bytes);
-
-  oldp    = mem2chunk(oldmem);
-  oldsize = chunksize(oldp);
-
-  checked_request2size(bytes, nb);
-
-
-  ar_ptr = arena_for_chunk(oldp);
-  (void)mutex_lock(&ar_ptr->mutex);
-
-
-  newp = _int_realloc(ar_ptr, oldmem, bytes);
-
-  (void)mutex_unlock(&ar_ptr->mutex);
-  assert(!newp || chunk_is_mmapped(mem2chunk(newp)) ||
-	 ar_ptr == arena_for_chunk(mem2chunk(newp)));
-  return newp;
-}
-
-#undef DEBUG_MEMALIGN
-Void_t*
-public_mEMALIGn(cvmx_arena_list_t arena_list, size_t alignment, size_t bytes)
-{
-  mstate ar_ptr, orig_ar_ptr;
-  Void_t *p = NULL;
-#ifdef DEBUG_MEMALIGN
-  int arena_cnt=0;
-#endif
-
-
-  /* If need less alignment than we give anyway, just relay to malloc */
-  if (alignment <= MALLOC_ALIGNMENT) return public_mALLOc(arena_list, bytes);
-
-  /* Otherwise, ensure that it is at least a minimum chunk size */
-  if (alignment <  MINSIZE) alignment = MINSIZE;
-
-
-  ar_ptr = arena_list;
-
-  if (!ar_ptr)
-  {
-     return(NULL);
-  }
-
-  orig_ar_ptr = ar_ptr;
-
-
-  // try to get an arena without contention
-  do
-  {
-
-#ifdef DEBUG_MEMALIGN
-   arena_cnt++;
-#endif
-      if (!mutex_trylock(&ar_ptr->mutex))
-      {
-          // we locked it
-          p = _int_memalign(ar_ptr, alignment, bytes);
-          (void)mutex_unlock(&ar_ptr->mutex);
-          if(p)
-          {
-              break;
-          }
-      }
-      ar_ptr = ar_ptr->next;
-  } while (ar_ptr != orig_ar_ptr);
-
-
-  // we couldn't get the memory without contention, so try all
-  // arenas.  SLOW!
-  if (!p)
-  {
-#ifdef DEBUG_MEMALIGN
-   arena_cnt++;
-#endif
-      ar_ptr = orig_ar_ptr;
-      do
-      {
-          mutex_lock(&ar_ptr->mutex);
-          p = _int_memalign(ar_ptr, alignment, bytes);
-          (void)mutex_unlock(&ar_ptr->mutex);
-          if(p)
-          {
-              break;
-          }
-          ar_ptr = ar_ptr->next;
-      } while (ar_ptr != orig_ar_ptr);
-  }
-
-
-  if (p)
-  {
-     assert(ar_ptr == arena_for_chunk(mem2chunk(p)));
-  }
-  else
-  {
-#ifdef DEBUG_MEMALIGN
-     cvmx_dprintf("Memalign failed: align: 0x%x, size: %ld, arena_cnt: %ld\n", alignment, bytes, arena_cnt);
-#endif
-  }
-
-  assert(!p || ar_ptr == arena_for_chunk(mem2chunk(p)));
-  return p;
-}
-
-
-
-Void_t*
-public_cALLOc(cvmx_arena_list_t arena_list, size_t n, size_t elem_size)
-{
-  mstate av;
-  mchunkptr oldtop, p;
-  INTERNAL_SIZE_T sz, csz, oldtopsize;
-  Void_t* mem;
-  unsigned long clearsize;
-  unsigned long nclears;
-  INTERNAL_SIZE_T* d;
-
-
-  /* FIXME: check for overflow on multiplication.  */
-  sz = n * elem_size;
-
-  mem = public_mALLOc(arena_list, sz);
-  if (mem)
-  {
-     memset(mem, 0, sz);
-  }
-
-  return mem;
-}
-
-
-#ifndef _LIBC
-
-void
-public_cFREe(Void_t* m)
-{
-  public_fREe(m);
-}
-
-#endif /* _LIBC */
-
-/*
-  ------------------------------ malloc ------------------------------
-*/
-
-static Void_t*
-_int_malloc(mstate av, size_t bytes)
-{
-  INTERNAL_SIZE_T nb;               /* normalized request size */
-  unsigned int    idx;              /* associated bin index */
-  mbinptr         bin;              /* associated bin */
-  mfastbinptr*    fb;               /* associated fastbin */
-
-  mchunkptr       victim;           /* inspected/selected chunk */
-  INTERNAL_SIZE_T size;             /* its size */
-  int             victim_index;     /* its bin index */
-
-  mchunkptr       remainder;        /* remainder from a split */
-  unsigned long   remainder_size;   /* its size */
-
-  unsigned int    block;            /* bit map traverser */
-  unsigned int    bit;              /* bit map traverser */
-  unsigned int    map;              /* current word of binmap */
-
-  mchunkptr       fwd;              /* misc temp for linking */
-  mchunkptr       bck;              /* misc temp for linking */
-
-  /*
-    Convert request size to internal form by adding SIZE_SZ bytes
-    overhead plus possibly more to obtain necessary alignment and/or
-    to obtain a size of at least MINSIZE, the smallest allocatable
-    size. Also, checked_request2size traps (returning 0) request sizes
-    that are so large that they wrap around zero when padded and
-    aligned.
-  */
-
-
-  checked_request2size(bytes, nb);
-
-  /*
-    If the size qualifies as a fastbin, first check corresponding bin.
-    This code is safe to execute even if av is not yet initialized, so we
-    can try it without checking, which saves some time on this fast path.
-  */
-
-  if ((unsigned long)(nb) <= (unsigned long)(av->max_fast)) {
-    fb = &(av->fastbins[(fastbin_index(nb))]);
-    if ( (victim = *fb) != 0) {
-      *fb = victim->fd;
-      check_remalloced_chunk(av, victim, nb);
-      set_arena_for_chunk(victim, av);
-      return chunk2mem(victim);
-    }
-  }
-
-  /*
-    If a small request, check regular bin.  Since these "smallbins"
-    hold one size each, no searching within bins is necessary.
-    (For a large request, we need to wait until unsorted chunks are
-    processed to find best fit. But for small ones, fits are exact
-    anyway, so we can check now, which is faster.)
-  */
-
-  if (in_smallbin_range(nb)) {
-    idx = smallbin_index(nb);
-    bin = bin_at(av,idx);
-
-    if ( (victim = last(bin)) != bin) {
-      if (victim == 0) /* initialization check */
-        malloc_consolidate(av);
-      else {
-        bck = victim->bk;
-        set_inuse_bit_at_offset(victim, nb);
-        bin->bk = bck;
-        bck->fd = bin;
-
-        set_arena_for_chunk(victim, av);
-        check_malloced_chunk(av, victim, nb);
-        return chunk2mem(victim);
-      }
-    }
-  }
-
-  /*
-     If this is a large request, consolidate fastbins before continuing.
-     While it might look excessive to kill all fastbins before
-     even seeing if there is space available, this avoids
-     fragmentation problems normally associated with fastbins.
-     Also, in practice, programs tend to have runs of either small or
-     large requests, but less often mixtures, so consolidation is not
-     invoked all that often in most programs. And the programs that
-     it is called frequently in otherwise tend to fragment.
-  */
-
-  else {
-    idx = largebin_index(nb);
-    if (have_fastchunks(av))
-      malloc_consolidate(av);
-  }
-
-  /*
-    Process recently freed or remaindered chunks, taking one only if
-    it is exact fit, or, if this a small request, the chunk is remainder from
-    the most recent non-exact fit.  Place other traversed chunks in
-    bins.  Note that this step is the only place in any routine where
-    chunks are placed in bins.
-
-    The outer loop here is needed because we might not realize until
-    near the end of malloc that we should have consolidated, so must
-    do so and retry. This happens at most once, and only when we would
-    otherwise need to expand memory to service a "small" request.
-  */
-
-  for(;;) {
-
-    while ( (victim = unsorted_chunks(av)->bk) != unsorted_chunks(av)) {
-      bck = victim->bk;
-      size = chunksize(victim);
-
-      /*
-         If a small request, try to use last remainder if it is the
-         only chunk in unsorted bin.  This helps promote locality for
-         runs of consecutive small requests. This is the only
-         exception to best-fit, and applies only when there is
-         no exact fit for a small chunk.
-      */
-
-      if (in_smallbin_range(nb) &&
-          bck == unsorted_chunks(av) &&
-          victim == av->last_remainder &&
-          (unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
-
-        /* split and reattach remainder */
-        remainder_size = size - nb;
-        remainder = chunk_at_offset(victim, nb);
-        unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
-        av->last_remainder = remainder;
-        remainder->bk = remainder->fd = unsorted_chunks(av);
-
-        set_head(victim, nb | PREV_INUSE);
-        set_head(remainder, remainder_size | PREV_INUSE);
-        set_foot(remainder, remainder_size);
-
-        set_arena_for_chunk(victim, av);
-        check_malloced_chunk(av, victim, nb);
-        return chunk2mem(victim);
-      }
-
-      /* remove from unsorted list */
-      unsorted_chunks(av)->bk = bck;
-      bck->fd = unsorted_chunks(av);
-
-      /* Take now instead of binning if exact fit */
-
-      if (size == nb) {
-        set_inuse_bit_at_offset(victim, size);
-        set_arena_for_chunk(victim, av);
-        check_malloced_chunk(av, victim, nb);
-        return chunk2mem(victim);
-      }
-
-      /* place chunk in bin */
-
-      if (in_smallbin_range(size)) {
-        victim_index = smallbin_index(size);
-        bck = bin_at(av, victim_index);
-        fwd = bck->fd;
-      }
-      else {
-        victim_index = largebin_index(size);
-        bck = bin_at(av, victim_index);
-        fwd = bck->fd;
-
-        if (fwd != bck) {
-          /* if smaller than smallest, place first */
-          if ((unsigned long)(size) < (unsigned long)(bck->bk->size)) {
-            fwd = bck;
-            bck = bck->bk;
-          }
-          else if ((unsigned long)(size) >= 
-                   (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
-
-            /* maintain large bins in sorted order */
-            size |= PREV_INUSE; /* Or with inuse bit to speed comparisons */
-            while ((unsigned long)(size) < (unsigned long)(fwd->size)) {
-              fwd = fwd->fd;
-	    }
-            bck = fwd->bk;
-          }
-        }
-      }
-
-      mark_bin(av, victim_index);
-      victim->bk = bck;
-      victim->fd = fwd;
-      fwd->bk = victim;
-      bck->fd = victim;
-    }
-
-    /*
-      If a large request, scan through the chunks of current bin in
-      sorted order to find smallest that fits.  This is the only step
-      where an unbounded number of chunks might be scanned without doing
-      anything useful with them. However the lists tend to be short.
-    */
-
-    if (!in_smallbin_range(nb)) {
-      bin = bin_at(av, idx);
-
-      for (victim = last(bin); victim != bin; victim = victim->bk) {
-	size = chunksize(victim);
-
-	if ((unsigned long)(size) >= (unsigned long)(nb)) {
-	  remainder_size = size - nb;
-	  unlink(victim, bck, fwd);
-
-	  /* Exhaust */
-	  if (remainder_size < MINSIZE)  {
-	    set_inuse_bit_at_offset(victim, size);
-        set_arena_for_chunk(victim, av);
-	    check_malloced_chunk(av, victim, nb);
-	    return chunk2mem(victim);
-	  }
-	  /* Split */
-	  else {
-	    remainder = chunk_at_offset(victim, nb);
-	    unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
-	    remainder->bk = remainder->fd = unsorted_chunks(av);
-	    set_head(victim, nb | PREV_INUSE);
-	    set_head(remainder, remainder_size | PREV_INUSE);
-	    set_foot(remainder, remainder_size);
-        set_arena_for_chunk(victim, av);
-	    check_malloced_chunk(av, victim, nb);
-	    return chunk2mem(victim);
-	  }
-	}
-      }
-    }
-
-    /*
-      Search for a chunk by scanning bins, starting with next largest
-      bin. This search is strictly by best-fit; i.e., the smallest
-      (with ties going to approximately the least recently used) chunk
-      that fits is selected.
-
-      The bitmap avoids needing to check that most blocks are nonempty.
-      The particular case of skipping all bins during warm-up phases
-      when no chunks have been returned yet is faster than it might look.
-    */
-
-    ++idx;
-    bin = bin_at(av,idx);
-    block = idx2block(idx);
-    map = av->binmap[block];
-    bit = idx2bit(idx);
-
-    for (;;) {
-
-      /* Skip rest of block if there are no more set bits in this block.  */
-      if (bit > map || bit == 0) {
-        do {
-          if (++block >= BINMAPSIZE)  /* out of bins */
-            goto use_top;
-        } while ( (map = av->binmap[block]) == 0);
-
-        bin = bin_at(av, (block << BINMAPSHIFT));
-        bit = 1;
-      }
-
-      /* Advance to bin with set bit. There must be one. */
-      while ((bit & map) == 0) {
-        bin = next_bin(bin);
-        bit <<= 1;
-        assert(bit != 0);
-      }
-
-      /* Inspect the bin. It is likely to be non-empty */
-      victim = last(bin);
-
-      /*  If a false alarm (empty bin), clear the bit. */
-      if (victim == bin) {
-        av->binmap[block] = map &= ~bit; /* Write through */
-        bin = next_bin(bin);
-        bit <<= 1;
-      }
-
-      else {
-        size = chunksize(victim);
-
-        /*  We know the first chunk in this bin is big enough to use. */
-        assert((unsigned long)(size) >= (unsigned long)(nb));
-
-        remainder_size = size - nb;
-
-        /* unlink */
-        bck = victim->bk;
-        bin->bk = bck;
-        bck->fd = bin;
-
-        /* Exhaust */
-        if (remainder_size < MINSIZE) {
-          set_inuse_bit_at_offset(victim, size);
-          set_arena_for_chunk(victim, av);
-          check_malloced_chunk(av, victim, nb);
-          return chunk2mem(victim);
-        }
-
-        /* Split */
-        else {
-          remainder = chunk_at_offset(victim, nb);
-
-          unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
-          remainder->bk = remainder->fd = unsorted_chunks(av);
-          /* advertise as last remainder */
-          if (in_smallbin_range(nb))
-            av->last_remainder = remainder;
-
-          set_head(victim, nb | PREV_INUSE);
-          set_head(remainder, remainder_size | PREV_INUSE);
-          set_foot(remainder, remainder_size);
-          set_arena_for_chunk(victim, av);
-          check_malloced_chunk(av, victim, nb);
-          return chunk2mem(victim);
-        }
-      }
-    }
-
-  use_top:
-    /*
-      If large enough, split off the chunk bordering the end of memory
-      (held in av->top). Note that this is in accord with the best-fit
-      search rule.  In effect, av->top is treated as larger (and thus
-      less well fitting) than any other available chunk since it can
-      be extended to be as large as necessary (up to system
-      limitations).
-
-      We require that av->top always exists (i.e., has size >=
-      MINSIZE) after initialization, so if it would otherwise be
-      exhuasted by current request, it is replenished. (The main
-      reason for ensuring it exists is that we may need MINSIZE space
-      to put in fenceposts in sysmalloc.)
-    */
-
-    victim = av->top;
-    size = chunksize(victim);
-
-    if ((unsigned long)(size) >= (unsigned long)(nb + MINSIZE)) {
-      remainder_size = size - nb;
-      remainder = chunk_at_offset(victim, nb);
-      av->top = remainder;
-      set_head(victim, nb | PREV_INUSE);
-      set_head(remainder, remainder_size | PREV_INUSE);
-
-      set_arena_for_chunk(victim, av);
-      check_malloced_chunk(av, victim, nb);
-      return chunk2mem(victim);
-    }
-
-    /*
-      If there is space available in fastbins, consolidate and retry,
-      to possibly avoid expanding memory. This can occur only if nb is
-      in smallbin range so we didn't consolidate upon entry.
-    */
-
-    else if (have_fastchunks(av)) {
-      assert(in_smallbin_range(nb));
-      malloc_consolidate(av);
-      idx = smallbin_index(nb); /* restore original bin index */
-    }
-
-    /*
-       Otherwise, relay to handle system-dependent cases
-    */
-    else
-      return(NULL); // sysmalloc not supported
-  }
-}
-
-/*
-  ------------------------------ free ------------------------------
-*/
-
-static void
-_int_free(mstate av, Void_t* mem)
-{
-  mchunkptr       p;           /* chunk corresponding to mem */
-  INTERNAL_SIZE_T size;        /* its size */
-  mfastbinptr*    fb;          /* associated fastbin */
-  mchunkptr       nextchunk;   /* next contiguous chunk */
-  INTERNAL_SIZE_T nextsize;    /* its size */
-  int             nextinuse;   /* true if nextchunk is used */
-  INTERNAL_SIZE_T prevsize;    /* size of previous contiguous chunk */
-  mchunkptr       bck;         /* misc temp for linking */
-  mchunkptr       fwd;         /* misc temp for linking */
-
-
-  /* free(0) has no effect */
-  if (mem != 0) {
-    p = mem2chunk(mem);
-    size = chunksize(p);
-
-    check_inuse_chunk(av, p);
-
-    /*
-      If eligible, place chunk on a fastbin so it can be found
-      and used quickly in malloc.
-    */
-
-    if ((unsigned long)(size) <= (unsigned long)(av->max_fast)
-
-#if TRIM_FASTBINS
-        /*
-           If TRIM_FASTBINS set, don't place chunks
-           bordering top into fastbins
-        */
-        && (chunk_at_offset(p, size) != av->top)
-#endif
-        ) {
-
-      set_fastchunks(av);
-      fb = &(av->fastbins[fastbin_index(size)]);
-      p->fd = *fb;
-      *fb = p;
-    }
-
-    /*
-       Consolidate other non-mmapped chunks as they arrive.
-    */
-
-    else if (!chunk_is_mmapped(p)) {
-      nextchunk = chunk_at_offset(p, size);
-      nextsize = chunksize(nextchunk);
-      assert(nextsize > 0);
-
-      /* consolidate backward */
-      if (!prev_inuse(p)) {
-        prevsize = p->prev_size;
-        size += prevsize;
-        p = chunk_at_offset(p, -((long) prevsize));
-        unlink(p, bck, fwd);
-      }
-
-      if (nextchunk != av->top) {
-        /* get and clear inuse bit */
-        nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
-
-        /* consolidate forward */
-        if (!nextinuse) {
-          unlink(nextchunk, bck, fwd);
-          size += nextsize;
-        } else
-	  clear_inuse_bit_at_offset(nextchunk, 0);
-
-        /*
-          Place the chunk in unsorted chunk list. Chunks are
-          not placed into regular bins until after they have
-          been given one chance to be used in malloc.
-        */
-
-        bck = unsorted_chunks(av);
-        fwd = bck->fd;
-        p->bk = bck;
-        p->fd = fwd;
-        bck->fd = p;
-        fwd->bk = p;
-
-        set_head(p, size | PREV_INUSE);
-        set_foot(p, size);
-
-        check_free_chunk(av, p);
-      }
-
-      /*
-         If the chunk borders the current high end of memory,
-         consolidate into top
-      */
-
-      else {
-        size += nextsize;
-        set_head(p, size | PREV_INUSE);
-        av->top = p;
-        check_chunk(av, p);
-      }
-
-      /*
-        If freeing a large space, consolidate possibly-surrounding
-        chunks. Then, if the total unused topmost memory exceeds trim
-        threshold, ask malloc_trim to reduce top.
-
-        Unless max_fast is 0, we don't know if there are fastbins
-        bordering top, so we cannot tell for sure whether threshold
-        has been reached unless fastbins are consolidated.  But we
-        don't want to consolidate on each free.  As a compromise,
-        consolidation is performed if FASTBIN_CONSOLIDATION_THRESHOLD
-        is reached.
-      */
-
-      if ((unsigned long)(size) >= FASTBIN_CONSOLIDATION_THRESHOLD) {
-        if (have_fastchunks(av))
-          malloc_consolidate(av);
-      }
-    }
-  }
-}
-
-/*
-  ------------------------- malloc_consolidate -------------------------
-
-  malloc_consolidate is a specialized version of free() that tears
-  down chunks held in fastbins.  Free itself cannot be used for this
-  purpose since, among other things, it might place chunks back onto
-  fastbins.  So, instead, we need to use a minor variant of the same
-  code.
-
-  Also, because this routine needs to be called the first time through
-  malloc anyway, it turns out to be the perfect place to trigger
-  initialization code.
-*/
-
-#if __STD_C
-static void malloc_consolidate(mstate av)
-#else
-static void malloc_consolidate(av) mstate av;
-#endif
-{
-  mfastbinptr*    fb;                 /* current fastbin being consolidated */
-  mfastbinptr*    maxfb;              /* last fastbin (for loop control) */
-  mchunkptr       p;                  /* current chunk being consolidated */
-  mchunkptr       nextp;              /* next chunk to consolidate */
-  mchunkptr       unsorted_bin;       /* bin header */
-  mchunkptr       first_unsorted;     /* chunk to link to */
-
-  /* These have same use as in free() */
-  mchunkptr       nextchunk;
-  INTERNAL_SIZE_T size;
-  INTERNAL_SIZE_T nextsize;
-  INTERNAL_SIZE_T prevsize;
-  int             nextinuse;
-  mchunkptr       bck;
-  mchunkptr       fwd;
-
-  /*
-    If max_fast is 0, we know that av hasn't
-    yet been initialized, in which case do so below
-  */
-
-  if (av->max_fast != 0) {
-    clear_fastchunks(av);
-
-    unsorted_bin = unsorted_chunks(av);
-
-    /*
-      Remove each chunk from fast bin and consolidate it, placing it
-      then in unsorted bin. Among other reasons for doing this,
-      placing in unsorted bin avoids needing to calculate actual bins
-      until malloc is sure that chunks aren't immediately going to be
-      reused anyway.
-    */
-
-    maxfb = &(av->fastbins[fastbin_index(av->max_fast)]);
-    fb = &(av->fastbins[0]);
-    do {
-      if ( (p = *fb) != 0) {
-        *fb = 0;
-
-        do {
-          check_inuse_chunk(av, p);
-          nextp = p->fd;
-
-          /* Slightly streamlined version of consolidation code in free() */
-          size = p->size & ~(PREV_INUSE);
-          nextchunk = chunk_at_offset(p, size);
-          nextsize = chunksize(nextchunk);
-
-          if (!prev_inuse(p)) {
-            prevsize = p->prev_size;
-            size += prevsize;
-            p = chunk_at_offset(p, -((long) prevsize));
-            unlink(p, bck, fwd);
-          }
-
-          if (nextchunk != av->top) {
-            nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
-
-            if (!nextinuse) {
-              size += nextsize;
-              unlink(nextchunk, bck, fwd);
-            } else
-	      clear_inuse_bit_at_offset(nextchunk, 0);
-
-            first_unsorted = unsorted_bin->fd;
-            unsorted_bin->fd = p;
-            first_unsorted->bk = p;
-
-            set_head(p, size | PREV_INUSE);
-            p->bk = unsorted_bin;
-            p->fd = first_unsorted;
-            set_foot(p, size);
-          }
-
-          else {
-            size += nextsize;
-            set_head(p, size | PREV_INUSE);
-            av->top = p;
-          }
-
-        } while ( (p = nextp) != 0);
-
-      }
-    } while (fb++ != maxfb);
-  }
-  else {
-    malloc_init_state(av);
-    check_malloc_state(av);
-  }
-}
-
-/*
-  ------------------------------ realloc ------------------------------
-*/
-
-static Void_t*
-_int_realloc(mstate av, Void_t* oldmem, size_t bytes)
-{
-  INTERNAL_SIZE_T  nb;              /* padded request size */
-
-  mchunkptr        oldp;            /* chunk corresponding to oldmem */
-  INTERNAL_SIZE_T  oldsize;         /* its size */
-
-  mchunkptr        newp;            /* chunk to return */
-  INTERNAL_SIZE_T  newsize;         /* its size */
-  Void_t*          newmem;          /* corresponding user mem */
-
-  mchunkptr        next;            /* next contiguous chunk after oldp */
-
-  mchunkptr        remainder;       /* extra space at end of newp */
-  unsigned long    remainder_size;  /* its size */
-
-  mchunkptr        bck;             /* misc temp for linking */
-  mchunkptr        fwd;             /* misc temp for linking */
-
-  unsigned long    copysize;        /* bytes to copy */
-  unsigned int     ncopies;         /* INTERNAL_SIZE_T words to copy */
-  INTERNAL_SIZE_T* s;               /* copy source */
-  INTERNAL_SIZE_T* d;               /* copy destination */
-
-
-#if REALLOC_ZERO_BYTES_FREES
-  if (bytes == 0) {
-    _int_free(av, oldmem);
-    return 0;
-  }
-#endif
-
-  /* realloc of null is supposed to be same as malloc */
-  if (oldmem == 0) return _int_malloc(av, bytes);
-
-  checked_request2size(bytes, nb);
-
-  oldp    = mem2chunk(oldmem);
-  oldsize = chunksize(oldp);
-
-  check_inuse_chunk(av, oldp);
-
-  // force to act like not mmapped
-  if (1) {
-
-    if ((unsigned long)(oldsize) >= (unsigned long)(nb)) {
-      /* already big enough; split below */
-      newp = oldp;
-      newsize = oldsize;
-    }
-
-    else {
-      next = chunk_at_offset(oldp, oldsize);
-
-      /* Try to expand forward into top */
-      if (next == av->top &&
-          (unsigned long)(newsize = oldsize + chunksize(next)) >=
-          (unsigned long)(nb + MINSIZE)) {
-        set_head_size(oldp, nb );
-        av->top = chunk_at_offset(oldp, nb);
-        set_head(av->top, (newsize - nb) | PREV_INUSE);
-    	check_inuse_chunk(av, oldp);
-        set_arena_for_chunk(oldp, av);
-        return chunk2mem(oldp);
-      }
-
-      /* Try to expand forward into next chunk;  split off remainder below */
-      else if (next != av->top &&
-               !inuse(next) &&
-               (unsigned long)(newsize = oldsize + chunksize(next)) >=
-               (unsigned long)(nb)) {
-        newp = oldp;
-        unlink(next, bck, fwd);
-      }
-
-      /* allocate, copy, free */
-      else {
-        newmem = _int_malloc(av, nb - MALLOC_ALIGN_MASK);
-        if (newmem == 0)
-          return 0; /* propagate failure */
-
-        newp = mem2chunk(newmem);
-        newsize = chunksize(newp);
-
-        /*
-          Avoid copy if newp is next chunk after oldp.
-        */
-        if (newp == next) {
-          newsize += oldsize;
-          newp = oldp;
-        }
-        else {
-          /*
-            Unroll copy of <= 36 bytes (72 if 8byte sizes)
-            We know that contents have an odd number of
-            INTERNAL_SIZE_T-sized words; minimally 3.
-          */
-
-          copysize = oldsize - SIZE_SZ;
-          s = (INTERNAL_SIZE_T*)(oldmem);
-          d = (INTERNAL_SIZE_T*)(newmem);
-          ncopies = copysize / sizeof(INTERNAL_SIZE_T);
-          assert(ncopies >= 3);
-
-          if (ncopies > 9)
-            MALLOC_COPY(d, s, copysize);
-
-          else {
-            *(d+0) = *(s+0);
-            *(d+1) = *(s+1);
-            *(d+2) = *(s+2);
-            if (ncopies > 4) {
-              *(d+3) = *(s+3);
-              *(d+4) = *(s+4);
-              if (ncopies > 6) {
-                *(d+5) = *(s+5);
-                *(d+6) = *(s+6);
-                if (ncopies > 8) {
-                  *(d+7) = *(s+7);
-                  *(d+8) = *(s+8);
-                }
-              }
-            }
-          }
-
-          _int_free(av, oldmem);
-          set_arena_for_chunk(newp, av);
-          check_inuse_chunk(av, newp);
-          return chunk2mem(newp);
-        }
-      }
-    }
-
-    /* If possible, free extra space in old or extended chunk */
-
-    assert((unsigned long)(newsize) >= (unsigned long)(nb));
-
-    remainder_size = newsize - nb;
-
-    if (remainder_size < MINSIZE) { /* not enough extra to split off */
-      set_head_size(newp, newsize);
-      set_inuse_bit_at_offset(newp, newsize);
-    }
-    else { /* split remainder */
-      remainder = chunk_at_offset(newp, nb);
-      set_head_size(newp, nb );
-      set_head(remainder, remainder_size | PREV_INUSE );
-      /* Mark remainder as inuse so free() won't complain */
-      set_inuse_bit_at_offset(remainder, remainder_size);
-      set_arena_for_chunk(remainder, av);
-      _int_free(av, chunk2mem(remainder));
-    }
-
-    set_arena_for_chunk(newp, av);
-    check_inuse_chunk(av, newp);
-    return chunk2mem(newp);
-  }
-
-  /*
-    Handle mmap cases
-  */
-
-  else {
-    /* If !HAVE_MMAP, but chunk_is_mmapped, user must have overwritten mem */
-    check_malloc_state(av);
-    MALLOC_FAILURE_ACTION;
-    return 0;
-  }
-}
-
-/*
-  ------------------------------ memalign ------------------------------
-*/
-
-static Void_t*
-_int_memalign(mstate av, size_t alignment, size_t bytes)
-{
-  INTERNAL_SIZE_T nb;             /* padded  request size */
-  char*           m;              /* memory returned by malloc call */
-  mchunkptr       p;              /* corresponding chunk */
-  char*           brk;            /* alignment point within p */
-  mchunkptr       newp;           /* chunk to return */
-  INTERNAL_SIZE_T newsize;        /* its size */
-  INTERNAL_SIZE_T leadsize;       /* leading space before alignment point */
-  mchunkptr       remainder;      /* spare room at end to split off */
-  unsigned long   remainder_size; /* its size */
-  INTERNAL_SIZE_T size;
-
-  /* If need less alignment than we give anyway, just relay to malloc */
-
-  if (alignment <= MALLOC_ALIGNMENT) return _int_malloc(av, bytes);
-
-  /* Otherwise, ensure that it is at least a minimum chunk size */
-
-  if (alignment <  MINSIZE) alignment = MINSIZE;
-
-  /* Make sure alignment is power of 2 (in case MINSIZE is not).  */
-  if ((alignment & (alignment - 1)) != 0) {
-    size_t a = MALLOC_ALIGNMENT * 2;
-    while ((unsigned long)a < (unsigned long)alignment) a <<= 1;
-    alignment = a;
-  }
-
-  checked_request2size(bytes, nb);
-
-  /*
-    Strategy: find a spot within that chunk that meets the alignment
-    request, and then possibly free the leading and trailing space.
-  */
-
-
-  /* Call malloc with worst case padding to hit alignment. */
-
-  m  = (char*)(_int_malloc(av, nb + alignment + MINSIZE));
-
-  if (m == 0) return 0; /* propagate failure */
-
-  p = mem2chunk(m);
-
-  if ((((unsigned long)(m)) % alignment) != 0) { /* misaligned */
-
-    /*
-      Find an aligned spot inside chunk.  Since we need to give back
-      leading space in a chunk of at least MINSIZE, if the first
-      calculation places us at a spot with less than MINSIZE leader,
-      we can move to the next aligned spot -- we've allocated enough
-      total room so that this is always possible.
-    */
-
-    brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) &
-                           -((signed long) alignment));
-    if ((unsigned long)(brk - (char*)(p)) < MINSIZE)
-      brk += alignment;
-
-    newp = (mchunkptr)brk;
-    leadsize = brk - (char*)(p);
-    newsize = chunksize(p) - leadsize;
-
-    /* For mmapped chunks, just adjust offset */
-    if (chunk_is_mmapped(p)) {
-      newp->prev_size = p->prev_size + leadsize;
-      set_head(newp, newsize|IS_MMAPPED);
-      set_arena_for_chunk(newp, av);
-      return chunk2mem(newp);
-    }
-
-    /* Otherwise, give back leader, use the rest */
-    set_head(newp, newsize | PREV_INUSE );
-    set_inuse_bit_at_offset(newp, newsize);
-    set_head_size(p, leadsize);
-    set_arena_for_chunk(p, av);
-    _int_free(av, chunk2mem(p));
-    p = newp;
-
-    assert (newsize >= nb &&
-            (((unsigned long)(chunk2mem(p))) % alignment) == 0);
-  }
-
-  /* Also give back spare room at the end */
-  if (!chunk_is_mmapped(p)) {
-    size = chunksize(p);
-    if ((unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
-      remainder_size = size - nb;
-      remainder = chunk_at_offset(p, nb);
-      set_head(remainder, remainder_size | PREV_INUSE );
-      set_head_size(p, nb);
-      set_arena_for_chunk(remainder, av);
-      _int_free(av, chunk2mem(remainder));
-    }
-  }
-
-  set_arena_for_chunk(p, av);
-  check_inuse_chunk(av, p);
-  return chunk2mem(p);
-}
-
-#if 1
-/*
-  ------------------------------ calloc ------------------------------
-*/
-
-#if __STD_C
-Void_t* cALLOc(cvmx_arena_list_t arena_list, size_t n_elements, size_t elem_size)
-#else
-Void_t* cALLOc(n_elements, elem_size) size_t n_elements; size_t elem_size;
-#endif
-{
-  mchunkptr p;
-  unsigned long clearsize;
-  unsigned long nclears;
-  INTERNAL_SIZE_T* d;
-
-  Void_t* mem = public_mALLOc(arena_list, n_elements * elem_size);
-
-  if (mem != 0) {
-    p = mem2chunk(mem);
-
-    {
-      /*
-        Unroll clear of <= 36 bytes (72 if 8byte sizes)
-        We know that contents have an odd number of
-        INTERNAL_SIZE_T-sized words; minimally 3.
-      */
-
-      d = (INTERNAL_SIZE_T*)mem;
-      clearsize = chunksize(p) - SIZE_SZ;
-      nclears = clearsize / sizeof(INTERNAL_SIZE_T);
-      assert(nclears >= 3);
-
-      if (nclears > 9)
-        MALLOC_ZERO(d, clearsize);
-
-      else {
-        *(d+0) = 0;
-        *(d+1) = 0;
-        *(d+2) = 0;
-        if (nclears > 4) {
-          *(d+3) = 0;
-          *(d+4) = 0;
-          if (nclears > 6) {
-            *(d+5) = 0;
-            *(d+6) = 0;
-            if (nclears > 8) {
-              *(d+7) = 0;
-              *(d+8) = 0;
-            }
-          }
-        }
-      }
-    }
-  }
-  return mem;
-}
-#endif
-
-
-/*
-  ------------------------- malloc_usable_size -------------------------
-*/
-
-#if __STD_C
-size_t mUSABLe(Void_t* mem)
-#else
-size_t mUSABLe(mem) Void_t* mem;
-#endif
-{
-  mchunkptr p;
-  if (mem != 0) {
-    p = mem2chunk(mem);
-    if (chunk_is_mmapped(p))
-      return chunksize(p) - 3*SIZE_SZ; /* updated size for adding arena_ptr */
-    else if (inuse(p))
-      return chunksize(p) - 2*SIZE_SZ; /* updated size for adding arena_ptr */
-  }
-  return 0;
-}
-
-/*
-  ------------------------------ mallinfo ------------------------------
-*/
-
-struct mallinfo mALLINFo(mstate av)
-{
-  struct mallinfo mi;
-  int i;
-  mbinptr b;
-  mchunkptr p;
-  INTERNAL_SIZE_T avail;
-  INTERNAL_SIZE_T fastavail;
-  int nblocks;
-  int nfastblocks;
-
-  /* Ensure initialization */
-  if (av->top == 0)  malloc_consolidate(av);
-
-  check_malloc_state(av);
-
-  /* Account for top */
-  avail = chunksize(av->top);
-  nblocks = 1;  /* top always exists */
-
-  /* traverse fastbins */
-  nfastblocks = 0;
-  fastavail = 0;
-
-  for (i = 0; i < NFASTBINS; ++i) {
-    for (p = av->fastbins[i]; p != 0; p = p->fd) {
-      ++nfastblocks;
-      fastavail += chunksize(p);
-    }
-  }
-
-  avail += fastavail;
-
-  /* traverse regular bins */
-  for (i = 1; i < NBINS; ++i) {
-    b = bin_at(av, i);
-    for (p = last(b); p != b; p = p->bk) {
-      ++nblocks;
-      avail += chunksize(p);
-    }
-  }
-
-  mi.smblks = nfastblocks;
-  mi.ordblks = nblocks;
-  mi.fordblks = avail;
-  mi.uordblks = av->system_mem - avail;
-  mi.arena = av->system_mem;
-  mi.fsmblks = fastavail;
-  mi.keepcost = chunksize(av->top);
-  return mi;
-}
-
-/*
-  ------------------------------ malloc_stats ------------------------------
-*/
-
-void mSTATs()
-{
-}
-
-
-/*
-  ------------------------------ mallopt ------------------------------
-*/
-
-#if 0
-#if __STD_C
-int mALLOPt(int param_number, int value)
-#else
-int mALLOPt(param_number, value) int param_number; int value;
-#endif
-{
-}
-#endif
-
-
-/*
-  -------------------- Alternative MORECORE functions --------------------
-*/
-
-
-/*
-  General Requirements for MORECORE.
-
-  The MORECORE function must have the following properties:
-
-  If MORECORE_CONTIGUOUS is false:
-
-    * MORECORE must allocate in multiples of pagesize. It will
-      only be called with arguments that are multiples of pagesize.
-
-    * MORECORE(0) must return an address that is at least
-      MALLOC_ALIGNMENT aligned. (Page-aligning always suffices.)
-
-  else (i.e. If MORECORE_CONTIGUOUS is true):
-
-    * Consecutive calls to MORECORE with positive arguments
-      return increasing addresses, indicating that space has been
-      contiguously extended.
-
-    * MORECORE need not allocate in multiples of pagesize.
-      Calls to MORECORE need not have args of multiples of pagesize.
-
-    * MORECORE need not page-align.
-
-  In either case:
-
-    * MORECORE may allocate more memory than requested. (Or even less,
-      but this will generally result in a malloc failure.)
-
-    * MORECORE must not allocate memory when given argument zero, but
-      instead return one past the end address of memory from previous
-      nonzero call. This malloc does NOT call MORECORE(0)
-      until at least one call with positive arguments is made, so
-      the initial value returned is not important.
-
-    * Even though consecutive calls to MORECORE need not return contiguous
-      addresses, it must be OK for malloc'ed chunks to span multiple
-      regions in those cases where they do happen to be contiguous.
-
-    * MORECORE need not handle negative arguments -- it may instead
-      just return MORECORE_FAILURE when given negative arguments.
-      Negative arguments are always multiples of pagesize. MORECORE
-      must not misinterpret negative args as large positive unsigned
-      args. You can suppress all such calls from even occurring by defining
-      MORECORE_CANNOT_TRIM,
-
-  There is some variation across systems about the type of the
-  argument to sbrk/MORECORE. If size_t is unsigned, then it cannot
-  actually be size_t, because sbrk supports negative args, so it is
-  normally the signed type of the same width as size_t (sometimes
-  declared as "intptr_t", and sometimes "ptrdiff_t").  It doesn't much
-  matter though. Internally, we use "long" as arguments, which should
-  work across all reasonable possibilities.
-
-  Additionally, if MORECORE ever returns failure for a positive
-  request, and HAVE_MMAP is true, then mmap is used as a noncontiguous
-  system allocator. This is a useful backup strategy for systems with
-  holes in address spaces -- in this case sbrk cannot contiguously
-  expand the heap, but mmap may be able to map noncontiguous space.
-
-  If you'd like mmap to ALWAYS be used, you can define MORECORE to be
-  a function that always returns MORECORE_FAILURE.
-
-  If you are using this malloc with something other than sbrk (or its
-  emulation) to supply memory regions, you probably want to set
-  MORECORE_CONTIGUOUS as false.  As an example, here is a custom
-  allocator kindly contributed for pre-OSX macOS.  It uses virtually
-  but not necessarily physically contiguous non-paged memory (locked
-  in, present and won't get swapped out).  You can use it by
-  uncommenting this section, adding some #includes, and setting up the
-  appropriate defines above:
-
-      #define MORECORE osMoreCore
-      #define MORECORE_CONTIGUOUS 0
-
-  There is also a shutdown routine that should somehow be called for
-  cleanup upon program exit.
-
-  #define MAX_POOL_ENTRIES 100
-  #define MINIMUM_MORECORE_SIZE  (64 * 1024)
-  static int next_os_pool;
-  void *our_os_pools[MAX_POOL_ENTRIES];
-
-  void *osMoreCore(int size)
-  {
-    void *ptr = 0;
-    static void *sbrk_top = 0;
-
-    if (size > 0)
-    {
-      if (size < MINIMUM_MORECORE_SIZE)
-         size = MINIMUM_MORECORE_SIZE;
-      if (CurrentExecutionLevel() == kTaskLevel)
-         ptr = PoolAllocateResident(size + RM_PAGE_SIZE, 0);
-      if (ptr == 0)
-      {
-        return (void *) MORECORE_FAILURE;
-      }
-      // save ptrs so they can be freed during cleanup
-      our_os_pools[next_os_pool] = ptr;
-      next_os_pool++;
-      ptr = (void *) ((((unsigned long) ptr) + RM_PAGE_MASK) & ~RM_PAGE_MASK);
-      sbrk_top = (char *) ptr + size;
-      return ptr;
-    }
-    else if (size < 0)
-    {
-      // we don't currently support shrink behavior
-      return (void *) MORECORE_FAILURE;
-    }
-    else
-    {
-      return sbrk_top;
-    }
-  }
-
-  // cleanup any allocated memory pools
-  // called as last thing before shutting down driver
-
-  void osCleanupMem(void)
-  {
-    void **ptr;
-
-    for (ptr = our_os_pools; ptr < &our_os_pools[MAX_POOL_ENTRIES]; ptr++)
-      if (*ptr)
-      {
-         PoolDeallocate(*ptr);
-         *ptr = 0;
-      }
-  }
-
-*/
-
-
-
-/* ------------------------------------------------------------
-History:
-
-[see ftp://g.oswego.edu/pub/misc/malloc.c for the history of dlmalloc]
-
-*/
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h b/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h
deleted file mode 100644
index 6d6f634..0000000
--- a/sys/contrib/octeon-sdk/cvmx-malloc/malloc.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
-Copyright (c) 2001 Wolfram Gloger
-Copyright (c) 2006 Cavium networks
-
-Permission to use, copy, modify, distribute, and sell this software
-and its documentation for any purpose is hereby granted without fee,
-provided that (i) the above copyright notices and this permission
-notice appear in all copies of the software and related documentation,
-and (ii) the name of Wolfram Gloger may not be used in any advertising
-or publicity relating to the software.
-
-THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
-EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
-WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-
-IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
-INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
-DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
-WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
-OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-PERFORMANCE OF THIS SOFTWARE.
-*/
-
-#ifndef _MALLOC_H
-#define _MALLOC_H 1
-
-#undef _LIBC
-#ifdef _LIBC
-#include <features.h>
-#endif
-
-/*
-  $Id: malloc.h 30481 2007-12-05 21:46:59Z rfranz $
-  `ptmalloc2', a malloc implementation for multiple threads without
-  lock contention, by Wolfram Gloger <wg@malloc.de>.
-
-  VERSION 2.7.0
-
-  This work is mainly derived from malloc-2.7.0 by Doug Lea
-  <dl@cs.oswego.edu>, which is available from:
-
-                 ftp://gee.cs.oswego.edu/pub/misc/malloc.c
-
-  This trimmed-down header file only provides function prototypes and
-  the exported data structures.  For more detailed function
-  descriptions and compile-time options, see the source file
-  `malloc.c'.
-*/
-
-#if 0
-# include <stddef.h>
-# define __malloc_ptr_t  void *
-# undef  size_t
-# define size_t          unsigned long
-# undef  ptrdiff_t
-# define ptrdiff_t       long
-#else
-# undef  Void_t
-# define Void_t       void
-# define __malloc_ptr_t  char *
-#endif
-
-#ifdef _LIBC
-/* Used by GNU libc internals. */
-# define __malloc_size_t size_t
-# define __malloc_ptrdiff_t ptrdiff_t
-#elif !defined __attribute_malloc__
-# define __attribute_malloc__
-#endif
-
-#ifdef __GNUC__
-
-/* GCC can always grok prototypes.  For C++ programs we add throw()
-   to help it optimize the function calls.  But this works only with
-   gcc 2.8.x and egcs.  */
-# if defined __cplusplus && (__GNUC__ >= 3 || __GNUC_MINOR__ >= 8)
-#  define __THROW	throw ()
-# else
-#  define __THROW
-# endif
-# define __MALLOC_P(args)	args __THROW
-/* This macro will be used for functions which might take C++ callback
-   functions.  */
-# define __MALLOC_PMT(args)	args
-
-#else	/* Not GCC.  */
-
-# define __THROW
-
-# if (defined __STDC__ && __STDC__) || defined __cplusplus
-
-#  define __MALLOC_P(args)	args
-#  define __MALLOC_PMT(args)	args
-
-# else	/* Not ANSI C or C++.  */
-
-#  define __MALLOC_P(args)	()	/* No prototypes.  */
-#  define __MALLOC_PMT(args)	()
-
-# endif	/* ANSI C or C++.  */
-
-#endif	/* GCC.  */
-
-#ifndef NULL
-# ifdef __cplusplus
-#  define NULL	0
-# else
-#  define NULL	((__malloc_ptr_t) 0)
-# endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Nonzero if the malloc is already initialized.  */
-#ifdef _LIBC
-/* In the GNU libc we rename the global variable
-   `__malloc_initialized' to `__libc_malloc_initialized'.  */
-# define __malloc_initialized __libc_malloc_initialized
-#endif
-extern int cvmx__malloc_initialized;
-
-
-/* SVID2/XPG mallinfo structure */
-
-struct mallinfo {
-  int arena;    /* non-mmapped space allocated from system */
-  int ordblks;  /* number of free chunks */
-  int smblks;   /* number of fastbin blocks */
-  int hblks;    /* number of mmapped regions */
-  int hblkhd;   /* space in mmapped regions */
-  int usmblks;  /* maximum total allocated space */
-  int fsmblks;  /* space available in freed fastbin blocks */
-  int uordblks; /* total allocated space */
-  int fordblks; /* total free space */
-  int keepcost; /* top-most, releasable (via malloc_trim) space */
-};
-
-/* Returns a copy of the updated current mallinfo. */
-extern struct mallinfo mallinfo __MALLOC_P ((void));
-
-/* SVID2/XPG mallopt options */
-#ifndef M_MXFAST
-# define M_MXFAST  1	/* maximum request size for "fastbins" */
-#endif
-#ifndef M_NLBLKS
-# define M_NLBLKS  2	/* UNUSED in this malloc */
-#endif
-#ifndef M_GRAIN
-# define M_GRAIN   3	/* UNUSED in this malloc */
-#endif
-#ifndef M_KEEP
-# define M_KEEP    4	/* UNUSED in this malloc */
-#endif
-
-/* mallopt options that actually do something */
-#define M_TRIM_THRESHOLD    -1
-#define M_TOP_PAD           -2
-#define M_MMAP_THRESHOLD    -3
-#define M_MMAP_MAX          -4
-#define M_CHECK_ACTION      -5
-
-/* General SVID/XPG interface to tunable parameters. */
-extern int mallopt __MALLOC_P ((int __param, int __val));
-
-/* Release all but __pad bytes of freed top-most memory back to the
-   system. Return 1 if successful, else 0. */
-extern int malloc_trim __MALLOC_P ((size_t __pad));
-
-/* Report the number of usable allocated bytes associated with allocated
-   chunk __ptr. */
-extern size_t malloc_usable_size __MALLOC_P ((__malloc_ptr_t __ptr));
-
-/* Prints brief summary statistics on stderr. */
-extern void malloc_stats __MALLOC_P ((void));
-
-/* Record the state of all malloc variables in an opaque data structure. */
-extern __malloc_ptr_t malloc_get_state __MALLOC_P ((void));
-
-/* Restore the state of all malloc variables from data obtained with
-   malloc_get_state(). */
-extern int malloc_set_state __MALLOC_P ((__malloc_ptr_t __ptr));
-
-/* Called once when malloc is initialized; redefining this variable in
-   the application provides the preferred way to set up the hook
-   pointers. */
-extern void (*cmvx__malloc_initialize_hook) __MALLOC_PMT ((void));
-/* Hooks for debugging and user-defined versions. */
-extern void (*cvmx__free_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
-					__const __malloc_ptr_t));
-extern __malloc_ptr_t (*cvmx__malloc_hook) __MALLOC_PMT ((size_t __size,
-						    __const __malloc_ptr_t));
-extern __malloc_ptr_t (*cvmx__realloc_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
-						     size_t __size,
-						     __const __malloc_ptr_t));
-extern __malloc_ptr_t (*cvmx__memalign_hook) __MALLOC_PMT ((size_t __alignment,
-						      size_t __size,
-						      __const __malloc_ptr_t));
-extern void (*__after_morecore_hook) __MALLOC_PMT ((void));
-
-/* Activate a standard set of debugging hooks. */
-extern void cvmx__malloc_check_init __MALLOC_P ((void));
-
-/* Internal routines, operating on "arenas".  */
-struct malloc_state;
-typedef struct malloc_state *mstate;
-#ifdef __cplusplus
-}; /* end of extern "C" */
-#endif
-
-
-#endif /* malloc.h */
diff --git a/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h b/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h
deleted file mode 100644
index de9ba6c..0000000
--- a/sys/contrib/octeon-sdk/cvmx-malloc/thread-m.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
-Copyright (c) 2001 Wolfram Gloger
-Copyright (c) 2006 Cavium networks
-
-Permission to use, copy, modify, distribute, and sell this software
-and its documentation for any purpose is hereby granted without fee,
-provided that (i) the above copyright notices and this permission
-notice appear in all copies of the software and related documentation,
-and (ii) the name of Wolfram Gloger may not be used in any advertising
-or publicity relating to the software.
-
-THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
-EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
-WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-
-IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
-INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
-DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
-WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
-OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-PERFORMANCE OF THIS SOFTWARE.
-*/
-
-/* $Id: thread-m.h 30481 2007-12-05 21:46:59Z rfranz $
-   One out of _LIBC, USE_PTHREADS, USE_THR or USE_SPROC should be
-   defined, otherwise the token NO_THREADS and dummy implementations
-   of the macros will be defined.  */
-
-#ifndef _THREAD_M_H
-#define _THREAD_M_H
-
-#undef thread_atfork_static
-
-
-#undef NO_THREADS /* No threads, provide dummy macros */
-
-typedef int thread_id;
-
-/* The mutex functions used to do absolutely nothing, i.e. lock,
-   trylock and unlock would always just return 0.  However, even
-   without any concurrently active threads, a mutex can be used
-   legitimately as an `in use' flag.  To make the code that is
-   protected by a mutex async-signal safe, these macros would have to
-   be based on atomic test-and-set operations, for example. */
-#ifdef __OCTEON__
-typedef cvmx_spinlock_t mutex_t;
-#define MUTEX_INITIALIZER          CMVX_SPINLOCK_UNLOCKED_VAL
-#define mutex_init(m)              cvmx_spinlock_init(m)
-#define mutex_lock(m)              cvmx_spinlock_lock(m)
-#define mutex_trylock(m)           (cvmx_spinlock_trylock(m))
-#define mutex_unlock(m)            cvmx_spinlock_unlock(m)
-#else
-
-typedef int mutex_t;
-
-#define MUTEX_INITIALIZER          0
-#define mutex_init(m)              (*(m) = 0)
-#define mutex_lock(m)              ((*(m) = 1), 0)
-#define mutex_trylock(m)           (*(m) ? 1 : ((*(m) = 1), 0))
-#define mutex_unlock(m)            (*(m) = 0)
-#endif
-
-
-
-typedef void *tsd_key_t;
-#define tsd_key_create(key, destr) do {} while(0)
-#define tsd_setspecific(key, data) ((key) = (data))
-#define tsd_getspecific(key, vptr) (vptr = (key))
-
-#define thread_atfork(prepare, parent, child) do {} while(0)
-
-
-#endif /* !defined(_THREAD_M_H) */
diff --git a/sys/contrib/octeon-sdk/cvmx-mdio.h b/sys/contrib/octeon-sdk/cvmx-mdio.h
index e203ffe..859f03e 100644
--- a/sys/contrib/octeon-sdk/cvmx-mdio.h
+++ b/sys/contrib/octeon-sdk/cvmx-mdio.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,26 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
  * clause 22 and clause 45 operations.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
 
 #ifndef __CVMX_MIO_H__
 #define __CVMX_MIO_H__
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-clock.h>
+#else
+#include "cvmx-clock.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -310,6 +319,8 @@ typedef union
 #define CVMX_MMD_DEVICE_VENDOR_1     30
 #define CVMX_MMD_DEVICE_VENDOR_2     31
 
+#define CVMX_MDIO_TIMEOUT   100000 /* 100 millisec */
+
 /* Helper function to put MDIO interface into clause 45 mode */
 static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
 {
@@ -331,6 +342,30 @@ static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
 }
 
 /**
+ * @INTERNAL
+ * Function to read SMIX_RD_DAT and check for timeouts. This
+ * code sequence is done fairly often, so put in in one spot.
+ *
+ * @param bus_id SMI/MDIO bus to read
+ *
+ * @return Value of SMIX_RD_DAT. pending will be set on
+ *         a timeout.
+ */
+static inline cvmx_smix_rd_dat_t __cvmx_mdio_read_rd_dat(int bus_id)
+{
+    cvmx_smix_rd_dat_t smi_rd;
+    uint64_t done = cvmx_get_cycle() + (uint64_t)CVMX_MDIO_TIMEOUT *
+                       cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
+    do
+    {
+        cvmx_wait(1000);
+        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
+    } while (smi_rd.s.pending && (cvmx_get_cycle() < done));
+    return smi_rd;
+}
+
+
+/**
  * Perform an MII read. This function is used to read PHY
  * registers controlling auto negotiation.
  *
@@ -343,9 +378,24 @@ static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
  */
 static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
 {
+#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) && defined(CONFIG_PHYLIB)
+	struct mii_bus *bus;
+	int rv;
+
+	BUG_ON(bus_id > 1 || bus_id < 0);
+
+	bus = octeon_mdiobuses[bus_id];
+	if (bus == NULL)
+		return -1;
+
+	rv = mdiobus_read(bus, phy_id, location);
+
+	if (rv < 0)
+		return -1;
+	return rv;
+#else
     cvmx_smix_cmd_t smi_cmd;
     cvmx_smix_rd_dat_t smi_rd;
-    int timeout = 1000;
 
     if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
         __cvmx_mdio_set_clause22_mode(bus_id);
@@ -356,16 +406,12 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
     smi_cmd.s.reg_adr = location;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
-    } while (smi_rd.s.pending && timeout--);
-
+    smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
     if (smi_rd.s.val)
         return smi_rd.s.dat;
     else
         return -1;
+#endif
 }
 
 
@@ -384,9 +430,24 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
  */
 static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
 {
-    cvmx_smix_cmd_t smi_cmd;
+#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) && defined(CONFIG_PHYLIB)
+	struct mii_bus *bus;
+	int rv;
+
+	BUG_ON(bus_id > 1 || bus_id < 0);
+
+	bus = octeon_mdiobuses[bus_id];
+	if (bus == NULL)
+		return -1;
+
+	rv = mdiobus_write(bus, phy_id, location, (u16)val);
+
+	if (rv < 0)
+		return -1;
+	return 0;
+#else
+     cvmx_smix_cmd_t smi_cmd;
     cvmx_smix_wr_dat_t smi_wr;
-    int timeout = 1000;
 
     if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
         __cvmx_mdio_set_clause22_mode(bus_id);
@@ -401,17 +462,15 @@ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
     smi_cmd.s.reg_adr = location;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-    } while (smi_wr.s.pending && --timeout);
-    if (timeout <= 0)
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
+        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
         return -1;
 
     return 0;
+#endif
 }
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 /**
  * Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY
  * registers controlling auto negotiation.
@@ -430,7 +489,6 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int loca
     cvmx_smix_cmd_t smi_cmd;
     cvmx_smix_rd_dat_t smi_rd;
     cvmx_smix_wr_dat_t smi_wr;
-    int timeout = 1000;
 
     if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
         return -1;
@@ -447,12 +505,8 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int loca
     smi_cmd.s.reg_adr = device;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-    } while (smi_wr.s.pending && --timeout);
-    if (timeout <= 0)
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
+        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
     {
         cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(address)\n", bus_id, phy_id, device, location);
         return -1;
@@ -464,13 +518,8 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int loca
     smi_cmd.s.reg_adr = device;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
-    } while (smi_rd.s.pending && timeout--);
-
-    if(timeout <= 0)
+    smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
+    if (smi_rd.s.pending)
     {
         cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(data)\n", bus_id, phy_id, device, location);
         return -1;
@@ -504,7 +553,6 @@ static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int loc
 {
     cvmx_smix_cmd_t smi_cmd;
     cvmx_smix_wr_dat_t smi_wr;
-    int timeout = 1000;
 
     if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
         return -1;
@@ -521,12 +569,8 @@ static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int loc
     smi_cmd.s.reg_adr = device;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-    } while (smi_wr.s.pending && --timeout);
-    if (timeout <= 0)
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
+        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
         return -1;
 
     smi_wr.u64 = 0;
@@ -539,17 +583,13 @@ static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int loc
     smi_cmd.s.reg_adr = device;
     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
 
-    do
-    {
-        cvmx_wait(1000);
-        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-    } while (smi_wr.s.pending && --timeout);
-    if (timeout <= 0)
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
+        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
         return -1;
 
     return 0;
 }
-
+#endif
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-mgmt-port.c b/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
index f40cb8c..108ef00 100644
--- a/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
+++ b/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Support functions for managing the MII management port
  *
- * <hr>$Revision: 42151 $<hr>
+ * <hr>$Revision: 49628 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-bootmem.h"
@@ -54,6 +56,17 @@
 #include "cvmx-mdio.h"
 #include "cvmx-mgmt-port.h"
 #include "cvmx-sysinfo.h"
+#include "cvmx-error.h"
+
+/**
+ * Enum of MIX interface modes
+ */
+typedef enum
+{
+    CVMX_MGMT_PORT_NONE = 0,
+    CVMX_MGMT_PORT_MII_MODE,
+    CVMX_MGMT_PORT_RGMII_MODE,
+} cvmx_mgmt_port_mode_t;
 
 /**
  * Format of the TX/RX ring buffer entries
@@ -65,7 +78,8 @@ typedef union
     {
         uint64_t    reserved_62_63  : 2;
         uint64_t    len             : 14;   /* Length of the buffer/packet in bytes */
-        uint64_t    code            : 8;    /* The RX error code */
+        uint64_t    tstamp          : 1;    /* For TX, signals that the packet should be timestamped */
+        uint64_t    code            : 7;    /* The RX error code */
         uint64_t    addr            : 40;   /* Physical address of the buffer */
     } s;
 } cvmx_mgmt_port_ring_entry_t;
@@ -78,12 +92,13 @@ typedef struct
     cvmx_spinlock_t             lock;           /* Used for exclusive access to this structure */
     int                         tx_write_index; /* Where the next TX will write in the tx_ring and tx_buffers */
     int                         rx_read_index;  /* Where the next RX will be in the rx_ring and rx_buffers */
-    int                         phy_id;         /* The SMI/MDIO PHY address */
+    int                         port;           /* Port to use.  (This is the 'fake' IPD port number */
     uint64_t                    mac;            /* Our MAC address */
     cvmx_mgmt_port_ring_entry_t tx_ring[CVMX_MGMT_PORT_NUM_TX_BUFFERS];
     cvmx_mgmt_port_ring_entry_t rx_ring[CVMX_MGMT_PORT_NUM_RX_BUFFERS];
     char                        tx_buffers[CVMX_MGMT_PORT_NUM_TX_BUFFERS][CVMX_MGMT_PORT_TX_BUFFER_SIZE];
     char                        rx_buffers[CVMX_MGMT_PORT_NUM_RX_BUFFERS][CVMX_MGMT_PORT_RX_BUFFER_SIZE];
+    cvmx_mgmt_port_mode_t       mode;          /* Mode of the interface */
 } cvmx_mgmt_port_state_t;
 
 /**
@@ -101,7 +116,7 @@ int __cvmx_mgmt_port_num_ports(void)
 {
     if (OCTEON_IS_MODEL(OCTEON_CN56XX))
         return 1;
-    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
         return 2;
     else
         return 0;
@@ -110,7 +125,7 @@ int __cvmx_mgmt_port_num_ports(void)
 
 /**
  * Called to initialize a management port for use. Multiple calls
- * to this function accross applications is safe.
+ * to this function across applications is safe.
  *
  * @param port   Port to initialize
  *
@@ -132,12 +147,12 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
     }
     else
     {
-        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
+        const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
         if (block_desc)
             cvmx_mgmt_port_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
         else
         {
-            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Unable to get named block %s.\n", alloc_name);
+            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Unable to get named block %s on MIX%d.\n", alloc_name, port);
             return CVMX_MGMT_PORT_NO_MEMORY;
         }
     }
@@ -164,7 +179,6 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
         }
     }
 
-
     if (cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0)
     {
         cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port;
@@ -174,15 +188,16 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
         cvmx_mixx_oring1_t oring1;
         cvmx_mixx_iring1_t iring1;
         cvmx_mixx_ctl_t mix_ctl;
+        cvmx_agl_prtx_ctl_t agl_prtx_ctl;
 
         /* Make sure BIST passed */
         mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(port));
         if (mix_bist.u64)
-            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port MIX failed BIST (0x%016llx)\n", CAST64(mix_bist.u64));
+            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port MIX failed BIST (0x%016llx) on MIX%d\n", CAST64(mix_bist.u64), port);
 
         agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
         if (agl_gmx_bist.u64)
-            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port AGL failed BIST (0x%016llx)\n", CAST64(agl_gmx_bist.u64));
+            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port AGL failed BIST (0x%016llx) on MIX%d\n", CAST64(agl_gmx_bist.u64), port);
 
         /* Clear all state information */
         memset(state, 0, sizeof(*state));
@@ -192,11 +207,57 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
         mix_ctl.s.reset = 0;
         cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
 
-        /* Set the PHY address */
+        /* Read until reset == 0.  Timeout should never happen... */
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_MIXX_CTL(port), cvmx_mixx_ctl_t, reset, ==, 0, 300000000))
+        {
+            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Timeout waiting for MIX(%d) reset.\n", port);
+            return CVMX_MGMT_PORT_INIT_ERROR;
+        }
+
+        /* Set the PHY address and mode of the interface (RGMII/MII mode). */
         if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
-            state->phy_id = -1;
+        {
+            state->port = -1;
+            state->mode = CVMX_MGMT_PORT_MII_MODE;
+        }
         else
-            state->phy_id = port;  /* Will need to be change to match the board */
+        {
+            int port_num = CVMX_HELPER_BOARD_MGMT_IPD_PORT + port;
+            int phy_addr = cvmx_helper_board_get_mii_address(port_num);
+            if (phy_addr != -1)
+            {
+                cvmx_mdio_phy_reg_status_t phy_status;
+                /* Read PHY status register to find the mode of the interface. */
+                phy_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
+                if (phy_status.s.capable_extended_status == 0) // MII mode
+                    state->mode = CVMX_MGMT_PORT_MII_MODE;
+                else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                         && phy_status.s.capable_extended_status) // RGMII mode
+                    state->mode = CVMX_MGMT_PORT_RGMII_MODE;
+                else
+                    state->mode = CVMX_MGMT_PORT_NONE;
+            }
+            else
+            {
+                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Not able to read the PHY on MIX%d\n", port);
+                return CVMX_MGMT_PORT_INVALID_PARAM;
+            }
+            state->port = port_num;
+        }
+
+        /* All interfaces should be configured in same mode */
+        for (i = 0; i < __cvmx_mgmt_port_num_ports(); i++)
+        {
+            if (i != port
+                && cvmx_mgmt_port_state_ptr[i].mode != CVMX_MGMT_PORT_NONE
+                && cvmx_mgmt_port_state_ptr[i].mode != state->mode)
+            {
+                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: All ports in MIX interface are not configured in same mode.\n \
+	Port %d is configured as %d\n \
+	And Port %d is configured as %d\n", port, state->mode, i, cvmx_mgmt_port_state_ptr[i].mode);
+                return CVMX_MGMT_PORT_INVALID_PARAM;
+            }
+        }
 
         /* Create a default MAC address */
         state->mac = 0x000000dead000000ull;
@@ -249,7 +310,64 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
         mix_ctl.s.mrq_hwm = 1;      /* MII CB-request FIFO programmable high watermark */
         cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
 
-        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+        /* Select the mode of operation for the interface. */
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        {
+            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
+
+            if (state->mode == CVMX_MGMT_PORT_RGMII_MODE)
+                agl_prtx_ctl.s.mode = 0;
+            else if (state->mode == CVMX_MGMT_PORT_MII_MODE)
+                agl_prtx_ctl.s.mode = 1;
+            else
+            {
+                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Invalid mode for MIX(%d)\n", port);
+                return CVMX_MGMT_PORT_INVALID_PARAM;
+            }
+
+            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+	}
+
+        /* Initialize the physical layer. */
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        {
+            /* MII clocks counts are based on the 125Mhz reference, so our
+                delays need to be scaled to match the core clock rate. The
+                "+1" is to make sure rounding always waits a little too
+                long. */
+            uint64_t clock_scale = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 125000000 + 1;
+
+            /* Take the DLL and clock tree out of reset */
+            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
+            agl_prtx_ctl.s.clkrst = 0;
+            if (state->mode == CVMX_MGMT_PORT_RGMII_MODE) // RGMII Initialization
+            {
+                agl_prtx_ctl.s.dllrst = 0;
+                agl_prtx_ctl.s.clktx_byp = 0;
+            }
+            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+            cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));  /* Force write out before wait */
+
+            /* Wait for the DLL to lock.  External 125 MHz reference clock must be stable at this point. */
+            cvmx_wait(256 * clock_scale);
+
+            /* The rest of the config is common between RGMII/MII */
+
+            /* Enable the interface */
+            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
+            agl_prtx_ctl.s.enable = 1;
+            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+
+            /* Read the value back to force the previous write */
+            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
+
+            /* Enable the componsation controller */
+            agl_prtx_ctl.s.comp = 1;
+            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+            cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));  /* Force write out before wait */
+            cvmx_wait(1024 * clock_scale); // for componsation state to lock.
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
         {
             /* Force compensation values, as they are not determined properly by HW */
             cvmx_agl_gmx_drv_ctl_t drv_ctl;
@@ -270,6 +388,7 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
             cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
         }
     }
+    cvmx_error_enable_group(CVMX_ERROR_GROUP_MGMT_PORT, port);
     return CVMX_MGMT_PORT_SUCCESS;
 }
 
@@ -288,6 +407,8 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port)
     if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
         return CVMX_MGMT_PORT_INVALID_PARAM;
 
+    cvmx_error_disable_group(CVMX_ERROR_GROUP_MGMT_PORT, port);
+
     /* Stop packets from comming in */
     cvmx_mgmt_port_disable(port);
 
@@ -306,7 +427,6 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port)
 cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port)
 {
     cvmx_mgmt_port_state_t *state;
-    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
     cvmx_agl_gmx_inf_mode_t agl_gmx_inf_mode;
     cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl;
 
@@ -331,20 +451,15 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port)
     cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
 
     /* Enable the AGL block */
-    agl_gmx_inf_mode.u64 = 0;
-    agl_gmx_inf_mode.s.en = 1;
-    cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
+    if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+    {
+        agl_gmx_inf_mode.u64 = 0;
+        agl_gmx_inf_mode.s.en = 1;
+        cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
+    }
 
     /* Configure the port duplex and enables */
-    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
-    agl_gmx_prtx.s.tx_en = 1;
-    agl_gmx_prtx.s.rx_en = 1;
-    if (cvmx_mgmt_port_get_link(port) < 0)
-        agl_gmx_prtx.s.duplex = 0;
-    else
-        agl_gmx_prtx.s.duplex = 1;
-    agl_gmx_prtx.s.en = 1;
-    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+    cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port));
 
     cvmx_spinlock_unlock(&state->lock);
     return CVMX_MGMT_PORT_SUCCESS;
@@ -423,9 +538,11 @@ cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, void *buff
         memcpy(state->tx_buffers[state->tx_write_index] + 6, ((char*)&state->mac) + 2, 6);
         /* Update the TX ring buffer entry size */
         state->tx_ring[state->tx_write_index].s.len = packet_len;
+        /* This code doesn't support TX timestamps */
+        state->tx_ring[state->tx_write_index].s.tstamp = 0;
         /* Increment our TX index */
         state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS;
-        /* Ring the doorbell, send ing the packet */
+        /* Ring the doorbell, sending the packet */
         CVMX_SYNCWS;
         cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
         if (cvmx_read_csr(CVMX_MIXX_ORCNT(port)))
@@ -526,19 +643,13 @@ int cvmx_mgmt_port_receive(int port, int buffer_len, void *buffer)
         }
         else
         {
-            cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
             cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Receive error code %d. Packet dropped(Len %d), \n",
                          state->rx_ring[state->rx_read_index].s.code, state->rx_ring[state->rx_read_index].s.len + result);
             result = -state->rx_ring[state->rx_read_index].s.code;
 
 
             /* Check to see if we need to change the duplex. */
-            agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
-            if (cvmx_mgmt_port_get_link(port) < 0)
-                agl_gmx_prtx.s.duplex = 0;
-            else
-                agl_gmx_prtx.s.duplex = 1;
-            cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+            cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port));
         }
 
         /* Clean out the ring buffer entry. This size is -8 due to an errata
@@ -563,73 +674,6 @@ int cvmx_mgmt_port_receive(int port, int buffer_len, void *buffer)
     return result;
 }
 
-
-/**
- * Get the management port link status:
- * 100 = 100Mbps, full duplex
- * 10 = 10Mbps, full duplex
- * 0 = Link down
- * -10 = 10Mpbs, half duplex
- * -100 = 100Mbps, half duplex
- *
- * @param port   Management port
- *
- * @return
- */
-int cvmx_mgmt_port_get_link(int port)
-{
-    cvmx_mgmt_port_state_t *state;
-    int phy_status;
-
-    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
-        return CVMX_MGMT_PORT_INVALID_PARAM;
-
-    state = cvmx_mgmt_port_state_ptr + port;
-
-    /* Assume 100Mbps if we don't know the PHY address */
-    if (state->phy_id == -1)
-        return 100;
-
-
-    /* read BCM phy MDIO aux status summary register */
-    phy_status = cvmx_mdio_read(state->phy_id >> 8, state->phy_id & 0xff,
-				    0x19);
-    /* check the link status first */
-    if ((phy_status & 0x8000) == 0)
-      return 0;
-
-    switch ((phy_status >> 8) & 0x7)
-      {
-      case 0:
-	/* link down */
-	return 0;
-      case 1:
-	/* 10 half */
-	return -10;
-      case 2:
-	/* 10 full */
-	return 10;
-      case 3:
-	/* 100 half */
-	return -100;
-      case 4:
-	/* 100 T4 */
-	return 100;
-      case 5:
-	/* 100 full */
-	return 100;
-      case 6:
-	/* 1000 half */
-	return -1000;
-      case 7:
-	/* 1000 full */
-	return 1000;
-      }
-    /* something's amiss if we get here... */
-    return 0;
-}
-
-
 /**
  * Set the MAC address for a management port
  *
@@ -707,7 +751,7 @@ void cvmx_mgmt_port_set_multicast_list(int port, int flags)
     cvmx_spinlock_lock(&state->lock);
 
     agl_gmx_rxx_adr_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port));
-    
+
     /* Allow broadcast MAC addresses */
     if (!agl_gmx_rxx_adr_ctl.s.bcst)
 	agl_gmx_rxx_adr_ctl.s.bcst = 1;
@@ -728,7 +772,7 @@ void cvmx_mgmt_port_set_multicast_list(int port, int flags)
 	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 0);
     else
 	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1);
-    
+
     cvmx_spinlock_unlock(&state->lock);
 }
 
@@ -757,3 +801,151 @@ void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs)
     cvmx_spinlock_unlock(&state->lock);
 }
 
+/**
+ * Return the link state of an RGMII/MII port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_mgmt_port_link_set().
+ *
+ * @param port     The RGMII/MII interface port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t cvmx_mgmt_port_link_get(int port)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_helper_link_info_t result;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+    result.u64 = 0;
+
+    if (port > __cvmx_mgmt_port_num_ports())
+    {
+        cvmx_dprintf("WARNING: Invalid port %d\n", port);
+        return result;
+    }
+
+    if (state->port != -1)
+        return __cvmx_helper_board_link_get(state->port);
+    else // Simulator does not have PHY, use some defaults.
+    {
+        result.s.full_duplex = 1;
+        result.s.link_up = 1;
+        result.s.speed = 100;
+        return result;
+    }
+    return result;
+}
+
+/**
+ * Configure RGMII/MII port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ *
+ * @param port      RGMII/MII interface port
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_mgmt_port_link_set(int port, cvmx_helper_link_info_t link_info)
+{
+    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
+
+    /* Disable GMX before we make any changes. */
+    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+    agl_gmx_prtx.s.en = 0;
+    agl_gmx_prtx.s.tx_en = 0;
+    agl_gmx_prtx.s.rx_en = 0;
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t one_second = cvmx_clock_get_rate(CVMX_CLOCK_CORE);
+        /* Wait for GMX to be idle */
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==, 1, one_second)
+            || CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==, 1, one_second))
+        {
+            cvmx_dprintf("MIX%d: Timeout waiting for GMX to be idle\n", port);
+            return -1;
+        }
+    }
+
+    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+
+    /* Set duplex mode */
+    if (!link_info.s.link_up)
+        agl_gmx_prtx.s.duplex = 1;   /* Force full duplex on down links */
+    else
+        agl_gmx_prtx.s.duplex = link_info.s.full_duplex;
+
+   switch(link_info.s.speed)
+    {
+        case 10:
+            agl_gmx_prtx.s.speed = 0;
+            agl_gmx_prtx.s.slottime = 0;
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            {
+                agl_gmx_prtx.s.speed_msb = 1;
+                agl_gmx_prtx.s.burst = 1;
+            }
+         break;
+
+        case 100:
+            agl_gmx_prtx.s.speed = 0;
+            agl_gmx_prtx.s.slottime = 0;
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            {
+                agl_gmx_prtx.s.speed_msb = 0;
+                agl_gmx_prtx.s.burst = 1;
+            }
+            break;
+
+        case 1000:
+            /* 1000 MBits is only supported on 6XXX chips */
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            {
+                agl_gmx_prtx.s.speed_msb = 0;
+                agl_gmx_prtx.s.speed = 1;
+                agl_gmx_prtx.s.slottime = 1;  /* Only matters for half-duplex */
+                agl_gmx_prtx.s.burst = agl_gmx_prtx.s.duplex;
+            }
+            break;
+
+        /* No link */
+        case 0:
+        default:
+            break;
+    }
+
+    /* Write the new GMX setting with the port still disabled. */
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+    /* Read GMX CFG again to make sure the config is completed. */
+    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port;
+        cvmx_agl_gmx_txx_clk_t agl_clk;
+        agl_clk.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_CLK(port));
+        agl_clk.s.clk_cnt = 1;    /* MII (both speeds) and RGMII 1000 setting */
+        if (state->mode == CVMX_MGMT_PORT_RGMII_MODE)
+        {
+            if (link_info.s.speed == 10)
+                agl_clk.s.clk_cnt = 50;
+            else if (link_info.s.speed == 100)
+                agl_clk.s.clk_cnt = 5;
+        }
+        cvmx_write_csr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64);
+    }
+
+    /* Enable transmit and receive ports */
+    agl_gmx_prtx.s.tx_en = 1;
+    agl_gmx_prtx.s.rx_en = 1;
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+    /* Enable the link. */
+    agl_gmx_prtx.s.en = 1;
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+    return 0;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-mgmt-port.h b/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
index 6b78cf6..90b531d 100644
--- a/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
+++ b/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,25 @@
 
 
 
+
 /**
  * @file
  *
  * Support functions for managing the MII management port
  *
- * <hr>$Revision: 42115 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_MGMT_PORT_H__
 #define __CVMX_MGMT_PORT_H__
 
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define CVMX_MGMT_PORT_NUM_PORTS        2       /* Right now we only have one mgmt port */
 #define CVMX_MGMT_PORT_NUM_TX_BUFFERS   16      /* Number of TX ring buffer entries and buffers */
 #define CVMX_MGMT_PORT_NUM_RX_BUFFERS   128     /* Number of RX ring buffer entries and buffers */
@@ -63,11 +72,12 @@ typedef enum
     CVMX_MGMT_PORT_SUCCESS = 0,
     CVMX_MGMT_PORT_NO_MEMORY = -1,
     CVMX_MGMT_PORT_INVALID_PARAM = -2,
+    CVMX_MGMT_PORT_INIT_ERROR = -3,
 } cvmx_mgmt_port_result_t;
 
 
 /* Enumeration of Net Device interface flags. */
-typedef enum 
+typedef enum
 {
     CVMX_IFF_PROMISC = 0x100, 		/* receive all packets           */
     CVMX_IFF_ALLMULTI = 0x200, 		/* receive all multicast packets */
@@ -137,20 +147,6 @@ extern cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, voi
 extern int cvmx_mgmt_port_receive(int port, int buffer_len, void *buffer);
 
 /**
- * Get the management port link status:
- * 100 = 100Mbps, full duplex
- * 10 = 10Mbps, full duplex
- * 0 = Link down
- * -10 = 10Mpbs, half duplex
- * -100 = 100Mbps, half duplex
- *
- * @param port   Management port
- *
- * @return
- */
-extern int cvmx_mgmt_port_get_link(int port);
-
-/**
  * Set the MAC address for a management port
  *
  * @param port   Management port
@@ -168,6 +164,7 @@ extern cvmx_mgmt_port_result_t cvmx_mgmt_port_set_mac(int port, uint64_t mac);
  * @return MAC address
  */
 extern uint64_t cvmx_mgmt_port_get_mac(int port);
+#define CVMX_MGMT_PORT_GET_MAC_ERROR ((unsigned long long)-2LL)
 
 /**
  * Set the multicast list.
@@ -185,9 +182,36 @@ extern void cvmx_mgmt_port_set_multicast_list(int port, int flags);
  * to 1514 assuming the standard 14 byte L2 header.
  *
  * @param port   Management port
- * @param size_without_crc
+ * @param size_without_fcs
  *               Size in bytes without FCS
  */
 extern void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs);
 
+/**
+ * Return the link state of an RGMII/MII port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to __cvmx_mgmt_port_link_set().
+ *
+ * @param port     The RGMII/MII interface port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t cvmx_mgmt_port_link_get(int port);
+
+/**
+ * Configure RGMII/MII port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ *
+ * @param port      RGMII/MII interface port
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_mgmt_port_link_set(int port, cvmx_helper_link_info_t link_info);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __CVMX_MGMT_PORT_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-mio-defs.h b/sys/contrib/octeon-sdk/cvmx-mio-defs.h
new file mode 100644
index 0000000..bd006f6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-mio-defs.h
@@ -0,0 +1,6586 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-mio-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon mio.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_MIO_TYPEDEFS_H__
+#define __CVMX_MIO_TYPEDEFS_H__
+
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
+}
+#else
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#endif
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#endif
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
+}
+#else
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#endif
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
+static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001550ull);
+}
+#else
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001420ull);
+}
+#else
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001580ull);
+}
+#else
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#endif
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001518ull);
+}
+#else
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#endif
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_READ_TIMES CVMX_MIO_FUS_READ_TIMES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_READ_TIMES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001570ull);
+}
+#else
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_REPAIR_RES0 CVMX_MIO_FUS_REPAIR_RES0_FUNC()
+static inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001558ull);
+}
+#else
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_REPAIR_RES1 CVMX_MIO_FUS_REPAIR_RES1_FUNC()
+static inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001560ull);
+}
+#else
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_REPAIR_RES2 CVMX_MIO_FUS_REPAIR_RES2_FUNC()
+static inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_FUS_REPAIR_RES2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001568ull);
+}
+#else
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#endif
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
+static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001578ull);
+}
+#else
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#endif
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_GPIO_COMP CVMX_MIO_GPIO_COMP_FUNC()
+static inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_GPIO_COMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800000000C8ull);
+}
+#else
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000168ull);
+}
+#else
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000170ull);
+}
+#else
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000178ull);
+}
+#else
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
+static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001448ull);
+}
+#else
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+		cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001440ull);
+}
+#else
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CLOCK_CFG CVMX_MIO_PTP_CLOCK_CFG_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_CLOCK_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F00ull);
+}
+#else
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CLOCK_COMP CVMX_MIO_PTP_CLOCK_COMP_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_CLOCK_COMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F18ull);
+}
+#else
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CLOCK_HI CVMX_MIO_PTP_CLOCK_HI_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_CLOCK_HI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F10ull);
+}
+#else
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_CLOCK_LO CVMX_MIO_PTP_CLOCK_LO_FUNC()
+static inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_CLOCK_LO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F08ull);
+}
+#else
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_EVT_CNT CVMX_MIO_PTP_EVT_CNT_FUNC()
+static inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_EVT_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F28ull);
+}
+#else
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_PTP_TIMESTAMP CVMX_MIO_PTP_TIMESTAMP_FUNC()
+static inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_PTP_TIMESTAMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000000F20ull);
+}
+#else
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_BOOT CVMX_MIO_RST_BOOT_FUNC()
+static inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_RST_BOOT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001600ull);
+}
+#else
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_CFG CVMX_MIO_RST_CFG_FUNC()
+static inline uint64_t CVMX_MIO_RST_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_RST_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001610ull);
+}
+#else
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_DELAY CVMX_MIO_RST_DELAY_FUNC()
+static inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_RST_DELAY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001608ull);
+}
+#else
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_INT CVMX_MIO_RST_INT_FUNC()
+static inline uint64_t CVMX_MIO_RST_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_RST_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001628ull);
+}
+#else
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_RST_INT_EN CVMX_MIO_RST_INT_EN_FUNC()
+static inline uint64_t CVMX_MIO_RST_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_MIO_RST_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001630ull);
+}
+#else
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512;
+}
+#else
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512;
+}
+#else
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512;
+}
+#else
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512;
+}
+#else
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000488ull);
+}
+#else
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000480ull);
+}
+#else
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000520ull);
+}
+#else
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000450ull);
+}
+#else
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
+static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000708ull);
+}
+#else
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000408ull);
+}
+#else
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000410ull);
+}
+#else
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000418ull);
+}
+#else
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000428ull);
+}
+#else
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000420ull);
+}
+#else
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000430ull);
+}
+#else
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000400ull);
+}
+#else
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000608ull);
+}
+#else
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000530ull);
+}
+#else
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000620ull);
+}
+#else
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000438ull);
+}
+#else
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000630ull);
+}
+#else
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000610ull);
+}
+#else
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000638ull);
+}
+#else
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000618ull);
+}
+#else
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000700ull);
+}
+#else
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000600ull);
+}
+#else
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000528ull);
+}
+#else
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000440ull);
+}
+#else
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000000538ull);
+}
+#else
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024;
+}
+#else
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
+#endif
+
+/**
+ * cvmx_mio_boot_bist_stat
+ *
+ * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register
+ *
+ * Contains the BIST status for the MIO boot memories.  '0' = pass, '1' = fail.
+ */
+union cvmx_mio_boot_bist_stat
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_bist_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_mio_boot_bist_stat_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ncbo_1                       : 1;  /**< NCB output FIFO 1 BIST status */
+	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO 0 BIST status */
+	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
+#else
+	uint64_t ncbi                         : 1;
+	uint64_t loc                          : 1;
+	uint64_t ncbo_0                       : 1;
+	uint64_t ncbo_1                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
+	struct cvmx_mio_boot_bist_stat_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
+	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
+#else
+	uint64_t ncbi                         : 1;
+	uint64_t loc                          : 1;
+	uint64_t ncbo_0                       : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn38xx;
+	struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
+	struct cvmx_mio_boot_bist_stat_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t pcm_1                        : 1;  /**< PCM memory 1 BIST status */
+	uint64_t pcm_0                        : 1;  /**< PCM memory 0 BIST status */
+	uint64_t ncbo_1                       : 1;  /**< NCB output FIFO 1 BIST status */
+	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO 0 BIST status */
+	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
+#else
+	uint64_t ncbi                         : 1;
+	uint64_t loc                          : 1;
+	uint64_t ncbo_0                       : 1;
+	uint64_t ncbo_1                       : 1;
+	uint64_t pcm_0                        : 1;
+	uint64_t pcm_1                        : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn50xx;
+	struct cvmx_mio_boot_bist_stat_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t ndf                          : 2;  /**< NAND flash BIST status */
+	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
+	uint64_t dma                          : 1;  /**< DMA memory BIST status */
+	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
+#else
+	uint64_t ncbi                         : 1;
+	uint64_t loc                          : 1;
+	uint64_t dma                          : 1;
+	uint64_t ncbo_0                       : 1;
+	uint64_t ndf                          : 2;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn52xx;
+	struct cvmx_mio_boot_bist_stat_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t ncbo_0                       : 1;  /**< NCB output FIFO BIST status */
+	uint64_t dma                          : 1;  /**< DMA memory BIST status */
+	uint64_t loc                          : 1;  /**< Local memory BIST status */
+	uint64_t ncbi                         : 1;  /**< NCB input FIFO BIST status */
+#else
+	uint64_t ncbi                         : 1;
+	uint64_t loc                          : 1;
+	uint64_t dma                          : 1;
+	uint64_t ncbo_0                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xxp1;
+	struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
+	struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
+	struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
+	struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+	struct cvmx_mio_boot_bist_stat_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t stat                         : 9;  /**< BIST status */
+#else
+	uint64_t stat                         : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn63xx;
+	struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
+};
+typedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t;
+
+/**
+ * cvmx_mio_boot_comp
+ *
+ * MIO_BOOT_COMP = MIO Boot Compensation Register
+ *
+ * Reset value is as follows:
+ *
+ * no pullups,               PCTL=38, NCTL=30 (25 ohm termination)
+ * pullup on boot_ad[9],     PCTL=19, NCTL=15 (50 ohm termination)
+ * pullup on boot_ad[10],    PCTL=15, NCTL=12 (65 ohm termination)
+ * pullups on boot_ad[10:9], PCTL=15, NCTL=12 (65 ohm termination)
+ */
+union cvmx_mio_boot_comp
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_comp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_mio_boot_comp_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pctl                         : 5;  /**< Boot bus PCTL */
+	uint64_t nctl                         : 5;  /**< Boot bus NCTL */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn50xx;
+	struct cvmx_mio_boot_comp_cn50xx      cn52xx;
+	struct cvmx_mio_boot_comp_cn50xx      cn52xxp1;
+	struct cvmx_mio_boot_comp_cn50xx      cn56xx;
+	struct cvmx_mio_boot_comp_cn50xx      cn56xxp1;
+	struct cvmx_mio_boot_comp_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t pctl                         : 6;  /**< Boot bus PCTL */
+	uint64_t nctl                         : 6;  /**< Boot bus NCTL */
+#else
+	uint64_t nctl                         : 6;
+	uint64_t pctl                         : 6;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn63xx;
+	struct cvmx_mio_boot_comp_cn63xx      cn63xxp1;
+};
+typedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t;
+
+/**
+ * cvmx_mio_boot_dma_cfg#
+ *
+ * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines)
+ *
+ * SIZE is specified in number of bus transfers, where one transfer is equal to the following number
+ * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]:
+ *
+ * WIDTH     DDR      Transfer Size (bytes)
+ * ----------------------------------------
+ *   0        0               2
+ *   0        1               4
+ *   1        0               4
+ *   1        1               8
+ *
+ * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1).
+ */
+union cvmx_mio_boot_dma_cfgx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_dma_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t en                           : 1;  /**< DMA Engine X enable */
+	uint64_t rw                           : 1;  /**< DMA Engine X R/W bit (0 = read, 1 = write) */
+	uint64_t clr                          : 1;  /**< DMA Engine X clear EN on device terminated burst */
+	uint64_t reserved_60_60               : 1;
+	uint64_t swap32                       : 1;  /**< DMA Engine X 32 bit swap */
+	uint64_t swap16                       : 1;  /**< DMA Engine X 16 bit swap */
+	uint64_t swap8                        : 1;  /**< DMA Engine X 8 bit swap */
+	uint64_t endian                       : 1;  /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */
+	uint64_t size                         : 20; /**< DMA Engine X size */
+	uint64_t adr                          : 36; /**< DMA Engine X address */
+#else
+	uint64_t adr                          : 36;
+	uint64_t size                         : 20;
+	uint64_t endian                       : 1;
+	uint64_t swap8                        : 1;
+	uint64_t swap16                       : 1;
+	uint64_t swap32                       : 1;
+	uint64_t reserved_60_60               : 1;
+	uint64_t clr                          : 1;
+	uint64_t rw                           : 1;
+	uint64_t en                           : 1;
+#endif
+	} s;
+	struct cvmx_mio_boot_dma_cfgx_s       cn52xx;
+	struct cvmx_mio_boot_dma_cfgx_s       cn52xxp1;
+	struct cvmx_mio_boot_dma_cfgx_s       cn56xx;
+	struct cvmx_mio_boot_dma_cfgx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_cfgx_s       cn63xx;
+	struct cvmx_mio_boot_dma_cfgx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t;
+
+/**
+ * cvmx_mio_boot_dma_int#
+ *
+ * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines)
+ *
+ */
+union cvmx_mio_boot_dma_intx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_dma_intx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dmarq                        : 1;  /**< DMA Engine X DMARQ asserted interrupt */
+	uint64_t done                         : 1;  /**< DMA Engine X request completion interrupt */
+#else
+	uint64_t done                         : 1;
+	uint64_t dmarq                        : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_boot_dma_intx_s       cn52xx;
+	struct cvmx_mio_boot_dma_intx_s       cn52xxp1;
+	struct cvmx_mio_boot_dma_intx_s       cn56xx;
+	struct cvmx_mio_boot_dma_intx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_intx_s       cn63xx;
+	struct cvmx_mio_boot_dma_intx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t;
+
+/**
+ * cvmx_mio_boot_dma_int_en#
+ *
+ * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines)
+ *
+ */
+union cvmx_mio_boot_dma_int_enx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_dma_int_enx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dmarq                        : 1;  /**< DMA Engine X DMARQ asserted interrupt enable */
+	uint64_t done                         : 1;  /**< DMA Engine X request completion interrupt enable */
+#else
+	uint64_t done                         : 1;
+	uint64_t dmarq                        : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_boot_dma_int_enx_s    cn52xx;
+	struct cvmx_mio_boot_dma_int_enx_s    cn52xxp1;
+	struct cvmx_mio_boot_dma_int_enx_s    cn56xx;
+	struct cvmx_mio_boot_dma_int_enx_s    cn56xxp1;
+	struct cvmx_mio_boot_dma_int_enx_s    cn63xx;
+	struct cvmx_mio_boot_dma_int_enx_s    cn63xxp1;
+};
+typedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t;
+
+/**
+ * cvmx_mio_boot_dma_tim#
+ *
+ * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines)
+ *
+ * DMACK_PI inverts the assertion level of boot_dmack[n].  The default polarity of boot_dmack[1:0] is
+ * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high
+ * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity).
+ * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default
+ * polarity on engine n.  To interface with CF cards in True IDE Mode, either a pullup should be placed
+ * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set.
+ *
+ * DMARQ_PI inverts the assertion level of boot_dmarq[n].  The default polarity of boot_dmarq[1:0] is
+ * active high, thus setting the polarity inversion bits changes the polarity to active low.  To
+ * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear.
+ *
+ * TIM_MULT specifies the timing multiplier for an engine.  The timing multiplier applies to all timing
+ * parameters, except for DMARQ and RD_DLY, which simply count eclks.  TIM_MULT is encoded as follows:
+ * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x.
+ *
+ * RD_DLY specifies the read sample delay in eclk cycles for an engine.  For reads, the data bus is
+ * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode).
+ * This parameter can delay that sampling edge by up to 7 eclks.  Note: the number of eclk cycles
+ * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY.
+ *
+ * If DDR is set, then WE_N must be less than WE_A.
+ */
+union cvmx_mio_boot_dma_timx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_dma_timx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dmack_pi                     : 1;  /**< DMA Engine X DMA ack polarity inversion */
+	uint64_t dmarq_pi                     : 1;  /**< DMA Engine X DMA request polarity inversion */
+	uint64_t tim_mult                     : 2;  /**< DMA Engine X timing multiplier */
+	uint64_t rd_dly                       : 3;  /**< DMA Engine X read sample delay */
+	uint64_t ddr                          : 1;  /**< DMA Engine X DDR mode */
+	uint64_t width                        : 1;  /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */
+	uint64_t reserved_48_54               : 7;
+	uint64_t pause                        : 6;  /**< DMA Engine X pause count */
+	uint64_t dmack_h                      : 6;  /**< DMA Engine X DMA ack hold count */
+	uint64_t we_n                         : 6;  /**< DMA Engine X write enable negated count */
+	uint64_t we_a                         : 6;  /**< DMA Engine X write enable asserted count */
+	uint64_t oe_n                         : 6;  /**< DMA Engine X output enable negated count */
+	uint64_t oe_a                         : 6;  /**< DMA Engine X output enable asserted count */
+	uint64_t dmack_s                      : 6;  /**< DMA Engine X DMA ack setup count */
+	uint64_t dmarq                        : 6;  /**< DMA Engine X DMA request count (must be non-zero) */
+#else
+	uint64_t dmarq                        : 6;
+	uint64_t dmack_s                      : 6;
+	uint64_t oe_a                         : 6;
+	uint64_t oe_n                         : 6;
+	uint64_t we_a                         : 6;
+	uint64_t we_n                         : 6;
+	uint64_t dmack_h                      : 6;
+	uint64_t pause                        : 6;
+	uint64_t reserved_48_54               : 7;
+	uint64_t width                        : 1;
+	uint64_t ddr                          : 1;
+	uint64_t rd_dly                       : 3;
+	uint64_t tim_mult                     : 2;
+	uint64_t dmarq_pi                     : 1;
+	uint64_t dmack_pi                     : 1;
+#endif
+	} s;
+	struct cvmx_mio_boot_dma_timx_s       cn52xx;
+	struct cvmx_mio_boot_dma_timx_s       cn52xxp1;
+	struct cvmx_mio_boot_dma_timx_s       cn56xx;
+	struct cvmx_mio_boot_dma_timx_s       cn56xxp1;
+	struct cvmx_mio_boot_dma_timx_s       cn63xx;
+	struct cvmx_mio_boot_dma_timx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t;
+
+/**
+ * cvmx_mio_boot_err
+ *
+ * MIO_BOOT_ERR = MIO Boot Error Register
+ *
+ * Contains the address decode error and wait mode error bits.  Address decode error is set when a
+ * boot bus access does not hit in any of the 8 remote regions or 2 local regions.  Wait mode error is
+ * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles.
+ */
+union cvmx_mio_boot_err
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t wait_err                     : 1;  /**< Wait mode error */
+	uint64_t adr_err                      : 1;  /**< Address decode error */
+#else
+	uint64_t adr_err                      : 1;
+	uint64_t wait_err                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_boot_err_s            cn30xx;
+	struct cvmx_mio_boot_err_s            cn31xx;
+	struct cvmx_mio_boot_err_s            cn38xx;
+	struct cvmx_mio_boot_err_s            cn38xxp2;
+	struct cvmx_mio_boot_err_s            cn50xx;
+	struct cvmx_mio_boot_err_s            cn52xx;
+	struct cvmx_mio_boot_err_s            cn52xxp1;
+	struct cvmx_mio_boot_err_s            cn56xx;
+	struct cvmx_mio_boot_err_s            cn56xxp1;
+	struct cvmx_mio_boot_err_s            cn58xx;
+	struct cvmx_mio_boot_err_s            cn58xxp1;
+	struct cvmx_mio_boot_err_s            cn63xx;
+	struct cvmx_mio_boot_err_s            cn63xxp1;
+};
+typedef union cvmx_mio_boot_err cvmx_mio_boot_err_t;
+
+/**
+ * cvmx_mio_boot_int
+ *
+ * MIO_BOOT_INT = MIO Boot Interrupt Register
+ *
+ * Contains the interrupt enable bits for address decode error and wait mode error.
+ */
+union cvmx_mio_boot_int
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t wait_int                     : 1;  /**< Wait mode error interrupt enable */
+	uint64_t adr_int                      : 1;  /**< Address decode error interrupt enable */
+#else
+	uint64_t adr_int                      : 1;
+	uint64_t wait_int                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_boot_int_s            cn30xx;
+	struct cvmx_mio_boot_int_s            cn31xx;
+	struct cvmx_mio_boot_int_s            cn38xx;
+	struct cvmx_mio_boot_int_s            cn38xxp2;
+	struct cvmx_mio_boot_int_s            cn50xx;
+	struct cvmx_mio_boot_int_s            cn52xx;
+	struct cvmx_mio_boot_int_s            cn52xxp1;
+	struct cvmx_mio_boot_int_s            cn56xx;
+	struct cvmx_mio_boot_int_s            cn56xxp1;
+	struct cvmx_mio_boot_int_s            cn58xx;
+	struct cvmx_mio_boot_int_s            cn58xxp1;
+	struct cvmx_mio_boot_int_s            cn63xx;
+	struct cvmx_mio_boot_int_s            cn63xxp1;
+};
+typedef union cvmx_mio_boot_int cvmx_mio_boot_int_t;
+
+/**
+ * cvmx_mio_boot_loc_adr
+ *
+ * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Address Register
+ *
+ * Specifies the address for reading or writing the local memory.  This address will post-increment
+ * following an access to the MIO Boot Local Memory Data Register (MIO_BOOT_LOC_DAT).
+ *
+ * Local memory region 0 exists from addresses 0x00 - 0x78.
+ * Local memory region 1 exists from addresses 0x80 - 0xf8.
+ */
+union cvmx_mio_boot_loc_adr
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_loc_adr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t adr                          : 5;  /**< Local memory address */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t adr                          : 5;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_boot_loc_adr_s        cn30xx;
+	struct cvmx_mio_boot_loc_adr_s        cn31xx;
+	struct cvmx_mio_boot_loc_adr_s        cn38xx;
+	struct cvmx_mio_boot_loc_adr_s        cn38xxp2;
+	struct cvmx_mio_boot_loc_adr_s        cn50xx;
+	struct cvmx_mio_boot_loc_adr_s        cn52xx;
+	struct cvmx_mio_boot_loc_adr_s        cn52xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cn56xx;
+	struct cvmx_mio_boot_loc_adr_s        cn56xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cn58xx;
+	struct cvmx_mio_boot_loc_adr_s        cn58xxp1;
+	struct cvmx_mio_boot_loc_adr_s        cn63xx;
+	struct cvmx_mio_boot_loc_adr_s        cn63xxp1;
+};
+typedef union cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_adr_t;
+
+/**
+ * cvmx_mio_boot_loc_cfg#
+ *
+ * MIO_BOOT_LOC_CFG = MIO Boot Local Region Config Register (1 per region * 2 regions)
+ *
+ * Contains local region enable and local region base address parameters.  Each local region is 128
+ * bytes organized as 16 entries x 8 bytes.
+ *
+ * Base address specifies address bits [31:7] of the region.
+ */
+union cvmx_mio_boot_loc_cfgx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_loc_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t en                           : 1;  /**< Local region X enable */
+	uint64_t reserved_28_30               : 3;
+	uint64_t base                         : 25; /**< Local region X base address */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t base                         : 25;
+	uint64_t reserved_28_30               : 3;
+	uint64_t en                           : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_boot_loc_cfgx_s       cn30xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn31xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn38xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn38xxp2;
+	struct cvmx_mio_boot_loc_cfgx_s       cn50xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn52xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn52xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cn56xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn56xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cn58xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn58xxp1;
+	struct cvmx_mio_boot_loc_cfgx_s       cn63xx;
+	struct cvmx_mio_boot_loc_cfgx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_loc_cfgx cvmx_mio_boot_loc_cfgx_t;
+
+/**
+ * cvmx_mio_boot_loc_dat
+ *
+ * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Data Register
+ *
+ * This is a pseudo-register that will read/write the local memory at the address specified by the MIO
+ * Boot Local Address Register (MIO_BOOT_LOC_ADR) when accessed.
+ */
+union cvmx_mio_boot_loc_dat
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_loc_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Local memory data */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_mio_boot_loc_dat_s        cn30xx;
+	struct cvmx_mio_boot_loc_dat_s        cn31xx;
+	struct cvmx_mio_boot_loc_dat_s        cn38xx;
+	struct cvmx_mio_boot_loc_dat_s        cn38xxp2;
+	struct cvmx_mio_boot_loc_dat_s        cn50xx;
+	struct cvmx_mio_boot_loc_dat_s        cn52xx;
+	struct cvmx_mio_boot_loc_dat_s        cn52xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cn56xx;
+	struct cvmx_mio_boot_loc_dat_s        cn56xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cn58xx;
+	struct cvmx_mio_boot_loc_dat_s        cn58xxp1;
+	struct cvmx_mio_boot_loc_dat_s        cn63xx;
+	struct cvmx_mio_boot_loc_dat_s        cn63xxp1;
+};
+typedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t;
+
+/**
+ * cvmx_mio_boot_pin_defs
+ *
+ * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register
+ *
+ */
+union cvmx_mio_boot_pin_defs
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_pin_defs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
+	uint64_t width                        : 1;  /**< Region 0 default bus width */
+	uint64_t dmack_p2                     : 1;  /**< boot_dmack[2] default polarity */
+	uint64_t dmack_p1                     : 1;  /**< boot_dmack[1] default polarity */
+	uint64_t dmack_p0                     : 1;  /**< boot_dmack[0] default polarity */
+	uint64_t term                         : 2;  /**< Selects default driver termination */
+	uint64_t nand                         : 1;  /**< Region 0 is NAND flash */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t nand                         : 1;
+	uint64_t term                         : 2;
+	uint64_t dmack_p0                     : 1;
+	uint64_t dmack_p1                     : 1;
+	uint64_t dmack_p2                     : 1;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_mio_boot_pin_defs_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
+	uint64_t width                        : 1;  /**< Region 0 default bus width */
+	uint64_t reserved_13_13               : 1;
+	uint64_t dmack_p1                     : 1;  /**< boot_dmack[1] default polarity */
+	uint64_t dmack_p0                     : 1;  /**< boot_dmack[0] default polarity */
+	uint64_t term                         : 2;  /**< Selects default driver termination */
+	uint64_t nand                         : 1;  /**< Region 0 is NAND flash */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t nand                         : 1;
+	uint64_t term                         : 2;
+	uint64_t dmack_p0                     : 1;
+	uint64_t dmack_p1                     : 1;
+	uint64_t reserved_13_13               : 1;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn52xx;
+	struct cvmx_mio_boot_pin_defs_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ale                          : 1;  /**< Region 0 default ALE mode */
+	uint64_t width                        : 1;  /**< Region 0 default bus width */
+	uint64_t dmack_p2                     : 1;  /**< boot_dmack[2] default polarity */
+	uint64_t dmack_p1                     : 1;  /**< boot_dmack[1] default polarity */
+	uint64_t dmack_p0                     : 1;  /**< boot_dmack[0] default polarity */
+	uint64_t term                         : 2;  /**< Selects default driver termination */
+	uint64_t reserved_0_8                 : 9;
+#else
+	uint64_t reserved_0_8                 : 9;
+	uint64_t term                         : 2;
+	uint64_t dmack_p0                     : 1;
+	uint64_t dmack_p1                     : 1;
+	uint64_t dmack_p2                     : 1;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn56xx;
+	struct cvmx_mio_boot_pin_defs_cn52xx  cn63xx;
+	struct cvmx_mio_boot_pin_defs_cn52xx  cn63xxp1;
+};
+typedef union cvmx_mio_boot_pin_defs cvmx_mio_boot_pin_defs_t;
+
+/**
+ * cvmx_mio_boot_reg_cfg#
+ */
+union cvmx_mio_boot_reg_cfgx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_reg_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t dmack                        : 2;  /**< Region X DMACK */
+	uint64_t tim_mult                     : 2;  /**< Region X timing multiplier */
+	uint64_t rd_dly                       : 3;  /**< Region X read sample delay */
+	uint64_t sam                          : 1;  /**< Region X SAM mode */
+	uint64_t we_ext                       : 2;  /**< Region X write enable count extension */
+	uint64_t oe_ext                       : 2;  /**< Region X output enable count extension */
+	uint64_t en                           : 1;  /**< Region X enable */
+	uint64_t orbit                        : 1;  /**< Region X or bit */
+	uint64_t ale                          : 1;  /**< Region X ALE mode */
+	uint64_t width                        : 1;  /**< Region X bus width */
+	uint64_t size                         : 12; /**< Region X size */
+	uint64_t base                         : 16; /**< Region X base address */
+#else
+	uint64_t base                         : 16;
+	uint64_t size                         : 12;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t orbit                        : 1;
+	uint64_t en                           : 1;
+	uint64_t oe_ext                       : 2;
+	uint64_t we_ext                       : 2;
+	uint64_t sam                          : 1;
+	uint64_t rd_dly                       : 3;
+	uint64_t tim_mult                     : 2;
+	uint64_t dmack                        : 2;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_mio_boot_reg_cfgx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t sam                          : 1;  /**< Region X SAM mode */
+	uint64_t we_ext                       : 2;  /**< Region X write enable count extension */
+	uint64_t oe_ext                       : 2;  /**< Region X output enable count extension */
+	uint64_t en                           : 1;  /**< Region X enable */
+	uint64_t orbit                        : 1;  /**< Region X or bit */
+	uint64_t ale                          : 1;  /**< Region X ALE mode */
+	uint64_t width                        : 1;  /**< Region X bus width */
+	uint64_t size                         : 12; /**< Region X size */
+	uint64_t base                         : 16; /**< Region X base address */
+#else
+	uint64_t base                         : 16;
+	uint64_t size                         : 12;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t orbit                        : 1;
+	uint64_t en                           : 1;
+	uint64_t oe_ext                       : 2;
+	uint64_t we_ext                       : 2;
+	uint64_t sam                          : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn30xx;
+	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn31xx;
+	struct cvmx_mio_boot_reg_cfgx_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t en                           : 1;  /**< Region X enable */
+	uint64_t orbit                        : 1;  /**< Region X or bit */
+	uint64_t reserved_28_29               : 2;
+	uint64_t size                         : 12; /**< Region X size */
+	uint64_t base                         : 16; /**< Region X base address */
+#else
+	uint64_t base                         : 16;
+	uint64_t size                         : 12;
+	uint64_t reserved_28_29               : 2;
+	uint64_t orbit                        : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_mio_boot_reg_cfgx_cn38xx  cn38xxp2;
+	struct cvmx_mio_boot_reg_cfgx_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t tim_mult                     : 2;  /**< Region X timing multiplier */
+	uint64_t rd_dly                       : 3;  /**< Region X read sample delay */
+	uint64_t sam                          : 1;  /**< Region X SAM mode */
+	uint64_t we_ext                       : 2;  /**< Region X write enable count extension */
+	uint64_t oe_ext                       : 2;  /**< Region X output enable count extension */
+	uint64_t en                           : 1;  /**< Region X enable */
+	uint64_t orbit                        : 1;  /**< Region X or bit */
+	uint64_t ale                          : 1;  /**< Region X ALE mode */
+	uint64_t width                        : 1;  /**< Region X bus width */
+	uint64_t size                         : 12; /**< Region X size */
+	uint64_t base                         : 16; /**< Region X base address */
+#else
+	uint64_t base                         : 16;
+	uint64_t size                         : 12;
+	uint64_t width                        : 1;
+	uint64_t ale                          : 1;
+	uint64_t orbit                        : 1;
+	uint64_t en                           : 1;
+	uint64_t oe_ext                       : 2;
+	uint64_t we_ext                       : 2;
+	uint64_t sam                          : 1;
+	uint64_t rd_dly                       : 3;
+	uint64_t tim_mult                     : 2;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} cn50xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn52xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn52xxp1;
+	struct cvmx_mio_boot_reg_cfgx_s       cn56xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn56xxp1;
+	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn58xx;
+	struct cvmx_mio_boot_reg_cfgx_cn30xx  cn58xxp1;
+	struct cvmx_mio_boot_reg_cfgx_s       cn63xx;
+	struct cvmx_mio_boot_reg_cfgx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_reg_cfgx cvmx_mio_boot_reg_cfgx_t;
+
+/**
+ * cvmx_mio_boot_reg_tim#
+ */
+union cvmx_mio_boot_reg_timx
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_reg_timx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pagem                        : 1;  /**< Region X page mode */
+	uint64_t waitm                        : 1;  /**< Region X wait mode */
+	uint64_t pages                        : 2;  /**< Region X page size */
+	uint64_t ale                          : 6;  /**< Region X ALE count */
+	uint64_t page                         : 6;  /**< Region X page count */
+	uint64_t wait                         : 6;  /**< Region X wait count */
+	uint64_t pause                        : 6;  /**< Region X pause count */
+	uint64_t wr_hld                       : 6;  /**< Region X write hold count */
+	uint64_t rd_hld                       : 6;  /**< Region X read hold count */
+	uint64_t we                           : 6;  /**< Region X write enable count */
+	uint64_t oe                           : 6;  /**< Region X output enable count */
+	uint64_t ce                           : 6;  /**< Region X chip enable count */
+	uint64_t adr                          : 6;  /**< Region X address count */
+#else
+	uint64_t adr                          : 6;
+	uint64_t ce                           : 6;
+	uint64_t oe                           : 6;
+	uint64_t we                           : 6;
+	uint64_t rd_hld                       : 6;
+	uint64_t wr_hld                       : 6;
+	uint64_t pause                        : 6;
+	uint64_t wait                         : 6;
+	uint64_t page                         : 6;
+	uint64_t ale                          : 6;
+	uint64_t pages                        : 2;
+	uint64_t waitm                        : 1;
+	uint64_t pagem                        : 1;
+#endif
+	} s;
+	struct cvmx_mio_boot_reg_timx_s       cn30xx;
+	struct cvmx_mio_boot_reg_timx_s       cn31xx;
+	struct cvmx_mio_boot_reg_timx_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pagem                        : 1;  /**< Region X page mode */
+	uint64_t waitm                        : 1;  /**< Region X wait mode */
+	uint64_t pages                        : 2;  /**< Region X page size (NOT IN PASS 1) */
+	uint64_t reserved_54_59               : 6;
+	uint64_t page                         : 6;  /**< Region X page count */
+	uint64_t wait                         : 6;  /**< Region X wait count */
+	uint64_t pause                        : 6;  /**< Region X pause count */
+	uint64_t wr_hld                       : 6;  /**< Region X write hold count */
+	uint64_t rd_hld                       : 6;  /**< Region X read hold count */
+	uint64_t we                           : 6;  /**< Region X write enable count */
+	uint64_t oe                           : 6;  /**< Region X output enable count */
+	uint64_t ce                           : 6;  /**< Region X chip enable count */
+	uint64_t adr                          : 6;  /**< Region X address count */
+#else
+	uint64_t adr                          : 6;
+	uint64_t ce                           : 6;
+	uint64_t oe                           : 6;
+	uint64_t we                           : 6;
+	uint64_t rd_hld                       : 6;
+	uint64_t wr_hld                       : 6;
+	uint64_t pause                        : 6;
+	uint64_t wait                         : 6;
+	uint64_t page                         : 6;
+	uint64_t reserved_54_59               : 6;
+	uint64_t pages                        : 2;
+	uint64_t waitm                        : 1;
+	uint64_t pagem                        : 1;
+#endif
+	} cn38xx;
+	struct cvmx_mio_boot_reg_timx_cn38xx  cn38xxp2;
+	struct cvmx_mio_boot_reg_timx_s       cn50xx;
+	struct cvmx_mio_boot_reg_timx_s       cn52xx;
+	struct cvmx_mio_boot_reg_timx_s       cn52xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cn56xx;
+	struct cvmx_mio_boot_reg_timx_s       cn56xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cn58xx;
+	struct cvmx_mio_boot_reg_timx_s       cn58xxp1;
+	struct cvmx_mio_boot_reg_timx_s       cn63xx;
+	struct cvmx_mio_boot_reg_timx_s       cn63xxp1;
+};
+typedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t;
+
+/**
+ * cvmx_mio_boot_thr
+ *
+ * MIO_BOOT_THR = MIO Boot Threshold Register
+ *
+ * Contains MIO Boot threshold values:
+ *
+ * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for
+ *           customer use).
+ *
+ * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA
+ *           accesses have completed.  If set to zero, only perform a DMA access when non-DMA
+ *           accesses are not pending.
+ */
+union cvmx_mio_boot_thr
+{
+	uint64_t u64;
+	struct cvmx_mio_boot_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t dma_thr                      : 6;  /**< DMA threshold */
+	uint64_t reserved_14_15               : 2;
+	uint64_t fif_cnt                      : 6;  /**< Current NCB FIFO count */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t fif_thr                      : 6;  /**< NCB busy threshold */
+#else
+	uint64_t fif_thr                      : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t fif_cnt                      : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t dma_thr                      : 6;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_mio_boot_thr_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t fif_cnt                      : 6;  /**< Current NCB FIFO count */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t fif_thr                      : 6;  /**< NCB busy threshold */
+#else
+	uint64_t fif_thr                      : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t fif_cnt                      : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn30xx;
+	struct cvmx_mio_boot_thr_cn30xx       cn31xx;
+	struct cvmx_mio_boot_thr_cn30xx       cn38xx;
+	struct cvmx_mio_boot_thr_cn30xx       cn38xxp2;
+	struct cvmx_mio_boot_thr_cn30xx       cn50xx;
+	struct cvmx_mio_boot_thr_s            cn52xx;
+	struct cvmx_mio_boot_thr_s            cn52xxp1;
+	struct cvmx_mio_boot_thr_s            cn56xx;
+	struct cvmx_mio_boot_thr_s            cn56xxp1;
+	struct cvmx_mio_boot_thr_cn30xx       cn58xx;
+	struct cvmx_mio_boot_thr_cn30xx       cn58xxp1;
+	struct cvmx_mio_boot_thr_s            cn63xx;
+	struct cvmx_mio_boot_thr_s            cn63xxp1;
+};
+typedef union cvmx_mio_boot_thr cvmx_mio_boot_thr_t;
+
+/**
+ * cvmx_mio_fus_bnk_dat#
+ *
+ * Notes:
+ * The intial state of MIO_FUS_BNK_DAT* is as if bank6 was just read i.e. DAT* = fus[895:768]
+ *
+ */
+union cvmx_mio_fus_bnk_datx
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_bnk_datx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dat                          : 64; /**< Efuse bank store
+                                                         For reads, the DAT gets the fus bank last read
+                                                         For write, the DAT determines which fuses to blow */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_mio_fus_bnk_datx_s        cn50xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn52xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn52xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cn56xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn56xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cn58xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn58xxp1;
+	struct cvmx_mio_fus_bnk_datx_s        cn63xx;
+	struct cvmx_mio_fus_bnk_datx_s        cn63xxp1;
+};
+typedef union cvmx_mio_fus_bnk_datx cvmx_mio_fus_bnk_datx_t;
+
+/**
+ * cvmx_mio_fus_dat0
+ */
+union cvmx_mio_fus_dat0
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_dat0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t man_info                     : 32; /**< Fuse information - manufacturing info [31:0] */
+#else
+	uint64_t man_info                     : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_fus_dat0_s            cn30xx;
+	struct cvmx_mio_fus_dat0_s            cn31xx;
+	struct cvmx_mio_fus_dat0_s            cn38xx;
+	struct cvmx_mio_fus_dat0_s            cn38xxp2;
+	struct cvmx_mio_fus_dat0_s            cn50xx;
+	struct cvmx_mio_fus_dat0_s            cn52xx;
+	struct cvmx_mio_fus_dat0_s            cn52xxp1;
+	struct cvmx_mio_fus_dat0_s            cn56xx;
+	struct cvmx_mio_fus_dat0_s            cn56xxp1;
+	struct cvmx_mio_fus_dat0_s            cn58xx;
+	struct cvmx_mio_fus_dat0_s            cn58xxp1;
+	struct cvmx_mio_fus_dat0_s            cn63xx;
+	struct cvmx_mio_fus_dat0_s            cn63xxp1;
+};
+typedef union cvmx_mio_fus_dat0 cvmx_mio_fus_dat0_t;
+
+/**
+ * cvmx_mio_fus_dat1
+ */
+union cvmx_mio_fus_dat1
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_dat1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t man_info                     : 32; /**< Fuse information - manufacturing info [63:32] */
+#else
+	uint64_t man_info                     : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_fus_dat1_s            cn30xx;
+	struct cvmx_mio_fus_dat1_s            cn31xx;
+	struct cvmx_mio_fus_dat1_s            cn38xx;
+	struct cvmx_mio_fus_dat1_s            cn38xxp2;
+	struct cvmx_mio_fus_dat1_s            cn50xx;
+	struct cvmx_mio_fus_dat1_s            cn52xx;
+	struct cvmx_mio_fus_dat1_s            cn52xxp1;
+	struct cvmx_mio_fus_dat1_s            cn56xx;
+	struct cvmx_mio_fus_dat1_s            cn56xxp1;
+	struct cvmx_mio_fus_dat1_s            cn58xx;
+	struct cvmx_mio_fus_dat1_s            cn58xxp1;
+	struct cvmx_mio_fus_dat1_s            cn63xx;
+	struct cvmx_mio_fus_dat1_s            cn63xxp1;
+};
+typedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t;
+
+/**
+ * cvmx_mio_fus_dat2
+ *
+ * Notes:
+ * CHIP_ID is consumed in several places within Octeon.
+ *
+ *    * Core COP0 ProcessorIdentification[Revision]
+ *    * Core EJTAG DeviceIdentification[Version]
+ *    * PCI_CFG02[RID]
+ *    * JTAG controller
+ *
+ * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses.
+ * Modification to the efuses will not change what the JTAG controller reports
+ * for CHIP_ID.
+ */
+union cvmx_mio_fus_dat2
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_dat2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - Dormant Encryption enable */
+	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_30_31               : 2;
+	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t nokasu                       : 1;
+	uint64_t reserved_30_31               : 2;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t dorm_crypto                  : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} s;
+	struct cvmx_mio_fus_dat2_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t pll_off                      : 4;  /**< Fuse information - core pll offset
+                                                         Used to compute the base offset for the core pll.
+                                                         the offset will be (PLL_OFF ^ 8)
+                                                         Note, these fuses can only be set from laser fuse */
+	uint64_t reserved_1_11                : 11;
+	uint64_t pp_dis                       : 1;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 1;
+	uint64_t reserved_1_11                : 11;
+	uint64_t pll_off                      : 4;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn30xx;
+	struct cvmx_mio_fus_dat2_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t pll_off                      : 4;  /**< Fuse information - core pll offset
+                                                         Used to compute the base offset for the core pll.
+                                                         the offset will be (PLL_OFF ^ 8)
+                                                         Note, these fuses can only be set from laser fuse */
+	uint64_t reserved_2_11                : 10;
+	uint64_t pp_dis                       : 2;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 2;
+	uint64_t reserved_2_11                : 10;
+	uint64_t pll_off                      : 4;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn31xx;
+	struct cvmx_mio_fus_dat2_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2)
+                                                         (PASS2 Only) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable
+                                                         (PASS2 Only) */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable
+                                                         (PASS2 Only) */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t pp_dis                       : 16; /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 16;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn38xx;
+	struct cvmx_mio_fus_dat2_cn38xx       cn38xxp2;
+	struct cvmx_mio_fus_dat2_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled
+                                                         (5020 does not have RAID co-processor) */
+	uint64_t reserved_30_31               : 2;
+	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2)
+                                                         (5020 does not have DFA co-processor) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_2_15                : 14;
+	uint64_t pp_dis                       : 2;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 2;
+	uint64_t reserved_2_15                : 14;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t nokasu                       : 1;
+	uint64_t reserved_30_31               : 2;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn50xx;
+	struct cvmx_mio_fus_dat2_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_30_31               : 2;
+	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_4_15                : 12;
+	uint64_t pp_dis                       : 4;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 4;
+	uint64_t reserved_4_15                : 12;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t nokasu                       : 1;
+	uint64_t reserved_30_31               : 2;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn52xx;
+	struct cvmx_mio_fus_dat2_cn52xx       cn52xxp1;
+	struct cvmx_mio_fus_dat2_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_30_31               : 2;
+	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_12_15               : 4;
+	uint64_t pp_dis                       : 12; /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 12;
+	uint64_t reserved_12_15               : 4;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t nokasu                       : 1;
+	uint64_t reserved_30_31               : 2;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn56xx;
+	struct cvmx_mio_fus_dat2_cn56xx       cn56xxp1;
+	struct cvmx_mio_fus_dat2_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_30_63               : 34;
+	uint64_t nokasu                       : 1;  /**< Fuse information - Disable Kasumi */
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t rst_sht                      : 1;  /**< Fuse information - When set, use short reset count */
+	uint64_t bist_dis                     : 1;  /**< Fuse information - BIST Disable */
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t pp_dis                       : 16; /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 16;
+	uint64_t chip_id                      : 8;
+	uint64_t bist_dis                     : 1;
+	uint64_t rst_sht                      : 1;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t nokasu                       : 1;
+	uint64_t reserved_30_63               : 34;
+#endif
+	} cn58xx;
+	struct cvmx_mio_fus_dat2_cn58xx       cn58xxp1;
+	struct cvmx_mio_fus_dat2_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t dorm_crypto                  : 1;  /**< Fuse information - Dormant Encryption enable */
+	uint64_t fus318                       : 1;  /**< Fuse information - a copy of fuse318 */
+	uint64_t raid_en                      : 1;  /**< Fuse information - RAID enabled */
+	uint64_t reserved_29_31               : 3;
+	uint64_t nodfa_cp2                    : 1;  /**< Fuse information - DFA Disable (CP2) */
+	uint64_t nomul                        : 1;  /**< Fuse information - VMUL disable */
+	uint64_t nocrypto                     : 1;  /**< Fuse information - AES/DES/HASH disable */
+	uint64_t reserved_24_25               : 2;
+	uint64_t chip_id                      : 8;  /**< Fuse information - CHIP_ID */
+	uint64_t reserved_6_15                : 10;
+	uint64_t pp_dis                       : 6;  /**< Fuse information - PP_DISABLES */
+#else
+	uint64_t pp_dis                       : 6;
+	uint64_t reserved_6_15                : 10;
+	uint64_t chip_id                      : 8;
+	uint64_t reserved_24_25               : 2;
+	uint64_t nocrypto                     : 1;
+	uint64_t nomul                        : 1;
+	uint64_t nodfa_cp2                    : 1;
+	uint64_t reserved_29_31               : 3;
+	uint64_t raid_en                      : 1;
+	uint64_t fus318                       : 1;
+	uint64_t dorm_crypto                  : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn63xx;
+	struct cvmx_mio_fus_dat2_cn63xx       cn63xxp1;
+};
+typedef union cvmx_mio_fus_dat2 cvmx_mio_fus_dat2_t;
+
+/**
+ * cvmx_mio_fus_dat3
+ */
+union cvmx_mio_fus_dat3
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_dat3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t pll_ctl                      : 10; /**< Fuse information - PLL control */
+	uint64_t dfa_info_dte                 : 3;  /**< Fuse information - DFA information (DTE) */
+	uint64_t dfa_info_clm                 : 4;  /**< Fuse information - DFA information (Cluster mask) */
+	uint64_t reserved_40_40               : 1;
+	uint64_t ema                          : 2;  /**< Fuse information - EMA */
+	uint64_t efus_lck_rsv                 : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_lck_man                 : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t pll_half_dis                 : 1;  /**< Fuse information - RCLK PLL control */
+	uint64_t l2c_crip                     : 3;  /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */
+	uint64_t pll_div4                     : 1;  /**< Fuse information - PLL DIV4 mode
+                                                         (laser fuse only) */
+	uint64_t reserved_29_30               : 2;
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Present (when blown '1') */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE) */
+	uint64_t icache                       : 24; /**< Fuse information - ICACHE Hard Repair Data */
+#else
+	uint64_t icache                       : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t reserved_29_30               : 2;
+	uint64_t pll_div4                     : 1;
+	uint64_t l2c_crip                     : 3;
+	uint64_t pll_half_dis                 : 1;
+	uint64_t efus_lck_man                 : 1;
+	uint64_t efus_lck_rsv                 : 1;
+	uint64_t ema                          : 2;
+	uint64_t reserved_40_40               : 1;
+	uint64_t dfa_info_clm                 : 4;
+	uint64_t dfa_info_dte                 : 3;
+	uint64_t pll_ctl                      : 10;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_mio_fus_dat3_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pll_div4                     : 1;  /**< Fuse information - PLL DIV4 mode
+                                                         (laser fuse only) */
+	uint64_t reserved_29_30               : 2;
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Enable (when blown '1') */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store. */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE) */
+	uint64_t icache                       : 24; /**< Fuse information - ICACHE Hard Repair Data */
+#else
+	uint64_t icache                       : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t reserved_29_30               : 2;
+	uint64_t pll_div4                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_mio_fus_dat3_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pll_div4                     : 1;  /**< Fuse information - PLL DIV4 mode
+                                                         (laser fuse only) */
+	uint64_t zip_crip                     : 2;  /**< Fuse information - Zip Cripple
+                                                         (O2P Only) */
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Enable (when blown '1') */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store. */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE) */
+	uint64_t icache                       : 24; /**< Fuse information - ICACHE Hard Repair Data */
+#else
+	uint64_t icache                       : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t zip_crip                     : 2;
+	uint64_t pll_div4                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_mio_fus_dat3_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t zip_crip                     : 2;  /**< Fuse information - Zip Cripple
+                                                         (PASS3 Only) */
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Enable (when blown '1')
+                                                         (PASS2 Only) */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown
+                                                         (PASS2 Only) */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store.
+                                                         (PASS2 Only) */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable
+                                                         (PASS2 Only) */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE)
+                                                         (PASS2 Only) */
+	uint64_t icache                       : 24; /**< Fuse information - ICACHE Hard Repair Data */
+#else
+	uint64_t icache                       : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t zip_crip                     : 2;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn38xx;
+	struct cvmx_mio_fus_dat3_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Enable (when blown '1')
+                                                         (PASS2 Only) */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown
+                                                         (PASS2 Only) */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store.
+                                                         (PASS2 Only) */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable
+                                                         (PASS2 Only) */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE)
+                                                         (PASS2 Only) */
+	uint64_t icache                       : 24; /**< Fuse information - ICACHE Hard Repair Data */
+#else
+	uint64_t icache                       : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn38xxp2;
+	struct cvmx_mio_fus_dat3_cn38xx       cn50xx;
+	struct cvmx_mio_fus_dat3_cn38xx       cn52xx;
+	struct cvmx_mio_fus_dat3_cn38xx       cn52xxp1;
+	struct cvmx_mio_fus_dat3_cn38xx       cn56xx;
+	struct cvmx_mio_fus_dat3_cn38xx       cn56xxp1;
+	struct cvmx_mio_fus_dat3_cn38xx       cn58xx;
+	struct cvmx_mio_fus_dat3_cn38xx       cn58xxp1;
+	struct cvmx_mio_fus_dat3_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t pll_ctl                      : 10; /**< Fuse information - PLL control */
+	uint64_t dfa_info_dte                 : 3;  /**< Fuse information - DFA information (DTE) */
+	uint64_t dfa_info_clm                 : 4;  /**< Fuse information - DFA information (Cluster mask) */
+	uint64_t reserved_40_40               : 1;
+	uint64_t ema                          : 2;  /**< Fuse information - EMA */
+	uint64_t efus_lck_rsv                 : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_lck_man                 : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t pll_half_dis                 : 1;  /**< Fuse information - RCLK PLL control */
+	uint64_t l2c_crip                     : 3;  /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t zip_info                     : 2;  /**< Fuse information - Zip information */
+	uint64_t bar2_en                      : 1;  /**< Fuse information - BAR2 Present (when blown '1') */
+	uint64_t efus_lck                     : 1;  /**< Fuse information - efuse lockdown */
+	uint64_t efus_ign                     : 1;  /**< Fuse information - efuse ignore */
+	uint64_t nozip                        : 1;  /**< Fuse information - ZIP disable */
+	uint64_t nodfa_dte                    : 1;  /**< Fuse information - DFA Disable (DTE) */
+	uint64_t reserved_0_23                : 24;
+#else
+	uint64_t reserved_0_23                : 24;
+	uint64_t nodfa_dte                    : 1;
+	uint64_t nozip                        : 1;
+	uint64_t efus_ign                     : 1;
+	uint64_t efus_lck                     : 1;
+	uint64_t bar2_en                      : 1;
+	uint64_t zip_info                     : 2;
+	uint64_t reserved_31_31               : 1;
+	uint64_t l2c_crip                     : 3;
+	uint64_t pll_half_dis                 : 1;
+	uint64_t efus_lck_man                 : 1;
+	uint64_t efus_lck_rsv                 : 1;
+	uint64_t ema                          : 2;
+	uint64_t reserved_40_40               : 1;
+	uint64_t dfa_info_clm                 : 4;
+	uint64_t dfa_info_dte                 : 3;
+	uint64_t pll_ctl                      : 10;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn63xx;
+	struct cvmx_mio_fus_dat3_cn63xx       cn63xxp1;
+};
+typedef union cvmx_mio_fus_dat3 cvmx_mio_fus_dat3_t;
+
+/**
+ * cvmx_mio_fus_ema
+ */
+union cvmx_mio_fus_ema
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_ema_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t eff_ema                      : 3;  /**< Reserved */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t ema                          : 3;  /**< Reserved */
+#else
+	uint64_t ema                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t eff_ema                      : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_fus_ema_s             cn50xx;
+	struct cvmx_mio_fus_ema_s             cn52xx;
+	struct cvmx_mio_fus_ema_s             cn52xxp1;
+	struct cvmx_mio_fus_ema_s             cn56xx;
+	struct cvmx_mio_fus_ema_s             cn56xxp1;
+	struct cvmx_mio_fus_ema_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t ema                          : 2;  /**< EMA Settings */
+#else
+	uint64_t ema                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn58xx;
+	struct cvmx_mio_fus_ema_cn58xx        cn58xxp1;
+	struct cvmx_mio_fus_ema_s             cn63xx;
+	struct cvmx_mio_fus_ema_s             cn63xxp1;
+};
+typedef union cvmx_mio_fus_ema cvmx_mio_fus_ema_t;
+
+/**
+ * cvmx_mio_fus_pdf
+ */
+union cvmx_mio_fus_pdf
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_pdf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pdf                          : 64; /**< Fuse information - Product Definition Field */
+#else
+	uint64_t pdf                          : 64;
+#endif
+	} s;
+	struct cvmx_mio_fus_pdf_s             cn50xx;
+	struct cvmx_mio_fus_pdf_s             cn52xx;
+	struct cvmx_mio_fus_pdf_s             cn52xxp1;
+	struct cvmx_mio_fus_pdf_s             cn56xx;
+	struct cvmx_mio_fus_pdf_s             cn56xxp1;
+	struct cvmx_mio_fus_pdf_s             cn58xx;
+	struct cvmx_mio_fus_pdf_s             cn63xx;
+	struct cvmx_mio_fus_pdf_s             cn63xxp1;
+};
+typedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t;
+
+/**
+ * cvmx_mio_fus_pll
+ *
+ * Notes:
+ * The core clkout postscaler should be placed in reset at least 10 ref clocks prior to changing
+ * the core clkout select.  The core clkout postscaler should remain under reset for at least 10
+ * ref clocks after the core clkout select changes.
+ *
+ * The pnr clkout postscaler should be placed in reset at least 10 ref clocks prior to changing
+ * the pnr clkout select.  The pnr clkout postscaler should remain under reset for at least 10
+ * ref clocks after the pnr clkout select changes.
+ */
+union cvmx_mio_fus_pll
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_pll_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t c_cout_rst                   : 1;  /**< Core clkout postscaler reset */
+	uint64_t c_cout_sel                   : 2;  /**< Core clkout select
+                                                         (0=RCLK,1=PS output,2=PLL output, 3=GND)         |   $PR */
+	uint64_t pnr_cout_rst                 : 1;  /**< PNR  clkout postscaler reset */
+	uint64_t pnr_cout_sel                 : 2;  /**< PNR  clkout select
+                                                         (0=SCLK,1=PS output,2=PLL output, 3=GND)         |   $PR */
+	uint64_t rfslip                       : 1;  /**< Reserved */
+	uint64_t fbslip                       : 1;  /**< Reserved */
+#else
+	uint64_t fbslip                       : 1;
+	uint64_t rfslip                       : 1;
+	uint64_t pnr_cout_sel                 : 2;
+	uint64_t pnr_cout_rst                 : 1;
+	uint64_t c_cout_sel                   : 2;
+	uint64_t c_cout_rst                   : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_fus_pll_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t rfslip                       : 1;  /**< PLL reference clock slip */
+	uint64_t fbslip                       : 1;  /**< PLL feedback clock slip */
+#else
+	uint64_t fbslip                       : 1;
+	uint64_t rfslip                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn50xx;
+	struct cvmx_mio_fus_pll_cn50xx        cn52xx;
+	struct cvmx_mio_fus_pll_cn50xx        cn52xxp1;
+	struct cvmx_mio_fus_pll_cn50xx        cn56xx;
+	struct cvmx_mio_fus_pll_cn50xx        cn56xxp1;
+	struct cvmx_mio_fus_pll_cn50xx        cn58xx;
+	struct cvmx_mio_fus_pll_cn50xx        cn58xxp1;
+	struct cvmx_mio_fus_pll_s             cn63xx;
+	struct cvmx_mio_fus_pll_s             cn63xxp1;
+};
+typedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t;
+
+/**
+ * cvmx_mio_fus_prog
+ *
+ * DON'T PUT IN HRM*
+ *
+ *
+ * Notes:
+ * This CSR is not present in the HRM.
+ *
+ * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be
+ * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which
+ * fuses to blow.  Once ADDR, and DAT are setup, SW can write to
+ * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG.  Once PROG is
+ * clear, the bank write is complete.
+ *
+ * A soft blow is still subject to lockdown fuses.  After a soft/warm reset, the
+ * chip will behave as though the fuses were actually blown.  A cold reset restores
+ * the actual fuse valuse.
+ */
+union cvmx_mio_fus_prog
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_prog_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t soft                         : 1;  /**< When set with PROG, causes only the local storeage
+                                                         to change.  Will not really blow any fuses.  HW
+                                                         will clear when the program operation is complete */
+	uint64_t prog                         : 1;  /**< Blow the fuse bank
+                                                         SW will set PROG, and then the HW will clear
+                                                         when the program operation is complete */
+#else
+	uint64_t prog                         : 1;
+	uint64_t soft                         : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_fus_prog_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t prog                         : 1;  /**< Blow the fuse
+                                                         SW will set PROG, hold it for 10us, then clear it */
+#else
+	uint64_t prog                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn30xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn31xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn38xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn38xxp2;
+	struct cvmx_mio_fus_prog_cn30xx       cn50xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn52xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn52xxp1;
+	struct cvmx_mio_fus_prog_cn30xx       cn56xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn56xxp1;
+	struct cvmx_mio_fus_prog_cn30xx       cn58xx;
+	struct cvmx_mio_fus_prog_cn30xx       cn58xxp1;
+	struct cvmx_mio_fus_prog_s            cn63xx;
+	struct cvmx_mio_fus_prog_s            cn63xxp1;
+};
+typedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t;
+
+/**
+ * cvmx_mio_fus_prog_times
+ *
+ * DON'T PUT IN HRM*
+ *
+ *
+ * Notes:
+ * This CSR is not present in the HRM.
+ *
+ * All values must be > 0 for correct electrical operation.
+ *
+ * IFB fuses are 0..1791
+ * L6G fuses are 1792 to 2047
+ *
+ * The reset values are for IFB fuses for ref_clk of 100MHZ
+ */
+union cvmx_mio_fus_prog_times
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_prog_times_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t vgate_pin                    : 1;  /**< efuse vgate pin (L6G) */
+	uint64_t fsrc_pin                     : 1;  /**< efuse fsource pin (L6G) */
+	uint64_t prog_pin                     : 1;  /**< efuse program pin (IFB) */
+	uint64_t reserved_6_31                : 26;
+	uint64_t setup                        : 6;  /**< efuse timing param
+
+                                                         SETUP = (tWRS/refclk period)-1
+
+                                                         For IFB: tWRS =  20ns
+                                                         For L6G: tWRS =  20ns */
+#else
+	uint64_t setup                        : 6;
+	uint64_t reserved_6_31                : 26;
+	uint64_t prog_pin                     : 1;
+	uint64_t fsrc_pin                     : 1;
+	uint64_t vgate_pin                    : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} s;
+	struct cvmx_mio_fus_prog_times_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t prog_pin                     : 1;  /**< efuse program pin */
+	uint64_t out                          : 8;  /**< efuse timing param (ref_clks to delay 10ns) */
+	uint64_t sclk_lo                      : 4;  /**< efuse timing param (ref_clks to delay 5ns) */
+	uint64_t sclk_hi                      : 12; /**< efuse timing param (ref_clks to delay 1000ns) */
+	uint64_t setup                        : 8;  /**< efuse timing param (ref_clks to delay 10ns) */
+#else
+	uint64_t setup                        : 8;
+	uint64_t sclk_hi                      : 12;
+	uint64_t sclk_lo                      : 4;
+	uint64_t out                          : 8;
+	uint64_t prog_pin                     : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} cn50xx;
+	struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
+	struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
+	struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
+	struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
+	struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
+	struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
+	struct cvmx_mio_fus_prog_times_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t vgate_pin                    : 1;  /**< efuse vgate pin (L6G) */
+	uint64_t fsrc_pin                     : 1;  /**< efuse fsource pin (L6G) */
+	uint64_t prog_pin                     : 1;  /**< efuse program pin (IFB) */
+	uint64_t out                          : 7;  /**< efuse timing param
+
+                                                         OUT = (tOUT/refclk period)-1
+
+                                                         For IFB: tOUT =  20ns
+                                                         For L6G: tOUT =  20ns */
+	uint64_t sclk_lo                      : 4;  /**< efuse timing param
+
+                                                         SCLK_LO=(tSLO/refclk period)-1
+
+                                                         For IFB: tSLO =  20ns
+                                                         For L6G: tSLO =  20ns */
+	uint64_t sclk_hi                      : 15; /**< efuse timing param
+                                                         ***NOTE: Pass 1.x reset value is 20000
+
+                                                         SCLK_HI=(tSHI/refclk period)-1
+
+                                                         For IFB: tSHI =  200us
+                                                         For L6G: tSHI =  25us */
+	uint64_t setup                        : 6;  /**< efuse timing param
+
+                                                         SETUP = (tWRS/refclk period)-1
+
+                                                         For IFB: tWRS =  20ns
+                                                         For L6G: tWRS =  20ns */
+#else
+	uint64_t setup                        : 6;
+	uint64_t sclk_hi                      : 15;
+	uint64_t sclk_lo                      : 4;
+	uint64_t out                          : 7;
+	uint64_t prog_pin                     : 1;
+	uint64_t fsrc_pin                     : 1;
+	uint64_t vgate_pin                    : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn63xx;
+	struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
+};
+typedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t;
+
+/**
+ * cvmx_mio_fus_rcmd
+ *
+ * Notes:
+ * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of
+ * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND].  When PEND is
+ * clear, then MIO_FUS_RCMD[DAT] is valid.  In addition, if the efuse read went
+ * to the efuse banks (eg. ((ADDR/16) not [0,1,7]) || EFUSE) SW can read
+ * MIO_FUS_BNK_DATX which contains all 128 fuses in the bank associated in
+ * ADDR.
+ */
+union cvmx_mio_fus_rcmd
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_rcmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t dat                          : 8;  /**< 8bits of fuse data */
+	uint64_t reserved_13_15               : 3;
+	uint64_t pend                         : 1;  /**< SW sets this bit on a write to start FUSE read
+                                                         operation.  HW clears when read is complete and
+                                                         the DAT is valid */
+	uint64_t reserved_9_11                : 3;
+	uint64_t efuse                        : 1;  /**< When set, return data from the efuse storage
+                                                         rather than the local storage */
+	uint64_t addr                         : 8;  /**< The byte address of the fuse to read */
+#else
+	uint64_t addr                         : 8;
+	uint64_t efuse                        : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pend                         : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t dat                          : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_mio_fus_rcmd_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t dat                          : 8;  /**< 8bits of fuse data */
+	uint64_t reserved_13_15               : 3;
+	uint64_t pend                         : 1;  /**< SW sets this bit on a write to start FUSE read
+                                                         operation.  HW clears when read is complete and
+                                                         the DAT is valid */
+	uint64_t reserved_9_11                : 3;
+	uint64_t efuse                        : 1;  /**< When set, return data from the efuse storage
+                                                         rather than the local storage for the 320 HW fuses */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t addr                         : 7;  /**< The byte address of the fuse to read */
+#else
+	uint64_t addr                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t efuse                        : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pend                         : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t dat                          : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn30xx;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn31xx;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn38xx;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn38xxp2;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn50xx;
+	struct cvmx_mio_fus_rcmd_s            cn52xx;
+	struct cvmx_mio_fus_rcmd_s            cn52xxp1;
+	struct cvmx_mio_fus_rcmd_s            cn56xx;
+	struct cvmx_mio_fus_rcmd_s            cn56xxp1;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn58xx;
+	struct cvmx_mio_fus_rcmd_cn30xx       cn58xxp1;
+	struct cvmx_mio_fus_rcmd_s            cn63xx;
+	struct cvmx_mio_fus_rcmd_s            cn63xxp1;
+};
+typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t;
+
+/**
+ * cvmx_mio_fus_read_times
+ *
+ * Notes:
+ * IFB fuses are 0..1791
+ * L6G fuses are 1792 to 2047
+ *
+ * The reset values are for IFB fuses for refclk up to 100MHZ when core PLL is enagaged
+ * The reset values are for IFB fuses for refclk up to 500MHZ when core PLL is not enagaged
+ *
+ * If any of the formulas above result in a value less than zero, the corresponding
+ * timing parameter should be set to zero.
+ *
+ * Prior to issuing a read to the fuse banks (via. MIO_FUS_RCMD), this register
+ * should be written with the timing parameters which correspond to the fuse bank type (IFB vs L6G)
+ * that will be read.
+ *
+ * This register should not be written while MIO_FUS_RCMD[PEND]=1.
+ */
+union cvmx_mio_fus_read_times
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_read_times_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t sch                          : 4;  /**< Hold CS for (SCH+1) refclks after FSET desserts
+
+                                                         SCH = (tSCH/refclk period)-1
+
+                                                         For IFB: tSCH = 160ns
+                                                         For L6G: tSCH =  10ns */
+	uint64_t fsh                          : 4;  /**< Hold FSET for (FSH+1) refclks after PRCHG deasserts
+
+                                                         FSH = (tFSH/refclk period)-1
+
+                                                         For IFB: tFSH = 160ns
+                                                         For L6G: tFSH =  10ns */
+	uint64_t prh                          : 4;  /**< Assert PRCHG (PRH+1) refclks after SIGDEV deasserts
+
+                                                         PRH = (tPRH/refclk period)-1
+
+                                                         For IFB: tPRH =  70ns
+                                                         For L6G: tPRH =  10ns */
+	uint64_t sdh                          : 4;  /**< Hold SIGDEV for (SDH+1) refclks after FSET asserts
+
+                                                         SDH = (tSDH/refclk period)-1
+
+                                                         For IFB: tPRH =  10ns
+                                                         For L6G: tPRH =  10ns */
+	uint64_t setup                        : 10; /**< Assert CS for (SETUP+1) refclks before asserting
+                                                         SIGDEV, FSET, or PRCHG
+
+                                                         SETUP=(tRDS/refclk period)-1
+
+                                                         For IFB: tRDS = 10000ns
+                                                         For L6G: tRDS = max(tSCS,tSDS,tPRS)
+                                                           where tSCS   = 10ns
+                                                                 tSDS   = 10ns
+                                                                 tPRS   = 10ns */
+#else
+	uint64_t setup                        : 10;
+	uint64_t sdh                          : 4;
+	uint64_t prh                          : 4;
+	uint64_t fsh                          : 4;
+	uint64_t sch                          : 4;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_mio_fus_read_times_s      cn63xx;
+	struct cvmx_mio_fus_read_times_s      cn63xxp1;
+};
+typedef union cvmx_mio_fus_read_times cvmx_mio_fus_read_times_t;
+
+/**
+ * cvmx_mio_fus_repair_res0
+ */
+union cvmx_mio_fus_repair_res0
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_repair_res0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_55_63               : 9;
+	uint64_t too_many                     : 1;  /**< Too many defects */
+	uint64_t repair2                      : 18; /**< BISR Results */
+	uint64_t repair1                      : 18; /**< BISR Results */
+	uint64_t repair0                      : 18; /**< BISR Results */
+#else
+	uint64_t repair0                      : 18;
+	uint64_t repair1                      : 18;
+	uint64_t repair2                      : 18;
+	uint64_t too_many                     : 1;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} s;
+	struct cvmx_mio_fus_repair_res0_s     cn63xx;
+	struct cvmx_mio_fus_repair_res0_s     cn63xxp1;
+};
+typedef union cvmx_mio_fus_repair_res0 cvmx_mio_fus_repair_res0_t;
+
+/**
+ * cvmx_mio_fus_repair_res1
+ */
+union cvmx_mio_fus_repair_res1
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_repair_res1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t repair5                      : 18; /**< BISR Results */
+	uint64_t repair4                      : 18; /**< BISR Results */
+	uint64_t repair3                      : 18; /**< BISR Results */
+#else
+	uint64_t repair3                      : 18;
+	uint64_t repair4                      : 18;
+	uint64_t repair5                      : 18;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_mio_fus_repair_res1_s     cn63xx;
+	struct cvmx_mio_fus_repair_res1_s     cn63xxp1;
+};
+typedef union cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res1_t;
+
+/**
+ * cvmx_mio_fus_repair_res2
+ */
+union cvmx_mio_fus_repair_res2
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_repair_res2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t repair6                      : 18; /**< BISR Results */
+#else
+	uint64_t repair6                      : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_mio_fus_repair_res2_s     cn63xx;
+	struct cvmx_mio_fus_repair_res2_s     cn63xxp1;
+};
+typedef union cvmx_mio_fus_repair_res2 cvmx_mio_fus_repair_res2_t;
+
+/**
+ * cvmx_mio_fus_spr_repair_res
+ *
+ * Notes:
+ * Pass3 Only
+ *
+ */
+union cvmx_mio_fus_spr_repair_res
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_spr_repair_res_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t repair2                      : 14; /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
+	uint64_t repair1                      : 14; /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
+	uint64_t repair0                      : 14; /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
+#else
+	uint64_t repair0                      : 14;
+	uint64_t repair1                      : 14;
+	uint64_t repair2                      : 14;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_mio_fus_spr_repair_res_s  cn30xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn31xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn38xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn50xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn52xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn52xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cn56xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn56xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cn58xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn58xxp1;
+	struct cvmx_mio_fus_spr_repair_res_s  cn63xx;
+	struct cvmx_mio_fus_spr_repair_res_s  cn63xxp1;
+};
+typedef union cvmx_mio_fus_spr_repair_res cvmx_mio_fus_spr_repair_res_t;
+
+/**
+ * cvmx_mio_fus_spr_repair_sum
+ *
+ * Notes:
+ * Pass3 Only
+ *
+ */
+union cvmx_mio_fus_spr_repair_sum
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_spr_repair_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t too_many                     : 1;  /**< Reserved (see  MIO_FUS_REPAIR_RES*) */
+#else
+	uint64_t too_many                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn30xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn31xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn38xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn50xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn52xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn52xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn56xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn56xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn58xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn58xxp1;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn63xx;
+	struct cvmx_mio_fus_spr_repair_sum_s  cn63xxp1;
+};
+typedef union cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_spr_repair_sum_t;
+
+/**
+ * cvmx_mio_fus_unlock
+ */
+union cvmx_mio_fus_unlock
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_unlock_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t key                          : 24; /**< When set to the typical value, allows SW to
+                                                         program the efuses */
+#else
+	uint64_t key                          : 24;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_mio_fus_unlock_s          cn30xx;
+	struct cvmx_mio_fus_unlock_s          cn31xx;
+};
+typedef union cvmx_mio_fus_unlock cvmx_mio_fus_unlock_t;
+
+/**
+ * cvmx_mio_fus_wadr
+ */
+union cvmx_mio_fus_wadr
+{
+	uint64_t u64;
+	struct cvmx_mio_fus_wadr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t addr                         : 10; /**< Which of the banks of 128 fuses to blow */
+#else
+	uint64_t addr                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_fus_wadr_s            cn30xx;
+	struct cvmx_mio_fus_wadr_s            cn31xx;
+	struct cvmx_mio_fus_wadr_s            cn38xx;
+	struct cvmx_mio_fus_wadr_s            cn38xxp2;
+	struct cvmx_mio_fus_wadr_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t addr                         : 2;  /**< Which of the four banks of 256 fuses to blow */
+#else
+	uint64_t addr                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn50xx;
+	struct cvmx_mio_fus_wadr_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t addr                         : 3;  /**< Which of the four banks of 256 fuses to blow */
+#else
+	uint64_t addr                         : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn52xx;
+	struct cvmx_mio_fus_wadr_cn52xx       cn52xxp1;
+	struct cvmx_mio_fus_wadr_cn52xx       cn56xx;
+	struct cvmx_mio_fus_wadr_cn52xx       cn56xxp1;
+	struct cvmx_mio_fus_wadr_cn50xx       cn58xx;
+	struct cvmx_mio_fus_wadr_cn50xx       cn58xxp1;
+	struct cvmx_mio_fus_wadr_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t addr                         : 4;  /**< Which of the banks of 128 fuses to blow */
+#else
+	uint64_t addr                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn63xx;
+	struct cvmx_mio_fus_wadr_cn63xx       cn63xxp1;
+};
+typedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t;
+
+/**
+ * cvmx_mio_gpio_comp
+ *
+ * MIO_GPIO_COMP = MIO GPIO Compensation Register
+ *
+ */
+union cvmx_mio_gpio_comp
+{
+	uint64_t u64;
+	struct cvmx_mio_gpio_comp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t pctl                         : 6;  /**< GPIO bus PCTL */
+	uint64_t nctl                         : 6;  /**< GPIO bus NCTL */
+#else
+	uint64_t nctl                         : 6;
+	uint64_t pctl                         : 6;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_mio_gpio_comp_s           cn63xx;
+	struct cvmx_mio_gpio_comp_s           cn63xxp1;
+};
+typedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t;
+
+/**
+ * cvmx_mio_ndf_dma_cfg
+ *
+ * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register
+ *
+ * SIZE is specified in number of 64 bit transfers (encoded in -1 notation).
+ *
+ * ADR must be 64 bit aligned.
+ */
+union cvmx_mio_ndf_dma_cfg
+{
+	uint64_t u64;
+	struct cvmx_mio_ndf_dma_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t en                           : 1;  /**< DMA Engine enable */
+	uint64_t rw                           : 1;  /**< DMA Engine R/W bit (0 = read, 1 = write) */
+	uint64_t clr                          : 1;  /**< DMA Engine clear EN on device terminated burst */
+	uint64_t reserved_60_60               : 1;
+	uint64_t swap32                       : 1;  /**< DMA Engine 32 bit swap */
+	uint64_t swap16                       : 1;  /**< DMA Engine 16 bit swap */
+	uint64_t swap8                        : 1;  /**< DMA Engine 8 bit swap */
+	uint64_t endian                       : 1;  /**< DMA Engine NCB endian mode (0 = big, 1 = little) */
+	uint64_t size                         : 20; /**< DMA Engine size */
+	uint64_t adr                          : 36; /**< DMA Engine address */
+#else
+	uint64_t adr                          : 36;
+	uint64_t size                         : 20;
+	uint64_t endian                       : 1;
+	uint64_t swap8                        : 1;
+	uint64_t swap16                       : 1;
+	uint64_t swap32                       : 1;
+	uint64_t reserved_60_60               : 1;
+	uint64_t clr                          : 1;
+	uint64_t rw                           : 1;
+	uint64_t en                           : 1;
+#endif
+	} s;
+	struct cvmx_mio_ndf_dma_cfg_s         cn52xx;
+	struct cvmx_mio_ndf_dma_cfg_s         cn63xx;
+	struct cvmx_mio_ndf_dma_cfg_s         cn63xxp1;
+};
+typedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t;
+
+/**
+ * cvmx_mio_ndf_dma_int
+ *
+ * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register
+ *
+ */
+union cvmx_mio_ndf_dma_int
+{
+	uint64_t u64;
+	struct cvmx_mio_ndf_dma_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t done                         : 1;  /**< DMA Engine request completion interrupt */
+#else
+	uint64_t done                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_ndf_dma_int_s         cn52xx;
+	struct cvmx_mio_ndf_dma_int_s         cn63xx;
+	struct cvmx_mio_ndf_dma_int_s         cn63xxp1;
+};
+typedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t;
+
+/**
+ * cvmx_mio_ndf_dma_int_en
+ *
+ * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register
+ *
+ */
+union cvmx_mio_ndf_dma_int_en
+{
+	uint64_t u64;
+	struct cvmx_mio_ndf_dma_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t done                         : 1;  /**< DMA Engine request completion interrupt enable */
+#else
+	uint64_t done                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_ndf_dma_int_en_s      cn52xx;
+	struct cvmx_mio_ndf_dma_int_en_s      cn63xx;
+	struct cvmx_mio_ndf_dma_int_en_s      cn63xxp1;
+};
+typedef union cvmx_mio_ndf_dma_int_en cvmx_mio_ndf_dma_int_en_t;
+
+/**
+ * cvmx_mio_pll_ctl
+ */
+union cvmx_mio_pll_ctl
+{
+	uint64_t u64;
+	struct cvmx_mio_pll_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
+#else
+	uint64_t bw_ctl                       : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_mio_pll_ctl_s             cn30xx;
+	struct cvmx_mio_pll_ctl_s             cn31xx;
+};
+typedef union cvmx_mio_pll_ctl cvmx_mio_pll_ctl_t;
+
+/**
+ * cvmx_mio_pll_setting
+ */
+union cvmx_mio_pll_setting
+{
+	uint64_t u64;
+	struct cvmx_mio_pll_setting_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t setting                      : 17; /**< Core PLL setting */
+#else
+	uint64_t setting                      : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_mio_pll_setting_s         cn30xx;
+	struct cvmx_mio_pll_setting_s         cn31xx;
+};
+typedef union cvmx_mio_pll_setting cvmx_mio_pll_setting_t;
+
+/**
+ * cvmx_mio_ptp_clock_cfg
+ *
+ * MIO_PTP_CLOCK_CFG = Configuration
+ *
+ */
+union cvmx_mio_ptp_clock_cfg
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_clock_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t evcnt_in                     : 6;  /**< Source for event counter input
+                                                         0x00-0x0f : GPIO[EVCNT_IN[3:0]]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x3f : Reserved */
+	uint64_t evcnt_edge                   : 1;  /**< Event counter input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t evcnt_en                     : 1;  /**< Enable event counter */
+	uint64_t tstmp_in                     : 6;  /**< Source for timestamp input
+                                                         0x00-0x0f : GPIO[TSTMP_IN[3:0]]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x3f : Reserved */
+	uint64_t tstmp_edge                   : 1;  /**< External timestamp input edge
+                                                         0 = falling edge
+                                                         1 = rising edge */
+	uint64_t tstmp_en                     : 1;  /**< Enable external timestamp */
+	uint64_t ext_clk_in                   : 6;  /**< Source for external clock
+                                                         0x00-0x0f : GPIO[EXT_CLK_IN[3:0]]
+                                                         0x10      : QLM0_REF_CLK
+                                                         0x11      : QLM1_REF_CLK
+                                                         0x12      : QLM2_REF_CLK
+                                                         0x13-0x3f : Reserved */
+	uint64_t ext_clk_en                   : 1;  /**< Use positive edge of external clock */
+	uint64_t ptp_en                       : 1;  /**< Enable PTP Module */
+#else
+	uint64_t ptp_en                       : 1;
+	uint64_t ext_clk_en                   : 1;
+	uint64_t ext_clk_in                   : 6;
+	uint64_t tstmp_en                     : 1;
+	uint64_t tstmp_edge                   : 1;
+	uint64_t tstmp_in                     : 6;
+	uint64_t evcnt_en                     : 1;
+	uint64_t evcnt_edge                   : 1;
+	uint64_t evcnt_in                     : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_mio_ptp_clock_cfg_s       cn63xx;
+	struct cvmx_mio_ptp_clock_cfg_s       cn63xxp1;
+};
+typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
+
+/**
+ * cvmx_mio_ptp_clock_comp
+ *
+ * MIO_PTP_CLOCK_COMP = Compensator
+ *
+ */
+union cvmx_mio_ptp_clock_comp
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_clock_comp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t nanosec                      : 32; /**< Nanoseconds */
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t nanosec                      : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_clock_comp_s      cn63xx;
+	struct cvmx_mio_ptp_clock_comp_s      cn63xxp1;
+};
+typedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t;
+
+/**
+ * cvmx_mio_ptp_clock_hi
+ *
+ * MIO_PTP_CLOCK_HI = Hi bytes of CLOCK
+ *
+ * Writes to MIO_PTP_CLOCK_HI also clear MIO_PTP_CLOCK_LO. To update all 96 bits, write MIO_PTP_CLOCK_HI followed
+ * by MIO_PTP_CLOCK_LO
+ */
+union cvmx_mio_ptp_clock_hi
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_clock_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t nanosec                      : 64; /**< Nanoseconds */
+#else
+	uint64_t nanosec                      : 64;
+#endif
+	} s;
+	struct cvmx_mio_ptp_clock_hi_s        cn63xx;
+	struct cvmx_mio_ptp_clock_hi_s        cn63xxp1;
+};
+typedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t;
+
+/**
+ * cvmx_mio_ptp_clock_lo
+ *
+ * MIO_PTP_CLOCK_LO = Lo bytes of CLOCK
+ *
+ */
+union cvmx_mio_ptp_clock_lo
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_clock_lo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t frnanosec                    : 32; /**< Fractions of Nanoseconds */
+#else
+	uint64_t frnanosec                    : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_ptp_clock_lo_s        cn63xx;
+	struct cvmx_mio_ptp_clock_lo_s        cn63xxp1;
+};
+typedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t;
+
+/**
+ * cvmx_mio_ptp_evt_cnt
+ *
+ * MIO_PTP_EVT_CNT = Event Counter
+ *
+ * Writes to MIO_PTP_EVT_CNT increment this register by the written data. The register counts down by
+ * 1 for every MIO_PTP_CLOCK_CFG[EVCNT_EDGE] edge of MIO_PTP_CLOCK_CFG[EVCNT_IN]. When register equals
+ * 0, an interrupt gets gerated
+ */
+union cvmx_mio_ptp_evt_cnt
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_evt_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cntr                         : 64; /**< Nanoseconds */
+#else
+	uint64_t cntr                         : 64;
+#endif
+	} s;
+	struct cvmx_mio_ptp_evt_cnt_s         cn63xx;
+	struct cvmx_mio_ptp_evt_cnt_s         cn63xxp1;
+};
+typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t;
+
+/**
+ * cvmx_mio_ptp_timestamp
+ *
+ * MIO_PTP_TIMESTAMP = Timestamp latched on MIO_PTP_CLOCK_CFG[TSTMP_EDGE] edge of MIO_PTP_CLOCK_CFG[TSTMP_IN]
+ *
+ */
+union cvmx_mio_ptp_timestamp
+{
+	uint64_t u64;
+	struct cvmx_mio_ptp_timestamp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t nanosec                      : 64; /**< Nanoseconds */
+#else
+	uint64_t nanosec                      : 64;
+#endif
+	} s;
+	struct cvmx_mio_ptp_timestamp_s       cn63xx;
+	struct cvmx_mio_ptp_timestamp_s       cn63xxp1;
+};
+typedef union cvmx_mio_ptp_timestamp cvmx_mio_ptp_timestamp_t;
+
+/**
+ * cvmx_mio_rst_boot
+ */
+union cvmx_mio_rst_boot
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_boot_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t c_mul                        : 6;  /**< Core clock multiplier:
+                                                           C_MUL = (core clk speed) / (ref clock speed)
+                                                         "ref clock speed" should always be 50MHz.
+                                                         If PLL_QLM_REF_CLK_EN=0, "ref clock" comes
+                                                              from PLL_REF_CLK pin.
+                                                         If PLL_QLM_REF_CLK_EN=1, "ref clock" is
+                                                              1/2 speed of QLMC_REF_CLK_* pins. */
+	uint64_t pnr_mul                      : 6;  /**< Coprocessor clock multiplier:
+                                                           PNR_MUL = (coprocessor clk speed) /
+                                                                           (ref clock speed)
+                                                         See C_MUL comments about ref clock. */
+	uint64_t qlm2_spd                     : 4;  /**< QLM2_SPD pins sampled at DCOK assertion */
+	uint64_t qlm1_spd                     : 4;  /**< QLM1_SPD pins sampled at DCOK assertion */
+	uint64_t qlm0_spd                     : 4;  /**< QLM0_SPD pins sampled at DCOK assertion */
+	uint64_t lboot                        : 10; /**< Last boot cause mask, resets only with dock.
+
+                                                         bit9 - Soft reset due to watchdog
+                                                         bit8 - Soft reset due to CIU_SOFT_RST write
+                                                         bit7 - Warm reset due to cntl0 link-down or
+                                                                hot-reset
+                                                         bit6 - Warm reset due to cntl1 link-down or
+                                                                hot-reset
+                                                         bit5 - Cntl1 reset due to PERST1_L pin
+                                                         bit4 - Cntl0 reset due to PERST0_L pin
+                                                         bit3 - Warm reset due to PERST1_L pin
+                                                         bit2 - Warm reset due to PERST0_L pin
+                                                         bit1 - Warm reset due to CHIP_RESET_L pin
+                                                         bit0 - Cold reset due to DCOK pin */
+	uint64_t rboot                        : 1;  /**< Determines whether core 0 remains in reset after
+                                                         after chip cold/warm/soft reset. */
+	uint64_t rboot_pin                    : 1;  /**< Read-only access to REMOTE_BOOT pin */
+#else
+	uint64_t rboot_pin                    : 1;
+	uint64_t rboot                        : 1;
+	uint64_t lboot                        : 10;
+	uint64_t qlm0_spd                     : 4;
+	uint64_t qlm1_spd                     : 4;
+	uint64_t qlm2_spd                     : 4;
+	uint64_t pnr_mul                      : 6;
+	uint64_t c_mul                        : 6;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_mio_rst_boot_s            cn63xx;
+	struct cvmx_mio_rst_boot_s            cn63xxp1;
+};
+typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;
+
+/**
+ * cvmx_mio_rst_cfg
+ *
+ * Notes:
+ * Cold reset will always performs a full bist.
+ *
+ */
+union cvmx_mio_rst_cfg
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bist_delay                   : 58; /**< Reserved */
+	uint64_t reserved_3_5                 : 3;
+	uint64_t cntl_clr_bist                : 1;  /**< Peform clear bist during cntl only reset,
+                                                         instead of a full bist. A warm/soft reset will
+                                                         not change this field. */
+	uint64_t warm_clr_bist                : 1;  /**< Peform clear bist during warm reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+	uint64_t soft_clr_bist                : 1;  /**< Peform clear bist during soft reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+#else
+	uint64_t soft_clr_bist                : 1;
+	uint64_t warm_clr_bist                : 1;
+	uint64_t cntl_clr_bist                : 1;
+	uint64_t reserved_3_5                 : 3;
+	uint64_t bist_delay                   : 58;
+#endif
+	} s;
+	struct cvmx_mio_rst_cfg_s             cn63xx;
+	struct cvmx_mio_rst_cfg_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bist_delay                   : 58; /**< Reserved */
+	uint64_t reserved_2_5                 : 4;
+	uint64_t warm_clr_bist                : 1;  /**< Peform clear bist during warm reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+	uint64_t soft_clr_bist                : 1;  /**< Peform clear bist during soft reset, instead
+                                                         of a full bist. A warm/soft reset will not
+                                                         change this field. */
+#else
+	uint64_t soft_clr_bist                : 1;
+	uint64_t warm_clr_bist                : 1;
+	uint64_t reserved_2_5                 : 4;
+	uint64_t bist_delay                   : 58;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_mio_rst_cfg cvmx_mio_rst_cfg_t;
+
+/**
+ * cvmx_mio_rst_ctl#
+ */
+union cvmx_mio_rst_ctlx
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_ctlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t prst_link                    : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes the assertion of
+                                                         CIU_SOFT_PRST*[SOFT_PRST]
+
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=1
+                                                            1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         ***NOTE: Added in pass 2.0 */
+	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
+
+                                                         RESET_DONE is always zero (i.e. the controller
+                                                         is held in reset) when:
+                                                           - CIU_SOFT_PRST*[SOFT_PRST]=1, or
+                                                           - RST_RCV==1 and PERST*_L pin is asserted */
+	uint64_t rst_link                     : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes a warm chip reset
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=1
+                                                            1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         Note that a link-down or hot-reset event can
+                                                         never cause a warm chip reset when the
+                                                         controller is in reset (i.e. can never cause a
+                                                         warm reset when RST_DONE==0). */
+	uint64_t host_mode                    : 1;  /**< RO access to corresponding strap QLM*_HOST_MODE */
+	uint64_t prtmode                      : 2;  /**< Port mode
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                            2,3 = Reserved
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=0
+                                                            1 = when corresponding strap QLM*_HOST_MODE=1 */
+	uint64_t rst_drv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is driven by the OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding strap QLM*_HOST_MODE=0
+                                                          1 = when corresponding strap QLM*_HOST_MODE=1
+
+                                                         When set, OCTEON drives the corresponding
+                                                         PERST*_L pin. Otherwise, OCTEON does not drive
+                                                         the corresponding PERST*_L pin. */
+	uint64_t rst_rcv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is recieved by OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding strap QLM*_HOST_MODE=1
+                                                          1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         When RST_RCV==1, the PERST*_L value is
+                                                         received and may be used to reset the
+                                                         controller and (optionally, based on RST_CHIP)
+                                                         warm reset the chip.
+
+                                                         When RST_RCV==1 (and RST_CHIP=0),
+                                                         MIO_RST_INT[PERST*] gets set when the PERST*_L
+                                                         pin asserts. (This interrupt can alert SW
+                                                         whenever the external reset pin initiates a
+                                                         controller reset sequence.)
+
+                                                         RST_VAL gives the PERST*_L pin value when
+                                                         RST_RCV==1.
+
+                                                         When RST_RCV==0, the PERST*_L pin value is
+                                                         ignored. */
+	uint64_t rst_chip                     : 1;  /**< Controls whether corresponding PERST*_L chip
+                                                         pin causes a chip warm reset like CHIP_RESET_L.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0.
+
+                                                         RST_CHIP is not used when RST_RCV==0.
+
+                                                         When RST_RCV==0, RST_CHIP is ignored.
+
+                                                         When RST_RCV==1, RST_CHIP==1, and PERST*_L
+                                                         asserts, a chip warm reset will be generated. */
+	uint64_t rst_val                      : 1;  /**< Read-only access to corresponding PERST*_L pin
+                                                         Unpredictable when RST_RCV==0. Reads as 1 when
+                                                         RST_RCV==1 and the PERST*_L pin is asserted.
+                                                         Reads as 0 when RST_RCV==1 and the PERST*_L
+                                                         pin is not asserted. */
+#else
+	uint64_t rst_val                      : 1;
+	uint64_t rst_chip                     : 1;
+	uint64_t rst_rcv                      : 1;
+	uint64_t rst_drv                      : 1;
+	uint64_t prtmode                      : 2;
+	uint64_t host_mode                    : 1;
+	uint64_t rst_link                     : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t prst_link                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_rst_ctlx_s            cn63xx;
+	struct cvmx_mio_rst_ctlx_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t rst_done                     : 1;  /**< Read-only access to controller reset status
+
+                                                         RESET_DONE is always zero (i.e. the controller
+                                                         is held in reset) when:
+                                                           - CIU_SOFT_PRST*[SOFT_PRST]=1, or
+                                                           - RST_RCV==1 and PERST*_L pin is asserted */
+	uint64_t rst_link                     : 1;  /**< Controls whether corresponding controller
+                                                         link-down or hot-reset causes a warm chip reset
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=1
+                                                            1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         Note that a link-down or hot-reset event can
+                                                         never cause a warm chip reset when the
+                                                         controller is in reset (i.e. can never cause a
+                                                         warm reset when RST_DONE==0). */
+	uint64_t host_mode                    : 1;  /**< RO access to corresponding strap QLM*_HOST_MODE */
+	uint64_t prtmode                      : 2;  /**< Port mode
+                                                            0 = port is EP mode
+                                                            1 = port is RC mode
+                                                            2,3 = Reserved
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized as
+                                                         follows:
+                                                            0 = when corresponding strap QLM*_HOST_MODE=0
+                                                            1 = when corresponding strap QLM*_HOST_MODE=1 */
+	uint64_t rst_drv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is driven by the OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding strap QLM*_HOST_MODE=0
+                                                          1 = when corresponding strap QLM*_HOST_MODE=1
+
+                                                         When set, OCTEON drives the corresponding
+                                                         PERST*_L pin. Otherwise, OCTEON does not drive
+                                                         the corresponding PERST*_L pin. */
+	uint64_t rst_rcv                      : 1;  /**< Controls whether corresponding PERST*_L chip pin
+                                                         is recieved by OCTEON.  A warm/soft reset
+                                                         will not change this field.  On cold reset,
+                                                         this field is initialized as follows:
+                                                          0 = when corresponding strap QLM*_HOST_MODE=1
+                                                          1 = when corresponding strap QLM*_HOST_MODE=0
+
+                                                         When RST_RCV==1, the PERST*_L value is
+                                                         received and may be used to reset the
+                                                         controller and (optionally, based on RST_CHIP)
+                                                         warm reset the chip.
+
+                                                         When RST_RCV==1 (and RST_CHIP=0),
+                                                         MIO_RST_INT[PERST*] gets set when the PERST*_L
+                                                         pin asserts. (This interrupt can alert SW
+                                                         whenever the external reset pin initiates a
+                                                         controller reset sequence.)
+
+                                                         RST_VAL gives the PERST*_L pin value when
+                                                         RST_RCV==1.
+
+                                                         When RST_RCV==0, the PERST*_L pin value is
+                                                         ignored. */
+	uint64_t rst_chip                     : 1;  /**< Controls whether corresponding PERST*_L chip
+                                                         pin causes a chip warm reset like CHIP_RESET_L.
+                                                         A warm/soft reset will not change this field.
+                                                         On cold reset, this field is initialized to 0.
+
+                                                         RST_CHIP is not used when RST_RCV==0.
+
+                                                         When RST_RCV==0, RST_CHIP is ignored.
+
+                                                         When RST_RCV==1, RST_CHIP==1, and PERST*_L
+                                                         asserts, a chip warm reset will be generated. */
+	uint64_t rst_val                      : 1;  /**< Read-only access to corresponding PERST*_L pin
+                                                         Unpredictable when RST_RCV==0. Reads as 1 when
+                                                         RST_RCV==1 and the PERST*_L pin is asserted.
+                                                         Reads as 0 when RST_RCV==1 and the PERST*_L
+                                                         pin is not asserted. */
+#else
+	uint64_t rst_val                      : 1;
+	uint64_t rst_chip                     : 1;
+	uint64_t rst_rcv                      : 1;
+	uint64_t rst_drv                      : 1;
+	uint64_t prtmode                      : 2;
+	uint64_t host_mode                    : 1;
+	uint64_t rst_link                     : 1;
+	uint64_t rst_done                     : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t;
+
+/**
+ * cvmx_mio_rst_delay
+ */
+union cvmx_mio_rst_delay
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_delay_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t soft_rst_dly                 : 16; /**< A soft reset immediately causes an early soft
+                                                         reset notification.  However, the assertion of
+                                                         soft reset will be delayed this many sclks.
+                                                         A warm/soft reset will not change this field.
+                                                         NOTE: This must be at least 500 dclks */
+	uint64_t warm_rst_dly                 : 16; /**< A warm reset immediately causes an early warm
+                                                         reset notification.  However, the assertion of
+                                                         warm reset will be delayed this many sclks.
+                                                         A warm/soft reset will not change this field.
+                                                         NOTE: This must be at least 500 dclks */
+#else
+	uint64_t warm_rst_dly                 : 16;
+	uint64_t soft_rst_dly                 : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_mio_rst_delay_s           cn63xx;
+	struct cvmx_mio_rst_delay_s           cn63xxp1;
+};
+typedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t;
+
+/**
+ * cvmx_mio_rst_int
+ *
+ * MIO_RST_INT = MIO Reset Interrupt Register
+ *
+ */
+union cvmx_mio_rst_int
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t perst1                       : 1;  /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1
+                                                         and MIO_RST_CTL1[RST_CHIP]=0 */
+	uint64_t perst0                       : 1;  /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1
+                                                         and MIO_RST_CTL0[RST_CHIP]=0 */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t rst_link1                    : 1;  /**< A controller1 link-down/hot-reset occurred while
+                                                         MIO_RST_CTL1[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST1[SOFT_PRST] */
+	uint64_t rst_link0                    : 1;  /**< A controller0 link-down/hot-reset occurred while
+                                                         MIO_RST_CTL0[RST_LINK]=0.  Software must assert
+                                                         then de-assert CIU_SOFT_PRST[SOFT_PRST] */
+#else
+	uint64_t rst_link0                    : 1;
+	uint64_t rst_link1                    : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t perst0                       : 1;
+	uint64_t perst1                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_rst_int_s             cn63xx;
+	struct cvmx_mio_rst_int_s             cn63xxp1;
+};
+typedef union cvmx_mio_rst_int cvmx_mio_rst_int_t;
+
+/**
+ * cvmx_mio_rst_int_en
+ *
+ * MIO_RST_INT_EN = MIO Reset Interrupt Enable Register
+ *
+ */
+union cvmx_mio_rst_int_en
+{
+	uint64_t u64;
+	struct cvmx_mio_rst_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t perst1                       : 1;  /**< Controller1 PERST reset interrupt enable */
+	uint64_t perst0                       : 1;  /**< Controller0 PERST reset interrupt enable */
+	uint64_t reserved_2_7                 : 6;
+	uint64_t rst_link1                    : 1;  /**< Controller1 link-down/hot reset interrupt enable */
+	uint64_t rst_link0                    : 1;  /**< Controller0 link-down/hot reset interrupt enable */
+#else
+	uint64_t rst_link0                    : 1;
+	uint64_t rst_link1                    : 1;
+	uint64_t reserved_2_7                 : 6;
+	uint64_t perst0                       : 1;
+	uint64_t perst1                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_rst_int_en_s          cn63xx;
+	struct cvmx_mio_rst_int_en_s          cn63xxp1;
+};
+typedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t;
+
+/**
+ * cvmx_mio_tws#_int
+ *
+ * MIO_TWSX_INT = TWSX Interrupt Register
+ *
+ * This register contains the TWSI interrupt enable mask and the interrupt source bits.  Note: the
+ * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence
+ * must be written to the TWSI core to clear this interrupt.  The other interrupt source bits are write-
+ * one-to-clear.  TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written
+ * by a TWSI device).  ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above
+ * for reasons).
+ *
+ * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored.
+ * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT /
+ * TS_INT should be ignored.
+ *
+ * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to
+ * override the current state of the TWSI bus (SCL_OVR and SDA_OVR).  Setting an override bit high will
+ * result in the open drain driver being activated, thus driving the corresponding signal low.
+ */
+union cvmx_mio_twsx_int
+{
+	uint64_t u64;
+	struct cvmx_mio_twsx_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t scl                          : 1;  /**< SCL */
+	uint64_t sda                          : 1;  /**< SDA */
+	uint64_t scl_ovr                      : 1;  /**< SCL override */
+	uint64_t sda_ovr                      : 1;  /**< SDA override */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t core_en                      : 1;  /**< TWSI core interrupt enable */
+	uint64_t ts_en                        : 1;  /**< MIO_TWS_TWSI_SW register update interrupt enable */
+	uint64_t st_en                        : 1;  /**< MIO_TWS_SW_TWSI register update interrupt enable */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t core_int                     : 1;  /**< TWSI core interrupt */
+	uint64_t ts_int                       : 1;  /**< MIO_TWS_TWSI_SW register update interrupt */
+	uint64_t st_int                       : 1;  /**< MIO_TWS_SW_TWSI register update interrupt */
+#else
+	uint64_t st_int                       : 1;
+	uint64_t ts_int                       : 1;
+	uint64_t core_int                     : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t st_en                        : 1;
+	uint64_t ts_en                        : 1;
+	uint64_t core_en                      : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t sda_ovr                      : 1;
+	uint64_t scl_ovr                      : 1;
+	uint64_t sda                          : 1;
+	uint64_t scl                          : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_mio_twsx_int_s            cn30xx;
+	struct cvmx_mio_twsx_int_s            cn31xx;
+	struct cvmx_mio_twsx_int_s            cn38xx;
+	struct cvmx_mio_twsx_int_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t core_en                      : 1;  /**< TWSI core interrupt enable */
+	uint64_t ts_en                        : 1;  /**< MIO_TWS_TWSI_SW register update interrupt enable */
+	uint64_t st_en                        : 1;  /**< MIO_TWS_SW_TWSI register update interrupt enable */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t core_int                     : 1;  /**< TWSI core interrupt */
+	uint64_t ts_int                       : 1;  /**< MIO_TWS_TWSI_SW register update interrupt */
+	uint64_t st_int                       : 1;  /**< MIO_TWS_SW_TWSI register update interrupt */
+#else
+	uint64_t st_int                       : 1;
+	uint64_t ts_int                       : 1;
+	uint64_t core_int                     : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t st_en                        : 1;
+	uint64_t ts_en                        : 1;
+	uint64_t core_en                      : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn38xxp2;
+	struct cvmx_mio_twsx_int_s            cn50xx;
+	struct cvmx_mio_twsx_int_s            cn52xx;
+	struct cvmx_mio_twsx_int_s            cn52xxp1;
+	struct cvmx_mio_twsx_int_s            cn56xx;
+	struct cvmx_mio_twsx_int_s            cn56xxp1;
+	struct cvmx_mio_twsx_int_s            cn58xx;
+	struct cvmx_mio_twsx_int_s            cn58xxp1;
+	struct cvmx_mio_twsx_int_s            cn63xx;
+	struct cvmx_mio_twsx_int_s            cn63xxp1;
+};
+typedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t;
+
+/**
+ * cvmx_mio_tws#_sw_twsi
+ *
+ * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register
+ *
+ * This register allows software to
+ *    - initiate TWSI interface master-mode operations with a write and read the result with a read
+ *    - load four bytes for later retrieval (slave mode) with a write and check validity with a read
+ *    - launch a TWSI controller configuration read/write with a write and read the result with a read
+ *
+ * This register should be read or written by software, and read by the TWSI device. The TWSI device can
+ * use either two-byte or five-byte reads to reference this register.
+ *
+ * The TWSI device considers this register valid when V==1 and SLONLY==1.
+ */
+union cvmx_mio_twsx_sw_twsi
+{
+	uint64_t u64;
+	struct cvmx_mio_twsx_sw_twsi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t v                            : 1;  /**< Valid bit
+                                                         - Set on a write (should always be written with
+                                                           a 1)
+                                                         - Cleared when a TWSI master mode op completes
+                                                         - Cleared when a TWSI configuration register
+                                                           access completes
+                                                         - Cleared when the TWSI device reads the
+                                                           register if SLONLY==1 */
+	uint64_t slonly                       : 1;  /**< Slave Only Mode
+                                                         - No operation is initiated with a write when
+                                                           this bit is set - only D field is updated in
+                                                           this case
+                                                         - When clear, a write initiates either a TWSI
+                                                           master-mode operation or a TWSI configuration
+                                                           register access */
+	uint64_t eia                          : 1;  /**< Extended Internal Address - send additional
+                                                         internal address byte (MSB of IA is from IA field
+                                                         of MIO_TWS_SW_TWSI_EXT) */
+	uint64_t op                           : 4;  /**< Opcode field - When the register is written with
+                                                         SLONLY==0, initiate a read or write:
+                                                           0000 => 7-bit Byte Master Mode TWSI Op
+                                                           0001 => 7-bit Byte Combined Read Master Mode Op
+                                                                   7-bit Byte Write w/ IA Master Mode Op
+                                                           0010 => 10-bit Byte Master Mode TWSI Op
+                                                           0011 => 10-bit Byte Combined Read Master Mode Op
+                                                                   10-bit Byte Write w/ IA Master Mode Op
+                                                           0100 => TWSI Master Clock Register
+                                                           0110 => See EOP field
+                                                           1000 => 7-bit 4-byte Master Mode TWSI Op
+                                                           1001 => 7-bit 4-byte Comb. Read Master Mode Op
+                                                                   7-bit 4-byte Write w/ IA Master Mode Op
+                                                           1010 => 10-bit 4-byte Master Mode TWSI Op
+                                                           1011 => 10-bit 4-byte Comb. Read Master Mode Op
+                                                                   10-bit 4-byte Write w/ IA Master Mode Op */
+	uint64_t r                            : 1;  /**< Read bit or result
+                                                         - If set on a write when SLONLY==0, the
+                                                           operation is a read
+                                                         - On a read, this bit returns the result
+                                                           indication for the most recent master mode
+                                                           operation (1 = success, 0 = fail) */
+	uint64_t sovr                         : 1;  /**< Size Override - if set, use the SIZE field to
+                                                         determine Master Mode Op size rather than what
+                                                         the Opcode field specifies.  For operations
+                                                         greater than 4 bytes, the additional data will be
+                                                         contained in the D field of MIO_TWS_SW_TWSI_EXT */
+	uint64_t size                         : 3;  /**< Size in bytes of Master Mode Op if the Size
+                                                         Override bit is set.  Specified in -1 notation
+                                                         (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes) */
+	uint64_t scr                          : 2;  /**< Scratch - unused, but retain state */
+	uint64_t a                            : 10; /**< Address field
+                                                          - the address of the remote device for a master
+                                                            mode operation
+                                                          - A<9:7> are only used for 10-bit addressing
+                                                         Note that when mastering a 7-bit OP, A<6:0> should
+                                                         not take any of the values 0x78, 0x79, 0x7A nor
+                                                         0x7B (these 7-bit addresses are reserved to
+                                                         extend to 10-bit addressing). */
+	uint64_t ia                           : 5;  /**< Internal Address - Used when launching a master
+                                                         mode combined read / write with internal address
+                                                         (lower 3 bits are contained in the EOP_IA field) */
+	uint64_t eop_ia                       : 3;  /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0):
+                                                           000 => TWSI Slave Address Register
+                                                           001 => TWSI Data Register
+                                                           010 => TWSI Control Register
+                                                           011 => TWSI Clock Control Register (when R == 0)
+                                                           011 => TWSI Status Register (when R == 1)
+                                                           100 => TWSI Extended Slave Register
+                                                           111 => TWSI Soft Reset Register
+                                                         Also the lower 3 bits of Internal Address when
+                                                           launching a master mode combined read / write
+                                                           with internal address */
+	uint64_t d                            : 32; /**< Data Field
+                                                         Used on a write when
+                                                           - initiating a master-mode write (SLONLY==0)
+                                                           - writing a TWSI config register (SLONLY==0)
+                                                           - a slave mode write (SLONLY==1)
+                                                         The read value is updated by
+                                                           - a write to this register
+                                                           - master mode completion (contains result or
+                                                             error code)
+                                                           - TWSI config register read (contains result) */
+#else
+	uint64_t d                            : 32;
+	uint64_t eop_ia                       : 3;
+	uint64_t ia                           : 5;
+	uint64_t a                            : 10;
+	uint64_t scr                          : 2;
+	uint64_t size                         : 3;
+	uint64_t sovr                         : 1;
+	uint64_t r                            : 1;
+	uint64_t op                           : 4;
+	uint64_t eia                          : 1;
+	uint64_t slonly                       : 1;
+	uint64_t v                            : 1;
+#endif
+	} s;
+	struct cvmx_mio_twsx_sw_twsi_s        cn30xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn31xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn38xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn38xxp2;
+	struct cvmx_mio_twsx_sw_twsi_s        cn50xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn52xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn52xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cn56xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn56xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cn58xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn58xxp1;
+	struct cvmx_mio_twsx_sw_twsi_s        cn63xx;
+	struct cvmx_mio_twsx_sw_twsi_s        cn63xxp1;
+};
+typedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t;
+
+/**
+ * cvmx_mio_tws#_sw_twsi_ext
+ *
+ * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register
+ *
+ * This register contains an additional byte of internal address and 4 additional bytes of data to be
+ * used with TWSI master mode operations.  IA will be sent as the first byte of internal address when
+ * performing master mode combined read / write with internal address operations and the EIA bit of
+ * MIO_TWS_SW_TWSI is set.  D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR
+ * must be set to perform operations greater than 4 bytes).
+ */
+union cvmx_mio_twsx_sw_twsi_ext
+{
+	uint64_t u64;
+	struct cvmx_mio_twsx_sw_twsi_ext_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ia                           : 8;  /**< Extended Internal Address */
+	uint64_t d                            : 32; /**< Extended Data Field */
+#else
+	uint64_t d                            : 32;
+	uint64_t ia                           : 8;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn30xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn31xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn38xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn38xxp2;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn50xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn52xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn52xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn56xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn56xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn58xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn58xxp1;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn63xx;
+	struct cvmx_mio_twsx_sw_twsi_ext_s    cn63xxp1;
+};
+typedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t;
+
+/**
+ * cvmx_mio_tws#_twsi_sw
+ *
+ * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register
+ *
+ * This register allows the TWSI device to transfer data to software and later check that software has
+ * received the information.
+ *
+ * This register should be read or written by the TWSI device, and read by software. The TWSI device can
+ * use one-byte or four-byte payload writes, and two-byte payload reads.
+ *
+ * The TWSI device considers this register valid when V==1.
+ */
+union cvmx_mio_twsx_twsi_sw
+{
+	uint64_t u64;
+	struct cvmx_mio_twsx_twsi_sw_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t v                            : 2;  /**< Valid Bits
+                                                         - Not directly writable
+                                                         - Set to 1 on any write by the TWSI device
+                                                         - Cleared on any read by software */
+	uint64_t reserved_32_61               : 30;
+	uint64_t d                            : 32; /**< Data Field - updated on a write by the TWSI device */
+#else
+	uint64_t d                            : 32;
+	uint64_t reserved_32_61               : 30;
+	uint64_t v                            : 2;
+#endif
+	} s;
+	struct cvmx_mio_twsx_twsi_sw_s        cn30xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn31xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn38xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn38xxp2;
+	struct cvmx_mio_twsx_twsi_sw_s        cn50xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn52xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn52xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cn56xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn56xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cn58xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn58xxp1;
+	struct cvmx_mio_twsx_twsi_sw_s        cn63xx;
+	struct cvmx_mio_twsx_twsi_sw_s        cn63xxp1;
+};
+typedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t;
+
+/**
+ * cvmx_mio_uart#_dlh
+ *
+ * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register
+ *
+ * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
+ * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
+ * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
+ * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
+ * follows: baud rate = eclk / (16 * divisor).
+ *
+ * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
+ * register. BUSY bit is always clear in PASS3.
+ *
+ * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
+ * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
+ * of eclk should be allowed to pass before transmitting or receiving data.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IER and DLH registers are the same.
+ */
+union cvmx_mio_uartx_dlh
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_dlh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dlh                          : 8;  /**< Divisor Latch High Register */
+#else
+	uint64_t dlh                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_dlh_s           cn30xx;
+	struct cvmx_mio_uartx_dlh_s           cn31xx;
+	struct cvmx_mio_uartx_dlh_s           cn38xx;
+	struct cvmx_mio_uartx_dlh_s           cn38xxp2;
+	struct cvmx_mio_uartx_dlh_s           cn50xx;
+	struct cvmx_mio_uartx_dlh_s           cn52xx;
+	struct cvmx_mio_uartx_dlh_s           cn52xxp1;
+	struct cvmx_mio_uartx_dlh_s           cn56xx;
+	struct cvmx_mio_uartx_dlh_s           cn56xxp1;
+	struct cvmx_mio_uartx_dlh_s           cn58xx;
+	struct cvmx_mio_uartx_dlh_s           cn58xxp1;
+	struct cvmx_mio_uartx_dlh_s           cn63xx;
+	struct cvmx_mio_uartx_dlh_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_dlh cvmx_mio_uartx_dlh_t;
+typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
+
+/**
+ * cvmx_mio_uart#_dll
+ *
+ * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register
+ *
+ * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
+ * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
+ * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
+ * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
+ * follows: baud rate = eclk / (16 * divisor).
+ *
+ * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
+ * register. BUSY bit is always clear in PASS3.
+ *
+ * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
+ * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
+ * of eclk should be allowed to pass before transmitting or receiving data.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+union cvmx_mio_uartx_dll
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_dll_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dll                          : 8;  /**< Divisor Latch Low Register */
+#else
+	uint64_t dll                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_dll_s           cn30xx;
+	struct cvmx_mio_uartx_dll_s           cn31xx;
+	struct cvmx_mio_uartx_dll_s           cn38xx;
+	struct cvmx_mio_uartx_dll_s           cn38xxp2;
+	struct cvmx_mio_uartx_dll_s           cn50xx;
+	struct cvmx_mio_uartx_dll_s           cn52xx;
+	struct cvmx_mio_uartx_dll_s           cn52xxp1;
+	struct cvmx_mio_uartx_dll_s           cn56xx;
+	struct cvmx_mio_uartx_dll_s           cn56xxp1;
+	struct cvmx_mio_uartx_dll_s           cn58xx;
+	struct cvmx_mio_uartx_dll_s           cn58xxp1;
+	struct cvmx_mio_uartx_dll_s           cn63xx;
+	struct cvmx_mio_uartx_dll_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_dll cvmx_mio_uartx_dll_t;
+typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
+
+/**
+ * cvmx_mio_uart#_far
+ *
+ * MIO_UARTX_FAR = MIO UARTX FIFO Access Register
+ *
+ * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive
+ * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are
+ * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read
+ * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the
+ * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.
+ */
+union cvmx_mio_uartx_far
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_far_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t far                          : 1;  /**< FIFO Access Register */
+#else
+	uint64_t far                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uartx_far_s           cn30xx;
+	struct cvmx_mio_uartx_far_s           cn31xx;
+	struct cvmx_mio_uartx_far_s           cn38xx;
+	struct cvmx_mio_uartx_far_s           cn38xxp2;
+	struct cvmx_mio_uartx_far_s           cn50xx;
+	struct cvmx_mio_uartx_far_s           cn52xx;
+	struct cvmx_mio_uartx_far_s           cn52xxp1;
+	struct cvmx_mio_uartx_far_s           cn56xx;
+	struct cvmx_mio_uartx_far_s           cn56xxp1;
+	struct cvmx_mio_uartx_far_s           cn58xx;
+	struct cvmx_mio_uartx_far_s           cn58xxp1;
+	struct cvmx_mio_uartx_far_s           cn63xx;
+	struct cvmx_mio_uartx_far_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_far cvmx_mio_uartx_far_t;
+typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
+
+/**
+ * cvmx_mio_uart#_fcr
+ *
+ * MIO_UARTX_FCR = MIO UARTX FIFO Control Register
+ *
+ * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO
+ * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls
+ * the THRE Interrupt empty threshold level.
+ *
+ * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is
+ * changed both the TX and RX FIFOs will be reset.
+ *
+ * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is
+ * self-clearing and it is not necessary to clear this bit.
+ *
+ * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is
+ * self-clearing and it is not necessary to clear this bit.
+ *
+ * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty
+ * threshold level at which THRE Interrupts are generated when the mode is active.  See the following
+ * table for encodings:
+ *
+ * TX Trigger
+ * ----------
+ * 00 = empty FIFO
+ * 01 = 2 chars in FIFO
+ * 10 = FIFO 1/4 full
+ * 11 = FIFO 1/2 full
+ *
+ * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7
+ * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI).
+ * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted.
+ * See the following table for encodings:
+ *
+ * RX Trigger
+ * ----------
+ * 00 = 1 char in FIFO
+ * 01 = FIFO 1/4 full
+ * 10 = FIFO 1/2 full
+ * 11 = FIFO 2 chars less than full
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IIR and FCR registers are the same.
+ */
+union cvmx_mio_uartx_fcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_fcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rxtrig                       : 2;  /**< RX Trigger */
+	uint64_t txtrig                       : 2;  /**< TX Trigger */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txfr                         : 1;  /**< TX FIFO reset */
+	uint64_t rxfr                         : 1;  /**< RX FIFO reset */
+	uint64_t en                           : 1;  /**< FIFO enable */
+#else
+	uint64_t en                           : 1;
+	uint64_t rxfr                         : 1;
+	uint64_t txfr                         : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txtrig                       : 2;
+	uint64_t rxtrig                       : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_fcr_s           cn30xx;
+	struct cvmx_mio_uartx_fcr_s           cn31xx;
+	struct cvmx_mio_uartx_fcr_s           cn38xx;
+	struct cvmx_mio_uartx_fcr_s           cn38xxp2;
+	struct cvmx_mio_uartx_fcr_s           cn50xx;
+	struct cvmx_mio_uartx_fcr_s           cn52xx;
+	struct cvmx_mio_uartx_fcr_s           cn52xxp1;
+	struct cvmx_mio_uartx_fcr_s           cn56xx;
+	struct cvmx_mio_uartx_fcr_s           cn56xxp1;
+	struct cvmx_mio_uartx_fcr_s           cn58xx;
+	struct cvmx_mio_uartx_fcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_fcr_s           cn63xx;
+	struct cvmx_mio_uartx_fcr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_fcr cvmx_mio_uartx_fcr_t;
+typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
+
+/**
+ * cvmx_mio_uart#_htx
+ *
+ * MIO_UARTX_HTX = MIO UARTX Halt TX Register
+ *
+ * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be
+ * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will
+ * have no effect.
+ */
+union cvmx_mio_uartx_htx
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_htx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t htx                          : 1;  /**< Halt TX */
+#else
+	uint64_t htx                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uartx_htx_s           cn30xx;
+	struct cvmx_mio_uartx_htx_s           cn31xx;
+	struct cvmx_mio_uartx_htx_s           cn38xx;
+	struct cvmx_mio_uartx_htx_s           cn38xxp2;
+	struct cvmx_mio_uartx_htx_s           cn50xx;
+	struct cvmx_mio_uartx_htx_s           cn52xx;
+	struct cvmx_mio_uartx_htx_s           cn52xxp1;
+	struct cvmx_mio_uartx_htx_s           cn56xx;
+	struct cvmx_mio_uartx_htx_s           cn56xxp1;
+	struct cvmx_mio_uartx_htx_s           cn58xx;
+	struct cvmx_mio_uartx_htx_s           cn58xxp1;
+	struct cvmx_mio_uartx_htx_s           cn63xx;
+	struct cvmx_mio_uartx_htx_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_htx cvmx_mio_uartx_htx_t;
+typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
+
+/**
+ * cvmx_mio_uart#_ier
+ *
+ * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register
+ *
+ * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable
+ * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt
+ * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line
+ * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI).
+ *
+ * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode.
+ *
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IER and DLH registers are the same.
+ */
+union cvmx_mio_uartx_ier
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_ier_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ptime                        : 1;  /**< Programmable THRE Interrupt mode enable */
+	uint64_t reserved_4_6                 : 3;
+	uint64_t edssi                        : 1;  /**< Enable Modem Status Interrupt */
+	uint64_t elsi                         : 1;  /**< Enable Receiver Line Status Interrupt */
+	uint64_t etbei                        : 1;  /**< Enable Transmitter Holding Register Empty Interrupt */
+	uint64_t erbfi                        : 1;  /**< Enable Received Data Available Interrupt */
+#else
+	uint64_t erbfi                        : 1;
+	uint64_t etbei                        : 1;
+	uint64_t elsi                         : 1;
+	uint64_t edssi                        : 1;
+	uint64_t reserved_4_6                 : 3;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_ier_s           cn30xx;
+	struct cvmx_mio_uartx_ier_s           cn31xx;
+	struct cvmx_mio_uartx_ier_s           cn38xx;
+	struct cvmx_mio_uartx_ier_s           cn38xxp2;
+	struct cvmx_mio_uartx_ier_s           cn50xx;
+	struct cvmx_mio_uartx_ier_s           cn52xx;
+	struct cvmx_mio_uartx_ier_s           cn52xxp1;
+	struct cvmx_mio_uartx_ier_s           cn56xx;
+	struct cvmx_mio_uartx_ier_s           cn56xxp1;
+	struct cvmx_mio_uartx_ier_s           cn58xx;
+	struct cvmx_mio_uartx_ier_s           cn58xxp1;
+	struct cvmx_mio_uartx_ier_s           cn63xx;
+	struct cvmx_mio_uartx_ier_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_ier cvmx_mio_uartx_ier_t;
+typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
+
+/**
+ * cvmx_mio_uart#_iir
+ *
+ * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register
+ *
+ * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an
+ * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs
+ * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending
+ * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt
+ * reset control:
+ *
+ * Interrupt   Priority   Interrupt         Interrupt                                       Interrupt
+ * ID          Level      Type              Source                                          Reset By
+ * ---------------------------------------------------------------------------------------------------------------------------------
+ * 0001        -          None              None                                            -
+ *
+ * 0110        Highest    Receiver Line     Overrun, parity, or framing errors or break     Reading the Line Status Register
+ *                        Status            interrupt
+ *
+ * 0100        Second     Received Data     Receiver data available (FIFOs disabled) or     Reading the Receiver Buffer Register
+ *                        Available         RX FIFO trigger level reached (FIFOs            (FIFOs disabled) or the FIFO drops below
+ *                                          enabled)                                        the trigger level (FIFOs enabled)
+ *
+ * 1100        Second     Character         No characters in or out of the RX FIFO          Reading the Receiver Buffer Register
+ *                        Timeout           during the last 4 character times and there
+ *                        Indication        is at least 1 character in it during this
+ *                                          time
+ *
+ * 0010        Third      Transmitter       Transmitter Holding Register Empty              Reading the Interrupt Identity Register
+ *                        Holding           (Programmable THRE Mode disabled) or TX         (if source of interrupt) or writing into
+ *                        Register          FIFO at or below threshold (Programmable        THR (FIFOs or THRE Mode disabled) or TX
+ *                        Empty             THRE Mode enabled)                              FIFO above threshold (FIFOs and THRE
+ *                                                                                          Mode enabled)
+ *
+ * 0000        Fourth     Modem Status      Clear To Send (CTS) or Data Set Ready (DSR)     Reading the Modem Status Register
+ *                        Changed           or Ring Indicator (RI) or Data Carrier
+ *                                          Detect (DCD) changed (note: if auto flow
+ *                                          control mode is enabled, a change in CTS
+ *                                          will not cause an interrupt)
+ *
+ * 0111        Fifth      Busy Detect       Software has tried to write to the Line         Reading the UART Status Register
+ *                        Indication        Control Register while the BUSY bit of the
+ *                                          UART Status Register was set
+ *
+ * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IIR and FCR registers are the same.
+ */
+union cvmx_mio_uartx_iir
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_iir_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t fen                          : 2;  /**< FIFO-enabled bits */
+	uint64_t reserved_4_5                 : 2;
+	cvmx_uart_iid_t iid                   : 4;  /**< Interrupt ID */
+#else
+	cvmx_uart_iid_t iid                   : 4;
+	uint64_t reserved_4_5                 : 2;
+	uint64_t fen                          : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_iir_s           cn30xx;
+	struct cvmx_mio_uartx_iir_s           cn31xx;
+	struct cvmx_mio_uartx_iir_s           cn38xx;
+	struct cvmx_mio_uartx_iir_s           cn38xxp2;
+	struct cvmx_mio_uartx_iir_s           cn50xx;
+	struct cvmx_mio_uartx_iir_s           cn52xx;
+	struct cvmx_mio_uartx_iir_s           cn52xxp1;
+	struct cvmx_mio_uartx_iir_s           cn56xx;
+	struct cvmx_mio_uartx_iir_s           cn56xxp1;
+	struct cvmx_mio_uartx_iir_s           cn58xx;
+	struct cvmx_mio_uartx_iir_s           cn58xxp1;
+	struct cvmx_mio_uartx_iir_s           cn63xx;
+	struct cvmx_mio_uartx_iir_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_iir cvmx_mio_uartx_iir_t;
+typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
+
+/**
+ * cvmx_mio_uart#_lcr
+ *
+ * MIO_UARTX_LCR = MIO UARTX Line Control Register
+ *
+ * The Line Control Register (LCR) controls the format of the data that is transmitted and received by
+ * the UART.
+ *
+ * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of
+ * data bits per character that are transmitted and received. See the following table for encodings:
+ *
+ * CLS
+ * ---
+ * 00 = 5 bits (bits 0-4 sent)
+ * 01 = 6 bits (bits 0-5 sent)
+ * 10 = 7 bits (bits 0-6 sent)
+ * 11 = 8 bits (all bits sent)
+ *
+ * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted
+ * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are
+ * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that
+ * regardless of the number of stop bits selected the receiver will only check the first stop bit.
+ *
+ * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and
+ * detection in transmitted and received serial character respectively.
+ *
+ * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd
+ * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd
+ * number of ones is transmitted or checked.
+ *
+ * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout
+ * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback
+ * mode, the break condition is internally looped back to the receiver.
+ *
+ * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the
+ * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after
+ * initial baud rate setup in order to access other registers.
+ *
+ * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART
+ * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable
+ * because the BUSY bit is always clear.
+ */
+union cvmx_mio_uartx_lcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_lcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dlab                         : 1;  /**< Divisor Latch Address bit */
+	uint64_t brk                          : 1;  /**< Break Control bit */
+	uint64_t reserved_5_5                 : 1;
+	uint64_t eps                          : 1;  /**< Even Parity Select bit */
+	uint64_t pen                          : 1;  /**< Parity Enable bit */
+	uint64_t stop                         : 1;  /**< Stop Control bit */
+	cvmx_uart_bits_t cls                  : 2;  /**< Character Length Select */
+#else
+	cvmx_uart_bits_t cls                  : 2;
+	uint64_t stop                         : 1;
+	uint64_t pen                          : 1;
+	uint64_t eps                          : 1;
+	uint64_t reserved_5_5                 : 1;
+	uint64_t brk                          : 1;
+	uint64_t dlab                         : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_lcr_s           cn30xx;
+	struct cvmx_mio_uartx_lcr_s           cn31xx;
+	struct cvmx_mio_uartx_lcr_s           cn38xx;
+	struct cvmx_mio_uartx_lcr_s           cn38xxp2;
+	struct cvmx_mio_uartx_lcr_s           cn50xx;
+	struct cvmx_mio_uartx_lcr_s           cn52xx;
+	struct cvmx_mio_uartx_lcr_s           cn52xxp1;
+	struct cvmx_mio_uartx_lcr_s           cn56xx;
+	struct cvmx_mio_uartx_lcr_s           cn56xxp1;
+	struct cvmx_mio_uartx_lcr_s           cn58xx;
+	struct cvmx_mio_uartx_lcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_lcr_s           cn63xx;
+	struct cvmx_mio_uartx_lcr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_lcr cvmx_mio_uartx_lcr_t;
+typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
+
+/**
+ * cvmx_mio_uart#_lsr
+ *
+ * MIO_UARTX_LSR = MIO UARTX Line Status Register
+ *
+ * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This
+ * status can be read by the user at anytime.
+ *
+ * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one
+ * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO
+ * mode, or when the receiver FIFO is empty, in FIFO mode.
+ *
+ * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred
+ * because a new data character was received before the previous data was read. In the non-FIFO mode, the
+ * OE bit is set when a new character arrives in the receiver before the previous character was read from
+ * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error
+ * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is
+ * retained and the data in the receive shift register is lost.
+ *
+ * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the
+ * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is
+ * associated with a character received, it is revealed when the character with the parity error arrives
+ * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break
+ * interrupt has occurred, as indicated by the Break Interrupt (BI) bit.
+ *
+ * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the
+ * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received
+ * data. In the FIFO mode, since the framing error is associated with a character received, it is
+ * revealed when the character with the framing error is at the top of the FIFO. When a framing error
+ * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start
+ * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and
+ * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has
+ * occurred, as indicated by the Break Interrupt (BI) bit.
+ *
+ * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed.
+ *
+ * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in
+ * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on
+ * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the
+ * FIFO mode, the character associated with the break condition is carried through the FIFO and is
+ * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-
+ * FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
+ *
+ * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode
+ * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is
+ * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no
+ * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the
+ * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5
+ * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE
+ * Interrupts, which are then controlled by the FCR[5:4] threshold setting.
+ *
+ * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the
+ * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever
+ * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is
+ * typically used to make sure it is safe to change control registers. Changing control registers while
+ * the transmitter is busy can result in corrupt data being transmitted.
+ *
+ * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It
+ * is set when there is at least one parity error, framing error, or break indication in the FIFO. This
+ * bit is cleared when the LSR is read and the character with the error is at the top of the receiver
+ * FIFO and there are no subsequent errors in the FIFO.
+ */
+union cvmx_mio_uartx_lsr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_lsr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ferr                         : 1;  /**< Error in Receiver FIFO bit */
+	uint64_t temt                         : 1;  /**< Transmitter Empty bit */
+	uint64_t thre                         : 1;  /**< Transmitter Holding Register Empty bit */
+	uint64_t bi                           : 1;  /**< Break Interrupt bit */
+	uint64_t fe                           : 1;  /**< Framing Error bit */
+	uint64_t pe                           : 1;  /**< Parity Error bit */
+	uint64_t oe                           : 1;  /**< Overrun Error bit */
+	uint64_t dr                           : 1;  /**< Data Ready bit */
+#else
+	uint64_t dr                           : 1;
+	uint64_t oe                           : 1;
+	uint64_t pe                           : 1;
+	uint64_t fe                           : 1;
+	uint64_t bi                           : 1;
+	uint64_t thre                         : 1;
+	uint64_t temt                         : 1;
+	uint64_t ferr                         : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_lsr_s           cn30xx;
+	struct cvmx_mio_uartx_lsr_s           cn31xx;
+	struct cvmx_mio_uartx_lsr_s           cn38xx;
+	struct cvmx_mio_uartx_lsr_s           cn38xxp2;
+	struct cvmx_mio_uartx_lsr_s           cn50xx;
+	struct cvmx_mio_uartx_lsr_s           cn52xx;
+	struct cvmx_mio_uartx_lsr_s           cn52xxp1;
+	struct cvmx_mio_uartx_lsr_s           cn56xx;
+	struct cvmx_mio_uartx_lsr_s           cn56xxp1;
+	struct cvmx_mio_uartx_lsr_s           cn58xx;
+	struct cvmx_mio_uartx_lsr_s           cn58xxp1;
+	struct cvmx_mio_uartx_lsr_s           cn63xx;
+	struct cvmx_mio_uartx_lsr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_lsr cvmx_mio_uartx_lsr_t;
+typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
+
+/**
+ * cvmx_mio_uart#_mcr
+ *
+ * MIO_UARTX_MCR = MIO UARTX Modem Control Register
+ *
+ * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART.
+ * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the
+ * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n.  In loopback mode, these outputs are
+ * driven inactive high while the values in these locations are internally looped back to the inputs.
+ *
+ * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated
+ * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The
+ * rts_n output will be de-asserted whenever RTS (bit 1) is set low.
+ *
+ * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1
+ * and OUT2 bits still function in Loopback mode.  The UART1 dtr_n, out1_n, and out2_n outputs are not
+ * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback
+ * mode.
+ *
+ * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output
+ * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This
+ * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n,
+ * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n)
+ * are looped back to the inputs, internally.
+ *
+ * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set,
+ * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled.
+ *
+ * Auto RTS becomes active when the following occurs:
+ * 1. MCR bit 1 is set
+ * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
+ * 3. MCR bit 5 is set (must be set after FCR bit 0)
+ *
+ * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the
+ * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the
+ * other UART stops sending serial data until the receiver FIFO has available space.
+ *
+ * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one
+ * additional character may be transmitted to the UART after rts_n has become inactive (due to data
+ * already having entered the transmitter block in the other UART), setting the threshold to 2 less
+ * than full allows maximum use of the FIFO with a safety zone of one character.
+ *
+ * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n
+ * again becomes active-low, signalling the other UART to continue sending data. It is important to note
+ * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are
+ * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive,
+ * rts_n is controlled solely by MCR[1].
+ *
+ * Auto CTS becomes active when the following occurs:
+ * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
+ * 2. MCR bit 5 is set (must be set after FCR bit 0)
+ *
+ * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This
+ * prevents overflowing the FIFO of the receiving UART.
+ *
+ * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another
+ * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the
+ * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either
+ * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode
+ * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO
+ * full status, software can poll this before each write to the Transmitter FIFO.
+ *
+ * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the
+ * FIFO may be read through the Transmit FIFO Level (TFL) register.
+ *
+ * When the cts_n input becomes active-low again, transmission resumes. It is important to note that,
+ * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are
+ * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by
+ * cts_n.
+ */
+union cvmx_mio_uartx_mcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_mcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t afce                         : 1;  /**< Auto Flow Control Enable bit */
+	uint64_t loop                         : 1;  /**< Loopback bit */
+	uint64_t out2                         : 1;  /**< OUT2 output bit */
+	uint64_t out1                         : 1;  /**< OUT1 output bit */
+	uint64_t rts                          : 1;  /**< Request To Send output bit */
+	uint64_t dtr                          : 1;  /**< Data Terminal Ready output bit */
+#else
+	uint64_t dtr                          : 1;
+	uint64_t rts                          : 1;
+	uint64_t out1                         : 1;
+	uint64_t out2                         : 1;
+	uint64_t loop                         : 1;
+	uint64_t afce                         : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_mio_uartx_mcr_s           cn30xx;
+	struct cvmx_mio_uartx_mcr_s           cn31xx;
+	struct cvmx_mio_uartx_mcr_s           cn38xx;
+	struct cvmx_mio_uartx_mcr_s           cn38xxp2;
+	struct cvmx_mio_uartx_mcr_s           cn50xx;
+	struct cvmx_mio_uartx_mcr_s           cn52xx;
+	struct cvmx_mio_uartx_mcr_s           cn52xxp1;
+	struct cvmx_mio_uartx_mcr_s           cn56xx;
+	struct cvmx_mio_uartx_mcr_s           cn56xxp1;
+	struct cvmx_mio_uartx_mcr_s           cn58xx;
+	struct cvmx_mio_uartx_mcr_s           cn58xxp1;
+	struct cvmx_mio_uartx_mcr_s           cn63xx;
+	struct cvmx_mio_uartx_mcr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_mcr cvmx_mio_uartx_mcr_t;
+typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
+
+/**
+ * cvmx_mio_uart#_msr
+ *
+ * MIO_UARTX_MSR = MIO UARTX Modem Status Register
+ *
+ * The Modem Status Register (MSR) contains the current status of the modem control input lines and if
+ * they changed.
+ *
+ * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n,
+ * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n
+ * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In
+ * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and
+ * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state
+ * from a high to a low.
+ *
+ * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software
+ * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains
+ * asserted.
+ *
+ * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem
+ * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI
+ * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS
+ * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2
+ * (Out1), and DCD is the same as MCR bit 3 (Out2).
+ *
+ * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip.
+ * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode.  The UART1 dsr_n, ri_n, and dcd_n
+ * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and
+ * DCD bits will be '0' when not in Loopback mode.
+ */
+union cvmx_mio_uartx_msr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_msr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dcd                          : 1;  /**< Data Carrier Detect input bit */
+	uint64_t ri                           : 1;  /**< Ring Indicator input bit */
+	uint64_t dsr                          : 1;  /**< Data Set Ready input bit */
+	uint64_t cts                          : 1;  /**< Clear To Send input bit */
+	uint64_t ddcd                         : 1;  /**< Delta Data Carrier Detect bit */
+	uint64_t teri                         : 1;  /**< Trailing Edge of Ring Indicator bit */
+	uint64_t ddsr                         : 1;  /**< Delta Data Set Ready bit */
+	uint64_t dcts                         : 1;  /**< Delta Clear To Send bit */
+#else
+	uint64_t dcts                         : 1;
+	uint64_t ddsr                         : 1;
+	uint64_t teri                         : 1;
+	uint64_t ddcd                         : 1;
+	uint64_t cts                          : 1;
+	uint64_t dsr                          : 1;
+	uint64_t ri                           : 1;
+	uint64_t dcd                          : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_msr_s           cn30xx;
+	struct cvmx_mio_uartx_msr_s           cn31xx;
+	struct cvmx_mio_uartx_msr_s           cn38xx;
+	struct cvmx_mio_uartx_msr_s           cn38xxp2;
+	struct cvmx_mio_uartx_msr_s           cn50xx;
+	struct cvmx_mio_uartx_msr_s           cn52xx;
+	struct cvmx_mio_uartx_msr_s           cn52xxp1;
+	struct cvmx_mio_uartx_msr_s           cn56xx;
+	struct cvmx_mio_uartx_msr_s           cn56xxp1;
+	struct cvmx_mio_uartx_msr_s           cn58xx;
+	struct cvmx_mio_uartx_msr_s           cn58xxp1;
+	struct cvmx_mio_uartx_msr_s           cn63xx;
+	struct cvmx_mio_uartx_msr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_msr cvmx_mio_uartx_msr_t;
+typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
+
+/**
+ * cvmx_mio_uart#_rbr
+ *
+ * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register
+ *
+ * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the
+ * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the
+ * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be
+ * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When
+ * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO
+ * is full (64 characters) and this register is not read before the next data character arrives, then the
+ * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs.
+ *
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+union cvmx_mio_uartx_rbr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_rbr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rbr                          : 8;  /**< Receive Buffer Register */
+#else
+	uint64_t rbr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_rbr_s           cn30xx;
+	struct cvmx_mio_uartx_rbr_s           cn31xx;
+	struct cvmx_mio_uartx_rbr_s           cn38xx;
+	struct cvmx_mio_uartx_rbr_s           cn38xxp2;
+	struct cvmx_mio_uartx_rbr_s           cn50xx;
+	struct cvmx_mio_uartx_rbr_s           cn52xx;
+	struct cvmx_mio_uartx_rbr_s           cn52xxp1;
+	struct cvmx_mio_uartx_rbr_s           cn56xx;
+	struct cvmx_mio_uartx_rbr_s           cn56xxp1;
+	struct cvmx_mio_uartx_rbr_s           cn58xx;
+	struct cvmx_mio_uartx_rbr_s           cn58xxp1;
+	struct cvmx_mio_uartx_rbr_s           cn63xx;
+	struct cvmx_mio_uartx_rbr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_rbr cvmx_mio_uartx_rbr_t;
+typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
+
+/**
+ * cvmx_mio_uart#_rfl
+ *
+ * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register
+ *
+ * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO.
+ */
+union cvmx_mio_uartx_rfl
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_rfl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t rfl                          : 7;  /**< Receive FIFO Level Register */
+#else
+	uint64_t rfl                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_uartx_rfl_s           cn30xx;
+	struct cvmx_mio_uartx_rfl_s           cn31xx;
+	struct cvmx_mio_uartx_rfl_s           cn38xx;
+	struct cvmx_mio_uartx_rfl_s           cn38xxp2;
+	struct cvmx_mio_uartx_rfl_s           cn50xx;
+	struct cvmx_mio_uartx_rfl_s           cn52xx;
+	struct cvmx_mio_uartx_rfl_s           cn52xxp1;
+	struct cvmx_mio_uartx_rfl_s           cn56xx;
+	struct cvmx_mio_uartx_rfl_s           cn56xxp1;
+	struct cvmx_mio_uartx_rfl_s           cn58xx;
+	struct cvmx_mio_uartx_rfl_s           cn58xxp1;
+	struct cvmx_mio_uartx_rfl_s           cn63xx;
+	struct cvmx_mio_uartx_rfl_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_rfl cvmx_mio_uartx_rfl_t;
+typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
+
+/**
+ * cvmx_mio_uart#_rfw
+ *
+ * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register
+ *
+ * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is
+ * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each
+ * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are
+ * not enabled, this register is used to write data to the RBR.
+ */
+union cvmx_mio_uartx_rfw
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_rfw_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t rffe                         : 1;  /**< Receive FIFO Framing Error */
+	uint64_t rfpe                         : 1;  /**< Receive FIFO Parity Error */
+	uint64_t rfwd                         : 8;  /**< Receive FIFO Write Data */
+#else
+	uint64_t rfwd                         : 8;
+	uint64_t rfpe                         : 1;
+	uint64_t rffe                         : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_uartx_rfw_s           cn30xx;
+	struct cvmx_mio_uartx_rfw_s           cn31xx;
+	struct cvmx_mio_uartx_rfw_s           cn38xx;
+	struct cvmx_mio_uartx_rfw_s           cn38xxp2;
+	struct cvmx_mio_uartx_rfw_s           cn50xx;
+	struct cvmx_mio_uartx_rfw_s           cn52xx;
+	struct cvmx_mio_uartx_rfw_s           cn52xxp1;
+	struct cvmx_mio_uartx_rfw_s           cn56xx;
+	struct cvmx_mio_uartx_rfw_s           cn56xxp1;
+	struct cvmx_mio_uartx_rfw_s           cn58xx;
+	struct cvmx_mio_uartx_rfw_s           cn58xxp1;
+	struct cvmx_mio_uartx_rfw_s           cn63xx;
+	struct cvmx_mio_uartx_rfw_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_rfw cvmx_mio_uartx_rfw_t;
+typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
+
+/**
+ * cvmx_mio_uart#_sbcr
+ *
+ * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register
+ *
+ * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can
+ * be used to remove the burden of having to perform a read-modify-write on the LCR.
+ */
+union cvmx_mio_uartx_sbcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_sbcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t sbcr                         : 1;  /**< Shadow Break Control */
+#else
+	uint64_t sbcr                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uartx_sbcr_s          cn30xx;
+	struct cvmx_mio_uartx_sbcr_s          cn31xx;
+	struct cvmx_mio_uartx_sbcr_s          cn38xx;
+	struct cvmx_mio_uartx_sbcr_s          cn38xxp2;
+	struct cvmx_mio_uartx_sbcr_s          cn50xx;
+	struct cvmx_mio_uartx_sbcr_s          cn52xx;
+	struct cvmx_mio_uartx_sbcr_s          cn52xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cn56xx;
+	struct cvmx_mio_uartx_sbcr_s          cn56xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cn58xx;
+	struct cvmx_mio_uartx_sbcr_s          cn58xxp1;
+	struct cvmx_mio_uartx_sbcr_s          cn63xx;
+	struct cvmx_mio_uartx_sbcr_s          cn63xxp1;
+};
+typedef union cvmx_mio_uartx_sbcr cvmx_mio_uartx_sbcr_t;
+typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
+
+/**
+ * cvmx_mio_uart#_scr
+ *
+ * MIO_UARTX_SCR = MIO UARTX Scratchpad Register
+ *
+ * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary
+ * storage space.
+ */
+union cvmx_mio_uartx_scr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_scr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t scr                          : 8;  /**< Scratchpad Register */
+#else
+	uint64_t scr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_scr_s           cn30xx;
+	struct cvmx_mio_uartx_scr_s           cn31xx;
+	struct cvmx_mio_uartx_scr_s           cn38xx;
+	struct cvmx_mio_uartx_scr_s           cn38xxp2;
+	struct cvmx_mio_uartx_scr_s           cn50xx;
+	struct cvmx_mio_uartx_scr_s           cn52xx;
+	struct cvmx_mio_uartx_scr_s           cn52xxp1;
+	struct cvmx_mio_uartx_scr_s           cn56xx;
+	struct cvmx_mio_uartx_scr_s           cn56xxp1;
+	struct cvmx_mio_uartx_scr_s           cn58xx;
+	struct cvmx_mio_uartx_scr_s           cn58xxp1;
+	struct cvmx_mio_uartx_scr_s           cn63xx;
+	struct cvmx_mio_uartx_scr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_scr cvmx_mio_uartx_scr_t;
+typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
+
+/**
+ * cvmx_mio_uart#_sfe
+ *
+ * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register
+ *
+ * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the FIFO enable bit gets updated.
+ */
+union cvmx_mio_uartx_sfe
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_sfe_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t sfe                          : 1;  /**< Shadow FIFO Enable */
+#else
+	uint64_t sfe                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uartx_sfe_s           cn30xx;
+	struct cvmx_mio_uartx_sfe_s           cn31xx;
+	struct cvmx_mio_uartx_sfe_s           cn38xx;
+	struct cvmx_mio_uartx_sfe_s           cn38xxp2;
+	struct cvmx_mio_uartx_sfe_s           cn50xx;
+	struct cvmx_mio_uartx_sfe_s           cn52xx;
+	struct cvmx_mio_uartx_sfe_s           cn52xxp1;
+	struct cvmx_mio_uartx_sfe_s           cn56xx;
+	struct cvmx_mio_uartx_sfe_s           cn56xxp1;
+	struct cvmx_mio_uartx_sfe_s           cn58xx;
+	struct cvmx_mio_uartx_sfe_s           cn58xxp1;
+	struct cvmx_mio_uartx_sfe_s           cn63xx;
+	struct cvmx_mio_uartx_sfe_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_sfe cvmx_mio_uartx_sfe_t;
+typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
+
+/**
+ * cvmx_mio_uart#_srr
+ *
+ * MIO_UARTX_SRR = MIO UARTX Software Reset Register
+ *
+ * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive
+ * FIFO and/or the transmit FIFO.
+ *
+ * Bit 0 of the SRR is the UART Soft Reset (USR) bit.  Setting this bit resets the UART.
+ *
+ * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove
+ * the burden on software having to store previously written FCR values (which are pretty static) just
+ * to reset the receive FIFO.
+ *
+ * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove
+ * the burden on software having to store previously written FCR values (which are pretty static) just
+ * to reset the transmit FIFO.
+ */
+union cvmx_mio_uartx_srr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_srr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t stfr                         : 1;  /**< Shadow TX FIFO Reset */
+	uint64_t srfr                         : 1;  /**< Shadow RX FIFO Reset */
+	uint64_t usr                          : 1;  /**< UART Soft Reset */
+#else
+	uint64_t usr                          : 1;
+	uint64_t srfr                         : 1;
+	uint64_t stfr                         : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_mio_uartx_srr_s           cn30xx;
+	struct cvmx_mio_uartx_srr_s           cn31xx;
+	struct cvmx_mio_uartx_srr_s           cn38xx;
+	struct cvmx_mio_uartx_srr_s           cn38xxp2;
+	struct cvmx_mio_uartx_srr_s           cn50xx;
+	struct cvmx_mio_uartx_srr_s           cn52xx;
+	struct cvmx_mio_uartx_srr_s           cn52xxp1;
+	struct cvmx_mio_uartx_srr_s           cn56xx;
+	struct cvmx_mio_uartx_srr_s           cn56xxp1;
+	struct cvmx_mio_uartx_srr_s           cn58xx;
+	struct cvmx_mio_uartx_srr_s           cn58xxp1;
+	struct cvmx_mio_uartx_srr_s           cn63xx;
+	struct cvmx_mio_uartx_srr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_srr cvmx_mio_uartx_srr_t;
+typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
+
+/**
+ * cvmx_mio_uart#_srt
+ *
+ * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register
+ *
+ * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the RX Trigger bits get updated.
+ */
+union cvmx_mio_uartx_srt
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_srt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t srt                          : 2;  /**< Shadow RX Trigger */
+#else
+	uint64_t srt                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_uartx_srt_s           cn30xx;
+	struct cvmx_mio_uartx_srt_s           cn31xx;
+	struct cvmx_mio_uartx_srt_s           cn38xx;
+	struct cvmx_mio_uartx_srt_s           cn38xxp2;
+	struct cvmx_mio_uartx_srt_s           cn50xx;
+	struct cvmx_mio_uartx_srt_s           cn52xx;
+	struct cvmx_mio_uartx_srt_s           cn52xxp1;
+	struct cvmx_mio_uartx_srt_s           cn56xx;
+	struct cvmx_mio_uartx_srt_s           cn56xxp1;
+	struct cvmx_mio_uartx_srt_s           cn58xx;
+	struct cvmx_mio_uartx_srt_s           cn58xxp1;
+	struct cvmx_mio_uartx_srt_s           cn63xx;
+	struct cvmx_mio_uartx_srt_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_srt cvmx_mio_uartx_srt_t;
+typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
+
+/**
+ * cvmx_mio_uart#_srts
+ *
+ * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register
+ *
+ * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can
+ * be used to remove the burden of having to perform a read-modify-write on the MCR.
+ */
+union cvmx_mio_uartx_srts
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_srts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t srts                         : 1;  /**< Shadow Request To Send */
+#else
+	uint64_t srts                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uartx_srts_s          cn30xx;
+	struct cvmx_mio_uartx_srts_s          cn31xx;
+	struct cvmx_mio_uartx_srts_s          cn38xx;
+	struct cvmx_mio_uartx_srts_s          cn38xxp2;
+	struct cvmx_mio_uartx_srts_s          cn50xx;
+	struct cvmx_mio_uartx_srts_s          cn52xx;
+	struct cvmx_mio_uartx_srts_s          cn52xxp1;
+	struct cvmx_mio_uartx_srts_s          cn56xx;
+	struct cvmx_mio_uartx_srts_s          cn56xxp1;
+	struct cvmx_mio_uartx_srts_s          cn58xx;
+	struct cvmx_mio_uartx_srts_s          cn58xxp1;
+	struct cvmx_mio_uartx_srts_s          cn63xx;
+	struct cvmx_mio_uartx_srts_s          cn63xxp1;
+};
+typedef union cvmx_mio_uartx_srts cvmx_mio_uartx_srts_t;
+typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
+
+/**
+ * cvmx_mio_uart#_stt
+ *
+ * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register
+ *
+ * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the TX Trigger bits get updated.
+ */
+union cvmx_mio_uartx_stt
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_stt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t stt                          : 2;  /**< Shadow TX Trigger */
+#else
+	uint64_t stt                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_uartx_stt_s           cn30xx;
+	struct cvmx_mio_uartx_stt_s           cn31xx;
+	struct cvmx_mio_uartx_stt_s           cn38xx;
+	struct cvmx_mio_uartx_stt_s           cn38xxp2;
+	struct cvmx_mio_uartx_stt_s           cn50xx;
+	struct cvmx_mio_uartx_stt_s           cn52xx;
+	struct cvmx_mio_uartx_stt_s           cn52xxp1;
+	struct cvmx_mio_uartx_stt_s           cn56xx;
+	struct cvmx_mio_uartx_stt_s           cn56xxp1;
+	struct cvmx_mio_uartx_stt_s           cn58xx;
+	struct cvmx_mio_uartx_stt_s           cn58xxp1;
+	struct cvmx_mio_uartx_stt_s           cn63xx;
+	struct cvmx_mio_uartx_stt_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_stt cvmx_mio_uartx_stt_t;
+typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
+
+/**
+ * cvmx_mio_uart#_tfl
+ *
+ * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register
+ *
+ * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO.
+ */
+union cvmx_mio_uartx_tfl
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_tfl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t tfl                          : 7;  /**< Transmit FIFO Level Register */
+#else
+	uint64_t tfl                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_uartx_tfl_s           cn30xx;
+	struct cvmx_mio_uartx_tfl_s           cn31xx;
+	struct cvmx_mio_uartx_tfl_s           cn38xx;
+	struct cvmx_mio_uartx_tfl_s           cn38xxp2;
+	struct cvmx_mio_uartx_tfl_s           cn50xx;
+	struct cvmx_mio_uartx_tfl_s           cn52xx;
+	struct cvmx_mio_uartx_tfl_s           cn52xxp1;
+	struct cvmx_mio_uartx_tfl_s           cn56xx;
+	struct cvmx_mio_uartx_tfl_s           cn56xxp1;
+	struct cvmx_mio_uartx_tfl_s           cn58xx;
+	struct cvmx_mio_uartx_tfl_s           cn58xxp1;
+	struct cvmx_mio_uartx_tfl_s           cn63xx;
+	struct cvmx_mio_uartx_tfl_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_tfl cvmx_mio_uartx_tfl_t;
+typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
+
+/**
+ * cvmx_mio_uart#_tfr
+ *
+ * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register
+ *
+ * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is
+ * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO.
+ * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the
+ * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR.
+ */
+union cvmx_mio_uartx_tfr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_tfr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t tfr                          : 8;  /**< Transmit FIFO Read Register */
+#else
+	uint64_t tfr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_tfr_s           cn30xx;
+	struct cvmx_mio_uartx_tfr_s           cn31xx;
+	struct cvmx_mio_uartx_tfr_s           cn38xx;
+	struct cvmx_mio_uartx_tfr_s           cn38xxp2;
+	struct cvmx_mio_uartx_tfr_s           cn50xx;
+	struct cvmx_mio_uartx_tfr_s           cn52xx;
+	struct cvmx_mio_uartx_tfr_s           cn52xxp1;
+	struct cvmx_mio_uartx_tfr_s           cn56xx;
+	struct cvmx_mio_uartx_tfr_s           cn56xxp1;
+	struct cvmx_mio_uartx_tfr_s           cn58xx;
+	struct cvmx_mio_uartx_tfr_s           cn58xxp1;
+	struct cvmx_mio_uartx_tfr_s           cn63xx;
+	struct cvmx_mio_uartx_tfr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_tfr cvmx_mio_uartx_tfr_t;
+typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
+
+/**
+ * cvmx_mio_uart#_thr
+ *
+ * MIO_UARTX_THR = MIO UARTX Transmit Holding Register
+ *
+ * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the
+ * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of
+ * the Line Status Register (LSR) is set.
+ *
+ * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any
+ * additional writes to the THR before the THRE is set again causes the THR data to be overwritten.
+ *
+ * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may
+ * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results
+ * in the write data being lost.
+ *
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ *
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+union cvmx_mio_uartx_thr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t thr                          : 8;  /**< Transmit Holding Register */
+#else
+	uint64_t thr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uartx_thr_s           cn30xx;
+	struct cvmx_mio_uartx_thr_s           cn31xx;
+	struct cvmx_mio_uartx_thr_s           cn38xx;
+	struct cvmx_mio_uartx_thr_s           cn38xxp2;
+	struct cvmx_mio_uartx_thr_s           cn50xx;
+	struct cvmx_mio_uartx_thr_s           cn52xx;
+	struct cvmx_mio_uartx_thr_s           cn52xxp1;
+	struct cvmx_mio_uartx_thr_s           cn56xx;
+	struct cvmx_mio_uartx_thr_s           cn56xxp1;
+	struct cvmx_mio_uartx_thr_s           cn58xx;
+	struct cvmx_mio_uartx_thr_s           cn58xxp1;
+	struct cvmx_mio_uartx_thr_s           cn63xx;
+	struct cvmx_mio_uartx_thr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_thr cvmx_mio_uartx_thr_t;
+typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
+
+/**
+ * cvmx_mio_uart#_usr
+ *
+ * MIO_UARTX_USR = MIO UARTX UART Status Register
+ *
+ * The UART Status Register (USR) contains UART status information.
+ *
+ * USR bit 0 is the BUSY bit.  When set this bit indicates that a serial transfer is in progress, when
+ * clear it indicates that the UART is idle or inactive.
+ *
+ * Note: In PASS3, the BUSY bit will always be clear.
+ *
+ * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX
+ * FIFO Not Empty (RFNE), and RX FIFO Full (RFF).
+ */
+union cvmx_mio_uartx_usr
+{
+	uint64_t u64;
+	struct cvmx_mio_uartx_usr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t rff                          : 1;  /**< RX FIFO Full */
+	uint64_t rfne                         : 1;  /**< RX FIFO Not Empty */
+	uint64_t tfe                          : 1;  /**< TX FIFO Empty */
+	uint64_t tfnf                         : 1;  /**< TX FIFO Not Full */
+	uint64_t busy                         : 1;  /**< Busy bit (always 0 in PASS3) */
+#else
+	uint64_t busy                         : 1;
+	uint64_t tfnf                         : 1;
+	uint64_t tfe                          : 1;
+	uint64_t rfne                         : 1;
+	uint64_t rff                          : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_mio_uartx_usr_s           cn30xx;
+	struct cvmx_mio_uartx_usr_s           cn31xx;
+	struct cvmx_mio_uartx_usr_s           cn38xx;
+	struct cvmx_mio_uartx_usr_s           cn38xxp2;
+	struct cvmx_mio_uartx_usr_s           cn50xx;
+	struct cvmx_mio_uartx_usr_s           cn52xx;
+	struct cvmx_mio_uartx_usr_s           cn52xxp1;
+	struct cvmx_mio_uartx_usr_s           cn56xx;
+	struct cvmx_mio_uartx_usr_s           cn56xxp1;
+	struct cvmx_mio_uartx_usr_s           cn58xx;
+	struct cvmx_mio_uartx_usr_s           cn58xxp1;
+	struct cvmx_mio_uartx_usr_s           cn63xx;
+	struct cvmx_mio_uartx_usr_s           cn63xxp1;
+};
+typedef union cvmx_mio_uartx_usr cvmx_mio_uartx_usr_t;
+typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
+
+/**
+ * cvmx_mio_uart2_dlh
+ */
+union cvmx_mio_uart2_dlh
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_dlh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dlh                          : 8;  /**< Divisor Latch High Register */
+#else
+	uint64_t dlh                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_dlh_s           cn52xx;
+	struct cvmx_mio_uart2_dlh_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_dlh cvmx_mio_uart2_dlh_t;
+
+/**
+ * cvmx_mio_uart2_dll
+ */
+union cvmx_mio_uart2_dll
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_dll_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dll                          : 8;  /**< Divisor Latch Low Register */
+#else
+	uint64_t dll                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_dll_s           cn52xx;
+	struct cvmx_mio_uart2_dll_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_dll cvmx_mio_uart2_dll_t;
+
+/**
+ * cvmx_mio_uart2_far
+ */
+union cvmx_mio_uart2_far
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_far_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t far                          : 1;  /**< FIFO Access Register */
+#else
+	uint64_t far                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uart2_far_s           cn52xx;
+	struct cvmx_mio_uart2_far_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_far cvmx_mio_uart2_far_t;
+
+/**
+ * cvmx_mio_uart2_fcr
+ */
+union cvmx_mio_uart2_fcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_fcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rxtrig                       : 2;  /**< RX Trigger */
+	uint64_t txtrig                       : 2;  /**< TX Trigger */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txfr                         : 1;  /**< TX FIFO reset */
+	uint64_t rxfr                         : 1;  /**< RX FIFO reset */
+	uint64_t en                           : 1;  /**< FIFO enable */
+#else
+	uint64_t en                           : 1;
+	uint64_t rxfr                         : 1;
+	uint64_t txfr                         : 1;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t txtrig                       : 2;
+	uint64_t rxtrig                       : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_fcr_s           cn52xx;
+	struct cvmx_mio_uart2_fcr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_fcr cvmx_mio_uart2_fcr_t;
+
+/**
+ * cvmx_mio_uart2_htx
+ */
+union cvmx_mio_uart2_htx
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_htx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t htx                          : 1;  /**< Halt TX */
+#else
+	uint64_t htx                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uart2_htx_s           cn52xx;
+	struct cvmx_mio_uart2_htx_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_htx cvmx_mio_uart2_htx_t;
+
+/**
+ * cvmx_mio_uart2_ier
+ */
+union cvmx_mio_uart2_ier
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_ier_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ptime                        : 1;  /**< Programmable THRE Interrupt mode enable */
+	uint64_t reserved_4_6                 : 3;
+	uint64_t edssi                        : 1;  /**< Enable Modem Status Interrupt */
+	uint64_t elsi                         : 1;  /**< Enable Receiver Line Status Interrupt */
+	uint64_t etbei                        : 1;  /**< Enable Transmitter Holding Register Empty Interrupt */
+	uint64_t erbfi                        : 1;  /**< Enable Received Data Available Interrupt */
+#else
+	uint64_t erbfi                        : 1;
+	uint64_t etbei                        : 1;
+	uint64_t elsi                         : 1;
+	uint64_t edssi                        : 1;
+	uint64_t reserved_4_6                 : 3;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_ier_s           cn52xx;
+	struct cvmx_mio_uart2_ier_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_ier cvmx_mio_uart2_ier_t;
+
+/**
+ * cvmx_mio_uart2_iir
+ */
+union cvmx_mio_uart2_iir
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_iir_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t fen                          : 2;  /**< FIFO-enabled bits */
+	uint64_t reserved_4_5                 : 2;
+	uint64_t iid                          : 4;  /**< Interrupt ID */
+#else
+	uint64_t iid                          : 4;
+	uint64_t reserved_4_5                 : 2;
+	uint64_t fen                          : 2;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_iir_s           cn52xx;
+	struct cvmx_mio_uart2_iir_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_iir cvmx_mio_uart2_iir_t;
+
+/**
+ * cvmx_mio_uart2_lcr
+ */
+union cvmx_mio_uart2_lcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_lcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dlab                         : 1;  /**< Divisor Latch Address bit */
+	uint64_t brk                          : 1;  /**< Break Control bit */
+	uint64_t reserved_5_5                 : 1;
+	uint64_t eps                          : 1;  /**< Even Parity Select bit */
+	uint64_t pen                          : 1;  /**< Parity Enable bit */
+	uint64_t stop                         : 1;  /**< Stop Control bit */
+	uint64_t cls                          : 2;  /**< Character Length Select */
+#else
+	uint64_t cls                          : 2;
+	uint64_t stop                         : 1;
+	uint64_t pen                          : 1;
+	uint64_t eps                          : 1;
+	uint64_t reserved_5_5                 : 1;
+	uint64_t brk                          : 1;
+	uint64_t dlab                         : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_lcr_s           cn52xx;
+	struct cvmx_mio_uart2_lcr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_lcr cvmx_mio_uart2_lcr_t;
+
+/**
+ * cvmx_mio_uart2_lsr
+ */
+union cvmx_mio_uart2_lsr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_lsr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ferr                         : 1;  /**< Error in Receiver FIFO bit */
+	uint64_t temt                         : 1;  /**< Transmitter Empty bit */
+	uint64_t thre                         : 1;  /**< Transmitter Holding Register Empty bit */
+	uint64_t bi                           : 1;  /**< Break Interrupt bit */
+	uint64_t fe                           : 1;  /**< Framing Error bit */
+	uint64_t pe                           : 1;  /**< Parity Error bit */
+	uint64_t oe                           : 1;  /**< Overrun Error bit */
+	uint64_t dr                           : 1;  /**< Data Ready bit */
+#else
+	uint64_t dr                           : 1;
+	uint64_t oe                           : 1;
+	uint64_t pe                           : 1;
+	uint64_t fe                           : 1;
+	uint64_t bi                           : 1;
+	uint64_t thre                         : 1;
+	uint64_t temt                         : 1;
+	uint64_t ferr                         : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_lsr_s           cn52xx;
+	struct cvmx_mio_uart2_lsr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_lsr cvmx_mio_uart2_lsr_t;
+
+/**
+ * cvmx_mio_uart2_mcr
+ */
+union cvmx_mio_uart2_mcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_mcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t afce                         : 1;  /**< Auto Flow Control Enable bit */
+	uint64_t loop                         : 1;  /**< Loopback bit */
+	uint64_t out2                         : 1;  /**< OUT2 output bit */
+	uint64_t out1                         : 1;  /**< OUT1 output bit */
+	uint64_t rts                          : 1;  /**< Request To Send output bit */
+	uint64_t dtr                          : 1;  /**< Data Terminal Ready output bit */
+#else
+	uint64_t dtr                          : 1;
+	uint64_t rts                          : 1;
+	uint64_t out1                         : 1;
+	uint64_t out2                         : 1;
+	uint64_t loop                         : 1;
+	uint64_t afce                         : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_mio_uart2_mcr_s           cn52xx;
+	struct cvmx_mio_uart2_mcr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_mcr cvmx_mio_uart2_mcr_t;
+
+/**
+ * cvmx_mio_uart2_msr
+ */
+union cvmx_mio_uart2_msr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_msr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t dcd                          : 1;  /**< Data Carrier Detect input bit */
+	uint64_t ri                           : 1;  /**< Ring Indicator input bit */
+	uint64_t dsr                          : 1;  /**< Data Set Ready input bit */
+	uint64_t cts                          : 1;  /**< Clear To Send input bit */
+	uint64_t ddcd                         : 1;  /**< Delta Data Carrier Detect bit */
+	uint64_t teri                         : 1;  /**< Trailing Edge of Ring Indicator bit */
+	uint64_t ddsr                         : 1;  /**< Delta Data Set Ready bit */
+	uint64_t dcts                         : 1;  /**< Delta Clear To Send bit */
+#else
+	uint64_t dcts                         : 1;
+	uint64_t ddsr                         : 1;
+	uint64_t teri                         : 1;
+	uint64_t ddcd                         : 1;
+	uint64_t cts                          : 1;
+	uint64_t dsr                          : 1;
+	uint64_t ri                           : 1;
+	uint64_t dcd                          : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_msr_s           cn52xx;
+	struct cvmx_mio_uart2_msr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_msr cvmx_mio_uart2_msr_t;
+
+/**
+ * cvmx_mio_uart2_rbr
+ */
+union cvmx_mio_uart2_rbr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_rbr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rbr                          : 8;  /**< Receive Buffer Register */
+#else
+	uint64_t rbr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_rbr_s           cn52xx;
+	struct cvmx_mio_uart2_rbr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_rbr cvmx_mio_uart2_rbr_t;
+
+/**
+ * cvmx_mio_uart2_rfl
+ */
+union cvmx_mio_uart2_rfl
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_rfl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t rfl                          : 7;  /**< Receive FIFO Level Register */
+#else
+	uint64_t rfl                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_uart2_rfl_s           cn52xx;
+	struct cvmx_mio_uart2_rfl_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_rfl cvmx_mio_uart2_rfl_t;
+
+/**
+ * cvmx_mio_uart2_rfw
+ */
+union cvmx_mio_uart2_rfw
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_rfw_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t rffe                         : 1;  /**< Receive FIFO Framing Error */
+	uint64_t rfpe                         : 1;  /**< Receive FIFO Parity Error */
+	uint64_t rfwd                         : 8;  /**< Receive FIFO Write Data */
+#else
+	uint64_t rfwd                         : 8;
+	uint64_t rfpe                         : 1;
+	uint64_t rffe                         : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_mio_uart2_rfw_s           cn52xx;
+	struct cvmx_mio_uart2_rfw_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_rfw cvmx_mio_uart2_rfw_t;
+
+/**
+ * cvmx_mio_uart2_sbcr
+ */
+union cvmx_mio_uart2_sbcr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_sbcr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t sbcr                         : 1;  /**< Shadow Break Control */
+#else
+	uint64_t sbcr                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uart2_sbcr_s          cn52xx;
+	struct cvmx_mio_uart2_sbcr_s          cn52xxp1;
+};
+typedef union cvmx_mio_uart2_sbcr cvmx_mio_uart2_sbcr_t;
+
+/**
+ * cvmx_mio_uart2_scr
+ */
+union cvmx_mio_uart2_scr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_scr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t scr                          : 8;  /**< Scratchpad Register */
+#else
+	uint64_t scr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_scr_s           cn52xx;
+	struct cvmx_mio_uart2_scr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_scr cvmx_mio_uart2_scr_t;
+
+/**
+ * cvmx_mio_uart2_sfe
+ */
+union cvmx_mio_uart2_sfe
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_sfe_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t sfe                          : 1;  /**< Shadow FIFO Enable */
+#else
+	uint64_t sfe                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uart2_sfe_s           cn52xx;
+	struct cvmx_mio_uart2_sfe_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_sfe cvmx_mio_uart2_sfe_t;
+
+/**
+ * cvmx_mio_uart2_srr
+ */
+union cvmx_mio_uart2_srr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_srr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t stfr                         : 1;  /**< Shadow TX FIFO Reset */
+	uint64_t srfr                         : 1;  /**< Shadow RX FIFO Reset */
+	uint64_t usr                          : 1;  /**< UART Soft Reset */
+#else
+	uint64_t usr                          : 1;
+	uint64_t srfr                         : 1;
+	uint64_t stfr                         : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_mio_uart2_srr_s           cn52xx;
+	struct cvmx_mio_uart2_srr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_srr cvmx_mio_uart2_srr_t;
+
+/**
+ * cvmx_mio_uart2_srt
+ */
+union cvmx_mio_uart2_srt
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_srt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t srt                          : 2;  /**< Shadow RX Trigger */
+#else
+	uint64_t srt                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_uart2_srt_s           cn52xx;
+	struct cvmx_mio_uart2_srt_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_srt cvmx_mio_uart2_srt_t;
+
+/**
+ * cvmx_mio_uart2_srts
+ */
+union cvmx_mio_uart2_srts
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_srts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t srts                         : 1;  /**< Shadow Request To Send */
+#else
+	uint64_t srts                         : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_mio_uart2_srts_s          cn52xx;
+	struct cvmx_mio_uart2_srts_s          cn52xxp1;
+};
+typedef union cvmx_mio_uart2_srts cvmx_mio_uart2_srts_t;
+
+/**
+ * cvmx_mio_uart2_stt
+ */
+union cvmx_mio_uart2_stt
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_stt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t stt                          : 2;  /**< Shadow TX Trigger */
+#else
+	uint64_t stt                          : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_mio_uart2_stt_s           cn52xx;
+	struct cvmx_mio_uart2_stt_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_stt cvmx_mio_uart2_stt_t;
+
+/**
+ * cvmx_mio_uart2_tfl
+ */
+union cvmx_mio_uart2_tfl
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_tfl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t tfl                          : 7;  /**< Transmit FIFO Level Register */
+#else
+	uint64_t tfl                          : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_mio_uart2_tfl_s           cn52xx;
+	struct cvmx_mio_uart2_tfl_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_tfl cvmx_mio_uart2_tfl_t;
+
+/**
+ * cvmx_mio_uart2_tfr
+ */
+union cvmx_mio_uart2_tfr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_tfr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t tfr                          : 8;  /**< Transmit FIFO Read Register */
+#else
+	uint64_t tfr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_tfr_s           cn52xx;
+	struct cvmx_mio_uart2_tfr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_tfr cvmx_mio_uart2_tfr_t;
+
+/**
+ * cvmx_mio_uart2_thr
+ */
+union cvmx_mio_uart2_thr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t thr                          : 8;  /**< Transmit Holding Register */
+#else
+	uint64_t thr                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mio_uart2_thr_s           cn52xx;
+	struct cvmx_mio_uart2_thr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_thr cvmx_mio_uart2_thr_t;
+
+/**
+ * cvmx_mio_uart2_usr
+ */
+union cvmx_mio_uart2_usr
+{
+	uint64_t u64;
+	struct cvmx_mio_uart2_usr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t rff                          : 1;  /**< RX FIFO Full */
+	uint64_t rfne                         : 1;  /**< RX FIFO Not Empty */
+	uint64_t tfe                          : 1;  /**< TX FIFO Empty */
+	uint64_t tfnf                         : 1;  /**< TX FIFO Not Full */
+	uint64_t busy                         : 1;  /**< Busy bit (always 0 in PASS3) */
+#else
+	uint64_t busy                         : 1;
+	uint64_t tfnf                         : 1;
+	uint64_t tfe                          : 1;
+	uint64_t rfne                         : 1;
+	uint64_t rff                          : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_mio_uart2_usr_s           cn52xx;
+	struct cvmx_mio_uart2_usr_s           cn52xxp1;
+};
+typedef union cvmx_mio_uart2_usr cvmx_mio_uart2_usr_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-mio.h b/sys/contrib/octeon-sdk/cvmx-mio.h
deleted file mode 100644
index ee85968..0000000
--- a/sys/contrib/octeon-sdk/cvmx-mio.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-
-/**
- * @file
- *
- * Interface to the MIO hardware.
- *
- * <hr>$Revision: 41586 $<hr>
- */
-
-#ifndef __CVMX_MIO_H__
-#define __CVMX_MIO_H__
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif
-
diff --git a/sys/contrib/octeon-sdk/cvmx-mixx-defs.h b/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
new file mode 100644
index 0000000..c5d0274
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
@@ -0,0 +1,1447 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-mixx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon mixx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_MIXX_TYPEDEFS_H__
+#define __CVMX_MIXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048;
+}
+#else
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
+#endif
+
+/**
+ * cvmx_mix#_bist
+ *
+ * MIX_BIST = MIX BIST Register
+ *
+ * Description:
+ *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_bist
+{
+	uint64_t u64;
+	struct cvmx_mixx_bist_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t opfdat                       : 1;  /**< Bist Results for AGO OPF Buffer RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mrgdat                       : 1;  /**< Bist Results for AGI MRG Buffer RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t orfdat                       : 1;
+	uint64_t irfdat                       : 1;
+	uint64_t ipfdat                       : 1;
+	uint64_t mrqdat                       : 1;
+	uint64_t mrgdat                       : 1;
+	uint64_t opfdat                       : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_mixx_bist_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t orfdat                       : 1;
+	uint64_t irfdat                       : 1;
+	uint64_t ipfdat                       : 1;
+	uint64_t mrqdat                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_bist_cn52xx          cn52xxp1;
+	struct cvmx_mixx_bist_cn52xx          cn56xx;
+	struct cvmx_mixx_bist_cn52xx          cn56xxp1;
+	struct cvmx_mixx_bist_s               cn63xx;
+	struct cvmx_mixx_bist_s               cn63xxp1;
+};
+typedef union cvmx_mixx_bist cvmx_mixx_bist_t;
+
+/**
+ * cvmx_mix#_ctl
+ *
+ * MIX_CTL = MIX Control Register
+ *
+ * Description:
+ *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_ctl
+{
+	uint64_t u64;
+	struct cvmx_mixx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t ts_thresh                    : 4;  /**< TimeStamp Interrupt Threshold
+                                                         When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT]
+                                                         is greater than MIX_CTL[TS_THRESH], then a programmable
+                                                         TimeStamp Interrupt is issued (see MIX_INTR[TS]
+                                                         MIX_INTENA[TSENA]).
+                                                         SWNOTE: For o63, since the implementation only supports
+                                                         4 oustanding timestamp interrupts, this field should
+                                                         only be programmed from [0..3]. */
+	uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
+                                                         When enabled, the last 4 bytes(CRC) of the ingress packet
+                                                         are not included in cumulative packet byte length.
+                                                         In other words, the cumulative LEN field for all
+                                                         I-Ring Buffer Entries associated with a given ingress
+                                                         packet will be 4 bytes less (so that the final 4B HW CRC
+                                                         packet data is not processed by software). */
+	uint64_t busy                         : 1;  /**< MIX Busy Status bit
+                                                         MIX will assert busy status any time there are:
+                                                           1) L2/DRAM reads in-flight (NCB-arb to read
+                                                              response)
+                                                           2) L2/DRAM writes in-flight (NCB-arb to write
+                                                              data is sent.
+                                                           3) L2/DRAM write commits in-flight (NCB-arb to write
+                                                              commit response).
+                                                         NOTE: After MIX_CTL[EN]=0, the MIX will eventually
+                                                         complete any "inflight" transactions, at which point the
+                                                         BUSY will de-assert. */
+	uint64_t en                           : 1;  /**< MIX Enable bit
+                                                         When EN=0, MIX will no longer arbitrate for
+                                                         any new L2/DRAM read/write requests on the NCB Bus.
+                                                         MIX will complete any requests that are currently
+                                                         pended for the NCB Bus. */
+	uint64_t reset                        : 1;  /**< MIX Soft Reset
+                                                          When SW writes a '1' to MIX_CTL[RESET], the
+                                                          MII-MIX/AGL logic will execute a soft reset.
+                                                          NOTE: During a soft reset, CSR accesses are not effected.
+                                                          However, the values of the CSR fields will be effected by
+                                                          soft reset (except MIX_CTL[RESET] itself).
+                                                          NOTE: After power-on, the MII-AGL/MIX are held in reset
+                                                          until the MIX_CTL[RESET] is written to zero.
+                                                          The intended "soft reset" sequence is: (please also
+                                                          refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
+                                                             1) Write MIX_CTL[EN]=0
+                                                                [To prevent any NEW transactions from being started]
+                                                             2) Wait for MIX_CTL[BUSY]=0
+                                                                [To indicate that all inflight transactions have
+                                                                 completed]
+                                                             3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
+                                                                and wait for the result.
+                                                             4) Re-Initialize the MIX/AGL just as would be done
+                                                                for a hard reset.
+                                                         NOTE: Once the MII has been soft-reset, please refer to HRM Section
+                                                         12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
+                                                         re-initialization sequence. */
+	uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
+                                                         (0: Big Endian Mode/1: Little Endian Mode)
+                                                         When the mode is set, MIX will byte-swap packet data
+                                                         loads/stores at the MIX/NCB boundary. */
+	uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
+                                                         When set to zero, the arbiter is fixed priority with
+                                                         the following priority scheme:
+                                                             Highest Priority: I-Ring Packet Write Request
+                                                                               O-Ring Packet Read Request
+                                                                               I-Ring Entry Write Request
+                                                                               I-Ring Entry Read Request
+                                                                               O-Ring Entry Read Request
+                                                         When set to one, the arbiter is round robin. */
+	uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
+                                                         The MRQ contains 16 CB-Requests which are CSR Rd/Wr
+                                                         Requests. If the MRQ backs up with "HWM" entries,
+                                                         then new CB-Requests are 'stalled'.
+                                                            [0]: HWM = 11
+                                                            [1]: HWM = 10
+                                                            [2]: HWM = 9
+                                                            [3]: HWM = 8
+                                                         NOTE: This must only be written at power-on/boot time. */
+#else
+	uint64_t mrq_hwm                      : 2;
+	uint64_t nbtarb                       : 1;
+	uint64_t lendian                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t en                           : 1;
+	uint64_t busy                         : 1;
+	uint64_t crc_strip                    : 1;
+	uint64_t ts_thresh                    : 4;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_mixx_ctl_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
+                                                         When enabled, the last 4 bytes(CRC) of the ingress packet
+                                                         are not included in cumulative packet byte length.
+                                                         In other words, the cumulative LEN field for all
+                                                         I-Ring Buffer Entries associated with a given ingress
+                                                         packet will be 4 bytes less (so that the final 4B HW CRC
+                                                         packet data is not processed by software). */
+	uint64_t busy                         : 1;  /**< MIX Busy Status bit
+                                                         MIX will assert busy status any time there are:
+                                                           1) L2/DRAM reads in-flight (NCB-arb to read
+                                                              response)
+                                                           2) L2/DRAM writes in-flight (NCB-arb to write
+                                                              data is sent.
+                                                           3) L2/DRAM write commits in-flight (NCB-arb to write
+                                                              commit response).
+                                                         NOTE: After MIX_CTL[EN]=0, the MIX will eventually
+                                                         complete any "inflight" transactions, at which point the
+                                                         BUSY will de-assert. */
+	uint64_t en                           : 1;  /**< MIX Enable bit
+                                                         When EN=0, MIX will no longer arbitrate for
+                                                         any new L2/DRAM read/write requests on the NCB Bus.
+                                                         MIX will complete any requests that are currently
+                                                         pended for the NCB Bus. */
+	uint64_t reset                        : 1;  /**< MIX Soft Reset
+                                                          When SW writes a '1' to MIX_CTL[RESET], the
+                                                          MII-MIX/AGL logic will execute a soft reset.
+                                                          NOTE: During a soft reset, CSR accesses are not effected.
+                                                          However, the values of the CSR fields will be effected by
+                                                          soft reset (except MIX_CTL[RESET] itself).
+                                                          NOTE: After power-on, the MII-AGL/MIX are held in reset
+                                                          until the MIX_CTL[RESET] is written to zero.
+                                                          The intended "soft reset" sequence is: (please also
+                                                          refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
+                                                             1) Write MIX_CTL[EN]=0
+                                                                [To prevent any NEW transactions from being started]
+                                                             2) Wait for MIX_CTL[BUSY]=0
+                                                                [To indicate that all inflight transactions have
+                                                                 completed]
+                                                             3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
+                                                                and wait for the result.
+                                                             4) Re-Initialize the MIX/AGL just as would be done
+                                                                for a hard reset.
+                                                         NOTE: Once the MII has been soft-reset, please refer to HRM Section
+                                                         12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
+                                                         re-initialization sequence. */
+	uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
+                                                         (0: Big Endian Mode/1: Little Endian Mode)
+                                                         When the mode is set, MIX will byte-swap packet data
+                                                         loads/stores at the MIX/NCB boundary. */
+	uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
+                                                         When set to zero, the arbiter is fixed priority with
+                                                         the following priority scheme:
+                                                             Highest Priority: I-Ring Packet Write Request
+                                                                               O-Ring Packet Read Request
+                                                                               I-Ring Entry Write Request
+                                                                               I-Ring Entry Read Request
+                                                                               O-Ring Entry Read Request
+                                                         When set to one, the arbiter is round robin. */
+	uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
+                                                         The MRQ contains 16 CB-Requests which are CSR Rd/Wr
+                                                         Requests. If the MRQ backs up with "HWM" entries,
+                                                         then new CB-Requests are 'stalled'.
+                                                            [0]: HWM = 11
+                                                            [1]: HWM = 10
+                                                            [2]: HWM = 9
+                                                            [3]: HWM = 8
+                                                         NOTE: This must only be written at power-on/boot time. */
+#else
+	uint64_t mrq_hwm                      : 2;
+	uint64_t nbtarb                       : 1;
+	uint64_t lendian                      : 1;
+	uint64_t reset                        : 1;
+	uint64_t en                           : 1;
+	uint64_t busy                         : 1;
+	uint64_t crc_strip                    : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_ctl_cn52xx           cn52xxp1;
+	struct cvmx_mixx_ctl_cn52xx           cn56xx;
+	struct cvmx_mixx_ctl_cn52xx           cn56xxp1;
+	struct cvmx_mixx_ctl_s                cn63xx;
+	struct cvmx_mixx_ctl_s                cn63xxp1;
+};
+typedef union cvmx_mixx_ctl cvmx_mixx_ctl_t;
+
+/**
+ * cvmx_mix#_intena
+ *
+ * MIX_INTENA = MIX Local Interrupt Enable Mask Register
+ *
+ * Description:
+ *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_intena
+{
+	uint64_t u64;
+	struct cvmx_mixx_intena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t tsena                        : 1;  /**< TimeStamp Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Ring with Timestamp
+                                                         event (see: MIX_ISR[TS]). */
+	uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an ORCNT underflow condition
+                                                         MIX_ISR[ORUN]. */
+	uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an IRCNT underflow condition
+                                                         MIX_ISR[IRUN]. */
+	uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
+                                                         enable. If both the global interrupt mask bits
+                                                         (CIU_INTx_EN*[MII]) and the local interrupt mask
+                                                         bit(DATA_DRPENA) is set, than an interrupt is
+                                                         reported for this event. */
+	uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Ring Threshold
+                                                         Exceeded event(IRTHRESH). */
+	uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Ring Threshold
+                                                         Exceeded event(ORTHRESH). */
+	uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Doorbell Overflow
+                                                         event(IDBOVF). */
+	uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Doorbell Overflow
+                                                         event(ODBOVF). */
+#else
+	uint64_t ovfena                       : 1;
+	uint64_t ivfena                       : 1;
+	uint64_t othena                       : 1;
+	uint64_t ithena                       : 1;
+	uint64_t data_drpena                  : 1;
+	uint64_t irunena                      : 1;
+	uint64_t orunena                      : 1;
+	uint64_t tsena                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mixx_intena_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an ORCNT underflow condition
+                                                         MIX_ISR[ORUN]. */
+	uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an IRCNT underflow condition
+                                                         MIX_ISR[IRUN]. */
+	uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
+                                                         enable. If both the global interrupt mask bits
+                                                         (CIU_INTx_EN*[MII]) and the local interrupt mask
+                                                         bit(DATA_DRPENA) is set, than an interrupt is
+                                                         reported for this event. */
+	uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Ring Threshold
+                                                         Exceeded event(IRTHRESH). */
+	uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Ring Threshold
+                                                         Exceeded event(ORTHRESH). */
+	uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Doorbell Overflow
+                                                         event(IDBOVF). */
+	uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Doorbell Overflow
+                                                         event(ODBOVF). */
+#else
+	uint64_t ovfena                       : 1;
+	uint64_t ivfena                       : 1;
+	uint64_t othena                       : 1;
+	uint64_t ithena                       : 1;
+	uint64_t data_drpena                  : 1;
+	uint64_t irunena                      : 1;
+	uint64_t orunena                      : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_intena_cn52xx        cn52xxp1;
+	struct cvmx_mixx_intena_cn52xx        cn56xx;
+	struct cvmx_mixx_intena_cn52xx        cn56xxp1;
+	struct cvmx_mixx_intena_s             cn63xx;
+	struct cvmx_mixx_intena_s             cn63xxp1;
+};
+typedef union cvmx_mixx_intena cvmx_mixx_intena_t;
+
+/**
+ * cvmx_mix#_ircnt
+ *
+ * MIX_IRCNT = MIX I-Ring Pending Packet Counter
+ *
+ * Description:
+ *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_ircnt
+{
+	uint64_t u64;
+	struct cvmx_mixx_ircnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t ircnt                        : 20; /**< Pending \# of I-Ring Packets.
+                                                         Whenever HW writes a completion code of Done, Trunc,
+                                                         CRCErr or Err, it increments the IRCNT (to indicate
+                                                         to SW the \# of pending Input packets in system memory).
+                                                         NOTE: The HW guarantees that the completion code write
+                                                         is always visible in system memory BEFORE it increments
+                                                         the IRCNT.
+                                                         Reads of IRCNT return the current inbound packet count.
+                                                         Writes of IRCNT decrement the count by the value
+                                                         written.
+                                                         This register is used to generate interrupts to alert
+                                                         SW of pending inbound MIX packets in system memory.
+                                                         NOTE: In the case of inbound packets that span multiple
+                                                         I-Ring entries, SW must keep track of the \# of I-Ring Entries
+                                                         associated with a given inbound packet to reclaim the
+                                                         proper \# of I-Ring Entries for re-use. */
+#else
+	uint64_t ircnt                        : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_mixx_ircnt_s              cn52xx;
+	struct cvmx_mixx_ircnt_s              cn52xxp1;
+	struct cvmx_mixx_ircnt_s              cn56xx;
+	struct cvmx_mixx_ircnt_s              cn56xxp1;
+	struct cvmx_mixx_ircnt_s              cn63xx;
+	struct cvmx_mixx_ircnt_s              cn63xxp1;
+};
+typedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t;
+
+/**
+ * cvmx_mix#_irhwm
+ *
+ * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register
+ *
+ * Description:
+ *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_irhwm
+{
+	uint64_t u64;
+	struct cvmx_mixx_irhwm_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t ibplwm                       : 20; /**< I-Ring BackPressure Low Water Mark Threshold.
+                                                         When the \#of available I-Ring Entries (IDBELL)
+                                                         is less than IBPLWM, the AGL-MAC will:
+                                                           a) In full-duplex mode: send periodic PAUSE packets.
+                                                           b) In half-duplex mode: Force collisions.
+                                                         This programmable mechanism is provided as a means
+                                                         to backpressure input traffic 'early' enough (so
+                                                         that packets are not 'dropped' by OCTEON). */
+	uint64_t irhwm                        : 20; /**< I-Ring Entry High Water Mark Threshold.
+                                                         Used to determine when the \# of Inbound packets
+                                                         in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
+                                                         threshold.
+                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         interrupt enable bits is zero and must be enabled
+                                                         to allow interrupts to be reported. */
+#else
+	uint64_t irhwm                        : 20;
+	uint64_t ibplwm                       : 20;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_mixx_irhwm_s              cn52xx;
+	struct cvmx_mixx_irhwm_s              cn52xxp1;
+	struct cvmx_mixx_irhwm_s              cn56xx;
+	struct cvmx_mixx_irhwm_s              cn56xxp1;
+	struct cvmx_mixx_irhwm_s              cn63xx;
+	struct cvmx_mixx_irhwm_s              cn63xxp1;
+};
+typedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t;
+
+/**
+ * cvmx_mix#_iring1
+ *
+ * MIX_IRING1 = MIX Inbound Ring Register \#1
+ *
+ * Description:
+ *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_iring1
+{
+	uint64_t u64;
+	struct cvmx_mixx_iring1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when IDBELL/IRCNT=0). */
+	uint64_t ibase                        : 37; /**< Represents the 8B-aligned base address of the first
+                                                         Inbound Ring entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t ibase                        : 37;
+	uint64_t isize                        : 20;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_mixx_iring1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when IDBELL/IRCNT=0). */
+	uint64_t reserved_36_39               : 4;
+	uint64_t ibase                        : 33; /**< Represents the 8B-aligned base address of the first
+                                                         Inbound Ring entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t ibase                        : 33;
+	uint64_t reserved_36_39               : 4;
+	uint64_t isize                        : 20;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_iring1_cn52xx        cn52xxp1;
+	struct cvmx_mixx_iring1_cn52xx        cn56xx;
+	struct cvmx_mixx_iring1_cn52xx        cn56xxp1;
+	struct cvmx_mixx_iring1_s             cn63xx;
+	struct cvmx_mixx_iring1_s             cn63xxp1;
+};
+typedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t;
+
+/**
+ * cvmx_mix#_iring2
+ *
+ * MIX_IRING2 = MIX Inbound Ring Register \#2
+ *
+ * Description:
+ *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_iring2
+{
+	uint64_t u64;
+	struct cvmx_mixx_iring2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_52_63               : 12;
+	uint64_t itlptr                       : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring
+                                                         Entry that the HW will process next. After the HW
+                                                         completes receiving an inbound packet, it increments
+                                                         the I-Ring Tail Pointer. [NOTE: The I-Ring Tail
+                                                         Pointer HW increment is always modulo ISIZE.
+                                                         NOTE: This field is 'read-only' to SW. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t idbell                       : 20; /**< Represents the cumulative total of pending
+                                                         Inbound Ring Buffer Entries. Each I-Ring
+                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
+                                                         along with a 2) a Byte Length.
+                                                         After SW inserts a new entry into the I-Ring Buffer,
+                                                         it "rings the doorbell for the inbound ring". When
+                                                         the MIX HW receives the doorbell ring, it advances
+                                                         the doorbell count for the I-Ring.
+                                                         SW must never cause the doorbell count for the
+                                                         I-Ring to exceed the size of the I-ring(ISIZE).
+                                                         A read of the CSR indicates the current doorbell
+                                                         count. */
+#else
+	uint64_t idbell                       : 20;
+	uint64_t reserved_20_31               : 12;
+	uint64_t itlptr                       : 20;
+	uint64_t reserved_52_63               : 12;
+#endif
+	} s;
+	struct cvmx_mixx_iring2_s             cn52xx;
+	struct cvmx_mixx_iring2_s             cn52xxp1;
+	struct cvmx_mixx_iring2_s             cn56xx;
+	struct cvmx_mixx_iring2_s             cn56xxp1;
+	struct cvmx_mixx_iring2_s             cn63xx;
+	struct cvmx_mixx_iring2_s             cn63xxp1;
+};
+typedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t;
+
+/**
+ * cvmx_mix#_isr
+ *
+ * MIX_ISR = MIX Interrupt/Status Register
+ *
+ * Description:
+ *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_isr
+{
+	uint64_t u64;
+	struct cvmx_mixx_isr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ts                           : 1;  /**< TimeStamp Interrupt
+                                                         When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT])
+                                                         is greater than the TimeStamp Interrupt Threshold
+                                                         (MIX_CTL[TS_THRESH]) value this interrupt bit is set.
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Ring with Timestamp
+                                                         event (see: MIX_INTENA[TSENA]). */
+	uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_ORCNT[ORCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
+                                                         NOTE: If an ORUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+	uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_IRCNT[IRCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
+                                                         NOTE: If an IRUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+	uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
+                                                         If this does occur, the DATA_DRP is set and the
+                                                         CIU_INTx_SUM0,4[MII] bits are set.
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(DATA_DRPENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
+                                                         When the pending \#inbound packets in system
+                                                         memory(IRCNT) has exceeded a programmable threshold
+                                                         (IRHWM), then this bit is set. If this does occur,
+                                                         the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(ITHENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
+                                                         When the pending \#outbound packets in system
+                                                         memory(ORCNT) has exceeded a programmable threshold
+                                                         (ORHWM), then this bit is set. If this does occur,
+                                                         the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OTHENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_IRING2[IDBELL]
+                                                         with a value greater than the remaining \#of
+                                                         I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_IRING2[IDBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(IVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of IDBELL writes),  and ensure that
+                                                         future IDBELL writes don't exceed the size of the
+                                                         I-Ring Buffer (MIX_IRING2[ISIZE]).
+                                                         SW must reclaim I-Ring Entries by keeping track of the
+                                                         \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
+                                                         NOTE: The MIX_IRCNT[IRCNT] register represents the
+                                                         total \#packets(not IRing Entries) and SW must further
+                                                         keep track of the \# of I-Ring Entries associated with
+                                                         each packet as they are processed.
+                                                         NOTE: There is no recovery from an IDBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the I-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+	uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_ORING2[ODBELL]
+                                                         with a value greater than the remaining \#of
+                                                         O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_ORING2[ODBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of ODBELL writes),  and ensure that
+                                                         future ODBELL writes don't exceed the size of the
+                                                         O-Ring Buffer (MIX_ORING2[OSIZE]).
+                                                         SW must reclaim O-Ring Entries by writing to the
+                                                         MIX_ORCNT[ORCNT]. .
+                                                         NOTE: There is no recovery from an ODBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the O-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+#else
+	uint64_t odblovf                      : 1;
+	uint64_t idblovf                      : 1;
+	uint64_t orthresh                     : 1;
+	uint64_t irthresh                     : 1;
+	uint64_t data_drp                     : 1;
+	uint64_t irun                         : 1;
+	uint64_t orun                         : 1;
+	uint64_t ts                           : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mixx_isr_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_ORCNT[ORCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
+                                                         NOTE: If an ORUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+	uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_IRCNT[IRCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
+                                                         NOTE: If an IRUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+	uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
+                                                         If this does occur, the DATA_DRP is set and the
+                                                         CIU_INTx_SUM0,4[MII] bits are set.
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(DATA_DRPENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
+                                                         When the pending \#inbound packets in system
+                                                         memory(IRCNT) has exceeded a programmable threshold
+                                                         (IRHWM), then this bit is set. If this does occur,
+                                                         the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(ITHENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
+                                                         When the pending \#outbound packets in system
+                                                         memory(ORCNT) has exceeded a programmable threshold
+                                                         (ORHWM), then this bit is set. If this does occur,
+                                                         the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OTHENA) is set, than an
+                                                         interrupt is reported for this event. */
+	uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_IRING2[IDBELL]
+                                                         with a value greater than the remaining \#of
+                                                         I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_IRING2[IDBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(IVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of IDBELL writes),  and ensure that
+                                                         future IDBELL writes don't exceed the size of the
+                                                         I-Ring Buffer (MIX_IRING2[ISIZE]).
+                                                         SW must reclaim I-Ring Entries by keeping track of the
+                                                         \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
+                                                         NOTE: The MIX_IRCNT[IRCNT] register represents the
+                                                         total \#packets(not IRing Entries) and SW must further
+                                                         keep track of the \# of I-Ring Entries associated with
+                                                         each packet as they are processed.
+                                                         NOTE: There is no recovery from an IDBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the I-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+	uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_ORING2[ODBELL]
+                                                         with a value greater than the remaining \#of
+                                                         O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_ORING2[ODBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of ODBELL writes),  and ensure that
+                                                         future ODBELL writes don't exceed the size of the
+                                                         O-Ring Buffer (MIX_ORING2[OSIZE]).
+                                                         SW must reclaim O-Ring Entries by writing to the
+                                                         MIX_ORCNT[ORCNT]. .
+                                                         NOTE: There is no recovery from an ODBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the O-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+#else
+	uint64_t odblovf                      : 1;
+	uint64_t idblovf                      : 1;
+	uint64_t orthresh                     : 1;
+	uint64_t irthresh                     : 1;
+	uint64_t data_drp                     : 1;
+	uint64_t irun                         : 1;
+	uint64_t orun                         : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_isr_cn52xx           cn52xxp1;
+	struct cvmx_mixx_isr_cn52xx           cn56xx;
+	struct cvmx_mixx_isr_cn52xx           cn56xxp1;
+	struct cvmx_mixx_isr_s                cn63xx;
+	struct cvmx_mixx_isr_s                cn63xxp1;
+};
+typedef union cvmx_mixx_isr cvmx_mixx_isr_t;
+
+/**
+ * cvmx_mix#_orcnt
+ *
+ * MIX_ORCNT = MIX O-Ring Packets Sent Counter
+ *
+ * Description:
+ *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_orcnt
+{
+	uint64_t u64;
+	struct cvmx_mixx_orcnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t orcnt                        : 20; /**< Pending \# of O-Ring Packets.
+                                                         Whenever HW removes a packet from the O-Ring, it
+                                                         increments the ORCNT (to indicate to SW the \# of
+                                                         Output packets in system memory that can be reclaimed).
+                                                         Reads of ORCNT return the current count.
+                                                         Writes of ORCNT decrement the count by the value
+                                                         written.
+                                                         This register is used to generate interrupts to alert
+                                                         SW of pending outbound MIX packets that have been
+                                                         removed from system memory. (see MIX_ISR[ORTHRESH]
+                                                         description for more details).
+                                                         NOTE: For outbound packets, the \# of O-Ring Packets
+                                                         is equal to the \# of O-Ring Entries. */
+#else
+	uint64_t orcnt                        : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_mixx_orcnt_s              cn52xx;
+	struct cvmx_mixx_orcnt_s              cn52xxp1;
+	struct cvmx_mixx_orcnt_s              cn56xx;
+	struct cvmx_mixx_orcnt_s              cn56xxp1;
+	struct cvmx_mixx_orcnt_s              cn63xx;
+	struct cvmx_mixx_orcnt_s              cn63xxp1;
+};
+typedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t;
+
+/**
+ * cvmx_mix#_orhwm
+ *
+ * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register
+ *
+ * Description:
+ *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_orhwm
+{
+	uint64_t u64;
+	struct cvmx_mixx_orhwm_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t orhwm                        : 20; /**< O-Ring Entry High Water Mark Threshold.
+                                                         Used to determine when the \# of Outbound packets
+                                                         in system memory that can be reclaimed
+                                                         (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
+                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         interrupt enable bits is zero and must be enabled
+                                                         to allow interrupts to be reported. */
+#else
+	uint64_t orhwm                        : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_mixx_orhwm_s              cn52xx;
+	struct cvmx_mixx_orhwm_s              cn52xxp1;
+	struct cvmx_mixx_orhwm_s              cn56xx;
+	struct cvmx_mixx_orhwm_s              cn56xxp1;
+	struct cvmx_mixx_orhwm_s              cn63xx;
+	struct cvmx_mixx_orhwm_s              cn63xxp1;
+};
+typedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t;
+
+/**
+ * cvmx_mix#_oring1
+ *
+ * MIX_ORING1 = MIX Outbound Ring Register \#1
+ *
+ * Description:
+ *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_oring1
+{
+	uint64_t u64;
+	struct cvmx_mixx_oring1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when ODBELL/ORCNT=0). */
+	uint64_t obase                        : 37; /**< Represents the 8B-aligned base address of the first
+                                                         Outbound Ring(O-Ring) Entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t obase                        : 37;
+	uint64_t osize                        : 20;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_mixx_oring1_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when ODBELL/ORCNT=0). */
+	uint64_t reserved_36_39               : 4;
+	uint64_t obase                        : 33; /**< Represents the 8B-aligned base address of the first
+                                                         Outbound Ring(O-Ring) Entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t obase                        : 33;
+	uint64_t reserved_36_39               : 4;
+	uint64_t osize                        : 20;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} cn52xx;
+	struct cvmx_mixx_oring1_cn52xx        cn52xxp1;
+	struct cvmx_mixx_oring1_cn52xx        cn56xx;
+	struct cvmx_mixx_oring1_cn52xx        cn56xxp1;
+	struct cvmx_mixx_oring1_s             cn63xx;
+	struct cvmx_mixx_oring1_s             cn63xxp1;
+};
+typedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t;
+
+/**
+ * cvmx_mix#_oring2
+ *
+ * MIX_ORING2 = MIX Outbound Ring Register \#2
+ *
+ * Description:
+ *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_oring2
+{
+	uint64_t u64;
+	struct cvmx_mixx_oring2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_52_63               : 12;
+	uint64_t otlptr                       : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring
+                                                         Entry that the HW will process next. After the HW
+                                                         completes sending an outbound packet, it increments
+                                                         the O-Ring Tail Pointer. [NOTE: The O-Ring Tail
+                                                         Pointer HW increment is always modulo
+                                                         MIX_ORING2[OSIZE].
+                                                         NOTE: This field is 'read-only' to SW. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t odbell                       : 20; /**< Represents the cumulative total of pending
+                                                         Outbound Ring(O-Ring) Buffer Entries. Each O-Ring
+                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
+                                                         along with a 2) a Byte Length.
+                                                         After SW inserts new entries into the O-Ring Buffer,
+                                                         it "rings the doorbell with the count of the newly
+                                                         inserted entries". When the MIX HW receives the
+                                                         doorbell ring, it increments the current doorbell
+                                                         count by the CSR write value.
+                                                         SW must never cause the doorbell count for the
+                                                         O-Ring to exceed the size of the ring(OSIZE).
+                                                         A read of the CSR indicates the current doorbell
+                                                         count. */
+#else
+	uint64_t odbell                       : 20;
+	uint64_t reserved_20_31               : 12;
+	uint64_t otlptr                       : 20;
+	uint64_t reserved_52_63               : 12;
+#endif
+	} s;
+	struct cvmx_mixx_oring2_s             cn52xx;
+	struct cvmx_mixx_oring2_s             cn52xxp1;
+	struct cvmx_mixx_oring2_s             cn56xx;
+	struct cvmx_mixx_oring2_s             cn56xxp1;
+	struct cvmx_mixx_oring2_s             cn63xx;
+	struct cvmx_mixx_oring2_s             cn63xxp1;
+};
+typedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t;
+
+/**
+ * cvmx_mix#_remcnt
+ *
+ * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only)
+ *
+ * Description:
+ *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_remcnt
+{
+	uint64_t u64;
+	struct cvmx_mixx_remcnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_52_63               : 12;
+	uint64_t iremcnt                      : 20; /**< Remaining I-Ring Buffer Count
+                                                         Reflects the \# of unused/remaining I-Ring Entries
+                                                         that HW  currently detects in the I-Ring Buffer.
+                                                         HW uses this value to detect I-Ring Doorbell overflows.
+                                                         (see: MIX_ISR[IDBLOVF])
+                                                         When SW writes the MIX_IRING1[ISIZE], the IREMCNT
+                                                         is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only
+                                                         be written at power-on, when it's known that there are
+                                                         no I-Ring Entries currently in use by HW).
+                                                         When SW writes to the IDBELL register, the IREMCNT
+                                                         is decremented by the CSR write value.
+                                                         When HW issues an IRing Write Request(onto NCB Bus),
+                                                         the IREMCNT is incremented by 1. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t oremcnt                      : 20; /**< Remaining O-Ring Buffer Count
+                                                         Reflects the \# of unused/remaining O-Ring Entries
+                                                         that HW  currently detects in the O-Ring Buffer.
+                                                         HW uses this value to detect O-Ring Doorbell overflows.
+                                                         (see: MIX_ISR[ODBLOVF])
+                                                         When SW writes the MIX_IRING1[OSIZE], the OREMCNT
+                                                         is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only
+                                                         be written at power-on, when it's known that there are
+                                                         no O-Ring Entries currently in use by HW).
+                                                         When SW writes to the ODBELL register, the OREMCNT
+                                                         is decremented by the CSR write value.
+                                                         When SW writes to MIX_[OREMCNT], the OREMCNT is decremented
+                                                         by the CSR write value. */
+#else
+	uint64_t oremcnt                      : 20;
+	uint64_t reserved_20_31               : 12;
+	uint64_t iremcnt                      : 20;
+	uint64_t reserved_52_63               : 12;
+#endif
+	} s;
+	struct cvmx_mixx_remcnt_s             cn52xx;
+	struct cvmx_mixx_remcnt_s             cn52xxp1;
+	struct cvmx_mixx_remcnt_s             cn56xx;
+	struct cvmx_mixx_remcnt_s             cn56xxp1;
+	struct cvmx_mixx_remcnt_s             cn63xx;
+	struct cvmx_mixx_remcnt_s             cn63xxp1;
+};
+typedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t;
+
+/**
+ * cvmx_mix#_tsctl
+ *
+ * MIX_TSCTL = MIX TimeStamp Control Register
+ *
+ * Description:
+ *  NOTE: To read the MIX_TSCTL register, a device would issue an IOBLD64 directed at the MIO.
+ *
+ * Notes:
+ * SW can read the MIX_TSCTL register to determine the \#pending timestamp interrupts(TSCNT)
+ * as well as the \#outstanding timestamp requests in flight(TSTOT), as well as the \#of available
+ * timestamp entries (TSAVL) in the timestamp fifo.
+ * A write to the MIX_TSCTL register will advance the MIX*_TSTAMP fifo head ptr by 1, and
+ * also decrements the MIX*_TSCTL[TSCNT] and MIX*_TSCTL[TSTOT] pending count(s) by 1.
+ * For example, if SW reads MIX*_TSCTL[TSCNT]=2 (2 pending timestamp interrupts), it would immediately
+ * issue this sequence:
+ *      1) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
+ *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
+ *      2) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
+ *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
+ *
+ * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored.
+ */
+union cvmx_mixx_tsctl
+{
+	uint64_t u64;
+	struct cvmx_mixx_tsctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t tsavl                        : 5;  /**< # of MIX TimeStamp Entries Available for use
+                                                         For o63: TSAVL MAX=4 (implementation
+                                                         depth of timestamp fifo)
+                                                         TSAVL = [IMPLEMENTATION_DEPTH=4(MAX) - TSCNT] */
+	uint64_t reserved_13_15               : 3;
+	uint64_t tstot                        : 5;  /**< # of pending MIX TimeStamp Requests in-flight
+                                                         For o63: TSTOT must never exceed MAX=4 (implementation
+                                                         depth of timestamp fifo) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t tscnt                        : 5;  /**< # of pending MIX TimeStamp Interrupts
+                                                         For o63: TSCNT must never exceed MAX=4 (implementation
+                                                         depth of timestamp fifo) */
+#else
+	uint64_t tscnt                        : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t tstot                        : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t tsavl                        : 5;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_mixx_tsctl_s              cn63xx;
+	struct cvmx_mixx_tsctl_s              cn63xxp1;
+};
+typedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t;
+
+/**
+ * cvmx_mix#_tstamp
+ *
+ * MIX_TSTAMP = MIX TimeStamp Register
+ *
+ * Description:
+ *  NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO.
+ */
+union cvmx_mixx_tstamp
+{
+	uint64_t u64;
+	struct cvmx_mixx_tstamp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t tstamp                       : 64; /**< MIX TimeStamp Value
+                                                          When SW sets up an ORING Entry with [47]=1(TSTAMP),
+                                                          The packet is tagged with a specal SOP w/TSTAMP flag
+                                                          as it is sent to the AGL.
+                                                          Later the AGL will send "sample" strobe(s) to capture
+                                                          a global 64bit timestamp value followed by a "commit"
+                                                          strobe which writes the last sampled value into the
+                                                          outbound Timestamp fifo (max depth=4) and increments
+                                                          the MIX_TSCTL[TSCNT] register to indicate the total
+                                                          \#of pending Timestamp interrupts.
+                                                          If the \#pending Timestamp interrupts (MIX_TSCTL[TSCNT])
+                                                          is greater than the MIX_CTL[TS_THRESH] value, then
+                                                          a programmable interrupt is also triggered (see:
+                                                          MIX_ISR[TS] MIX_INTENA[TSENA]).
+                                                          SW will then read the MIX*_TSTAMP[TSTAMP]
+                                                          register value, and MUST THEN write the MIX_TSCTL
+                                                          register, which will decrement MIX_TSCTL[TSCNT] register,
+                                                          to indicate that a single timestamp interrupt has
+                                                          been serviced.
+                                                          NOTE: The MIO-MIX HW tracks upto MAX=4 outstanding
+                                                          timestamped outbound packets at a time. All subsequent
+                                                          ORING Entries w/SOP-TSTAMP will be stalled until
+                                                          SW can service the 4 outstanding interrupts.
+                                                          SW can read the MIX_TSCTL register to determine the
+                                                          \#pending timestamp interrupts(TSCNT) as well as the
+                                                          \#outstanding timestamp requests in flight(TSTOT), as
+                                                          well as the \#of available timestamp entries (TSAVL).
+                                                         SW NOTE: A MIX_TSTAMP read when MIX_TSCTL[TSCNT]=0, will
+                                                         result in a return value of all zeroes. SW should only
+                                                         read this register when MIX_ISR[TS]=1 (or when
+                                                         MIX_TSCTL[TSCNT] != 0) to retrieve the timestamp value
+                                                         recorded by HW. If SW reads the TSTAMP when HW has not
+                                                         recorded a valid timestamp, then an  all zeroes value is
+                                                         returned. */
+#else
+	uint64_t tstamp                       : 64;
+#endif
+	} s;
+	struct cvmx_mixx_tstamp_s             cn63xx;
+	struct cvmx_mixx_tstamp_s             cn63xxp1;
+};
+typedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-mpi-defs.h b/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
new file mode 100644
index 0000000..058d845
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
@@ -0,0 +1,299 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-mpi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon mpi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_MPI_TYPEDEFS_H__
+#define __CVMX_MPI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
+static inline uint64_t CVMX_MPI_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000001000ull);
+}
+#else
+#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
+		cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
+static inline uint64_t CVMX_MPI_STS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000001008ull);
+}
+#else
+#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
+static inline uint64_t CVMX_MPI_TX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070000001010ull);
+}
+#else
+#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
+#endif
+
+/**
+ * cvmx_mpi_cfg
+ */
+union cvmx_mpi_cfg
+{
+	uint64_t u64;
+	struct cvmx_mpi_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t clkdiv                       : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
+                                                         CLKDIV = Feclk / (2 * Fsclk) */
+	uint64_t reserved_12_15               : 4;
+	uint64_t cslate                       : 1;  /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
+                                                            1, MPI_CS assert coincident with transaction
+                                                         NOTE: only used if CSENA == 1 */
+	uint64_t tritx                        : 1;  /**< If 0, MPI_TX pin is driven when slave is not
+                                                               expected to be driving
+                                                            1, MPI_TX pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+	uint64_t idleclks                     : 2;  /**< Guarantee IDLECLKS idle sclk cycles between
+                                                         commands. */
+	uint64_t cshi                         : 1;  /**< If 0, CS is low asserted
+                                                         1, CS is high asserted */
+	uint64_t csena                        : 1;  /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
+                                                         1, CS is driven per MPI_TX intruction */
+	uint64_t int_ena                      : 1;  /**< If 0, polling is required
+                                                         1, MPI engine interrupts X end of transaction */
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift MSB first
+                                                         1, shift LSB first */
+	uint64_t wireor                       : 1;  /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
+                                                               MPI_TX pin is always driven
+                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
+                                                               MPI_TX pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
+                                                               MPI engine */
+	uint64_t clk_cont                     : 1;  /**< If 0, clock idles to value given by IDLELO after
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+	uint64_t idlelo                       : 1;  /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
+                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
+	uint64_t enable                       : 1;  /**< If 0, all MPI pins are GPIOs
+                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
+#else
+	uint64_t enable                       : 1;
+	uint64_t idlelo                       : 1;
+	uint64_t clk_cont                     : 1;
+	uint64_t wireor                       : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t int_ena                      : 1;
+	uint64_t csena                        : 1;
+	uint64_t cshi                         : 1;
+	uint64_t idleclks                     : 2;
+	uint64_t tritx                        : 1;
+	uint64_t cslate                       : 1;
+	uint64_t reserved_12_15               : 4;
+	uint64_t clkdiv                       : 13;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_mpi_cfg_s                 cn30xx;
+	struct cvmx_mpi_cfg_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t clkdiv                       : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
+                                                         CLKDIV = Feclk / (2 * Fsclk) */
+	uint64_t reserved_11_15               : 5;
+	uint64_t tritx                        : 1;  /**< If 0, MPI_TX pin is driven when slave is not
+                                                               expected to be driving
+                                                            1, MPI_TX pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+	uint64_t idleclks                     : 2;  /**< Guarantee IDLECLKS idle sclk cycles between
+                                                         commands. */
+	uint64_t cshi                         : 1;  /**< If 0, CS is low asserted
+                                                         1, CS is high asserted */
+	uint64_t csena                        : 1;  /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
+                                                         1, CS is driven per MPI_TX intruction */
+	uint64_t int_ena                      : 1;  /**< If 0, polling is required
+                                                         1, MPI engine interrupts X end of transaction */
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift MSB first
+                                                         1, shift LSB first */
+	uint64_t wireor                       : 1;  /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
+                                                               MPI_TX pin is always driven
+                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
+                                                               MPI_TX pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
+                                                               MPI engine */
+	uint64_t clk_cont                     : 1;  /**< If 0, clock idles to value given by IDLELO after
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+	uint64_t idlelo                       : 1;  /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
+                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
+	uint64_t enable                       : 1;  /**< If 0, all MPI pins are GPIOs
+                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
+#else
+	uint64_t enable                       : 1;
+	uint64_t idlelo                       : 1;
+	uint64_t clk_cont                     : 1;
+	uint64_t wireor                       : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t int_ena                      : 1;
+	uint64_t csena                        : 1;
+	uint64_t cshi                         : 1;
+	uint64_t idleclks                     : 2;
+	uint64_t tritx                        : 1;
+	uint64_t reserved_11_15               : 5;
+	uint64_t clkdiv                       : 13;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn31xx;
+	struct cvmx_mpi_cfg_s                 cn50xx;
+};
+typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
+
+/**
+ * cvmx_mpi_dat#
+ */
+union cvmx_mpi_datx
+{
+	uint64_t u64;
+	struct cvmx_mpi_datx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t data                         : 8;  /**< Data to transmit/received */
+#else
+	uint64_t data                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_mpi_datx_s                cn30xx;
+	struct cvmx_mpi_datx_s                cn31xx;
+	struct cvmx_mpi_datx_s                cn50xx;
+};
+typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
+
+/**
+ * cvmx_mpi_sts
+ */
+union cvmx_mpi_sts
+{
+	uint64_t u64;
+	struct cvmx_mpi_sts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t rxnum                        : 5;  /**< Number of bytes written for transaction */
+	uint64_t reserved_1_7                 : 7;
+	uint64_t busy                         : 1;  /**< If 0, no MPI transaction in progress
+                                                         1, MPI engine is processing a transaction */
+#else
+	uint64_t busy                         : 1;
+	uint64_t reserved_1_7                 : 7;
+	uint64_t rxnum                        : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_mpi_sts_s                 cn30xx;
+	struct cvmx_mpi_sts_s                 cn31xx;
+	struct cvmx_mpi_sts_s                 cn50xx;
+};
+typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
+
+/**
+ * cvmx_mpi_tx
+ */
+union cvmx_mpi_tx
+{
+	uint64_t u64;
+	struct cvmx_mpi_tx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t leavecs                      : 1;  /**< If 0, deassert CS after transaction is done
+                                                         1, leave CS asserted after transactrion is done */
+	uint64_t reserved_13_15               : 3;
+	uint64_t txnum                        : 5;  /**< Number of bytes to transmit */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t totnum                       : 5;  /**< Number of bytes to shift (transmit + receive) */
+#else
+	uint64_t totnum                       : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t txnum                        : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t leavecs                      : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_mpi_tx_s                  cn30xx;
+	struct cvmx_mpi_tx_s                  cn31xx;
+	struct cvmx_mpi_tx_s                  cn50xx;
+};
+typedef union cvmx_mpi_tx cvmx_mpi_tx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-nand.c b/sys/contrib/octeon-sdk/cvmx-nand.c
index 30377ca..0d5a948 100644
--- a/sys/contrib/octeon-sdk/cvmx-nand.c
+++ b/sys/contrib/octeon-sdk/cvmx-nand.c
@@ -1,42 +1,44 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
+
 /**
  * @file
  *
@@ -46,10 +48,21 @@
  * <hr>$Revision: 35726 $<hr>
  */
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-nand.h>
+#include <asm/octeon/cvmx-ndf-defs.h>
+#include <asm/octeon/cvmx-swap.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#else
 #include "cvmx.h"
 #include "cvmx-nand.h"
 #include "cvmx-swap.h"
 #include "cvmx-bootmem.h"
+#endif
 
 #define NAND_COMMAND_READ_ID            0x90
 #define NAND_COMMAND_READ_PARAM_PAGE    0xec
@@ -77,7 +90,7 @@
 
 /* Structure to store the parameters that we care about that
 ** describe the ONFI speed modes.  This is used to configure
-** the flash timing to match what is reported in the 
+** the flash timing to match what is reported in the
 ** parameter page of the ONFI flash chip. */
 typedef struct
 {
@@ -98,6 +111,13 @@ static const onfi_speed_mode_desc_t onfi_speed_modes[] =
     {10, 7, 20, 5,10},  /* Mode 5, requries EDO timings */
 };
 
+
+
+typedef enum
+{
+    CVMX_NAND_STATE_16BIT = 1<<0,
+} cvmx_nand_state_flags_t;
+
 /**
  * Structure used to store data about the NAND devices hooked
  * to the bootbus.
@@ -115,6 +135,7 @@ typedef struct
     int rdn[4];
     int wrn[2];
     int onfi_timing;
+    cvmx_nand_state_flags_t flags;
 } cvmx_nand_state_t;
 
 /**
@@ -130,12 +151,14 @@ typedef struct
 #endif
 
 #ifdef USE_DATA_IN_TEXT
-static uint8_t cvmx_nand_buffer[4096] __attribute__((aligned(8)))  __attribute__ ((section (".data_in_text")));
+static uint8_t cvmx_nand_buffer[CVMX_NAND_MAX_PAGE_AND_OOB_SIZE] __attribute__((aligned(8)))  __attribute__ ((section (".data_in_text")));
 static cvmx_nand_state_t cvmx_nand_state[8] __attribute__ ((section (".data_in_text")));
+static cvmx_nand_state_t cvmx_nand_default __attribute__ ((section (".data_in_text")));
 static cvmx_nand_initialize_flags_t cvmx_nand_flags __attribute__ ((section (".data_in_text")));
 static int debug_indent __attribute__ ((section (".data_in_text")));
 #else
 static CVMX_SHARED cvmx_nand_state_t cvmx_nand_state[8];
+static CVMX_SHARED cvmx_nand_state_t cvmx_nand_default;
 static CVMX_SHARED cvmx_nand_initialize_flags_t cvmx_nand_flags;
 static CVMX_SHARED uint8_t *cvmx_nand_buffer = NULL;
 static int debug_indent = 0;
@@ -269,13 +292,13 @@ static cvmx_nand_onfi_param_page_t *__cvmx_nand_onfi_process(cvmx_nand_onfi_para
 
     if (index == 4)
     {
-        cvmx_dprintf("%s: No valid ONFI parameter pages found.\n", __FUNCTION__);
+        cvmx_dprintf("%s: WARNING: ONFI part but no valid ONFI parameter pages found.\n", __FUNCTION__);
         return NULL;
     }
 
     if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
     {
-        cvmx_dprintf("%*sONFI Information\n", 2*debug_indent, "");
+        cvmx_dprintf("%*sONFI Information (from copy %d in param page)\n", 2*debug_indent, "", index);
         debug_indent++;
         cvmx_dprintf("%*sonfi = %c%c%c%c\n", 2*debug_indent, "", param_page[index].onfi[0], param_page[index].onfi[1],
             param_page[index].onfi[2], param_page[index].onfi[3]);
@@ -353,19 +376,83 @@ void __set_onfi_timing_mode(int *tim_par, int clocks_us, int mode)
 
 }
 
+
+/* Internal helper function to set chip configuration to use default values */
+static void __set_chip_defaults(int chip, int clocks_us)
+{
+    if (!cvmx_nand_default.page_size)
+        return;
+    cvmx_nand_state[chip].page_size = cvmx_nand_default.page_size;  /* NAND page size in bytes */
+    cvmx_nand_state[chip].oob_size = cvmx_nand_default.oob_size;     /* NAND OOB (spare) size in bytes (per page) */
+    cvmx_nand_state[chip].pages_per_block = cvmx_nand_default.pages_per_block;
+    cvmx_nand_state[chip].blocks = cvmx_nand_default.blocks;
+    cvmx_nand_state[chip].onfi_timing = cvmx_nand_default.onfi_timing;
+    __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+    if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+    {
+
+        cvmx_dprintf("%s: Using default NAND parameters.\n", __FUNCTION__);
+        cvmx_dprintf("%s: Defaults: page size: %d, OOB size: %d, pages per block %d, blocks: %d, timing mode: %d\n",
+                     __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
+                     cvmx_nand_state[chip].blocks, cvmx_nand_state[chip].onfi_timing);
+    }
+}
+/* Do the proper wait for the ready/busy signal.  First wait
+** for busy to be valid, then wait for busy to de-assert.
+*/
+static int __wait_for_busy_done(int chip)
+{
+    cvmx_nand_cmd_t cmd;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.r_b=0;
+    cmd.wait.n = 2;
+
+    /* Wait for RB to be valied (tWB).
+    ** Use 5 * tWC as proxy.  In some modes this is
+    ** much longer than required, but does not affect performance
+    ** since we will wait much longer for busy to de-assert.
+    */
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+    cmd.wait.r_b=1; /* Now wait for busy to be de-asserted */
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
 /**
  * Called to initialize the NAND controller for use. Note that
  * you must be running out of L2 or memory and not NAND before
  * calling this function.
+ * When probing for NAND chips, this function attempts to autoconfigure based on the NAND parts detected.
+ * It currently supports autodetection for ONFI parts (with valid parameter pages), and some Samsung NAND
+ * parts (decoding ID bits.)  If autoconfiguration fails, the defaults set with __set_chip_defaults()
+ * prior to calling cvmx_nand_initialize() are used.
+ * If defaults are set and the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is provided, the defaults are used
+ * for all chips in the active_chips mask.
  *
  * @param flags  Optional initialization flags
+ *               If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is passed, chips are not probed,
+ *               and the default parameters (if set with cvmx_nand_set_defaults) are used for all chips
+ *               in the active_chips mask.
  * @param active_chips
  *               Each bit in this parameter represents a chip select that might
  *               contain NAND flash. Any chip select present in this bitmask may
  *               be connected to NAND. It is normally safe to pass 0xff here and
  *               let the API probe all 8 chip selects.
  *
- * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ * @return Zero on success, a negative cvmx_nand_status error code on failure
  */
 cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips)
 {
@@ -373,7 +460,8 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
     int start_chip;
     int stop_chip;
     uint64_t clocks_us;
-    cvmx_ndf_misc_t ndf_misc;
+    union cvmx_ndf_misc ndf_misc;
+    uint8_t nand_id_buffer[16];
 
     cvmx_nand_flags = flags;
     CVMX_NAND_LOG_CALLED();
@@ -382,11 +470,12 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
     memset(&cvmx_nand_state,  0,  sizeof(cvmx_nand_state));
 
 #ifndef USE_DATA_IN_TEXT
+    /* cvmx_nand_buffer is statically allocated in the TEXT_IN_DATA case */
     if (!cvmx_nand_buffer)
-        cvmx_nand_buffer = cvmx_bootmem_alloc(4096, 128);
-#endif
+        cvmx_nand_buffer = cvmx_bootmem_alloc(CVMX_NAND_MAX_PAGE_AND_OOB_SIZE, 128);
     if (!cvmx_nand_buffer)
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+#endif
 
     /* Disable boot mode and reset the fifo */
     ndf_misc.u64 = cvmx_read_csr(CVMX_NDF_MISC);
@@ -414,8 +503,6 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
     cvmx_write_csr(CVMX_MIO_NDF_DMA_INT, cvmx_read_csr(CVMX_MIO_NDF_DMA_INT));
     cvmx_write_csr(CVMX_MIO_NDF_DMA_INT_EN, 0);
 
-    if (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE)
-        CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 
     /* The simulator crashes if you access non existant devices. Assume
         only chip select 1 is connected to NAND */
@@ -431,13 +518,33 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
     }
 
     /* Figure out how many clocks are in one microsecond, rounding up */
-    clocks_us = CVMX_NAND_ROUNDUP(cvmx_sysinfo_get()->cpu_clock_hz, 1000000);
+    clocks_us = CVMX_NAND_ROUNDUP(cvmx_clock_get_rate(CVMX_CLOCK_SCLK), 1000000);
+
+    /* If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is set, then
+    ** use the supplied default values to configured the chips in the
+    ** active_chips mask */
+    if (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE)
+    {
+        if (cvmx_nand_default.page_size)
+        {
+            for (chip=start_chip; chip<stop_chip; chip++)
+            {
+                /* Skip chip selects that the caller didn't supply in the active chip bits */
+                if (((1<<chip) & active_chips) == 0)
+                    continue;
+                __set_chip_defaults(chip, clocks_us);
+            }
+        }
+        CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+    }
 
     /* Probe and see what NAND flash we can find */
     for (chip=start_chip; chip<stop_chip; chip++)
     {
-        cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
+        union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
         cvmx_nand_onfi_param_page_t *onfi_param_page;
+        int probe_failed;
+        int width_16;
 
         /* Skip chip selects that the caller didn't supply in the active chip bits */
         if (((1<<chip) & active_chips) == 0)
@@ -453,7 +560,6 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
         cvmx_nand_state[chip].oob_size = 64;
         cvmx_nand_state[chip].pages_per_block = 64;
         cvmx_nand_state[chip].blocks = 100;
-        cvmx_nand_state[chip].tim_mult = 0; /* Don't use a multiplier. Values are in cycles */
 
 
         /* Set timing mode to ONFI mode 0 for initial accesses */
@@ -480,102 +586,174 @@ cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int
         cvmx_nand_state[chip].wrn[0] = 1; /* Twp, WE# pulse width */
         cvmx_nand_state[chip].wrn[1] = 2; /* Twh, WE# pulse width high */
 
-        /* Probe and see if we get an answer */
-        memset(cvmx_nand_buffer, 0xff, 8);
-        if (cvmx_nand_read_id(chip, 0x0, cvmx_ptr_to_phys(cvmx_nand_buffer), 8) < 4)
+        /* Probe and see if we get an answer.  Read more than required, as in
+        ** 16 bit mode only every other byte is valid.
+        ** Here we probe twice, once in 8 bit mode, and once in 16 bit mode to autodetect
+        ** the width.
+        */
+        probe_failed = 1;
+        for (width_16 = 0; width_16 <= 1 && probe_failed; width_16++)
         {
-            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
-                cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
-            continue;
+            probe_failed = 0;
+
+            if (width_16)
+                cvmx_nand_state[chip].flags |= CVMX_NAND_STATE_16BIT;
+            memset(cvmx_nand_buffer, 0xff, 16);
+            if (cvmx_nand_read_id(chip, 0x0, cvmx_ptr_to_phys(cvmx_nand_buffer), 16) < 16)
+            {
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                    cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
+                probe_failed = 1;
+
+            }
+            if (*(uint32_t*)cvmx_nand_buffer == 0xffffffff || *(uint32_t*)cvmx_nand_buffer == 0x0)
+            {
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                    cvmx_dprintf("%s: Probe returned nothing for chip %d\n", __FUNCTION__, chip);
+                probe_failed = 1;
+            }
         }
-        if (*(uint32_t*)cvmx_nand_buffer == 0xffffffff)
-        {
-            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
-                cvmx_dprintf("%s: Probe returned nothing for chip %d\n", __FUNCTION__, chip);
+        /* Neither 8 or 16 bit mode worked, so go on to next chip select */
+        if (probe_failed)
             continue;
-        }
+
+        /* Save copy of ID for later use */
+        memcpy(nand_id_buffer, cvmx_nand_buffer, sizeof(nand_id_buffer));
 
         if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
             cvmx_dprintf("%s: NAND chip %d has ID 0x%08llx\n", __FUNCTION__, chip, (unsigned long long int)*(uint64_t*)cvmx_nand_buffer);
-
-        if (cvmx_nand_read_id(chip, 0x20, cvmx_ptr_to_phys(cvmx_nand_buffer), 4) < 4)
+        /* Read more than required, as in 16 bit mode only every other byte is valid. */
+        if (cvmx_nand_read_id(chip, 0x20, cvmx_ptr_to_phys(cvmx_nand_buffer), 8) < 8)
         {
             if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
                 cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
             continue;
         }
 
-        if (!((cvmx_nand_buffer[0] == 'O') && (cvmx_nand_buffer[1] == 'N') &&
+        if (((cvmx_nand_buffer[0] == 'O') && (cvmx_nand_buffer[1] == 'N') &&
             (cvmx_nand_buffer[2] == 'F') && (cvmx_nand_buffer[3] == 'I')))
         {
-            /* FIXME: This is where non ONFI NAND devices need to be handled */
-            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
-                cvmx_dprintf("%s: Chip %d doesn't support ONFI, skipping\n", __FUNCTION__, chip);
-            continue;
-        }
+            /* We have an ONFI part, so read the parameter page */
 
-        cvmx_nand_read_param_page(chip, cvmx_ptr_to_phys(cvmx_nand_buffer), 1024);
-        onfi_param_page = __cvmx_nand_onfi_process((cvmx_nand_onfi_param_page_t *)cvmx_nand_buffer);
-        if (onfi_param_page)
-        {
-            /* ONFI NAND parts are described by a parameter page.  Here we extract the configuration values
-            ** from the parameter page that we need to access the chip. */
-            cvmx_nand_state[chip].page_size = cvmx_le32_to_cpu(onfi_param_page->page_data_bytes);
-            cvmx_nand_state[chip].oob_size = cvmx_le16_to_cpu(onfi_param_page->page_spare_bytes);
-            cvmx_nand_state[chip].pages_per_block = cvmx_le32_to_cpu(onfi_param_page->pages_per_block);
-            cvmx_nand_state[chip].blocks = cvmx_le32_to_cpu(onfi_param_page->blocks_per_lun) * onfi_param_page->number_lun;
-
-            if (cvmx_le16_to_cpu(onfi_param_page->timing_mode) <= 0x3f)
+            cvmx_nand_read_param_page(chip, cvmx_ptr_to_phys(cvmx_nand_buffer), 2048);
+            onfi_param_page = __cvmx_nand_onfi_process((cvmx_nand_onfi_param_page_t *)cvmx_nand_buffer);
+            if (onfi_param_page)
             {
-                int mode_mask = cvmx_le16_to_cpu(onfi_param_page->timing_mode);
-                int mode = 0;
-                int i;
-                for (i = 0; i < 6;i++)
+                /* ONFI NAND parts are described by a parameter page.  Here we extract the configuration values
+                ** from the parameter page that we need to access the chip. */
+                cvmx_nand_state[chip].page_size = cvmx_le32_to_cpu(onfi_param_page->page_data_bytes);
+                cvmx_nand_state[chip].oob_size = cvmx_le16_to_cpu(onfi_param_page->page_spare_bytes);
+                cvmx_nand_state[chip].pages_per_block = cvmx_le32_to_cpu(onfi_param_page->pages_per_block);
+                cvmx_nand_state[chip].blocks = cvmx_le32_to_cpu(onfi_param_page->blocks_per_lun) * onfi_param_page->number_lun;
+
+                if (cvmx_le16_to_cpu(onfi_param_page->timing_mode) <= 0x3f)
                 {
-                    if (mode_mask & (1 << i))
-                        mode = i;
+                    int mode_mask = cvmx_le16_to_cpu(onfi_param_page->timing_mode);
+                    int mode = 0;
+                    int i;
+                    for (i = 0; i < 6;i++)
+                    {
+                        if (mode_mask & (1 << i))
+                            mode = i;
+                    }
+                    cvmx_nand_state[chip].onfi_timing = mode;
                 }
-                cvmx_nand_state[chip].onfi_timing = mode;
+                else
+                {
+                    cvmx_dprintf("%s: Invalid timing mode (%d) in ONFI parameter page, ignoring\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
+                    cvmx_nand_state[chip].onfi_timing = 0;
+
+                }
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                    cvmx_dprintf("%s: Using ONFI timing mode: %d\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
+                __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+                if (cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size > CVMX_NAND_MAX_PAGE_AND_OOB_SIZE)
+                {
+                    cvmx_dprintf("%s: ERROR: Page size (%d) + OOB size (%d) is greater than max size (%d)\n",
+                                 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, CVMX_NAND_MAX_PAGE_AND_OOB_SIZE);
+                    return(CVMX_NAND_ERROR);
+                }
+                /* We have completed setup for this ONFI chip, so go on to next chip. */
+                continue;
             }
             else
             {
-                cvmx_dprintf("%s: Invalid timing mode (%d) in ONFI parameter page, ignoring\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
-                cvmx_nand_state[chip].onfi_timing = 0;
+                /* Parameter page is not valid */
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                    cvmx_dprintf("%s: ONFI paramater page missing or invalid.\n", __FUNCTION__);
 
             }
-            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
-                cvmx_dprintf("%s: Using ONFI timing mode: %d\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
-            __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+
+
         }
         else
         {
-            /* We did not find a valid parameter page in the FLASH part.  This means that the part
-            ** does not provide the parameter page that ONFI requires.  In this case, hard coded defaults
-            ** can be used, but they _must_ be updated to match the flash used.
-            */
-            /* Enable this code to force a configuration for NAND chip that doesn't have a proper parameter page.
-            ** ONFI requires a parameter page, so this should not be needed for compliant chips */
-
-            /* The default values below are for the Numonyx NAND08GW3B2CN6E part */
-#define NAND_SIZE_BITS  (8*1024*1024*1024ULL)
-            cvmx_nand_state[chip].page_size = 2048;  /* NAND page size in bytes */
-            cvmx_nand_state[chip].oob_size = 64;     /* NAND OOB (spare) size in bytes (per page) */
-            cvmx_nand_state[chip].pages_per_block = 64;
-            cvmx_nand_state[chip].blocks = (NAND_SIZE_BITS)/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
-            cvmx_nand_state[chip].onfi_timing = 2;
-            cvmx_dprintf("%s: WARNING: No valid ONFI parameter page found, using fixed defaults.\n", __FUNCTION__);
-            cvmx_dprintf("%s: Defaults: page size: %d, OOB size: %d, pages per block %d, part size: %d MBytes, timing mode: %d\n",
-                         __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
-                         (int)(NAND_SIZE_BITS/(8*1024*1024)), cvmx_nand_state[chip].onfi_timing);
-
-            __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+            /* We have a non-ONFI part. */
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Chip %d doesn't support ONFI.\n", __FUNCTION__, chip);
+
+
+            if (nand_id_buffer[0] == 0xEC)
+            {
+                /* We have a Samsung part, so decode part info from ID bytes */
+                uint64_t nand_size_bits = (64*1024*1024ULL) << ((nand_id_buffer[4] & 0x70) >> 4); /* Plane size */
+                cvmx_nand_state[chip].page_size = 1024 << (nand_id_buffer[3] & 0x3);  /* NAND page size in bytes */
+                cvmx_nand_state[chip].oob_size = 128;     /* NAND OOB (spare) size in bytes (per page) */
+                cvmx_nand_state[chip].pages_per_block = (0x10000 << ((nand_id_buffer[3] & 0x30) >> 4))/cvmx_nand_state[chip].page_size;
+
+                nand_size_bits *= 1 << ((nand_id_buffer[4] & 0xc) >> 2);
+
+                cvmx_nand_state[chip].oob_size = cvmx_nand_state[chip].page_size/64;
+                if (nand_id_buffer[3] & 0x4)
+                    cvmx_nand_state[chip].oob_size *= 2;
+
+                cvmx_nand_state[chip].blocks = nand_size_bits/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
+                cvmx_nand_state[chip].onfi_timing = 2;
+
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                {
+                    cvmx_dprintf("%s: Samsung NAND chip detected, using parameters decoded from ID bytes.\n", __FUNCTION__);
+                    cvmx_dprintf("%s: Defaults: page size: %d, OOB size: %d, pages per block %d, part size: %d MBytes, timing mode: %d\n",
+                                 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
+                                 (int)(nand_size_bits/(8*1024*1024)), cvmx_nand_state[chip].onfi_timing);
+                }
+
+                __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+                if (cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size > CVMX_NAND_MAX_PAGE_AND_OOB_SIZE)
+                {
+                    cvmx_dprintf("%s: ERROR: Page size (%d) + OOB size (%d) is greater than max size (%d)\n",
+                                 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, CVMX_NAND_MAX_PAGE_AND_OOB_SIZE);
+                    return(CVMX_NAND_ERROR);
+                }
+
+                /* We have completed setup for this Samsung chip, so go on to next chip. */
+                continue;
+
+
+            }
+
         }
 
 
-    }
 
+        /*  We were not able to automatically identify the NAND chip parameters.  If default values were configured,
+        ** use them. */
+        if (cvmx_nand_default.page_size)
+        {
+            __set_chip_defaults(chip, clocks_us);
+        }
+        else
+        {
+
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Unable to determine NAND parameters, and no defaults supplied.\n", __FUNCTION__);
+        }
+    }
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_initialize);
+#endif
 
 
 /**
@@ -612,6 +790,9 @@ int cvmx_nand_get_active_chips(void)
     }
     return result;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_get_active_chips);
+#endif
 
 
 /**
@@ -661,7 +842,7 @@ cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[8],
  */
 static inline int __cvmx_nand_get_free_cmd_bytes(void)
 {
-    cvmx_ndf_misc_t ndf_misc;
+    union cvmx_ndf_misc ndf_misc;
     CVMX_NAND_LOG_CALLED();
     ndf_misc.u64 = cvmx_read_csr(CVMX_NDF_MISC);
     CVMX_NAND_RETURN((int)ndf_misc.s.fr_byt);
@@ -829,7 +1010,7 @@ static inline cvmx_nand_status_t __cvmx_nand_build_pre_cmd(int chip, int cmd_dat
     cmd.chip_en.chip = chip;
     cmd.chip_en.one = 1;
     cmd.chip_en.three = 3;
-    cmd.chip_en.width = (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_16BIT) ? 2 : 1;
+    cmd.chip_en.width = (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT) ? 2 : 1;
     result = cvmx_nand_submit(cmd);
     if (result)
         CVMX_NAND_RETURN(result);
@@ -948,7 +1129,7 @@ static inline cvmx_nand_status_t __cvmx_nand_build_post_cmd(void)
  */
 static inline void __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length)
 {
-    cvmx_mio_ndf_dma_cfg_t ndf_dma_cfg;
+    union cvmx_mio_ndf_dma_cfg ndf_dma_cfg;
     CVMX_NAND_LOG_CALLED();
     CVMX_NAND_LOG_PARAM("%d", chip);
     CVMX_NAND_LOG_PARAM("%d", is_write);
@@ -1019,7 +1200,7 @@ static void __cvmx_nand_hex_dump(uint64_t buffer_address, int buffer_length)
 static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length)
 {
     cvmx_nand_cmd_t cmd;
-    cvmx_mio_ndf_dma_cfg_t ndf_dma_cfg;
+    union cvmx_mio_ndf_dma_cfg ndf_dma_cfg;
     int bytes;
 
     CVMX_NAND_LOG_CALLED();
@@ -1037,6 +1218,8 @@ static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int ad
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (buffer_address & 7)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_length & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (!buffer_length)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
@@ -1046,17 +1229,14 @@ static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int ad
 
     /* Send WAIT.  This waits for some time, then
     ** waits for busy to be de-asserted. */
-    memset(&cmd,  0,  sizeof(cmd));
-    cmd.wait.two = 2;
-    cmd.wait.r_b=1;
-    cmd.wait.n = 1;
-    if (cvmx_nand_submit(cmd))
+    if (__wait_for_busy_done(chip))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     /* Wait for tRR after busy de-asserts.
     ** Use 2* tALS as proxy.  This is overkill in
     ** the slow modes, but not bad in the faster ones. */
-    cmd.wait.r_b=0;
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
     cmd.wait.n=4;
     if (cvmx_nand_submit(cmd))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
@@ -1129,12 +1309,21 @@ int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (buffer_address & 7)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_length & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (!buffer_length)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
+    /* For 16 bit mode, addresses within a page are word address, rather than byte addresses */
+    if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
+            nand_address = (nand_address & ~(cvmx_nand_state[chip].page_size - 1)) |  ((nand_address & (cvmx_nand_state[chip].page_size - 1)) >> 1);
+
     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ, __cvmx_nand_get_address_cycles(chip), nand_address, NAND_COMMAND_READ_FIN, buffer_address, buffer_length);
     CVMX_NAND_RETURN(bytes);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_page_read);
+#endif
 
 
 /**
@@ -1168,8 +1357,19 @@ cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_
     if (buffer_address & 7)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
+    /* For 16 bit mode, addresses within a page are word address, rather than byte addresses */
+    if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
+            nand_address = (nand_address & ~(cvmx_nand_state[chip].page_size - 1)) |  ((nand_address & (cvmx_nand_state[chip].page_size - 1)) >> 1);
+
     buffer_length = cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size;
 
+    /* The NAND DMA engine always does transfers in 8 byte blocks, so round the buffer size down
+    ** to a multiple of 8, otherwise we will transfer too much data to the NAND chip.
+    ** Note this prevents the last few bytes of the OOB being written.  If these bytes
+    ** need to be written, then this check needs to be removed, but this will result in
+    ** extra write cycles beyond the end of the OOB. */
+    buffer_length &= ~0x7;
+
     /* Build the command and address cycles */
     if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_PROGRAM, __cvmx_nand_get_address_cycles(chip), nand_address, 0))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
@@ -1196,11 +1396,7 @@ cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_
     __cvmx_nand_setup_dma(chip, 1, buffer_address, buffer_length);
 
     /* WAIT for R_B to signal program is complete  */
-    memset(&cmd,  0,  sizeof(cmd));
-    cmd.wait.two = 2;
-    cmd.wait.r_b=1;
-    cmd.wait.n = 1;
-    if (cvmx_nand_submit(cmd))
+    if (__wait_for_busy_done(chip))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     if (__cvmx_nand_build_post_cmd())
@@ -1212,6 +1408,9 @@ cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_
 
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_page_write);
+#endif
 
 
 /**
@@ -1225,8 +1424,6 @@ cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_
  */
 cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
 {
-    cvmx_nand_cmd_t cmd;
-
     CVMX_NAND_LOG_CALLED();
     CVMX_NAND_LOG_PARAM("%d", chip);
     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
@@ -1244,11 +1441,7 @@ cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     /* WAIT for R_B to signal erase is complete  */
-    memset(&cmd,  0,  sizeof(cmd));
-    cmd.wait.two = 2;
-    cmd.wait.r_b=1;
-    cmd.wait.n = 1;
-    if (cvmx_nand_submit(cmd))
+    if (__wait_for_busy_done(chip))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     if (__cvmx_nand_build_post_cmd())
@@ -1260,7 +1453,22 @@ cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
 
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_block_erase);
+#endif
+
 
+/* Some reads (read ID, read parameter page) only use the low 8 bits of the bus
+** in 16 bit mode.  We remove the unused bytes so that the data we present to the
+** caller is as expected (same as 8 bit mode.)
+*/
+static void __cvmx_nand_fixup_16bit_id_reads(uint8_t *buf, int buffer_length)
+{
+    /* Decimate data, taking only every other byte. */
+    int i;
+    for (i = 0; i < buffer_length/2; i++)
+        buf[i] = buf[2*i + 1];
+}
 
 /**
  * Read the NAND ID information
@@ -1271,7 +1479,8 @@ cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
  * @param buffer_address
  *               Physical address to store data in
  * @param buffer_length
- *               Length of the buffer. Usually this is 4 bytes
+ *               Length of the buffer. Usually this is 4-8 bytes.  For 16 bit mode, this must be twice
+ *               as large as the actual expected data.
  *
  * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
  */
@@ -1295,8 +1504,14 @@ int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address,
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_ID, 1, nand_address, 0, buffer_address, buffer_length);
+    if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
+        __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);
+
     CVMX_NAND_RETURN(bytes);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_read_id);
+#endif
 
 
 /**
@@ -1306,7 +1521,7 @@ int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address,
  * @param buffer_address
  *               Physical address to store data in
  * @param buffer_length
- *               Length of the buffer. Usually this is 4 bytes
+ *               Length of the buffer.  Usually 1024 bytes for 8 bit, 2048 for 16 bit mode.
  *
  * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
  */
@@ -1325,10 +1540,14 @@ int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_leng
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (buffer_address & 7)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_length & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
     if (!buffer_length)
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_PARAM_PAGE, 1, 0x0, 0, buffer_address, buffer_length);
+    if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
+        __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);
     CVMX_NAND_RETURN(bytes);
 }
 
@@ -1343,6 +1562,7 @@ int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_leng
 int cvmx_nand_get_status(int chip)
 {
     int status;
+    int offset = !!(cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT);  /* Normalize flag to 0/1 */
 
     CVMX_NAND_LOG_CALLED();
     CVMX_NAND_LOG_PARAM("%d", chip);
@@ -1350,13 +1570,16 @@ int cvmx_nand_get_status(int chip)
     if ((chip < 0) || (chip > 7))
         CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
 
-    *(uint8_t*)cvmx_nand_buffer = 0xff;
-    status = __cvmx_nand_low_level_read(chip, NAND_COMMAND_STATUS, 0, 0, 0, cvmx_ptr_to_phys(cvmx_nand_buffer), (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_16BIT) ? 2 : 1);
+    *((uint8_t*)cvmx_nand_buffer + offset)  = 0xff;
+    status = __cvmx_nand_low_level_read(chip, NAND_COMMAND_STATUS, 0, 0, 0, cvmx_ptr_to_phys(cvmx_nand_buffer), 8);
     if (status > 0)
-        status = *(uint8_t*)cvmx_nand_buffer;
+        status = *((uint8_t*)cvmx_nand_buffer + offset);
 
     CVMX_NAND_RETURN(status);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_get_status);
+#endif
 
 
 /**
@@ -1446,8 +1669,6 @@ int cvmx_nand_get_blocks(int chip)
  */
 cvmx_nand_status_t cvmx_nand_reset(int chip)
 {
-    cvmx_nand_cmd_t cmd;
-
     CVMX_NAND_LOG_CALLED();
     CVMX_NAND_LOG_PARAM("%d", chip);
 
@@ -1460,11 +1681,7 @@ cvmx_nand_status_t cvmx_nand_reset(int chip)
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     /* WAIT for R_B to signal reset is complete  */
-    memset(&cmd,  0,  sizeof(cmd));
-    cmd.wait.two = 2;
-    cmd.wait.r_b=1;
-    cmd.wait.n = 1;
-    if (cvmx_nand_submit(cmd))
+    if (__wait_for_busy_done(chip))
         CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
 
     if (__cvmx_nand_build_post_cmd())
@@ -1472,6 +1689,9 @@ cvmx_nand_status_t cvmx_nand_reset(int chip)
 
     CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_nand_reset);
+#endif
 
 
 
@@ -1479,7 +1699,7 @@ cvmx_nand_status_t cvmx_nand_reset(int chip)
 /**
  * This function computes the Octeon specific ECC data used by the NAND boot
  * feature.
- * 
+ *
  * @param block  pointer to 256 bytes of data
  * @param eccp   pointer to where 8 bytes of ECC data will be stored
  */
@@ -1717,3 +1937,17 @@ int cvmx_nand_correct_boot_ecc(uint8_t *block)
 
     return 1;
 }
+
+cvmx_nand_status_t cvmx_nand_set_defaults(int page_size, int oob_size, int pages_per_block, int blocks, int onfi_timing_mode)
+{
+    if (!page_size || !oob_size || !pages_per_block || !blocks || onfi_timing_mode > 5)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    cvmx_nand_default.page_size = page_size;
+    cvmx_nand_default.oob_size = oob_size;
+    cvmx_nand_default.pages_per_block = pages_per_block;
+    cvmx_nand_default.blocks = blocks;
+    cvmx_nand_default.onfi_timing = onfi_timing_mode;
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-nand.h b/sys/contrib/octeon-sdk/cvmx-nand.h
index 8ca4f9a..580dbb3 100644
--- a/sys/contrib/octeon-sdk/cvmx-nand.h
+++ b/sys/contrib/octeon-sdk/cvmx-nand.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -104,6 +106,10 @@
 extern "C" {
 #endif
 
+/* Maxium PAGE + OOB size supported.  This is used to size
+** buffers, some that must be statically allocated. */
+#define CVMX_NAND_MAX_PAGE_AND_OOB_SIZE      (4096 + 256)
+
 
 /* Block size for boot ECC */
 #define CVMX_NAND_BOOT_ECC_BLOCK_SIZE    (256)
@@ -130,6 +136,7 @@ typedef enum
     CVMX_NAND_BUSY = -2,
     CVMX_NAND_INVALID_PARAM = -3,
     CVMX_NAND_TIMEOUT = -4,
+    CVMX_NAND_ERROR = -5,
 } cvmx_nand_status_t;
 
 /**
@@ -472,8 +479,17 @@ typedef struct __attribute__ ((packed))
  * Called to initialize the NAND controller for use. Note that
  * you must be running out of L2 or memory and not NAND before
  * calling this function.
+ * When probing for NAND chips, this function attempts to autoconfigure based on the NAND parts detected.
+ * It currently supports autodetection for ONFI parts (with valid parameter pages), and some Samsung NAND
+ * parts (decoding ID bits.)  If autoconfiguration fails, the defaults set with __set_chip_defaults()
+ * prior to calling cvmx_nand_initialize() are used.
+ * If defaults are set and the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is provided, the defaults are used
+ * for all chips in the active_chips mask.
  *
  * @param flags  Optional initialization flags
+ *               If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is passed, chips are not probed,
+ *               and the default parameters (if set with cvmx_nand_set_defaults) are used for all chips
+ *               in the active_chips mask.
  * @param active_chips
  *               Each bit in this parameter represents a chip select that might
  *               contain NAND flash. Any chip select present in this bitmask may
@@ -485,6 +501,30 @@ typedef struct __attribute__ ((packed))
 extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips);
 
 
+
+/**
+ * This function may be called before cvmx_nand_initialize to set default values that will be used
+ * for NAND chips that do not identify themselves in a way that allows autoconfiguration. (ONFI chip with
+ * missing parameter page, for example.)
+ * The parameters set by this function will be used by _all_ non-autoconfigured NAND chips.
+ *
+ *
+ *   NOTE:  This function signature is _NOT_ stable, and will change in the future as required to support
+ *          various NAND chips.
+ *
+ * @param page_size page size in bytes
+ * @param oob_size  Out of band size in bytes (per page)
+ * @param pages_per_block
+ *                  number of pages per block
+ * @param blocks    Total number of blocks in device
+ * @param onfi_timing_mode
+ *                  ONFI timing mode
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_set_defaults(int page_size, int oob_size, int pages_per_block, int blocks, int onfi_timing_mode);
+
+
 /**
  * Call to shutdown the NAND controller after all transactions
  * are done. In most setups this will never be called.
@@ -660,7 +700,7 @@ extern cvmx_nand_status_t cvmx_nand_reset(int chip);
 /**
  * This function computes the Octeon specific ECC data used by the NAND boot
  * feature.
- * 
+ *
  * @param block  pointer to 256 bytes of data
  * @param eccp   pointer to where 8 bytes of ECC data will be stored
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-ndf-defs.h b/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
new file mode 100644
index 0000000..e004236
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
@@ -0,0 +1,534 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-ndf-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon ndf.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_NDF_TYPEDEFS_H__
+#define __CVMX_NDF_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
+static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000018ull);
+}
+#else
+#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
+static inline uint64_t CVMX_NDF_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000000ull);
+}
+#else
+#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
+static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000030ull);
+}
+#else
+#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
+static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000010ull);
+}
+#else
+#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
+static inline uint64_t CVMX_NDF_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000020ull);
+}
+#else
+#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
+static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000028ull);
+}
+#else
+#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
+static inline uint64_t CVMX_NDF_MISC_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000008ull);
+}
+#else
+#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
+static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001070001000038ull);
+}
+#else
+#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull))
+#endif
+
+/**
+ * cvmx_ndf_bt_pg_info
+ *
+ * Notes:
+ * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
+ * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
+ * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
+ * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
+ *
+ * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
+ * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
+ *
+ * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
+ * field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_bt_pg_info
+{
+	uint64_t u64;
+	struct cvmx_ndf_bt_pg_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t t_mult                       : 4;  /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
+                                                         command */
+	uint64_t adr_cyc                      : 4;  /**< # of column address cycles */
+	uint64_t size                         : 3;  /**< bytes per page in the nand device */
+#else
+	uint64_t size                         : 3;
+	uint64_t adr_cyc                      : 4;
+	uint64_t t_mult                       : 4;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_ndf_bt_pg_info_s          cn52xx;
+	struct cvmx_ndf_bt_pg_info_s          cn63xx;
+	struct cvmx_ndf_bt_pg_info_s          cn63xxp1;
+};
+typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;
+
+/**
+ * cvmx_ndf_cmd
+ *
+ * Notes:
+ * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
+ * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
+ * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
+ * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_cmd
+{
+	uint64_t u64;
+	struct cvmx_ndf_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t nf_cmd                       : 64; /**< 8 Command Bytes */
+#else
+	uint64_t nf_cmd                       : 64;
+#endif
+	} s;
+	struct cvmx_ndf_cmd_s                 cn52xx;
+	struct cvmx_ndf_cmd_s                 cn63xx;
+	struct cvmx_ndf_cmd_s                 cn63xxp1;
+};
+typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;
+
+/**
+ * cvmx_ndf_drbell
+ *
+ * Notes:
+ * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
+ * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
+ * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
+ * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
+ * non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
+ *
+ * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
+ * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
+ * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
+ * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
+ * the last command in the sequence will be a bus release command. The execution unit will start execution of
+ * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
+ * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
+ * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
+ * CNT field by the number of the command sequences, loaded to the command fifo.
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_drbell
+{
+	uint64_t u64;
+	struct cvmx_ndf_drbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t cnt                          : 8;  /**< Doorbell count register, 2's complement 8 bit value */
+#else
+	uint64_t cnt                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_ndf_drbell_s              cn52xx;
+	struct cvmx_ndf_drbell_s              cn63xx;
+	struct cvmx_ndf_drbell_s              cn63xxp1;
+};
+typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;
+
+/**
+ * cvmx_ndf_ecc_cnt
+ *
+ * Notes:
+ * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
+ *         ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
+ *         ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_ecc_cnt
+{
+	uint64_t u64;
+	struct cvmx_ndf_ecc_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t xor_ecc                      : 24; /**< result of XOR of ecc read bytes and ecc genarated
+                                                         bytes. The value pertains to the last 1 bit ecc err */
+	uint64_t ecc_err                      : 8;  /**< Count = \# of 1 bit errors fixed during boot
+                                                         This count saturates instead of wrapping around. */
+#else
+	uint64_t ecc_err                      : 8;
+	uint64_t xor_ecc                      : 24;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_ndf_ecc_cnt_s             cn52xx;
+	struct cvmx_ndf_ecc_cnt_s             cn63xx;
+	struct cvmx_ndf_ecc_cnt_s             cn63xxp1;
+};
+typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;
+
+/**
+ * cvmx_ndf_int
+ *
+ * Notes:
+ * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
+ *
+ * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
+ * last instruction out of the command fifo.
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_int
+{
+	uint64_t u64;
+	struct cvmx_ndf_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t ovrf                         : 1;  /**< NDF_CMD write when fifo is full. Generally a
+                                                         fatal error. */
+	uint64_t ecc_mult                     : 1;  /**< Multi bit ECC error detected during boot */
+	uint64_t ecc_1bit                     : 1;  /**< Single bit ECC error detected and fixed during boot */
+	uint64_t sm_bad                       : 1;  /**< One of the state machines in a bad state */
+	uint64_t wdog                         : 1;  /**< Watch Dog timer expired during command execution */
+	uint64_t full                         : 1;  /**< Command fifo is full */
+	uint64_t empty                        : 1;  /**< Command fifo is empty */
+#else
+	uint64_t empty                        : 1;
+	uint64_t full                         : 1;
+	uint64_t wdog                         : 1;
+	uint64_t sm_bad                       : 1;
+	uint64_t ecc_1bit                     : 1;
+	uint64_t ecc_mult                     : 1;
+	uint64_t ovrf                         : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_ndf_int_s                 cn52xx;
+	struct cvmx_ndf_int_s                 cn63xx;
+	struct cvmx_ndf_int_s                 cn63xxp1;
+};
+typedef union cvmx_ndf_int cvmx_ndf_int_t;
+
+/**
+ * cvmx_ndf_int_en
+ *
+ * Notes:
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ *
+ */
+union cvmx_ndf_int_en
+{
+	uint64_t u64;
+	struct cvmx_ndf_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t ovrf                         : 1;  /**< Wrote to a full command fifo */
+	uint64_t ecc_mult                     : 1;  /**< Multi bit ECC error detected during boot */
+	uint64_t ecc_1bit                     : 1;  /**< Single bit ECC error detected and fixed during boot */
+	uint64_t sm_bad                       : 1;  /**< One of the state machines in a bad state */
+	uint64_t wdog                         : 1;  /**< Watch Dog timer expired during command execution */
+	uint64_t full                         : 1;  /**< Command fifo is full */
+	uint64_t empty                        : 1;  /**< Command fifo is empty */
+#else
+	uint64_t empty                        : 1;
+	uint64_t full                         : 1;
+	uint64_t wdog                         : 1;
+	uint64_t sm_bad                       : 1;
+	uint64_t ecc_1bit                     : 1;
+	uint64_t ecc_mult                     : 1;
+	uint64_t ovrf                         : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_ndf_int_en_s              cn52xx;
+	struct cvmx_ndf_int_en_s              cn63xx;
+	struct cvmx_ndf_int_en_s              cn63xxp1;
+};
+typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;
+
+/**
+ * cvmx_ndf_misc
+ *
+ * Notes:
+ * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
+ *   the fifo size is 16 entries.
+ *
+ * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
+ *   represents number of eclk cycles.
+ *
+ * FR_BYT  this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
+ *   complete execution and exit. (fifo is 256 bytes when BT_DIS=0,  and 1536 bytes when BT_DIS=1)
+ *
+ * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
+ *   in response to RD_CMD bit being set to 1 by SW.
+ *
+ * RD_VAL  this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
+ *   to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
+ *
+ * RD_CMD  this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
+ *   RD_VAL bit in  this csr to see if next 8 bytes from the command fifo are available in the
+ *   NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
+ *   middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
+ *   bit will be cleared on any NDF_CMD csr write by SW.
+ *
+ * BT_DMA  this indicates to the NAND flash boot control state machine that boot dma read can begin.
+ *   SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
+ *   when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
+ *   permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
+ *
+ * BT_DIS  this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
+ *   whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
+ *   never be set when booting from nand flash and region zero is enabled.
+ *
+ * EX_DIS  When 1, command execution stops after completing execution of all commands currently in the command
+ *   fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
+ *   will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
+ *   is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
+ *
+ * RST_FF  reset command fifo to make it empty, any command inflight is not aborted before reseting
+ *   the fifo. The fifo comes up empty at the end of power on reset.
+ *
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_misc
+{
+	uint64_t u64;
+	struct cvmx_ndf_misc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t mb_dis                       : 1;  /**< Disable multibit error hangs and allow boot loads
+                                                         or boot dma's proceed as if no multi bit errors
+                                                         occured. HW will fix single bit errors as usual */
+	uint64_t nbr_hwm                      : 3;  /**< Hi Water mark for NBR fifo or load/stores */
+	uint64_t wait_cnt                     : 6;  /**< WAIT input filter count */
+	uint64_t fr_byt                       : 11; /**< Number of unfilled Command fifo bytes */
+	uint64_t rd_done                      : 1;  /**< This W1C bit is set to 1 by HW when it completes
+                                                         command fifo read out, in response to RD_CMD */
+	uint64_t rd_val                       : 1;  /**< This RO bit is set to 1 by HW when it reads next 8
+                                                         bytes from Command fifo into the NDF_CMD csr
+                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
+	uint64_t rd_cmd                       : 1;  /**< When 1, HW reads out contents of the Command fifo 8
+                                                         bytes at a time into the NDF_CMD csr */
+	uint64_t bt_dma                       : 1;  /**< When set to 1, boot time dma is enabled */
+	uint64_t bt_dis                       : 1;  /**< When boot operation is over SW must set to 1
+                                                         causes boot state mchines to sleep */
+	uint64_t ex_dis                       : 1;  /**< When set to 1, suspends execution of commands at
+                                                         next command in the fifo. */
+	uint64_t rst_ff                       : 1;  /**< 1=reset command fifo to make it empty,
+                                                         0=normal operation */
+#else
+	uint64_t rst_ff                       : 1;
+	uint64_t ex_dis                       : 1;
+	uint64_t bt_dis                       : 1;
+	uint64_t bt_dma                       : 1;
+	uint64_t rd_cmd                       : 1;
+	uint64_t rd_val                       : 1;
+	uint64_t rd_done                      : 1;
+	uint64_t fr_byt                       : 11;
+	uint64_t wait_cnt                     : 6;
+	uint64_t nbr_hwm                      : 3;
+	uint64_t mb_dis                       : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_ndf_misc_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t nbr_hwm                      : 3;  /**< Hi Water mark for NBR fifo or load/stores */
+	uint64_t wait_cnt                     : 6;  /**< WAIT input filter count */
+	uint64_t fr_byt                       : 11; /**< Number of unfilled Command fifo bytes */
+	uint64_t rd_done                      : 1;  /**< This W1C bit is set to 1 by HW when it completes
+                                                         command fifo read out, in response to RD_CMD */
+	uint64_t rd_val                       : 1;  /**< This RO bit is set to 1 by HW when it reads next 8
+                                                         bytes from Command fifo into the NDF_CMD csr
+                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
+	uint64_t rd_cmd                       : 1;  /**< When 1, HW reads out contents of the Command fifo 8
+                                                         bytes at a time into the NDF_CMD csr */
+	uint64_t bt_dma                       : 1;  /**< When set to 1, boot time dma is enabled */
+	uint64_t bt_dis                       : 1;  /**< When boot operation is over SW must set to 1
+                                                         causes boot state mchines to sleep */
+	uint64_t ex_dis                       : 1;  /**< When set to 1, suspends execution of commands at
+                                                         next command in the fifo. */
+	uint64_t rst_ff                       : 1;  /**< 1=reset command fifo to make it empty,
+                                                         0=normal operation */
+#else
+	uint64_t rst_ff                       : 1;
+	uint64_t ex_dis                       : 1;
+	uint64_t bt_dis                       : 1;
+	uint64_t bt_dma                       : 1;
+	uint64_t rd_cmd                       : 1;
+	uint64_t rd_val                       : 1;
+	uint64_t rd_done                      : 1;
+	uint64_t fr_byt                       : 11;
+	uint64_t wait_cnt                     : 6;
+	uint64_t nbr_hwm                      : 3;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn52xx;
+	struct cvmx_ndf_misc_s                cn63xx;
+	struct cvmx_ndf_misc_s                cn63xxp1;
+};
+typedef union cvmx_ndf_misc cvmx_ndf_misc_t;
+
+/**
+ * cvmx_ndf_st_reg
+ *
+ * Notes:
+ * This CSR aggregates all state machines used in nand flash controller for debug.
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+union cvmx_ndf_st_reg
+{
+	uint64_t u64;
+	struct cvmx_ndf_st_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t exe_idle                     : 1;  /**< Command Execution status 1=IDLE, 0=Busy
+                                                         1 means execution of command sequence is complete
+                                                         and command fifo is empty */
+	uint64_t exe_sm                       : 4;  /**< Command Execution State machine states */
+	uint64_t bt_sm                        : 4;  /**< Boot load and Boot dma State machine states */
+	uint64_t rd_ff_bad                    : 1;  /**< CMD fifo read back State machine in bad state */
+	uint64_t rd_ff                        : 2;  /**< CMD fifo read back State machine states */
+	uint64_t main_bad                     : 1;  /**< Main State machine in bad state */
+	uint64_t main_sm                      : 3;  /**< Main State machine states */
+#else
+	uint64_t main_sm                      : 3;
+	uint64_t main_bad                     : 1;
+	uint64_t rd_ff                        : 2;
+	uint64_t rd_ff_bad                    : 1;
+	uint64_t bt_sm                        : 4;
+	uint64_t exe_sm                       : 4;
+	uint64_t exe_idle                     : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_ndf_st_reg_s              cn52xx;
+	struct cvmx_ndf_st_reg_s              cn63xx;
+	struct cvmx_ndf_st_reg_s              cn63xxp1;
+};
+typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-npei-defs.h b/sys/contrib/octeon-sdk/cvmx-npei-defs.h
new file mode 100644
index 0000000..72155f8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-npei-defs.h
@@ -0,0 +1,7676 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-npei-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon npei.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_NPEI_TYPEDEFS_H__
+#define __CVMX_NPEI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000000ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
+	return 0x0000000000000580ull;
+}
+#else
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
+	return 0x0000000000000680ull;
+}
+#else
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
+	return 0x0000000000000250ull;
+}
+#else
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
+	return 0x0000000000000260ull;
+}
+#else
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
+	return 0x0000000000000570ull;
+}
+#else
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
+	return 0x0000000000003C00ull;
+}
+#else
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
+	return 0x00000000000005F0ull;
+}
+#else
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
+	return 0x0000000000000510ull;
+}
+#else
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
+	return 0x0000000000000500ull;
+}
+#else
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+	return 0x00000000000005C0ull;
+}
+#else
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+	return 0x00000000000005D0ull;
+}
+#else
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000450ull + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000003B0ull + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000400ull + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000004A0ull + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
+	return 0x00000000000005E0ull;
+}
+#else
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
+	return 0x00000000000003A0ull;
+}
+#else
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
+	return 0x00000000000005B0ull;
+}
+#else
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n");
+	return 0x00000000000006C0ull;
+}
+#else
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#endif
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n");
+	return 0x00000000000006D0ull;
+}
+#else
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#endif
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
+	return 0x0000000000000560ull;
+}
+#else
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
+	return 0x0000000000003CE0ull;
+}
+#else
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
+	return 0x0000000000000550ull;
+}
+#else
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
+	return 0x0000000000000540ull;
+}
+#else
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
+	return 0x0000000000003CD0ull;
+}
+#else
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
+	return 0x0000000000000590ull;
+}
+#else
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
+	return 0x0000000000000530ull;
+}
+#else
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
+	return 0x0000000000003CC0ull;
+}
+#else
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+	return 0x0000000000000600ull;
+}
+#else
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+	return 0x0000000000000610ull;
+}
+#else
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+	return 0x00000000000004F0ull;
+}
+#else
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
+		cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000340ull + ((offset) & 31) * 16 - 16*12;
+}
+#else
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
+	return 0x0000000000003C50ull;
+}
+#else
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
+	return 0x0000000000003C60ull;
+}
+#else
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
+	return 0x0000000000003C70ull;
+}
+#else
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
+	return 0x0000000000003C80ull;
+}
+#else
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
+	return 0x0000000000003C10ull;
+}
+#else
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
+	return 0x0000000000003C20ull;
+}
+#else
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
+	return 0x0000000000003C30ull;
+}
+#else
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
+	return 0x0000000000003C40ull;
+}
+#else
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
+	return 0x0000000000003CA0ull;
+}
+#else
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+	return 0x0000000000003CF0ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+	return 0x0000000000003D00ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+	return 0x0000000000003D10ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+	return 0x0000000000003D20ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+	return 0x0000000000003D30ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+	return 0x0000000000003D40ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+	return 0x0000000000003D50ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+	return 0x0000000000003D60ull;
+}
+#else
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
+	return 0x0000000000003C90ull;
+}
+#else
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+	return 0x0000000000003D70ull;
+}
+#else
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+	return 0x0000000000003CB0ull;
+}
+#else
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+	return 0x0000000000000650ull;
+}
+#else
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+	return 0x0000000000000660ull;
+}
+#else
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+	return 0x0000000000000670ull;
+}
+#else
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002C00ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003000ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001C00ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
+	return 0x0000000000001110ull;
+}
+#else
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+	return 0x0000000000001130ull;
+}
+#else
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+	return 0x00000000000010B0ull;
+}
+#else
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+	return 0x00000000000010A0ull;
+}
+#else
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+	return 0x0000000000001090ull;
+}
+#else
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
+	return 0x0000000000001080ull;
+}
+#else
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+	return 0x0000000000001150ull;
+}
+#else
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+	return 0x0000000000001000ull;
+}
+#else
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+	return 0x0000000000001190ull;
+}
+#else
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+	return 0x0000000000001020ull;
+}
+#else
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+	return 0x0000000000001100ull;
+}
+#else
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
+	return 0x00000000000006B0ull;
+}
+#else
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002000ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+	return 0x00000000000006A0ull;
+}
+#else
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+	return 0x00000000000011A0ull;
+}
+#else
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
+	return 0x0000000000001070ull;
+}
+#else
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+	return 0x0000000000001160ull;
+}
+#else
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+	return 0x00000000000010D0ull;
+}
+#else
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
+	return 0x0000000000001010ull;
+}
+#else
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+	return 0x00000000000010E0ull;
+}
+#else
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+	return 0x0000000000000690ull;
+}
+#else
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
+	return 0x0000000000001050ull;
+}
+#else
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+	return 0x0000000000001180ull;
+}
+#else
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
+	return 0x0000000000001040ull;
+}
+#else
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+	return 0x0000000000001030ull;
+}
+#else
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
+	return 0x0000000000001120ull;
+}
+#else
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+	return 0x0000000000001140ull;
+}
+#else
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+	return 0x0000000000000520ull;
+}
+#else
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
+	return 0x0000000000000270ull;
+}
+#else
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
+	return 0x0000000000000620ull;
+}
+#else
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
+	return 0x0000000000000630ull;
+}
+#else
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
+	return 0x0000000000000640ull;
+}
+#else
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
+	return 0x0000000000000380ull;
+}
+#else
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
+	return 0x0000000000000210ull;
+}
+#else
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
+	return 0x0000000000000240ull;
+}
+#else
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
+	return 0x0000000000000200ull;
+}
+#else
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
+	return 0x0000000000000220ull;
+}
+#else
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
+	return 0x0000000000000230ull;
+}
+#else
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
+#endif
+
+/**
+ * cvmx_npei_bar1_index#
+ *
+ * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
+ *
+ * General  5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
+ * PktMem  10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
+ * Rsvd     1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
+ *                                   == NPEI_PKT_CNT_INT_ENB[PORT]
+ *                                   == NPEI_PKT_TIME_INT_ENB[PORT]
+ *                                   == NPEI_PKT_CNT_INT[PORT]
+ *                                   == NPEI_PKT_TIME_INT[PORT]
+ *                                   == NPEI_PKT_PCIE_PORT[PP]
+ *                                   == NPEI_PKT_SLIST_ROR[ROR]
+ *                                   == NPEI_PKT_SLIST_ROR[NSR] ?
+ *                                   == NPEI_PKT_SLIST_ES[ES]
+ *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
+ *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ *                                   == NPEI_PKTn_CNTS[CNT]
+ * NPEI_CTL_STATUS[OUTn_ENB]         == NPEI_PKT_OUT_ENB[ENB]
+ * NPEI_BASE_ADDRESS_OUTPUTn[BADDR]  == NPEI_PKTn_SLIST_BADDR[ADDR]
+ * NPEI_DESC_OUTPUTn[SIZE]           == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE]
+ * NPEI_Pn_DBPAIR_ADDR[NADDR]        == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
+ * NPEI_PKT_CREDITSn[PTR_CNT]        == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ * NPEI_P0_PAIR_CNTS[AVAIL]          == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ * NPEI_P0_PAIR_CNTS[FCNT]           ==
+ * NPEI_PKTS_SENTn[PKT_CNT]          == NPEI_PKTn_CNTS[CNT]
+ * NPEI_OUTPUT_CONTROL[Pn_BMODE]     == NPEI_PKT_OUT_BMODE[BMODE]
+ * NPEI_PKT_CREDITSn[PKT_CNT]        == NPEI_PKTn_CNTS[CNT]
+ * NPEI_BUFF_SIZE_OUTPUTn[BSIZE]     == NPEI_PKT_SLIST_ID_SIZE[BSIZE]
+ * NPEI_BUFF_SIZE_OUTPUTn[ISIZE]     == NPEI_PKT_SLIST_ID_SIZE[ISIZE]
+ * NPEI_OUTPUT_CONTROL[On_CSRM]      == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT]
+ * NPEI_OUTPUT_CONTROL[On_ES]        == NPEI_PKT_DATA_OUT_ES[ES]
+ * NPEI_OUTPUT_CONTROL[On_NS]        == NPEI_PKT_DATA_OUT_NS[NSR] ?
+ * NPEI_OUTPUT_CONTROL[On_RO]        == NPEI_PKT_DATA_OUT_ROR[ROR]
+ * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT]  == NPEI_PKT_INT_LEVELS[CNT]
+ * NPEI_PKTS_SENT_TIMEn[PKT_TIME]    == NPEI_PKT_INT_LEVELS[TIME]
+ * NPEI_OUTPUT_CONTROL[IPTR_On]      == NPEI_PKT_IPTR[IPTR]
+ * NPEI_PCIE_PORT_OUTPUT[]           == NPEI_PKT_PCIE_PORT[PP]
+ *
+ *                  NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register
+ *
+ * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
+ * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16
+ * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1.
+ */
+union cvmx_npei_bar1_indexx
+{
+	uint32_t u32;
+	struct cvmx_npei_bar1_indexx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_18_31               : 14;
+	uint32_t addr_idx                     : 14; /**< Address bits [35:22] sent to L2C */
+	uint32_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
+	uint32_t end_swp                      : 2;  /**< Endian Swap Mode */
+	uint32_t addr_v                       : 1;  /**< Set '1' when the selected address range is valid. */
+#else
+	uint32_t addr_v                       : 1;
+	uint32_t end_swp                      : 2;
+	uint32_t ca                           : 1;
+	uint32_t addr_idx                     : 14;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_npei_bar1_indexx_s        cn52xx;
+	struct cvmx_npei_bar1_indexx_s        cn52xxp1;
+	struct cvmx_npei_bar1_indexx_s        cn56xx;
+	struct cvmx_npei_bar1_indexx_s        cn56xxp1;
+};
+typedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t;
+
+/**
+ * cvmx_npei_bist_status
+ *
+ * NPEI_BIST_STATUS = NPI's BIST Status Register
+ *
+ * Results from BIST runs of NPEI's memories.
+ */
+union cvmx_npei_bist_status
+{
+	uint64_t u64;
+	struct cvmx_npei_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pkt_rdf                      : 1;  /**< BIST Status for PKT Read FIFO */
+	uint64_t reserved_60_62               : 3;
+	uint64_t pcr_gim                      : 1;  /**< BIST Status for PKT Gather Instr MEM */
+	uint64_t pkt_pif                      : 1;  /**< BIST Status for PKT INB FIFO */
+	uint64_t pcsr_int                     : 1;  /**< BIST Status for PKT pout_int_bstatus */
+	uint64_t pcsr_im                      : 1;  /**< BIST Status for PKT pcsr_instr_mem_bstatus */
+	uint64_t pcsr_cnt                     : 1;  /**< BIST Status for PKT pin_cnt_bstatus */
+	uint64_t pcsr_id                      : 1;  /**< BIST Status for PKT pcsr_in_done_bstatus */
+	uint64_t pcsr_sl                      : 1;  /**< BIST Status for PKT pcsr_slist_bstatus */
+	uint64_t reserved_50_52               : 3;
+	uint64_t pkt_ind                      : 1;  /**< BIST Status for PKT Instruction Done MEM */
+	uint64_t pkt_slm                      : 1;  /**< BIST Status for PKT SList MEM */
+	uint64_t reserved_36_47               : 12;
+	uint64_t d0_pst                       : 1;  /**< BIST Status for DMA0 Pcie Store */
+	uint64_t d1_pst                       : 1;  /**< BIST Status for DMA1 Pcie Store */
+	uint64_t d2_pst                       : 1;  /**< BIST Status for DMA2 Pcie Store */
+	uint64_t d3_pst                       : 1;  /**< BIST Status for DMA3 Pcie Store */
+	uint64_t reserved_31_31               : 1;
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t p2n1_po                      : 1;  /**< BIST Status for P2N Port1 P Order */
+	uint64_t p2n1_no                      : 1;  /**< BIST Status for P2N Port1 N Order */
+	uint64_t p2n1_co                      : 1;  /**< BIST Status for P2N Port1 C Order */
+	uint64_t p2n0_po                      : 1;  /**< BIST Status for P2N Port0 P Order */
+	uint64_t p2n0_no                      : 1;  /**< BIST Status for P2N Port0 N Order */
+	uint64_t p2n0_co                      : 1;  /**< BIST Status for P2N Port0 C Order */
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t csm0                         : 1;  /**< BIST Status for CSM0 */
+	uint64_t csm1                         : 1;  /**< BIST Status for CSM1 */
+	uint64_t dif0                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif1                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif2                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif3                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t dif3                         : 1;
+	uint64_t dif2                         : 1;
+	uint64_t dif1                         : 1;
+	uint64_t dif0                         : 1;
+	uint64_t csm1                         : 1;
+	uint64_t csm0                         : 1;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t p2n0_co                      : 1;
+	uint64_t p2n0_no                      : 1;
+	uint64_t p2n0_po                      : 1;
+	uint64_t p2n1_co                      : 1;
+	uint64_t p2n1_no                      : 1;
+	uint64_t p2n1_po                      : 1;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t d3_pst                       : 1;
+	uint64_t d2_pst                       : 1;
+	uint64_t d1_pst                       : 1;
+	uint64_t d0_pst                       : 1;
+	uint64_t reserved_36_47               : 12;
+	uint64_t pkt_slm                      : 1;
+	uint64_t pkt_ind                      : 1;
+	uint64_t reserved_50_52               : 3;
+	uint64_t pcsr_sl                      : 1;
+	uint64_t pcsr_id                      : 1;
+	uint64_t pcsr_cnt                     : 1;
+	uint64_t pcsr_im                      : 1;
+	uint64_t pcsr_int                     : 1;
+	uint64_t pkt_pif                      : 1;
+	uint64_t pcr_gim                      : 1;
+	uint64_t reserved_60_62               : 3;
+	uint64_t pkt_rdf                      : 1;
+#endif
+	} s;
+	struct cvmx_npei_bist_status_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pkt_rdf                      : 1;  /**< BIST Status for PKT Read FIFO */
+	uint64_t reserved_60_62               : 3;
+	uint64_t pcr_gim                      : 1;  /**< BIST Status for PKT Gather Instr MEM */
+	uint64_t pkt_pif                      : 1;  /**< BIST Status for PKT INB FIFO */
+	uint64_t pcsr_int                     : 1;  /**< BIST Status for PKT OUTB Interrupt MEM */
+	uint64_t pcsr_im                      : 1;  /**< BIST Status for PKT CSR Instr MEM */
+	uint64_t pcsr_cnt                     : 1;  /**< BIST Status for PKT INB Count MEM */
+	uint64_t pcsr_id                      : 1;  /**< BIST Status for PKT INB Instr Done MEM */
+	uint64_t pcsr_sl                      : 1;  /**< BIST Status for PKT OUTB SLIST MEM */
+	uint64_t pkt_imem                     : 1;  /**< BIST Status for PKT OUTB IFIFO */
+	uint64_t pkt_pfm                      : 1;  /**< BIST Status for PKT Front MEM */
+	uint64_t pkt_pof                      : 1;  /**< BIST Status for PKT OUTB FIFO */
+	uint64_t reserved_48_49               : 2;
+	uint64_t pkt_pop0                     : 1;  /**< BIST Status for PKT OUTB Slist0 */
+	uint64_t pkt_pop1                     : 1;  /**< BIST Status for PKT OUTB Slist1 */
+	uint64_t d0_mem                       : 1;  /**< BIST Status for DMA MEM 0 */
+	uint64_t d1_mem                       : 1;  /**< BIST Status for DMA MEM 1 */
+	uint64_t d2_mem                       : 1;  /**< BIST Status for DMA MEM 2 */
+	uint64_t d3_mem                       : 1;  /**< BIST Status for DMA MEM 3 */
+	uint64_t d4_mem                       : 1;  /**< BIST Status for DMA MEM 4 */
+	uint64_t ds_mem                       : 1;  /**< BIST Status for DMA  Memory */
+	uint64_t reserved_36_39               : 4;
+	uint64_t d0_pst                       : 1;  /**< BIST Status for DMA0 Pcie Store */
+	uint64_t d1_pst                       : 1;  /**< BIST Status for DMA1 Pcie Store */
+	uint64_t d2_pst                       : 1;  /**< BIST Status for DMA2 Pcie Store */
+	uint64_t d3_pst                       : 1;  /**< BIST Status for DMA3 Pcie Store */
+	uint64_t d4_pst                       : 1;  /**< BIST Status for DMA4 Pcie Store */
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t p2n1_po                      : 1;  /**< BIST Status for P2N Port1 P Order */
+	uint64_t p2n1_no                      : 1;  /**< BIST Status for P2N Port1 N Order */
+	uint64_t p2n1_co                      : 1;  /**< BIST Status for P2N Port1 C Order */
+	uint64_t p2n0_po                      : 1;  /**< BIST Status for P2N Port0 P Order */
+	uint64_t p2n0_no                      : 1;  /**< BIST Status for P2N Port0 N Order */
+	uint64_t p2n0_co                      : 1;  /**< BIST Status for P2N Port0 C Order */
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t csm0                         : 1;  /**< BIST Status for CSM0 */
+	uint64_t csm1                         : 1;  /**< BIST Status for CSM1 */
+	uint64_t dif0                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif1                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif2                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif3                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif4                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dif4                         : 1;
+	uint64_t dif3                         : 1;
+	uint64_t dif2                         : 1;
+	uint64_t dif1                         : 1;
+	uint64_t dif0                         : 1;
+	uint64_t csm1                         : 1;
+	uint64_t csm0                         : 1;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t p2n0_co                      : 1;
+	uint64_t p2n0_no                      : 1;
+	uint64_t p2n0_po                      : 1;
+	uint64_t p2n1_co                      : 1;
+	uint64_t p2n1_no                      : 1;
+	uint64_t p2n1_po                      : 1;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t d4_pst                       : 1;
+	uint64_t d3_pst                       : 1;
+	uint64_t d2_pst                       : 1;
+	uint64_t d1_pst                       : 1;
+	uint64_t d0_pst                       : 1;
+	uint64_t reserved_36_39               : 4;
+	uint64_t ds_mem                       : 1;
+	uint64_t d4_mem                       : 1;
+	uint64_t d3_mem                       : 1;
+	uint64_t d2_mem                       : 1;
+	uint64_t d1_mem                       : 1;
+	uint64_t d0_mem                       : 1;
+	uint64_t pkt_pop1                     : 1;
+	uint64_t pkt_pop0                     : 1;
+	uint64_t reserved_48_49               : 2;
+	uint64_t pkt_pof                      : 1;
+	uint64_t pkt_pfm                      : 1;
+	uint64_t pkt_imem                     : 1;
+	uint64_t pcsr_sl                      : 1;
+	uint64_t pcsr_id                      : 1;
+	uint64_t pcsr_cnt                     : 1;
+	uint64_t pcsr_im                      : 1;
+	uint64_t pcsr_int                     : 1;
+	uint64_t pkt_pif                      : 1;
+	uint64_t pcr_gim                      : 1;
+	uint64_t reserved_60_62               : 3;
+	uint64_t pkt_rdf                      : 1;
+#endif
+	} cn52xx;
+	struct cvmx_npei_bist_status_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t d0_mem0                      : 1;  /**< BIST Status for DMA0 Memory */
+	uint64_t d1_mem1                      : 1;  /**< BIST Status for DMA1 Memory */
+	uint64_t d2_mem2                      : 1;  /**< BIST Status for DMA2 Memory */
+	uint64_t d3_mem3                      : 1;  /**< BIST Status for DMA3 Memory */
+	uint64_t dr0_mem                      : 1;  /**< BIST Status for DMA0 Store */
+	uint64_t d0_mem                       : 1;  /**< BIST Status for DMA0 Memory */
+	uint64_t d1_mem                       : 1;  /**< BIST Status for DMA1 Memory */
+	uint64_t d2_mem                       : 1;  /**< BIST Status for DMA2 Memory */
+	uint64_t d3_mem                       : 1;  /**< BIST Status for DMA3 Memory */
+	uint64_t dr1_mem                      : 1;  /**< BIST Status for DMA1 Store */
+	uint64_t d0_pst                       : 1;  /**< BIST Status for DMA0 Pcie Store */
+	uint64_t d1_pst                       : 1;  /**< BIST Status for DMA1 Pcie Store */
+	uint64_t d2_pst                       : 1;  /**< BIST Status for DMA2 Pcie Store */
+	uint64_t d3_pst                       : 1;  /**< BIST Status for DMA3 Pcie Store */
+	uint64_t dr2_mem                      : 1;  /**< BIST Status for DMA2 Store */
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t p2n1_po                      : 1;  /**< BIST Status for P2N Port1 P Order */
+	uint64_t p2n1_no                      : 1;  /**< BIST Status for P2N Port1 N Order */
+	uint64_t p2n1_co                      : 1;  /**< BIST Status for P2N Port1 C Order */
+	uint64_t p2n0_po                      : 1;  /**< BIST Status for P2N Port0 P Order */
+	uint64_t p2n0_no                      : 1;  /**< BIST Status for P2N Port0 N Order */
+	uint64_t p2n0_co                      : 1;  /**< BIST Status for P2N Port0 C Order */
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t csm0                         : 1;  /**< BIST Status for CSM0 */
+	uint64_t csm1                         : 1;  /**< BIST Status for CSM1 */
+	uint64_t dif0                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif1                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif2                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif3                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dr3_mem                      : 1;  /**< BIST Status for DMA3 Store */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dr3_mem                      : 1;
+	uint64_t dif3                         : 1;
+	uint64_t dif2                         : 1;
+	uint64_t dif1                         : 1;
+	uint64_t dif0                         : 1;
+	uint64_t csm1                         : 1;
+	uint64_t csm0                         : 1;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t p2n0_co                      : 1;
+	uint64_t p2n0_no                      : 1;
+	uint64_t p2n0_po                      : 1;
+	uint64_t p2n1_co                      : 1;
+	uint64_t p2n1_no                      : 1;
+	uint64_t p2n1_po                      : 1;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t dr2_mem                      : 1;
+	uint64_t d3_pst                       : 1;
+	uint64_t d2_pst                       : 1;
+	uint64_t d1_pst                       : 1;
+	uint64_t d0_pst                       : 1;
+	uint64_t dr1_mem                      : 1;
+	uint64_t d3_mem                       : 1;
+	uint64_t d2_mem                       : 1;
+	uint64_t d1_mem                       : 1;
+	uint64_t d0_mem                       : 1;
+	uint64_t dr0_mem                      : 1;
+	uint64_t d3_mem3                      : 1;
+	uint64_t d2_mem2                      : 1;
+	uint64_t d1_mem1                      : 1;
+	uint64_t d0_mem0                      : 1;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_bist_status_cn52xx   cn56xx;
+	struct cvmx_npei_bist_status_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t pcsr_int                     : 1;  /**< BIST Status for PKT pout_int_bstatus */
+	uint64_t pcsr_im                      : 1;  /**< BIST Status for PKT pcsr_instr_mem_bstatus */
+	uint64_t pcsr_cnt                     : 1;  /**< BIST Status for PKT pin_cnt_bstatus */
+	uint64_t pcsr_id                      : 1;  /**< BIST Status for PKT pcsr_in_done_bstatus */
+	uint64_t pcsr_sl                      : 1;  /**< BIST Status for PKT pcsr_slist_bstatus */
+	uint64_t pkt_pout                     : 1;  /**< BIST Status for PKT OUT Count MEM */
+	uint64_t pkt_imem                     : 1;  /**< BIST Status for PKT Instruction MEM */
+	uint64_t pkt_cntm                     : 1;  /**< BIST Status for PKT Count MEM */
+	uint64_t pkt_ind                      : 1;  /**< BIST Status for PKT Instruction Done MEM */
+	uint64_t pkt_slm                      : 1;  /**< BIST Status for PKT SList MEM */
+	uint64_t pkt_odf                      : 1;  /**< BIST Status for PKT Output Data FIFO */
+	uint64_t pkt_oif                      : 1;  /**< BIST Status for PKT Output INFO FIFO */
+	uint64_t pkt_out                      : 1;  /**< BIST Status for PKT Output FIFO */
+	uint64_t pkt_i0                       : 1;  /**< BIST Status for PKT Instr0 */
+	uint64_t pkt_i1                       : 1;  /**< BIST Status for PKT Instr1 */
+	uint64_t pkt_s0                       : 1;  /**< BIST Status for PKT Slist0 */
+	uint64_t pkt_s1                       : 1;  /**< BIST Status for PKT Slist1 */
+	uint64_t d0_mem                       : 1;  /**< BIST Status for DMA0 Memory */
+	uint64_t d1_mem                       : 1;  /**< BIST Status for DMA1 Memory */
+	uint64_t d2_mem                       : 1;  /**< BIST Status for DMA2 Memory */
+	uint64_t d3_mem                       : 1;  /**< BIST Status for DMA3 Memory */
+	uint64_t d4_mem                       : 1;  /**< BIST Status for DMA4 Memory */
+	uint64_t d0_pst                       : 1;  /**< BIST Status for DMA0 Pcie Store */
+	uint64_t d1_pst                       : 1;  /**< BIST Status for DMA1 Pcie Store */
+	uint64_t d2_pst                       : 1;  /**< BIST Status for DMA2 Pcie Store */
+	uint64_t d3_pst                       : 1;  /**< BIST Status for DMA3 Pcie Store */
+	uint64_t d4_pst                       : 1;  /**< BIST Status for DMA4 Pcie Store */
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t p2n1_po                      : 1;  /**< BIST Status for P2N Port1 P Order */
+	uint64_t p2n1_no                      : 1;  /**< BIST Status for P2N Port1 N Order */
+	uint64_t p2n1_co                      : 1;  /**< BIST Status for P2N Port1 C Order */
+	uint64_t p2n0_po                      : 1;  /**< BIST Status for P2N Port0 P Order */
+	uint64_t p2n0_no                      : 1;  /**< BIST Status for P2N Port0 N Order */
+	uint64_t p2n0_co                      : 1;  /**< BIST Status for P2N Port0 C Order */
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t csm0                         : 1;  /**< BIST Status for CSM0 */
+	uint64_t csm1                         : 1;  /**< BIST Status for CSM1 */
+	uint64_t dif0                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif1                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif2                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif3                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t dif4                         : 1;  /**< BIST Status for DMA Instr0 */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dif4                         : 1;
+	uint64_t dif3                         : 1;
+	uint64_t dif2                         : 1;
+	uint64_t dif1                         : 1;
+	uint64_t dif0                         : 1;
+	uint64_t csm1                         : 1;
+	uint64_t csm0                         : 1;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t p2n0_co                      : 1;
+	uint64_t p2n0_no                      : 1;
+	uint64_t p2n0_po                      : 1;
+	uint64_t p2n1_co                      : 1;
+	uint64_t p2n1_no                      : 1;
+	uint64_t p2n1_po                      : 1;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t d4_pst                       : 1;
+	uint64_t d3_pst                       : 1;
+	uint64_t d2_pst                       : 1;
+	uint64_t d1_pst                       : 1;
+	uint64_t d0_pst                       : 1;
+	uint64_t d4_mem                       : 1;
+	uint64_t d3_mem                       : 1;
+	uint64_t d2_mem                       : 1;
+	uint64_t d1_mem                       : 1;
+	uint64_t d0_mem                       : 1;
+	uint64_t pkt_s1                       : 1;
+	uint64_t pkt_s0                       : 1;
+	uint64_t pkt_i1                       : 1;
+	uint64_t pkt_i0                       : 1;
+	uint64_t pkt_out                      : 1;
+	uint64_t pkt_oif                      : 1;
+	uint64_t pkt_odf                      : 1;
+	uint64_t pkt_slm                      : 1;
+	uint64_t pkt_ind                      : 1;
+	uint64_t pkt_cntm                     : 1;
+	uint64_t pkt_imem                     : 1;
+	uint64_t pkt_pout                     : 1;
+	uint64_t pcsr_sl                      : 1;
+	uint64_t pcsr_id                      : 1;
+	uint64_t pcsr_cnt                     : 1;
+	uint64_t pcsr_im                      : 1;
+	uint64_t pcsr_int                     : 1;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_bist_status cvmx_npei_bist_status_t;
+
+/**
+ * cvmx_npei_bist_status2
+ *
+ * NPEI_BIST_STATUS2 = NPI's BIST Status Register2
+ *
+ * Results from BIST runs of NPEI's memories.
+ */
+union cvmx_npei_bist_status2
+{
+	uint64_t u64;
+	struct cvmx_npei_bist_status2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t prd_tag                      : 1;  /**< BIST Status for DMA PCIE RD Tag MEM */
+	uint64_t prd_st0                      : 1;  /**< BIST Status for DMA PCIE RD state MEM 0 */
+	uint64_t prd_st1                      : 1;  /**< BIST Status for DMA PCIE RD state MEM 1 */
+	uint64_t prd_err                      : 1;  /**< BIST Status for DMA PCIE RD ERR state MEM */
+	uint64_t nrd_st                       : 1;  /**< BIST Status for DMA L2C RD state MEM */
+	uint64_t nwe_st                       : 1;  /**< BIST Status for DMA L2C WR state MEM */
+	uint64_t nwe_wr0                      : 1;  /**< BIST Status for DMA L2C WR MEM 0 */
+	uint64_t nwe_wr1                      : 1;  /**< BIST Status for DMA L2C WR MEM 1 */
+	uint64_t pkt_rd                       : 1;  /**< BIST Status for Inbound PKT MEM */
+	uint64_t psc_p0                       : 1;  /**< BIST Status for PSC TLP 0 MEM */
+	uint64_t psc_p1                       : 1;  /**< BIST Status for PSC TLP 1 MEM */
+	uint64_t pkt_gd                       : 1;  /**< BIST Status for PKT OUTB Gather Data FIFO */
+	uint64_t pkt_gl                       : 1;  /**< BIST Status for PKT_OUTB Gather List FIFO */
+	uint64_t pkt_blk                      : 1;  /**< BIST Status for PKT OUTB Blocked FIFO */
+#else
+	uint64_t pkt_blk                      : 1;
+	uint64_t pkt_gl                       : 1;
+	uint64_t pkt_gd                       : 1;
+	uint64_t psc_p1                       : 1;
+	uint64_t psc_p0                       : 1;
+	uint64_t pkt_rd                       : 1;
+	uint64_t nwe_wr1                      : 1;
+	uint64_t nwe_wr0                      : 1;
+	uint64_t nwe_st                       : 1;
+	uint64_t nrd_st                       : 1;
+	uint64_t prd_err                      : 1;
+	uint64_t prd_st1                      : 1;
+	uint64_t prd_st0                      : 1;
+	uint64_t prd_tag                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_npei_bist_status2_s       cn52xx;
+	struct cvmx_npei_bist_status2_s       cn56xx;
+};
+typedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t;
+
+/**
+ * cvmx_npei_ctl_port0
+ *
+ * NPEI_CTL_PORT0 = NPEI's Control Port 0
+ *
+ * Contains control for access for Port0
+ */
+union cvmx_npei_ctl_port0
+{
+	uint64_t u64;
+	struct cvmx_npei_ctl_port0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t waitl_com                    : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional completions
+                                                         to the L2C from the PCIe.
+                                                         Set this for more conservative behavior. Clear
+                                                         this for more aggressive, higher-performance
+                                                         behavior */
+	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
+	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
+	uint64_t intb                         : 1;  /**< When '0' Intb wire asserted. Before mapping. */
+	uint64_t inta                         : 1;  /**< When '0' Inta wire asserted. Before mapping. */
+	uint64_t intd_map                     : 2;  /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intc_map                     : 2;  /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intb_map                     : 2;  /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t inta_map                     : 2;  /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t ctlp_ro                      : 1;  /**< Relaxed ordering enable for Completion TLPS. */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ptlp_ro                      : 1;  /**< Relaxed ordering enable for Posted TLPS. */
+	uint64_t bar2_enb                     : 1;  /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will cause UR responses. */
+	uint64_t bar2_esx                     : 2;  /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+	uint64_t bar2_cax                     : 1;  /**< Value will be XORed with pcie-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         Not cached in L2 if XOR result is 1 */
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional stores to
+                                                         the L2C from the PCIe.
+                                                         Most applications will not notice a difference, so
+                                                         should not set this bit. Setting the bit is more
+                                                         conservative on ordering, lower performance */
+#else
+	uint64_t wait_com                     : 1;
+	uint64_t bar2_cax                     : 1;
+	uint64_t bar2_esx                     : 2;
+	uint64_t bar2_enb                     : 1;
+	uint64_t ptlp_ro                      : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ctlp_ro                      : 1;
+	uint64_t inta_map                     : 2;
+	uint64_t intb_map                     : 2;
+	uint64_t intc_map                     : 2;
+	uint64_t intd_map                     : 2;
+	uint64_t inta                         : 1;
+	uint64_t intb                         : 1;
+	uint64_t intc                         : 1;
+	uint64_t intd                         : 1;
+	uint64_t waitl_com                    : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_npei_ctl_port0_s          cn52xx;
+	struct cvmx_npei_ctl_port0_s          cn52xxp1;
+	struct cvmx_npei_ctl_port0_s          cn56xx;
+	struct cvmx_npei_ctl_port0_s          cn56xxp1;
+};
+typedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t;
+
+/**
+ * cvmx_npei_ctl_port1
+ *
+ * NPEI_CTL_PORT1 = NPEI's Control Port1
+ *
+ * Contains control for access for Port1
+ */
+union cvmx_npei_ctl_port1
+{
+	uint64_t u64;
+	struct cvmx_npei_ctl_port1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t waitl_com                    : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional completions
+                                                         to the L2C from the PCIe.
+                                                         Set this for more conservative behavior. Clear
+                                                         this for more aggressive, higher-performance */
+	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
+	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
+	uint64_t intb                         : 1;  /**< When '0' Intv wire asserted. Before mapping. */
+	uint64_t inta                         : 1;  /**< When '0' Inta wire asserted. Before mapping. */
+	uint64_t intd_map                     : 2;  /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intc_map                     : 2;  /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intb_map                     : 2;  /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t inta_map                     : 2;  /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t ctlp_ro                      : 1;  /**< Relaxed ordering enable for Completion TLPS. */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ptlp_ro                      : 1;  /**< Relaxed ordering enable for Posted TLPS. */
+	uint64_t bar2_enb                     : 1;  /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will cause UR responses. */
+	uint64_t bar2_esx                     : 2;  /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+	uint64_t bar2_cax                     : 1;  /**< Value will be XORed with pcie-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         Not cached in L2 if XOR result is 1 */
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional stores to
+                                                         the L2C from the PCIe.
+                                                         Most applications will not notice a difference, so
+                                                         should not set this bit. Setting the bit is more
+                                                         conservative on ordering, lower performance */
+#else
+	uint64_t wait_com                     : 1;
+	uint64_t bar2_cax                     : 1;
+	uint64_t bar2_esx                     : 2;
+	uint64_t bar2_enb                     : 1;
+	uint64_t ptlp_ro                      : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ctlp_ro                      : 1;
+	uint64_t inta_map                     : 2;
+	uint64_t intb_map                     : 2;
+	uint64_t intc_map                     : 2;
+	uint64_t intd_map                     : 2;
+	uint64_t inta                         : 1;
+	uint64_t intb                         : 1;
+	uint64_t intc                         : 1;
+	uint64_t intd                         : 1;
+	uint64_t waitl_com                    : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_npei_ctl_port1_s          cn52xx;
+	struct cvmx_npei_ctl_port1_s          cn52xxp1;
+	struct cvmx_npei_ctl_port1_s          cn56xx;
+	struct cvmx_npei_ctl_port1_s          cn56xxp1;
+};
+typedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t;
+
+/**
+ * cvmx_npei_ctl_status
+ *
+ * NPEI_CTL_STATUS = NPEI Control Status Register
+ *
+ * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space.
+ * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space)
+ * that requires the value of this register to be updated.
+ */
+union cvmx_npei_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_npei_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t p1_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port1.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t p0_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port0.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t cfg_rtry                     : 16; /**< The time x 0x10000 in core clocks to wait for a
+                                                         CPL to a CFG RD that does not carry a Retry Status.
+                                                         Until such time that the timeout occurs and Retry
+                                                         Status is received for a CFG RD, the Read CFG Read
+                                                         will be resent. A value of 0 disables retries and
+                                                         treats a CPL Retry as a CPL UR. */
+	uint64_t ring_en                      : 1;  /**< When '0' forces "relative Q position" received
+                                                         from PKO to be zero, and replicates the back-
+                                                         pressure indication for the first ring attached
+                                                         to a PKO port across all the rings attached to a
+                                                         PKO port.  When '1' backpressure is on a per
+                                                         port/ring. */
+	uint64_t lnk_rst                      : 1;  /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+	uint64_t arb                          : 1;  /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+	uint64_t pkt_bp                       : 4;  /**< Unused */
+	uint64_t host_mode                    : 1;  /**< Host mode */
+	uint64_t chip_rev                     : 8;  /**< The chip revision. */
+#else
+	uint64_t chip_rev                     : 8;
+	uint64_t host_mode                    : 1;
+	uint64_t pkt_bp                       : 4;
+	uint64_t arb                          : 1;
+	uint64_t lnk_rst                      : 1;
+	uint64_t ring_en                      : 1;
+	uint64_t cfg_rtry                     : 16;
+	uint64_t p0_ntags                     : 6;
+	uint64_t p1_ntags                     : 6;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npei_ctl_status_s         cn52xx;
+	struct cvmx_npei_ctl_status_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t p1_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port1.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t p0_ntags                     : 6;  /**< Number of tags avaiable for PCIe Port0.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t cfg_rtry                     : 16; /**< The time x 0x10000 in core clocks to wait for a
+                                                         CPL to a CFG RD that does not carry a Retry Status.
+                                                         Until such time that the timeout occurs and Retry
+                                                         Status is received for a CFG RD, the Read CFG Read
+                                                         will be resent. A value of 0 disables retries and
+                                                         treats a CPL Retry as a CPL UR. */
+	uint64_t reserved_15_15               : 1;
+	uint64_t lnk_rst                      : 1;  /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+	uint64_t arb                          : 1;  /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+	uint64_t reserved_9_12                : 4;
+	uint64_t host_mode                    : 1;  /**< Host mode */
+	uint64_t chip_rev                     : 8;  /**< The chip revision. */
+#else
+	uint64_t chip_rev                     : 8;
+	uint64_t host_mode                    : 1;
+	uint64_t reserved_9_12                : 4;
+	uint64_t arb                          : 1;
+	uint64_t lnk_rst                      : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t cfg_rtry                     : 16;
+	uint64_t p0_ntags                     : 6;
+	uint64_t p1_ntags                     : 6;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_ctl_status_s         cn56xx;
+	struct cvmx_npei_ctl_status_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t lnk_rst                      : 1;  /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+	uint64_t arb                          : 1;  /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+	uint64_t pkt_bp                       : 4;  /**< Unused */
+	uint64_t host_mode                    : 1;  /**< Host mode */
+	uint64_t chip_rev                     : 8;  /**< The chip revision. */
+#else
+	uint64_t chip_rev                     : 8;
+	uint64_t host_mode                    : 1;
+	uint64_t pkt_bp                       : 4;
+	uint64_t arb                          : 1;
+	uint64_t lnk_rst                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t;
+
+/**
+ * cvmx_npei_ctl_status2
+ *
+ * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register
+ *
+ * Contains control and status for NPEI.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+union cvmx_npei_ctl_status2
+{
+	uint64_t u64;
+	struct cvmx_npei_ctl_status2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mps                          : 1;  /**< Max Payload Size
+                                                                  0  = 128B
+                                                                  1  = 256B
+                                                         Note: PCIE*_CFG030[MPS] must be set to the same
+                                                               value for proper function. */
+	uint64_t mrrs                         : 3;  /**< Max Read Request Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                                 2 = 512B
+                                                                 3 = 1024B
+                                                                 4 = 2048B
+                                                                 5 = 4096B
+                                                         Note: This field must not exceed the desired
+                                                               max read request size. This means this field
+                                                               should not exceed PCIE*_CFG030[MRRS]. */
+	uint64_t c1_w_flt                     : 1;  /**< When '1' enables the window filter for reads and
+                                                         writes using the window registers.
+                                                         PCIE-Port1.
+                                                         Unfilter writes are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId1
+                                                         POW,   SubId2
+                                                         POW,   SubId3
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7 */
+	uint64_t c0_w_flt                     : 1;  /**< When '1' enables the window filter for reads and
+                                                         writes using the window registers.
+                                                         PCIE-Port0.
+                                                         Unfilter writes are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId1
+                                                         POW,   SubId2
+                                                         POW,   SubId3
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7 */
+	uint64_t c1_b1_s                      : 3;  /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB,
+                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
+                                                         0 and 7 are reserved. */
+	uint64_t c0_b1_s                      : 3;  /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
+                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
+                                                         0 and 7 are reserved. */
+	uint64_t c1_wi_d                      : 1;  /**< When set '1' disables access to the Window
+                                                         Registers from the PCIe-Port1. */
+	uint64_t c1_b0_d                      : 1;  /**< When set '1' disables access from PCIe-Port1 to
+                                                         BAR-0 address offsets: Less Than 0x270,
+                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
+                                                         0x3CD0. */
+	uint64_t c0_wi_d                      : 1;  /**< When set '1' disables access to the Window
+                                                         Registers from the PCIe-Port0. */
+	uint64_t c0_b0_d                      : 1;  /**< When set '1' disables access from PCIe-Port0 to
+                                                         BAR-0 address offsets: Less Than 0x270,
+                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
+                                                         0x3CD0. */
+#else
+	uint64_t c0_b0_d                      : 1;
+	uint64_t c0_wi_d                      : 1;
+	uint64_t c1_b0_d                      : 1;
+	uint64_t c1_wi_d                      : 1;
+	uint64_t c0_b1_s                      : 3;
+	uint64_t c1_b1_s                      : 3;
+	uint64_t c0_w_flt                     : 1;
+	uint64_t c1_w_flt                     : 1;
+	uint64_t mrrs                         : 3;
+	uint64_t mps                          : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npei_ctl_status2_s        cn52xx;
+	struct cvmx_npei_ctl_status2_s        cn52xxp1;
+	struct cvmx_npei_ctl_status2_s        cn56xx;
+	struct cvmx_npei_ctl_status2_s        cn56xxp1;
+};
+typedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t;
+
+/**
+ * cvmx_npei_data_out_cnt
+ *
+ * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT
+ *
+ * The EXEC data out fifo-count and the data unload counter.
+ */
+union cvmx_npei_data_out_cnt
+{
+	uint64_t u64;
+	struct cvmx_npei_data_out_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t p1_ucnt                      : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+	uint64_t p1_fcnt                      : 6;  /**< PCIE-Port1 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the PCIe port presently
+                                                         buffered in the FIFO. */
+	uint64_t p0_ucnt                      : 16; /**< PCIE-Port0 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+	uint64_t p0_fcnt                      : 6;  /**< PCIE-Port0 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the PCIe port presently
+                                                         buffered in the FIFO. */
+#else
+	uint64_t p0_fcnt                      : 6;
+	uint64_t p0_ucnt                      : 16;
+	uint64_t p1_fcnt                      : 6;
+	uint64_t p1_ucnt                      : 16;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npei_data_out_cnt_s       cn52xx;
+	struct cvmx_npei_data_out_cnt_s       cn52xxp1;
+	struct cvmx_npei_data_out_cnt_s       cn56xx;
+	struct cvmx_npei_data_out_cnt_s       cn56xxp1;
+};
+typedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t;
+
+/**
+ * cvmx_npei_dbg_data
+ *
+ * NPEI_DBG_DATA = NPEI Debug Data Register
+ *
+ * Value returned on the debug-data lines from the RSLs
+ */
+union cvmx_npei_dbg_data
+{
+	uint64_t u64;
+	struct cvmx_npei_dbg_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t qlm0_rev_lanes               : 1;  /**< Lane reversal for PCIe port 0 */
+	uint64_t reserved_25_26               : 2;
+	uint64_t qlm1_spd                     : 2;  /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+	uint64_t c_mul                        : 5;  /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t qlm1_spd                     : 2;
+	uint64_t reserved_25_26               : 2;
+	uint64_t qlm0_rev_lanes               : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_npei_dbg_data_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t qlm0_link_width              : 1;  /**< Link width of PCIe port 0
+                                                         0 = PCIe port 0 is 2 lanes,
+                                                             2 lane PCIe port 1 exists
+                                                         1 = PCIe port 0 is 4 lanes,
+                                                             PCIe port 1 does not exist */
+	uint64_t qlm0_rev_lanes               : 1;  /**< Lane reversal for PCIe port 0 */
+	uint64_t qlm1_mode                    : 2;  /**< Sets the QLM1 Mode
+                                                         0=Reserved
+                                                         1=XAUI
+                                                         2=SGMII
+                                                         3=PICMG */
+	uint64_t qlm1_spd                     : 2;  /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+	uint64_t c_mul                        : 5;  /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t qlm1_spd                     : 2;
+	uint64_t qlm1_mode                    : 2;
+	uint64_t qlm0_rev_lanes               : 1;
+	uint64_t qlm0_link_width              : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn52xx;
+	struct cvmx_npei_dbg_data_cn52xx      cn52xxp1;
+	struct cvmx_npei_dbg_data_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t qlm2_rev_lanes               : 1;  /**< Lane reversal for PCIe port 1 */
+	uint64_t qlm0_rev_lanes               : 1;  /**< Lane reversal for PCIe port 0 */
+	uint64_t qlm3_spd                     : 2;  /**< Sets the QLM3 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+	uint64_t qlm1_spd                     : 2;  /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+	uint64_t c_mul                        : 5;  /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t c_mul                        : 5;
+	uint64_t qlm1_spd                     : 2;
+	uint64_t qlm3_spd                     : 2;
+	uint64_t qlm0_rev_lanes               : 1;
+	uint64_t qlm2_rev_lanes               : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn56xx;
+	struct cvmx_npei_dbg_data_cn56xx      cn56xxp1;
+};
+typedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t;
+
+/**
+ * cvmx_npei_dbg_select
+ *
+ * NPEI_DBG_SELECT = Debug Select Register
+ *
+ * Contains the debug select value last written to the RSLs.
+ */
+union cvmx_npei_dbg_select
+{
+	uint64_t u64;
+	struct cvmx_npei_dbg_select_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dbg_sel                      : 16; /**< When this register is written its value is sent to
+                                                         all RSLs. */
+#else
+	uint64_t dbg_sel                      : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npei_dbg_select_s         cn52xx;
+	struct cvmx_npei_dbg_select_s         cn52xxp1;
+	struct cvmx_npei_dbg_select_s         cn56xx;
+	struct cvmx_npei_dbg_select_s         cn56xxp1;
+};
+typedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t;
+
+/**
+ * cvmx_npei_dma#_counts
+ *
+ * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts
+ *
+ * Values for determing the number of instructions for DMA[0..4] in the NPEI.
+ */
+union cvmx_npei_dmax_counts
+{
+	uint64_t u64;
+	struct cvmx_npei_dmax_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
+	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t fcnt                         : 7;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_npei_dmax_counts_s        cn52xx;
+	struct cvmx_npei_dmax_counts_s        cn52xxp1;
+	struct cvmx_npei_dmax_counts_s        cn56xx;
+	struct cvmx_npei_dmax_counts_s        cn56xxp1;
+};
+typedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t;
+
+/**
+ * cvmx_npei_dma#_dbell
+ *
+ * NPEI_DMA_DBELL[0..4] = DMA Door Bell
+ *
+ * The door bell register for DMA[0..4] queue.
+ */
+union cvmx_npei_dmax_dbell
+{
+	uint32_t u32;
+	struct cvmx_npei_dmax_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t dbell                        : 16; /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the low priority dma queue. */
+#else
+	uint32_t dbell                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_npei_dmax_dbell_s         cn52xx;
+	struct cvmx_npei_dmax_dbell_s         cn52xxp1;
+	struct cvmx_npei_dmax_dbell_s         cn56xx;
+	struct cvmx_npei_dmax_dbell_s         cn56xxp1;
+};
+typedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t;
+
+/**
+ * cvmx_npei_dma#_ibuff_saddr
+ *
+ * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
+ *
+ * The address to start reading Instructions from for DMA[0..4].
+ */
+union cvmx_npei_dmax_ibuff_saddr
+{
+	uint64_t u64;
+	struct cvmx_npei_dmax_ibuff_saddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t idle                         : 1;  /**< DMA Engine IDLE state */
+	uint64_t saddr                        : 29; /**< The 128 byte aligned starting address to read the
+                                                         first instruction. SADDR is address bit 35:7 of the
+                                                         first instructions address. */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t saddr                        : 29;
+	uint64_t idle                         : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_npei_dmax_ibuff_saddr_s   cn52xx;
+	struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t saddr                        : 29; /**< The 128 byte aligned starting address to read the
+                                                         first instruction. SADDR is address bit 35:7 of the
+                                                         first instructions address. */
+	uint64_t reserved_0_6                 : 7;
+#else
+	uint64_t reserved_0_6                 : 7;
+	uint64_t saddr                        : 29;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_dmax_ibuff_saddr_s   cn56xx;
+	struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
+};
+typedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t;
+
+/**
+ * cvmx_npei_dma#_naddr
+ *
+ * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address
+ *
+ * Place NPEI will read the next Ichunk data from. This is valid when state is 0
+ */
+union cvmx_npei_dmax_naddr
+{
+	uint64_t u64;
+	struct cvmx_npei_dmax_naddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< The next L2C address to read DMA# instructions
+                                                         from. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_npei_dmax_naddr_s         cn52xx;
+	struct cvmx_npei_dmax_naddr_s         cn52xxp1;
+	struct cvmx_npei_dmax_naddr_s         cn56xx;
+	struct cvmx_npei_dmax_naddr_s         cn56xxp1;
+};
+typedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t;
+
+/**
+ * cvmx_npei_dma0_int_level
+ *
+ * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level
+ *
+ * Thresholds for DMA count and timer interrupts for DMA0.
+ */
+union cvmx_npei_dma0_int_level
+{
+	uint64_t u64;
+	struct cvmx_npei_dma0_int_level_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t time                         : 32; /**< Whenever the DMA_CNT0 timer exceeds
+                                                         this value, NPEI_INT_SUM[DTIME0] is set.
+                                                         The DMA_CNT0 timer increments every core clock
+                                                         whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared
+                                                         when NPEI_INT_SUM[DTIME0] is written with one. */
+	uint64_t cnt                          : 32; /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value,
+                                                         NPEI_INT_SUM[DCNT0] is set. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t time                         : 32;
+#endif
+	} s;
+	struct cvmx_npei_dma0_int_level_s     cn52xx;
+	struct cvmx_npei_dma0_int_level_s     cn52xxp1;
+	struct cvmx_npei_dma0_int_level_s     cn56xx;
+	struct cvmx_npei_dma0_int_level_s     cn56xxp1;
+};
+typedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t;
+
+/**
+ * cvmx_npei_dma1_int_level
+ *
+ * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level
+ *
+ * Thresholds for DMA count and timer interrupts for DMA1.
+ */
+union cvmx_npei_dma1_int_level
+{
+	uint64_t u64;
+	struct cvmx_npei_dma1_int_level_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t time                         : 32; /**< Whenever the DMA_CNT1 timer exceeds
+                                                         this value, NPEI_INT_SUM[DTIME1] is set.
+                                                         The DMA_CNT1 timer increments every core clock
+                                                         whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared
+                                                         when NPEI_INT_SUM[DTIME1] is written with one. */
+	uint64_t cnt                          : 32; /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value,
+                                                         NPEI_INT_SUM[DCNT1] is set. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t time                         : 32;
+#endif
+	} s;
+	struct cvmx_npei_dma1_int_level_s     cn52xx;
+	struct cvmx_npei_dma1_int_level_s     cn52xxp1;
+	struct cvmx_npei_dma1_int_level_s     cn56xx;
+	struct cvmx_npei_dma1_int_level_s     cn56xxp1;
+};
+typedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t;
+
+/**
+ * cvmx_npei_dma_cnts
+ *
+ * NPEI_DMA_CNTS = NPEI DMA Count
+ *
+ * The DMA Count values for DMA0 and DMA1.
+ */
+union cvmx_npei_dma_cnts
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dma1                         : 32; /**< The DMA counter 1.
+                                                         Writing this field will cause the written value to
+                                                         be subtracted from DMA1. SW should use a 4-byte
+                                                         write to access this field so as not to change the
+                                                         value of other fields in this register.
+                                                         HW will optionally increment this field after
+                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
+                                                         instruction. These increments may cause interrupts.
+                                                         Refer to NPEI_DMA1_INT_LEVEL and
+                                                         NPEI_INT_SUM[DCNT1,DTIME1]. */
+	uint64_t dma0                         : 32; /**< The DMA counter 0.
+                                                         Writing this field will cause the written value to
+                                                         be subtracted from DMA0. SW should use a 4-byte
+                                                         write to access this field so as not to change the
+                                                         value of other fields in this register.
+                                                         HW will optionally increment this field after
+                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
+                                                         instruction. These increments may cause interrupts.
+                                                         Refer to NPEI_DMA0_INT_LEVEL and
+                                                         NPEI_INT_SUM[DCNT0,DTIME0]. */
+#else
+	uint64_t dma0                         : 32;
+	uint64_t dma1                         : 32;
+#endif
+	} s;
+	struct cvmx_npei_dma_cnts_s           cn52xx;
+	struct cvmx_npei_dma_cnts_s           cn52xxp1;
+	struct cvmx_npei_dma_cnts_s           cn56xx;
+	struct cvmx_npei_dma_cnts_s           cn56xxp1;
+};
+typedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t;
+
+/**
+ * cvmx_npei_dma_control
+ *
+ * NPEI_DMA_CONTROL = DMA Control Register
+ *
+ * Controls operation of the DMA IN/OUT.
+ */
+union cvmx_npei_dma_control
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t p_32b_m                      : 1;  /**< DMA PCIE 32-bit word read disable bit
+                                                         When 0, enable the feature */
+	uint64_t dma4_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma3_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma2_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma1_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma0_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+	uint64_t csize                        : 14; /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+	uint64_t csize                        : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t dma0_enb                     : 1;
+	uint64_t dma1_enb                     : 1;
+	uint64_t dma2_enb                     : 1;
+	uint64_t dma3_enb                     : 1;
+	uint64_t dma4_enb                     : 1;
+	uint64_t p_32b_m                      : 1;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_npei_dma_control_s        cn52xx;
+	struct cvmx_npei_dma_control_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t dma3_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma2_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma1_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma0_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+	uint64_t csize                        : 14; /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+	uint64_t csize                        : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t dma0_enb                     : 1;
+	uint64_t dma1_enb                     : 1;
+	uint64_t dma2_enb                     : 1;
+	uint64_t dma3_enb                     : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_dma_control_s        cn56xx;
+	struct cvmx_npei_dma_control_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t dma4_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma3_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma2_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma1_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t dma0_enb                     : 1;  /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+	uint64_t csize                        : 14; /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+	uint64_t csize                        : 14;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t dma0_enb                     : 1;
+	uint64_t dma1_enb                     : 1;
+	uint64_t dma2_enb                     : 1;
+	uint64_t dma3_enb                     : 1;
+	uint64_t dma4_enb                     : 1;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_dma_control cvmx_npei_dma_control_t;
+
+/**
+ * cvmx_npei_dma_pcie_req_num
+ *
+ * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number
+ *
+ * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16
+ */
+union cvmx_npei_dma_pcie_req_num
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_pcie_req_num_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dma_arb                      : 1;  /**< DMA_PKT Read Request Arbitration
+                                                         - 1: DMA0-4 and PKT are round robin. i.e.
+                                                             DMA0-DMA1-DMA2-DMA3-DMA4-PKT...
+                                                         - 0: DMA0-4 are round robin, pkt gets selected
+                                                             half the time. i.e.
+                                                             DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */
+	uint64_t reserved_53_62               : 10;
+	uint64_t pkt_cnt                      : 5;  /**< PKT outstanding PCIE Read Request Number for each
+                                                         PCIe port
+                                                         When PKT_CNT=x, for each PCIe port, the number
+                                                         of outstanding PCIe memory space reads by the PCIe
+                                                         packet input/output will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_45_47               : 3;
+	uint64_t dma4_cnt                     : 5;  /**< DMA4 outstanding PCIE Read Request Number
+                                                         When DMA4_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 4
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_37_39               : 3;
+	uint64_t dma3_cnt                     : 5;  /**< DMA3 outstanding PCIE Read Request Number
+                                                         When DMA3_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 3
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_29_31               : 3;
+	uint64_t dma2_cnt                     : 5;  /**< DMA2 outstanding PCIE Read Request Number
+                                                         When DMA2_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 2
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_21_23               : 3;
+	uint64_t dma1_cnt                     : 5;  /**< DMA1 outstanding PCIE Read Request Number
+                                                         When DMA1_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 1
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_13_15               : 3;
+	uint64_t dma0_cnt                     : 5;  /**< DMA0 outstanding PCIE Read Request Number
+                                                         When DMA0_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 0
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dma_cnt                      : 5;  /**< Total outstanding PCIE Read Request Number for each
+                                                         PCIe port
+                                                         When DMA_CNT=x, for each PCIe port, the total
+                                                         number of outstanding PCIe memory space reads
+                                                         by the PCIe DMA engines and packet input/output
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+#else
+	uint64_t dma_cnt                      : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dma0_cnt                     : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t dma1_cnt                     : 5;
+	uint64_t reserved_21_23               : 3;
+	uint64_t dma2_cnt                     : 5;
+	uint64_t reserved_29_31               : 3;
+	uint64_t dma3_cnt                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t dma4_cnt                     : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t pkt_cnt                      : 5;
+	uint64_t reserved_53_62               : 10;
+	uint64_t dma_arb                      : 1;
+#endif
+	} s;
+	struct cvmx_npei_dma_pcie_req_num_s   cn52xx;
+	struct cvmx_npei_dma_pcie_req_num_s   cn56xx;
+};
+typedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t;
+
+/**
+ * cvmx_npei_dma_state1
+ *
+ * NPEI_DMA_STATE1 = NPI's DMA State 1
+ *
+ * Results from DMA state register 1
+ */
+union cvmx_npei_dma_state1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t d4_dwe                       : 8;  /**< DMA4 PICe Write State */
+	uint64_t d3_dwe                       : 8;  /**< DMA3 PICe Write State */
+	uint64_t d2_dwe                       : 8;  /**< DMA2 PICe Write State */
+	uint64_t d1_dwe                       : 8;  /**< DMA1 PICe Write State */
+	uint64_t d0_dwe                       : 8;  /**< DMA0 PICe Write State */
+#else
+	uint64_t d0_dwe                       : 8;
+	uint64_t d1_dwe                       : 8;
+	uint64_t d2_dwe                       : 8;
+	uint64_t d3_dwe                       : 8;
+	uint64_t d4_dwe                       : 8;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_npei_dma_state1_s         cn52xx;
+};
+typedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t;
+
+/**
+ * cvmx_npei_dma_state1_p1
+ *
+ * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State
+ *
+ * DMA engine Debug information.
+ */
+union cvmx_npei_dma_state1_p1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state1_p1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t d0_difst                     : 7;  /**< DMA engine 0 dif instruction read state */
+	uint64_t d1_difst                     : 7;  /**< DMA engine 1 dif instruction read state */
+	uint64_t d2_difst                     : 7;  /**< DMA engine 2 dif instruction read state */
+	uint64_t d3_difst                     : 7;  /**< DMA engine 3 dif instruction read state */
+	uint64_t d4_difst                     : 7;  /**< DMA engine 4 dif instruction read state */
+	uint64_t d0_reqst                     : 5;  /**< DMA engine 0 request data state */
+	uint64_t d1_reqst                     : 5;  /**< DMA engine 1 request data state */
+	uint64_t d2_reqst                     : 5;  /**< DMA engine 2 request data state */
+	uint64_t d3_reqst                     : 5;  /**< DMA engine 3 request data state */
+	uint64_t d4_reqst                     : 5;  /**< DMA engine 4 request data state */
+#else
+	uint64_t d4_reqst                     : 5;
+	uint64_t d3_reqst                     : 5;
+	uint64_t d2_reqst                     : 5;
+	uint64_t d1_reqst                     : 5;
+	uint64_t d0_reqst                     : 5;
+	uint64_t d4_difst                     : 7;
+	uint64_t d3_difst                     : 7;
+	uint64_t d2_difst                     : 7;
+	uint64_t d1_difst                     : 7;
+	uint64_t d0_difst                     : 7;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_npei_dma_state1_p1_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t d0_difst                     : 7;  /**< DMA engine 0 dif instruction read state */
+	uint64_t d1_difst                     : 7;  /**< DMA engine 1 dif instruction read state */
+	uint64_t d2_difst                     : 7;  /**< DMA engine 2 dif instruction read state */
+	uint64_t d3_difst                     : 7;  /**< DMA engine 3 dif instruction read state */
+	uint64_t reserved_25_31               : 7;
+	uint64_t d0_reqst                     : 5;  /**< DMA engine 0 request data state */
+	uint64_t d1_reqst                     : 5;  /**< DMA engine 1 request data state */
+	uint64_t d2_reqst                     : 5;  /**< DMA engine 2 request data state */
+	uint64_t d3_reqst                     : 5;  /**< DMA engine 3 request data state */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t d3_reqst                     : 5;
+	uint64_t d2_reqst                     : 5;
+	uint64_t d1_reqst                     : 5;
+	uint64_t d0_reqst                     : 5;
+	uint64_t reserved_25_31               : 7;
+	uint64_t d3_difst                     : 7;
+	uint64_t d2_difst                     : 7;
+	uint64_t d1_difst                     : 7;
+	uint64_t d0_difst                     : 7;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_dma_state1_p1_s      cn56xxp1;
+};
+typedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t;
+
+/**
+ * cvmx_npei_dma_state2
+ *
+ * NPEI_DMA_STATE2 = NPI's DMA State 2
+ *
+ * Results from DMA state register 2
+ */
+union cvmx_npei_dma_state2
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t ndwe                         : 4;  /**< DMA L2C Write State */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ndre                         : 5;  /**< DMA L2C Read State */
+	uint64_t reserved_10_15               : 6;
+	uint64_t prd                          : 10; /**< DMA PICe Read State */
+#else
+	uint64_t prd                          : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t ndre                         : 5;
+	uint64_t reserved_21_23               : 3;
+	uint64_t ndwe                         : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_npei_dma_state2_s         cn52xx;
+};
+typedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t;
+
+/**
+ * cvmx_npei_dma_state2_p1
+ *
+ * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State
+ *
+ * DMA engine Debug information.
+ */
+union cvmx_npei_dma_state2_p1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state2_p1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_45_63               : 19;
+	uint64_t d0_dffst                     : 9;  /**< DMA engine 0 dif instruction fetch state */
+	uint64_t d1_dffst                     : 9;  /**< DMA engine 1 dif instruction fetch state */
+	uint64_t d2_dffst                     : 9;  /**< DMA engine 2 dif instruction fetch state */
+	uint64_t d3_dffst                     : 9;  /**< DMA engine 3 dif instruction fetch state */
+	uint64_t d4_dffst                     : 9;  /**< DMA engine 4 dif instruction fetch state */
+#else
+	uint64_t d4_dffst                     : 9;
+	uint64_t d3_dffst                     : 9;
+	uint64_t d2_dffst                     : 9;
+	uint64_t d1_dffst                     : 9;
+	uint64_t d0_dffst                     : 9;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} s;
+	struct cvmx_npei_dma_state2_p1_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_45_63               : 19;
+	uint64_t d0_dffst                     : 9;  /**< DMA engine 0 dif instruction fetch state */
+	uint64_t d1_dffst                     : 9;  /**< DMA engine 1 dif instruction fetch state */
+	uint64_t d2_dffst                     : 9;  /**< DMA engine 2 dif instruction fetch state */
+	uint64_t d3_dffst                     : 9;  /**< DMA engine 3 dif instruction fetch state */
+	uint64_t reserved_0_8                 : 9;
+#else
+	uint64_t reserved_0_8                 : 9;
+	uint64_t d3_dffst                     : 9;
+	uint64_t d2_dffst                     : 9;
+	uint64_t d1_dffst                     : 9;
+	uint64_t d0_dffst                     : 9;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_dma_state2_p1_s      cn56xxp1;
+};
+typedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t;
+
+/**
+ * cvmx_npei_dma_state3_p1
+ *
+ * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State
+ *
+ * DMA engine Debug information.
+ */
+union cvmx_npei_dma_state3_p1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state3_p1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t d0_drest                     : 15; /**< DMA engine 0 dre state */
+	uint64_t d1_drest                     : 15; /**< DMA engine 1 dre state */
+	uint64_t d2_drest                     : 15; /**< DMA engine 2 dre state */
+	uint64_t d3_drest                     : 15; /**< DMA engine 3 dre state */
+#else
+	uint64_t d3_drest                     : 15;
+	uint64_t d2_drest                     : 15;
+	uint64_t d1_drest                     : 15;
+	uint64_t d0_drest                     : 15;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_npei_dma_state3_p1_s      cn52xxp1;
+	struct cvmx_npei_dma_state3_p1_s      cn56xxp1;
+};
+typedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t;
+
+/**
+ * cvmx_npei_dma_state4_p1
+ *
+ * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State
+ *
+ * DMA engine Debug information.
+ */
+union cvmx_npei_dma_state4_p1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state4_p1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_52_63               : 12;
+	uint64_t d0_dwest                     : 13; /**< DMA engine 0 dwe state */
+	uint64_t d1_dwest                     : 13; /**< DMA engine 1 dwe state */
+	uint64_t d2_dwest                     : 13; /**< DMA engine 2 dwe state */
+	uint64_t d3_dwest                     : 13; /**< DMA engine 3 dwe state */
+#else
+	uint64_t d3_dwest                     : 13;
+	uint64_t d2_dwest                     : 13;
+	uint64_t d1_dwest                     : 13;
+	uint64_t d0_dwest                     : 13;
+	uint64_t reserved_52_63               : 12;
+#endif
+	} s;
+	struct cvmx_npei_dma_state4_p1_s      cn52xxp1;
+	struct cvmx_npei_dma_state4_p1_s      cn56xxp1;
+};
+typedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t;
+
+/**
+ * cvmx_npei_dma_state5_p1
+ *
+ * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State
+ *
+ * DMA engine Debug information.
+ */
+union cvmx_npei_dma_state5_p1
+{
+	uint64_t u64;
+	struct cvmx_npei_dma_state5_p1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t d4_drest                     : 15; /**< DMA engine 4 dre state */
+	uint64_t d4_dwest                     : 13; /**< DMA engine 4 dwe state */
+#else
+	uint64_t d4_dwest                     : 13;
+	uint64_t d4_drest                     : 15;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_npei_dma_state5_p1_s      cn56xxp1;
+};
+typedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t;
+
+/**
+ * cvmx_npei_int_a_enb
+ *
+ * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register
+ *
+ * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI
+ */
+union cvmx_npei_int_a_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_int_a_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pout_err                     : 1;  /**< Enables NPEI_INT_A_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pin_bp                       : 1;  /**< Enables NPEI_INT_A_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t p1_rdlk                      : 1;  /**< Enables NPEI_INT_A_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t p0_rdlk                      : 1;  /**< Enables NPEI_INT_A_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pgl_err                      : 1;  /**< Enables NPEI_INT_A_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pdi_err                      : 1;  /**< Enables NPEI_INT_A_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pop_err                      : 1;  /**< Enables NPEI_INT_A_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pins_err                     : 1;  /**< Enables NPEI_INT_A_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t p0_rdlk                      : 1;
+	uint64_t p1_rdlk                      : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_npei_int_a_enb_s          cn52xx;
+	struct cvmx_npei_int_a_enb_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_a_enb_s          cn56xx;
+};
+typedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t;
+
+/**
+ * cvmx_npei_int_a_enb2
+ *
+ * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register
+ *
+ * Used to enable the various interrupting conditions of NPEI
+ */
+union cvmx_npei_int_a_enb2
+{
+	uint64_t u64;
+	struct cvmx_npei_int_a_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pout_err                     : 1;  /**< Enables NPEI_INT_A_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pin_bp                       : 1;  /**< Enables NPEI_INT_A_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t p1_rdlk                      : 1;  /**< Enables NPEI_INT_A_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t p0_rdlk                      : 1;  /**< Enables NPEI_INT_A_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pgl_err                      : 1;  /**< Enables NPEI_INT_A_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pdi_err                      : 1;  /**< Enables NPEI_INT_A_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pop_err                      : 1;  /**< Enables NPEI_INT_A_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pins_err                     : 1;  /**< Enables NPEI_INT_A_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t p0_rdlk                      : 1;
+	uint64_t p1_rdlk                      : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_npei_int_a_enb2_s         cn52xx;
+	struct cvmx_npei_int_a_enb2_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dma1_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0_cpl                     : 1;  /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_a_enb2_s         cn56xx;
+};
+typedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t;
+
+/**
+ * cvmx_npei_int_a_sum
+ *
+ * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register
+ *
+ * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and
+ * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set.
+ */
+union cvmx_npei_int_a_sum
+{
+	uint64_t u64;
+	struct cvmx_npei_int_a_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
+                                                         See NPEI_PKT_IN_BP */
+	uint64_t p1_rdlk                      : 1;  /**< PCIe port 1 received a read lock. */
+	uint64_t p0_rdlk                      : 1;  /**< PCIe port 0 received a read lock. */
+	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+	uint64_t dma1_cpl                     : 1;  /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 1 */
+	uint64_t dma0_cpl                     : 1;  /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 0 */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t p0_rdlk                      : 1;
+	uint64_t p1_rdlk                      : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_npei_int_a_sum_s          cn52xx;
+	struct cvmx_npei_int_a_sum_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t dma1_cpl                     : 1;  /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 1 */
+	uint64_t dma0_cpl                     : 1;  /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 0 */
+#else
+	uint64_t dma0_cpl                     : 1;
+	uint64_t dma1_cpl                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_a_sum_s          cn56xx;
+};
+typedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t;
+
+/**
+ * cvmx_npei_int_enb
+ *
+ * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register
+ *
+ * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI
+ */
+union cvmx_npei_int_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM[61] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs1_dr                      : 1;  /**< Enables NPEI_INT_SUM[29] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs1_er                      : 1;  /**< Enables NPEI_INT_SUM[27] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs0_dr                      : 1;  /**< Enables NPEI_INT_SUM[22] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs0_er                      : 1;  /**< Enables NPEI_INT_SUM[20] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma4dbo                      : 1;  /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t mio_inta                     : 1;
+#endif
+	} s;
+	struct cvmx_npei_int_enb_s            cn52xx;
+	struct cvmx_npei_int_enb_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM[61] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs1_dr                      : 1;  /**< Enables NPEI_INT_SUM[29] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs1_er                      : 1;  /**< Enables NPEI_INT_SUM[27] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs0_dr                      : 1;  /**< Enables NPEI_INT_SUM[22] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t crs0_er                      : 1;  /**< Enables NPEI_INT_SUM[20] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t mio_inta                     : 1;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_enb_s            cn56xx;
+	struct cvmx_npei_int_enb_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_61_62               : 2;
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma4dbo                      : 1;  /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t reserved_61_62               : 2;
+	uint64_t mio_inta                     : 1;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_int_enb cvmx_npei_int_enb_t;
+
+/**
+ * cvmx_npei_int_enb2
+ *
+ * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register
+ *
+ * Used to enable the various interrupting conditions of NPI
+ */
+union cvmx_npei_int_enb2
+{
+	uint64_t u64;
+	struct cvmx_npei_int_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM2[61] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs1_dr                      : 1;  /**< Enables NPEI_INT_SUM2[29] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs1_er                      : 1;  /**< Enables NPEI_INT_SUM2[27] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs0_dr                      : 1;  /**< Enables NPEI_INT_SUM2[22] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs0_er                      : 1;  /**< Enables NPEI_INT_SUM2[20] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma4dbo                      : 1;  /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_UM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_npei_int_enb2_s           cn52xx;
+	struct cvmx_npei_int_enb2_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t int_a                        : 1;  /**< Enables NPEI_INT_SUM2[61] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM2[60] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM2[59] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM2[58] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM2[57] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM2[56] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM2[55] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM2[54] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM2[53] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM2[52] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM2[51] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM2[50] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM2[49] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM2[48] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM2[47] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM2[46] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM2[45] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM2[44] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM2[43] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM2[42] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM2[41] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM2[40] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM2[39] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM2[38] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM2[37] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM2[36] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM2[35] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM2[34] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM2[33] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM2[32] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM2[31] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM2[30] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs1_dr                      : 1;  /**< Enables NPEI_INT_SUM2[29] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM2[28] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs1_er                      : 1;  /**< Enables NPEI_INT_SUM2[27] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM2[26] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM2[25] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM2[24] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM2[23] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs0_dr                      : 1;  /**< Enables NPEI_INT_SUM2[22] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM2[21] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t crs0_er                      : 1;  /**< Enables NPEI_INT_SUM2[20] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM2[19] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM2[18] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM2[17] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM2[16] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM2[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM2[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM2[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM2[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM2[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM2[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM2[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM2[7] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM2[6] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM2[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM2[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM2[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM2[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM2[1] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_SUM2[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_enb2_s           cn56xx;
+	struct cvmx_npei_int_enb2_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t c1_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_ldwn                      : 1;  /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_exc                       : 1;  /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_exc                       : 1;  /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wf                     : 1;  /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wf                     : 1;  /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_bx                     : 1;  /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_wi                     : 1;  /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b2                     : 1;  /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b1                     : 1;  /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_un_b0                     : 1;  /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_bx                     : 1;  /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_wi                     : 1;  /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b2                     : 1;  /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b1                     : 1;  /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_up_b0                     : 1;  /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_hpint                     : 1;  /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_pmei                      : 1;  /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c1_wake                      : 1;  /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_se                        : 1;  /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_aeri                      : 1;  /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_hpint                     : 1;  /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_pmei                      : 1;  /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t c0_wake                      : 1;  /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_se                        : 1;  /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_aeri                      : 1;  /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t ptime                        : 1;  /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pidbof                       : 1;  /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t psldbof                      : 1;  /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime1                       : 1;  /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dtime0                       : 1;  /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt1                        : 1;  /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dcnt0                        : 1;  /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1fi                       : 1;  /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0fi                       : 1;  /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma4dbo                      : 1;  /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma3dbo                      : 1;  /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma2dbo                      : 1;  /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma1dbo                      : 1;  /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t dma0dbo                      : 1;  /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPEI_INT_UM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t;
+
+/**
+ * cvmx_npei_int_info
+ *
+ * NPEI_INT_INFO = NPI Interrupt Information
+ *
+ * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register.
+ */
+union cvmx_npei_int_info
+{
+	uint64_t u64;
+	struct cvmx_npei_int_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t pidbof                       : 6;  /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
+                                                         is set. This field when set will not change again
+                                                         unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */
+	uint64_t psldbof                      : 6;  /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit
+                                                         is set. This field when set will not change again
+                                                         unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */
+#else
+	uint64_t psldbof                      : 6;
+	uint64_t pidbof                       : 6;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_npei_int_info_s           cn52xx;
+	struct cvmx_npei_int_info_s           cn56xx;
+	struct cvmx_npei_int_info_s           cn56xxp1;
+};
+typedef union cvmx_npei_int_info cvmx_npei_int_info_t;
+
+/**
+ * cvmx_npei_int_sum
+ *
+ * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register
+ *
+ * Set when an interrupt condition occurs, write '1' to clear.
+ *
+ * HACK: These used to exist, how are TO handled?
+ *  <3>     PO0_2SML R/W1C    0x0         0         The packet being sent out on Port0 is smaller          $R     NS
+ *                                                            than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.
+ * <7>     I0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read instructions.
+ * <15>    P0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read packet data.
+ * <23>    G0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read a gather list.
+ * <31>    P0_PTOUT R/W1C    0x0         0         Port-0 output had a read timeout on a DATA/INFO         $R     NS
+ *                                                 pair.
+ */
+union cvmx_npei_int_sum
+{
+	uint64_t u64;
+	struct cvmx_npei_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t int_a                        : 1;  /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB
+                                                         register is set. */
+	uint64_t c1_ldwn                      : 1;  /**< Reset request due to link1 down status. */
+	uint64_t c0_ldwn                      : 1;  /**< Reset request due to link0 down status. */
+	uint64_t c1_exc                       : 1;  /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c0_exc                       : 1;  /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c1_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c1_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c0_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c0_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c1_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c1_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+	uint64_t c1_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t crs1_dr                      : 1;  /**< Had a CRS when Retries were disabled. */
+	uint64_t c1_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+	uint64_t crs1_er                      : 1;  /**< Had a CRS Timeout when Retries were enabled. */
+	uint64_t c1_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+	uint64_t c0_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c0_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+	uint64_t c0_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t crs0_dr                      : 1;  /**< Had a CRS when Retries were disabled. */
+	uint64_t c0_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+	uint64_t crs0_er                      : 1;  /**< Had a CRS Timeout when Retries were enabled. */
+	uint64_t c0_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in NPEI_PKT_TIME_INT. */
+	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in NPEI_PKT_CNT_INT. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in NPEI_INT_INFO[PIDBOF] */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in NPEI_INT_INFO[PSLDBOF] */
+	uint64_t dtime1                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+	uint64_t dtime0                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+	uint64_t dma1fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t dma0fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t dma4dbo                      : 1;  /**< DMA4 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma3dbo                      : 1;  /**< DMA3 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma2dbo                      : 1;  /**< DMA2 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma1dbo                      : 1;  /**< DMA1 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma0dbo                      : 1;  /**< DMA0 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t rml_wto                      : 1;  /**< RML write did not get commit in 0xffff core clocks. */
+	uint64_t rml_rto                      : 1;  /**< RML read did not return data in 0xffff core clocks. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pidbof                       : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t mio_inta                     : 1;
+#endif
+	} s;
+	struct cvmx_npei_int_sum_s            cn52xx;
+	struct cvmx_npei_int_sum_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t int_a                        : 1;  /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB
+                                                         register is set. */
+	uint64_t c1_ldwn                      : 1;  /**< Reset request due to link1 down status. */
+	uint64_t c0_ldwn                      : 1;  /**< Reset request due to link0 down status. */
+	uint64_t c1_exc                       : 1;  /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c0_exc                       : 1;  /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c1_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c1_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c0_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c0_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c1_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c1_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+	uint64_t c1_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t crs1_dr                      : 1;  /**< Had a CRS when Retries were disabled. */
+	uint64_t c1_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+	uint64_t crs1_er                      : 1;  /**< Had a CRS Timeout when Retries were enabled. */
+	uint64_t c1_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+	uint64_t c0_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c0_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+	uint64_t c0_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t crs0_dr                      : 1;  /**< Had a CRS when Retries were disabled. */
+	uint64_t c0_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+	uint64_t crs0_er                      : 1;  /**< Had a CRS Timeout when Retries were enabled. */
+	uint64_t c0_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+	uint64_t reserved_15_18               : 4;
+	uint64_t dtime1                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+	uint64_t dtime0                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+	uint64_t dma1fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t dma0fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma3dbo                      : 1;  /**< DMA3 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma2dbo                      : 1;  /**< DMA2 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma1dbo                      : 1;  /**< DMA1 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma0dbo                      : 1;  /**< DMA0 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t rml_wto                      : 1;  /**< RML write did not get commit in 0xffff core clocks. */
+	uint64_t rml_rto                      : 1;  /**< RML read did not return data in 0xffff core clocks. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t reserved_15_18               : 4;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t mio_inta                     : 1;
+#endif
+	} cn52xxp1;
+	struct cvmx_npei_int_sum_s            cn56xx;
+	struct cvmx_npei_int_sum_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Interrupt from MIO. */
+	uint64_t reserved_61_62               : 2;
+	uint64_t c1_ldwn                      : 1;  /**< Reset request due to link1 down status. */
+	uint64_t c0_ldwn                      : 1;  /**< Reset request due to link0 down status. */
+	uint64_t c1_exc                       : 1;  /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c0_exc                       : 1;  /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t c1_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_up_wf                     : 1;  /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+	uint64_t c0_un_wf                     : 1;  /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+	uint64_t c1_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c1_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+	uint64_t c1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+	uint64_t c1_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+	uint64_t c1_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+	uint64_t c1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+	uint64_t c0_un_bx                     : 1;  /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_un_b2                     : 1;  /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_un_b1                     : 1;  /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c0_up_bx                     : 1;  /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+	uint64_t c0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+	uint64_t c0_up_b2                     : 1;  /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+	uint64_t c0_up_b1                     : 1;  /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+	uint64_t c0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+	uint64_t c1_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c1_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+	uint64_t c1_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+	uint64_t c0_hpint                     : 1;  /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+	uint64_t c0_pmei                      : 1;  /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+	uint64_t c0_wake                      : 1;  /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_se                        : 1;  /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_aeri                      : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+	uint64_t reserved_15_18               : 4;
+	uint64_t dtime1                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+	uint64_t dtime0                       : 1;  /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+	uint64_t dma1fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t dma0fi                       : 1;  /**< DMA0 set Forced Interrupt. */
+	uint64_t dma4dbo                      : 1;  /**< DMA4 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma3dbo                      : 1;  /**< DMA3 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma2dbo                      : 1;  /**< DMA2 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma1dbo                      : 1;  /**< DMA1 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t dma0dbo                      : 1;  /**< DMA0 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t rml_wto                      : 1;  /**< RML write did not get commit in 0xffff core clocks. */
+	uint64_t rml_rto                      : 1;  /**< RML read did not return data in 0xffff core clocks. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t dma4dbo                      : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t reserved_15_18               : 4;
+	uint64_t c0_aeri                      : 1;
+	uint64_t reserved_20_20               : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t reserved_22_22               : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t reserved_29_29               : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t reserved_61_62               : 2;
+	uint64_t mio_inta                     : 1;
+#endif
+	} cn56xxp1;
+};
+typedef union cvmx_npei_int_sum cvmx_npei_int_sum_t;
+
+/**
+ * cvmx_npei_int_sum2
+ *
+ * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register
+ *
+ * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances.
+ */
+union cvmx_npei_int_sum2
+{
+	uint64_t u64;
+	struct cvmx_npei_int_sum2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mio_inta                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t reserved_62_62               : 1;
+	uint64_t int_a                        : 1;  /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB2
+                                                         register is set. */
+	uint64_t c1_ldwn                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_ldwn                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_exc                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_exc                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_wf                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_wf                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_wf                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_wf                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_bx                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_wi                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_b2                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_b1                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_un_b0                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_bx                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_wi                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_b2                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_b1                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_up_b0                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_bx                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_wi                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_b2                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_b1                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_un_b0                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_bx                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_wi                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_b2                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_b1                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_up_b0                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_hpint                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_pmei                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_wake                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t crs1_dr                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_se                        : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t crs1_er                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c1_aeri                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_hpint                     : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_pmei                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_wake                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t crs0_dr                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_se                        : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t crs0_er                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t c0_aeri                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t reserved_15_18               : 4;
+	uint64_t dtime1                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dtime0                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dcnt1                        : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dcnt0                        : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dma1fi                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dma0fi                       : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma3dbo                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dma2dbo                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dma1dbo                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t dma0dbo                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t iob2big                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t bar0_to                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t rml_wto                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+	uint64_t rml_rto                      : 1;  /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t dma0dbo                      : 1;
+	uint64_t dma1dbo                      : 1;
+	uint64_t dma2dbo                      : 1;
+	uint64_t dma3dbo                      : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t dma0fi                       : 1;
+	uint64_t dma1fi                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t reserved_15_18               : 4;
+	uint64_t c0_aeri                      : 1;
+	uint64_t crs0_er                      : 1;
+	uint64_t c0_se                        : 1;
+	uint64_t crs0_dr                      : 1;
+	uint64_t c0_wake                      : 1;
+	uint64_t c0_pmei                      : 1;
+	uint64_t c0_hpint                     : 1;
+	uint64_t c1_aeri                      : 1;
+	uint64_t crs1_er                      : 1;
+	uint64_t c1_se                        : 1;
+	uint64_t crs1_dr                      : 1;
+	uint64_t c1_wake                      : 1;
+	uint64_t c1_pmei                      : 1;
+	uint64_t c1_hpint                     : 1;
+	uint64_t c0_up_b0                     : 1;
+	uint64_t c0_up_b1                     : 1;
+	uint64_t c0_up_b2                     : 1;
+	uint64_t c0_up_wi                     : 1;
+	uint64_t c0_up_bx                     : 1;
+	uint64_t c0_un_b0                     : 1;
+	uint64_t c0_un_b1                     : 1;
+	uint64_t c0_un_b2                     : 1;
+	uint64_t c0_un_wi                     : 1;
+	uint64_t c0_un_bx                     : 1;
+	uint64_t c1_up_b0                     : 1;
+	uint64_t c1_up_b1                     : 1;
+	uint64_t c1_up_b2                     : 1;
+	uint64_t c1_up_wi                     : 1;
+	uint64_t c1_up_bx                     : 1;
+	uint64_t c1_un_b0                     : 1;
+	uint64_t c1_un_b1                     : 1;
+	uint64_t c1_un_b2                     : 1;
+	uint64_t c1_un_wi                     : 1;
+	uint64_t c1_un_bx                     : 1;
+	uint64_t c0_un_wf                     : 1;
+	uint64_t c1_un_wf                     : 1;
+	uint64_t c0_up_wf                     : 1;
+	uint64_t c1_up_wf                     : 1;
+	uint64_t c0_exc                       : 1;
+	uint64_t c1_exc                       : 1;
+	uint64_t c0_ldwn                      : 1;
+	uint64_t c1_ldwn                      : 1;
+	uint64_t int_a                        : 1;
+	uint64_t reserved_62_62               : 1;
+	uint64_t mio_inta                     : 1;
+#endif
+	} s;
+	struct cvmx_npei_int_sum2_s           cn52xx;
+	struct cvmx_npei_int_sum2_s           cn52xxp1;
+	struct cvmx_npei_int_sum2_s           cn56xx;
+};
+typedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t;
+
+/**
+ * cvmx_npei_last_win_rdata0
+ *
+ * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0
+ *
+ * The data from the last initiated window read.
+ */
+union cvmx_npei_last_win_rdata0
+{
+	uint64_t u64;
+	struct cvmx_npei_last_win_rdata0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_last_win_rdata0_s    cn52xx;
+	struct cvmx_npei_last_win_rdata0_s    cn52xxp1;
+	struct cvmx_npei_last_win_rdata0_s    cn56xx;
+	struct cvmx_npei_last_win_rdata0_s    cn56xxp1;
+};
+typedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t;
+
+/**
+ * cvmx_npei_last_win_rdata1
+ *
+ * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1
+ *
+ * The data from the last initiated window read.
+ */
+union cvmx_npei_last_win_rdata1
+{
+	uint64_t u64;
+	struct cvmx_npei_last_win_rdata1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_last_win_rdata1_s    cn52xx;
+	struct cvmx_npei_last_win_rdata1_s    cn52xxp1;
+	struct cvmx_npei_last_win_rdata1_s    cn56xx;
+	struct cvmx_npei_last_win_rdata1_s    cn56xxp1;
+};
+typedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t;
+
+/**
+ * cvmx_npei_mem_access_ctl
+ *
+ * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control
+ *
+ * Contains control for access to the PCIe address space.
+ */
+union cvmx_npei_mem_access_ctl
+{
+	uint64_t u64;
+	struct cvmx_npei_mem_access_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t max_word                     : 4;  /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCIe. Legal
+                                                         values are 1 to 16, where a '0' is treated as 16. */
+	uint64_t timer                        : 10; /**< When the NPEI starts a PP to PCIe write it waits
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+	uint64_t timer                        : 10;
+	uint64_t max_word                     : 4;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_npei_mem_access_ctl_s     cn52xx;
+	struct cvmx_npei_mem_access_ctl_s     cn52xxp1;
+	struct cvmx_npei_mem_access_ctl_s     cn56xx;
+	struct cvmx_npei_mem_access_ctl_s     cn56xxp1;
+};
+typedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t;
+
+/**
+ * cvmx_npei_mem_access_subid#
+ *
+ * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register
+ *
+ * Contains address index and control bits for access to memory from Core PPs.
+ */
+union cvmx_npei_mem_access_subidx
+{
+	uint64_t u64;
+	struct cvmx_npei_mem_access_subidx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
+                                                         Returns to the EXEC a zero for all read data. */
+	uint64_t port                         : 2;  /**< Port the request is sent to. */
+	uint64_t nmerge                       : 1;  /**< No merging is allowed in this window. */
+	uint64_t esr                          : 2;  /**< Endian-swap for Reads. */
+	uint64_t esw                          : 2;  /**< Endian-swap for Writes. */
+	uint64_t nsr                          : 1;  /**< No Snoop for Reads. */
+	uint64_t nsw                          : 1;  /**< No Snoop for Writes. */
+	uint64_t ror                          : 1;  /**< Relaxed Ordering for Reads. */
+	uint64_t row                          : 1;  /**< Relaxed Ordering for Writes. */
+	uint64_t ba                           : 30; /**< PCIe Adddress Bits <63:34>. */
+#else
+	uint64_t ba                           : 30;
+	uint64_t row                          : 1;
+	uint64_t ror                          : 1;
+	uint64_t nsw                          : 1;
+	uint64_t nsr                          : 1;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t nmerge                       : 1;
+	uint64_t port                         : 2;
+	uint64_t zero                         : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} s;
+	struct cvmx_npei_mem_access_subidx_s  cn52xx;
+	struct cvmx_npei_mem_access_subidx_s  cn52xxp1;
+	struct cvmx_npei_mem_access_subidx_s  cn56xx;
+	struct cvmx_npei_mem_access_subidx_s  cn56xxp1;
+};
+typedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t;
+
+/**
+ * cvmx_npei_msi_enb0
+ *
+ * NPEI_MSI_ENB0 = NPEI MSI Enable0
+ *
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0.
+ */
+union cvmx_npei_msi_enb0
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_enb0_s           cn52xx;
+	struct cvmx_npei_msi_enb0_s           cn52xxp1;
+	struct cvmx_npei_msi_enb0_s           cn56xx;
+	struct cvmx_npei_msi_enb0_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t;
+
+/**
+ * cvmx_npei_msi_enb1
+ *
+ * NPEI_MSI_ENB1 = NPEI MSI Enable1
+ *
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1.
+ */
+union cvmx_npei_msi_enb1
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_enb1_s           cn52xx;
+	struct cvmx_npei_msi_enb1_s           cn52xxp1;
+	struct cvmx_npei_msi_enb1_s           cn56xx;
+	struct cvmx_npei_msi_enb1_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t;
+
+/**
+ * cvmx_npei_msi_enb2
+ *
+ * NPEI_MSI_ENB2 = NPEI MSI Enable2
+ *
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2.
+ */
+union cvmx_npei_msi_enb2
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_enb2_s           cn52xx;
+	struct cvmx_npei_msi_enb2_s           cn52xxp1;
+	struct cvmx_npei_msi_enb2_s           cn56xx;
+	struct cvmx_npei_msi_enb2_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t;
+
+/**
+ * cvmx_npei_msi_enb3
+ *
+ * NPEI_MSI_ENB3 = NPEI MSI Enable3
+ *
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3.
+ */
+union cvmx_npei_msi_enb3
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_enb3_s           cn52xx;
+	struct cvmx_npei_msi_enb3_s           cn52xxp1;
+	struct cvmx_npei_msi_enb3_s           cn56xx;
+	struct cvmx_npei_msi_enb3_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t;
+
+/**
+ * cvmx_npei_msi_rcv0
+ *
+ * NPEI_MSI_RCV0 = NPEI MSI Receive0
+ *
+ * Contains bits [63:0] of the 256 bits oof MSI interrupts.
+ */
+union cvmx_npei_msi_rcv0
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_rcv0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_rcv0_s           cn52xx;
+	struct cvmx_npei_msi_rcv0_s           cn52xxp1;
+	struct cvmx_npei_msi_rcv0_s           cn56xx;
+	struct cvmx_npei_msi_rcv0_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t;
+
+/**
+ * cvmx_npei_msi_rcv1
+ *
+ * NPEI_MSI_RCV1 = NPEI MSI Receive1
+ *
+ * Contains bits [127:64] of the 256 bits oof MSI interrupts.
+ */
+union cvmx_npei_msi_rcv1
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_rcv1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_rcv1_s           cn52xx;
+	struct cvmx_npei_msi_rcv1_s           cn52xxp1;
+	struct cvmx_npei_msi_rcv1_s           cn56xx;
+	struct cvmx_npei_msi_rcv1_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t;
+
+/**
+ * cvmx_npei_msi_rcv2
+ *
+ * NPEI_MSI_RCV2 = NPEI MSI Receive2
+ *
+ * Contains bits [191:128] of the 256 bits oof MSI interrupts.
+ */
+union cvmx_npei_msi_rcv2
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_rcv2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_rcv2_s           cn52xx;
+	struct cvmx_npei_msi_rcv2_s           cn52xxp1;
+	struct cvmx_npei_msi_rcv2_s           cn56xx;
+	struct cvmx_npei_msi_rcv2_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t;
+
+/**
+ * cvmx_npei_msi_rcv3
+ *
+ * NPEI_MSI_RCV3 = NPEI MSI Receive3
+ *
+ * Contains bits [255:192] of the 256 bits oof MSI interrupts.
+ */
+union cvmx_npei_msi_rcv3
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_rcv3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_rcv3_s           cn52xx;
+	struct cvmx_npei_msi_rcv3_s           cn52xxp1;
+	struct cvmx_npei_msi_rcv3_s           cn56xx;
+	struct cvmx_npei_msi_rcv3_s           cn56xxp1;
+};
+typedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t;
+
+/**
+ * cvmx_npei_msi_rd_map
+ *
+ * NPEI_MSI_RD_MAP = NPEI MSI Read MAP
+ *
+ * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
+ */
+union cvmx_npei_msi_rd_map
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_rd_map_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t rd_int                       : 8;  /**< The value of the map at the location PREVIOUSLY
+                                                         written to the MSI_INT field of this register. */
+	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
+                                                         NPEI_PCIE_MSI_RCV register is written. */
+#else
+	uint64_t msi_int                      : 8;
+	uint64_t rd_int                       : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npei_msi_rd_map_s         cn52xx;
+	struct cvmx_npei_msi_rd_map_s         cn52xxp1;
+	struct cvmx_npei_msi_rd_map_s         cn56xx;
+	struct cvmx_npei_msi_rd_map_s         cn56xxp1;
+};
+typedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t;
+
+/**
+ * cvmx_npei_msi_w1c_enb0
+ *
+ * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0
+ *
+ * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1c_enb0
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1c_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1c_enb0_s       cn52xx;
+	struct cvmx_npei_msi_w1c_enb0_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t;
+
+/**
+ * cvmx_npei_msi_w1c_enb1
+ *
+ * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1
+ *
+ * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1c_enb1
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1c_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1c_enb1_s       cn52xx;
+	struct cvmx_npei_msi_w1c_enb1_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t;
+
+/**
+ * cvmx_npei_msi_w1c_enb2
+ *
+ * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2
+ *
+ * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1c_enb2
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1c_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1c_enb2_s       cn52xx;
+	struct cvmx_npei_msi_w1c_enb2_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t;
+
+/**
+ * cvmx_npei_msi_w1c_enb3
+ *
+ * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3
+ *
+ * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1c_enb3
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1c_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1c_enb3_s       cn52xx;
+	struct cvmx_npei_msi_w1c_enb3_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t;
+
+/**
+ * cvmx_npei_msi_w1s_enb0
+ *
+ * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0
+ *
+ * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1s_enb0
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1s_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1s_enb0_s       cn52xx;
+	struct cvmx_npei_msi_w1s_enb0_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t;
+
+/**
+ * cvmx_npei_msi_w1s_enb1
+ *
+ * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1
+ *
+ * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1s_enb1
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1s_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1s_enb1_s       cn52xx;
+	struct cvmx_npei_msi_w1s_enb1_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t;
+
+/**
+ * cvmx_npei_msi_w1s_enb2
+ *
+ * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2
+ *
+ * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1s_enb2
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1s_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1s_enb2_s       cn52xx;
+	struct cvmx_npei_msi_w1s_enb2_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t;
+
+/**
+ * cvmx_npei_msi_w1s_enb3
+ *
+ * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3
+ *
+ * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register.
+ */
+union cvmx_npei_msi_w1s_enb3
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_w1s_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_npei_msi_w1s_enb3_s       cn52xx;
+	struct cvmx_npei_msi_w1s_enb3_s       cn56xx;
+};
+typedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t;
+
+/**
+ * cvmx_npei_msi_wr_map
+ *
+ * NPEI_MSI_WR_MAP = NPEI MSI Write MAP
+ *
+ * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
+ */
+union cvmx_npei_msi_wr_map
+{
+	uint64_t u64;
+	struct cvmx_npei_msi_wr_map_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ciu_int                      : 8;  /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
+                                                         will be set when the value specified in the
+                                                         MSI_INT of this register is recevied during a
+                                                         write to the NPEI_PCIE_MSI_RCV register. */
+	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
+                                                         NPEI_PCIE_MSI_RCV register is written. */
+#else
+	uint64_t msi_int                      : 8;
+	uint64_t ciu_int                      : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npei_msi_wr_map_s         cn52xx;
+	struct cvmx_npei_msi_wr_map_s         cn52xxp1;
+	struct cvmx_npei_msi_wr_map_s         cn56xx;
+	struct cvmx_npei_msi_wr_map_s         cn56xxp1;
+};
+typedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t;
+
+/**
+ * cvmx_npei_pcie_credit_cnt
+ *
+ * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count
+ *
+ * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic
+ * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two
+ * PCIE ports to be reset to the value in this register.
+ */
+union cvmx_npei_pcie_credit_cnt
+{
+	uint64_t u64;
+	struct cvmx_npei_pcie_credit_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p1_ncnt                      : 8;  /**< Port1 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p1_pcnt                      : 8;  /**< Port1 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ccnt                      : 8;  /**< Port0 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ncnt                      : 8;  /**< Port0 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p0_pcnt                      : 8;  /**< Port0 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+#else
+	uint64_t p0_pcnt                      : 8;
+	uint64_t p0_ncnt                      : 8;
+	uint64_t p0_ccnt                      : 8;
+	uint64_t p1_pcnt                      : 8;
+	uint64_t p1_ncnt                      : 8;
+	uint64_t p1_ccnt                      : 8;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_npei_pcie_credit_cnt_s    cn52xx;
+	struct cvmx_npei_pcie_credit_cnt_s    cn56xx;
+};
+typedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t;
+
+/**
+ * cvmx_npei_pcie_msi_rcv
+ *
+ * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive
+ *
+ * Register where MSI writes are directed from the PCIe.
+ */
+union cvmx_npei_pcie_msi_rcv
+{
+	uint64_t u64;
+	struct cvmx_npei_pcie_msi_rcv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+#else
+	uint64_t intr                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_npei_pcie_msi_rcv_s       cn52xx;
+	struct cvmx_npei_pcie_msi_rcv_s       cn52xxp1;
+	struct cvmx_npei_pcie_msi_rcv_s       cn56xx;
+	struct cvmx_npei_pcie_msi_rcv_s       cn56xxp1;
+};
+typedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t;
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b1
+ *
+ * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1
+ *
+ * Register where MSI writes are directed from the PCIe.
+ */
+union cvmx_npei_pcie_msi_rcv_b1
+{
+	uint64_t u64;
+	struct cvmx_npei_pcie_msi_rcv_b1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t intr                         : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npei_pcie_msi_rcv_b1_s    cn52xx;
+	struct cvmx_npei_pcie_msi_rcv_b1_s    cn52xxp1;
+	struct cvmx_npei_pcie_msi_rcv_b1_s    cn56xx;
+	struct cvmx_npei_pcie_msi_rcv_b1_s    cn56xxp1;
+};
+typedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t;
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b2
+ *
+ * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2
+ *
+ * Register where MSI writes are directed from the PCIe.
+ */
+union cvmx_npei_pcie_msi_rcv_b2
+{
+	uint64_t u64;
+	struct cvmx_npei_pcie_msi_rcv_b2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t intr                         : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_npei_pcie_msi_rcv_b2_s    cn52xx;
+	struct cvmx_npei_pcie_msi_rcv_b2_s    cn52xxp1;
+	struct cvmx_npei_pcie_msi_rcv_b2_s    cn56xx;
+	struct cvmx_npei_pcie_msi_rcv_b2_s    cn56xxp1;
+};
+typedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t;
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b3
+ *
+ * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3
+ *
+ * Register where MSI writes are directed from the PCIe.
+ */
+union cvmx_npei_pcie_msi_rcv_b3
+{
+	uint64_t u64;
+	struct cvmx_npei_pcie_msi_rcv_b3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_23                : 24;
+#else
+	uint64_t reserved_0_23                : 24;
+	uint64_t intr                         : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pcie_msi_rcv_b3_s    cn52xx;
+	struct cvmx_npei_pcie_msi_rcv_b3_s    cn52xxp1;
+	struct cvmx_npei_pcie_msi_rcv_b3_s    cn56xx;
+	struct cvmx_npei_pcie_msi_rcv_b3_s    cn56xxp1;
+};
+typedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t;
+
+/**
+ * cvmx_npei_pkt#_cnts
+ *
+ * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts
+ *
+ * The counters for output rings.
+ */
+union cvmx_npei_pktx_cnts
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t timer                        : 22; /**< Timer incremented every 1024 core clocks
+                                                         when NPEI_PKTS#_CNTS[CNT] is non zero. Field
+                                                         cleared when NPEI_PKTS#_CNTS[CNT] goes to 0.
+                                                         Field is also cleared when NPEI_PKT_TIME_INT is
+                                                         cleared.
+                                                         The first increment of this count can occur
+                                                         between 0 to 1023 core clocks. */
+	uint64_t cnt                          : 32; /**< ring counter. This field is incremented as
+                                                         packets are sent out and decremented in response to
+                                                         writes to this field.
+                                                         When NPEI_PKT_OUT_BMODE is '0' a value of 1 is
+                                                         added to the register for each packet, when '1'
+                                                         and the info-pointer is NOT used the length of the
+                                                         packet plus 8 is added, when '1' and info-pointer
+                                                         mode IS used the packet length is added to this
+                                                         field. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t timer                        : 22;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_npei_pktx_cnts_s          cn52xx;
+	struct cvmx_npei_pktx_cnts_s          cn56xx;
+};
+typedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t;
+
+/**
+ * cvmx_npei_pkt#_in_bp
+ *
+ * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure
+ *
+ * The counters and thresholds for input packets to apply backpressure to processing of the packets.
+ */
+union cvmx_npei_pktx_in_bp
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_in_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wmark                        : 32; /**< When CNT is greater than this threshold no more
+                                                         packets will be processed for this ring.
+                                                         When writing this field of the NPEI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+	uint64_t cnt                          : 32; /**< ring counter. This field is incremented by one
+                                                         whenever OCTEON receives, buffers, and creates a
+                                                         work queue entry for a packet that arrives by the
+                                                         cooresponding input ring. A write to this field
+                                                         will be subtracted from the field value.
+                                                         When writing this field of the NPEI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t wmark                        : 32;
+#endif
+	} s;
+	struct cvmx_npei_pktx_in_bp_s         cn52xx;
+	struct cvmx_npei_pktx_in_bp_s         cn56xx;
+};
+typedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t;
+
+/**
+ * cvmx_npei_pkt#_instr_baddr
+ *
+ * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address
+ *
+ * Start of Instruction for input packets.
+ */
+union cvmx_npei_pktx_instr_baddr
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_instr_baddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 61; /**< Base address for Instructions. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t addr                         : 61;
+#endif
+	} s;
+	struct cvmx_npei_pktx_instr_baddr_s   cn52xx;
+	struct cvmx_npei_pktx_instr_baddr_s   cn56xx;
+};
+typedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t;
+
+/**
+ * cvmx_npei_pkt#_instr_baoff_dbell
+ *
+ * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell
+ *
+ * The doorbell and base address offset for next read.
+ */
+union cvmx_npei_pktx_instr_baoff_dbell
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_instr_baoff_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t aoff                         : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
+                                                         where the next instruction will be read. */
+	uint64_t dbell                        : 32; /**< Instruction doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. A write of 0xffffffff will set the
+                                                         DBELL and AOFF fields to '0'. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t aoff                         : 32;
+#endif
+	} s;
+	struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
+	struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
+};
+typedef union cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_baoff_dbell_t;
+
+/**
+ * cvmx_npei_pkt#_instr_fifo_rsize
+ *
+ * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size.
+ *
+ * Fifo field and ring size for Instructions.
+ */
+union cvmx_npei_pktx_instr_fifo_rsize
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_instr_fifo_rsize_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t max                          : 9;  /**< Max Fifo Size. */
+	uint64_t rrp                          : 9;  /**< Fifo read pointer. */
+	uint64_t wrp                          : 9;  /**< Fifo write pointer. */
+	uint64_t fcnt                         : 5;  /**< Fifo count. */
+	uint64_t rsize                        : 32; /**< Instruction ring size. */
+#else
+	uint64_t rsize                        : 32;
+	uint64_t fcnt                         : 5;
+	uint64_t wrp                          : 9;
+	uint64_t rrp                          : 9;
+	uint64_t max                          : 9;
+#endif
+	} s;
+	struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
+	struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
+};
+typedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t;
+
+/**
+ * cvmx_npei_pkt#_instr_header
+ *
+ * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header.
+ *
+ * VAlues used to build input packet header.
+ */
+union cvmx_npei_pktx_instr_header
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_instr_header_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t reserved_38_42               : 5;
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t reserved_35_35               : 1;
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t reserved_22_27               : 6;
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t reserved_16_20               : 5;
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t reserved_13_13               : 1;
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t reserved_0_5                 : 6;
+#else
+	uint64_t reserved_0_5                 : 6;
+	uint64_t skp_len                      : 7;
+	uint64_t reserved_13_13               : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t reserved_16_20               : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t reserved_22_27               : 6;
+	uint64_t rskp_len                     : 7;
+	uint64_t reserved_35_35               : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t reserved_38_42               : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npei_pktx_instr_header_s  cn52xx;
+	struct cvmx_npei_pktx_instr_header_s  cn56xx;
+};
+typedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t;
+
+/**
+ * cvmx_npei_pkt#_slist_baddr
+ *
+ * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address
+ *
+ * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
+ */
+union cvmx_npei_pktx_slist_baddr
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_slist_baddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 60; /**< Base address for scatter list pointers. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t addr                         : 60;
+#endif
+	} s;
+	struct cvmx_npei_pktx_slist_baddr_s   cn52xx;
+	struct cvmx_npei_pktx_slist_baddr_s   cn56xx;
+};
+typedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t;
+
+/**
+ * cvmx_npei_pkt#_slist_baoff_dbell
+ *
+ * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell
+ *
+ * The doorbell and base address offset for next read.
+ */
+union cvmx_npei_pktx_slist_baoff_dbell
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_slist_baoff_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t aoff                         : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
+                                                         where the next SList pointer will be read.
+                                                         A write of 0xFFFFFFFF to the DBELL field will
+                                                         clear DBELL and AOFF */
+	uint64_t dbell                        : 32; /**< Scatter list doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. The value of this field is
+                                                         decremented as read operations are ISSUED for
+                                                         scatter pointers.
+                                                         A write of 0xFFFFFFFF will clear DBELL and AOFF */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t aoff                         : 32;
+#endif
+	} s;
+	struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
+	struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
+};
+typedef union cvmx_npei_pktx_slist_baoff_dbell cvmx_npei_pktx_slist_baoff_dbell_t;
+
+/**
+ * cvmx_npei_pkt#_slist_fifo_rsize
+ *
+ * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size.
+ *
+ * The number of scatter pointer pairs in the scatter list.
+ */
+union cvmx_npei_pktx_slist_fifo_rsize
+{
+	uint64_t u64;
+	struct cvmx_npei_pktx_slist_fifo_rsize_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rsize                        : 32; /**< The number of scatter pointer pairs contained in
+                                                         the scatter list ring. */
+#else
+	uint64_t rsize                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
+	struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
+};
+typedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t;
+
+/**
+ * cvmx_npei_pkt_cnt_int
+ *
+ * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt
+ *
+ * The packets rings that are interrupting because of Packet Counters.
+ */
+union cvmx_npei_pkt_cnt_int
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_cnt_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number is set when
+                                                         NPEI_PKT#_CNTS[CNT] is greater
+                                                         than NPEI_PKT_INT_LEVELS[CNT]. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_cnt_int_s        cn52xx;
+	struct cvmx_npei_pkt_cnt_int_s        cn56xx;
+};
+typedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t;
+
+/**
+ * cvmx_npei_pkt_cnt_int_enb
+ *
+ * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable
+ *
+ * Enable for the packets rings that are interrupting because of Packet Counters.
+ */
+union cvmx_npei_pkt_cnt_int_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_cnt_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number when set
+                                                         allows NPEI_PKT_CNT_INT to generate an interrupt. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_cnt_int_enb_s    cn52xx;
+	struct cvmx_npei_pkt_cnt_int_enb_s    cn56xx;
+};
+typedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t;
+
+/**
+ * cvmx_npei_pkt_data_out_es
+ *
+ * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap
+ *
+ * The Endian Swap for writing Data Out.
+ */
+union cvmx_npei_pkt_data_out_es
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_data_out_es_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t es                           : 64; /**< The endian swap mode for Packet rings 0 through 31.
+                                                         Two bits are used per ring (i.e. ring 0 [1:0],
+                                                         ring 1 [3:2], ....). */
+#else
+	uint64_t es                           : 64;
+#endif
+	} s;
+	struct cvmx_npei_pkt_data_out_es_s    cn52xx;
+	struct cvmx_npei_pkt_data_out_es_s    cn56xx;
+};
+typedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t;
+
+/**
+ * cvmx_npei_pkt_data_out_ns
+ *
+ * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop
+ *
+ * The NS field for the TLP when writing packet data.
+ */
+union cvmx_npei_pkt_data_out_ns
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_data_out_ns_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nsr                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable NS in TLP header. */
+#else
+	uint64_t nsr                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_data_out_ns_s    cn52xx;
+	struct cvmx_npei_pkt_data_out_ns_s    cn56xx;
+};
+typedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t;
+
+/**
+ * cvmx_npei_pkt_data_out_ror
+ *
+ * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering
+ *
+ * The ROR field for the TLP when writing Packet Data.
+ */
+union cvmx_npei_pkt_data_out_ror
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_data_out_ror_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ror                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable ROR in TLP header. */
+#else
+	uint64_t ror                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_data_out_ror_s   cn52xx;
+	struct cvmx_npei_pkt_data_out_ror_s   cn56xx;
+};
+typedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t;
+
+/**
+ * cvmx_npei_pkt_dpaddr
+ *
+ * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr
+ *
+ * Used to detemine address and attributes for packet data writes.
+ */
+union cvmx_npei_pkt_dpaddr
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_dpaddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dptr                         : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will use:
+                                                         the address[63:60] to write packet data
+                                                         comes from the DPTR[63:60] in the scatter-list
+                                                         pair and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. */
+#else
+	uint64_t dptr                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_dpaddr_s         cn52xx;
+	struct cvmx_npei_pkt_dpaddr_s         cn56xx;
+};
+typedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t;
+
+/**
+ * cvmx_npei_pkt_in_bp
+ *
+ * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure
+ *
+ * Which input rings have backpressure applied.
+ */
+union cvmx_npei_pkt_in_bp
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_in_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bp                           : 32; /**< A packet input  ring that has its count greater
+                                                         than its WMARK will have backpressure applied.
+                                                         Each of the 32 bits coorespond to an input ring.
+                                                         When '1' that ring has backpressure applied an
+                                                         will fetch no more instructions, but will process
+                                                         any previously fetched instructions. */
+#else
+	uint64_t bp                           : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_in_bp_s          cn52xx;
+	struct cvmx_npei_pkt_in_bp_s          cn56xx;
+};
+typedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t;
+
+/**
+ * cvmx_npei_pkt_in_done#_cnts
+ *
+ * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts
+ *
+ * Counters for instructions completed on Input rings.
+ */
+union cvmx_npei_pkt_in_donex_cnts
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_in_donex_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< This field is incrmented by '1' when an instruction
+                                                         is completed. This field is incremented as the
+                                                         last of the data is read from the PCIe. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_in_donex_cnts_s  cn52xx;
+	struct cvmx_npei_pkt_in_donex_cnts_s  cn56xx;
+};
+typedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t;
+
+/**
+ * cvmx_npei_pkt_in_instr_counts
+ *
+ * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts
+ *
+ * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
+ */
+union cvmx_npei_pkt_in_instr_counts
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_in_instr_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_cnt                       : 32; /**< Shows the number of packets sent to the IPD. */
+	uint64_t rd_cnt                       : 32; /**< Shows the value of instructions that have had reads
+                                                         issued for them.
+                                                         to the Packet-ring is in reset. */
+#else
+	uint64_t rd_cnt                       : 32;
+	uint64_t wr_cnt                       : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
+	struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
+};
+typedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t;
+
+/**
+ * cvmx_npei_pkt_in_pcie_port
+ *
+ * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment
+ *
+ * Assigns Packet Input rings to PCIe ports.
+ */
+union cvmx_npei_pkt_in_pcie_port
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_in_pcie_port_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pp                           : 64; /**< The PCIe port that the Packet ring number is
+                                                         assigned. Two bits are used per ring (i.e. ring 0
+                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to PCIe Port 0, a '1'
+                                                         PCIe Port 1, '2' and '3' are reserved. */
+#else
+	uint64_t pp                           : 64;
+#endif
+	} s;
+	struct cvmx_npei_pkt_in_pcie_port_s   cn52xx;
+	struct cvmx_npei_pkt_in_pcie_port_s   cn56xx;
+};
+typedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t;
+
+/**
+ * cvmx_npei_pkt_input_control
+ *
+ * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control
+ *
+ * Control for reads for gather list and instructions.
+ */
+union cvmx_npei_pkt_input_control
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_input_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet ring is fixed in priority,
+                                                         where the lower ring number has higher priority. */
+	uint64_t pbp_dhi                      : 13; /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+	uint64_t d_nsr                        : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+	uint64_t d_esr                        : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+	uint64_t d_ror                        : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+	uint64_t use_csr                      : 1;  /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+	uint64_t nsr                          : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+	uint64_t esr                          : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+	uint64_t ror                          : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+	uint64_t ror                          : 1;
+	uint64_t esr                          : 2;
+	uint64_t nsr                          : 1;
+	uint64_t use_csr                      : 1;
+	uint64_t d_ror                        : 1;
+	uint64_t d_esr                        : 2;
+	uint64_t d_nsr                        : 1;
+	uint64_t pbp_dhi                      : 13;
+	uint64_t pkt_rr                       : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_npei_pkt_input_control_s  cn52xx;
+	struct cvmx_npei_pkt_input_control_s  cn56xx;
+};
+typedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t;
+
+/**
+ * cvmx_npei_pkt_instr_enb
+ *
+ * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable
+ *
+ * Enables the instruction fetch for a Packet-ring.
+ */
+union cvmx_npei_pkt_instr_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_instr_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enb                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is enabled. */
+#else
+	uint64_t enb                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_instr_enb_s      cn52xx;
+	struct cvmx_npei_pkt_instr_enb_s      cn56xx;
+};
+typedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t;
+
+/**
+ * cvmx_npei_pkt_instr_rd_size
+ *
+ * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size
+ *
+ * The number of instruction allowed to be read at one time.
+ */
+union cvmx_npei_pkt_instr_rd_size
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_instr_rd_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rdsize                       : 64; /**< Number of instructions to be read in one PCIe read
+                                                         request for the 4 PKOport - 8 rings. Every two bits
+                                                         (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
+                                                         combinations.
+                                                         - 15:0  PKOPort0,Ring 7..0  31:16 PKOPort1,Ring 7..0
+                                                         - 47:32 PKOPort2,Ring 7..0  63:48 PKOPort3,Ring 7..0
+                                                         Two bit value are:
+                                                         0 - 1 Instruction
+                                                         1 - 2 Instructions
+                                                         2 - 3 Instructions
+                                                         3 - 4 Instructions */
+#else
+	uint64_t rdsize                       : 64;
+#endif
+	} s;
+	struct cvmx_npei_pkt_instr_rd_size_s  cn52xx;
+	struct cvmx_npei_pkt_instr_rd_size_s  cn56xx;
+};
+typedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t;
+
+/**
+ * cvmx_npei_pkt_instr_size
+ *
+ * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size
+ *
+ * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
+ */
+union cvmx_npei_pkt_instr_size
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_instr_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t is_64b                       : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is a 64-byte instruction. */
+#else
+	uint64_t is_64b                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_instr_size_s     cn52xx;
+	struct cvmx_npei_pkt_instr_size_s     cn56xx;
+};
+typedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t;
+
+/**
+ * cvmx_npei_pkt_int_levels
+ *
+ * 0x90F0 reserved NPEI_PKT_PCIE_PORT2
+ *
+ *
+ *                  NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels
+ *
+ * Output packet interrupt levels.
+ */
+union cvmx_npei_pkt_int_levels
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_int_levels_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t time                         : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this
+                                                         value an interrupt is generated. */
+	uint64_t cnt                          : 32; /**< When NPEI_PKT#_CNTS[CNT] becomes
+                                                         greater than this value an interrupt is generated. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t time                         : 22;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_npei_pkt_int_levels_s     cn52xx;
+	struct cvmx_npei_pkt_int_levels_s     cn56xx;
+};
+typedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t;
+
+/**
+ * cvmx_npei_pkt_iptr
+ *
+ * NPEI_PKT_IPTR = NPEI's Packet Info Poitner
+ *
+ * Controls using the Info-Pointer to store length and data.
+ */
+union cvmx_npei_pkt_iptr
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_iptr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iptr                         : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will use the Info-Pointer to
+                                                         store length and data. */
+#else
+	uint64_t iptr                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_iptr_s           cn52xx;
+	struct cvmx_npei_pkt_iptr_s           cn56xx;
+};
+typedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t;
+
+/**
+ * cvmx_npei_pkt_out_bmode
+ *
+ * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode
+ *
+ * Control the updating of the NPEI_PKT#_CNT register.
+ */
+union cvmx_npei_pkt_out_bmode
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_out_bmode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bmode                        : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will have its NPEI_PKT#_CNT
+                                                         register updated with the number of bytes in the
+                                                         packet sent, when '0' the register will have a
+                                                         value of '1' added. */
+#else
+	uint64_t bmode                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_out_bmode_s      cn52xx;
+	struct cvmx_npei_pkt_out_bmode_s      cn56xx;
+};
+typedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t;
+
+/**
+ * cvmx_npei_pkt_out_enb
+ *
+ * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable
+ *
+ * Enables the output packet engines.
+ */
+union cvmx_npei_pkt_out_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_out_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enb                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is enabled.
+                                                         If an error occurs on reading pointers for an
+                                                         output ring, the ring will be disabled by clearing
+                                                         the bit associated with the ring to '0'. */
+#else
+	uint64_t enb                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_out_enb_s        cn52xx;
+	struct cvmx_npei_pkt_out_enb_s        cn56xx;
+};
+typedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t;
+
+/**
+ * cvmx_npei_pkt_output_wmark
+ *
+ * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark
+ *
+ * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
+ */
+union cvmx_npei_pkt_output_wmark
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_output_wmark_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wmark                        : 32; /**< Value when DBELL count drops below backpressure
+                                                         for the ring will be applied to the PKO. */
+#else
+	uint64_t wmark                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_output_wmark_s   cn52xx;
+	struct cvmx_npei_pkt_output_wmark_s   cn56xx;
+};
+typedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t;
+
+/**
+ * cvmx_npei_pkt_pcie_port
+ *
+ * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment
+ *
+ * Assigns Packet Ports to PCIe ports.
+ */
+union cvmx_npei_pkt_pcie_port
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_pcie_port_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pp                           : 64; /**< The PCIe port that the Packet ring number is
+                                                         assigned. Two bits are used per ring (i.e. ring 0
+                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to PCIe Port 0, a '1'
+                                                         PCIe Port 1, '2' and '3' are reserved. */
+#else
+	uint64_t pp                           : 64;
+#endif
+	} s;
+	struct cvmx_npei_pkt_pcie_port_s      cn52xx;
+	struct cvmx_npei_pkt_pcie_port_s      cn56xx;
+};
+typedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t;
+
+/**
+ * cvmx_npei_pkt_port_in_rst
+ *
+ * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset
+ *
+ * Vector bits related to ring-port for ones that are reset.
+ */
+union cvmx_npei_pkt_port_in_rst
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_port_in_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t in_rst                       : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the inbound Packet-ring is in reset. */
+	uint64_t out_rst                      : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the outbound Packet-ring is in reset. */
+#else
+	uint64_t out_rst                      : 32;
+	uint64_t in_rst                       : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_port_in_rst_s    cn52xx;
+	struct cvmx_npei_pkt_port_in_rst_s    cn56xx;
+};
+typedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t;
+
+/**
+ * cvmx_npei_pkt_slist_es
+ *
+ * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap
+ *
+ * The Endian Swap for Scatter List Read.
+ */
+union cvmx_npei_pkt_slist_es
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_slist_es_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t es                           : 64; /**< The endian swap mode for Packet rings 0 through 31.
+                                                         Two bits are used per ring (i.e. ring 0 [1:0],
+                                                         ring 1 [3:2], ....). */
+#else
+	uint64_t es                           : 64;
+#endif
+	} s;
+	struct cvmx_npei_pkt_slist_es_s       cn52xx;
+	struct cvmx_npei_pkt_slist_es_s       cn56xx;
+};
+typedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t;
+
+/**
+ * cvmx_npei_pkt_slist_id_size
+ *
+ * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size
+ *
+ * The Size of the information and data fields pointed to by Scatter List pointers.
+ */
+union cvmx_npei_pkt_slist_id_size
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_slist_id_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t isize                        : 7;  /**< Information size. Legal sizes are 0 to 120. */
+	uint64_t bsize                        : 16; /**< Data size. */
+#else
+	uint64_t bsize                        : 16;
+	uint64_t isize                        : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_npei_pkt_slist_id_size_s  cn52xx;
+	struct cvmx_npei_pkt_slist_id_size_s  cn56xx;
+};
+typedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t;
+
+/**
+ * cvmx_npei_pkt_slist_ns
+ *
+ * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop
+ *
+ * The NS field for the TLP when fetching Scatter List.
+ */
+union cvmx_npei_pkt_slist_ns
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_slist_ns_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nsr                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable NS in TLP header. */
+#else
+	uint64_t nsr                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_slist_ns_s       cn52xx;
+	struct cvmx_npei_pkt_slist_ns_s       cn56xx;
+};
+typedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t;
+
+/**
+ * cvmx_npei_pkt_slist_ror
+ *
+ * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering
+ *
+ * The ROR field for the TLP when fetching Scatter List.
+ */
+union cvmx_npei_pkt_slist_ror
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_slist_ror_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ror                          : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable ROR in TLP header. */
+#else
+	uint64_t ror                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_slist_ror_s      cn52xx;
+	struct cvmx_npei_pkt_slist_ror_s      cn56xx;
+};
+typedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t;
+
+/**
+ * cvmx_npei_pkt_time_int
+ *
+ * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt
+ *
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+union cvmx_npei_pkt_time_int
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_time_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number is set when
+                                                         NPEI_PKT#_CNTS[TIMER] is greater than
+                                                         NPEI_PKT_INT_LEVELS[TIME]. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_time_int_s       cn52xx;
+	struct cvmx_npei_pkt_time_int_s       cn56xx;
+};
+typedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t;
+
+/**
+ * cvmx_npei_pkt_time_int_enb
+ *
+ * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable
+ *
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+union cvmx_npei_pkt_time_int_enb
+{
+	uint64_t u64;
+	struct cvmx_npei_pkt_time_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Bit vector cooresponding to ring number when set
+                                                         allows NPEI_PKT_TIME_INT to generate an interrupt. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_pkt_time_int_enb_s   cn52xx;
+	struct cvmx_npei_pkt_time_int_enb_s   cn56xx;
+};
+typedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t;
+
+/**
+ * cvmx_npei_rsl_int_blocks
+ *
+ * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register
+ *
+ * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
+ * that presently has an interrupt pending. The Field Description below supplies the name of the
+ * register that software should read to find out why that intterupt bit is set.
+ */
+union cvmx_npei_rsl_int_blocks
+{
+	uint64_t u64;
+	struct cvmx_npei_rsl_int_blocks_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
+	uint64_t lmc1                         : 1;  /**< LMC1_MEM_CFG0 */
+	uint64_t agl                          : 1;  /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */
+	uint64_t reserved_24_27               : 4;
+	uint64_t asxpcs1                      : 1;  /**< PCS1_INT*_REG */
+	uint64_t asxpcs0                      : 1;  /**< PCS0_INT*_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP_INT_REG. */
+	uint64_t spx1                         : 1;  /**< Always reads as zero */
+	uint64_t spx0                         : 1;  /**< Always reads as zero */
+	uint64_t lmc0                         : 1;  /**< LMC0_MEM_CFG0 */
+	uint64_t l2c                          : 1;  /**< L2C_INT_STAT */
+	uint64_t usb1                         : 1;  /**< Always reads as zero */
+	uint64_t rad                          : 1;  /**< RAD_REG_ERROR */
+	uint64_t usb                          : 1;  /**< USBN0_INT_SUM */
+	uint64_t pow                          : 1;  /**< POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< Always reads as zero */
+	uint64_t fpa                          : 1;  /**< FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY_INT_SUM */
+	uint64_t npei                         : 1;  /**< NPEI_INT_SUM */
+	uint64_t gmx1                         : 1;  /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t npei                         : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t usb1                         : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc0                         : 1;
+	uint64_t spx0                         : 1;
+	uint64_t spx1                         : 1;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asxpcs0                      : 1;
+	uint64_t asxpcs1                      : 1;
+	uint64_t reserved_24_27               : 4;
+	uint64_t agl                          : 1;
+	uint64_t lmc1                         : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_npei_rsl_int_blocks_s     cn52xx;
+	struct cvmx_npei_rsl_int_blocks_s     cn52xxp1;
+	struct cvmx_npei_rsl_int_blocks_s     cn56xx;
+	struct cvmx_npei_rsl_int_blocks_s     cn56xxp1;
+};
+typedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t;
+
+/**
+ * cvmx_npei_scratch_1
+ *
+ * NPEI_SCRATCH_1 = NPEI's Scratch 1
+ *
+ * A general purpose 64 bit register for SW use.
+ */
+union cvmx_npei_scratch_1
+{
+	uint64_t u64;
+	struct cvmx_npei_scratch_1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_npei_scratch_1_s          cn52xx;
+	struct cvmx_npei_scratch_1_s          cn52xxp1;
+	struct cvmx_npei_scratch_1_s          cn56xx;
+	struct cvmx_npei_scratch_1_s          cn56xxp1;
+};
+typedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t;
+
+/**
+ * cvmx_npei_state1
+ *
+ * NPEI_STATE1 = NPEI State 1
+ *
+ * State machines in NPEI. For debug.
+ */
+union cvmx_npei_state1
+{
+	uint64_t u64;
+	struct cvmx_npei_state1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cpl1                         : 12; /**< CPL1 State */
+	uint64_t cpl0                         : 12; /**< CPL0 State */
+	uint64_t arb                          : 1;  /**< ARB State */
+	uint64_t csr                          : 39; /**< CSR State */
+#else
+	uint64_t csr                          : 39;
+	uint64_t arb                          : 1;
+	uint64_t cpl0                         : 12;
+	uint64_t cpl1                         : 12;
+#endif
+	} s;
+	struct cvmx_npei_state1_s             cn52xx;
+	struct cvmx_npei_state1_s             cn52xxp1;
+	struct cvmx_npei_state1_s             cn56xx;
+	struct cvmx_npei_state1_s             cn56xxp1;
+};
+typedef union cvmx_npei_state1 cvmx_npei_state1_t;
+
+/**
+ * cvmx_npei_state2
+ *
+ * NPEI_STATE2 = NPEI State 2
+ *
+ * State machines in NPEI. For debug.
+ */
+union cvmx_npei_state2
+{
+	uint64_t u64;
+	struct cvmx_npei_state2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t npei                         : 1;  /**< NPEI State */
+	uint64_t rac                          : 1;  /**< RAC State */
+	uint64_t csm1                         : 15; /**< CSM1 State */
+	uint64_t csm0                         : 15; /**< CSM0 State */
+	uint64_t nnp0                         : 8;  /**< NNP0 State */
+	uint64_t nnd                          : 8;  /**< NND State */
+#else
+	uint64_t nnd                          : 8;
+	uint64_t nnp0                         : 8;
+	uint64_t csm0                         : 15;
+	uint64_t csm1                         : 15;
+	uint64_t rac                          : 1;
+	uint64_t npei                         : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_npei_state2_s             cn52xx;
+	struct cvmx_npei_state2_s             cn52xxp1;
+	struct cvmx_npei_state2_s             cn56xx;
+	struct cvmx_npei_state2_s             cn56xxp1;
+};
+typedef union cvmx_npei_state2 cvmx_npei_state2_t;
+
+/**
+ * cvmx_npei_state3
+ *
+ * NPEI_STATE3 = NPEI State 3
+ *
+ * State machines in NPEI. For debug.
+ */
+union cvmx_npei_state3
+{
+	uint64_t u64;
+	struct cvmx_npei_state3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t psm1                         : 15; /**< PSM1 State */
+	uint64_t psm0                         : 15; /**< PSM0 State */
+	uint64_t nsm1                         : 13; /**< NSM1 State */
+	uint64_t nsm0                         : 13; /**< NSM0 State */
+#else
+	uint64_t nsm0                         : 13;
+	uint64_t nsm1                         : 13;
+	uint64_t psm0                         : 15;
+	uint64_t psm1                         : 15;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_npei_state3_s             cn52xx;
+	struct cvmx_npei_state3_s             cn52xxp1;
+	struct cvmx_npei_state3_s             cn56xx;
+	struct cvmx_npei_state3_s             cn56xxp1;
+};
+typedef union cvmx_npei_state3 cvmx_npei_state3_t;
+
+/**
+ * cvmx_npei_win_rd_addr
+ *
+ * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register
+ *
+ * The address to be read when the NPEI_WIN_RD_DATA register is read.
+ */
+union cvmx_npei_win_rd_addr
+{
+	uint64_t u64;
+	struct cvmx_npei_win_rd_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_51_63               : 13;
+	uint64_t ld_cmd                       : 2;  /**< The load command sent wit hthe read.
+                                                         0x0 == Load 8-bytes, 0x1 == Load 4-bytes,
+                                                         0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t rd_addr                      : 48; /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:0]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:0]  == RSL Register Offset */
+#else
+	uint64_t rd_addr                      : 48;
+	uint64_t iobit                        : 1;
+	uint64_t ld_cmd                       : 2;
+	uint64_t reserved_51_63               : 13;
+#endif
+	} s;
+	struct cvmx_npei_win_rd_addr_s        cn52xx;
+	struct cvmx_npei_win_rd_addr_s        cn52xxp1;
+	struct cvmx_npei_win_rd_addr_s        cn56xx;
+	struct cvmx_npei_win_rd_addr_s        cn56xxp1;
+};
+typedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t;
+
+/**
+ * cvmx_npei_win_rd_data
+ *
+ * NPEI_WIN_RD_DATA = NPEI Window Read Data Register
+ *
+ * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR
+ * register.
+ */
+union cvmx_npei_win_rd_data
+{
+	uint64_t u64;
+	struct cvmx_npei_win_rd_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rd_data                      : 64; /**< The read data. */
+#else
+	uint64_t rd_data                      : 64;
+#endif
+	} s;
+	struct cvmx_npei_win_rd_data_s        cn52xx;
+	struct cvmx_npei_win_rd_data_s        cn52xxp1;
+	struct cvmx_npei_win_rd_data_s        cn56xx;
+	struct cvmx_npei_win_rd_data_s        cn56xxp1;
+};
+typedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t;
+
+/**
+ * cvmx_npei_win_wr_addr
+ *
+ * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register
+ *
+ * Contains the address to be writen to when a write operation is started by writing the
+ * NPEI_WIN_WR_DATA register (see below).
+ *
+ * Notes:
+ * Even though address bit [2] can be set, it should always be kept to '0'.
+ *
+ */
+union cvmx_npei_win_wr_addr
+{
+	uint64_t u64;
+	struct cvmx_npei_win_wr_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t wr_addr                      : 46; /**< The address that will be written to when the
+                                                         NPEI_WIN_WR_DATA register is written.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:2]  == RSL Register Offset
+                                                              [1:0]   == x, Not Used */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t wr_addr                      : 46;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_npei_win_wr_addr_s        cn52xx;
+	struct cvmx_npei_win_wr_addr_s        cn52xxp1;
+	struct cvmx_npei_win_wr_addr_s        cn56xx;
+	struct cvmx_npei_win_wr_addr_s        cn56xxp1;
+};
+typedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t;
+
+/**
+ * cvmx_npei_win_wr_data
+ *
+ * NPEI_WIN_WR_DATA = NPEI Window Write Data Register
+ *
+ * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register.
+ * Writing the least-significant-byte of this register will cause a write operation to take place.
+ */
+union cvmx_npei_win_wr_data
+{
+	uint64_t u64;
+	struct cvmx_npei_win_wr_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
+                                                         register is written, the Window Write will take
+                                                         place. */
+#else
+	uint64_t wr_data                      : 64;
+#endif
+	} s;
+	struct cvmx_npei_win_wr_data_s        cn52xx;
+	struct cvmx_npei_win_wr_data_s        cn52xxp1;
+	struct cvmx_npei_win_wr_data_s        cn56xx;
+	struct cvmx_npei_win_wr_data_s        cn56xxp1;
+};
+typedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t;
+
+/**
+ * cvmx_npei_win_wr_mask
+ *
+ * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register
+ *
+ * Contains the mask for the data in the NPEI_WIN_WR_DATA Register.
+ */
+union cvmx_npei_win_wr_mask
+{
+	uint64_t u64;
+	struct cvmx_npei_win_wr_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is '0'
+                                                         the corresponding byte will be written. */
+#else
+	uint64_t wr_mask                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_npei_win_wr_mask_s        cn52xx;
+	struct cvmx_npei_win_wr_mask_s        cn52xxp1;
+	struct cvmx_npei_win_wr_mask_s        cn56xx;
+	struct cvmx_npei_win_wr_mask_s        cn56xxp1;
+};
+typedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t;
+
+/**
+ * cvmx_npei_window_ctl
+ *
+ * NPEI_WINDOW_CTL = NPEI's Window Control
+ *
+ * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1.
+ * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next
+ * RML access will start, and interrupt will be set, and in the case of reads no data will be returned.
+ *
+ * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
+ * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.
+ */
+union cvmx_npei_window_ctl
+{
+	uint64_t u64;
+	struct cvmx_npei_window_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t time                         : 32; /**< Time to wait in core clocks to wait for a
+                                                         BAR0 access to completeon the NCB
+                                                         before timing out. A value of 0 will cause no
+                                                         timeouts. A minimum value of 0x200000 should be
+                                                         used when this register is not set to 0x0. */
+#else
+	uint64_t time                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npei_window_ctl_s         cn52xx;
+	struct cvmx_npei_window_ctl_s         cn52xxp1;
+	struct cvmx_npei_window_ctl_s         cn56xx;
+	struct cvmx_npei_window_ctl_s         cn56xxp1;
+};
+typedef union cvmx_npei_window_ctl cvmx_npei_window_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-npi-defs.h b/sys/contrib/octeon-sdk/cvmx-npi-defs.h
new file mode 100644
index 0000000..f8e18e9
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-npi-defs.h
@@ -0,0 +1,4746 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-npi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon npi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_NPI_TYPEDEFS_H__
+#define __CVMX_NPI_TYPEDEFS_H__
+
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#endif
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
+}
+#else
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#endif
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
+static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
+}
+#else
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
+}
+#else
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
+}
+#else
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
+}
+#else
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
+}
+#else
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
+}
+#else
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
+}
+#else
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
+}
+#else
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
+}
+#else
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
+}
+#else
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
+}
+#else
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
+}
+#else
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
+}
+#else
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
+}
+#else
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
+}
+#else
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#endif
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6))))))
+		cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3;
+}
+#else
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
+	return 0x0000000000000190ull;
+}
+#else
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
+}
+#else
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#endif
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
+}
+#else
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#endif
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4;
+}
+#else
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
+}
+#else
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
+}
+#else
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
+}
+#else
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
+}
+#else
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
+}
+#else
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
+}
+#else
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
+}
+#else
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
+}
+#else
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
+}
+#else
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
+}
+#else
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
+}
+#else
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
+}
+#else
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
+}
+#else
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
+}
+#else
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
+}
+#else
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
+}
+#else
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
+}
+#else
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
+}
+#else
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
+}
+#else
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
+}
+#else
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
+}
+#else
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
+}
+#else
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
+}
+#else
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
+}
+#else
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
+}
+#else
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
+}
+#else
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
+}
+#else
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#endif
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
+static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
+}
+#else
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
+#endif
+
+/**
+ * cvmx_npi_base_addr_input#
+ *
+ * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register
+ *
+ * The address to start reading Instructions from for Input-0.
+ */
+union cvmx_npi_base_addr_inputx
+{
+	uint64_t u64;
+	struct cvmx_npi_base_addr_inputx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t baddr                        : 61; /**< The address to read Instruction from for output 0.
+                                                         This address is 8-byte aligned, for this reason
+                                                         address bits [2:0] will always be zero. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t baddr                        : 61;
+#endif
+	} s;
+	struct cvmx_npi_base_addr_inputx_s    cn30xx;
+	struct cvmx_npi_base_addr_inputx_s    cn31xx;
+	struct cvmx_npi_base_addr_inputx_s    cn38xx;
+	struct cvmx_npi_base_addr_inputx_s    cn38xxp2;
+	struct cvmx_npi_base_addr_inputx_s    cn50xx;
+	struct cvmx_npi_base_addr_inputx_s    cn58xx;
+	struct cvmx_npi_base_addr_inputx_s    cn58xxp1;
+};
+typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t;
+
+/**
+ * cvmx_npi_base_addr_output#
+ *
+ * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register
+ *
+ * The address to start reading Instructions from for Output-0.
+ */
+union cvmx_npi_base_addr_outputx
+{
+	uint64_t u64;
+	struct cvmx_npi_base_addr_outputx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t baddr                        : 61; /**< The address to read Instruction from for output 0.
+                                                         This address is 8-byte aligned, for this reason
+                                                         address bits [2:0] will always be zero. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t baddr                        : 61;
+#endif
+	} s;
+	struct cvmx_npi_base_addr_outputx_s   cn30xx;
+	struct cvmx_npi_base_addr_outputx_s   cn31xx;
+	struct cvmx_npi_base_addr_outputx_s   cn38xx;
+	struct cvmx_npi_base_addr_outputx_s   cn38xxp2;
+	struct cvmx_npi_base_addr_outputx_s   cn50xx;
+	struct cvmx_npi_base_addr_outputx_s   cn58xx;
+	struct cvmx_npi_base_addr_outputx_s   cn58xxp1;
+};
+typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t;
+
+/**
+ * cvmx_npi_bist_status
+ *
+ * NPI_BIST_STATUS = NPI's BIST Status Register
+ *
+ * Results from BIST runs of NPI's memories.
+ */
+union cvmx_npi_bist_status
+{
+	uint64_t u64;
+	struct cvmx_npi_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
+	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
+	uint64_t rdp_bs                       : 1;  /**< BIST Status for the rdp_fifo */
+	uint64_t pcnc_bs                      : 1;  /**< BIST Status for the pcn_cnt_fifo */
+	uint64_t pcn_bs                       : 1;  /**< BIST Status for the pcn_fifo */
+	uint64_t rdn_bs                       : 1;  /**< BIST Status for the rdn_fifo */
+	uint64_t pcac_bs                      : 1;  /**< BIST Status for the pca_cmd_fifo */
+	uint64_t pcad_bs                      : 1;  /**< BIST Status for the pca_data_fifo */
+	uint64_t rdnl_bs                      : 1;  /**< BIST Status for the rdn_length_fifo */
+	uint64_t pgf_bs                       : 1;  /**< BIST Status for the pgf_fifo */
+	uint64_t pig_bs                       : 1;  /**< BIST Status for the pig_fifo */
+	uint64_t pof0_bs                      : 1;  /**< BIST Status for the pof0_fifo */
+	uint64_t pof1_bs                      : 1;  /**< BIST Status for the pof1_fifo */
+	uint64_t pof2_bs                      : 1;  /**< BIST Status for the pof2_fifo */
+	uint64_t pof3_bs                      : 1;  /**< BIST Status for the pof3_fifo */
+	uint64_t pos_bs                       : 1;  /**< BIST Status for the pos_fifo */
+	uint64_t nus_bs                       : 1;  /**< BIST Status for the nus_fifo */
+	uint64_t dob_bs                       : 1;  /**< BIST Status for the dob_fifo */
+	uint64_t pdf_bs                       : 1;  /**< BIST Status for the pdf_fifo */
+	uint64_t dpi_bs                       : 1;  /**< BIST Status for the dpi_fifo */
+#else
+	uint64_t dpi_bs                       : 1;
+	uint64_t pdf_bs                       : 1;
+	uint64_t dob_bs                       : 1;
+	uint64_t nus_bs                       : 1;
+	uint64_t pos_bs                       : 1;
+	uint64_t pof3_bs                      : 1;
+	uint64_t pof2_bs                      : 1;
+	uint64_t pof1_bs                      : 1;
+	uint64_t pof0_bs                      : 1;
+	uint64_t pig_bs                       : 1;
+	uint64_t pgf_bs                       : 1;
+	uint64_t rdnl_bs                      : 1;
+	uint64_t pcad_bs                      : 1;
+	uint64_t pcac_bs                      : 1;
+	uint64_t rdn_bs                       : 1;
+	uint64_t pcn_bs                       : 1;
+	uint64_t pcnc_bs                      : 1;
+	uint64_t rdp_bs                       : 1;
+	uint64_t dif_bs                       : 1;
+	uint64_t csr_bs                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_npi_bist_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
+	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
+	uint64_t rdp_bs                       : 1;  /**< BIST Status for the rdp_fifo */
+	uint64_t pcnc_bs                      : 1;  /**< BIST Status for the pcn_cnt_fifo */
+	uint64_t pcn_bs                       : 1;  /**< BIST Status for the pcn_fifo */
+	uint64_t rdn_bs                       : 1;  /**< BIST Status for the rdn_fifo */
+	uint64_t pcac_bs                      : 1;  /**< BIST Status for the pca_cmd_fifo */
+	uint64_t pcad_bs                      : 1;  /**< BIST Status for the pca_data_fifo */
+	uint64_t rdnl_bs                      : 1;  /**< BIST Status for the rdn_length_fifo */
+	uint64_t pgf_bs                       : 1;  /**< BIST Status for the pgf_fifo */
+	uint64_t pig_bs                       : 1;  /**< BIST Status for the pig_fifo */
+	uint64_t pof0_bs                      : 1;  /**< BIST Status for the pof0_fifo */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pos_bs                       : 1;  /**< BIST Status for the pos_fifo */
+	uint64_t nus_bs                       : 1;  /**< BIST Status for the nus_fifo */
+	uint64_t dob_bs                       : 1;  /**< BIST Status for the dob_fifo */
+	uint64_t pdf_bs                       : 1;  /**< BIST Status for the pdf_fifo */
+	uint64_t dpi_bs                       : 1;  /**< BIST Status for the dpi_fifo */
+#else
+	uint64_t dpi_bs                       : 1;
+	uint64_t pdf_bs                       : 1;
+	uint64_t dob_bs                       : 1;
+	uint64_t nus_bs                       : 1;
+	uint64_t pos_bs                       : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pof0_bs                      : 1;
+	uint64_t pig_bs                       : 1;
+	uint64_t pgf_bs                       : 1;
+	uint64_t rdnl_bs                      : 1;
+	uint64_t pcad_bs                      : 1;
+	uint64_t pcac_bs                      : 1;
+	uint64_t rdn_bs                       : 1;
+	uint64_t pcn_bs                       : 1;
+	uint64_t pcnc_bs                      : 1;
+	uint64_t rdp_bs                       : 1;
+	uint64_t dif_bs                       : 1;
+	uint64_t csr_bs                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn30xx;
+	struct cvmx_npi_bist_status_s         cn31xx;
+	struct cvmx_npi_bist_status_s         cn38xx;
+	struct cvmx_npi_bist_status_s         cn38xxp2;
+	struct cvmx_npi_bist_status_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t csr_bs                       : 1;  /**< BIST Status for the csr_fifo */
+	uint64_t dif_bs                       : 1;  /**< BIST Status for the dif_fifo */
+	uint64_t rdp_bs                       : 1;  /**< BIST Status for the rdp_fifo */
+	uint64_t pcnc_bs                      : 1;  /**< BIST Status for the pcn_cnt_fifo */
+	uint64_t pcn_bs                       : 1;  /**< BIST Status for the pcn_fifo */
+	uint64_t rdn_bs                       : 1;  /**< BIST Status for the rdn_fifo */
+	uint64_t pcac_bs                      : 1;  /**< BIST Status for the pca_cmd_fifo */
+	uint64_t pcad_bs                      : 1;  /**< BIST Status for the pca_data_fifo */
+	uint64_t rdnl_bs                      : 1;  /**< BIST Status for the rdn_length_fifo */
+	uint64_t pgf_bs                       : 1;  /**< BIST Status for the pgf_fifo */
+	uint64_t pig_bs                       : 1;  /**< BIST Status for the pig_fifo */
+	uint64_t pof0_bs                      : 1;  /**< BIST Status for the pof0_fifo */
+	uint64_t pof1_bs                      : 1;  /**< BIST Status for the pof1_fifo */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t pos_bs                       : 1;  /**< BIST Status for the pos_fifo */
+	uint64_t nus_bs                       : 1;  /**< BIST Status for the nus_fifo */
+	uint64_t dob_bs                       : 1;  /**< BIST Status for the dob_fifo */
+	uint64_t pdf_bs                       : 1;  /**< BIST Status for the pdf_fifo */
+	uint64_t dpi_bs                       : 1;  /**< BIST Status for the dpi_fifo */
+#else
+	uint64_t dpi_bs                       : 1;
+	uint64_t pdf_bs                       : 1;
+	uint64_t dob_bs                       : 1;
+	uint64_t nus_bs                       : 1;
+	uint64_t pos_bs                       : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t pof1_bs                      : 1;
+	uint64_t pof0_bs                      : 1;
+	uint64_t pig_bs                       : 1;
+	uint64_t pgf_bs                       : 1;
+	uint64_t rdnl_bs                      : 1;
+	uint64_t pcad_bs                      : 1;
+	uint64_t pcac_bs                      : 1;
+	uint64_t rdn_bs                       : 1;
+	uint64_t pcn_bs                       : 1;
+	uint64_t pcnc_bs                      : 1;
+	uint64_t rdp_bs                       : 1;
+	uint64_t dif_bs                       : 1;
+	uint64_t csr_bs                       : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn50xx;
+	struct cvmx_npi_bist_status_s         cn58xx;
+	struct cvmx_npi_bist_status_s         cn58xxp1;
+};
+typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t;
+
+/**
+ * cvmx_npi_buff_size_output#
+ *
+ * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0
+ *
+ * The size in bytes of the Data Bufffer and Information Buffer for output 0.
+ */
+union cvmx_npi_buff_size_outputx
+{
+	uint64_t u64;
+	struct cvmx_npi_buff_size_outputx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t isize                        : 7;  /**< The number of bytes to move to the Info-Pointer
+                                                         from the front of the packet.
+                                                         Legal values are 0-120. */
+	uint64_t bsize                        : 16; /**< The size in bytes of the area pointed to by
+                                                         buffer pointer for output packet data. */
+#else
+	uint64_t bsize                        : 16;
+	uint64_t isize                        : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_npi_buff_size_outputx_s   cn30xx;
+	struct cvmx_npi_buff_size_outputx_s   cn31xx;
+	struct cvmx_npi_buff_size_outputx_s   cn38xx;
+	struct cvmx_npi_buff_size_outputx_s   cn38xxp2;
+	struct cvmx_npi_buff_size_outputx_s   cn50xx;
+	struct cvmx_npi_buff_size_outputx_s   cn58xx;
+	struct cvmx_npi_buff_size_outputx_s   cn58xxp1;
+};
+typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t;
+
+/**
+ * cvmx_npi_comp_ctl
+ *
+ * NPI_COMP_CTL = PCI Compensation Control
+ *
+ * PCI Compensation Control
+ */
+union cvmx_npi_comp_ctl
+{
+	uint64_t u64;
+	struct cvmx_npi_comp_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t pctl                         : 5;  /**< Bypass value for PCTL */
+	uint64_t nctl                         : 5;  /**< Bypass value for NCTL */
+#else
+	uint64_t nctl                         : 5;
+	uint64_t pctl                         : 5;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_npi_comp_ctl_s            cn50xx;
+	struct cvmx_npi_comp_ctl_s            cn58xx;
+	struct cvmx_npi_comp_ctl_s            cn58xxp1;
+};
+typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t;
+
+/**
+ * cvmx_npi_ctl_status
+ *
+ * NPI_CTL_STATUS = NPI's Control Status Register
+ *
+ * Contains control ans status for NPI.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+union cvmx_npi_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_npi_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_63_63               : 1;
+	uint64_t chip_rev                     : 8;  /**< The revision of the N3. */
+	uint64_t dis_pniw                     : 1;  /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+	uint64_t out3_enb                     : 1;  /**< When asserted '1' the output3 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t out2_enb                     : 1;  /**< When asserted '1' the output2 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t out1_enb                     : 1;  /**< When asserted '1' the output1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t out0_enb                     : 1;  /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins3_enb                     : 1;  /**< When asserted '1' the gather3 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins2_enb                     : 1;  /**< When asserted '1' the gather2 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins1_enb                     : 1;  /**< When asserted '1' the gather1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins0_enb                     : 1;  /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins3_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather3 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t ins2_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather2 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t ins1_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather1 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t ins0_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t pci_wdis                     : 1;  /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+	uint64_t reserved_37_39               : 3;
+	uint64_t max_word                     : 5;  /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+	uint64_t reserved_10_31               : 22;
+	uint64_t timer                        : 10; /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+	uint64_t timer                        : 10;
+	uint64_t reserved_10_31               : 22;
+	uint64_t max_word                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t wait_com                     : 1;
+	uint64_t pci_wdis                     : 1;
+	uint64_t ins0_64b                     : 1;
+	uint64_t ins1_64b                     : 1;
+	uint64_t ins2_64b                     : 1;
+	uint64_t ins3_64b                     : 1;
+	uint64_t ins0_enb                     : 1;
+	uint64_t ins1_enb                     : 1;
+	uint64_t ins2_enb                     : 1;
+	uint64_t ins3_enb                     : 1;
+	uint64_t out0_enb                     : 1;
+	uint64_t out1_enb                     : 1;
+	uint64_t out2_enb                     : 1;
+	uint64_t out3_enb                     : 1;
+	uint64_t dis_pniw                     : 1;
+	uint64_t chip_rev                     : 8;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} s;
+	struct cvmx_npi_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_63_63               : 1;
+	uint64_t chip_rev                     : 8;  /**< The revision of the N3. */
+	uint64_t dis_pniw                     : 1;  /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+	uint64_t reserved_51_53               : 3;
+	uint64_t out0_enb                     : 1;  /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t reserved_47_49               : 3;
+	uint64_t ins0_enb                     : 1;  /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t reserved_43_45               : 3;
+	uint64_t ins0_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t pci_wdis                     : 1;  /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+	uint64_t reserved_37_39               : 3;
+	uint64_t max_word                     : 5;  /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+	uint64_t reserved_10_31               : 22;
+	uint64_t timer                        : 10; /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+	uint64_t timer                        : 10;
+	uint64_t reserved_10_31               : 22;
+	uint64_t max_word                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t wait_com                     : 1;
+	uint64_t pci_wdis                     : 1;
+	uint64_t ins0_64b                     : 1;
+	uint64_t reserved_43_45               : 3;
+	uint64_t ins0_enb                     : 1;
+	uint64_t reserved_47_49               : 3;
+	uint64_t out0_enb                     : 1;
+	uint64_t reserved_51_53               : 3;
+	uint64_t dis_pniw                     : 1;
+	uint64_t chip_rev                     : 8;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} cn30xx;
+	struct cvmx_npi_ctl_status_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_63_63               : 1;
+	uint64_t chip_rev                     : 8;  /**< The revision of the N3.
+                                                         0 => pass1.x, 1 => 2.0 */
+	uint64_t dis_pniw                     : 1;  /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+	uint64_t reserved_52_53               : 2;
+	uint64_t out1_enb                     : 1;  /**< When asserted '1' the output1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t out0_enb                     : 1;  /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t reserved_48_49               : 2;
+	uint64_t ins1_enb                     : 1;  /**< When asserted '1' the gather1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t ins0_enb                     : 1;  /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+	uint64_t reserved_44_45               : 2;
+	uint64_t ins1_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather1 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t ins0_64b                     : 1;  /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+	uint64_t pci_wdis                     : 1;  /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+	uint64_t reserved_37_39               : 3;
+	uint64_t max_word                     : 5;  /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+	uint64_t reserved_10_31               : 22;
+	uint64_t timer                        : 10; /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+	uint64_t timer                        : 10;
+	uint64_t reserved_10_31               : 22;
+	uint64_t max_word                     : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t wait_com                     : 1;
+	uint64_t pci_wdis                     : 1;
+	uint64_t ins0_64b                     : 1;
+	uint64_t ins1_64b                     : 1;
+	uint64_t reserved_44_45               : 2;
+	uint64_t ins0_enb                     : 1;
+	uint64_t ins1_enb                     : 1;
+	uint64_t reserved_48_49               : 2;
+	uint64_t out0_enb                     : 1;
+	uint64_t out1_enb                     : 1;
+	uint64_t reserved_52_53               : 2;
+	uint64_t dis_pniw                     : 1;
+	uint64_t chip_rev                     : 8;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} cn31xx;
+	struct cvmx_npi_ctl_status_s          cn38xx;
+	struct cvmx_npi_ctl_status_s          cn38xxp2;
+	struct cvmx_npi_ctl_status_cn31xx     cn50xx;
+	struct cvmx_npi_ctl_status_s          cn58xx;
+	struct cvmx_npi_ctl_status_s          cn58xxp1;
+};
+typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t;
+
+/**
+ * cvmx_npi_dbg_select
+ *
+ * NPI_DBG_SELECT = Debug Select Register
+ *
+ * Contains the debug select value in last written to the RSLs.
+ */
+union cvmx_npi_dbg_select
+{
+	uint64_t u64;
+	struct cvmx_npi_dbg_select_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dbg_sel                      : 16; /**< When this register is written its value is sent to
+                                                         all RSLs. */
+#else
+	uint64_t dbg_sel                      : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npi_dbg_select_s          cn30xx;
+	struct cvmx_npi_dbg_select_s          cn31xx;
+	struct cvmx_npi_dbg_select_s          cn38xx;
+	struct cvmx_npi_dbg_select_s          cn38xxp2;
+	struct cvmx_npi_dbg_select_s          cn50xx;
+	struct cvmx_npi_dbg_select_s          cn58xx;
+	struct cvmx_npi_dbg_select_s          cn58xxp1;
+};
+typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t;
+
+/**
+ * cvmx_npi_dma_control
+ *
+ * NPI_DMA_CONTROL = DMA Control Register
+ *
+ * Controls operation of the DMA IN/OUT of the NPI.
+ */
+union cvmx_npi_dma_control
+{
+	uint64_t u64;
+	struct cvmx_npi_dma_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t b0_lend                      : 1;  /**< When set '1' and the NPI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. This field is new to PASS-2. */
+	uint64_t dwb_denb                     : 1;  /**< When set '1' the NPI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data in N3. */
+	uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+	uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+	uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+	uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
+	uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
+	uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
+	uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+	uint64_t hp_enb                       : 1;  /**< Enables the High Priority DMA.
+                                                         While this bit is disabled '0' then the value
+                                                         in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the
+                                                         starting address of the High Priority DMA engine.
+                                                         CSIZE field will be reloaded, for the High Priority
+                                                         DMA Engine. */
+	uint64_t lp_enb                       : 1;  /**< Enables the Low Priority DMA.
+                                                         While this bit is disabled '0' then the value
+                                                         in the NPI_LOWP_IBUFF_SADDR is re-loaded to the
+                                                         starting address of the Low Priority DMA engine.
+                                                         PASS-2: When this bit is '0' the value in the
+                                                         CSIZE field will be reloaded, for the Low Priority
+                                                         DMA Engine. */
+	uint64_t csize                        : 14; /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+	uint64_t csize                        : 14;
+	uint64_t lp_enb                       : 1;
+	uint64_t hp_enb                       : 1;
+	uint64_t o_mode                       : 1;
+	uint64_t o_es                         : 2;
+	uint64_t o_ns                         : 1;
+	uint64_t o_ro                         : 1;
+	uint64_t o_add1                       : 1;
+	uint64_t fpa_que                      : 3;
+	uint64_t dwb_ichk                     : 9;
+	uint64_t dwb_denb                     : 1;
+	uint64_t b0_lend                      : 1;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_npi_dma_control_s         cn30xx;
+	struct cvmx_npi_dma_control_s         cn31xx;
+	struct cvmx_npi_dma_control_s         cn38xx;
+	struct cvmx_npi_dma_control_s         cn38xxp2;
+	struct cvmx_npi_dma_control_s         cn50xx;
+	struct cvmx_npi_dma_control_s         cn58xx;
+	struct cvmx_npi_dma_control_s         cn58xxp1;
+};
+typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t;
+
+/**
+ * cvmx_npi_dma_highp_counts
+ *
+ * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts
+ *
+ * Values for determing the number of instructions for High Priority DMA in the NPI.
+ */
+union cvmx_npi_dma_highp_counts
+{
+	uint64_t u64;
+	struct cvmx_npi_dma_highp_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
+	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t fcnt                         : 7;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_npi_dma_highp_counts_s    cn30xx;
+	struct cvmx_npi_dma_highp_counts_s    cn31xx;
+	struct cvmx_npi_dma_highp_counts_s    cn38xx;
+	struct cvmx_npi_dma_highp_counts_s    cn38xxp2;
+	struct cvmx_npi_dma_highp_counts_s    cn50xx;
+	struct cvmx_npi_dma_highp_counts_s    cn58xx;
+	struct cvmx_npi_dma_highp_counts_s    cn58xxp1;
+};
+typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t;
+
+/**
+ * cvmx_npi_dma_highp_naddr
+ *
+ * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address
+ *
+ * Place NPI will read the next Ichunk data from. This is valid when state is 0
+ */
+union cvmx_npi_dma_highp_naddr
+{
+	uint64_t u64;
+	struct cvmx_npi_dma_highp_naddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t state                        : 4;  /**< The DMA instruction engine state vector.
+                                                         Typical value is 0 (IDLE). */
+	uint64_t addr                         : 36; /**< The next L2C address to read DMA instructions
+                                                         from for the High Priority DMA engine. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t state                        : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_npi_dma_highp_naddr_s     cn30xx;
+	struct cvmx_npi_dma_highp_naddr_s     cn31xx;
+	struct cvmx_npi_dma_highp_naddr_s     cn38xx;
+	struct cvmx_npi_dma_highp_naddr_s     cn38xxp2;
+	struct cvmx_npi_dma_highp_naddr_s     cn50xx;
+	struct cvmx_npi_dma_highp_naddr_s     cn58xx;
+	struct cvmx_npi_dma_highp_naddr_s     cn58xxp1;
+};
+typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t;
+
+/**
+ * cvmx_npi_dma_lowp_counts
+ *
+ * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts
+ *
+ * Values for determing the number of instructions for Low Priority DMA in the NPI.
+ */
+union cvmx_npi_dma_lowp_counts
+{
+	uint64_t u64;
+	struct cvmx_npi_dma_lowp_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_39_63               : 25;
+	uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO. */
+	uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t fcnt                         : 7;
+	uint64_t reserved_39_63               : 25;
+#endif
+	} s;
+	struct cvmx_npi_dma_lowp_counts_s     cn30xx;
+	struct cvmx_npi_dma_lowp_counts_s     cn31xx;
+	struct cvmx_npi_dma_lowp_counts_s     cn38xx;
+	struct cvmx_npi_dma_lowp_counts_s     cn38xxp2;
+	struct cvmx_npi_dma_lowp_counts_s     cn50xx;
+	struct cvmx_npi_dma_lowp_counts_s     cn58xx;
+	struct cvmx_npi_dma_lowp_counts_s     cn58xxp1;
+};
+typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t;
+
+/**
+ * cvmx_npi_dma_lowp_naddr
+ *
+ * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address
+ *
+ * Place NPI will read the next Ichunk data from. This is valid when state is 0
+ */
+union cvmx_npi_dma_lowp_naddr
+{
+	uint64_t u64;
+	struct cvmx_npi_dma_lowp_naddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t state                        : 4;  /**< The DMA instruction engine state vector.
+                                                         Typical value is 0 (IDLE). */
+	uint64_t addr                         : 36; /**< The next L2C address to read DMA instructions
+                                                         from for the Low Priority DMA engine. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t state                        : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_npi_dma_lowp_naddr_s      cn30xx;
+	struct cvmx_npi_dma_lowp_naddr_s      cn31xx;
+	struct cvmx_npi_dma_lowp_naddr_s      cn38xx;
+	struct cvmx_npi_dma_lowp_naddr_s      cn38xxp2;
+	struct cvmx_npi_dma_lowp_naddr_s      cn50xx;
+	struct cvmx_npi_dma_lowp_naddr_s      cn58xx;
+	struct cvmx_npi_dma_lowp_naddr_s      cn58xxp1;
+};
+typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t;
+
+/**
+ * cvmx_npi_highp_dbell
+ *
+ * NPI_HIGHP_DBELL = High Priority Door Bell
+ *
+ * The door bell register for the high priority DMA queue.
+ */
+union cvmx_npi_highp_dbell
+{
+	uint64_t u64;
+	struct cvmx_npi_highp_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dbell                        : 16; /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the high priority dma queue. */
+#else
+	uint64_t dbell                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npi_highp_dbell_s         cn30xx;
+	struct cvmx_npi_highp_dbell_s         cn31xx;
+	struct cvmx_npi_highp_dbell_s         cn38xx;
+	struct cvmx_npi_highp_dbell_s         cn38xxp2;
+	struct cvmx_npi_highp_dbell_s         cn50xx;
+	struct cvmx_npi_highp_dbell_s         cn58xx;
+	struct cvmx_npi_highp_dbell_s         cn58xxp1;
+};
+typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t;
+
+/**
+ * cvmx_npi_highp_ibuff_saddr
+ *
+ * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address
+ *
+ * The address to start reading Instructions from for HIGHP.
+ */
+union cvmx_npi_highp_ibuff_saddr
+{
+	uint64_t u64;
+	struct cvmx_npi_highp_ibuff_saddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t saddr                        : 36; /**< The starting address to read the first instruction. */
+#else
+	uint64_t saddr                        : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn30xx;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn31xx;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn38xx;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn38xxp2;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn50xx;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn58xx;
+	struct cvmx_npi_highp_ibuff_saddr_s   cn58xxp1;
+};
+typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t;
+
+/**
+ * cvmx_npi_input_control
+ *
+ * NPI_INPUT_CONTROL = NPI's Input Control Register
+ *
+ * Control for reads for gather list and instructions.
+ */
+union cvmx_npi_input_control
+{
+	uint64_t u64;
+	struct cvmx_npi_input_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS3 Field */
+	uint64_t pbp_dhi                      : 13; /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+	uint64_t d_nsr                        : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+	uint64_t d_esr                        : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+	uint64_t d_ror                        : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+	uint64_t use_csr                      : 1;  /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+	uint64_t nsr                          : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+	uint64_t esr                          : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+	uint64_t ror                          : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+	uint64_t ror                          : 1;
+	uint64_t esr                          : 2;
+	uint64_t nsr                          : 1;
+	uint64_t use_csr                      : 1;
+	uint64_t d_ror                        : 1;
+	uint64_t d_esr                        : 2;
+	uint64_t d_nsr                        : 1;
+	uint64_t pbp_dhi                      : 13;
+	uint64_t pkt_rr                       : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_npi_input_control_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t pbp_dhi                      : 13; /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+	uint64_t d_nsr                        : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+	uint64_t d_esr                        : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+	uint64_t d_ror                        : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+	uint64_t use_csr                      : 1;  /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+	uint64_t nsr                          : 1;  /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+	uint64_t esr                          : 2;  /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+	uint64_t ror                          : 1;  /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+	uint64_t ror                          : 1;
+	uint64_t esr                          : 2;
+	uint64_t nsr                          : 1;
+	uint64_t use_csr                      : 1;
+	uint64_t d_ror                        : 1;
+	uint64_t d_esr                        : 2;
+	uint64_t d_nsr                        : 1;
+	uint64_t pbp_dhi                      : 13;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn30xx;
+	struct cvmx_npi_input_control_cn30xx  cn31xx;
+	struct cvmx_npi_input_control_s       cn38xx;
+	struct cvmx_npi_input_control_cn30xx  cn38xxp2;
+	struct cvmx_npi_input_control_s       cn50xx;
+	struct cvmx_npi_input_control_s       cn58xx;
+	struct cvmx_npi_input_control_s       cn58xxp1;
+};
+typedef union cvmx_npi_input_control cvmx_npi_input_control_t;
+
+/**
+ * cvmx_npi_int_enb
+ *
+ * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register
+ *
+ * Used to enable the various interrupting conditions of NPI
+ */
+union cvmx_npi_int_enb
+{
+	uint64_t u64;
+	struct cvmx_npi_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q1_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t rdx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t rwx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pnc_a_f                      : 1;  /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pnc_s_e                      : 1;  /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+	uint64_t com_a_f                      : 1;  /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+	uint64_t com_s_e                      : 1;  /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q3_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q3_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q2_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q2_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t fcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t fcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t iobdma                       : 1;  /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+	uint64_t p_dperr                      : 1;  /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+	uint64_t win_rto                      : 1;  /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+	uint64_t i3_pperr                     : 1;  /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i2_pperr                     : 1;  /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i1_pperr                     : 1;  /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i0_pperr                     : 1;  /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p3_ptout                     : 1;  /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p2_ptout                     : 1;  /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p1_ptout                     : 1;  /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_ptout                     : 1;  /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p3_pperr                     : 1;  /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p2_pperr                     : 1;  /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p1_pperr                     : 1;  /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_pperr                     : 1;  /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t g3_rtout                     : 1;  /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g2_rtout                     : 1;  /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g1_rtout                     : 1;  /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g0_rtout                     : 1;  /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p3_perr                      : 1;  /**< Enables NPI_INT_SUM[P3_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p2_perr                      : 1;  /**< Enables NPI_INT_SUM[P2_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p1_perr                      : 1;  /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_perr                      : 1;  /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p3_rtout                     : 1;  /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p2_rtout                     : 1;  /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p1_rtout                     : 1;  /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_rtout                     : 1;  /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i3_overf                     : 1;  /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i2_overf                     : 1;  /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i1_overf                     : 1;  /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i0_overf                     : 1;  /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i3_rtout                     : 1;  /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i2_rtout                     : 1;  /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i1_rtout                     : 1;  /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i0_rtout                     : 1;  /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t po3_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po2_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po1_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po0_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+	uint64_t pci_rsl                      : 1;  /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t po2_2sml                     : 1;
+	uint64_t po3_2sml                     : 1;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t i2_rtout                     : 1;
+	uint64_t i3_rtout                     : 1;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t i2_overf                     : 1;
+	uint64_t i3_overf                     : 1;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t p2_rtout                     : 1;
+	uint64_t p3_rtout                     : 1;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t p2_perr                      : 1;
+	uint64_t p3_perr                      : 1;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t g2_rtout                     : 1;
+	uint64_t g3_rtout                     : 1;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t p2_pperr                     : 1;
+	uint64_t p3_pperr                     : 1;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t p2_ptout                     : 1;
+	uint64_t p3_ptout                     : 1;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t i2_pperr                     : 1;
+	uint64_t i3_pperr                     : 1;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_npi_int_enb_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q1_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t rdx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t rwx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pnc_a_f                      : 1;  /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pnc_s_e                      : 1;  /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+	uint64_t com_a_f                      : 1;  /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+	uint64_t com_s_e                      : 1;  /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q3_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q3_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q2_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q2_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t fcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t fcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t iobdma                       : 1;  /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+	uint64_t p_dperr                      : 1;  /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+	uint64_t win_rto                      : 1;  /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+	uint64_t reserved_36_38               : 3;
+	uint64_t i0_pperr                     : 1;  /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_32_34               : 3;
+	uint64_t p0_ptout                     : 1;  /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_28_30               : 3;
+	uint64_t p0_pperr                     : 1;  /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_24_26               : 3;
+	uint64_t g0_rtout                     : 1;  /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_20_22               : 3;
+	uint64_t p0_perr                      : 1;  /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_16_18               : 3;
+	uint64_t p0_rtout                     : 1;  /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_12_14               : 3;
+	uint64_t i0_overf                     : 1;  /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t reserved_8_10                : 3;
+	uint64_t i0_rtout                     : 1;  /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_4_6                 : 3;
+	uint64_t po0_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+	uint64_t pci_rsl                      : 1;  /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t reserved_4_6                 : 3;
+	uint64_t i0_rtout                     : 1;
+	uint64_t reserved_8_10                : 3;
+	uint64_t i0_overf                     : 1;
+	uint64_t reserved_12_14               : 3;
+	uint64_t p0_rtout                     : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t p0_perr                      : 1;
+	uint64_t reserved_20_22               : 3;
+	uint64_t g0_rtout                     : 1;
+	uint64_t reserved_24_26               : 3;
+	uint64_t p0_pperr                     : 1;
+	uint64_t reserved_28_30               : 3;
+	uint64_t p0_ptout                     : 1;
+	uint64_t reserved_32_34               : 3;
+	uint64_t i0_pperr                     : 1;
+	uint64_t reserved_36_38               : 3;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn30xx;
+	struct cvmx_npi_int_enb_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q1_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pdf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_f                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+	uint64_t pcf_p_e                      : 1;  /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+	uint64_t rdx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t rwx_s_e                      : 1;  /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pnc_a_f                      : 1;  /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pnc_s_e                      : 1;  /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+	uint64_t com_a_f                      : 1;  /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+	uint64_t com_s_e                      : 1;  /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q3_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q3_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+	uint64_t q2_a_f                       : 1;  /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+	uint64_t q2_s_e                       : 1;  /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+	uint64_t pcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t pcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t fcr_a_f                      : 1;  /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+	uint64_t fcr_s_e                      : 1;  /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+	uint64_t iobdma                       : 1;  /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+	uint64_t p_dperr                      : 1;  /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+	uint64_t win_rto                      : 1;  /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+	uint64_t reserved_37_38               : 2;
+	uint64_t i1_pperr                     : 1;  /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i0_pperr                     : 1;  /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_33_34               : 2;
+	uint64_t p1_ptout                     : 1;  /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_ptout                     : 1;  /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_29_30               : 2;
+	uint64_t p1_pperr                     : 1;  /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_pperr                     : 1;  /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_25_26               : 2;
+	uint64_t g1_rtout                     : 1;  /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g0_rtout                     : 1;  /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_21_22               : 2;
+	uint64_t p1_perr                      : 1;  /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_perr                      : 1;  /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+	uint64_t reserved_17_18               : 2;
+	uint64_t p1_rtout                     : 1;  /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_rtout                     : 1;  /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_13_14               : 2;
+	uint64_t i1_overf                     : 1;  /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i0_overf                     : 1;  /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t reserved_9_10                : 2;
+	uint64_t i1_rtout                     : 1;  /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i0_rtout                     : 1;  /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t po1_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po0_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+	uint64_t pci_rsl                      : 1;  /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t reserved_9_10                : 2;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t reserved_13_14               : 2;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t reserved_17_18               : 2;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t reserved_21_22               : 2;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t reserved_25_26               : 2;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t reserved_29_30               : 2;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t reserved_33_34               : 2;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t reserved_37_38               : 2;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn31xx;
+	struct cvmx_npi_int_enb_s             cn38xx;
+	struct cvmx_npi_int_enb_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t iobdma                       : 1;  /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+	uint64_t p_dperr                      : 1;  /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+	uint64_t win_rto                      : 1;  /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+	uint64_t i3_pperr                     : 1;  /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i2_pperr                     : 1;  /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i1_pperr                     : 1;  /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t i0_pperr                     : 1;  /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p3_ptout                     : 1;  /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p2_ptout                     : 1;  /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p1_ptout                     : 1;  /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_ptout                     : 1;  /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p3_pperr                     : 1;  /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p2_pperr                     : 1;  /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p1_pperr                     : 1;  /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_pperr                     : 1;  /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+	uint64_t g3_rtout                     : 1;  /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g2_rtout                     : 1;  /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g1_rtout                     : 1;  /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t g0_rtout                     : 1;  /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p3_perr                      : 1;  /**< Enables NPI_INT_SUM[P3_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p2_perr                      : 1;  /**< Enables NPI_INT_SUM[P2_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p1_perr                      : 1;  /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p0_perr                      : 1;  /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+	uint64_t p3_rtout                     : 1;  /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p2_rtout                     : 1;  /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p1_rtout                     : 1;  /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t p0_rtout                     : 1;  /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i3_overf                     : 1;  /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i2_overf                     : 1;  /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i1_overf                     : 1;  /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i0_overf                     : 1;  /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+	uint64_t i3_rtout                     : 1;  /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i2_rtout                     : 1;  /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i1_rtout                     : 1;  /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t i0_rtout                     : 1;  /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+	uint64_t po3_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po2_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po1_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+	uint64_t po0_2sml                     : 1;  /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+	uint64_t pci_rsl                      : 1;  /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+	uint64_t rml_wto                      : 1;  /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+	uint64_t rml_rto                      : 1;  /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t po2_2sml                     : 1;
+	uint64_t po3_2sml                     : 1;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t i2_rtout                     : 1;
+	uint64_t i3_rtout                     : 1;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t i2_overf                     : 1;
+	uint64_t i3_overf                     : 1;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t p2_rtout                     : 1;
+	uint64_t p3_rtout                     : 1;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t p2_perr                      : 1;
+	uint64_t p3_perr                      : 1;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t g2_rtout                     : 1;
+	uint64_t g3_rtout                     : 1;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t p2_pperr                     : 1;
+	uint64_t p3_pperr                     : 1;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t p2_ptout                     : 1;
+	uint64_t p3_ptout                     : 1;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t i2_pperr                     : 1;
+	uint64_t i3_pperr                     : 1;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} cn38xxp2;
+	struct cvmx_npi_int_enb_cn31xx        cn50xx;
+	struct cvmx_npi_int_enb_s             cn58xx;
+	struct cvmx_npi_int_enb_s             cn58xxp1;
+};
+typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t;
+
+/**
+ * cvmx_npi_int_sum
+ *
+ * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register
+ *
+ * Set when an interrupt condition occurs, write '1' to clear.
+ */
+union cvmx_npi_int_sum
+{
+	uint64_t u64;
+	struct cvmx_npi_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full.
+                                                         PASS3 Field. */
+	uint64_t q1_s_e                       : 1;  /**< Attempted to subtract when Queue-1 FIFO is empty.
+                                                         PASS3 Field. */
+	uint64_t pdf_p_f                      : 1;  /**< Attempted to push a full PCN-DATA-FIFO.
+                                                         PASS3 Field. */
+	uint64_t pdf_p_e                      : 1;  /**< Attempted to pop an empty PCN-DATA-FIFO.
+                                                         PASS3 Field. */
+	uint64_t pcf_p_f                      : 1;  /**< Attempted to push a full PCN-CNT-FIFO.
+                                                         PASS3 Field. */
+	uint64_t pcf_p_e                      : 1;  /**< Attempted to pop an empty PCN-CNT-FIFO.
+                                                         PASS3 Field. */
+	uint64_t rdx_s_e                      : 1;  /**< Attempted to subtract when DPI-XFR-Wait count is 0.
+                                                         PASS3 Field. */
+	uint64_t rwx_s_e                      : 1;  /**< Attempted to subtract when RDN-XFR-Wait count is 0.
+                                                         PASS3 Field. */
+	uint64_t pnc_a_f                      : 1;  /**< Attempted to add when PNI-NPI Credits are max.
+                                                         PASS3 Field. */
+	uint64_t pnc_s_e                      : 1;  /**< Attempted to subtract when PNI-NPI Credits are 0.
+                                                         PASS3 Field. */
+	uint64_t com_a_f                      : 1;  /**< Attempted to add when PCN-Commit Counter is max.
+                                                         PASS3 Field. */
+	uint64_t com_s_e                      : 1;  /**< Attempted to subtract when PCN-Commit Counter is 0.
+                                                         PASS3 Field. */
+	uint64_t q3_a_f                       : 1;  /**< Attempted to add when Queue-3 FIFO is full.
+                                                         PASS3 Field. */
+	uint64_t q3_s_e                       : 1;  /**< Attempted to subtract when Queue-3 FIFO is empty.
+                                                         PASS3 Field. */
+	uint64_t q2_a_f                       : 1;  /**< Attempted to add when Queue-2 FIFO is full.
+                                                         PASS3 Field. */
+	uint64_t q2_s_e                       : 1;  /**< Attempted to subtract when Queue-2 FIFO is empty.
+                                                         PASS3 Field. */
+	uint64_t pcr_a_f                      : 1;  /**< Attempted to add when POW Credits is full.
+                                                         PASS3 Field. */
+	uint64_t pcr_s_e                      : 1;  /**< Attempted to subtract when POW Credits is empty.
+                                                         PASS3 Field. */
+	uint64_t fcr_a_f                      : 1;  /**< Attempted to add when FPA Credits is full.
+                                                         PASS3 Field. */
+	uint64_t fcr_s_e                      : 1;  /**< Attempted to subtract when FPA Credits is empty.
+                                                         PASS3 Field. */
+	uint64_t iobdma                       : 1;  /**< Requested IOBDMA read size exceeded 128 words. */
+	uint64_t p_dperr                      : 1;  /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+	uint64_t win_rto                      : 1;  /**< Windowed Load Timed Out. */
+	uint64_t i3_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i2_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i1_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i0_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t p3_ptout                     : 1;  /**< Port-3 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p2_ptout                     : 1;  /**< Port-2 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p1_ptout                     : 1;  /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p0_ptout                     : 1;  /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p3_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p2_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p1_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p0_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t g3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t p3_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p2_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p1_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p0_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t i3_overf                     : 1;  /**< Port-3 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i2_overf                     : 1;  /**< Port-2 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i1_overf                     : 1;  /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i0_overf                     : 1;  /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t po3_2sml                     : 1;  /**< The packet being sent out on Port3 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
+	uint64_t po2_2sml                     : 1;  /**< The packet being sent out on Port2 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
+	uint64_t po1_2sml                     : 1;  /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+	uint64_t po0_2sml                     : 1;  /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+	uint64_t pci_rsl                      : 1;  /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+	uint64_t rml_wto                      : 1;  /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+	uint64_t rml_rto                      : 1;  /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t po2_2sml                     : 1;
+	uint64_t po3_2sml                     : 1;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t i2_rtout                     : 1;
+	uint64_t i3_rtout                     : 1;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t i2_overf                     : 1;
+	uint64_t i3_overf                     : 1;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t p2_rtout                     : 1;
+	uint64_t p3_rtout                     : 1;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t p2_perr                      : 1;
+	uint64_t p3_perr                      : 1;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t g2_rtout                     : 1;
+	uint64_t g3_rtout                     : 1;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t p2_pperr                     : 1;
+	uint64_t p3_pperr                     : 1;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t p2_ptout                     : 1;
+	uint64_t p3_ptout                     : 1;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t i2_pperr                     : 1;
+	uint64_t i3_pperr                     : 1;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_npi_int_sum_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full. */
+	uint64_t q1_s_e                       : 1;  /**< Attempted to subtract when Queue-1 FIFO is empty. */
+	uint64_t pdf_p_f                      : 1;  /**< Attempted to push a full PCN-DATA-FIFO. */
+	uint64_t pdf_p_e                      : 1;  /**< Attempted to pop an empty PCN-DATA-FIFO. */
+	uint64_t pcf_p_f                      : 1;  /**< Attempted to push a full PCN-CNT-FIFO. */
+	uint64_t pcf_p_e                      : 1;  /**< Attempted to pop an empty PCN-CNT-FIFO. */
+	uint64_t rdx_s_e                      : 1;  /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
+	uint64_t rwx_s_e                      : 1;  /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
+	uint64_t pnc_a_f                      : 1;  /**< Attempted to add when PNI-NPI Credits are max. */
+	uint64_t pnc_s_e                      : 1;  /**< Attempted to subtract when PNI-NPI Credits are 0. */
+	uint64_t com_a_f                      : 1;  /**< Attempted to add when PCN-Commit Counter is max. */
+	uint64_t com_s_e                      : 1;  /**< Attempted to subtract when PCN-Commit Counter is 0. */
+	uint64_t q3_a_f                       : 1;  /**< Attempted to add when Queue-3 FIFO is full. */
+	uint64_t q3_s_e                       : 1;  /**< Attempted to subtract when Queue-3 FIFO is empty. */
+	uint64_t q2_a_f                       : 1;  /**< Attempted to add when Queue-2 FIFO is full. */
+	uint64_t q2_s_e                       : 1;  /**< Attempted to subtract when Queue-2 FIFO is empty. */
+	uint64_t pcr_a_f                      : 1;  /**< Attempted to add when POW Credits is full. */
+	uint64_t pcr_s_e                      : 1;  /**< Attempted to subtract when POW Credits is empty. */
+	uint64_t fcr_a_f                      : 1;  /**< Attempted to add when FPA Credits is full. */
+	uint64_t fcr_s_e                      : 1;  /**< Attempted to subtract when FPA Credits is empty. */
+	uint64_t iobdma                       : 1;  /**< Requested IOBDMA read size exceeded 128 words. */
+	uint64_t p_dperr                      : 1;  /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+	uint64_t win_rto                      : 1;  /**< Windowed Load Timed Out. */
+	uint64_t reserved_36_38               : 3;
+	uint64_t i0_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t reserved_32_34               : 3;
+	uint64_t p0_ptout                     : 1;  /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t reserved_28_30               : 3;
+	uint64_t p0_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t reserved_24_26               : 3;
+	uint64_t g0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t reserved_20_22               : 3;
+	uint64_t p0_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t reserved_16_18               : 3;
+	uint64_t p0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t reserved_12_14               : 3;
+	uint64_t i0_overf                     : 1;  /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t reserved_8_10                : 3;
+	uint64_t i0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t reserved_4_6                 : 3;
+	uint64_t po0_2sml                     : 1;  /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+	uint64_t pci_rsl                      : 1;  /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+	uint64_t rml_wto                      : 1;  /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+	uint64_t rml_rto                      : 1;  /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t reserved_4_6                 : 3;
+	uint64_t i0_rtout                     : 1;
+	uint64_t reserved_8_10                : 3;
+	uint64_t i0_overf                     : 1;
+	uint64_t reserved_12_14               : 3;
+	uint64_t p0_rtout                     : 1;
+	uint64_t reserved_16_18               : 3;
+	uint64_t p0_perr                      : 1;
+	uint64_t reserved_20_22               : 3;
+	uint64_t g0_rtout                     : 1;
+	uint64_t reserved_24_26               : 3;
+	uint64_t p0_pperr                     : 1;
+	uint64_t reserved_28_30               : 3;
+	uint64_t p0_ptout                     : 1;
+	uint64_t reserved_32_34               : 3;
+	uint64_t i0_pperr                     : 1;
+	uint64_t reserved_36_38               : 3;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn30xx;
+	struct cvmx_npi_int_sum_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t q1_a_f                       : 1;  /**< Attempted to add when Queue-1 FIFO is full. */
+	uint64_t q1_s_e                       : 1;  /**< Attempted to subtract when Queue-1 FIFO is empty. */
+	uint64_t pdf_p_f                      : 1;  /**< Attempted to push a full PCN-DATA-FIFO. */
+	uint64_t pdf_p_e                      : 1;  /**< Attempted to pop an empty PCN-DATA-FIFO. */
+	uint64_t pcf_p_f                      : 1;  /**< Attempted to push a full PCN-CNT-FIFO. */
+	uint64_t pcf_p_e                      : 1;  /**< Attempted to pop an empty PCN-CNT-FIFO. */
+	uint64_t rdx_s_e                      : 1;  /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
+	uint64_t rwx_s_e                      : 1;  /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
+	uint64_t pnc_a_f                      : 1;  /**< Attempted to add when PNI-NPI Credits are max. */
+	uint64_t pnc_s_e                      : 1;  /**< Attempted to subtract when PNI-NPI Credits are 0. */
+	uint64_t com_a_f                      : 1;  /**< Attempted to add when PCN-Commit Counter is max. */
+	uint64_t com_s_e                      : 1;  /**< Attempted to subtract when PCN-Commit Counter is 0. */
+	uint64_t q3_a_f                       : 1;  /**< Attempted to add when Queue-3 FIFO is full. */
+	uint64_t q3_s_e                       : 1;  /**< Attempted to subtract when Queue-3 FIFO is empty. */
+	uint64_t q2_a_f                       : 1;  /**< Attempted to add when Queue-2 FIFO is full. */
+	uint64_t q2_s_e                       : 1;  /**< Attempted to subtract when Queue-2 FIFO is empty. */
+	uint64_t pcr_a_f                      : 1;  /**< Attempted to add when POW Credits is full. */
+	uint64_t pcr_s_e                      : 1;  /**< Attempted to subtract when POW Credits is empty. */
+	uint64_t fcr_a_f                      : 1;  /**< Attempted to add when FPA Credits is full. */
+	uint64_t fcr_s_e                      : 1;  /**< Attempted to subtract when FPA Credits is empty. */
+	uint64_t iobdma                       : 1;  /**< Requested IOBDMA read size exceeded 128 words. */
+	uint64_t p_dperr                      : 1;  /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+	uint64_t win_rto                      : 1;  /**< Windowed Load Timed Out. */
+	uint64_t reserved_37_38               : 2;
+	uint64_t i1_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i0_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t reserved_33_34               : 2;
+	uint64_t p1_ptout                     : 1;  /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p0_ptout                     : 1;  /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t reserved_29_30               : 2;
+	uint64_t p1_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p0_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t reserved_25_26               : 2;
+	uint64_t g1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t reserved_21_22               : 2;
+	uint64_t p1_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p0_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t reserved_17_18               : 2;
+	uint64_t p1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t reserved_13_14               : 2;
+	uint64_t i1_overf                     : 1;  /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i0_overf                     : 1;  /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t reserved_9_10                : 2;
+	uint64_t i1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t reserved_5_6                 : 2;
+	uint64_t po1_2sml                     : 1;  /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+	uint64_t po0_2sml                     : 1;  /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+	uint64_t pci_rsl                      : 1;  /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+	uint64_t rml_wto                      : 1;  /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+	uint64_t rml_rto                      : 1;  /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t reserved_5_6                 : 2;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t reserved_9_10                : 2;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t reserved_13_14               : 2;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t reserved_17_18               : 2;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t reserved_21_22               : 2;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t reserved_25_26               : 2;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t reserved_29_30               : 2;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t reserved_33_34               : 2;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t reserved_37_38               : 2;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t fcr_s_e                      : 1;
+	uint64_t fcr_a_f                      : 1;
+	uint64_t pcr_s_e                      : 1;
+	uint64_t pcr_a_f                      : 1;
+	uint64_t q2_s_e                       : 1;
+	uint64_t q2_a_f                       : 1;
+	uint64_t q3_s_e                       : 1;
+	uint64_t q3_a_f                       : 1;
+	uint64_t com_s_e                      : 1;
+	uint64_t com_a_f                      : 1;
+	uint64_t pnc_s_e                      : 1;
+	uint64_t pnc_a_f                      : 1;
+	uint64_t rwx_s_e                      : 1;
+	uint64_t rdx_s_e                      : 1;
+	uint64_t pcf_p_e                      : 1;
+	uint64_t pcf_p_f                      : 1;
+	uint64_t pdf_p_e                      : 1;
+	uint64_t pdf_p_f                      : 1;
+	uint64_t q1_s_e                       : 1;
+	uint64_t q1_a_f                       : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} cn31xx;
+	struct cvmx_npi_int_sum_s             cn38xx;
+	struct cvmx_npi_int_sum_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_42_63               : 22;
+	uint64_t iobdma                       : 1;  /**< Requested IOBDMA read size exceeded 128 words. */
+	uint64_t p_dperr                      : 1;  /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+	uint64_t win_rto                      : 1;  /**< Windowed Load Timed Out. */
+	uint64_t i3_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i2_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i1_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t i0_pperr                     : 1;  /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+	uint64_t p3_ptout                     : 1;  /**< Port-3 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p2_ptout                     : 1;  /**< Port-2 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p1_ptout                     : 1;  /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p0_ptout                     : 1;  /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+	uint64_t p3_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p2_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p1_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t p0_pperr                     : 1;  /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+	uint64_t g3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t g0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+	uint64_t p3_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p2_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p1_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p0_perr                      : 1;  /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+	uint64_t p3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t p0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+	uint64_t i3_overf                     : 1;  /**< Port-3 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i2_overf                     : 1;  /**< Port-2 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i1_overf                     : 1;  /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i0_overf                     : 1;  /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+	uint64_t i3_rtout                     : 1;  /**< Port-3 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i2_rtout                     : 1;  /**< Port-2 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i1_rtout                     : 1;  /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t i0_rtout                     : 1;  /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+	uint64_t po3_2sml                     : 1;  /**< The packet being sent out on Port3 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
+	uint64_t po2_2sml                     : 1;  /**< The packet being sent out on Port2 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
+	uint64_t po1_2sml                     : 1;  /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+	uint64_t po0_2sml                     : 1;  /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+	uint64_t pci_rsl                      : 1;  /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+	uint64_t rml_wto                      : 1;  /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+	uint64_t rml_rto                      : 1;  /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+	uint64_t rml_rto                      : 1;
+	uint64_t rml_wto                      : 1;
+	uint64_t pci_rsl                      : 1;
+	uint64_t po0_2sml                     : 1;
+	uint64_t po1_2sml                     : 1;
+	uint64_t po2_2sml                     : 1;
+	uint64_t po3_2sml                     : 1;
+	uint64_t i0_rtout                     : 1;
+	uint64_t i1_rtout                     : 1;
+	uint64_t i2_rtout                     : 1;
+	uint64_t i3_rtout                     : 1;
+	uint64_t i0_overf                     : 1;
+	uint64_t i1_overf                     : 1;
+	uint64_t i2_overf                     : 1;
+	uint64_t i3_overf                     : 1;
+	uint64_t p0_rtout                     : 1;
+	uint64_t p1_rtout                     : 1;
+	uint64_t p2_rtout                     : 1;
+	uint64_t p3_rtout                     : 1;
+	uint64_t p0_perr                      : 1;
+	uint64_t p1_perr                      : 1;
+	uint64_t p2_perr                      : 1;
+	uint64_t p3_perr                      : 1;
+	uint64_t g0_rtout                     : 1;
+	uint64_t g1_rtout                     : 1;
+	uint64_t g2_rtout                     : 1;
+	uint64_t g3_rtout                     : 1;
+	uint64_t p0_pperr                     : 1;
+	uint64_t p1_pperr                     : 1;
+	uint64_t p2_pperr                     : 1;
+	uint64_t p3_pperr                     : 1;
+	uint64_t p0_ptout                     : 1;
+	uint64_t p1_ptout                     : 1;
+	uint64_t p2_ptout                     : 1;
+	uint64_t p3_ptout                     : 1;
+	uint64_t i0_pperr                     : 1;
+	uint64_t i1_pperr                     : 1;
+	uint64_t i2_pperr                     : 1;
+	uint64_t i3_pperr                     : 1;
+	uint64_t win_rto                      : 1;
+	uint64_t p_dperr                      : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_42_63               : 22;
+#endif
+	} cn38xxp2;
+	struct cvmx_npi_int_sum_cn31xx        cn50xx;
+	struct cvmx_npi_int_sum_s             cn58xx;
+	struct cvmx_npi_int_sum_s             cn58xxp1;
+};
+typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t;
+
+/**
+ * cvmx_npi_lowp_dbell
+ *
+ * NPI_LOWP_DBELL = Low Priority Door Bell
+ *
+ * The door bell register for the low priority DMA queue.
+ */
+union cvmx_npi_lowp_dbell
+{
+	uint64_t u64;
+	struct cvmx_npi_lowp_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dbell                        : 16; /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the low priority dma queue. */
+#else
+	uint64_t dbell                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_npi_lowp_dbell_s          cn30xx;
+	struct cvmx_npi_lowp_dbell_s          cn31xx;
+	struct cvmx_npi_lowp_dbell_s          cn38xx;
+	struct cvmx_npi_lowp_dbell_s          cn38xxp2;
+	struct cvmx_npi_lowp_dbell_s          cn50xx;
+	struct cvmx_npi_lowp_dbell_s          cn58xx;
+	struct cvmx_npi_lowp_dbell_s          cn58xxp1;
+};
+typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t;
+
+/**
+ * cvmx_npi_lowp_ibuff_saddr
+ *
+ * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address
+ *
+ * The address to start reading Instructions from for LOWP.
+ */
+union cvmx_npi_lowp_ibuff_saddr
+{
+	uint64_t u64;
+	struct cvmx_npi_lowp_ibuff_saddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t saddr                        : 36; /**< The starting address to read the first instruction. */
+#else
+	uint64_t saddr                        : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn30xx;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn31xx;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn38xx;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn38xxp2;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn50xx;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn58xx;
+	struct cvmx_npi_lowp_ibuff_saddr_s    cn58xxp1;
+};
+typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t;
+
+/**
+ * cvmx_npi_mem_access_subid#
+ *
+ * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register
+ *
+ * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+union cvmx_npi_mem_access_subidx
+{
+	uint64_t u64;
+	struct cvmx_npi_mem_access_subidx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t shortl                       : 1;  /**< Generate CMD-6 on PCI(x) when '1'.
+                                                         Loads from the cores to the corresponding subid
+                                                         that are 32-bits or smaller:
+                                                         - Will generate the PCI-X "Memory Read DWORD"
+                                                           command in PCI-X mode. (Note that "Memory
+                                                           Read DWORD" appears much like an IO read on
+                                                           the PCI-X bus.)
+                                                         - Will generate the PCI "Memory Read" command
+                                                           in PCI-X mode, irrespective of the
+                                                           NPI_PCI_READ_CMD[CMD_SIZE] value.
+                                                         NOT IN PASS 1 NOR PASS 2 */
+	uint64_t nmerge                       : 1;  /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */
+	uint64_t esr                          : 2;  /**< Endian-Swap on read. */
+	uint64_t esw                          : 2;  /**< Endian-Swap on write. */
+	uint64_t nsr                          : 1;  /**< No-Snoop on read. */
+	uint64_t nsw                          : 1;  /**< No-Snoop on write. */
+	uint64_t ror                          : 1;  /**< Relax Read on read. */
+	uint64_t row                          : 1;  /**< Relax Order on write. */
+	uint64_t ba                           : 28; /**< PCI Address bits [63:36]. */
+#else
+	uint64_t ba                           : 28;
+	uint64_t row                          : 1;
+	uint64_t ror                          : 1;
+	uint64_t nsw                          : 1;
+	uint64_t nsr                          : 1;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t nmerge                       : 1;
+	uint64_t shortl                       : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_npi_mem_access_subidx_s   cn30xx;
+	struct cvmx_npi_mem_access_subidx_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t esr                          : 2;  /**< Endian-Swap on read. */
+	uint64_t esw                          : 2;  /**< Endian-Swap on write. */
+	uint64_t nsr                          : 1;  /**< No-Snoop on read. */
+	uint64_t nsw                          : 1;  /**< No-Snoop on write. */
+	uint64_t ror                          : 1;  /**< Relax Read on read. */
+	uint64_t row                          : 1;  /**< Relax Order on write. */
+	uint64_t ba                           : 28; /**< PCI Address bits [63:36]. */
+#else
+	uint64_t ba                           : 28;
+	uint64_t row                          : 1;
+	uint64_t ror                          : 1;
+	uint64_t nsw                          : 1;
+	uint64_t nsr                          : 1;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_npi_mem_access_subidx_s   cn38xx;
+	struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
+	struct cvmx_npi_mem_access_subidx_s   cn50xx;
+	struct cvmx_npi_mem_access_subidx_s   cn58xx;
+	struct cvmx_npi_mem_access_subidx_s   cn58xxp1;
+};
+typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t;
+
+/**
+ * cvmx_npi_msi_rcv
+ *
+ * NPI_MSI_RCV = NPI MSI Receive Vector Register
+ *
+ * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
+ */
+union cvmx_npi_msi_rcv
+{
+	uint64_t u64;
+	struct cvmx_npi_msi_rcv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t int_vec                      : 64; /**< Refer to PCI_MSI_RCV */
+#else
+	uint64_t int_vec                      : 64;
+#endif
+	} s;
+	struct cvmx_npi_msi_rcv_s             cn30xx;
+	struct cvmx_npi_msi_rcv_s             cn31xx;
+	struct cvmx_npi_msi_rcv_s             cn38xx;
+	struct cvmx_npi_msi_rcv_s             cn38xxp2;
+	struct cvmx_npi_msi_rcv_s             cn50xx;
+	struct cvmx_npi_msi_rcv_s             cn58xx;
+	struct cvmx_npi_msi_rcv_s             cn58xxp1;
+};
+typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t;
+
+/**
+ * cvmx_npi_num_desc_output#
+ *
+ * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0
+ *
+ * The size of the Buffer/Info Pointer Pair ring for Output-0.
+ */
+union cvmx_npi_num_desc_outputx
+{
+	uint64_t u64;
+	struct cvmx_npi_num_desc_outputx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t size                         : 32; /**< The size of the Buffer/Info Pointer Pair ring. */
+#else
+	uint64_t size                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npi_num_desc_outputx_s    cn30xx;
+	struct cvmx_npi_num_desc_outputx_s    cn31xx;
+	struct cvmx_npi_num_desc_outputx_s    cn38xx;
+	struct cvmx_npi_num_desc_outputx_s    cn38xxp2;
+	struct cvmx_npi_num_desc_outputx_s    cn50xx;
+	struct cvmx_npi_num_desc_outputx_s    cn58xx;
+	struct cvmx_npi_num_desc_outputx_s    cn58xxp1;
+};
+typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t;
+
+/**
+ * cvmx_npi_output_control
+ *
+ * NPI_OUTPUT_CONTROL = NPI's Output Control Register
+ *
+ * The address to start reading Instructions from for Output-3.
+ */
+union cvmx_npi_output_control
+{
+	uint64_t u64;
+	struct cvmx_npi_output_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the output packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the output packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS3 Field */
+	uint64_t p3_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT3 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p2_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT2 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p1_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t o3_es                        : 2;  /**< Endian Swap for Output3 Data. */
+	uint64_t o3_ns                        : 1;  /**< NoSnoop Enable for Output3 Data. */
+	uint64_t o3_ro                        : 1;  /**< Relaxed Ordering Enable for Output3 Data. */
+	uint64_t o2_es                        : 2;  /**< Endian Swap for Output2 Data. */
+	uint64_t o2_ns                        : 1;  /**< NoSnoop Enable for Output2 Data. */
+	uint64_t o2_ro                        : 1;  /**< Relaxed Ordering Enable for Output2 Data. */
+	uint64_t o1_es                        : 2;  /**< Endian Swap for Output1 Data. */
+	uint64_t o1_ns                        : 1;  /**< NoSnoop Enable for Output1 Data. */
+	uint64_t o1_ro                        : 1;  /**< Relaxed Ordering Enable for Output1 Data. */
+	uint64_t o0_es                        : 2;  /**< Endian Swap for Output0 Data. */
+	uint64_t o0_ns                        : 1;  /**< NoSnoop Enable for Output0 Data. */
+	uint64_t o0_ro                        : 1;  /**< Relaxed Ordering Enable for Output0 Data. */
+	uint64_t o3_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O3_ES,
+                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
+	uint64_t o2_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O2_ES,
+                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
+	uint64_t o1_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+	uint64_t o0_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+	uint64_t reserved_20_23               : 4;
+	uint64_t iptr_o3                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-3. */
+	uint64_t iptr_o2                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-2. */
+	uint64_t iptr_o1                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+	uint64_t iptr_o0                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+	uint64_t esr_sl3                      : 2;  /**< The Endian-Swap-Mode for Slist3 reads. */
+	uint64_t nsr_sl3                      : 1;  /**< Enables '1' NoSnoop for Slist3 reads. */
+	uint64_t ror_sl3                      : 1;  /**< Enables '1' Relaxed Ordering for Slist3 reads. */
+	uint64_t esr_sl2                      : 2;  /**< The Endian-Swap-Mode for Slist2 reads. */
+	uint64_t nsr_sl2                      : 1;  /**< Enables '1' NoSnoop for Slist2 reads. */
+	uint64_t ror_sl2                      : 1;  /**< Enables '1' Relaxed Ordering for Slist2 reads. */
+	uint64_t esr_sl1                      : 2;  /**< The Endian-Swap-Mode for Slist1 reads. */
+	uint64_t nsr_sl1                      : 1;  /**< Enables '1' NoSnoop for Slist1 reads. */
+	uint64_t ror_sl1                      : 1;  /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+	uint64_t esr_sl0                      : 2;  /**< The Endian-Swap-Mode for Slist0 reads. */
+	uint64_t nsr_sl0                      : 1;  /**< Enables '1' NoSnoop for Slist0 reads. */
+	uint64_t ror_sl0                      : 1;  /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+	uint64_t ror_sl0                      : 1;
+	uint64_t nsr_sl0                      : 1;
+	uint64_t esr_sl0                      : 2;
+	uint64_t ror_sl1                      : 1;
+	uint64_t nsr_sl1                      : 1;
+	uint64_t esr_sl1                      : 2;
+	uint64_t ror_sl2                      : 1;
+	uint64_t nsr_sl2                      : 1;
+	uint64_t esr_sl2                      : 2;
+	uint64_t ror_sl3                      : 1;
+	uint64_t nsr_sl3                      : 1;
+	uint64_t esr_sl3                      : 2;
+	uint64_t iptr_o0                      : 1;
+	uint64_t iptr_o1                      : 1;
+	uint64_t iptr_o2                      : 1;
+	uint64_t iptr_o3                      : 1;
+	uint64_t reserved_20_23               : 4;
+	uint64_t o0_csrm                      : 1;
+	uint64_t o1_csrm                      : 1;
+	uint64_t o2_csrm                      : 1;
+	uint64_t o3_csrm                      : 1;
+	uint64_t o0_ro                        : 1;
+	uint64_t o0_ns                        : 1;
+	uint64_t o0_es                        : 2;
+	uint64_t o1_ro                        : 1;
+	uint64_t o1_ns                        : 1;
+	uint64_t o1_es                        : 2;
+	uint64_t o2_ro                        : 1;
+	uint64_t o2_ns                        : 1;
+	uint64_t o2_es                        : 2;
+	uint64_t o3_ro                        : 1;
+	uint64_t o3_ns                        : 1;
+	uint64_t o3_es                        : 2;
+	uint64_t p0_bmode                     : 1;
+	uint64_t p1_bmode                     : 1;
+	uint64_t p2_bmode                     : 1;
+	uint64_t p3_bmode                     : 1;
+	uint64_t pkt_rr                       : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_npi_output_control_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_45_63               : 19;
+	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t reserved_32_43               : 12;
+	uint64_t o0_es                        : 2;  /**< Endian Swap for Output0 Data. */
+	uint64_t o0_ns                        : 1;  /**< NoSnoop Enable for Output0 Data. */
+	uint64_t o0_ro                        : 1;  /**< Relaxed Ordering Enable for Output0 Data. */
+	uint64_t reserved_25_27               : 3;
+	uint64_t o0_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+	uint64_t reserved_17_23               : 7;
+	uint64_t iptr_o0                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+	uint64_t reserved_4_15                : 12;
+	uint64_t esr_sl0                      : 2;  /**< The Endian-Swap-Mode for Slist0 reads. */
+	uint64_t nsr_sl0                      : 1;  /**< Enables '1' NoSnoop for Slist0 reads. */
+	uint64_t ror_sl0                      : 1;  /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+	uint64_t ror_sl0                      : 1;
+	uint64_t nsr_sl0                      : 1;
+	uint64_t esr_sl0                      : 2;
+	uint64_t reserved_4_15                : 12;
+	uint64_t iptr_o0                      : 1;
+	uint64_t reserved_17_23               : 7;
+	uint64_t o0_csrm                      : 1;
+	uint64_t reserved_25_27               : 3;
+	uint64_t o0_ro                        : 1;
+	uint64_t o0_ns                        : 1;
+	uint64_t o0_es                        : 2;
+	uint64_t reserved_32_43               : 12;
+	uint64_t p0_bmode                     : 1;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} cn30xx;
+	struct cvmx_npi_output_control_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_46_63               : 18;
+	uint64_t p1_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t reserved_36_43               : 8;
+	uint64_t o1_es                        : 2;  /**< Endian Swap for Output1 Data. */
+	uint64_t o1_ns                        : 1;  /**< NoSnoop Enable for Output1 Data. */
+	uint64_t o1_ro                        : 1;  /**< Relaxed Ordering Enable for Output1 Data. */
+	uint64_t o0_es                        : 2;  /**< Endian Swap for Output0 Data. */
+	uint64_t o0_ns                        : 1;  /**< NoSnoop Enable for Output0 Data. */
+	uint64_t o0_ro                        : 1;  /**< Relaxed Ordering Enable for Output0 Data. */
+	uint64_t reserved_26_27               : 2;
+	uint64_t o1_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+	uint64_t o0_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+	uint64_t reserved_18_23               : 6;
+	uint64_t iptr_o1                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+	uint64_t iptr_o0                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t esr_sl1                      : 2;  /**< The Endian-Swap-Mode for Slist1 reads. */
+	uint64_t nsr_sl1                      : 1;  /**< Enables '1' NoSnoop for Slist1 reads. */
+	uint64_t ror_sl1                      : 1;  /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+	uint64_t esr_sl0                      : 2;  /**< The Endian-Swap-Mode for Slist0 reads. */
+	uint64_t nsr_sl0                      : 1;  /**< Enables '1' NoSnoop for Slist0 reads. */
+	uint64_t ror_sl0                      : 1;  /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+	uint64_t ror_sl0                      : 1;
+	uint64_t nsr_sl0                      : 1;
+	uint64_t esr_sl0                      : 2;
+	uint64_t ror_sl1                      : 1;
+	uint64_t nsr_sl1                      : 1;
+	uint64_t esr_sl1                      : 2;
+	uint64_t reserved_8_15                : 8;
+	uint64_t iptr_o0                      : 1;
+	uint64_t iptr_o1                      : 1;
+	uint64_t reserved_18_23               : 6;
+	uint64_t o0_csrm                      : 1;
+	uint64_t o1_csrm                      : 1;
+	uint64_t reserved_26_27               : 2;
+	uint64_t o0_ro                        : 1;
+	uint64_t o0_ns                        : 1;
+	uint64_t o0_es                        : 2;
+	uint64_t o1_ro                        : 1;
+	uint64_t o1_ns                        : 1;
+	uint64_t o1_es                        : 2;
+	uint64_t reserved_36_43               : 8;
+	uint64_t p0_bmode                     : 1;
+	uint64_t p1_bmode                     : 1;
+	uint64_t reserved_46_63               : 18;
+#endif
+	} cn31xx;
+	struct cvmx_npi_output_control_s      cn38xx;
+	struct cvmx_npi_output_control_cn38xxp2
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t p3_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT3 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p2_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT2 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p1_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t o3_es                        : 2;  /**< Endian Swap for Output3 Data. */
+	uint64_t o3_ns                        : 1;  /**< NoSnoop Enable for Output3 Data. */
+	uint64_t o3_ro                        : 1;  /**< Relaxed Ordering Enable for Output3 Data. */
+	uint64_t o2_es                        : 2;  /**< Endian Swap for Output2 Data. */
+	uint64_t o2_ns                        : 1;  /**< NoSnoop Enable for Output2 Data. */
+	uint64_t o2_ro                        : 1;  /**< Relaxed Ordering Enable for Output2 Data. */
+	uint64_t o1_es                        : 2;  /**< Endian Swap for Output1 Data. */
+	uint64_t o1_ns                        : 1;  /**< NoSnoop Enable for Output1 Data. */
+	uint64_t o1_ro                        : 1;  /**< Relaxed Ordering Enable for Output1 Data. */
+	uint64_t o0_es                        : 2;  /**< Endian Swap for Output0 Data. */
+	uint64_t o0_ns                        : 1;  /**< NoSnoop Enable for Output0 Data. */
+	uint64_t o0_ro                        : 1;  /**< Relaxed Ordering Enable for Output0 Data. */
+	uint64_t o3_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O3_ES,
+                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
+	uint64_t o2_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O2_ES,
+                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
+	uint64_t o1_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+	uint64_t o0_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+	uint64_t reserved_20_23               : 4;
+	uint64_t iptr_o3                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-3. */
+	uint64_t iptr_o2                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-2. */
+	uint64_t iptr_o1                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+	uint64_t iptr_o0                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+	uint64_t esr_sl3                      : 2;  /**< The Endian-Swap-Mode for Slist3 reads. */
+	uint64_t nsr_sl3                      : 1;  /**< Enables '1' NoSnoop for Slist3 reads. */
+	uint64_t ror_sl3                      : 1;  /**< Enables '1' Relaxed Ordering for Slist3 reads. */
+	uint64_t esr_sl2                      : 2;  /**< The Endian-Swap-Mode for Slist2 reads. */
+	uint64_t nsr_sl2                      : 1;  /**< Enables '1' NoSnoop for Slist2 reads. */
+	uint64_t ror_sl2                      : 1;  /**< Enables '1' Relaxed Ordering for Slist2 reads. */
+	uint64_t esr_sl1                      : 2;  /**< The Endian-Swap-Mode for Slist1 reads. */
+	uint64_t nsr_sl1                      : 1;  /**< Enables '1' NoSnoop for Slist1 reads. */
+	uint64_t ror_sl1                      : 1;  /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+	uint64_t esr_sl0                      : 2;  /**< The Endian-Swap-Mode for Slist0 reads. */
+	uint64_t nsr_sl0                      : 1;  /**< Enables '1' NoSnoop for Slist0 reads. */
+	uint64_t ror_sl0                      : 1;  /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+	uint64_t ror_sl0                      : 1;
+	uint64_t nsr_sl0                      : 1;
+	uint64_t esr_sl0                      : 2;
+	uint64_t ror_sl1                      : 1;
+	uint64_t nsr_sl1                      : 1;
+	uint64_t esr_sl1                      : 2;
+	uint64_t ror_sl2                      : 1;
+	uint64_t nsr_sl2                      : 1;
+	uint64_t esr_sl2                      : 2;
+	uint64_t ror_sl3                      : 1;
+	uint64_t nsr_sl3                      : 1;
+	uint64_t esr_sl3                      : 2;
+	uint64_t iptr_o0                      : 1;
+	uint64_t iptr_o1                      : 1;
+	uint64_t iptr_o2                      : 1;
+	uint64_t iptr_o3                      : 1;
+	uint64_t reserved_20_23               : 4;
+	uint64_t o0_csrm                      : 1;
+	uint64_t o1_csrm                      : 1;
+	uint64_t o2_csrm                      : 1;
+	uint64_t o3_csrm                      : 1;
+	uint64_t o0_ro                        : 1;
+	uint64_t o0_ns                        : 1;
+	uint64_t o0_es                        : 2;
+	uint64_t o1_ro                        : 1;
+	uint64_t o1_ns                        : 1;
+	uint64_t o1_es                        : 2;
+	uint64_t o2_ro                        : 1;
+	uint64_t o2_ns                        : 1;
+	uint64_t o2_es                        : 2;
+	uint64_t o3_ro                        : 1;
+	uint64_t o3_ns                        : 1;
+	uint64_t o3_es                        : 2;
+	uint64_t p0_bmode                     : 1;
+	uint64_t p1_bmode                     : 1;
+	uint64_t p2_bmode                     : 1;
+	uint64_t p3_bmode                     : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn38xxp2;
+	struct cvmx_npi_output_control_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the output packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the output packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS2 Field */
+	uint64_t reserved_46_47               : 2;
+	uint64_t p1_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t p0_bmode                     : 1;  /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+	uint64_t reserved_36_43               : 8;
+	uint64_t o1_es                        : 2;  /**< Endian Swap for Output1 Data. */
+	uint64_t o1_ns                        : 1;  /**< NoSnoop Enable for Output1 Data. */
+	uint64_t o1_ro                        : 1;  /**< Relaxed Ordering Enable for Output1 Data. */
+	uint64_t o0_es                        : 2;  /**< Endian Swap for Output0 Data. */
+	uint64_t o0_ns                        : 1;  /**< NoSnoop Enable for Output0 Data. */
+	uint64_t o0_ro                        : 1;  /**< Relaxed Ordering Enable for Output0 Data. */
+	uint64_t reserved_26_27               : 2;
+	uint64_t o1_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+	uint64_t o0_csrm                      : 1;  /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+	uint64_t reserved_18_23               : 6;
+	uint64_t iptr_o1                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+	uint64_t iptr_o0                      : 1;  /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+	uint64_t reserved_8_15                : 8;
+	uint64_t esr_sl1                      : 2;  /**< The Endian-Swap-Mode for Slist1 reads. */
+	uint64_t nsr_sl1                      : 1;  /**< Enables '1' NoSnoop for Slist1 reads. */
+	uint64_t ror_sl1                      : 1;  /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+	uint64_t esr_sl0                      : 2;  /**< The Endian-Swap-Mode for Slist0 reads. */
+	uint64_t nsr_sl0                      : 1;  /**< Enables '1' NoSnoop for Slist0 reads. */
+	uint64_t ror_sl0                      : 1;  /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+	uint64_t ror_sl0                      : 1;
+	uint64_t nsr_sl0                      : 1;
+	uint64_t esr_sl0                      : 2;
+	uint64_t ror_sl1                      : 1;
+	uint64_t nsr_sl1                      : 1;
+	uint64_t esr_sl1                      : 2;
+	uint64_t reserved_8_15                : 8;
+	uint64_t iptr_o0                      : 1;
+	uint64_t iptr_o1                      : 1;
+	uint64_t reserved_18_23               : 6;
+	uint64_t o0_csrm                      : 1;
+	uint64_t o1_csrm                      : 1;
+	uint64_t reserved_26_27               : 2;
+	uint64_t o0_ro                        : 1;
+	uint64_t o0_ns                        : 1;
+	uint64_t o0_es                        : 2;
+	uint64_t o1_ro                        : 1;
+	uint64_t o1_ns                        : 1;
+	uint64_t o1_es                        : 2;
+	uint64_t reserved_36_43               : 8;
+	uint64_t p0_bmode                     : 1;
+	uint64_t p1_bmode                     : 1;
+	uint64_t reserved_46_47               : 2;
+	uint64_t pkt_rr                       : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn50xx;
+	struct cvmx_npi_output_control_s      cn58xx;
+	struct cvmx_npi_output_control_s      cn58xxp1;
+};
+typedef union cvmx_npi_output_control cvmx_npi_output_control_t;
+
+/**
+ * cvmx_npi_p#_dbpair_addr
+ *
+ * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.
+ *
+ * Contains the next address to read for Port's-0 Data/Buffer Pair.
+ */
+union cvmx_npi_px_dbpair_addr
+{
+	uint64_t u64;
+	struct cvmx_npi_px_dbpair_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_63_63               : 1;
+	uint64_t state                        : 2;  /**< POS state machine vector. Used to tell when NADDR
+                                                         is valid (when STATE == 0). */
+	uint64_t naddr                        : 61; /**< Bits [63:3] of the next Data-Info Pair to read.
+                                                         Value is only valid when STATE == 0. */
+#else
+	uint64_t naddr                        : 61;
+	uint64_t state                        : 2;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} s;
+	struct cvmx_npi_px_dbpair_addr_s      cn30xx;
+	struct cvmx_npi_px_dbpair_addr_s      cn31xx;
+	struct cvmx_npi_px_dbpair_addr_s      cn38xx;
+	struct cvmx_npi_px_dbpair_addr_s      cn38xxp2;
+	struct cvmx_npi_px_dbpair_addr_s      cn50xx;
+	struct cvmx_npi_px_dbpair_addr_s      cn58xx;
+	struct cvmx_npi_px_dbpair_addr_s      cn58xxp1;
+};
+typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t;
+
+/**
+ * cvmx_npi_p#_instr_addr
+ *
+ * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.
+ *
+ * Contains the next address to read for Port's-0 Instructions.
+ */
+union cvmx_npi_px_instr_addr
+{
+	uint64_t u64;
+	struct cvmx_npi_px_instr_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t state                        : 3;  /**< Gather engine state vector. Used to tell when
+                                                         NADDR is valid (when STATE == 0). */
+	uint64_t naddr                        : 61; /**< Bits [63:3] of the next Instruction to read.
+                                                         Value is only valid when STATE == 0. */
+#else
+	uint64_t naddr                        : 61;
+	uint64_t state                        : 3;
+#endif
+	} s;
+	struct cvmx_npi_px_instr_addr_s       cn30xx;
+	struct cvmx_npi_px_instr_addr_s       cn31xx;
+	struct cvmx_npi_px_instr_addr_s       cn38xx;
+	struct cvmx_npi_px_instr_addr_s       cn38xxp2;
+	struct cvmx_npi_px_instr_addr_s       cn50xx;
+	struct cvmx_npi_px_instr_addr_s       cn58xx;
+	struct cvmx_npi_px_instr_addr_s       cn58xxp1;
+};
+typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t;
+
+/**
+ * cvmx_npi_p#_instr_cnts
+ *
+ * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.
+ *
+ * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
+ */
+union cvmx_npi_px_instr_cnts
+{
+	uint64_t u64;
+	struct cvmx_npi_px_instr_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t fcnt                         : 6;  /**< Number entries in the Instruction FIFO. */
+	uint64_t avail                        : 32; /**< Doorbell count to be read. */
+#else
+	uint64_t avail                        : 32;
+	uint64_t fcnt                         : 6;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_npi_px_instr_cnts_s       cn30xx;
+	struct cvmx_npi_px_instr_cnts_s       cn31xx;
+	struct cvmx_npi_px_instr_cnts_s       cn38xx;
+	struct cvmx_npi_px_instr_cnts_s       cn38xxp2;
+	struct cvmx_npi_px_instr_cnts_s       cn50xx;
+	struct cvmx_npi_px_instr_cnts_s       cn58xx;
+	struct cvmx_npi_px_instr_cnts_s       cn58xxp1;
+};
+typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t;
+
+/**
+ * cvmx_npi_p#_pair_cnts
+ *
+ * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.
+ *
+ * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
+ */
+union cvmx_npi_px_pair_cnts
+{
+	uint64_t u64;
+	struct cvmx_npi_px_pair_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t fcnt                         : 5;  /**< 16 - number entries in the D/I Pair FIFO. */
+	uint64_t avail                        : 32; /**< Doorbell count to be read. */
+#else
+	uint64_t avail                        : 32;
+	uint64_t fcnt                         : 5;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_npi_px_pair_cnts_s        cn30xx;
+	struct cvmx_npi_px_pair_cnts_s        cn31xx;
+	struct cvmx_npi_px_pair_cnts_s        cn38xx;
+	struct cvmx_npi_px_pair_cnts_s        cn38xxp2;
+	struct cvmx_npi_px_pair_cnts_s        cn50xx;
+	struct cvmx_npi_px_pair_cnts_s        cn58xx;
+	struct cvmx_npi_px_pair_cnts_s        cn58xxp1;
+};
+typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t;
+
+/**
+ * cvmx_npi_pci_burst_size
+ *
+ * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register
+ *
+ * Control the number of words the NPI will attempt to read / write to/from the PCI.
+ */
+union cvmx_npi_pci_burst_size
+{
+	uint64_t u64;
+	struct cvmx_npi_pci_burst_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t wr_brst                      : 7;  /**< The number of 8B words to write to PCI in any one
+                                                         write operation. A zero is equal to 128. This
+                                                         value is used the packet reads and is clamped at
+                                                         a max of 112 for dma writes. */
+	uint64_t rd_brst                      : 7;  /**< Number of 8B words to read from PCI in any one
+                                                         read operation. Legal values are 1 to 127, where
+                                                         a 0 will be treated as a 1.
+                                                         "For reading of packet data value is limited to 64
+                                                         in PASS-2."
+                                                         This value does not control the size of a read
+                                                         caused by an IOBDMA from a PP. */
+#else
+	uint64_t rd_brst                      : 7;
+	uint64_t wr_brst                      : 7;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_npi_pci_burst_size_s      cn30xx;
+	struct cvmx_npi_pci_burst_size_s      cn31xx;
+	struct cvmx_npi_pci_burst_size_s      cn38xx;
+	struct cvmx_npi_pci_burst_size_s      cn38xxp2;
+	struct cvmx_npi_pci_burst_size_s      cn50xx;
+	struct cvmx_npi_pci_burst_size_s      cn58xx;
+	struct cvmx_npi_pci_burst_size_s      cn58xxp1;
+};
+typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t;
+
+/**
+ * cvmx_npi_pci_int_arb_cfg
+ *
+ * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter
+ *
+ * Controls operation of the Internal PCI Arbiter.  This register should
+ * only be written when PRST# is asserted.  NPI_PCI_INT_ARB_CFG[EN] should
+ * only be set when Octane is a host.
+ */
+union cvmx_npi_pci_int_arb_cfg
+{
+	uint64_t u64;
+	struct cvmx_npi_pci_int_arb_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t hostmode                     : 1;  /**< PCI Host Mode Pin (sampled for use by software).
+                                                         This bit reflects the sampled PCI_HOSTMODE pin.
+                                                         In HOST Mode, OCTEON drives the PCI_CLK_OUT and
+                                                         PCI initialization pattern during PCI_RST_N deassertion). */
+	uint64_t pci_ovr                      : 4;  /**< PCI Host Mode Bus Speed/Type Override
+                                                          When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting
+                                                          as the PCI Central Agent, samples the PCI_PCI100,
+                                                          PCI_M66EN and PCI_PCIXCAP pins to determine the
+                                                          'sampled' PCI Bus speed and Bus Type (PCI or PCIX).
+                                                          (see: PCI_CNT_REG[HM_SPEED,HM_PCIX])
+                                                          However, in some cases, SW may want to override the
+                                                          the 'sampled' PCI Bus Type/Speed, and use some
+                                                          SLOWER Bus frequency.
+                                                          The PCI_OVR field encoding represents the 'override'
+                                                          PCI Bus Type/Speed which will be used to generate the
+                                                          PCI_CLK_OUT and determines the PCI initialization pattern
+                                                          driven during PCI_RST_N deassertion.
+                                                              PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE)
+                                                              PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX)
+                                                              PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133)
+                                                         OVERRIDE TYPE SPEED |  Override Configuration
+                                                            [3]   [2]  [1:0] | TYPE       SPEED
+                                                           ------------------+-------------------------------
+                                                             0     x      xx | No override(uses 'sampled'
+                                                                             | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX)
+                                                             1     0      00 | PCI Mode    33MHz
+                                                             1     0      01 | PCI Mode    66MHz
+                                                             1     0      10 | RESERVED (DO NOT USE)
+                                                             1     0      11 | RESERVED (DO NOT USE)
+                                                             1     1      00 | RESERVED (DO NOT USE)
+                                                             1     1      01 | PCIX Mode   66MHz
+                                                             1     1      10 | PCIX Mode  100MHz
+                                                             1     1      11 | PCIX Mode  133MHz
+                                                          NOTES:
+                                                          - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on
+                                                            PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus
+                                                            Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX]
+                                                            which reflects the actual PCI Bus Type(0:PCI/1:PCIX).
+                                                          - Software should never 'up' configure the recommended values.
+                                                            In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0),
+                                                            then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode.
+                                                            Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01),
+                                                            then SW should NOT attempt to 'speed up' the bus [ie:
+                                                            SPEED[1:0]=10(100MHz)].
+                                                          - If PCI_OVR<3> is set prior to PCI reset de-assertion
+                                                            in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR]
+                                                            indicates the Bus Type/Speed that OCTEON drove on the
+                                                            DEVSEL/STOP/TRDY pins during reset de-assertion. (user
+                                                            should then ignore the 'sampled' Bus Type/Speed
+                                                            contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields.
+                                                          - If PCI_OVR<3> is clear prior to PCI reset de-assertion
+                                                            in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED])
+                                                            indicates the Bus Type/Speed that OCTEON drove on the
+                                                            DEVSEL/STOP/TRDY pins during reset de-assertion. */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t en                           : 1;  /**< Internal arbiter enable. */
+	uint64_t park_mod                     : 1;  /**< Bus park mode. 0=park on last, 1=park on device. */
+	uint64_t park_dev                     : 3;  /**< Bus park device. 0-3 External device, 4 = Octane. */
+#else
+	uint64_t park_dev                     : 3;
+	uint64_t park_mod                     : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pci_ovr                      : 4;
+	uint64_t hostmode                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_npi_pci_int_arb_cfg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t en                           : 1;  /**< Internal arbiter enable. */
+	uint64_t park_mod                     : 1;  /**< Bus park mode. 0=park on last, 1=park on device. */
+	uint64_t park_dev                     : 3;  /**< Bus park device. 0-3 External device, 4 = Octane. */
+#else
+	uint64_t park_dev                     : 3;
+	uint64_t park_mod                     : 1;
+	uint64_t en                           : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} cn30xx;
+	struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
+	struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
+	struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
+	struct cvmx_npi_pci_int_arb_cfg_s     cn50xx;
+	struct cvmx_npi_pci_int_arb_cfg_s     cn58xx;
+	struct cvmx_npi_pci_int_arb_cfg_s     cn58xxp1;
+};
+typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t;
+
+/**
+ * cvmx_npi_pci_read_cmd
+ *
+ * NPI_PCI_READ_CMD = NPI PCI Read Command Register
+ *
+ * Controls the type of read command sent.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
+ * FIFO will use the value of this register after it has been updated.
+ */
+union cvmx_npi_pci_read_cmd
+{
+	uint64_t u64;
+	struct cvmx_npi_pci_read_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t cmd_size                     : 11; /**< Number bytes to be read is equal to or exceeds this
+                                                         size will cause the PCI in PCI mode to use a
+                                                         Memory-Read-Multiple. This register has a value
+                                                         from 8 to 2048. A value of 0-7 will be treated as
+                                                         a value of 2048. */
+#else
+	uint64_t cmd_size                     : 11;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_npi_pci_read_cmd_s        cn30xx;
+	struct cvmx_npi_pci_read_cmd_s        cn31xx;
+	struct cvmx_npi_pci_read_cmd_s        cn38xx;
+	struct cvmx_npi_pci_read_cmd_s        cn38xxp2;
+	struct cvmx_npi_pci_read_cmd_s        cn50xx;
+	struct cvmx_npi_pci_read_cmd_s        cn58xx;
+	struct cvmx_npi_pci_read_cmd_s        cn58xxp1;
+};
+typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t;
+
+/**
+ * cvmx_npi_port32_instr_hdr
+ *
+ * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header
+ *
+ * Contains bits [62:42] of the Instruction Header for port 32.
+ */
+union cvmx_npi_port32_instr_hdr
+{
+	uint64_t u64;
+	struct cvmx_npi_port32_instr_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t rsv_f                        : 5;  /**< Reserved */
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t rsv_e                        : 1;  /**< Reserved */
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t rsv_d                        : 6;  /**< Reserved */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t rsv_c                        : 5;  /**< Reserved */
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_b                        : 1;  /**< Reserved
+                                                         instruction header sent to IPD. */
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_a                        : 6;  /**< Reserved */
+#else
+	uint64_t rsv_a                        : 6;
+	uint64_t skp_len                      : 7;
+	uint64_t rsv_b                        : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t rsv_c                        : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rsv_d                        : 6;
+	uint64_t rskp_len                     : 7;
+	uint64_t rsv_e                        : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t rsv_f                        : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npi_port32_instr_hdr_s    cn30xx;
+	struct cvmx_npi_port32_instr_hdr_s    cn31xx;
+	struct cvmx_npi_port32_instr_hdr_s    cn38xx;
+	struct cvmx_npi_port32_instr_hdr_s    cn38xxp2;
+	struct cvmx_npi_port32_instr_hdr_s    cn50xx;
+	struct cvmx_npi_port32_instr_hdr_s    cn58xx;
+	struct cvmx_npi_port32_instr_hdr_s    cn58xxp1;
+};
+typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t;
+
+/**
+ * cvmx_npi_port33_instr_hdr
+ *
+ * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header
+ *
+ * Contains bits [62:42] of the Instruction Header for port 33.
+ */
+union cvmx_npi_port33_instr_hdr
+{
+	uint64_t u64;
+	struct cvmx_npi_port33_instr_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t rsv_f                        : 5;  /**< Reserved */
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t rsv_e                        : 1;  /**< Reserved */
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t rsv_d                        : 6;  /**< Reserved */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t rsv_c                        : 5;  /**< Reserved */
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_b                        : 1;  /**< Reserved
+                                                         instruction header sent to IPD. */
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_a                        : 6;  /**< Reserved */
+#else
+	uint64_t rsv_a                        : 6;
+	uint64_t skp_len                      : 7;
+	uint64_t rsv_b                        : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t rsv_c                        : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rsv_d                        : 6;
+	uint64_t rskp_len                     : 7;
+	uint64_t rsv_e                        : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t rsv_f                        : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npi_port33_instr_hdr_s    cn31xx;
+	struct cvmx_npi_port33_instr_hdr_s    cn38xx;
+	struct cvmx_npi_port33_instr_hdr_s    cn38xxp2;
+	struct cvmx_npi_port33_instr_hdr_s    cn50xx;
+	struct cvmx_npi_port33_instr_hdr_s    cn58xx;
+	struct cvmx_npi_port33_instr_hdr_s    cn58xxp1;
+};
+typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t;
+
+/**
+ * cvmx_npi_port34_instr_hdr
+ *
+ * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header
+ *
+ * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
+ */
+union cvmx_npi_port34_instr_hdr
+{
+	uint64_t u64;
+	struct cvmx_npi_port34_instr_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t rsv_f                        : 5;  /**< Reserved */
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t rsv_e                        : 1;  /**< Reserved */
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t rsv_d                        : 6;  /**< Reserved */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t rsv_c                        : 5;  /**< Reserved */
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_b                        : 1;  /**< Reserved
+                                                         instruction header sent to IPD. */
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_a                        : 6;  /**< Reserved */
+#else
+	uint64_t rsv_a                        : 6;
+	uint64_t skp_len                      : 7;
+	uint64_t rsv_b                        : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t rsv_c                        : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rsv_d                        : 6;
+	uint64_t rskp_len                     : 7;
+	uint64_t rsv_e                        : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t rsv_f                        : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npi_port34_instr_hdr_s    cn38xx;
+	struct cvmx_npi_port34_instr_hdr_s    cn38xxp2;
+	struct cvmx_npi_port34_instr_hdr_s    cn58xx;
+	struct cvmx_npi_port34_instr_hdr_s    cn58xxp1;
+};
+typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t;
+
+/**
+ * cvmx_npi_port35_instr_hdr
+ *
+ * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header
+ *
+ * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
+ */
+union cvmx_npi_port35_instr_hdr
+{
+	uint64_t u64;
+	struct cvmx_npi_port35_instr_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t rsv_f                        : 5;  /**< Reserved */
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t rsv_e                        : 1;  /**< Reserved */
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t rsv_d                        : 6;  /**< Reserved */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t rsv_c                        : 5;  /**< Reserved */
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_b                        : 1;  /**< Reserved
+                                                         instruction header sent to IPD. */
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t rsv_a                        : 6;  /**< Reserved */
+#else
+	uint64_t rsv_a                        : 6;
+	uint64_t skp_len                      : 7;
+	uint64_t rsv_b                        : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t rsv_c                        : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rsv_d                        : 6;
+	uint64_t rskp_len                     : 7;
+	uint64_t rsv_e                        : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t rsv_f                        : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_npi_port35_instr_hdr_s    cn38xx;
+	struct cvmx_npi_port35_instr_hdr_s    cn38xxp2;
+	struct cvmx_npi_port35_instr_hdr_s    cn58xx;
+	struct cvmx_npi_port35_instr_hdr_s    cn58xxp1;
+};
+typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t;
+
+/**
+ * cvmx_npi_port_bp_control
+ *
+ * NPI_PORT_BP_CONTROL = Port Backpressure Control
+ *
+ * Enables Port Level Backpressure
+ */
+union cvmx_npi_port_bp_control
+{
+	uint64_t u64;
+	struct cvmx_npi_port_bp_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t bp_on                        : 4;  /**< Port 35-32 port level backpressure applied. */
+	uint64_t enb                          : 4;  /**< Enables port level backpressure from the IPD. */
+#else
+	uint64_t enb                          : 4;
+	uint64_t bp_on                        : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_npi_port_bp_control_s     cn30xx;
+	struct cvmx_npi_port_bp_control_s     cn31xx;
+	struct cvmx_npi_port_bp_control_s     cn38xx;
+	struct cvmx_npi_port_bp_control_s     cn38xxp2;
+	struct cvmx_npi_port_bp_control_s     cn50xx;
+	struct cvmx_npi_port_bp_control_s     cn58xx;
+	struct cvmx_npi_port_bp_control_s     cn58xxp1;
+};
+typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t;
+
+/**
+ * cvmx_npi_rsl_int_blocks
+ *
+ * RSL_INT_BLOCKS = RSL Interrupt Blocks Register
+ *
+ * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
+ * that presently has an interrupt pending. The Field Description below supplies the name of the
+ * register that software should read to find out why that intterupt bit is set.
+ */
+union cvmx_npi_rsl_int_blocks
+{
+	uint64_t u64;
+	struct cvmx_npi_rsl_int_blocks_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
+	uint64_t reserved_28_29               : 2;
+	uint64_t rint_27                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_26                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_25                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_24                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t asx1                         : 1;  /**< ASX1_INT_REG */
+	uint64_t asx0                         : 1;  /**< ASX0_INT_REG */
+	uint64_t rint_21                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t pip                          : 1;  /**< PIP_INT_REG. */
+	uint64_t spx1                         : 1;  /**< SPX1_INT_REG & STX1_INT_REG */
+	uint64_t spx0                         : 1;  /**< SPX0_INT_REG & STX0_INT_REG */
+	uint64_t lmc                          : 1;  /**< LMC_MEM_CFG0 */
+	uint64_t l2c                          : 1;  /**< L2T_ERR & L2D_ERR */
+	uint64_t rint_15                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t reserved_13_14               : 2;
+	uint64_t pow                          : 1;  /**< POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD_INT_SUM */
+	uint64_t rint_8                       : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t zip                          : 1;  /**< ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA_ERR */
+	uint64_t fpa                          : 1;  /**< FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY_INT_SUM */
+	uint64_t npi                          : 1;  /**< NPI_INT_SUM */
+	uint64_t gmx1                         : 1;  /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t npi                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rint_8                       : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_14               : 2;
+	uint64_t rint_15                      : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc                          : 1;
+	uint64_t spx0                         : 1;
+	uint64_t spx1                         : 1;
+	uint64_t pip                          : 1;
+	uint64_t rint_21                      : 1;
+	uint64_t asx0                         : 1;
+	uint64_t asx1                         : 1;
+	uint64_t rint_24                      : 1;
+	uint64_t rint_25                      : 1;
+	uint64_t rint_26                      : 1;
+	uint64_t rint_27                      : 1;
+	uint64_t reserved_28_29               : 2;
+	uint64_t iob                          : 1;
+	uint64_t rint_31                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npi_rsl_int_blocks_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
+	uint64_t rint_29                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_28                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_27                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_26                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_25                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_24                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t asx1                         : 1;  /**< ASX1_INT_REG */
+	uint64_t asx0                         : 1;  /**< ASX0_INT_REG */
+	uint64_t rint_21                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t pip                          : 1;  /**< PIP_INT_REG. */
+	uint64_t spx1                         : 1;  /**< SPX1_INT_REG & STX1_INT_REG */
+	uint64_t spx0                         : 1;  /**< SPX0_INT_REG & STX0_INT_REG */
+	uint64_t lmc                          : 1;  /**< LMC_MEM_CFG0 */
+	uint64_t l2c                          : 1;  /**< L2T_ERR & L2D_ERR */
+	uint64_t rint_15                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_14                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t usb                          : 1;  /**< USBN_INT_SUM */
+	uint64_t pow                          : 1;  /**< POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD_INT_SUM */
+	uint64_t rint_8                       : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t zip                          : 1;  /**< ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA_ERR */
+	uint64_t fpa                          : 1;  /**< FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t npi                          : 1;  /**< NPI_INT_SUM */
+	uint64_t gmx1                         : 1;  /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t npi                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rint_8                       : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rint_14                      : 1;
+	uint64_t rint_15                      : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc                          : 1;
+	uint64_t spx0                         : 1;
+	uint64_t spx1                         : 1;
+	uint64_t pip                          : 1;
+	uint64_t rint_21                      : 1;
+	uint64_t asx0                         : 1;
+	uint64_t asx1                         : 1;
+	uint64_t rint_24                      : 1;
+	uint64_t rint_25                      : 1;
+	uint64_t rint_26                      : 1;
+	uint64_t rint_27                      : 1;
+	uint64_t rint_28                      : 1;
+	uint64_t rint_29                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t rint_31                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn30xx;
+	struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
+	struct cvmx_npi_rsl_int_blocks_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rint_31                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
+	uint64_t rint_29                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_28                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_27                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_26                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_25                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_24                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t asx1                         : 1;  /**< ASX1_INT_REG */
+	uint64_t asx0                         : 1;  /**< ASX0_INT_REG */
+	uint64_t rint_21                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t pip                          : 1;  /**< PIP_INT_REG. */
+	uint64_t spx1                         : 1;  /**< SPX1_INT_REG & STX1_INT_REG */
+	uint64_t spx0                         : 1;  /**< SPX0_INT_REG & STX0_INT_REG */
+	uint64_t lmc                          : 1;  /**< LMC_MEM_CFG0 */
+	uint64_t l2c                          : 1;  /**< L2T_ERR & L2D_ERR */
+	uint64_t rint_15                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_14                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t rint_13                      : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t pow                          : 1;  /**< POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD_INT_SUM */
+	uint64_t rint_8                       : 1;  /**< Set '1' when RSL bLock has an interrupt. */
+	uint64_t zip                          : 1;  /**< ZIP_ERROR */
+	uint64_t dfa                          : 1;  /**< DFA_ERR */
+	uint64_t fpa                          : 1;  /**< FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< KEY_INT_SUM */
+	uint64_t npi                          : 1;  /**< NPI_INT_SUM */
+	uint64_t gmx1                         : 1;  /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+	uint64_t gmx0                         : 1;  /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t npi                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rint_8                       : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t rint_13                      : 1;
+	uint64_t rint_14                      : 1;
+	uint64_t rint_15                      : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc                          : 1;
+	uint64_t spx0                         : 1;
+	uint64_t spx1                         : 1;
+	uint64_t pip                          : 1;
+	uint64_t rint_21                      : 1;
+	uint64_t asx0                         : 1;
+	uint64_t asx1                         : 1;
+	uint64_t rint_24                      : 1;
+	uint64_t rint_25                      : 1;
+	uint64_t rint_26                      : 1;
+	uint64_t rint_27                      : 1;
+	uint64_t rint_28                      : 1;
+	uint64_t rint_29                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t rint_31                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
+	struct cvmx_npi_rsl_int_blocks_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t iob                          : 1;  /**< IOB_INT_SUM */
+	uint64_t lmc1                         : 1;  /**< Always reads as zero */
+	uint64_t agl                          : 1;  /**< Always reads as zero */
+	uint64_t reserved_24_27               : 4;
+	uint64_t asx1                         : 1;  /**< Always reads as zero */
+	uint64_t asx0                         : 1;  /**< ASX0_INT_REG */
+	uint64_t reserved_21_21               : 1;
+	uint64_t pip                          : 1;  /**< PIP_INT_REG. */
+	uint64_t spx1                         : 1;  /**< Always reads as zero */
+	uint64_t spx0                         : 1;  /**< Always reads as zero */
+	uint64_t lmc                          : 1;  /**< LMC_MEM_CFG0 */
+	uint64_t l2c                          : 1;  /**< L2T_ERR & L2D_ERR */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rad                          : 1;  /**< Always reads as zero */
+	uint64_t usb                          : 1;  /**< USBN_INT_SUM */
+	uint64_t pow                          : 1;  /**< POW_ECC_ERR */
+	uint64_t tim                          : 1;  /**< TIM_REG_ERROR */
+	uint64_t pko                          : 1;  /**< PKO_REG_ERROR */
+	uint64_t ipd                          : 1;  /**< IPD_INT_SUM */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t zip                          : 1;  /**< Always reads as zero */
+	uint64_t dfa                          : 1;  /**< Always reads as zero */
+	uint64_t fpa                          : 1;  /**< FPA_INT_SUM */
+	uint64_t key                          : 1;  /**< Always reads as zero */
+	uint64_t npi                          : 1;  /**< NPI_INT_SUM */
+	uint64_t gmx1                         : 1;  /**< Always reads as zero */
+	uint64_t gmx0                         : 1;  /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+	uint64_t mio                          : 1;  /**< MIO_BOOT_ERR */
+#else
+	uint64_t mio                          : 1;
+	uint64_t gmx0                         : 1;
+	uint64_t gmx1                         : 1;
+	uint64_t npi                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t tim                          : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb                          : 1;
+	uint64_t rad                          : 1;
+	uint64_t reserved_15_15               : 1;
+	uint64_t l2c                          : 1;
+	uint64_t lmc                          : 1;
+	uint64_t spx0                         : 1;
+	uint64_t spx1                         : 1;
+	uint64_t pip                          : 1;
+	uint64_t reserved_21_21               : 1;
+	uint64_t asx0                         : 1;
+	uint64_t asx1                         : 1;
+	uint64_t reserved_24_27               : 4;
+	uint64_t agl                          : 1;
+	uint64_t lmc1                         : 1;
+	uint64_t iob                          : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn50xx;
+	struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
+	struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
+};
+typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t;
+
+/**
+ * cvmx_npi_size_input#
+ *
+ * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register
+ *
+ * The size (in instructions) of Instruction Queue-0.
+ */
+union cvmx_npi_size_inputx
+{
+	uint64_t u64;
+	struct cvmx_npi_size_inputx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t size                         : 32; /**< The size of the Instruction Queue used by Octane.
+                                                         The value [SIZE] is in Instructions.
+                                                         A value of 0 in this field is illegal. */
+#else
+	uint64_t size                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npi_size_inputx_s         cn30xx;
+	struct cvmx_npi_size_inputx_s         cn31xx;
+	struct cvmx_npi_size_inputx_s         cn38xx;
+	struct cvmx_npi_size_inputx_s         cn38xxp2;
+	struct cvmx_npi_size_inputx_s         cn50xx;
+	struct cvmx_npi_size_inputx_s         cn58xx;
+	struct cvmx_npi_size_inputx_s         cn58xxp1;
+};
+typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t;
+
+/**
+ * cvmx_npi_win_read_to
+ *
+ * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register
+ *
+ * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
+ */
+union cvmx_npi_win_read_to
+{
+	uint64_t u64;
+	struct cvmx_npi_win_read_to_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t time                         : 32; /**< Time to wait in core clocks. A value of 0 will
+                                                         cause no timeouts. */
+#else
+	uint64_t time                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_npi_win_read_to_s         cn30xx;
+	struct cvmx_npi_win_read_to_s         cn31xx;
+	struct cvmx_npi_win_read_to_s         cn38xx;
+	struct cvmx_npi_win_read_to_s         cn38xxp2;
+	struct cvmx_npi_win_read_to_s         cn50xx;
+	struct cvmx_npi_win_read_to_s         cn58xx;
+	struct cvmx_npi_win_read_to_s         cn58xxp1;
+};
+typedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-npi.h b/sys/contrib/octeon-sdk/cvmx-npi.h
index dc02006..5c90717 100644
--- a/sys/contrib/octeon-sdk/cvmx-npi.h
+++ b/sys/contrib/octeon-sdk/cvmx-npi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * PCI / PCIe packet engine related structures.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_NPI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-packet.h b/sys/contrib/octeon-sdk/cvmx-packet.h
index f5c4f8c8..8dbf554 100644
--- a/sys/contrib/octeon-sdk/cvmx-packet.h
+++ b/sys/contrib/octeon-sdk/cvmx-packet.h
@@ -1,44 +1,41 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
 
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
 
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
 
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
 
 
 /**
@@ -46,8 +43,7 @@
  *
  * Packet buffer defines.
  *
- * <hr>$Revision: 41586 $<hr>
- *
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -61,8 +57,7 @@ extern "C" {
 /**
  * This structure defines a buffer pointer on Octeon
  */
-typedef union
-{
+union cvmx_buf_ptr {
     void*           ptr;
     uint64_t        u64;
     struct
@@ -74,7 +69,9 @@ typedef union
         uint64_t    size :16; /**< The size of the segment pointed to by addr (in bytes) */
         uint64_t    addr :40; /**< Pointer to the first byte of the data, NOT buffer */
     } s;
-} cvmx_buf_ptr_t;
+};
+
+typedef union cvmx_buf_ptr cvmx_buf_ptr_t;
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-pci-defs.h b/sys/contrib/octeon-sdk/cvmx-pci-defs.h
new file mode 100644
index 0000000..df38d8d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pci-defs.h
@@ -0,0 +1,4714 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pci-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pci.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCI_TYPEDEFS_H__
+#define __CVMX_PCI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000100ull + ((offset) & 31) * 4;
+}
+#else
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+		cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n");
+	return 0x00000000000001C0ull;
+}
+#else
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_PCI_CFG00_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n");
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_PCI_CFG01_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n");
+	return 0x0000000000000004ull;
+}
+#else
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_PCI_CFG02_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n");
+	return 0x0000000000000008ull;
+}
+#else
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_PCI_CFG03_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n");
+	return 0x000000000000000Cull;
+}
+#else
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_PCI_CFG04_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n");
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_PCI_CFG05_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n");
+	return 0x0000000000000014ull;
+}
+#else
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_PCI_CFG06_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n");
+	return 0x0000000000000018ull;
+}
+#else
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_PCI_CFG07_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n");
+	return 0x000000000000001Cull;
+}
+#else
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_PCI_CFG08_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n");
+	return 0x0000000000000020ull;
+}
+#else
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_PCI_CFG09_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n");
+	return 0x0000000000000024ull;
+}
+#else
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_PCI_CFG10_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n");
+	return 0x0000000000000028ull;
+}
+#else
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_PCI_CFG11_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n");
+	return 0x000000000000002Cull;
+}
+#else
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_PCI_CFG12_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n");
+	return 0x0000000000000030ull;
+}
+#else
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_PCI_CFG13_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n");
+	return 0x0000000000000034ull;
+}
+#else
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_PCI_CFG15_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n");
+	return 0x000000000000003Cull;
+}
+#else
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_PCI_CFG16_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n");
+	return 0x0000000000000040ull;
+}
+#else
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_PCI_CFG17_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n");
+	return 0x0000000000000044ull;
+}
+#else
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_PCI_CFG18_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n");
+	return 0x0000000000000048ull;
+}
+#else
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_PCI_CFG19_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n");
+	return 0x000000000000004Cull;
+}
+#else
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_PCI_CFG20_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n");
+	return 0x0000000000000050ull;
+}
+#else
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_PCI_CFG21_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n");
+	return 0x0000000000000054ull;
+}
+#else
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_PCI_CFG22_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n");
+	return 0x0000000000000058ull;
+}
+#else
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_PCI_CFG56_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n");
+	return 0x00000000000000E0ull;
+}
+#else
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_PCI_CFG57_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n");
+	return 0x00000000000000E4ull;
+}
+#else
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_PCI_CFG58_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n");
+	return 0x00000000000000E8ull;
+}
+#else
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_PCI_CFG59_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n");
+	return 0x00000000000000ECull;
+}
+#else
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_PCI_CFG60_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n");
+	return 0x00000000000000F0ull;
+}
+#else
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_PCI_CFG61_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n");
+	return 0x00000000000000F4ull;
+}
+#else
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_PCI_CFG62_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n");
+	return 0x00000000000000F8ull;
+}
+#else
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_PCI_CFG63_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n");
+	return 0x00000000000000FCull;
+}
+#else
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n");
+	return 0x00000000000001B8ull;
+}
+#else
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n");
+	return 0x000000000000018Cull;
+}
+#else
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000080ull + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#endif
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000000A0ull + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#endif
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000000A4ull + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#endif
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000000B0ull + ((offset) & 1) * 4;
+}
+#else
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#endif
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000084ull + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n");
+	return 0x0000000000000038ull;
+}
+#else
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n");
+	return 0x00000000000001A0ull;
+}
+#else
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n");
+	return 0x0000000000000030ull;
+}
+#else
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n");
+	return 0x0000000000000198ull;
+}
+#else
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n");
+	return 0x00000000000000F0ull;
+}
+#else
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#endif
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000040ull + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#endif
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000048ull + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#endif
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset);
+	return 0x000000000000004Cull + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#endif
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000044ull + ((offset) & 3) * 16;
+}
+#else
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n");
+	return 0x0000000000000180ull;
+}
+#else
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n");
+	return 0x0000000000000184ull;
+}
+#else
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n");
+	return 0x0000000000000188ull;
+}
+#else
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC()
+static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000000B0ull);
+}
+#else
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n");
+	return 0x00000000000001A8ull;
+}
+#else
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n");
+	return 0x00000000000001B0ull;
+}
+#else
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n");
+	return 0x0000000000000008ull;
+}
+#else
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n");
+	return 0x0000000000000020ull;
+}
+#else
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n");
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n");
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n");
+	return 0x0000000000000018ull;
+}
+#else
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
+#endif
+
+/**
+ * cvmx_pci_bar1_index#
+ *
+ * PCI_BAR1_INDEXX = PCI IndexX Register
+ *
+ * Contains address index and control bits for access to memory ranges of Bar-1,
+ * when PCI supplied address-bits [26:22] == X.
+ */
+union cvmx_pci_bar1_indexx
+{
+	uint32_t u32;
+	struct cvmx_pci_bar1_indexx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_18_31               : 14;
+	uint32_t addr_idx                     : 14; /**< Address bits [35:22] sent to L2C */
+	uint32_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
+	uint32_t end_swp                      : 2;  /**< Endian Swap Mode */
+	uint32_t addr_v                       : 1;  /**< Set '1' when the selected address range is valid. */
+#else
+	uint32_t addr_v                       : 1;
+	uint32_t end_swp                      : 2;
+	uint32_t ca                           : 1;
+	uint32_t addr_idx                     : 14;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_pci_bar1_indexx_s         cn30xx;
+	struct cvmx_pci_bar1_indexx_s         cn31xx;
+	struct cvmx_pci_bar1_indexx_s         cn38xx;
+	struct cvmx_pci_bar1_indexx_s         cn38xxp2;
+	struct cvmx_pci_bar1_indexx_s         cn50xx;
+	struct cvmx_pci_bar1_indexx_s         cn58xx;
+	struct cvmx_pci_bar1_indexx_s         cn58xxp1;
+};
+typedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t;
+
+/**
+ * cvmx_pci_bist_reg
+ *
+ * PCI_BIST_REG = PCI PNI BIST Status Register
+ *
+ * Contains the bist results for the PNI memories.
+ */
+union cvmx_pci_bist_reg
+{
+	uint64_t u64;
+	struct cvmx_pci_bist_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t rsp_bs                       : 1;  /**< Bist Status For b12_rsp_fifo_bist
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t dma0_bs                      : 1;  /**< Bist Status For dmao_count
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t cmd0_bs                      : 1;  /**< Bist Status For npi_cmd0_pni_am0
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t cmd_bs                       : 1;  /**< Bist Status For npi_cmd_pni_am1
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t csr2p_bs                     : 1;  /**< Bist Status For npi_csr_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t csrr_bs                      : 1;  /**< Bist Status For npi_csr_rsp_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t rsp2p_bs                     : 1;  /**< Bist Status For npi_rsp_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t csr2n_bs                     : 1;  /**< Bist Status For pni_csr_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t dat2n_bs                     : 1;  /**< Bist Status For pni_data_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+	uint64_t dbg2n_bs                     : 1;  /**< Bist Status For pni_dbg_data_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+#else
+	uint64_t dbg2n_bs                     : 1;
+	uint64_t dat2n_bs                     : 1;
+	uint64_t csr2n_bs                     : 1;
+	uint64_t rsp2p_bs                     : 1;
+	uint64_t csrr_bs                      : 1;
+	uint64_t csr2p_bs                     : 1;
+	uint64_t cmd_bs                       : 1;
+	uint64_t cmd0_bs                      : 1;
+	uint64_t dma0_bs                      : 1;
+	uint64_t rsp_bs                       : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_pci_bist_reg_s            cn50xx;
+};
+typedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t;
+
+/**
+ * cvmx_pci_cfg00
+ *
+ * Registers at address 0x1000 -> 0x17FF are PNI
+ * Start at 0x100 into range
+ * these are shifted by 2 to the left to make address
+ *                Registers at address 0x1800 -> 0x18FF are CFG
+ * these are shifted by 2 to the left to make address
+ *
+ *           PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device)
+ *
+ * This register contains the first 32-bits of the PCI config space registers
+ */
+union cvmx_pci_cfg00
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg00_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t devid                        : 16; /**< This is the device ID for OCTEON (90nm shhrink) */
+	uint32_t vendid                       : 16; /**< This is the Cavium's vendor ID */
+#else
+	uint32_t vendid                       : 16;
+	uint32_t devid                        : 16;
+#endif
+	} s;
+	struct cvmx_pci_cfg00_s               cn30xx;
+	struct cvmx_pci_cfg00_s               cn31xx;
+	struct cvmx_pci_cfg00_s               cn38xx;
+	struct cvmx_pci_cfg00_s               cn38xxp2;
+	struct cvmx_pci_cfg00_s               cn50xx;
+	struct cvmx_pci_cfg00_s               cn58xx;
+	struct cvmx_pci_cfg00_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t;
+
+/**
+ * cvmx_pci_cfg01
+ *
+ * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register)
+ *
+ */
+union cvmx_pci_cfg01
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg01_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dpe                          : 1;  /**< Detected Parity Error */
+	uint32_t sse                          : 1;  /**< Signaled System Error */
+	uint32_t rma                          : 1;  /**< Received Master Abort */
+	uint32_t rta                          : 1;  /**< Received Target Abort */
+	uint32_t sta                          : 1;  /**< Signaled Target Abort */
+	uint32_t devt                         : 2;  /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */
+	uint32_t mdpe                         : 1;  /**< Master Data Parity Error */
+	uint32_t fbb                          : 1;  /**< Fast Back-to-Back Transactions Capable
+                                                         Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */
+	uint32_t reserved_22_22               : 1;
+	uint32_t m66                          : 1;  /**< 66MHz Capable */
+	uint32_t cle                          : 1;  /**< Capabilities List Enable */
+	uint32_t i_stat                       : 1;  /**< When INTx# is asserted by OCTEON this bit will be set.
+                                                         When deasserted by OCTEON this bit will be cleared. */
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_dis                        : 1;  /**< When asserted '1' disables the generation of INTx#
+                                                         by OCTEON. When disabled '0' allows assertion of INTx#
+                                                         by OCTEON. */
+	uint32_t fbbe                         : 1;  /**< Fast Back to Back Transaction Enable */
+	uint32_t see                          : 1;  /**< System Error Enable */
+	uint32_t ads                          : 1;  /**< Address/Data Stepping
+                                                         NOTE: Octeon does NOT support address/data stepping. */
+	uint32_t pee                          : 1;  /**< PERR# Enable */
+	uint32_t vps                          : 1;  /**< VGA Palette Snooping */
+	uint32_t mwice                        : 1;  /**< Memory Write & Invalidate Command Enable */
+	uint32_t scse                         : 1;  /**< Special Cycle Snooping Enable */
+	uint32_t me                           : 1;  /**< Master Enable
+                                                         Must be set for OCTEON to master a PCI/PCI-X
+                                                         transaction. This should always be set any time
+                                                         that OCTEON is connected to a PCI/PCI-X bus. */
+	uint32_t msae                         : 1;  /**< Memory Space Access Enable
+                                                         Must be set to recieve a PCI/PCI-X memory space
+                                                         transaction. This must always be set any time that
+                                                         OCTEON is connected to a PCI/PCI-X bus. */
+	uint32_t isae                         : 1;  /**< I/O Space Access Enable
+                                                         NOTE: For OCTEON, this bit MUST NEVER be set
+                                                         (it is read-only and OCTEON does not respond to I/O
+                                                         Space accesses). */
+#else
+	uint32_t isae                         : 1;
+	uint32_t msae                         : 1;
+	uint32_t me                           : 1;
+	uint32_t scse                         : 1;
+	uint32_t mwice                        : 1;
+	uint32_t vps                          : 1;
+	uint32_t pee                          : 1;
+	uint32_t ads                          : 1;
+	uint32_t see                          : 1;
+	uint32_t fbbe                         : 1;
+	uint32_t i_dis                        : 1;
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_stat                       : 1;
+	uint32_t cle                          : 1;
+	uint32_t m66                          : 1;
+	uint32_t reserved_22_22               : 1;
+	uint32_t fbb                          : 1;
+	uint32_t mdpe                         : 1;
+	uint32_t devt                         : 2;
+	uint32_t sta                          : 1;
+	uint32_t rta                          : 1;
+	uint32_t rma                          : 1;
+	uint32_t sse                          : 1;
+	uint32_t dpe                          : 1;
+#endif
+	} s;
+	struct cvmx_pci_cfg01_s               cn30xx;
+	struct cvmx_pci_cfg01_s               cn31xx;
+	struct cvmx_pci_cfg01_s               cn38xx;
+	struct cvmx_pci_cfg01_s               cn38xxp2;
+	struct cvmx_pci_cfg01_s               cn50xx;
+	struct cvmx_pci_cfg01_s               cn58xx;
+	struct cvmx_pci_cfg01_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t;
+
+/**
+ * cvmx_pci_cfg02
+ *
+ * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID)
+ *
+ */
+union cvmx_pci_cfg02
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg02_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t cc                           : 24; /**< Class Code (Processor/MIPS)
+                                                         (was 0x100000 in pass 1 and pass 2) */
+	uint32_t rid                          : 8;  /**< Revision ID
+                                                         (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */
+#else
+	uint32_t rid                          : 8;
+	uint32_t cc                           : 24;
+#endif
+	} s;
+	struct cvmx_pci_cfg02_s               cn30xx;
+	struct cvmx_pci_cfg02_s               cn31xx;
+	struct cvmx_pci_cfg02_s               cn38xx;
+	struct cvmx_pci_cfg02_s               cn38xxp2;
+	struct cvmx_pci_cfg02_s               cn50xx;
+	struct cvmx_pci_cfg02_s               cn58xx;
+	struct cvmx_pci_cfg02_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t;
+
+/**
+ * cvmx_pci_cfg03
+ *
+ * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size)
+ *
+ */
+union cvmx_pci_cfg03
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg03_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bcap                         : 1;  /**< BIST Capable */
+	uint32_t brb                          : 1;  /**< BIST Request/busy bit
+                                                         Note: OCTEON does not support PCI BIST, therefore
+                                                         this bit should remain zero. */
+	uint32_t reserved_28_29               : 2;
+	uint32_t bcod                         : 4;  /**< BIST Code */
+	uint32_t ht                           : 8;  /**< Header Type (Type 0) */
+	uint32_t lt                           : 8;  /**< Latency Timer
+                                                         (0=PCI)                 (0=PCI)
+                                                         (0x40=PCIX)             (0x40=PCIX) */
+	uint32_t cls                          : 8;  /**< Cache Line Size */
+#else
+	uint32_t cls                          : 8;
+	uint32_t lt                           : 8;
+	uint32_t ht                           : 8;
+	uint32_t bcod                         : 4;
+	uint32_t reserved_28_29               : 2;
+	uint32_t brb                          : 1;
+	uint32_t bcap                         : 1;
+#endif
+	} s;
+	struct cvmx_pci_cfg03_s               cn30xx;
+	struct cvmx_pci_cfg03_s               cn31xx;
+	struct cvmx_pci_cfg03_s               cn38xx;
+	struct cvmx_pci_cfg03_s               cn38xxp2;
+	struct cvmx_pci_cfg03_s               cn50xx;
+	struct cvmx_pci_cfg03_s               cn58xx;
+	struct cvmx_pci_cfg03_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t;
+
+/**
+ * cvmx_pci_cfg04
+ *
+ * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low)
+ *
+ * Description: BAR0: 4KB 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [11:4]:  RAZ (to imply 4KB space)
+ *       [31:12]: RW (User may define base address)
+ */
+union cvmx_pci_cfg04
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg04_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lbase                        : 20; /**< Base Address[31:12]
+                                                         Base Address[30:12] read as zero if
+                                                         PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */
+	uint32_t lbasez                       : 8;  /**< Base Address[11:4] (Read as Zero) */
+	uint32_t pf                           : 1;  /**< Prefetchable Space */
+	uint32_t typ                          : 2;  /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t lbasez                       : 8;
+	uint32_t lbase                        : 20;
+#endif
+	} s;
+	struct cvmx_pci_cfg04_s               cn30xx;
+	struct cvmx_pci_cfg04_s               cn31xx;
+	struct cvmx_pci_cfg04_s               cn38xx;
+	struct cvmx_pci_cfg04_s               cn38xxp2;
+	struct cvmx_pci_cfg04_s               cn50xx;
+	struct cvmx_pci_cfg04_s               cn58xx;
+	struct cvmx_pci_cfg04_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t;
+
+/**
+ * cvmx_pci_cfg05
+ *
+ * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High)
+ *
+ */
+union cvmx_pci_cfg05
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg05_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t hbase                        : 32; /**< Base Address[63:32] */
+#else
+	uint32_t hbase                        : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg05_s               cn30xx;
+	struct cvmx_pci_cfg05_s               cn31xx;
+	struct cvmx_pci_cfg05_s               cn38xx;
+	struct cvmx_pci_cfg05_s               cn38xxp2;
+	struct cvmx_pci_cfg05_s               cn50xx;
+	struct cvmx_pci_cfg05_s               cn58xx;
+	struct cvmx_pci_cfg05_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t;
+
+/**
+ * cvmx_pci_cfg06
+ *
+ * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low)
+ *
+ * Description: BAR1: 128MB 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [26:4]:  RAZ (to imply 128MB space)
+ *       [31:27]: RW (User may define base address)
+ */
+union cvmx_pci_cfg06
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg06_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lbase                        : 5;  /**< Base Address[31:27]
+                                                         In pass 3+:
+                                                           Base Address[29:27] read as zero if
+                                                            PCI_CTL_STATUS_2[BB1] is set
+                                                           Base Address[30] reads as zero if
+                                                            PCI_CTL_STATUS_2[BB1] is set and
+                                                            PCI_CTL_STATUS_2[BB1_SIZE] is set */
+	uint32_t lbasez                       : 23; /**< Base Address[26:4] (Read as Zero) */
+	uint32_t pf                           : 1;  /**< Prefetchable Space */
+	uint32_t typ                          : 2;  /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t lbasez                       : 23;
+	uint32_t lbase                        : 5;
+#endif
+	} s;
+	struct cvmx_pci_cfg06_s               cn30xx;
+	struct cvmx_pci_cfg06_s               cn31xx;
+	struct cvmx_pci_cfg06_s               cn38xx;
+	struct cvmx_pci_cfg06_s               cn38xxp2;
+	struct cvmx_pci_cfg06_s               cn50xx;
+	struct cvmx_pci_cfg06_s               cn58xx;
+	struct cvmx_pci_cfg06_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t;
+
+/**
+ * cvmx_pci_cfg07
+ *
+ * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High)
+ *
+ */
+union cvmx_pci_cfg07
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg07_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t hbase                        : 32; /**< Base Address[63:32] */
+#else
+	uint32_t hbase                        : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg07_s               cn30xx;
+	struct cvmx_pci_cfg07_s               cn31xx;
+	struct cvmx_pci_cfg07_s               cn38xx;
+	struct cvmx_pci_cfg07_s               cn38xxp2;
+	struct cvmx_pci_cfg07_s               cn50xx;
+	struct cvmx_pci_cfg07_s               cn58xx;
+	struct cvmx_pci_cfg07_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t;
+
+/**
+ * cvmx_pci_cfg08
+ *
+ * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low)
+ *
+ * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [31:4]:  RAZ
+ */
+union cvmx_pci_cfg08
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg08_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lbasez                       : 28; /**< Base Address[31:4] (Read as Zero) */
+	uint32_t pf                           : 1;  /**< Prefetchable Space */
+	uint32_t typ                          : 2;  /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t lbasez                       : 28;
+#endif
+	} s;
+	struct cvmx_pci_cfg08_s               cn30xx;
+	struct cvmx_pci_cfg08_s               cn31xx;
+	struct cvmx_pci_cfg08_s               cn38xx;
+	struct cvmx_pci_cfg08_s               cn38xxp2;
+	struct cvmx_pci_cfg08_s               cn50xx;
+	struct cvmx_pci_cfg08_s               cn58xx;
+	struct cvmx_pci_cfg08_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t;
+
+/**
+ * cvmx_pci_cfg09
+ *
+ * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High)
+ *
+ */
+union cvmx_pci_cfg09
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg09_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t hbase                        : 25; /**< Base Address[63:39] */
+	uint32_t hbasez                       : 7;  /**< Base Address[38:31]  (Read as Zero) */
+#else
+	uint32_t hbasez                       : 7;
+	uint32_t hbase                        : 25;
+#endif
+	} s;
+	struct cvmx_pci_cfg09_s               cn30xx;
+	struct cvmx_pci_cfg09_s               cn31xx;
+	struct cvmx_pci_cfg09_s               cn38xx;
+	struct cvmx_pci_cfg09_s               cn38xxp2;
+	struct cvmx_pci_cfg09_s               cn50xx;
+	struct cvmx_pci_cfg09_s               cn58xx;
+	struct cvmx_pci_cfg09_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t;
+
+/**
+ * cvmx_pci_cfg10
+ *
+ * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer)
+ *
+ */
+union cvmx_pci_cfg10
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg10_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t cisp                         : 32; /**< CardBus CIS Pointer (UNUSED) */
+#else
+	uint32_t cisp                         : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg10_s               cn30xx;
+	struct cvmx_pci_cfg10_s               cn31xx;
+	struct cvmx_pci_cfg10_s               cn38xx;
+	struct cvmx_pci_cfg10_s               cn38xxp2;
+	struct cvmx_pci_cfg10_s               cn50xx;
+	struct cvmx_pci_cfg10_s               cn58xx;
+	struct cvmx_pci_cfg10_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t;
+
+/**
+ * cvmx_pci_cfg11
+ *
+ * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register)
+ *
+ */
+union cvmx_pci_cfg11
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg11_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ssid                         : 16; /**< SubSystem ID */
+	uint32_t ssvid                        : 16; /**< Subsystem Vendor ID */
+#else
+	uint32_t ssvid                        : 16;
+	uint32_t ssid                         : 16;
+#endif
+	} s;
+	struct cvmx_pci_cfg11_s               cn30xx;
+	struct cvmx_pci_cfg11_s               cn31xx;
+	struct cvmx_pci_cfg11_s               cn38xx;
+	struct cvmx_pci_cfg11_s               cn38xxp2;
+	struct cvmx_pci_cfg11_s               cn50xx;
+	struct cvmx_pci_cfg11_s               cn58xx;
+	struct cvmx_pci_cfg11_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t;
+
+/**
+ * cvmx_pci_cfg12
+ *
+ * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register)
+ *
+ */
+union cvmx_pci_cfg12
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg12_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t erbar                        : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */
+	uint32_t erbarz                       : 5;  /**< Expansion ROM Base Base Address (Read as Zero) */
+	uint32_t reserved_1_10                : 10;
+	uint32_t erbar_en                     : 1;  /**< Expansion ROM Address Decode Enable */
+#else
+	uint32_t erbar_en                     : 1;
+	uint32_t reserved_1_10                : 10;
+	uint32_t erbarz                       : 5;
+	uint32_t erbar                        : 16;
+#endif
+	} s;
+	struct cvmx_pci_cfg12_s               cn30xx;
+	struct cvmx_pci_cfg12_s               cn31xx;
+	struct cvmx_pci_cfg12_s               cn38xx;
+	struct cvmx_pci_cfg12_s               cn38xxp2;
+	struct cvmx_pci_cfg12_s               cn50xx;
+	struct cvmx_pci_cfg12_s               cn58xx;
+	struct cvmx_pci_cfg12_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t;
+
+/**
+ * cvmx_pci_cfg13
+ *
+ * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register)
+ *
+ */
+union cvmx_pci_cfg13
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg13_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_8_31                : 24;
+	uint32_t cp                           : 8;  /**< Capabilities Pointer */
+#else
+	uint32_t cp                           : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_pci_cfg13_s               cn30xx;
+	struct cvmx_pci_cfg13_s               cn31xx;
+	struct cvmx_pci_cfg13_s               cn38xx;
+	struct cvmx_pci_cfg13_s               cn38xxp2;
+	struct cvmx_pci_cfg13_s               cn50xx;
+	struct cvmx_pci_cfg13_s               cn58xx;
+	struct cvmx_pci_cfg13_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t;
+
+/**
+ * cvmx_pci_cfg15
+ *
+ * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register)
+ *
+ */
+union cvmx_pci_cfg15
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg15_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ml                           : 8;  /**< Maximum Latency */
+	uint32_t mg                           : 8;  /**< Minimum Grant */
+	uint32_t inta                         : 8;  /**< Interrupt Pin (INTA#) */
+	uint32_t il                           : 8;  /**< Interrupt Line */
+#else
+	uint32_t il                           : 8;
+	uint32_t inta                         : 8;
+	uint32_t mg                           : 8;
+	uint32_t ml                           : 8;
+#endif
+	} s;
+	struct cvmx_pci_cfg15_s               cn30xx;
+	struct cvmx_pci_cfg15_s               cn31xx;
+	struct cvmx_pci_cfg15_s               cn38xx;
+	struct cvmx_pci_cfg15_s               cn38xxp2;
+	struct cvmx_pci_cfg15_s               cn50xx;
+	struct cvmx_pci_cfg15_s               cn58xx;
+	struct cvmx_pci_cfg15_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t;
+
+/**
+ * cvmx_pci_cfg16
+ *
+ * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register)
+ *
+ */
+union cvmx_pci_cfg16
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg16_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t trdnpr                       : 1;  /**< Target Read Delayed Transaction for I/O and
+                                                         non-prefetchable regions discarded. */
+	uint32_t trdard                       : 1;  /**< Target Read Delayed Transaction for all regions
+                                                         discarded. */
+	uint32_t rdsati                       : 1;  /**< Target(I/O and Memory) Read Delayed/Split at
+                                                          timeout/immediately (default timeout).
+                                                         Note: OCTEON requires that this bit MBZ(must be zero). */
+	uint32_t trdrs                        : 1;  /**< Target(I/O and Memory) Read Delayed/Split or Retry
+                                                         select (of the application interface is not ready)
+                                                          0 = Delayed Split Transaction
+                                                          1 = Retry Transaction (always Immediate Retry, no
+                                                              AT_REQ to application). */
+	uint32_t trtae                        : 1;  /**< Target(I/O and Memory) Read Target Abort Enable
+                                                         (if application interface is not ready at the
+                                                         latency timeout).
+                                                         Note: OCTEON as target will never target-abort,
+                                                         therefore this bit should never be set. */
+	uint32_t twsei                        : 1;  /**< Target(I/O) Write Split Enable (at timeout /
+                                                         immediately; default timeout) */
+	uint32_t twsen                        : 1;  /**< T(I/O) write split Enable (if the application
+                                                         interface is not ready) */
+	uint32_t twtae                        : 1;  /**< Target(I/O and Memory) Write Target Abort Enable
+                                                         (if the application interface is not ready at the
+                                                         start of the cycle).
+                                                         Note: OCTEON as target will never target-abort,
+                                                         therefore this bit should never be set. */
+	uint32_t tmae                         : 1;  /**< Target(Read/Write) Master Abort Enable; check
+                                                         at the start of each transaction.
+                                                         Note: This bit can be used to force a Master
+                                                         Abort when OCTEON is acting as the intended target
+                                                         device. */
+	uint32_t tslte                        : 3;  /**< Target Subsequent(2nd-last) Latency Timeout Enable
+                                                         Valid range: [1..7] and 0=8. */
+	uint32_t tilt                         : 4;  /**< Target Initial(1st data) Latency Timeout in PCI
+                                                         ModeValid range: [8..15] and 0=16. */
+	uint32_t pbe                          : 12; /**< Programmable Boundary Enable to disconnect/prefetch
+                                                         for target burst read cycles to prefetchable
+                                                         region in PCI. A value of 1 indicates end of
+                                                         boundary (64 KB down to 16 Bytes). */
+	uint32_t dppmr                        : 1;  /**< Disconnect/Prefetch to prefetchable memory
+                                                         regions Enable. Prefetchable memory regions
+                                                         are always disconnected on a region boundary.
+                                                         Non-prefetchable regions for PCI are always
+                                                         disconnected on the first transfer.
+                                                         Note: OCTEON as target will never target-disconnect,
+                                                         therefore this bit should never be set. */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t tswc                         : 1;  /**< Target Split Write Control
+                                                         0 = Blocks all requests except PMW
+                                                         1 = Blocks all requests including PMW until
+                                                             split completion occurs. */
+	uint32_t mltd                         : 1;  /**< Master Latency Timer Disable
+                                                         Note: For OCTEON, it is recommended that this bit
+                                                         be set(to disable the Master Latency timer). */
+#else
+	uint32_t mltd                         : 1;
+	uint32_t tswc                         : 1;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t dppmr                        : 1;
+	uint32_t pbe                          : 12;
+	uint32_t tilt                         : 4;
+	uint32_t tslte                        : 3;
+	uint32_t tmae                         : 1;
+	uint32_t twtae                        : 1;
+	uint32_t twsen                        : 1;
+	uint32_t twsei                        : 1;
+	uint32_t trtae                        : 1;
+	uint32_t trdrs                        : 1;
+	uint32_t rdsati                       : 1;
+	uint32_t trdard                       : 1;
+	uint32_t trdnpr                       : 1;
+#endif
+	} s;
+	struct cvmx_pci_cfg16_s               cn30xx;
+	struct cvmx_pci_cfg16_s               cn31xx;
+	struct cvmx_pci_cfg16_s               cn38xx;
+	struct cvmx_pci_cfg16_s               cn38xxp2;
+	struct cvmx_pci_cfg16_s               cn50xx;
+	struct cvmx_pci_cfg16_s               cn58xx;
+	struct cvmx_pci_cfg16_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t;
+
+/**
+ * cvmx_pci_cfg17
+ *
+ * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message
+ * Enable Register)
+ */
+union cvmx_pci_cfg17
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg17_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t tscme                        : 32; /**< Target Split Completion Message Enable
+                                                          [31:30]: 00
+                                                          [29]: Split Completion Error Indication
+                                                          [28]: 0
+                                                          [27:20]: Split Completion Message Index
+                                                          [19:0]: 0x00000
+                                                         For OCTEON, this register is intended for debug use
+                                                         only. (as such, it is recommended NOT to be written
+                                                         with anything other than ZEROES). */
+#else
+	uint32_t tscme                        : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg17_s               cn30xx;
+	struct cvmx_pci_cfg17_s               cn31xx;
+	struct cvmx_pci_cfg17_s               cn38xx;
+	struct cvmx_pci_cfg17_s               cn38xxp2;
+	struct cvmx_pci_cfg17_s               cn50xx;
+	struct cvmx_pci_cfg17_s               cn58xx;
+	struct cvmx_pci_cfg17_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t;
+
+/**
+ * cvmx_pci_cfg18
+ *
+ * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request
+ * Pending Sequences)
+ */
+union cvmx_pci_cfg18
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg18_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t tdsrps                       : 32; /**< Target Delayed/Split Request Pending Sequences
+                                                         The application uses this address to remove a
+                                                         pending split sequence from the target queue by
+                                                         clearing the appropriate bit. Example: Clearing [14]
+                                                         clears the pending sequence \#14. An application
+                                                         or configuration write to this address can clear this
+                                                         register.
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+	uint32_t tdsrps                       : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg18_s               cn30xx;
+	struct cvmx_pci_cfg18_s               cn31xx;
+	struct cvmx_pci_cfg18_s               cn38xx;
+	struct cvmx_pci_cfg18_s               cn38xxp2;
+	struct cvmx_pci_cfg18_s               cn50xx;
+	struct cvmx_pci_cfg18_s               cn58xx;
+	struct cvmx_pci_cfg18_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t;
+
+/**
+ * cvmx_pci_cfg19
+ *
+ * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register)
+ *
+ */
+union cvmx_pci_cfg19
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg19_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mrbcm                        : 1;  /**< Master Request (Memory Read) Byte Count/Byte
+                                                         Enable select.
+                                                           0 = Byte Enables valid. In PCI mode, a burst
+                                                               transaction cannot be performed using
+                                                               Memory Read command=4'h6.
+                                                           1 = DWORD Byte Count valid (default). In PCI
+                                                               Mode, the memory read byte enables are
+                                                               automatically generated by the core.
+                                                          NOTE:  For OCTEON, this bit must always be one
+                                                          for proper operation. */
+	uint32_t mrbci                        : 1;  /**< Master Request (I/O and CR cycles) byte count/byte
+                                                         enable select.
+                                                           0 = Byte Enables valid (default)
+                                                           1 = DWORD byte count valid
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation (in support of
+                                                          Type0/1 Cfg Space accesses which require byte
+                                                          enable generation directly from a read mask). */
+	uint32_t mdwe                         : 1;  /**< Master (Retry) Deferred Write Enable (allow
+                                                         read requests to pass).
+                                                          NOTE: Applicable to PCI Mode I/O and memory
+                                                          transactions only.
+                                                           0 = New read requests are NOT accepted until
+                                                               the current write cycle completes. [Reads
+                                                               cannot pass writes]
+                                                           1 = New read requests are accepted, even when
+                                                               there is a write cycle pending [Reads can
+                                                               pass writes].
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation. */
+	uint32_t mdre                         : 1;  /**< Master (Retry) Deferred Read Enable (Allows
+                                                         read/write requests to pass).
+                                                          NOTE: Applicable to PCI mode I/O and memory
+                                                          transactions only.
+                                                           0 = New read/write requests are NOT accepted
+                                                               until the current read cycle completes.
+                                                               [Read/write requests CANNOT pass reads]
+                                                           1 = New read/write requests are accepted, even
+                                                               when there is a read cycle pending.
+                                                               [Read/write requests CAN pass reads]
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation. */
+	uint32_t mdrimc                       : 1;  /**< Master I/O Deferred/Split Request Outstanding
+                                                         Maximum Count
+                                                           0 = MDRRMC[26:24]
+                                                           1 = 1 */
+	uint32_t mdrrmc                       : 3;  /**< Master Deferred Read Request Outstanding Max
+                                                         Count (PCI only).
+                                                          CR4C[26:24]  Max SAC cycles   MAX DAC cycles
+                                                           000              8                4
+                                                           001              1                0
+                                                           010              2                1
+                                                           011              3                1
+                                                           100              4                2
+                                                           101              5                2
+                                                           110              6                3
+                                                           111              7                3
+                                                          For example, if these bits are programmed to
+                                                          100, the core can support 2 DAC cycles, 4 SAC
+                                                          cycles or a combination of 1 DAC and 2 SAC cycles.
+                                                          NOTE: For the PCI-X maximum outstanding split
+                                                          transactions, refer to CRE0[22:20] */
+	uint32_t tmes                         : 8;  /**< Target/Master Error Sequence \# */
+	uint32_t teci                         : 1;  /**< Target Error Command Indication
+                                                         0 = Delayed/Split
+                                                         1 = Others */
+	uint32_t tmei                         : 1;  /**< Target/Master Error Indication
+                                                         0 = Target
+                                                         1 = Master */
+	uint32_t tmse                         : 1;  /**< Target/Master System Error. This bit is set
+                                                         whenever ATM_SERR_O is active. */
+	uint32_t tmdpes                       : 1;  /**< Target/Master Data PERR# error status. This
+                                                         bit is set whenever ATM_DATA_PERR_O is active. */
+	uint32_t tmapes                       : 1;  /**< Target/Master Address PERR# error status. This
+                                                         bit is set whenever ATM_ADDR_PERR_O is active. */
+	uint32_t reserved_9_10                : 2;
+	uint32_t tibcd                        : 1;  /**< Target Illegal I/O DWORD byte combinations detected. */
+	uint32_t tibde                        : 1;  /**< Target Illegal I/O DWORD byte detection enable */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t tidomc                       : 1;  /**< Target I/O Delayed/Split request outstanding
+                                                         maximum count.
+                                                          0 = TDOMC[4:0]
+                                                          1 = 1 */
+	uint32_t tdomc                        : 5;  /**< Target Delayed/Split request outstanding maximum
+                                                         count. [1..31] and 0=32.
+                                                         NOTE: If the user programs these bits beyond the
+                                                         Designed Maximum outstanding count, then the
+                                                         designed maximum table depth will be used instead.
+                                                         No additional Deferred/Split transactions will be
+                                                         accepted if this outstanding maximum count
+                                                         is reached. Furthermore, no additional
+                                                         deferred/split transactions will be accepted if
+                                                         the I/O delay/ I/O Split Request outstanding
+                                                         maximum is reached.
+                                                         NOTE: For OCTEON in PCI Mode, this field MUST BE
+                                                         programmed to 1. (OCTEON can only handle 1 delayed
+                                                         read at a time).
+                                                         For OCTEON in PCIX Mode, this field can range from
+                                                         1-4. (The designed maximum table depth is 4
+                                                         for PCIX mode splits). */
+#else
+	uint32_t tdomc                        : 5;
+	uint32_t tidomc                       : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t tibde                        : 1;
+	uint32_t tibcd                        : 1;
+	uint32_t reserved_9_10                : 2;
+	uint32_t tmapes                       : 1;
+	uint32_t tmdpes                       : 1;
+	uint32_t tmse                         : 1;
+	uint32_t tmei                         : 1;
+	uint32_t teci                         : 1;
+	uint32_t tmes                         : 8;
+	uint32_t mdrrmc                       : 3;
+	uint32_t mdrimc                       : 1;
+	uint32_t mdre                         : 1;
+	uint32_t mdwe                         : 1;
+	uint32_t mrbci                        : 1;
+	uint32_t mrbcm                        : 1;
+#endif
+	} s;
+	struct cvmx_pci_cfg19_s               cn30xx;
+	struct cvmx_pci_cfg19_s               cn31xx;
+	struct cvmx_pci_cfg19_s               cn38xx;
+	struct cvmx_pci_cfg19_s               cn38xxp2;
+	struct cvmx_pci_cfg19_s               cn50xx;
+	struct cvmx_pci_cfg19_s               cn58xx;
+	struct cvmx_pci_cfg19_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t;
+
+/**
+ * cvmx_pci_cfg20
+ *
+ * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending)
+ *
+ */
+union cvmx_pci_cfg20
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg20_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mdsp                         : 32; /**< Master Deferred/Split sequence Pending
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+	uint32_t mdsp                         : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg20_s               cn30xx;
+	struct cvmx_pci_cfg20_s               cn31xx;
+	struct cvmx_pci_cfg20_s               cn38xx;
+	struct cvmx_pci_cfg20_s               cn38xxp2;
+	struct cvmx_pci_cfg20_s               cn50xx;
+	struct cvmx_pci_cfg20_s               cn58xx;
+	struct cvmx_pci_cfg20_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t;
+
+/**
+ * cvmx_pci_cfg21
+ *
+ * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register)
+ *
+ */
+union cvmx_pci_cfg21
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg21_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t scmre                        : 32; /**< Master Split Completion message received with
+                                                         error message.
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+	uint32_t scmre                        : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg21_s               cn30xx;
+	struct cvmx_pci_cfg21_s               cn31xx;
+	struct cvmx_pci_cfg21_s               cn38xx;
+	struct cvmx_pci_cfg21_s               cn38xxp2;
+	struct cvmx_pci_cfg21_s               cn50xx;
+	struct cvmx_pci_cfg21_s               cn58xx;
+	struct cvmx_pci_cfg21_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t;
+
+/**
+ * cvmx_pci_cfg22
+ *
+ * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register)
+ *
+ */
+union cvmx_pci_cfg22
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg22_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mac                          : 7;  /**< Master Arbiter Control
+                                                         [31:26]: Used only in Fixed Priority mode
+                                                                  (when [25]=1)
+                                                         [31:30]: MSI Request
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [29:28]: Target Split Completion
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [27:26]: New Request; Deferred Read,Deferred Write
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [25]: Fixed/Round Robin Priority Selector
+                                                            0 = Round Robin
+                                                            1 = Fixed
+                                                         NOTE: When [25]=1(fixed priority), the three levels
+                                                         [31:26] MUST BE programmed to have mutually exclusive
+                                                         priority levels for proper operation. (Failure to do
+                                                         so may result in PCI hangs). */
+	uint32_t reserved_19_24               : 6;
+	uint32_t flush                        : 1;  /**< AM_DO_FLUSH_I control
+                                                         NOTE: This bit MUST BE ONE for proper OCTEON operation */
+	uint32_t mra                          : 1;  /**< Master Retry Aborted */
+	uint32_t mtta                         : 1;  /**< Master TRDY timeout aborted */
+	uint32_t mrv                          : 8;  /**< Master Retry Value [1..255] and 0=infinite */
+	uint32_t mttv                         : 8;  /**< Master TRDY timeout value [1..255] and 0=disabled
+                                                         NOTE: For OCTEON, this bit must always be zero
+                                                         for proper operation. (OCTEON does not support
+                                                         master TRDY timeout - target is expected to be
+                                                         well behaved). */
+#else
+	uint32_t mttv                         : 8;
+	uint32_t mrv                          : 8;
+	uint32_t mtta                         : 1;
+	uint32_t mra                          : 1;
+	uint32_t flush                        : 1;
+	uint32_t reserved_19_24               : 6;
+	uint32_t mac                          : 7;
+#endif
+	} s;
+	struct cvmx_pci_cfg22_s               cn30xx;
+	struct cvmx_pci_cfg22_s               cn31xx;
+	struct cvmx_pci_cfg22_s               cn38xx;
+	struct cvmx_pci_cfg22_s               cn38xxp2;
+	struct cvmx_pci_cfg22_s               cn50xx;
+	struct cvmx_pci_cfg22_s               cn58xx;
+	struct cvmx_pci_cfg22_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t;
+
+/**
+ * cvmx_pci_cfg56
+ *
+ * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register)
+ *
+ */
+union cvmx_pci_cfg56
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg56_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_23_31               : 9;
+	uint32_t most                         : 3;  /**< Maximum outstanding Split transactions
+                                                           Encoded Value    \#Max outstanding splits
+                                                               000                   1
+                                                               001                   2
+                                                               010                   3
+                                                               011                   4
+                                                               100                   8
+                                                               101                   8(clamped)
+                                                               110                   8(clamped)
+                                                               111                   8(clamped)
+                                                         NOTE: OCTEON only supports upto a MAXIMUM of 8
+                                                         outstanding master split transactions. */
+	uint32_t mmbc                         : 2;  /**< Maximum Memory Byte Count
+                                                                 [0=512B,1=1024B,2=2048B,3=4096B]
+                                                         NOTE: OCTEON does not support this field and has
+                                                         no effect on limiting the maximum memory byte count. */
+	uint32_t roe                          : 1;  /**< Relaxed Ordering Enable */
+	uint32_t dpere                        : 1;  /**< Data Parity Error Recovery Enable */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer */
+	uint32_t pxcid                        : 8;  /**< PCI-X Capability ID */
+#else
+	uint32_t pxcid                        : 8;
+	uint32_t ncp                          : 8;
+	uint32_t dpere                        : 1;
+	uint32_t roe                          : 1;
+	uint32_t mmbc                         : 2;
+	uint32_t most                         : 3;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_pci_cfg56_s               cn30xx;
+	struct cvmx_pci_cfg56_s               cn31xx;
+	struct cvmx_pci_cfg56_s               cn38xx;
+	struct cvmx_pci_cfg56_s               cn38xxp2;
+	struct cvmx_pci_cfg56_s               cn50xx;
+	struct cvmx_pci_cfg56_s               cn58xx;
+	struct cvmx_pci_cfg56_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t;
+
+/**
+ * cvmx_pci_cfg57
+ *
+ * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register)
+ *
+ */
+union cvmx_pci_cfg57
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg57_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t scemr                        : 1;  /**< Split Completion Error Message Received */
+	uint32_t mcrsd                        : 3;  /**< Maximum Cumulative Read Size designed */
+	uint32_t mostd                        : 3;  /**< Maximum Outstanding Split transaction designed */
+	uint32_t mmrbcd                       : 2;  /**< Maximum Memory Read byte count designed */
+	uint32_t dc                           : 1;  /**< Device Complexity
+                                                         0 = Simple Device
+                                                         1 = Bridge Device */
+	uint32_t usc                          : 1;  /**< Unexpected Split Completion */
+	uint32_t scd                          : 1;  /**< Split Completion Discarded */
+	uint32_t m133                         : 1;  /**< 133MHz Capable */
+	uint32_t w64                          : 1;  /**< Indicates a 32b(=0) or 64b(=1) device */
+	uint32_t bn                           : 8;  /**< Bus Number. Updated on all configuration write
+                                                         (0x11=PCI)             cycles. Its value is dependent upon the PCI/X
+                                                         (0xFF=PCIX)            mode. */
+	uint32_t dn                           : 5;  /**< Device Number. Updated on all configuration
+                                                         write cycles. */
+	uint32_t fn                           : 3;  /**< Function Number */
+#else
+	uint32_t fn                           : 3;
+	uint32_t dn                           : 5;
+	uint32_t bn                           : 8;
+	uint32_t w64                          : 1;
+	uint32_t m133                         : 1;
+	uint32_t scd                          : 1;
+	uint32_t usc                          : 1;
+	uint32_t dc                           : 1;
+	uint32_t mmrbcd                       : 2;
+	uint32_t mostd                        : 3;
+	uint32_t mcrsd                        : 3;
+	uint32_t scemr                        : 1;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pci_cfg57_s               cn30xx;
+	struct cvmx_pci_cfg57_s               cn31xx;
+	struct cvmx_pci_cfg57_s               cn38xx;
+	struct cvmx_pci_cfg57_s               cn38xxp2;
+	struct cvmx_pci_cfg57_s               cn50xx;
+	struct cvmx_pci_cfg57_s               cn58xx;
+	struct cvmx_pci_cfg57_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t;
+
+/**
+ * cvmx_pci_cfg58
+ *
+ * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register)
+ *
+ */
+union cvmx_pci_cfg58
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg58_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmes                         : 5;  /**< PME Support (D0 to D3cold) */
+	uint32_t d2s                          : 1;  /**< D2_Support */
+	uint32_t d1s                          : 1;  /**< D1_Support */
+	uint32_t auxc                         : 3;  /**< AUX_Current (0..375mA) */
+	uint32_t dsi                          : 1;  /**< Device Specific Initialization */
+	uint32_t reserved_20_20               : 1;
+	uint32_t pmec                         : 1;  /**< PME Clock */
+	uint32_t pcimiv                       : 3;  /**< Indicates the version of the PCI
+                                                         Management
+                                                          Interface Specification with which the core
+                                                          complies.
+                                                            010b = Complies with PCI Management Interface
+                                                            Specification Revision 1.1 */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer */
+	uint32_t pmcid                        : 8;  /**< Power Management Capability ID */
+#else
+	uint32_t pmcid                        : 8;
+	uint32_t ncp                          : 8;
+	uint32_t pcimiv                       : 3;
+	uint32_t pmec                         : 1;
+	uint32_t reserved_20_20               : 1;
+	uint32_t dsi                          : 1;
+	uint32_t auxc                         : 3;
+	uint32_t d1s                          : 1;
+	uint32_t d2s                          : 1;
+	uint32_t pmes                         : 5;
+#endif
+	} s;
+	struct cvmx_pci_cfg58_s               cn30xx;
+	struct cvmx_pci_cfg58_s               cn31xx;
+	struct cvmx_pci_cfg58_s               cn38xx;
+	struct cvmx_pci_cfg58_s               cn38xxp2;
+	struct cvmx_pci_cfg58_s               cn50xx;
+	struct cvmx_pci_cfg58_s               cn58xx;
+	struct cvmx_pci_cfg58_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t;
+
+/**
+ * cvmx_pci_cfg59
+ *
+ * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s))
+ *
+ */
+union cvmx_pci_cfg59
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg59_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmdia                        : 8;  /**< Power Management data input from application
+                                                         (PME_DATA) */
+	uint32_t bpccen                       : 1;  /**< BPCC_En (bus power/clock control) enable */
+	uint32_t bd3h                         : 1;  /**< B2_B3\#, B2/B3 Support for D3hot */
+	uint32_t reserved_16_21               : 6;
+	uint32_t pmess                        : 1;  /**< PME_Status sticky bit */
+	uint32_t pmedsia                      : 2;  /**< PME_Data_Scale input from application
+                                                         Device                  (PME_DATA_SCALE[1:0])
+                                                         Specific */
+	uint32_t pmds                         : 4;  /**< Power Management Data_select */
+	uint32_t pmeens                       : 1;  /**< PME_En sticky bit */
+	uint32_t reserved_2_7                 : 6;
+	uint32_t ps                           : 2;  /**< Power State (D0 to D3)
+                                                         The N2 DOES NOT support D1/D2 Power Management
+                                                         states, therefore writing to this register has
+                                                         no effect (please refer to the PCI Power
+                                                         Management
+                                                         Specification v1.1 for further details about
+                                                         it?s R/W nature. This is not a conventional
+                                                         R/W style register. */
+#else
+	uint32_t ps                           : 2;
+	uint32_t reserved_2_7                 : 6;
+	uint32_t pmeens                       : 1;
+	uint32_t pmds                         : 4;
+	uint32_t pmedsia                      : 2;
+	uint32_t pmess                        : 1;
+	uint32_t reserved_16_21               : 6;
+	uint32_t bd3h                         : 1;
+	uint32_t bpccen                       : 1;
+	uint32_t pmdia                        : 8;
+#endif
+	} s;
+	struct cvmx_pci_cfg59_s               cn30xx;
+	struct cvmx_pci_cfg59_s               cn31xx;
+	struct cvmx_pci_cfg59_s               cn38xx;
+	struct cvmx_pci_cfg59_s               cn38xxp2;
+	struct cvmx_pci_cfg59_s               cn50xx;
+	struct cvmx_pci_cfg59_s               cn58xx;
+	struct cvmx_pci_cfg59_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t;
+
+/**
+ * cvmx_pci_cfg60
+ *
+ * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register)
+ *
+ */
+union cvmx_pci_cfg60
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg60_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t m64                          : 1;  /**< 32/64 b message */
+	uint32_t mme                          : 3;  /**< Multiple Message Enable(1,2,4,8,16,32) */
+	uint32_t mmc                          : 3;  /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */
+	uint32_t msien                        : 1;  /**< MSI Enable */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer */
+	uint32_t msicid                       : 8;  /**< MSI Capability ID */
+#else
+	uint32_t msicid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t msien                        : 1;
+	uint32_t mmc                          : 3;
+	uint32_t mme                          : 3;
+	uint32_t m64                          : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pci_cfg60_s               cn30xx;
+	struct cvmx_pci_cfg60_s               cn31xx;
+	struct cvmx_pci_cfg60_s               cn38xx;
+	struct cvmx_pci_cfg60_s               cn38xxp2;
+	struct cvmx_pci_cfg60_s               cn50xx;
+	struct cvmx_pci_cfg60_s               cn58xx;
+	struct cvmx_pci_cfg60_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t;
+
+/**
+ * cvmx_pci_cfg61
+ *
+ * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register)
+ *
+ */
+union cvmx_pci_cfg61
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg61_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t msi31t2                      : 30; /**< App Specific    MSI Address [31:2] */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t msi31t2                      : 30;
+#endif
+	} s;
+	struct cvmx_pci_cfg61_s               cn30xx;
+	struct cvmx_pci_cfg61_s               cn31xx;
+	struct cvmx_pci_cfg61_s               cn38xx;
+	struct cvmx_pci_cfg61_s               cn38xxp2;
+	struct cvmx_pci_cfg61_s               cn50xx;
+	struct cvmx_pci_cfg61_s               cn58xx;
+	struct cvmx_pci_cfg61_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t;
+
+/**
+ * cvmx_pci_cfg62
+ *
+ * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register)
+ *
+ */
+union cvmx_pci_cfg62
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg62_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t msi                          : 32; /**< MSI Address [63:32] */
+#else
+	uint32_t msi                          : 32;
+#endif
+	} s;
+	struct cvmx_pci_cfg62_s               cn30xx;
+	struct cvmx_pci_cfg62_s               cn31xx;
+	struct cvmx_pci_cfg62_s               cn38xx;
+	struct cvmx_pci_cfg62_s               cn38xxp2;
+	struct cvmx_pci_cfg62_s               cn50xx;
+	struct cvmx_pci_cfg62_s               cn58xx;
+	struct cvmx_pci_cfg62_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t;
+
+/**
+ * cvmx_pci_cfg63
+ *
+ * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register)
+ *
+ */
+union cvmx_pci_cfg63
+{
+	uint32_t u32;
+	struct cvmx_pci_cfg63_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t msimd                        : 16; /**< MSI Message Data */
+#else
+	uint32_t msimd                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_pci_cfg63_s               cn30xx;
+	struct cvmx_pci_cfg63_s               cn31xx;
+	struct cvmx_pci_cfg63_s               cn38xx;
+	struct cvmx_pci_cfg63_s               cn38xxp2;
+	struct cvmx_pci_cfg63_s               cn50xx;
+	struct cvmx_pci_cfg63_s               cn58xx;
+	struct cvmx_pci_cfg63_s               cn58xxp1;
+};
+typedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t;
+
+/**
+ * cvmx_pci_cnt_reg
+ *
+ * PCI_CNT_REG = PCI Clock Count Register
+ *
+ * This register is provided to software as a means to determine PCI Bus Type/Speed.
+ */
+union cvmx_pci_cnt_reg
+{
+	uint64_t u64;
+	struct cvmx_pci_cnt_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t hm_pcix                      : 1;  /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX)
+                                                         This field represents what OCTEON(in Host mode)
+                                                         sampled as the 'intended' PCI Bus Type based on
+                                                         the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed
+                                                         encoding table). */
+	uint64_t hm_speed                     : 2;  /**< PCI Host Mode Sampled Bus Speed
+                                                          This field represents what OCTEON(in Host mode)
+                                                          sampled as the 'intended' PCI Bus Speed based on
+                                                          the PCI100, PCI_M66EN and PCI_PCIXCAP pins.
+                                                          NOTE: This DOES NOT reflect what the actual PCI
+                                                          Bus Type/Speed values are. They only indicate what
+                                                          OCTEON sampled as the 'intended' values.
+                                                          PCI Host Mode Sampled Bus Type/Speed Table:
+                                                            M66EN | PCIXCAP | PCI100  |  HM_PCIX | HM_SPEED[1:0]
+                                                         ---------+---------+---------+----------+-------------
+                                                              0   |    0    |    0    | 0=PCI    |  00=33 MHz
+                                                              0   |    0    |    1    | 0=PCI    |  00=33 MHz
+                                                              0   |    Z    |    0    | 0=PCI    |  01=66 MHz
+                                                              0   |    Z    |    1    | 0=PCI    |  01=66 MHz
+                                                              1   |    0    |    0    | 0=PCI    |  01=66 MHz
+                                                              1   |    0    |    1    | 0=PCI    |  01=66 MHz
+                                                              1   |    Z    |    0    | 0=PCI    |  01=66 MHz
+                                                              1   |    Z    |    1    | 0=PCI    |  01=66 MHz
+                                                              0   |    1    |    1    | 1=PCIX   |  10=100 MHz
+                                                              1   |    1    |    1    | 1=PCIX   |  10=100 MHz
+                                                              0   |    1    |    0    | 1=PCIX   |  11=133 MHz
+                                                              1   |    1    |    0    | 1=PCIX   |  11=133 MHz
+                                                          NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification
+                                                          for more details on board level hookup to achieve these
+                                                          values.
+                                                          NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR]
+                                                          to override the 'sampled' PCI Bus Type/Speed.
+                                                          NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine
+                                                          the exact PCI(X) Bus speed.
+                                                          Example: PCI_REF_CLKIN=133MHz
+                                                             PCI_HOST_MODE=1
+                                                             PCI_M66EN=0
+                                                             PCI_PCIXCAP=1
+                                                             PCI_PCI100=1
+                                                          For this example, OCTEON will generate
+                                                          PCI_CLK_OUT=100MHz and drive the proper PCI
+                                                          Initialization sequence (DEVSEL#=Deasserted,
+                                                          STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N
+                                                          deassertion.
+                                                          NOTE: The HM_SPEED field is only valid after
+                                                          PLL_REF_CLK is active and PLL_DCOK is asserted.
+                                                          (see HRM description for power-on/reset sequence).
+                                                          NOTE: PCI_REF_CLKIN input must be 133MHz (and is used
+                                                          to generate the PCI_CLK_OUT pin in Host Mode). */
+	uint64_t ap_pcix                      : 1;  /**< PCI(X) Bus Type (0:PCI/1:PCIX)
+                                                         At PCI_RST_N de-assertion, the PCI Initialization
+                                                         pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
+                                                         captured to provide information to software regarding
+                                                         the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */
+	uint64_t ap_speed                     : 2;  /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133)
+                                                                                    At PCI_RST_N de-assertion, the PCI Initialization
+                                                                                    pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
+                                                                                    captured to provide information to software regarding
+                                                                                    the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range.
+                                                                                    PCI-X Initialization Pattern(see PCIX Spec):
+                                                           PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode    MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz)
+                                                         -------------+----------+----------+-------+---------+----------+----------+------------------
+                                                            Deasserted Deasserted Deasserted PCI 33    --         30          0         33
+                                                                                             PCI 66    30         15         33         66
+                                                            Deasserted Deasserted Asserted   PCI-X     20         15         50         66
+                                                            Deasserted Asserted   Deasserted PCI-X     15         10         66        100
+                                                            Deasserted Asserted   Asserted   PCI-X     10         7.5       100        133
+                                                            Asserted   Deasserted Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Deasserted Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Asserted   Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Asserted   Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                                                    NOTE: The PCI Bus speed 'assumed' from the initialization
+                                                                                    pattern is really intended for an operational range.
+                                                                                    For example: If PINIT=100, this indicates PCI-X in the
+                                                                                    100-133MHz range. The PCI_CNT field can be used to further
+                                                                                    determine a more exacting PCI Bus frequency value if
+                                                                                    required. */
+	uint64_t pcicnt                       : 32; /**< Free Running PCI Clock counter.
+                                                         At PCI Reset, the PCICNT=0, and is auto-incremented
+                                                         on every PCI clock and will auto-wrap back to zero
+                                                         when saturated.
+                                                         NOTE: Writes override the auto-increment to allow
+                                                         software to preload any initial value.
+                                                         The PCICNT field is provided to software as a means
+                                                         to determine the PCI Bus Speed.
+                                                         Assuming software has knowledge of the core frequency
+                                                         (eclk), this register can be written with a value X,
+                                                         wait 'n' core clocks(eclk) and then read later(Y) to
+                                                         determine \#PCI clocks(Y-X) have elapsed within 'n' core
+                                                         clocks to determine the PCI input Clock frequency. */
+#else
+	uint64_t pcicnt                       : 32;
+	uint64_t ap_speed                     : 2;
+	uint64_t ap_pcix                      : 1;
+	uint64_t hm_speed                     : 2;
+	uint64_t hm_pcix                      : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_pci_cnt_reg_s             cn50xx;
+	struct cvmx_pci_cnt_reg_s             cn58xx;
+	struct cvmx_pci_cnt_reg_s             cn58xxp1;
+};
+typedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t;
+
+/**
+ * cvmx_pci_ctl_status_2
+ *
+ * PCI_CTL_STATUS_2 = PCI Control Status 2 Register
+ *
+ * Control status register accessable from both PCI and NCB.
+ */
+union cvmx_pci_ctl_status_2
+{
+	uint32_t u32;
+	struct cvmx_pci_ctl_status_2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_29_31               : 3;
+	uint32_t bb1_hole                     : 3;  /**< Big BAR 1 Hole
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
+                                                         an encoded size of the upper BAR1 region which
+                                                         OCTEON will mask out (ie: not respond to).
+                                                         (see definition of BB1_HOLE and BB1_SIZ encodings
+                                                         in the PCI_CTL_STATUS_2[BB1] definition below). */
+	uint32_t bb1_siz                      : 1;  /**< Big BAR 1 Size
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
+                                                         the programmable SIZE of BAR 1.
+                                                           - 0: 1GB / 1: 2GB */
+	uint32_t bb_ca                        : 1;  /**< Set to '1' for Big Bar Mode to do STT/LDT L2C
+                                                         operations.
+                                                         NOT IN PASS 1 NOR PASS 2 */
+	uint32_t bb_es                        : 2;  /**< Big Bar Node Endian Swap Mode
+                                                           - 0: No Swizzle
+                                                           - 1: Byte Swizzle (per-QW)
+                                                           - 2: Byte Swizzle (per-LW)
+                                                           - 3: LongWord Swizzle
+                                                         NOT IN PASS 1 NOR PASS 2 */
+	uint32_t bb1                          : 1;  /**< Big Bar 1 Enable
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1] is set, the following differences
+                                                         occur:
+                                                         - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather
+                                                           than the default 128MB.
+                                                         - The following table indicates the effective size of
+                                                           BAR1 when BB1 is set:
+                                                             BB1_SIZ   BB1_HOLE  Effective size    Comment
+                                                           +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+                                                                0          0         1024 MB      Normal 1GB BAR
+                                                                0          1         1008 MB      1 GB, 16 MB hole
+                                                                0          2          992 MB      1 GB, 32 MB hole
+                                                                0          3          960 MB      1 GB, 64 MB hole
+                                                                0          4          896 MB      1 GB,128 MB hole
+                                                                0          5          768 MB      1 GB,256 MB hole
+                                                                0          6          512 MB      1 GB,512 MB hole
+                                                                0          7         Illegal
+                                                                1          0         2048 MB      Normal 2GB BAR
+                                                                1          1         2032 MB      2 GB, 16 MB hole
+                                                                1          2         2016 MB      2 GB, 32 MB hole
+                                                                1          3         1984 MB      2 GB, 64 MB hole
+                                                                1          4         1920 MB      2 GB,128 MB hole
+                                                                1          5         1792 MB      2 GB,256 MB hole
+                                                                1          6         1536 MB      2 GB,512 MB hole
+                                                                1          7         Illegal
+                                                         - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero
+                                                           and are ignored on write. BAR1 is an entirely ordinary
+                                                           1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
+                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
+                                                           as if the BAR were 1GB, but, OCTEON does not respond
+                                                           to addresses in the programmed holes.
+                                                         - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero
+                                                           and are ignored on write. BAR1 is an entirely ordinary
+                                                           2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
+                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
+                                                           as if the BAR were 2GB, but, OCTEON does not respond
+                                                           to addresses in the programmed holes.
+                                                         - Note that the BB1_HOLE value has no effect on the
+                                                           PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether
+                                                           OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE]
+                                                           behavior, however.
+                                                         - The first 128MB, i.e. addresses on the PCI bus in the range
+                                                             BAR1+0          .. BAR1+0x07FFFFFF
+                                                           access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's
+                                                           as before
+                                                         - The remaining address space, i.e. addresses
+                                                           on the PCI bus in the range
+                                                              BAR1+0x08000000 .. BAR1+size-1,
+                                                           where size is the size of BAR1 as selected by the above
+                                                           table (based on the BB1_SIZ and BB1_HOLE values), are mapped to
+                                                           OCTEON physical DRAM addresses as follows:
+                                                                   PCI Address Range         OCTEON Physical Address Range
+                                                           ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+                                                            BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size
+                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
+                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
+                                                           for these references.
+                                                           The consequences of any burst that crosses the end of the PCI
+                                                           Address Range for BAR1 are unpredicable.
+                                                         - The consequences of any burst access that crosses the boundary
+                                                           between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X
+                                                           mode. OCTEON may disconnect PCI references at this boundary. */
+	uint32_t bb0                          : 1;  /**< Big Bar 0 Enable
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB0] is set, the following
+                                                         differences occur:
+                                                         - OCTEON's BAR0 becomes 2GB rather than the default 4KB.
+                                                           PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write.
+                                                         - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON
+                                                           single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0
+                                                           writes, and splits (burstably) PCI-X BAR0 reads.)
+                                                         - The first 4KB, i.e. addresses on the PCI bus in the range
+                                                               BAR0+0      .. BAR0+0xFFF
+                                                           access OCTEON's PCI-type CSR's as when BB0 is clear.
+                                                         - The remaining address space, i.e. addresses on the PCI bus
+                                                           in the range
+                                                               BAR0+0x1000 .. BAR0+0x7FFFFFFF
+                                                           are mapped to OCTEON physical DRAM addresses as follows:
+                                                              PCI Address Range                  OCTEON Physical Address Range
+                                                           ------------------------------------+------------------------------
+                                                            BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF
+                                                            BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF
+                                                            BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF
+                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
+                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
+                                                           for these references.
+                                                           The consequences of any burst that crosses the end of the PCI
+                                                           Address Range for BAR0 are unpredicable.
+                                                         - The consequences of any burst access that crosses the boundary
+                                                           between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X
+                                                           mode. OCTEON may disconnect PCI references at this boundary.
+                                                         - The results of any burst read that crosses the boundary
+                                                           between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable.
+                                                           The consequences of any burst write that crosses this same
+                                                           boundary are unpredictable.
+                                                         - The results of any burst read that crosses the boundary
+                                                           between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable.
+                                                           The consequences of any burst write that crosses this same
+                                                           boundary are unpredictable. */
+	uint32_t erst_n                       : 1;  /**< Reset active Low. PASS-2 */
+	uint32_t bar2pres                     : 1;  /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
+                                                         is NOT blown the value of this field is '0' after
+                                                         reset and BAR2 is NOT present. When the fuse IS
+                                                         blown the value of this field is '1' after reset
+                                                         and BAR2 is present. Note that SW can change this
+                                                         field after reset. This is a PASS-2 field. */
+	uint32_t scmtyp                       : 1;  /**< Split Completion Message CMD Type (0=RD/1=WR)
+                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
+	uint32_t scm                          : 1;  /**< Split Completion Message Detected (Read or Write) */
+	uint32_t en_wfilt                     : 1;  /**< When '1' the window-access filter is enabled.
+                                                         Unfilter writes are:
+                                                         MIO, SubId0
+                                                         MIO, SubId7
+                                                         NPI, SubId0
+                                                         NPI, SubId7
+                                                         POW, SubId7
+                                                         DFA, SubId7
+                                                         IPD, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO, SubId0
+                                                         MIO, SubId7
+                                                         NPI, SubId0
+                                                         NPI, SubId7
+                                                         POW, SubId1
+                                                         POW, SubId2
+                                                         POW, SubId3
+                                                         POW, SubId7
+                                                         DFA, SubId7
+                                                         IPD, SubId7 */
+	uint32_t reserved_14_14               : 1;
+	uint32_t ap_pcix                      : 1;  /**< PCX Core Mode status (0=PCI Bus/1=PCIX)
+                                                         If one or more of PCI_DEVSEL_N, PCI_STOP_N, and
+                                                         PCI_TRDY_N are asserted at the rising edge of
+                                                         PCI_RST_N, the device enters PCI-X mode.
+                                                         Otherwise, the device enters conventional PCI
+                                                         mode at the rising edge of RST#. */
+	uint32_t ap_64ad                      : 1;  /**< PCX Core Bus status (0=32b Bus/1=64b Bus)
+                                                         When PCI_RST_N pin is de-asserted, the state
+                                                         of PCI_REQ64_N(driven by central agent) determines
+                                                         the width of the PCI/X bus. */
+	uint32_t b12_bist                     : 1;  /**< Bist Status For Memeory In B12 */
+	uint32_t pmo_amod                     : 1;  /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
+	uint32_t pmo_fpc                      : 3;  /**< PMO-ARB Fixed Priority Counter
+                                                         When PMO_AMOD=0 (FP mode), this field represents
+                                                         the \# of CMD1 requests that are issued (at higher
+                                                         priority) before a single lower priority CMD0
+                                                         is allowed to issue (to ensure foward progress).
+                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
+                                                           - ...
+                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
+	uint32_t tsr_hwm                      : 3;  /**< Target Split-Read ADB(allowable disconnect boundary)
+                                                         High Water Mark.
+                                                         Specifies the number of ADBs(128 Byte aligned chunks)
+                                                         that are accumulated(pending) BEFORE the Target Split
+                                                         completion is attempted on the PCI bus.
+                                                            - 0: RESERVED/ILLEGAL
+                                                            - 1: 2 Pending ADBs (129B-256B)
+                                                            - 2: 3 Pending ADBs (257B-384B)
+                                                            - 3: 4 Pending ADBs (385B-512B)
+                                                            - 4: 5 Pending ADBs (513B-640B)
+                                                            - 5: 6 Pending ADBs (641B-768B)
+                                                            - 6: 7 Pending ADBs (769B-896B)
+                                                            - 7: 8 Pending ADBs (897B-1024B)
+                                                         Example: Suppose a 1KB target memory request with
+                                                         starting byte offset address[6:0]=0x7F is split by
+                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
+                                                         The OCTEON will start the target split completion
+                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
+                                                         of data have been received from memory (even though
+                                                         the remaining 895B has not yet been received). The
+                                                         OCTEON will continue the split completion until it
+                                                         has consumed all of the pended split data. If the
+                                                         full transaction length(1KB) of data was NOT entirely
+                                                         transferred, then OCTEON will terminate the split
+                                                         completion and again wait for another 2 ADB-aligned data
+                                                         chunks(256B) of pended split data to be received from
+                                                         memory before starting another split completion request.
+                                                         This allows Octeon (as split completer), to send back
+                                                         multiple split completions for a given large split
+                                                         transaction without having to wait for the entire
+                                                         transaction length to be received from memory.
+                                                         NOTE: For split transaction sizes 'smaller' than the
+                                                         specified TSR_HWM value, the split completion
+                                                         is started when the last datum has been received from
+                                                         memory.
+                                                         NOTE: It is IMPERATIVE that this field NEVER BE
+                                                         written to a ZERO value. A value of zero is
+                                                         reserved/illegal and can result in PCIX bus hangs). */
+	uint32_t bar2_enb                     : 1;  /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will be target-aborted. */
+	uint32_t bar2_esx                     : 2;  /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+	uint32_t bar2_cax                     : 1;  /**< Value will be XORed with pci-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         When XOR result is 1, not cached in L2 */
+#else
+	uint32_t bar2_cax                     : 1;
+	uint32_t bar2_esx                     : 2;
+	uint32_t bar2_enb                     : 1;
+	uint32_t tsr_hwm                      : 3;
+	uint32_t pmo_fpc                      : 3;
+	uint32_t pmo_amod                     : 1;
+	uint32_t b12_bist                     : 1;
+	uint32_t ap_64ad                      : 1;
+	uint32_t ap_pcix                      : 1;
+	uint32_t reserved_14_14               : 1;
+	uint32_t en_wfilt                     : 1;
+	uint32_t scm                          : 1;
+	uint32_t scmtyp                       : 1;
+	uint32_t bar2pres                     : 1;
+	uint32_t erst_n                       : 1;
+	uint32_t bb0                          : 1;
+	uint32_t bb1                          : 1;
+	uint32_t bb_es                        : 2;
+	uint32_t bb_ca                        : 1;
+	uint32_t bb1_siz                      : 1;
+	uint32_t bb1_hole                     : 3;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_pci_ctl_status_2_s        cn30xx;
+	struct cvmx_pci_ctl_status_2_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t erst_n                       : 1;  /**< Reset active Low. */
+	uint32_t bar2pres                     : 1;  /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
+                                                         is NOT blown the value of this field is '0' after
+                                                         reset and BAR2 is NOT present. When the fuse IS
+                                                         blown the value of this field is '1' after reset
+                                                         and BAR2 is present. Note that SW can change this
+                                                         field after reset. */
+	uint32_t scmtyp                       : 1;  /**< Split Completion Message CMD Type (0=RD/1=WR)
+                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
+	uint32_t scm                          : 1;  /**< Split Completion Message Detected (Read or Write) */
+	uint32_t en_wfilt                     : 1;  /**< When '1' the window-access filter is enabled.
+                                                         Unfilter writes are:
+                                                         MIO,  SubId0
+                                                         MIO,  SubId7
+                                                         NPI,  SubId0
+                                                         NPI,  SubId7
+                                                         POW,  SubId7
+                                                         DFA,  SubId7
+                                                         IPD,  SubId7
+                                                         USBN, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,  SubId0
+                                                         MIO,  SubId7
+                                                         NPI,  SubId0
+                                                         NPI,  SubId7
+                                                         POW,  SubId1
+                                                         POW,  SubId2
+                                                         POW,  SubId3
+                                                         POW,  SubId7
+                                                         DFA,  SubId7
+                                                         IPD,  SubId7
+                                                         USBN, SubId7 */
+	uint32_t reserved_14_14               : 1;
+	uint32_t ap_pcix                      : 1;  /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */
+	uint32_t ap_64ad                      : 1;  /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */
+	uint32_t b12_bist                     : 1;  /**< Bist Status For Memeory In B12 */
+	uint32_t pmo_amod                     : 1;  /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
+	uint32_t pmo_fpc                      : 3;  /**< PMO-ARB Fixed Priority Counter
+                                                         When PMO_AMOD=0 (FP mode), this field represents
+                                                         the \# of CMD1 requests that are issued (at higher
+                                                         priority) before a single lower priority CMD0
+                                                         is allowed to issue (to ensure foward progress).
+                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
+                                                           - ...
+                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
+	uint32_t tsr_hwm                      : 3;  /**< Target Split-Read ADB(allowable disconnect boundary)
+                                                         High Water Mark.
+                                                         Specifies the number of ADBs(128 Byte aligned chunks)
+                                                         that are accumulated(pending) BEFORE the Target Split
+                                                         completion is attempted on the PCI bus.
+                                                            - 0: RESERVED/ILLEGAL
+                                                            - 1: 2 Pending ADBs (129B-256B)
+                                                            - 2: 3 Pending ADBs (257B-384B)
+                                                            - 3: 4 Pending ADBs (385B-512B)
+                                                            - 4: 5 Pending ADBs (513B-640B)
+                                                            - 5: 6 Pending ADBs (641B-768B)
+                                                            - 6: 7 Pending ADBs (769B-896B)
+                                                            - 7: 8 Pending ADBs (897B-1024B)
+                                                         Example: Suppose a 1KB target memory request with
+                                                         starting byte offset address[6:0]=0x7F is split by
+                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
+                                                         The OCTEON will start the target split completion
+                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
+                                                         of data have been received from memory (even though
+                                                         the remaining 895B has not yet been received). The
+                                                         OCTEON will continue the split completion until it
+                                                         has consumed all of the pended split data. If the
+                                                         full transaction length(1KB) of data was NOT entirely
+                                                         transferred, then OCTEON will terminate the split
+                                                         completion and again wait for another 2 ADB-aligned data
+                                                         chunks(256B) of pended split data to be received from
+                                                         memory before starting another split completion request.
+                                                         This allows Octeon (as split completer), to send back
+                                                         multiple split completions for a given large split
+                                                         transaction without having to wait for the entire
+                                                         transaction length to be received from memory.
+                                                         NOTE: For split transaction sizes 'smaller' than the
+                                                         specified TSR_HWM value, the split completion
+                                                         is started when the last datum has been received from
+                                                         memory.
+                                                         NOTE: It is IMPERATIVE that this field NEVER BE
+                                                         written to a ZERO value. A value of zero is
+                                                         reserved/illegal and can result in PCIX bus hangs). */
+	uint32_t bar2_enb                     : 1;  /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will be target-aborted. */
+	uint32_t bar2_esx                     : 2;  /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+	uint32_t bar2_cax                     : 1;  /**< Value will be XORed with pci-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         When XOR result is 1, not allocated in L2 cache */
+#else
+	uint32_t bar2_cax                     : 1;
+	uint32_t bar2_esx                     : 2;
+	uint32_t bar2_enb                     : 1;
+	uint32_t tsr_hwm                      : 3;
+	uint32_t pmo_fpc                      : 3;
+	uint32_t pmo_amod                     : 1;
+	uint32_t b12_bist                     : 1;
+	uint32_t ap_64ad                      : 1;
+	uint32_t ap_pcix                      : 1;
+	uint32_t reserved_14_14               : 1;
+	uint32_t en_wfilt                     : 1;
+	uint32_t scm                          : 1;
+	uint32_t scmtyp                       : 1;
+	uint32_t bar2pres                     : 1;
+	uint32_t erst_n                       : 1;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} cn31xx;
+	struct cvmx_pci_ctl_status_2_s        cn38xx;
+	struct cvmx_pci_ctl_status_2_cn31xx   cn38xxp2;
+	struct cvmx_pci_ctl_status_2_s        cn50xx;
+	struct cvmx_pci_ctl_status_2_s        cn58xx;
+	struct cvmx_pci_ctl_status_2_s        cn58xxp1;
+};
+typedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t;
+
+/**
+ * cvmx_pci_dbell#
+ *
+ * PCI_DBELL0 = PCI Doorbell-0
+ *
+ * The value to write to the doorbell 0 register. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+union cvmx_pci_dbellx
+{
+	uint32_t u32;
+	struct cvmx_pci_dbellx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t inc_val                      : 16; /**< Software writes this register with the
+                                                         number of new Instructions to be processed
+                                                         on the Instruction Queue. When read this
+                                                         register contains the last write value. */
+#else
+	uint32_t inc_val                      : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_pci_dbellx_s              cn30xx;
+	struct cvmx_pci_dbellx_s              cn31xx;
+	struct cvmx_pci_dbellx_s              cn38xx;
+	struct cvmx_pci_dbellx_s              cn38xxp2;
+	struct cvmx_pci_dbellx_s              cn50xx;
+	struct cvmx_pci_dbellx_s              cn58xx;
+	struct cvmx_pci_dbellx_s              cn58xxp1;
+};
+typedef union cvmx_pci_dbellx cvmx_pci_dbellx_t;
+
+/**
+ * cvmx_pci_dma_cnt#
+ *
+ * PCI_DMA_CNT0 = PCI DMA Count0
+ *
+ * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+union cvmx_pci_dma_cntx
+{
+	uint32_t u32;
+	struct cvmx_pci_dma_cntx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dma_cnt                      : 32; /**< Update with the number of DMAs completed or the
+                                                         number of bytes sent for DMA's associated with
+                                                         this counter. When this register is written the
+                                                         value written to [15:0] will be subtracted from
+                                                         the value in this register. */
+#else
+	uint32_t dma_cnt                      : 32;
+#endif
+	} s;
+	struct cvmx_pci_dma_cntx_s            cn30xx;
+	struct cvmx_pci_dma_cntx_s            cn31xx;
+	struct cvmx_pci_dma_cntx_s            cn38xx;
+	struct cvmx_pci_dma_cntx_s            cn38xxp2;
+	struct cvmx_pci_dma_cntx_s            cn50xx;
+	struct cvmx_pci_dma_cntx_s            cn58xx;
+	struct cvmx_pci_dma_cntx_s            cn58xxp1;
+};
+typedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t;
+
+/**
+ * cvmx_pci_dma_int_lev#
+ *
+ * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0
+ *
+ * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value.
+ */
+union cvmx_pci_dma_int_levx
+{
+	uint32_t u32;
+	struct cvmx_pci_dma_int_levx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_cnt                      : 32; /**< When PCI_DMA_CNT0 exceeds the value in this
+                                                         DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */
+#else
+	uint32_t pkt_cnt                      : 32;
+#endif
+	} s;
+	struct cvmx_pci_dma_int_levx_s        cn30xx;
+	struct cvmx_pci_dma_int_levx_s        cn31xx;
+	struct cvmx_pci_dma_int_levx_s        cn38xx;
+	struct cvmx_pci_dma_int_levx_s        cn38xxp2;
+	struct cvmx_pci_dma_int_levx_s        cn50xx;
+	struct cvmx_pci_dma_int_levx_s        cn58xx;
+	struct cvmx_pci_dma_int_levx_s        cn58xxp1;
+};
+typedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t;
+
+/**
+ * cvmx_pci_dma_time#
+ *
+ * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0
+ *
+ * Time to wait from DMA being sent before issuing an interrupt.
+ */
+union cvmx_pci_dma_timex
+{
+	uint32_t u32;
+	struct cvmx_pci_dma_timex_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dma_time                     : 32; /**< Number of PCI clock cycle to wait before
+                                                         setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2.
+                                                         After PCI_DMA_CNT0 becomes non-zero.
+                                                         The timer is reset when the
+                                                         PCI_INT_SUM[27] register is cleared. */
+#else
+	uint32_t dma_time                     : 32;
+#endif
+	} s;
+	struct cvmx_pci_dma_timex_s           cn30xx;
+	struct cvmx_pci_dma_timex_s           cn31xx;
+	struct cvmx_pci_dma_timex_s           cn38xx;
+	struct cvmx_pci_dma_timex_s           cn38xxp2;
+	struct cvmx_pci_dma_timex_s           cn50xx;
+	struct cvmx_pci_dma_timex_s           cn58xx;
+	struct cvmx_pci_dma_timex_s           cn58xxp1;
+};
+typedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t;
+
+/**
+ * cvmx_pci_instr_count#
+ *
+ * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count
+ *
+ * The number of instructions to be fetched by the Instruction-0 Engine.
+ */
+union cvmx_pci_instr_countx
+{
+	uint32_t u32;
+	struct cvmx_pci_instr_countx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t icnt                         : 32; /**< Number of Instructions to be fetched by the
+                                                         Instruction Engine.
+                                                         A write of any non zero value to this register
+                                                         will clear the value of this register. */
+#else
+	uint32_t icnt                         : 32;
+#endif
+	} s;
+	struct cvmx_pci_instr_countx_s        cn30xx;
+	struct cvmx_pci_instr_countx_s        cn31xx;
+	struct cvmx_pci_instr_countx_s        cn38xx;
+	struct cvmx_pci_instr_countx_s        cn38xxp2;
+	struct cvmx_pci_instr_countx_s        cn50xx;
+	struct cvmx_pci_instr_countx_s        cn58xx;
+	struct cvmx_pci_instr_countx_s        cn58xxp1;
+};
+typedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t;
+
+/**
+ * cvmx_pci_int_enb
+ *
+ * PCI_INT_ENB = PCI Interrupt Enable
+ *
+ * Enables interrupt bits in the PCI_INT_SUM register.
+ */
+union cvmx_pci_int_enb
+{
+	uint64_t u64;
+	struct cvmx_pci_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+	uint64_t win_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+	uint64_t dma1_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+	uint64_t dma0_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+	uint64_t idtime1                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+	uint64_t idtime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+	uint64_t idcnt1                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+	uint64_t idcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+	uint64_t iptime3                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */
+	uint64_t iptime2                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */
+	uint64_t iptime1                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
+	uint64_t iptime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+	uint64_t ipcnt3                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */
+	uint64_t ipcnt2                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */
+	uint64_t ipcnt1                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
+	uint64_t ipcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+	uint64_t irsl_int                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+	uint64_t ill_rrd                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+	uint64_t ill_rwr                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+	uint64_t idperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+	uint64_t iaperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+	uint64_t iserr                        : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+	uint64_t itsr_abt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+	uint64_t imsc_msg                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+	uint64_t imsi_mabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+	uint64_t imsi_tabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+	uint64_t imsi_per                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+	uint64_t imr_tto                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+	uint64_t imr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+	uint64_t itr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+	uint64_t imr_wtto                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+	uint64_t imr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+	uint64_t itr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+	uint64_t itr_wabt                     : 1;
+	uint64_t imr_wabt                     : 1;
+	uint64_t imr_wtto                     : 1;
+	uint64_t itr_abt                      : 1;
+	uint64_t imr_abt                      : 1;
+	uint64_t imr_tto                      : 1;
+	uint64_t imsi_per                     : 1;
+	uint64_t imsi_tabt                    : 1;
+	uint64_t imsi_mabt                    : 1;
+	uint64_t imsc_msg                     : 1;
+	uint64_t itsr_abt                     : 1;
+	uint64_t iserr                        : 1;
+	uint64_t iaperr                       : 1;
+	uint64_t idperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t irsl_int                     : 1;
+	uint64_t ipcnt0                       : 1;
+	uint64_t ipcnt1                       : 1;
+	uint64_t ipcnt2                       : 1;
+	uint64_t ipcnt3                       : 1;
+	uint64_t iptime0                      : 1;
+	uint64_t iptime1                      : 1;
+	uint64_t iptime2                      : 1;
+	uint64_t iptime3                      : 1;
+	uint64_t idcnt0                       : 1;
+	uint64_t idcnt1                       : 1;
+	uint64_t idtime0                      : 1;
+	uint64_t idtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_pci_int_enb_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+	uint64_t win_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+	uint64_t dma1_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+	uint64_t dma0_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+	uint64_t idtime1                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+	uint64_t idtime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+	uint64_t idcnt1                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+	uint64_t idcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+	uint64_t reserved_22_24               : 3;
+	uint64_t iptime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+	uint64_t reserved_18_20               : 3;
+	uint64_t ipcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+	uint64_t irsl_int                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+	uint64_t ill_rrd                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+	uint64_t ill_rwr                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+	uint64_t idperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+	uint64_t iaperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+	uint64_t iserr                        : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+	uint64_t itsr_abt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+	uint64_t imsc_msg                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+	uint64_t imsi_mabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+	uint64_t imsi_tabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+	uint64_t imsi_per                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+	uint64_t imr_tto                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+	uint64_t imr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+	uint64_t itr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+	uint64_t imr_wtto                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+	uint64_t imr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+	uint64_t itr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+	uint64_t itr_wabt                     : 1;
+	uint64_t imr_wabt                     : 1;
+	uint64_t imr_wtto                     : 1;
+	uint64_t itr_abt                      : 1;
+	uint64_t imr_abt                      : 1;
+	uint64_t imr_tto                      : 1;
+	uint64_t imsi_per                     : 1;
+	uint64_t imsi_tabt                    : 1;
+	uint64_t imsi_mabt                    : 1;
+	uint64_t imsc_msg                     : 1;
+	uint64_t itsr_abt                     : 1;
+	uint64_t iserr                        : 1;
+	uint64_t iaperr                       : 1;
+	uint64_t idperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t irsl_int                     : 1;
+	uint64_t ipcnt0                       : 1;
+	uint64_t reserved_18_20               : 3;
+	uint64_t iptime0                      : 1;
+	uint64_t reserved_22_24               : 3;
+	uint64_t idcnt0                       : 1;
+	uint64_t idcnt1                       : 1;
+	uint64_t idtime0                      : 1;
+	uint64_t idtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn30xx;
+	struct cvmx_pci_int_enb_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+	uint64_t ill_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+	uint64_t win_wr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+	uint64_t dma1_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+	uint64_t dma0_fi                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+	uint64_t idtime1                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+	uint64_t idtime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+	uint64_t idcnt1                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+	uint64_t idcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+	uint64_t reserved_23_24               : 2;
+	uint64_t iptime1                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
+	uint64_t iptime0                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+	uint64_t reserved_19_20               : 2;
+	uint64_t ipcnt1                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
+	uint64_t ipcnt0                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+	uint64_t irsl_int                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+	uint64_t ill_rrd                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+	uint64_t ill_rwr                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+	uint64_t idperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+	uint64_t iaperr                       : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+	uint64_t iserr                        : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+	uint64_t itsr_abt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+	uint64_t imsc_msg                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+	uint64_t imsi_mabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+	uint64_t imsi_tabt                    : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+	uint64_t imsi_per                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+	uint64_t imr_tto                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+	uint64_t imr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+	uint64_t itr_abt                      : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+	uint64_t imr_wtto                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+	uint64_t imr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+	uint64_t itr_wabt                     : 1;  /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+	uint64_t itr_wabt                     : 1;
+	uint64_t imr_wabt                     : 1;
+	uint64_t imr_wtto                     : 1;
+	uint64_t itr_abt                      : 1;
+	uint64_t imr_abt                      : 1;
+	uint64_t imr_tto                      : 1;
+	uint64_t imsi_per                     : 1;
+	uint64_t imsi_tabt                    : 1;
+	uint64_t imsi_mabt                    : 1;
+	uint64_t imsc_msg                     : 1;
+	uint64_t itsr_abt                     : 1;
+	uint64_t iserr                        : 1;
+	uint64_t iaperr                       : 1;
+	uint64_t idperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t irsl_int                     : 1;
+	uint64_t ipcnt0                       : 1;
+	uint64_t ipcnt1                       : 1;
+	uint64_t reserved_19_20               : 2;
+	uint64_t iptime0                      : 1;
+	uint64_t iptime1                      : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t idcnt0                       : 1;
+	uint64_t idcnt1                       : 1;
+	uint64_t idtime0                      : 1;
+	uint64_t idtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn31xx;
+	struct cvmx_pci_int_enb_s             cn38xx;
+	struct cvmx_pci_int_enb_s             cn38xxp2;
+	struct cvmx_pci_int_enb_cn31xx        cn50xx;
+	struct cvmx_pci_int_enb_s             cn58xx;
+	struct cvmx_pci_int_enb_s             cn58xxp1;
+};
+typedef union cvmx_pci_int_enb cvmx_pci_int_enb_t;
+
+/**
+ * cvmx_pci_int_enb2
+ *
+ * PCI_INT_ENB2 = PCI Interrupt Enable2 Register
+ *
+ * Enables interrupt bits in the PCI_INT_SUM2 register.
+ */
+union cvmx_pci_int_enb2
+{
+	uint64_t u64;
+	struct cvmx_pci_int_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+	uint64_t win_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+	uint64_t dma1_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+	uint64_t dma0_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+	uint64_t rdtime1                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+	uint64_t rdtime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+	uint64_t rdcnt1                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+	uint64_t rdcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+	uint64_t rptime3                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */
+	uint64_t rptime2                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */
+	uint64_t rptime1                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
+	uint64_t rptime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+	uint64_t rpcnt3                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */
+	uint64_t rpcnt2                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */
+	uint64_t rpcnt1                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
+	uint64_t rpcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+	uint64_t rrsl_int                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+	uint64_t ill_rrd                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+	uint64_t ill_rwr                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+	uint64_t rdperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+	uint64_t raperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+	uint64_t rserr                        : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+	uint64_t rtsr_abt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+	uint64_t rmsc_msg                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+	uint64_t rmsi_mabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+	uint64_t rmsi_tabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+	uint64_t rmsi_per                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+	uint64_t rmr_tto                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+	uint64_t rmr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+	uint64_t rtr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+	uint64_t rmr_wtto                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+	uint64_t rmr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+	uint64_t rtr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+	uint64_t rtr_wabt                     : 1;
+	uint64_t rmr_wabt                     : 1;
+	uint64_t rmr_wtto                     : 1;
+	uint64_t rtr_abt                      : 1;
+	uint64_t rmr_abt                      : 1;
+	uint64_t rmr_tto                      : 1;
+	uint64_t rmsi_per                     : 1;
+	uint64_t rmsi_tabt                    : 1;
+	uint64_t rmsi_mabt                    : 1;
+	uint64_t rmsc_msg                     : 1;
+	uint64_t rtsr_abt                     : 1;
+	uint64_t rserr                        : 1;
+	uint64_t raperr                       : 1;
+	uint64_t rdperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rrsl_int                     : 1;
+	uint64_t rpcnt0                       : 1;
+	uint64_t rpcnt1                       : 1;
+	uint64_t rpcnt2                       : 1;
+	uint64_t rpcnt3                       : 1;
+	uint64_t rptime0                      : 1;
+	uint64_t rptime1                      : 1;
+	uint64_t rptime2                      : 1;
+	uint64_t rptime3                      : 1;
+	uint64_t rdcnt0                       : 1;
+	uint64_t rdcnt1                       : 1;
+	uint64_t rdtime0                      : 1;
+	uint64_t rdtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_pci_int_enb2_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+	uint64_t win_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+	uint64_t dma1_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+	uint64_t dma0_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+	uint64_t rdtime1                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+	uint64_t rdtime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+	uint64_t rdcnt1                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+	uint64_t rdcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+	uint64_t reserved_22_24               : 3;
+	uint64_t rptime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+	uint64_t reserved_18_20               : 3;
+	uint64_t rpcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+	uint64_t rrsl_int                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+	uint64_t ill_rrd                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+	uint64_t ill_rwr                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+	uint64_t rdperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+	uint64_t raperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+	uint64_t rserr                        : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+	uint64_t rtsr_abt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+	uint64_t rmsc_msg                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+	uint64_t rmsi_mabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+	uint64_t rmsi_tabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+	uint64_t rmsi_per                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+	uint64_t rmr_tto                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+	uint64_t rmr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+	uint64_t rtr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+	uint64_t rmr_wtto                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+	uint64_t rmr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+	uint64_t rtr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+	uint64_t rtr_wabt                     : 1;
+	uint64_t rmr_wabt                     : 1;
+	uint64_t rmr_wtto                     : 1;
+	uint64_t rtr_abt                      : 1;
+	uint64_t rmr_abt                      : 1;
+	uint64_t rmr_tto                      : 1;
+	uint64_t rmsi_per                     : 1;
+	uint64_t rmsi_tabt                    : 1;
+	uint64_t rmsi_mabt                    : 1;
+	uint64_t rmsc_msg                     : 1;
+	uint64_t rtsr_abt                     : 1;
+	uint64_t rserr                        : 1;
+	uint64_t raperr                       : 1;
+	uint64_t rdperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rrsl_int                     : 1;
+	uint64_t rpcnt0                       : 1;
+	uint64_t reserved_18_20               : 3;
+	uint64_t rptime0                      : 1;
+	uint64_t reserved_22_24               : 3;
+	uint64_t rdcnt0                       : 1;
+	uint64_t rdcnt1                       : 1;
+	uint64_t rdtime0                      : 1;
+	uint64_t rdtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn30xx;
+	struct cvmx_pci_int_enb2_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+	uint64_t ill_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+	uint64_t win_wr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+	uint64_t dma1_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+	uint64_t dma0_fi                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+	uint64_t rdtime1                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+	uint64_t rdtime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+	uint64_t rdcnt1                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+	uint64_t rdcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+	uint64_t reserved_23_24               : 2;
+	uint64_t rptime1                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
+	uint64_t rptime0                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+	uint64_t reserved_19_20               : 2;
+	uint64_t rpcnt1                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
+	uint64_t rpcnt0                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+	uint64_t rrsl_int                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+	uint64_t ill_rrd                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+	uint64_t ill_rwr                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+	uint64_t rdperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+	uint64_t raperr                       : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+	uint64_t rserr                        : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+	uint64_t rtsr_abt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+	uint64_t rmsc_msg                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+	uint64_t rmsi_mabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+	uint64_t rmsi_tabt                    : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+	uint64_t rmsi_per                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+	uint64_t rmr_tto                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+	uint64_t rmr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+	uint64_t rtr_abt                      : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+	uint64_t rmr_wtto                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+	uint64_t rmr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+	uint64_t rtr_wabt                     : 1;  /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+	uint64_t rtr_wabt                     : 1;
+	uint64_t rmr_wabt                     : 1;
+	uint64_t rmr_wtto                     : 1;
+	uint64_t rtr_abt                      : 1;
+	uint64_t rmr_abt                      : 1;
+	uint64_t rmr_tto                      : 1;
+	uint64_t rmsi_per                     : 1;
+	uint64_t rmsi_tabt                    : 1;
+	uint64_t rmsi_mabt                    : 1;
+	uint64_t rmsc_msg                     : 1;
+	uint64_t rtsr_abt                     : 1;
+	uint64_t rserr                        : 1;
+	uint64_t raperr                       : 1;
+	uint64_t rdperr                       : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rrsl_int                     : 1;
+	uint64_t rpcnt0                       : 1;
+	uint64_t rpcnt1                       : 1;
+	uint64_t reserved_19_20               : 2;
+	uint64_t rptime0                      : 1;
+	uint64_t rptime1                      : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t rdcnt0                       : 1;
+	uint64_t rdcnt1                       : 1;
+	uint64_t rdtime0                      : 1;
+	uint64_t rdtime1                      : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn31xx;
+	struct cvmx_pci_int_enb2_s            cn38xx;
+	struct cvmx_pci_int_enb2_s            cn38xxp2;
+	struct cvmx_pci_int_enb2_cn31xx       cn50xx;
+	struct cvmx_pci_int_enb2_s            cn58xx;
+	struct cvmx_pci_int_enb2_s            cn58xxp1;
+};
+typedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t;
+
+/**
+ * cvmx_pci_int_sum
+ *
+ * PCI_INT_SUM = PCI Interrupt Summary
+ *
+ * The PCI Interrupt Summary Register.
+ */
+union cvmx_pci_int_sum
+{
+	uint64_t u64;
+	struct cvmx_pci_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t ptime3                       : 1;  /**< When the value in the PCI_PKTS_SENT3
+                                                         register is not 0 the Sent-3 timer counts.
+                                                         When the Sent-3 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME3 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime2                       : 1;  /**< When the value in the PCI_PKTS_SENT2
+                                                         register is not 0 the Sent-2 timer counts.
+                                                         When the Sent-2 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME2 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime1                       : 1;  /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t pcnt3                        : 1;  /**< This bit indicates that PCI_PKTS_SENT3
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
+	uint64_t pcnt2                        : 1;  /**< This bit indicates that PCI_PKTS_SENT2
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
+	uint64_t pcnt1                        : 1;  /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO. */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected
+                                                         CN58XX (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the CN58XX (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+	uint64_t msi_mabt                     : 1;  /**< PCI Master Abort on Master MSI */
+	uint64_t msi_tabt                     : 1;  /**< PCI Target-Abort on Master MSI */
+	uint64_t msi_per                      : 1;  /**< PCI Parity Error on Master MSI */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Master-Read */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Master-Read */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Master-Read */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on Master-write */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on Master-write */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on Master-write */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t pcnt1                        : 1;
+	uint64_t pcnt2                        : 1;
+	uint64_t pcnt3                        : 1;
+	uint64_t ptime0                       : 1;
+	uint64_t ptime1                       : 1;
+	uint64_t ptime2                       : 1;
+	uint64_t ptime3                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_pci_int_sum_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t reserved_22_24               : 3;
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t reserved_18_20               : 3;
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected
+                                                         N3K (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the N3K (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+	uint64_t msi_mabt                     : 1;  /**< PCI Master Abort on Master MSI */
+	uint64_t msi_tabt                     : 1;  /**< PCI Target-Abort on Master MSI */
+	uint64_t msi_per                      : 1;  /**< PCI Parity Error on Master MSI */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Master-Read */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Master-Read */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Master-Read */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on Master-write */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on Master-write */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on Master-write */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t reserved_18_20               : 3;
+	uint64_t ptime0                       : 1;
+	uint64_t reserved_22_24               : 3;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn30xx;
+	struct cvmx_pci_int_sum_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t reserved_23_24               : 2;
+	uint64_t ptime1                       : 1;  /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t reserved_19_20               : 2;
+	uint64_t pcnt1                        : 1;  /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected
+                                                         N3K (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the N3K (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+	uint64_t msi_mabt                     : 1;  /**< PCI Master Abort on Master MSI */
+	uint64_t msi_tabt                     : 1;  /**< PCI Target-Abort on Master MSI */
+	uint64_t msi_per                      : 1;  /**< PCI Parity Error on Master MSI */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Master-Read */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Master-Read */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Master-Read */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on Master-write */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on Master-write */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on Master-write */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t pcnt1                        : 1;
+	uint64_t reserved_19_20               : 2;
+	uint64_t ptime0                       : 1;
+	uint64_t ptime1                       : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn31xx;
+	struct cvmx_pci_int_sum_s             cn38xx;
+	struct cvmx_pci_int_sum_s             cn38xxp2;
+	struct cvmx_pci_int_sum_cn31xx        cn50xx;
+	struct cvmx_pci_int_sum_s             cn58xx;
+	struct cvmx_pci_int_sum_s             cn58xxp1;
+};
+typedef union cvmx_pci_int_sum cvmx_pci_int_sum_t;
+
+/**
+ * cvmx_pci_int_sum2
+ *
+ * PCI_INT_SUM2 = PCI Interrupt Summary2 Register
+ *
+ * The PCI Interrupt Summary2 Register copy used for RSL interrupts.
+ */
+union cvmx_pci_int_sum2
+{
+	uint64_t u64;
+	struct cvmx_pci_int_sum2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t ptime3                       : 1;  /**< When the value in the PCI_PKTS_SENT3
+                                                         register is not 0 the Sent-3 timer counts.
+                                                         When the Sent-3 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME3 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime2                       : 1;  /**< When the value in the PCI_PKTS_SENT2
+                                                         register is not 0 the Sent-2 timer counts.
+                                                         When the Sent-2 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME2 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime1                       : 1;  /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t pcnt3                        : 1;  /**< This bit indicates that PCI_PKTS_SENT3
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
+	uint64_t pcnt2                        : 1;  /**< This bit indicates that PCI_PKTS_SENT2
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
+	uint64_t pcnt1                        : 1;  /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message Detected */
+	uint64_t msi_mabt                     : 1;  /**< PCI MSI Master Abort. */
+	uint64_t msi_tabt                     : 1;  /**< PCI MSI Target Abort. */
+	uint64_t msi_per                      : 1;  /**< PCI MSI Parity Error. */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Read. */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Read. */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Read. */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on write. */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on write. */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on write. */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t pcnt1                        : 1;
+	uint64_t pcnt2                        : 1;
+	uint64_t pcnt3                        : 1;
+	uint64_t ptime0                       : 1;
+	uint64_t ptime1                       : 1;
+	uint64_t ptime2                       : 1;
+	uint64_t ptime3                       : 1;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} s;
+	struct cvmx_pci_int_sum2_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t reserved_22_24               : 3;
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t reserved_18_20               : 3;
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message Detected */
+	uint64_t msi_mabt                     : 1;  /**< PCI MSI Master Abort. */
+	uint64_t msi_tabt                     : 1;  /**< PCI MSI Target Abort. */
+	uint64_t msi_per                      : 1;  /**< PCI MSI Parity Error. */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Read. */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Read. */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Read. */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on write. */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on write. */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on write. */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t reserved_18_20               : 3;
+	uint64_t ptime0                       : 1;
+	uint64_t reserved_22_24               : 3;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn30xx;
+	struct cvmx_pci_int_sum2_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_34_63               : 30;
+	uint64_t ill_rd                       : 1;  /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t ill_wr                       : 1;  /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+	uint64_t win_wr                       : 1;  /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+	uint64_t dma1_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+	uint64_t dma0_fi                      : 1;  /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+	uint64_t dtime1                       : 1;  /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dtime0                       : 1;  /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t dcnt1                        : 1;  /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+	uint64_t dcnt0                        : 1;  /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+	uint64_t reserved_23_24               : 2;
+	uint64_t ptime1                       : 1;  /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t ptime0                       : 1;  /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+	uint64_t reserved_19_20               : 2;
+	uint64_t pcnt1                        : 1;  /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+	uint64_t pcnt0                        : 1;  /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+	uint64_t rsl_int                      : 1;  /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+	uint64_t ill_rrd                      : 1;  /**< A read  to the disabled PCI registers took place. */
+	uint64_t ill_rwr                      : 1;  /**< A write to the disabled PCI registers took place. */
+	uint64_t dperr                        : 1;  /**< Data Parity Error detected by PCX Core */
+	uint64_t aperr                        : 1;  /**< Address Parity Error detected by PCX Core */
+	uint64_t serr                         : 1;  /**< SERR# detected by PCX Core */
+	uint64_t tsr_abt                      : 1;  /**< Target Split-Read Abort Detected */
+	uint64_t msc_msg                      : 1;  /**< Master Split Completion Message Detected */
+	uint64_t msi_mabt                     : 1;  /**< PCI MSI Master Abort. */
+	uint64_t msi_tabt                     : 1;  /**< PCI MSI Target Abort. */
+	uint64_t msi_per                      : 1;  /**< PCI MSI Parity Error. */
+	uint64_t mr_tto                       : 1;  /**< PCI Master Retry Timeout On Read. */
+	uint64_t mr_abt                       : 1;  /**< PCI Master Abort On Read. */
+	uint64_t tr_abt                       : 1;  /**< PCI Target Abort On Read. */
+	uint64_t mr_wtto                      : 1;  /**< PCI Master Retry Timeout on write. */
+	uint64_t mr_wabt                      : 1;  /**< PCI Master Abort detected on write. */
+	uint64_t tr_wabt                      : 1;  /**< PCI Target Abort detected on write. */
+#else
+	uint64_t tr_wabt                      : 1;
+	uint64_t mr_wabt                      : 1;
+	uint64_t mr_wtto                      : 1;
+	uint64_t tr_abt                       : 1;
+	uint64_t mr_abt                       : 1;
+	uint64_t mr_tto                       : 1;
+	uint64_t msi_per                      : 1;
+	uint64_t msi_tabt                     : 1;
+	uint64_t msi_mabt                     : 1;
+	uint64_t msc_msg                      : 1;
+	uint64_t tsr_abt                      : 1;
+	uint64_t serr                         : 1;
+	uint64_t aperr                        : 1;
+	uint64_t dperr                        : 1;
+	uint64_t ill_rwr                      : 1;
+	uint64_t ill_rrd                      : 1;
+	uint64_t rsl_int                      : 1;
+	uint64_t pcnt0                        : 1;
+	uint64_t pcnt1                        : 1;
+	uint64_t reserved_19_20               : 2;
+	uint64_t ptime0                       : 1;
+	uint64_t ptime1                       : 1;
+	uint64_t reserved_23_24               : 2;
+	uint64_t dcnt0                        : 1;
+	uint64_t dcnt1                        : 1;
+	uint64_t dtime0                       : 1;
+	uint64_t dtime1                       : 1;
+	uint64_t dma0_fi                      : 1;
+	uint64_t dma1_fi                      : 1;
+	uint64_t win_wr                       : 1;
+	uint64_t ill_wr                       : 1;
+	uint64_t ill_rd                       : 1;
+	uint64_t reserved_34_63               : 30;
+#endif
+	} cn31xx;
+	struct cvmx_pci_int_sum2_s            cn38xx;
+	struct cvmx_pci_int_sum2_s            cn38xxp2;
+	struct cvmx_pci_int_sum2_cn31xx       cn50xx;
+	struct cvmx_pci_int_sum2_s            cn58xx;
+	struct cvmx_pci_int_sum2_s            cn58xxp1;
+};
+typedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t;
+
+/**
+ * cvmx_pci_msi_rcv
+ *
+ * PCI_MSI_RCV = PCI's MSI Received Vector Register
+ *
+ * A bit is set in this register relative to the vector received during a MSI. The value in this
+ * register is acted upon when the least-significant-byte of this register is written.
+ */
+union cvmx_pci_msi_rcv
+{
+	uint32_t u32;
+	struct cvmx_pci_msi_rcv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_6_31                : 26;
+	uint32_t intr                         : 6;  /**< When an MSI is received on the PCI the bit selected
+                                                         by data [5:0] will be set in this register. To
+                                                         clear this bit a write must take place to the
+                                                         NPI_MSI_RCV register where any bit set to 1 is
+                                                         cleared. Reading this address will return an
+                                                         unpredicatable value. */
+#else
+	uint32_t intr                         : 6;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_pci_msi_rcv_s             cn30xx;
+	struct cvmx_pci_msi_rcv_s             cn31xx;
+	struct cvmx_pci_msi_rcv_s             cn38xx;
+	struct cvmx_pci_msi_rcv_s             cn38xxp2;
+	struct cvmx_pci_msi_rcv_s             cn50xx;
+	struct cvmx_pci_msi_rcv_s             cn58xx;
+	struct cvmx_pci_msi_rcv_s             cn58xxp1;
+};
+typedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t;
+
+/**
+ * cvmx_pci_pkt_credits#
+ *
+ * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0
+ *
+ * Used to decrease the number of packets to be processed by the host from Output-0 and return
+ * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+union cvmx_pci_pkt_creditsx
+{
+	uint32_t u32;
+	struct cvmx_pci_pkt_creditsx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_cnt                      : 16; /**< The value written to this field will be
+                                                         subtracted from PCI_PKTS_SENT0[PKT_CNT]. */
+	uint32_t ptr_cnt                      : 16; /**< This field value is added to the
+                                                         NPI's internal Buffer/Info Pointer Pair count. */
+#else
+	uint32_t ptr_cnt                      : 16;
+	uint32_t pkt_cnt                      : 16;
+#endif
+	} s;
+	struct cvmx_pci_pkt_creditsx_s        cn30xx;
+	struct cvmx_pci_pkt_creditsx_s        cn31xx;
+	struct cvmx_pci_pkt_creditsx_s        cn38xx;
+	struct cvmx_pci_pkt_creditsx_s        cn38xxp2;
+	struct cvmx_pci_pkt_creditsx_s        cn50xx;
+	struct cvmx_pci_pkt_creditsx_s        cn58xx;
+	struct cvmx_pci_pkt_creditsx_s        cn58xxp1;
+};
+typedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t;
+
+/**
+ * cvmx_pci_pkts_sent#
+ *
+ * PCI_PKTS_SENT0 = PCI Packets Sent 0
+ *
+ * Number of packets sent to the host memory from PCI Output 0
+ */
+union cvmx_pci_pkts_sentx
+{
+	uint32_t u32;
+	struct cvmx_pci_pkts_sentx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_cnt                      : 32; /**< Each time a packet is written to the memory via
+                                                         PCI from PCI Output 0,  this counter is
+                                                         incremented by 1 or the byte count of the packet
+                                                         as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */
+#else
+	uint32_t pkt_cnt                      : 32;
+#endif
+	} s;
+	struct cvmx_pci_pkts_sentx_s          cn30xx;
+	struct cvmx_pci_pkts_sentx_s          cn31xx;
+	struct cvmx_pci_pkts_sentx_s          cn38xx;
+	struct cvmx_pci_pkts_sentx_s          cn38xxp2;
+	struct cvmx_pci_pkts_sentx_s          cn50xx;
+	struct cvmx_pci_pkts_sentx_s          cn58xx;
+	struct cvmx_pci_pkts_sentx_s          cn58xxp1;
+};
+typedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t;
+
+/**
+ * cvmx_pci_pkts_sent_int_lev#
+ *
+ * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0
+ *
+ * Interrupt when number of packets sent is equal to or greater than the register value.
+ */
+union cvmx_pci_pkts_sent_int_levx
+{
+	uint32_t u32;
+	struct cvmx_pci_pkts_sent_int_levx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_cnt                      : 32; /**< When corresponding port's PCI_PKTS_SENT0 value
+                                                         exceeds the value in this register, PCNT0 of the
+                                                         PCI_INT_SUM and PCI_INT_SUM2 will be set. */
+#else
+	uint32_t pkt_cnt                      : 32;
+#endif
+	} s;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn30xx;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn31xx;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn38xx;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn38xxp2;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn50xx;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn58xx;
+	struct cvmx_pci_pkts_sent_int_levx_s  cn58xxp1;
+};
+typedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t;
+
+/**
+ * cvmx_pci_pkts_sent_time#
+ *
+ * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0
+ *
+ * Time to wait from packet being sent to host from Output-0 before issuing an interrupt.
+ */
+union cvmx_pci_pkts_sent_timex
+{
+	uint32_t u32;
+	struct cvmx_pci_pkts_sent_timex_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_time                     : 32; /**< Number of PCI clock cycle to wait before
+                                                         issuing an interrupt to the host when a
+                                                         packet from this port has been sent to the
+                                                         host.  The timer is reset when the
+                                                         PCI_INT_SUM[21] register is cleared. */
+#else
+	uint32_t pkt_time                     : 32;
+#endif
+	} s;
+	struct cvmx_pci_pkts_sent_timex_s     cn30xx;
+	struct cvmx_pci_pkts_sent_timex_s     cn31xx;
+	struct cvmx_pci_pkts_sent_timex_s     cn38xx;
+	struct cvmx_pci_pkts_sent_timex_s     cn38xxp2;
+	struct cvmx_pci_pkts_sent_timex_s     cn50xx;
+	struct cvmx_pci_pkts_sent_timex_s     cn58xx;
+	struct cvmx_pci_pkts_sent_timex_s     cn58xxp1;
+};
+typedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t;
+
+/**
+ * cvmx_pci_read_cmd_6
+ *
+ * PCI_READ_CMD_6 = PCI Read Command 6 Register
+ *
+ * Contains control inforamtion related to a received PCI Command 6.
+ */
+union cvmx_pci_read_cmd_6
+{
+	uint32_t u32;
+	struct cvmx_pci_read_cmd_6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
+                                                         before informing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+	uint32_t prefetch                     : 3;  /**< Control the amount of data to be preteched when
+                                                         this type of bhmstREAD command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+	uint32_t prefetch                     : 3;
+	uint32_t min_data                     : 6;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pci_read_cmd_6_s          cn30xx;
+	struct cvmx_pci_read_cmd_6_s          cn31xx;
+	struct cvmx_pci_read_cmd_6_s          cn38xx;
+	struct cvmx_pci_read_cmd_6_s          cn38xxp2;
+	struct cvmx_pci_read_cmd_6_s          cn50xx;
+	struct cvmx_pci_read_cmd_6_s          cn58xx;
+	struct cvmx_pci_read_cmd_6_s          cn58xxp1;
+};
+typedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t;
+
+/**
+ * cvmx_pci_read_cmd_c
+ *
+ * PCI_READ_CMD_C = PCI Read Command C Register
+ *
+ * Contains control inforamtion related to a received PCI Command C.
+ */
+union cvmx_pci_read_cmd_c
+{
+	uint32_t u32;
+	struct cvmx_pci_read_cmd_c_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
+                                                         before informing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+	uint32_t prefetch                     : 3;  /**< Control the amount of data to be preteched when
+                                                         this type of READ command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+	uint32_t prefetch                     : 3;
+	uint32_t min_data                     : 6;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pci_read_cmd_c_s          cn30xx;
+	struct cvmx_pci_read_cmd_c_s          cn31xx;
+	struct cvmx_pci_read_cmd_c_s          cn38xx;
+	struct cvmx_pci_read_cmd_c_s          cn38xxp2;
+	struct cvmx_pci_read_cmd_c_s          cn50xx;
+	struct cvmx_pci_read_cmd_c_s          cn58xx;
+	struct cvmx_pci_read_cmd_c_s          cn58xxp1;
+};
+typedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t;
+
+/**
+ * cvmx_pci_read_cmd_e
+ *
+ * PCI_READ_CMD_E = PCI Read Command E Register
+ *
+ * Contains control inforamtion related to a received PCI Command 6.
+ */
+union cvmx_pci_read_cmd_e
+{
+	uint32_t u32;
+	struct cvmx_pci_read_cmd_e_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t min_data                     : 6;  /**< The number of words to have buffered in the PNI
+                                                         before informaing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+	uint32_t prefetch                     : 3;  /**< Control the amount of data to be preteched when
+                                                         this type of READ command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+	uint32_t prefetch                     : 3;
+	uint32_t min_data                     : 6;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pci_read_cmd_e_s          cn30xx;
+	struct cvmx_pci_read_cmd_e_s          cn31xx;
+	struct cvmx_pci_read_cmd_e_s          cn38xx;
+	struct cvmx_pci_read_cmd_e_s          cn38xxp2;
+	struct cvmx_pci_read_cmd_e_s          cn50xx;
+	struct cvmx_pci_read_cmd_e_s          cn58xx;
+	struct cvmx_pci_read_cmd_e_s          cn58xxp1;
+};
+typedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t;
+
+/**
+ * cvmx_pci_read_timeout
+ *
+ * PCI_READ_TIMEOUT = PCI Read Timeour Register
+ *
+ * The address to start reading Instructions from for Input-3.
+ */
+union cvmx_pci_read_timeout
+{
+	uint64_t u64;
+	struct cvmx_pci_read_timeout_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enb                          : 1;  /**< Enable the use of the Timeout function. */
+	uint64_t cnt                          : 31; /**< The number of eclk cycles to wait after issuing
+                                                         a read request to the PNI before setting a
+                                                         timeout and not expecting the data to return.
+                                                         This is considered a fatal condition by the NPI. */
+#else
+	uint64_t cnt                          : 31;
+	uint64_t enb                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pci_read_timeout_s        cn30xx;
+	struct cvmx_pci_read_timeout_s        cn31xx;
+	struct cvmx_pci_read_timeout_s        cn38xx;
+	struct cvmx_pci_read_timeout_s        cn38xxp2;
+	struct cvmx_pci_read_timeout_s        cn50xx;
+	struct cvmx_pci_read_timeout_s        cn58xx;
+	struct cvmx_pci_read_timeout_s        cn58xxp1;
+};
+typedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t;
+
+/**
+ * cvmx_pci_scm_reg
+ *
+ * PCI_SCM_REG = PCI Master Split Completion Message Register
+ *
+ * This register contains the Master Split Completion Message(SCM) generated when a master split
+ * transaction is aborted.
+ */
+union cvmx_pci_scm_reg
+{
+	uint64_t u64;
+	struct cvmx_pci_scm_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t scm                          : 32; /**< Contains the Split Completion Message (SCM)
+                                                         driven when a master-split transaction is aborted.
+                                                            [31:28]: Message Class
+                                                            [27:20]: Message Index
+                                                            [19]:    Reserved
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:8]:  Upper Remaining Byte Count
+                                                            [7:0]:   Lower Remaining Byte Count
+                                                         Refer to the PCIX1.0a specification, Fig 2-40
+                                                         for additional details for the split completion
+                                                         message format. */
+#else
+	uint64_t scm                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pci_scm_reg_s             cn30xx;
+	struct cvmx_pci_scm_reg_s             cn31xx;
+	struct cvmx_pci_scm_reg_s             cn38xx;
+	struct cvmx_pci_scm_reg_s             cn38xxp2;
+	struct cvmx_pci_scm_reg_s             cn50xx;
+	struct cvmx_pci_scm_reg_s             cn58xx;
+	struct cvmx_pci_scm_reg_s             cn58xxp1;
+};
+typedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t;
+
+/**
+ * cvmx_pci_tsr_reg
+ *
+ * PCI_TSR_REG = PCI Target Split Attribute Register
+ *
+ * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split
+ * transaction is aborted.
+ */
+union cvmx_pci_tsr_reg
+{
+	uint64_t u64;
+	struct cvmx_pci_tsr_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t tsr                          : 36; /**< Contains the Target Split Attribute field when a
+                                                         target-split transaction is aborted.
+                                                           [35:32]: Upper Byte Count
+                                                           [31]:    BCM=Byte Count Modified
+                                                           [30]:    SCE=Split Completion Error
+                                                           [29]:    SCM=Split Completion Message
+                                                           [28:24]: RESERVED
+                                                           [23:16]: Completer Bus Number
+                                                           [15:11]: Completer Device Number
+                                                           [10:8]:  Completer Function Number
+                                                           [7:0]:   Lower Byte Count
+                                                         Refer to the PCIX1.0a specification, Fig 2-39
+                                                         for additional details on the completer attribute
+                                                         bit assignments. */
+#else
+	uint64_t tsr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_pci_tsr_reg_s             cn30xx;
+	struct cvmx_pci_tsr_reg_s             cn31xx;
+	struct cvmx_pci_tsr_reg_s             cn38xx;
+	struct cvmx_pci_tsr_reg_s             cn38xxp2;
+	struct cvmx_pci_tsr_reg_s             cn50xx;
+	struct cvmx_pci_tsr_reg_s             cn58xx;
+	struct cvmx_pci_tsr_reg_s             cn58xxp1;
+};
+typedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t;
+
+/**
+ * cvmx_pci_win_rd_addr
+ *
+ * PCI_WIN_RD_ADDR = PCI Window Read Address Register
+ *
+ * Writing the least-significant-byte of this register will cause a read operation to take place,
+ * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA
+ * register is read.
+ */
+union cvmx_pci_win_rd_addr
+{
+	uint64_t u64;
+	struct cvmx_pci_win_rd_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t reserved_0_47                : 48;
+#else
+	uint64_t reserved_0_47                : 48;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_pci_win_rd_addr_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t rd_addr                      : 46; /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:2]  == RSL Register Offset
+                                                              [1:0]   == x, Not Used */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t rd_addr                      : 46;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn30xx;
+	struct cvmx_pci_win_rd_addr_cn30xx    cn31xx;
+	struct cvmx_pci_win_rd_addr_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t rd_addr                      : 45; /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:3]  == RSL Register Offset
+                                                              [2:0]   == x, Not Used */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t rd_addr                      : 45;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn38xx;
+	struct cvmx_pci_win_rd_addr_cn38xx    cn38xxp2;
+	struct cvmx_pci_win_rd_addr_cn30xx    cn50xx;
+	struct cvmx_pci_win_rd_addr_cn38xx    cn58xx;
+	struct cvmx_pci_win_rd_addr_cn38xx    cn58xxp1;
+};
+typedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t;
+
+/**
+ * cvmx_pci_win_rd_data
+ *
+ * PCI_WIN_RD_DATA = PCI Window Read Data Register
+ *
+ * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR
+ * register was written.
+ */
+union cvmx_pci_win_rd_data
+{
+	uint64_t u64;
+	struct cvmx_pci_win_rd_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rd_data                      : 64; /**< The read data. */
+#else
+	uint64_t rd_data                      : 64;
+#endif
+	} s;
+	struct cvmx_pci_win_rd_data_s         cn30xx;
+	struct cvmx_pci_win_rd_data_s         cn31xx;
+	struct cvmx_pci_win_rd_data_s         cn38xx;
+	struct cvmx_pci_win_rd_data_s         cn38xxp2;
+	struct cvmx_pci_win_rd_data_s         cn50xx;
+	struct cvmx_pci_win_rd_data_s         cn58xx;
+	struct cvmx_pci_win_rd_data_s         cn58xxp1;
+};
+typedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t;
+
+/**
+ * cvmx_pci_win_wr_addr
+ *
+ * PCI_WIN_WR_ADDR = PCI Window Write Address Register
+ *
+ * Contains the address to be writen to when a write operation is started by writing the
+ * PCI_WIN_WR_DATA register (see below).
+ */
+union cvmx_pci_win_wr_addr
+{
+	uint64_t u64;
+	struct cvmx_pci_win_wr_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t wr_addr                      : 45; /**< The address that will be written to when the
+                                                         PCI_WIN_WR_DATA register is written.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:3]  == RSL Register Offset
+                                                              [2:0]   == x, Not Used */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t wr_addr                      : 45;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_pci_win_wr_addr_s         cn30xx;
+	struct cvmx_pci_win_wr_addr_s         cn31xx;
+	struct cvmx_pci_win_wr_addr_s         cn38xx;
+	struct cvmx_pci_win_wr_addr_s         cn38xxp2;
+	struct cvmx_pci_win_wr_addr_s         cn50xx;
+	struct cvmx_pci_win_wr_addr_s         cn58xx;
+	struct cvmx_pci_win_wr_addr_s         cn58xxp1;
+};
+typedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t;
+
+/**
+ * cvmx_pci_win_wr_data
+ *
+ * PCI_WIN_WR_DATA = PCI Window Write Data Register
+ *
+ * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register.
+ * Writing the least-significant-byte of this register will cause a write operation to take place.
+ */
+union cvmx_pci_win_wr_data
+{
+	uint64_t u64;
+	struct cvmx_pci_win_wr_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
+                                                         register is written, the Window Write will take
+                                                         place. */
+#else
+	uint64_t wr_data                      : 64;
+#endif
+	} s;
+	struct cvmx_pci_win_wr_data_s         cn30xx;
+	struct cvmx_pci_win_wr_data_s         cn31xx;
+	struct cvmx_pci_win_wr_data_s         cn38xx;
+	struct cvmx_pci_win_wr_data_s         cn38xxp2;
+	struct cvmx_pci_win_wr_data_s         cn50xx;
+	struct cvmx_pci_win_wr_data_s         cn58xx;
+	struct cvmx_pci_win_wr_data_s         cn58xxp1;
+};
+typedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t;
+
+/**
+ * cvmx_pci_win_wr_mask
+ *
+ * PCI_WIN_WR_MASK = PCI Window Write Mask Register
+ *
+ * Contains the mask for the data in the PCI_WIN_WR_DATA Register.
+ */
+union cvmx_pci_win_wr_mask
+{
+	uint64_t u64;
+	struct cvmx_pci_win_wr_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is set '1'
+                                                         the corresponding byte will not be written. */
+#else
+	uint64_t wr_mask                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pci_win_wr_mask_s         cn30xx;
+	struct cvmx_pci_win_wr_mask_s         cn31xx;
+	struct cvmx_pci_win_wr_mask_s         cn38xx;
+	struct cvmx_pci_win_wr_mask_s         cn38xxp2;
+	struct cvmx_pci_win_wr_mask_s         cn50xx;
+	struct cvmx_pci_win_wr_mask_s         cn58xx;
+	struct cvmx_pci_win_wr_mask_s         cn58xxp1;
+};
+typedef union cvmx_pci_win_wr_mask cvmx_pci_win_wr_mask_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pci.h b/sys/contrib/octeon-sdk/cvmx-pci.h
index 710a656..a1d9b37 100644
--- a/sys/contrib/octeon-sdk/cvmx-pci.h
+++ b/sys/contrib/octeon-sdk/cvmx-pci.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * PCI related structures.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_PCI_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.c b/sys/contrib/octeon-sdk/cvmx-pcie.c
index 21a9b87..8053737 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcie.c
+++ b/sys/contrib/octeon-sdk/cvmx-pcie.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,21 +42,56 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to PCIe as a host(RC) or target(EP)
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-ciu-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pci-defs.h>
+#include <asm/octeon/cvmx-pcieepx-defs.h>
+#include <asm/octeon/cvmx-pciercx-defs.h>
+#include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-pescx-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
+
+#ifdef CONFIG_CAVIUM_DECODE_RSL
+#include <asm/octeon/cvmx-error.h>
+#endif
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-pcie.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/cvmx-swap.h>
+#include <asm/octeon/cvmx-wqe.h>
+#else
 #include "cvmx.h"
 #include "cvmx-csr-db.h"
 #include "cvmx-pcie.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-swap.h"
 #include "cvmx-wqe.h"
+#include "cvmx-error.h"
 #include "cvmx-helper-errata.h"
+#endif
 
+#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
+#define MPS_CN5XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
+#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
+#define MPS_CN6XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
 
 /**
  * Return the Core virtual base address for PCIe IO access. IOs are
@@ -142,8 +178,16 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
     {
         cvmx_pciercx_cfg030_t pciercx_cfg030;
         pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
-        pciercx_cfg030.s.mps = 0; /* Max payload size = 128 bytes for best Octeon DMA performance */
-        pciercx_cfg030.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        {
+            pciercx_cfg030.s.mps = MPS_CN5XXX;
+            pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
+        }
+        else
+        {
+            pciercx_cfg030.s.mps = MPS_CN6XXX;
+            pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
+        }
         pciercx_cfg030.s.ro_en = 1; /* Enable relaxed order processing. This will allow devices to affect read response ordering */
         pciercx_cfg030.s.ns_en = 1; /* Enable no snoop processing. Not used by Octeon */
         pciercx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
@@ -153,15 +197,36 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
     }
 
-    /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
-    /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
+        /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
+        /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
         cvmx_npei_ctl_status2_t npei_ctl_status2;
         npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
-        npei_ctl_status2.s.mps = 0; /* Max payload size = 128 bytes for best Octeon DMA performance */
-        npei_ctl_status2.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mps = MPS_CN5XXX; /* Max payload size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mrrs = MRRS_CN5XXX; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        if (pcie_port)
+            npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+        else
+            npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
+
         cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
     }
+    else
+    {
+        /* Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match PCIE*_CFG030[MPS] */
+        /* Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+        cvmx_dpi_sli_prtx_cfg_t prt_cfg;
+        cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
+        prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
+        prt_cfg.s.mps = MPS_CN6XXX;
+        prt_cfg.s.mrrs = MRRS_CN6XXX;
+        cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
+
+        sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
+        sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
+        cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
+    }
 
     /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
     {
@@ -202,9 +267,6 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
     }
 
-    /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
-    // FIXME: Anything needed here?
-
     /* Link Width Mode (PCIERCn_CFG452[LME]) - Set during cvmx_pcie_rc_initialize_link() */
     /* Primary Bus Number (PCIERCn_CFG006[PBNUM]) */
     {
@@ -283,10 +345,9 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
     }
 }
 
-
 /**
  * @INTERNAL
- * Initialize a host mode PCIe link. This function takes a PCIe
+ * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
  * port from reset to a link up state. Software can then begin
  * configuring the rest of the link.
  *
@@ -294,7 +355,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
  *
  * @return Zero on success
  */
-static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
 {
     uint64_t start_cycle;
     cvmx_pescx_ctl_status_t pescx_ctl_status;
@@ -348,7 +409,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
     start_cycle = cvmx_get_cycle();
     do
     {
-        if (cvmx_get_cycle() - start_cycle > 2*cvmx_sysinfo_get()->cpu_clock_hz)
+        if (cvmx_get_cycle() - start_cycle > 2*cvmx_clock_get_rate(CVMX_CLOCK_CORE))
         {
             cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
             return -1;
@@ -357,6 +418,9 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
         pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
     } while (pciercx_cfg032.s.dlla == 0);
 
+    /* Clear all pending errors */
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+
     /* Update the Replay Time Limit. Empirically, some PCIe devices take a
         little longer to respond than expected under load. As a workaround for
         this we configure the Replay Time Limit to the value expected for a 512
@@ -385,15 +449,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
 
 
 /**
- * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't enumerate
+ * the bus.
  *
  * @param pcie_port PCIe port to initialize
  *
  * @return Zero on success
  */
-int cvmx_pcie_rc_initialize(int pcie_port)
+static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
 {
     int i;
+    int base;
+    uint64_t addr_swizzle;
     cvmx_ciu_soft_prst_t ciu_soft_prst;
     cvmx_pescx_bist_status_t pescx_bist_status;
     cvmx_pescx_bist_status2_t pescx_bist_status2;
@@ -403,13 +470,14 @@ int cvmx_pcie_rc_initialize(int pcie_port)
     cvmx_npei_dbg_data_t npei_dbg_data;
     cvmx_pescx_ctl_status2_t pescx_ctl_status2;
     cvmx_pciercx_cfg032_t pciercx_cfg032;
+    cvmx_npei_bar1_indexx_t bar1_index;
 
 retry:
     /* Make sure we aren't trying to setup a target mode interface in host mode */
     npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
     if ((pcie_port==0) && !npei_ctl_status.s.host_mode)
     {
-        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port0, but port0 is not in host mode\n");
+        cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
         return -1;
     }
 
@@ -554,9 +622,9 @@ retry:
     __cvmx_pcie_rc_initialize_config_space(pcie_port);
 
     /* Bring the link up */
-    if (__cvmx_pcie_rc_initialize_link(pcie_port))
+    if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port))
     {
-        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+        cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n", pcie_port);
         return -1;
     }
 
@@ -597,10 +665,29 @@ retry:
     /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
     cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
 
-    /* Disable Octeon's BAR1. It isn't needed in RC mode since BAR2
-        maps all of memory. BAR2 also maps 256MB-512MB into the 2nd
-        256MB of memory */
-    cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
+    /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
+    cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+    bar1_index.u32 = 0;
+    bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+    bar1_index.s.ca = 1;       /* Not Cached */
+    bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+    bar1_index.s.addr_v = 1;   /* Valid entry */
+
+    base = pcie_port ? 16 : 0;
+
+    /* Big endian swizzle for 32-bit PEXP_NCB register. */
+#ifdef __MIPSEB__
+    addr_swizzle = 4;
+#else
+    addr_swizzle = 0;
+#endif
+    for (i = 0; i < 16; i++) {
+        cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), bar1_index.u32);
+        base++;
+        /* 256MB / 16 >> 22 == 4 */
+        bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+    }
 
     /* Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take precedence
         where they overlap. It also overlaps with the device addresses, so
@@ -722,6 +809,315 @@ retry:
 
 
 /**
+ * @INTERNAL
+ * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
+{
+    uint64_t start_cycle;
+    cvmx_pemx_ctl_status_t pem_ctl_status;
+    cvmx_pciercx_cfg032_t pciercx_cfg032;
+    cvmx_pciercx_cfg448_t pciercx_cfg448;
+
+    /* Bring up the link */
+    pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+    pem_ctl_status.s.lnk_enb = 1;
+    cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
+
+    /* Wait for the link to come up */
+    start_cycle = cvmx_get_cycle();
+    do
+    {
+        if (cvmx_get_cycle() - start_cycle > cvmx_clock_get_rate(CVMX_CLOCK_CORE))
+            return -1;
+        cvmx_wait(10000);
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+    } while (pciercx_cfg032.s.dlla == 0);
+
+    /* Update the Replay Time Limit. Empirically, some PCIe devices take a
+        little longer to respond than expected under load. As a workaround for
+        this we configure the Replay Time Limit to the value expected for a 512
+        byte MPS instead of our actual 256 byte MPS. The numbers below are
+        directly from the PCIe spec table 3-4 */
+    pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+    switch (pciercx_cfg032.s.nlw)
+    {
+        case 1: /* 1 lane */
+            pciercx_cfg448.s.rtl = 1677;
+            break;
+        case 2: /* 2 lanes */
+            pciercx_cfg448.s.rtl = 867;
+            break;
+        case 4: /* 4 lanes */
+            pciercx_cfg448.s.rtl = 462;
+            break;
+        case 8: /* 8 lanes */
+            pciercx_cfg448.s.rtl = 258;
+            break;
+    }
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
+
+    return 0;
+}
+
+
+/**
+ * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
+ * the bus.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
+{
+    int i;
+    cvmx_ciu_soft_prst_t ciu_soft_prst;
+    cvmx_mio_rst_ctlx_t mio_rst_ctl;
+    cvmx_pemx_bar_ctl_t pemx_bar_ctl;
+    cvmx_pemx_ctl_status_t pemx_ctl_status;
+    cvmx_pemx_bist_status_t pemx_bist_status;
+    cvmx_pemx_bist_status2_t pemx_bist_status2;
+    cvmx_pciercx_cfg032_t pciercx_cfg032;
+    cvmx_pciercx_cfg515_t pciercx_cfg515;
+    cvmx_sli_ctl_portx_t sli_ctl_portx;
+    cvmx_sli_mem_access_ctl_t sli_mem_access_ctl;
+    cvmx_sli_mem_access_subidx_t mem_access_subid;
+    cvmx_mio_rst_ctlx_t mio_rst_ctlx;
+    cvmx_sriox_status_reg_t sriox_status_reg;
+    cvmx_pemx_bar1_indexx_t bar1_index;
+
+    /* Make sure this interface isn't SRIO */
+    sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
+    if (sriox_status_reg.s.srio)
+    {
+        cvmx_dprintf("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+        return -1;
+    }
+
+    /* Make sure we aren't trying to setup a target mode interface in host mode */
+    mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+    if (!mio_rst_ctl.s.host_mode)
+    {
+        cvmx_dprintf("PCIe: Port %d in endpoint mode.\n", pcie_port);
+        return -1;
+    }
+
+    /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
+    {
+        if (pcie_port)
+        {
+            cvmx_ciu_qlm1_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+        }
+        else
+        {
+            cvmx_ciu_qlm0_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+        }
+    }
+
+    /* Bring the PCIe out of reset */
+    if (pcie_port)
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+    else
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+    /* After a chip reset the PCIe will also be in reset. If it isn't,
+        most likely someone is trying to init it again without a proper
+        PCIe reset */
+    if (ciu_soft_prst.s.soft_prst == 0)
+    {
+        /* Reset the port */
+        ciu_soft_prst.s.soft_prst = 1;
+        if (pcie_port)
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+        else
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+        /* Wait until pcie resets the ports. */
+        cvmx_wait_usec(2000);
+    }
+    if (pcie_port)
+    {
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        ciu_soft_prst.s.soft_prst = 0;
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+    }
+    else
+    {
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        ciu_soft_prst.s.soft_prst = 0;
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+    }
+
+    /* Wait for PCIe reset to complete */
+    cvmx_wait_usec(1000);
+
+    /* Check and make sure PCIe came out of reset. If it doesn't the board
+        probably hasn't wired the clocks up and the interface should be
+        skipped */
+    mio_rst_ctlx.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+    if (!mio_rst_ctlx.s.rst_done)
+    {
+        cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
+        return -1;
+    }
+
+    /* Check BIST status */
+    pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
+    if (pemx_bist_status.u64)
+        cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
+    pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
+    if (pemx_bist_status2.u64)
+        cvmx_dprintf("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
+
+    /* Initialize the config space CSRs */
+    __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+    /* Enable gen2 speed selection */
+    pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
+    pciercx_cfg515.s.dsc = 1;
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
+
+    /* Bring the link up */
+    if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port))
+    {
+        /* Some gen1 devices don't handle the gen 2 training correctly. Disable
+            gen2 and try again with only gen1 */
+        cvmx_pciercx_cfg031_t pciercx_cfg031;
+        pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
+        pciercx_cfg031.s.mls = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg515.u32);
+        if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port))
+        {
+            cvmx_dprintf("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
+            return -1;
+        }
+    }
+
+    /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+    sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
+    sli_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+    sli_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
+    cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
+
+    /* Setup Mem access SubDIDs */
+    mem_access_subid.u64 = 0;
+    mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+    mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
+    mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+    mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+    mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+    mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+    mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+
+    /* Setup mem access 12-15 for port 0, 16-19 for port 1, supplying 36 bits of address space */
+    for (i=12 + pcie_port*4; i<16 + pcie_port*4; i++)
+    {
+        cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+        mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
+    }
+
+    /* Disable the peer to peer forwarding register. This must be setup
+        by the OS after it enumerates the bus and assigns addresses to the
+        PCIe busses */
+    for (i=0; i<4; i++)
+    {
+        cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
+        cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+    }
+
+    /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+    cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
+
+    /* Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take precedence
+        where they overlap. It also overlaps with the device addresses, so
+        make sure the peer to peer forwarding is set right */
+    cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
+
+    /* Setup BAR2 attributes */
+    /* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
+    /* ­ PTLP_RO,CTLP_RO should normally be set (except for debug). */
+    /* ­ WAIT_COM=0 will likely work for all applications. */
+    /* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
+    pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
+    pemx_bar_ctl.s.bar1_siz = 3;  /* 256MB BAR1*/
+    pemx_bar_ctl.s.bar2_enb = 1;
+    pemx_bar_ctl.s.bar2_esx = 1;
+    pemx_bar_ctl.s.bar2_cax = 0;
+    cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
+    sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
+    sli_ctl_portx.s.ptlp_ro = 1;
+    sli_ctl_portx.s.ctlp_ro = 1;
+    sli_ctl_portx.s.wait_com = 0;
+    sli_ctl_portx.s.waitl_com = 0;
+    cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
+
+    /* BAR1 follows BAR2 */
+    cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+    bar1_index.u64 = 0;
+    bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+    bar1_index.s.ca = 1;       /* Not Cached */
+    bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+    bar1_index.s.addr_v = 1;   /* Valid entry */
+
+    for (i = 0; i < 16; i++) {
+        cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
+        /* 256MB / 16 >> 22 == 4 */
+        bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+    }
+
+    /* Allow config retries for 250ms. Count is based off the 5Ghz SERDES
+        clock */
+    pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+    pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
+    cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
+
+    /* Display the link status */
+    pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+    cvmx_dprintf("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
+
+    return 0;
+}
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_rc_initialize(int pcie_port)
+{
+    int result;
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+        result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
+    else
+        result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(CONFIG_CAVIUM_DECODE_RSL)
+    if (result == 0)
+        cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
+#endif
+    return result;
+}
+
+
+/**
  * Shutdown a PCIe port and put it in reset
  *
  * @param pcie_port PCIe port to shutdown
@@ -730,9 +1126,20 @@ retry:
  */
 int cvmx_pcie_rc_shutdown(int pcie_port)
 {
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(CONFIG_CAVIUM_DECODE_RSL)
+    cvmx_error_disable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
+#endif
     /* Wait for all pending operations to complete */
-    if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port), cvmx_pescx_cpl_lut_valid_t, tag, ==, 0, 2000))
-        cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    {
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port), cvmx_pescx_cpl_lut_valid_t, tag, ==, 0, 2000))
+            cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
+    }
+    else
+    {
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_PEMX_CPL_LUT_VALID(pcie_port), cvmx_pemx_cpl_lut_valid_t, tag, ==, 0, 2000))
+            cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
+    }
 
     /* Force reset */
     if (pcie_port)
@@ -918,12 +1325,24 @@ void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg,
  */
 uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
 {
-    cvmx_pescx_cfg_rd_t pescx_cfg_rd;
-    pescx_cfg_rd.u64 = 0;
-    pescx_cfg_rd.s.addr = cfg_offset;
-    cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
-    pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
-    return pescx_cfg_rd.s.data;
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    {
+        cvmx_pescx_cfg_rd_t pescx_cfg_rd;
+        pescx_cfg_rd.u64 = 0;
+        pescx_cfg_rd.s.addr = cfg_offset;
+        cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+        pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+        return pescx_cfg_rd.s.data;
+    }
+    else
+    {
+        cvmx_pemx_cfg_rd_t pemx_cfg_rd;
+        pemx_cfg_rd.u64 = 0;
+        pemx_cfg_rd.s.addr = cfg_offset;
+        cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
+        pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
+        return pemx_cfg_rd.s.data;
+    }
 }
 
 
@@ -937,65 +1356,134 @@ uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
  */
 void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
 {
-    cvmx_pescx_cfg_wr_t pescx_cfg_wr;
-    pescx_cfg_wr.u64 = 0;
-    pescx_cfg_wr.s.addr = cfg_offset;
-    pescx_cfg_wr.s.data = val;
-    cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    {
+        cvmx_pescx_cfg_wr_t pescx_cfg_wr;
+        pescx_cfg_wr.u64 = 0;
+        pescx_cfg_wr.s.addr = cfg_offset;
+        pescx_cfg_wr.s.data = val;
+        cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+    }
+    else
+    {
+        cvmx_pemx_cfg_wr_t pemx_cfg_wr;
+        pemx_cfg_wr.u64 = 0;
+        pemx_cfg_wr.s.addr = cfg_offset;
+        pemx_cfg_wr.s.data = val;
+        cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
+    }
 }
 
 
 /**
  * Initialize a PCIe port for use in target(EP) mode.
  *
+ * @param pcie_port PCIe port to initialize
+ *
  * @return Zero on success
  */
-int cvmx_pcie_ep_initialize(void)
+int cvmx_pcie_ep_initialize(int pcie_port)
 {
-    int pcie_port = 0;
-    cvmx_npei_ctl_status_t npei_ctl_status;
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+    {
+        cvmx_npei_ctl_status_t npei_ctl_status;
+        npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+        if (npei_ctl_status.s.host_mode)
+            return -1;
+    }
+    else
+    {
+        cvmx_mio_rst_ctlx_t mio_rst_ctl;
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+        if (mio_rst_ctl.s.host_mode)
+            return -1;
+    }
 
-    npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
-    if (npei_ctl_status.s.host_mode)
-        return -1;
+    /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
+    {
+        if (pcie_port)
+        {
+            cvmx_ciu_qlm1_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+        }
+        else
+        {
+            cvmx_ciu_qlm0_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+        }
+    }
 
     /* Enable bus master and memory */
-    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEP_CFG001, 0x6);
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEPX_CFG001(pcie_port), 0x6);
 
     /* Max Payload Size (PCIE*_CFG030[MPS]) */
     /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
     /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
     /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
     {
-        cvmx_pciercx_cfg030_t pciercx_cfg030;
-        pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
-        pciercx_cfg030.s.mps = 0; /* Max payload size = 128 bytes (Limit of most PCs) */
-        pciercx_cfg030.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
-        pciercx_cfg030.s.ro_en = 1; /* Enable relaxed ordering. */
-        pciercx_cfg030.s.ns_en = 1; /* Enable no snoop. */
-        pciercx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
-        pciercx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
-        pciercx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
-        pciercx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
+        cvmx_pcieepx_cfg030_t pcieepx_cfg030;
+        pcieepx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port));
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+        {
+            pcieepx_cfg030.s.mps = MPS_CN5XXX;
+            pcieepx_cfg030.s.mrrs = MRRS_CN5XXX;
+        }
+        else
+        {
+            pcieepx_cfg030.s.mps = MPS_CN6XXX;
+            pcieepx_cfg030.s.mrrs = MRRS_CN6XXX;
+        }
+        pcieepx_cfg030.s.ro_en = 1; /* Enable relaxed ordering. */
+        pcieepx_cfg030.s.ns_en = 1; /* Enable no snoop. */
+        pcieepx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
+        pcieepx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
+        pcieepx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
+        pcieepx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port), pcieepx_cfg030.u32);
     }
 
-    /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
-    /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
+        /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
+        /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
         cvmx_npei_ctl_status2_t npei_ctl_status2;
         npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
-        npei_ctl_status2.s.mps = 0; /* Max payload size = 128 bytes (Limit of most PCs) */
-        npei_ctl_status2.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mps = MPS_CN5XXX; /* Max payload size = 128 bytes (Limit of most PCs) */
+        npei_ctl_status2.s.mrrs = MRRS_CN5XXX; /* Max read request size = 128 bytes for best Octeon DMA performance */
         cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
     }
+    else
+    {
+        /* Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match PCIE*_CFG030[MPS] */
+        /* Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+        cvmx_dpi_sli_prtx_cfg_t prt_cfg;
+        cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
+        prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
+        prt_cfg.s.mps = MPS_CN6XXX;
+        prt_cfg.s.mrrs = MRRS_CN6XXX;
+        cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
+
+        sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
+        sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
+        cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
+    }
 
     /* Setup Mem access SubDID 12 to access Host memory */
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
         cvmx_npei_mem_access_subidx_t mem_access_subid;
         mem_access_subid.u64 = 0;
         mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
-        mem_access_subid.s.nmerge = 1;  /* Merging is allowed in this window. */
+        mem_access_subid.s.nmerge = 1;  /* Merging is not allowed in this window. */
         mem_access_subid.s.esr = 0;     /* Endian-swap for Reads. */
         mem_access_subid.s.esw = 0;     /* Endian-swap for Writes. */
         mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
@@ -1005,6 +1493,19 @@ int cvmx_pcie_ep_initialize(void)
         mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
         cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(12), mem_access_subid.u64);
     }
+    else
+    {
+        cvmx_sli_mem_access_subidx_t mem_access_subid;
+        mem_access_subid.u64 = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 0;  /* Merging is allowed in this window. */
+        mem_access_subid.s.esr = 0;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 0;     /* Endian-swap for Writes. */
+        mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+        cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(12 + pcie_port*4), mem_access_subid.u64);
+    }
     return 0;
 }
 
@@ -1020,43 +1521,84 @@ int cvmx_pcie_ep_initialize(void)
  */
 void cvmx_pcie_wait_for_pending(int pcie_port)
 {
-    cvmx_npei_data_out_cnt_t npei_data_out_cnt;
-    int a;
-    int b;
-    int c;
-
-    /* See section 9.8, PCIe Core-initiated Requests, in the manual for a
-        description of how this code works */
-    npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
-    if (pcie_port)
+    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
-        if (!npei_data_out_cnt.s.p1_fcnt)
-            return;
-        a = npei_data_out_cnt.s.p1_ucnt;
-        b = (a + npei_data_out_cnt.s.p1_fcnt-1) & 0xffff;
+        cvmx_npei_data_out_cnt_t npei_data_out_cnt;
+        int a;
+        int b;
+        int c;
+
+        /* See section 9.8, PCIe Core-initiated Requests, in the manual for a
+            description of how this code works */
+        npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
+        if (pcie_port)
+        {
+            if (!npei_data_out_cnt.s.p1_fcnt)
+                return;
+            a = npei_data_out_cnt.s.p1_ucnt;
+            b = (a + npei_data_out_cnt.s.p1_fcnt-1) & 0xffff;
+        }
+        else
+        {
+            if (!npei_data_out_cnt.s.p0_fcnt)
+                return;
+            a = npei_data_out_cnt.s.p0_ucnt;
+            b = (a + npei_data_out_cnt.s.p0_fcnt-1) & 0xffff;
+        }
+
+        while (1)
+        {
+            npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
+            c = (pcie_port) ? npei_data_out_cnt.s.p1_ucnt : npei_data_out_cnt.s.p0_ucnt;
+            if (a<=b)
+            {
+                if ((c<a) || (c>b))
+                    return;
+            }
+            else
+            {
+                if ((c>b) && (c<a))
+                    return;
+            }
+        }
     }
     else
     {
-        if (!npei_data_out_cnt.s.p0_fcnt)
-            return;
-        a = npei_data_out_cnt.s.p0_ucnt;
-        b = (a + npei_data_out_cnt.s.p0_fcnt-1) & 0xffff;
-    }
+        cvmx_sli_data_out_cnt_t sli_data_out_cnt;
+        int a;
+        int b;
+        int c;
 
-    while (1)
-    {
-        npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
-        c = (pcie_port) ? npei_data_out_cnt.s.p1_ucnt : npei_data_out_cnt.s.p0_ucnt;
-        if (a<=b)
+        sli_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_SLI_DATA_OUT_CNT);
+        if (pcie_port)
         {
-            if ((c<a) || (c>b))
+            if (!sli_data_out_cnt.s.p1_fcnt)
                 return;
+            a = sli_data_out_cnt.s.p1_ucnt;
+            b = (a + sli_data_out_cnt.s.p1_fcnt-1) & 0xffff;
         }
         else
         {
-            if ((c>b) && (c<a))
+            if (!sli_data_out_cnt.s.p0_fcnt)
                 return;
+            a = sli_data_out_cnt.s.p0_ucnt;
+            b = (a + sli_data_out_cnt.s.p0_fcnt-1) & 0xffff;
+        }
+
+        while (1)
+        {
+            sli_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_SLI_DATA_OUT_CNT);
+            c = (pcie_port) ? sli_data_out_cnt.s.p1_ucnt : sli_data_out_cnt.s.p0_ucnt;
+            if (a<=b)
+            {
+                if ((c<a) || (c>b))
+                    return;
+            }
+            else
+            {
+                if ((c>b) && (c<a))
+                    return;
+            }
         }
     }
 }
-
diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.h b/sys/contrib/octeon-sdk/cvmx-pcie.h
index 56c108f..962150f 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcie.h
+++ b/sys/contrib/octeon-sdk/cvmx-pcie.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to PCIe as a host(RC) or target(EP)
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
 
 #ifndef __CVMX_PCIE_H__
@@ -56,6 +58,19 @@
 extern "C" {
 #endif
 
+/*
+ * The physical memory base mapped by BAR1.  256MB at the end of the
+ * first 4GB.
+ */
+#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
+#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
+
+/*
+ * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * place BAR1 so it is the same for both.
+ */
+#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+
 typedef union
 {
     uint64_t    u64;
@@ -282,9 +297,11 @@ static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
 /**
  * Initialize a PCIe port for use in target(EP) mode.
  *
+ * @param pcie_port PCIe port to initialize
+ *
  * @return Zero on success
  */
-int cvmx_pcie_ep_initialize(void);
+int cvmx_pcie_ep_initialize(int pcie_port);
 
 /**
  * Wait for posted PCIe read/writes to reach the other side of
diff --git a/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
new file mode 100644
index 0000000..6af85a1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
@@ -0,0 +1,4421 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pcieepx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcieepx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCIEEPX_TYPEDEFS_H__
+#define __CVMX_PCIEEPX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG000(block_id) (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000004ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG001(block_id) (0x0000000000000004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000008ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG002(block_id) (0x0000000000000008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000000Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG003(block_id) (0x000000000000000Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG004(block_id) (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000010ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG004_MASK(block_id) (0x0000000080000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000014ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG005(block_id) (0x0000000000000014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000014ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG005_MASK(block_id) (0x0000000080000014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000018ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG006(block_id) (0x0000000000000018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000018ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG006_MASK(block_id) (0x0000000080000018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000001Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG007(block_id) (0x000000000000001Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x000000008000001Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG007_MASK(block_id) (0x000000008000001Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000020ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG008(block_id) (0x0000000000000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000020ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG008_MASK(block_id) (0x0000000080000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000024ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG009(block_id) (0x0000000000000024ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000024ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG009_MASK(block_id) (0x0000000080000024ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000028ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG010(block_id) (0x0000000000000028ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000002Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG011(block_id) (0x000000000000002Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000030ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG012(block_id) (0x0000000000000030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000080000030ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG012_MASK(block_id) (0x0000000080000030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000034ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG013(block_id) (0x0000000000000034ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000003Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG015(block_id) (0x000000000000003Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000040ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG016(block_id) (0x0000000000000040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000044ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG017(block_id) (0x0000000000000044ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000050ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG020(block_id) (0x0000000000000050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000054ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG021(block_id) (0x0000000000000054ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000058ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG022(block_id) (0x0000000000000058ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000005Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG023(block_id) (0x000000000000005Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000070ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG028(block_id) (0x0000000000000070ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000074ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG029(block_id) (0x0000000000000074ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000078ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG030(block_id) (0x0000000000000078ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000007Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG031(block_id) (0x000000000000007Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000080ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG032(block_id) (0x0000000000000080ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG033(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG033(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000084ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG033(block_id) (0x0000000000000084ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG034(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG034(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000088ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG034(block_id) (0x0000000000000088ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000094ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG037(block_id) (0x0000000000000094ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000098ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG038(block_id) (0x0000000000000098ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000009Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG039(block_id) (0x000000000000009Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A0ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG040(block_id) (0x00000000000000A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG041(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG041(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A4ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG041(block_id) (0x00000000000000A4ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG042(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG042(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A8ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG042(block_id) (0x00000000000000A8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000100ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG064(block_id) (0x0000000000000100ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000104ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG065(block_id) (0x0000000000000104ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000108ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG066(block_id) (0x0000000000000108ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000010Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG067(block_id) (0x000000000000010Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000110ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG068(block_id) (0x0000000000000110ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000114ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG069(block_id) (0x0000000000000114ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000118ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG070(block_id) (0x0000000000000118ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000011Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG071(block_id) (0x000000000000011Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000120ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG072(block_id) (0x0000000000000120ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000124ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG073(block_id) (0x0000000000000124ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000128ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG074(block_id) (0x0000000000000128ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000700ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG448(block_id) (0x0000000000000700ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000704ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG449(block_id) (0x0000000000000704ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000708ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG450(block_id) (0x0000000000000708ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000070Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG451(block_id) (0x000000000000070Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000710ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG452(block_id) (0x0000000000000710ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000714ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG453(block_id) (0x0000000000000714ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000718ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG454(block_id) (0x0000000000000718ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000071Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG455(block_id) (0x000000000000071Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000720ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG456(block_id) (0x0000000000000720ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000728ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG458(block_id) (0x0000000000000728ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000072Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG459(block_id) (0x000000000000072Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000730ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG460(block_id) (0x0000000000000730ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000734ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG461(block_id) (0x0000000000000734ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000738ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG462(block_id) (0x0000000000000738ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000073Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG463(block_id) (0x000000000000073Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000740ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG464(block_id) (0x0000000000000740ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000744ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG465(block_id) (0x0000000000000744ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000748ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG466(block_id) (0x0000000000000748ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000074Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG467(block_id) (0x000000000000074Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000750ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG468(block_id) (0x0000000000000750ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007A8ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG490(block_id) (0x00000000000007A8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007ACull;
+}
+#else
+#define CVMX_PCIEEPX_CFG491(block_id) (0x00000000000007ACull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007B0ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG492(block_id) (0x00000000000007B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000080Cull;
+}
+#else
+#define CVMX_PCIEEPX_CFG515(block_id) (0x000000000000080Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000810ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG516(block_id) (0x0000000000000810ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000814ull;
+}
+#else
+#define CVMX_PCIEEPX_CFG517(block_id) (0x0000000000000814ull)
+#endif
+
+/**
+ * cvmx_pcieep#_cfg000
+ *
+ * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register)
+ *
+ */
+union cvmx_pcieepx_cfg000
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg000_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t devid                        : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR
+                                                          However, the application must not change this field.
+                                                         For EEPROM loads also see VENDID of this register. */
+	uint32_t vendid                       : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR
+                                                          However, the application must not change this field.
+                                                         During and EPROM Load is a value of 0xFFFF is loaded to this
+                                                         field and a value of 0xFFFF is loaded to the DEVID field of
+                                                         this register, the value will not be loaded, EEPROM load will
+                                                         stop, and the FastLinkEnable bit will be set in the
+                                                         PCIE_CFG452 register. */
+#else
+	uint32_t vendid                       : 16;
+	uint32_t devid                        : 16;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg000_s          cn52xx;
+	struct cvmx_pcieepx_cfg000_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg000_s          cn56xx;
+	struct cvmx_pcieepx_cfg000_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg000_s          cn63xx;
+	struct cvmx_pcieepx_cfg000_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;
+
+/**
+ * cvmx_pcieep#_cfg001
+ *
+ * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register)
+ *
+ */
+union cvmx_pcieepx_cfg001
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg001_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dpe                          : 1;  /**< Detected Parity Error */
+	uint32_t sse                          : 1;  /**< Signaled System Error */
+	uint32_t rma                          : 1;  /**< Received Master Abort */
+	uint32_t rta                          : 1;  /**< Received Target Abort */
+	uint32_t sta                          : 1;  /**< Signaled Target Abort */
+	uint32_t devt                         : 2;  /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t mdpe                         : 1;  /**< Master Data Parity Error */
+	uint32_t fbb                          : 1;  /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t reserved_22_22               : 1;
+	uint32_t m66                          : 1;  /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t cl                           : 1;  /**< Capabilities List
+                                                         Indicates presence of an extended capability item.
+                                                         Hardwired to 1. */
+	uint32_t i_stat                       : 1;  /**< INTx Status */
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_dis                        : 1;  /**< INTx Assertion Disable */
+	uint32_t fbbe                         : 1;  /**< Fast Back-to-Back Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t see                          : 1;  /**< SERR# Enable */
+	uint32_t ids_wcc                      : 1;  /**< IDSEL Stepping/Wait Cycle Control
+                                                         Not applicable for PCI Express. Must be hardwired to 0 */
+	uint32_t per                          : 1;  /**< Parity Error Response */
+	uint32_t vps                          : 1;  /**< VGA Palette Snoop
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t mwice                        : 1;  /**< Memory Write and Invalidate
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t scse                         : 1;  /**< Special Cycle Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t me                           : 1;  /**< Bus Master Enable */
+	uint32_t msae                         : 1;  /**< Memory Space Enable */
+	uint32_t isae                         : 1;  /**< I/O Space Enable */
+#else
+	uint32_t isae                         : 1;
+	uint32_t msae                         : 1;
+	uint32_t me                           : 1;
+	uint32_t scse                         : 1;
+	uint32_t mwice                        : 1;
+	uint32_t vps                          : 1;
+	uint32_t per                          : 1;
+	uint32_t ids_wcc                      : 1;
+	uint32_t see                          : 1;
+	uint32_t fbbe                         : 1;
+	uint32_t i_dis                        : 1;
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_stat                       : 1;
+	uint32_t cl                           : 1;
+	uint32_t m66                          : 1;
+	uint32_t reserved_22_22               : 1;
+	uint32_t fbb                          : 1;
+	uint32_t mdpe                         : 1;
+	uint32_t devt                         : 2;
+	uint32_t sta                          : 1;
+	uint32_t rta                          : 1;
+	uint32_t rma                          : 1;
+	uint32_t sse                          : 1;
+	uint32_t dpe                          : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg001_s          cn52xx;
+	struct cvmx_pcieepx_cfg001_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg001_s          cn56xx;
+	struct cvmx_pcieepx_cfg001_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg001_s          cn63xx;
+	struct cvmx_pcieepx_cfg001_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;
+
+/**
+ * cvmx_pcieep#_cfg002
+ *
+ * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register)
+ *
+ */
+union cvmx_pcieepx_cfg002
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg002_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bcc                          : 8;  /**< Base Class Code, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t sc                           : 8;  /**< Subclass Code, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pi                           : 8;  /**< Programming Interface, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t rid                          : 8;  /**< Revision ID, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t rid                          : 8;
+	uint32_t pi                           : 8;
+	uint32_t sc                           : 8;
+	uint32_t bcc                          : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg002_s          cn52xx;
+	struct cvmx_pcieepx_cfg002_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg002_s          cn56xx;
+	struct cvmx_pcieepx_cfg002_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg002_s          cn63xx;
+	struct cvmx_pcieepx_cfg002_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;
+
+/**
+ * cvmx_pcieep#_cfg003
+ *
+ * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
+ *
+ */
+union cvmx_pcieepx_cfg003
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg003_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bist                         : 8;  /**< The BIST register functions are not supported.
+                                                         All 8 bits of the BIST register are hardwired to 0. */
+	uint32_t mfd                          : 1;  /**< Multi Function Device
+                                                         The Multi Function Device bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, this is a single function device. Therefore, the
+                                                         application must not write a 1 to this bit. */
+	uint32_t chf                          : 7;  /**< Configuration Header Format
+                                                         Hardwired to 0 for type 0. */
+	uint32_t lt                           : 8;  /**< Master Latency Timer
+                                                         Not applicable for PCI Express, hardwired to 0. */
+	uint32_t cls                          : 8;  /**< Cache Line Size
+                                                         The Cache Line Size register is RW for legacy compatibility
+                                                         purposes and is not applicable to PCI Express device
+                                                         functionality.
+                                                         Writing to the Cache Line Size register does not impact
+                                                         functionality. */
+#else
+	uint32_t cls                          : 8;
+	uint32_t lt                           : 8;
+	uint32_t chf                          : 7;
+	uint32_t mfd                          : 1;
+	uint32_t bist                         : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg003_s          cn52xx;
+	struct cvmx_pcieepx_cfg003_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg003_s          cn56xx;
+	struct cvmx_pcieepx_cfg003_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg003_s          cn63xx;
+	struct cvmx_pcieepx_cfg003_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;
+
+/**
+ * cvmx_pcieep#_cfg004
+ *
+ * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low)
+ *
+ */
+union cvmx_pcieepx_cfg004
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg004_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lbab                         : 18; /**< Lower bits of the BAR 0 base address */
+	uint32_t reserved_4_13                : 10;
+	uint32_t pf                           : 1;  /**< Prefetchable
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t typ                          : 2;  /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t reserved_4_13                : 10;
+	uint32_t lbab                         : 18;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg004_s          cn52xx;
+	struct cvmx_pcieepx_cfg004_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg004_s          cn56xx;
+	struct cvmx_pcieepx_cfg004_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg004_s          cn63xx;
+	struct cvmx_pcieepx_cfg004_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;
+
+/**
+ * cvmx_pcieep#_cfg004_mask
+ *
+ * PCIE_CFG004_MASK (BAR Mask 0 - Low)
+ * The BAR 0 Mask register is invisible to host software and not readable from the application.
+ * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg004_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg004_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmask                        : 31; /**< Bar Mask Low */
+	uint32_t enb                          : 1;  /**< Bar Enable
+                                                         o 0: BAR 0 is disabled
+                                                         o 1: BAR 0 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+	uint32_t enb                          : 1;
+	uint32_t lmask                        : 31;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg004_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg004_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg004_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg004_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg004_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg004_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg005
+ *
+ * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High)
+ *
+ */
+union cvmx_pcieepx_cfg005
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg005_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ubab                         : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */
+#else
+	uint32_t ubab                         : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg005_s          cn52xx;
+	struct cvmx_pcieepx_cfg005_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg005_s          cn56xx;
+	struct cvmx_pcieepx_cfg005_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg005_s          cn63xx;
+	struct cvmx_pcieepx_cfg005_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;
+
+/**
+ * cvmx_pcieep#_cfg005_mask
+ *
+ * PCIE_CFG005_MASK = (BAR Mask 0 - High)
+ * The BAR 0 Mask register is invisible to host software and not readable from the application.
+ * The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg005_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg005_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umask                        : 32; /**< Bar Mask High */
+#else
+	uint32_t umask                        : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg005_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg005_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg005_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg005_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg005_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg005_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg006
+ *
+ * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low)
+ *
+ */
+union cvmx_pcieepx_cfg006
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg006_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lbab                         : 6;  /**< Lower bits of the BAR 1 base address */
+	uint32_t reserved_4_25                : 22;
+	uint32_t pf                           : 1;  /**< Prefetchable
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t typ                          : 2;  /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t reserved_4_25                : 22;
+	uint32_t lbab                         : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg006_s          cn52xx;
+	struct cvmx_pcieepx_cfg006_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg006_s          cn56xx;
+	struct cvmx_pcieepx_cfg006_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg006_s          cn63xx;
+	struct cvmx_pcieepx_cfg006_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;
+
+/**
+ * cvmx_pcieep#_cfg006_mask
+ *
+ * PCIE_CFG006_MASK (BAR Mask 1 - Low)
+ * The BAR 1 Mask register is invisible to host software and not readable from the application.
+ * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg006_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg006_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmask                        : 31; /**< Bar Mask Low */
+	uint32_t enb                          : 1;  /**< Bar Enable
+                                                         o 0: BAR 1 is disabled
+                                                         o 1: BAR 1 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+	uint32_t enb                          : 1;
+	uint32_t lmask                        : 31;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg006_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg006_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg006_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg006_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg006_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg006_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg007
+ *
+ * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High)
+ *
+ */
+union cvmx_pcieepx_cfg007
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg007_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ubab                         : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */
+#else
+	uint32_t ubab                         : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg007_s          cn52xx;
+	struct cvmx_pcieepx_cfg007_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg007_s          cn56xx;
+	struct cvmx_pcieepx_cfg007_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg007_s          cn63xx;
+	struct cvmx_pcieepx_cfg007_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;
+
+/**
+ * cvmx_pcieep#_cfg007_mask
+ *
+ * PCIE_CFG007_MASK (BAR Mask 1 - High)
+ * The BAR 1 Mask register is invisible to host software and not readable from the application.
+ * The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg007_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg007_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umask                        : 32; /**< Bar Mask High */
+#else
+	uint32_t umask                        : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg007_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg007_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg007_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg007_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg007_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg007_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg008
+ *
+ * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low)
+ *
+ */
+union cvmx_pcieepx_cfg008
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg008_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_4_31                : 28;
+	uint32_t pf                           : 1;  /**< Prefetchable
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t typ                          : 2;  /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mspc                         : 1;  /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mspc                         : 1;
+	uint32_t typ                          : 2;
+	uint32_t pf                           : 1;
+	uint32_t reserved_4_31                : 28;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg008_s          cn52xx;
+	struct cvmx_pcieepx_cfg008_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg008_s          cn56xx;
+	struct cvmx_pcieepx_cfg008_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg008_s          cn63xx;
+	struct cvmx_pcieepx_cfg008_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;
+
+/**
+ * cvmx_pcieep#_cfg008_mask
+ *
+ * PCIE_CFG008_MASK (BAR Mask 2 - Low)
+ * The BAR 2 Mask register is invisible to host software and not readable from the application.
+ * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg008_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg008_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmask                        : 31; /**< Bar Mask Low */
+	uint32_t enb                          : 1;  /**< Bar Enable
+                                                         o 0: BAR 2 is disabled
+                                                         o 1: BAR 2 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+	uint32_t enb                          : 1;
+	uint32_t lmask                        : 31;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg008_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg008_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg008_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg008_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg008_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg008_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg009
+ *
+ * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High)
+ *
+ */
+union cvmx_pcieepx_cfg009
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg009_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg009_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ubab                         : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */
+	uint32_t reserved_0_6                 : 7;
+#else
+	uint32_t reserved_0_6                 : 7;
+	uint32_t ubab                         : 25;
+#endif
+	} cn52xx;
+	struct cvmx_pcieepx_cfg009_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg009_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg009_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg009_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ubab                         : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */
+	uint32_t reserved_0_8                 : 9;
+#else
+	uint32_t reserved_0_8                 : 9;
+	uint32_t ubab                         : 23;
+#endif
+	} cn63xx;
+	struct cvmx_pcieepx_cfg009_cn63xx     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;
+
+/**
+ * cvmx_pcieep#_cfg009_mask
+ *
+ * PCIE_CFG009_MASK (BAR Mask 2 - High)
+ * The BAR 2 Mask register is invisible to host software and not readable from the application.
+ * The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg009_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg009_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umask                        : 32; /**< Bar Mask High */
+#else
+	uint32_t umask                        : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg009_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg009_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg009_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg009_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg009_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg009_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg010
+ *
+ * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register)
+ *
+ */
+union cvmx_pcieepx_cfg010
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg010_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t cisp                         : 32; /**< CardBus CIS Pointer
+                                                         Optional, writable through PEM(0..1)_CFG_WR. */
+#else
+	uint32_t cisp                         : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg010_s          cn52xx;
+	struct cvmx_pcieepx_cfg010_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg010_s          cn56xx;
+	struct cvmx_pcieepx_cfg010_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg010_s          cn63xx;
+	struct cvmx_pcieepx_cfg010_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;
+
+/**
+ * cvmx_pcieep#_cfg011
+ *
+ * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register)
+ *
+ */
+union cvmx_pcieepx_cfg011
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg011_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ssid                         : 16; /**< Subsystem ID
+                                                         Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR.                                                                                                           However, the application must not change this field. */
+	uint32_t ssvid                        : 16; /**< Subsystem Vendor ID
+                                                         Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t ssvid                        : 16;
+	uint32_t ssid                         : 16;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg011_s          cn52xx;
+	struct cvmx_pcieepx_cfg011_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg011_s          cn56xx;
+	struct cvmx_pcieepx_cfg011_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg011_s          cn63xx;
+	struct cvmx_pcieepx_cfg011_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;
+
+/**
+ * cvmx_pcieep#_cfg012
+ *
+ * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register)
+ *
+ */
+union cvmx_pcieepx_cfg012
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg012_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t eraddr                       : 16; /**< Expansion ROM Address */
+	uint32_t reserved_1_15                : 15;
+	uint32_t er_en                        : 1;  /**< Expansion ROM Enable */
+#else
+	uint32_t er_en                        : 1;
+	uint32_t reserved_1_15                : 15;
+	uint32_t eraddr                       : 16;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg012_s          cn52xx;
+	struct cvmx_pcieepx_cfg012_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg012_s          cn56xx;
+	struct cvmx_pcieepx_cfg012_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg012_s          cn63xx;
+	struct cvmx_pcieepx_cfg012_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;
+
+/**
+ * cvmx_pcieep#_cfg012_mask
+ *
+ * PCIE_CFG012_MASK (Exapansion ROM BAR Mask)
+ * The ROM Mask register is invisible to host software and not readable from the application.
+ * The ROM Mask register is only writable through PEM(0..1)_CFG_WR.
+ */
+union cvmx_pcieepx_cfg012_mask
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg012_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mask                         : 31; /**< Bar Mask Low                                                                 NS */
+	uint32_t enb                          : 1;  /**< Bar Enable                                                                   NS
+                                                         o 0: BAR ROM is disabled
+                                                         o 1: BAR ROM is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+	uint32_t enb                          : 1;
+	uint32_t mask                         : 31;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg012_mask_s     cn52xx;
+	struct cvmx_pcieepx_cfg012_mask_s     cn52xxp1;
+	struct cvmx_pcieepx_cfg012_mask_s     cn56xx;
+	struct cvmx_pcieepx_cfg012_mask_s     cn56xxp1;
+	struct cvmx_pcieepx_cfg012_mask_s     cn63xx;
+	struct cvmx_pcieepx_cfg012_mask_s     cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;
+
+/**
+ * cvmx_pcieep#_cfg013
+ *
+ * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register)
+ *
+ */
+union cvmx_pcieepx_cfg013
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg013_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_8_31                : 24;
+	uint32_t cp                           : 8;  /**< First Capability Pointer.
+                                                         Points to Power Management Capability structure by
+                                                         default, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t cp                           : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg013_s          cn52xx;
+	struct cvmx_pcieepx_cfg013_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg013_s          cn56xx;
+	struct cvmx_pcieepx_cfg013_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg013_s          cn63xx;
+	struct cvmx_pcieepx_cfg013_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;
+
+/**
+ * cvmx_pcieep#_cfg015
+ *
+ * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
+ *
+ */
+union cvmx_pcieepx_cfg015
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg015_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ml                           : 8;  /**< Maximum Latency     (Hardwired to 0) */
+	uint32_t mg                           : 8;  /**< Minimum Grant       (Hardwired to 0) */
+	uint32_t inta                         : 8;  /**< Interrupt Pin
+                                                         Identifies the legacy interrupt Message that the device
+                                                         (or device function) uses.
+                                                         The Interrupt Pin register is writable through PEM(0..1)_CFG_WR.
+                                                         In a single-function configuration, only INTA is used.
+                                                         Therefore, the application must not change this field. */
+	uint32_t il                           : 8;  /**< Interrupt Line */
+#else
+	uint32_t il                           : 8;
+	uint32_t inta                         : 8;
+	uint32_t mg                           : 8;
+	uint32_t ml                           : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg015_s          cn52xx;
+	struct cvmx_pcieepx_cfg015_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg015_s          cn56xx;
+	struct cvmx_pcieepx_cfg015_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg015_s          cn63xx;
+	struct cvmx_pcieepx_cfg015_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;
+
+/**
+ * cvmx_pcieep#_cfg016
+ *
+ * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space
+ * (Power Management Capability ID/
+ * Power Management Next Item Pointer/
+ * Power Management Capabilities Register)
+ */
+union cvmx_pcieepx_cfg016
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg016_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmes                         : 5;  /**< PME_Support
+                                                         o Bit 11: If set, PME Messages can be generated from D0
+                                                         o Bit 12: If set, PME Messages can be generated from D1
+                                                         o Bit 13: If set, PME Messages can be generated from D2
+                                                         o Bit 14: If set, PME Messages can be generated from D3hot
+                                                         o Bit 15: If set, PME Messages can be generated from D3cold
+                                                         The PME_Support field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t d2s                          : 1;  /**< D2 Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t d1s                          : 1;  /**< D1 Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t auxc                         : 3;  /**< AUX Current, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t dsi                          : 1;  /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t pme_clock                    : 1;  /**< PME Clock, hardwired to 0 */
+	uint32_t pmsv                         : 3;  /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to the MSI capabilities by default, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t pmcid                        : 8;  /**< Power Management Capability ID */
+#else
+	uint32_t pmcid                        : 8;
+	uint32_t ncp                          : 8;
+	uint32_t pmsv                         : 3;
+	uint32_t pme_clock                    : 1;
+	uint32_t reserved_20_20               : 1;
+	uint32_t dsi                          : 1;
+	uint32_t auxc                         : 3;
+	uint32_t d1s                          : 1;
+	uint32_t d2s                          : 1;
+	uint32_t pmes                         : 5;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg016_s          cn52xx;
+	struct cvmx_pcieepx_cfg016_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg016_s          cn56xx;
+	struct cvmx_pcieepx_cfg016_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg016_s          cn63xx;
+	struct cvmx_pcieepx_cfg016_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;
+
+/**
+ * cvmx_pcieep#_cfg017
+ *
+ * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register)
+ *
+ */
+union cvmx_pcieepx_cfg017
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg017_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmdia                        : 8;  /**< Data register for additional information (not supported) */
+	uint32_t bpccee                       : 1;  /**< Bus Power/Clock Control Enable, hardwired to 0 */
+	uint32_t bd3h                         : 1;  /**< B2/B3 Support, hardwired to 0 */
+	uint32_t reserved_16_21               : 6;
+	uint32_t pmess                        : 1;  /**< PME Status
+                                                         Indicates if a previously enabled PME event occurred or not. */
+	uint32_t pmedsia                      : 2;  /**< Data Scale (not supported) */
+	uint32_t pmds                         : 4;  /**< Data Select (not supported) */
+	uint32_t pmeens                       : 1;  /**< PME Enable
+                                                         A value of 1 indicates that the device is enabled to
+                                                         generate PME. */
+	uint32_t reserved_4_7                 : 4;
+	uint32_t nsr                          : 1;  /**< No Soft Reset, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t ps                           : 2;  /**< Power State
+                                                         Controls the device power state:
+                                                           o 00b: D0
+                                                           o 01b: D1
+                                                           o 10b: D2
+                                                           o 11b: D3
+                                                         The written value is ignored if the specific state is
+                                                         not supported. */
+#else
+	uint32_t ps                           : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t nsr                          : 1;
+	uint32_t reserved_4_7                 : 4;
+	uint32_t pmeens                       : 1;
+	uint32_t pmds                         : 4;
+	uint32_t pmedsia                      : 2;
+	uint32_t pmess                        : 1;
+	uint32_t reserved_16_21               : 6;
+	uint32_t bd3h                         : 1;
+	uint32_t bpccee                       : 1;
+	uint32_t pmdia                        : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg017_s          cn52xx;
+	struct cvmx_pcieepx_cfg017_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg017_s          cn56xx;
+	struct cvmx_pcieepx_cfg017_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg017_s          cn63xx;
+	struct cvmx_pcieepx_cfg017_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;
+
+/**
+ * cvmx_pcieep#_cfg020
+ *
+ * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space
+ * (MSI Capability ID/
+ *  MSI Next Item Pointer/
+ *  MSI Control Register)
+ */
+union cvmx_pcieepx_cfg020
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg020_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mme                          : 3;  /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+	uint32_t mmc                          : 3;  /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t msien                        : 1;  /**< MSI Enabled
+                                                         When set, INTx must be disabled. */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t msicid                       : 8;  /**< MSI Capability ID */
+#else
+	uint32_t msicid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t msien                        : 1;
+	uint32_t mmc                          : 3;
+	uint32_t mme                          : 3;
+	uint32_t m64                          : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg020_s          cn52xx;
+	struct cvmx_pcieepx_cfg020_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg020_s          cn56xx;
+	struct cvmx_pcieepx_cfg020_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg020_s          cn63xx;
+	struct cvmx_pcieepx_cfg020_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;
+
+/**
+ * cvmx_pcieep#_cfg021
+ *
+ * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register)
+ *
+ */
+union cvmx_pcieepx_cfg021
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg021_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmsi                         : 30; /**< Lower 32-bit Address */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t lmsi                         : 30;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg021_s          cn52xx;
+	struct cvmx_pcieepx_cfg021_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg021_s          cn56xx;
+	struct cvmx_pcieepx_cfg021_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg021_s          cn63xx;
+	struct cvmx_pcieepx_cfg021_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;
+
+/**
+ * cvmx_pcieep#_cfg022
+ *
+ * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register)
+ *
+ */
+union cvmx_pcieepx_cfg022
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg022_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umsi                         : 32; /**< Upper 32-bit Address */
+#else
+	uint32_t umsi                         : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg022_s          cn52xx;
+	struct cvmx_pcieepx_cfg022_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg022_s          cn56xx;
+	struct cvmx_pcieepx_cfg022_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg022_s          cn63xx;
+	struct cvmx_pcieepx_cfg022_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;
+
+/**
+ * cvmx_pcieep#_cfg023
+ *
+ * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register)
+ *
+ */
+union cvmx_pcieepx_cfg023
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg023_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t msimd                        : 16; /**< MSI Data
+                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
+                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
+#else
+	uint32_t msimd                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg023_s          cn52xx;
+	struct cvmx_pcieepx_cfg023_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg023_s          cn56xx;
+	struct cvmx_pcieepx_cfg023_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg023_s          cn63xx;
+	struct cvmx_pcieepx_cfg023_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;
+
+/**
+ * cvmx_pcieep#_cfg028
+ *
+ * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space
+ * (PCI Express Capabilities List Register/
+ *  PCI Express Capabilities Register)
+ */
+union cvmx_pcieepx_cfg028
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg028_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t imn                          : 5;  /**< Interrupt Message Number
+                                                         Updated by hardware, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t si                           : 1;  /**< Slot Implemented
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, it must be 0 for
+                                                         an Endpoint device. Therefore, the application must not write a
+                                                         1 to this bit. */
+	uint32_t dpt                          : 4;  /**< Device Port Type */
+	uint32_t pciecv                       : 4;  /**< PCI Express Capability Version */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t pcieid                       : 8;  /**< PCIE Capability ID */
+#else
+	uint32_t pcieid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t pciecv                       : 4;
+	uint32_t dpt                          : 4;
+	uint32_t si                           : 1;
+	uint32_t imn                          : 5;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg028_s          cn52xx;
+	struct cvmx_pcieepx_cfg028_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg028_s          cn56xx;
+	struct cvmx_pcieepx_cfg028_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg028_s          cn63xx;
+	struct cvmx_pcieepx_cfg028_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;
+
+/**
+ * cvmx_pcieep#_cfg029
+ *
+ * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register)
+ *
+ */
+union cvmx_pcieepx_cfg029
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg029_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_28_31               : 4;
+	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
+                                                         From Message from RC, upstream port only. */
+	uint32_t csplv                        : 8;  /**< Captured Slot Power Limit Value
+                                                         From Message from RC, upstream port only. */
+	uint32_t reserved_16_17               : 2;
+	uint32_t rber                         : 1;  /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_12_14               : 3;
+	uint32_t el1al                        : 3;  /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t el0al                        : 3;  /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t etfs                         : 1;  /**< Extended Tag Field Supported
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application
+                                                         must not write a 1 to this bit. */
+	uint32_t pfs                          : 2;  /**< Phantom Function Supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+	uint32_t mpss                         : 3;  /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mpss                         : 3;
+	uint32_t pfs                          : 2;
+	uint32_t etfs                         : 1;
+	uint32_t el0al                        : 3;
+	uint32_t el1al                        : 3;
+	uint32_t reserved_12_14               : 3;
+	uint32_t rber                         : 1;
+	uint32_t reserved_16_17               : 2;
+	uint32_t csplv                        : 8;
+	uint32_t cspls                        : 2;
+	uint32_t reserved_28_31               : 4;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg029_s          cn52xx;
+	struct cvmx_pcieepx_cfg029_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg029_s          cn56xx;
+	struct cvmx_pcieepx_cfg029_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg029_s          cn63xx;
+	struct cvmx_pcieepx_cfg029_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;
+
+/**
+ * cvmx_pcieep#_cfg030
+ *
+ * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space
+ * (Device Control Register/Device Status Register)
+ */
+union cvmx_pcieepx_cfg030
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg030_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_22_31               : 10;
+	uint32_t tp                           : 1;  /**< Transaction Pending
+                                                         Set to 1 when Non-Posted Requests are not yet completed
+                                                         and clear when they are completed. */
+	uint32_t ap_d                         : 1;  /**< Aux Power Detected
+                                                         Set to 1 if Aux power detected. */
+	uint32_t ur_d                         : 1;  /**< Unsupported Request Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         UR_D occurs when we receive something we don't support.
+                                                         Unsupported requests are Nonfatal errors, so UR_D should
+                                                         cause NFE_D.  Receiving a  vendor defined message should
+                                                         cause an unsupported request. */
+	uint32_t fe_d                         : 1;  /**< Fatal Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
+                                                         has a severity set to Fatal.  Malformed TLP's generally fit
+                                                         into this category. */
+	uint32_t nfe_d                        : 1;  /**< Non-Fatal Error detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
+                                                         that has a severity set to Nonfatal and does NOT meet Advisory
+                                                         Nonfatal criteria , which
+                                                         most poisoned TLP's should be. */
+	uint32_t ce_d                         : 1;  /**< Correctable Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
+                                                         for example a Replay Timer Timeout.  Also, it can be set if
+                                                         we get any of the errors in PCIE_CFG066 that has a severity
+                                                         set to Nonfatal and meets the Advisory Nonfatal criteria,
+                                                         which most ECRC errors
+                                                         should be. */
+	uint32_t reserved_15_15               : 1;
+	uint32_t mrrs                         : 3;  /**< Max Read Request Size
+                                                          0 = 128B
+                                                          1 = 256B
+                                                          2 = 512B
+                                                          3 = 1024B
+                                                          4 = 2048B
+                                                          5 = 4096B
+                                                         Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and
+                                                               also must be set properly.
+                                                               SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must
+                                                               not exceed the desired max read request size. */
+	uint32_t ns_en                        : 1;  /**< Enable No Snoop */
+	uint32_t ap_en                        : 1;  /**< AUX Power PM Enable */
+	uint32_t pf_en                        : 1;  /**< Phantom Function Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         phantom functions. */
+	uint32_t etf_en                       : 1;  /**< Extended Tag Field Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         extended tags. */
+	uint32_t mps                          : 3;  /**< Max Payload Size
+                                                          Legal values:
+                                                           0  = 128B
+                                                           1  = 256B
+                                                          Larger sizes not supported by OCTEON.
+                                                         Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same
+                                                               value for proper functionality. */
+	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering */
+	uint32_t ur_en                        : 1;  /**< Unsupported Request Reporting Enable */
+	uint32_t fe_en                        : 1;  /**< Fatal Error Reporting Enable */
+	uint32_t nfe_en                       : 1;  /**< Non-Fatal Error Reporting Enable */
+	uint32_t ce_en                        : 1;  /**< Correctable Error Reporting Enable */
+#else
+	uint32_t ce_en                        : 1;
+	uint32_t nfe_en                       : 1;
+	uint32_t fe_en                        : 1;
+	uint32_t ur_en                        : 1;
+	uint32_t ro_en                        : 1;
+	uint32_t mps                          : 3;
+	uint32_t etf_en                       : 1;
+	uint32_t pf_en                        : 1;
+	uint32_t ap_en                        : 1;
+	uint32_t ns_en                        : 1;
+	uint32_t mrrs                         : 3;
+	uint32_t reserved_15_15               : 1;
+	uint32_t ce_d                         : 1;
+	uint32_t nfe_d                        : 1;
+	uint32_t fe_d                         : 1;
+	uint32_t ur_d                         : 1;
+	uint32_t ap_d                         : 1;
+	uint32_t tp                           : 1;
+	uint32_t reserved_22_31               : 10;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg030_s          cn52xx;
+	struct cvmx_pcieepx_cfg030_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg030_s          cn56xx;
+	struct cvmx_pcieepx_cfg030_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg030_s          cn63xx;
+	struct cvmx_pcieepx_cfg030_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;
+
+/**
+ * cvmx_pcieep#_cfg031
+ *
+ * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space
+ * (Link Capabilities Register)
+ */
+union cvmx_pcieepx_cfg031
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg031_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pnum                         : 8;  /**< Port Number, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
+	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable */
+	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t cpm                          : 1;  /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l1el                         : 3;  /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l0el                         : 3;  /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t aslpms                       : 2;  /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mlw                          : 6;  /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */
+	uint32_t mls                          : 4;  /**< Maximum Link Speed
+                                                         The following values are accepted:
+                                                         0001b: 2.5 GHz supported
+                                                         0010b: 5.0 GHz and 2.5 GHz supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mls                          : 4;
+	uint32_t mlw                          : 6;
+	uint32_t aslpms                       : 2;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t cpm                          : 1;
+	uint32_t sderc                        : 1;
+	uint32_t dllarc                       : 1;
+	uint32_t lbnc                         : 1;
+	uint32_t reserved_22_23               : 2;
+	uint32_t pnum                         : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg031_s          cn52xx;
+	struct cvmx_pcieepx_cfg031_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg031_s          cn56xx;
+	struct cvmx_pcieepx_cfg031_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg031_s          cn63xx;
+	struct cvmx_pcieepx_cfg031_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;
+
+/**
+ * cvmx_pcieep#_cfg032
+ *
+ * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space
+ * (Link Control Register/Link Status Register)
+ */
+union cvmx_pcieepx_cfg032
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg032_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t dlla                         : 1;  /**< Data Link Layer Active
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t scc                          : 1;  /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector.
+                                                         Writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t lt                           : 1;  /**< Link Training
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t reserved_26_26               : 1;
+	uint32_t nlw                          : 6;  /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization. */
+	uint32_t ls                           : 4;  /**< Link Speed
+                                                         The negotiated Link speed: 2.5 Gbps */
+	uint32_t reserved_10_15               : 6;
+	uint32_t hawd                         : 1;  /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+	uint32_t ecpm                         : 1;  /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+	uint32_t es                           : 1;  /**< Extended Synch */
+	uint32_t ccc                          : 1;  /**< Common Clock Configuration */
+	uint32_t rl                           : 1;  /**< Retrain Link
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t ld                           : 1;  /**< Link Disable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t rcb                          : 1;  /**< Read Completion Boundary (RCB) */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t aslpc                        : 2;  /**< Active State Link PM Control */
+#else
+	uint32_t aslpc                        : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t rcb                          : 1;
+	uint32_t ld                           : 1;
+	uint32_t rl                           : 1;
+	uint32_t ccc                          : 1;
+	uint32_t es                           : 1;
+	uint32_t ecpm                         : 1;
+	uint32_t hawd                         : 1;
+	uint32_t reserved_10_15               : 6;
+	uint32_t ls                           : 4;
+	uint32_t nlw                          : 6;
+	uint32_t reserved_26_26               : 1;
+	uint32_t lt                           : 1;
+	uint32_t scc                          : 1;
+	uint32_t dlla                         : 1;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg032_s          cn52xx;
+	struct cvmx_pcieepx_cfg032_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg032_s          cn56xx;
+	struct cvmx_pcieepx_cfg032_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg032_s          cn63xx;
+	struct cvmx_pcieepx_cfg032_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;
+
+/**
+ * cvmx_pcieep#_cfg033
+ *
+ * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space
+ * (Slot Capabilities Register)
+ */
+union cvmx_pcieepx_cfg033
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg033_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ps_num                       : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t nccs                         : 1;  /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t emip                         : 1;  /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t sp_ls                        : 2;  /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t sp_lv                        : 8;  /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t hp_c                         : 1;  /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t hp_s                         : 1;  /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pip                          : 1;  /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t aip                          : 1;  /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mrlsp                        : 1;  /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pcp                          : 1;  /**< Power Controller Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t abp                          : 1;  /**< Attention Button Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t abp                          : 1;
+	uint32_t pcp                          : 1;
+	uint32_t mrlsp                        : 1;
+	uint32_t aip                          : 1;
+	uint32_t pip                          : 1;
+	uint32_t hp_s                         : 1;
+	uint32_t hp_c                         : 1;
+	uint32_t sp_lv                        : 8;
+	uint32_t sp_ls                        : 2;
+	uint32_t emip                         : 1;
+	uint32_t nccs                         : 1;
+	uint32_t ps_num                       : 13;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg033_s          cn52xx;
+	struct cvmx_pcieepx_cfg033_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg033_s          cn56xx;
+	struct cvmx_pcieepx_cfg033_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg033_s          cn63xx;
+	struct cvmx_pcieepx_cfg033_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t;
+
+/**
+ * cvmx_pcieep#_cfg034
+ *
+ * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space
+ * (Slot Control Register/Slot Status Register)
+ */
+union cvmx_pcieepx_cfg034
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg034_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_25_31               : 7;
+	uint32_t dlls_c                       : 1;  /**< Data Link Layer State Changed
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t emis                         : 1;  /**< Electromechanical Interlock Status */
+	uint32_t pds                          : 1;  /**< Presence Detect State */
+	uint32_t mrlss                        : 1;  /**< MRL Sensor State */
+	uint32_t ccint_d                      : 1;  /**< Command Completed */
+	uint32_t pd_c                         : 1;  /**< Presence Detect Changed */
+	uint32_t mrls_c                       : 1;  /**< MRL Sensor Changed */
+	uint32_t pf_d                         : 1;  /**< Power Fault Detected */
+	uint32_t abp_d                        : 1;  /**< Attention Button Pressed */
+	uint32_t reserved_13_15               : 3;
+	uint32_t dlls_en                      : 1;  /**< Data Link Layer State Changed Enable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+	uint32_t emic                         : 1;  /**< Electromechanical Interlock Control */
+	uint32_t pcc                          : 1;  /**< Power Controller Control */
+	uint32_t pic                          : 2;  /**< Power Indicator Control */
+	uint32_t aic                          : 2;  /**< Attention Indicator Control */
+	uint32_t hpint_en                     : 1;  /**< Hot-Plug Interrupt Enable */
+	uint32_t ccint_en                     : 1;  /**< Command Completed Interrupt Enable */
+	uint32_t pd_en                        : 1;  /**< Presence Detect Changed Enable */
+	uint32_t mrls_en                      : 1;  /**< MRL Sensor Changed Enable */
+	uint32_t pf_en                        : 1;  /**< Power Fault Detected Enable */
+	uint32_t abp_en                       : 1;  /**< Attention Button Pressed Enable */
+#else
+	uint32_t abp_en                       : 1;
+	uint32_t pf_en                        : 1;
+	uint32_t mrls_en                      : 1;
+	uint32_t pd_en                        : 1;
+	uint32_t ccint_en                     : 1;
+	uint32_t hpint_en                     : 1;
+	uint32_t aic                          : 2;
+	uint32_t pic                          : 2;
+	uint32_t pcc                          : 1;
+	uint32_t emic                         : 1;
+	uint32_t dlls_en                      : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t abp_d                        : 1;
+	uint32_t pf_d                         : 1;
+	uint32_t mrls_c                       : 1;
+	uint32_t pd_c                         : 1;
+	uint32_t ccint_d                      : 1;
+	uint32_t mrlss                        : 1;
+	uint32_t pds                          : 1;
+	uint32_t emis                         : 1;
+	uint32_t dlls_c                       : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg034_s          cn52xx;
+	struct cvmx_pcieepx_cfg034_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg034_s          cn56xx;
+	struct cvmx_pcieepx_cfg034_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg034_s          cn63xx;
+	struct cvmx_pcieepx_cfg034_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t;
+
+/**
+ * cvmx_pcieep#_cfg037
+ *
+ * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space
+ * (Device Capabilities 2 Register)
+ */
+union cvmx_pcieepx_cfg037
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg037_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported
+                                                         Value of 0 indicates that Completion Timeout Programming
+                                                         is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg037_s          cn52xx;
+	struct cvmx_pcieepx_cfg037_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg037_s          cn56xx;
+	struct cvmx_pcieepx_cfg037_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg037_s          cn63xx;
+	struct cvmx_pcieepx_cfg037_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;
+
+/**
+ * cvmx_pcieep#_cfg038
+ *
+ * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space
+ * (Device Control 2 Register/Device Status 2 Register)
+ */
+union cvmx_pcieepx_cfg038
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg038_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg038_s          cn52xx;
+	struct cvmx_pcieepx_cfg038_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg038_s          cn56xx;
+	struct cvmx_pcieepx_cfg038_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg038_s          cn63xx;
+	struct cvmx_pcieepx_cfg038_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;
+
+/**
+ * cvmx_pcieep#_cfg039
+ *
+ * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space
+ * (Link Capabilities 2 Register)
+ */
+union cvmx_pcieepx_cfg039
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg039_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg039_s          cn52xx;
+	struct cvmx_pcieepx_cfg039_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg039_s          cn56xx;
+	struct cvmx_pcieepx_cfg039_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg039_s          cn63xx;
+	struct cvmx_pcieepx_cfg039_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;
+
+/**
+ * cvmx_pcieep#_cfg040
+ *
+ * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space
+ * (Link Control 2 Register/Link Status 2 Register)
+ */
+union cvmx_pcieepx_cfg040
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg040_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_17_31               : 15;
+	uint32_t cdl                          : 1;  /**< Current De-emphasis Level
+                                                         When the Link is operating at 5 GT/s speed, this bit
+                                                         reflects the level of de-emphasis. Encodings:
+                                                          1b: -3.5 dB
+                                                          0b: -6 dB
+                                                         Note: The value in this bit is undefined when the Link is
+                                                         operating at 2.5 GT/s speed */
+	uint32_t reserved_13_15               : 3;
+	uint32_t cde                          : 1;  /**< Compliance De-emphasis
+                                                         This bit sets the de-emphasis level in Polling. Compliance
+                                                         state if the entry occurred due to the Tx Compliance
+                                                         Receive bit being 1b. Encodings:
+                                                          1b: -3.5 dB
+                                                          0b: -6 dB
+                                                         Note: When the Link is operating at 2.5 GT/s, the setting
+                                                         of this bit has no effect. */
+	uint32_t csos                         : 1;  /**< Compliance SOS
+                                                         When set to 1b, the LTSSM is required to send SKP
+                                                         Ordered Sets periodically in between the (modified)
+                                                         compliance patterns.
+                                                         Note: When the Link is operating at 2.5 GT/s, the setting
+                                                         of this bit has no effect. */
+	uint32_t emc                          : 1;  /**< Enter Modified Compliance
+                                                         When this bit is set to 1b, the device transmits a modified
+                                                         compliance pattern if the LTSSM enters Polling.
+                                                         Compliance state. */
+	uint32_t tm                           : 3;  /**< Transmit Margin
+                                                         This field controls the value of the non-de-emphasized
+                                                         voltage level at the Transmitter pins:
+                                                          - 000: 800-1200 mV for full swing 400-600 mV for half-swing
+                                                          - 001-010: values must be monotonic with a non-zero slope
+                                                          - 011: 200-400 mV for full-swing and 100-200 mV for halfswing
+                                                          - 100-111: reserved
+                                                         This field is reset to 000b on entry to the LTSSM Polling.
+                                                         Compliance substate.
+                                                         When operating in 5.0 GT/s mode with full swing, the
+                                                         de-emphasis ratio must be maintained within +/- 1 dB
+                                                         from the specification-defined operational value
+                                                         either -3.5 or -6 dB). */
+	uint32_t sde                          : 1;  /**< Selectable De-emphasis
+                                                         Not applicable for an upstream Port or Endpoint device.
+                                                         Hardwired to 0. */
+	uint32_t hasd                         : 1;  /**< Hardware Autonomous Speed Disable
+                                                         When asserted, the
+                                                         application must disable hardware from changing the Link
+                                                         speed for device-specific reasons other than attempting to
+                                                         correct unreliable Link operation by reducing Link speed.
+                                                         Initial transition to the highest supported common link
+                                                         speed is not blocked by this signal. */
+	uint32_t ec                           : 1;  /**< Enter Compliance
+                                                         Software is permitted to force a link to enter Compliance
+                                                         mode at the speed indicated in the Target Link Speed
+                                                         field by setting this bit to 1b in both components on a link
+                                                         and then initiating a hot reset on the link. */
+	uint32_t tls                          : 4;  /**< Target Link Speed
+                                                         For Downstream ports, this field sets an upper limit on link
+                                                         operational speed by restricting the values advertised by
+                                                         the upstream component in its training sequences:
+                                                           - 0001: 2.5Gb/s Target Link Speed
+                                                           - 0010: 5Gb/s Target Link Speed
+                                                         All other encodings are reserved.
+                                                         If a value is written to this field that does not correspond to
+                                                         a speed included in the Supported Link Speeds field, the
+                                                         result is undefined.
+                                                         For both Upstream and Downstream ports, this field is
+                                                         used to set the target compliance mode speed when
+                                                         software is using the Enter Compliance bit to force a link
+                                                         into compliance mode.
+                                                         Out of reset this will have a value of 1 or 2 which is
+                                                         selected by qlmCfgx[1]. */
+#else
+	uint32_t tls                          : 4;
+	uint32_t ec                           : 1;
+	uint32_t hasd                         : 1;
+	uint32_t sde                          : 1;
+	uint32_t tm                           : 3;
+	uint32_t emc                          : 1;
+	uint32_t csos                         : 1;
+	uint32_t cde                          : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t cdl                          : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg040_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} cn52xx;
+	struct cvmx_pcieepx_cfg040_cn52xx     cn52xxp1;
+	struct cvmx_pcieepx_cfg040_cn52xx     cn56xx;
+	struct cvmx_pcieepx_cfg040_cn52xx     cn56xxp1;
+	struct cvmx_pcieepx_cfg040_s          cn63xx;
+	struct cvmx_pcieepx_cfg040_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;
+
+/**
+ * cvmx_pcieep#_cfg041
+ *
+ * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space
+ * (Slot Capabilities 2 Register)
+ */
+union cvmx_pcieepx_cfg041
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg041_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg041_s          cn52xx;
+	struct cvmx_pcieepx_cfg041_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg041_s          cn56xx;
+	struct cvmx_pcieepx_cfg041_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg041_s          cn63xx;
+	struct cvmx_pcieepx_cfg041_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t;
+
+/**
+ * cvmx_pcieep#_cfg042
+ *
+ * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space
+ * (Slot Control 2 Register/Slot Status 2 Register)
+ */
+union cvmx_pcieepx_cfg042
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg042_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg042_s          cn52xx;
+	struct cvmx_pcieepx_cfg042_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg042_s          cn56xx;
+	struct cvmx_pcieepx_cfg042_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg042_s          cn63xx;
+	struct cvmx_pcieepx_cfg042_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t;
+
+/**
+ * cvmx_pcieep#_cfg064
+ *
+ * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space
+ * (PCI Express Enhanced Capability Header)
+ */
+union cvmx_pcieepx_cfg064
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg064_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t nco                          : 12; /**< Next Capability Offset */
+	uint32_t cv                           : 4;  /**< Capability Version */
+	uint32_t pcieec                       : 16; /**< PCIE Express Extended Capability */
+#else
+	uint32_t pcieec                       : 16;
+	uint32_t cv                           : 4;
+	uint32_t nco                          : 12;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg064_s          cn52xx;
+	struct cvmx_pcieepx_cfg064_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg064_s          cn56xx;
+	struct cvmx_pcieepx_cfg064_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg064_s          cn63xx;
+	struct cvmx_pcieepx_cfg064_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;
+
+/**
+ * cvmx_pcieep#_cfg065
+ *
+ * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Status Register)
+ */
+union cvmx_pcieepx_cfg065
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg065_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg065_s          cn52xx;
+	struct cvmx_pcieepx_cfg065_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg065_s          cn56xx;
+	struct cvmx_pcieepx_cfg065_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg065_s          cn63xx;
+	struct cvmx_pcieepx_cfg065_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;
+
+/**
+ * cvmx_pcieep#_cfg066
+ *
+ * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Mask Register)
+ */
+union cvmx_pcieepx_cfg066
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg066_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg066_s          cn52xx;
+	struct cvmx_pcieepx_cfg066_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg066_s          cn56xx;
+	struct cvmx_pcieepx_cfg066_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg066_s          cn63xx;
+	struct cvmx_pcieepx_cfg066_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;
+
+/**
+ * cvmx_pcieep#_cfg067
+ *
+ * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Severity Register)
+ */
+union cvmx_pcieepx_cfg067
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg067_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg067_s          cn52xx;
+	struct cvmx_pcieepx_cfg067_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg067_s          cn56xx;
+	struct cvmx_pcieepx_cfg067_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg067_s          cn63xx;
+	struct cvmx_pcieepx_cfg067_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;
+
+/**
+ * cvmx_pcieep#_cfg068
+ *
+ * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space
+ * (Correctable Error Status Register)
+ */
+union cvmx_pcieepx_cfg068
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg068_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
+	uint32_t rtts                         : 1;  /**< Reply Timer Timeout Status */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrs                         : 1;  /**< REPLAY_NUM Rollover Status */
+	uint32_t bdllps                       : 1;  /**< Bad DLLP Status */
+	uint32_t btlps                        : 1;  /**< Bad TLP Status */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t res                          : 1;  /**< Receiver Error Status */
+#else
+	uint32_t res                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlps                        : 1;
+	uint32_t bdllps                       : 1;
+	uint32_t rnrs                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rtts                         : 1;
+	uint32_t anfes                        : 1;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg068_s          cn52xx;
+	struct cvmx_pcieepx_cfg068_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg068_s          cn56xx;
+	struct cvmx_pcieepx_cfg068_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg068_s          cn63xx;
+	struct cvmx_pcieepx_cfg068_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;
+
+/**
+ * cvmx_pcieep#_cfg069
+ *
+ * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space
+ * (Correctable Error Mask Register)
+ */
+union cvmx_pcieepx_cfg069
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg069_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
+	uint32_t rttm                         : 1;  /**< Reply Timer Timeout Mask */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrm                         : 1;  /**< REPLAY_NUM Rollover Mask */
+	uint32_t bdllpm                       : 1;  /**< Bad DLLP Mask */
+	uint32_t btlpm                        : 1;  /**< Bad TLP Mask */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t rem                          : 1;  /**< Receiver Error Mask */
+#else
+	uint32_t rem                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlpm                        : 1;
+	uint32_t bdllpm                       : 1;
+	uint32_t rnrm                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rttm                         : 1;
+	uint32_t anfem                        : 1;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg069_s          cn52xx;
+	struct cvmx_pcieepx_cfg069_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg069_s          cn56xx;
+	struct cvmx_pcieepx_cfg069_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg069_s          cn63xx;
+	struct cvmx_pcieepx_cfg069_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;
+
+/**
+ * cvmx_pcieep#_cfg070
+ *
+ * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space
+ * (Advanced Error Capabilities and Control Register)
+ */
+union cvmx_pcieepx_cfg070
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg070_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t ce                           : 1;  /**< ECRC Check Enable */
+	uint32_t cc                           : 1;  /**< ECRC Check Capable */
+	uint32_t ge                           : 1;  /**< ECRC Generation Enable */
+	uint32_t gc                           : 1;  /**< ECRC Generation Capability */
+	uint32_t fep                          : 5;  /**< First Error Pointer */
+#else
+	uint32_t fep                          : 5;
+	uint32_t gc                           : 1;
+	uint32_t ge                           : 1;
+	uint32_t cc                           : 1;
+	uint32_t ce                           : 1;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg070_s          cn52xx;
+	struct cvmx_pcieepx_cfg070_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg070_s          cn56xx;
+	struct cvmx_pcieepx_cfg070_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg070_s          cn63xx;
+	struct cvmx_pcieepx_cfg070_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;
+
+/**
+ * cvmx_pcieep#_cfg071
+ *
+ * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space
+ * (Header Log Register 1)
+ */
+union cvmx_pcieepx_cfg071
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg071_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword1                       : 32; /**< Header Log Register (first DWORD) */
+#else
+	uint32_t dword1                       : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg071_s          cn52xx;
+	struct cvmx_pcieepx_cfg071_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg071_s          cn56xx;
+	struct cvmx_pcieepx_cfg071_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg071_s          cn63xx;
+	struct cvmx_pcieepx_cfg071_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;
+
+/**
+ * cvmx_pcieep#_cfg072
+ *
+ * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space
+ * (Header Log Register 2)
+ */
+union cvmx_pcieepx_cfg072
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg072_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword2                       : 32; /**< Header Log Register (second DWORD) */
+#else
+	uint32_t dword2                       : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg072_s          cn52xx;
+	struct cvmx_pcieepx_cfg072_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg072_s          cn56xx;
+	struct cvmx_pcieepx_cfg072_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg072_s          cn63xx;
+	struct cvmx_pcieepx_cfg072_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;
+
+/**
+ * cvmx_pcieep#_cfg073
+ *
+ * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space
+ * (Header Log Register 3)
+ */
+union cvmx_pcieepx_cfg073
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg073_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword3                       : 32; /**< Header Log Register (third DWORD) */
+#else
+	uint32_t dword3                       : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg073_s          cn52xx;
+	struct cvmx_pcieepx_cfg073_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg073_s          cn56xx;
+	struct cvmx_pcieepx_cfg073_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg073_s          cn63xx;
+	struct cvmx_pcieepx_cfg073_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;
+
+/**
+ * cvmx_pcieep#_cfg074
+ *
+ * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space
+ * (Header Log Register 4)
+ */
+union cvmx_pcieepx_cfg074
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg074_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword4                       : 32; /**< Header Log Register (fourth DWORD) */
+#else
+	uint32_t dword4                       : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg074_s          cn52xx;
+	struct cvmx_pcieepx_cfg074_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg074_s          cn56xx;
+	struct cvmx_pcieepx_cfg074_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg074_s          cn63xx;
+	struct cvmx_pcieepx_cfg074_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;
+
+/**
+ * cvmx_pcieep#_cfg448
+ *
+ * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space
+ * (Ack Latency Timer and Replay Timer Register)
+ */
+union cvmx_pcieepx_cfg448
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg448_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t rtl                          : 16; /**< Replay Time Limit
+                                                         The replay timer expires when it reaches this limit. The PCI
+                                                         Express bus initiates a replay upon reception of a Nak or when
+                                                         the replay timer expires.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+	uint32_t rtltl                        : 16; /**< Round Trip Latency Time Limit
+                                                         The Ack/Nak latency timer expires when it reaches this limit.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+#else
+	uint32_t rtltl                        : 16;
+	uint32_t rtl                          : 16;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg448_s          cn52xx;
+	struct cvmx_pcieepx_cfg448_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg448_s          cn56xx;
+	struct cvmx_pcieepx_cfg448_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg448_s          cn63xx;
+	struct cvmx_pcieepx_cfg448_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;
+
+/**
+ * cvmx_pcieep#_cfg449
+ *
+ * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space
+ * (Other Message Register)
+ */
+union cvmx_pcieepx_cfg449
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg449_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t omr                          : 32; /**< Other Message Register
+                                                         This register can be used for either of the following purposes:
+                                                         o To send a specific PCI Express Message, the application
+                                                           writes the payload of the Message into this register, then
+                                                           sets bit 0 of the Port Link Control Register to send the
+                                                           Message.
+                                                         o To store a corruption pattern for corrupting the LCRC on all
+                                                           TLPs, the application places a 32-bit corruption pattern into
+                                                           this register and enables this function by setting bit 25 of
+                                                           the Port Link Control Register. When enabled, the transmit
+                                                           LCRC result is XOR'd with this pattern before inserting
+                                                           it into the packet. */
+#else
+	uint32_t omr                          : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg449_s          cn52xx;
+	struct cvmx_pcieepx_cfg449_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg449_s          cn56xx;
+	struct cvmx_pcieepx_cfg449_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg449_s          cn63xx;
+	struct cvmx_pcieepx_cfg449_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;
+
+/**
+ * cvmx_pcieep#_cfg450
+ *
+ * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space
+ * (Port Force Link Register)
+ */
+union cvmx_pcieepx_cfg450
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg450_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lpec                         : 8;  /**< Low Power Entrance Count
+                                                         The Power Management state will wait for this many clock cycles
+                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
+                                                         Power State (PS) field register to go low-power. This register
+                                                         is intended for applications that do not let the PCI Express
+                                                         bus handle a completion for configuration request to the
+                                                         Power Management Control and Status (PCIE_CFG017) register. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t link_state                   : 6;  /**< Link State
+                                                         The Link state that the PCI Express Bus will be forced to
+                                                         when bit 15 (Force Link) is set.
+                                                         State encoding:
+                                                         o DETECT_QUIET              00h
+                                                         o DETECT_ACT                01h
+                                                         o POLL_ACTIVE               02h
+                                                         o POLL_COMPLIANCE           03h
+                                                         o POLL_CONFIG               04h
+                                                         o PRE_DETECT_QUIET          05h
+                                                         o DETECT_WAIT               06h
+                                                         o CFG_LINKWD_START          07h
+                                                         o CFG_LINKWD_ACEPT          08h
+                                                         o CFG_LANENUM_WAIT          09h
+                                                         o CFG_LANENUM_ACEPT         0Ah
+                                                         o CFG_COMPLETE              0Bh
+                                                         o CFG_IDLE                  0Ch
+                                                         o RCVRY_LOCK                0Dh
+                                                         o RCVRY_SPEED               0Eh
+                                                         o RCVRY_RCVRCFG             0Fh
+                                                         o RCVRY_IDLE                10h
+                                                         o L0                        11h
+                                                         o L0S                       12h
+                                                         o L123_SEND_EIDLE           13h
+                                                         o L1_IDLE                   14h
+                                                         o L2_IDLE                   15h
+                                                         o L2_WAKE                   16h
+                                                         o DISABLED_ENTRY            17h
+                                                         o DISABLED_IDLE             18h
+                                                         o DISABLED                  19h
+                                                         o LPBK_ENTRY                1Ah
+                                                         o LPBK_ACTIVE               1Bh
+                                                         o LPBK_EXIT                 1Ch
+                                                         o LPBK_EXIT_TIMEOUT         1Dh
+                                                         o HOT_RESET_ENTRY           1Eh
+                                                         o HOT_RESET                 1Fh */
+	uint32_t force_link                   : 1;  /**< Force Link
+                                                         Forces the Link to the state specified by the Link State field.
+                                                         The Force Link pulse will trigger Link re-negotiation.
+                                                         * As the The Force Link is a pulse, writing a 1 to it does
+                                                           trigger the forced link state event, even thought reading it
+                                                           always returns a 0. */
+	uint32_t reserved_8_14                : 7;
+	uint32_t link_num                     : 8;  /**< Link Number
+                                                         Not used for Endpoint */
+#else
+	uint32_t link_num                     : 8;
+	uint32_t reserved_8_14                : 7;
+	uint32_t force_link                   : 1;
+	uint32_t link_state                   : 6;
+	uint32_t reserved_22_23               : 2;
+	uint32_t lpec                         : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg450_s          cn52xx;
+	struct cvmx_pcieepx_cfg450_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg450_s          cn56xx;
+	struct cvmx_pcieepx_cfg450_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg450_s          cn63xx;
+	struct cvmx_pcieepx_cfg450_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;
+
+/**
+ * cvmx_pcieep#_cfg451
+ *
+ * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space
+ * (Ack Frequency Register)
+ */
+union cvmx_pcieepx_cfg451
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg451_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+	uint32_t l0el                         : 3;  /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+	uint32_t n_fts_cc                     : 8;  /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: A value of zero is not supported; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: A value of zero is not supported; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+	uint32_t ack_freq                     : 8;  /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+	uint32_t ack_freq                     : 8;
+	uint32_t n_fts                        : 8;
+	uint32_t n_fts_cc                     : 8;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg451_s          cn52xx;
+	struct cvmx_pcieepx_cfg451_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg451_s          cn56xx;
+	struct cvmx_pcieepx_cfg451_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg451_s          cn63xx;
+	struct cvmx_pcieepx_cfg451_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;
+
+/**
+ * cvmx_pcieep#_cfg452
+ *
+ * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space
+ * (Port Link Control Register)
+ */
+union cvmx_pcieepx_cfg452
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg452_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t eccrc                        : 1;  /**< Enable Corrupted CRC
+                                                         Causes corrupt LCRC for TLPs when set,
+                                                         using the pattern contained in the Other Message register.
+                                                         This is a test feature, not to be used in normal operation. */
+	uint32_t reserved_22_24               : 3;
+	uint32_t lme                          : 6;  /**< Link Mode Enable
+                                                         o 000001: x1
+                                                         o 000011: x2
+                                                         o 000111: x4
+                                                         o 001111: x8  (not supported)
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port. The value can be set less than 0x7
+                                                         to limit the number of lanes the PCIe will attempt to use.
+                                                         If the value of 0x7 set by the HW is not desired,
+                                                         this field can be programmed to a smaller value (i.e. EEPROM)
+                                                         See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width, so all
+                                                          of x4, x2, and x1 are supported when LME=0x7,
+                                                          for example.) */
+	uint32_t reserved_8_15                : 8;
+	uint32_t flm                          : 1;  /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes.
+                                                         If during an eeprom load, the first word loaded is 0xffffffff,
+                                                         then the EEPROM load will be terminated and this bit will be set. */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t dllle                        : 1;  /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+	uint32_t reserved_4_4                 : 1;
+	uint32_t ra                           : 1;  /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+	uint32_t le                           : 1;  /**< Loopback Enable
+                                                         Initiate loopback mode as a master. On a 0->1 transition,
+                                                         the PCIe core sends TS ordered sets with the loopback bit set
+                                                         to cause the link partner to enter into loopback mode as a
+                                                         slave. Normal transmission is not possible when LE=1. To exit
+                                                         loopback mode, take the link through a reset sequence. */
+	uint32_t sd                           : 1;  /**< Scramble Disable
+                                                         Turns off data scrambling. */
+	uint32_t omr                          : 1;  /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+	uint32_t omr                          : 1;
+	uint32_t sd                           : 1;
+	uint32_t le                           : 1;
+	uint32_t ra                           : 1;
+	uint32_t reserved_4_4                 : 1;
+	uint32_t dllle                        : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t flm                          : 1;
+	uint32_t reserved_8_15                : 8;
+	uint32_t lme                          : 6;
+	uint32_t reserved_22_24               : 3;
+	uint32_t eccrc                        : 1;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg452_s          cn52xx;
+	struct cvmx_pcieepx_cfg452_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg452_s          cn56xx;
+	struct cvmx_pcieepx_cfg452_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg452_s          cn63xx;
+	struct cvmx_pcieepx_cfg452_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;
+
+/**
+ * cvmx_pcieep#_cfg453
+ *
+ * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space
+ * (Lane Skew Register)
+ */
+union cvmx_pcieepx_cfg453
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg453_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dlld                         : 1;  /**< Disable Lane-to-Lane Deskew
+                                                         Disables the internal Lane-to-Lane deskew logic. */
+	uint32_t reserved_26_30               : 5;
+	uint32_t ack_nak                      : 1;  /**< Ack/Nak Disable
+                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
+	uint32_t fcd                          : 1;  /**< Flow Control Disable
+                                                         Prevents the PCI Express bus from sending FC DLLPs. */
+	uint32_t ilst                         : 24; /**< Insert Lane Skew for Transmit
+                                                         Causes skew between lanes for test purposes. There are three
+                                                         bits per Lane. The value is in units of one symbol time. For
+                                                         example, the value 010b for a Lane forces a skew of two symbol
+                                                         times for that Lane. The maximum skew value for any Lane is 5
+                                                         symbol times. */
+#else
+	uint32_t ilst                         : 24;
+	uint32_t fcd                          : 1;
+	uint32_t ack_nak                      : 1;
+	uint32_t reserved_26_30               : 5;
+	uint32_t dlld                         : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg453_s          cn52xx;
+	struct cvmx_pcieepx_cfg453_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg453_s          cn56xx;
+	struct cvmx_pcieepx_cfg453_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg453_s          cn63xx;
+	struct cvmx_pcieepx_cfg453_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;
+
+/**
+ * cvmx_pcieep#_cfg454
+ *
+ * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space
+ * (Symbol Number Register)
+ */
+union cvmx_pcieepx_cfg454
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg454_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_29_31               : 3;
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_11_13               : 3;
+	uint32_t nskps                        : 3;  /**< Number of SKP Symbols */
+	uint32_t reserved_4_7                 : 4;
+	uint32_t ntss                         : 4;  /**< Number of TS Symbols
+                                                         Sets the number of TS identifier symbols that are sent in TS1
+                                                         and TS2 ordered sets. */
+#else
+	uint32_t ntss                         : 4;
+	uint32_t reserved_4_7                 : 4;
+	uint32_t nskps                        : 3;
+	uint32_t reserved_11_13               : 3;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg454_s          cn52xx;
+	struct cvmx_pcieepx_cfg454_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg454_s          cn56xx;
+	struct cvmx_pcieepx_cfg454_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg454_s          cn63xx;
+	struct cvmx_pcieepx_cfg454_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;
+
+/**
+ * cvmx_pcieep#_cfg455
+ *
+ * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space
+ * (Symbol Timer Register/Filter Mask Register 1)
+ */
+union cvmx_pcieepx_cfg455
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg455_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t m_cfg0_filt                  : 1;  /**< Mask filtering of received Configuration Requests (RC mode only) */
+	uint32_t m_io_filt                    : 1;  /**< Mask filtering of received I/O Requests (RC mode only) */
+	uint32_t msg_ctrl                     : 1;  /**< Message Control
+                                                         The application must not change this field. */
+	uint32_t m_cpl_ecrc_filt              : 1;  /**< Mask ECRC error filtering for Completions */
+	uint32_t m_ecrc_filt                  : 1;  /**< Mask ECRC error filtering */
+	uint32_t m_cpl_len_err                : 1;  /**< Mask Length mismatch error for received Completions */
+	uint32_t m_cpl_attr_err               : 1;  /**< Mask Attributes mismatch error for received Completions */
+	uint32_t m_cpl_tc_err                 : 1;  /**< Mask Traffic Class mismatch error for received Completions */
+	uint32_t m_cpl_fun_err                : 1;  /**< Mask function mismatch error for received Completions */
+	uint32_t m_cpl_rid_err                : 1;  /**< Mask Requester ID mismatch error for received Completions */
+	uint32_t m_cpl_tag_err                : 1;  /**< Mask Tag error rules for received Completions */
+	uint32_t m_lk_filt                    : 1;  /**< Mask Locked Request filtering */
+	uint32_t m_cfg1_filt                  : 1;  /**< Mask Type 1 Configuration Request filtering */
+	uint32_t m_bar_match                  : 1;  /**< Mask BAR match filtering */
+	uint32_t m_pois_filt                  : 1;  /**< Mask poisoned TLP filtering */
+	uint32_t m_fun                        : 1;  /**< Mask function */
+	uint32_t dfcwt                        : 1;  /**< Disable FC Watchdog Timer */
+	uint32_t reserved_11_14               : 4;
+	uint32_t skpiv                        : 11; /**< SKP Interval Value */
+#else
+	uint32_t skpiv                        : 11;
+	uint32_t reserved_11_14               : 4;
+	uint32_t dfcwt                        : 1;
+	uint32_t m_fun                        : 1;
+	uint32_t m_pois_filt                  : 1;
+	uint32_t m_bar_match                  : 1;
+	uint32_t m_cfg1_filt                  : 1;
+	uint32_t m_lk_filt                    : 1;
+	uint32_t m_cpl_tag_err                : 1;
+	uint32_t m_cpl_rid_err                : 1;
+	uint32_t m_cpl_fun_err                : 1;
+	uint32_t m_cpl_tc_err                 : 1;
+	uint32_t m_cpl_attr_err               : 1;
+	uint32_t m_cpl_len_err                : 1;
+	uint32_t m_ecrc_filt                  : 1;
+	uint32_t m_cpl_ecrc_filt              : 1;
+	uint32_t msg_ctrl                     : 1;
+	uint32_t m_io_filt                    : 1;
+	uint32_t m_cfg0_filt                  : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg455_s          cn52xx;
+	struct cvmx_pcieepx_cfg455_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg455_s          cn56xx;
+	struct cvmx_pcieepx_cfg455_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg455_s          cn63xx;
+	struct cvmx_pcieepx_cfg455_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;
+
+/**
+ * cvmx_pcieep#_cfg456
+ *
+ * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space
+ * (Filter Mask Register 2)
+ */
+union cvmx_pcieepx_cfg456
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg456_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_2_31                : 30;
+	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
+	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+	uint32_t m_vend0_drp                  : 1;
+	uint32_t m_vend1_drp                  : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg456_s          cn52xx;
+	struct cvmx_pcieepx_cfg456_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg456_s          cn56xx;
+	struct cvmx_pcieepx_cfg456_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg456_s          cn63xx;
+	struct cvmx_pcieepx_cfg456_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;
+
+/**
+ * cvmx_pcieep#_cfg458
+ *
+ * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space
+ * (Debug Register 0)
+ */
+union cvmx_pcieepx_cfg458
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg458_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dbg_info_l32                 : 32; /**< Debug Info Lower 32 Bits */
+#else
+	uint32_t dbg_info_l32                 : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg458_s          cn52xx;
+	struct cvmx_pcieepx_cfg458_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg458_s          cn56xx;
+	struct cvmx_pcieepx_cfg458_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg458_s          cn63xx;
+	struct cvmx_pcieepx_cfg458_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;
+
+/**
+ * cvmx_pcieep#_cfg459
+ *
+ * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space
+ * (Debug Register 1)
+ */
+union cvmx_pcieepx_cfg459
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg459_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dbg_info_u32                 : 32; /**< Debug Info Upper 32 Bits */
+#else
+	uint32_t dbg_info_u32                 : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg459_s          cn52xx;
+	struct cvmx_pcieepx_cfg459_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg459_s          cn56xx;
+	struct cvmx_pcieepx_cfg459_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg459_s          cn63xx;
+	struct cvmx_pcieepx_cfg459_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;
+
+/**
+ * cvmx_pcieep#_cfg460
+ *
+ * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space
+ * (Transmit Posted FC Credit Status)
+ */
+union cvmx_pcieepx_cfg460
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg460_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tphfcc                       : 8;  /**< Transmit Posted Header FC Credits
+                                                         The Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tpdfcc                       : 12; /**< Transmit Posted Data FC Credits
+                                                         The Posted Data credits advertised by the receiver at the other
+                                                         end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tpdfcc                       : 12;
+	uint32_t tphfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg460_s          cn52xx;
+	struct cvmx_pcieepx_cfg460_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg460_s          cn56xx;
+	struct cvmx_pcieepx_cfg460_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg460_s          cn63xx;
+	struct cvmx_pcieepx_cfg460_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;
+
+/**
+ * cvmx_pcieep#_cfg461
+ *
+ * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space
+ * (Transmit Non-Posted FC Credit Status)
+ */
+union cvmx_pcieepx_cfg461
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg461_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tchfcc                       : 8;  /**< Transmit Non-Posted Header FC Credits
+                                                         The Non-Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tcdfcc                       : 12; /**< Transmit Non-Posted Data FC Credits
+                                                         The Non-Posted Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tcdfcc                       : 12;
+	uint32_t tchfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg461_s          cn52xx;
+	struct cvmx_pcieepx_cfg461_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg461_s          cn56xx;
+	struct cvmx_pcieepx_cfg461_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg461_s          cn63xx;
+	struct cvmx_pcieepx_cfg461_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;
+
+/**
+ * cvmx_pcieep#_cfg462
+ *
+ * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space
+ * (Transmit Completion FC Credit Status )
+ */
+union cvmx_pcieepx_cfg462
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg462_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tchfcc                       : 8;  /**< Transmit Completion Header FC Credits
+                                                         The Completion Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tcdfcc                       : 12; /**< Transmit Completion Data FC Credits
+                                                         The Completion Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tcdfcc                       : 12;
+	uint32_t tchfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg462_s          cn52xx;
+	struct cvmx_pcieepx_cfg462_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg462_s          cn56xx;
+	struct cvmx_pcieepx_cfg462_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg462_s          cn63xx;
+	struct cvmx_pcieepx_cfg462_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;
+
+/**
+ * cvmx_pcieep#_cfg463
+ *
+ * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space
+ * (Queue Status)
+ */
+union cvmx_pcieepx_cfg463
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg463_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t rqne                         : 1;  /**< Received Queue Not Empty
+                                                         Indicates there is data in one or more of the receive buffers. */
+	uint32_t trbne                        : 1;  /**< Transmit Retry Buffer Not Empty
+                                                         Indicates that there is data in the transmit retry buffer. */
+	uint32_t rtlpfccnr                    : 1;  /**< Received TLP FC Credits Not Returned
+                                                         Indicates that the PCI Express bus has sent a TLP but has not
+                                                         yet received an UpdateFC DLLP indicating that the credits for
+                                                         that TLP have been restored by the receiver at the other end of
+                                                         the Link. */
+#else
+	uint32_t rtlpfccnr                    : 1;
+	uint32_t trbne                        : 1;
+	uint32_t rqne                         : 1;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg463_s          cn52xx;
+	struct cvmx_pcieepx_cfg463_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg463_s          cn56xx;
+	struct cvmx_pcieepx_cfg463_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg463_s          cn63xx;
+	struct cvmx_pcieepx_cfg463_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;
+
+/**
+ * cvmx_pcieep#_cfg464
+ *
+ * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space
+ * (VC Transmit Arbitration Register 1)
+ */
+union cvmx_pcieepx_cfg464
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg464_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wrr_vc3                      : 8;  /**< WRR Weight for VC3 */
+	uint32_t wrr_vc2                      : 8;  /**< WRR Weight for VC2 */
+	uint32_t wrr_vc1                      : 8;  /**< WRR Weight for VC1 */
+	uint32_t wrr_vc0                      : 8;  /**< WRR Weight for VC0 */
+#else
+	uint32_t wrr_vc0                      : 8;
+	uint32_t wrr_vc1                      : 8;
+	uint32_t wrr_vc2                      : 8;
+	uint32_t wrr_vc3                      : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg464_s          cn52xx;
+	struct cvmx_pcieepx_cfg464_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg464_s          cn56xx;
+	struct cvmx_pcieepx_cfg464_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg464_s          cn63xx;
+	struct cvmx_pcieepx_cfg464_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;
+
+/**
+ * cvmx_pcieep#_cfg465
+ *
+ * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space
+ * (VC Transmit Arbitration Register 2)
+ */
+union cvmx_pcieepx_cfg465
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg465_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wrr_vc7                      : 8;  /**< WRR Weight for VC7 */
+	uint32_t wrr_vc6                      : 8;  /**< WRR Weight for VC6 */
+	uint32_t wrr_vc5                      : 8;  /**< WRR Weight for VC5 */
+	uint32_t wrr_vc4                      : 8;  /**< WRR Weight for VC4 */
+#else
+	uint32_t wrr_vc4                      : 8;
+	uint32_t wrr_vc5                      : 8;
+	uint32_t wrr_vc6                      : 8;
+	uint32_t wrr_vc7                      : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg465_s          cn52xx;
+	struct cvmx_pcieepx_cfg465_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg465_s          cn56xx;
+	struct cvmx_pcieepx_cfg465_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg465_s          cn63xx;
+	struct cvmx_pcieepx_cfg465_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;
+
+/**
+ * cvmx_pcieep#_cfg466
+ *
+ * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space
+ * (VC0 Posted Receive Queue Control)
+ */
+union cvmx_pcieepx_cfg466
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg466_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t rx_queue_order               : 1;  /**< VC Ordering for Receive Queues
+                                                         Determines the VC ordering rule for the receive queues, used
+                                                         only in the segmented-buffer configuration,
+                                                         writable through PEM(0..1)_CFG_WR:
+                                                         o 1: Strict ordering, higher numbered VCs have higher priority
+                                                         o 0: Round robin
+                                                         However, the application must not change this field. */
+	uint32_t type_ordering                : 1;  /**< TLP Type Ordering for VC0
+                                                         Determines the TLP type ordering rule for VC0 receive queues,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR:
+                                                         o 1: Ordering of received TLPs follows the rules in
+                                                              PCI Express Base Specification
+                                                         o 0: Strict ordering for received TLPs: Posted, then
+                                                              Completion, then Non-Posted
+                                                         However, the application must not change this field. */
+	uint32_t reserved_24_29               : 6;
+	uint32_t queue_mode                   : 3;  /**< VC0 Posted TLP Queue Mode
+                                                         The operating mode of the Posted receive queue for VC0, used
+                                                         only in the segmented-buffer configuration, writable through
+                                                         PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Posted Header Credits
+                                                         The number of initial Posted header credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Posted Data Credits
+                                                         The number of initial Posted data credits for VC0, used for all
+                                                         receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_29               : 6;
+	uint32_t type_ordering                : 1;
+	uint32_t rx_queue_order               : 1;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg466_s          cn52xx;
+	struct cvmx_pcieepx_cfg466_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg466_s          cn56xx;
+	struct cvmx_pcieepx_cfg466_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg466_s          cn63xx;
+	struct cvmx_pcieepx_cfg466_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;
+
+/**
+ * cvmx_pcieep#_cfg467
+ *
+ * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space
+ * (VC0 Non-Posted Receive Queue Control)
+ */
+union cvmx_pcieepx_cfg467
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg467_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t queue_mode                   : 3;  /**< VC0 Non-Posted TLP Queue Mode
+                                                         The operating mode of the Non-Posted receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Non-Posted Header Credits
+                                                         The number of initial Non-Posted header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Non-Posted Data Credits
+                                                         The number of initial Non-Posted data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg467_s          cn52xx;
+	struct cvmx_pcieepx_cfg467_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg467_s          cn56xx;
+	struct cvmx_pcieepx_cfg467_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg467_s          cn63xx;
+	struct cvmx_pcieepx_cfg467_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;
+
+/**
+ * cvmx_pcieep#_cfg468
+ *
+ * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space
+ * (VC0 Completion Receive Queue Control)
+ */
+union cvmx_pcieepx_cfg468
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg468_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t queue_mode                   : 3;  /**< VC0 Completion TLP Queue Mode
+                                                         The operating mode of the Completion receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Completion Header Credits
+                                                         The number of initial Completion header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Completion Data Credits
+                                                         The number of initial Completion data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg468_s          cn52xx;
+	struct cvmx_pcieepx_cfg468_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg468_s          cn56xx;
+	struct cvmx_pcieepx_cfg468_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg468_s          cn63xx;
+	struct cvmx_pcieepx_cfg468_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;
+
+/**
+ * cvmx_pcieep#_cfg490
+ *
+ * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space
+ * (VC0 Posted Buffer Depth)
+ */
+union cvmx_pcieepx_cfg490
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg490_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Posted Header Queue Depth
+                                                         Sets the number of entries in the Posted header queue for VC0
+                                                         when using the segmented-buffer configuration, writable through
+                                                         PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Posted Data Queue Depth
+                                                         Sets the number of entries in the Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg490_s          cn52xx;
+	struct cvmx_pcieepx_cfg490_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg490_s          cn56xx;
+	struct cvmx_pcieepx_cfg490_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg490_s          cn63xx;
+	struct cvmx_pcieepx_cfg490_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;
+
+/**
+ * cvmx_pcieep#_cfg491
+ *
+ * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space
+ * (VC0 Non-Posted Buffer Depth)
+ */
+union cvmx_pcieepx_cfg491
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg491_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Non-Posted Header Queue Depth
+                                                         Sets the number of entries in the Non-Posted header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Non-Posted Data Queue Depth
+                                                         Sets the number of entries in the Non-Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg491_s          cn52xx;
+	struct cvmx_pcieepx_cfg491_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg491_s          cn56xx;
+	struct cvmx_pcieepx_cfg491_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg491_s          cn63xx;
+	struct cvmx_pcieepx_cfg491_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;
+
+/**
+ * cvmx_pcieep#_cfg492
+ *
+ * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space
+ * (VC0 Completion Buffer Depth)
+ */
+union cvmx_pcieepx_cfg492
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg492_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Completion Header Queue Depth
+                                                         Sets the number of entries in the Completion header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Completion Data Queue Depth
+                                                         Sets the number of entries in the Completion data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg492_s          cn52xx;
+	struct cvmx_pcieepx_cfg492_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg492_s          cn56xx;
+	struct cvmx_pcieepx_cfg492_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg492_s          cn63xx;
+	struct cvmx_pcieepx_cfg492_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;
+
+/**
+ * cvmx_pcieep#_cfg515
+ *
+ * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space
+ * (Port Logic Register (Gen2))
+ */
+union cvmx_pcieepx_cfg515
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg515_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t s_d_e                        : 1;  /**< SEL_DE_EMPHASIS
+                                                         Used to set the de-emphasis level for upstream ports. */
+	uint32_t ctcrb                        : 1;  /**< Config Tx Compliance Receive Bit
+                                                         When set to 1, signals LTSSM to transmit TS ordered sets
+                                                         with the compliance receive bit assert (equal to 1). */
+	uint32_t cpyts                        : 1;  /**< Config PHY Tx Swing
+                                                         Indicates the voltage level the PHY should drive. When set to
+                                                         1, indicates Full Swing. When set to 0, indicates Low Swing */
+	uint32_t dsc                          : 1;  /**< Directed Speed Change
+                                                         Indicates to the LTSSM whether or not to initiate a speed
+                                                         change. */
+	uint32_t le                           : 9;  /**< Lane Enable
+                                                         Indicates the number of lanes to check for exit from electrical
+                                                         idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2,
+                                                         etc. Used to limit the maximum link width to ignore broken
+                                                         lanes that detect a receiver, but will not exit electrical
+                                                         idle and
+                                                         would otherwise prevent a valid link from being configured. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         Sets the Number of Fast Training Sequences (N_FTS) that
+                                                         the core advertises as its N_FTS during GEN2 Link training.
+                                                         This value is used to inform the Link partner about the PHYs
+                                                         ability to recover synchronization after a low power state.
+                                                         Note: Do not set N_FTS to zero; doing so can cause the
+                                                               LTSSM to go into the recovery state when exiting from
+                                                               L0s. */
+#else
+	uint32_t n_fts                        : 8;
+	uint32_t le                           : 9;
+	uint32_t dsc                          : 1;
+	uint32_t cpyts                        : 1;
+	uint32_t ctcrb                        : 1;
+	uint32_t s_d_e                        : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg515_s          cn63xx;
+	struct cvmx_pcieepx_cfg515_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;
+
+/**
+ * cvmx_pcieep#_cfg516
+ *
+ * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space
+ * (PHY Status Register)
+ */
+union cvmx_pcieepx_cfg516
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg516_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t phy_stat                     : 32; /**< PHY Status */
+#else
+	uint32_t phy_stat                     : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg516_s          cn52xx;
+	struct cvmx_pcieepx_cfg516_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg516_s          cn56xx;
+	struct cvmx_pcieepx_cfg516_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg516_s          cn63xx;
+	struct cvmx_pcieepx_cfg516_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;
+
+/**
+ * cvmx_pcieep#_cfg517
+ *
+ * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space
+ * (PHY Control Register)
+ */
+union cvmx_pcieepx_cfg517
+{
+	uint32_t u32;
+	struct cvmx_pcieepx_cfg517_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t phy_ctrl                     : 32; /**< PHY Control */
+#else
+	uint32_t phy_ctrl                     : 32;
+#endif
+	} s;
+	struct cvmx_pcieepx_cfg517_s          cn52xx;
+	struct cvmx_pcieepx_cfg517_s          cn52xxp1;
+	struct cvmx_pcieepx_cfg517_s          cn56xx;
+	struct cvmx_pcieepx_cfg517_s          cn56xxp1;
+	struct cvmx_pcieepx_cfg517_s          cn63xx;
+	struct cvmx_pcieepx_cfg517_s          cn63xxp1;
+};
+typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h b/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
new file mode 100644
index 0000000..3094bac
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
@@ -0,0 +1,4432 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pciercx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pciercx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCIERCX_TYPEDEFS_H__
+#define __CVMX_PCIERCX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000004ull;
+}
+#else
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000008ull;
+}
+#else
+#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000000Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000014ull;
+}
+#else
+#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000018ull;
+}
+#else
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000001Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000020ull;
+}
+#else
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000024ull;
+}
+#else
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000028ull;
+}
+#else
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000002Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000030ull;
+}
+#else
+#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000034ull;
+}
+#else
+#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000038ull;
+}
+#else
+#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000003Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000040ull;
+}
+#else
+#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000044ull;
+}
+#else
+#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000050ull;
+}
+#else
+#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000054ull;
+}
+#else
+#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000058ull;
+}
+#else
+#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000005Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000070ull;
+}
+#else
+#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000074ull;
+}
+#else
+#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000078ull;
+}
+#else
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000007Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000080ull;
+}
+#else
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000084ull;
+}
+#else
+#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000088ull;
+}
+#else
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000008Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000090ull;
+}
+#else
+#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000094ull;
+}
+#else
+#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000098ull;
+}
+#else
+#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000009Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A0ull;
+}
+#else
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A4ull;
+}
+#else
+#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000000A8ull;
+}
+#else
+#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000100ull;
+}
+#else
+#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000104ull;
+}
+#else
+#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000108ull;
+}
+#else
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000010Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000110ull;
+}
+#else
+#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000114ull;
+}
+#else
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000118ull;
+}
+#else
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000011Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000120ull;
+}
+#else
+#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000124ull;
+}
+#else
+#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000128ull;
+}
+#else
+#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000012Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000130ull;
+}
+#else
+#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000134ull;
+}
+#else
+#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000700ull;
+}
+#else
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000704ull;
+}
+#else
+#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000708ull;
+}
+#else
+#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000070Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000710ull;
+}
+#else
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000714ull;
+}
+#else
+#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000718ull;
+}
+#else
+#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000071Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000720ull;
+}
+#else
+#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000728ull;
+}
+#else
+#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000072Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000730ull;
+}
+#else
+#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000734ull;
+}
+#else
+#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000738ull;
+}
+#else
+#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000073Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000740ull;
+}
+#else
+#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000744ull;
+}
+#else
+#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000748ull;
+}
+#else
+#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000074Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000750ull;
+}
+#else
+#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007A8ull;
+}
+#else
+#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007ACull;
+}
+#else
+#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id);
+	return 0x00000000000007B0ull;
+}
+#else
+#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000080Cull;
+}
+#else
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000810ull;
+}
+#else
+#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000814ull;
+}
+#else
+#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
+#endif
+
+/**
+ * cvmx_pcierc#_cfg000
+ *
+ * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register)
+ *
+ */
+union cvmx_pciercx_cfg000
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg000_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t devid                        : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t vendid                       : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t vendid                       : 16;
+	uint32_t devid                        : 16;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg000_s          cn52xx;
+	struct cvmx_pciercx_cfg000_s          cn52xxp1;
+	struct cvmx_pciercx_cfg000_s          cn56xx;
+	struct cvmx_pciercx_cfg000_s          cn56xxp1;
+	struct cvmx_pciercx_cfg000_s          cn63xx;
+	struct cvmx_pciercx_cfg000_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t;
+
+/**
+ * cvmx_pcierc#_cfg001
+ *
+ * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register)
+ *
+ */
+union cvmx_pciercx_cfg001
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg001_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dpe                          : 1;  /**< Detected Parity Error */
+	uint32_t sse                          : 1;  /**< Signaled System Error */
+	uint32_t rma                          : 1;  /**< Received Master Abort */
+	uint32_t rta                          : 1;  /**< Received Target Abort */
+	uint32_t sta                          : 1;  /**< Signaled Target Abort */
+	uint32_t devt                         : 2;  /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t mdpe                         : 1;  /**< Master Data Parity Error */
+	uint32_t fbb                          : 1;  /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t reserved_22_22               : 1;
+	uint32_t m66                          : 1;  /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t cl                           : 1;  /**< Capabilities List
+                                                         Indicates presence of an extended capability item.
+                                                         Hardwired to 1. */
+	uint32_t i_stat                       : 1;  /**< INTx Status */
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_dis                        : 1;  /**< INTx Assertion Disable */
+	uint32_t fbbe                         : 1;  /**< Fast Back-to-Back Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t see                          : 1;  /**< SERR# Enable */
+	uint32_t ids_wcc                      : 1;  /**< IDSEL Stepping/Wait Cycle Control
+                                                         Not applicable for PCI Express. Must be hardwired to 0 */
+	uint32_t per                          : 1;  /**< Parity Error Response */
+	uint32_t vps                          : 1;  /**< VGA Palette Snoop
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t mwice                        : 1;  /**< Memory Write and Invalidate
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t scse                         : 1;  /**< Special Cycle Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+	uint32_t me                           : 1;  /**< Bus Master Enable */
+	uint32_t msae                         : 1;  /**< Memory Space Enable */
+	uint32_t isae                         : 1;  /**< I/O Space Enable */
+#else
+	uint32_t isae                         : 1;
+	uint32_t msae                         : 1;
+	uint32_t me                           : 1;
+	uint32_t scse                         : 1;
+	uint32_t mwice                        : 1;
+	uint32_t vps                          : 1;
+	uint32_t per                          : 1;
+	uint32_t ids_wcc                      : 1;
+	uint32_t see                          : 1;
+	uint32_t fbbe                         : 1;
+	uint32_t i_dis                        : 1;
+	uint32_t reserved_11_18               : 8;
+	uint32_t i_stat                       : 1;
+	uint32_t cl                           : 1;
+	uint32_t m66                          : 1;
+	uint32_t reserved_22_22               : 1;
+	uint32_t fbb                          : 1;
+	uint32_t mdpe                         : 1;
+	uint32_t devt                         : 2;
+	uint32_t sta                          : 1;
+	uint32_t rta                          : 1;
+	uint32_t rma                          : 1;
+	uint32_t sse                          : 1;
+	uint32_t dpe                          : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg001_s          cn52xx;
+	struct cvmx_pciercx_cfg001_s          cn52xxp1;
+	struct cvmx_pciercx_cfg001_s          cn56xx;
+	struct cvmx_pciercx_cfg001_s          cn56xxp1;
+	struct cvmx_pciercx_cfg001_s          cn63xx;
+	struct cvmx_pciercx_cfg001_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t;
+
+/**
+ * cvmx_pcierc#_cfg002
+ *
+ * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register)
+ *
+ */
+union cvmx_pciercx_cfg002
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg002_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bcc                          : 8;  /**< Base Class Code, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t sc                           : 8;  /**< Subclass Code, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pi                           : 8;  /**< Programming Interface, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t rid                          : 8;  /**< Revision ID, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t rid                          : 8;
+	uint32_t pi                           : 8;
+	uint32_t sc                           : 8;
+	uint32_t bcc                          : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg002_s          cn52xx;
+	struct cvmx_pciercx_cfg002_s          cn52xxp1;
+	struct cvmx_pciercx_cfg002_s          cn56xx;
+	struct cvmx_pciercx_cfg002_s          cn56xxp1;
+	struct cvmx_pciercx_cfg002_s          cn63xx;
+	struct cvmx_pciercx_cfg002_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t;
+
+/**
+ * cvmx_pcierc#_cfg003
+ *
+ * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
+ *
+ */
+union cvmx_pciercx_cfg003
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg003_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bist                         : 8;  /**< The BIST register functions are not supported.
+                                                         All 8 bits of the BIST register are hardwired to 0. */
+	uint32_t mfd                          : 1;  /**< Multi Function Device
+                                                         The Multi Function Device bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, this is a single function device. Therefore, the
+                                                         application must not write a 1 to this bit. */
+	uint32_t chf                          : 7;  /**< Configuration Header Format
+                                                         Hardwired to 1. */
+	uint32_t lt                           : 8;  /**< Master Latency Timer
+                                                         Not applicable for PCI Express, hardwired to 0. */
+	uint32_t cls                          : 8;  /**< Cache Line Size
+                                                         The Cache Line Size register is RW for legacy compatibility
+                                                         purposes and is not applicable to PCI Express device
+                                                         functionality. */
+#else
+	uint32_t cls                          : 8;
+	uint32_t lt                           : 8;
+	uint32_t chf                          : 7;
+	uint32_t mfd                          : 1;
+	uint32_t bist                         : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg003_s          cn52xx;
+	struct cvmx_pciercx_cfg003_s          cn52xxp1;
+	struct cvmx_pciercx_cfg003_s          cn56xx;
+	struct cvmx_pciercx_cfg003_s          cn56xxp1;
+	struct cvmx_pciercx_cfg003_s          cn63xx;
+	struct cvmx_pciercx_cfg003_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t;
+
+/**
+ * cvmx_pcierc#_cfg004
+ *
+ * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low)
+ *
+ */
+union cvmx_pciercx_cfg004
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg004_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg004_s          cn52xx;
+	struct cvmx_pciercx_cfg004_s          cn52xxp1;
+	struct cvmx_pciercx_cfg004_s          cn56xx;
+	struct cvmx_pciercx_cfg004_s          cn56xxp1;
+	struct cvmx_pciercx_cfg004_s          cn63xx;
+	struct cvmx_pciercx_cfg004_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t;
+
+/**
+ * cvmx_pcierc#_cfg005
+ *
+ * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High)
+ *
+ */
+union cvmx_pciercx_cfg005
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg005_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg005_s          cn52xx;
+	struct cvmx_pciercx_cfg005_s          cn52xxp1;
+	struct cvmx_pciercx_cfg005_s          cn56xx;
+	struct cvmx_pciercx_cfg005_s          cn56xxp1;
+	struct cvmx_pciercx_cfg005_s          cn63xx;
+	struct cvmx_pciercx_cfg005_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t;
+
+/**
+ * cvmx_pcierc#_cfg006
+ *
+ * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers)
+ *
+ */
+union cvmx_pciercx_cfg006
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg006_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t slt                          : 8;  /**< Secondary Latency Timer
+                                                         Not applicable to PCI Express, hardwired to 0x00. */
+	uint32_t subbnum                      : 8;  /**< Subordinate Bus Number */
+	uint32_t sbnum                        : 8;  /**< Secondary Bus Number */
+	uint32_t pbnum                        : 8;  /**< Primary Bus Number */
+#else
+	uint32_t pbnum                        : 8;
+	uint32_t sbnum                        : 8;
+	uint32_t subbnum                      : 8;
+	uint32_t slt                          : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg006_s          cn52xx;
+	struct cvmx_pciercx_cfg006_s          cn52xxp1;
+	struct cvmx_pciercx_cfg006_s          cn56xx;
+	struct cvmx_pciercx_cfg006_s          cn56xxp1;
+	struct cvmx_pciercx_cfg006_s          cn63xx;
+	struct cvmx_pciercx_cfg006_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t;
+
+/**
+ * cvmx_pcierc#_cfg007
+ *
+ * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register)
+ *
+ */
+union cvmx_pciercx_cfg007
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg007_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dpe                          : 1;  /**< Detected Parity Error */
+	uint32_t sse                          : 1;  /**< Signaled System Error */
+	uint32_t rma                          : 1;  /**< Received Master Abort */
+	uint32_t rta                          : 1;  /**< Received Target Abort */
+	uint32_t sta                          : 1;  /**< Signaled Target Abort */
+	uint32_t devt                         : 2;  /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t mdpe                         : 1;  /**< Master Data Parity Error */
+	uint32_t fbb                          : 1;  /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t reserved_22_22               : 1;
+	uint32_t m66                          : 1;  /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+	uint32_t reserved_16_20               : 5;
+	uint32_t lio_limi                     : 4;  /**< I/O Space Limit */
+	uint32_t reserved_9_11                : 3;
+	uint32_t io32b                        : 1;  /**< 32-Bit I/O Space */
+	uint32_t lio_base                     : 4;  /**< I/O Space Base */
+	uint32_t reserved_1_3                 : 3;
+	uint32_t io32a                        : 1;  /**< 32-Bit I/O Space
+                                                         o 0 = 16-bit I/O addressing
+                                                         o 1 = 32-bit I/O addressing
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         When the application
+                                                         writes to this bit through PEM(0..1)_CFG_WR,
+                                                         the same value is written
+                                                         to bit 8 of this register. */
+#else
+	uint32_t io32a                        : 1;
+	uint32_t reserved_1_3                 : 3;
+	uint32_t lio_base                     : 4;
+	uint32_t io32b                        : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t lio_limi                     : 4;
+	uint32_t reserved_16_20               : 5;
+	uint32_t m66                          : 1;
+	uint32_t reserved_22_22               : 1;
+	uint32_t fbb                          : 1;
+	uint32_t mdpe                         : 1;
+	uint32_t devt                         : 2;
+	uint32_t sta                          : 1;
+	uint32_t rta                          : 1;
+	uint32_t rma                          : 1;
+	uint32_t sse                          : 1;
+	uint32_t dpe                          : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg007_s          cn52xx;
+	struct cvmx_pciercx_cfg007_s          cn52xxp1;
+	struct cvmx_pciercx_cfg007_s          cn56xx;
+	struct cvmx_pciercx_cfg007_s          cn56xxp1;
+	struct cvmx_pciercx_cfg007_s          cn63xx;
+	struct cvmx_pciercx_cfg007_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t;
+
+/**
+ * cvmx_pcierc#_cfg008
+ *
+ * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register)
+ *
+ */
+union cvmx_pciercx_cfg008
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg008_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ml_addr                      : 12; /**< Memory Limit Address */
+	uint32_t reserved_16_19               : 4;
+	uint32_t mb_addr                      : 12; /**< Memory Base Address */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t mb_addr                      : 12;
+	uint32_t reserved_16_19               : 4;
+	uint32_t ml_addr                      : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg008_s          cn52xx;
+	struct cvmx_pciercx_cfg008_s          cn52xxp1;
+	struct cvmx_pciercx_cfg008_s          cn56xx;
+	struct cvmx_pciercx_cfg008_s          cn56xxp1;
+	struct cvmx_pciercx_cfg008_s          cn63xx;
+	struct cvmx_pciercx_cfg008_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t;
+
+/**
+ * cvmx_pcierc#_cfg009
+ *
+ * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register)
+ *
+ */
+union cvmx_pciercx_cfg009
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg009_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmem_limit                   : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */
+	uint32_t reserved_17_19               : 3;
+	uint32_t mem64b                       : 1;  /**< 64-Bit Memory Addressing
+                                                         o 0 = 32-bit memory addressing
+                                                         o 1 = 64-bit memory addressing */
+	uint32_t lmem_base                    : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */
+	uint32_t reserved_1_3                 : 3;
+	uint32_t mem64a                       : 1;  /**< 64-Bit Memory Addressing
+                                                         o 0 = 32-bit memory addressing
+                                                         o 1 = 64-bit memory addressing
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         When the application
+                                                         writes to this bit through PEM(0..1)_CFG_WR,
+                                                         the same value is written
+                                                         to bit 16 of this register. */
+#else
+	uint32_t mem64a                       : 1;
+	uint32_t reserved_1_3                 : 3;
+	uint32_t lmem_base                    : 12;
+	uint32_t mem64b                       : 1;
+	uint32_t reserved_17_19               : 3;
+	uint32_t lmem_limit                   : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg009_s          cn52xx;
+	struct cvmx_pciercx_cfg009_s          cn52xxp1;
+	struct cvmx_pciercx_cfg009_s          cn56xx;
+	struct cvmx_pciercx_cfg009_s          cn56xxp1;
+	struct cvmx_pciercx_cfg009_s          cn63xx;
+	struct cvmx_pciercx_cfg009_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t;
+
+/**
+ * cvmx_pcierc#_cfg010
+ *
+ * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register)
+ *
+ */
+union cvmx_pciercx_cfg010
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg010_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umem_base                    : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space
+                                                         Used only when 64-bit prefetchable memory addressing is
+                                                         enabled. */
+#else
+	uint32_t umem_base                    : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg010_s          cn52xx;
+	struct cvmx_pciercx_cfg010_s          cn52xxp1;
+	struct cvmx_pciercx_cfg010_s          cn56xx;
+	struct cvmx_pciercx_cfg010_s          cn56xxp1;
+	struct cvmx_pciercx_cfg010_s          cn63xx;
+	struct cvmx_pciercx_cfg010_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t;
+
+/**
+ * cvmx_pcierc#_cfg011
+ *
+ * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register)
+ *
+ */
+union cvmx_pciercx_cfg011
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg011_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umem_limit                   : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space
+                                                         Used only when 64-bit prefetchable memory addressing is
+                                                         enabled. */
+#else
+	uint32_t umem_limit                   : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg011_s          cn52xx;
+	struct cvmx_pciercx_cfg011_s          cn52xxp1;
+	struct cvmx_pciercx_cfg011_s          cn56xx;
+	struct cvmx_pciercx_cfg011_s          cn56xxp1;
+	struct cvmx_pciercx_cfg011_s          cn63xx;
+	struct cvmx_pciercx_cfg011_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t;
+
+/**
+ * cvmx_pcierc#_cfg012
+ *
+ * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register)
+ *
+ */
+union cvmx_pciercx_cfg012
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg012_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t uio_limit                    : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported
+                                                         for devices on the secondary side) */
+	uint32_t uio_base                     : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported
+                                                         for devices on the secondary side) */
+#else
+	uint32_t uio_base                     : 16;
+	uint32_t uio_limit                    : 16;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg012_s          cn52xx;
+	struct cvmx_pciercx_cfg012_s          cn52xxp1;
+	struct cvmx_pciercx_cfg012_s          cn56xx;
+	struct cvmx_pciercx_cfg012_s          cn56xxp1;
+	struct cvmx_pciercx_cfg012_s          cn63xx;
+	struct cvmx_pciercx_cfg012_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t;
+
+/**
+ * cvmx_pcierc#_cfg013
+ *
+ * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register)
+ *
+ */
+union cvmx_pciercx_cfg013
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg013_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_8_31                : 24;
+	uint32_t cp                           : 8;  /**< First Capability Pointer.
+                                                         Points to Power Management Capability structure by
+                                                         default, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t cp                           : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg013_s          cn52xx;
+	struct cvmx_pciercx_cfg013_s          cn52xxp1;
+	struct cvmx_pciercx_cfg013_s          cn56xx;
+	struct cvmx_pciercx_cfg013_s          cn56xxp1;
+	struct cvmx_pciercx_cfg013_s          cn63xx;
+	struct cvmx_pciercx_cfg013_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t;
+
+/**
+ * cvmx_pcierc#_cfg014
+ *
+ * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register)
+ *
+ */
+union cvmx_pciercx_cfg014
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg014_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg014_s          cn52xx;
+	struct cvmx_pciercx_cfg014_s          cn52xxp1;
+	struct cvmx_pciercx_cfg014_s          cn56xx;
+	struct cvmx_pciercx_cfg014_s          cn56xxp1;
+	struct cvmx_pciercx_cfg014_s          cn63xx;
+	struct cvmx_pciercx_cfg014_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t;
+
+/**
+ * cvmx_pcierc#_cfg015
+ *
+ * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
+ *
+ */
+union cvmx_pciercx_cfg015
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg015_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_28_31               : 4;
+	uint32_t dtsees                       : 1;  /**< Discard Timer SERR Enable Status
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t dts                          : 1;  /**< Discard Timer Status
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t sdt                          : 1;  /**< Secondary Discard Timer
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t pdt                          : 1;  /**< Primary Discard Timer
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t fbbe                         : 1;  /**< Fast Back-to-Back Transactions Enable
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t sbrst                        : 1;  /**< Secondary Bus Reset
+                                                         Hot reset. Causes TS1s with the hot reset bit to be sent to
+                                                         the link partner. When set, SW should wait 2ms before
+                                                         clearing. The link partner normally responds by sending TS1s
+                                                         with the hot reset bit set, which will cause a link
+                                                         down event - refer to "PCIe Link-Down Reset in RC Mode"
+                                                         section. */
+	uint32_t mam                          : 1;  /**< Master Abort Mode
+                                                         Not applicable to PCI Express, hardwired to 0. */
+	uint32_t vga16d                       : 1;  /**< VGA 16-Bit Decode */
+	uint32_t vgae                         : 1;  /**< VGA Enable */
+	uint32_t isae                         : 1;  /**< ISA Enable */
+	uint32_t see                          : 1;  /**< SERR Enable */
+	uint32_t pere                         : 1;  /**< Parity Error Response Enable */
+	uint32_t inta                         : 8;  /**< Interrupt Pin
+                                                         Identifies the legacy interrupt Message that the device
+                                                         (or device function) uses.
+                                                         The Interrupt Pin register is writable through PEM(0..1)_CFG_WR.
+                                                         In a single-function configuration, only INTA is used.
+                                                         Therefore, the application must not change this field. */
+	uint32_t il                           : 8;  /**< Interrupt Line */
+#else
+	uint32_t il                           : 8;
+	uint32_t inta                         : 8;
+	uint32_t pere                         : 1;
+	uint32_t see                          : 1;
+	uint32_t isae                         : 1;
+	uint32_t vgae                         : 1;
+	uint32_t vga16d                       : 1;
+	uint32_t mam                          : 1;
+	uint32_t sbrst                        : 1;
+	uint32_t fbbe                         : 1;
+	uint32_t pdt                          : 1;
+	uint32_t sdt                          : 1;
+	uint32_t dts                          : 1;
+	uint32_t dtsees                       : 1;
+	uint32_t reserved_28_31               : 4;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg015_s          cn52xx;
+	struct cvmx_pciercx_cfg015_s          cn52xxp1;
+	struct cvmx_pciercx_cfg015_s          cn56xx;
+	struct cvmx_pciercx_cfg015_s          cn56xxp1;
+	struct cvmx_pciercx_cfg015_s          cn63xx;
+	struct cvmx_pciercx_cfg015_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t;
+
+/**
+ * cvmx_pcierc#_cfg016
+ *
+ * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space
+ * (Power Management Capability ID/
+ * Power Management Next Item Pointer/
+ * Power Management Capabilities Register)
+ */
+union cvmx_pciercx_cfg016
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg016_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmes                         : 5;  /**< PME_Support
+                                                         A value of 0 for any bit indicates that the
+                                                         device (or function) is not capable of generating PME Messages
+                                                         while in that power state:
+                                                         o Bit 11: If set, PME Messages can be generated from D0
+                                                         o Bit 12: If set, PME Messages can be generated from D1
+                                                         o Bit 13: If set, PME Messages can be generated from D2
+                                                         o Bit 14: If set, PME Messages can be generated from D3hot
+                                                         o Bit 15: If set, PME Messages can be generated from D3cold
+                                                         The PME_Support field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t d2s                          : 1;  /**< D2 Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t d1s                          : 1;  /**< D1 Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t auxc                         : 3;  /**< AUX Current, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t dsi                          : 1;  /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t pme_clock                    : 1;  /**< PME Clock, hardwired to 0 */
+	uint32_t pmsv                         : 3;  /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to the MSI capabilities by default, writable
+                                                         through PEM(0..1)_CFG_WR. */
+	uint32_t pmcid                        : 8;  /**< Power Management Capability ID */
+#else
+	uint32_t pmcid                        : 8;
+	uint32_t ncp                          : 8;
+	uint32_t pmsv                         : 3;
+	uint32_t pme_clock                    : 1;
+	uint32_t reserved_20_20               : 1;
+	uint32_t dsi                          : 1;
+	uint32_t auxc                         : 3;
+	uint32_t d1s                          : 1;
+	uint32_t d2s                          : 1;
+	uint32_t pmes                         : 5;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg016_s          cn52xx;
+	struct cvmx_pciercx_cfg016_s          cn52xxp1;
+	struct cvmx_pciercx_cfg016_s          cn56xx;
+	struct cvmx_pciercx_cfg016_s          cn56xxp1;
+	struct cvmx_pciercx_cfg016_s          cn63xx;
+	struct cvmx_pciercx_cfg016_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t;
+
+/**
+ * cvmx_pcierc#_cfg017
+ *
+ * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register)
+ *
+ */
+union cvmx_pciercx_cfg017
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg017_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pmdia                        : 8;  /**< Data register for additional information (not supported) */
+	uint32_t bpccee                       : 1;  /**< Bus Power/Clock Control Enable, hardwired to 0 */
+	uint32_t bd3h                         : 1;  /**< B2/B3 Support, hardwired to 0 */
+	uint32_t reserved_16_21               : 6;
+	uint32_t pmess                        : 1;  /**< PME Status
+                                                         Indicates if a previously enabled PME event occurred or not. */
+	uint32_t pmedsia                      : 2;  /**< Data Scale (not supported) */
+	uint32_t pmds                         : 4;  /**< Data Select (not supported) */
+	uint32_t pmeens                       : 1;  /**< PME Enable
+                                                         A value of 1 indicates that the device is enabled to
+                                                         generate PME. */
+	uint32_t reserved_4_7                 : 4;
+	uint32_t nsr                          : 1;  /**< No Soft Reset, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t ps                           : 2;  /**< Power State
+                                                         Controls the device power state:
+                                                           o 00b: D0
+                                                           o 01b: D1
+                                                           o 10b: D2
+                                                           o 11b: D3
+                                                         The written value is ignored if the specific state is
+                                                         not supported. */
+#else
+	uint32_t ps                           : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t nsr                          : 1;
+	uint32_t reserved_4_7                 : 4;
+	uint32_t pmeens                       : 1;
+	uint32_t pmds                         : 4;
+	uint32_t pmedsia                      : 2;
+	uint32_t pmess                        : 1;
+	uint32_t reserved_16_21               : 6;
+	uint32_t bd3h                         : 1;
+	uint32_t bpccee                       : 1;
+	uint32_t pmdia                        : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg017_s          cn52xx;
+	struct cvmx_pciercx_cfg017_s          cn52xxp1;
+	struct cvmx_pciercx_cfg017_s          cn56xx;
+	struct cvmx_pciercx_cfg017_s          cn56xxp1;
+	struct cvmx_pciercx_cfg017_s          cn63xx;
+	struct cvmx_pciercx_cfg017_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t;
+
+/**
+ * cvmx_pcierc#_cfg020
+ *
+ * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space
+ * (MSI Capability ID/
+ *  MSI Next Item Pointer/
+ *  MSI Control Register)
+ */
+union cvmx_pciercx_cfg020
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg020_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t m64                          : 1;  /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mme                          : 3;  /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+	uint32_t mmc                          : 3;  /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t msien                        : 1;  /**< MSI Enabled
+                                                         When set, INTx must be disabled.
+                                                         This bit must never be set, as internal-MSI is not supported in
+                                                         RC mode. (Note that this has no effect on external MSI, which
+                                                         will be commonly used in RC mode.) */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t msicid                       : 8;  /**< MSI Capability ID */
+#else
+	uint32_t msicid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t msien                        : 1;
+	uint32_t mmc                          : 3;
+	uint32_t mme                          : 3;
+	uint32_t m64                          : 1;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg020_s          cn52xx;
+	struct cvmx_pciercx_cfg020_s          cn52xxp1;
+	struct cvmx_pciercx_cfg020_s          cn56xx;
+	struct cvmx_pciercx_cfg020_s          cn56xxp1;
+	struct cvmx_pciercx_cfg020_s          cn63xx;
+	struct cvmx_pciercx_cfg020_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t;
+
+/**
+ * cvmx_pcierc#_cfg021
+ *
+ * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register)
+ *
+ */
+union cvmx_pciercx_cfg021
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg021_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lmsi                         : 30; /**< Lower 32-bit Address */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t lmsi                         : 30;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg021_s          cn52xx;
+	struct cvmx_pciercx_cfg021_s          cn52xxp1;
+	struct cvmx_pciercx_cfg021_s          cn56xx;
+	struct cvmx_pciercx_cfg021_s          cn56xxp1;
+	struct cvmx_pciercx_cfg021_s          cn63xx;
+	struct cvmx_pciercx_cfg021_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t;
+
+/**
+ * cvmx_pcierc#_cfg022
+ *
+ * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register)
+ *
+ */
+union cvmx_pciercx_cfg022
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg022_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t umsi                         : 32; /**< Upper 32-bit Address */
+#else
+	uint32_t umsi                         : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg022_s          cn52xx;
+	struct cvmx_pciercx_cfg022_s          cn52xxp1;
+	struct cvmx_pciercx_cfg022_s          cn56xx;
+	struct cvmx_pciercx_cfg022_s          cn56xxp1;
+	struct cvmx_pciercx_cfg022_s          cn63xx;
+	struct cvmx_pciercx_cfg022_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t;
+
+/**
+ * cvmx_pcierc#_cfg023
+ *
+ * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register)
+ *
+ */
+union cvmx_pciercx_cfg023
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg023_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t msimd                        : 16; /**< MSI Data
+                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
+                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
+#else
+	uint32_t msimd                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg023_s          cn52xx;
+	struct cvmx_pciercx_cfg023_s          cn52xxp1;
+	struct cvmx_pciercx_cfg023_s          cn56xx;
+	struct cvmx_pciercx_cfg023_s          cn56xxp1;
+	struct cvmx_pciercx_cfg023_s          cn63xx;
+	struct cvmx_pciercx_cfg023_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t;
+
+/**
+ * cvmx_pcierc#_cfg028
+ *
+ * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space
+ * (PCI Express Capabilities List Register/
+ *  PCI Express Capabilities Register)
+ */
+union cvmx_pciercx_cfg028
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg028_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t imn                          : 5;  /**< Interrupt Message Number
+                                                         Updated by hardware, writable through PEM(0..1)_CFG_WR.
+                                                          However, the application must not change this field. */
+	uint32_t si                           : 1;  /**< Slot Implemented
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, it must 0 for an
+                                                         Endpoint device. Therefore, the application must not write a
+                                                         1 to this bit. */
+	uint32_t dpt                          : 4;  /**< Device Port Type */
+	uint32_t pciecv                       : 4;  /**< PCI Express Capability Version */
+	uint32_t ncp                          : 8;  /**< Next Capability Pointer
+                                                         writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t pcieid                       : 8;  /**< PCIE Capability ID */
+#else
+	uint32_t pcieid                       : 8;
+	uint32_t ncp                          : 8;
+	uint32_t pciecv                       : 4;
+	uint32_t dpt                          : 4;
+	uint32_t si                           : 1;
+	uint32_t imn                          : 5;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg028_s          cn52xx;
+	struct cvmx_pciercx_cfg028_s          cn52xxp1;
+	struct cvmx_pciercx_cfg028_s          cn56xx;
+	struct cvmx_pciercx_cfg028_s          cn56xxp1;
+	struct cvmx_pciercx_cfg028_s          cn63xx;
+	struct cvmx_pciercx_cfg028_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t;
+
+/**
+ * cvmx_pcierc#_cfg029
+ *
+ * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register)
+ *
+ */
+union cvmx_pciercx_cfg029
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg029_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_28_31               : 4;
+	uint32_t cspls                        : 2;  /**< Captured Slot Power Limit Scale
+                                                         Not applicable for RC port, upstream port only. */
+	uint32_t csplv                        : 8;  /**< Captured Slot Power Limit Value
+                                                         Not applicable for RC port, upstream port only. */
+	uint32_t reserved_16_17               : 2;
+	uint32_t rber                         : 1;  /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_12_14               : 3;
+	uint32_t el1al                        : 3;  /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         Must be 0x0 for non-endpoint devices. */
+	uint32_t el0al                        : 3;  /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+                                                         Must be 0x0 for non-endpoint devices. */
+	uint32_t etfs                         : 1;  /**< Extended Tag Field Supported
+                                                         This bit is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application
+                                                         must not write a 1 to this bit. */
+	uint32_t pfs                          : 2;  /**< Phantom Function Supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+	uint32_t mpss                         : 3;  /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mpss                         : 3;
+	uint32_t pfs                          : 2;
+	uint32_t etfs                         : 1;
+	uint32_t el0al                        : 3;
+	uint32_t el1al                        : 3;
+	uint32_t reserved_12_14               : 3;
+	uint32_t rber                         : 1;
+	uint32_t reserved_16_17               : 2;
+	uint32_t csplv                        : 8;
+	uint32_t cspls                        : 2;
+	uint32_t reserved_28_31               : 4;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg029_s          cn52xx;
+	struct cvmx_pciercx_cfg029_s          cn52xxp1;
+	struct cvmx_pciercx_cfg029_s          cn56xx;
+	struct cvmx_pciercx_cfg029_s          cn56xxp1;
+	struct cvmx_pciercx_cfg029_s          cn63xx;
+	struct cvmx_pciercx_cfg029_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t;
+
+/**
+ * cvmx_pcierc#_cfg030
+ *
+ * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space
+ * (Device Control Register/Device Status Register)
+ */
+union cvmx_pciercx_cfg030
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg030_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_22_31               : 10;
+	uint32_t tp                           : 1;  /**< Transaction Pending
+                                                         Set to 1 when Non-Posted Requests are not yet completed
+                                                         and clear when they are completed. */
+	uint32_t ap_d                         : 1;  /**< Aux Power Detected
+                                                         Set to 1 if Aux power detected. */
+	uint32_t ur_d                         : 1;  /**< Unsupported Request Detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         UR_D occurs when we receive something we don't support.
+                                                         Unsupported requests are Nonfatal errors, so UR_D should
+                                                         cause NFE_D.  Receiving a  vendor defined message should
+                                                         cause an unsupported request. */
+	uint32_t fe_d                         : 1;  /**< Fatal Error Detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
+                                                         has a severity set to Fatal.  Malformed TLP's generally fit
+                                                         into this category. */
+	uint32_t nfe_d                        : 1;  /**< Non-Fatal Error detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
+                                                         that has a severity set to Nonfatal and does NOT meet Advisory
+                                                         Nonfatal criteria , which
+                                                         most poisoned TLP's should be. */
+	uint32_t ce_d                         : 1;  /**< Correctable Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
+                                                         for example a Replay Timer Timeout.  Also, it can be set if
+                                                         we get any of the errors in PCIE_CFG066 that has a severity
+                                                         set to Nonfatal and meets the Advisory Nonfatal criteria,
+                                                         which most ECRC errors should be. */
+	uint32_t reserved_15_15               : 1;
+	uint32_t mrrs                         : 3;  /**< Max Read Request Size
+                                                          0 = 128B
+                                                          1 = 256B
+                                                          2 = 512B
+                                                          3 = 1024B
+                                                          4 = 2048B
+                                                          5 = 4096B
+                                                         Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and
+                                                               also must be set properly.
+                                                               SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must
+                                                               not exceed the desired max read request size. */
+	uint32_t ns_en                        : 1;  /**< Enable No Snoop */
+	uint32_t ap_en                        : 1;  /**< AUX Power PM Enable */
+	uint32_t pf_en                        : 1;  /**< Phantom Function Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         phantom functions. */
+	uint32_t etf_en                       : 1;  /**< Extended Tag Field Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         extended tags. */
+	uint32_t mps                          : 3;  /**< Max Payload Size
+                                                          Legal values:
+                                                           0  = 128B
+                                                           1  = 256B
+                                                          Larger sizes not supported.
+                                                         Note: Both PCI Express Ports must be set to the same value
+                                                               for Peer-to-Peer to function properly.
+                                                         Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same
+                                                               value for proper functionality. */
+	uint32_t ro_en                        : 1;  /**< Enable Relaxed Ordering */
+	uint32_t ur_en                        : 1;  /**< Unsupported Request Reporting Enable */
+	uint32_t fe_en                        : 1;  /**< Fatal Error Reporting Enable */
+	uint32_t nfe_en                       : 1;  /**< Non-Fatal Error Reporting Enable */
+	uint32_t ce_en                        : 1;  /**< Correctable Error Reporting Enable */
+#else
+	uint32_t ce_en                        : 1;
+	uint32_t nfe_en                       : 1;
+	uint32_t fe_en                        : 1;
+	uint32_t ur_en                        : 1;
+	uint32_t ro_en                        : 1;
+	uint32_t mps                          : 3;
+	uint32_t etf_en                       : 1;
+	uint32_t pf_en                        : 1;
+	uint32_t ap_en                        : 1;
+	uint32_t ns_en                        : 1;
+	uint32_t mrrs                         : 3;
+	uint32_t reserved_15_15               : 1;
+	uint32_t ce_d                         : 1;
+	uint32_t nfe_d                        : 1;
+	uint32_t fe_d                         : 1;
+	uint32_t ur_d                         : 1;
+	uint32_t ap_d                         : 1;
+	uint32_t tp                           : 1;
+	uint32_t reserved_22_31               : 10;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg030_s          cn52xx;
+	struct cvmx_pciercx_cfg030_s          cn52xxp1;
+	struct cvmx_pciercx_cfg030_s          cn56xx;
+	struct cvmx_pciercx_cfg030_s          cn56xxp1;
+	struct cvmx_pciercx_cfg030_s          cn63xx;
+	struct cvmx_pciercx_cfg030_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t;
+
+/**
+ * cvmx_pcierc#_cfg031
+ *
+ * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space
+ * (Link Capabilities Register)
+ */
+union cvmx_pciercx_cfg031
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg031_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pnum                         : 8;  /**< Port Number, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t lbnc                         : 1;  /**< Link Bandwith Notification Capability */
+	uint32_t dllarc                       : 1;  /**< Data Link Layer Active Reporting Capable
+                                                         Set to 1 for Root Complex devices and 0 for Endpoint devices. */
+	uint32_t sderc                        : 1;  /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t cpm                          : 1;  /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l1el                         : 3;  /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t l0el                         : 3;  /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t aslpms                       : 2;  /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t mlw                          : 6;  /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */
+	uint32_t mls                          : 4;  /**< Maximum Link Speed
+                                                         The following values are accepted:
+                                                         0001b: 2.5 GHz supported
+                                                         0010b: 5.0 GHz and 2.5 GHz supported
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t mls                          : 4;
+	uint32_t mlw                          : 6;
+	uint32_t aslpms                       : 2;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t cpm                          : 1;
+	uint32_t sderc                        : 1;
+	uint32_t dllarc                       : 1;
+	uint32_t lbnc                         : 1;
+	uint32_t reserved_22_23               : 2;
+	uint32_t pnum                         : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg031_s          cn52xx;
+	struct cvmx_pciercx_cfg031_s          cn52xxp1;
+	struct cvmx_pciercx_cfg031_s          cn56xx;
+	struct cvmx_pciercx_cfg031_s          cn56xxp1;
+	struct cvmx_pciercx_cfg031_s          cn63xx;
+	struct cvmx_pciercx_cfg031_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t;
+
+/**
+ * cvmx_pcierc#_cfg032
+ *
+ * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space
+ * (Link Control Register/Link Status Register)
+ */
+union cvmx_pciercx_cfg032
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg032_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lab                          : 1;  /**< Link Autonomous Bandwidth Status */
+	uint32_t lbm                          : 1;  /**< Link Bandwidth Management Status */
+	uint32_t dlla                         : 1;  /**< Data Link Layer Active */
+	uint32_t scc                          : 1;  /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector. The default
+                                                         value is the value you select during hardware configuration,
+                                                         writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t lt                           : 1;  /**< Link Training */
+	uint32_t reserved_26_26               : 1;
+	uint32_t nlw                          : 6;  /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization. */
+	uint32_t ls                           : 4;  /**< Link Speed
+                                                         The negotiated Link speed: 2.5 Gbps */
+	uint32_t reserved_12_15               : 4;
+	uint32_t lab_int_enb                  : 1;  /**< Link Autonomous Bandwidth Interrupt Enable
+                                                         This interrupt is for Gen2 and is not supported. This bit should
+                                                         always be written to zero. */
+	uint32_t lbm_int_enb                  : 1;  /**< Link Bandwidth Management Interrupt Enable
+                                                         This interrupt is for Gen2 and is not supported. This bit should
+                                                         always be written to zero. */
+	uint32_t hawd                         : 1;  /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+	uint32_t ecpm                         : 1;  /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+	uint32_t es                           : 1;  /**< Extended Synch */
+	uint32_t ccc                          : 1;  /**< Common Clock Configuration */
+	uint32_t rl                           : 1;  /**< Retrain Link */
+	uint32_t ld                           : 1;  /**< Link Disable */
+	uint32_t rcb                          : 1;  /**< Read Completion Boundary (RCB), writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field
+                                                         because an RCB of 64 bytes is not supported. */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t aslpc                        : 2;  /**< Active State Link PM Control */
+#else
+	uint32_t aslpc                        : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t rcb                          : 1;
+	uint32_t ld                           : 1;
+	uint32_t rl                           : 1;
+	uint32_t ccc                          : 1;
+	uint32_t es                           : 1;
+	uint32_t ecpm                         : 1;
+	uint32_t hawd                         : 1;
+	uint32_t lbm_int_enb                  : 1;
+	uint32_t lab_int_enb                  : 1;
+	uint32_t reserved_12_15               : 4;
+	uint32_t ls                           : 4;
+	uint32_t nlw                          : 6;
+	uint32_t reserved_26_26               : 1;
+	uint32_t lt                           : 1;
+	uint32_t scc                          : 1;
+	uint32_t dlla                         : 1;
+	uint32_t lbm                          : 1;
+	uint32_t lab                          : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg032_s          cn52xx;
+	struct cvmx_pciercx_cfg032_s          cn52xxp1;
+	struct cvmx_pciercx_cfg032_s          cn56xx;
+	struct cvmx_pciercx_cfg032_s          cn56xxp1;
+	struct cvmx_pciercx_cfg032_s          cn63xx;
+	struct cvmx_pciercx_cfg032_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t;
+
+/**
+ * cvmx_pcierc#_cfg033
+ *
+ * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space
+ * (Slot Capabilities Register)
+ */
+union cvmx_pciercx_cfg033
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg033_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ps_num                       : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t nccs                         : 1;  /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t emip                         : 1;  /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t sp_ls                        : 2;  /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR. */
+	uint32_t sp_lv                        : 8;  /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR. */
+	uint32_t hp_c                         : 1;  /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t hp_s                         : 1;  /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pip                          : 1;  /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t aip                          : 1;  /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t mrlsp                        : 1;  /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t pcp                          : 1;  /**< Power Controller Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+	uint32_t abp                          : 1;  /**< Attention Button Present, writable through PEM(0..1)_CFG_WR
+                                                         However, the application must not change this field. */
+#else
+	uint32_t abp                          : 1;
+	uint32_t pcp                          : 1;
+	uint32_t mrlsp                        : 1;
+	uint32_t aip                          : 1;
+	uint32_t pip                          : 1;
+	uint32_t hp_s                         : 1;
+	uint32_t hp_c                         : 1;
+	uint32_t sp_lv                        : 8;
+	uint32_t sp_ls                        : 2;
+	uint32_t emip                         : 1;
+	uint32_t nccs                         : 1;
+	uint32_t ps_num                       : 13;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg033_s          cn52xx;
+	struct cvmx_pciercx_cfg033_s          cn52xxp1;
+	struct cvmx_pciercx_cfg033_s          cn56xx;
+	struct cvmx_pciercx_cfg033_s          cn56xxp1;
+	struct cvmx_pciercx_cfg033_s          cn63xx;
+	struct cvmx_pciercx_cfg033_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t;
+
+/**
+ * cvmx_pcierc#_cfg034
+ *
+ * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space
+ * (Slot Control Register/Slot Status Register)
+ */
+union cvmx_pciercx_cfg034
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg034_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_25_31               : 7;
+	uint32_t dlls_c                       : 1;  /**< Data Link Layer State Changed */
+	uint32_t emis                         : 1;  /**< Electromechanical Interlock Status */
+	uint32_t pds                          : 1;  /**< Presence Detect State */
+	uint32_t mrlss                        : 1;  /**< MRL Sensor State */
+	uint32_t ccint_d                      : 1;  /**< Command Completed */
+	uint32_t pd_c                         : 1;  /**< Presence Detect Changed */
+	uint32_t mrls_c                       : 1;  /**< MRL Sensor Changed */
+	uint32_t pf_d                         : 1;  /**< Power Fault Detected */
+	uint32_t abp_d                        : 1;  /**< Attention Button Pressed */
+	uint32_t reserved_13_15               : 3;
+	uint32_t dlls_en                      : 1;  /**< Data Link Layer State Changed Enable */
+	uint32_t emic                         : 1;  /**< Electromechanical Interlock Control */
+	uint32_t pcc                          : 1;  /**< Power Controller Control */
+	uint32_t pic                          : 2;  /**< Power Indicator Control */
+	uint32_t aic                          : 2;  /**< Attention Indicator Control */
+	uint32_t hpint_en                     : 1;  /**< Hot-Plug Interrupt Enable */
+	uint32_t ccint_en                     : 1;  /**< Command Completed Interrupt Enable */
+	uint32_t pd_en                        : 1;  /**< Presence Detect Changed Enable */
+	uint32_t mrls_en                      : 1;  /**< MRL Sensor Changed Enable */
+	uint32_t pf_en                        : 1;  /**< Power Fault Detected Enable */
+	uint32_t abp_en                       : 1;  /**< Attention Button Pressed Enable */
+#else
+	uint32_t abp_en                       : 1;
+	uint32_t pf_en                        : 1;
+	uint32_t mrls_en                      : 1;
+	uint32_t pd_en                        : 1;
+	uint32_t ccint_en                     : 1;
+	uint32_t hpint_en                     : 1;
+	uint32_t aic                          : 2;
+	uint32_t pic                          : 2;
+	uint32_t pcc                          : 1;
+	uint32_t emic                         : 1;
+	uint32_t dlls_en                      : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t abp_d                        : 1;
+	uint32_t pf_d                         : 1;
+	uint32_t mrls_c                       : 1;
+	uint32_t pd_c                         : 1;
+	uint32_t ccint_d                      : 1;
+	uint32_t mrlss                        : 1;
+	uint32_t pds                          : 1;
+	uint32_t emis                         : 1;
+	uint32_t dlls_c                       : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg034_s          cn52xx;
+	struct cvmx_pciercx_cfg034_s          cn52xxp1;
+	struct cvmx_pciercx_cfg034_s          cn56xx;
+	struct cvmx_pciercx_cfg034_s          cn56xxp1;
+	struct cvmx_pciercx_cfg034_s          cn63xx;
+	struct cvmx_pciercx_cfg034_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t;
+
+/**
+ * cvmx_pcierc#_cfg035
+ *
+ * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space
+ * (Root Control Register/Root Capabilities Register)
+ */
+union cvmx_pciercx_cfg035
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg035_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_17_31               : 15;
+	uint32_t crssv                        : 1;  /**< CRS Software Visibility
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t reserved_5_15                : 11;
+	uint32_t crssve                       : 1;  /**< CRS Software Visibility Enable
+                                                         Not supported, hardwired to 0x0. */
+	uint32_t pmeie                        : 1;  /**< PME Interrupt Enable */
+	uint32_t sefee                        : 1;  /**< System Error on Fatal Error Enable */
+	uint32_t senfee                       : 1;  /**< System Error on Non-fatal Error Enable */
+	uint32_t secee                        : 1;  /**< System Error on Correctable Error Enable */
+#else
+	uint32_t secee                        : 1;
+	uint32_t senfee                       : 1;
+	uint32_t sefee                        : 1;
+	uint32_t pmeie                        : 1;
+	uint32_t crssve                       : 1;
+	uint32_t reserved_5_15                : 11;
+	uint32_t crssv                        : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg035_s          cn52xx;
+	struct cvmx_pciercx_cfg035_s          cn52xxp1;
+	struct cvmx_pciercx_cfg035_s          cn56xx;
+	struct cvmx_pciercx_cfg035_s          cn56xxp1;
+	struct cvmx_pciercx_cfg035_s          cn63xx;
+	struct cvmx_pciercx_cfg035_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t;
+
+/**
+ * cvmx_pcierc#_cfg036
+ *
+ * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space
+ * (Root Status Register)
+ */
+union cvmx_pciercx_cfg036
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg036_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_18_31               : 14;
+	uint32_t pme_pend                     : 1;  /**< PME Pending */
+	uint32_t pme_stat                     : 1;  /**< PME Status */
+	uint32_t pme_rid                      : 16; /**< PME Requester ID */
+#else
+	uint32_t pme_rid                      : 16;
+	uint32_t pme_stat                     : 1;
+	uint32_t pme_pend                     : 1;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg036_s          cn52xx;
+	struct cvmx_pciercx_cfg036_s          cn52xxp1;
+	struct cvmx_pciercx_cfg036_s          cn56xx;
+	struct cvmx_pciercx_cfg036_s          cn56xxp1;
+	struct cvmx_pciercx_cfg036_s          cn63xx;
+	struct cvmx_pciercx_cfg036_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t;
+
+/**
+ * cvmx_pcierc#_cfg037
+ *
+ * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space
+ * (Device Capabilities 2 Register)
+ */
+union cvmx_pciercx_cfg037
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg037_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t ctds                         : 1;  /**< Completion Timeout Disable Supported */
+	uint32_t ctrs                         : 4;  /**< Completion Timeout Ranges Supported
+                                                         Value of 0 indicates that Completion Timeout Programming
+                                                         is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+	uint32_t ctrs                         : 4;
+	uint32_t ctds                         : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg037_s          cn52xx;
+	struct cvmx_pciercx_cfg037_s          cn52xxp1;
+	struct cvmx_pciercx_cfg037_s          cn56xx;
+	struct cvmx_pciercx_cfg037_s          cn56xxp1;
+	struct cvmx_pciercx_cfg037_s          cn63xx;
+	struct cvmx_pciercx_cfg037_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t;
+
+/**
+ * cvmx_pcierc#_cfg038
+ *
+ * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space
+ * (Device Control 2 Register)
+ */
+union cvmx_pciercx_cfg038
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg038_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t ctd                          : 1;  /**< Completion Timeout Disable */
+	uint32_t ctv                          : 4;  /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+	uint32_t ctv                          : 4;
+	uint32_t ctd                          : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg038_s          cn52xx;
+	struct cvmx_pciercx_cfg038_s          cn52xxp1;
+	struct cvmx_pciercx_cfg038_s          cn56xx;
+	struct cvmx_pciercx_cfg038_s          cn56xxp1;
+	struct cvmx_pciercx_cfg038_s          cn63xx;
+	struct cvmx_pciercx_cfg038_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t;
+
+/**
+ * cvmx_pcierc#_cfg039
+ *
+ * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space
+ * (Link Capabilities 2 Register)
+ */
+union cvmx_pciercx_cfg039
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg039_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg039_s          cn52xx;
+	struct cvmx_pciercx_cfg039_s          cn52xxp1;
+	struct cvmx_pciercx_cfg039_s          cn56xx;
+	struct cvmx_pciercx_cfg039_s          cn56xxp1;
+	struct cvmx_pciercx_cfg039_s          cn63xx;
+	struct cvmx_pciercx_cfg039_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t;
+
+/**
+ * cvmx_pcierc#_cfg040
+ *
+ * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space
+ * (Link Control 2 Register/Link Status 2 Register)
+ */
+union cvmx_pciercx_cfg040
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg040_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_17_31               : 15;
+	uint32_t cdl                          : 1;  /**< Current De-emphasis Level
+                                                         When the Link is operating at 5 GT/s speed, this bit
+                                                         reflects the level of de-emphasis. Encodings:
+                                                          1b: -3.5 dB
+                                                          0b: -6 dB
+                                                         Note: The value in this bit is undefined when the Link is
+                                                         operating at 2.5 GT/s speed */
+	uint32_t reserved_13_15               : 3;
+	uint32_t cde                          : 1;  /**< Compliance De-emphasis
+                                                         This bit sets the de-emphasis level in Polling. Compliance
+                                                         state if the entry occurred due to the Tx Compliance
+                                                         Receive bit being 1b. Encodings:
+                                                          1b: -3.5 dB
+                                                          0b: -6 dB
+                                                         Note: When the Link is operating at 2.5 GT/s, the setting
+                                                         of this bit has no effect. */
+	uint32_t csos                         : 1;  /**< Compliance SOS
+                                                         When set to 1b, the LTSSM is required to send SKP
+                                                         Ordered Sets periodically in between the (modified)
+                                                         compliance patterns.
+                                                         Note: When the Link is operating at 2.5 GT/s, the setting
+                                                         of this bit has no effect. */
+	uint32_t emc                          : 1;  /**< Enter Modified Compliance
+                                                         When this bit is set to 1b, the device transmits a modified
+                                                         compliance pattern if the LTSSM enters Polling.
+                                                         Compliance state. */
+	uint32_t tm                           : 3;  /**< Transmit Margin
+                                                         This field controls the value of the non-de-emphasized
+                                                         voltage level at the Transmitter pins:
+                                                          - 000: 800-1200 mV for full swing 400-600 mV for half-swing
+                                                          - 001-010: values must be monotonic with a non-zero slope
+                                                          - 011: 200-400 mV for full-swing and 100-200 mV for halfswing
+                                                          - 100-111: reserved
+                                                         This field is reset to 000b on entry to the LTSSM Polling.
+                                                         Compliance substate.
+                                                         When operating in 5.0 GT/s mode with full swing, the
+                                                         de-emphasis ratio must be maintained within +/- 1 dB
+                                                         from the specification-defined operational value
+                                                         either -3.5 or -6 dB). */
+	uint32_t sde                          : 1;  /**< Selectable De-emphasis
+                                                         When the Link is operating at 5.0 GT/s speed, selects the
+                                                         level of de-emphasis:
+                                                         - 1: -3.5 dB
+                                                         - 0: -6 dB
+                                                         When the Link is operating at 2.5 GT/s speed, the setting
+                                                         of this bit has no effect. */
+	uint32_t hasd                         : 1;  /**< Hardware Autonomous Speed Disable
+                                                         When asserted, the
+                                                         application must disable hardware from changing the Link
+                                                         speed for device-specific reasons other than attempting to
+                                                         correct unreliable Link operation by reducing Link speed.
+                                                         Initial transition to the highest supported common link
+                                                         speed is not blocked by this signal. */
+	uint32_t ec                           : 1;  /**< Enter Compliance
+                                                         Software is permitted to force a link to enter Compliance
+                                                         mode at the speed indicated in the Target Link Speed
+                                                         field by setting this bit to 1b in both components on a link
+                                                         and then initiating a hot reset on the link. */
+	uint32_t tls                          : 4;  /**< Target Link Speed
+                                                         For Downstream ports, this field sets an upper limit on link
+                                                         operational speed by restricting the values advertised by
+                                                         the upstream component in its training sequences:
+                                                           - 0001: 2.5Gb/s Target Link Speed
+                                                           - 0010: 5Gb/s Target Link Speed
+                                                         All other encodings are reserved.
+                                                         If a value is written to this field that does not correspond to
+                                                         a speed included in the Supported Link Speeds field, the
+                                                         result is undefined.
+                                                         For both Upstream and Downstream ports, this field is
+                                                         used to set the target compliance mode speed when
+                                                         software is using the Enter Compliance bit to force a link
+                                                         into compliance mode.
+                                                         Out of reset this will have a value of 1 or 2 which is
+                                                         selected by qlmCfgx[1]. */
+#else
+	uint32_t tls                          : 4;
+	uint32_t ec                           : 1;
+	uint32_t hasd                         : 1;
+	uint32_t sde                          : 1;
+	uint32_t tm                           : 3;
+	uint32_t emc                          : 1;
+	uint32_t csos                         : 1;
+	uint32_t cde                          : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t cdl                          : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg040_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} cn52xx;
+	struct cvmx_pciercx_cfg040_cn52xx     cn52xxp1;
+	struct cvmx_pciercx_cfg040_cn52xx     cn56xx;
+	struct cvmx_pciercx_cfg040_cn52xx     cn56xxp1;
+	struct cvmx_pciercx_cfg040_s          cn63xx;
+	struct cvmx_pciercx_cfg040_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t;
+
+/**
+ * cvmx_pcierc#_cfg041
+ *
+ * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space
+ * (Slot Capabilities 2 Register)
+ */
+union cvmx_pciercx_cfg041
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg041_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg041_s          cn52xx;
+	struct cvmx_pciercx_cfg041_s          cn52xxp1;
+	struct cvmx_pciercx_cfg041_s          cn56xx;
+	struct cvmx_pciercx_cfg041_s          cn56xxp1;
+	struct cvmx_pciercx_cfg041_s          cn63xx;
+	struct cvmx_pciercx_cfg041_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t;
+
+/**
+ * cvmx_pcierc#_cfg042
+ *
+ * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space
+ * (Slot Control 2 Register/Slot Status 2 Register)
+ */
+union cvmx_pciercx_cfg042
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg042_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_0_31                : 32;
+#else
+	uint32_t reserved_0_31                : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg042_s          cn52xx;
+	struct cvmx_pciercx_cfg042_s          cn52xxp1;
+	struct cvmx_pciercx_cfg042_s          cn56xx;
+	struct cvmx_pciercx_cfg042_s          cn56xxp1;
+	struct cvmx_pciercx_cfg042_s          cn63xx;
+	struct cvmx_pciercx_cfg042_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t;
+
+/**
+ * cvmx_pcierc#_cfg064
+ *
+ * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space
+ * (PCI Express Enhanced Capability Header)
+ */
+union cvmx_pciercx_cfg064
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg064_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t nco                          : 12; /**< Next Capability Offset */
+	uint32_t cv                           : 4;  /**< Capability Version */
+	uint32_t pcieec                       : 16; /**< PCIE Express Extended Capability */
+#else
+	uint32_t pcieec                       : 16;
+	uint32_t cv                           : 4;
+	uint32_t nco                          : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg064_s          cn52xx;
+	struct cvmx_pciercx_cfg064_s          cn52xxp1;
+	struct cvmx_pciercx_cfg064_s          cn56xx;
+	struct cvmx_pciercx_cfg064_s          cn56xxp1;
+	struct cvmx_pciercx_cfg064_s          cn63xx;
+	struct cvmx_pciercx_cfg064_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t;
+
+/**
+ * cvmx_pcierc#_cfg065
+ *
+ * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Status Register)
+ */
+union cvmx_pciercx_cfg065
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg065_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Status */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Status */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Status */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Status */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Status */
+	uint32_t cas                          : 1;  /**< Completer Abort Status */
+	uint32_t cts                          : 1;  /**< Completion Timeout Status */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Status */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Status */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Status (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Status */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg065_s          cn52xx;
+	struct cvmx_pciercx_cfg065_s          cn52xxp1;
+	struct cvmx_pciercx_cfg065_s          cn56xx;
+	struct cvmx_pciercx_cfg065_s          cn56xxp1;
+	struct cvmx_pciercx_cfg065_s          cn63xx;
+	struct cvmx_pciercx_cfg065_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t;
+
+/**
+ * cvmx_pcierc#_cfg066
+ *
+ * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Mask Register)
+ */
+union cvmx_pciercx_cfg066
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg066_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t urem                         : 1;  /**< Unsupported Request Error Mask */
+	uint32_t ecrcem                       : 1;  /**< ECRC Error Mask */
+	uint32_t mtlpm                        : 1;  /**< Malformed TLP Mask */
+	uint32_t rom                          : 1;  /**< Receiver Overflow Mask */
+	uint32_t ucm                          : 1;  /**< Unexpected Completion Mask */
+	uint32_t cam                          : 1;  /**< Completer Abort Mask */
+	uint32_t ctm                          : 1;  /**< Completion Timeout Mask */
+	uint32_t fcpem                        : 1;  /**< Flow Control Protocol Error Mask */
+	uint32_t ptlpm                        : 1;  /**< Poisoned TLP Mask */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdem                         : 1;  /**< Surprise Down Error Mask (not supported) */
+	uint32_t dlpem                        : 1;  /**< Data Link Protocol Error Mask */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpem                        : 1;
+	uint32_t sdem                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlpm                        : 1;
+	uint32_t fcpem                        : 1;
+	uint32_t ctm                          : 1;
+	uint32_t cam                          : 1;
+	uint32_t ucm                          : 1;
+	uint32_t rom                          : 1;
+	uint32_t mtlpm                        : 1;
+	uint32_t ecrcem                       : 1;
+	uint32_t urem                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg066_s          cn52xx;
+	struct cvmx_pciercx_cfg066_s          cn52xxp1;
+	struct cvmx_pciercx_cfg066_s          cn56xx;
+	struct cvmx_pciercx_cfg066_s          cn56xxp1;
+	struct cvmx_pciercx_cfg066_s          cn63xx;
+	struct cvmx_pciercx_cfg066_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t;
+
+/**
+ * cvmx_pcierc#_cfg067
+ *
+ * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Severity Register)
+ */
+union cvmx_pciercx_cfg067
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg067_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t ures                         : 1;  /**< Unsupported Request Error Severity */
+	uint32_t ecrces                       : 1;  /**< ECRC Error Severity */
+	uint32_t mtlps                        : 1;  /**< Malformed TLP Severity */
+	uint32_t ros                          : 1;  /**< Receiver Overflow Severity */
+	uint32_t ucs                          : 1;  /**< Unexpected Completion Severity */
+	uint32_t cas                          : 1;  /**< Completer Abort Severity */
+	uint32_t cts                          : 1;  /**< Completion Timeout Severity */
+	uint32_t fcpes                        : 1;  /**< Flow Control Protocol Error Severity */
+	uint32_t ptlps                        : 1;  /**< Poisoned TLP Severity */
+	uint32_t reserved_6_11                : 6;
+	uint32_t sdes                         : 1;  /**< Surprise Down Error Severity (not supported) */
+	uint32_t dlpes                        : 1;  /**< Data Link Protocol Error Severity */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dlpes                        : 1;
+	uint32_t sdes                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t ptlps                        : 1;
+	uint32_t fcpes                        : 1;
+	uint32_t cts                          : 1;
+	uint32_t cas                          : 1;
+	uint32_t ucs                          : 1;
+	uint32_t ros                          : 1;
+	uint32_t mtlps                        : 1;
+	uint32_t ecrces                       : 1;
+	uint32_t ures                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg067_s          cn52xx;
+	struct cvmx_pciercx_cfg067_s          cn52xxp1;
+	struct cvmx_pciercx_cfg067_s          cn56xx;
+	struct cvmx_pciercx_cfg067_s          cn56xxp1;
+	struct cvmx_pciercx_cfg067_s          cn63xx;
+	struct cvmx_pciercx_cfg067_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t;
+
+/**
+ * cvmx_pcierc#_cfg068
+ *
+ * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space
+ * (Correctable Error Status Register)
+ */
+union cvmx_pciercx_cfg068
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg068_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t anfes                        : 1;  /**< Advisory Non-Fatal Error Status */
+	uint32_t rtts                         : 1;  /**< Replay Timer Timeout Status */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrs                         : 1;  /**< REPLAY_NUM Rollover Status */
+	uint32_t bdllps                       : 1;  /**< Bad DLLP Status */
+	uint32_t btlps                        : 1;  /**< Bad TLP Status */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t res                          : 1;  /**< Receiver Error Status */
+#else
+	uint32_t res                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlps                        : 1;
+	uint32_t bdllps                       : 1;
+	uint32_t rnrs                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rtts                         : 1;
+	uint32_t anfes                        : 1;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg068_s          cn52xx;
+	struct cvmx_pciercx_cfg068_s          cn52xxp1;
+	struct cvmx_pciercx_cfg068_s          cn56xx;
+	struct cvmx_pciercx_cfg068_s          cn56xxp1;
+	struct cvmx_pciercx_cfg068_s          cn63xx;
+	struct cvmx_pciercx_cfg068_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t;
+
+/**
+ * cvmx_pcierc#_cfg069
+ *
+ * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space
+ * (Correctable Error Mask Register)
+ */
+union cvmx_pciercx_cfg069
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg069_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t anfem                        : 1;  /**< Advisory Non-Fatal Error Mask */
+	uint32_t rttm                         : 1;  /**< Replay Timer Timeout Mask */
+	uint32_t reserved_9_11                : 3;
+	uint32_t rnrm                         : 1;  /**< REPLAY_NUM Rollover Mask */
+	uint32_t bdllpm                       : 1;  /**< Bad DLLP Mask */
+	uint32_t btlpm                        : 1;  /**< Bad TLP Mask */
+	uint32_t reserved_1_5                 : 5;
+	uint32_t rem                          : 1;  /**< Receiver Error Mask */
+#else
+	uint32_t rem                          : 1;
+	uint32_t reserved_1_5                 : 5;
+	uint32_t btlpm                        : 1;
+	uint32_t bdllpm                       : 1;
+	uint32_t rnrm                         : 1;
+	uint32_t reserved_9_11                : 3;
+	uint32_t rttm                         : 1;
+	uint32_t anfem                        : 1;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg069_s          cn52xx;
+	struct cvmx_pciercx_cfg069_s          cn52xxp1;
+	struct cvmx_pciercx_cfg069_s          cn56xx;
+	struct cvmx_pciercx_cfg069_s          cn56xxp1;
+	struct cvmx_pciercx_cfg069_s          cn63xx;
+	struct cvmx_pciercx_cfg069_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t;
+
+/**
+ * cvmx_pcierc#_cfg070
+ *
+ * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space
+ * (Advanced Capabilities and Control Register)
+ */
+union cvmx_pciercx_cfg070
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg070_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t ce                           : 1;  /**< ECRC Check Enable */
+	uint32_t cc                           : 1;  /**< ECRC Check Capable */
+	uint32_t ge                           : 1;  /**< ECRC Generation Enable */
+	uint32_t gc                           : 1;  /**< ECRC Generation Capability */
+	uint32_t fep                          : 5;  /**< First Error Pointer */
+#else
+	uint32_t fep                          : 5;
+	uint32_t gc                           : 1;
+	uint32_t ge                           : 1;
+	uint32_t cc                           : 1;
+	uint32_t ce                           : 1;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg070_s          cn52xx;
+	struct cvmx_pciercx_cfg070_s          cn52xxp1;
+	struct cvmx_pciercx_cfg070_s          cn56xx;
+	struct cvmx_pciercx_cfg070_s          cn56xxp1;
+	struct cvmx_pciercx_cfg070_s          cn63xx;
+	struct cvmx_pciercx_cfg070_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t;
+
+/**
+ * cvmx_pcierc#_cfg071
+ *
+ * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 1)
+ *
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+union cvmx_pciercx_cfg071
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg071_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword1                       : 32; /**< Header Log Register (first DWORD) */
+#else
+	uint32_t dword1                       : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg071_s          cn52xx;
+	struct cvmx_pciercx_cfg071_s          cn52xxp1;
+	struct cvmx_pciercx_cfg071_s          cn56xx;
+	struct cvmx_pciercx_cfg071_s          cn56xxp1;
+	struct cvmx_pciercx_cfg071_s          cn63xx;
+	struct cvmx_pciercx_cfg071_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t;
+
+/**
+ * cvmx_pcierc#_cfg072
+ *
+ * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 2)
+ *
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+union cvmx_pciercx_cfg072
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg072_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword2                       : 32; /**< Header Log Register (second DWORD) */
+#else
+	uint32_t dword2                       : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg072_s          cn52xx;
+	struct cvmx_pciercx_cfg072_s          cn52xxp1;
+	struct cvmx_pciercx_cfg072_s          cn56xx;
+	struct cvmx_pciercx_cfg072_s          cn56xxp1;
+	struct cvmx_pciercx_cfg072_s          cn63xx;
+	struct cvmx_pciercx_cfg072_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t;
+
+/**
+ * cvmx_pcierc#_cfg073
+ *
+ * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 3)
+ *
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+union cvmx_pciercx_cfg073
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg073_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword3                       : 32; /**< Header Log Register (third DWORD) */
+#else
+	uint32_t dword3                       : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg073_s          cn52xx;
+	struct cvmx_pciercx_cfg073_s          cn52xxp1;
+	struct cvmx_pciercx_cfg073_s          cn56xx;
+	struct cvmx_pciercx_cfg073_s          cn56xxp1;
+	struct cvmx_pciercx_cfg073_s          cn63xx;
+	struct cvmx_pciercx_cfg073_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t;
+
+/**
+ * cvmx_pcierc#_cfg074
+ *
+ * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 4)
+ *
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+union cvmx_pciercx_cfg074
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg074_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dword4                       : 32; /**< Header Log Register (fourth DWORD) */
+#else
+	uint32_t dword4                       : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg074_s          cn52xx;
+	struct cvmx_pciercx_cfg074_s          cn52xxp1;
+	struct cvmx_pciercx_cfg074_s          cn56xx;
+	struct cvmx_pciercx_cfg074_s          cn56xxp1;
+	struct cvmx_pciercx_cfg074_s          cn63xx;
+	struct cvmx_pciercx_cfg074_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t;
+
+/**
+ * cvmx_pcierc#_cfg075
+ *
+ * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space
+ * (Root Error Command Register)
+ */
+union cvmx_pciercx_cfg075
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg075_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t fere                         : 1;  /**< Fatal Error Reporting Enable */
+	uint32_t nfere                        : 1;  /**< Non-Fatal Error Reporting Enable */
+	uint32_t cere                         : 1;  /**< Correctable Error Reporting Enable */
+#else
+	uint32_t cere                         : 1;
+	uint32_t nfere                        : 1;
+	uint32_t fere                         : 1;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg075_s          cn52xx;
+	struct cvmx_pciercx_cfg075_s          cn52xxp1;
+	struct cvmx_pciercx_cfg075_s          cn56xx;
+	struct cvmx_pciercx_cfg075_s          cn56xxp1;
+	struct cvmx_pciercx_cfg075_s          cn63xx;
+	struct cvmx_pciercx_cfg075_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t;
+
+/**
+ * cvmx_pcierc#_cfg076
+ *
+ * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space
+ * (Root Error Status Register)
+ */
+union cvmx_pciercx_cfg076
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg076_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t aeimn                        : 5;  /**< Advanced Error Interrupt Message Number,
+                                                         writable through PEM(0..1)_CFG_WR */
+	uint32_t reserved_7_26                : 20;
+	uint32_t femr                         : 1;  /**< Fatal Error Messages Received */
+	uint32_t nfemr                        : 1;  /**< Non-Fatal Error Messages Received */
+	uint32_t fuf                          : 1;  /**< First Uncorrectable Fatal */
+	uint32_t multi_efnfr                  : 1;  /**< Multiple ERR_FATAL/NONFATAL Received */
+	uint32_t efnfr                        : 1;  /**< ERR_FATAL/NONFATAL Received */
+	uint32_t multi_ecr                    : 1;  /**< Multiple ERR_COR Received */
+	uint32_t ecr                          : 1;  /**< ERR_COR Received */
+#else
+	uint32_t ecr                          : 1;
+	uint32_t multi_ecr                    : 1;
+	uint32_t efnfr                        : 1;
+	uint32_t multi_efnfr                  : 1;
+	uint32_t fuf                          : 1;
+	uint32_t nfemr                        : 1;
+	uint32_t femr                         : 1;
+	uint32_t reserved_7_26                : 20;
+	uint32_t aeimn                        : 5;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg076_s          cn52xx;
+	struct cvmx_pciercx_cfg076_s          cn52xxp1;
+	struct cvmx_pciercx_cfg076_s          cn56xx;
+	struct cvmx_pciercx_cfg076_s          cn56xxp1;
+	struct cvmx_pciercx_cfg076_s          cn63xx;
+	struct cvmx_pciercx_cfg076_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t;
+
+/**
+ * cvmx_pcierc#_cfg077
+ *
+ * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space
+ * (Error Source Identification Register)
+ */
+union cvmx_pciercx_cfg077
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg077_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t efnfsi                       : 16; /**< ERR_FATAL/NONFATAL Source Identification */
+	uint32_t ecsi                         : 16; /**< ERR_COR Source Identification */
+#else
+	uint32_t ecsi                         : 16;
+	uint32_t efnfsi                       : 16;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg077_s          cn52xx;
+	struct cvmx_pciercx_cfg077_s          cn52xxp1;
+	struct cvmx_pciercx_cfg077_s          cn56xx;
+	struct cvmx_pciercx_cfg077_s          cn56xxp1;
+	struct cvmx_pciercx_cfg077_s          cn63xx;
+	struct cvmx_pciercx_cfg077_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t;
+
+/**
+ * cvmx_pcierc#_cfg448
+ *
+ * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space
+ * (Ack Latency Timer and Replay Timer Register)
+ */
+union cvmx_pciercx_cfg448
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg448_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t rtl                          : 16; /**< Replay Time Limit
+                                                         The replay timer expires when it reaches this limit. The PCI
+                                                         Express bus initiates a replay upon reception of a Nak or when
+                                                         the replay timer expires.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+	uint32_t rtltl                        : 16; /**< Round Trip Latency Time Limit
+                                                         The Ack/Nak latency timer expires when it reaches this limit.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+#else
+	uint32_t rtltl                        : 16;
+	uint32_t rtl                          : 16;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg448_s          cn52xx;
+	struct cvmx_pciercx_cfg448_s          cn52xxp1;
+	struct cvmx_pciercx_cfg448_s          cn56xx;
+	struct cvmx_pciercx_cfg448_s          cn56xxp1;
+	struct cvmx_pciercx_cfg448_s          cn63xx;
+	struct cvmx_pciercx_cfg448_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t;
+
+/**
+ * cvmx_pcierc#_cfg449
+ *
+ * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space
+ * (Other Message Register)
+ */
+union cvmx_pciercx_cfg449
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg449_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t omr                          : 32; /**< Other Message Register
+                                                         This register can be used for either of the following purposes:
+                                                         o To send a specific PCI Express Message, the application
+                                                           writes the payload of the Message into this register, then
+                                                           sets bit 0 of the Port Link Control Register to send the
+                                                           Message.
+                                                         o To store a corruption pattern for corrupting the LCRC on all
+                                                           TLPs, the application places a 32-bit corruption pattern into
+                                                           this register and enables this function by setting bit 25 of
+                                                           the Port Link Control Register. When enabled, the transmit
+                                                           LCRC result is XOR'd with this pattern before inserting
+                                                           it into the packet. */
+#else
+	uint32_t omr                          : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg449_s          cn52xx;
+	struct cvmx_pciercx_cfg449_s          cn52xxp1;
+	struct cvmx_pciercx_cfg449_s          cn56xx;
+	struct cvmx_pciercx_cfg449_s          cn56xxp1;
+	struct cvmx_pciercx_cfg449_s          cn63xx;
+	struct cvmx_pciercx_cfg449_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t;
+
+/**
+ * cvmx_pcierc#_cfg450
+ *
+ * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space
+ * (Port Force Link Register)
+ */
+union cvmx_pciercx_cfg450
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg450_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lpec                         : 8;  /**< Low Power Entrance Count
+                                                         The Power Management state will wait for this many clock cycles
+                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
+                                                         Power State (PS) field register to go low-power. This register
+                                                         is intended for applications that do not let the PCI Express
+                                                         bus handle a completion for configuration request to the
+                                                         Power Management Control and Status (PCIE_CFG017) register. */
+	uint32_t reserved_22_23               : 2;
+	uint32_t link_state                   : 6;  /**< Link State
+                                                         The Link state that the PCI Express Bus will be forced to
+                                                         when bit 15 (Force Link) is set.
+                                                         State encoding:
+                                                         o DETECT_QUIET              00h
+                                                         o DETECT_ACT                01h
+                                                         o POLL_ACTIVE               02h
+                                                         o POLL_COMPLIANCE           03h
+                                                         o POLL_CONFIG               04h
+                                                         o PRE_DETECT_QUIET          05h
+                                                         o DETECT_WAIT               06h
+                                                         o CFG_LINKWD_START          07h
+                                                         o CFG_LINKWD_ACEPT          08h
+                                                         o CFG_LANENUM_WAIT          09h
+                                                         o CFG_LANENUM_ACEPT         0Ah
+                                                         o CFG_COMPLETE              0Bh
+                                                         o CFG_IDLE                  0Ch
+                                                         o RCVRY_LOCK                0Dh
+                                                         o RCVRY_SPEED               0Eh
+                                                         o RCVRY_RCVRCFG             0Fh
+                                                         o RCVRY_IDLE                10h
+                                                         o L0                        11h
+                                                         o L0S                       12h
+                                                         o L123_SEND_EIDLE           13h
+                                                         o L1_IDLE                   14h
+                                                         o L2_IDLE                   15h
+                                                         o L2_WAKE                   16h
+                                                         o DISABLED_ENTRY            17h
+                                                         o DISABLED_IDLE             18h
+                                                         o DISABLED                  19h
+                                                         o LPBK_ENTRY                1Ah
+                                                         o LPBK_ACTIVE               1Bh
+                                                         o LPBK_EXIT                 1Ch
+                                                         o LPBK_EXIT_TIMEOUT         1Dh
+                                                         o HOT_RESET_ENTRY           1Eh
+                                                         o HOT_RESET                 1Fh */
+	uint32_t force_link                   : 1;  /**< Force Link
+                                                         Forces the Link to the state specified by the Link State field.
+                                                         The Force Link pulse will trigger Link re-negotiation.
+                                                         * As the The Force Link is a pulse, writing a 1 to it does
+                                                           trigger the forced link state event, even thought reading it
+                                                           always returns a 0. */
+	uint32_t reserved_8_14                : 7;
+	uint32_t link_num                     : 8;  /**< Link Number */
+#else
+	uint32_t link_num                     : 8;
+	uint32_t reserved_8_14                : 7;
+	uint32_t force_link                   : 1;
+	uint32_t link_state                   : 6;
+	uint32_t reserved_22_23               : 2;
+	uint32_t lpec                         : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg450_s          cn52xx;
+	struct cvmx_pciercx_cfg450_s          cn52xxp1;
+	struct cvmx_pciercx_cfg450_s          cn56xx;
+	struct cvmx_pciercx_cfg450_s          cn56xxp1;
+	struct cvmx_pciercx_cfg450_s          cn63xx;
+	struct cvmx_pciercx_cfg450_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t;
+
+/**
+ * cvmx_pcierc#_cfg451
+ *
+ * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space
+ * (Ack Frequency Register)
+ */
+union cvmx_pciercx_cfg451
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg451_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t l1el                         : 3;  /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+	uint32_t l0el                         : 3;  /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+	uint32_t n_fts_cc                     : 8;  /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: The core does not support a value of zero; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: The core does not support a value of zero; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+	uint32_t ack_freq                     : 8;  /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+	uint32_t ack_freq                     : 8;
+	uint32_t n_fts                        : 8;
+	uint32_t n_fts_cc                     : 8;
+	uint32_t l0el                         : 3;
+	uint32_t l1el                         : 3;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg451_s          cn52xx;
+	struct cvmx_pciercx_cfg451_s          cn52xxp1;
+	struct cvmx_pciercx_cfg451_s          cn56xx;
+	struct cvmx_pciercx_cfg451_s          cn56xxp1;
+	struct cvmx_pciercx_cfg451_s          cn63xx;
+	struct cvmx_pciercx_cfg451_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t;
+
+/**
+ * cvmx_pcierc#_cfg452
+ *
+ * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space
+ * (Port Link Control Register)
+ */
+union cvmx_pciercx_cfg452
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg452_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t eccrc                        : 1;  /**< Enable Corrupted CRC
+                                                         Causes corrupt LCRC for TLPs when set,
+                                                         using the pattern contained in the Other Message register.
+                                                         This is a test feature, not to be used in normal operation. */
+	uint32_t reserved_22_24               : 3;
+	uint32_t lme                          : 6;  /**< Link Mode Enable
+                                                         o 000001: x1
+                                                         o 000011: x2
+                                                         o 000111: x4
+                                                         o 001111: x8  (not supported)
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port. The value can be set less than 0x7
+                                                         to limit the number of lanes the PCIe will attempt to use.
+                                                         The programming of this field needs to be done by SW BEFORE
+                                                         enabling the link. See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width, so all
+                                                          of x4, x2, and x1 are supported when LME=0x7,
+                                                          for example.) */
+	uint32_t reserved_8_15                : 8;
+	uint32_t flm                          : 1;  /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes. */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t dllle                        : 1;  /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+	uint32_t reserved_4_4                 : 1;
+	uint32_t ra                           : 1;  /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+	uint32_t le                           : 1;  /**< Loopback Enable
+                                                         Initiate loopback mode as a master. On a 0->1 transition,
+                                                         the PCIe core sends TS ordered sets with the loopback bit set
+                                                         to cause the link partner to enter into loopback mode as a
+                                                         slave. Normal transmission is not possible when LE=1. To exit
+                                                         loopback mode, take the link through a reset sequence. */
+	uint32_t sd                           : 1;  /**< Scramble Disable
+                                                         Turns off data scrambling. */
+	uint32_t omr                          : 1;  /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+	uint32_t omr                          : 1;
+	uint32_t sd                           : 1;
+	uint32_t le                           : 1;
+	uint32_t ra                           : 1;
+	uint32_t reserved_4_4                 : 1;
+	uint32_t dllle                        : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t flm                          : 1;
+	uint32_t reserved_8_15                : 8;
+	uint32_t lme                          : 6;
+	uint32_t reserved_22_24               : 3;
+	uint32_t eccrc                        : 1;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg452_s          cn52xx;
+	struct cvmx_pciercx_cfg452_s          cn52xxp1;
+	struct cvmx_pciercx_cfg452_s          cn56xx;
+	struct cvmx_pciercx_cfg452_s          cn56xxp1;
+	struct cvmx_pciercx_cfg452_s          cn63xx;
+	struct cvmx_pciercx_cfg452_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t;
+
+/**
+ * cvmx_pcierc#_cfg453
+ *
+ * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space
+ * (Lane Skew Register)
+ */
+union cvmx_pciercx_cfg453
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg453_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dlld                         : 1;  /**< Disable Lane-to-Lane Deskew
+                                                         Disables the internal Lane-to-Lane deskew logic. */
+	uint32_t reserved_26_30               : 5;
+	uint32_t ack_nak                      : 1;  /**< Ack/Nak Disable
+                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
+	uint32_t fcd                          : 1;  /**< Flow Control Disable
+                                                         Prevents the PCI Express bus from sending FC DLLPs. */
+	uint32_t ilst                         : 24; /**< Insert Lane Skew for Transmit (not supported for x16)
+                                                         Causes skew between lanes for test purposes. There are three
+                                                         bits per Lane. The value is in units of one symbol time. For
+                                                         example, the value 010b for a Lane forces a skew of two symbol
+                                                         times for that Lane. The maximum skew value for any Lane is 5
+                                                         symbol times. */
+#else
+	uint32_t ilst                         : 24;
+	uint32_t fcd                          : 1;
+	uint32_t ack_nak                      : 1;
+	uint32_t reserved_26_30               : 5;
+	uint32_t dlld                         : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg453_s          cn52xx;
+	struct cvmx_pciercx_cfg453_s          cn52xxp1;
+	struct cvmx_pciercx_cfg453_s          cn56xx;
+	struct cvmx_pciercx_cfg453_s          cn56xxp1;
+	struct cvmx_pciercx_cfg453_s          cn63xx;
+	struct cvmx_pciercx_cfg453_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t;
+
+/**
+ * cvmx_pcierc#_cfg454
+ *
+ * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space
+ * (Symbol Number Register)
+ */
+union cvmx_pciercx_cfg454
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg454_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_29_31               : 3;
+	uint32_t tmfcwt                       : 5;  /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+	uint32_t tmanlt                       : 5;  /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+	uint32_t tmrt                         : 5;  /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+	uint32_t reserved_11_13               : 3;
+	uint32_t nskps                        : 3;  /**< Number of SKP Symbols */
+	uint32_t reserved_4_7                 : 4;
+	uint32_t ntss                         : 4;  /**< Number of TS Symbols
+                                                         Sets the number of TS identifier symbols that are sent in TS1
+                                                         and TS2 ordered sets. */
+#else
+	uint32_t ntss                         : 4;
+	uint32_t reserved_4_7                 : 4;
+	uint32_t nskps                        : 3;
+	uint32_t reserved_11_13               : 3;
+	uint32_t tmrt                         : 5;
+	uint32_t tmanlt                       : 5;
+	uint32_t tmfcwt                       : 5;
+	uint32_t reserved_29_31               : 3;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg454_s          cn52xx;
+	struct cvmx_pciercx_cfg454_s          cn52xxp1;
+	struct cvmx_pciercx_cfg454_s          cn56xx;
+	struct cvmx_pciercx_cfg454_s          cn56xxp1;
+	struct cvmx_pciercx_cfg454_s          cn63xx;
+	struct cvmx_pciercx_cfg454_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t;
+
+/**
+ * cvmx_pcierc#_cfg455
+ *
+ * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space
+ * (Symbol Timer Register/Filter Mask Register 1)
+ */
+union cvmx_pciercx_cfg455
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg455_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t m_cfg0_filt                  : 1;  /**< Mask filtering of received Configuration Requests (RC mode only) */
+	uint32_t m_io_filt                    : 1;  /**< Mask filtering of received I/O Requests (RC mode only) */
+	uint32_t msg_ctrl                     : 1;  /**< Message Control
+                                                         The application must not change this field. */
+	uint32_t m_cpl_ecrc_filt              : 1;  /**< Mask ECRC error filtering for Completions */
+	uint32_t m_ecrc_filt                  : 1;  /**< Mask ECRC error filtering */
+	uint32_t m_cpl_len_err                : 1;  /**< Mask Length mismatch error for received Completions */
+	uint32_t m_cpl_attr_err               : 1;  /**< Mask Attributes mismatch error for received Completions */
+	uint32_t m_cpl_tc_err                 : 1;  /**< Mask Traffic Class mismatch error for received Completions */
+	uint32_t m_cpl_fun_err                : 1;  /**< Mask function mismatch error for received Completions */
+	uint32_t m_cpl_rid_err                : 1;  /**< Mask Requester ID mismatch error for received Completions */
+	uint32_t m_cpl_tag_err                : 1;  /**< Mask Tag error rules for received Completions */
+	uint32_t m_lk_filt                    : 1;  /**< Mask Locked Request filtering */
+	uint32_t m_cfg1_filt                  : 1;  /**< Mask Type 1 Configuration Request filtering */
+	uint32_t m_bar_match                  : 1;  /**< Mask BAR match filtering */
+	uint32_t m_pois_filt                  : 1;  /**< Mask poisoned TLP filtering */
+	uint32_t m_fun                        : 1;  /**< Mask function */
+	uint32_t dfcwt                        : 1;  /**< Disable FC Watchdog Timer */
+	uint32_t reserved_11_14               : 4;
+	uint32_t skpiv                        : 11; /**< SKP Interval Value */
+#else
+	uint32_t skpiv                        : 11;
+	uint32_t reserved_11_14               : 4;
+	uint32_t dfcwt                        : 1;
+	uint32_t m_fun                        : 1;
+	uint32_t m_pois_filt                  : 1;
+	uint32_t m_bar_match                  : 1;
+	uint32_t m_cfg1_filt                  : 1;
+	uint32_t m_lk_filt                    : 1;
+	uint32_t m_cpl_tag_err                : 1;
+	uint32_t m_cpl_rid_err                : 1;
+	uint32_t m_cpl_fun_err                : 1;
+	uint32_t m_cpl_tc_err                 : 1;
+	uint32_t m_cpl_attr_err               : 1;
+	uint32_t m_cpl_len_err                : 1;
+	uint32_t m_ecrc_filt                  : 1;
+	uint32_t m_cpl_ecrc_filt              : 1;
+	uint32_t msg_ctrl                     : 1;
+	uint32_t m_io_filt                    : 1;
+	uint32_t m_cfg0_filt                  : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg455_s          cn52xx;
+	struct cvmx_pciercx_cfg455_s          cn52xxp1;
+	struct cvmx_pciercx_cfg455_s          cn56xx;
+	struct cvmx_pciercx_cfg455_s          cn56xxp1;
+	struct cvmx_pciercx_cfg455_s          cn63xx;
+	struct cvmx_pciercx_cfg455_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t;
+
+/**
+ * cvmx_pcierc#_cfg456
+ *
+ * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space
+ * (Filter Mask Register 2)
+ */
+union cvmx_pciercx_cfg456
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg456_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_2_31                : 30;
+	uint32_t m_vend1_drp                  : 1;  /**< Mask Vendor MSG Type 1 dropped silently */
+	uint32_t m_vend0_drp                  : 1;  /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+	uint32_t m_vend0_drp                  : 1;
+	uint32_t m_vend1_drp                  : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg456_s          cn52xx;
+	struct cvmx_pciercx_cfg456_s          cn52xxp1;
+	struct cvmx_pciercx_cfg456_s          cn56xx;
+	struct cvmx_pciercx_cfg456_s          cn56xxp1;
+	struct cvmx_pciercx_cfg456_s          cn63xx;
+	struct cvmx_pciercx_cfg456_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t;
+
+/**
+ * cvmx_pcierc#_cfg458
+ *
+ * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space
+ * (Debug Register 0)
+ */
+union cvmx_pciercx_cfg458
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg458_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dbg_info_l32                 : 32; /**< The value on cxpl_debug_info[31:0]. */
+#else
+	uint32_t dbg_info_l32                 : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg458_s          cn52xx;
+	struct cvmx_pciercx_cfg458_s          cn52xxp1;
+	struct cvmx_pciercx_cfg458_s          cn56xx;
+	struct cvmx_pciercx_cfg458_s          cn56xxp1;
+	struct cvmx_pciercx_cfg458_s          cn63xx;
+	struct cvmx_pciercx_cfg458_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t;
+
+/**
+ * cvmx_pcierc#_cfg459
+ *
+ * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space
+ * (Debug Register 1)
+ */
+union cvmx_pciercx_cfg459
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg459_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dbg_info_u32                 : 32; /**< The value on cxpl_debug_info[63:32]. */
+#else
+	uint32_t dbg_info_u32                 : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg459_s          cn52xx;
+	struct cvmx_pciercx_cfg459_s          cn52xxp1;
+	struct cvmx_pciercx_cfg459_s          cn56xx;
+	struct cvmx_pciercx_cfg459_s          cn56xxp1;
+	struct cvmx_pciercx_cfg459_s          cn63xx;
+	struct cvmx_pciercx_cfg459_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t;
+
+/**
+ * cvmx_pcierc#_cfg460
+ *
+ * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space
+ * (Transmit Posted FC Credit Status)
+ */
+union cvmx_pciercx_cfg460
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg460_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tphfcc                       : 8;  /**< Transmit Posted Header FC Credits
+                                                         The Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tpdfcc                       : 12; /**< Transmit Posted Data FC Credits
+                                                         The Posted Data credits advertised by the receiver at the other
+                                                         end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tpdfcc                       : 12;
+	uint32_t tphfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg460_s          cn52xx;
+	struct cvmx_pciercx_cfg460_s          cn52xxp1;
+	struct cvmx_pciercx_cfg460_s          cn56xx;
+	struct cvmx_pciercx_cfg460_s          cn56xxp1;
+	struct cvmx_pciercx_cfg460_s          cn63xx;
+	struct cvmx_pciercx_cfg460_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t;
+
+/**
+ * cvmx_pcierc#_cfg461
+ *
+ * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space
+ * (Transmit Non-Posted FC Credit Status)
+ */
+union cvmx_pciercx_cfg461
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg461_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tchfcc                       : 8;  /**< Transmit Non-Posted Header FC Credits
+                                                         The Non-Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tcdfcc                       : 12; /**< Transmit Non-Posted Data FC Credits
+                                                         The Non-Posted Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tcdfcc                       : 12;
+	uint32_t tchfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg461_s          cn52xx;
+	struct cvmx_pciercx_cfg461_s          cn52xxp1;
+	struct cvmx_pciercx_cfg461_s          cn56xx;
+	struct cvmx_pciercx_cfg461_s          cn56xxp1;
+	struct cvmx_pciercx_cfg461_s          cn63xx;
+	struct cvmx_pciercx_cfg461_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t;
+
+/**
+ * cvmx_pcierc#_cfg462
+ *
+ * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space
+ * (Transmit Completion FC Credit Status )
+ */
+union cvmx_pciercx_cfg462
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg462_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t tchfcc                       : 8;  /**< Transmit Completion Header FC Credits
+                                                         The Completion Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+	uint32_t tcdfcc                       : 12; /**< Transmit Completion Data FC Credits
+                                                         The Completion Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+	uint32_t tcdfcc                       : 12;
+	uint32_t tchfcc                       : 8;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg462_s          cn52xx;
+	struct cvmx_pciercx_cfg462_s          cn52xxp1;
+	struct cvmx_pciercx_cfg462_s          cn56xx;
+	struct cvmx_pciercx_cfg462_s          cn56xxp1;
+	struct cvmx_pciercx_cfg462_s          cn63xx;
+	struct cvmx_pciercx_cfg462_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t;
+
+/**
+ * cvmx_pcierc#_cfg463
+ *
+ * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space
+ * (Queue Status)
+ */
+union cvmx_pciercx_cfg463
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg463_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t rqne                         : 1;  /**< Received Queue Not Empty
+                                                         Indicates there is data in one or more of the receive buffers. */
+	uint32_t trbne                        : 1;  /**< Transmit Retry Buffer Not Empty
+                                                         Indicates that there is data in the transmit retry buffer. */
+	uint32_t rtlpfccnr                    : 1;  /**< Received TLP FC Credits Not Returned
+                                                         Indicates that the PCI Express bus has sent a TLP but has not
+                                                         yet received an UpdateFC DLLP indicating that the credits for
+                                                         that TLP have been restored by the receiver at the other end of
+                                                         the Link. */
+#else
+	uint32_t rtlpfccnr                    : 1;
+	uint32_t trbne                        : 1;
+	uint32_t rqne                         : 1;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg463_s          cn52xx;
+	struct cvmx_pciercx_cfg463_s          cn52xxp1;
+	struct cvmx_pciercx_cfg463_s          cn56xx;
+	struct cvmx_pciercx_cfg463_s          cn56xxp1;
+	struct cvmx_pciercx_cfg463_s          cn63xx;
+	struct cvmx_pciercx_cfg463_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t;
+
+/**
+ * cvmx_pcierc#_cfg464
+ *
+ * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space
+ * (VC Transmit Arbitration Register 1)
+ */
+union cvmx_pciercx_cfg464
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg464_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wrr_vc3                      : 8;  /**< WRR Weight for VC3 */
+	uint32_t wrr_vc2                      : 8;  /**< WRR Weight for VC2 */
+	uint32_t wrr_vc1                      : 8;  /**< WRR Weight for VC1 */
+	uint32_t wrr_vc0                      : 8;  /**< WRR Weight for VC0 */
+#else
+	uint32_t wrr_vc0                      : 8;
+	uint32_t wrr_vc1                      : 8;
+	uint32_t wrr_vc2                      : 8;
+	uint32_t wrr_vc3                      : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg464_s          cn52xx;
+	struct cvmx_pciercx_cfg464_s          cn52xxp1;
+	struct cvmx_pciercx_cfg464_s          cn56xx;
+	struct cvmx_pciercx_cfg464_s          cn56xxp1;
+	struct cvmx_pciercx_cfg464_s          cn63xx;
+	struct cvmx_pciercx_cfg464_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t;
+
+/**
+ * cvmx_pcierc#_cfg465
+ *
+ * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space
+ * (VC Transmit Arbitration Register 2)
+ */
+union cvmx_pciercx_cfg465
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg465_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wrr_vc7                      : 8;  /**< WRR Weight for VC7 */
+	uint32_t wrr_vc6                      : 8;  /**< WRR Weight for VC6 */
+	uint32_t wrr_vc5                      : 8;  /**< WRR Weight for VC5 */
+	uint32_t wrr_vc4                      : 8;  /**< WRR Weight for VC4 */
+#else
+	uint32_t wrr_vc4                      : 8;
+	uint32_t wrr_vc5                      : 8;
+	uint32_t wrr_vc6                      : 8;
+	uint32_t wrr_vc7                      : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg465_s          cn52xx;
+	struct cvmx_pciercx_cfg465_s          cn52xxp1;
+	struct cvmx_pciercx_cfg465_s          cn56xx;
+	struct cvmx_pciercx_cfg465_s          cn56xxp1;
+	struct cvmx_pciercx_cfg465_s          cn63xx;
+	struct cvmx_pciercx_cfg465_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t;
+
+/**
+ * cvmx_pcierc#_cfg466
+ *
+ * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space
+ * (VC0 Posted Receive Queue Control)
+ */
+union cvmx_pciercx_cfg466
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg466_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t rx_queue_order               : 1;  /**< VC Ordering for Receive Queues
+                                                         Determines the VC ordering rule for the receive queues, used
+                                                         only in the segmented-buffer configuration,
+                                                         writable through PEM(0..1)_CFG_WR:
+                                                         o 1: Strict ordering, higher numbered VCs have higher priority
+                                                         o 0: Round robin
+                                                         However, the application must not change this field. */
+	uint32_t type_ordering                : 1;  /**< TLP Type Ordering for VC0
+                                                         Determines the TLP type ordering rule for VC0 receive queues,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR:
+                                                         o 1: Ordering of received TLPs follows the rules in
+                                                              PCI Express Base Specification
+                                                         o 0: Strict ordering for received TLPs: Posted, then
+                                                              Completion, then Non-Posted
+                                                         However, the application must not change this field. */
+	uint32_t reserved_24_29               : 6;
+	uint32_t queue_mode                   : 3;  /**< VC0 Posted TLP Queue Mode
+                                                         The operating mode of the Posted receive queue for VC0, used
+                                                         only in the segmented-buffer configuration, writable through
+                                                         PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Posted Header Credits
+                                                         The number of initial Posted header credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Posted Data Credits
+                                                         The number of initial Posted data credits for VC0, used for all
+                                                         receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_29               : 6;
+	uint32_t type_ordering                : 1;
+	uint32_t rx_queue_order               : 1;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg466_s          cn52xx;
+	struct cvmx_pciercx_cfg466_s          cn52xxp1;
+	struct cvmx_pciercx_cfg466_s          cn56xx;
+	struct cvmx_pciercx_cfg466_s          cn56xxp1;
+	struct cvmx_pciercx_cfg466_s          cn63xx;
+	struct cvmx_pciercx_cfg466_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t;
+
+/**
+ * cvmx_pcierc#_cfg467
+ *
+ * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space
+ * (VC0 Non-Posted Receive Queue Control)
+ */
+union cvmx_pciercx_cfg467
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg467_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t queue_mode                   : 3;  /**< VC0 Non-Posted TLP Queue Mode
+                                                         The operating mode of the Non-Posted receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Non-Posted Header Credits
+                                                         The number of initial Non-Posted header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Non-Posted Data Credits
+                                                         The number of initial Non-Posted data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg467_s          cn52xx;
+	struct cvmx_pciercx_cfg467_s          cn52xxp1;
+	struct cvmx_pciercx_cfg467_s          cn56xx;
+	struct cvmx_pciercx_cfg467_s          cn56xxp1;
+	struct cvmx_pciercx_cfg467_s          cn63xx;
+	struct cvmx_pciercx_cfg467_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t;
+
+/**
+ * cvmx_pcierc#_cfg468
+ *
+ * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space
+ * (VC0 Completion Receive Queue Control)
+ */
+union cvmx_pciercx_cfg468
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg468_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t queue_mode                   : 3;  /**< VC0 Completion TLP Queue Mode
+                                                         The operating mode of the Completion receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t header_credits               : 8;  /**< VC0 Completion Header Credits
+                                                         The number of initial Completion header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t data_credits                 : 12; /**< VC0 Completion Data Credits
+                                                         The number of initial Completion data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_credits                 : 12;
+	uint32_t header_credits               : 8;
+	uint32_t reserved_20_20               : 1;
+	uint32_t queue_mode                   : 3;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg468_s          cn52xx;
+	struct cvmx_pciercx_cfg468_s          cn52xxp1;
+	struct cvmx_pciercx_cfg468_s          cn56xx;
+	struct cvmx_pciercx_cfg468_s          cn56xxp1;
+	struct cvmx_pciercx_cfg468_s          cn63xx;
+	struct cvmx_pciercx_cfg468_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t;
+
+/**
+ * cvmx_pcierc#_cfg490
+ *
+ * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space
+ * (VC0 Posted Buffer Depth)
+ */
+union cvmx_pciercx_cfg490
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg490_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Posted Header Queue Depth
+                                                         Sets the number of entries in the Posted header queue for VC0
+                                                         when using the segmented-buffer configuration, writable through
+                                                         PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Posted Data Queue Depth
+                                                         Sets the number of entries in the Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg490_s          cn52xx;
+	struct cvmx_pciercx_cfg490_s          cn52xxp1;
+	struct cvmx_pciercx_cfg490_s          cn56xx;
+	struct cvmx_pciercx_cfg490_s          cn56xxp1;
+	struct cvmx_pciercx_cfg490_s          cn63xx;
+	struct cvmx_pciercx_cfg490_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t;
+
+/**
+ * cvmx_pcierc#_cfg491
+ *
+ * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space
+ * (VC0 Non-Posted Buffer Depth)
+ */
+union cvmx_pciercx_cfg491
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg491_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Non-Posted Header Queue Depth
+                                                         Sets the number of entries in the Non-Posted header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Non-Posted Data Queue Depth
+                                                         Sets the number of entries in the Non-Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg491_s          cn52xx;
+	struct cvmx_pciercx_cfg491_s          cn52xxp1;
+	struct cvmx_pciercx_cfg491_s          cn56xx;
+	struct cvmx_pciercx_cfg491_s          cn56xxp1;
+	struct cvmx_pciercx_cfg491_s          cn63xx;
+	struct cvmx_pciercx_cfg491_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t;
+
+/**
+ * cvmx_pcierc#_cfg492
+ *
+ * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space
+ * (VC0 Completion Buffer Depth)
+ */
+union cvmx_pciercx_cfg492
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg492_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_26_31               : 6;
+	uint32_t header_depth                 : 10; /**< VC0 Completion Header Queue Depth
+                                                         Sets the number of entries in the Completion header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t data_depth                   : 14; /**< VC0 Completion Data Queue Depth
+                                                         Sets the number of entries in the Completion data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through PEM(0..1)_CFG_WR.
+                                                         However, the application must not change this field. */
+#else
+	uint32_t data_depth                   : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t header_depth                 : 10;
+	uint32_t reserved_26_31               : 6;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg492_s          cn52xx;
+	struct cvmx_pciercx_cfg492_s          cn52xxp1;
+	struct cvmx_pciercx_cfg492_s          cn56xx;
+	struct cvmx_pciercx_cfg492_s          cn56xxp1;
+	struct cvmx_pciercx_cfg492_s          cn63xx;
+	struct cvmx_pciercx_cfg492_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t;
+
+/**
+ * cvmx_pcierc#_cfg515
+ *
+ * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space
+ * (Port Logic Register (Gen2))
+ */
+union cvmx_pciercx_cfg515
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg515_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t s_d_e                        : 1;  /**< SEL_DE_EMPHASIS
+                                                         Used to set the de-emphasis level for upstream ports. */
+	uint32_t ctcrb                        : 1;  /**< Config Tx Compliance Receive Bit
+                                                         When set to 1, signals LTSSM to transmit TS ordered sets
+                                                         with the compliance receive bit assert (equal to 1). */
+	uint32_t cpyts                        : 1;  /**< Config PHY Tx Swing
+                                                         Indicates the voltage level the PHY should drive. When set to
+                                                         1, indicates Full Swing. When set to 0, indicates Low Swing */
+	uint32_t dsc                          : 1;  /**< Directed Speed Change
+                                                         Indicates to the LTSSM whether or not to initiate a speed
+                                                         change. */
+	uint32_t le                           : 9;  /**< Lane Enable
+                                                         Indicates the number of lanes to check for exit from electrical
+                                                         idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2,
+                                                         etc. Used to limit the maximum link width to ignore broken
+                                                         lanes that detect a receiver, but will not exit electrical
+                                                         idle and
+                                                         would otherwise prevent a valid link from being configured. */
+	uint32_t n_fts                        : 8;  /**< N_FTS
+                                                         Sets the Number of Fast Training Sequences (N_FTS) that
+                                                         the core advertises as its N_FTS during GEN2 Link training.
+                                                         This value is used to inform the Link partner about the PHYs
+                                                         ability to recover synchronization after a low power state.
+                                                         Note: Do not set N_FTS to zero; doing so can cause the
+                                                               LTSSM to go into the recovery state when exiting from
+                                                               L0s. */
+#else
+	uint32_t n_fts                        : 8;
+	uint32_t le                           : 9;
+	uint32_t dsc                          : 1;
+	uint32_t cpyts                        : 1;
+	uint32_t ctcrb                        : 1;
+	uint32_t s_d_e                        : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg515_s          cn63xx;
+	struct cvmx_pciercx_cfg515_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t;
+
+/**
+ * cvmx_pcierc#_cfg516
+ *
+ * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space
+ * (PHY Status Register)
+ */
+union cvmx_pciercx_cfg516
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg516_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t phy_stat                     : 32; /**< PHY Status */
+#else
+	uint32_t phy_stat                     : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg516_s          cn52xx;
+	struct cvmx_pciercx_cfg516_s          cn52xxp1;
+	struct cvmx_pciercx_cfg516_s          cn56xx;
+	struct cvmx_pciercx_cfg516_s          cn56xxp1;
+	struct cvmx_pciercx_cfg516_s          cn63xx;
+	struct cvmx_pciercx_cfg516_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t;
+
+/**
+ * cvmx_pcierc#_cfg517
+ *
+ * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space
+ * (PHY Control Register)
+ */
+union cvmx_pciercx_cfg517
+{
+	uint32_t u32;
+	struct cvmx_pciercx_cfg517_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t phy_ctrl                     : 32; /**< PHY Control */
+#else
+	uint32_t phy_ctrl                     : 32;
+#endif
+	} s;
+	struct cvmx_pciercx_cfg517_s          cn52xx;
+	struct cvmx_pciercx_cfg517_s          cn52xxp1;
+	struct cvmx_pciercx_cfg517_s          cn56xx;
+	struct cvmx_pciercx_cfg517_s          cn56xxp1;
+	struct cvmx_pciercx_cfg517_s          cn63xx;
+	struct cvmx_pciercx_cfg517_s          cn63xxp1;
+};
+typedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pcm-defs.h b/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
new file mode 100644
index 0000000..808f1b2
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
@@ -0,0 +1,230 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pcm-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcm.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCM_TYPEDEFS_H__
+#define __CVMX_PCM_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
+}
+#else
+#define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
+#endif
+
+/**
+ * cvmx_pcm_clk#_cfg
+ */
+union cvmx_pcm_clkx_cfg
+{
+	uint64_t u64;
+	struct cvmx_pcm_clkx_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fsyncgood                    : 1;  /**< FSYNC status
+                                                         If 1, the last frame had a correctly positioned
+                                                               fsync pulse
+                                                         If 0, none/extra fsync pulse seen on most recent
+                                                               frame
+                                                         NOTE: this is intended for startup. the FSYNCEXTRA
+                                                         and FSYNCMISSING interrupts are intended for
+                                                         detecting loss of sync during normal operation. */
+	uint64_t reserved_48_62               : 15;
+	uint64_t fsyncsamp                    : 16; /**< Number of ECLKs from internal BCLK edge to
+                                                         sample FSYNC
+                                                         NOTE: used to sync to the start of a frame and to
+                                                         check for FSYNC errors. */
+	uint64_t reserved_26_31               : 6;
+	uint64_t fsynclen                     : 5;  /**< Number of 1/2 BCLKs FSYNC is asserted for
+                                                         NOTE: only used when GEN==1 */
+	uint64_t fsyncloc                     : 5;  /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
+                                                         bit 0.
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+	uint64_t numslots                     : 10; /**< Number of 8-bit slots in a frame
+                                                         NOTE: this, along with EXTRABIT and Fbclk
+                                                         determines FSYNC frequency when GEN == 1
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+	uint64_t extrabit                     : 1;  /**< If 0, no frame bit
+                                                         If 1, add one extra bit time for frame bit
+                                                         NOTE: if GEN == 1, then FSYNC will be delayed one
+                                                         extra bit time.
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0
+                                                         NOTE: the extra bit comes from the LSB/MSB of the
+                                                         first byte of the frame in the transmit memory
+                                                         region.  LSB vs MSB is determined from the setting
+                                                         of PCMn_TDM_CFG[LSBFIRST]. */
+	uint64_t bitlen                       : 2;  /**< Number of BCLKs in a bit time.
+                                                         0 : 1 BCLK
+                                                         1 : 2 BCLKs
+                                                         2 : 4 BCLKs
+                                                         3 : operation undefined */
+	uint64_t bclkpol                      : 1;  /**< If 0, BCLK rise edge is start of bit time
+                                                         If 1, BCLK fall edge is start of bit time
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+	uint64_t fsyncpol                     : 1;  /**< If 0, FSYNC idles low, asserts high
+                                                         If 1, FSYNC idles high, asserts low
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+	uint64_t ena                          : 1;  /**< If 0, Clock receiving logic is doing nothing
+                                                         1, Clock receiving logic is looking for sync */
+#else
+	uint64_t ena                          : 1;
+	uint64_t fsyncpol                     : 1;
+	uint64_t bclkpol                      : 1;
+	uint64_t bitlen                       : 2;
+	uint64_t extrabit                     : 1;
+	uint64_t numslots                     : 10;
+	uint64_t fsyncloc                     : 5;
+	uint64_t fsynclen                     : 5;
+	uint64_t reserved_26_31               : 6;
+	uint64_t fsyncsamp                    : 16;
+	uint64_t reserved_48_62               : 15;
+	uint64_t fsyncgood                    : 1;
+#endif
+	} s;
+	struct cvmx_pcm_clkx_cfg_s            cn30xx;
+	struct cvmx_pcm_clkx_cfg_s            cn31xx;
+	struct cvmx_pcm_clkx_cfg_s            cn50xx;
+};
+typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
+
+/**
+ * cvmx_pcm_clk#_dbg
+ */
+union cvmx_pcm_clkx_dbg
+{
+	uint64_t u64;
+	struct cvmx_pcm_clkx_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information */
+#else
+	uint64_t debuginfo                    : 64;
+#endif
+	} s;
+	struct cvmx_pcm_clkx_dbg_s            cn30xx;
+	struct cvmx_pcm_clkx_dbg_s            cn31xx;
+	struct cvmx_pcm_clkx_dbg_s            cn50xx;
+};
+typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
+
+/**
+ * cvmx_pcm_clk#_gen
+ */
+union cvmx_pcm_clkx_gen
+{
+	uint64_t u64;
+	struct cvmx_pcm_clkx_gen_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t deltasamp                    : 16; /**< Signed number of ECLKs to move sampled BCLK edge
+                                                         NOTE: the complete number of ECLKs to move is:
+                                                                   NUMSAMP + 2 + 1 + DELTASAMP
+                                                               NUMSAMP to compensate for sampling delay
+                                                               + 2 to compensate for dual-rank synchronizer
+                                                               + 1 for uncertainity
+                                                               + DELTASAMP to CMA/debugging */
+	uint64_t numsamp                      : 16; /**< Number of ECLK samples to detect BCLK change when
+                                                         receiving clock. */
+	uint64_t n                            : 32; /**< Determines BCLK frequency when generating clock
+                                                         NOTE: Fbclk = Feclk * N / 2^32
+                                                               N = (Fbclk / Feclk) * 2^32
+                                                         NOTE: writing N == 0 stops the clock generator, and
+                                                               causes bclk and fsync to be RECEIVED */
+#else
+	uint64_t n                            : 32;
+	uint64_t numsamp                      : 16;
+	uint64_t deltasamp                    : 16;
+#endif
+	} s;
+	struct cvmx_pcm_clkx_gen_s            cn30xx;
+	struct cvmx_pcm_clkx_gen_s            cn31xx;
+	struct cvmx_pcm_clkx_gen_s            cn50xx;
+};
+typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
new file mode 100644
index 0000000..6e2495b
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
@@ -0,0 +1,1082 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pcmx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcmx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCMX_TYPEDEFS_H__
+#define __CVMX_PCMX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
+}
+#else
+#define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384)
+#endif
+
+/**
+ * cvmx_pcm#_dma_cfg
+ */
+union cvmx_pcmx_dma_cfg
+{
+	uint64_t u64;
+	struct cvmx_pcmx_dma_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rdpend                       : 1;  /**< If 0, no L2C read responses pending
+                                                            1, L2C read responses are outstanding
+                                                         NOTE: When restarting after stopping a running TDM
+                                                         engine, software must wait for RDPEND to read 0
+                                                         before writing PCMn_TDM_CFG[ENABLE] to a 1 */
+	uint64_t reserved_54_62               : 9;
+	uint64_t rxslots                      : 10; /**< Number of 8-bit slots to receive per frame
+                                                         (number of slots in a receive superframe) */
+	uint64_t reserved_42_43               : 2;
+	uint64_t txslots                      : 10; /**< Number of 8-bit slots to transmit per frame
+                                                         (number of slots in a transmit superframe) */
+	uint64_t reserved_30_31               : 2;
+	uint64_t rxst                         : 10; /**< Number of frame writes for interrupt */
+	uint64_t reserved_19_19               : 1;
+	uint64_t useldt                       : 1;  /**< If 0, use LDI command to read from L2C
+                                                         1, use LDT command to read from L2C */
+	uint64_t txrd                         : 10; /**< Number of frame reads for interrupt */
+	uint64_t fetchsiz                     : 4;  /**< FETCHSIZ+1 timeslots are read when threshold is
+                                                         reached. */
+	uint64_t thresh                       : 4;  /**< If number of bytes remaining in the DMA fifo is <=
+                                                         THRESH, initiate a fetch of timeslot data from the
+                                                         transmit memory region.
+                                                         NOTE: there are only 16B of buffer for each engine
+                                                         so the seetings for FETCHSIZ and THRESH must be
+                                                         such that the buffer will not be overrun:
+
+                                                         THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */
+#else
+	uint64_t thresh                       : 4;
+	uint64_t fetchsiz                     : 4;
+	uint64_t txrd                         : 10;
+	uint64_t useldt                       : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t rxst                         : 10;
+	uint64_t reserved_30_31               : 2;
+	uint64_t txslots                      : 10;
+	uint64_t reserved_42_43               : 2;
+	uint64_t rxslots                      : 10;
+	uint64_t reserved_54_62               : 9;
+	uint64_t rdpend                       : 1;
+#endif
+	} s;
+	struct cvmx_pcmx_dma_cfg_s            cn30xx;
+	struct cvmx_pcmx_dma_cfg_s            cn31xx;
+	struct cvmx_pcmx_dma_cfg_s            cn50xx;
+};
+typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t;
+
+/**
+ * cvmx_pcm#_int_ena
+ */
+union cvmx_pcmx_int_ena
+{
+	uint64_t u64;
+	struct cvmx_pcmx_int_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rxovf                        : 1;  /**< Enable interrupt if RX byte overflows */
+	uint64_t txempty                      : 1;  /**< Enable interrupt on TX byte empty */
+	uint64_t txrd                         : 1;  /**< Enable DMA engine frame read interrupts */
+	uint64_t txwrap                       : 1;  /**< Enable TX region wrap interrupts */
+	uint64_t rxst                         : 1;  /**< Enable DMA engine frame store interrupts */
+	uint64_t rxwrap                       : 1;  /**< Enable RX region wrap interrupts */
+	uint64_t fsyncextra                   : 1;  /**< Enable FSYNC extra interrupts
+                                                         NOTE: FSYNCEXTRA errors are defined as an FSYNC
+                                                         found in the "wrong" spot of a frame given the
+                                                         programming of PCMn_CLK_CFG[NUMSLOTS] and
+                                                         PCMn_CLK_CFG[EXTRABIT]. */
+	uint64_t fsyncmissed                  : 1;  /**< Enable FSYNC missed interrupts
+                                                         NOTE: FSYNCMISSED errors are defined as an FSYNC
+                                                         missing from the correct spot in a frame given
+                                                         the programming of PCMn_CLK_CFG[NUMSLOTS] and
+                                                         PCMn_CLK_CFG[EXTRABIT]. */
+#else
+	uint64_t fsyncmissed                  : 1;
+	uint64_t fsyncextra                   : 1;
+	uint64_t rxwrap                       : 1;
+	uint64_t rxst                         : 1;
+	uint64_t txwrap                       : 1;
+	uint64_t txrd                         : 1;
+	uint64_t txempty                      : 1;
+	uint64_t rxovf                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pcmx_int_ena_s            cn30xx;
+	struct cvmx_pcmx_int_ena_s            cn31xx;
+	struct cvmx_pcmx_int_ena_s            cn50xx;
+};
+typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t;
+
+/**
+ * cvmx_pcm#_int_sum
+ */
+union cvmx_pcmx_int_sum
+{
+	uint64_t u64;
+	struct cvmx_pcmx_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rxovf                        : 1;  /**< RX byte overflowed */
+	uint64_t txempty                      : 1;  /**< TX byte was empty when sampled */
+	uint64_t txrd                         : 1;  /**< DMA engine frame read interrupt occurred */
+	uint64_t txwrap                       : 1;  /**< TX region wrap interrupt occurred */
+	uint64_t rxst                         : 1;  /**< DMA engine frame store interrupt occurred */
+	uint64_t rxwrap                       : 1;  /**< RX region wrap interrupt occurred */
+	uint64_t fsyncextra                   : 1;  /**< FSYNC extra interrupt occurred */
+	uint64_t fsyncmissed                  : 1;  /**< FSYNC missed interrupt occurred */
+#else
+	uint64_t fsyncmissed                  : 1;
+	uint64_t fsyncextra                   : 1;
+	uint64_t rxwrap                       : 1;
+	uint64_t rxst                         : 1;
+	uint64_t txwrap                       : 1;
+	uint64_t txrd                         : 1;
+	uint64_t txempty                      : 1;
+	uint64_t rxovf                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pcmx_int_sum_s            cn30xx;
+	struct cvmx_pcmx_int_sum_s            cn31xx;
+	struct cvmx_pcmx_int_sum_s            cn50xx;
+};
+typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t;
+
+/**
+ * cvmx_pcm#_rxaddr
+ */
+union cvmx_pcmx_rxaddr
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxaddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Address of the next write to the receive memory
+                                                         region */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_pcmx_rxaddr_s             cn30xx;
+	struct cvmx_pcmx_rxaddr_s             cn31xx;
+	struct cvmx_pcmx_rxaddr_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t;
+
+/**
+ * cvmx_pcm#_rxcnt
+ */
+union cvmx_pcmx_rxcnt
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxcnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Number of superframes in receive memory region */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcmx_rxcnt_s              cn30xx;
+	struct cvmx_pcmx_rxcnt_s              cn31xx;
+	struct cvmx_pcmx_rxcnt_s              cn50xx;
+};
+typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t;
+
+/**
+ * cvmx_pcm#_rxmsk0
+ */
+union cvmx_pcmx_rxmsk0
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 63 to 0
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk0_s             cn30xx;
+	struct cvmx_pcmx_rxmsk0_s             cn31xx;
+	struct cvmx_pcmx_rxmsk0_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t;
+
+/**
+ * cvmx_pcm#_rxmsk1
+ */
+union cvmx_pcmx_rxmsk1
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 127 to 64
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk1_s             cn30xx;
+	struct cvmx_pcmx_rxmsk1_s             cn31xx;
+	struct cvmx_pcmx_rxmsk1_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t;
+
+/**
+ * cvmx_pcm#_rxmsk2
+ */
+union cvmx_pcmx_rxmsk2
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 191 to 128
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk2_s             cn30xx;
+	struct cvmx_pcmx_rxmsk2_s             cn31xx;
+	struct cvmx_pcmx_rxmsk2_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t;
+
+/**
+ * cvmx_pcm#_rxmsk3
+ */
+union cvmx_pcmx_rxmsk3
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 255 to 192
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk3_s             cn30xx;
+	struct cvmx_pcmx_rxmsk3_s             cn31xx;
+	struct cvmx_pcmx_rxmsk3_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t;
+
+/**
+ * cvmx_pcm#_rxmsk4
+ */
+union cvmx_pcmx_rxmsk4
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 319 to 256
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk4_s             cn30xx;
+	struct cvmx_pcmx_rxmsk4_s             cn31xx;
+	struct cvmx_pcmx_rxmsk4_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t;
+
+/**
+ * cvmx_pcm#_rxmsk5
+ */
+union cvmx_pcmx_rxmsk5
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 383 to 320
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk5_s             cn30xx;
+	struct cvmx_pcmx_rxmsk5_s             cn31xx;
+	struct cvmx_pcmx_rxmsk5_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t;
+
+/**
+ * cvmx_pcm#_rxmsk6
+ */
+union cvmx_pcmx_rxmsk6
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 447 to 384
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk6_s             cn30xx;
+	struct cvmx_pcmx_rxmsk6_s             cn31xx;
+	struct cvmx_pcmx_rxmsk6_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t;
+
+/**
+ * cvmx_pcm#_rxmsk7
+ */
+union cvmx_pcmx_rxmsk7
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxmsk7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Receive mask bits for slots 511 to 448
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_rxmsk7_s             cn30xx;
+	struct cvmx_pcmx_rxmsk7_s             cn31xx;
+	struct cvmx_pcmx_rxmsk7_s             cn50xx;
+};
+typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t;
+
+/**
+ * cvmx_pcm#_rxstart
+ */
+union cvmx_pcmx_rxstart
+{
+	uint64_t u64;
+	struct cvmx_pcmx_rxstart_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 33; /**< Starting address for the receive memory region */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t addr                         : 33;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_pcmx_rxstart_s            cn30xx;
+	struct cvmx_pcmx_rxstart_s            cn31xx;
+	struct cvmx_pcmx_rxstart_s            cn50xx;
+};
+typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t;
+
+/**
+ * cvmx_pcm#_tdm_cfg
+ */
+union cvmx_pcmx_tdm_cfg
+{
+	uint64_t u64;
+	struct cvmx_pcmx_tdm_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t drvtim                       : 16; /**< Number of ECLKs from start of bit time to stop
+                                                         driving last bit of timeslot (if not driving next
+                                                         timeslot) */
+	uint64_t samppt                       : 16; /**< Number of ECLKs from start of bit time to sample
+                                                         data bit. */
+	uint64_t reserved_3_31                : 29;
+	uint64_t lsbfirst                     : 1;  /**< If 0, shift/receive MSB first
+                                                         1, shift/receive LSB first */
+	uint64_t useclk1                      : 1;  /**< If 0, this PCM is based on BCLK/FSYNC0
+                                                         1, this PCM is based on BCLK/FSYNC1 */
+	uint64_t enable                       : 1;  /**< If 1, PCM is enabled, otherwise pins are GPIOs
+                                                         NOTE: when TDM is disabled by detection of an
+                                                         FSYNC error all transmission and reception is
+                                                         halted.  In addition, PCMn_TX/RXADDR are updated
+                                                         to point to the position at which the error was
+                                                         detected. */
+#else
+	uint64_t enable                       : 1;
+	uint64_t useclk1                      : 1;
+	uint64_t lsbfirst                     : 1;
+	uint64_t reserved_3_31                : 29;
+	uint64_t samppt                       : 16;
+	uint64_t drvtim                       : 16;
+#endif
+	} s;
+	struct cvmx_pcmx_tdm_cfg_s            cn30xx;
+	struct cvmx_pcmx_tdm_cfg_s            cn31xx;
+	struct cvmx_pcmx_tdm_cfg_s            cn50xx;
+};
+typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t;
+
+/**
+ * cvmx_pcm#_tdm_dbg
+ */
+union cvmx_pcmx_tdm_dbg
+{
+	uint64_t u64;
+	struct cvmx_pcmx_tdm_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t debuginfo                    : 64; /**< Miscellaneous debug information */
+#else
+	uint64_t debuginfo                    : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_tdm_dbg_s            cn30xx;
+	struct cvmx_pcmx_tdm_dbg_s            cn31xx;
+	struct cvmx_pcmx_tdm_dbg_s            cn50xx;
+};
+typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t;
+
+/**
+ * cvmx_pcm#_txaddr
+ */
+union cvmx_pcmx_txaddr
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txaddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 33; /**< Address of the next read from the transmit memory
+                                                         region */
+	uint64_t fram                         : 3;  /**< Frame offset
+                                                         NOTE: this is used to extract the correct byte from
+                                                         each 64b word read from the transmit memory region */
+#else
+	uint64_t fram                         : 3;
+	uint64_t addr                         : 33;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_pcmx_txaddr_s             cn30xx;
+	struct cvmx_pcmx_txaddr_s             cn31xx;
+	struct cvmx_pcmx_txaddr_s             cn50xx;
+};
+typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t;
+
+/**
+ * cvmx_pcm#_txcnt
+ */
+union cvmx_pcmx_txcnt
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txcnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t cnt                          : 16; /**< Number of superframes in transmit memory region */
+#else
+	uint64_t cnt                          : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcmx_txcnt_s              cn30xx;
+	struct cvmx_pcmx_txcnt_s              cn31xx;
+	struct cvmx_pcmx_txcnt_s              cn50xx;
+};
+typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t;
+
+/**
+ * cvmx_pcm#_txmsk0
+ */
+union cvmx_pcmx_txmsk0
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 63 to 0
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk0_s             cn30xx;
+	struct cvmx_pcmx_txmsk0_s             cn31xx;
+	struct cvmx_pcmx_txmsk0_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t;
+
+/**
+ * cvmx_pcm#_txmsk1
+ */
+union cvmx_pcmx_txmsk1
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 127 to 64
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk1_s             cn30xx;
+	struct cvmx_pcmx_txmsk1_s             cn31xx;
+	struct cvmx_pcmx_txmsk1_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t;
+
+/**
+ * cvmx_pcm#_txmsk2
+ */
+union cvmx_pcmx_txmsk2
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 191 to 128
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk2_s             cn30xx;
+	struct cvmx_pcmx_txmsk2_s             cn31xx;
+	struct cvmx_pcmx_txmsk2_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t;
+
+/**
+ * cvmx_pcm#_txmsk3
+ */
+union cvmx_pcmx_txmsk3
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 255 to 192
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk3_s             cn30xx;
+	struct cvmx_pcmx_txmsk3_s             cn31xx;
+	struct cvmx_pcmx_txmsk3_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t;
+
+/**
+ * cvmx_pcm#_txmsk4
+ */
+union cvmx_pcmx_txmsk4
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 319 to 256
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk4_s             cn30xx;
+	struct cvmx_pcmx_txmsk4_s             cn31xx;
+	struct cvmx_pcmx_txmsk4_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t;
+
+/**
+ * cvmx_pcm#_txmsk5
+ */
+union cvmx_pcmx_txmsk5
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 383 to 320
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk5_s             cn30xx;
+	struct cvmx_pcmx_txmsk5_s             cn31xx;
+	struct cvmx_pcmx_txmsk5_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t;
+
+/**
+ * cvmx_pcm#_txmsk6
+ */
+union cvmx_pcmx_txmsk6
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 447 to 384
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk6_s             cn30xx;
+	struct cvmx_pcmx_txmsk6_s             cn31xx;
+	struct cvmx_pcmx_txmsk6_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t;
+
+/**
+ * cvmx_pcm#_txmsk7
+ */
+union cvmx_pcmx_txmsk7
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txmsk7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t mask                         : 64; /**< Transmit mask bits for slots 511 to 448
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+	uint64_t mask                         : 64;
+#endif
+	} s;
+	struct cvmx_pcmx_txmsk7_s             cn30xx;
+	struct cvmx_pcmx_txmsk7_s             cn31xx;
+	struct cvmx_pcmx_txmsk7_s             cn50xx;
+};
+typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t;
+
+/**
+ * cvmx_pcm#_txstart
+ */
+union cvmx_pcmx_txstart
+{
+	uint64_t u64;
+	struct cvmx_pcmx_txstart_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 33; /**< Starting address for the transmit memory region */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t addr                         : 33;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_pcmx_txstart_s            cn30xx;
+	struct cvmx_pcmx_txstart_s            cn31xx;
+	struct cvmx_pcmx_txstart_s            cn50xx;
+};
+typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
new file mode 100644
index 0000000..53bd30c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
@@ -0,0 +1,1180 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pcsx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcsx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCSX_TYPEDEFS_H__
+#define __CVMX_PCSX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_INTX_EN_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_INTX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
+}
+#else
+#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)
+#endif
+
+/**
+ * cvmx_pcs#_an#_adv_reg
+ *
+ * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification,
+ * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating
+ * that the chip cannot operate in the corresponding modes.
+ *
+ * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.
+ *
+ *
+ *
+ * PCS_AN_ADV_REG = AN Advertisement Register4
+ */
+union cvmx_pcsx_anx_adv_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_anx_adv_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t np                           : 1;  /**< Always 0, no next page capability supported */
+	uint64_t reserved_14_14               : 1;
+	uint64_t rem_flt                      : 2;  /**< [<13>,<12>]
+                                                         0    0  Link OK  XMIT=DATA
+                                                         0    1  Link failure (loss of sync, XMIT!= DATA)
+                                                         1    0  local device Offline
+                                                         1    1  AN Error failure to complete AN
+                                                                 AN Error is set if resolution function
+                                                                 precludes operation with link partner */
+	uint64_t reserved_9_11                : 3;
+	uint64_t pause                        : 2;  /**< [<8>, <7>] Pause frame flow capability across link
+                                                                  Exchanged during Auto Negotiation
+                                                         0    0  No Pause
+                                                         0    1  Symmetric pause
+                                                         1    0  Asymmetric Pause
+                                                         1    1  Both symm and asymm pause to local device */
+	uint64_t hfd                          : 1;  /**< 1 means local device Half Duplex capable */
+	uint64_t fd                           : 1;  /**< 1 means local device Full Duplex capable */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t fd                           : 1;
+	uint64_t hfd                          : 1;
+	uint64_t pause                        : 2;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rem_flt                      : 2;
+	uint64_t reserved_14_14               : 1;
+	uint64_t np                           : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_anx_adv_reg_s        cn52xx;
+	struct cvmx_pcsx_anx_adv_reg_s        cn52xxp1;
+	struct cvmx_pcsx_anx_adv_reg_s        cn56xx;
+	struct cvmx_pcsx_anx_adv_reg_s        cn56xxp1;
+	struct cvmx_pcsx_anx_adv_reg_s        cn63xx;
+	struct cvmx_pcsx_anx_adv_reg_s        cn63xxp1;
+};
+typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t;
+
+/**
+ * cvmx_pcs#_an#_ext_st_reg
+ *
+ * NOTE:
+ * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1
+ * the an_results_reg is valid.
+ *
+ *
+ * PCS_AN_EXT_ST_REG = AN Extended Status Register15
+ * as per IEEE802.3 Clause 22
+ */
+union cvmx_pcsx_anx_ext_st_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_anx_ext_st_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t thou_xfd                     : 1;  /**< 1 means PHY is 1000BASE-X Full Dup capable */
+	uint64_t thou_xhd                     : 1;  /**< 1 means PHY is 1000BASE-X Half Dup capable */
+	uint64_t thou_tfd                     : 1;  /**< 1 means PHY is 1000BASE-T Full Dup capable */
+	uint64_t thou_thd                     : 1;  /**< 1 means PHY is 1000BASE-T Half Dup capable */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t thou_thd                     : 1;
+	uint64_t thou_tfd                     : 1;
+	uint64_t thou_xhd                     : 1;
+	uint64_t thou_xfd                     : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn52xx;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn52xxp1;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn56xx;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn56xxp1;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn63xx;
+	struct cvmx_pcsx_anx_ext_st_reg_s     cn63xxp1;
+};
+typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t;
+
+/**
+ * cvmx_pcs#_an#_lp_abil_reg
+ *
+ * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5
+ * as per IEEE802.3 Clause 37
+ */
+union cvmx_pcsx_anx_lp_abil_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_anx_lp_abil_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t np                           : 1;  /**< 1=lp next page capable, 0=lp not next page capable */
+	uint64_t ack                          : 1;  /**< 1=Acknowledgement received */
+	uint64_t rem_flt                      : 2;  /**< [<13>,<12>] Link Partner's link status
+                                                         0    0  Link OK
+                                                         0    1  Offline
+                                                         1    0  Link failure
+                                                         1    1  AN Error */
+	uint64_t reserved_9_11                : 3;
+	uint64_t pause                        : 2;  /**< [<8>, <7>] Link Partner Pause setting
+                                                         0    0  No Pause
+                                                         0    1  Symmetric pause
+                                                         1    0  Asymmetric Pause
+                                                         1    1  Both symm and asymm pause to local device */
+	uint64_t hfd                          : 1;  /**< 1 means link partner Half Duplex capable */
+	uint64_t fd                           : 1;  /**< 1 means link partner Full Duplex capable */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t fd                           : 1;
+	uint64_t hfd                          : 1;
+	uint64_t pause                        : 2;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rem_flt                      : 2;
+	uint64_t ack                          : 1;
+	uint64_t np                           : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn52xx;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn52xxp1;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn56xx;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn56xxp1;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn63xx;
+	struct cvmx_pcsx_anx_lp_abil_reg_s    cn63xxp1;
+};
+typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t;
+
+/**
+ * cvmx_pcs#_an#_results_reg
+ *
+ * PCS_AN_RESULTS_REG = AN Results Register
+ *
+ */
+union cvmx_pcsx_anx_results_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_anx_results_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t pause                        : 2;  /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII)
+                                                         0    0  Disable Pause, TX and RX
+                                                         0    1  Enable pause frames RX only
+                                                         1    0  Enable Pause frames TX only
+                                                         1    1  Enable pause frames TX and RX */
+	uint64_t spd                          : 2;  /**< [<4>, <3>] Link Speed Selection
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  NS */
+	uint64_t an_cpt                       : 1;  /**< 1=AN Completed, 0=AN not completed or failed */
+	uint64_t dup                          : 1;  /**< 1=Full Duplex, 0=Half Duplex */
+	uint64_t link_ok                      : 1;  /**< 1=Link up(OK), 0=Link down */
+#else
+	uint64_t link_ok                      : 1;
+	uint64_t dup                          : 1;
+	uint64_t an_cpt                       : 1;
+	uint64_t spd                          : 2;
+	uint64_t pause                        : 2;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pcsx_anx_results_reg_s    cn52xx;
+	struct cvmx_pcsx_anx_results_reg_s    cn52xxp1;
+	struct cvmx_pcsx_anx_results_reg_s    cn56xx;
+	struct cvmx_pcsx_anx_results_reg_s    cn56xxp1;
+	struct cvmx_pcsx_anx_results_reg_s    cn63xx;
+	struct cvmx_pcsx_anx_results_reg_s    cn63xxp1;
+};
+typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t;
+
+/**
+ * cvmx_pcs#_int#_en_reg
+ *
+ * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising
+ *      DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from
+ *      SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an indication that a bad code group
+ *      was received after code group synchronizaton was achieved. This interrupt should be disabled during normal link operation.
+ *      Use it as a debug help feature only.
+ *
+ *
+ * PCS Interrupt Enable Register
+ */
+union cvmx_pcsx_intx_en_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_intx_en_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t dbg_sync_en                  : 1;  /**< Code Group sync failure debug help */
+	uint64_t dup                          : 1;  /**< Enable duplex mode changed interrupt */
+	uint64_t sync_bad_en                  : 1;  /**< Enable rx sync st machine in bad state interrupt */
+	uint64_t an_bad_en                    : 1;  /**< Enable AN state machine bad state interrupt */
+	uint64_t rxlock_en                    : 1;  /**< Enable rx code group sync/bit lock failure interrupt */
+	uint64_t rxbad_en                     : 1;  /**< Enable rx state machine in bad state interrupt */
+	uint64_t rxerr_en                     : 1;  /**< Enable RX error condition interrupt */
+	uint64_t txbad_en                     : 1;  /**< Enable tx state machine in bad state interrupt */
+	uint64_t txfifo_en                    : 1;  /**< Enable tx fifo overflow condition interrupt */
+	uint64_t txfifu_en                    : 1;  /**< Enable tx fifo underflow condition intrrupt */
+	uint64_t an_err_en                    : 1;  /**< Enable AN Error condition interrupt */
+	uint64_t xmit_en                      : 1;  /**< Enable XMIT variable state change interrupt */
+	uint64_t lnkspd_en                    : 1;  /**< Enable Link Speed has changed interrupt */
+#else
+	uint64_t lnkspd_en                    : 1;
+	uint64_t xmit_en                      : 1;
+	uint64_t an_err_en                    : 1;
+	uint64_t txfifu_en                    : 1;
+	uint64_t txfifo_en                    : 1;
+	uint64_t txbad_en                     : 1;
+	uint64_t rxerr_en                     : 1;
+	uint64_t rxbad_en                     : 1;
+	uint64_t rxlock_en                    : 1;
+	uint64_t an_bad_en                    : 1;
+	uint64_t sync_bad_en                  : 1;
+	uint64_t dup                          : 1;
+	uint64_t dbg_sync_en                  : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pcsx_intx_en_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t dup                          : 1;  /**< Enable duplex mode changed interrupt */
+	uint64_t sync_bad_en                  : 1;  /**< Enable rx sync st machine in bad state interrupt */
+	uint64_t an_bad_en                    : 1;  /**< Enable AN state machine bad state interrupt */
+	uint64_t rxlock_en                    : 1;  /**< Enable rx code group sync/bit lock failure interrupt */
+	uint64_t rxbad_en                     : 1;  /**< Enable rx state machine in bad state interrupt */
+	uint64_t rxerr_en                     : 1;  /**< Enable RX error condition interrupt */
+	uint64_t txbad_en                     : 1;  /**< Enable tx state machine in bad state interrupt */
+	uint64_t txfifo_en                    : 1;  /**< Enable tx fifo overflow condition interrupt */
+	uint64_t txfifu_en                    : 1;  /**< Enable tx fifo underflow condition intrrupt */
+	uint64_t an_err_en                    : 1;  /**< Enable AN Error condition interrupt */
+	uint64_t xmit_en                      : 1;  /**< Enable XMIT variable state change interrupt */
+	uint64_t lnkspd_en                    : 1;  /**< Enable Link Speed has changed interrupt */
+#else
+	uint64_t lnkspd_en                    : 1;
+	uint64_t xmit_en                      : 1;
+	uint64_t an_err_en                    : 1;
+	uint64_t txfifu_en                    : 1;
+	uint64_t txfifo_en                    : 1;
+	uint64_t txbad_en                     : 1;
+	uint64_t rxerr_en                     : 1;
+	uint64_t rxbad_en                     : 1;
+	uint64_t rxlock_en                    : 1;
+	uint64_t an_bad_en                    : 1;
+	uint64_t sync_bad_en                  : 1;
+	uint64_t dup                          : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn52xx;
+	struct cvmx_pcsx_intx_en_reg_cn52xx   cn52xxp1;
+	struct cvmx_pcsx_intx_en_reg_cn52xx   cn56xx;
+	struct cvmx_pcsx_intx_en_reg_cn52xx   cn56xxp1;
+	struct cvmx_pcsx_intx_en_reg_s        cn63xx;
+	struct cvmx_pcsx_intx_en_reg_s        cn63xxp1;
+};
+typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t;
+
+/**
+ * cvmx_pcs#_int#_reg
+ *
+ * SGMII bit [12] is really a misnomer, it is a decode  of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes.
+ *
+ * Note: MODE bit
+ * When MODE=1,  1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37.
+ * When MODE=0,  SGMII mode is selected and the following note will apply.
+ * Repeat note from SGM_AN_ADV register
+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
+ *
+ * PCS Interrupt Register
+ */
+union cvmx_pcsx_intx_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_intx_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t dbg_sync                     : 1;  /**< Code Group sync failure debug help */
+	uint64_t dup                          : 1;  /**< Set whenever Duplex mode changes on the link */
+	uint64_t sync_bad                     : 1;  /**< Set by HW whenever rx sync st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t an_bad                       : 1;  /**< Set by HW whenever AN st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t rxlock                       : 1;  /**< Set by HW whenever code group Sync or bit lock
+                                                         failure occurs
+                                                         Cannot fire in loopback1 mode */
+	uint64_t rxbad                        : 1;  /**< Set by HW whenever rx st machine reaches a  bad
+                                                         state. Should never be set during normal operation */
+	uint64_t rxerr                        : 1;  /**< Set whenever RX receives a code group error in
+                                                         10 bit to 8 bit decode logic
+                                                         Cannot fire in loopback1 mode */
+	uint64_t txbad                        : 1;  /**< Set by HW whenever tx st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t txfifo                       : 1;  /**< Set whenever HW detects a TX fifo overflow
+                                                         condition */
+	uint64_t txfifu                       : 1;  /**< Set whenever HW detects a TX fifo underflowflow
+                                                         condition */
+	uint64_t an_err                       : 1;  /**< AN Error, AN resolution function failed */
+	uint64_t xmit                         : 1;  /**< Set whenever HW detects a change in the XMIT
+                                                         variable. XMIT variable states are IDLE, CONFIG and
+                                                         DATA */
+	uint64_t lnkspd                       : 1;  /**< Set by HW whenever Link Speed has changed */
+#else
+	uint64_t lnkspd                       : 1;
+	uint64_t xmit                         : 1;
+	uint64_t an_err                       : 1;
+	uint64_t txfifu                       : 1;
+	uint64_t txfifo                       : 1;
+	uint64_t txbad                        : 1;
+	uint64_t rxerr                        : 1;
+	uint64_t rxbad                        : 1;
+	uint64_t rxlock                       : 1;
+	uint64_t an_bad                       : 1;
+	uint64_t sync_bad                     : 1;
+	uint64_t dup                          : 1;
+	uint64_t dbg_sync                     : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pcsx_intx_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t dup                          : 1;  /**< Set whenever Duplex mode changes on the link */
+	uint64_t sync_bad                     : 1;  /**< Set by HW whenever rx sync st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t an_bad                       : 1;  /**< Set by HW whenever AN st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t rxlock                       : 1;  /**< Set by HW whenever code group Sync or bit lock
+                                                         failure occurs
+                                                         Cannot fire in loopback1 mode */
+	uint64_t rxbad                        : 1;  /**< Set by HW whenever rx st machine reaches a  bad
+                                                         state. Should never be set during normal operation */
+	uint64_t rxerr                        : 1;  /**< Set whenever RX receives a code group error in
+                                                         10 bit to 8 bit decode logic
+                                                         Cannot fire in loopback1 mode */
+	uint64_t txbad                        : 1;  /**< Set by HW whenever tx st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+	uint64_t txfifo                       : 1;  /**< Set whenever HW detects a TX fifo overflow
+                                                         condition */
+	uint64_t txfifu                       : 1;  /**< Set whenever HW detects a TX fifo underflowflow
+                                                         condition */
+	uint64_t an_err                       : 1;  /**< AN Error, AN resolution function failed */
+	uint64_t xmit                         : 1;  /**< Set whenever HW detects a change in the XMIT
+                                                         variable. XMIT variable states are IDLE, CONFIG and
+                                                         DATA */
+	uint64_t lnkspd                       : 1;  /**< Set by HW whenever Link Speed has changed */
+#else
+	uint64_t lnkspd                       : 1;
+	uint64_t xmit                         : 1;
+	uint64_t an_err                       : 1;
+	uint64_t txfifu                       : 1;
+	uint64_t txfifo                       : 1;
+	uint64_t txbad                        : 1;
+	uint64_t rxerr                        : 1;
+	uint64_t rxbad                        : 1;
+	uint64_t rxlock                       : 1;
+	uint64_t an_bad                       : 1;
+	uint64_t sync_bad                     : 1;
+	uint64_t dup                          : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn52xx;
+	struct cvmx_pcsx_intx_reg_cn52xx      cn52xxp1;
+	struct cvmx_pcsx_intx_reg_cn52xx      cn56xx;
+	struct cvmx_pcsx_intx_reg_cn52xx      cn56xxp1;
+	struct cvmx_pcsx_intx_reg_s           cn63xx;
+	struct cvmx_pcsx_intx_reg_s           cn63xxp1;
+};
+typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t;
+
+/**
+ * cvmx_pcs#_link#_timer_count_reg
+ *
+ * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register
+ *
+ */
+union cvmx_pcsx_linkx_timer_count_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_linkx_timer_count_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t count                        : 16; /**< (core clock period times 1024) times "COUNT" should
+                                                         be 1.6ms(SGMII)/10ms(otherwise) which is the link
+                                                         timer used in auto negotiation.
+                                                         Reset assums a 700MHz eclk for 1.6ms link timer */
+#else
+	uint64_t count                        : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
+	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
+};
+typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t;
+
+/**
+ * cvmx_pcs#_log_anl#_reg
+ *
+ * PCS Logic Analyzer Register
+ *
+ */
+union cvmx_pcsx_log_anlx_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_log_anlx_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t lafifovfl                    : 1;  /**< 1=logic analyser fif overflowed during packetization
+                                                         Write 1 to clear this bit */
+	uint64_t la_en                        : 1;  /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
+	uint64_t pkt_sz                       : 2;  /**< [<1>, <0>]  Logic Analyzer Packet Size
+                                                         0    0   Packet size 1k bytes
+                                                         0    1   Packet size 4k bytes
+                                                         1    0   Packet size 8k bytes
+                                                         1    1   Packet size 16k bytes */
+#else
+	uint64_t pkt_sz                       : 2;
+	uint64_t la_en                        : 1;
+	uint64_t lafifovfl                    : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pcsx_log_anlx_reg_s       cn52xx;
+	struct cvmx_pcsx_log_anlx_reg_s       cn52xxp1;
+	struct cvmx_pcsx_log_anlx_reg_s       cn56xx;
+	struct cvmx_pcsx_log_anlx_reg_s       cn56xxp1;
+	struct cvmx_pcsx_log_anlx_reg_s       cn63xx;
+	struct cvmx_pcsx_log_anlx_reg_s       cn63xxp1;
+};
+typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t;
+
+/**
+ * cvmx_pcs#_misc#_ctl_reg
+ *
+ * SGMII Misc Control Register
+ *
+ */
+union cvmx_pcsx_miscx_ctl_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_miscx_ctl_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t sgmii                        : 1;  /**< 1=SGMII or 1000Base-X mode selected,
+                                                         0=XAUI or PCIE mode selected
+                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
+	uint64_t gmxeno                       : 1;  /**< GMX Enable override. When set to 1, forces GMX to
+                                                         appear disabled. The enable/disable status of GMX
+                                                         is checked only at SOP of every packet. */
+	uint64_t loopbck2                     : 1;  /**< Sets external loopback mode to return rx data back
+                                                         out via tx data path. 0=no loopback, 1=loopback */
+	uint64_t mac_phy                      : 1;  /**< 0=MAC, 1=PHY decides the tx_config_reg value to be
+                                                         sent during auto negotiation.
+                                                         See SGMII spec ENG-46158 from CISCO */
+	uint64_t mode                         : 1;  /**< 0=SGMII or 1= 1000 Base X */
+	uint64_t an_ovrd                      : 1;  /**< 0=disable, 1= enable over ride AN results
+                                                         Auto negotiation is allowed to happen but the
+                                                         results are ignored when set. Duplex and Link speed
+                                                         values are set from the pcs_mr_ctrl reg */
+	uint64_t samp_pt                      : 7;  /**< Byte# in elongated frames for 10/100Mb/s operation
+                                                         for data sampling on RX side in PCS.
+                                                         Recommended values are 0x5 for 100Mb/s operation
+                                                         and 0x32 for 10Mb/s operation.
+                                                         For 10Mb/s operaton this field should be set to a
+                                                         value less than 99 and greater than 0. If set out
+                                                         of this range a value of 50 will be used for actual
+                                                         sampling internally without affecting the CSR field
+                                                         For 100Mb/s operation this field should be set to a
+                                                         value less than 9 and greater than 0. If set out of
+                                                         this range a value of 5 will be used for actual
+                                                         sampling internally without affecting the CSR field */
+#else
+	uint64_t samp_pt                      : 7;
+	uint64_t an_ovrd                      : 1;
+	uint64_t mode                         : 1;
+	uint64_t mac_phy                      : 1;
+	uint64_t loopbck2                     : 1;
+	uint64_t gmxeno                       : 1;
+	uint64_t sgmii                        : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn52xx;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn52xxp1;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn56xx;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn56xxp1;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn63xx;
+	struct cvmx_pcsx_miscx_ctl_reg_s      cn63xxp1;
+};
+typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t;
+
+/**
+ * cvmx_pcs#_mr#_control_reg
+ *
+ * PCS_MR_CONTROL_REG = Control Register0
+ *
+ */
+union cvmx_pcsx_mrx_control_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_mrx_control_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t reset                        : 1;  /**< 1=SW Reset, the bit will return to 0 after pcs has
+                                                         been reset. Takes 32 eclk cycles to reset pcs */
+	uint64_t loopbck1                     : 1;  /**< 0=normal operation, 1=loopback. The loopback mode
+                                                         will return(loopback) tx data from GMII tx back to
+                                                         GMII rx interface. The loopback happens in the pcs
+                                                         module. Auto Negotiation will be disabled even if
+                                                         the AN_EN bit is set, during loopback */
+	uint64_t spdlsb                       : 1;  /**< See bit 6 description */
+	uint64_t an_en                        : 1;  /**< 1=AN Enable, 0=AN Disable */
+	uint64_t pwr_dn                       : 1;  /**< 1=Power Down(HW reset), 0=Normal operation */
+	uint64_t reserved_10_10               : 1;
+	uint64_t rst_an                       : 1;  /**< If bit 12 is set and bit 3 of status reg is 1
+                                                         Auto Negotiation begins. Else,SW writes are ignored
+                                                         and this bit remians at 0. This bit clears itself
+                                                         to 0, when AN starts. */
+	uint64_t dup                          : 1;  /**< 1=full duplex, 0=half duplex; effective only if AN
+                                                         disabled. If status register bits [15:9] and and
+                                                         extended status reg bits [15:12] allow only one
+                                                         duplex mode|, this bit will correspond to that
+                                                         value and any attempt to write will be ignored. */
+	uint64_t coltst                       : 1;  /**< 1=enable COL signal test, 0=disable test
+                                                         During COL test, the COL signal will reflect the
+                                                         GMII TX_EN signal with less than 16BT delay */
+	uint64_t spdmsb                       : 1;  /**< [<6>, <13>]Link Speed effective only if AN disabled
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  NS */
+	uint64_t uni                          : 1;  /**< Unidirectional (Std 802.3-2005, Clause 66.2)
+                                                         This bit will override the AN_EN bit and disable
+                                                         auto-negotiation variable mr_an_enable, when set
+                                                         Used in both 1000Base-X and SGMII modes */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t uni                          : 1;
+	uint64_t spdmsb                       : 1;
+	uint64_t coltst                       : 1;
+	uint64_t dup                          : 1;
+	uint64_t rst_an                       : 1;
+	uint64_t reserved_10_10               : 1;
+	uint64_t pwr_dn                       : 1;
+	uint64_t an_en                        : 1;
+	uint64_t spdlsb                       : 1;
+	uint64_t loopbck1                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_mrx_control_reg_s    cn52xx;
+	struct cvmx_pcsx_mrx_control_reg_s    cn52xxp1;
+	struct cvmx_pcsx_mrx_control_reg_s    cn56xx;
+	struct cvmx_pcsx_mrx_control_reg_s    cn56xxp1;
+	struct cvmx_pcsx_mrx_control_reg_s    cn63xx;
+	struct cvmx_pcsx_mrx_control_reg_s    cn63xxp1;
+};
+typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t;
+
+/**
+ * cvmx_pcs#_mr#_status_reg
+ *
+ * NOTE:
+ * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results
+ * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set,
+ * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values
+ * from the pcs_mr_ctrl reg.
+ *
+ *  PCS_MR_STATUS_REG = Status Register1
+ */
+union cvmx_pcsx_mrx_status_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_mrx_status_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t hun_t4                       : 1;  /**< 1 means 100Base-T4 capable */
+	uint64_t hun_xfd                      : 1;  /**< 1 means 100Base-X Full Duplex */
+	uint64_t hun_xhd                      : 1;  /**< 1 means 100Base-X Half Duplex */
+	uint64_t ten_fd                       : 1;  /**< 1 means 10Mb/s Full Duplex */
+	uint64_t ten_hd                       : 1;  /**< 1 means 10Mb/s Half Duplex */
+	uint64_t hun_t2fd                     : 1;  /**< 1 means 100Base-T2 Full Duplex */
+	uint64_t hun_t2hd                     : 1;  /**< 1 means 100Base-T2 Half Duplex */
+	uint64_t ext_st                       : 1;  /**< 1 means extended status info in reg15 */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t prb_sup                      : 1;  /**< 1 means able to work without preamble bytes at the
+                                                         beginning of frames. 0 means not able to accept
+                                                         frames without preamble bytes preceding them. */
+	uint64_t an_cpt                       : 1;  /**< 1 means Auto Negotiation is complete and the
+                                                         contents of the an_results_reg are valid. */
+	uint64_t rm_flt                       : 1;  /**< Set to 1 when remote flt condition occurs. This bit
+                                                         implements a latching Hi behavior. It is cleared by
+                                                         SW read of this reg or when reset bit [15] in
+                                                         Control Reg is asserted.
+                                                         See an adv reg[13:12] for flt conditions */
+	uint64_t an_abil                      : 1;  /**< 1 means Auto Negotiation capable */
+	uint64_t lnk_st                       : 1;  /**< 1=link up, 0=link down. Set during AN process
+                                                         Set whenever XMIT=DATA. Latching Lo behavior when
+                                                         link goes down. Link down value of the bit stays
+                                                         low until SW reads the reg. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t extnd                        : 1;  /**< Always 0, no extended capability regs present */
+#else
+	uint64_t extnd                        : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t lnk_st                       : 1;
+	uint64_t an_abil                      : 1;
+	uint64_t rm_flt                       : 1;
+	uint64_t an_cpt                       : 1;
+	uint64_t prb_sup                      : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t ext_st                       : 1;
+	uint64_t hun_t2hd                     : 1;
+	uint64_t hun_t2fd                     : 1;
+	uint64_t ten_hd                       : 1;
+	uint64_t ten_fd                       : 1;
+	uint64_t hun_xhd                      : 1;
+	uint64_t hun_xfd                      : 1;
+	uint64_t hun_t4                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_mrx_status_reg_s     cn52xx;
+	struct cvmx_pcsx_mrx_status_reg_s     cn52xxp1;
+	struct cvmx_pcsx_mrx_status_reg_s     cn56xx;
+	struct cvmx_pcsx_mrx_status_reg_s     cn56xxp1;
+	struct cvmx_pcsx_mrx_status_reg_s     cn63xx;
+	struct cvmx_pcsx_mrx_status_reg_s     cn63xxp1;
+};
+typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t;
+
+/**
+ * cvmx_pcs#_rx#_states_reg
+ *
+ * PCS_RX_STATES_REG = RX State Machines states register
+ *
+ */
+union cvmx_pcsx_rxx_states_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_rxx_states_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t rx_bad                       : 1;  /**< Receive state machine in an illegal state */
+	uint64_t rx_st                        : 5;  /**< Receive state machine state */
+	uint64_t sync_bad                     : 1;  /**< Receive synchronization SM in an illegal state */
+	uint64_t sync                         : 4;  /**< Receive synchronization SM state */
+	uint64_t an_bad                       : 1;  /**< Auto Negotiation state machine in an illegal state */
+	uint64_t an_st                        : 4;  /**< Auto Negotiation state machine state */
+#else
+	uint64_t an_st                        : 4;
+	uint64_t an_bad                       : 1;
+	uint64_t sync                         : 4;
+	uint64_t sync_bad                     : 1;
+	uint64_t rx_st                        : 5;
+	uint64_t rx_bad                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_rxx_states_reg_s     cn52xx;
+	struct cvmx_pcsx_rxx_states_reg_s     cn52xxp1;
+	struct cvmx_pcsx_rxx_states_reg_s     cn56xx;
+	struct cvmx_pcsx_rxx_states_reg_s     cn56xxp1;
+	struct cvmx_pcsx_rxx_states_reg_s     cn63xx;
+	struct cvmx_pcsx_rxx_states_reg_s     cn63xxp1;
+};
+typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t;
+
+/**
+ * cvmx_pcs#_rx#_sync_reg
+ *
+ * Note:
+ * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved.
+ *
+ *
+ *  PCS_RX_SYNC_REG = Code Group synchronization reg
+ */
+union cvmx_pcsx_rxx_sync_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_rxx_sync_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t sync                         : 1;  /**< 1 means code group synchronization achieved */
+	uint64_t bit_lock                     : 1;  /**< 1 means bit lock achieved */
+#else
+	uint64_t bit_lock                     : 1;
+	uint64_t sync                         : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn52xx;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn52xxp1;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn56xx;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn56xxp1;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn63xx;
+	struct cvmx_pcsx_rxx_sync_reg_s       cn63xxp1;
+};
+typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t;
+
+/**
+ * cvmx_pcs#_sgm#_an_adv_reg
+ *
+ * SGMII AN Advertisement Register (sent out as tx_config_reg)
+ *
+ */
+union cvmx_pcsx_sgmx_an_adv_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t link                         : 1;  /**< Link status 1 Link Up, 0 Link Down */
+	uint64_t ack                          : 1;  /**< Auto negotiation ack */
+	uint64_t reserved_13_13               : 1;
+	uint64_t dup                          : 1;  /**< Duplex mode 1=full duplex, 0=half duplex */
+	uint64_t speed                        : 2;  /**< Link Speed
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  NS */
+	uint64_t reserved_1_9                 : 9;
+	uint64_t one                          : 1;  /**< Always set to match tx_config_reg<0> */
+#else
+	uint64_t one                          : 1;
+	uint64_t reserved_1_9                 : 9;
+	uint64_t speed                        : 2;
+	uint64_t dup                          : 1;
+	uint64_t reserved_13_13               : 1;
+	uint64_t ack                          : 1;
+	uint64_t link                         : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn52xx;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn52xxp1;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn56xx;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn56xxp1;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn63xx;
+	struct cvmx_pcsx_sgmx_an_adv_reg_s    cn63xxp1;
+};
+typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t;
+
+/**
+ * cvmx_pcs#_sgm#_lp_adv_reg
+ *
+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
+ *
+ * SGMII LP Advertisement Register (received as rx_config_reg)
+ */
+union cvmx_pcsx_sgmx_lp_adv_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t link                         : 1;  /**< Link status 1 Link Up, 0 Link Down */
+	uint64_t reserved_13_14               : 2;
+	uint64_t dup                          : 1;  /**< Duplex mode 1=full duplex, 0=half duplex */
+	uint64_t speed                        : 2;  /**< Link Speed
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  NS */
+	uint64_t reserved_1_9                 : 9;
+	uint64_t one                          : 1;  /**< Always set to match tx_config_reg<0> */
+#else
+	uint64_t one                          : 1;
+	uint64_t reserved_1_9                 : 9;
+	uint64_t speed                        : 2;
+	uint64_t dup                          : 1;
+	uint64_t reserved_13_14               : 2;
+	uint64_t link                         : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn52xx;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn52xxp1;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn56xx;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn56xxp1;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn63xx;
+	struct cvmx_pcsx_sgmx_lp_adv_reg_s    cn63xxp1;
+};
+typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t;
+
+/**
+ * cvmx_pcs#_tx#_states_reg
+ *
+ * PCS_TX_STATES_REG = TX State Machines states register
+ *
+ */
+union cvmx_pcsx_txx_states_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_txx_states_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t xmit                         : 2;  /**< 0=undefined, 1=config, 2=idle, 3=data */
+	uint64_t tx_bad                       : 1;  /**< Xmit state machine in a bad state */
+	uint64_t ord_st                       : 4;  /**< Xmit ordered set state machine state */
+#else
+	uint64_t ord_st                       : 4;
+	uint64_t tx_bad                       : 1;
+	uint64_t xmit                         : 2;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pcsx_txx_states_reg_s     cn52xx;
+	struct cvmx_pcsx_txx_states_reg_s     cn52xxp1;
+	struct cvmx_pcsx_txx_states_reg_s     cn56xx;
+	struct cvmx_pcsx_txx_states_reg_s     cn56xxp1;
+	struct cvmx_pcsx_txx_states_reg_s     cn63xx;
+	struct cvmx_pcsx_txx_states_reg_s     cn63xxp1;
+};
+typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t;
+
+/**
+ * cvmx_pcs#_tx_rx#_polarity_reg
+ *
+ * PCS_POLARITY_REG = TX_RX polarity reg
+ *
+ */
+union cvmx_pcsx_tx_rxx_polarity_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t rxovrd                       : 1;  /**< When 0, <2> determines polarity
+                                                         when 1, <1> determines polarity */
+	uint64_t autorxpl                     : 1;  /**< Auto RX polarity detected. 1=inverted, 0=normal
+                                                         This bit always represents the correct rx polarity
+                                                         setting needed for successful rx path operartion,
+                                                         once a successful code group sync is obtained */
+	uint64_t rxplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+	uint64_t txplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+	uint64_t txplrt                       : 1;
+	uint64_t rxplrt                       : 1;
+	uint64_t autorxpl                     : 1;
+	uint64_t rxovrd                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
+	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
+};
+typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h b/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
new file mode 100644
index 0000000..8483d6a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
@@ -0,0 +1,926 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pcsxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcsxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PCSXX_TYPEDEFS_H__
+#define __CVMX_PCSXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_BIST_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_CONTROL1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_CONTROL2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_INT_EN_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_LOG_ANL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_MISC_CTL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_SPD_ABIL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_STATUS1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_STATUS2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_pcsx#_10gbx_status_reg
+ *
+ * PCSX_10GBX_STATUS_REG = 10gbx_status_reg
+ *
+ */
+union cvmx_pcsxx_10gbx_status_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_10gbx_status_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t alignd                       : 1;  /**< 1=Lane alignment achieved, 0=Lanes not aligned */
+	uint64_t pattst                       : 1;  /**< Always at 0, no pattern testing capability */
+	uint64_t reserved_4_10                : 7;
+	uint64_t l3sync                       : 1;  /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */
+	uint64_t l2sync                       : 1;  /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */
+	uint64_t l1sync                       : 1;  /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */
+	uint64_t l0sync                       : 1;  /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */
+#else
+	uint64_t l0sync                       : 1;
+	uint64_t l1sync                       : 1;
+	uint64_t l2sync                       : 1;
+	uint64_t l3sync                       : 1;
+	uint64_t reserved_4_10                : 7;
+	uint64_t pattst                       : 1;
+	uint64_t alignd                       : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn52xx;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn52xxp1;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn56xx;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn56xxp1;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn63xx;
+	struct cvmx_pcsxx_10gbx_status_reg_s  cn63xxp1;
+};
+typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t;
+
+/**
+ * cvmx_pcsx#_bist_status_reg
+ *
+ * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0].
+ * See pcs.csr  for sgmii/1000Base-X logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ *
+ *
+ *  PCSX Bist Status Register
+ */
+union cvmx_pcsxx_bist_status_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_bist_status_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t bist_status                  : 1;  /**< 1=bist failure, 0=bisted memory ok or bist in progress
+                                                         pcsx.tx_sm.drf8x36m1_async_bist */
+#else
+	uint64_t bist_status                  : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_pcsxx_bist_status_reg_s   cn52xx;
+	struct cvmx_pcsxx_bist_status_reg_s   cn52xxp1;
+	struct cvmx_pcsxx_bist_status_reg_s   cn56xx;
+	struct cvmx_pcsxx_bist_status_reg_s   cn56xxp1;
+	struct cvmx_pcsxx_bist_status_reg_s   cn63xx;
+	struct cvmx_pcsxx_bist_status_reg_s   cn63xxp1;
+};
+typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t;
+
+/**
+ * cvmx_pcsx#_bit_lock_status_reg
+ *
+ * LN_SWAP for XAUI is to simplify interconnection layout between devices
+ *
+ *
+ * PCSX Bit Lock Status Register
+ */
+union cvmx_pcsxx_bit_lock_status_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_bit_lock_status_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t bitlck3                      : 1;  /**< Receive Lane 3 bit lock status */
+	uint64_t bitlck2                      : 1;  /**< Receive Lane 2 bit lock status */
+	uint64_t bitlck1                      : 1;  /**< Receive Lane 1 bit lock status */
+	uint64_t bitlck0                      : 1;  /**< Receive Lane 0 bit lock status */
+#else
+	uint64_t bitlck0                      : 1;
+	uint64_t bitlck1                      : 1;
+	uint64_t bitlck2                      : 1;
+	uint64_t bitlck3                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
+	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
+};
+typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t;
+
+/**
+ * cvmx_pcsx#_control1_reg
+ *
+ * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(sgmii or 1000Base-X), this bit must be 0.
+ * See pcsx.csr for xaui logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ *
+ *
+ *  PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3
+ *
+ *
+ *  PCSX_CONTROL1_REG = Control Register1
+ */
+union cvmx_pcsxx_control1_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_control1_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t reset                        : 1;  /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
+                                                         has been reset. Takes 32 eclk cycles to reset pcs
+                                                         0=Normal operation */
+	uint64_t loopbck1                     : 1;  /**< 0=normal operation, 1=internal loopback mode
+                                                         xgmii tx data received from gmx tx port is returned
+                                                         back into gmx, xgmii rx port. */
+	uint64_t spdsel1                      : 1;  /**< See bit 6 description */
+	uint64_t reserved_12_12               : 1;
+	uint64_t lo_pwr                       : 1;  /**< 1=Power Down(HW reset), 0=Normal operation */
+	uint64_t reserved_7_10                : 4;
+	uint64_t spdsel0                      : 1;  /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has
+                                                         no effect.
+                                                         [<6>, <13>]Link Speed selection
+                                                           1    1   Bits 5:2 select speed */
+	uint64_t spd                          : 4;  /**< Always select 10Gb/s, writes have no effect */
+	uint64_t reserved_0_1                 : 2;
+#else
+	uint64_t reserved_0_1                 : 2;
+	uint64_t spd                          : 4;
+	uint64_t spdsel0                      : 1;
+	uint64_t reserved_7_10                : 4;
+	uint64_t lo_pwr                       : 1;
+	uint64_t reserved_12_12               : 1;
+	uint64_t spdsel1                      : 1;
+	uint64_t loopbck1                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsxx_control1_reg_s      cn52xx;
+	struct cvmx_pcsxx_control1_reg_s      cn52xxp1;
+	struct cvmx_pcsxx_control1_reg_s      cn56xx;
+	struct cvmx_pcsxx_control1_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_control1_reg_s      cn63xx;
+	struct cvmx_pcsxx_control1_reg_s      cn63xxp1;
+};
+typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t;
+
+/**
+ * cvmx_pcsx#_control2_reg
+ *
+ * PCSX_CONTROL2_REG = Control Register2
+ *
+ */
+union cvmx_pcsxx_control2_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_control2_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t type                         : 2;  /**< Always 2'b01, 10GBASE-X only supported */
+#else
+	uint64_t type                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pcsxx_control2_reg_s      cn52xx;
+	struct cvmx_pcsxx_control2_reg_s      cn52xxp1;
+	struct cvmx_pcsxx_control2_reg_s      cn56xx;
+	struct cvmx_pcsxx_control2_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_control2_reg_s      cn63xx;
+	struct cvmx_pcsxx_control2_reg_s      cn63xxp1;
+};
+typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t;
+
+/**
+ * cvmx_pcsx#_int_en_reg
+ *
+ * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in
+ *       Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2
+ *       indicating an invalid code group was received on one of the 4 receive lanes.
+ *       This interrupt should be always disabled and used only for link problem debugging help.
+ *
+ *
+ * PCSX Interrupt Enable Register
+ */
+union cvmx_pcsxx_int_en_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_int_en_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t dbg_sync_en                  : 1;  /**< Code Group sync failure debug help */
+	uint64_t algnlos_en                   : 1;  /**< Enable ALGNLOS interrupt */
+	uint64_t synlos_en                    : 1;  /**< Enable SYNLOS interrupt */
+	uint64_t bitlckls_en                  : 1;  /**< Enable BITLCKLS interrupt */
+	uint64_t rxsynbad_en                  : 1;  /**< Enable RXSYNBAD  interrupt */
+	uint64_t rxbad_en                     : 1;  /**< Enable RXBAD  interrupt */
+	uint64_t txflt_en                     : 1;  /**< Enable TXFLT   interrupt */
+#else
+	uint64_t txflt_en                     : 1;
+	uint64_t rxbad_en                     : 1;
+	uint64_t rxsynbad_en                  : 1;
+	uint64_t bitlckls_en                  : 1;
+	uint64_t synlos_en                    : 1;
+	uint64_t algnlos_en                   : 1;
+	uint64_t dbg_sync_en                  : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pcsxx_int_en_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t algnlos_en                   : 1;  /**< Enable ALGNLOS interrupt */
+	uint64_t synlos_en                    : 1;  /**< Enable SYNLOS interrupt */
+	uint64_t bitlckls_en                  : 1;  /**< Enable BITLCKLS interrupt */
+	uint64_t rxsynbad_en                  : 1;  /**< Enable RXSYNBAD  interrupt */
+	uint64_t rxbad_en                     : 1;  /**< Enable RXBAD  interrupt */
+	uint64_t txflt_en                     : 1;  /**< Enable TXFLT   interrupt */
+#else
+	uint64_t txflt_en                     : 1;
+	uint64_t rxbad_en                     : 1;
+	uint64_t rxsynbad_en                  : 1;
+	uint64_t bitlckls_en                  : 1;
+	uint64_t synlos_en                    : 1;
+	uint64_t algnlos_en                   : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn52xx;
+	struct cvmx_pcsxx_int_en_reg_cn52xx   cn52xxp1;
+	struct cvmx_pcsxx_int_en_reg_cn52xx   cn56xx;
+	struct cvmx_pcsxx_int_en_reg_cn52xx   cn56xxp1;
+	struct cvmx_pcsxx_int_en_reg_s        cn63xx;
+	struct cvmx_pcsxx_int_en_reg_s        cn63xxp1;
+};
+typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t;
+
+/**
+ * cvmx_pcsx#_int_reg
+ *
+ * PCSX Interrupt Register
+ *
+ */
+union cvmx_pcsxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t dbg_sync                     : 1;  /**< Code Group sync failure debug help, see Note below */
+	uint64_t algnlos                      : 1;  /**< Set when XAUI lanes lose alignment */
+	uint64_t synlos                       : 1;  /**< Set when Code group sync lost on 1 or more  lanes */
+	uint64_t bitlckls                     : 1;  /**< Set when Bit lock lost on 1 or more xaui lanes */
+	uint64_t rxsynbad                     : 1;  /**< Set when RX code grp sync st machine in bad state
+                                                         in one of the 4 xaui lanes */
+	uint64_t rxbad                        : 1;  /**< Set when RX state machine in bad state */
+	uint64_t txflt                        : 1;  /**< None defined at this time, always 0x0 */
+#else
+	uint64_t txflt                        : 1;
+	uint64_t rxbad                        : 1;
+	uint64_t rxsynbad                     : 1;
+	uint64_t bitlckls                     : 1;
+	uint64_t synlos                       : 1;
+	uint64_t algnlos                      : 1;
+	uint64_t dbg_sync                     : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pcsxx_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t algnlos                      : 1;  /**< Set when XAUI lanes lose alignment */
+	uint64_t synlos                       : 1;  /**< Set when Code group sync lost on 1 or more  lanes */
+	uint64_t bitlckls                     : 1;  /**< Set when Bit lock lost on 1 or more xaui lanes */
+	uint64_t rxsynbad                     : 1;  /**< Set when RX code grp sync st machine in bad state
+                                                         in one of the 4 xaui lanes */
+	uint64_t rxbad                        : 1;  /**< Set when RX state machine in bad state */
+	uint64_t txflt                        : 1;  /**< None defined at this time, always 0x0 */
+#else
+	uint64_t txflt                        : 1;
+	uint64_t rxbad                        : 1;
+	uint64_t rxsynbad                     : 1;
+	uint64_t bitlckls                     : 1;
+	uint64_t synlos                       : 1;
+	uint64_t algnlos                      : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} cn52xx;
+	struct cvmx_pcsxx_int_reg_cn52xx      cn52xxp1;
+	struct cvmx_pcsxx_int_reg_cn52xx      cn56xx;
+	struct cvmx_pcsxx_int_reg_cn52xx      cn56xxp1;
+	struct cvmx_pcsxx_int_reg_s           cn63xx;
+	struct cvmx_pcsxx_int_reg_s           cn63xxp1;
+};
+typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t;
+
+/**
+ * cvmx_pcsx#_log_anl_reg
+ *
+ * PCSX Logic Analyzer Register
+ *
+ */
+union cvmx_pcsxx_log_anl_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_log_anl_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t enc_mode                     : 1;  /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
+                                                         See .../rtl/pcs/readme_logic_analyzer.txt for details */
+	uint64_t drop_ln                      : 2;  /**< xaui lane# to drop from logic analyzer packets
+                                                         [<5>, <4>]  Drop lane \#
+                                                          0    0   Drop lane 0 data
+                                                          0    1   Drop lane 1 data
+                                                          1    0   Drop lane 2 data
+                                                          1    1   Drop lane 3 data */
+	uint64_t lafifovfl                    : 1;  /**< 1=logic analyser fif overflowed one or more times
+                                                         during packetization.
+                                                         Write 1 to clear this bit */
+	uint64_t la_en                        : 1;  /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
+	uint64_t pkt_sz                       : 2;  /**< [<1>, <0>]  Logic Analyzer Packet Size
+                                                         0    0   Packet size 1k bytes
+                                                         0    1   Packet size 4k bytes
+                                                         1    0   Packet size 8k bytes
+                                                         1    1   Packet size 16k bytes */
+#else
+	uint64_t pkt_sz                       : 2;
+	uint64_t la_en                        : 1;
+	uint64_t lafifovfl                    : 1;
+	uint64_t drop_ln                      : 2;
+	uint64_t enc_mode                     : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pcsxx_log_anl_reg_s       cn52xx;
+	struct cvmx_pcsxx_log_anl_reg_s       cn52xxp1;
+	struct cvmx_pcsxx_log_anl_reg_s       cn56xx;
+	struct cvmx_pcsxx_log_anl_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_log_anl_reg_s       cn63xx;
+	struct cvmx_pcsxx_log_anl_reg_s       cn63xxp1;
+};
+typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t;
+
+/**
+ * cvmx_pcsx#_misc_ctl_reg
+ *
+ * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6>  ^  [4[RXPLRT<1>]];
+ *
+ * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2>  ^  [4[TXPLRT<0>]];
+ *
+ * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities
+ *
+ *
+ *
+ * PCSX Misc Control Register
+ */
+union cvmx_pcsxx_misc_ctl_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_misc_ctl_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t tx_swap                      : 1;  /**< 0=do not swap xaui lanes going out to qlm's
+                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
+	uint64_t rx_swap                      : 1;  /**< 0=do not swap xaui lanes coming in from qlm's
+                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
+	uint64_t xaui                         : 1;  /**< 1=XAUI mode selected, 0=not XAUI mode selected
+                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
+	uint64_t gmxeno                       : 1;  /**< GMX port enable override, GMX en/dis status is held
+                                                         during data packet reception. */
+#else
+	uint64_t gmxeno                       : 1;
+	uint64_t xaui                         : 1;
+	uint64_t rx_swap                      : 1;
+	uint64_t tx_swap                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn52xx;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn52xxp1;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn56xx;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn63xx;
+	struct cvmx_pcsxx_misc_ctl_reg_s      cn63xxp1;
+};
+typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t;
+
+/**
+ * cvmx_pcsx#_rx_sync_states_reg
+ *
+ * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
+ *
+ */
+union cvmx_pcsxx_rx_sync_states_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_rx_sync_states_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t sync3st                      : 4;  /**< Receive lane 3 code grp sync state machine state */
+	uint64_t sync2st                      : 4;  /**< Receive lane 2 code grp sync state machine state */
+	uint64_t sync1st                      : 4;  /**< Receive lane 1 code grp sync state machine state */
+	uint64_t sync0st                      : 4;  /**< Receive lane 0 code grp sync state machine state */
+#else
+	uint64_t sync0st                      : 4;
+	uint64_t sync1st                      : 4;
+	uint64_t sync2st                      : 4;
+	uint64_t sync3st                      : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
+	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
+};
+typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t;
+
+/**
+ * cvmx_pcsx#_spd_abil_reg
+ *
+ * PCSX_SPD_ABIL_REG = Speed ability register
+ *
+ */
+union cvmx_pcsxx_spd_abil_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_spd_abil_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t tenpasst                     : 1;  /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
+	uint64_t tengb                        : 1;  /**< Always 1, 10Gb/s supported */
+#else
+	uint64_t tengb                        : 1;
+	uint64_t tenpasst                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn52xx;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn52xxp1;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn56xx;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn56xxp1;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn63xx;
+	struct cvmx_pcsxx_spd_abil_reg_s      cn63xxp1;
+};
+typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t;
+
+/**
+ * cvmx_pcsx#_status1_reg
+ *
+ * PCSX_STATUS1_REG = Status Register1
+ *
+ */
+union cvmx_pcsxx_status1_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_status1_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t flt                          : 1;  /**< 1=Fault condition detected, 0=No fault condition
+                                                         This bit is a logical OR of Status2 reg bits 11,10 */
+	uint64_t reserved_3_6                 : 4;
+	uint64_t rcv_lnk                      : 1;  /**< 1=Receive Link up, 0=Receive Link down
+                                                         Latching Low version of r_10gbx_status_reg[12],
+                                                         Link down status continues until SW read. */
+	uint64_t lpable                       : 1;  /**< Always set to 1 for Low Power ablility indication */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t lpable                       : 1;
+	uint64_t rcv_lnk                      : 1;
+	uint64_t reserved_3_6                 : 4;
+	uint64_t flt                          : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pcsxx_status1_reg_s       cn52xx;
+	struct cvmx_pcsxx_status1_reg_s       cn52xxp1;
+	struct cvmx_pcsxx_status1_reg_s       cn56xx;
+	struct cvmx_pcsxx_status1_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_status1_reg_s       cn63xx;
+	struct cvmx_pcsxx_status1_reg_s       cn63xxp1;
+};
+typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t;
+
+/**
+ * cvmx_pcsx#_status2_reg
+ *
+ * PCSX_STATUS2_REG = Status Register2
+ *
+ */
+union cvmx_pcsxx_status2_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_status2_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t dev                          : 2;  /**< Always at 2'b10, means a Device present at the addr */
+	uint64_t reserved_12_13               : 2;
+	uint64_t xmtflt                       : 1;  /**< 0=No xmit fault, 1=xmit fault. Implements latching
+                                                         High function until SW read. */
+	uint64_t rcvflt                       : 1;  /**< 0=No rcv fault, 1=rcv fault. Implements latching
+                                                         High function until SW read */
+	uint64_t reserved_3_9                 : 7;
+	uint64_t tengb_w                      : 1;  /**< Always 0, no 10GBASE-W capability */
+	uint64_t tengb_x                      : 1;  /**< Always 1, 10GBASE-X capable */
+	uint64_t tengb_r                      : 1;  /**< Always 0, no 10GBASE-R capability */
+#else
+	uint64_t tengb_r                      : 1;
+	uint64_t tengb_x                      : 1;
+	uint64_t tengb_w                      : 1;
+	uint64_t reserved_3_9                 : 7;
+	uint64_t rcvflt                       : 1;
+	uint64_t xmtflt                       : 1;
+	uint64_t reserved_12_13               : 2;
+	uint64_t dev                          : 2;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pcsxx_status2_reg_s       cn52xx;
+	struct cvmx_pcsxx_status2_reg_s       cn52xxp1;
+	struct cvmx_pcsxx_status2_reg_s       cn56xx;
+	struct cvmx_pcsxx_status2_reg_s       cn56xxp1;
+	struct cvmx_pcsxx_status2_reg_s       cn63xx;
+	struct cvmx_pcsxx_status2_reg_s       cn63xxp1;
+};
+typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t;
+
+/**
+ * cvmx_pcsx#_tx_rx_polarity_reg
+ *
+ * PCSX_POLARITY_REG = TX_RX polarity reg
+ *
+ */
+union cvmx_pcsxx_tx_rx_polarity_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t xor_rxplrt                   : 4;  /**< Per lane RX polarity control */
+	uint64_t xor_txplrt                   : 4;  /**< Per lane TX polarity control */
+	uint64_t rxplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+	uint64_t txplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+	uint64_t txplrt                       : 1;
+	uint64_t rxplrt                       : 1;
+	uint64_t xor_txplrt                   : 4;
+	uint64_t xor_rxplrt                   : 4;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t rxplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+	uint64_t txplrt                       : 1;  /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+	uint64_t txplrt                       : 1;
+	uint64_t rxplrt                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn52xxp1;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
+	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
+};
+typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t;
+
+/**
+ * cvmx_pcsx#_tx_rx_states_reg
+ *
+ * PCSX_TX_RX_STATES_REG = Transmit Receive States Register
+ *
+ */
+union cvmx_pcsxx_tx_rx_states_reg
+{
+	uint64_t u64;
+	struct cvmx_pcsxx_tx_rx_states_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t term_err                     : 1;  /**< 1=Check end function detected error in packet
+                                                         terminate ||T|| column or the one after it */
+	uint64_t syn3bad                      : 1;  /**< 1=lane 3 code grp sync state machine in bad state */
+	uint64_t syn2bad                      : 1;  /**< 1=lane 2 code grp sync state machine in bad state */
+	uint64_t syn1bad                      : 1;  /**< 1=lane 1 code grp sync state machine in bad state */
+	uint64_t syn0bad                      : 1;  /**< 1=lane 0 code grp sync state machine in bad state */
+	uint64_t rxbad                        : 1;  /**< 1=Rcv state machine in a bad state, HW malfunction */
+	uint64_t algn_st                      : 3;  /**< Lane alignment state machine state state */
+	uint64_t rx_st                        : 2;  /**< Receive state machine state state */
+	uint64_t tx_st                        : 3;  /**< Transmit state machine state state */
+#else
+	uint64_t tx_st                        : 3;
+	uint64_t rx_st                        : 2;
+	uint64_t algn_st                      : 3;
+	uint64_t rxbad                        : 1;
+	uint64_t syn0bad                      : 1;
+	uint64_t syn1bad                      : 1;
+	uint64_t syn2bad                      : 1;
+	uint64_t syn3bad                      : 1;
+	uint64_t term_err                     : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn52xx;
+	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t syn3bad                      : 1;  /**< 1=lane 3 code grp sync state machine in bad state */
+	uint64_t syn2bad                      : 1;  /**< 1=lane 2 code grp sync state machine in bad state */
+	uint64_t syn1bad                      : 1;  /**< 1=lane 1 code grp sync state machine in bad state */
+	uint64_t syn0bad                      : 1;  /**< 1=lane 0 code grp sync state machine in bad state */
+	uint64_t rxbad                        : 1;  /**< 1=Rcv state machine in a bad state, HW malfunction */
+	uint64_t algn_st                      : 3;  /**< Lane alignment state machine state state */
+	uint64_t rx_st                        : 2;  /**< Receive state machine state state */
+	uint64_t tx_st                        : 3;  /**< Transmit state machine state state */
+#else
+	uint64_t tx_st                        : 3;
+	uint64_t rx_st                        : 2;
+	uint64_t algn_st                      : 3;
+	uint64_t rxbad                        : 1;
+	uint64_t syn0bad                      : 1;
+	uint64_t syn1bad                      : 1;
+	uint64_t syn2bad                      : 1;
+	uint64_t syn3bad                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn52xxp1;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn56xx;
+	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn63xx;
+	struct cvmx_pcsxx_tx_rx_states_reg_s  cn63xxp1;
+};
+typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pemx-defs.h b/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
new file mode 100644
index 0000000..bb0269a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
@@ -0,0 +1,1192 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pemx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pemx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PEMX_TYPEDEFS_H__
+#define __CVMX_PEMX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
+}
+#else
+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
+}
+#else
+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+
+/**
+ * cvmx_pem#_bar1_index#
+ *
+ * PEM_BAR1_INDEXX = PEM BAR1 IndexX Register
+ *
+ * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
+ */
+union cvmx_pemx_bar1_indexx
+{
+	uint64_t u64;
+	struct cvmx_pemx_bar1_indexx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t addr_idx                     : 16; /**< Address bits [37:22] sent to L2C */
+	uint64_t ca                           : 1;  /**< Set '1' when access is not to be cached in L2. */
+	uint64_t end_swp                      : 2;  /**< Endian Swap Mode */
+	uint64_t addr_v                       : 1;  /**< Set '1' when the selected address range is valid. */
+#else
+	uint64_t addr_v                       : 1;
+	uint64_t end_swp                      : 2;
+	uint64_t ca                           : 1;
+	uint64_t addr_idx                     : 16;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_pemx_bar1_indexx_s        cn63xx;
+	struct cvmx_pemx_bar1_indexx_s        cn63xxp1;
+};
+typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
+
+/**
+ * cvmx_pem#_bar_ctl
+ *
+ * PEM_BAR_CTUS = PEM BAR Control
+ *
+ * Contains control for BAR accesses.
+ */
+union cvmx_pemx_bar_ctl
+{
+	uint64_t u64;
+	struct cvmx_pemx_bar_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t bar1_siz                     : 3;  /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
+                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
+                                                         0 and 7 are reserved. */
+	uint64_t bar2_enb                     : 1;  /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will cause UR responses. */
+	uint64_t bar2_esx                     : 2;  /**< Value will be XORed with pci-address[39:38] to
+                                                         determine the endian swap mode. */
+	uint64_t bar2_cax                     : 1;  /**< Value will be XORed with pcie-address[40] to
+                                                         determine the L2 cache attribute.
+                                                         Not cached in L2 if XOR result is 1 */
+#else
+	uint64_t bar2_cax                     : 1;
+	uint64_t bar2_esx                     : 2;
+	uint64_t bar2_enb                     : 1;
+	uint64_t bar1_siz                     : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pemx_bar_ctl_s            cn63xx;
+	struct cvmx_pemx_bar_ctl_s            cn63xxp1;
+};
+typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
+
+/**
+ * cvmx_pem#_bist_status
+ *
+ * PEM_BIST_STATUS = PEM Bist Status
+ *
+ * Contains the diffrent interrupt summary bits of the PEM.
+ */
+union cvmx_pemx_bist_status
+{
+	uint64_t u64;
+	struct cvmx_pemx_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t retry                        : 1;  /**< Retry Buffer. */
+	uint64_t rqdata0                      : 1;  /**< Rx Queue Data Memory0. */
+	uint64_t rqdata1                      : 1;  /**< Rx Queue Data Memory1. */
+	uint64_t rqdata2                      : 1;  /**< Rx Queue Data Memory2. */
+	uint64_t rqdata3                      : 1;  /**< Rx Queue Data Memory3. */
+	uint64_t rqhdr1                       : 1;  /**< Rx Queue Header1. */
+	uint64_t rqhdr0                       : 1;  /**< Rx Queue Header0. */
+	uint64_t sot                          : 1;  /**< SOT Buffer. */
+#else
+	uint64_t sot                          : 1;
+	uint64_t rqhdr0                       : 1;
+	uint64_t rqhdr1                       : 1;
+	uint64_t rqdata3                      : 1;
+	uint64_t rqdata2                      : 1;
+	uint64_t rqdata1                      : 1;
+	uint64_t rqdata0                      : 1;
+	uint64_t retry                        : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pemx_bist_status_s        cn63xx;
+	struct cvmx_pemx_bist_status_s        cn63xxp1;
+};
+typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
+
+/**
+ * cvmx_pem#_bist_status2
+ *
+ * PEM(0..1)_BIST_STATUS2 = PEM BIST Status Register
+ *
+ * Results from BIST runs of PEM's memories.
+ */
+union cvmx_pemx_bist_status2
+{
+	uint64_t u64;
+	struct cvmx_pemx_bist_status2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t e2p_cpl                      : 1;  /**< BIST Status for the e2p_cpl_fifo */
+	uint64_t e2p_n                        : 1;  /**< BIST Status for the e2p_n_fifo */
+	uint64_t e2p_p                        : 1;  /**< BIST Status for the e2p_p_fifo */
+	uint64_t peai_p2e                     : 1;  /**< BIST Status for the peai__pesc_fifo */
+	uint64_t pef_tpf1                     : 1;  /**< BIST Status for the pef_tlp_p_fifo1 */
+	uint64_t pef_tpf0                     : 1;  /**< BIST Status for the pef_tlp_p_fifo0 */
+	uint64_t pef_tnf                      : 1;  /**< BIST Status for the pef_tlp_n_fifo */
+	uint64_t pef_tcf1                     : 1;  /**< BIST Status for the pef_tlp_cpl_fifo1 */
+	uint64_t pef_tc0                      : 1;  /**< BIST Status for the pef_tlp_cpl_fifo0 */
+	uint64_t ppf                          : 1;  /**< BIST Status for the ppf_fifo */
+#else
+	uint64_t ppf                          : 1;
+	uint64_t pef_tc0                      : 1;
+	uint64_t pef_tcf1                     : 1;
+	uint64_t pef_tnf                      : 1;
+	uint64_t pef_tpf0                     : 1;
+	uint64_t pef_tpf1                     : 1;
+	uint64_t peai_p2e                     : 1;
+	uint64_t e2p_p                        : 1;
+	uint64_t e2p_n                        : 1;
+	uint64_t e2p_cpl                      : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_pemx_bist_status2_s       cn63xx;
+	struct cvmx_pemx_bist_status2_s       cn63xxp1;
+};
+typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
+
+/**
+ * cvmx_pem#_cfg_rd
+ *
+ * PEM_CFG_RD = PEM Configuration Read
+ *
+ * Allows read access to the configuration in the PCIe Core.
+ */
+union cvmx_pemx_cfg_rd
+{
+	uint64_t u64;
+	struct cvmx_pemx_cfg_rd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 32; /**< Data. */
+	uint64_t addr                         : 32; /**< Address to read. A write to this register
+                                                         starts a read operation. */
+#else
+	uint64_t addr                         : 32;
+	uint64_t data                         : 32;
+#endif
+	} s;
+	struct cvmx_pemx_cfg_rd_s             cn63xx;
+	struct cvmx_pemx_cfg_rd_s             cn63xxp1;
+};
+typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
+
+/**
+ * cvmx_pem#_cfg_wr
+ *
+ * PEM_CFG_WR = PEM Configuration Write
+ *
+ * Allows write access to the configuration in the PCIe Core.
+ */
+union cvmx_pemx_cfg_wr
+{
+	uint64_t u64;
+	struct cvmx_pemx_cfg_wr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 32; /**< Data to write. A write to this register starts
+                                                         a write operation. */
+	uint64_t addr                         : 32; /**< Address to write. A write to this register starts
+                                                         a write operation. */
+#else
+	uint64_t addr                         : 32;
+	uint64_t data                         : 32;
+#endif
+	} s;
+	struct cvmx_pemx_cfg_wr_s             cn63xx;
+	struct cvmx_pemx_cfg_wr_s             cn63xxp1;
+};
+typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
+
+/**
+ * cvmx_pem#_cpl_lut_valid
+ *
+ * PEM_CPL_LUT_VALID = PEM Cmpletion Lookup Table Valid
+ *
+ * Bit set for outstanding tag read.
+ */
+union cvmx_pemx_cpl_lut_valid
+{
+	uint64_t u64;
+	struct cvmx_pemx_cpl_lut_valid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t tag                          : 32; /**< Bit vector set cooresponds to an outstanding tag
+                                                         expecting a completion. */
+#else
+	uint64_t tag                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pemx_cpl_lut_valid_s      cn63xx;
+	struct cvmx_pemx_cpl_lut_valid_s      cn63xxp1;
+};
+typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
+
+/**
+ * cvmx_pem#_ctl_status
+ *
+ * PEM_CTL_STATUS = PEM Control Status
+ *
+ * General control and status of the PEM.
+ */
+union cvmx_pemx_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_pemx_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t auto_sd                      : 1;  /**< Link Hardware Autonomous Speed Disable. */
+	uint64_t dnum                         : 5;  /**< Primary bus device number. */
+	uint64_t pbus                         : 8;  /**< Primary bus number. */
+	uint64_t reserved_32_33               : 2;
+	uint64_t cfg_rtry                     : 16; /**< The time x 0x10000 in core clocks to wait for a
+                                                         CPL to a CFG RD that does not carry a Retry Status.
+                                                         Until such time that the timeout occurs and Retry
+                                                         Status is received for a CFG RD, the Read CFG Read
+                                                         will be resent. A value of 0 disables retries and
+                                                         treats a CPL Retry as a CPL UR.
+                                                         When enabled only one CFG RD may be issued until
+                                                         either successful completion or CPL UR. */
+	uint64_t reserved_12_15               : 4;
+	uint64_t pm_xtoff                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
+	uint64_t pm_xpme                      : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_pme port. EP mode. */
+	uint64_t ob_p_cmd                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t nf_ecrc                      : 1;  /**< Do not forward peer-to-peer ECRC TLPs. */
+	uint64_t dly_one                      : 1;  /**< When set the output client state machines will
+                                                         wait one cycle before starting a new TLP out. */
+	uint64_t lnk_enb                      : 1;  /**< When set '1' the link is enabled when '0' the
+                                                         link is disabled. This bit only is active when in
+                                                         RC mode. */
+	uint64_t ro_ctlp                      : 1;  /**< When set '1' C-TLPs that have the RO bit set will
+                                                         not wait for P-TLPs that normaly would be sent
+                                                         first. */
+	uint64_t fast_lm                      : 1;  /**< When '1' forces fast link mode. */
+	uint64_t inv_ecrc                     : 1;  /**< When '1' causes the LSB of the ECRC to be inverted. */
+	uint64_t inv_lcrc                     : 1;  /**< When '1' causes the LSB of the LCRC to be inverted. */
+#else
+	uint64_t inv_lcrc                     : 1;
+	uint64_t inv_ecrc                     : 1;
+	uint64_t fast_lm                      : 1;
+	uint64_t ro_ctlp                      : 1;
+	uint64_t lnk_enb                      : 1;
+	uint64_t dly_one                      : 1;
+	uint64_t nf_ecrc                      : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t ob_p_cmd                     : 1;
+	uint64_t pm_xpme                      : 1;
+	uint64_t pm_xtoff                     : 1;
+	uint64_t reserved_12_15               : 4;
+	uint64_t cfg_rtry                     : 16;
+	uint64_t reserved_32_33               : 2;
+	uint64_t pbus                         : 8;
+	uint64_t dnum                         : 5;
+	uint64_t auto_sd                      : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pemx_ctl_status_s         cn63xx;
+	struct cvmx_pemx_ctl_status_s         cn63xxp1;
+};
+typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
+
+/**
+ * cvmx_pem#_dbg_info
+ *
+ * PEM(0..1)_DBG_INFO = PEM Debug Information
+ *
+ * General debug info.
+ */
+union cvmx_pemx_dbg_info
+{
+	uint64_t u64;
+	struct cvmx_pemx_dbg_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t ecrc_e                       : 1;  /**< Received a ECRC error.
+                                                         radm_ecrc_err */
+	uint64_t rawwpp                       : 1;  /**< Received a write with poisoned payload
+                                                         radm_rcvd_wreq_poisoned */
+	uint64_t racpp                        : 1;  /**< Received a completion with poisoned payload
+                                                         radm_rcvd_cpl_poisoned */
+	uint64_t ramtlp                       : 1;  /**< Received a malformed TLP
+                                                         radm_mlf_tlp_err */
+	uint64_t rarwdns                      : 1;  /**< Recieved a request which device does not support
+                                                         radm_rcvd_ur_req */
+	uint64_t caar                         : 1;  /**< Completer aborted a request
+                                                         radm_rcvd_ca_req
+                                                         This bit will never be set because Octeon does
+                                                         not generate Completer Aborts. */
+	uint64_t racca                        : 1;  /**< Received a completion with CA status
+                                                         radm_rcvd_cpl_ca */
+	uint64_t racur                        : 1;  /**< Received a completion with UR status
+                                                         radm_rcvd_cpl_ur */
+	uint64_t rauc                         : 1;  /**< Received an unexpected completion
+                                                         radm_unexp_cpl_err */
+	uint64_t rqo                          : 1;  /**< Receive queue overflow. Normally happens only when
+                                                         flow control advertisements are ignored
+                                                         radm_qoverflow */
+	uint64_t fcuv                         : 1;  /**< Flow Control Update Violation (opt. checks)
+                                                         int_xadm_fc_prot_err */
+	uint64_t rpe                          : 1;  /**< When the PHY reports 8B/10B decode error
+                                                         (RxStatus = 3b100) or disparity error
+                                                         (RxStatus = 3b111), the signal rmlh_rcvd_err will
+                                                         be asserted.
+                                                         rmlh_rcvd_err */
+	uint64_t fcpvwt                       : 1;  /**< Flow Control Protocol Violation (Watchdog Timer)
+                                                         rtlh_fc_prot_err */
+	uint64_t dpeoosd                      : 1;  /**< DLLP protocol error (out of sequence DLLP)
+                                                         rdlh_prot_err */
+	uint64_t rtwdle                       : 1;  /**< Received TLP with DataLink Layer Error
+                                                         rdlh_bad_tlp_err */
+	uint64_t rdwdle                       : 1;  /**< Received DLLP with DataLink Layer Error
+                                                         rdlh_bad_dllp_err */
+	uint64_t mre                          : 1;  /**< Max Retries Exceeded
+                                                         xdlh_replay_num_rlover_err */
+	uint64_t rte                          : 1;  /**< Replay Timer Expired
+                                                         xdlh_replay_timeout_err
+                                                         This bit is set when the REPLAY_TIMER expires in
+                                                         the PCIE core. The probability of this bit being
+                                                         set will increase with the traffic load. */
+	uint64_t acto                         : 1;  /**< A Completion Timeout Occured
+                                                         pedc_radm_cpl_timeout */
+	uint64_t rvdm                         : 1;  /**< Received Vendor-Defined Message
+                                                         pedc_radm_vendor_msg */
+	uint64_t rumep                        : 1;  /**< Received Unlock Message (EP Mode Only)
+                                                         pedc_radm_msg_unlock */
+	uint64_t rptamrc                      : 1;  /**< Received PME Turnoff Acknowledge Message
+                                                         (RC Mode only)
+                                                         pedc_radm_pm_to_ack */
+	uint64_t rpmerc                       : 1;  /**< Received PME Message (RC Mode only)
+                                                         pedc_radm_pm_pme */
+	uint64_t rfemrc                       : 1;  /**< Received Fatal Error Message (RC Mode only)
+                                                         pedc_radm_fatal_err
+                                                         Bit set when a message with ERR_FATAL is set. */
+	uint64_t rnfemrc                      : 1;  /**< Received Non-Fatal Error Message (RC Mode only)
+                                                         pedc_radm_nonfatal_err */
+	uint64_t rcemrc                       : 1;  /**< Received Correctable Error Message (RC Mode only)
+                                                         pedc_radm_correctable_err */
+	uint64_t rpoison                      : 1;  /**< Received Poisoned TLP
+                                                         pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
+	uint64_t recrce                       : 1;  /**< Received ECRC Error
+                                                         pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
+	uint64_t rtlplle                      : 1;  /**< Received TLP has link layer error
+                                                         pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
+	uint64_t rtlpmal                      : 1;  /**< Received TLP is malformed or a message.
+                                                         pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
+                                                         If the core receives a MSG (or Vendor Message)
+                                                         this bit will be set. */
+	uint64_t spoison                      : 1;  /**< Poisoned TLP sent
+                                                         peai__client0_tlp_ep & peai__client0_tlp_hv */
+#else
+	uint64_t spoison                      : 1;
+	uint64_t rtlpmal                      : 1;
+	uint64_t rtlplle                      : 1;
+	uint64_t recrce                       : 1;
+	uint64_t rpoison                      : 1;
+	uint64_t rcemrc                       : 1;
+	uint64_t rnfemrc                      : 1;
+	uint64_t rfemrc                       : 1;
+	uint64_t rpmerc                       : 1;
+	uint64_t rptamrc                      : 1;
+	uint64_t rumep                        : 1;
+	uint64_t rvdm                         : 1;
+	uint64_t acto                         : 1;
+	uint64_t rte                          : 1;
+	uint64_t mre                          : 1;
+	uint64_t rdwdle                       : 1;
+	uint64_t rtwdle                       : 1;
+	uint64_t dpeoosd                      : 1;
+	uint64_t fcpvwt                       : 1;
+	uint64_t rpe                          : 1;
+	uint64_t fcuv                         : 1;
+	uint64_t rqo                          : 1;
+	uint64_t rauc                         : 1;
+	uint64_t racur                        : 1;
+	uint64_t racca                        : 1;
+	uint64_t caar                         : 1;
+	uint64_t rarwdns                      : 1;
+	uint64_t ramtlp                       : 1;
+	uint64_t racpp                        : 1;
+	uint64_t rawwpp                       : 1;
+	uint64_t ecrc_e                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_pemx_dbg_info_s           cn63xx;
+	struct cvmx_pemx_dbg_info_s           cn63xxp1;
+};
+typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
+
+/**
+ * cvmx_pem#_dbg_info_en
+ *
+ * PEM(0..1)_DBG_INFO_EN = PEM Debug Information Enable
+ *
+ * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.
+ */
+union cvmx_pemx_dbg_info_en
+{
+	uint64_t u64;
+	struct cvmx_pemx_dbg_info_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t ecrc_e                       : 1;  /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */
+	uint64_t rawwpp                       : 1;  /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */
+	uint64_t racpp                        : 1;  /**< Allows PEM_DBG_INFO[28] to generate an interrupt. */
+	uint64_t ramtlp                       : 1;  /**< Allows PEM_DBG_INFO[27] to generate an interrupt. */
+	uint64_t rarwdns                      : 1;  /**< Allows PEM_DBG_INFO[26] to generate an interrupt. */
+	uint64_t caar                         : 1;  /**< Allows PEM_DBG_INFO[25] to generate an interrupt. */
+	uint64_t racca                        : 1;  /**< Allows PEM_DBG_INFO[24] to generate an interrupt. */
+	uint64_t racur                        : 1;  /**< Allows PEM_DBG_INFO[23] to generate an interrupt. */
+	uint64_t rauc                         : 1;  /**< Allows PEM_DBG_INFO[22] to generate an interrupt. */
+	uint64_t rqo                          : 1;  /**< Allows PEM_DBG_INFO[21] to generate an interrupt. */
+	uint64_t fcuv                         : 1;  /**< Allows PEM_DBG_INFO[20] to generate an interrupt. */
+	uint64_t rpe                          : 1;  /**< Allows PEM_DBG_INFO[19] to generate an interrupt. */
+	uint64_t fcpvwt                       : 1;  /**< Allows PEM_DBG_INFO[18] to generate an interrupt. */
+	uint64_t dpeoosd                      : 1;  /**< Allows PEM_DBG_INFO[17] to generate an interrupt. */
+	uint64_t rtwdle                       : 1;  /**< Allows PEM_DBG_INFO[16] to generate an interrupt. */
+	uint64_t rdwdle                       : 1;  /**< Allows PEM_DBG_INFO[15] to generate an interrupt. */
+	uint64_t mre                          : 1;  /**< Allows PEM_DBG_INFO[14] to generate an interrupt. */
+	uint64_t rte                          : 1;  /**< Allows PEM_DBG_INFO[13] to generate an interrupt. */
+	uint64_t acto                         : 1;  /**< Allows PEM_DBG_INFO[12] to generate an interrupt. */
+	uint64_t rvdm                         : 1;  /**< Allows PEM_DBG_INFO[11] to generate an interrupt. */
+	uint64_t rumep                        : 1;  /**< Allows PEM_DBG_INFO[10] to generate an interrupt. */
+	uint64_t rptamrc                      : 1;  /**< Allows PEM_DBG_INFO[9] to generate an interrupt. */
+	uint64_t rpmerc                       : 1;  /**< Allows PEM_DBG_INFO[8] to generate an interrupt. */
+	uint64_t rfemrc                       : 1;  /**< Allows PEM_DBG_INFO[7] to generate an interrupt. */
+	uint64_t rnfemrc                      : 1;  /**< Allows PEM_DBG_INFO[6] to generate an interrupt. */
+	uint64_t rcemrc                       : 1;  /**< Allows PEM_DBG_INFO[5] to generate an interrupt. */
+	uint64_t rpoison                      : 1;  /**< Allows PEM_DBG_INFO[4] to generate an interrupt. */
+	uint64_t recrce                       : 1;  /**< Allows PEM_DBG_INFO[3] to generate an interrupt. */
+	uint64_t rtlplle                      : 1;  /**< Allows PEM_DBG_INFO[2] to generate an interrupt. */
+	uint64_t rtlpmal                      : 1;  /**< Allows PEM_DBG_INFO[1] to generate an interrupt. */
+	uint64_t spoison                      : 1;  /**< Allows PEM_DBG_INFO[0] to generate an interrupt. */
+#else
+	uint64_t spoison                      : 1;
+	uint64_t rtlpmal                      : 1;
+	uint64_t rtlplle                      : 1;
+	uint64_t recrce                       : 1;
+	uint64_t rpoison                      : 1;
+	uint64_t rcemrc                       : 1;
+	uint64_t rnfemrc                      : 1;
+	uint64_t rfemrc                       : 1;
+	uint64_t rpmerc                       : 1;
+	uint64_t rptamrc                      : 1;
+	uint64_t rumep                        : 1;
+	uint64_t rvdm                         : 1;
+	uint64_t acto                         : 1;
+	uint64_t rte                          : 1;
+	uint64_t mre                          : 1;
+	uint64_t rdwdle                       : 1;
+	uint64_t rtwdle                       : 1;
+	uint64_t dpeoosd                      : 1;
+	uint64_t fcpvwt                       : 1;
+	uint64_t rpe                          : 1;
+	uint64_t fcuv                         : 1;
+	uint64_t rqo                          : 1;
+	uint64_t rauc                         : 1;
+	uint64_t racur                        : 1;
+	uint64_t racca                        : 1;
+	uint64_t caar                         : 1;
+	uint64_t rarwdns                      : 1;
+	uint64_t ramtlp                       : 1;
+	uint64_t racpp                        : 1;
+	uint64_t rawwpp                       : 1;
+	uint64_t ecrc_e                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_pemx_dbg_info_en_s        cn63xx;
+	struct cvmx_pemx_dbg_info_en_s        cn63xxp1;
+};
+typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
+
+/**
+ * cvmx_pem#_diag_status
+ *
+ * PEM_DIAG_STATUS = PEM Diagnostic Status
+ *
+ * Selection control for the cores diagnostic bus.
+ */
+union cvmx_pemx_diag_status
+{
+	uint64_t u64;
+	struct cvmx_pemx_diag_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t pm_dst                       : 1;  /**< Current power management DSTATE. */
+	uint64_t pm_stat                      : 1;  /**< Power Management Status. */
+	uint64_t pm_en                        : 1;  /**< Power Management Event Enable. */
+	uint64_t aux_en                       : 1;  /**< Auxilary Power Enable. */
+#else
+	uint64_t aux_en                       : 1;
+	uint64_t pm_en                        : 1;
+	uint64_t pm_stat                      : 1;
+	uint64_t pm_dst                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pemx_diag_status_s        cn63xx;
+	struct cvmx_pemx_diag_status_s        cn63xxp1;
+};
+typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
+
+/**
+ * cvmx_pem#_int_enb
+ *
+ * PEM(0..1)_INT_ENB = PEM Interrupt Enable
+ *
+ * Enables interrupt conditions for the PEM to generate an RSL interrupt.
+ */
+union cvmx_pemx_int_enb
+{
+	uint64_t u64;
+	struct cvmx_pemx_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t crs_dr                       : 1;  /**< Enables PEM_INT_SUM[13] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t crs_er                       : 1;  /**< Enables PEM_INT_SUM[12] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t rdlk                         : 1;  /**< Enables PEM_INT_SUM[11] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t exc                          : 1;  /**< Enables PEM_INT_SUM[10] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t un_bx                        : 1;  /**< Enables PEM_INT_SUM[9] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t un_b2                        : 1;  /**< Enables PEM_INT_SUM[8] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t un_b1                        : 1;  /**< Enables PEM_INT_SUM[7] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t up_bx                        : 1;  /**< Enables PEM_INT_SUM[6] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t up_b2                        : 1;  /**< Enables PEM_INT_SUM[5] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t up_b1                        : 1;  /**< Enables PEM_INT_SUM[4] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t pmem                         : 1;  /**< Enables PEM_INT_SUM[3] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t pmei                         : 1;  /**< Enables PEM_INT_SUM[2] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t se                           : 1;  /**< Enables PEM_INT_SUM[1] to generate an
+                                                         interrupt to the MIO. */
+	uint64_t aeri                         : 1;  /**< Enables PEM_INT_SUM[0] to generate an
+                                                         interrupt to the MIO. */
+#else
+	uint64_t aeri                         : 1;
+	uint64_t se                           : 1;
+	uint64_t pmei                         : 1;
+	uint64_t pmem                         : 1;
+	uint64_t up_b1                        : 1;
+	uint64_t up_b2                        : 1;
+	uint64_t up_bx                        : 1;
+	uint64_t un_b1                        : 1;
+	uint64_t un_b2                        : 1;
+	uint64_t un_bx                        : 1;
+	uint64_t exc                          : 1;
+	uint64_t rdlk                         : 1;
+	uint64_t crs_er                       : 1;
+	uint64_t crs_dr                       : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_pemx_int_enb_s            cn63xx;
+	struct cvmx_pemx_int_enb_s            cn63xxp1;
+};
+typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
+
+/**
+ * cvmx_pem#_int_enb_int
+ *
+ * PEM(0..1)_INT_ENB_INT = PEM Interrupt Enable
+ *
+ * Enables interrupt conditions for the PEM to generate an RSL interrupt.
+ */
+union cvmx_pemx_int_enb_int
+{
+	uint64_t u64;
+	struct cvmx_pemx_int_enb_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t crs_dr                       : 1;  /**< Enables PEM_INT_SUM[13] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t crs_er                       : 1;  /**< Enables PEM_INT_SUM[12] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t rdlk                         : 1;  /**< Enables PEM_INT_SUM[11] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t exc                          : 1;  /**< Enables PEM_INT_SUM[10] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t un_bx                        : 1;  /**< Enables PEM_INT_SUM[9] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t un_b2                        : 1;  /**< Enables PEM_INT_SUM[8] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t un_b1                        : 1;  /**< Enables PEM_INT_SUM[7] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t up_bx                        : 1;  /**< Enables PEM_INT_SUM[6] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t up_b2                        : 1;  /**< Enables PEM_INT_SUM[5] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t up_b1                        : 1;  /**< Enables PEM_INT_SUM[4] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t pmem                         : 1;  /**< Enables PEM_INT_SUM[3] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t pmei                         : 1;  /**< Enables PEM_INT_SUM[2] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t se                           : 1;  /**< Enables PEM_INT_SUM[1] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+	uint64_t aeri                         : 1;  /**< Enables PEM_INT_SUM[0] to generate an
+                                                         interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
+#else
+	uint64_t aeri                         : 1;
+	uint64_t se                           : 1;
+	uint64_t pmei                         : 1;
+	uint64_t pmem                         : 1;
+	uint64_t up_b1                        : 1;
+	uint64_t up_b2                        : 1;
+	uint64_t up_bx                        : 1;
+	uint64_t un_b1                        : 1;
+	uint64_t un_b2                        : 1;
+	uint64_t un_bx                        : 1;
+	uint64_t exc                          : 1;
+	uint64_t rdlk                         : 1;
+	uint64_t crs_er                       : 1;
+	uint64_t crs_dr                       : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_pemx_int_enb_int_s        cn63xx;
+	struct cvmx_pemx_int_enb_int_s        cn63xxp1;
+};
+typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
+
+/**
+ * cvmx_pem#_int_sum
+ *
+ * Below are in pesc_csr
+ *
+ *                  PEM(0..1)_INT_SUM = PEM Interrupt Summary
+ *
+ * Interrupt conditions for the PEM.
+ */
+union cvmx_pemx_int_sum
+{
+	uint64_t u64;
+	struct cvmx_pemx_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t crs_dr                       : 1;  /**< Had a CRS Timeout when Retries were disabled. */
+	uint64_t crs_er                       : 1;  /**< Had a CRS Timeout when Retries were enabled. */
+	uint64_t rdlk                         : 1;  /**< Received Read Lock TLP. */
+	uint64_t exc                          : 1;  /**< Set when the PEM_DBG_INFO register has a bit
+                                                         set and its cooresponding PEM_DBG_INFO_EN bit
+                                                         is set. */
+	uint64_t un_bx                        : 1;  /**< Received N-TLP for an unknown Bar. */
+	uint64_t un_b2                        : 1;  /**< Received N-TLP for Bar2 when bar2 is disabled. */
+	uint64_t un_b1                        : 1;  /**< Received N-TLP for Bar1 when bar1 index valid
+                                                         is not set. */
+	uint64_t up_bx                        : 1;  /**< Received P-TLP for an unknown Bar. */
+	uint64_t up_b2                        : 1;  /**< Received P-TLP for Bar2 when bar2 is disabeld. */
+	uint64_t up_b1                        : 1;  /**< Received P-TLP for Bar1 when bar1 index valid
+                                                         is not set. */
+	uint64_t pmem                         : 1;  /**< Recived PME MSG.
+                                                         (radm_pm_pme) */
+	uint64_t pmei                         : 1;  /**< PME Interrupt.
+                                                         (cfg_pme_int) */
+	uint64_t se                           : 1;  /**< System Error, RC Mode Only.
+                                                         (cfg_sys_err_rc) */
+	uint64_t aeri                         : 1;  /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         (cfg_aer_rc_err_int). */
+#else
+	uint64_t aeri                         : 1;
+	uint64_t se                           : 1;
+	uint64_t pmei                         : 1;
+	uint64_t pmem                         : 1;
+	uint64_t up_b1                        : 1;
+	uint64_t up_b2                        : 1;
+	uint64_t up_bx                        : 1;
+	uint64_t un_b1                        : 1;
+	uint64_t un_b2                        : 1;
+	uint64_t un_bx                        : 1;
+	uint64_t exc                          : 1;
+	uint64_t rdlk                         : 1;
+	uint64_t crs_er                       : 1;
+	uint64_t crs_dr                       : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_pemx_int_sum_s            cn63xx;
+	struct cvmx_pemx_int_sum_s            cn63xxp1;
+};
+typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
+
+/**
+ * cvmx_pem#_p2n_bar0_start
+ *
+ * PEM_P2N_BAR0_START = PEM PCIe to Npei BAR0 Start
+ *
+ * The starting address for addresses to forwarded to the SLI in RC Mode.
+ */
+union cvmx_pemx_p2n_bar0_start
+{
+	uint64_t u64;
+	struct cvmx_pemx_p2n_bar0_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 50; /**< The starting address of the 16KB address space that
+                                                         is the BAR0 address space. */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t addr                         : 50;
+#endif
+	} s;
+	struct cvmx_pemx_p2n_bar0_start_s     cn63xx;
+	struct cvmx_pemx_p2n_bar0_start_s     cn63xxp1;
+};
+typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
+
+/**
+ * cvmx_pem#_p2n_bar1_start
+ *
+ * PEM_P2N_BAR1_START = PEM PCIe to Npei BAR1 Start
+ *
+ * The starting address for addresses to forwarded to the SLI in RC Mode.
+ */
+union cvmx_pemx_p2n_bar1_start
+{
+	uint64_t u64;
+	struct cvmx_pemx_p2n_bar1_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 38; /**< The starting address of the 64KB address space
+                                                         that is the BAR1 address space. */
+	uint64_t reserved_0_25                : 26;
+#else
+	uint64_t reserved_0_25                : 26;
+	uint64_t addr                         : 38;
+#endif
+	} s;
+	struct cvmx_pemx_p2n_bar1_start_s     cn63xx;
+	struct cvmx_pemx_p2n_bar1_start_s     cn63xxp1;
+};
+typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
+
+/**
+ * cvmx_pem#_p2n_bar2_start
+ *
+ * PEM_P2N_BAR2_START = PEM PCIe to Npei BAR2 Start
+ *
+ * The starting address for addresses to forwarded to the SLI in RC Mode.
+ */
+union cvmx_pemx_p2n_bar2_start
+{
+	uint64_t u64;
+	struct cvmx_pemx_p2n_bar2_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 23; /**< The starting address of the 2^41 address space
+                                                         that is the BAR2 address space. */
+	uint64_t reserved_0_40                : 41;
+#else
+	uint64_t reserved_0_40                : 41;
+	uint64_t addr                         : 23;
+#endif
+	} s;
+	struct cvmx_pemx_p2n_bar2_start_s     cn63xx;
+	struct cvmx_pemx_p2n_bar2_start_s     cn63xxp1;
+};
+typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
+
+/**
+ * cvmx_pem#_p2p_bar#_end
+ *
+ * PEM_P2P_BAR#_END = PEM Peer-To-Peer BAR0 End
+ *
+ * The ending address for addresses to forwarded to the PCIe peer port.
+ */
+union cvmx_pemx_p2p_barx_end
+{
+	uint64_t u64;
+	struct cvmx_pemx_p2p_barx_end_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 52; /**< The ending address of the address window created
+                                                         this field and the PEM_P2P_BAR0_START[63:12]
+                                                         field. The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t addr                         : 52;
+#endif
+	} s;
+	struct cvmx_pemx_p2p_barx_end_s       cn63xx;
+	struct cvmx_pemx_p2p_barx_end_s       cn63xxp1;
+};
+typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
+
+/**
+ * cvmx_pem#_p2p_bar#_start
+ *
+ * PEM_P2P_BAR#_START = PEM Peer-To-Peer BAR0 Start
+ *
+ * The starting address and enable for addresses to forwarded to the PCIe peer port.
+ */
+union cvmx_pemx_p2p_barx_start
+{
+	uint64_t u64;
+	struct cvmx_pemx_p2p_barx_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 52; /**< The starting address of the address window created
+                                                         by this field and the PEM_P2P_BAR0_END[63:12]
+                                                         field. The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t addr                         : 52;
+#endif
+	} s;
+	struct cvmx_pemx_p2p_barx_start_s     cn63xx;
+	struct cvmx_pemx_p2p_barx_start_s     cn63xxp1;
+};
+typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
+
+/**
+ * cvmx_pem#_tlp_credits
+ *
+ * PEM_TLP_CREDITS = PEM TLP Credits
+ *
+ * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are
+ * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
+ */
+union cvmx_pemx_tlp_credits
+{
+	uint64_t u64;
+	struct cvmx_pemx_tlp_credits_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t peai_ppf                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t pem_cpl                      : 8;  /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t pem_np                       : 8;  /**< TLP credits for Non-Posted TLPs in the Peer.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t pem_p                        : 8;  /**< TLP credits for Posted TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t sli_cpl                      : 8;  /**< TLP credits for Completion TLPs in the SLI.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t sli_np                       : 8;  /**< TLP credits for Non-Posted TLPs in the SLI.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t sli_p                        : 8;  /**< TLP credits for Posted TLPs in the SLI.
+                                                         Legal values are 0x24 to 0x80. */
+#else
+	uint64_t sli_p                        : 8;
+	uint64_t sli_np                       : 8;
+	uint64_t sli_cpl                      : 8;
+	uint64_t pem_p                        : 8;
+	uint64_t pem_np                       : 8;
+	uint64_t pem_cpl                      : 8;
+	uint64_t peai_ppf                     : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_pemx_tlp_credits_s        cn63xx;
+	struct cvmx_pemx_tlp_credits_s        cn63xxp1;
+};
+typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pescx-defs.h b/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
new file mode 100644
index 0000000..0f9b4e3
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
@@ -0,0 +1,1092 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pescx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pescx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PESCX_TYPEDEFS_H__
+#define __CVMX_PESCX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16;
+}
+#else
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16;
+}
+#else
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_pesc#_bist_status
+ *
+ * PESC_BIST_STATUS = PESC Bist Status
+ *
+ * Contains the diffrent interrupt summary bits of the PESC.
+ */
+union cvmx_pescx_bist_status
+{
+	uint64_t u64;
+	struct cvmx_pescx_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t rqdata5                      : 1;  /**< Rx Queue Data Memory5. */
+	uint64_t ctlp_or                      : 1;  /**< C-TLP Order Fifo. */
+	uint64_t ntlp_or                      : 1;  /**< N-TLP Order Fifo. */
+	uint64_t ptlp_or                      : 1;  /**< P-TLP Order Fifo. */
+	uint64_t retry                        : 1;  /**< Retry Buffer. */
+	uint64_t rqdata0                      : 1;  /**< Rx Queue Data Memory0. */
+	uint64_t rqdata1                      : 1;  /**< Rx Queue Data Memory1. */
+	uint64_t rqdata2                      : 1;  /**< Rx Queue Data Memory2. */
+	uint64_t rqdata3                      : 1;  /**< Rx Queue Data Memory3. */
+	uint64_t rqdata4                      : 1;  /**< Rx Queue Data Memory4. */
+	uint64_t rqhdr1                       : 1;  /**< Rx Queue Header1. */
+	uint64_t rqhdr0                       : 1;  /**< Rx Queue Header0. */
+	uint64_t sot                          : 1;  /**< SOT Buffer. */
+#else
+	uint64_t sot                          : 1;
+	uint64_t rqhdr0                       : 1;
+	uint64_t rqhdr1                       : 1;
+	uint64_t rqdata4                      : 1;
+	uint64_t rqdata3                      : 1;
+	uint64_t rqdata2                      : 1;
+	uint64_t rqdata1                      : 1;
+	uint64_t rqdata0                      : 1;
+	uint64_t retry                        : 1;
+	uint64_t ptlp_or                      : 1;
+	uint64_t ntlp_or                      : 1;
+	uint64_t ctlp_or                      : 1;
+	uint64_t rqdata5                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pescx_bist_status_s       cn52xx;
+	struct cvmx_pescx_bist_status_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t ctlp_or                      : 1;  /**< C-TLP Order Fifo. */
+	uint64_t ntlp_or                      : 1;  /**< N-TLP Order Fifo. */
+	uint64_t ptlp_or                      : 1;  /**< P-TLP Order Fifo. */
+	uint64_t retry                        : 1;  /**< Retry Buffer. */
+	uint64_t rqdata0                      : 1;  /**< Rx Queue Data Memory0. */
+	uint64_t rqdata1                      : 1;  /**< Rx Queue Data Memory1. */
+	uint64_t rqdata2                      : 1;  /**< Rx Queue Data Memory2. */
+	uint64_t rqdata3                      : 1;  /**< Rx Queue Data Memory3. */
+	uint64_t rqdata4                      : 1;  /**< Rx Queue Data Memory4. */
+	uint64_t rqhdr1                       : 1;  /**< Rx Queue Header1. */
+	uint64_t rqhdr0                       : 1;  /**< Rx Queue Header0. */
+	uint64_t sot                          : 1;  /**< SOT Buffer. */
+#else
+	uint64_t sot                          : 1;
+	uint64_t rqhdr0                       : 1;
+	uint64_t rqhdr1                       : 1;
+	uint64_t rqdata4                      : 1;
+	uint64_t rqdata3                      : 1;
+	uint64_t rqdata2                      : 1;
+	uint64_t rqdata1                      : 1;
+	uint64_t rqdata0                      : 1;
+	uint64_t retry                        : 1;
+	uint64_t ptlp_or                      : 1;
+	uint64_t ntlp_or                      : 1;
+	uint64_t ctlp_or                      : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn52xxp1;
+	struct cvmx_pescx_bist_status_s       cn56xx;
+	struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
+};
+typedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t;
+
+/**
+ * cvmx_pesc#_bist_status2
+ *
+ * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
+ *
+ * Results from BIST runs of PESC's memories.
+ */
+union cvmx_pescx_bist_status2
+{
+	uint64_t u64;
+	struct cvmx_pescx_bist_status2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t cto_p2e                      : 1;  /**< BIST Status for the cto_p2e_fifo */
+	uint64_t e2p_cpl                      : 1;  /**< BIST Status for the e2p_cpl_fifo */
+	uint64_t e2p_n                        : 1;  /**< BIST Status for the e2p_n_fifo */
+	uint64_t e2p_p                        : 1;  /**< BIST Status for the e2p_p_fifo */
+	uint64_t e2p_rsl                      : 1;  /**< BIST Status for the e2p_rsl__fifo */
+	uint64_t dbg_p2e                      : 1;  /**< BIST Status for the dbg_p2e_fifo */
+	uint64_t peai_p2e                     : 1;  /**< BIST Status for the peai__pesc_fifo */
+	uint64_t rsl_p2e                      : 1;  /**< BIST Status for the rsl_p2e_fifo */
+	uint64_t pef_tpf1                     : 1;  /**< BIST Status for the pef_tlp_p_fifo1 */
+	uint64_t pef_tpf0                     : 1;  /**< BIST Status for the pef_tlp_p_fifo0 */
+	uint64_t pef_tnf                      : 1;  /**< BIST Status for the pef_tlp_n_fifo */
+	uint64_t pef_tcf1                     : 1;  /**< BIST Status for the pef_tlp_cpl_fifo1 */
+	uint64_t pef_tc0                      : 1;  /**< BIST Status for the pef_tlp_cpl_fifo0 */
+	uint64_t ppf                          : 1;  /**< BIST Status for the ppf_fifo */
+#else
+	uint64_t ppf                          : 1;
+	uint64_t pef_tc0                      : 1;
+	uint64_t pef_tcf1                     : 1;
+	uint64_t pef_tnf                      : 1;
+	uint64_t pef_tpf0                     : 1;
+	uint64_t pef_tpf1                     : 1;
+	uint64_t rsl_p2e                      : 1;
+	uint64_t peai_p2e                     : 1;
+	uint64_t dbg_p2e                      : 1;
+	uint64_t e2p_rsl                      : 1;
+	uint64_t e2p_p                        : 1;
+	uint64_t e2p_n                        : 1;
+	uint64_t e2p_cpl                      : 1;
+	uint64_t cto_p2e                      : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_pescx_bist_status2_s      cn52xx;
+	struct cvmx_pescx_bist_status2_s      cn52xxp1;
+	struct cvmx_pescx_bist_status2_s      cn56xx;
+	struct cvmx_pescx_bist_status2_s      cn56xxp1;
+};
+typedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t;
+
+/**
+ * cvmx_pesc#_cfg_rd
+ *
+ * PESC_CFG_RD = PESC Configuration Read
+ *
+ * Allows read access to the configuration in the PCIe Core.
+ */
+union cvmx_pescx_cfg_rd
+{
+	uint64_t u64;
+	struct cvmx_pescx_cfg_rd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 32; /**< Data. */
+	uint64_t addr                         : 32; /**< Address to read. A write to this register
+                                                         starts a read operation. */
+#else
+	uint64_t addr                         : 32;
+	uint64_t data                         : 32;
+#endif
+	} s;
+	struct cvmx_pescx_cfg_rd_s            cn52xx;
+	struct cvmx_pescx_cfg_rd_s            cn52xxp1;
+	struct cvmx_pescx_cfg_rd_s            cn56xx;
+	struct cvmx_pescx_cfg_rd_s            cn56xxp1;
+};
+typedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t;
+
+/**
+ * cvmx_pesc#_cfg_wr
+ *
+ * PESC_CFG_WR = PESC Configuration Write
+ *
+ * Allows write access to the configuration in the PCIe Core.
+ */
+union cvmx_pescx_cfg_wr
+{
+	uint64_t u64;
+	struct cvmx_pescx_cfg_wr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 32; /**< Data to write. A write to this register starts
+                                                         a write operation. */
+	uint64_t addr                         : 32; /**< Address to write. A write to this register starts
+                                                         a write operation. */
+#else
+	uint64_t addr                         : 32;
+	uint64_t data                         : 32;
+#endif
+	} s;
+	struct cvmx_pescx_cfg_wr_s            cn52xx;
+	struct cvmx_pescx_cfg_wr_s            cn52xxp1;
+	struct cvmx_pescx_cfg_wr_s            cn56xx;
+	struct cvmx_pescx_cfg_wr_s            cn56xxp1;
+};
+typedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t;
+
+/**
+ * cvmx_pesc#_cpl_lut_valid
+ *
+ * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid
+ *
+ * Bit set for outstanding tag read.
+ */
+union cvmx_pescx_cpl_lut_valid
+{
+	uint64_t u64;
+	struct cvmx_pescx_cpl_lut_valid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t tag                          : 32; /**< Bit vector set cooresponds to an outstanding tag
+                                                         expecting a completion. */
+#else
+	uint64_t tag                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pescx_cpl_lut_valid_s     cn52xx;
+	struct cvmx_pescx_cpl_lut_valid_s     cn52xxp1;
+	struct cvmx_pescx_cpl_lut_valid_s     cn56xx;
+	struct cvmx_pescx_cpl_lut_valid_s     cn56xxp1;
+};
+typedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t;
+
+/**
+ * cvmx_pesc#_ctl_status
+ *
+ * PESC_CTL_STATUS = PESC Control Status
+ *
+ * General control and status of the PESC.
+ */
+union cvmx_pescx_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_pescx_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t dnum                         : 5;  /**< Primary bus device number. */
+	uint64_t pbus                         : 8;  /**< Primary bus number. */
+	uint64_t qlm_cfg                      : 2;  /**< The QLM configuration pad bits. */
+	uint64_t lane_swp                     : 1;  /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1'
+                                                         enables LANE SWAP. THis bit has no effect on PEDC0.
+                                                         This bit should be set before enabling PEDC1. */
+	uint64_t pm_xtoff                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
+	uint64_t pm_xpme                      : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_pme port. EP mode. */
+	uint64_t ob_p_cmd                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t nf_ecrc                      : 1;  /**< Do not forward peer-to-peer ECRC TLPs. */
+	uint64_t dly_one                      : 1;  /**< When set the output client state machines will
+                                                         wait one cycle before starting a new TLP out. */
+	uint64_t lnk_enb                      : 1;  /**< When set '1' the link is enabled when '0' the
+                                                         link is disabled. This bit only is active when in
+                                                         RC mode. */
+	uint64_t ro_ctlp                      : 1;  /**< When set '1' C-TLPs that have the RO bit set will
+                                                         not wait for P-TLPs that normaly would be sent
+                                                         first. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t inv_ecrc                     : 1;  /**< When '1' causes the LSB of the ECRC to be inverted. */
+	uint64_t inv_lcrc                     : 1;  /**< When '1' causes the LSB of the LCRC to be inverted. */
+#else
+	uint64_t inv_lcrc                     : 1;
+	uint64_t inv_ecrc                     : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ro_ctlp                      : 1;
+	uint64_t lnk_enb                      : 1;
+	uint64_t dly_one                      : 1;
+	uint64_t nf_ecrc                      : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t ob_p_cmd                     : 1;
+	uint64_t pm_xpme                      : 1;
+	uint64_t pm_xtoff                     : 1;
+	uint64_t lane_swp                     : 1;
+	uint64_t qlm_cfg                      : 2;
+	uint64_t pbus                         : 8;
+	uint64_t dnum                         : 5;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_pescx_ctl_status_s        cn52xx;
+	struct cvmx_pescx_ctl_status_s        cn52xxp1;
+	struct cvmx_pescx_ctl_status_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t dnum                         : 5;  /**< Primary bus device number. */
+	uint64_t pbus                         : 8;  /**< Primary bus number. */
+	uint64_t qlm_cfg                      : 2;  /**< The QLM configuration pad bits. */
+	uint64_t reserved_12_12               : 1;
+	uint64_t pm_xtoff                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
+	uint64_t pm_xpme                      : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_pme port. EP mode. */
+	uint64_t ob_p_cmd                     : 1;  /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
+	uint64_t reserved_7_8                 : 2;
+	uint64_t nf_ecrc                      : 1;  /**< Do not forward peer-to-peer ECRC TLPs. */
+	uint64_t dly_one                      : 1;  /**< When set the output client state machines will
+                                                         wait one cycle before starting a new TLP out. */
+	uint64_t lnk_enb                      : 1;  /**< When set '1' the link is enabled when '0' the
+                                                         link is disabled. This bit only is active when in
+                                                         RC mode. */
+	uint64_t ro_ctlp                      : 1;  /**< When set '1' C-TLPs that have the RO bit set will
+                                                         not wait for P-TLPs that normaly would be sent
+                                                         first. */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t inv_ecrc                     : 1;  /**< When '1' causes the LSB of the ECRC to be inverted. */
+	uint64_t inv_lcrc                     : 1;  /**< When '1' causes the LSB of the LCRC to be inverted. */
+#else
+	uint64_t inv_lcrc                     : 1;
+	uint64_t inv_ecrc                     : 1;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t ro_ctlp                      : 1;
+	uint64_t lnk_enb                      : 1;
+	uint64_t dly_one                      : 1;
+	uint64_t nf_ecrc                      : 1;
+	uint64_t reserved_7_8                 : 2;
+	uint64_t ob_p_cmd                     : 1;
+	uint64_t pm_xpme                      : 1;
+	uint64_t pm_xtoff                     : 1;
+	uint64_t reserved_12_12               : 1;
+	uint64_t qlm_cfg                      : 2;
+	uint64_t pbus                         : 8;
+	uint64_t dnum                         : 5;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn56xx;
+	struct cvmx_pescx_ctl_status_cn56xx   cn56xxp1;
+};
+typedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t;
+
+/**
+ * cvmx_pesc#_ctl_status2
+ *
+ * Below are in PESC
+ *
+ *                  PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
+ *
+ * Results from BIST runs of PESC's memories.
+ */
+union cvmx_pescx_ctl_status2
+{
+	uint64_t u64;
+	struct cvmx_pescx_ctl_status2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t pclk_run                     : 1;  /**< When the pce_clk is running this bit will be '1'.
+                                                         Writing a '1' to this location will cause the
+                                                         bit to be cleared, but if the pce_clk is running
+                                                         this bit will be re-set. */
+	uint64_t pcierst                      : 1;  /**< Set to '1' when PCIe is in reset. */
+#else
+	uint64_t pcierst                      : 1;
+	uint64_t pclk_run                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pescx_ctl_status2_s       cn52xx;
+	struct cvmx_pescx_ctl_status2_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t pcierst                      : 1;  /**< Set to '1' when PCIe is in reset. */
+#else
+	uint64_t pcierst                      : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn52xxp1;
+	struct cvmx_pescx_ctl_status2_s       cn56xx;
+	struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
+};
+typedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t;
+
+/**
+ * cvmx_pesc#_dbg_info
+ *
+ * PESC(0..1)_DBG_INFO = PESC Debug Information
+ *
+ * General debug info.
+ */
+union cvmx_pescx_dbg_info
+{
+	uint64_t u64;
+	struct cvmx_pescx_dbg_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t ecrc_e                       : 1;  /**< Received a ECRC error.
+                                                         radm_ecrc_err */
+	uint64_t rawwpp                       : 1;  /**< Received a write with poisoned payload
+                                                         radm_rcvd_wreq_poisoned */
+	uint64_t racpp                        : 1;  /**< Received a completion with poisoned payload
+                                                         radm_rcvd_cpl_poisoned */
+	uint64_t ramtlp                       : 1;  /**< Received a malformed TLP
+                                                         radm_mlf_tlp_err */
+	uint64_t rarwdns                      : 1;  /**< Recieved a request which device does not support
+                                                         radm_rcvd_ur_req */
+	uint64_t caar                         : 1;  /**< Completer aborted a request
+                                                         radm_rcvd_ca_req
+                                                         This bit will never be set because Octeon does
+                                                         not generate Completer Aborts. */
+	uint64_t racca                        : 1;  /**< Received a completion with CA status
+                                                         radm_rcvd_cpl_ca */
+	uint64_t racur                        : 1;  /**< Received a completion with UR status
+                                                         radm_rcvd_cpl_ur */
+	uint64_t rauc                         : 1;  /**< Received an unexpected completion
+                                                         radm_unexp_cpl_err */
+	uint64_t rqo                          : 1;  /**< Receive queue overflow. Normally happens only when
+                                                         flow control advertisements are ignored
+                                                         radm_qoverflow */
+	uint64_t fcuv                         : 1;  /**< Flow Control Update Violation (opt. checks)
+                                                         int_xadm_fc_prot_err */
+	uint64_t rpe                          : 1;  /**< When the PHY reports 8B/10B decode error
+                                                         (RxStatus = 3b100) or disparity error
+                                                         (RxStatus = 3b111), the signal rmlh_rcvd_err will
+                                                         be asserted.
+                                                         rmlh_rcvd_err */
+	uint64_t fcpvwt                       : 1;  /**< Flow Control Protocol Violation (Watchdog Timer)
+                                                         rtlh_fc_prot_err */
+	uint64_t dpeoosd                      : 1;  /**< DLLP protocol error (out of sequence DLLP)
+                                                         rdlh_prot_err */
+	uint64_t rtwdle                       : 1;  /**< Received TLP with DataLink Layer Error
+                                                         rdlh_bad_tlp_err */
+	uint64_t rdwdle                       : 1;  /**< Received DLLP with DataLink Layer Error
+                                                         rdlh_bad_dllp_err */
+	uint64_t mre                          : 1;  /**< Max Retries Exceeded
+                                                         xdlh_replay_num_rlover_err */
+	uint64_t rte                          : 1;  /**< Replay Timer Expired
+                                                         xdlh_replay_timeout_err
+                                                         This bit is set when the REPLAY_TIMER expires in
+                                                         the PCIE core. The probability of this bit being
+                                                         set will increase with the traffic load. */
+	uint64_t acto                         : 1;  /**< A Completion Timeout Occured
+                                                         pedc_radm_cpl_timeout */
+	uint64_t rvdm                         : 1;  /**< Received Vendor-Defined Message
+                                                         pedc_radm_vendor_msg */
+	uint64_t rumep                        : 1;  /**< Received Unlock Message (EP Mode Only)
+                                                         pedc_radm_msg_unlock */
+	uint64_t rptamrc                      : 1;  /**< Received PME Turnoff Acknowledge Message
+                                                         (RC Mode only)
+                                                         pedc_radm_pm_to_ack */
+	uint64_t rpmerc                       : 1;  /**< Received PME Message (RC Mode only)
+                                                         pedc_radm_pm_pme */
+	uint64_t rfemrc                       : 1;  /**< Received Fatal Error Message (RC Mode only)
+                                                         pedc_radm_fatal_err
+                                                         Bit set when a message with ERR_FATAL is set. */
+	uint64_t rnfemrc                      : 1;  /**< Received Non-Fatal Error Message (RC Mode only)
+                                                         pedc_radm_nonfatal_err */
+	uint64_t rcemrc                       : 1;  /**< Received Correctable Error Message (RC Mode only)
+                                                         pedc_radm_correctable_err */
+	uint64_t rpoison                      : 1;  /**< Received Poisoned TLP
+                                                         pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
+	uint64_t recrce                       : 1;  /**< Received ECRC Error
+                                                         pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
+	uint64_t rtlplle                      : 1;  /**< Received TLP has link layer error
+                                                         pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
+	uint64_t rtlpmal                      : 1;  /**< Received TLP is malformed or a message.
+                                                         pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
+                                                         If the core receives a MSG (or Vendor Message)
+                                                         this bit will be set. */
+	uint64_t spoison                      : 1;  /**< Poisoned TLP sent
+                                                         peai__client0_tlp_ep & peai__client0_tlp_hv */
+#else
+	uint64_t spoison                      : 1;
+	uint64_t rtlpmal                      : 1;
+	uint64_t rtlplle                      : 1;
+	uint64_t recrce                       : 1;
+	uint64_t rpoison                      : 1;
+	uint64_t rcemrc                       : 1;
+	uint64_t rnfemrc                      : 1;
+	uint64_t rfemrc                       : 1;
+	uint64_t rpmerc                       : 1;
+	uint64_t rptamrc                      : 1;
+	uint64_t rumep                        : 1;
+	uint64_t rvdm                         : 1;
+	uint64_t acto                         : 1;
+	uint64_t rte                          : 1;
+	uint64_t mre                          : 1;
+	uint64_t rdwdle                       : 1;
+	uint64_t rtwdle                       : 1;
+	uint64_t dpeoosd                      : 1;
+	uint64_t fcpvwt                       : 1;
+	uint64_t rpe                          : 1;
+	uint64_t fcuv                         : 1;
+	uint64_t rqo                          : 1;
+	uint64_t rauc                         : 1;
+	uint64_t racur                        : 1;
+	uint64_t racca                        : 1;
+	uint64_t caar                         : 1;
+	uint64_t rarwdns                      : 1;
+	uint64_t ramtlp                       : 1;
+	uint64_t racpp                        : 1;
+	uint64_t rawwpp                       : 1;
+	uint64_t ecrc_e                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_pescx_dbg_info_s          cn52xx;
+	struct cvmx_pescx_dbg_info_s          cn52xxp1;
+	struct cvmx_pescx_dbg_info_s          cn56xx;
+	struct cvmx_pescx_dbg_info_s          cn56xxp1;
+};
+typedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t;
+
+/**
+ * cvmx_pesc#_dbg_info_en
+ *
+ * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable
+ *
+ * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set.
+ */
+union cvmx_pescx_dbg_info_en
+{
+	uint64_t u64;
+	struct cvmx_pescx_dbg_info_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t ecrc_e                       : 1;  /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */
+	uint64_t rawwpp                       : 1;  /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */
+	uint64_t racpp                        : 1;  /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */
+	uint64_t ramtlp                       : 1;  /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */
+	uint64_t rarwdns                      : 1;  /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */
+	uint64_t caar                         : 1;  /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */
+	uint64_t racca                        : 1;  /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */
+	uint64_t racur                        : 1;  /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */
+	uint64_t rauc                         : 1;  /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */
+	uint64_t rqo                          : 1;  /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */
+	uint64_t fcuv                         : 1;  /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */
+	uint64_t rpe                          : 1;  /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */
+	uint64_t fcpvwt                       : 1;  /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */
+	uint64_t dpeoosd                      : 1;  /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */
+	uint64_t rtwdle                       : 1;  /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */
+	uint64_t rdwdle                       : 1;  /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */
+	uint64_t mre                          : 1;  /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */
+	uint64_t rte                          : 1;  /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */
+	uint64_t acto                         : 1;  /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */
+	uint64_t rvdm                         : 1;  /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */
+	uint64_t rumep                        : 1;  /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */
+	uint64_t rptamrc                      : 1;  /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */
+	uint64_t rpmerc                       : 1;  /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */
+	uint64_t rfemrc                       : 1;  /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */
+	uint64_t rnfemrc                      : 1;  /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */
+	uint64_t rcemrc                       : 1;  /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */
+	uint64_t rpoison                      : 1;  /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */
+	uint64_t recrce                       : 1;  /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */
+	uint64_t rtlplle                      : 1;  /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */
+	uint64_t rtlpmal                      : 1;  /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */
+	uint64_t spoison                      : 1;  /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */
+#else
+	uint64_t spoison                      : 1;
+	uint64_t rtlpmal                      : 1;
+	uint64_t rtlplle                      : 1;
+	uint64_t recrce                       : 1;
+	uint64_t rpoison                      : 1;
+	uint64_t rcemrc                       : 1;
+	uint64_t rnfemrc                      : 1;
+	uint64_t rfemrc                       : 1;
+	uint64_t rpmerc                       : 1;
+	uint64_t rptamrc                      : 1;
+	uint64_t rumep                        : 1;
+	uint64_t rvdm                         : 1;
+	uint64_t acto                         : 1;
+	uint64_t rte                          : 1;
+	uint64_t mre                          : 1;
+	uint64_t rdwdle                       : 1;
+	uint64_t rtwdle                       : 1;
+	uint64_t dpeoosd                      : 1;
+	uint64_t fcpvwt                       : 1;
+	uint64_t rpe                          : 1;
+	uint64_t fcuv                         : 1;
+	uint64_t rqo                          : 1;
+	uint64_t rauc                         : 1;
+	uint64_t racur                        : 1;
+	uint64_t racca                        : 1;
+	uint64_t caar                         : 1;
+	uint64_t rarwdns                      : 1;
+	uint64_t ramtlp                       : 1;
+	uint64_t racpp                        : 1;
+	uint64_t rawwpp                       : 1;
+	uint64_t ecrc_e                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_pescx_dbg_info_en_s       cn52xx;
+	struct cvmx_pescx_dbg_info_en_s       cn52xxp1;
+	struct cvmx_pescx_dbg_info_en_s       cn56xx;
+	struct cvmx_pescx_dbg_info_en_s       cn56xxp1;
+};
+typedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t;
+
+/**
+ * cvmx_pesc#_diag_status
+ *
+ * PESC_DIAG_STATUS = PESC Diagnostic Status
+ *
+ * Selection control for the cores diagnostic bus.
+ */
+union cvmx_pescx_diag_status
+{
+	uint64_t u64;
+	struct cvmx_pescx_diag_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t pm_dst                       : 1;  /**< Current power management DSTATE. */
+	uint64_t pm_stat                      : 1;  /**< Power Management Status. */
+	uint64_t pm_en                        : 1;  /**< Power Management Event Enable. */
+	uint64_t aux_en                       : 1;  /**< Auxilary Power Enable. */
+#else
+	uint64_t aux_en                       : 1;
+	uint64_t pm_en                        : 1;
+	uint64_t pm_stat                      : 1;
+	uint64_t pm_dst                       : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pescx_diag_status_s       cn52xx;
+	struct cvmx_pescx_diag_status_s       cn52xxp1;
+	struct cvmx_pescx_diag_status_s       cn56xx;
+	struct cvmx_pescx_diag_status_s       cn56xxp1;
+};
+typedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t;
+
+/**
+ * cvmx_pesc#_p2n_bar0_start
+ *
+ * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start
+ *
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+union cvmx_pescx_p2n_bar0_start
+{
+	uint64_t u64;
+	struct cvmx_pescx_p2n_bar0_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 50; /**< The starting address of the 16KB address space that
+                                                         is the BAR0 address space. */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t addr                         : 50;
+#endif
+	} s;
+	struct cvmx_pescx_p2n_bar0_start_s    cn52xx;
+	struct cvmx_pescx_p2n_bar0_start_s    cn52xxp1;
+	struct cvmx_pescx_p2n_bar0_start_s    cn56xx;
+	struct cvmx_pescx_p2n_bar0_start_s    cn56xxp1;
+};
+typedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t;
+
+/**
+ * cvmx_pesc#_p2n_bar1_start
+ *
+ * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start
+ *
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+union cvmx_pescx_p2n_bar1_start
+{
+	uint64_t u64;
+	struct cvmx_pescx_p2n_bar1_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 38; /**< The starting address of the 64KB address space
+                                                         that is the BAR1 address space. */
+	uint64_t reserved_0_25                : 26;
+#else
+	uint64_t reserved_0_25                : 26;
+	uint64_t addr                         : 38;
+#endif
+	} s;
+	struct cvmx_pescx_p2n_bar1_start_s    cn52xx;
+	struct cvmx_pescx_p2n_bar1_start_s    cn52xxp1;
+	struct cvmx_pescx_p2n_bar1_start_s    cn56xx;
+	struct cvmx_pescx_p2n_bar1_start_s    cn56xxp1;
+};
+typedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t;
+
+/**
+ * cvmx_pesc#_p2n_bar2_start
+ *
+ * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start
+ *
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+union cvmx_pescx_p2n_bar2_start
+{
+	uint64_t u64;
+	struct cvmx_pescx_p2n_bar2_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 25; /**< The starting address of the 2^39 address space
+                                                         that is the BAR2 address space. */
+	uint64_t reserved_0_38                : 39;
+#else
+	uint64_t reserved_0_38                : 39;
+	uint64_t addr                         : 25;
+#endif
+	} s;
+	struct cvmx_pescx_p2n_bar2_start_s    cn52xx;
+	struct cvmx_pescx_p2n_bar2_start_s    cn52xxp1;
+	struct cvmx_pescx_p2n_bar2_start_s    cn56xx;
+	struct cvmx_pescx_p2n_bar2_start_s    cn56xxp1;
+};
+typedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t;
+
+/**
+ * cvmx_pesc#_p2p_bar#_end
+ *
+ * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End
+ *
+ * The ending address for addresses to forwarded to the PCIe peer port.
+ */
+union cvmx_pescx_p2p_barx_end
+{
+	uint64_t u64;
+	struct cvmx_pescx_p2p_barx_end_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 52; /**< The ending address of the address window created
+                                                         this field and the PESC_P2P_BAR0_START[63:12]
+                                                         field. The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t addr                         : 52;
+#endif
+	} s;
+	struct cvmx_pescx_p2p_barx_end_s      cn52xx;
+	struct cvmx_pescx_p2p_barx_end_s      cn52xxp1;
+	struct cvmx_pescx_p2p_barx_end_s      cn56xx;
+	struct cvmx_pescx_p2p_barx_end_s      cn56xxp1;
+};
+typedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t;
+
+/**
+ * cvmx_pesc#_p2p_bar#_start
+ *
+ * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start
+ *
+ * The starting address and enable for addresses to forwarded to the PCIe peer port.
+ */
+union cvmx_pescx_p2p_barx_start
+{
+	uint64_t u64;
+	struct cvmx_pescx_p2p_barx_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 52; /**< The starting address of the address window created
+                                                         this field and the PESC_P2P_BAR0_END[63:12] field.
+                                                         The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t addr                         : 52;
+#endif
+	} s;
+	struct cvmx_pescx_p2p_barx_start_s    cn52xx;
+	struct cvmx_pescx_p2p_barx_start_s    cn52xxp1;
+	struct cvmx_pescx_p2p_barx_start_s    cn56xx;
+	struct cvmx_pescx_p2p_barx_start_s    cn56xxp1;
+};
+typedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t;
+
+/**
+ * cvmx_pesc#_tlp_credits
+ *
+ * PESC_TLP_CREDITS = PESC TLP Credits
+ *
+ * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are
+ * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
+ */
+union cvmx_pescx_tlp_credits
+{
+	uint64_t u64;
+	struct cvmx_pescx_tlp_credits_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pescx_tlp_credits_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t peai_ppf                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t pesc_cpl                     : 8;  /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t pesc_np                      : 8;  /**< TLP credits for Non-Posted TLPs in the Peer.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t pesc_p                       : 8;  /**< TLP credits for Posted TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t npei_cpl                     : 8;  /**< TLP credits for Completion TLPs in the NPEI.
+                                                         Legal values are 0x24 to 0x80. */
+	uint64_t npei_np                      : 8;  /**< TLP credits for Non-Posted TLPs in the NPEI.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t npei_p                       : 8;  /**< TLP credits for Posted TLPs in the NPEI.
+                                                         Legal values are 0x24 to 0x80. */
+#else
+	uint64_t npei_p                       : 8;
+	uint64_t npei_np                      : 8;
+	uint64_t npei_cpl                     : 8;
+	uint64_t pesc_p                       : 8;
+	uint64_t pesc_np                      : 8;
+	uint64_t pesc_cpl                     : 8;
+	uint64_t peai_ppf                     : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pescx_tlp_credits_cn52xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t peai_ppf                     : 8;  /**< TLP credits in core clk pre-buffer that holds TLPs
+                                                         being sent from PCIe Core to NPEI or PEER. */
+	uint64_t pesc_cpl                     : 5;  /**< TLP credits for Completion TLPs in the Peer. */
+	uint64_t pesc_np                      : 5;  /**< TLP credits for Non-Posted TLPs in the Peer. */
+	uint64_t pesc_p                       : 5;  /**< TLP credits for Posted TLPs in the Peer. */
+	uint64_t npei_cpl                     : 5;  /**< TLP credits for Completion TLPs in the NPEI. */
+	uint64_t npei_np                      : 5;  /**< TLP credits for Non-Posted TLPs in the NPEI. */
+	uint64_t npei_p                       : 5;  /**< TLP credits for Posted TLPs in the NPEI. */
+#else
+	uint64_t npei_p                       : 5;
+	uint64_t npei_np                      : 5;
+	uint64_t npei_cpl                     : 5;
+	uint64_t pesc_p                       : 5;
+	uint64_t pesc_np                      : 5;
+	uint64_t pesc_cpl                     : 5;
+	uint64_t peai_ppf                     : 8;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn52xxp1;
+	struct cvmx_pescx_tlp_credits_cn52xx  cn56xx;
+	struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
+};
+typedef union cvmx_pescx_tlp_credits cvmx_pescx_tlp_credits_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pexp-defs.h b/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
new file mode 100644
index 0000000..75d3153
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
@@ -0,0 +1,2065 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pexp-defs.h
+ *
+ * Configuration and status register (CSR) definitions for
+ * OCTEON PEXP.
+ *
+ * <hr>$Revision$<hr>
+ */
+#ifndef __CVMX_PEXP_DEFS_H__
+#define __CVMX_PEXP_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
+}
+#else
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
+}
+#else
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
+}
+#else
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
+}
+#else
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
+}
+#else
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
+}
+#else
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
+		cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#endif
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#endif
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
+}
+#else
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
+}
+#else
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
+		cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
+}
+#else
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
+}
+#else
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
+}
+#else
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
+}
+#else
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
+}
+#else
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
+}
+#else
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
+}
+#else
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
+}
+#else
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+		cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
+}
+#else
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
+}
+#else
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
+}
+#else
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
+}
+#else
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
+}
+#else
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
+}
+#else
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
+}
+#else
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
+}
+#else
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
+}
+#else
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
+}
+#else
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
+}
+#else
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
+}
+#else
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
+		cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
+}
+#else
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
+}
+#else
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
+}
+#else
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
+}
+#else
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
+}
+#else
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
+}
+#else
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
+}
+#else
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
+}
+#else
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
+}
+#else
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
+}
+#else
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
+}
+#else
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
+}
+#else
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pip-defs.h b/sys/contrib/octeon-sdk/cvmx-pip-defs.h
new file mode 100644
index 0000000..c11038f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pip-defs.h
@@ -0,0 +1,3926 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pip-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pip.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PIP_TYPEDEFS_H__
+#define __CVMX_PIP_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
+static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
+}
+#else
+#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
+#endif
+#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PIP_CLKEN CVMX_PIP_CLKEN_FUNC()
+static inline uint64_t CVMX_PIP_CLKEN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PIP_CLKEN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A0000040ull);
+}
+#else
+#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+		cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8;
+}
+#else
+#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
+}
+#else
+#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
+}
+#else
+#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0)))))
+		cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
+#endif
+#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
+#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
+static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
+}
+#else
+#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
+#endif
+#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
+#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
+#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
+#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+		cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80;
+}
+#else
+#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
+#endif
+#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32;
+}
+#else
+#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63)))))
+		cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8;
+}
+#else
+#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
+#endif
+#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
+#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
+#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43))))))
+		cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40;
+}
+#else
+#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
+#endif
+
+/**
+ * cvmx_pip_bck_prs
+ *
+ * PIP_BCK_PRS = PIP's Back Pressure Register
+ *
+ * When to assert backpressure based on the todo list filling up
+ */
+union cvmx_pip_bck_prs
+{
+	uint64_t u64;
+	struct cvmx_pip_bck_prs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bckprs                       : 1;  /**< PIP is currently asserting backpressure to IOB
+                                                         Backpressure from PIP will assert when the
+                                                         entries to the todo list exceed HIWATER.
+                                                         Backpressure will be held until the todo entries
+                                                         is less than or equal to LOWATER. */
+	uint64_t reserved_13_62               : 50;
+	uint64_t hiwater                      : 5;  /**< Water mark in the todo list to assert backpressure
+                                                         Legal values are 1-26.  A 0 value will deadlock
+                                                         the machine.  A value > 26, will trash memory */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t lowater                      : 5;  /**< Water mark in the todo list to release backpressure
+                                                         The LOWATER value should be < HIWATER. */
+#else
+	uint64_t lowater                      : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t hiwater                      : 5;
+	uint64_t reserved_13_62               : 50;
+	uint64_t bckprs                       : 1;
+#endif
+	} s;
+	struct cvmx_pip_bck_prs_s             cn38xx;
+	struct cvmx_pip_bck_prs_s             cn38xxp2;
+	struct cvmx_pip_bck_prs_s             cn56xx;
+	struct cvmx_pip_bck_prs_s             cn56xxp1;
+	struct cvmx_pip_bck_prs_s             cn58xx;
+	struct cvmx_pip_bck_prs_s             cn58xxp1;
+	struct cvmx_pip_bck_prs_s             cn63xx;
+	struct cvmx_pip_bck_prs_s             cn63xxp1;
+};
+typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t;
+
+/**
+ * cvmx_pip_bist_status
+ *
+ * PIP_BIST_STATUS = PIP's BIST Results
+ *
+ */
+union cvmx_pip_bist_status
+{
+	uint64_t u64;
+	struct cvmx_pip_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t bist                         : 18; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 18;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_pip_bist_status_s         cn30xx;
+	struct cvmx_pip_bist_status_s         cn31xx;
+	struct cvmx_pip_bist_status_s         cn38xx;
+	struct cvmx_pip_bist_status_s         cn38xxp2;
+	struct cvmx_pip_bist_status_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t bist                         : 17; /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+	uint64_t bist                         : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn50xx;
+	struct cvmx_pip_bist_status_s         cn52xx;
+	struct cvmx_pip_bist_status_s         cn52xxp1;
+	struct cvmx_pip_bist_status_s         cn56xx;
+	struct cvmx_pip_bist_status_s         cn56xxp1;
+	struct cvmx_pip_bist_status_s         cn58xx;
+	struct cvmx_pip_bist_status_s         cn58xxp1;
+	struct cvmx_pip_bist_status_s         cn63xx;
+	struct cvmx_pip_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_pip_bist_status cvmx_pip_bist_status_t;
+
+/**
+ * cvmx_pip_clken
+ */
+union cvmx_pip_clken
+{
+	uint64_t u64;
+	struct cvmx_pip_clken_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t clken                        : 1;  /**< Controls the conditional clocking within PIP
+                                                         0=Allow HW to control the clocks
+                                                         1=Force the clocks to be always on */
+#else
+	uint64_t clken                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_pip_clken_s               cn63xx;
+	struct cvmx_pip_clken_s               cn63xxp1;
+};
+typedef union cvmx_pip_clken cvmx_pip_clken_t;
+
+/**
+ * cvmx_pip_crc_ctl#
+ *
+ * PIP_CRC_CTL = PIP CRC Control Register
+ *
+ * Controls datapath reflection when calculating CRC
+ */
+union cvmx_pip_crc_ctlx
+{
+	uint64_t u64;
+	struct cvmx_pip_crc_ctlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t invres                       : 1;  /**< Invert the result */
+	uint64_t reflect                      : 1;  /**< Reflect the bits in each byte.
+                                                          Byte order does not change.
+                                                         - 0: CRC is calculated MSB to LSB
+                                                         - 1: CRC is calculated LSB to MSB */
+#else
+	uint64_t reflect                      : 1;
+	uint64_t invres                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pip_crc_ctlx_s            cn38xx;
+	struct cvmx_pip_crc_ctlx_s            cn38xxp2;
+	struct cvmx_pip_crc_ctlx_s            cn58xx;
+	struct cvmx_pip_crc_ctlx_s            cn58xxp1;
+};
+typedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t;
+
+/**
+ * cvmx_pip_crc_iv#
+ *
+ * PIP_CRC_IV = PIP CRC IV Register
+ *
+ * Determines the IV used by the CRC algorithm
+ *
+ * Notes:
+ * * PIP_CRC_IV
+ * PIP_CRC_IV controls the initial state of the CRC algorithm.  Octane can
+ * support a wide range of CRC algorithms and as such, the IV must be
+ * carefully constructed to meet the specific algorithm.  The code below
+ * determines the value to program into Octane based on the algorthim's IV
+ * and width.  In the case of Octane, the width should always be 32.
+ *
+ * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for
+ * ports 16-31.
+ *
+ *  unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
+ *  [
+ *    int i;
+ *    int doit;
+ *    unsigned int current_val = algorithm_iv;
+ *
+ *    for(i = 0; i < w; i++) [
+ *      doit = current_val & 0x1;
+ *
+ *      if(doit) current_val ^= poly;
+ *      assert(!(current_val & 0x1));
+ *
+ *      current_val = (current_val >> 1) | (doit << (w-1));
+ *    ]
+ *
+ *    return current_val;
+ *  ]
+ */
+union cvmx_pip_crc_ivx
+{
+	uint64_t u64;
+	struct cvmx_pip_crc_ivx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iv                           : 32; /**< IV used by the CRC algorithm.  Default is FCS32. */
+#else
+	uint64_t iv                           : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pip_crc_ivx_s             cn38xx;
+	struct cvmx_pip_crc_ivx_s             cn38xxp2;
+	struct cvmx_pip_crc_ivx_s             cn58xx;
+	struct cvmx_pip_crc_ivx_s             cn58xxp1;
+};
+typedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t;
+
+/**
+ * cvmx_pip_dec_ipsec#
+ *
+ * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC
+ *
+ * PIP sets the dec_ipsec based on TCP or UDP destination port.
+ */
+union cvmx_pip_dec_ipsecx
+{
+	uint64_t u64;
+	struct cvmx_pip_dec_ipsecx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t tcp                          : 1;  /**< This DPRT should be used for TCP packets */
+	uint64_t udp                          : 1;  /**< This DPRT should be used for UDP packets */
+	uint64_t dprt                         : 16; /**< UDP or TCP destination port to match on */
+#else
+	uint64_t dprt                         : 16;
+	uint64_t udp                          : 1;
+	uint64_t tcp                          : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_pip_dec_ipsecx_s          cn30xx;
+	struct cvmx_pip_dec_ipsecx_s          cn31xx;
+	struct cvmx_pip_dec_ipsecx_s          cn38xx;
+	struct cvmx_pip_dec_ipsecx_s          cn38xxp2;
+	struct cvmx_pip_dec_ipsecx_s          cn50xx;
+	struct cvmx_pip_dec_ipsecx_s          cn52xx;
+	struct cvmx_pip_dec_ipsecx_s          cn52xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cn56xx;
+	struct cvmx_pip_dec_ipsecx_s          cn56xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cn58xx;
+	struct cvmx_pip_dec_ipsecx_s          cn58xxp1;
+	struct cvmx_pip_dec_ipsecx_s          cn63xx;
+	struct cvmx_pip_dec_ipsecx_s          cn63xxp1;
+};
+typedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t;
+
+/**
+ * cvmx_pip_dsa_src_grp
+ */
+union cvmx_pip_dsa_src_grp
+{
+	uint64_t u64;
+	struct cvmx_pip_dsa_src_grp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t map15                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map14                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map13                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map12                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map11                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map10                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map9                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map8                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map7                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map6                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map5                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map4                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map3                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map2                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map1                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map0                         : 4;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+#else
+	uint64_t map0                         : 4;
+	uint64_t map1                         : 4;
+	uint64_t map2                         : 4;
+	uint64_t map3                         : 4;
+	uint64_t map4                         : 4;
+	uint64_t map5                         : 4;
+	uint64_t map6                         : 4;
+	uint64_t map7                         : 4;
+	uint64_t map8                         : 4;
+	uint64_t map9                         : 4;
+	uint64_t map10                        : 4;
+	uint64_t map11                        : 4;
+	uint64_t map12                        : 4;
+	uint64_t map13                        : 4;
+	uint64_t map14                        : 4;
+	uint64_t map15                        : 4;
+#endif
+	} s;
+	struct cvmx_pip_dsa_src_grp_s         cn52xx;
+	struct cvmx_pip_dsa_src_grp_s         cn52xxp1;
+	struct cvmx_pip_dsa_src_grp_s         cn56xx;
+	struct cvmx_pip_dsa_src_grp_s         cn63xx;
+	struct cvmx_pip_dsa_src_grp_s         cn63xxp1;
+};
+typedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t;
+
+/**
+ * cvmx_pip_dsa_vid_grp
+ */
+union cvmx_pip_dsa_vid_grp
+{
+	uint64_t u64;
+	struct cvmx_pip_dsa_vid_grp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t map15                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map14                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map13                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map12                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map11                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map10                        : 4;  /**< DSA Group Algorithm */
+	uint64_t map9                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map8                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map7                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map6                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map5                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map4                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map3                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map2                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map1                         : 4;  /**< DSA Group Algorithm */
+	uint64_t map0                         : 4;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+#else
+	uint64_t map0                         : 4;
+	uint64_t map1                         : 4;
+	uint64_t map2                         : 4;
+	uint64_t map3                         : 4;
+	uint64_t map4                         : 4;
+	uint64_t map5                         : 4;
+	uint64_t map6                         : 4;
+	uint64_t map7                         : 4;
+	uint64_t map8                         : 4;
+	uint64_t map9                         : 4;
+	uint64_t map10                        : 4;
+	uint64_t map11                        : 4;
+	uint64_t map12                        : 4;
+	uint64_t map13                        : 4;
+	uint64_t map14                        : 4;
+	uint64_t map15                        : 4;
+#endif
+	} s;
+	struct cvmx_pip_dsa_vid_grp_s         cn52xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn52xxp1;
+	struct cvmx_pip_dsa_vid_grp_s         cn56xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn63xx;
+	struct cvmx_pip_dsa_vid_grp_s         cn63xxp1;
+};
+typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t;
+
+/**
+ * cvmx_pip_frm_len_chk#
+ *
+ * Notes:
+ * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports.
+ * PIP_FRM_LEN_CHK1 is unused.
+ */
+union cvmx_pip_frm_len_chkx
+{
+	uint64_t u64;
+	struct cvmx_pip_frm_len_chkx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t maxlen                       : 16; /**< Byte count for Max-sized frame check
+                                                         PIP_PRT_CFGn[MAXERR_EN] enables the check for
+                                                         port n.
+                                                         If enabled, failing packets set the MAXERR
+                                                         interrupt and work-queue entry WORD2[opcode] is
+                                                         set to OVER_FCS (0x3, if packet has bad FCS) or
+                                                         OVER_ERR (0x4, if packet has good FCS).
+                                                         The effective MAXLEN used by HW is
+                                                         PIP_PRT_CFG[DSA_EN] == 0,
+                                                          PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS
+                                                         PIP_PRT_CFG[DSA_EN] == 1,
+                                                          PIP_FRM_LEN_CHK[MAXLEN] + PIP_PRT_CFG[SKIP]+4*VS
+                                                         If PTP_MODE, the 8B timestamp is prepended to the
+                                                          packet.  MAXLEN should be increased by 8 to
+                                                          compensate for the additional timestamp field. */
+	uint64_t minlen                       : 16; /**< Byte count for Min-sized frame check
+                                                         PIP_PRT_CFGn[MINERR_EN] enables the check for
+                                                         port n.
+                                                         If enabled, failing packets set the MINERR
+                                                         interrupt and work-queue entry WORD2[opcode] is
+                                                         set to UNDER_FCS (0x6, if packet has bad FCS) or
+                                                         UNDER_ERR (0x8, if packet has good FCS).
+                                                         If PTP_MODE, the 8B timestamp is prepended to the
+                                                          packet.  MINLEN should be increased by 8 to
+                                                          compensate for the additional timestamp field. */
+#else
+	uint64_t minlen                       : 16;
+	uint64_t maxlen                       : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pip_frm_len_chkx_s        cn50xx;
+	struct cvmx_pip_frm_len_chkx_s        cn52xx;
+	struct cvmx_pip_frm_len_chkx_s        cn52xxp1;
+	struct cvmx_pip_frm_len_chkx_s        cn56xx;
+	struct cvmx_pip_frm_len_chkx_s        cn56xxp1;
+	struct cvmx_pip_frm_len_chkx_s        cn63xx;
+	struct cvmx_pip_frm_len_chkx_s        cn63xxp1;
+};
+typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t;
+
+/**
+ * cvmx_pip_gbl_cfg
+ *
+ * PIP_GBL_CFG = PIP's Global Config Register
+ *
+ * Global config information that applies to all ports.
+ *
+ * Notes:
+ * * IP6_UDP
+ * IPv4 allows optional UDP checksum by sending the all 0's patterns.  IPv6
+ * outlaws this and the spec says to always check UDP checksum.  This mode
+ * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's
+ * pattern will cause a UDP checksum pass.
+ */
+union cvmx_pip_gbl_cfg
+{
+	uint64_t u64;
+	struct cvmx_pip_gbl_cfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t tag_syn                      : 1;  /**< Do not include src_crc for TCP/SYN&!ACK packets
+                                                         0 = include src_crc
+                                                         1 = tag hash is dst_crc for TCP/SYN&!ACK packets */
+	uint64_t ip6_udp                      : 1;  /**< IPv6/UDP checksum is not optional
+                                                         0 = Allow optional checksum code
+                                                         1 = Do not allow optional checksum code */
+	uint64_t max_l2                       : 1;  /**< Config bit to choose the largest L2 frame size
+                                                         Chooses the value of the L2 Type/Length field
+                                                         to classify the frame as length.
+                                                         0 = 1500 / 0x5dc
+                                                         1 = 1535 / 0x5ff */
+	uint64_t reserved_11_15               : 5;
+	uint64_t raw_shf                      : 3;  /**< RAW Packet shift amount
+                                                         Number of bytes to pad a RAW packet. */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t nip_shf                      : 3;  /**< Non-IP shift amount
+                                                         Number of bytes to pad a packet that has been
+                                                         classified as not IP. */
+#else
+	uint64_t nip_shf                      : 3;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t raw_shf                      : 3;
+	uint64_t reserved_11_15               : 5;
+	uint64_t max_l2                       : 1;
+	uint64_t ip6_udp                      : 1;
+	uint64_t tag_syn                      : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_pip_gbl_cfg_s             cn30xx;
+	struct cvmx_pip_gbl_cfg_s             cn31xx;
+	struct cvmx_pip_gbl_cfg_s             cn38xx;
+	struct cvmx_pip_gbl_cfg_s             cn38xxp2;
+	struct cvmx_pip_gbl_cfg_s             cn50xx;
+	struct cvmx_pip_gbl_cfg_s             cn52xx;
+	struct cvmx_pip_gbl_cfg_s             cn52xxp1;
+	struct cvmx_pip_gbl_cfg_s             cn56xx;
+	struct cvmx_pip_gbl_cfg_s             cn56xxp1;
+	struct cvmx_pip_gbl_cfg_s             cn58xx;
+	struct cvmx_pip_gbl_cfg_s             cn58xxp1;
+	struct cvmx_pip_gbl_cfg_s             cn63xx;
+	struct cvmx_pip_gbl_cfg_s             cn63xxp1;
+};
+typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t;
+
+/**
+ * cvmx_pip_gbl_ctl
+ *
+ * PIP_GBL_CTL = PIP's Global Control Register
+ *
+ * Global control information.  These are the global checker enables for
+ * IPv4/IPv6 and TCP/UDP parsing.  The enables effect all ports.
+ *
+ * Notes:
+ * The following text describes the conditions in which each checker will
+ * assert and flag an exception.  By disabling the checker, the exception will
+ * not be flagged and the packet will be parsed as best it can.  Note, by
+ * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and
+ * L4_MAL could cause bits to be seen in the wrong place.  IP_CHK and L4_CHK
+ * means that the packet was corrupted).
+ *
+ * * IP_CHK
+ *   Indicates that an IPv4 packet contained an IPv4 header checksum
+ *   violations.  Only applies to packets classified as IPv4.
+ *
+ * * IP_MAL
+ *   Indicates that the packet was malformed.  Malformed packets are defined as
+ *   packets that are not long enough to cover the IP header or not long enough
+ *   to cover the length in the IP header.
+ *
+ * * IP_HOP
+ *   Indicates that the IPv4 TTL field or IPv6 HOP field is zero.
+ *
+ * * IP4_OPTS
+ *   Indicates the presence of IPv4 options.  It is set when the length != 5.
+ *   This only applies to packets classified as IPv4.
+ *
+ * * IP6_EEXT
+ *   Indicate the presence of IPv6 early extension headers.  These bits only
+ *   apply to packets classified as IPv6.  Bit 0 will flag early extensions
+ *   when next_header is any one of the following...
+ *
+ *         - hop-by-hop (0)
+ *         - destination (60)
+ *         - routing (43)
+ *
+ *   Bit 1 will flag early extentions when next_header is NOT any of the
+ *   following...
+ *
+ *         - TCP (6)
+ *         - UDP (17)
+ *         - fragmentation (44)
+ *         - ICMP (58)
+ *         - IPSEC ESP (50)
+ *         - IPSEC AH (51)
+ *         - IPCOMP
+ *
+ * * L4_MAL
+ *   Indicates that a TCP or UDP packet is not long enough to cover the TCP or
+ *   UDP header.
+ *
+ * * L4_PRT
+ *   Indicates that a TCP or UDP packet has an illegal port number - either the
+ *   source or destination port is zero.
+ *
+ * * L4_CHK
+ *   Indicates that a packet classified as either TCP or UDP contains an L4
+ *   checksum failure
+ *
+ * * L4_LEN
+ *   Indicates that the TCP or UDP length does not match the the IP length.
+ *
+ * * TCP_FLAG
+ *   Indicates any of the following conditions...
+ *
+ *         [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag
+ *         6'b000001: (FIN only)
+ *         6'b000000: (0)
+ *         6'bxxx1x1: (RST+FIN+*)
+ *         6'b1xxx1x: (URG+SYN+*)
+ *         6'bxxx11x: (RST+SYN+*)
+ *         6'bxxxx11: (SYN+FIN+*)
+ */
+union cvmx_pip_gbl_ctl
+{
+	uint64_t u64;
+	struct cvmx_pip_gbl_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t ihmsk_dis                    : 1;  /**< Instruction Header Mask Disable
+                                                         0=Allow NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header to control which fields from
+                                                           the instruction header are used for WQE WORD2.
+                                                         1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
+                                                           instruction header and act as if these fields
+                                                           were zero.  Thus always use the TAG,TT,GRP,QOS
+                                                           (depending on the instruction header length)
+                                                           from the instruction header for the WQE WORD2. */
+	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+	uint64_t dsa_grp_scmd                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU */
+	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ring_en                      : 1;  /**< Enable PCIe ring information in WQE */
+	uint64_t reserved_17_19               : 3;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Does not apply to PCI ports (32-35)
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which DSA/VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t ring_en                      : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t dsa_grp_sid                  : 1;
+	uint64_t dsa_grp_scmd                 : 1;
+	uint64_t dsa_grp_tvid                 : 1;
+	uint64_t ihmsk_dis                    : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_pip_gbl_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Only applies to the packet interface prts (0-31)
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which VLAN CFI and ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn30xx;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn31xx;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn38xx;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn38xxp2;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn50xx;
+	struct cvmx_pip_gbl_ctl_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t dsa_grp_tvid                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP */
+	uint64_t dsa_grp_scmd                 : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU */
+	uint64_t dsa_grp_sid                  : 1;  /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ring_en                      : 1;  /**< Enable PCIe ring information in WQE */
+	uint64_t reserved_17_19               : 3;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Does not apply to PCI ports (32-35)
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which DSA/VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t ring_en                      : 1;
+	uint64_t reserved_21_23               : 3;
+	uint64_t dsa_grp_sid                  : 1;
+	uint64_t dsa_grp_scmd                 : 1;
+	uint64_t dsa_grp_tvid                 : 1;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn52xx;
+	struct cvmx_pip_gbl_ctl_cn52xx        cn52xxp1;
+	struct cvmx_pip_gbl_ctl_cn52xx        cn56xx;
+	struct cvmx_pip_gbl_ctl_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t ring_en                      : 1;  /**< Enable PCIe ring information in WQE */
+	uint64_t reserved_17_19               : 3;
+	uint64_t ignrs                        : 1;  /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Does not apply to PCI ports (32-35)
+                                                         When using 2-byte instruction header words,
+                                                         either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
+	uint64_t vs_wqe                       : 1;  /**< Which VLAN CFI and ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t vs_qos                       : 1;  /**< Which VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+	uint64_t l2_mal                       : 1;  /**< Enable L2 malformed packet check */
+	uint64_t tcp_flag                     : 1;  /**< Enable TCP flags checks */
+	uint64_t l4_len                       : 1;  /**< Enable TCP/UDP length check */
+	uint64_t l4_chk                       : 1;  /**< Enable TCP/UDP checksum check */
+	uint64_t l4_prt                       : 1;  /**< Enable TCP/UDP illegal port check */
+	uint64_t l4_mal                       : 1;  /**< Enable TCP/UDP malformed packet check */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ip6_eext                     : 2;  /**< Enable IPv6 early extension headers */
+	uint64_t ip4_opts                     : 1;  /**< Enable IPv4 options check */
+	uint64_t ip_hop                       : 1;  /**< Enable TTL (IPv4) / hop (IPv6) check */
+	uint64_t ip_mal                       : 1;  /**< Enable malformed check */
+	uint64_t ip_chk                       : 1;  /**< Enable IPv4 header checksum check */
+#else
+	uint64_t ip_chk                       : 1;
+	uint64_t ip_mal                       : 1;
+	uint64_t ip_hop                       : 1;
+	uint64_t ip4_opts                     : 1;
+	uint64_t ip6_eext                     : 2;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t l4_mal                       : 1;
+	uint64_t l4_prt                       : 1;
+	uint64_t l4_chk                       : 1;
+	uint64_t l4_len                       : 1;
+	uint64_t tcp_flag                     : 1;
+	uint64_t l2_mal                       : 1;
+	uint64_t vs_qos                       : 1;
+	uint64_t vs_wqe                       : 1;
+	uint64_t ignrs                        : 1;
+	uint64_t reserved_17_19               : 3;
+	uint64_t ring_en                      : 1;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} cn56xxp1;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn58xx;
+	struct cvmx_pip_gbl_ctl_cn30xx        cn58xxp1;
+	struct cvmx_pip_gbl_ctl_s             cn63xx;
+	struct cvmx_pip_gbl_ctl_s             cn63xxp1;
+};
+typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t;
+
+/**
+ * cvmx_pip_hg_pri_qos
+ *
+ * Notes:
+ * This register controls accesses to the HG_QOS_TABLE.  To write an entry of
+ * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level,
+ * UP_QOS=1.  To read an entry of the table, write PIP_HG_PRI_QOS with
+ * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read
+ * PIP_HG_PRI_QOS.  The table data will be in PIP_HG_PRI_QOS[QOS].
+ */
+union cvmx_pip_hg_pri_qos
+{
+	uint64_t u64;
+	struct cvmx_pip_hg_pri_qos_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t up_qos                       : 1;  /**< When written to '1', updates the entry in the
+                                                         HG_QOS_TABLE as specified by PRI to a value of
+                                                         QOS as follows
+                                                         HG_QOS_TABLE[PRI] = QOS */
+	uint64_t reserved_11_11               : 1;
+	uint64_t qos                          : 3;  /**< QOS Map level to priority */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pri                          : 6;  /**< The priority level from HiGig header
+                                                         HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
+                                                         HiGig2       PRI = [DP[1:0], TC[3:0]] */
+#else
+	uint64_t pri                          : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t qos                          : 3;
+	uint64_t reserved_11_11               : 1;
+	uint64_t up_qos                       : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pip_hg_pri_qos_s          cn52xx;
+	struct cvmx_pip_hg_pri_qos_s          cn52xxp1;
+	struct cvmx_pip_hg_pri_qos_s          cn56xx;
+	struct cvmx_pip_hg_pri_qos_s          cn63xx;
+	struct cvmx_pip_hg_pri_qos_s          cn63xxp1;
+};
+typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t;
+
+/**
+ * cvmx_pip_int_en
+ *
+ * PIP_INT_EN = PIP's Interrupt Enable Register
+ *
+ * Determines if hardward should raise an interrupt to software
+ * when an exception event occurs.
+ */
+union cvmx_pip_int_en
+{
+	uint64_t u64;
+	struct cvmx_pip_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pip_int_en_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow
+                                                         (not used in O2P) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure
+                                                         (not used in O2P) */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC
+                                                         (not used in O2P) */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn30xx;
+	struct cvmx_pip_int_en_cn30xx         cn31xx;
+	struct cvmx_pip_int_en_cn30xx         cn38xx;
+	struct cvmx_pip_int_en_cn30xx         cn38xxp2;
+	struct cvmx_pip_int_en_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn50xx;
+	struct cvmx_pip_int_en_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn52xx;
+	struct cvmx_pip_int_en_cn52xx         cn52xxp1;
+	struct cvmx_pip_int_en_s              cn56xx;
+	struct cvmx_pip_int_en_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC
+                                                         (Disabled in 56xx) */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xxp1;
+	struct cvmx_pip_int_en_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t reserved_9_11                : 3;
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn58xx;
+	struct cvmx_pip_int_en_cn30xx         cn58xxp1;
+	struct cvmx_pip_int_en_s              cn63xx;
+	struct cvmx_pip_int_en_s              cn63xxp1;
+};
+typedef union cvmx_pip_int_en cvmx_pip_int_en_t;
+
+/**
+ * cvmx_pip_int_reg
+ *
+ * PIP_INT_REG = PIP's Interrupt Register
+ *
+ * Any exception event that occurs is captured in the PIP_INT_REG.
+ * PIP_INT_REG will set the exception bit regardless of the value
+ * of PIP_INT_EN.  PIP_INT_EN only controls if an interrupt is
+ * raised to software.
+ *
+ * Notes:
+ * * TODOOVR
+ *   The PIP Todo list stores packets that have been received and require work
+ *   queue entry generation.  PIP will normally assert backpressure when the
+ *   list fills up such that any error is normally is result of a programming
+ *   the PIP_BCK_PRS[HIWATER] incorrectly.  PIP itself can handle 29M
+ *   packets/sec X500MHz or 15Gbs X 64B packets.
+ *
+ * * SKPRUNT
+ *   If a packet size is less then the amount programmed in the per port
+ *   skippers, then there will be nothing to parse and the entire packet will
+ *   basically be skipped over.  This is probably not what the user desired, so
+ *   there is an indication to software.
+ *
+ * * BADTAG
+ *   A tag is considered bad when it is resued by a new packet before it was
+ *   released by PIP.  PIP considers a tag released by one of two methods.
+ *   . QOS dropped so that it is released over the pip__ipd_release bus.
+ *   . WorkQ entry is validated by the pip__ipd_done signal
+ *
+ * * PRTNXA
+ *   If PIP receives a packet that is not in the valid port range, the port
+ *   processed will be mapped into the valid port space (the mapping is
+ *   currently unpredictable) and the PRTNXA bit will be set.  PRTNXA will be
+ *   set for packets received under the following conditions:
+ *
+ *   * packet ports (ports 0-31)
+ *     - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-15 or 20-31
+ *     - GMX_INF_MODE[TYPE]==1 (XAUI),  received port is 1-15 or 17-31
+ *   * upper ports (pci and loopback ports 32-63)
+ *     - received port is 40-47 or 52-63
+ *
+ * * BCKPRS
+ *   PIP can assert backpressure to the receive logic when the todo list
+ *   exceeds a high-water mark (see PIP_BCK_PRS for more details).  When this
+ *   occurs, PIP can raise an interrupt to software.
+ *
+ * * CRCERR
+ *   Octane can compute CRC in two places.  Each RGMII port will compute its
+ *   own CRC, but PIP can provide an additional check or check loopback or
+ *   PCI ports. If PIP computes a bad CRC, then PIP will raise an interrupt.
+ *
+ * * PKTDRP
+ *   PIP can drop packets based on QOS results received from IPD.  If the QOS
+ *   algorithm decides to drop a packet, PIP will assert an interrupt.
+ */
+union cvmx_pip_int_reg
+{
+	uint64_t u64;
+	struct cvmx_pip_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_pip_int_reg_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow
+                                                         (not used in O2P) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure
+                                                         (not used in O2P) */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC
+                                                         (not used in O2P) */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn30xx;
+	struct cvmx_pip_int_reg_cn30xx        cn31xx;
+	struct cvmx_pip_int_reg_cn30xx        cn38xx;
+	struct cvmx_pip_int_reg_cn30xx        cn38xxp2;
+	struct cvmx_pip_int_reg_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn50xx;
+	struct cvmx_pip_int_reg_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn52xx;
+	struct cvmx_pip_int_reg_cn52xx        cn52xxp1;
+	struct cvmx_pip_int_reg_s             cn56xx;
+	struct cvmx_pip_int_reg_cn56xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t lenerr                       : 1;  /**< Frame was received with length error */
+	uint64_t maxerr                       : 1;  /**< Frame was received with length > max_length */
+	uint64_t minerr                       : 1;  /**< Frame was received with length < min_length */
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC
+                                                         (Disabled in 56xx) */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t minerr                       : 1;
+	uint64_t maxerr                       : 1;
+	uint64_t lenerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} cn56xxp1;
+	struct cvmx_pip_int_reg_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t punyerr                      : 1;  /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+	uint64_t reserved_9_11                : 3;
+	uint64_t beperr                       : 1;  /**< Parity Error in back end memory */
+	uint64_t feperr                       : 1;  /**< Parity Error in front end memory */
+	uint64_t todoovr                      : 1;  /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+	uint64_t skprunt                      : 1;  /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+	uint64_t badtag                       : 1;  /**< A bad tag was sent from IPD */
+	uint64_t prtnxa                       : 1;  /**< Non-existent port */
+	uint64_t bckprs                       : 1;  /**< PIP asserted backpressure */
+	uint64_t crcerr                       : 1;  /**< PIP calculated bad CRC */
+	uint64_t pktdrp                       : 1;  /**< Packet Dropped due to QOS */
+#else
+	uint64_t pktdrp                       : 1;
+	uint64_t crcerr                       : 1;
+	uint64_t bckprs                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t badtag                       : 1;
+	uint64_t skprunt                      : 1;
+	uint64_t todoovr                      : 1;
+	uint64_t feperr                       : 1;
+	uint64_t beperr                       : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t punyerr                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} cn58xx;
+	struct cvmx_pip_int_reg_cn30xx        cn58xxp1;
+	struct cvmx_pip_int_reg_s             cn63xx;
+	struct cvmx_pip_int_reg_s             cn63xxp1;
+};
+typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t;
+
+/**
+ * cvmx_pip_ip_offset
+ *
+ * PIP_IP_OFFSET = Location of the IP in the workQ entry
+ *
+ * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires
+ *
+ * Notes:
+ * In normal configurations, OFFSET must be set in the 0..4 range to allow the
+ * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4
+ * checksum for TCP/UDP packets.
+ *
+ * The MAX value of OFFSET is determined by the the types of packets that can
+ * be sent to PIP as follows...
+ *
+ * Packet Type              MAX OFFSET
+ * IPv4/TCP/UDP             7
+ * IPv6/TCP/UDP             5
+ * IPv6/without L4 parsing  6
+ *
+ * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase
+ * to 6.  Here are the following programming restrictions for IPv6 packets and
+ * OFFSET==6:
+ *
+ *  . PIP_GBL_CTL[TCP_FLAG] == 0
+ *  . PIP_GBL_CTL[L4_LEN]   == 0
+ *  . PIP_GBL_CTL[L4_CHK]   == 0
+ *  . PIP_GBL_CTL[L4_PRT]   == 0
+ *  . PIP_GBL_CTL[L4_MAL]   == 0
+ *  . PIP_DEC_IPSEC[TCP]    == 0
+ *  . PIP_DEC_IPSEC[UDP]    == 0
+ *  . PIP_PRT_TAG[IP6_DPRT] == 0
+ *  . PIP_PRT_TAG[IP6_SPRT] == 0
+ *  . PIP_PRT_TAG[TCP6_TAG] == 0
+ *  . PIP_GBL_CFG[TAG_SYN]  == 0
+ */
+union cvmx_pip_ip_offset
+{
+	uint64_t u64;
+	struct cvmx_pip_ip_offset_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t offset                       : 3;  /**< Number of 8B ticks to include in workQ entry
+                                                          prior to IP data
+                                                         - 0:  0 Bytes / IP start at WORD4 of workQ entry
+                                                         - 1:  8 Bytes / IP start at WORD5 of workQ entry
+                                                         - 2: 16 Bytes / IP start at WORD6 of workQ entry
+                                                         - 3: 24 Bytes / IP start at WORD7 of workQ entry
+                                                         - 4: 32 Bytes / IP start at WORD8 of workQ entry
+                                                         - 5: 40 Bytes / IP start at WORD9 of workQ entry
+                                                         - 6: 48 Bytes / IP start at WORD10 of workQ entry
+                                                         - 7: 56 Bytes / IP start at WORD11 of workQ entry */
+#else
+	uint64_t offset                       : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_pip_ip_offset_s           cn30xx;
+	struct cvmx_pip_ip_offset_s           cn31xx;
+	struct cvmx_pip_ip_offset_s           cn38xx;
+	struct cvmx_pip_ip_offset_s           cn38xxp2;
+	struct cvmx_pip_ip_offset_s           cn50xx;
+	struct cvmx_pip_ip_offset_s           cn52xx;
+	struct cvmx_pip_ip_offset_s           cn52xxp1;
+	struct cvmx_pip_ip_offset_s           cn56xx;
+	struct cvmx_pip_ip_offset_s           cn56xxp1;
+	struct cvmx_pip_ip_offset_s           cn58xx;
+	struct cvmx_pip_ip_offset_s           cn58xxp1;
+	struct cvmx_pip_ip_offset_s           cn63xx;
+	struct cvmx_pip_ip_offset_s           cn63xxp1;
+};
+typedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t;
+
+/**
+ * cvmx_pip_prt_cfg#
+ *
+ * PIP_PRT_CFGX = Per port config information
+ *
+ */
+union cvmx_pip_prt_cfgx
+{
+	uint64_t u64;
+	struct cvmx_pip_prt_cfgx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_53_63               : 11;
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for DSA/VLAN
+                                                         pkts */
+	uint64_t lenerr_en                    : 1;  /**< L2 length error check enable
+                                                         Frame was received with length error
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the PCIe ports. */
+	uint64_t maxerr_en                    : 1;  /**< Max frame error check enable
+                                                         Frame was received with length > max_length */
+	uint64_t minerr_en                    : 1;  /**< Min frame error check enable
+                                                         Frame was received with length < min_length
+                                                          Typically, this check will not be enabled for
+                                                          incoming packets on the PCIe ports. */
+	uint64_t grp_wat_47                   : 4;  /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t qos_wat_47                   : 4;  /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t reserved_37_39               : 3;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35)
+                                                         Must be zero in DSA mode */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t hg_qos                       : 1;  /**< When set, uses the HiGig priority bits as a
+                                                         lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
+                                                         to determine the QOS value
+                                                         HG_QOS must not be set when HIGIG_EN=0 */
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable
+                                                         (Watchers 0-3) */
+	uint64_t qos_vsel                     : 1;  /**< Which QOS in PIP_QOS_VLAN to use
+                                                         0 = PIP_QOS_VLAN[QOS]
+                                                         1 = PIP_QOS_VLAN[QOS1] */
+	uint64_t qos_vod                      : 1;  /**< QOS VLAN over Diffserv
+                                                         if DSA/VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled */
+	uint64_t higig_en                     : 1;  /**< Enable HiGig parsing
+                                                         Should not be set for PCIe ports (ports 32-35)
+                                                         Should not be set for ports in which PTP_MODE=1
+                                                         When HIGIG_EN=1:
+                                                          DSA_EN field below must be zero
+                                                          SKIP field below is both Skip I size and the
+                                                            size of the HiGig* header (12 or 16 bytes) */
+	uint64_t dsa_en                       : 1;  /**< Enable DSA tag parsing
+                                                         When DSA_EN=1:
+                                                          HIGIG_EN field above must be zero
+                                                          SKIP field below is size of DSA tag (4, 8, or
+                                                            12 bytes) rather than the size of Skip I
+                                                          total SKIP (Skip I + header + Skip II
+                                                            must be zero
+                                                          INST_HDR field above must be zero (non-PCIe
+                                                            ports)
+                                                          For PCIe ports, NPEI_PKT*_INSTR_HDR[USE_IHDR]
+                                                            and PCIE_INST_HDR[R] should be clear
+                                                          MODE field below must be "skip to L2" */
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = (illegal)
+                                                         Must be 2 ("skip to L2") when in DSA mode. */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details.
+                                                         In DSA mode, indicates the DSA header length, not
+                                                           Skip I size. (Must be 4,8,or 12)
+                                                         In HIGIG mode, indicates both the Skip I size and
+                                                           the HiGig header size (Must be 12 or 16).
+                                                         If PTP_MODE, the 8B timestamp is prepended to the
+                                                          packet.  SKIP should be increased by 8 to
+                                                          compensate for the additional timestamp field. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t dsa_en                       : 1;
+	uint64_t higig_en                     : 1;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t qos_vod                      : 1;
+	uint64_t qos_vsel                     : 1;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t hg_qos                       : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t qos_wat_47                   : 4;
+	uint64_t grp_wat_47                   : 4;
+	uint64_t minerr_en                    : 1;
+	uint64_t maxerr_en                    : 1;
+	uint64_t lenerr_en                    : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} s;
+	struct cvmx_pip_prt_cfgx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable */
+	uint64_t reserved_18_19               : 2;
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_10_15               : 6;
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t reserved_27_27               : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn30xx;
+	struct cvmx_pip_prt_cfgx_cn30xx       cn31xx;
+	struct cvmx_pip_prt_cfgx_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable */
+	uint64_t reserved_18_19               : 2;
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled (for ports 0-31 only) */
+	uint64_t reserved_10_11               : 2;
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t reserved_18_19               : 2;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t reserved_27_27               : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn38xx;
+	struct cvmx_pip_prt_cfgx_cn38xx       cn38xxp2;
+	struct cvmx_pip_prt_cfgx_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_53_63               : 11;
+	uint64_t pad_len                      : 1;  /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+	uint64_t vlan_len                     : 1;  /**< When set, disables the length check for VLAN pkts */
+	uint64_t lenerr_en                    : 1;  /**< L2 length error check enable
+                                                         Frame was received with length error */
+	uint64_t maxerr_en                    : 1;  /**< Max frame error check enable
+                                                         Frame was received with length > max_length */
+	uint64_t minerr_en                    : 1;  /**< Min frame error check enable
+                                                         Frame was received with length < min_length */
+	uint64_t grp_wat_47                   : 4;  /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t qos_wat_47                   : 4;  /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+	uint64_t reserved_37_39               : 3;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable
+                                                         (Watchers 0-3) */
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_vod                      : 1;  /**< QOS VLAN over Diffserv
+                                                         if VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled
+                                                         (Disabled in 5020) */
+	uint64_t reserved_10_11               : 2;
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t qos_vod                      : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t reserved_27_27               : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_39               : 3;
+	uint64_t qos_wat_47                   : 4;
+	uint64_t grp_wat_47                   : 4;
+	uint64_t minerr_en                    : 1;
+	uint64_t maxerr_en                    : 1;
+	uint64_t lenerr_en                    : 1;
+	uint64_t vlan_len                     : 1;
+	uint64_t pad_len                      : 1;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} cn50xx;
+	struct cvmx_pip_prt_cfgx_s            cn52xx;
+	struct cvmx_pip_prt_cfgx_s            cn52xxp1;
+	struct cvmx_pip_prt_cfgx_s            cn56xx;
+	struct cvmx_pip_prt_cfgx_cn50xx       cn56xxp1;
+	struct cvmx_pip_prt_cfgx_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t rawdrp                       : 1;  /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+	uint64_t tag_inc                      : 2;  /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+	uint64_t dyn_rs                       : 1;  /**< Dynamically calculate RS based on pkt size and
+                                                         configuration.  If DYN_RS is set then
+                                                         PKT_INST_HDR[RS] is not used.  When using 2-byte
+                                                         instruction header words, either DYN_RS or
+                                                         PIP_GBL_CTL[IGNRS] should be set. */
+	uint64_t inst_hdr                     : 1;  /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+	uint64_t grp_wat                      : 4;  /**< GRP Watcher enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t qos                          : 3;  /**< Default QOS level of the port */
+	uint64_t qos_wat                      : 4;  /**< QOS Watcher enable */
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_vod                      : 1;  /**< QOS VLAN over Diffserv
+                                                         if VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+	uint64_t qos_diff                     : 1;  /**< QOS Diffserv */
+	uint64_t qos_vlan                     : 1;  /**< QOS VLAN */
+	uint64_t reserved_13_15               : 3;
+	uint64_t crc_en                       : 1;  /**< CRC Checking enabled (for ports 0-31 only) */
+	uint64_t reserved_10_11               : 2;
+	cvmx_pip_port_parse_mode_t mode       : 2;  /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t skip                         : 7;  /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+	uint64_t skip                         : 7;
+	uint64_t reserved_7_7                 : 1;
+	cvmx_pip_port_parse_mode_t mode       : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t crc_en                       : 1;
+	uint64_t reserved_13_15               : 3;
+	uint64_t qos_vlan                     : 1;
+	uint64_t qos_diff                     : 1;
+	uint64_t qos_vod                      : 1;
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos_wat                      : 4;
+	uint64_t qos                          : 3;
+	uint64_t reserved_27_27               : 1;
+	uint64_t grp_wat                      : 4;
+	uint64_t inst_hdr                     : 1;
+	uint64_t dyn_rs                       : 1;
+	uint64_t tag_inc                      : 2;
+	uint64_t rawdrp                       : 1;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn58xx;
+	struct cvmx_pip_prt_cfgx_cn58xx       cn58xxp1;
+	struct cvmx_pip_prt_cfgx_s            cn63xx;
+	struct cvmx_pip_prt_cfgx_s            cn63xxp1;
+};
+typedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t;
+
+/**
+ * cvmx_pip_prt_tag#
+ *
+ * PIP_PRT_TAGX = Per port config information
+ *
+ */
+union cvmx_pip_prt_tagx
+{
+	uint64_t u64;
+	struct cvmx_pip_prt_tagx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t grptagbase                   : 4;  /**< Offset to use when computing group from tag bits
+                                                         when GRPTAG is set. */
+	uint64_t grptagmask                   : 4;  /**< Which bits of the tag to exclude when computing
+                                                         group when GRPTAG is set. */
+	uint64_t grptag                       : 1;  /**< When set, use the lower bit of the tag to compute
+                                                         the group in the work queue entry
+                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
+	uint64_t grptag_mskip                 : 1;  /**< When set, GRPTAG will be used regardless if the
+                                                         packet IS_IP. */
+	uint64_t tag_mode                     : 2;  /**< Which tag algorithm to use
+                                                         0 = always use tuple tag algorithm
+                                                         1 = always use mask tag algorithm
+                                                         2 = if packet is IP, use tuple else use mask
+                                                         3 = tuple XOR mask */
+	uint64_t inc_vs                       : 2;  /**< determines the DSA/VLAN ID (VID) to be included in
+                                                         tuple tag when VLAN stacking is detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID (VLAN0) in hash
+                                                         2 = include VID (VLAN1) in hash
+                                                         3 = include VID ([VLAN0,VLAN1]) in hash */
+	uint64_t inc_vlan                     : 1;  /**< when set, the DSA/VLAN ID is included in tuple tag
+                                                         when VLAN stacking is not detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID in hash */
+	uint64_t inc_prt_flag                 : 1;  /**< sets whether the port is included in tuple tag */
+	uint64_t ip6_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_nxth_flag                : 1;  /**< sets whether ipv6 includes next header in tuple
+                                                         tag hash */
+	uint64_t ip4_pctl_flag                : 1;  /**< sets whether ipv4 includes protocol in tuple
+                                                         tag hash */
+	uint64_t ip6_dst_flag                 : 1;  /**< sets whether ipv6 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip4_dst_flag                 : 1;  /**< sets whether ipv4 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip6_src_flag                 : 1;  /**< sets whether ipv6 includes src address in tuple
+                                                         tag hash */
+	uint64_t ip4_src_flag                 : 1;  /**< sets whether ipv4 includes src address in tuple
+                                                         tag hash */
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv6)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv4)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;  /**< sets whether IPv6 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;  /**< sets whether IPv4 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t non_tag_type      : 2;  /**< sets whether non-IP packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	uint64_t grp                          : 4;  /**< 4-bit value indicating the group to schedule to */
+#else
+	uint64_t grp                          : 4;
+	cvmx_pow_tag_type_t non_tag_type      : 2;
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;
+	uint64_t ip4_src_flag                 : 1;
+	uint64_t ip6_src_flag                 : 1;
+	uint64_t ip4_dst_flag                 : 1;
+	uint64_t ip6_dst_flag                 : 1;
+	uint64_t ip4_pctl_flag                : 1;
+	uint64_t ip6_nxth_flag                : 1;
+	uint64_t ip4_sprt_flag                : 1;
+	uint64_t ip6_sprt_flag                : 1;
+	uint64_t ip4_dprt_flag                : 1;
+	uint64_t ip6_dprt_flag                : 1;
+	uint64_t inc_prt_flag                 : 1;
+	uint64_t inc_vlan                     : 1;
+	uint64_t inc_vs                       : 2;
+	uint64_t tag_mode                     : 2;
+	uint64_t grptag_mskip                 : 1;
+	uint64_t grptag                       : 1;
+	uint64_t grptagmask                   : 4;
+	uint64_t grptagbase                   : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_pip_prt_tagx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t grptagbase                   : 4;  /**< Offset to use when computing group from tag bits
+                                                         when GRPTAG is set. */
+	uint64_t grptagmask                   : 4;  /**< Which bits of the tag to exclude when computing
+                                                         group when GRPTAG is set. */
+	uint64_t grptag                       : 1;  /**< When set, use the lower bit of the tag to compute
+                                                         the group in the work queue entry
+                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
+	uint64_t reserved_30_30               : 1;
+	uint64_t tag_mode                     : 2;  /**< Which tag algorithm to use
+                                                         0 = always use tuple tag algorithm
+                                                         1 = always use mask tag algorithm
+                                                         2 = if packet is IP, use tuple else use mask
+                                                         3 = tuple XOR mask */
+	uint64_t inc_vs                       : 2;  /**< determines the VLAN ID (VID) to be included in
+                                                         tuple tag when VLAN stacking is detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID (VLAN0) in hash
+                                                         2 = include VID (VLAN1) in hash
+                                                         3 = include VID ([VLAN0,VLAN1]) in hash */
+	uint64_t inc_vlan                     : 1;  /**< when set, the VLAN ID is included in tuple tag
+                                                         when VLAN stacking is not detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID in hash */
+	uint64_t inc_prt_flag                 : 1;  /**< sets whether the port is included in tuple tag */
+	uint64_t ip6_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_dprt_flag                : 1;  /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv6 packets */
+	uint64_t ip4_sprt_flag                : 1;  /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv4 */
+	uint64_t ip6_nxth_flag                : 1;  /**< sets whether ipv6 includes next header in tuple
+                                                         tag hash */
+	uint64_t ip4_pctl_flag                : 1;  /**< sets whether ipv4 includes protocol in tuple
+                                                         tag hash */
+	uint64_t ip6_dst_flag                 : 1;  /**< sets whether ipv6 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip4_dst_flag                 : 1;  /**< sets whether ipv4 includes dst address in tuple
+                                                         tag hash */
+	uint64_t ip6_src_flag                 : 1;  /**< sets whether ipv6 includes src address in tuple
+                                                         tag hash */
+	uint64_t ip4_src_flag                 : 1;  /**< sets whether ipv4 includes src address in tuple
+                                                         tag hash */
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv6)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;  /**< sets the tag_type of a TCP packet (IPv4)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;  /**< sets whether IPv6 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;  /**< sets whether IPv4 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	cvmx_pow_tag_type_t non_tag_type      : 2;  /**< sets whether non-IP packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+	uint64_t grp                          : 4;  /**< 4-bit value indicating the group to schedule to */
+#else
+	uint64_t grp                          : 4;
+	cvmx_pow_tag_type_t non_tag_type      : 2;
+	cvmx_pow_tag_type_t ip4_tag_type      : 2;
+	cvmx_pow_tag_type_t ip6_tag_type      : 2;
+	cvmx_pow_tag_type_t tcp4_tag_type     : 2;
+	cvmx_pow_tag_type_t tcp6_tag_type     : 2;
+	uint64_t ip4_src_flag                 : 1;
+	uint64_t ip6_src_flag                 : 1;
+	uint64_t ip4_dst_flag                 : 1;
+	uint64_t ip6_dst_flag                 : 1;
+	uint64_t ip4_pctl_flag                : 1;
+	uint64_t ip6_nxth_flag                : 1;
+	uint64_t ip4_sprt_flag                : 1;
+	uint64_t ip6_sprt_flag                : 1;
+	uint64_t ip4_dprt_flag                : 1;
+	uint64_t ip6_dprt_flag                : 1;
+	uint64_t inc_prt_flag                 : 1;
+	uint64_t inc_vlan                     : 1;
+	uint64_t inc_vs                       : 2;
+	uint64_t tag_mode                     : 2;
+	uint64_t reserved_30_30               : 1;
+	uint64_t grptag                       : 1;
+	uint64_t grptagmask                   : 4;
+	uint64_t grptagbase                   : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn30xx;
+	struct cvmx_pip_prt_tagx_cn30xx       cn31xx;
+	struct cvmx_pip_prt_tagx_cn30xx       cn38xx;
+	struct cvmx_pip_prt_tagx_cn30xx       cn38xxp2;
+	struct cvmx_pip_prt_tagx_s            cn50xx;
+	struct cvmx_pip_prt_tagx_s            cn52xx;
+	struct cvmx_pip_prt_tagx_s            cn52xxp1;
+	struct cvmx_pip_prt_tagx_s            cn56xx;
+	struct cvmx_pip_prt_tagx_s            cn56xxp1;
+	struct cvmx_pip_prt_tagx_cn30xx       cn58xx;
+	struct cvmx_pip_prt_tagx_cn30xx       cn58xxp1;
+	struct cvmx_pip_prt_tagx_s            cn63xx;
+	struct cvmx_pip_prt_tagx_s            cn63xxp1;
+};
+typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t;
+
+/**
+ * cvmx_pip_qos_diff#
+ *
+ * PIP_QOS_DIFFX = QOS Diffserv Tables
+ *
+ */
+union cvmx_pip_qos_diffx
+{
+	uint64_t u64;
+	struct cvmx_pip_qos_diffx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t qos                          : 3;  /**< Diffserv QOS level */
+#else
+	uint64_t qos                          : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_pip_qos_diffx_s           cn30xx;
+	struct cvmx_pip_qos_diffx_s           cn31xx;
+	struct cvmx_pip_qos_diffx_s           cn38xx;
+	struct cvmx_pip_qos_diffx_s           cn38xxp2;
+	struct cvmx_pip_qos_diffx_s           cn50xx;
+	struct cvmx_pip_qos_diffx_s           cn52xx;
+	struct cvmx_pip_qos_diffx_s           cn52xxp1;
+	struct cvmx_pip_qos_diffx_s           cn56xx;
+	struct cvmx_pip_qos_diffx_s           cn56xxp1;
+	struct cvmx_pip_qos_diffx_s           cn58xx;
+	struct cvmx_pip_qos_diffx_s           cn58xxp1;
+	struct cvmx_pip_qos_diffx_s           cn63xx;
+	struct cvmx_pip_qos_diffx_s           cn63xxp1;
+};
+typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t;
+
+/**
+ * cvmx_pip_qos_vlan#
+ *
+ * PIP_QOS_VLANX = QOS VLAN Tables
+ *
+ * If the PIP indentifies a packet is DSA/VLAN tagged, then the QOS
+ * can be set based on the DSA/VLAN user priority.  These eight register
+ * comprise the QOS values for all DSA/VLAN user priority values.
+ */
+union cvmx_pip_qos_vlanx
+{
+	uint64_t u64;
+	struct cvmx_pip_qos_vlanx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t qos1                         : 3;  /**< DSA/VLAN QOS level
+                                                         Selected when PIP_PRT_CFGx[QOS_VSEL] = 1 */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t qos                          : 3;  /**< DSA/VLAN QOS level
+                                                         Selected when PIP_PRT_CFGx[QOS_VSEL] = 0 */
+#else
+	uint64_t qos                          : 3;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t qos1                         : 3;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_pip_qos_vlanx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t qos                          : 3;  /**< VLAN QOS level */
+#else
+	uint64_t qos                          : 3;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn31xx;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn38xx;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn38xxp2;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn50xx;
+	struct cvmx_pip_qos_vlanx_s           cn52xx;
+	struct cvmx_pip_qos_vlanx_s           cn52xxp1;
+	struct cvmx_pip_qos_vlanx_s           cn56xx;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn56xxp1;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn58xx;
+	struct cvmx_pip_qos_vlanx_cn30xx      cn58xxp1;
+	struct cvmx_pip_qos_vlanx_s           cn63xx;
+	struct cvmx_pip_qos_vlanx_s           cn63xxp1;
+};
+typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t;
+
+/**
+ * cvmx_pip_qos_watch#
+ *
+ * PIP_QOS_WATCHX = QOS Watcher Tables
+ *
+ * Sets up the Configuration CSRs for the four QOS Watchers.
+ * Each Watcher can be set to look for a specific protocol,
+ * TCP/UDP destination port, or Ethertype to override the
+ * default QOS value.
+ */
+union cvmx_pip_qos_watchx
+{
+	uint64_t u64;
+	struct cvmx_pip_qos_watchx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t mask                         : 16; /**< Mask off a range of values */
+	uint64_t reserved_28_31               : 4;
+	uint64_t grp                          : 4;  /**< The GRP number of the watcher */
+	uint64_t reserved_23_23               : 1;
+	uint64_t qos                          : 3;  /**< The QOS level of the watcher */
+	uint64_t reserved_19_19               : 1;
+	cvmx_pip_qos_watch_types match_type   : 3;  /**< The field for the watcher match against
+                                                         0   = disable across all ports
+                                                         1   = protocol (ipv4)
+                                                             = next_header (ipv6)
+                                                         2   = TCP destination port
+                                                         3   = UDP destination port
+                                                         4   = Ether type
+                                                         5-7 = Reserved */
+	uint64_t match_value                  : 16; /**< The value to watch for */
+#else
+	uint64_t match_value                  : 16;
+	cvmx_pip_qos_watch_types match_type   : 3;
+	uint64_t reserved_19_19               : 1;
+	uint64_t qos                          : 3;
+	uint64_t reserved_23_23               : 1;
+	uint64_t grp                          : 4;
+	uint64_t reserved_28_31               : 4;
+	uint64_t mask                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_qos_watchx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t mask                         : 16; /**< Mask off a range of values */
+	uint64_t reserved_28_31               : 4;
+	uint64_t grp                          : 4;  /**< The GRP number of the watcher */
+	uint64_t reserved_23_23               : 1;
+	uint64_t qos                          : 3;  /**< The QOS level of the watcher */
+	uint64_t reserved_18_19               : 2;
+	cvmx_pip_qos_watch_types match_type   : 2;  /**< The field for the watcher match against
+                                                         0 = disable across all ports
+                                                         1 = protocol (ipv4)
+                                                           = next_header (ipv6)
+                                                         2 = TCP destination port
+                                                         3 = UDP destination port */
+	uint64_t match_value                  : 16; /**< The value to watch for */
+#else
+	uint64_t match_value                  : 16;
+	cvmx_pip_qos_watch_types match_type   : 2;
+	uint64_t reserved_18_19               : 2;
+	uint64_t qos                          : 3;
+	uint64_t reserved_23_23               : 1;
+	uint64_t grp                          : 4;
+	uint64_t reserved_28_31               : 4;
+	uint64_t mask                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn30xx;
+	struct cvmx_pip_qos_watchx_cn30xx     cn31xx;
+	struct cvmx_pip_qos_watchx_cn30xx     cn38xx;
+	struct cvmx_pip_qos_watchx_cn30xx     cn38xxp2;
+	struct cvmx_pip_qos_watchx_s          cn50xx;
+	struct cvmx_pip_qos_watchx_s          cn52xx;
+	struct cvmx_pip_qos_watchx_s          cn52xxp1;
+	struct cvmx_pip_qos_watchx_s          cn56xx;
+	struct cvmx_pip_qos_watchx_s          cn56xxp1;
+	struct cvmx_pip_qos_watchx_cn30xx     cn58xx;
+	struct cvmx_pip_qos_watchx_cn30xx     cn58xxp1;
+	struct cvmx_pip_qos_watchx_s          cn63xx;
+	struct cvmx_pip_qos_watchx_s          cn63xxp1;
+};
+typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t;
+
+/**
+ * cvmx_pip_raw_word
+ *
+ * PIP_RAW_WORD = The RAW Word2 of the workQ entry.
+ *
+ * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.
+ */
+union cvmx_pip_raw_word
+{
+	uint64_t u64;
+	struct cvmx_pip_raw_word_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t word                         : 56; /**< Word2 of the workQ entry
+                                                         The 8-bit bufs field is still set by HW (IPD) */
+#else
+	uint64_t word                         : 56;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_pip_raw_word_s            cn30xx;
+	struct cvmx_pip_raw_word_s            cn31xx;
+	struct cvmx_pip_raw_word_s            cn38xx;
+	struct cvmx_pip_raw_word_s            cn38xxp2;
+	struct cvmx_pip_raw_word_s            cn50xx;
+	struct cvmx_pip_raw_word_s            cn52xx;
+	struct cvmx_pip_raw_word_s            cn52xxp1;
+	struct cvmx_pip_raw_word_s            cn56xx;
+	struct cvmx_pip_raw_word_s            cn56xxp1;
+	struct cvmx_pip_raw_word_s            cn58xx;
+	struct cvmx_pip_raw_word_s            cn58xxp1;
+	struct cvmx_pip_raw_word_s            cn63xx;
+	struct cvmx_pip_raw_word_s            cn63xxp1;
+};
+typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t;
+
+/**
+ * cvmx_pip_sft_rst
+ *
+ * PIP_SFT_RST = PIP Soft Reset
+ *
+ * When written to a '1', resets the pip block
+ *
+ * Notes:
+ * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles
+ * in duration).  Although this will reset much of PIP's internal state, some
+ * CSRs will not reset.
+ *
+ * . PIP_BIST_STATUS
+ * . PIP_STAT0_PRT*
+ * . PIP_STAT1_PRT*
+ * . PIP_STAT2_PRT*
+ * . PIP_STAT3_PRT*
+ * . PIP_STAT4_PRT*
+ * . PIP_STAT5_PRT*
+ * . PIP_STAT6_PRT*
+ * . PIP_STAT7_PRT*
+ * . PIP_STAT8_PRT*
+ * . PIP_STAT9_PRT*
+ * . PIP_XSTAT0_PRT*
+ * . PIP_XSTAT1_PRT*
+ * . PIP_XSTAT2_PRT*
+ * . PIP_XSTAT3_PRT*
+ * . PIP_XSTAT4_PRT*
+ * . PIP_XSTAT5_PRT*
+ * . PIP_XSTAT6_PRT*
+ * . PIP_XSTAT7_PRT*
+ * . PIP_XSTAT8_PRT*
+ * . PIP_XSTAT9_PRT*
+ * . PIP_STAT_INB_PKTS*
+ * . PIP_STAT_INB_OCTS*
+ * . PIP_STAT_INB_ERRS*
+ * . PIP_TAG_INC*
+ */
+union cvmx_pip_sft_rst
+{
+	uint64_t u64;
+	struct cvmx_pip_sft_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rst                          : 1;  /**< Soft Reset */
+#else
+	uint64_t rst                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_pip_sft_rst_s             cn30xx;
+	struct cvmx_pip_sft_rst_s             cn31xx;
+	struct cvmx_pip_sft_rst_s             cn38xx;
+	struct cvmx_pip_sft_rst_s             cn50xx;
+	struct cvmx_pip_sft_rst_s             cn52xx;
+	struct cvmx_pip_sft_rst_s             cn52xxp1;
+	struct cvmx_pip_sft_rst_s             cn56xx;
+	struct cvmx_pip_sft_rst_s             cn56xxp1;
+	struct cvmx_pip_sft_rst_s             cn58xx;
+	struct cvmx_pip_sft_rst_s             cn58xxp1;
+	struct cvmx_pip_sft_rst_s             cn63xx;
+	struct cvmx_pip_sft_rst_s             cn63xxp1;
+};
+typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t;
+
+/**
+ * cvmx_pip_stat0_prt#
+ *
+ * PIP Statistics Counters
+ *
+ * Note: special stat counter behavior
+ *
+ * 1) Read and write operations must arbitrate for the statistics resources
+ *     along with the packet engines which are incrementing the counters.
+ *     In order to not drop packet information, the packet HW is always a
+ *     higher priority and the CSR requests will only be satisified when
+ *     there are idle cycles.  This can potentially cause long delays if the
+ *     system becomes full.
+ *
+ * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is
+ *     set, then all read accesses will clear the register.  In addition,
+ *     any write to a stats register will also reset the register to zero.
+ *     Please note that the clearing operations must obey rule \#1 above.
+ *
+ * 3) all counters are wrapping - software must ensure they are read periodically
+ *
+ * 4) The counters accumulate statistics for packets that are sent to PKI.  If
+ *    PTP_MODE is enabled, the 8B timestamp is prepended to the packet.  This
+ *    additional 8B of data is captured in the octet counts.
+ * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
+ */
+union cvmx_pip_stat0_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat0_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t drp_pkts                     : 32; /**< Inbound packets marked to be dropped by the IPD
+                                                         QOS widget per port */
+	uint64_t drp_octs                     : 32; /**< Inbound octets marked to be dropped by the IPD
+                                                         QOS widget per port */
+#else
+	uint64_t drp_octs                     : 32;
+	uint64_t drp_pkts                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat0_prtx_s          cn30xx;
+	struct cvmx_pip_stat0_prtx_s          cn31xx;
+	struct cvmx_pip_stat0_prtx_s          cn38xx;
+	struct cvmx_pip_stat0_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat0_prtx_s          cn50xx;
+	struct cvmx_pip_stat0_prtx_s          cn52xx;
+	struct cvmx_pip_stat0_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat0_prtx_s          cn56xx;
+	struct cvmx_pip_stat0_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat0_prtx_s          cn58xx;
+	struct cvmx_pip_stat0_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat0_prtx_s          cn63xx;
+	struct cvmx_pip_stat0_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t;
+
+/**
+ * cvmx_pip_stat1_prt#
+ *
+ * PIP_STAT1_PRTX = PIP_STAT_OCTS
+ *
+ */
+union cvmx_pip_stat1_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat1_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Number of octets received by PIP (good and bad) */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_stat1_prtx_s          cn30xx;
+	struct cvmx_pip_stat1_prtx_s          cn31xx;
+	struct cvmx_pip_stat1_prtx_s          cn38xx;
+	struct cvmx_pip_stat1_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat1_prtx_s          cn50xx;
+	struct cvmx_pip_stat1_prtx_s          cn52xx;
+	struct cvmx_pip_stat1_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat1_prtx_s          cn56xx;
+	struct cvmx_pip_stat1_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat1_prtx_s          cn58xx;
+	struct cvmx_pip_stat1_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat1_prtx_s          cn63xx;
+	struct cvmx_pip_stat1_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t;
+
+/**
+ * cvmx_pip_stat2_prt#
+ *
+ * PIP_STAT2_PRTX = PIP_STAT_PKTS     / PIP_STAT_RAW
+ *
+ */
+union cvmx_pip_stat2_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat2_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pkts                         : 32; /**< Number of packets processed by PIP */
+	uint64_t raw                          : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
+                                                         received by PIP per port */
+#else
+	uint64_t raw                          : 32;
+	uint64_t pkts                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat2_prtx_s          cn30xx;
+	struct cvmx_pip_stat2_prtx_s          cn31xx;
+	struct cvmx_pip_stat2_prtx_s          cn38xx;
+	struct cvmx_pip_stat2_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat2_prtx_s          cn50xx;
+	struct cvmx_pip_stat2_prtx_s          cn52xx;
+	struct cvmx_pip_stat2_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat2_prtx_s          cn56xx;
+	struct cvmx_pip_stat2_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat2_prtx_s          cn58xx;
+	struct cvmx_pip_stat2_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat2_prtx_s          cn63xx;
+	struct cvmx_pip_stat2_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t;
+
+/**
+ * cvmx_pip_stat3_prt#
+ *
+ * PIP_STAT3_PRTX = PIP_STAT_BCST     / PIP_STAT_MCST
+ *
+ */
+union cvmx_pip_stat3_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat3_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bcst                         : 32; /**< Number of indentified L2 broadcast packets
+                                                         Does not include multicast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+	uint64_t mcst                         : 32; /**< Number of indentified L2 multicast packets
+                                                         Does not include broadcast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+#else
+	uint64_t mcst                         : 32;
+	uint64_t bcst                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat3_prtx_s          cn30xx;
+	struct cvmx_pip_stat3_prtx_s          cn31xx;
+	struct cvmx_pip_stat3_prtx_s          cn38xx;
+	struct cvmx_pip_stat3_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat3_prtx_s          cn50xx;
+	struct cvmx_pip_stat3_prtx_s          cn52xx;
+	struct cvmx_pip_stat3_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat3_prtx_s          cn56xx;
+	struct cvmx_pip_stat3_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat3_prtx_s          cn58xx;
+	struct cvmx_pip_stat3_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat3_prtx_s          cn63xx;
+	struct cvmx_pip_stat3_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t;
+
+/**
+ * cvmx_pip_stat4_prt#
+ *
+ * PIP_STAT4_PRTX = PIP_STAT_HIST1    / PIP_STAT_HIST0
+ *
+ */
+union cvmx_pip_stat4_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat4_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h65to127                     : 32; /**< Number of 65-127B packets */
+	uint64_t h64                          : 32; /**< Number of 1-64B packets */
+#else
+	uint64_t h64                          : 32;
+	uint64_t h65to127                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat4_prtx_s          cn30xx;
+	struct cvmx_pip_stat4_prtx_s          cn31xx;
+	struct cvmx_pip_stat4_prtx_s          cn38xx;
+	struct cvmx_pip_stat4_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat4_prtx_s          cn50xx;
+	struct cvmx_pip_stat4_prtx_s          cn52xx;
+	struct cvmx_pip_stat4_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat4_prtx_s          cn56xx;
+	struct cvmx_pip_stat4_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat4_prtx_s          cn58xx;
+	struct cvmx_pip_stat4_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat4_prtx_s          cn63xx;
+	struct cvmx_pip_stat4_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t;
+
+/**
+ * cvmx_pip_stat5_prt#
+ *
+ * PIP_STAT5_PRTX = PIP_STAT_HIST3    / PIP_STAT_HIST2
+ *
+ */
+union cvmx_pip_stat5_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat5_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h256to511                    : 32; /**< Number of 256-511B packets */
+	uint64_t h128to255                    : 32; /**< Number of 128-255B packets */
+#else
+	uint64_t h128to255                    : 32;
+	uint64_t h256to511                    : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat5_prtx_s          cn30xx;
+	struct cvmx_pip_stat5_prtx_s          cn31xx;
+	struct cvmx_pip_stat5_prtx_s          cn38xx;
+	struct cvmx_pip_stat5_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat5_prtx_s          cn50xx;
+	struct cvmx_pip_stat5_prtx_s          cn52xx;
+	struct cvmx_pip_stat5_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat5_prtx_s          cn56xx;
+	struct cvmx_pip_stat5_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat5_prtx_s          cn58xx;
+	struct cvmx_pip_stat5_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat5_prtx_s          cn63xx;
+	struct cvmx_pip_stat5_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t;
+
+/**
+ * cvmx_pip_stat6_prt#
+ *
+ * PIP_STAT6_PRTX = PIP_STAT_HIST5    / PIP_STAT_HIST4
+ *
+ */
+union cvmx_pip_stat6_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat6_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h1024to1518                  : 32; /**< Number of 1024-1518B packets */
+	uint64_t h512to1023                   : 32; /**< Number of 512-1023B packets */
+#else
+	uint64_t h512to1023                   : 32;
+	uint64_t h1024to1518                  : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat6_prtx_s          cn30xx;
+	struct cvmx_pip_stat6_prtx_s          cn31xx;
+	struct cvmx_pip_stat6_prtx_s          cn38xx;
+	struct cvmx_pip_stat6_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat6_prtx_s          cn50xx;
+	struct cvmx_pip_stat6_prtx_s          cn52xx;
+	struct cvmx_pip_stat6_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat6_prtx_s          cn56xx;
+	struct cvmx_pip_stat6_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat6_prtx_s          cn58xx;
+	struct cvmx_pip_stat6_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat6_prtx_s          cn63xx;
+	struct cvmx_pip_stat6_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t;
+
+/**
+ * cvmx_pip_stat7_prt#
+ *
+ * PIP_STAT7_PRTX = PIP_STAT_FCS      / PIP_STAT_HIST6
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_stat7_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat7_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fcs                          : 32; /**< Number of packets with FCS or Align opcode errors */
+	uint64_t h1519                        : 32; /**< Number of 1519-max packets */
+#else
+	uint64_t h1519                        : 32;
+	uint64_t fcs                          : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat7_prtx_s          cn30xx;
+	struct cvmx_pip_stat7_prtx_s          cn31xx;
+	struct cvmx_pip_stat7_prtx_s          cn38xx;
+	struct cvmx_pip_stat7_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat7_prtx_s          cn50xx;
+	struct cvmx_pip_stat7_prtx_s          cn52xx;
+	struct cvmx_pip_stat7_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat7_prtx_s          cn56xx;
+	struct cvmx_pip_stat7_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat7_prtx_s          cn58xx;
+	struct cvmx_pip_stat7_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat7_prtx_s          cn63xx;
+	struct cvmx_pip_stat7_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t;
+
+/**
+ * cvmx_pip_stat8_prt#
+ *
+ * PIP_STAT8_PRTX = PIP_STAT_FRAG     / PIP_STAT_UNDER
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_stat8_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat8_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t frag                         : 32; /**< Number of packets with length < min and FCS error */
+	uint64_t undersz                      : 32; /**< Number of packets with length < min */
+#else
+	uint64_t undersz                      : 32;
+	uint64_t frag                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat8_prtx_s          cn30xx;
+	struct cvmx_pip_stat8_prtx_s          cn31xx;
+	struct cvmx_pip_stat8_prtx_s          cn38xx;
+	struct cvmx_pip_stat8_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat8_prtx_s          cn50xx;
+	struct cvmx_pip_stat8_prtx_s          cn52xx;
+	struct cvmx_pip_stat8_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat8_prtx_s          cn56xx;
+	struct cvmx_pip_stat8_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat8_prtx_s          cn58xx;
+	struct cvmx_pip_stat8_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat8_prtx_s          cn63xx;
+	struct cvmx_pip_stat8_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t;
+
+/**
+ * cvmx_pip_stat9_prt#
+ *
+ * PIP_STAT9_PRTX = PIP_STAT_JABBER   / PIP_STAT_OVER
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_stat9_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat9_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t jabber                       : 32; /**< Number of packets with length > max and FCS error */
+	uint64_t oversz                       : 32; /**< Number of packets with length > max */
+#else
+	uint64_t oversz                       : 32;
+	uint64_t jabber                       : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat9_prtx_s          cn30xx;
+	struct cvmx_pip_stat9_prtx_s          cn31xx;
+	struct cvmx_pip_stat9_prtx_s          cn38xx;
+	struct cvmx_pip_stat9_prtx_s          cn38xxp2;
+	struct cvmx_pip_stat9_prtx_s          cn50xx;
+	struct cvmx_pip_stat9_prtx_s          cn52xx;
+	struct cvmx_pip_stat9_prtx_s          cn52xxp1;
+	struct cvmx_pip_stat9_prtx_s          cn56xx;
+	struct cvmx_pip_stat9_prtx_s          cn56xxp1;
+	struct cvmx_pip_stat9_prtx_s          cn58xx;
+	struct cvmx_pip_stat9_prtx_s          cn58xxp1;
+	struct cvmx_pip_stat9_prtx_s          cn63xx;
+	struct cvmx_pip_stat9_prtx_s          cn63xxp1;
+};
+typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t;
+
+/**
+ * cvmx_pip_stat_ctl
+ *
+ * PIP_STAT_CTL = PIP's Stat Control Register
+ *
+ * Controls how the PIP statistics counters are handled.
+ */
+union cvmx_pip_stat_ctl
+{
+	uint64_t u64;
+	struct cvmx_pip_stat_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t rdclr                        : 1;  /**< Stat registers are read and clear
+                                                         0 = stat registers hold value when read
+                                                         1 = stat registers are cleared when read */
+#else
+	uint64_t rdclr                        : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_pip_stat_ctl_s            cn30xx;
+	struct cvmx_pip_stat_ctl_s            cn31xx;
+	struct cvmx_pip_stat_ctl_s            cn38xx;
+	struct cvmx_pip_stat_ctl_s            cn38xxp2;
+	struct cvmx_pip_stat_ctl_s            cn50xx;
+	struct cvmx_pip_stat_ctl_s            cn52xx;
+	struct cvmx_pip_stat_ctl_s            cn52xxp1;
+	struct cvmx_pip_stat_ctl_s            cn56xx;
+	struct cvmx_pip_stat_ctl_s            cn56xxp1;
+	struct cvmx_pip_stat_ctl_s            cn58xx;
+	struct cvmx_pip_stat_ctl_s            cn58xxp1;
+	struct cvmx_pip_stat_ctl_s            cn63xx;
+	struct cvmx_pip_stat_ctl_s            cn63xxp1;
+};
+typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t;
+
+/**
+ * cvmx_pip_stat_inb_errs#
+ *
+ * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+union cvmx_pip_stat_inb_errsx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_errsx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t errs                         : 16; /**< Number of packets with errors
+                                                         received by PIP */
+#else
+	uint64_t errs                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_errsx_s      cn30xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn31xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn38xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn38xxp2;
+	struct cvmx_pip_stat_inb_errsx_s      cn50xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn52xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn52xxp1;
+	struct cvmx_pip_stat_inb_errsx_s      cn56xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn56xxp1;
+	struct cvmx_pip_stat_inb_errsx_s      cn58xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_errsx_s      cn63xx;
+	struct cvmx_pip_stat_inb_errsx_s      cn63xxp1;
+};
+typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t;
+
+/**
+ * cvmx_pip_stat_inb_octs#
+ *
+ * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems. The OCTS will include the bytes from
+ * timestamp fields in PTP_MODE.
+ */
+union cvmx_pip_stat_inb_octsx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_octsx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Total number of octets from all packets received
+                                                         by PIP */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_octsx_s      cn30xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn31xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn38xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn38xxp2;
+	struct cvmx_pip_stat_inb_octsx_s      cn50xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn52xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn52xxp1;
+	struct cvmx_pip_stat_inb_octsx_s      cn56xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn56xxp1;
+	struct cvmx_pip_stat_inb_octsx_s      cn58xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_octsx_s      cn63xx;
+	struct cvmx_pip_stat_inb_octsx_s      cn63xxp1;
+};
+typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t;
+
+/**
+ * cvmx_pip_stat_inb_pkts#
+ *
+ * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port
+ *
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+union cvmx_pip_stat_inb_pktsx
+{
+	uint64_t u64;
+	struct cvmx_pip_stat_inb_pktsx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pkts                         : 32; /**< Number of packets without errors
+                                                         received by PIP */
+#else
+	uint64_t pkts                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pip_stat_inb_pktsx_s      cn30xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn31xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn38xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn38xxp2;
+	struct cvmx_pip_stat_inb_pktsx_s      cn50xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn52xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn52xxp1;
+	struct cvmx_pip_stat_inb_pktsx_s      cn56xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn56xxp1;
+	struct cvmx_pip_stat_inb_pktsx_s      cn58xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn58xxp1;
+	struct cvmx_pip_stat_inb_pktsx_s      cn63xx;
+	struct cvmx_pip_stat_inb_pktsx_s      cn63xxp1;
+};
+typedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t;
+
+/**
+ * cvmx_pip_tag_inc#
+ *
+ * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm
+ *
+ * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)
+ */
+union cvmx_pip_tag_incx
+{
+	uint64_t u64;
+	struct cvmx_pip_tag_incx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t en                           : 8;  /**< Which bytes to include in mask tag algorithm
+                                                         Broken into 4, 16-entry masks to cover 128B
+                                                         PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use
+                                                         registers  0-15 map to PIP_PRT_CFG[TAG_INC] == 0
+                                                         registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1
+                                                         registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2
+                                                         registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3
+                                                         [7] coresponds to the MSB of the 8B word
+                                                         [0] coresponds to the LSB of the 8B word
+                                                         If PTP_MODE, the 8B timestamp is prepended to the
+                                                          packet.  The EN byte masks should be adjusted to
+                                                          compensate for the additional timestamp field. */
+#else
+	uint64_t en                           : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pip_tag_incx_s            cn30xx;
+	struct cvmx_pip_tag_incx_s            cn31xx;
+	struct cvmx_pip_tag_incx_s            cn38xx;
+	struct cvmx_pip_tag_incx_s            cn38xxp2;
+	struct cvmx_pip_tag_incx_s            cn50xx;
+	struct cvmx_pip_tag_incx_s            cn52xx;
+	struct cvmx_pip_tag_incx_s            cn52xxp1;
+	struct cvmx_pip_tag_incx_s            cn56xx;
+	struct cvmx_pip_tag_incx_s            cn56xxp1;
+	struct cvmx_pip_tag_incx_s            cn58xx;
+	struct cvmx_pip_tag_incx_s            cn58xxp1;
+	struct cvmx_pip_tag_incx_s            cn63xx;
+	struct cvmx_pip_tag_incx_s            cn63xxp1;
+};
+typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t;
+
+/**
+ * cvmx_pip_tag_mask
+ *
+ * PIP_TAG_MASK = Mask bit in the tag generation
+ *
+ */
+union cvmx_pip_tag_mask
+{
+	uint64_t u64;
+	struct cvmx_pip_tag_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< When set, MASK clears individual bits of lower 16
+                                                         bits of the computed tag.  Does not effect RAW
+                                                         or INSTR HDR packets. */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pip_tag_mask_s            cn30xx;
+	struct cvmx_pip_tag_mask_s            cn31xx;
+	struct cvmx_pip_tag_mask_s            cn38xx;
+	struct cvmx_pip_tag_mask_s            cn38xxp2;
+	struct cvmx_pip_tag_mask_s            cn50xx;
+	struct cvmx_pip_tag_mask_s            cn52xx;
+	struct cvmx_pip_tag_mask_s            cn52xxp1;
+	struct cvmx_pip_tag_mask_s            cn56xx;
+	struct cvmx_pip_tag_mask_s            cn56xxp1;
+	struct cvmx_pip_tag_mask_s            cn58xx;
+	struct cvmx_pip_tag_mask_s            cn58xxp1;
+	struct cvmx_pip_tag_mask_s            cn63xx;
+	struct cvmx_pip_tag_mask_s            cn63xxp1;
+};
+typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t;
+
+/**
+ * cvmx_pip_tag_secret
+ *
+ * PIP_TAG_SECRET = Initial value in tag generation
+ *
+ * The source and destination IV's provide a mechanism for each Octeon to be unique.
+ */
+union cvmx_pip_tag_secret
+{
+	uint64_t u64;
+	struct cvmx_pip_tag_secret_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dst                          : 16; /**< Secret for the destination tuple tag CRC calc */
+	uint64_t src                          : 16; /**< Secret for the source tuple tag CRC calc */
+#else
+	uint64_t src                          : 16;
+	uint64_t dst                          : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pip_tag_secret_s          cn30xx;
+	struct cvmx_pip_tag_secret_s          cn31xx;
+	struct cvmx_pip_tag_secret_s          cn38xx;
+	struct cvmx_pip_tag_secret_s          cn38xxp2;
+	struct cvmx_pip_tag_secret_s          cn50xx;
+	struct cvmx_pip_tag_secret_s          cn52xx;
+	struct cvmx_pip_tag_secret_s          cn52xxp1;
+	struct cvmx_pip_tag_secret_s          cn56xx;
+	struct cvmx_pip_tag_secret_s          cn56xxp1;
+	struct cvmx_pip_tag_secret_s          cn58xx;
+	struct cvmx_pip_tag_secret_s          cn58xxp1;
+	struct cvmx_pip_tag_secret_s          cn63xx;
+	struct cvmx_pip_tag_secret_s          cn63xxp1;
+};
+typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t;
+
+/**
+ * cvmx_pip_todo_entry
+ *
+ * PIP_TODO_ENTRY = Head entry of the Todo list (debug only)
+ *
+ * Summary of the current packet that has completed and waiting to be processed
+ */
+union cvmx_pip_todo_entry
+{
+	uint64_t u64;
+	struct cvmx_pip_todo_entry_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t val                          : 1;  /**< Entry is valid */
+	uint64_t reserved_62_62               : 1;
+	uint64_t entry                        : 62; /**< Todo list entry summary */
+#else
+	uint64_t entry                        : 62;
+	uint64_t reserved_62_62               : 1;
+	uint64_t val                          : 1;
+#endif
+	} s;
+	struct cvmx_pip_todo_entry_s          cn30xx;
+	struct cvmx_pip_todo_entry_s          cn31xx;
+	struct cvmx_pip_todo_entry_s          cn38xx;
+	struct cvmx_pip_todo_entry_s          cn38xxp2;
+	struct cvmx_pip_todo_entry_s          cn50xx;
+	struct cvmx_pip_todo_entry_s          cn52xx;
+	struct cvmx_pip_todo_entry_s          cn52xxp1;
+	struct cvmx_pip_todo_entry_s          cn56xx;
+	struct cvmx_pip_todo_entry_s          cn56xxp1;
+	struct cvmx_pip_todo_entry_s          cn58xx;
+	struct cvmx_pip_todo_entry_s          cn58xxp1;
+	struct cvmx_pip_todo_entry_s          cn63xx;
+	struct cvmx_pip_todo_entry_s          cn63xxp1;
+};
+typedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t;
+
+/**
+ * cvmx_pip_xstat0_prt#
+ *
+ * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS
+ *
+ */
+union cvmx_pip_xstat0_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat0_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t drp_pkts                     : 32; /**< Inbound packets marked to be dropped by the IPD
+                                                         QOS widget per port */
+	uint64_t drp_octs                     : 32; /**< Inbound octets marked to be dropped by the IPD
+                                                         QOS widget per port */
+#else
+	uint64_t drp_octs                     : 32;
+	uint64_t drp_pkts                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat0_prtx_s         cn63xx;
+	struct cvmx_pip_xstat0_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t;
+
+/**
+ * cvmx_pip_xstat1_prt#
+ *
+ * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS
+ *
+ */
+union cvmx_pip_xstat1_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat1_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t octs                         : 48; /**< Number of octets received by PIP (good and bad) */
+#else
+	uint64_t octs                         : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pip_xstat1_prtx_s         cn63xx;
+	struct cvmx_pip_xstat1_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t;
+
+/**
+ * cvmx_pip_xstat2_prt#
+ *
+ * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS     / PIP_XSTAT_RAW
+ *
+ */
+union cvmx_pip_xstat2_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat2_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pkts                         : 32; /**< Number of packets processed by PIP */
+	uint64_t raw                          : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
+                                                         received by PIP per port */
+#else
+	uint64_t raw                          : 32;
+	uint64_t pkts                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat2_prtx_s         cn63xx;
+	struct cvmx_pip_xstat2_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t;
+
+/**
+ * cvmx_pip_xstat3_prt#
+ *
+ * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST     / PIP_XSTAT_MCST
+ *
+ */
+union cvmx_pip_xstat3_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat3_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bcst                         : 32; /**< Number of indentified L2 broadcast packets
+                                                         Does not include multicast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+	uint64_t mcst                         : 32; /**< Number of indentified L2 multicast packets
+                                                         Does not include broadcast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+#else
+	uint64_t mcst                         : 32;
+	uint64_t bcst                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat3_prtx_s         cn63xx;
+	struct cvmx_pip_xstat3_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t;
+
+/**
+ * cvmx_pip_xstat4_prt#
+ *
+ * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1    / PIP_XSTAT_HIST0
+ *
+ */
+union cvmx_pip_xstat4_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat4_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h65to127                     : 32; /**< Number of 65-127B packets */
+	uint64_t h64                          : 32; /**< Number of 1-64B packets */
+#else
+	uint64_t h64                          : 32;
+	uint64_t h65to127                     : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat4_prtx_s         cn63xx;
+	struct cvmx_pip_xstat4_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t;
+
+/**
+ * cvmx_pip_xstat5_prt#
+ *
+ * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3    / PIP_XSTAT_HIST2
+ *
+ */
+union cvmx_pip_xstat5_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat5_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h256to511                    : 32; /**< Number of 256-511B packets */
+	uint64_t h128to255                    : 32; /**< Number of 128-255B packets */
+#else
+	uint64_t h128to255                    : 32;
+	uint64_t h256to511                    : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat5_prtx_s         cn63xx;
+	struct cvmx_pip_xstat5_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t;
+
+/**
+ * cvmx_pip_xstat6_prt#
+ *
+ * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5    / PIP_XSTAT_HIST4
+ *
+ */
+union cvmx_pip_xstat6_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat6_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t h1024to1518                  : 32; /**< Number of 1024-1518B packets */
+	uint64_t h512to1023                   : 32; /**< Number of 512-1023B packets */
+#else
+	uint64_t h512to1023                   : 32;
+	uint64_t h1024to1518                  : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat6_prtx_s         cn63xx;
+	struct cvmx_pip_xstat6_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t;
+
+/**
+ * cvmx_pip_xstat7_prt#
+ *
+ * PIP_XSTAT7_PRTX = PIP_XSTAT_FCS      / PIP_XSTAT_HIST6
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_xstat7_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat7_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fcs                          : 32; /**< Number of packets with FCS or Align opcode errors */
+	uint64_t h1519                        : 32; /**< Number of 1519-max packets */
+#else
+	uint64_t h1519                        : 32;
+	uint64_t fcs                          : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat7_prtx_s         cn63xx;
+	struct cvmx_pip_xstat7_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t;
+
+/**
+ * cvmx_pip_xstat8_prt#
+ *
+ * PIP_XSTAT8_PRTX = PIP_XSTAT_FRAG     / PIP_XSTAT_UNDER
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_xstat8_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat8_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t frag                         : 32; /**< Number of packets with length < min and FCS error */
+	uint64_t undersz                      : 32; /**< Number of packets with length < min */
+#else
+	uint64_t undersz                      : 32;
+	uint64_t frag                         : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat8_prtx_s         cn63xx;
+	struct cvmx_pip_xstat8_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t;
+
+/**
+ * cvmx_pip_xstat9_prt#
+ *
+ * PIP_XSTAT9_PRTX = PIP_XSTAT_JABBER   / PIP_XSTAT_OVER
+ *
+ *
+ * Notes:
+ * Note: FCS is not checked on the PCI ports 32..35.
+ *
+ */
+union cvmx_pip_xstat9_prtx
+{
+	uint64_t u64;
+	struct cvmx_pip_xstat9_prtx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t jabber                       : 32; /**< Number of packets with length > max and FCS error */
+	uint64_t oversz                       : 32; /**< Number of packets with length > max */
+#else
+	uint64_t oversz                       : 32;
+	uint64_t jabber                       : 32;
+#endif
+	} s;
+	struct cvmx_pip_xstat9_prtx_s         cn63xx;
+	struct cvmx_pip_xstat9_prtx_s         cn63xxp1;
+};
+typedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pip.h b/sys/contrib/octeon-sdk/cvmx-pip.h
index 8dabca7..c6745c3 100644
--- a/sys/contrib/octeon-sdk/cvmx-pip.h
+++ b/sys/contrib/octeon-sdk/cvmx-pip.h
@@ -1,52 +1,49 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
  * Interface to the hardware Packet Input Processing unit.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49504 $<hr>
  */
 
 
@@ -55,48 +52,46 @@
 
 #include "cvmx-wqe.h"
 #include "cvmx-fpa.h"
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-pip-defs.h"
+#else
 #ifndef CVMX_DONT_INCLUDE_CONFIG
 #include "executive-config.h"
 #endif
+#endif
+
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-#define CVMX_PIP_NUM_INPUT_PORTS                40
-#define CVMX_PIP_NUM_WATCHERS                   4
-
-
-
+#define CVMX_PIP_NUM_INPUT_PORTS                44
 
-
-
-
-//
-// Encodes the different error and exception codes
-//
+/*
+ * Encodes the different error and exception codes
+ */
 typedef enum
 {
     CVMX_PIP_L4_NO_ERR       = 0ull,
-    //        1  = TCP (UDP) packet not long enough to cover TCP (UDP) header
+    /*        1  = TCP (UDP) packet not long enough to cover TCP (UDP) header */
     CVMX_PIP_L4_MAL_ERR     = 1ull,
-    //        2  = TCP/UDP checksum failure
+    /*        2  = TCP/UDP checksum failure */
     CVMX_PIP_CHK_ERR        = 2ull,
-    //        3  = TCP/UDP length check (TCP/UDP length does not match IP length)
+    /*        3  = TCP/UDP length check (TCP/UDP length does not match IP length) */
     CVMX_PIP_L4_LENGTH_ERR  = 3ull,
-    //        4  = illegal TCP/UDP port (either source or dest port is zero)
+    /*        4  = illegal TCP/UDP port (either source or dest port is zero) */
     CVMX_PIP_BAD_PRT_ERR    = 4ull,
-    //        8  = TCP flags = FIN only
+    /*        8  = TCP flags = FIN only */
     CVMX_PIP_TCP_FLG8_ERR   = 8ull,
-    //        9  = TCP flags = 0
+    /*        9  = TCP flags = 0 */
     CVMX_PIP_TCP_FLG9_ERR   = 9ull,
-    //        10 = TCP flags = FIN+RST+*
+    /*        10 = TCP flags = FIN+RST+* */
     CVMX_PIP_TCP_FLG10_ERR  = 10ull,
-    //        11 = TCP flags = SYN+URG+*
+    /*        11 = TCP flags = SYN+URG+* */
     CVMX_PIP_TCP_FLG11_ERR  = 11ull,
-    //        12 = TCP flags = SYN+RST+*
+    /*        12 = TCP flags = SYN+RST+* */
     CVMX_PIP_TCP_FLG12_ERR  = 12ull,
-    //        13 = TCP flags = SYN+FIN+*
+    /*        13 = TCP flags = SYN+FIN+* */
     CVMX_PIP_TCP_FLG13_ERR  = 13ull
 } cvmx_pip_l4_err_t;
 
@@ -104,17 +99,17 @@ typedef enum
 {
 
     CVMX_PIP_IP_NO_ERR      = 0ull,
-    //        1 = not IPv4 or IPv6
+    /*        1 = not IPv4 or IPv6 */
     CVMX_PIP_NOT_IP        = 1ull,
-    //        2 = IPv4 header checksum violation
+    /*        2 = IPv4 header checksum violation */
     CVMX_PIP_IPV4_HDR_CHK  = 2ull,
-    //        3 = malformed (packet not long enough to cover IP hdr)
+    /*        3 = malformed (packet not long enough to cover IP hdr) */
     CVMX_PIP_IP_MAL_HDR    = 3ull,
-    //        4 = malformed (packet not long enough to cover len in IP hdr)
+    /*        4 = malformed (packet not long enough to cover len in IP hdr) */
     CVMX_PIP_IP_MAL_PKT    = 4ull,
-    //        5 = TTL / hop count equal zero
+    /*        5 = TTL / hop count equal zero */
     CVMX_PIP_TTL_HOP       = 5ull,
-    //        6 = IPv4 options / IPv6 early extension headers
+    /*        6 = IPv4 options / IPv6 early extension headers */
     CVMX_PIP_OPTS          = 6ull
 } cvmx_pip_ip_exc_t;
 
@@ -133,31 +128,31 @@ typedef enum
      */
     CVMX_PIP_RX_NO_ERR      = 0ull,
 
-    CVMX_PIP_PARTIAL_ERR   = 1ull,  // RGM+SPI            1 = partially received packet (buffering/bandwidth not adequate)
-    CVMX_PIP_JABBER_ERR    = 2ull,  // RGM+SPI            2 = receive packet too large and truncated
-    CVMX_PIP_OVER_FCS_ERR  = 3ull,  // RGM                3 = max frame error (pkt len > max frame len) (with FCS error)
-    CVMX_PIP_OVER_ERR      = 4ull,  // RGM+SPI            4 = max frame error (pkt len > max frame len)
-    CVMX_PIP_ALIGN_ERR     = 5ull,  // RGM                5 = nibble error (data not byte multiple - 100M and 10M only)
-    CVMX_PIP_UNDER_FCS_ERR = 6ull,  // RGM                6 = min frame error (pkt len < min frame len) (with FCS error)
-    CVMX_PIP_GMX_FCS_ERR   = 7ull,  // RGM                7 = FCS error
-    CVMX_PIP_UNDER_ERR     = 8ull,  // RGM+SPI            8 = min frame error (pkt len < min frame len)
-    CVMX_PIP_EXTEND_ERR    = 9ull,  // RGM                9 = Frame carrier extend error
-    CVMX_PIP_LENGTH_ERR    = 10ull, // RGM               10 = length mismatch (len did not match len in L2 length/type)
-    CVMX_PIP_DAT_ERR       = 11ull, // RGM               11 = Frame error (some or all data bits marked err)
-    CVMX_PIP_DIP_ERR       = 11ull, //     SPI           11 = DIP4 error
-    CVMX_PIP_SKIP_ERR      = 12ull, // RGM               12 = packet was not large enough to pass the skipper - no inspection could occur
-    CVMX_PIP_NIBBLE_ERR    = 13ull, // RGM               13 = studder error (data not repeated - 100M and 10M only)
-    CVMX_PIP_PIP_FCS       = 16L, // RGM+SPI           16 = FCS error
-    CVMX_PIP_PIP_SKIP_ERR  = 17L, // RGM+SPI+PCI       17 = packet was not large enough to pass the skipper - no inspection could occur
-    CVMX_PIP_PIP_L2_MAL_HDR= 18L  // RGM+SPI+PCI       18 = malformed l2 (packet not long enough to cover L2 hdr)
-    // NOTES
-                                              //       xx = late collision (data received before collision)
-                                              //            late collisions cannot be detected by the receiver
-                                              //            they would appear as JAM bits which would appear as bad FCS
-                                              //            or carrier extend error which is CVMX_PIP_EXTEND_ERR
-
-
-
+    CVMX_PIP_PARTIAL_ERR   = 1ull,  /* RGM+SPI            1 = partially received packet (buffering/bandwidth not adequate) */
+    CVMX_PIP_JABBER_ERR    = 2ull,  /* RGM+SPI            2 = receive packet too large and truncated */
+    CVMX_PIP_OVER_FCS_ERR  = 3ull,  /* RGM                3 = max frame error (pkt len > max frame len) (with FCS error) */
+    CVMX_PIP_OVER_ERR      = 4ull,  /* RGM+SPI            4 = max frame error (pkt len > max frame len) */
+    CVMX_PIP_ALIGN_ERR     = 5ull,  /* RGM                5 = nibble error (data not byte multiple - 100M and 10M only) */
+    CVMX_PIP_UNDER_FCS_ERR = 6ull,  /* RGM                6 = min frame error (pkt len < min frame len) (with FCS error) */
+    CVMX_PIP_GMX_FCS_ERR   = 7ull,  /* RGM                7 = FCS error */
+    CVMX_PIP_UNDER_ERR     = 8ull,  /* RGM+SPI            8 = min frame error (pkt len < min frame len) */
+    CVMX_PIP_EXTEND_ERR    = 9ull,  /* RGM                9 = Frame carrier extend error */
+    CVMX_PIP_TERMINATE_ERR = 9ull,  /* XAUI               9 = Packet was terminated with an idle cycle */
+    CVMX_PIP_LENGTH_ERR    = 10ull, /* RGM               10 = length mismatch (len did not match len in L2 length/type) */
+    CVMX_PIP_DAT_ERR       = 11ull, /* RGM               11 = Frame error (some or all data bits marked err) */
+    CVMX_PIP_DIP_ERR       = 11ull, /*     SPI           11 = DIP4 error */
+    CVMX_PIP_SKIP_ERR      = 12ull, /* RGM               12 = packet was not large enough to pass the skipper - no inspection could occur */
+    CVMX_PIP_NIBBLE_ERR    = 13ull, /* RGM               13 = studder error (data not repeated - 100M and 10M only) */
+    CVMX_PIP_PIP_FCS       = 16L, /* RGM+SPI           16 = FCS error */
+    CVMX_PIP_PIP_SKIP_ERR  = 17L, /* RGM+SPI+PCI       17 = packet was not large enough to pass the skipper - no inspection could occur */
+    CVMX_PIP_PIP_L2_MAL_HDR= 18L, /* RGM+SPI+PCI       18 = malformed l2 (packet not long enough to cover L2 hdr) */
+    CVMX_PIP_PUNY_ERR      = 47L  /* SGMII             47 = PUNY error (packet was 4B or less when FCS stripping is enabled) */
+    /* NOTES
+     *       xx = late collision (data received before collision)
+     *            late collisions cannot be detected by the receiver
+     *            they would appear as JAM bits which would appear as bad FCS
+     *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+     */
 } cvmx_pip_rcv_err_t;
 
 /**
@@ -222,7 +217,23 @@ typedef union
         cvmx_pip_port_parse_mode_t  parse_mode  : 2;    /**< PIP parse mode for this packet */
         uint64_t                    reserved1   : 1;    /**< Must be zero */
         uint64_t                    skip_len    : 7;    /**< Skip amount, including this header, to the beginning of the packet */
-        uint64_t                    reserved2   : 6;    /**< Must be zero */
+        uint64_t                    reserved2   : 2;    /**< Must be zero */
+        uint64_t                    nqos        : 1;    /**< Must be 0 when PKT_INST_HDR[R] = 0.
+                                                             When set to 1, NQOS prevents PIP from directly using
+                                                             PKT_INST_HDR[QOS] for the QOS value in WQE.
+                                                             When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NQOS */
+        uint64_t                    ngrp        : 1;    /**< Must be 0 when PKT_INST_HDR[R] = 0.
+                                                             When set to 1, NGPR prevents PIP from directly using
+                                                             PKT_INST_HDR[GPR] for the GPR value in WQE.
+                                                             When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NGRP */
+        uint64_t                    ntt         : 1;    /**< Must be 0 when PKT_INST_HDR[R] = 0.
+                                                             When set to 1, NTT prevents PIP from directly using
+                                                             PKT_INST_HDR[TT] for the TT value in WQE.
+                                                             When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTT */
+        uint64_t                    ntag        : 1;    /**< Must be 0 when PKT_INST_HDR[R] = 0.
+                                                             When set to 1, NTAG prevents PIP from directly using
+                                                             PKT_INST_HDR[TAG] for the TAG value in WQE.
+                                                             When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTAG */
         uint64_t                    qos         : 3;    /**< POW input queue for this packet */
         uint64_t                    grp         : 4;    /**< POW input group for this packet */
         uint64_t                    rs          : 1;    /**< Flag to store this packet in the work queue entry, if possible */
@@ -231,7 +242,7 @@ typedef union
     } s;
 } cvmx_pip_pkt_inst_hdr_t;
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-pip-defs.h */
 
 /**
  * Configure an ethernet input port
@@ -242,8 +253,8 @@ typedef union
  *                 Port POW tagging configuration
  */
 static inline void cvmx_pip_config_port(uint64_t port_num,
-                                        cvmx_pip_port_cfg_t port_cfg,
-                                        cvmx_pip_port_tag_cfg_t port_tag_cfg)
+                                        cvmx_pip_prt_cfgx_t port_cfg,
+                                        cvmx_pip_prt_tagx_t port_tag_cfg)
 {
     cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
     cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
@@ -270,7 +281,7 @@ static inline void cvmx_pip_config_watcher(uint64_t watcher,
                                            cvmx_pip_qos_watch_types match_type,
                                            uint64_t match_value, uint64_t qos)
 {
-    cvmx_pip_port_watcher_cfg_t watcher_config;
+    cvmx_pip_qos_watchx_t watcher_config;
 
     watcher_config.u64 = 0;
     watcher_config.s.match_type = match_type;
@@ -340,16 +351,32 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, c
     pip_stat_ctl.s.rdclr = clear;
     cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
 
-    stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
-    stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
-    stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
-    stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
-    stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
-    stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
-    stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
-    stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
-    stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
-    stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+    if (port_num >= 40)
+    {
+        stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num));
+        stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num));
+        stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num));
+        stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num));
+        stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num));
+        stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num));
+        stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num));
+        stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num));
+        stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num));
+        stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num));
+    }
+    else
+    {
+        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
+        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
+        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
+        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
+        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
+        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
+        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
+        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
+        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
+        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+    }
     pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
     pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
     pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
@@ -377,18 +404,6 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, c
     status->inb_octets              = pip_stat_inb_octsx.s.octs;
     status->inb_errors              = pip_stat_inb_errsx.s.errs;
 
-    if (cvmx_octeon_is_pass1())
-    {
-        /* Kludge to fix Octeon Pass 1 errata - Drop counts don't work */
-        if (status->inb_packets > status->packets)
-            status->dropped_packets = status->inb_packets - status->packets;
-        else
-            status->dropped_packets = 0;
-        if (status->inb_octets - status->inb_packets*4 > status->octets)
-            status->dropped_octets = status->inb_octets - status->inb_packets*4 - status->octets;
-        else
-            status->dropped_octets = 0;
-    }
 }
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pko-defs.h b/sys/contrib/octeon-sdk/cvmx-pko-defs.h
new file mode 100644
index 0000000..8c626a6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pko-defs.h
@@ -0,0 +1,2652 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pko-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pko.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_PKO_TYPEDEFS_H__
+#define __CVMX_PKO_TYPEDEFS_H__
+
+#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
+#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
+#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
+#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
+#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
+#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
+#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
+#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001170ull);
+}
+#else
+#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
+#endif
+#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
+#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
+#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
+#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
+#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
+#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
+#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
+#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001010ull);
+}
+#else
+#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001018ull);
+}
+#else
+#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001020ull);
+}
+#else
+#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050001028ull);
+}
+#else
+#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
+#endif
+#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
+#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
+#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
+#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
+static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+		cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000020ull);
+}
+#else
+#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
+#endif
+#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
+}
+#else
+#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
+}
+#else
+#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
+}
+#else
+#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000050ull);
+}
+#else
+#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000058ull);
+}
+#else
+#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
+#endif
+#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
+#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
+#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
+#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
+#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000100ull);
+}
+#else
+#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
+#endif
+#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC()
+static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180050000060ull);
+}
+#else
+#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
+#endif
+
+/**
+ * cvmx_pko_mem_count0
+ *
+ * Notes:
+ * Total number of packets seen by PKO, per port
+ * A write to this address will clear the entry whose index is specified as COUNT[5:0].
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_count0
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_count0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t count                        : 32; /**< Total number of packets seen by PKO */
+#else
+	uint64_t count                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_mem_count0_s          cn30xx;
+	struct cvmx_pko_mem_count0_s          cn31xx;
+	struct cvmx_pko_mem_count0_s          cn38xx;
+	struct cvmx_pko_mem_count0_s          cn38xxp2;
+	struct cvmx_pko_mem_count0_s          cn50xx;
+	struct cvmx_pko_mem_count0_s          cn52xx;
+	struct cvmx_pko_mem_count0_s          cn52xxp1;
+	struct cvmx_pko_mem_count0_s          cn56xx;
+	struct cvmx_pko_mem_count0_s          cn56xxp1;
+	struct cvmx_pko_mem_count0_s          cn58xx;
+	struct cvmx_pko_mem_count0_s          cn58xxp1;
+	struct cvmx_pko_mem_count0_s          cn63xx;
+	struct cvmx_pko_mem_count0_s          cn63xxp1;
+};
+typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;
+
+/**
+ * cvmx_pko_mem_count1
+ *
+ * Notes:
+ * Total number of bytes seen by PKO, per port
+ * A write to this address will clear the entry whose index is specified as COUNT[5:0].
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_count1
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_count1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t count                        : 48; /**< Total number of bytes seen by PKO */
+#else
+	uint64_t count                        : 48;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pko_mem_count1_s          cn30xx;
+	struct cvmx_pko_mem_count1_s          cn31xx;
+	struct cvmx_pko_mem_count1_s          cn38xx;
+	struct cvmx_pko_mem_count1_s          cn38xxp2;
+	struct cvmx_pko_mem_count1_s          cn50xx;
+	struct cvmx_pko_mem_count1_s          cn52xx;
+	struct cvmx_pko_mem_count1_s          cn52xxp1;
+	struct cvmx_pko_mem_count1_s          cn56xx;
+	struct cvmx_pko_mem_count1_s          cn56xxp1;
+	struct cvmx_pko_mem_count1_s          cn58xx;
+	struct cvmx_pko_mem_count1_s          cn58xxp1;
+	struct cvmx_pko_mem_count1_s          cn63xx;
+	struct cvmx_pko_mem_count1_s          cn63xxp1;
+};
+typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;
+
+/**
+ * cvmx_pko_mem_debug0
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug0
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fau                          : 28; /**< Fetch and add command words */
+	uint64_t cmd                          : 14; /**< Command word */
+	uint64_t segs                         : 6;  /**< Number of segments/gather size */
+	uint64_t size                         : 16; /**< Packet length in bytes */
+#else
+	uint64_t size                         : 16;
+	uint64_t segs                         : 6;
+	uint64_t cmd                          : 14;
+	uint64_t fau                          : 28;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug0_s          cn30xx;
+	struct cvmx_pko_mem_debug0_s          cn31xx;
+	struct cvmx_pko_mem_debug0_s          cn38xx;
+	struct cvmx_pko_mem_debug0_s          cn38xxp2;
+	struct cvmx_pko_mem_debug0_s          cn50xx;
+	struct cvmx_pko_mem_debug0_s          cn52xx;
+	struct cvmx_pko_mem_debug0_s          cn52xxp1;
+	struct cvmx_pko_mem_debug0_s          cn56xx;
+	struct cvmx_pko_mem_debug0_s          cn56xxp1;
+	struct cvmx_pko_mem_debug0_s          cn58xx;
+	struct cvmx_pko_mem_debug0_s          cn58xxp1;
+	struct cvmx_pko_mem_debug0_s          cn63xx;
+	struct cvmx_pko_mem_debug0_s          cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;
+
+/**
+ * cvmx_pko_mem_debug1
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug1
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t ptr                          : 40; /**< Data pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug1_s          cn30xx;
+	struct cvmx_pko_mem_debug1_s          cn31xx;
+	struct cvmx_pko_mem_debug1_s          cn38xx;
+	struct cvmx_pko_mem_debug1_s          cn38xxp2;
+	struct cvmx_pko_mem_debug1_s          cn50xx;
+	struct cvmx_pko_mem_debug1_s          cn52xx;
+	struct cvmx_pko_mem_debug1_s          cn52xxp1;
+	struct cvmx_pko_mem_debug1_s          cn56xx;
+	struct cvmx_pko_mem_debug1_s          cn56xxp1;
+	struct cvmx_pko_mem_debug1_s          cn58xx;
+	struct cvmx_pko_mem_debug1_s          cn58xxp1;
+	struct cvmx_pko_mem_debug1_s          cn63xx;
+	struct cvmx_pko_mem_debug1_s          cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;
+
+/**
+ * cvmx_pko_mem_debug10
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug10
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug10_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug10_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fau                          : 28; /**< Fetch and add command words */
+	uint64_t cmd                          : 14; /**< Command word */
+	uint64_t segs                         : 6;  /**< Number of segments/gather size */
+	uint64_t size                         : 16; /**< Packet length in bytes */
+#else
+	uint64_t size                         : 16;
+	uint64_t segs                         : 6;
+	uint64_t cmd                          : 14;
+	uint64_t fau                          : 28;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug10_cn30xx    cn31xx;
+	struct cvmx_pko_mem_debug10_cn30xx    cn38xx;
+	struct cvmx_pko_mem_debug10_cn30xx    cn38xxp2;
+	struct cvmx_pko_mem_debug10_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t ptrs1                        : 17; /**< Internal state */
+	uint64_t reserved_17_31               : 15;
+	uint64_t ptrs2                        : 17; /**< Internal state */
+#else
+	uint64_t ptrs2                        : 17;
+	uint64_t reserved_17_31               : 15;
+	uint64_t ptrs1                        : 17;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn52xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn52xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cn56xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn56xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cn58xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug10_cn50xx    cn63xx;
+	struct cvmx_pko_mem_debug10_cn50xx    cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;
+
+/**
+ * cvmx_pko_mem_debug11
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.sta.state[22:0]
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug11
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug11_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t reserved_0_39                : 40;
+#else
+	uint64_t reserved_0_39                : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug11_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t ptr                          : 40; /**< Data pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug11_cn30xx    cn31xx;
+	struct cvmx_pko_mem_debug11_cn30xx    cn38xx;
+	struct cvmx_pko_mem_debug11_cn30xx    cn38xxp2;
+	struct cvmx_pko_mem_debug11_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t maj                          : 1;  /**< Internal state */
+	uint64_t uid                          : 3;  /**< Internal state */
+	uint64_t sop                          : 1;  /**< Internal state */
+	uint64_t len                          : 1;  /**< Internal state */
+	uint64_t chk                          : 1;  /**< Internal state */
+	uint64_t cnt                          : 13; /**< Internal state */
+	uint64_t mod                          : 3;  /**< Internal state */
+#else
+	uint64_t mod                          : 3;
+	uint64_t cnt                          : 13;
+	uint64_t chk                          : 1;
+	uint64_t len                          : 1;
+	uint64_t sop                          : 1;
+	uint64_t uid                          : 3;
+	uint64_t maj                          : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn52xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn52xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cn56xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn56xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cn58xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug11_cn50xx    cn63xx;
+	struct cvmx_pko_mem_debug11_cn50xx    cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;
+
+/**
+ * cvmx_pko_mem_debug12
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0]
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug12
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug12_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug12_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
+#else
+	uint64_t data                         : 64;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug12_cn30xx    cn31xx;
+	struct cvmx_pko_mem_debug12_cn30xx    cn38xx;
+	struct cvmx_pko_mem_debug12_cn30xx    cn38xxp2;
+	struct cvmx_pko_mem_debug12_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t fau                          : 28; /**< Fetch and add command words */
+	uint64_t cmd                          : 14; /**< Command word */
+	uint64_t segs                         : 6;  /**< Number of segments/gather size */
+	uint64_t size                         : 16; /**< Packet length in bytes */
+#else
+	uint64_t size                         : 16;
+	uint64_t segs                         : 6;
+	uint64_t cmd                          : 14;
+	uint64_t fau                          : 28;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug12_cn50xx    cn52xx;
+	struct cvmx_pko_mem_debug12_cn50xx    cn52xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cn56xx;
+	struct cvmx_pko_mem_debug12_cn50xx    cn56xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cn58xx;
+	struct cvmx_pko_mem_debug12_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug12_cn50xx    cn63xx;
+	struct cvmx_pko_mem_debug12_cn50xx    cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;
+
+/**
+ * cvmx_pko_mem_debug13
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0]
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug13
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug13_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t reserved_0_55                : 56;
+#else
+	uint64_t reserved_0_55                : 56;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug13_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_51_63               : 13;
+	uint64_t widx                         : 17; /**< PDB widx */
+	uint64_t ridx2                        : 17; /**< PDB ridx2 */
+	uint64_t widx2                        : 17; /**< PDB widx2 */
+#else
+	uint64_t widx2                        : 17;
+	uint64_t ridx2                        : 17;
+	uint64_t widx                         : 17;
+	uint64_t reserved_51_63               : 13;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug13_cn30xx    cn31xx;
+	struct cvmx_pko_mem_debug13_cn30xx    cn38xx;
+	struct cvmx_pko_mem_debug13_cn30xx    cn38xxp2;
+	struct cvmx_pko_mem_debug13_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t ptr                          : 40; /**< Data pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug13_cn50xx    cn52xx;
+	struct cvmx_pko_mem_debug13_cn50xx    cn52xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cn56xx;
+	struct cvmx_pko_mem_debug13_cn50xx    cn56xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cn58xx;
+	struct cvmx_pko_mem_debug13_cn50xx    cn58xxp1;
+	struct cvmx_pko_mem_debug13_cn50xx    cn63xx;
+	struct cvmx_pko_mem_debug13_cn50xx    cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;
+
+/**
+ * cvmx_pko_mem_debug14
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
+ * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug14
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug14_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug14_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t ridx                         : 17; /**< PDB ridx */
+#else
+	uint64_t ridx                         : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug14_cn30xx    cn31xx;
+	struct cvmx_pko_mem_debug14_cn30xx    cn38xx;
+	struct cvmx_pko_mem_debug14_cn30xx    cn38xxp2;
+	struct cvmx_pko_mem_debug14_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Command words */
+#else
+	uint64_t data                         : 64;
+#endif
+	} cn52xx;
+	struct cvmx_pko_mem_debug14_cn52xx    cn52xxp1;
+	struct cvmx_pko_mem_debug14_cn52xx    cn56xx;
+	struct cvmx_pko_mem_debug14_cn52xx    cn56xxp1;
+	struct cvmx_pko_mem_debug14_cn52xx    cn63xx;
+	struct cvmx_pko_mem_debug14_cn52xx    cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;
+
+/**
+ * cvmx_pko_mem_debug2
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug2
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t ptr                          : 40; /**< Data pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug2_s          cn30xx;
+	struct cvmx_pko_mem_debug2_s          cn31xx;
+	struct cvmx_pko_mem_debug2_s          cn38xx;
+	struct cvmx_pko_mem_debug2_s          cn38xxp2;
+	struct cvmx_pko_mem_debug2_s          cn50xx;
+	struct cvmx_pko_mem_debug2_s          cn52xx;
+	struct cvmx_pko_mem_debug2_s          cn52xxp1;
+	struct cvmx_pko_mem_debug2_s          cn56xx;
+	struct cvmx_pko_mem_debug2_s          cn56xxp1;
+	struct cvmx_pko_mem_debug2_s          cn58xx;
+	struct cvmx_pko_mem_debug2_s          cn58xxp1;
+	struct cvmx_pko_mem_debug2_s          cn63xx;
+	struct cvmx_pko_mem_debug2_s          cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;
+
+/**
+ * cvmx_pko_mem_debug3
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug3
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug3_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t i                            : 1;  /**< "I"  value used for free operation */
+	uint64_t back                         : 4;  /**< Back value used for free operation */
+	uint64_t pool                         : 3;  /**< Pool value used for free operation */
+	uint64_t size                         : 16; /**< Size in bytes */
+	uint64_t ptr                          : 40; /**< Data pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t pool                         : 3;
+	uint64_t back                         : 4;
+	uint64_t i                            : 1;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug3_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug3_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug3_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug3_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
+#else
+	uint64_t data                         : 64;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn52xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn52xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cn56xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn56xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug3_cn50xx     cn63xx;
+	struct cvmx_pko_mem_debug3_cn50xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;
+
+/**
+ * cvmx_pko_mem_debug4
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug4
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug4_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
+#else
+	uint64_t data                         : 64;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug4_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug4_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug4_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug4_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cmnd_segs                    : 3;  /**< Internal state */
+	uint64_t cmnd_siz                     : 16; /**< Internal state */
+	uint64_t cmnd_off                     : 6;  /**< Internal state */
+	uint64_t uid                          : 3;  /**< Internal state */
+	uint64_t dread_sop                    : 1;  /**< Internal state */
+	uint64_t init_dwrite                  : 1;  /**< Internal state */
+	uint64_t chk_once                     : 1;  /**< Internal state */
+	uint64_t chk_mode                     : 1;  /**< Internal state */
+	uint64_t active                       : 1;  /**< Internal state */
+	uint64_t static_p                     : 1;  /**< Internal state */
+	uint64_t qos                          : 3;  /**< Internal state */
+	uint64_t qcb_ridx                     : 5;  /**< Internal state */
+	uint64_t qid_off_max                  : 4;  /**< Internal state */
+	uint64_t qid_off                      : 4;  /**< Internal state */
+	uint64_t qid_base                     : 8;  /**< Internal state */
+	uint64_t wait                         : 1;  /**< Internal state */
+	uint64_t minor                        : 2;  /**< Internal state */
+	uint64_t major                        : 3;  /**< Internal state */
+#else
+	uint64_t major                        : 3;
+	uint64_t minor                        : 2;
+	uint64_t wait                         : 1;
+	uint64_t qid_base                     : 8;
+	uint64_t qid_off                      : 4;
+	uint64_t qid_off_max                  : 4;
+	uint64_t qcb_ridx                     : 5;
+	uint64_t qos                          : 3;
+	uint64_t static_p                     : 1;
+	uint64_t active                       : 1;
+	uint64_t chk_mode                     : 1;
+	uint64_t chk_once                     : 1;
+	uint64_t init_dwrite                  : 1;
+	uint64_t dread_sop                    : 1;
+	uint64_t uid                          : 3;
+	uint64_t cmnd_off                     : 6;
+	uint64_t cmnd_siz                     : 16;
+	uint64_t cmnd_segs                    : 3;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug4_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t curr_siz                     : 8;  /**< Internal state */
+	uint64_t curr_off                     : 16; /**< Internal state */
+	uint64_t cmnd_segs                    : 6;  /**< Internal state */
+	uint64_t cmnd_siz                     : 16; /**< Internal state */
+	uint64_t cmnd_off                     : 6;  /**< Internal state */
+	uint64_t uid                          : 2;  /**< Internal state */
+	uint64_t dread_sop                    : 1;  /**< Internal state */
+	uint64_t init_dwrite                  : 1;  /**< Internal state */
+	uint64_t chk_once                     : 1;  /**< Internal state */
+	uint64_t chk_mode                     : 1;  /**< Internal state */
+	uint64_t wait                         : 1;  /**< Internal state */
+	uint64_t minor                        : 2;  /**< Internal state */
+	uint64_t major                        : 3;  /**< Internal state */
+#else
+	uint64_t major                        : 3;
+	uint64_t minor                        : 2;
+	uint64_t wait                         : 1;
+	uint64_t chk_mode                     : 1;
+	uint64_t chk_once                     : 1;
+	uint64_t init_dwrite                  : 1;
+	uint64_t dread_sop                    : 1;
+	uint64_t uid                          : 2;
+	uint64_t cmnd_off                     : 6;
+	uint64_t cmnd_siz                     : 16;
+	uint64_t cmnd_segs                    : 6;
+	uint64_t curr_off                     : 16;
+	uint64_t curr_siz                     : 8;
+#endif
+	} cn52xx;
+	struct cvmx_pko_mem_debug4_cn52xx     cn52xxp1;
+	struct cvmx_pko_mem_debug4_cn52xx     cn56xx;
+	struct cvmx_pko_mem_debug4_cn52xx     cn56xxp1;
+	struct cvmx_pko_mem_debug4_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug4_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug4_cn52xx     cn63xx;
+	struct cvmx_pko_mem_debug4_cn52xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;
+
+/**
+ * cvmx_pko_mem_debug5
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
+ * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug5
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug5_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dwri_mod                     : 1;  /**< Dwrite mod */
+	uint64_t dwri_sop                     : 1;  /**< Dwrite sop needed */
+	uint64_t dwri_len                     : 1;  /**< Dwrite len */
+	uint64_t dwri_cnt                     : 13; /**< Dwrite count */
+	uint64_t cmnd_siz                     : 16; /**< Copy of cmnd.size */
+	uint64_t uid                          : 1;  /**< UID */
+	uint64_t xfer_wor                     : 1;  /**< Transfer work needed */
+	uint64_t xfer_dwr                     : 1;  /**< Transfer dwrite needed */
+	uint64_t cbuf_fre                     : 1;  /**< Cbuf needs free */
+	uint64_t reserved_27_27               : 1;
+	uint64_t chk_mode                     : 1;  /**< Checksum mode */
+	uint64_t active                       : 1;  /**< Port is active */
+	uint64_t qos                          : 3;  /**< Current QOS round */
+	uint64_t qcb_ridx                     : 5;  /**< Buffer read  index for QCB */
+	uint64_t qid_off                      : 3;  /**< Offset to be added to QID_BASE for current queue */
+	uint64_t qid_base                     : 7;  /**< Absolute QID of the queue array base = &QUEUES[0] */
+	uint64_t wait                         : 1;  /**< State wait when set */
+	uint64_t minor                        : 2;  /**< State minor code */
+	uint64_t major                        : 4;  /**< State major code */
+#else
+	uint64_t major                        : 4;
+	uint64_t minor                        : 2;
+	uint64_t wait                         : 1;
+	uint64_t qid_base                     : 7;
+	uint64_t qid_off                      : 3;
+	uint64_t qcb_ridx                     : 5;
+	uint64_t qos                          : 3;
+	uint64_t active                       : 1;
+	uint64_t chk_mode                     : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t cbuf_fre                     : 1;
+	uint64_t xfer_dwr                     : 1;
+	uint64_t xfer_wor                     : 1;
+	uint64_t uid                          : 1;
+	uint64_t cmnd_siz                     : 16;
+	uint64_t dwri_cnt                     : 13;
+	uint64_t dwri_len                     : 1;
+	uint64_t dwri_sop                     : 1;
+	uint64_t dwri_mod                     : 1;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug5_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug5_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug5_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug5_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t curr_ptr                     : 29; /**< Internal state */
+	uint64_t curr_siz                     : 16; /**< Internal state */
+	uint64_t curr_off                     : 16; /**< Internal state */
+	uint64_t cmnd_segs                    : 3;  /**< Internal state */
+#else
+	uint64_t cmnd_segs                    : 3;
+	uint64_t curr_off                     : 16;
+	uint64_t curr_siz                     : 16;
+	uint64_t curr_ptr                     : 29;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug5_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t nxt_inflt                    : 6;  /**< Internal state */
+	uint64_t curr_ptr                     : 40; /**< Internal state */
+	uint64_t curr_siz                     : 8;  /**< Internal state */
+#else
+	uint64_t curr_siz                     : 8;
+	uint64_t curr_ptr                     : 40;
+	uint64_t nxt_inflt                    : 6;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} cn52xx;
+	struct cvmx_pko_mem_debug5_cn52xx     cn52xxp1;
+	struct cvmx_pko_mem_debug5_cn52xx     cn56xx;
+	struct cvmx_pko_mem_debug5_cn52xx     cn56xxp1;
+	struct cvmx_pko_mem_debug5_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug5_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug5_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t ptp                          : 1;  /**< Internal state */
+	uint64_t major_3                      : 1;  /**< Internal state */
+	uint64_t nxt_inflt                    : 6;  /**< Internal state */
+	uint64_t curr_ptr                     : 40; /**< Internal state */
+	uint64_t curr_siz                     : 8;  /**< Internal state */
+#else
+	uint64_t curr_siz                     : 8;
+	uint64_t curr_ptr                     : 40;
+	uint64_t nxt_inflt                    : 6;
+	uint64_t major_3                      : 1;
+	uint64_t ptp                          : 1;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} cn63xx;
+	struct cvmx_pko_mem_debug5_cn63xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;
+
+/**
+ * cvmx_pko_mem_debug6
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug6
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t qid_offres                   : 4;  /**< Internal state */
+	uint64_t qid_offths                   : 4;  /**< Internal state */
+	uint64_t preempter                    : 1;  /**< Internal state */
+	uint64_t preemptee                    : 1;  /**< Internal state */
+	uint64_t preempted                    : 1;  /**< Internal state */
+	uint64_t active                       : 1;  /**< Internal state */
+	uint64_t statc                        : 1;  /**< Internal state */
+	uint64_t qos                          : 3;  /**< Internal state */
+	uint64_t qcb_ridx                     : 5;  /**< Internal state */
+	uint64_t qid_offmax                   : 4;  /**< Internal state */
+	uint64_t reserved_0_11                : 12;
+#else
+	uint64_t reserved_0_11                : 12;
+	uint64_t qid_offmax                   : 4;
+	uint64_t qcb_ridx                     : 5;
+	uint64_t qos                          : 3;
+	uint64_t statc                        : 1;
+	uint64_t active                       : 1;
+	uint64_t preempted                    : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t preempter                    : 1;
+	uint64_t qid_offths                   : 4;
+	uint64_t qid_offres                   : 4;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug6_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t qid_offm                     : 3;  /**< Qid offset max */
+	uint64_t static_p                     : 1;  /**< Static port when set */
+	uint64_t work_min                     : 3;  /**< Work minor */
+	uint64_t dwri_chk                     : 1;  /**< Dwrite checksum mode */
+	uint64_t dwri_uid                     : 1;  /**< Dwrite UID */
+	uint64_t dwri_mod                     : 2;  /**< Dwrite mod */
+#else
+	uint64_t dwri_mod                     : 2;
+	uint64_t dwri_uid                     : 1;
+	uint64_t dwri_chk                     : 1;
+	uint64_t work_min                     : 3;
+	uint64_t static_p                     : 1;
+	uint64_t qid_offm                     : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug6_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug6_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug6_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug6_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t curr_ptr                     : 11; /**< Internal state */
+#else
+	uint64_t curr_ptr                     : 11;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug6_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_37_63               : 27;
+	uint64_t qid_offres                   : 4;  /**< Internal state */
+	uint64_t qid_offths                   : 4;  /**< Internal state */
+	uint64_t preempter                    : 1;  /**< Internal state */
+	uint64_t preemptee                    : 1;  /**< Internal state */
+	uint64_t preempted                    : 1;  /**< Internal state */
+	uint64_t active                       : 1;  /**< Internal state */
+	uint64_t statc                        : 1;  /**< Internal state */
+	uint64_t qos                          : 3;  /**< Internal state */
+	uint64_t qcb_ridx                     : 5;  /**< Internal state */
+	uint64_t qid_offmax                   : 4;  /**< Internal state */
+	uint64_t qid_off                      : 4;  /**< Internal state */
+	uint64_t qid_base                     : 8;  /**< Internal state */
+#else
+	uint64_t qid_base                     : 8;
+	uint64_t qid_off                      : 4;
+	uint64_t qid_offmax                   : 4;
+	uint64_t qcb_ridx                     : 5;
+	uint64_t qos                          : 3;
+	uint64_t statc                        : 1;
+	uint64_t active                       : 1;
+	uint64_t preempted                    : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t preempter                    : 1;
+	uint64_t qid_offths                   : 4;
+	uint64_t qid_offres                   : 4;
+	uint64_t reserved_37_63               : 27;
+#endif
+	} cn52xx;
+	struct cvmx_pko_mem_debug6_cn52xx     cn52xxp1;
+	struct cvmx_pko_mem_debug6_cn52xx     cn56xx;
+	struct cvmx_pko_mem_debug6_cn52xx     cn56xxp1;
+	struct cvmx_pko_mem_debug6_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug6_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug6_cn52xx     cn63xx;
+	struct cvmx_pko_mem_debug6_cn52xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;
+
+/**
+ * cvmx_pko_mem_debug7
+ *
+ * Notes:
+ * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug7
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
+	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
+	uint64_t reserved_0_57                : 58;
+#else
+	uint64_t reserved_0_57                : 58;
+	uint64_t tail                         : 1;
+	uint64_t qos                          : 5;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug7_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t dwb                          : 9;  /**< Calculated DWB count used for free operation */
+	uint64_t start                        : 33; /**< Calculated start address used for free operation */
+	uint64_t size                         : 16; /**< Packet length in bytes */
+#else
+	uint64_t size                         : 16;
+	uint64_t start                        : 33;
+	uint64_t dwb                          : 9;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug7_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug7_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug7_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug7_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
+	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
+	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
+	uint64_t buf_ptr                      : 33; /**< Command word pointer */
+	uint64_t qcb_widx                     : 6;  /**< Buffer write index for QCB */
+	uint64_t qcb_ridx                     : 6;  /**< Buffer read  index for QCB */
+#else
+	uint64_t qcb_ridx                     : 6;
+	uint64_t qcb_widx                     : 6;
+	uint64_t buf_ptr                      : 33;
+	uint64_t buf_siz                      : 13;
+	uint64_t tail                         : 1;
+	uint64_t qos                          : 5;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug7_cn50xx     cn52xx;
+	struct cvmx_pko_mem_debug7_cn50xx     cn52xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cn56xx;
+	struct cvmx_pko_mem_debug7_cn50xx     cn56xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug7_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug7_cn50xx     cn63xx;
+	struct cvmx_pko_mem_debug7_cn50xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;
+
+/**
+ * cvmx_pko_mem_debug8
+ *
+ * Notes:
+ * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug8
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug8_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
+	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
+	uint64_t reserved_0_44                : 45;
+#else
+	uint64_t reserved_0_44                : 45;
+	uint64_t buf_siz                      : 13;
+	uint64_t tail                         : 1;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug8_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
+	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
+	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
+	uint64_t buf_ptr                      : 33; /**< Command word pointer */
+	uint64_t qcb_widx                     : 6;  /**< Buffer write index for QCB */
+	uint64_t qcb_ridx                     : 6;  /**< Buffer read  index for QCB */
+#else
+	uint64_t qcb_ridx                     : 6;
+	uint64_t qcb_widx                     : 6;
+	uint64_t buf_ptr                      : 33;
+	uint64_t buf_siz                      : 13;
+	uint64_t tail                         : 1;
+	uint64_t qos                          : 5;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug8_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug8_cn30xx     cn38xx;
+	struct cvmx_pko_mem_debug8_cn30xx     cn38xxp2;
+	struct cvmx_pko_mem_debug8_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t static_p                     : 1;  /**< Static priority */
+	uint64_t s_tail                       : 1;  /**< Static tail */
+	uint64_t static_q                     : 1;  /**< Static priority */
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t static_p                     : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t doorbell                     : 20;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug8_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t preempter                    : 1;  /**< Preempter */
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t preemptee                    : 1;  /**< Preemptee */
+	uint64_t static_p                     : 1;  /**< Static priority */
+	uint64_t s_tail                       : 1;  /**< Static tail */
+	uint64_t static_q                     : 1;  /**< Static priority */
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t static_p                     : 1;
+	uint64_t preemptee                    : 1;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t doorbell                     : 20;
+	uint64_t preempter                    : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn52xx;
+	struct cvmx_pko_mem_debug8_cn52xx     cn52xxp1;
+	struct cvmx_pko_mem_debug8_cn52xx     cn56xx;
+	struct cvmx_pko_mem_debug8_cn52xx     cn56xxp1;
+	struct cvmx_pko_mem_debug8_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug8_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug8_cn52xx     cn63xx;
+	struct cvmx_pko_mem_debug8_cn52xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;
+
+/**
+ * cvmx_pko_mem_debug9
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_pko_mem_debug9
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_debug9_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t ptrs0                        : 17; /**< Internal state */
+	uint64_t reserved_0_31                : 32;
+#else
+	uint64_t reserved_0_31                : 32;
+	uint64_t ptrs0                        : 17;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_pko_mem_debug9_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t s_tail                       : 1;  /**< reads as zero (S_TAIL cannot be read) */
+	uint64_t static_q                     : 1;  /**< reads as zero (STATIC_Q cannot be read) */
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t doorbell                     : 20;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn30xx;
+	struct cvmx_pko_mem_debug9_cn30xx     cn31xx;
+	struct cvmx_pko_mem_debug9_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t doorbell                     : 20; /**< Doorbell count */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t static_p                     : 1;  /**< Static priority (port) */
+	uint64_t s_tail                       : 1;  /**< Static tail */
+	uint64_t static_q                     : 1;  /**< Static priority */
+	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
+#else
+	uint64_t qos                          : 3;
+	uint64_t static_q                     : 1;
+	uint64_t s_tail                       : 1;
+	uint64_t static_p                     : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t doorbell                     : 20;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn38xx;
+	struct cvmx_pko_mem_debug9_cn38xx     cn38xxp2;
+	struct cvmx_pko_mem_debug9_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t ptrs0                        : 17; /**< Internal state */
+	uint64_t reserved_17_31               : 15;
+	uint64_t ptrs3                        : 17; /**< Internal state */
+#else
+	uint64_t ptrs3                        : 17;
+	uint64_t reserved_17_31               : 15;
+	uint64_t ptrs0                        : 17;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} cn50xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn52xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn52xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cn56xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn56xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cn58xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn58xxp1;
+	struct cvmx_pko_mem_debug9_cn50xx     cn63xx;
+	struct cvmx_pko_mem_debug9_cn50xx     cn63xxp1;
+};
+typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
+
+/**
+ * cvmx_pko_mem_port_ptrs
+ *
+ * Notes:
+ * Sets the port to engine mapping, per port.  Ports marked as static priority need not be contiguous,
+ * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff.  If EID==8
+ * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface.
+ * EID==15 can be used for unused PKO-internal ports.
+ * BP_PORT==63 means that the PKO-internal port is not backpressured.
+ * BP_PORTs are assumed to belong to an interface as follows:
+ *   42 <= BP_PORT < 44 -> srio       interface 1
+ *   40 <= BP_PORT < 42 -> srio       interface 0
+ *   36 <= BP_PORT < 40 -> loopback   interface
+ *   32 <= BP_PORT < 36 -> PCIe       interface
+ *   0  <= BP_PORT < 16 -> SGMII/Xaui interface 0
+ *
+ * Note that the SRIO interfaces do not actually provide backpressure.  Thus, ports that use
+ * 40 <= BP_PORT < 44 for backpressure will never be backpressured.
+ *
+ * The reset configuration is the following:
+ *   PID EID(ext port) BP_PORT QOS_MASK STATIC_P
+ *   -------------------------------------------
+ *     0   0( 0)             0     0xff        0
+ *     1   1( 1)             1     0xff        0
+ *     2   2( 2)             2     0xff        0
+ *     3   3( 3)             3     0xff        0
+ *     4   0( 0)             4     0xff        0
+ *     5   1( 1)             5     0xff        0
+ *     6   2( 2)             6     0xff        0
+ *     7   3( 3)             7     0xff        0
+ *     8   0( 0)             8     0xff        0
+ *     9   1( 1)             9     0xff        0
+ *    10   2( 2)            10     0xff        0
+ *    11   3( 3)            11     0xff        0
+ *    12   0( 0)            12     0xff        0
+ *    13   1( 1)            13     0xff        0
+ *    14   2( 2)            14     0xff        0
+ *    15   3( 3)            15     0xff        0
+ *   -------------------------------------------
+ *    16   0( 0)             0     0xff        0
+ *    17   1( 1)             1     0xff        0
+ *    18   2( 2)             2     0xff        0
+ *    19   3( 3)             3     0xff        0
+ *    20   0( 0)             4     0xff        0
+ *    21   1( 1)             5     0xff        0
+ *    22   2( 2)             6     0xff        0
+ *    23   3( 3)             7     0xff        0
+ *    24   0( 0)             8     0xff        0
+ *    25   1( 1)             9     0xff        0
+ *    26   2( 2)            10     0xff        0
+ *    27   3( 3)            11     0xff        0
+ *    28   0( 0)            12     0xff        0
+ *    29   1( 1)            13     0xff        0
+ *    30   2( 2)            14     0xff        0
+ *    31   3( 3)            15     0xff        0
+ *   -------------------------------------------
+ *    32   8(32)            32     0xff        0
+ *    33   8(33)            33     0xff        0
+ *    34   8(34)            34     0xff        0
+ *    35   8(35)            35     0xff        0
+ *   -------------------------------------------
+ *    36   9(36)            36     0xff        0
+ *    37   9(37)            37     0xff        0
+ *    38   9(38)            38     0xff        0
+ *    39   9(39)            39     0xff        0
+ *   -------------------------------------------
+ *    40  10(40)            40     0xff        0
+ *    41  10(41)            41     0xff        0
+ *   -------------------------------------------
+ *    42  11(42)            42     0xff        0
+ *    43  11(43)            43     0xff        0
+ *
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_port_ptrs
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_port_ptrs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_62_63               : 2;
+	uint64_t static_p                     : 1;  /**< Set if this PID has static priority */
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t reserved_16_52               : 37;
+	uint64_t bp_port                      : 6;  /**< PID listens to BP_PORT for per-packet backpressure
+                                                         Legal BP_PORTs: 0-15, 32-43, 63 (63 means no BP) */
+	uint64_t eid                          : 4;  /**< Engine ID to which this port is mapped
+                                                         Legal EIDs: 0-3, 8-11, 15 (15 only if port not used) */
+	uint64_t pid                          : 6;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 6;
+	uint64_t eid                          : 4;
+	uint64_t bp_port                      : 6;
+	uint64_t reserved_16_52               : 37;
+	uint64_t qos_mask                     : 8;
+	uint64_t static_p                     : 1;
+	uint64_t reserved_62_63               : 2;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_ptrs_s       cn52xx;
+	struct cvmx_pko_mem_port_ptrs_s       cn52xxp1;
+	struct cvmx_pko_mem_port_ptrs_s       cn56xx;
+	struct cvmx_pko_mem_port_ptrs_s       cn56xxp1;
+	struct cvmx_pko_mem_port_ptrs_s       cn63xx;
+	struct cvmx_pko_mem_port_ptrs_s       cn63xxp1;
+};
+typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;
+
+/**
+ * cvmx_pko_mem_port_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per port.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_PORT_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other port state.  The engine to which port PID is mapped is engine
+ * EID.  Note that the port to engine mapping must be the same as was previously programmed via the
+ * PKO_MEM_PORT_PTRS CSR.
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_port_qos
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_port_qos_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t reserved_10_52               : 43;
+	uint64_t eid                          : 4;  /**< Engine ID to which this port is mapped
+                                                         Legal EIDs: 0-3, 8-11 */
+	uint64_t pid                          : 6;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 6;
+	uint64_t eid                          : 4;
+	uint64_t reserved_10_52               : 43;
+	uint64_t qos_mask                     : 8;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_qos_s        cn52xx;
+	struct cvmx_pko_mem_port_qos_s        cn52xxp1;
+	struct cvmx_pko_mem_port_qos_s        cn56xx;
+	struct cvmx_pko_mem_port_qos_s        cn56xxp1;
+	struct cvmx_pko_mem_port_qos_s        cn63xx;
+	struct cvmx_pko_mem_port_qos_s        cn63xxp1;
+};
+typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;
+
+/**
+ * cvmx_pko_mem_port_rate0
+ *
+ * Notes:
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_port_rate0
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_port_rate0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_51_63               : 13;
+	uint64_t rate_word                    : 19; /**< Rate limiting adder per 8 byte */
+	uint64_t rate_pkt                     : 24; /**< Rate limiting adder per packet */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pid                          : 6;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rate_pkt                     : 24;
+	uint64_t rate_word                    : 19;
+	uint64_t reserved_51_63               : 13;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_rate0_s      cn52xx;
+	struct cvmx_pko_mem_port_rate0_s      cn52xxp1;
+	struct cvmx_pko_mem_port_rate0_s      cn56xx;
+	struct cvmx_pko_mem_port_rate0_s      cn56xxp1;
+	struct cvmx_pko_mem_port_rate0_s      cn63xx;
+	struct cvmx_pko_mem_port_rate0_s      cn63xxp1;
+};
+typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;
+
+/**
+ * cvmx_pko_mem_port_rate1
+ *
+ * Notes:
+ * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding
+ * accumulator to zero.
+ * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_port_rate1
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_port_rate1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rate_lim                     : 24; /**< Rate limiting accumulator limit */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pid                          : 6;  /**< Port ID[5:0] */
+#else
+	uint64_t pid                          : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rate_lim                     : 24;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_mem_port_rate1_s      cn52xx;
+	struct cvmx_pko_mem_port_rate1_s      cn52xxp1;
+	struct cvmx_pko_mem_port_rate1_s      cn56xx;
+	struct cvmx_pko_mem_port_rate1_s      cn56xxp1;
+	struct cvmx_pko_mem_port_rate1_s      cn63xx;
+	struct cvmx_pko_mem_port_rate1_s      cn63xxp1;
+};
+typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;
+
+/**
+ * cvmx_pko_mem_queue_ptrs
+ *
+ * Notes:
+ * Sets the queue to port mapping and the initial command buffer pointer, per queue
+ * Each queue may map to at most one port.  No more than 16 queues may map to a port.  The set of
+ * queues that is mapped to a port must be a contiguous array of queues.  The port to which queue QID
+ * is mapped is port PID.  The index of queue QID in port PID's queue list is IDX.  The last queue in
+ * port PID's queue array must have its TAIL bit set.  Unused queues must be mapped to port 63.
+ * STATIC_Q marks queue QID as having static priority.  STATIC_P marks the port PID to which QID is
+ * mapped as having at least one queue with static priority.  If any QID that maps to PID has static
+ * priority, then all QID that map to PID must have STATIC_P set.  Queues marked as static priority
+ * must be contiguous and begin at IDX 0.  The last queue that is marked as having static priority
+ * must have its S_TAIL bit set.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_queue_ptrs
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_queue_ptrs_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t s_tail                       : 1;  /**< Set if this QID is the tail of the static queues */
+	uint64_t static_p                     : 1;  /**< Set if any QID in this PID has static priority */
+	uint64_t static_q                     : 1;  /**< Set if this QID has static priority */
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t buf_ptr                      : 36; /**< Command buffer pointer, <23:17> MBZ */
+	uint64_t tail                         : 1;  /**< Set if this QID is the tail of the queue array */
+	uint64_t index                        : 3;  /**< Index[2:0] (distance from head) in the queue array */
+	uint64_t port                         : 6;  /**< Port ID to which this queue is mapped */
+	uint64_t queue                        : 7;  /**< Queue ID[6:0] */
+#else
+	uint64_t queue                        : 7;
+	uint64_t port                         : 6;
+	uint64_t index                        : 3;
+	uint64_t tail                         : 1;
+	uint64_t buf_ptr                      : 36;
+	uint64_t qos_mask                     : 8;
+	uint64_t static_q                     : 1;
+	uint64_t static_p                     : 1;
+	uint64_t s_tail                       : 1;
+#endif
+	} s;
+	struct cvmx_pko_mem_queue_ptrs_s      cn30xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn31xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn38xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn38xxp2;
+	struct cvmx_pko_mem_queue_ptrs_s      cn50xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn52xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn52xxp1;
+	struct cvmx_pko_mem_queue_ptrs_s      cn56xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn56xxp1;
+	struct cvmx_pko_mem_queue_ptrs_s      cn58xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn58xxp1;
+	struct cvmx_pko_mem_queue_ptrs_s      cn63xx;
+	struct cvmx_pko_mem_queue_ptrs_s      cn63xxp1;
+};
+typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;
+
+/**
+ * cvmx_pko_mem_queue_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per queue.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_QUEUE_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other queue state.  The port to which queue QID is mapped is port
+ * PID.  Note that the queue to port mapping must be the same as was previously programmed via the
+ * PKO_MEM_QUEUE_PTRS CSR.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_pko_mem_queue_qos
+{
+	uint64_t u64;
+	struct cvmx_pko_mem_queue_qos_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
+	uint64_t reserved_13_52               : 40;
+	uint64_t pid                          : 6;  /**< Port ID to which this queue is mapped */
+	uint64_t qid                          : 7;  /**< Queue ID */
+#else
+	uint64_t qid                          : 7;
+	uint64_t pid                          : 6;
+	uint64_t reserved_13_52               : 40;
+	uint64_t qos_mask                     : 8;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_pko_mem_queue_qos_s       cn30xx;
+	struct cvmx_pko_mem_queue_qos_s       cn31xx;
+	struct cvmx_pko_mem_queue_qos_s       cn38xx;
+	struct cvmx_pko_mem_queue_qos_s       cn38xxp2;
+	struct cvmx_pko_mem_queue_qos_s       cn50xx;
+	struct cvmx_pko_mem_queue_qos_s       cn52xx;
+	struct cvmx_pko_mem_queue_qos_s       cn52xxp1;
+	struct cvmx_pko_mem_queue_qos_s       cn56xx;
+	struct cvmx_pko_mem_queue_qos_s       cn56xxp1;
+	struct cvmx_pko_mem_queue_qos_s       cn58xx;
+	struct cvmx_pko_mem_queue_qos_s       cn58xxp1;
+	struct cvmx_pko_mem_queue_qos_s       cn63xx;
+	struct cvmx_pko_mem_queue_qos_s       cn63xxp1;
+};
+typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t;
+
+/**
+ * cvmx_pko_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_pko_reg_bist_result
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_bist_result_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_bist_result_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_27_63               : 37;
+	uint64_t psb2                         : 5;  /**< BiST result of the PSB   memories (0=pass, !0=fail) */
+	uint64_t count                        : 1;  /**< BiST result of the COUNT memories (0=pass, !0=fail) */
+	uint64_t rif                          : 1;  /**< BiST result of the RIF   memories (0=pass, !0=fail) */
+	uint64_t wif                          : 1;  /**< BiST result of the WIF   memories (0=pass, !0=fail) */
+	uint64_t ncb                          : 1;  /**< BiST result of the NCB   memories (0=pass, !0=fail) */
+	uint64_t out                          : 1;  /**< BiST result of the OUT   memories (0=pass, !0=fail) */
+	uint64_t crc                          : 1;  /**< BiST result of the CRC   memories (0=pass, !0=fail) */
+	uint64_t chk                          : 1;  /**< BiST result of the CHK   memories (0=pass, !0=fail) */
+	uint64_t qsb                          : 2;  /**< BiST result of the QSB   memories (0=pass, !0=fail) */
+	uint64_t qcb                          : 2;  /**< BiST result of the QCB   memories (0=pass, !0=fail) */
+	uint64_t pdb                          : 4;  /**< BiST result of the PDB   memories (0=pass, !0=fail) */
+	uint64_t psb                          : 7;  /**< BiST result of the PSB   memories (0=pass, !0=fail) */
+#else
+	uint64_t psb                          : 7;
+	uint64_t pdb                          : 4;
+	uint64_t qcb                          : 2;
+	uint64_t qsb                          : 2;
+	uint64_t chk                          : 1;
+	uint64_t crc                          : 1;
+	uint64_t out                          : 1;
+	uint64_t ncb                          : 1;
+	uint64_t wif                          : 1;
+	uint64_t rif                          : 1;
+	uint64_t count                        : 1;
+	uint64_t psb2                         : 5;
+	uint64_t reserved_27_63               : 37;
+#endif
+	} cn30xx;
+	struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
+	struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
+	struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
+	struct cvmx_pko_reg_bist_result_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
+	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
+	uint64_t out_crc                      : 1;  /**< BiST result of OUT_CRC  memories (0=pass, !0=fail) */
+	uint64_t out_ctl                      : 3;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+	uint64_t prt_psb                      : 6;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+	uint64_t dat_dat                      : 4;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+	uint64_t dat_ptr                      : 4;
+	uint64_t dat_dat                      : 4;
+	uint64_t prt_qsb                      : 3;
+	uint64_t prt_qcb                      : 2;
+	uint64_t ncb_inb                      : 2;
+	uint64_t prt_psb                      : 6;
+	uint64_t prt_nxt                      : 1;
+	uint64_t prt_chk                      : 3;
+	uint64_t out_wif                      : 1;
+	uint64_t out_sta                      : 1;
+	uint64_t out_ctl                      : 3;
+	uint64_t out_crc                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t csr                          : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} cn50xx;
+	struct cvmx_pko_reg_bist_result_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_35_63               : 29;
+	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
+	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
+	uint64_t out_dat                      : 1;  /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
+	uint64_t out_ctl                      : 3;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+	uint64_t prt_psb                      : 8;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+	uint64_t prt_ctl                      : 2;  /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
+	uint64_t dat_dat                      : 2;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+	uint64_t dat_ptr                      : 4;
+	uint64_t dat_dat                      : 2;
+	uint64_t prt_ctl                      : 2;
+	uint64_t prt_qsb                      : 3;
+	uint64_t prt_qcb                      : 2;
+	uint64_t ncb_inb                      : 2;
+	uint64_t prt_psb                      : 8;
+	uint64_t prt_nxt                      : 1;
+	uint64_t prt_chk                      : 3;
+	uint64_t out_wif                      : 1;
+	uint64_t out_sta                      : 1;
+	uint64_t out_ctl                      : 3;
+	uint64_t out_dat                      : 1;
+	uint64_t iob                          : 1;
+	uint64_t csr                          : 1;
+	uint64_t reserved_35_63               : 29;
+#endif
+	} cn52xx;
+	struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
+	struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
+	struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
+	struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
+	struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
+	struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
+	struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
+};
+typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;
+
+/**
+ * cvmx_pko_reg_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
+ * lists to be used when freeing command buffer segments.
+ */
+union cvmx_pko_reg_cmd_buf
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_cmd_buf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
+	uint64_t reserved_13_19               : 7;
+	uint64_t size                         : 13; /**< Number of uint64s per command buffer segment */
+#else
+	uint64_t size                         : 13;
+	uint64_t reserved_13_19               : 7;
+	uint64_t pool                         : 3;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_pko_reg_cmd_buf_s         cn30xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn31xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn38xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn38xxp2;
+	struct cvmx_pko_reg_cmd_buf_s         cn50xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn52xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn52xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cn56xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn56xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cn58xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn58xxp1;
+	struct cvmx_pko_reg_cmd_buf_s         cn63xx;
+	struct cvmx_pko_reg_cmd_buf_s         cn63xxp1;
+};
+typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;
+
+/**
+ * cvmx_pko_reg_crc_ctl#
+ *
+ * Notes:
+ * Controls datapath reflection when calculating CRC
+ *
+ */
+union cvmx_pko_reg_crc_ctlx
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_crc_ctlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t invres                       : 1;  /**< Invert the result */
+	uint64_t refin                        : 1;  /**< Reflect the bits in each byte.
+                                                          Byte order does not change.
+                                                         - 0: CRC is calculated MSB to LSB
+                                                         - 1: CRC is calculated MLB to MSB */
+#else
+	uint64_t refin                        : 1;
+	uint64_t invres                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pko_reg_crc_ctlx_s        cn38xx;
+	struct cvmx_pko_reg_crc_ctlx_s        cn38xxp2;
+	struct cvmx_pko_reg_crc_ctlx_s        cn58xx;
+	struct cvmx_pko_reg_crc_ctlx_s        cn58xxp1;
+};
+typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t;
+
+/**
+ * cvmx_pko_reg_crc_enable
+ *
+ * Notes:
+ * Enables CRC for the GMX ports.
+ *
+ */
+union cvmx_pko_reg_crc_enable
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_crc_enable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enable                       : 32; /**< Mask for ports 31-0 to enable CRC
+                                                         Mask bit==0 means CRC not enabled
+                                                         Mask bit==1 means CRC     enabled
+                                                         Note that CRC should be enabled only when using SPI4.2 */
+#else
+	uint64_t enable                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_reg_crc_enable_s      cn38xx;
+	struct cvmx_pko_reg_crc_enable_s      cn38xxp2;
+	struct cvmx_pko_reg_crc_enable_s      cn58xx;
+	struct cvmx_pko_reg_crc_enable_s      cn58xxp1;
+};
+typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t;
+
+/**
+ * cvmx_pko_reg_crc_iv#
+ *
+ * Notes:
+ * Determines the IV used by the CRC algorithm
+ * * PKO_CRC_IV
+ *  PKO_CRC_IV controls the initial state of the CRC algorithm.  Octane can
+ *  support a wide range of CRC algorithms and as such, the IV must be
+ *  carefully constructed to meet the specific algorithm.  The code below
+ *  determines the value to program into Octane based on the algorthim's IV
+ *  and width.  In the case of Octane, the width should always be 32.
+ *
+ *  PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for
+ *  ports 16-31.
+ *
+ *   @verbatim
+ *   unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
+ *   [
+ *     int i;
+ *     int doit;
+ *     unsigned int current_val = algorithm_iv;
+ *
+ *     for(i = 0; i < w; i++) [
+ *       doit = current_val & 0x1;
+ *
+ *       if(doit) current_val ^= poly;
+ *       assert(!(current_val & 0x1));
+ *
+ *       current_val = (current_val >> 1) | (doit << (w-1));
+ *     ]
+ *
+ *     return current_val;
+ *   ]
+ *   @endverbatim
+ */
+union cvmx_pko_reg_crc_ivx
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_crc_ivx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iv                           : 32; /**< IV used by the CRC algorithm.  Default is FCS32. */
+#else
+	uint64_t iv                           : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pko_reg_crc_ivx_s         cn38xx;
+	struct cvmx_pko_reg_crc_ivx_s         cn38xxp2;
+	struct cvmx_pko_reg_crc_ivx_s         cn58xx;
+	struct cvmx_pko_reg_crc_ivx_s         cn58xxp1;
+};
+typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t;
+
+/**
+ * cvmx_pko_reg_debug0
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+union cvmx_pko_reg_debug0
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t asserts                      : 64; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_debug0_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t asserts                      : 17; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn30xx;
+	struct cvmx_pko_reg_debug0_cn30xx     cn31xx;
+	struct cvmx_pko_reg_debug0_cn30xx     cn38xx;
+	struct cvmx_pko_reg_debug0_cn30xx     cn38xxp2;
+	struct cvmx_pko_reg_debug0_s          cn50xx;
+	struct cvmx_pko_reg_debug0_s          cn52xx;
+	struct cvmx_pko_reg_debug0_s          cn52xxp1;
+	struct cvmx_pko_reg_debug0_s          cn56xx;
+	struct cvmx_pko_reg_debug0_s          cn56xxp1;
+	struct cvmx_pko_reg_debug0_s          cn58xx;
+	struct cvmx_pko_reg_debug0_s          cn58xxp1;
+	struct cvmx_pko_reg_debug0_s          cn63xx;
+	struct cvmx_pko_reg_debug0_s          cn63xxp1;
+};
+typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t;
+
+/**
+ * cvmx_pko_reg_debug1
+ */
+union cvmx_pko_reg_debug1
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t asserts                      : 64; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_debug1_s          cn50xx;
+	struct cvmx_pko_reg_debug1_s          cn52xx;
+	struct cvmx_pko_reg_debug1_s          cn52xxp1;
+	struct cvmx_pko_reg_debug1_s          cn56xx;
+	struct cvmx_pko_reg_debug1_s          cn56xxp1;
+	struct cvmx_pko_reg_debug1_s          cn58xx;
+	struct cvmx_pko_reg_debug1_s          cn58xxp1;
+	struct cvmx_pko_reg_debug1_s          cn63xx;
+	struct cvmx_pko_reg_debug1_s          cn63xxp1;
+};
+typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t;
+
+/**
+ * cvmx_pko_reg_debug2
+ */
+union cvmx_pko_reg_debug2
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t asserts                      : 64; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_debug2_s          cn50xx;
+	struct cvmx_pko_reg_debug2_s          cn52xx;
+	struct cvmx_pko_reg_debug2_s          cn52xxp1;
+	struct cvmx_pko_reg_debug2_s          cn56xx;
+	struct cvmx_pko_reg_debug2_s          cn56xxp1;
+	struct cvmx_pko_reg_debug2_s          cn58xx;
+	struct cvmx_pko_reg_debug2_s          cn58xxp1;
+	struct cvmx_pko_reg_debug2_s          cn63xx;
+	struct cvmx_pko_reg_debug2_s          cn63xxp1;
+};
+typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t;
+
+/**
+ * cvmx_pko_reg_debug3
+ */
+union cvmx_pko_reg_debug3
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_debug3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t asserts                      : 64; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 64;
+#endif
+	} s;
+	struct cvmx_pko_reg_debug3_s          cn50xx;
+	struct cvmx_pko_reg_debug3_s          cn52xx;
+	struct cvmx_pko_reg_debug3_s          cn52xxp1;
+	struct cvmx_pko_reg_debug3_s          cn56xx;
+	struct cvmx_pko_reg_debug3_s          cn56xxp1;
+	struct cvmx_pko_reg_debug3_s          cn58xx;
+	struct cvmx_pko_reg_debug3_s          cn58xxp1;
+	struct cvmx_pko_reg_debug3_s          cn63xx;
+	struct cvmx_pko_reg_debug3_s          cn63xxp1;
+};
+typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t;
+
+/**
+ * cvmx_pko_reg_engine_inflight
+ *
+ * Notes:
+ * Sets the maximum number of inflight packets, per engine.  Values greater than 4 are illegal.
+ * Setting an engine's value to 0 effectively stops the engine.
+ * Note that engines 4-7 do not exist
+ */
+union cvmx_pko_reg_engine_inflight
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_engine_inflight_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t engine11                     : 4;  /**< Maximum number of inflight packets for engine11 */
+	uint64_t engine10                     : 4;  /**< Maximum number of inflight packets for engine10 */
+	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
+	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
+	uint64_t engine7                      : 4;  /**< MBZ */
+	uint64_t engine6                      : 4;  /**< MBZ */
+	uint64_t engine5                      : 4;  /**< MBZ */
+	uint64_t engine4                      : 4;  /**< MBZ */
+	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
+	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
+	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
+	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
+#else
+	uint64_t engine0                      : 4;
+	uint64_t engine1                      : 4;
+	uint64_t engine2                      : 4;
+	uint64_t engine3                      : 4;
+	uint64_t engine4                      : 4;
+	uint64_t engine5                      : 4;
+	uint64_t engine6                      : 4;
+	uint64_t engine7                      : 4;
+	uint64_t engine8                      : 4;
+	uint64_t engine9                      : 4;
+	uint64_t engine10                     : 4;
+	uint64_t engine11                     : 4;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pko_reg_engine_inflight_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
+	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
+	uint64_t engine7                      : 4;  /**< MBZ */
+	uint64_t engine6                      : 4;  /**< MBZ */
+	uint64_t engine5                      : 4;  /**< MBZ */
+	uint64_t engine4                      : 4;  /**< MBZ */
+	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
+	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
+	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
+	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
+#else
+	uint64_t engine0                      : 4;
+	uint64_t engine1                      : 4;
+	uint64_t engine2                      : 4;
+	uint64_t engine3                      : 4;
+	uint64_t engine4                      : 4;
+	uint64_t engine5                      : 4;
+	uint64_t engine6                      : 4;
+	uint64_t engine7                      : 4;
+	uint64_t engine8                      : 4;
+	uint64_t engine9                      : 4;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} cn52xx;
+	struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
+	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
+	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
+	struct cvmx_pko_reg_engine_inflight_s cn63xx;
+	struct cvmx_pko_reg_engine_inflight_s cn63xxp1;
+};
+typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;
+
+/**
+ * cvmx_pko_reg_engine_thresh
+ *
+ * Notes:
+ * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers.
+ * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will
+ * be sent until all of it has been written into the PKO's internal buffer.  Note that a packet is
+ * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8.  When enabled and the
+ * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
+ * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
+ * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
+ * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
+ */
+union cvmx_pko_reg_engine_thresh
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_engine_thresh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t mask                         : 12; /**< Mask[n]=0 disables packet send threshold for engine n
+                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS
+                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
+#else
+	uint64_t mask                         : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_pko_reg_engine_thresh_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t mask                         : 10; /**< Mask[n]=0 disables packet send threshold for eng n
+                                                         Mask[n]=1 enables  packet send threshold for eng n     $PR       NS
+                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
+#else
+	uint64_t mask                         : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn52xx;
+	struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
+	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
+	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
+	struct cvmx_pko_reg_engine_thresh_s   cn63xx;
+	struct cvmx_pko_reg_engine_thresh_s   cn63xxp1;
+};
+typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;
+
+/**
+ * cvmx_pko_reg_error
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+union cvmx_pko_reg_error
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_error_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t currzero                     : 1;  /**< A packet data pointer has size=0 */
+	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
+	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t currzero                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_pko_reg_error_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
+	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn30xx;
+	struct cvmx_pko_reg_error_cn30xx      cn31xx;
+	struct cvmx_pko_reg_error_cn30xx      cn38xx;
+	struct cvmx_pko_reg_error_cn30xx      cn38xxp2;
+	struct cvmx_pko_reg_error_s           cn50xx;
+	struct cvmx_pko_reg_error_s           cn52xx;
+	struct cvmx_pko_reg_error_s           cn52xxp1;
+	struct cvmx_pko_reg_error_s           cn56xx;
+	struct cvmx_pko_reg_error_s           cn56xxp1;
+	struct cvmx_pko_reg_error_s           cn58xx;
+	struct cvmx_pko_reg_error_s           cn58xxp1;
+	struct cvmx_pko_reg_error_s           cn63xx;
+	struct cvmx_pko_reg_error_s           cn63xxp1;
+};
+typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;
+
+/**
+ * cvmx_pko_reg_flags
+ *
+ * Notes:
+ * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation.  When set, ENA_DWB
+ * enables the use of DontWriteBacks during the buffer freeing operations.  When not set, STORE_BE inverts
+ * bits[2:0] of the STORE0 byte write address.  When set, RESET causes a 4-cycle reset pulse to the
+ * entire box.
+ */
+union cvmx_pko_reg_flags
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_flags_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
+	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
+	uint64_t ena_dwb                      : 1;  /**< Set to enable DontWriteBacks */
+	uint64_t ena_pko                      : 1;  /**< Set to enable the PKO picker */
+#else
+	uint64_t ena_pko                      : 1;
+	uint64_t ena_dwb                      : 1;
+	uint64_t store_be                     : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pko_reg_flags_s           cn30xx;
+	struct cvmx_pko_reg_flags_s           cn31xx;
+	struct cvmx_pko_reg_flags_s           cn38xx;
+	struct cvmx_pko_reg_flags_s           cn38xxp2;
+	struct cvmx_pko_reg_flags_s           cn50xx;
+	struct cvmx_pko_reg_flags_s           cn52xx;
+	struct cvmx_pko_reg_flags_s           cn52xxp1;
+	struct cvmx_pko_reg_flags_s           cn56xx;
+	struct cvmx_pko_reg_flags_s           cn56xxp1;
+	struct cvmx_pko_reg_flags_s           cn58xx;
+	struct cvmx_pko_reg_flags_s           cn58xxp1;
+	struct cvmx_pko_reg_flags_s           cn63xx;
+	struct cvmx_pko_reg_flags_s           cn63xxp1;
+};
+typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;
+
+/**
+ * cvmx_pko_reg_gmx_port_mode
+ *
+ * Notes:
+ * The system has a total of 4 + 0 + 4 + 4 + 4 ports and 4 + 0 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1).
+ * This CSR sets the number of GMX0 ports and amount of local storage per engine.
+ * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP,
+ * SRIO0, or SRIO1.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
+ * storage.  Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
+ * increases the local storage per PKO GMX engine by a power of 2.
+ * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
+ *
+ * MODE[n] GM[0] PCI   LOOP  GM[0]                      PCI            LOOP            SRIO0           SRIO1
+ *         ports ports ports storage/engine             storage/engine storage/engine  storage/engine  storage/engine
+ * 0       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ * 1       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ * 2       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ * 3       2     4     4       5.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ * 4       1     4     4      10.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
+ */
+union cvmx_pko_reg_gmx_port_mode
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_gmx_port_mode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mode1                        : 3;  /**< MBZ */
+	uint64_t mode0                        : 3;  /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */
+#else
+	uint64_t mode0                        : 3;
+	uint64_t mode1                        : 3;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn30xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn31xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn38xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn38xxp2;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn50xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn52xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn52xxp1;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn56xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn56xxp1;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn58xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn58xxp1;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn63xx;
+	struct cvmx_pko_reg_gmx_port_mode_s   cn63xxp1;
+};
+typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;
+
+/**
+ * cvmx_pko_reg_int_mask
+ *
+ * Notes:
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ *
+ */
+union cvmx_pko_reg_int_mask
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_int_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t currzero                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
+	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t currzero                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_pko_reg_int_mask_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
+#else
+	uint64_t parity                       : 1;
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} cn30xx;
+	struct cvmx_pko_reg_int_mask_cn30xx   cn31xx;
+	struct cvmx_pko_reg_int_mask_cn30xx   cn38xx;
+	struct cvmx_pko_reg_int_mask_cn30xx   cn38xxp2;
+	struct cvmx_pko_reg_int_mask_s        cn50xx;
+	struct cvmx_pko_reg_int_mask_s        cn52xx;
+	struct cvmx_pko_reg_int_mask_s        cn52xxp1;
+	struct cvmx_pko_reg_int_mask_s        cn56xx;
+	struct cvmx_pko_reg_int_mask_s        cn56xxp1;
+	struct cvmx_pko_reg_int_mask_s        cn58xx;
+	struct cvmx_pko_reg_int_mask_s        cn58xxp1;
+	struct cvmx_pko_reg_int_mask_s        cn63xx;
+	struct cvmx_pko_reg_int_mask_s        cn63xxp1;
+};
+typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;
+
+/**
+ * cvmx_pko_reg_queue_mode
+ *
+ * Notes:
+ * Sets the number of queues and amount of local storage per queue
+ * The system has a total of 256 queues and (256*8) words of local command storage.  This CSR sets the
+ * number of queues that are used.  Increasing the value of MODE by 1 decreases the number of queues
+ * by a power of 2 and increases the local storage per queue by a power of 2.
+ * MODEn queues storage/queue
+ * 0     256     64B ( 8 words)
+ * 1     128    128B (16 words)
+ * 2      64    256B (32 words)
+ */
+union cvmx_pko_reg_queue_mode
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_queue_mode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t mode                         : 2;  /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
+#else
+	uint64_t mode                         : 2;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pko_reg_queue_mode_s      cn30xx;
+	struct cvmx_pko_reg_queue_mode_s      cn31xx;
+	struct cvmx_pko_reg_queue_mode_s      cn38xx;
+	struct cvmx_pko_reg_queue_mode_s      cn38xxp2;
+	struct cvmx_pko_reg_queue_mode_s      cn50xx;
+	struct cvmx_pko_reg_queue_mode_s      cn52xx;
+	struct cvmx_pko_reg_queue_mode_s      cn52xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cn56xx;
+	struct cvmx_pko_reg_queue_mode_s      cn56xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cn58xx;
+	struct cvmx_pko_reg_queue_mode_s      cn58xxp1;
+	struct cvmx_pko_reg_queue_mode_s      cn63xx;
+	struct cvmx_pko_reg_queue_mode_s      cn63xxp1;
+};
+typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;
+
+/**
+ * cvmx_pko_reg_queue_ptrs1
+ *
+ * Notes:
+ * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255
+ * and to allow up mapping of up to 16 queues per port.  When programming queues 128-255, the
+ * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or
+ * PKO_MEM_QUEUE_QOS for each queue.
+ * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
+ * programming.
+ */
+union cvmx_pko_reg_queue_ptrs1
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_queue_ptrs1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t idx3                         : 1;  /**< [3] of Index (distance from head) in the queue array */
+	uint64_t qid7                         : 1;  /**< [7] of Queue ID */
+#else
+	uint64_t qid7                         : 1;
+	uint64_t idx3                         : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn50xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn52xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn52xxp1;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn56xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn56xxp1;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn58xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn58xxp1;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn63xx;
+	struct cvmx_pko_reg_queue_ptrs1_s     cn63xxp1;
+};
+typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;
+
+/**
+ * cvmx_pko_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "PKO_MEM_".
+ * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+union cvmx_pko_reg_read_idx
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_read_idx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t index                        : 8;  /**< Index to use for next memory CSR read */
+#else
+	uint64_t index                        : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_pko_reg_read_idx_s        cn30xx;
+	struct cvmx_pko_reg_read_idx_s        cn31xx;
+	struct cvmx_pko_reg_read_idx_s        cn38xx;
+	struct cvmx_pko_reg_read_idx_s        cn38xxp2;
+	struct cvmx_pko_reg_read_idx_s        cn50xx;
+	struct cvmx_pko_reg_read_idx_s        cn52xx;
+	struct cvmx_pko_reg_read_idx_s        cn52xxp1;
+	struct cvmx_pko_reg_read_idx_s        cn56xx;
+	struct cvmx_pko_reg_read_idx_s        cn56xxp1;
+	struct cvmx_pko_reg_read_idx_s        cn58xx;
+	struct cvmx_pko_reg_read_idx_s        cn58xxp1;
+	struct cvmx_pko_reg_read_idx_s        cn63xx;
+	struct cvmx_pko_reg_read_idx_s        cn63xxp1;
+};
+typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t;
+
+/**
+ * cvmx_pko_reg_timestamp
+ *
+ * Notes:
+ * None.
+ *
+ */
+union cvmx_pko_reg_timestamp
+{
+	uint64_t u64;
+	struct cvmx_pko_reg_timestamp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t wqe_word                     : 4;  /**< Specifies the 8-byte word in the WQE to which a PTP
+                                                         timestamp is written.  Values 0 and 1 are illegal. */
+#else
+	uint64_t wqe_word                     : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_pko_reg_timestamp_s       cn63xx;
+	struct cvmx_pko_reg_timestamp_s       cn63xxp1;
+};
+typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pko.c b/sys/contrib/octeon-sdk/cvmx-pko.c
index dd439a3..74f250b 100644
--- a/sys/contrib/octeon-sdk/cvmx-pko.c
+++ b/sys/contrib/octeon-sdk/cvmx-pko.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,32 @@
 
 
 
+
 /**
  * @file
  *
  * Support library for the hardware Packet Output unit.
  *
- * <hr>$Revision: 42150 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-clock.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#endif
 #include "cvmx.h"
-#include "cvmx-pko.h"
 #include "cvmx-sysinfo.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
+#include "cvmx-pko.h"
 #include "cvmx-helper.h"
+#endif
 
 /**
  * Internal state of packet output
@@ -69,7 +85,7 @@ void cvmx_pko_initialize_global(void)
 {
     int i;
     uint64_t priority = 8;
-    cvmx_pko_pool_cfg_t config;
+    cvmx_pko_reg_cmd_buf_t config;
 
     /* Set the size of the PKO command buffers to an odd number of 64bit
         words. This allows the normal two word send to stay aligned and never
@@ -84,7 +100,7 @@ void cvmx_pko_initialize_global(void)
         cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority);
 
     /* If we aren't using all of the queues optimize PKO's internal memory */
-    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
     {
         int num_interfaces = cvmx_helper_get_number_of_interfaces();
         int last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
@@ -135,7 +151,7 @@ void cvmx_pko_enable(void)
 
     flags.s.ena_dwb = 1;
     flags.s.ena_pko = 1;
-    flags.s.store_be =1;  /* always enable big endian for 3-word command. Does nothing for 2-word */ 
+    flags.s.store_be =1;  /* always enable big endian for 3-word command. Does nothing for 2-word */
     cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
 }
 
@@ -171,7 +187,7 @@ static void __cvmx_pko_reset(void)
  */
 void cvmx_pko_shutdown(void)
 {
-    cvmx_pko_queue_cfg_t config;
+    cvmx_pko_mem_queue_ptrs_t config;
     int queue;
 
     cvmx_pko_disable();
@@ -220,7 +236,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
 {
     cvmx_pko_status_t          result_code;
     uint64_t                   queue;
-    cvmx_pko_queue_cfg_t       config;
+    cvmx_pko_mem_queue_ptrs_t  config;
     cvmx_pko_reg_queue_ptrs1_t config1;
     int static_priority_base = -1;
     int static_priority_end = -1;
@@ -292,12 +308,9 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
         config.s.port       = port;
         config.s.queue      = base_queue + queue;
 
-        if (!cvmx_octeon_is_pass1())
-        {
-            config.s.static_p   = static_priority_base >= 0;
-            config.s.static_q   = (int)queue <= static_priority_end;
-            config.s.s_tail     = (int)queue == static_priority_end;
-        }
+        config.s.static_p   = static_priority_base >= 0;
+        config.s.static_q   = (int)queue <= static_priority_end;
+        config.s.s_tail     = (int)queue == static_priority_end;
         /* Convert the priority into an enable bit field. Try to space the bits
             out evenly so the packet don't get grouped up */
         switch ((int)priority[queue])
@@ -312,11 +325,8 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
             case 7: config.s.qos_mask = 0x7f; break;
             case 8: config.s.qos_mask = 0xff; break;
             case CVMX_PKO_QUEUE_STATIC_PRIORITY:
-                if (!cvmx_octeon_is_pass1()) /* Pass 1 will fall through to the error case */
-                {
-                    config.s.qos_mask = 0xff;
-                    break;
-                }
+                config.s.qos_mask = 0xff;
+                break;
             default:
                 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", (unsigned long long)priority[queue]);
                 config.s.qos_mask = 0xff;
@@ -332,7 +342,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint6
                                                                         CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
             if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
             {
-	        switch (cmd_res) 
+	        switch (cmd_res)
 		{
 		    case CVMX_CMD_QUEUE_NO_MEMORY:
                         cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n");
@@ -410,7 +420,7 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
 
     pko_mem_port_rate0.u64 = 0;
     pko_mem_port_rate0.s.pid = port;
-    pko_mem_port_rate0.s.rate_pkt = cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
+    pko_mem_port_rate0.s.rate_pkt = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / packets_s / 16;
     /* No cost per word since we are limited by packets/sec, not bits/sec */
     pko_mem_port_rate0.s.rate_word = 0;
 
@@ -439,7 +449,7 @@ int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
 {
     cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
     cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
-    uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
+    uint64_t clock_rate = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
     uint64_t tokens_per_bit = clock_rate*16 / bits_s;
 
     pko_mem_port_rate0.u64 = 0;
diff --git a/sys/contrib/octeon-sdk/cvmx-pko.h b/sys/contrib/octeon-sdk/cvmx-pko.h
index 906f0f8..f7825b4 100644
--- a/sys/contrib/octeon-sdk/cvmx-pko.h
+++ b/sys/contrib/octeon-sdk/cvmx-pko.h
@@ -1,46 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
@@ -70,21 +67,26 @@
  * - PKO 3 word commands are now supported. Use
  *   cvmx_pko_send_packet_finish3().
  *
- * <hr>$Revision: 42150 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 
 #ifndef __CVMX_PKO_H__
 #define __CVMX_PKO_H__
 
-#ifndef CVMX_DONT_INCLUDE_CONFIG
-#include "executive-config.h"
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-config.h"
-#endif
+#include "cvmx-pko-defs.h"
+#else
+# ifndef CVMX_DONT_INCLUDE_CONFIG
+#  include "executive-config.h"
+#  ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#   include "cvmx-config.h"
+#  endif
+# endif
 #endif
 
-#include "cvmx-cvmmem.h"
+
 #include "cvmx-fau.h"
 #include "cvmx-fpa.h"
 #include "cvmx-pow.h"
@@ -100,9 +102,9 @@ extern "C" {
 #endif
 
 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
-#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
-#define CVMX_PKO_NUM_OUTPUT_PORTS       40
-#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 // use this for queues that are not used
+#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 256 : 128)
+#define CVMX_PKO_NUM_OUTPUT_PORTS       ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 44 : 40)
+#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 /* use this for queues that are not used */
 #define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
 #define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
 #define CVMX_PKO_MAX_QUEUE_DEPTH 0
@@ -190,7 +192,7 @@ typedef union
     } s;
 } cvmx_pko_command_word0_t;
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-pko-defs.h */
 
 /**
  * Definition of internal state for Packet output processing
@@ -423,6 +425,16 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
     #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
 #endif
+#ifndef CVMX_PKO_QUEUES_PER_PORT_SRIO0
+    /* We use two queues per port for SRIO0. Having two queues per
+        port with two ports gives us four queues, one for each mailbox */
+    #define CVMX_PKO_QUEUES_PER_PORT_SRIO0 2
+#endif
+#ifndef CVMX_PKO_QUEUES_PER_PORT_SRIO1
+    /* We use two queues per port for SRIO1. Having two queues per
+        port with two ports gives us four queues, one for each mailbox */
+    #define CVMX_PKO_QUEUES_PER_PORT_SRIO1 2
+#endif
     if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
         return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
     else if (port >=16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
@@ -437,6 +449,19 @@ static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
                CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
                4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
                (port-36) * CVMX_PKO_QUEUES_PER_PORT_LOOP;
+    else if ((port >= 40) && (port < 42))
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+               CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+               4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
+               4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
+	       (port-40) * CVMX_PKO_QUEUES_PER_PORT_SRIO0;
+    else if ((port >= 42) && (port < 44))
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+               CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+               4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
+               4 * CVMX_PKO_QUEUES_PER_PORT_LOOP +
+	       2 * CVMX_PKO_QUEUES_PER_PORT_SRIO0 +
+	       (port-42) * CVMX_PKO_QUEUES_PER_PORT_SRIO1;
     else
         /* Given the limit on the number of ports we can map to
          * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
@@ -473,6 +498,10 @@ static inline int cvmx_pko_get_num_queues(int port)
         return CVMX_PKO_QUEUES_PER_PORT_PCI;
     else if (port<40)
         return CVMX_PKO_QUEUES_PER_PORT_LOOP;
+    else if (port<42)
+        return CVMX_PKO_QUEUES_PER_PORT_SRIO0;
+    else if (port<44)
+        return CVMX_PKO_QUEUES_PER_PORT_SRIO1;
     else
         return 0;
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-platform.h b/sys/contrib/octeon-sdk/cvmx-platform.h
index 7021ade..d8b797b 100644
--- a/sys/contrib/octeon-sdk/cvmx-platform.h
+++ b/sys/contrib/octeon-sdk/cvmx-platform.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,13 +42,14 @@
 
 
 
+
 /**
  * @file
  *
  * This file is resposible for including all system dependent
  * headers for the cvmx-* files.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
 */
 
 #ifndef __CVMX_PLATFORM_H__
@@ -104,7 +106,7 @@
        should only use features available on all Octeon models.  */
     #define CVMX_BUILD_FOR_TOOLCHAIN
 #elif defined(__FreeBSD__) && defined(_KERNEL)
-    #define CVMX_BUILD_FOR_FREEBSD
+    #define CVMX_BUILD_FOR_FREEBSD_KERNEL
 #else
     /* We are building a simple exec standalone image for Octeon */
     #define CVMX_BUILD_FOR_STANDALONE
@@ -119,12 +121,15 @@
  * This is for data structures use by software ONLY,
  * as it is not 1-1 VA-PA mapped.
  */
-#if defined(CVMX_BUILD_FOR_FREEBSD)
+#if defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 #define CVMX_SHARED
 #else
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
 #define CVMX_SHARED __attribute__ ((cvmx_shared))
+#else
+#define CVMX_SHARED
+#endif
 #endif
-
 
 #if defined(CVMX_BUILD_FOR_UBOOT)
 
@@ -150,6 +155,35 @@
     #include <fcntl.h>
     #include <sys/mman.h>
     #include <unistd.h>
+    #include <errno.h>
+    #include <sys/sysmips.h>
+    #define MIPS_CAVIUM_XKPHYS_READ	   2010	/* XKPHYS */
+    #define MIPS_CAVIUM_XKPHYS_WRITE	   2011	/* XKPHYS */
+
+/* Enable access to XKPHYS segments. Warning message is printed in case of
+   error. If warn_count is set, the warning message is not displayed. */
+static inline void cvmx_linux_enable_xkphys_access(int32_t warn_count)
+{
+    int ret;
+    ret = sysmips(MIPS_CAVIUM_XKPHYS_WRITE, getpid(), 3, 0);
+    if (ret != 0 && !warn_count) {
+        switch(errno) {
+            case EINVAL:
+                perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
+	             "  Did you configure your kernel with both:\n"
+	             "     CONFIG_CAVIUM_OCTEON_USER_MEM_PER_PROCESS *and*\n"
+	             "     CONFIG_CAVIUM_OCTEON_USER_IO_PER_PROCESS?");
+                break;
+            case EPERM:
+                perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
+	             "  Are you running as root?");
+                break;
+            default:
+                perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed");
+                break;
+        }
+    }
+}
 
 #elif defined(CVMX_BUILD_FOR_LINUX_HOST)
 
@@ -193,7 +227,7 @@
     #include <string.h>
     #include <assert.h>
 
-#elif defined(CVMX_BUILD_FOR_FREEBSD)
+#elif defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
 
     #include <mips/cavium/cvmx_config.h>
 
diff --git a/sys/contrib/octeon-sdk/cvmx-pow-defs.h b/sys/contrib/octeon-sdk/cvmx-pow-defs.h
new file mode 100644
index 0000000..53065c9
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-pow-defs.h
@@ -0,0 +1,1827 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-pow-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pow.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_POW_TYPEDEFS_H__
+#define __CVMX_POW_TYPEDEFS_H__
+
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000238ull);
+}
+#else
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000240ull);
+}
+#else
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
+static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001670000000230ull);
+}
+#else
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+		cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
+		cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8;
+}
+#else
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#endif
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+		cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#endif
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+		cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+		cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
+#endif
+
+/**
+ * cvmx_pow_bist_stat
+ *
+ * POW_BIST_STAT = POW BIST Status Register
+ *
+ * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).
+ *
+ * Also contains the BIST status for the PP's.  Each bit in the PP field is the OR of all BIST
+ * results for the corresponding physical PP ('0' = pass, '1' = fail).
+ */
+union cvmx_pow_bist_stat
+{
+	uint64_t u64;
+	struct cvmx_pow_bist_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pp                           : 16; /**< Physical PP BIST status */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t pp                           : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_bist_stat_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t pp                           : 1;  /**< Physical PP BIST status */
+	uint64_t reserved_9_15                : 7;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbt1                         : 1;  /**< NCB transmitter memory 1 BIST status */
+	uint64_t nbt0                         : 1;  /**< NCB transmitter memory 0 BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t nbr1                         : 1;  /**< NCB receiver memory 1 BIST status */
+	uint64_t nbr0                         : 1;  /**< NCB receiver memory 0 BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t nbr0                         : 1;
+	uint64_t nbr1                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt0                         : 1;
+	uint64_t nbt1                         : 1;
+	uint64_t cam                          : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t pp                           : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn30xx;
+	struct cvmx_pow_bist_stat_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t pp                           : 2;  /**< Physical PP BIST status */
+	uint64_t reserved_9_15                : 7;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbt1                         : 1;  /**< NCB transmitter memory 1 BIST status */
+	uint64_t nbt0                         : 1;  /**< NCB transmitter memory 0 BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t nbr1                         : 1;  /**< NCB receiver memory 1 BIST status */
+	uint64_t nbr0                         : 1;  /**< NCB receiver memory 0 BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t nbr0                         : 1;
+	uint64_t nbr1                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt0                         : 1;
+	uint64_t nbt1                         : 1;
+	uint64_t cam                          : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t pp                           : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn31xx;
+	struct cvmx_pow_bist_stat_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t pp                           : 16; /**< Physical PP BIST status */
+	uint64_t reserved_10_15               : 6;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbt                          : 1;  /**< NCB transmitter memory BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t nbr1                         : 1;  /**< NCB receiver memory 1 BIST status */
+	uint64_t nbr0                         : 1;  /**< NCB receiver memory 0 BIST status */
+	uint64_t pend1                        : 1;  /**< Pending switch memory 1 BIST status */
+	uint64_t pend0                        : 1;  /**< Pending switch memory 0 BIST status */
+	uint64_t adr1                         : 1;  /**< Address memory 1 BIST status */
+	uint64_t adr0                         : 1;  /**< Address memory 0 BIST status */
+#else
+	uint64_t adr0                         : 1;
+	uint64_t adr1                         : 1;
+	uint64_t pend0                        : 1;
+	uint64_t pend1                        : 1;
+	uint64_t nbr0                         : 1;
+	uint64_t nbr1                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt                          : 1;
+	uint64_t cam                          : 1;
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp                           : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn38xx;
+	struct cvmx_pow_bist_stat_cn38xx      cn38xxp2;
+	struct cvmx_pow_bist_stat_cn31xx      cn50xx;
+	struct cvmx_pow_bist_stat_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t pp                           : 4;  /**< Physical PP BIST status */
+	uint64_t reserved_9_15                : 7;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbt1                         : 1;  /**< NCB transmitter memory 1 BIST status */
+	uint64_t nbt0                         : 1;  /**< NCB transmitter memory 0 BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t nbr1                         : 1;  /**< NCB receiver memory 1 BIST status */
+	uint64_t nbr0                         : 1;  /**< NCB receiver memory 0 BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t nbr0                         : 1;
+	uint64_t nbr1                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt0                         : 1;
+	uint64_t nbt1                         : 1;
+	uint64_t cam                          : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t pp                           : 4;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn52xx;
+	struct cvmx_pow_bist_stat_cn52xx      cn52xxp1;
+	struct cvmx_pow_bist_stat_cn56xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t pp                           : 12; /**< Physical PP BIST status */
+	uint64_t reserved_10_15               : 6;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbt                          : 1;  /**< NCB transmitter memory BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t nbr1                         : 1;  /**< NCB receiver memory 1 BIST status */
+	uint64_t nbr0                         : 1;  /**< NCB receiver memory 0 BIST status */
+	uint64_t pend1                        : 1;  /**< Pending switch memory 1 BIST status */
+	uint64_t pend0                        : 1;  /**< Pending switch memory 0 BIST status */
+	uint64_t adr1                         : 1;  /**< Address memory 1 BIST status */
+	uint64_t adr0                         : 1;  /**< Address memory 0 BIST status */
+#else
+	uint64_t adr0                         : 1;
+	uint64_t adr1                         : 1;
+	uint64_t pend0                        : 1;
+	uint64_t pend1                        : 1;
+	uint64_t nbr0                         : 1;
+	uint64_t nbr1                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt                          : 1;
+	uint64_t cam                          : 1;
+	uint64_t reserved_10_15               : 6;
+	uint64_t pp                           : 12;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn56xx;
+	struct cvmx_pow_bist_stat_cn56xx      cn56xxp1;
+	struct cvmx_pow_bist_stat_cn38xx      cn58xx;
+	struct cvmx_pow_bist_stat_cn38xx      cn58xxp1;
+	struct cvmx_pow_bist_stat_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t pp                           : 6;  /**< Physical PP BIST status */
+	uint64_t reserved_12_15               : 4;
+	uint64_t cam                          : 1;  /**< POW CAM BIST status */
+	uint64_t nbr                          : 3;  /**< NCB receiver memory BIST status */
+	uint64_t nbt                          : 4;  /**< NCB transmitter memory BIST status */
+	uint64_t index                        : 1;  /**< Index memory BIST status */
+	uint64_t fidx                         : 1;  /**< Forward index memory BIST status */
+	uint64_t pend                         : 1;  /**< Pending switch memory BIST status */
+	uint64_t adr                          : 1;  /**< Address memory BIST status */
+#else
+	uint64_t adr                          : 1;
+	uint64_t pend                         : 1;
+	uint64_t fidx                         : 1;
+	uint64_t index                        : 1;
+	uint64_t nbt                          : 4;
+	uint64_t nbr                          : 3;
+	uint64_t cam                          : 1;
+	uint64_t reserved_12_15               : 4;
+	uint64_t pp                           : 6;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn63xx;
+	struct cvmx_pow_bist_stat_cn63xx      cn63xxp1;
+};
+typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t;
+
+/**
+ * cvmx_pow_ds_pc
+ *
+ * POW_DS_PC = POW De-Schedule Performance Counter
+ *
+ * Counts the number of de-schedule requests.  Write to clear.
+ */
+union cvmx_pow_ds_pc
+{
+	uint64_t u64;
+	struct cvmx_pow_ds_pc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ds_pc                        : 32; /**< De-schedule performance counter */
+#else
+	uint64_t ds_pc                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_ds_pc_s               cn30xx;
+	struct cvmx_pow_ds_pc_s               cn31xx;
+	struct cvmx_pow_ds_pc_s               cn38xx;
+	struct cvmx_pow_ds_pc_s               cn38xxp2;
+	struct cvmx_pow_ds_pc_s               cn50xx;
+	struct cvmx_pow_ds_pc_s               cn52xx;
+	struct cvmx_pow_ds_pc_s               cn52xxp1;
+	struct cvmx_pow_ds_pc_s               cn56xx;
+	struct cvmx_pow_ds_pc_s               cn56xxp1;
+	struct cvmx_pow_ds_pc_s               cn58xx;
+	struct cvmx_pow_ds_pc_s               cn58xxp1;
+	struct cvmx_pow_ds_pc_s               cn63xx;
+	struct cvmx_pow_ds_pc_s               cn63xxp1;
+};
+typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t;
+
+/**
+ * cvmx_pow_ecc_err
+ *
+ * POW_ECC_ERR = POW ECC Error Register
+ *
+ * Contains the single and double error bits and the corresponding interrupt enables for the ECC-
+ * protected POW index memory.  Also contains the syndrome value in the event of an ECC error.
+ *
+ * Also contains the remote pointer error bit and interrupt enable.  RPE is set when the POW detected
+ * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer
+ * for the L2/DRAM input queue did not match the last entry on the the list).   This is caused by
+ * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work
+ * queue entries.
+ *
+ * This register also contains the illegal operation error bits and the corresponding interrupt
+ * enables as follows:
+ *
+ *  <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
+ *  <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
+ *  <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
+ *  <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
+ *  <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
+ *  <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
+ *  <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
+ *  <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
+ *  <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
+ *  <9> Received illegal opcode
+ * <10> Received ADD_WORK with tag specified as NULL_NULL
+ * <11> Received DBG load from PP with DBG load pending
+ * <12> Received CSR load from PP with CSR load pending
+ */
+union cvmx_pow_ecc_err
+{
+	uint64_t u64;
+	struct cvmx_pow_ecc_err_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_45_63               : 19;
+	uint64_t iop_ie                       : 13; /**< Illegal operation interrupt enables */
+	uint64_t reserved_29_31               : 3;
+	uint64_t iop                          : 13; /**< Illegal operation errors */
+	uint64_t reserved_14_15               : 2;
+	uint64_t rpe_ie                       : 1;  /**< Remote pointer error interrupt enable */
+	uint64_t rpe                          : 1;  /**< Remote pointer error */
+	uint64_t reserved_9_11                : 3;
+	uint64_t syn                          : 5;  /**< Syndrome value (only valid when DBE or SBE is set) */
+	uint64_t dbe_ie                       : 1;  /**< Double bit error interrupt enable */
+	uint64_t sbe_ie                       : 1;  /**< Single bit error interrupt enable */
+	uint64_t dbe                          : 1;  /**< Double bit error */
+	uint64_t sbe                          : 1;  /**< Single bit error */
+#else
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+	uint64_t sbe_ie                       : 1;
+	uint64_t dbe_ie                       : 1;
+	uint64_t syn                          : 5;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rpe                          : 1;
+	uint64_t rpe_ie                       : 1;
+	uint64_t reserved_14_15               : 2;
+	uint64_t iop                          : 13;
+	uint64_t reserved_29_31               : 3;
+	uint64_t iop_ie                       : 13;
+	uint64_t reserved_45_63               : 19;
+#endif
+	} s;
+	struct cvmx_pow_ecc_err_s             cn30xx;
+	struct cvmx_pow_ecc_err_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t rpe_ie                       : 1;  /**< Remote pointer error interrupt enable */
+	uint64_t rpe                          : 1;  /**< Remote pointer error */
+	uint64_t reserved_9_11                : 3;
+	uint64_t syn                          : 5;  /**< Syndrome value (only valid when DBE or SBE is set) */
+	uint64_t dbe_ie                       : 1;  /**< Double bit error interrupt enable */
+	uint64_t sbe_ie                       : 1;  /**< Single bit error interrupt enable */
+	uint64_t dbe                          : 1;  /**< Double bit error */
+	uint64_t sbe                          : 1;  /**< Single bit error */
+#else
+	uint64_t sbe                          : 1;
+	uint64_t dbe                          : 1;
+	uint64_t sbe_ie                       : 1;
+	uint64_t dbe_ie                       : 1;
+	uint64_t syn                          : 5;
+	uint64_t reserved_9_11                : 3;
+	uint64_t rpe                          : 1;
+	uint64_t rpe_ie                       : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn31xx;
+	struct cvmx_pow_ecc_err_s             cn38xx;
+	struct cvmx_pow_ecc_err_cn31xx        cn38xxp2;
+	struct cvmx_pow_ecc_err_s             cn50xx;
+	struct cvmx_pow_ecc_err_s             cn52xx;
+	struct cvmx_pow_ecc_err_s             cn52xxp1;
+	struct cvmx_pow_ecc_err_s             cn56xx;
+	struct cvmx_pow_ecc_err_s             cn56xxp1;
+	struct cvmx_pow_ecc_err_s             cn58xx;
+	struct cvmx_pow_ecc_err_s             cn58xxp1;
+	struct cvmx_pow_ecc_err_s             cn63xx;
+	struct cvmx_pow_ecc_err_s             cn63xxp1;
+};
+typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t;
+
+/**
+ * cvmx_pow_int_ctl
+ *
+ * POW_INT_CTL = POW Internal Control Register
+ *
+ * Contains POW internal control values (for internal use, not typically for customer use):
+ *
+ * PFR_DIS = Disable high-performance pre-fetch reset mode.
+ *
+ * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less
+ * than or equal to this value.
+ */
+union cvmx_pow_int_ctl
+{
+	uint64_t u64;
+	struct cvmx_pow_int_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t pfr_dis                      : 1;  /**< High-perf pre-fetch reset mode disable */
+	uint64_t nbr_thr                      : 5;  /**< NBR busy threshold */
+#else
+	uint64_t nbr_thr                      : 5;
+	uint64_t pfr_dis                      : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_pow_int_ctl_s             cn30xx;
+	struct cvmx_pow_int_ctl_s             cn31xx;
+	struct cvmx_pow_int_ctl_s             cn38xx;
+	struct cvmx_pow_int_ctl_s             cn38xxp2;
+	struct cvmx_pow_int_ctl_s             cn50xx;
+	struct cvmx_pow_int_ctl_s             cn52xx;
+	struct cvmx_pow_int_ctl_s             cn52xxp1;
+	struct cvmx_pow_int_ctl_s             cn56xx;
+	struct cvmx_pow_int_ctl_s             cn56xxp1;
+	struct cvmx_pow_int_ctl_s             cn58xx;
+	struct cvmx_pow_int_ctl_s             cn58xxp1;
+	struct cvmx_pow_int_ctl_s             cn63xx;
+	struct cvmx_pow_int_ctl_s             cn63xxp1;
+};
+typedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t;
+
+/**
+ * cvmx_pow_iq_cnt#
+ *
+ * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level)
+ *
+ * Contains a read-only count of the number of work queue entries for each QOS level.
+ */
+union cvmx_pow_iq_cntx
+{
+	uint64_t u64;
+	struct cvmx_pow_iq_cntx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_cnt                       : 32; /**< Input queue count for QOS level X */
+#else
+	uint64_t iq_cnt                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_iq_cntx_s             cn30xx;
+	struct cvmx_pow_iq_cntx_s             cn31xx;
+	struct cvmx_pow_iq_cntx_s             cn38xx;
+	struct cvmx_pow_iq_cntx_s             cn38xxp2;
+	struct cvmx_pow_iq_cntx_s             cn50xx;
+	struct cvmx_pow_iq_cntx_s             cn52xx;
+	struct cvmx_pow_iq_cntx_s             cn52xxp1;
+	struct cvmx_pow_iq_cntx_s             cn56xx;
+	struct cvmx_pow_iq_cntx_s             cn56xxp1;
+	struct cvmx_pow_iq_cntx_s             cn58xx;
+	struct cvmx_pow_iq_cntx_s             cn58xxp1;
+	struct cvmx_pow_iq_cntx_s             cn63xx;
+	struct cvmx_pow_iq_cntx_s             cn63xxp1;
+};
+typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t;
+
+/**
+ * cvmx_pow_iq_com_cnt
+ *
+ * POW_IQ_COM_CNT = POW Input Queue Combined Count Register
+ *
+ * Contains a read-only count of the total number of work queue entries in all QOS levels.
+ */
+union cvmx_pow_iq_com_cnt
+{
+	uint64_t u64;
+	struct cvmx_pow_iq_com_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_cnt                       : 32; /**< Input queue combined count */
+#else
+	uint64_t iq_cnt                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_iq_com_cnt_s          cn30xx;
+	struct cvmx_pow_iq_com_cnt_s          cn31xx;
+	struct cvmx_pow_iq_com_cnt_s          cn38xx;
+	struct cvmx_pow_iq_com_cnt_s          cn38xxp2;
+	struct cvmx_pow_iq_com_cnt_s          cn50xx;
+	struct cvmx_pow_iq_com_cnt_s          cn52xx;
+	struct cvmx_pow_iq_com_cnt_s          cn52xxp1;
+	struct cvmx_pow_iq_com_cnt_s          cn56xx;
+	struct cvmx_pow_iq_com_cnt_s          cn56xxp1;
+	struct cvmx_pow_iq_com_cnt_s          cn58xx;
+	struct cvmx_pow_iq_com_cnt_s          cn58xxp1;
+	struct cvmx_pow_iq_com_cnt_s          cn63xx;
+	struct cvmx_pow_iq_com_cnt_s          cn63xxp1;
+};
+typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t;
+
+/**
+ * cvmx_pow_iq_int
+ *
+ * POW_IQ_INT = POW Input Queue Interrupt Register
+ *
+ * Contains the bits (1 per QOS level) that can trigger the input queue interrupt.  An IQ_INT bit
+ * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.
+ */
+union cvmx_pow_iq_int
+{
+	uint64_t u64;
+	struct cvmx_pow_iq_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t iq_int                       : 8;  /**< Input queue interrupt bits */
+#else
+	uint64_t iq_int                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pow_iq_int_s              cn52xx;
+	struct cvmx_pow_iq_int_s              cn52xxp1;
+	struct cvmx_pow_iq_int_s              cn56xx;
+	struct cvmx_pow_iq_int_s              cn56xxp1;
+	struct cvmx_pow_iq_int_s              cn63xx;
+	struct cvmx_pow_iq_int_s              cn63xxp1;
+};
+typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t;
+
+/**
+ * cvmx_pow_iq_int_en
+ *
+ * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register
+ *
+ * Contains the bits (1 per QOS level) that enable the input queue interrupt.
+ */
+union cvmx_pow_iq_int_en
+{
+	uint64_t u64;
+	struct cvmx_pow_iq_int_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t int_en                       : 8;  /**< Input queue interrupt enable bits */
+#else
+	uint64_t int_en                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pow_iq_int_en_s           cn52xx;
+	struct cvmx_pow_iq_int_en_s           cn52xxp1;
+	struct cvmx_pow_iq_int_en_s           cn56xx;
+	struct cvmx_pow_iq_int_en_s           cn56xxp1;
+	struct cvmx_pow_iq_int_en_s           cn63xx;
+	struct cvmx_pow_iq_int_en_s           cn63xxp1;
+};
+typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t;
+
+/**
+ * cvmx_pow_iq_thr#
+ *
+ * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level)
+ *
+ * Threshold value for triggering input queue interrupts.
+ */
+union cvmx_pow_iq_thrx
+{
+	uint64_t u64;
+	struct cvmx_pow_iq_thrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_thr                       : 32; /**< Input queue threshold for QOS level X */
+#else
+	uint64_t iq_thr                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_iq_thrx_s             cn52xx;
+	struct cvmx_pow_iq_thrx_s             cn52xxp1;
+	struct cvmx_pow_iq_thrx_s             cn56xx;
+	struct cvmx_pow_iq_thrx_s             cn56xxp1;
+	struct cvmx_pow_iq_thrx_s             cn63xx;
+	struct cvmx_pow_iq_thrx_s             cn63xxp1;
+};
+typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t;
+
+/**
+ * cvmx_pow_nos_cnt
+ *
+ * POW_NOS_CNT = POW No-schedule Count Register
+ *
+ * Contains the number of work queue entries on the no-schedule list.
+ */
+union cvmx_pow_nos_cnt
+{
+	uint64_t u64;
+	struct cvmx_pow_nos_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t nos_cnt                      : 12; /**< # of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 12;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_pow_nos_cnt_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t nos_cnt                      : 7;  /**< # of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 7;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} cn30xx;
+	struct cvmx_pow_nos_cnt_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t nos_cnt                      : 9;  /**< # of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn31xx;
+	struct cvmx_pow_nos_cnt_s             cn38xx;
+	struct cvmx_pow_nos_cnt_s             cn38xxp2;
+	struct cvmx_pow_nos_cnt_cn31xx        cn50xx;
+	struct cvmx_pow_nos_cnt_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t nos_cnt                      : 10; /**< # of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn52xx;
+	struct cvmx_pow_nos_cnt_cn52xx        cn52xxp1;
+	struct cvmx_pow_nos_cnt_s             cn56xx;
+	struct cvmx_pow_nos_cnt_s             cn56xxp1;
+	struct cvmx_pow_nos_cnt_s             cn58xx;
+	struct cvmx_pow_nos_cnt_s             cn58xxp1;
+	struct cvmx_pow_nos_cnt_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t nos_cnt                      : 11; /**< # of work queue entries on the no-schedule list */
+#else
+	uint64_t nos_cnt                      : 11;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} cn63xx;
+	struct cvmx_pow_nos_cnt_cn63xx        cn63xxp1;
+};
+typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t;
+
+/**
+ * cvmx_pow_nw_tim
+ *
+ * POW_NW_TIM = POW New Work Timer Period Register
+ *
+ * Sets the minimum period for a new work request timeout.  Period is specified in n-1 notation
+ * where the increment value is 1024 clock cycles.  Thus, a value of 0x0 in this register translates
+ * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc...  Note: the
+ * maximum period for a new work request timeout is 2 times the minimum period.  Note: the new work
+ * request timeout counter is reset when this register is written.
+ *
+ * There are two new work request timeout cases:
+ *
+ * - WAIT bit clear.  The new work request can timeout if the timer expires before the pre-fetch
+ *   engine has reached the end of all work queues.  This can occur if the executable work queue
+ *   entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high switch,
+ *   de-schedule, or new work load from other PP's).  Thus, it is possible for a PP to receive a work
+ *   response with the NO_WORK bit set even though there was at least one executable entry in the
+ *   work queues.  The other (and typical) scenario for receiving a NO_WORK response with the WAIT
+ *   bit clear is that the pre-fetch engine has reached the end of all work queues without finding
+ *   executable work.
+ *
+ * - WAIT bit set.  The new work request can timeout if the timer expires before the pre-fetch
+ *   engine has found executable work.  In this case, the only scenario where the PP will receive a
+ *   work response with the NO_WORK bit set is if the timer expires.  Note: it is still possible for
+ *   a PP to receive a NO_WORK response even though there was at least one executable entry in the
+ *   work queues.
+ *
+ * In either case, it's important to note that switches and de-schedules are higher priority
+ * operations that can cause the pre-fetch engine to reset.  Thus in a system with many switches or
+ * de-schedules occuring, it's possible for the new work timer to expire (resulting in NO_WORK
+ * responses) before the pre-fetch engine is able to get very deep into the work queues.
+ */
+union cvmx_pow_nw_tim
+{
+	uint64_t u64;
+	struct cvmx_pow_nw_tim_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t nw_tim                       : 10; /**< New work timer period */
+#else
+	uint64_t nw_tim                       : 10;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_pow_nw_tim_s              cn30xx;
+	struct cvmx_pow_nw_tim_s              cn31xx;
+	struct cvmx_pow_nw_tim_s              cn38xx;
+	struct cvmx_pow_nw_tim_s              cn38xxp2;
+	struct cvmx_pow_nw_tim_s              cn50xx;
+	struct cvmx_pow_nw_tim_s              cn52xx;
+	struct cvmx_pow_nw_tim_s              cn52xxp1;
+	struct cvmx_pow_nw_tim_s              cn56xx;
+	struct cvmx_pow_nw_tim_s              cn56xxp1;
+	struct cvmx_pow_nw_tim_s              cn58xx;
+	struct cvmx_pow_nw_tim_s              cn58xxp1;
+	struct cvmx_pow_nw_tim_s              cn63xx;
+	struct cvmx_pow_nw_tim_s              cn63xxp1;
+};
+typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t;
+
+/**
+ * cvmx_pow_pf_rst_msk
+ *
+ * POW_PF_RST_MSK = POW Prefetch Reset Mask
+ *
+ * Resets the work prefetch engine when work is stored in an internal buffer (either when the add
+ * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level
+ * (1 bit per QOS level).
+ */
+union cvmx_pow_pf_rst_msk
+{
+	uint64_t u64;
+	struct cvmx_pow_pf_rst_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t rst_msk                      : 8;  /**< Prefetch engine reset mask */
+#else
+	uint64_t rst_msk                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_pow_pf_rst_msk_s          cn50xx;
+	struct cvmx_pow_pf_rst_msk_s          cn52xx;
+	struct cvmx_pow_pf_rst_msk_s          cn52xxp1;
+	struct cvmx_pow_pf_rst_msk_s          cn56xx;
+	struct cvmx_pow_pf_rst_msk_s          cn56xxp1;
+	struct cvmx_pow_pf_rst_msk_s          cn58xx;
+	struct cvmx_pow_pf_rst_msk_s          cn58xxp1;
+	struct cvmx_pow_pf_rst_msk_s          cn63xx;
+	struct cvmx_pow_pf_rst_msk_s          cn63xxp1;
+};
+typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t;
+
+/**
+ * cvmx_pow_pp_grp_msk#
+ *
+ * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP)
+ *
+ * Selects which group(s) a PP belongs to.  A '1' in any bit position sets the PP's membership in
+ * the corresponding group.  A value of 0x0 will prevent the PP from receiving new work.  Note:
+ * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to
+ * maximize POW performance.
+ *
+ * Also contains the QOS level priorities for each PP.  0x0 is highest priority, and 0x7 the lowest.
+ * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level.
+ * Priority values 0x8 through 0xe are reserved and should not be used.  For a given PP, priorities
+ * should begin at 0x0 and remain contiguous throughout the range.
+ */
+union cvmx_pow_pp_grp_mskx
+{
+	uint64_t u64;
+	struct cvmx_pow_pp_grp_mskx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t qos7_pri                     : 4;  /**< PPX priority for QOS level 7 */
+	uint64_t qos6_pri                     : 4;  /**< PPX priority for QOS level 6 */
+	uint64_t qos5_pri                     : 4;  /**< PPX priority for QOS level 5 */
+	uint64_t qos4_pri                     : 4;  /**< PPX priority for QOS level 4 */
+	uint64_t qos3_pri                     : 4;  /**< PPX priority for QOS level 3 */
+	uint64_t qos2_pri                     : 4;  /**< PPX priority for QOS level 2 */
+	uint64_t qos1_pri                     : 4;  /**< PPX priority for QOS level 1 */
+	uint64_t qos0_pri                     : 4;  /**< PPX priority for QOS level 0 */
+	uint64_t grp_msk                      : 16; /**< PPX group mask */
+#else
+	uint64_t grp_msk                      : 16;
+	uint64_t qos0_pri                     : 4;
+	uint64_t qos1_pri                     : 4;
+	uint64_t qos2_pri                     : 4;
+	uint64_t qos3_pri                     : 4;
+	uint64_t qos4_pri                     : 4;
+	uint64_t qos5_pri                     : 4;
+	uint64_t qos6_pri                     : 4;
+	uint64_t qos7_pri                     : 4;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_pow_pp_grp_mskx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t grp_msk                      : 16; /**< PPX group mask */
+#else
+	uint64_t grp_msk                      : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn30xx;
+	struct cvmx_pow_pp_grp_mskx_cn30xx    cn31xx;
+	struct cvmx_pow_pp_grp_mskx_cn30xx    cn38xx;
+	struct cvmx_pow_pp_grp_mskx_cn30xx    cn38xxp2;
+	struct cvmx_pow_pp_grp_mskx_s         cn50xx;
+	struct cvmx_pow_pp_grp_mskx_s         cn52xx;
+	struct cvmx_pow_pp_grp_mskx_s         cn52xxp1;
+	struct cvmx_pow_pp_grp_mskx_s         cn56xx;
+	struct cvmx_pow_pp_grp_mskx_s         cn56xxp1;
+	struct cvmx_pow_pp_grp_mskx_s         cn58xx;
+	struct cvmx_pow_pp_grp_mskx_s         cn58xxp1;
+	struct cvmx_pow_pp_grp_mskx_s         cn63xx;
+	struct cvmx_pow_pp_grp_mskx_s         cn63xxp1;
+};
+typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t;
+
+/**
+ * cvmx_pow_qos_rnd#
+ *
+ * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds)
+ *
+ * Contains the round definitions for issuing new work.  Each round consists of 8 bits with each bit
+ * corresponding to a QOS level.  There are 4 rounds contained in each register for a total of 32
+ * rounds.  The issue logic traverses through the rounds sequentially (lowest round to highest round)
+ * in an attempt to find new work for each PP.  Within each round, the issue logic traverses through
+ * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear
+ * bit in the round mask.  Note: setting a QOS level to all zeroes in all issue round registers will
+ * prevent work from being issued from that QOS level.
+ */
+union cvmx_pow_qos_rndx
+{
+	uint64_t u64;
+	struct cvmx_pow_qos_rndx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rnd_p3                       : 8;  /**< Round mask for round Xx4+3 */
+	uint64_t rnd_p2                       : 8;  /**< Round mask for round Xx4+2 */
+	uint64_t rnd_p1                       : 8;  /**< Round mask for round Xx4+1 */
+	uint64_t rnd                          : 8;  /**< Round mask for round Xx4 */
+#else
+	uint64_t rnd                          : 8;
+	uint64_t rnd_p1                       : 8;
+	uint64_t rnd_p2                       : 8;
+	uint64_t rnd_p3                       : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_qos_rndx_s            cn30xx;
+	struct cvmx_pow_qos_rndx_s            cn31xx;
+	struct cvmx_pow_qos_rndx_s            cn38xx;
+	struct cvmx_pow_qos_rndx_s            cn38xxp2;
+	struct cvmx_pow_qos_rndx_s            cn50xx;
+	struct cvmx_pow_qos_rndx_s            cn52xx;
+	struct cvmx_pow_qos_rndx_s            cn52xxp1;
+	struct cvmx_pow_qos_rndx_s            cn56xx;
+	struct cvmx_pow_qos_rndx_s            cn56xxp1;
+	struct cvmx_pow_qos_rndx_s            cn58xx;
+	struct cvmx_pow_qos_rndx_s            cn58xxp1;
+	struct cvmx_pow_qos_rndx_s            cn63xx;
+	struct cvmx_pow_qos_rndx_s            cn63xxp1;
+};
+typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t;
+
+/**
+ * cvmx_pow_qos_thr#
+ *
+ * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level)
+ *
+ * Contains the thresholds for allocating POW internal storage buffers.  If the number of remaining
+ * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for
+ * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries
+ * will be buffered externally rather than internally.  This register also contains a read-only count
+ * of the current number of free buffers (FREE_CNT), the number of internal buffers currently
+ * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list
+ * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).
+ */
+union cvmx_pow_qos_thrx
+{
+	uint64_t u64;
+	struct cvmx_pow_qos_thrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t des_cnt                      : 12; /**< # of buffers on de-schedule list */
+	uint64_t buf_cnt                      : 12; /**< # of internal buffers allocated to QOS level X */
+	uint64_t free_cnt                     : 12; /**< # of total free buffers */
+	uint64_t reserved_23_23               : 1;
+	uint64_t max_thr                      : 11; /**< Max threshold for QOS level X */
+	uint64_t reserved_11_11               : 1;
+	uint64_t min_thr                      : 11; /**< Min threshold for QOS level X */
+#else
+	uint64_t min_thr                      : 11;
+	uint64_t reserved_11_11               : 1;
+	uint64_t max_thr                      : 11;
+	uint64_t reserved_23_23               : 1;
+	uint64_t free_cnt                     : 12;
+	uint64_t buf_cnt                      : 12;
+	uint64_t des_cnt                      : 12;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_pow_qos_thrx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_55_63               : 9;
+	uint64_t des_cnt                      : 7;  /**< # of buffers on de-schedule list */
+	uint64_t reserved_43_47               : 5;
+	uint64_t buf_cnt                      : 7;  /**< # of internal buffers allocated to QOS level X */
+	uint64_t reserved_31_35               : 5;
+	uint64_t free_cnt                     : 7;  /**< # of total free buffers */
+	uint64_t reserved_18_23               : 6;
+	uint64_t max_thr                      : 6;  /**< Max threshold for QOS level X */
+	uint64_t reserved_6_11                : 6;
+	uint64_t min_thr                      : 6;  /**< Min threshold for QOS level X */
+#else
+	uint64_t min_thr                      : 6;
+	uint64_t reserved_6_11                : 6;
+	uint64_t max_thr                      : 6;
+	uint64_t reserved_18_23               : 6;
+	uint64_t free_cnt                     : 7;
+	uint64_t reserved_31_35               : 5;
+	uint64_t buf_cnt                      : 7;
+	uint64_t reserved_43_47               : 5;
+	uint64_t des_cnt                      : 7;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} cn30xx;
+	struct cvmx_pow_qos_thrx_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_57_63               : 7;
+	uint64_t des_cnt                      : 9;  /**< # of buffers on de-schedule list */
+	uint64_t reserved_45_47               : 3;
+	uint64_t buf_cnt                      : 9;  /**< # of internal buffers allocated to QOS level X */
+	uint64_t reserved_33_35               : 3;
+	uint64_t free_cnt                     : 9;  /**< # of total free buffers */
+	uint64_t reserved_20_23               : 4;
+	uint64_t max_thr                      : 8;  /**< Max threshold for QOS level X */
+	uint64_t reserved_8_11                : 4;
+	uint64_t min_thr                      : 8;  /**< Min threshold for QOS level X */
+#else
+	uint64_t min_thr                      : 8;
+	uint64_t reserved_8_11                : 4;
+	uint64_t max_thr                      : 8;
+	uint64_t reserved_20_23               : 4;
+	uint64_t free_cnt                     : 9;
+	uint64_t reserved_33_35               : 3;
+	uint64_t buf_cnt                      : 9;
+	uint64_t reserved_45_47               : 3;
+	uint64_t des_cnt                      : 9;
+	uint64_t reserved_57_63               : 7;
+#endif
+	} cn31xx;
+	struct cvmx_pow_qos_thrx_s            cn38xx;
+	struct cvmx_pow_qos_thrx_s            cn38xxp2;
+	struct cvmx_pow_qos_thrx_cn31xx       cn50xx;
+	struct cvmx_pow_qos_thrx_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t des_cnt                      : 10; /**< # of buffers on de-schedule list */
+	uint64_t reserved_46_47               : 2;
+	uint64_t buf_cnt                      : 10; /**< # of internal buffers allocated to QOS level X */
+	uint64_t reserved_34_35               : 2;
+	uint64_t free_cnt                     : 10; /**< # of total free buffers */
+	uint64_t reserved_21_23               : 3;
+	uint64_t max_thr                      : 9;  /**< Max threshold for QOS level X */
+	uint64_t reserved_9_11                : 3;
+	uint64_t min_thr                      : 9;  /**< Min threshold for QOS level X */
+#else
+	uint64_t min_thr                      : 9;
+	uint64_t reserved_9_11                : 3;
+	uint64_t max_thr                      : 9;
+	uint64_t reserved_21_23               : 3;
+	uint64_t free_cnt                     : 10;
+	uint64_t reserved_34_35               : 2;
+	uint64_t buf_cnt                      : 10;
+	uint64_t reserved_46_47               : 2;
+	uint64_t des_cnt                      : 10;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} cn52xx;
+	struct cvmx_pow_qos_thrx_cn52xx       cn52xxp1;
+	struct cvmx_pow_qos_thrx_s            cn56xx;
+	struct cvmx_pow_qos_thrx_s            cn56xxp1;
+	struct cvmx_pow_qos_thrx_s            cn58xx;
+	struct cvmx_pow_qos_thrx_s            cn58xxp1;
+	struct cvmx_pow_qos_thrx_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_59_63               : 5;
+	uint64_t des_cnt                      : 11; /**< # of buffers on de-schedule list */
+	uint64_t reserved_47_47               : 1;
+	uint64_t buf_cnt                      : 11; /**< # of internal buffers allocated to QOS level X */
+	uint64_t reserved_35_35               : 1;
+	uint64_t free_cnt                     : 11; /**< # of total free buffers */
+	uint64_t reserved_22_23               : 2;
+	uint64_t max_thr                      : 10; /**< Max threshold for QOS level X */
+	uint64_t reserved_10_11               : 2;
+	uint64_t min_thr                      : 10; /**< Min threshold for QOS level X */
+#else
+	uint64_t min_thr                      : 10;
+	uint64_t reserved_10_11               : 2;
+	uint64_t max_thr                      : 10;
+	uint64_t reserved_22_23               : 2;
+	uint64_t free_cnt                     : 11;
+	uint64_t reserved_35_35               : 1;
+	uint64_t buf_cnt                      : 11;
+	uint64_t reserved_47_47               : 1;
+	uint64_t des_cnt                      : 11;
+	uint64_t reserved_59_63               : 5;
+#endif
+	} cn63xx;
+	struct cvmx_pow_qos_thrx_cn63xx       cn63xxp1;
+};
+typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t;
+
+/**
+ * cvmx_pow_ts_pc
+ *
+ * POW_TS_PC = POW Tag Switch Performance Counter
+ *
+ * Counts the number of tag switch requests.  Write to clear.
+ */
+union cvmx_pow_ts_pc
+{
+	uint64_t u64;
+	struct cvmx_pow_ts_pc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ts_pc                        : 32; /**< Tag switch performance counter */
+#else
+	uint64_t ts_pc                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_ts_pc_s               cn30xx;
+	struct cvmx_pow_ts_pc_s               cn31xx;
+	struct cvmx_pow_ts_pc_s               cn38xx;
+	struct cvmx_pow_ts_pc_s               cn38xxp2;
+	struct cvmx_pow_ts_pc_s               cn50xx;
+	struct cvmx_pow_ts_pc_s               cn52xx;
+	struct cvmx_pow_ts_pc_s               cn52xxp1;
+	struct cvmx_pow_ts_pc_s               cn56xx;
+	struct cvmx_pow_ts_pc_s               cn56xxp1;
+	struct cvmx_pow_ts_pc_s               cn58xx;
+	struct cvmx_pow_ts_pc_s               cn58xxp1;
+	struct cvmx_pow_ts_pc_s               cn63xx;
+	struct cvmx_pow_ts_pc_s               cn63xxp1;
+};
+typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t;
+
+/**
+ * cvmx_pow_wa_com_pc
+ *
+ * POW_WA_COM_PC = POW Work Add Combined Performance Counter
+ *
+ * Counts the number of add new work requests for all QOS levels.  Write to clear.
+ */
+union cvmx_pow_wa_com_pc
+{
+	uint64_t u64;
+	struct cvmx_pow_wa_com_pc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wa_pc                        : 32; /**< Work add combined performance counter */
+#else
+	uint64_t wa_pc                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_wa_com_pc_s           cn30xx;
+	struct cvmx_pow_wa_com_pc_s           cn31xx;
+	struct cvmx_pow_wa_com_pc_s           cn38xx;
+	struct cvmx_pow_wa_com_pc_s           cn38xxp2;
+	struct cvmx_pow_wa_com_pc_s           cn50xx;
+	struct cvmx_pow_wa_com_pc_s           cn52xx;
+	struct cvmx_pow_wa_com_pc_s           cn52xxp1;
+	struct cvmx_pow_wa_com_pc_s           cn56xx;
+	struct cvmx_pow_wa_com_pc_s           cn56xxp1;
+	struct cvmx_pow_wa_com_pc_s           cn58xx;
+	struct cvmx_pow_wa_com_pc_s           cn58xxp1;
+	struct cvmx_pow_wa_com_pc_s           cn63xx;
+	struct cvmx_pow_wa_com_pc_s           cn63xxp1;
+};
+typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t;
+
+/**
+ * cvmx_pow_wa_pc#
+ *
+ * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level)
+ *
+ * Counts the number of add new work requests for each QOS level.  Write to clear.
+ */
+union cvmx_pow_wa_pcx
+{
+	uint64_t u64;
+	struct cvmx_pow_wa_pcx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wa_pc                        : 32; /**< Work add performance counter for QOS level X */
+#else
+	uint64_t wa_pc                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_wa_pcx_s              cn30xx;
+	struct cvmx_pow_wa_pcx_s              cn31xx;
+	struct cvmx_pow_wa_pcx_s              cn38xx;
+	struct cvmx_pow_wa_pcx_s              cn38xxp2;
+	struct cvmx_pow_wa_pcx_s              cn50xx;
+	struct cvmx_pow_wa_pcx_s              cn52xx;
+	struct cvmx_pow_wa_pcx_s              cn52xxp1;
+	struct cvmx_pow_wa_pcx_s              cn56xx;
+	struct cvmx_pow_wa_pcx_s              cn56xxp1;
+	struct cvmx_pow_wa_pcx_s              cn58xx;
+	struct cvmx_pow_wa_pcx_s              cn58xxp1;
+	struct cvmx_pow_wa_pcx_s              cn63xx;
+	struct cvmx_pow_wa_pcx_s              cn63xxp1;
+};
+typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t;
+
+/**
+ * cvmx_pow_wq_int
+ *
+ * POW_WQ_INT = POW Work Queue Interrupt Register
+ *
+ * Contains the bits (1 per group) that set work queue interrupts and are used to clear these
+ * interrupts.  Also contains the input queue interrupt temporary disable bits (1 per group).  For
+ * more information regarding this register, see the interrupt section.
+ */
+union cvmx_pow_wq_int
+{
+	uint64_t u64;
+	struct cvmx_pow_wq_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iq_dis                       : 16; /**< Input queue interrupt temporary disable mask
+                                                         Corresponding WQ_INT<*> bit cannot be set due to
+                                                         IQ_CNT/IQ_THR check when this bit is set.
+                                                         Corresponding IQ_DIS bit is cleared by HW whenever:
+                                                          - POW_WQ_INT_CNT*[IQ_CNT] is zero, or
+                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
+                                                            counter POW_WQ_INT_PC[PC]==0 */
+	uint64_t wq_int                       : 16; /**< Work queue interrupt bits
+                                                         Corresponding WQ_INT bit is set by HW whenever:
+                                                          - POW_WQ_INT_CNT*[IQ_CNT] >=
+                                                            POW_WQ_INT_THR*[IQ_THR] and the threshold
+                                                            interrupt is not disabled.
+                                                            IQ_DIS<*>==1 disables the interrupt.
+                                                            POW_WQ_INT_THR*[IQ_THR]==0 disables the int.
+                                                          - POW_WQ_INT_CNT*[DS_CNT] >=
+                                                            POW_WQ_INT_THR*[DS_THR] and the threshold
+                                                            interrupt is not disabled
+                                                            POW_WQ_INT_THR*[DS_THR]==0 disables the int.
+                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
+                                                            counter POW_WQ_INT_PC[PC]==0 and
+                                                            POW_WQ_INT_THR*[TC_EN]==1 and at least one of:
+                                                            - POW_WQ_INT_CNT*[IQ_CNT] > 0
+                                                            - POW_WQ_INT_CNT*[DS_CNT] > 0 */
+#else
+	uint64_t wq_int                       : 16;
+	uint64_t iq_dis                       : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_wq_int_s              cn30xx;
+	struct cvmx_pow_wq_int_s              cn31xx;
+	struct cvmx_pow_wq_int_s              cn38xx;
+	struct cvmx_pow_wq_int_s              cn38xxp2;
+	struct cvmx_pow_wq_int_s              cn50xx;
+	struct cvmx_pow_wq_int_s              cn52xx;
+	struct cvmx_pow_wq_int_s              cn52xxp1;
+	struct cvmx_pow_wq_int_s              cn56xx;
+	struct cvmx_pow_wq_int_s              cn56xxp1;
+	struct cvmx_pow_wq_int_s              cn58xx;
+	struct cvmx_pow_wq_int_s              cn58xxp1;
+	struct cvmx_pow_wq_int_s              cn63xx;
+	struct cvmx_pow_wq_int_s              cn63xxp1;
+};
+typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t;
+
+/**
+ * cvmx_pow_wq_int_cnt#
+ *
+ * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group)
+ *
+ * Contains a read-only copy of the counts used to trigger work queue interrupts.  For more
+ * information regarding this register, see the interrupt section.
+ */
+union cvmx_pow_wq_int_cntx
+{
+	uint64_t u64;
+	struct cvmx_pow_wq_int_cntx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+	uint64_t ds_cnt                       : 12; /**< De-schedule executable count for group X */
+	uint64_t iq_cnt                       : 12; /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 12;
+	uint64_t ds_cnt                       : 12;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_pow_wq_int_cntx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+	uint64_t reserved_19_23               : 5;
+	uint64_t ds_cnt                       : 7;  /**< De-schedule executable count for group X */
+	uint64_t reserved_7_11                : 5;
+	uint64_t iq_cnt                       : 7;  /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 7;
+	uint64_t reserved_7_11                : 5;
+	uint64_t ds_cnt                       : 7;
+	uint64_t reserved_19_23               : 5;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn30xx;
+	struct cvmx_pow_wq_int_cntx_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ds_cnt                       : 9;  /**< De-schedule executable count for group X */
+	uint64_t reserved_9_11                : 3;
+	uint64_t iq_cnt                       : 9;  /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 9;
+	uint64_t reserved_9_11                : 3;
+	uint64_t ds_cnt                       : 9;
+	uint64_t reserved_21_23               : 3;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn31xx;
+	struct cvmx_pow_wq_int_cntx_s         cn38xx;
+	struct cvmx_pow_wq_int_cntx_s         cn38xxp2;
+	struct cvmx_pow_wq_int_cntx_cn31xx    cn50xx;
+	struct cvmx_pow_wq_int_cntx_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+	uint64_t reserved_22_23               : 2;
+	uint64_t ds_cnt                       : 10; /**< De-schedule executable count for group X */
+	uint64_t reserved_10_11               : 2;
+	uint64_t iq_cnt                       : 10; /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 10;
+	uint64_t reserved_10_11               : 2;
+	uint64_t ds_cnt                       : 10;
+	uint64_t reserved_22_23               : 2;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn52xx;
+	struct cvmx_pow_wq_int_cntx_cn52xx    cn52xxp1;
+	struct cvmx_pow_wq_int_cntx_s         cn56xx;
+	struct cvmx_pow_wq_int_cntx_s         cn56xxp1;
+	struct cvmx_pow_wq_int_cntx_s         cn58xx;
+	struct cvmx_pow_wq_int_cntx_s         cn58xxp1;
+	struct cvmx_pow_wq_int_cntx_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t tc_cnt                       : 4;  /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+	uint64_t reserved_23_23               : 1;
+	uint64_t ds_cnt                       : 11; /**< De-schedule executable count for group X */
+	uint64_t reserved_11_11               : 1;
+	uint64_t iq_cnt                       : 11; /**< Input queue executable count for group X */
+#else
+	uint64_t iq_cnt                       : 11;
+	uint64_t reserved_11_11               : 1;
+	uint64_t ds_cnt                       : 11;
+	uint64_t reserved_23_23               : 1;
+	uint64_t tc_cnt                       : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} cn63xx;
+	struct cvmx_pow_wq_int_cntx_cn63xx    cn63xxp1;
+};
+typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t;
+
+/**
+ * cvmx_pow_wq_int_pc
+ *
+ * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register
+ *
+ * Contains the threshold value for the work queue interrupt periodic counter and also a read-only
+ * copy of the periodic counter.  For more information regarding this register, see the interrupt
+ * section.
+ */
+union cvmx_pow_wq_int_pc
+{
+	uint64_t u64;
+	struct cvmx_pow_wq_int_pc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_60_63               : 4;
+	uint64_t pc                           : 28; /**< Work queue interrupt periodic counter */
+	uint64_t reserved_28_31               : 4;
+	uint64_t pc_thr                       : 20; /**< Work queue interrupt periodic counter threshold */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t pc_thr                       : 20;
+	uint64_t reserved_28_31               : 4;
+	uint64_t pc                           : 28;
+	uint64_t reserved_60_63               : 4;
+#endif
+	} s;
+	struct cvmx_pow_wq_int_pc_s           cn30xx;
+	struct cvmx_pow_wq_int_pc_s           cn31xx;
+	struct cvmx_pow_wq_int_pc_s           cn38xx;
+	struct cvmx_pow_wq_int_pc_s           cn38xxp2;
+	struct cvmx_pow_wq_int_pc_s           cn50xx;
+	struct cvmx_pow_wq_int_pc_s           cn52xx;
+	struct cvmx_pow_wq_int_pc_s           cn52xxp1;
+	struct cvmx_pow_wq_int_pc_s           cn56xx;
+	struct cvmx_pow_wq_int_pc_s           cn56xxp1;
+	struct cvmx_pow_wq_int_pc_s           cn58xx;
+	struct cvmx_pow_wq_int_pc_s           cn58xxp1;
+	struct cvmx_pow_wq_int_pc_s           cn63xx;
+	struct cvmx_pow_wq_int_pc_s           cn63xxp1;
+};
+typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t;
+
+/**
+ * cvmx_pow_wq_int_thr#
+ *
+ * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group)
+ *
+ * Contains the thresholds for enabling and setting work queue interrupts.  For more information
+ * regarding this register, see the interrupt section.
+ *
+ * Note: Up to 8 of the POW's internal storage buffers can be allocated for hardware use and are
+ * therefore not available for incoming work queue entries.  Additionally, any PP that is not in the
+ * NULL_NULL state consumes a buffer.  Thus in a 6 PP system, it is not advisable to set either
+ * IQ_THR or DS_THR to greater than 1024 - 8 - 6 = 1010.  Doing so may prevent the interrupt from
+ * ever triggering.
+ */
+union cvmx_pow_wq_int_thrx
+{
+	uint64_t u64;
+	struct cvmx_pow_wq_int_thrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+	uint64_t reserved_23_23               : 1;
+	uint64_t ds_thr                       : 11; /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_11_11               : 1;
+	uint64_t iq_thr                       : 11; /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 11;
+	uint64_t reserved_11_11               : 1;
+	uint64_t ds_thr                       : 11;
+	uint64_t reserved_23_23               : 1;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} s;
+	struct cvmx_pow_wq_int_thrx_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+	uint64_t reserved_18_23               : 6;
+	uint64_t ds_thr                       : 6;  /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_6_11                : 6;
+	uint64_t iq_thr                       : 6;  /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 6;
+	uint64_t reserved_6_11                : 6;
+	uint64_t ds_thr                       : 6;
+	uint64_t reserved_18_23               : 6;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn30xx;
+	struct cvmx_pow_wq_int_thrx_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+	uint64_t reserved_20_23               : 4;
+	uint64_t ds_thr                       : 8;  /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_8_11                : 4;
+	uint64_t iq_thr                       : 8;  /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 8;
+	uint64_t reserved_8_11                : 4;
+	uint64_t ds_thr                       : 8;
+	uint64_t reserved_20_23               : 4;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn31xx;
+	struct cvmx_pow_wq_int_thrx_s         cn38xx;
+	struct cvmx_pow_wq_int_thrx_s         cn38xxp2;
+	struct cvmx_pow_wq_int_thrx_cn31xx    cn50xx;
+	struct cvmx_pow_wq_int_thrx_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+	uint64_t reserved_21_23               : 3;
+	uint64_t ds_thr                       : 9;  /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_9_11                : 3;
+	uint64_t iq_thr                       : 9;  /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 9;
+	uint64_t reserved_9_11                : 3;
+	uint64_t ds_thr                       : 9;
+	uint64_t reserved_21_23               : 3;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn52xx;
+	struct cvmx_pow_wq_int_thrx_cn52xx    cn52xxp1;
+	struct cvmx_pow_wq_int_thrx_s         cn56xx;
+	struct cvmx_pow_wq_int_thrx_s         cn56xxp1;
+	struct cvmx_pow_wq_int_thrx_s         cn58xx;
+	struct cvmx_pow_wq_int_thrx_s         cn58xxp1;
+	struct cvmx_pow_wq_int_thrx_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_29_63               : 35;
+	uint64_t tc_en                        : 1;  /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+	uint64_t tc_thr                       : 4;  /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+	uint64_t reserved_22_23               : 2;
+	uint64_t ds_thr                       : 10; /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+	uint64_t reserved_10_11               : 2;
+	uint64_t iq_thr                       : 10; /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+	uint64_t iq_thr                       : 10;
+	uint64_t reserved_10_11               : 2;
+	uint64_t ds_thr                       : 10;
+	uint64_t reserved_22_23               : 2;
+	uint64_t tc_thr                       : 4;
+	uint64_t tc_en                        : 1;
+	uint64_t reserved_29_63               : 35;
+#endif
+	} cn63xx;
+	struct cvmx_pow_wq_int_thrx_cn63xx    cn63xxp1;
+};
+typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t;
+
+/**
+ * cvmx_pow_ws_pc#
+ *
+ * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group)
+ *
+ * Counts the number of work schedules for each group.  Write to clear.
+ */
+union cvmx_pow_ws_pcx
+{
+	uint64_t u64;
+	struct cvmx_pow_ws_pcx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ws_pc                        : 32; /**< Work schedule performance counter for group X */
+#else
+	uint64_t ws_pc                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_pow_ws_pcx_s              cn30xx;
+	struct cvmx_pow_ws_pcx_s              cn31xx;
+	struct cvmx_pow_ws_pcx_s              cn38xx;
+	struct cvmx_pow_ws_pcx_s              cn38xxp2;
+	struct cvmx_pow_ws_pcx_s              cn50xx;
+	struct cvmx_pow_ws_pcx_s              cn52xx;
+	struct cvmx_pow_ws_pcx_s              cn52xxp1;
+	struct cvmx_pow_ws_pcx_s              cn56xx;
+	struct cvmx_pow_ws_pcx_s              cn56xxp1;
+	struct cvmx_pow_ws_pcx_s              cn58xx;
+	struct cvmx_pow_ws_pcx_s              cn58xxp1;
+	struct cvmx_pow_ws_pcx_s              cn63xx;
+	struct cvmx_pow_ws_pcx_s              cn63xxp1;
+};
+typedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pow.c b/sys/contrib/octeon-sdk/cvmx-pow.c
index 2a0902a..f34a9c1 100644
--- a/sys/contrib/octeon-sdk/cvmx-pow.c
+++ b/sys/contrib/octeon-sdk/cvmx-pow.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -108,6 +110,8 @@ int cvmx_pow_get_num_entries(void)
         return 256;
     else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
         return 512;
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+	return 1024;
     else
         return 2048;
 }
@@ -396,16 +400,14 @@ void cvmx_pow_display(void *buffer, int buffer_size)
         printf("\n");
     }
 
-    /* Print out the state of the 16 deschedule lists. Each group has two
-        lists. One for entries marked noshed, the other for normal
-        deschedules */
+    /* Print out the state of the nosched list and the 16 deschedule lists. */
+    __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_NOSCHED, dump, entry_list,
+                            dump->sindexload[0][2].sindexload1.nosched_val,
+                            dump->sindexload[0][2].sindexload1.nosched_one,
+                            dump->sindexload[0][2].sindexload1.nosched_head,
+                            dump->sindexload[0][2].sindexload1.nosched_tail);
     for (index=0; index<16; index++)
     {
-        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_NOSCHED + index, dump, entry_list,
-                                dump->sindexload[index][2].sindexload1.nosched_val,
-                                dump->sindexload[index][2].sindexload1.nosched_one,
-                                dump->sindexload[index][2].sindexload1.nosched_head,
-                                dump->sindexload[index][2].sindexload1.nosched_tail);
         __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_DESCHED + index, dump, entry_list,
                                 dump->sindexload[index][2].sindexload1.des_val,
                                 dump->sindexload[index][2].sindexload1.des_one,
diff --git a/sys/contrib/octeon-sdk/cvmx-pow.h b/sys/contrib/octeon-sdk/cvmx-pow.h
index dea5652..a398a41 100644
--- a/sys/contrib/octeon-sdk/cvmx-pow.h
+++ b/sys/contrib/octeon-sdk/cvmx-pow.h
@@ -1,46 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
@@ -64,7 +61,7 @@
  * - WQE pointer not matching the one attached to the core by
  *   the POW.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_POW_H__
@@ -72,7 +69,10 @@
 
 #include "cvmx-scratch.h"
 #include "cvmx-wqe.h"
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-warn.h"
+#endif
 
 #ifdef	__cplusplus
 extern "C" {
@@ -842,7 +842,7 @@ typedef union
 } cvmx_pow_iobdma_store_t;
 
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-pow-defs.h */
 
 /**
  * Get the POW tag for this core. This returns the current
@@ -1539,7 +1539,7 @@ static inline void cvmx_pow_tag_sw_desched_nocheck(uint32_t tag, cvmx_pow_tag_ty
     ptr.sio.is_io = 1;
     ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
 
-    cvmx_write_io(ptr.u64, tag_req.u64); // since TAG3 is used, this store will clear the local pending switch bit
+    cvmx_write_io(ptr.u64, tag_req.u64); /* since TAG3 is used, this store will clear the local pending switch bit */
 }
 /**
  * Performs a tag switch and then an immediate deschedule. This completes
@@ -1631,7 +1631,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
     ptr.sio.is_io = 1;
     ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
 
-    cvmx_write_io(ptr.u64, tag_req.u64); // since TAG3 is used, this store will clear the local pending switch bit
+    cvmx_write_io(ptr.u64, tag_req.u64); /* since TAG3 is used, this store will clear the local pending switch bit */
 }
 
 
@@ -1746,4 +1746,4 @@ extern int cvmx_pow_get_num_entries(void);
 }
 #endif
 
-#endif  // __CVMX_POW_H__
+#endif  /* __CVMX_POW_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-power-throttle.c b/sys/contrib/octeon-sdk/cvmx-power-throttle.c
new file mode 100644
index 0000000..9ca4044
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-power-throttle.c
@@ -0,0 +1,152 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to power-throttle control, measurement, and debugging
+ * facilities.
+ *
+ * <hr>$Revision<hr>
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-asm.h"
+#include "cvmx-power-throttle.h"
+
+#define CVMX_PTH_PPID_BCAST	63
+#define CVMX_PTH_PPID_MAX	64
+
+/**
+ * @INTERNAL
+ * Set the POWLIM field as percentage% of the MAXPOW field in r.
+ */
+static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t t;
+
+        assert(percentage < 101);
+        t = percentage * cvmx_power_throttle_get_field(CVMX_PTH_INDEX_MAXPOW, r) / 100;
+        r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t);
+
+        return r;
+    }
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR
+ * address. (ppid == PTH_PPID_BCAST is for broadcasting)
+ */
+static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t csr_addr, reg_num, reg_reg, reg_sel;
+
+        assert(ppid < CVMX_PTH_PPID_MAX);
+        /*
+         * register 11 selection 6
+         */
+        reg_reg = 11;
+        reg_sel = 6;
+        reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel;
+        csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3);
+
+        return csr_addr;
+    }
+    return 0;
+}
+
+/**
+ * Throttle power to percentage% of configured maximum (MAXPOW).
+ *
+ * @param percentage	0 to 100
+ * @return 0 for success
+ */
+int cvmx_power_throttle_self(uint8_t percentage)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t r; 
+
+        CVMX_MF_COP0(r, COP0_POWTHROTTLE);
+        r = __cvmx_power_throttle_set_powlim(r, percentage);
+        CVMX_MT_COP0(r, COP0_POWTHROTTLE);
+    }
+
+    return 0;
+}
+
+/**
+ * Throttle power to percentage% of configured maximum (MAXPOW)
+ * for the cores identified in coremask.
+ *
+ * @param percentage 	0 to 100
+ * @param coremask	bit mask where each bit identifies a core.
+ * @return 0 for success.
+ */
+int cvmx_power_throttle(uint8_t percentage, uint64_t coremask)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t ppid, csr_addr, b, r;
+
+        b = 1;
+        /*
+         * cvmx_read_csr() for PTH_PPID_BCAST does not make sense and
+         * therefore limit ppid to less.
+         */
+        for (ppid = 0; ppid < CVMX_PTH_PPID_BCAST; ppid ++)
+        {
+            if ((b << ppid) & coremask) {
+                csr_addr = __cvmx_power_throttle_csr_addr(ppid);
+                r = cvmx_read_csr(csr_addr);
+                r = __cvmx_power_throttle_set_powlim(r, percentage);
+                cvmx_write_csr(csr_addr, r);
+            }
+        }
+    }
+
+    return 0;
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-power-throttle.h b/sys/contrib/octeon-sdk/cvmx-power-throttle.h
new file mode 100644
index 0000000..7f921af
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-power-throttle.h
@@ -0,0 +1,137 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to power-throttle control, measurement, and debugging
+ * facilities.
+ *
+ * <hr>$Revision<hr>
+ *
+ */
+
+#ifndef __CVMX_POWER_THROTTLE_H__
+#define __CVMX_POWER_THROTTLE_H__
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * a field of the POWTHROTTLE register
+ */
+static struct cvmx_power_throttle_rfield_t {
+	char	name[16];	/* the field's name */
+	int32_t	pos;		/* position of the field's LSb */
+	int32_t	len;		/* the field's length */
+} cvmx_power_throttle_rfield[] = {
+#define CVMX_PTH_INDEX_MAXPOW	0
+	{"MAXPOW",   56,  8},
+#define CVMX_PTH_INDEX_POWER		1
+	{"POWER" ,   48,  8},
+#define CVMX_PTH_INDEX_THROTT	2
+	{"THROTT",   40,  8},
+#define CVMX_PTH_INDEX_RESERVED	3
+	{"Reserved", 28, 12},
+#define CVMX_PTH_INDEX_DISTAG	4
+	{"DISTAG",   27,  1},
+#define CVMX_PTH_INDEX_PERIOD	5
+	{"PERIOD",   24,  3},
+#define CVMX_PTH_INDEX_POWLIM	6
+	{"POWLIM",   16,  8},
+#define CVMX_PTH_INDEX_MAXTHR	7
+	{"MAXTHR",    8,  8},
+#define CVMX_PTH_INDEX_MINTHR	8
+	{"MINTHR",    0,  8}
+#define CVMX_PTH_INDEX_MAX		9
+};
+
+#define CVMX_PTH_GET_MASK(len, pos) \
+	((((uint64_t)1 << (len)) - 1) << (pos))
+
+/**
+ * Get the i'th field of power-throttle register r.
+ */
+static inline uint64_t cvmx_power_throttle_get_field(int i, uint64_t r)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t m;
+        struct cvmx_power_throttle_rfield_t *p;
+
+        assert((i >= 0) && (i < CVMX_PTH_INDEX_MAX));
+
+        p = &cvmx_power_throttle_rfield[i];
+        m = CVMX_PTH_GET_MASK(p->len, p->pos);
+
+        return((r & m) >> p->pos);
+    }
+    return 0;
+}
+
+/**
+ * Set the i'th field of power-throttle register r to v.
+ */
+static inline int cvmx_power_throttle_set_field(int i, uint64_t r, uint64_t v)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    {
+        uint64_t m;
+        struct cvmx_power_throttle_rfield_t *p;
+
+        assert((i >= 0) && (i < CVMX_PTH_INDEX_MAX));
+
+        p = &cvmx_power_throttle_rfield[i];
+        m = CVMX_PTH_GET_MASK(p->len, p->pos);
+
+        return((~m & r) | ((v << p->pos) & m));
+    }
+    return 0;
+}
+
+/**
+ * API Function Prototypes
+ */
+extern int cvmx_power_throttle_self(uint8_t percentage);
+extern int cvmx_power_throttle(uint8_t percentage, uint64_t coremask);
+
+#ifdef	__cplusplus
+}
+#endif
+#endif /* __CVMX_POWER_THROTTLE_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-rad-defs.h b/sys/contrib/octeon-sdk/cvmx-rad-defs.h
new file mode 100644
index 0000000..374fabe
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-rad-defs.h
@@ -0,0 +1,1006 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-rad-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon rad.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_RAD_TYPEDEFS_H__
+#define __CVMX_RAD_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070001000ull);
+}
+#else
+#define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070001008ull);
+}
+#else
+#define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070001010ull);
+}
+#else
+#define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000080ull);
+}
+#else
+#define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
+static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000008ull);
+}
+#else
+#define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
+static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000000ull);
+}
+#else
+#define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000100ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000108ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000150ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000158ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000160ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000110ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000118ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000120ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000128ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000130ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000138ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000140ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000148ull);
+}
+#else
+#define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
+static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000088ull);
+}
+#else
+#define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000090ull);
+}
+#else
+#define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
+static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000010ull);
+}
+#else
+#define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180070000018ull);
+}
+#else
+#define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull))
+#endif
+
+/**
+ * cvmx_rad_mem_debug0
+ *
+ * Notes:
+ * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_rad_mem_debug0
+{
+	uint64_t u64;
+	struct cvmx_rad_mem_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t iword                        : 64; /**< IWord */
+#else
+	uint64_t iword                        : 64;
+#endif
+	} s;
+	struct cvmx_rad_mem_debug0_s          cn52xx;
+	struct cvmx_rad_mem_debug0_s          cn52xxp1;
+	struct cvmx_rad_mem_debug0_s          cn56xx;
+	struct cvmx_rad_mem_debug0_s          cn56xxp1;
+	struct cvmx_rad_mem_debug0_s          cn63xx;
+	struct cvmx_rad_mem_debug0_s          cn63xxp1;
+};
+typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
+
+/**
+ * cvmx_rad_mem_debug1
+ *
+ * Notes:
+ * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_rad_mem_debug1
+{
+	uint64_t u64;
+	struct cvmx_rad_mem_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t p_dat                        : 64; /**< P data */
+#else
+	uint64_t p_dat                        : 64;
+#endif
+	} s;
+	struct cvmx_rad_mem_debug1_s          cn52xx;
+	struct cvmx_rad_mem_debug1_s          cn52xxp1;
+	struct cvmx_rad_mem_debug1_s          cn56xx;
+	struct cvmx_rad_mem_debug1_s          cn56xxp1;
+	struct cvmx_rad_mem_debug1_s          cn63xx;
+	struct cvmx_rad_mem_debug1_s          cn63xxp1;
+};
+typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
+
+/**
+ * cvmx_rad_mem_debug2
+ *
+ * Notes:
+ * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+union cvmx_rad_mem_debug2
+{
+	uint64_t u64;
+	struct cvmx_rad_mem_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t q_dat                        : 64; /**< Q data */
+#else
+	uint64_t q_dat                        : 64;
+#endif
+	} s;
+	struct cvmx_rad_mem_debug2_s          cn52xx;
+	struct cvmx_rad_mem_debug2_s          cn52xxp1;
+	struct cvmx_rad_mem_debug2_s          cn56xx;
+	struct cvmx_rad_mem_debug2_s          cn56xxp1;
+	struct cvmx_rad_mem_debug2_s          cn63xx;
+	struct cvmx_rad_mem_debug2_s          cn63xxp1;
+};
+typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
+
+/**
+ * cvmx_rad_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_rad_reg_bist_result
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_bist_result_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t sta                          : 1;  /**< BiST result of the STA     memories */
+	uint64_t ncb_oub                      : 1;  /**< BiST result of the NCB_OUB memories */
+	uint64_t ncb_inb                      : 2;  /**< BiST result of the NCB_INB memories */
+	uint64_t dat                          : 2;  /**< BiST result of the DAT     memories */
+#else
+	uint64_t dat                          : 2;
+	uint64_t ncb_inb                      : 2;
+	uint64_t ncb_oub                      : 1;
+	uint64_t sta                          : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_rad_reg_bist_result_s     cn52xx;
+	struct cvmx_rad_reg_bist_result_s     cn52xxp1;
+	struct cvmx_rad_reg_bist_result_s     cn56xx;
+	struct cvmx_rad_reg_bist_result_s     cn56xxp1;
+	struct cvmx_rad_reg_bist_result_s     cn63xx;
+	struct cvmx_rad_reg_bist_result_s     cn63xxp1;
+};
+typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
+
+/**
+ * cvmx_rad_reg_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies 1 of 8 free
+ * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
+ * pointer each time that the command buffer segment is exhausted.
+ */
+union cvmx_rad_reg_cmd_buf
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_cmd_buf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t dwb                          : 9;  /**< Number of DontWriteBacks */
+	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
+	uint64_t size                         : 13; /**< Number of uint64s per command buffer segment */
+	uint64_t ptr                          : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t size                         : 13;
+	uint64_t pool                         : 3;
+	uint64_t dwb                          : 9;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_rad_reg_cmd_buf_s         cn52xx;
+	struct cvmx_rad_reg_cmd_buf_s         cn52xxp1;
+	struct cvmx_rad_reg_cmd_buf_s         cn56xx;
+	struct cvmx_rad_reg_cmd_buf_s         cn56xxp1;
+	struct cvmx_rad_reg_cmd_buf_s         cn63xx;
+	struct cvmx_rad_reg_cmd_buf_s         cn63xxp1;
+};
+typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
+
+/**
+ * cvmx_rad_reg_ctl
+ *
+ * Notes:
+ * MAX_READ is a throttle to control NCB usage.  Values >8 are illegal.
+ *
+ */
+union cvmx_rad_reg_ctl
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t max_read                     : 4;  /**< Maximum number of outstanding data read commands */
+	uint64_t store_le                     : 1;  /**< Force STORE0 byte write address to little endian */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse (lasts for 4 cycles) */
+#else
+	uint64_t reset                        : 1;
+	uint64_t store_le                     : 1;
+	uint64_t max_read                     : 4;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_rad_reg_ctl_s             cn52xx;
+	struct cvmx_rad_reg_ctl_s             cn52xxp1;
+	struct cvmx_rad_reg_ctl_s             cn56xx;
+	struct cvmx_rad_reg_ctl_s             cn56xxp1;
+	struct cvmx_rad_reg_ctl_s             cn63xx;
+	struct cvmx_rad_reg_ctl_s             cn63xxp1;
+};
+typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t;
+
+/**
+ * cvmx_rad_reg_debug0
+ */
+union cvmx_rad_reg_debug0
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_57_63               : 7;
+	uint64_t loop                         : 25; /**< Loop offset */
+	uint64_t reserved_22_31               : 10;
+	uint64_t iridx                        : 6;  /**< IWords read index */
+	uint64_t reserved_14_15               : 2;
+	uint64_t iwidx                        : 6;  /**< IWords write index */
+	uint64_t owordqv                      : 1;  /**< Valid for OWORDQ */
+	uint64_t owordpv                      : 1;  /**< Valid for OWORDP */
+	uint64_t commit                       : 1;  /**< Waiting for write commit */
+	uint64_t state                        : 5;  /**< Main state */
+#else
+	uint64_t state                        : 5;
+	uint64_t commit                       : 1;
+	uint64_t owordpv                      : 1;
+	uint64_t owordqv                      : 1;
+	uint64_t iwidx                        : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t iridx                        : 6;
+	uint64_t reserved_22_31               : 10;
+	uint64_t loop                         : 25;
+	uint64_t reserved_57_63               : 7;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug0_s          cn52xx;
+	struct cvmx_rad_reg_debug0_s          cn52xxp1;
+	struct cvmx_rad_reg_debug0_s          cn56xx;
+	struct cvmx_rad_reg_debug0_s          cn56xxp1;
+	struct cvmx_rad_reg_debug0_s          cn63xx;
+	struct cvmx_rad_reg_debug0_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t;
+
+/**
+ * cvmx_rad_reg_debug1
+ */
+union cvmx_rad_reg_debug1
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cword                        : 64; /**< CWord */
+#else
+	uint64_t cword                        : 64;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug1_s          cn52xx;
+	struct cvmx_rad_reg_debug1_s          cn52xxp1;
+	struct cvmx_rad_reg_debug1_s          cn56xx;
+	struct cvmx_rad_reg_debug1_s          cn56xxp1;
+	struct cvmx_rad_reg_debug1_s          cn63xx;
+	struct cvmx_rad_reg_debug1_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t;
+
+/**
+ * cvmx_rad_reg_debug10
+ */
+union cvmx_rad_reg_debug10
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug10_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t flags                        : 8;  /**< OCTL flags */
+	uint64_t size                         : 16; /**< OCTL size (bytes) */
+	uint64_t ptr                          : 40; /**< OCTL pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t flags                        : 8;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug10_s         cn52xx;
+	struct cvmx_rad_reg_debug10_s         cn52xxp1;
+	struct cvmx_rad_reg_debug10_s         cn56xx;
+	struct cvmx_rad_reg_debug10_s         cn56xxp1;
+	struct cvmx_rad_reg_debug10_s         cn63xx;
+	struct cvmx_rad_reg_debug10_s         cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t;
+
+/**
+ * cvmx_rad_reg_debug11
+ */
+union cvmx_rad_reg_debug11
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug11_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t q                            : 1;  /**< OCTL q flag */
+	uint64_t p                            : 1;  /**< OCTL p flag */
+	uint64_t wc                           : 1;  /**< OCTL write commit flag */
+	uint64_t eod                          : 1;  /**< OCTL eod flag */
+	uint64_t sod                          : 1;  /**< OCTL sod flag */
+	uint64_t index                        : 8;  /**< OCTL index */
+#else
+	uint64_t index                        : 8;
+	uint64_t sod                          : 1;
+	uint64_t eod                          : 1;
+	uint64_t wc                           : 1;
+	uint64_t p                            : 1;
+	uint64_t q                            : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug11_s         cn52xx;
+	struct cvmx_rad_reg_debug11_s         cn52xxp1;
+	struct cvmx_rad_reg_debug11_s         cn56xx;
+	struct cvmx_rad_reg_debug11_s         cn56xxp1;
+	struct cvmx_rad_reg_debug11_s         cn63xx;
+	struct cvmx_rad_reg_debug11_s         cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t;
+
+/**
+ * cvmx_rad_reg_debug12
+ */
+union cvmx_rad_reg_debug12
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug12_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t asserts                      : 15; /**< Various assertion checks */
+#else
+	uint64_t asserts                      : 15;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug12_s         cn52xx;
+	struct cvmx_rad_reg_debug12_s         cn52xxp1;
+	struct cvmx_rad_reg_debug12_s         cn56xx;
+	struct cvmx_rad_reg_debug12_s         cn56xxp1;
+	struct cvmx_rad_reg_debug12_s         cn63xx;
+	struct cvmx_rad_reg_debug12_s         cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t;
+
+/**
+ * cvmx_rad_reg_debug2
+ */
+union cvmx_rad_reg_debug2
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t owordp                       : 64; /**< OWordP */
+#else
+	uint64_t owordp                       : 64;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug2_s          cn52xx;
+	struct cvmx_rad_reg_debug2_s          cn52xxp1;
+	struct cvmx_rad_reg_debug2_s          cn56xx;
+	struct cvmx_rad_reg_debug2_s          cn56xxp1;
+	struct cvmx_rad_reg_debug2_s          cn63xx;
+	struct cvmx_rad_reg_debug2_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t;
+
+/**
+ * cvmx_rad_reg_debug3
+ */
+union cvmx_rad_reg_debug3
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t owordq                       : 64; /**< OWordQ */
+#else
+	uint64_t owordq                       : 64;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug3_s          cn52xx;
+	struct cvmx_rad_reg_debug3_s          cn52xxp1;
+	struct cvmx_rad_reg_debug3_s          cn56xx;
+	struct cvmx_rad_reg_debug3_s          cn56xxp1;
+	struct cvmx_rad_reg_debug3_s          cn63xx;
+	struct cvmx_rad_reg_debug3_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t;
+
+/**
+ * cvmx_rad_reg_debug4
+ */
+union cvmx_rad_reg_debug4
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rword                        : 64; /**< RWord */
+#else
+	uint64_t rword                        : 64;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug4_s          cn52xx;
+	struct cvmx_rad_reg_debug4_s          cn52xxp1;
+	struct cvmx_rad_reg_debug4_s          cn56xx;
+	struct cvmx_rad_reg_debug4_s          cn56xxp1;
+	struct cvmx_rad_reg_debug4_s          cn63xx;
+	struct cvmx_rad_reg_debug4_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t;
+
+/**
+ * cvmx_rad_reg_debug5
+ */
+union cvmx_rad_reg_debug5
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_53_63               : 11;
+	uint64_t niropc7                      : 3;  /**< NCBI ropc (stage7 grant) */
+	uint64_t nirque7                      : 2;  /**< NCBI rque (stage7 grant) */
+	uint64_t nirval7                      : 5;  /**< NCBI rval (stage7 grant) */
+	uint64_t niropc6                      : 3;  /**< NCBI ropc (stage6 arb) */
+	uint64_t nirque6                      : 2;  /**< NCBI rque (stage6 arb) */
+	uint64_t nirarb6                      : 1;  /**< NCBI rarb (stage6 arb) */
+	uint64_t nirval6                      : 5;  /**< NCBI rval (stage6 arb) */
+	uint64_t niridx1                      : 4;  /**< NCBI ridx1 */
+	uint64_t niwidx1                      : 4;  /**< NCBI widx1 */
+	uint64_t niridx0                      : 4;  /**< NCBI ridx0 */
+	uint64_t niwidx0                      : 4;  /**< NCBI widx0 */
+	uint64_t wccreds                      : 2;  /**< WC credits */
+	uint64_t fpacreds                     : 2;  /**< POW credits */
+	uint64_t reserved_10_11               : 2;
+	uint64_t powcreds                     : 2;  /**< POW credits */
+	uint64_t n1creds                      : 4;  /**< NCBI1 credits */
+	uint64_t n0creds                      : 4;  /**< NCBI0 credits */
+#else
+	uint64_t n0creds                      : 4;
+	uint64_t n1creds                      : 4;
+	uint64_t powcreds                     : 2;
+	uint64_t reserved_10_11               : 2;
+	uint64_t fpacreds                     : 2;
+	uint64_t wccreds                      : 2;
+	uint64_t niwidx0                      : 4;
+	uint64_t niridx0                      : 4;
+	uint64_t niwidx1                      : 4;
+	uint64_t niridx1                      : 4;
+	uint64_t nirval6                      : 5;
+	uint64_t nirarb6                      : 1;
+	uint64_t nirque6                      : 2;
+	uint64_t niropc6                      : 3;
+	uint64_t nirval7                      : 5;
+	uint64_t nirque7                      : 2;
+	uint64_t niropc7                      : 3;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug5_s          cn52xx;
+	struct cvmx_rad_reg_debug5_s          cn52xxp1;
+	struct cvmx_rad_reg_debug5_s          cn56xx;
+	struct cvmx_rad_reg_debug5_s          cn56xxp1;
+	struct cvmx_rad_reg_debug5_s          cn63xx;
+	struct cvmx_rad_reg_debug5_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t;
+
+/**
+ * cvmx_rad_reg_debug6
+ */
+union cvmx_rad_reg_debug6
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cnt                          : 8;  /**< CCTL count[7:0] (bytes) */
+	uint64_t size                         : 16; /**< CCTL size (bytes) */
+	uint64_t ptr                          : 40; /**< CCTL pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t cnt                          : 8;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug6_s          cn52xx;
+	struct cvmx_rad_reg_debug6_s          cn52xxp1;
+	struct cvmx_rad_reg_debug6_s          cn56xx;
+	struct cvmx_rad_reg_debug6_s          cn56xxp1;
+	struct cvmx_rad_reg_debug6_s          cn63xx;
+	struct cvmx_rad_reg_debug6_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t;
+
+/**
+ * cvmx_rad_reg_debug7
+ */
+union cvmx_rad_reg_debug7
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t cnt                          : 15; /**< CCTL count[22:8] (bytes) */
+#else
+	uint64_t cnt                          : 15;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug7_s          cn52xx;
+	struct cvmx_rad_reg_debug7_s          cn52xxp1;
+	struct cvmx_rad_reg_debug7_s          cn56xx;
+	struct cvmx_rad_reg_debug7_s          cn56xxp1;
+	struct cvmx_rad_reg_debug7_s          cn63xx;
+	struct cvmx_rad_reg_debug7_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t;
+
+/**
+ * cvmx_rad_reg_debug8
+ */
+union cvmx_rad_reg_debug8
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug8_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t flags                        : 8;  /**< ICTL flags */
+	uint64_t size                         : 16; /**< ICTL size (bytes) */
+	uint64_t ptr                          : 40; /**< ICTL pointer */
+#else
+	uint64_t ptr                          : 40;
+	uint64_t size                         : 16;
+	uint64_t flags                        : 8;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug8_s          cn52xx;
+	struct cvmx_rad_reg_debug8_s          cn52xxp1;
+	struct cvmx_rad_reg_debug8_s          cn56xx;
+	struct cvmx_rad_reg_debug8_s          cn56xxp1;
+	struct cvmx_rad_reg_debug8_s          cn63xx;
+	struct cvmx_rad_reg_debug8_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t;
+
+/**
+ * cvmx_rad_reg_debug9
+ */
+union cvmx_rad_reg_debug9
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_debug9_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t eod                          : 1;  /**< ICTL eod flag */
+	uint64_t ini                          : 1;  /**< ICTL init flag */
+	uint64_t q                            : 1;  /**< ICTL q enable */
+	uint64_t p                            : 1;  /**< ICTL p enable */
+	uint64_t mul                          : 8;  /**< ICTL multiplier */
+	uint64_t index                        : 8;  /**< ICTL index */
+#else
+	uint64_t index                        : 8;
+	uint64_t mul                          : 8;
+	uint64_t p                            : 1;
+	uint64_t q                            : 1;
+	uint64_t ini                          : 1;
+	uint64_t eod                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_rad_reg_debug9_s          cn52xx;
+	struct cvmx_rad_reg_debug9_s          cn52xxp1;
+	struct cvmx_rad_reg_debug9_s          cn56xx;
+	struct cvmx_rad_reg_debug9_s          cn56xxp1;
+	struct cvmx_rad_reg_debug9_s          cn63xx;
+	struct cvmx_rad_reg_debug9_s          cn63xxp1;
+};
+typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t;
+
+/**
+ * cvmx_rad_reg_error
+ */
+union cvmx_rad_reg_error
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_error_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
+#else
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_rad_reg_error_s           cn52xx;
+	struct cvmx_rad_reg_error_s           cn52xxp1;
+	struct cvmx_rad_reg_error_s           cn56xx;
+	struct cvmx_rad_reg_error_s           cn56xxp1;
+	struct cvmx_rad_reg_error_s           cn63xx;
+	struct cvmx_rad_reg_error_s           cn63xxp1;
+};
+typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
+
+/**
+ * cvmx_rad_reg_int_mask
+ *
+ * Notes:
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ *
+ */
+union cvmx_rad_reg_int_mask
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_int_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
+#else
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_rad_reg_int_mask_s        cn52xx;
+	struct cvmx_rad_reg_int_mask_s        cn52xxp1;
+	struct cvmx_rad_reg_int_mask_s        cn56xx;
+	struct cvmx_rad_reg_int_mask_s        cn56xxp1;
+	struct cvmx_rad_reg_int_mask_s        cn63xx;
+	struct cvmx_rad_reg_int_mask_s        cn63xxp1;
+};
+typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
+
+/**
+ * cvmx_rad_reg_polynomial
+ *
+ * Notes:
+ * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
+ *
+ */
+union cvmx_rad_reg_polynomial
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_polynomial_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t coeffs                       : 8;  /**< coefficients of GF(2^8) irreducible polynomial */
+#else
+	uint64_t coeffs                       : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_rad_reg_polynomial_s      cn52xx;
+	struct cvmx_rad_reg_polynomial_s      cn52xxp1;
+	struct cvmx_rad_reg_polynomial_s      cn56xx;
+	struct cvmx_rad_reg_polynomial_s      cn56xxp1;
+	struct cvmx_rad_reg_polynomial_s      cn63xx;
+	struct cvmx_rad_reg_polynomial_s      cn63xxp1;
+};
+typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
+
+/**
+ * cvmx_rad_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "RAD_MEM_".
+ * IDX[15:0] is the read index.  INC[15:0] is an increment that is added to IDX[15:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+union cvmx_rad_reg_read_idx
+{
+	uint64_t u64;
+	struct cvmx_rad_reg_read_idx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t inc                          : 16; /**< Increment to add to current index for next index */
+	uint64_t index                        : 16; /**< Index to use for next memory CSR read */
+#else
+	uint64_t index                        : 16;
+	uint64_t inc                          : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_rad_reg_read_idx_s        cn52xx;
+	struct cvmx_rad_reg_read_idx_s        cn52xxp1;
+	struct cvmx_rad_reg_read_idx_s        cn56xx;
+	struct cvmx_rad_reg_read_idx_s        cn56xxp1;
+	struct cvmx_rad_reg_read_idx_s        cn63xx;
+	struct cvmx_rad_reg_read_idx_s        cn63xxp1;
+};
+typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-raid.c b/sys/contrib/octeon-sdk/cvmx-raid.c
index 9867f8e..07dd194 100644
--- a/sys/contrib/octeon-sdk/cvmx-raid.c
+++ b/sys/contrib/octeon-sdk/cvmx-raid.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to RAID block. This is not available on all chips.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #include "executive-config.h"
 #include "cvmx-config.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-raid.h b/sys/contrib/octeon-sdk/cvmx-raid.h
index 88dde4f..48682e8 100644
--- a/sys/contrib/octeon-sdk/cvmx-raid.h
+++ b/sys/contrib/octeon-sdk/cvmx-raid.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to RAID block. This is not available on all chips.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_RAID_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-resources.config b/sys/contrib/octeon-sdk/cvmx-resources.config
deleted file mode 100644
index 3bd53f7..0000000
--- a/sys/contrib/octeon-sdk/cvmx-resources.config
+++ /dev/null
@@ -1,172 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-/*
- * File version info: $Id: cvmx-resources.config 42150 2009-04-10 21:43:27Z pkapoor $
- *
- */
-#ifndef __CVMX_RESOURCES_CONFIG__
-#define __CVMX_RESOURCES_CONFIG__
-
-
-#if (CVMX_HELPER_FIRST_MBUFF_SKIP > 256)
-#error CVMX_HELPER_FIRST_MBUFF_SKIP is greater than the maximum of 256
-#endif
-
-#if (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP > 256)
-#error CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is greater than the maximum of 256
-#endif
-
-
-/* Content below this point is only used by the cvmx-config tool, and is
-** not used by any C files as CAVIUM_COMPONENT_REQUIREMENT is never
-defined.
-*/
- #ifdef CAVIUM_COMPONENT_REQUIREMENT
-    /* Define the number of LLM ports (interfaces), can be 1 or 2 */
-    cvmxconfig
-    {
-    	#if CVMX_LLM_CONFIG_NUM_PORTS == 2
-            define CVMX_LLM_NUM_PORTS value = 2;
-	#else
-            define CVMX_LLM_NUM_PORTS value = 1;
-	#endif
-    }
-    /* Control the setting of Null pointer detection, default to enabled */
-    cvmxconfig {
-    	#ifdef CVMX_CONFIG_NULL_POINTER_PROTECT
-            define CVMX_NULL_POINTER_PROTECT value = CVMX_CONFIG_NULL_POINTER_PROTECT;
-	#else
-            define CVMX_NULL_POINTER_PROTECT value = 1;
-	#endif
-    }
-    /* Control Debug prints, default to enabled */
-    cvmxconfig {
-    	#ifdef CVMX_CONFIG_ENABLE_DEBUG_PRINTS
-            define CVMX_ENABLE_DEBUG_PRINTS value = CVMX_CONFIG_ENABLE_DEBUG_PRINTS;
-	#else
-            define CVMX_ENABLE_DEBUG_PRINTS value = 1;
-	#endif
-    }
-
-    /* Define CVMX_ENABLE_DFA_FUNCTIONS to allocate resources for the DFA functions */
-    #ifdef CVMX_ENABLE_DFA_FUNCTIONS
-        cvmxconfig
-        {
-        	fpa CVMX_FPA_DFA_POOL
-                    size        = 2
-                    protected   = 1
-                    description = "DFA command buffers";
-        	fau CVMX_FAU_DFA_STATE
-                    size        = 8
-                    count       = 1
-                    description = "FAU registers for the state of the DFA command queue";
-        }
-    #endif
-
-    /* Define CVMX_ENABLE_PKO_FUNCTIONS to allocate resources for the PKO functions */
-    #ifdef CVMX_ENABLE_PKO_FUNCTIONS
-        cvmxconfig
-        {
-		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0
-		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0
-		    description = "PKO queues per port for interface 0 (ports 0-15)";
-		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1
-		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1
-		    description = "PKO queues per port for interface 1 (ports 16-31)";
-                define CVMX_PKO_MAX_PORTS_INTERFACE0
-                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
-                    description = "Limit on the number of PKO ports enabled for interface 0";
-                define CVMX_PKO_MAX_PORTS_INTERFACE1
-                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
-                    description = "Limit on the number of PKO ports enabled for interface 1";
-		define CVMX_PKO_QUEUES_PER_PORT_PCI
-		    value       = 1
-		    description = "PKO queues per port for PCI (ports 32-35)";
-		define CVMX_PKO_QUEUES_PER_PORT_LOOP
-		    value       = 1
-		    description = "PKO queues per port for Loop devices (ports 36-39)";
-        	fpa CVMX_FPA_PACKET_POOL
-                    pool        = 0
-                    size        = 16
-                    priority    = 1
-                    protected   = 1
-                    description = "Packet buffers";
-        	fpa CVMX_FPA_OUTPUT_BUFFER_POOL
-                    size        = 8
-                    protected   = 1
-                    description = "PKO queue command buffers";
-        	scratch CVMX_SCR_SCRATCH
-                    size        = 8
-                    iobdma      = true
-                    permanent   = false
-                    description = "Generic scratch iobdma area";
-        }
-    #endif
-
-    /* Define CVMX_ENABLE_HELPER_FUNCTIONS to allocate resources for the helper functions */
-    #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
-        cvmxconfig
-        {
-        	fpa CVMX_FPA_WQE_POOL
-                    size        = 1
-                    priority    = 1
-                    protected   = 1
-                    description = "Work queue entrys";
-        }
-    #endif
-
-    /* Define CVMX_ENABLE_TIMER_FUNCTIONS to allocate resources for the timer functions */
-    #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
-        cvmxconfig
-        {
-        	fpa CVMX_FPA_TIMER_POOL
-                    size        = 8
-                    protected   = 1
-                    description = "TIM command buffers";
-        }
-    #endif
-
-#endif
-
-
-#endif  /* __CVMX_RESOURCES_CONFIG__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-rng.h b/sys/contrib/octeon-sdk/cvmx-rng.h
index a708881..8ef128b 100644
--- a/sys/contrib/octeon-sdk/cvmx-rng.h
+++ b/sys/contrib/octeon-sdk/cvmx-rng.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Function and structure definitions for random number generator hardware
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 
@@ -80,7 +82,7 @@ typedef union
 static inline void cvmx_rng_enable(void)
 {
     cvmx_rnm_ctl_status_t rnm_ctl_status;
-    rnm_ctl_status.u64 = 0;
+    rnm_ctl_status.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
     rnm_ctl_status.s.ent_en = 1;
     rnm_ctl_status.s.rng_en = 1;
     cvmx_write_csr(CVMX_RNM_CTL_STATUS, rnm_ctl_status.u64);
diff --git a/sys/contrib/octeon-sdk/cvmx-rnm-defs.h b/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
new file mode 100644
index 0000000..f9eefbb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
@@ -0,0 +1,290 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-rnm-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon rnm.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_RNM_TYPEDEFS_H__
+#define __CVMX_RNM_TYPEDEFS_H__
+
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC()
+static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180040000018ull);
+}
+#else
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC()
+static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180040000010ull);
+}
+#else
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC()
+static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180040000020ull);
+}
+#else
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
+#endif
+
+/**
+ * cvmx_rnm_bist_status
+ *
+ * RNM_BIST_STATUS = RNM's BIST Status Register
+ *
+ * The RNM's Memory Bist Status register.
+ */
+union cvmx_rnm_bist_status
+{
+	uint64_t u64;
+	struct cvmx_rnm_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t rrc                          : 1;  /**< Status of RRC block bist. */
+	uint64_t mem                          : 1;  /**< Status of MEM block bist. */
+#else
+	uint64_t mem                          : 1;
+	uint64_t rrc                          : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_rnm_bist_status_s         cn30xx;
+	struct cvmx_rnm_bist_status_s         cn31xx;
+	struct cvmx_rnm_bist_status_s         cn38xx;
+	struct cvmx_rnm_bist_status_s         cn38xxp2;
+	struct cvmx_rnm_bist_status_s         cn50xx;
+	struct cvmx_rnm_bist_status_s         cn52xx;
+	struct cvmx_rnm_bist_status_s         cn52xxp1;
+	struct cvmx_rnm_bist_status_s         cn56xx;
+	struct cvmx_rnm_bist_status_s         cn56xxp1;
+	struct cvmx_rnm_bist_status_s         cn58xx;
+	struct cvmx_rnm_bist_status_s         cn58xxp1;
+	struct cvmx_rnm_bist_status_s         cn63xx;
+	struct cvmx_rnm_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t;
+
+/**
+ * cvmx_rnm_ctl_status
+ *
+ * RNM_CTL_STATUS = RNM's Control/Status Register
+ *
+ * The RNM's interrupt enable register.
+ */
+union cvmx_rnm_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_rnm_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t eer_lck                      : 1;  /**< Encryption enable register locked */
+	uint64_t eer_val                      : 1;  /**< Dormant encryption key match */
+	uint64_t ent_sel                      : 4;  /**< ? */
+	uint64_t exp_ent                      : 1;  /**< Exported entropy enable for random number generator */
+	uint64_t rng_rst                      : 1;  /**< Reset RNG as core reset. */
+	uint64_t rnm_rst                      : 1;  /**< Reset the RNM as core reset except for register
+                                                         logic. */
+	uint64_t rng_en                       : 1;  /**< Enable the output of the RNG. */
+	uint64_t ent_en                       : 1;  /**< Entropy enable for random number generator. */
+#else
+	uint64_t ent_en                       : 1;
+	uint64_t rng_en                       : 1;
+	uint64_t rnm_rst                      : 1;
+	uint64_t rng_rst                      : 1;
+	uint64_t exp_ent                      : 1;
+	uint64_t ent_sel                      : 4;
+	uint64_t eer_val                      : 1;
+	uint64_t eer_lck                      : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_rnm_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t rng_rst                      : 1;  /**< Reset RNG as core reset. */
+	uint64_t rnm_rst                      : 1;  /**< Reset the RNM as core reset except for register
+                                                         logic. */
+	uint64_t rng_en                       : 1;  /**< Enable the output of the RNG. */
+	uint64_t ent_en                       : 1;  /**< Entropy enable for random number generator. */
+#else
+	uint64_t ent_en                       : 1;
+	uint64_t rng_en                       : 1;
+	uint64_t rnm_rst                      : 1;
+	uint64_t rng_rst                      : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} cn30xx;
+	struct cvmx_rnm_ctl_status_cn30xx     cn31xx;
+	struct cvmx_rnm_ctl_status_cn30xx     cn38xx;
+	struct cvmx_rnm_ctl_status_cn30xx     cn38xxp2;
+	struct cvmx_rnm_ctl_status_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t ent_sel                      : 4;  /**< ? */
+	uint64_t exp_ent                      : 1;  /**< Exported entropy enable for random number generator */
+	uint64_t rng_rst                      : 1;  /**< Reset RNG as core reset. */
+	uint64_t rnm_rst                      : 1;  /**< Reset the RNM as core reset except for register
+                                                         logic. */
+	uint64_t rng_en                       : 1;  /**< Enable the output of the RNG. */
+	uint64_t ent_en                       : 1;  /**< Entropy enable for random number generator. */
+#else
+	uint64_t ent_en                       : 1;
+	uint64_t rng_en                       : 1;
+	uint64_t rnm_rst                      : 1;
+	uint64_t rng_rst                      : 1;
+	uint64_t exp_ent                      : 1;
+	uint64_t ent_sel                      : 4;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} cn50xx;
+	struct cvmx_rnm_ctl_status_cn50xx     cn52xx;
+	struct cvmx_rnm_ctl_status_cn50xx     cn52xxp1;
+	struct cvmx_rnm_ctl_status_cn50xx     cn56xx;
+	struct cvmx_rnm_ctl_status_cn50xx     cn56xxp1;
+	struct cvmx_rnm_ctl_status_cn50xx     cn58xx;
+	struct cvmx_rnm_ctl_status_cn50xx     cn58xxp1;
+	struct cvmx_rnm_ctl_status_s          cn63xx;
+	struct cvmx_rnm_ctl_status_s          cn63xxp1;
+};
+typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t;
+
+/**
+ * cvmx_rnm_eer_dbg
+ *
+ * RNM_EER_DBG = RNM's Encryption enable debug register
+ *
+ * The RNM's Encryption enable debug register
+ */
+union cvmx_rnm_eer_dbg
+{
+	uint64_t u64;
+	struct cvmx_rnm_eer_dbg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dat                          : 64; /**< Dormant encryption debug info. */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_rnm_eer_dbg_s             cn63xx;
+	struct cvmx_rnm_eer_dbg_s             cn63xxp1;
+};
+typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t;
+
+/**
+ * cvmx_rnm_eer_key
+ *
+ * RNM_EER_KEY = RNM's Encryption enable register
+ *
+ * The RNM's Encryption enable register
+ */
+union cvmx_rnm_eer_key
+{
+	uint64_t u64;
+	struct cvmx_rnm_eer_key_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t key                          : 64; /**< Dormant encryption key.  If dormant crypto is fuse
+                                                         enabled, crypto can be enable by writing this
+                                                         register with the correct key. */
+#else
+	uint64_t key                          : 64;
+#endif
+	} s;
+	struct cvmx_rnm_eer_key_s             cn63xx;
+	struct cvmx_rnm_eer_key_s             cn63xxp1;
+};
+typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t;
+
+/**
+ * cvmx_rnm_serial_num
+ *
+ * RNM_SERIAL_NUM = RNM's fuse serial number register
+ *
+ * The RNM's fuse serial number register
+ *
+ * Notes:
+ * Added RNM_SERIAL_NUM in pass 2.0
+ *
+ */
+union cvmx_rnm_serial_num
+{
+	uint64_t u64;
+	struct cvmx_rnm_serial_num_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dat                          : 64; /**< Dormant encryption serial number */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_rnm_serial_num_s          cn63xx;
+};
+typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-rtc.h b/sys/contrib/octeon-sdk/cvmx-rtc.h
index 0d103b9..f35739d 100644
--- a/sys/contrib/octeon-sdk/cvmx-rtc.h
+++ b/sys/contrib/octeon-sdk/cvmx-rtc.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file provides support for real time clocks on some boards
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-rwlock.h b/sys/contrib/octeon-sdk/cvmx-rwlock.h
index 08576e4..e674510 100644
--- a/sys/contrib/octeon-sdk/cvmx-rwlock.h
+++ b/sys/contrib/octeon-sdk/cvmx-rwlock.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * This file provides reader/writer locks.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-scratch.h b/sys/contrib/octeon-sdk/cvmx-scratch.h
index 00fc5d2..fc5d845 100644
--- a/sys/contrib/octeon-sdk/cvmx-scratch.h
+++ b/sys/contrib/octeon-sdk/cvmx-scratch.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -48,7 +50,7 @@
  * Scratch memory is byte addressable - all addresses are byte addresses.
  *
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld
deleted file mode 100644
index 04105f0..0000000
--- a/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld
+++ /dev/null
@@ -1,279 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-/*
- * This was created from a template supplied by GNU binutils.
- * Copyright (C) 2005 Cavium Networks
- */
-
-/**
- * @file
- * This linker script for use in building simple executive application to run
- * under Linux in userspace. The important difference from a standard Linux
- * binary is the addition of the ".cvmx_shared" memory section. This script
- * adds two symbols __cvmx_shared_start and __cvmx_shared_end before and after
- * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
- * shared region across all application processes.
- *
- * The original template for this files was:
- * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmipn32.x
- */
-OUTPUT_FORMAT("elf32-ntradbigmips", "elf32-ntradbigmips",
-	      "elf32-ntradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(__start)
-SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
-  .interp         : { *(.interp) }
-  .MIPS.options : { *(.MIPS.options) }
-  .dynamic        : { *(.dynamic) }
-  .hash           : { *(.hash) }
-  .dynsym         : { *(.dynsym) }
-  .dynstr         : { *(.dynstr) }
-  .gnu.version    : { *(.gnu.version) }
-  .gnu.version_d  : { *(.gnu.version_d) }
-  .gnu.version_r  : { *(.gnu.version_r) }
-  .rel.init       : { *(.rel.init) }
-  .rela.init      : { *(.rela.init) }
-  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
-  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
-  .rel.fini       : { *(.rel.fini) }
-  .rela.fini      : { *(.rela.fini) }
-  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
-  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
-  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
-  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
-  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
-  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
-  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
-  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
-  .rel.ctors      : { *(.rel.ctors) }
-  .rela.ctors     : { *(.rela.ctors) }
-  .rel.dtors      : { *(.rel.dtors) }
-  .rela.dtors     : { *(.rela.dtors) }
-  .rel.got        : { *(.rel.got) }
-  .rela.got       : { *(.rela.got) }
-  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
-  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
-  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
-  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
-  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
-  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
-  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
-  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
-  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
-  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
-  .rel.plt        : { *(.rel.plt) }
-  .rela.plt       : { *(.rela.plt) }
-  .init           :
-  {
-    KEEP (*(.init))
-  } =0
-  .plt            : { *(.plt) }
-  .text           :
-  {
-    _ftext = . ;
-    *(.text .stub .text.* .gnu.linkonce.t.*)
-    /* .gnu.warning sections are handled specially by elf32.em.  */
-    *(.gnu.warning)
-    *(.mips16.fn.*) *(.mips16.call.*)
-  } =0
-  .fini           :
-  {
-    KEEP (*(.fini))
-  } =0
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
-  .rodata1        : { *(.rodata1) }
-  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
-  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
-  .eh_frame_hdr : { *(.eh_frame_hdr) }
-  /* Adjust the address for the data segment.  We want to adjust up to
-     the same address within the page on the next page up.  */
-  . = ALIGN (0x100000) - ((0x100000 - .) & (0x100000 - 1)); . = DATA_SEGMENT_ALIGN (0x100000, 0x1000);
-  /* Ensure the __preinit_array_start label is properly aligned.  We
-     could instead move the label definition inside the section, but
-     the linker would then create the section even if it turns out to
-     be empty, which isn't pretty.  */
-  . = ALIGN(32 / 8);
-  PROVIDE (__preinit_array_start = .);
-  .preinit_array     : { *(.preinit_array) }
-  PROVIDE (__preinit_array_end = .);
-  PROVIDE (__init_array_start = .);
-  .init_array     : { *(.init_array) }
-  PROVIDE (__init_array_end = .);
-  PROVIDE (__fini_array_start = .);
-  .fini_array     : { *(.fini_array) }
-  PROVIDE (__fini_array_end = .);
-  .data           :
-  {
-    _fdata = . ;
-    *(.data .data.* .gnu.linkonce.d.*)
-    SORT(CONSTRUCTORS)
-  }
-  .data1          : { *(.data1) }
-  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
-  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
-  .eh_frame       : { KEEP (*(.eh_frame)) }
-  .gcc_except_table   : { *(.gcc_except_table) }
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin*.o(.ctors))
-    /* We don't want to include the .ctor section from
-       from the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  }
-  .dtors          :
-  {
-    KEEP (*crtbegin*.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  }
-  .jcr            : { KEEP (*(.jcr)) }
-  _gp = ALIGN(16) + 0x7ff0;
-  .got            : { *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata          :
-  {
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-  .lit8           : { *(.lit8) }
-  .lit4           : { *(.lit4) }
-  .srdata         : { *(.srdata) }
-
-  . = ALIGN (0x10000);
-  __cvmx_shared_start = .;
-  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
-  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
-  . = ALIGN (0x10000);
-  __cvmx_shared_end = .;
-
-  _edata = .;
-  PROVIDE (edata = .);
-  __bss_start = .;
-  _fbss = .;
-  .sbss           :
-  {
-    PROVIDE (__sbss_start = .);
-    PROVIDE (___sbss_start = .);
-    *(.dynsbss)
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-    PROVIDE (__sbss_end = .);
-    PROVIDE (___sbss_end = .);
-  }
-  .bss            :
-  {
-   *(.dynbss)
-   *(.bss .bss.* .gnu.linkonce.b.*)
-   *(COMMON)
-   /* Align here to ensure that the .bss section occupies space up to
-      _end.  Align after .bss to ensure correct alignment even if the
-      .bss section disappears because there are no input sections.  */
-   . = ALIGN(32 / 8);
-  }
-  . = ALIGN(32 / 8);
-  . = ALIGN(32M);    /* RBF added alignment of data */
-  .cvmx_shared : { *(.cvmx_shared) }
-  _end = .;
-  PROVIDE (end = .);
-  . = DATA_SEGMENT_END (.);
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
-  .stabstr       0 : { *(.stabstr) }
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-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment       0 : { *(.comment) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
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-  /* DWARF 1.1 and DWARF 2 */
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-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
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-  /DISCARD/ : { *(.note.GNU-stack) }
-}
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld
deleted file mode 100644
index 67c12c6..0000000
--- a/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld
+++ /dev/null
@@ -1,277 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-/*
- * This was created from a template supplied by GNU binutils.
- * Copyright (C) 2004 Cavium Networks
- */
-
-/**
- * @file
- * This linker script for use in building simple executive application to run
- * under Linux in userspace. The important difference from a standard Linux
- * binary is the addition of the ".cvmx_shared" memory section. This script
- * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
- * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
- * shared region across all application processes.
- *
- * The original template for this files was:
- * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmip.x
- */
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
-	      "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(__start)
-SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
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-  .reginfo        : { *(.reginfo) }
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-  . = ALIGN(32 / 8);
-  PROVIDE (__preinit_array_start = .);
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-  PROVIDE (__preinit_array_end = .);
-  PROVIDE (__init_array_start = .);
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-    SORT(CONSTRUCTORS)
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-  .eh_frame       : { KEEP (*(.eh_frame)) }
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-  .jcr            : { KEEP (*(.jcr)) }
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-  .got            : { *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
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-   . = ALIGN(32 / 8);
-  }
-  . = ALIGN(32 / 8);
-  . = ALIGN(32M);    /* RBF added alignment of data */
-  .cvmx_shared : { *(.cvmx_shared) }
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-  .debug_loc      0 : { *(.debug_loc) }
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-  /* SGI/MIPS DWARF 2 extensions */
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-  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
-  /DISCARD/ : { *(.note.GNU-stack) }
-}
diff --git a/sys/contrib/octeon-sdk/cvmx-shared-linux.ld b/sys/contrib/octeon-sdk/cvmx-shared-linux.ld
deleted file mode 100644
index 54f4d82..0000000
--- a/sys/contrib/octeon-sdk/cvmx-shared-linux.ld
+++ /dev/null
@@ -1,278 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-
-
-/*
- * This was created from a template supplied by GNU binutils.
- * Copyright (C) 2004 Cavium Networks
- */
- 
-/**
- * @file
- * This linker script for use in building simple executive application to run
- * under Linux in userspace. The important difference from a standard Linux 
- * binary is the addition of the ".cvmx_shared" memory section. This script 
- * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
- * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
- * shared region across all application processes.
- *
- * The original template for this files was:
- * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf64btsmip.x
- */
-OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips",
-	      "elf64-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(__start)
-SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
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-  PROVIDE (__preinit_array_start = .);
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-  PROVIDE (__preinit_array_end = .);
-  PROVIDE (__init_array_start = .);
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-  PROVIDE (__fini_array_start = .);
-  .fini_array     : { *(.fini_array) }
-  PROVIDE (__fini_array_end = .);
-  .data           :
-  {
-    _fdata = . ;
-    *(.data .data.* .gnu.linkonce.d.*)
-    SORT(CONSTRUCTORS)
-  }
-  .data1          : { *(.data1) }
-  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
-  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
-  .eh_frame       : { KEEP (*(.eh_frame)) }
-  .gcc_except_table   : { *(.gcc_except_table) }
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin*.o(.ctors))
-    /* We don't want to include the .ctor section from
-       from the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  }
-  .dtors          :
-  {
-    KEEP (*crtbegin*.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  }
-  .jcr            : { KEEP (*(.jcr)) }
-  _gp = ALIGN(16) + 0x7ff0;
-  .got            : { *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata          :
-  {
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
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-  .lit4           : { *(.lit4) }
-  .srdata         : { *(.srdata) }
-  
-  . = ALIGN (0x10000); 
-  __cvmx_shared_start = .;
-  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
-  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
-  . = ALIGN (0x10000);
-  __cvmx_shared_end = .;
-  
-  _edata = .;
-  PROVIDE (edata = .);
-  __bss_start = .;
-  _fbss = .;
-  .sbss           :
-  {
-    PROVIDE (__sbss_start = .);
-    PROVIDE (___sbss_start = .);
-    *(.dynsbss)
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-    PROVIDE (__sbss_end = .);
-    PROVIDE (___sbss_end = .);
-  }
-  .bss            :
-  {
-   *(.dynbss)
-   *(.bss .bss.* .gnu.linkonce.b.*)
-   *(COMMON)
-   /* Align here to ensure that the .bss section occupies space up to
-      _end.  Align after .bss to ensure correct alignment even if the
-      .bss section disappears because there are no input sections.  */
-   . = ALIGN(64 / 8);
-  }
-  . = ALIGN(64 / 8);
-  . = ALIGN(32M);    /* RBF added alignment of data */
-  .cvmx_shared : { *(.cvmx_shared) }
-  _end = .;
-  PROVIDE (end = .);
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
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-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
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-  /* GNU DWARF 1 extensions */
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-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
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-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
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-  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
-  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
-  /DISCARD/ : { *(.note.GNU-stack) }
-}
diff --git a/sys/contrib/octeon-sdk/cvmx-shmem.c b/sys/contrib/octeon-sdk/cvmx-shmem.c
new file mode 100644
index 0000000..c289d13
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-shmem.c
@@ -0,0 +1,748 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+/**
+ * @file
+ *   cvmx-shmem supplies the cross application shared memory implementation
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-tlb.h"
+#include "cvmx-shmem.h"
+
+//#define DEBUG
+
+struct cvmx_shmem_smdr *__smdr = NULL;
+
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+static int __cvmx_shmem_devmemfd = 0;   /* fd for /dev/mem */
+#endif
+
+#define __CHECK_APP_SMDR  do { \
+                if (__smdr == NULL) { \
+                    cvmx_dprintf("cvmx_shmem: %s is not set up, Quit line %d \n", \
+                        CVMX_SHMEM_DSCPTR_NAME, __LINE__ ); \
+                    exit(-1); \
+                } \
+              }while(0)
+
+
+
+/**
+ * @INTERNAL
+ * Virtual sbrk, assigning virtual address in a global virtual address space.
+ *
+ * @param alignment   alignment requirement in bytes
+ * @param size        size in bytes
+ */
+static inline void *__cvmx_shmem_vsbrk_64(uint64_t alignment, uint64_t size)
+{
+    uint64_t nbase_64 = CAST64(__smdr->break64);
+    void *nbase = NULL;
+
+    /* Skip unaligned bytes */
+    if (nbase_64 & alignment)
+        nbase_64 += ~(nbase_64 & alignment) + 1;
+
+    if (nbase_64 + size  <  CVMX_SHMEM_VADDR64_END)
+    {
+        nbase = CASTPTR(void *, nbase_64);
+        __smdr->break64 = nbase + size;
+    }
+
+    return nbase;
+}
+
+/**
+ * @INTERNAL
+ * Initialize all SMDR entries, only need to be called once
+ *
+ * @param smdr pointer to the SMDR
+ */
+static inline void __smdr_new(struct cvmx_shmem_smdr *smdr) {
+
+    if (smdr != NULL)
+    {
+        int i;
+
+        cvmx_spinlock_init (&smdr->lock);
+        cvmx_spinlock_lock (&smdr->lock);
+
+        for ( i = 0; i < CVMX_SHMEM_NUM_DSCPTR; i++ )
+        {
+            smdr -> shmd[i].owner = CVMX_SHMEM_OWNER_NONE;
+            smdr -> shmd[i].is_named_block = 0;
+            smdr -> shmd[i].use_count = 0;
+            smdr -> shmd[i].name = NULL;
+            smdr -> shmd[i].vaddr = NULL;
+            smdr -> shmd[i].paddr = 0;
+            smdr -> shmd[i].size = 0;
+            smdr -> shmd[i].alignment = 0;
+        };
+
+        /* Init vaddr */
+        smdr->break64 = (void *)CVMX_SHMEM_VADDR64_START;
+        cvmx_spinlock_unlock (&smdr->lock);
+    }
+
+    /* Make sure the shmem descriptor region is created */
+    __CHECK_APP_SMDR;
+};
+
+
+
+/**
+ * @INTERNAL
+ * Initialize __smdr pointer, if SMDR exits already. If not, create a new
+ * one.  Once SMDR is created (as a bootmem named block), it is persistent.
+ */
+static inline struct cvmx_shmem_smdr *__smdr_init()
+{
+    const cvmx_bootmem_named_block_desc_t *smdr_nblk = NULL;
+    size_t smdr_size = sizeof(*__smdr);
+    char *smdr_name = CVMX_SHMEM_DSCPTR_NAME;
+
+    __smdr = (struct cvmx_shmem_smdr *) cvmx_bootmem_alloc_named(smdr_size, 0x10000, smdr_name);
+
+    if (__smdr)
+       __smdr_new (__smdr);
+    else
+    {
+        /* Check if SMDR exists already */
+        smdr_nblk = cvmx_bootmem_find_named_block(smdr_name);
+        if (smdr_nblk)
+        {
+            __smdr = (struct cvmx_shmem_smdr *)
+            (cvmx_phys_to_ptr(smdr_nblk->base_addr));
+
+            cvmx_spinlock_lock (&__smdr->lock);
+            if (smdr_nblk->size != smdr_size)
+            {
+                cvmx_dprintf("SMDR named block is created by another "
+                    "application with different size %lu, "
+                    "expecting %lu \n",
+                    (long unsigned int)smdr_nblk->size, (long unsigned int)smdr_size);
+                __smdr = NULL;
+            }
+            cvmx_spinlock_unlock (&__smdr->lock);
+        }
+    }
+
+   if (!__smdr)
+       cvmx_dprintf("cvmx_shmem: Failed to allocate or find SMDR from bootmem \n");
+
+   return __smdr;
+};
+
+
+/**
+ * @INTERNAL
+ * Generic Iterator function for all SMDR entries
+ *
+ * @param void(*f)(dscptr) the function to be invoked for every descriptor
+ * @param param
+ *
+ * @return the descriptor iterator stopped at.
+ */
+static struct cvmx_shmem_dscptr *__smdr_iterator(struct cvmx_shmem_dscptr *(*f)(struct cvmx_shmem_dscptr *dscptr, void *p), void *param )
+{
+    struct cvmx_shmem_dscptr *d, *dscptr = NULL;
+    int i;
+
+    __CHECK_APP_SMDR;
+
+    for (i = 0; i < CVMX_SHMEM_NUM_DSCPTR; i++)
+    {
+        d = &__smdr->shmd[i];
+        if ((dscptr = (*f)(d, param)) != NULL)
+            break;      /* stop iteration */
+    }
+
+   return dscptr;
+}
+
+
+/**
+ * @INTERNAL
+ * SMDR name match functor. to be used for iterator.
+ *
+ * @param dscptr  descriptor passed in by the iterator
+ * @param   name    string to match against
+ *
+ * @return !NULL   descriptor matched
+ *     NULL    not match
+ */
+static struct cvmx_shmem_dscptr *__cvmx_shmem_smdr_match_name(struct cvmx_shmem_dscptr *dscptr, void *name)
+{
+    char *name_to_match = (char *) name;
+    struct cvmx_shmem_dscptr *ret = NULL;
+
+    if (dscptr->owner == CVMX_SHMEM_OWNER_NONE)
+        return NULL;
+
+    if (strcmp(dscptr->name, name_to_match) == 0)
+        ret =  dscptr;
+
+    return ret;
+}
+
+/**
+ * @INTERNAL
+ * Find by name
+ *
+ * @param   name    string to match against
+ *
+ * @return !NULL    descriptor matched
+ *          NULL    not match
+ */
+static struct cvmx_shmem_dscptr *__cvmx_shmem_smdr_find_by_name(char *name)
+{
+    return __smdr_iterator( __cvmx_shmem_smdr_match_name, name);
+}
+
+/**
+ * @INTERNAL
+ * SMDR is free functor. to be used for iterator.
+ *
+ * @param dscptr  descriptor passed in by the iterator
+ * @param nouse
+ *
+ * @return !NULL  descriptor is free
+ *          NULL  descriptor is not free
+ */
+static struct cvmx_shmem_dscptr *__cvmx_shmem_smdr_is_free(struct cvmx_shmem_dscptr* dscptr, void *nouse)
+{
+    if (dscptr->owner == CVMX_SHMEM_OWNER_NONE)
+        return dscptr;
+    else
+        return NULL;
+}
+
+/**
+ * @INTERNAL
+ * Search SMDR to find the first free descriptor
+ *
+ * @return !NULL   free descriptor found
+ *     NULL    nothing found
+ */
+struct cvmx_shmem_dscptr *__cvmx_shmem_smdr_find_free_dscptr(void)
+{
+    return __smdr_iterator(__cvmx_shmem_smdr_is_free, NULL);
+}
+
+/**
+ * @INTERNAL
+ * free a descriptor
+ *
+ * @param dscptr  descriptor to be freed
+ */
+static void __cvmx_shmem_smdr_free(struct cvmx_shmem_dscptr *dscptr)
+{
+    dscptr->owner = CVMX_SHMEM_OWNER_NONE;
+}
+
+
+/**
+ * Per core shmem init function
+ *
+ * @return  cvmx_shmem_smdr*   pointer to __smdr
+ */
+struct cvmx_shmem_smdr *cvmx_shmem_init()
+{
+    return __smdr_init();
+}
+
+/**
+ * Open shared memory based on named block
+ *
+ * @return  dscptr descriptor of the opened named block
+ */
+struct cvmx_shmem_dscptr *cvmx_shmem_named_block_open(char *name, uint32_t size, int oflag)
+{
+    const cvmx_bootmem_named_block_desc_t *shmem_nblk = NULL;
+    struct cvmx_shmem_dscptr *dscptr = NULL;
+    int nblk_allocated = 0; /* Assume we don't need to allocate a new
+                               bootmem block */
+    void *vaddr = NULL;
+    const uint64_t size_4k = 4*1024, size_512mb = 512*1024*1024;
+
+    __CHECK_APP_SMDR;
+
+    /* Check size, Make sure it is minimal 4K, no bigger than 512MB */
+    if (size > size_512mb) {
+        cvmx_dprintf("Shared memory size can not be bigger than 512MB \n");
+        return NULL;
+    }
+    if (size < size_4k)
+        size = size_4k;
+
+    size = __upper_power_of_two(size);
+
+    cvmx_spinlock_lock(&__smdr->lock);
+
+    shmem_nblk = cvmx_bootmem_find_named_block(name);
+    if ((shmem_nblk == NULL) &&  (oflag & CVMX_SHMEM_O_CREAT))
+    {
+       void *p;
+       /* The named block does not exist, create it if caller specifies
+          the O_CREAT flag */
+        nblk_allocated = 1;
+        p = cvmx_bootmem_alloc_named(size, size, name);
+        if (p)
+            shmem_nblk = cvmx_bootmem_find_named_block(name);
+#ifdef DEBUG
+        cvmx_dprintf("cvmx-shmem-dbg:"
+             "creating a new block %s: blk %p, shmem_nblk %p \n",
+             name, p, shmem_nblk);
+#endif
+    }
+
+    if (shmem_nblk == NULL)
+        goto err;
+
+    /* We are now holding a valid named block */
+
+    dscptr = __cvmx_shmem_smdr_find_by_name(name);
+    if (dscptr)
+    {
+        if (nblk_allocated)
+        {
+            /* name conflict between bootmem name space and SMDR name space */
+            cvmx_dprintf("cvmx-shmem: SMDR descriptor name conflict, %s \n", name);
+            goto err;
+        }
+        /* Make sure size and alignment matches with existing descriptor */
+        if ((size != dscptr->size) ||  (size != dscptr -> alignment))
+            goto err;
+    }
+    else
+    {
+        /* Create a new descriptor */
+        dscptr = __cvmx_shmem_smdr_find_free_dscptr();
+        if (dscptr)
+            goto init;
+        else
+        {
+            cvmx_dprintf("cvmx-shmem: SMDR out of descriptors \n");
+            goto err;
+        }
+    }
+
+    /* Maintain the reference count */
+    if (dscptr != NULL)
+        dscptr->use_count += 1;
+
+    cvmx_spinlock_unlock(&__smdr->lock);
+    return dscptr;
+
+err:
+#ifdef DEBUG
+    cvmx_dprintf("cvmx-shmem-dbg: named block open failed \n");
+#endif
+
+    if (dscptr)
+        __cvmx_shmem_smdr_free(dscptr);
+    if (shmem_nblk && nblk_allocated)
+        cvmx_bootmem_free_named(name);
+    cvmx_spinlock_unlock(&__smdr->lock);
+
+    return NULL;
+
+init:
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx-shmem-dbg: init SMDR descriptor %p \n", dscptr);
+#endif
+
+    /* Assign vaddr for single address space mapping */
+    vaddr = __cvmx_shmem_vsbrk_64(size, size);
+    if (vaddr == NULL) {
+        /* Failed to allocate virtual address, clean up */
+        goto err;
+    }
+
+#ifdef DEBUG
+    cvmx_dprintf("cmvx-shmem-dbg: allocated vaddr %p \n", vaddr);
+#endif
+    dscptr->vaddr = vaddr;
+
+    /* Store descriptor information,  name, alignment,size... */
+    dscptr->owner = cvmx_get_core_num();
+    dscptr->is_named_block = 1;
+    dscptr->use_count = 1;
+    dscptr->name =shmem_nblk->name ;
+    dscptr->paddr = shmem_nblk->base_addr;
+    dscptr->size = size;
+    dscptr->alignment = size;
+
+    /* Store permission bits */
+    if (oflag & CVMX_SHMEM_O_WRONLY)
+        dscptr->p_wronly = 1;
+    if (oflag & CVMX_SHMEM_O_RDWR)
+        dscptr->p_rdwr = 1;
+
+   cvmx_spinlock_unlock(&__smdr->lock);
+   return dscptr;
+}
+
+/**
+ * @INTERNAL
+ *
+ *  For stand along SE application only.
+ *
+ *  Add TLB mapping to map the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param pflag   protection flags
+ *
+ *  @return vaddr  the virtual address mapped for the shared memory
+ */
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+void *__cvmx_shmem_map_standalone(struct cvmx_shmem_dscptr *dscptr, int pflag)
+{
+    int free_index;
+
+    /* Find a free tlb entry */
+    free_index = cvmx_tlb_allocate_runtime_entry();
+
+    if (free_index < 0 )
+    {
+        cvmx_dprintf("cvmx-shmem: shmem_map failed, out TLB entries \n");
+        return NULL;
+    }
+
+#ifdef DEBUG
+    cvmx_dprintf("cmvx-shmem-dbg:"
+         "shmem_map TLB %d: vaddr %p paddr %lx, size %x \n",
+         free_index, dscptr->vaddr, dscptr->paddr, dscptr->size );
+#endif
+
+    cvmx_tlb_write_runtime_entry(free_index, CAST64(dscptr->vaddr),
+            dscptr->paddr, dscptr->size,
+            TLB_DIRTY | TLB_VALID | TLB_GLOBAL);
+
+    return dscptr -> vaddr;
+}
+#endif
+
+/**
+ * @INTERNAL
+ *
+ *  For Linux user application only
+ *
+ *  Add mmap the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param pflag   protection flags
+ *
+ *  @return vaddr  the virtual address mapped for the shared memory
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+static inline void *__cvmx_shmem_map_linux(struct cvmx_shmem_dscptr *dscptr, int pflag)
+{
+    void *vaddr = NULL;
+
+    if(__cvmx_shmem_devmemfd == 0)
+    {
+        __cvmx_shmem_devmemfd = open("/dev/mem", O_RDWR);
+        if (__cvmx_shmem_devmemfd < 0)
+        {
+            cvmx_dprintf("Failed to open /dev/mem\n");
+            exit(-1);
+        }
+    }
+
+    vaddr = mmap(dscptr->vaddr, dscptr->size, PROT_READ|PROT_WRITE,
+                 MAP_SHARED, __cvmx_shmem_devmemfd, 0);
+
+    /* Make sure the mmap maps to the same virtual address specified in
+     * descriptor
+     */
+    if ((vaddr!=NULL) && (vaddr != dscptr->vaddr))
+    {
+        munmap(vaddr, dscptr->size);
+        vaddr = NULL;
+    }
+    return vaddr;
+}
+#endif
+
+/**
+ *  cvmx_shmem API
+ *
+ *  Add mapping for the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param pflag   protection flags
+ *
+ *  @return vaddr  the virtual address mapped for the shared memory
+ */
+void *cvmx_shmem_map(struct cvmx_shmem_dscptr *dscptr, int pflag)
+{
+    void *vaddr = NULL;
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+    vaddr = __cvmx_shmem_map_linux(dscptr, pflag);
+#else
+    vaddr = __cvmx_shmem_map_standalone(dscptr, pflag);
+#endif
+    return vaddr;
+}
+
+
+/**
+ * @INTERNAL
+ *
+ *  For Linux user application only
+ *
+ *  ummap the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+static inline void __cvmx_shmem_unmap_linux(struct cvmx_shmem_dscptr* dscptr)
+{
+    if (__cvmx_shmem_devmemfd && dscptr)
+        munmap(dscptr->vaddr, dscptr->size);
+}
+#endif
+
+
+/**
+ * @INTERNAL
+ *
+ *  For stand along SE application only.
+ *
+ *  ummap the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *
+ */
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+static inline void
+__cvmx_shmem_unmap_standalone(struct cvmx_shmem_dscptr *dscptr)
+{
+    int index;
+
+    index = cvmx_tlb_lookup(CAST64(dscptr->vaddr));
+
+#ifdef DEBUG
+    cvmx_dprintf("cmvx-shmem-dbg:"
+             "shmem_unmap TLB %d \n", index);
+#endif
+    cvmx_tlb_free_runtime_entry(index);
+}
+#endif
+
+/**
+ *  ummap the shared memory
+ *
+ *  @param dscptr  shared memory descriptor
+ *
+ */
+void cvmx_shmem_unmap(struct cvmx_shmem_dscptr *dscptr)
+{
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+    __cvmx_shmem_unmap_linux(dscptr);
+#else
+    __cvmx_shmem_unmap_standalone(dscptr);
+#endif
+}
+
+/**
+ * @INTERNAL
+ *
+ *  Common implementation of closing a descriptor.
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param remove  1:  remove the descriptor and named block if this
+ *                  this is the last user of the descriptor
+ *             0:  do not remove
+ *  @return  0:   Success
+ *          !0:   Failed
+ *
+ */
+static inline int __cvmx_shmem_close_dscptr(struct cvmx_shmem_dscptr *dscptr, int remove)
+{
+    cvmx_spinlock_lock(&dscptr->lock);
+
+    if (dscptr->use_count >0)
+        dscptr->use_count-= 1;
+
+    if ((dscptr->use_count == 0) && remove)
+    {
+        /* Free this descriptor */
+        __cvmx_shmem_smdr_free(dscptr);
+
+        /* Free named block if this is the last user, and the block
+           is created by the application */
+        if (dscptr->is_named_block)
+        {
+#ifdef DEBUG
+            cvmx_dprintf("cvmx-shmem-dbg: remove named block %s \n", dscptr->name);
+#endif
+            cvmx_bootmem_phy_named_block_free(dscptr->name, 0);
+        }
+    }
+    cvmx_spinlock_unlock(&dscptr->lock);
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ *
+ *  For stand along SE application only.
+ *
+ *  close a descriptor.
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param remove  1:  remove the descriptor and named block if this
+ *                  this is the last user of the descriptor
+ *             0:  do not remove
+ *  @return  0:   Success
+ *          !0:   Failed
+ *
+ */
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+static inline int __cvmx_shmem_close_standalone(struct cvmx_shmem_dscptr *dscptr, int remove)
+{
+    return __cvmx_shmem_close_dscptr(dscptr, remove);
+}
+#endif
+
+/**
+ * @INTERNAL
+ *
+ *  For Linux user application only.
+ *
+ *  close a descriptor.
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param remove  1:  remove the descriptor and named block if this
+ *                  this is the last user of the descriptor
+ *             0:  do not remove
+ *  @return  0:   Success
+ *          !0:   Failed
+ *
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+int __cvmx_shmem_close_linux(struct cvmx_shmem_dscptr *dscptr, int remove)
+{
+    int ret;
+    ret = __cvmx_shmem_close_dscptr(dscptr, remove);
+
+    if (ret && __cvmx_shmem_devmemfd)
+    {
+        close(__cvmx_shmem_devmemfd);
+         __cvmx_shmem_devmemfd=0;
+    }
+
+    return ret;
+
+}
+#endif
+
+/**
+ *
+ *  close a descriptor.
+ *
+ *  @param dscptr  shared memory descriptor
+ *  @param remove  1:  remove the descriptor and named block if this
+ *                  this is the last user of the descriptor
+ *             0:  do not remove
+ *  @return  0:   Success
+ *          !0:   Failed
+ *
+ */
+int cvmx_shmem_close(struct cvmx_shmem_dscptr *dscptr, int remove)
+{
+    int ret;
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+    ret = __cvmx_shmem_close_linux(dscptr, remove);
+#else
+    ret = __cvmx_shmem_close_standalone(dscptr, remove);
+#endif
+    return ret;
+}
+
+#ifdef DEBUG
+/**
+ * @INTERNAL
+ *  SMDR non-free descriptor dump functor. to be used for iterator.
+ *
+ * @param dscptr  descriptor passed in by the iterator
+ *
+ * @return NULL  always
+ */
+static struct cvmx_shmem_dscptr *__cvmx_shmem_smdr_display_dscptr(struct cvmx_shmem_dscptr *dscptr, void *nouse)
+{
+    if ((dscptr != NULL ) && (dscptr -> owner != CVMX_SHMEM_OWNER_NONE))
+    {
+        cvmx_dprintf("  %s: phy: %lx, size %d, alignment %lx, virt %p use_count %d\n",
+            dscptr->name, dscptr-> paddr,
+            dscptr->size, dscptr-> alignment,
+            dscptr->vaddr, dscptr->use_count);
+    }
+
+    return NULL;
+}
+#endif
+
+/**
+ *  SMDR descriptor show
+ *
+ *  list all non-free descriptors
+ */
+void cvmx_shmem_show(void)
+{
+    __CHECK_APP_SMDR;
+
+#ifdef DEBUG
+    cvmx_dprintf("SMDR descriptor list: \n");
+    cvmx_spinlock_lock(&__smdr->lock);
+    __smdr_iterator(__cvmx_shmem_smdr_display_dscptr, NULL);
+    cvmx_spinlock_unlock(&__smdr->lock);
+    cvmx_dprintf("\n\n");
+#endif
+}
diff --git a/sys/contrib/octeon-sdk/cvmx-shmem.h b/sys/contrib/octeon-sdk/cvmx-shmem.h
new file mode 100644
index 0000000..f99cad5
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-shmem.h
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+#ifndef __CVMX_SHMEM_H__
+#define __CVMX_SHMEM_H__
+
+/**
+ * @file
+ *
+ * cvmx-shmem provides APIs for setting up shared memory between Linux
+ * and simple executive applications.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+#include "cvmx-spinlock.h"
+
+#define CVMX_SHMEM_NUM_DSCPTR       8
+#define CVMX_SHMEM_DSCPTR_NAME         "SMDR"
+
+#define CVMX_SHMEM_O_RDONLY         0x00
+#define CVMX_SHMEM_O_WRONLY         0x01
+#define CVMX_SHMEM_O_RDWR           0x02
+#define CVMX_SHMEM_O_CREAT          0x04
+
+#define CVMX_SHMEM_MAP_PROT_READ    0x01
+#define CVMX_SHMEM_MAP_PROT_WRITE   0x02
+#define CVMX_SHMEM_MAP_EXEC         0x04
+
+#define CVMX_SHMEM_OWNER_NONE       0xff
+
+#define CVMX_SHMEM_VADDR64_START    0x500000000ULL
+#define CVMX_SHMEM_VADDR64_END      0x600000000ULL
+
+#define CVMX_SHMEM_VADDR32_START    0x10000000
+#define CVMX_SHMEM_VADDR32_END      0x18000000
+
+struct cvmx_shmem_dscptr {
+    cvmx_spinlock_t lock;
+    uint64_t owner:           8;
+    uint64_t is_named_block:  1;
+    uint64_t p_wronly:        1;
+    uint64_t p_rdwr:          1;
+    int32_t use_count;	      /* must use atomic operation to maintain count */
+    const char *name;
+    void *vaddr;
+    uint64_t paddr;
+    uint32_t size;
+    uint64_t alignment;
+};
+
+struct cvmx_shmem_smdr {
+    cvmx_spinlock_t lock;
+    struct cvmx_shmem_dscptr  shmd[CVMX_SHMEM_NUM_DSCPTR];
+    void *break64;    /* Keep track of unused 64 bit virtual address space */
+};
+
+
+struct cvmx_shmem_smdr *cvmx_shmem_init(void);
+
+/**
+ *  Create a piece memory out of named block
+ *
+ *  @param name Named block name
+ *  @param flag create flag
+ */
+struct cvmx_shmem_dscptr *cvmx_shmem_named_block_open(char *name, uint32_t size, int oflag);
+
+/**
+ *  Update TLB mapping based on the descriptor
+ */
+void*  cvmx_shmem_map(struct cvmx_shmem_dscptr *desc, int pflag);
+
+/**
+ *  Remove the TLB mapping created for the descriptor
+ */
+void   cvmx_shmem_unmap(struct cvmx_shmem_dscptr *desc);
+
+
+/**
+ *  Close the share memory,
+ *
+ *  @Param remove  Remove the named block if it is created by the application
+ */
+int cvmx_shmem_close(struct cvmx_shmem_dscptr *desc, int remove);
+
+/**
+ * Debug function, dump all SMDR descriptors
+ */
+void cvmx_shmem_show(void);
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sim-magic.h b/sys/contrib/octeon-sdk/cvmx-sim-magic.h
new file mode 100644
index 0000000..5145b64
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-sim-magic.h
@@ -0,0 +1,198 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * This is file defines ASM primitives for sim magic functions.
+
+ * <hr>$Revision: 49448 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_SIM_MAGIC_H__
+#define __CVMX_SIM_MAGIC_H__
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+/* Note, the following Magic function are only useful in the simulator
+ * environment. Typical simple executive application should not use
+ * these functions. Their access functions are defined and implemented in
+ * the newlib
+ *  SIM_MAGIC_PUTS
+ *  SIM_MAGIC_WRITE
+ *  SIM_MAGIC_READ
+ *  SIM_MAGIC_OPEN
+ *  SIM_MAGIC_CLOSE
+ *  SIM_MAGIC_STAT
+ *  SIM_MAGIC_FSTAT
+ *  SIM_MAGIC_LSEEK
+ *  SIM_MAGIC_ALLOC_MEM
+ */
+
+/* Assembler macros for accessing simulator magic functions */
+#define OCTEON_SIM_MAGIC_TRAP_ADDRESS 0x8000000feffe0000ull
+
+/* Reg t9 (r25) specifies the actual magic function*/
+#define SIM_MAGIC_PUTS        0x05
+#define SIM_MAGIC_SIMPRINTF   0x06
+#define SIM_MAGIC_WRITE       0x07
+#define SIM_MAGIC_READ        0x08
+#define SIM_MAGIC_OPEN        0x09
+#define SIM_MAGIC_CLOSE       0x0A
+#define SIM_MAGIC_STAT        0x0B
+#define SIM_MAGIC_FSTAT       0x0C
+#define SIM_MAGIC_LSEEK       0x0D
+#define SIM_MAGIC_ALLOC_MEM   0x20
+#define SIM_MAGIC_GET_CPUFREQ 0x31      /* SDK 1.9 release and after */
+#define SIM_MAGIC_GET_MEMFREQ 0x32      /* SDK 1.9 release and after */
+#define SIM_MAGIC_GET_IOFREQ  0x33      /* SDK 2.0 release and after, only set in Octeon2 */
+
+/**
+ * @INTERNAL
+ * sim_magci implementation function with return code.
+ *
+ * @param func_no   SIM magic function to invoke
+ *
+ * @return Result of the SIM magic function
+ */
+static inline int __cvmx_sim_magic_return(unsigned long long func_no)
+{
+    register unsigned long long  magic_addr asm ("$15");
+    register unsigned long long  magic_func asm ("$25");  /* t9 */
+    int ret;
+
+    magic_addr = OCTEON_SIM_MAGIC_TRAP_ADDRESS;
+    magic_func = func_no;
+    asm volatile (
+        "dadd $24, $31, $0 \n"
+        "jalr  $15 \n"
+        "dadd $31, $24, $0 \n"
+        "move %0, $2"
+        : "=r" (ret)
+        : "r" (magic_addr), "r" (magic_func)
+	: "$2", "$24" );
+
+
+    return ret;
+}
+
+/**
+ * @INTERNAL
+ * sim_magci implementation function without return code.
+ *
+ * @param func_no   SIM magic function to invoke
+ */
+static inline void __cvmx_sim_magic_no_return(unsigned long long func_no)
+{
+    register unsigned long long  magic_addr asm ("$15");
+    register unsigned long long  magic_func asm ("$25");  /* t9 */
+
+    magic_addr = OCTEON_SIM_MAGIC_TRAP_ADDRESS;
+    magic_func = func_no;
+    asm volatile (
+        "dadd $24, $31, $0 \n"
+        "jalr  $15 \n"
+        "dadd $31, $24, $0 \n"
+        :
+        : "r" (magic_addr), "r" (magic_func)
+	: "$24" );
+
+}
+
+/**
+ * @INTERNAL
+ * SIM magic printf function, only support up to 8 parameters
+ *
+ * @param format
+ */
+static inline void __cvmx_sim_magic_simprintf(const char *format, ...)
+{
+    CVMX_SYNC;
+
+    __cvmx_sim_magic_no_return( SIM_MAGIC_SIMPRINTF);
+}
+
+/**
+ * Retrive cpu core clock frequency from the simulator
+ *
+ * @return simulating core frequency
+ */
+static inline int cvmx_sim_magic_get_cpufreq(void)
+{
+    CVMX_SYNC;
+
+    return  __cvmx_sim_magic_return(SIM_MAGIC_GET_CPUFREQ);
+}
+
+/**
+ * Retrive DDR clock frequency from the simulator
+ *
+ * @return simulating DDR frequency
+ */
+static inline int cvmx_sim_magic_get_memfreq(void)
+{
+    CVMX_SYNC;
+
+    return __cvmx_sim_magic_return(SIM_MAGIC_GET_MEMFREQ);
+}
+
+/**
+ * Retrive io core clock frequency from the simulator
+ *
+ * @return simulating core frequency
+ */
+static inline int cvmx_sim_magic_get_iofreq(void)
+{
+    CVMX_SYNC;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+       return  __cvmx_sim_magic_return(SIM_MAGIC_GET_IOFREQ);
+    else
+       return 0;
+}
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* __CVMX_SIM_MAGIC_H__ */
diff --git a/sys/contrib/octeon-sdk/cvmx-sli-defs.h b/sys/contrib/octeon-sdk/cvmx-sli-defs.h
new file mode 100644
index 0000000..6a1518e
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-sli-defs.h
@@ -0,0 +1,4229 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-sli-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon sli.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SLI_TYPEDEFS_H__
+#define __CVMX_SLI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n");
+	return 0x0000000000000580ull;
+}
+#else
+#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000050ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n");
+	return 0x0000000000000570ull;
+}
+#else
+#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n");
+	return 0x00000000000005F0ull;
+}
+#else
+#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n");
+	return 0x0000000000000310ull;
+}
+#else
+#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n");
+	return 0x0000000000000300ull;
+}
+#else
+#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000400ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000003E0ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000420ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC()
+static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n");
+	return 0x0000000000003CD0ull;
+}
+#else
+#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000340ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC()
+static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n");
+	return 0x0000000000000330ull;
+}
+#else
+#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
+	return 0x0000000000000600ull;
+}
+#else
+#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
+	return 0x0000000000000610ull;
+}
+#else
+#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n");
+	return 0x0000000000003D70ull;
+}
+#else
+#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
+static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n");
+	return 0x0000000000003E00ull;
+}
+#else
+#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n");
+	return 0x00000000000002F0ull;
+}
+#else
+#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
+		cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+	return 0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12;
+}
+#else
+#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n");
+	return 0x0000000000003C50ull;
+}
+#else
+#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n");
+	return 0x0000000000003C60ull;
+}
+#else
+#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n");
+	return 0x0000000000003C70ull;
+}
+#else
+#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n");
+	return 0x0000000000003C80ull;
+}
+#else
+#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n");
+	return 0x0000000000003C10ull;
+}
+#else
+#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n");
+	return 0x0000000000003C20ull;
+}
+#else
+#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n");
+	return 0x0000000000003C30ull;
+}
+#else
+#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n");
+	return 0x0000000000003C40ull;
+}
+#else
+#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n");
+	return 0x0000000000003CA0ull;
+}
+#else
+#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n");
+	return 0x0000000000003CF0ull;
+}
+#else
+#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n");
+	return 0x0000000000003D00ull;
+}
+#else
+#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n");
+	return 0x0000000000003D10ull;
+}
+#else
+#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n");
+	return 0x0000000000003D20ull;
+}
+#else
+#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n");
+	return 0x0000000000003D30ull;
+}
+#else
+#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n");
+	return 0x0000000000003D40ull;
+}
+#else
+#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n");
+	return 0x0000000000003D50ull;
+}
+#else
+#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n");
+	return 0x0000000000003D60ull;
+}
+#else
+#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n");
+	return 0x0000000000003C90ull;
+}
+#else
+#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n");
+	return 0x0000000000003CB0ull;
+}
+#else
+#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+	return 0x0000000000000650ull;
+}
+#else
+#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+	return 0x0000000000000660ull;
+}
+#else
+#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+	return 0x0000000000000670ull;
+}
+#else
+#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002C00ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003000ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000000C00ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001400ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001800ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000001C00ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n");
+	return 0x0000000000001130ull;
+}
+#else
+#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
+	return 0x0000000000001150ull;
+}
+#else
+#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC()
+static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n");
+	return 0x0000000000001220ull;
+}
+#else
+#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
+	return 0x00000000000010B0ull;
+}
+#else
+#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
+	return 0x00000000000010A0ull;
+}
+#else
+#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
+	return 0x0000000000001090ull;
+}
+#else
+#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n");
+	return 0x0000000000001080ull;
+}
+#else
+#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
+	return 0x0000000000001170ull;
+}
+#else
+#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n");
+	return 0x0000000000001000ull;
+}
+#else
+#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+	return 0x00000000000011A0ull;
+}
+#else
+#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n");
+	return 0x0000000000001020ull;
+}
+#else
+#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n");
+	return 0x0000000000001120ull;
+}
+#else
+#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n");
+	return 0x0000000000001210ull;
+}
+#else
+#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
+		cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000002000ull + ((offset) & 31) * 16;
+}
+#else
+#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+	return 0x0000000000001200ull;
+}
+#else
+#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
+	return 0x00000000000011B0ull;
+}
+#else
+#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n");
+	return 0x0000000000001070ull;
+}
+#else
+#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
+	return 0x0000000000001180ull;
+}
+#else
+#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n");
+	return 0x00000000000010D0ull;
+}
+#else
+#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n");
+	return 0x0000000000001010ull;
+}
+#else
+#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n");
+	return 0x00000000000010E0ull;
+}
+#else
+#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n");
+	return 0x00000000000011F0ull;
+}
+#else
+#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n");
+	return 0x0000000000001050ull;
+}
+#else
+#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n");
+	return 0x0000000000001040ull;
+}
+#else
+#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n");
+	return 0x0000000000001030ull;
+}
+#else
+#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n");
+	return 0x0000000000001140ull;
+}
+#else
+#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
+	return 0x0000000000001160ull;
+}
+#else
+#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
+	return 0x0000000000003D80ull + ((offset) & 1) * 16;
+}
+#else
+#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 1) * 16)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n");
+	return 0x00000000000003C0ull;
+}
+#else
+#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
+static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n");
+	return 0x00000000000003D0ull;
+}
+#else
+#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
+static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n");
+	return 0x0000000000000620ull;
+}
+#else
+#define CVMX_SLI_STATE1 (0x0000000000000620ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
+static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n");
+	return 0x0000000000000630ull;
+}
+#else
+#define CVMX_SLI_STATE2 (0x0000000000000630ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
+static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n");
+	return 0x0000000000000640ull;
+}
+#else
+#define CVMX_SLI_STATE3 (0x0000000000000640ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n");
+	return 0x00000000000002E0ull;
+}
+#else
+#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n");
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n");
+	return 0x0000000000000040ull;
+}
+#else
+#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n");
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n");
+	return 0x0000000000000020ull;
+}
+#else
+#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n");
+	return 0x0000000000000030ull;
+}
+#else
+#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
+#endif
+
+/**
+ * cvmx_sli_bist_status
+ *
+ * SLI_BIST_STATUS = SLI's BIST Status Register
+ *
+ * Results from BIST runs of SLI's memories.
+ */
+union cvmx_sli_bist_status
+{
+	uint64_t u64;
+	struct cvmx_sli_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
+	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
+	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
+	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
+	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
+	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
+	uint64_t reserved_19_24               : 6;
+	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
+	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
+	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
+	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
+	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
+	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
+	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
+	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
+	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
+	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
+	uint64_t reserved_6_8                 : 3;
+	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
+	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
+	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
+	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
+	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
+	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
+#else
+	uint64_t ncb_cmd                      : 1;
+	uint64_t msi                          : 1;
+	uint64_t dsi0_0                       : 1;
+	uint64_t dsi0_1                       : 1;
+	uint64_t dsi1_0                       : 1;
+	uint64_t dsi1_1                       : 1;
+	uint64_t reserved_6_8                 : 3;
+	uint64_t p2n1_p1                      : 1;
+	uint64_t p2n1_p0                      : 1;
+	uint64_t p2n1_n                       : 1;
+	uint64_t p2n1_c1                      : 1;
+	uint64_t p2n1_c0                      : 1;
+	uint64_t p2n0_p1                      : 1;
+	uint64_t p2n0_p0                      : 1;
+	uint64_t p2n0_n                       : 1;
+	uint64_t p2n0_c1                      : 1;
+	uint64_t p2n0_c0                      : 1;
+	uint64_t reserved_19_24               : 6;
+	uint64_t cpl_p1                       : 1;
+	uint64_t cpl_p0                       : 1;
+	uint64_t n2p1_o                       : 1;
+	uint64_t n2p1_c                       : 1;
+	uint64_t n2p0_o                       : 1;
+	uint64_t n2p0_c                       : 1;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} s;
+	struct cvmx_sli_bist_status_s         cn63xx;
+	struct cvmx_sli_bist_status_s         cn63xxp1;
+};
+typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
+
+/**
+ * cvmx_sli_ctl_port#
+ *
+ * SLI_CTL_PORTX = SLI's Control Port X
+ *
+ * Contains control for access for Port0
+ */
+union cvmx_sli_ctl_portx
+{
+	uint64_t u64;
+	struct cvmx_sli_ctl_portx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
+	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
+	uint64_t intb                         : 1;  /**< When '0' Intb wire asserted. Before mapping. */
+	uint64_t inta                         : 1;  /**< When '0' Inta wire asserted. Before mapping. */
+	uint64_t dis_port                     : 1;  /**< When set the output to the MAC is disabled. This
+                                                         occurs when the MAC reset line transitions from
+                                                         de-asserted to asserted. Writing a '1' to this
+                                                         location will clear this condition when the MAC is
+                                                         no longer in reset and the output to the MAC is at
+                                                         the begining of a transfer. */
+	uint64_t waitl_com                    : 1;  /**< When set '1' casues the SLI to wait for a commit
+                                                         from the L2C before sending additional completions
+                                                         to the L2C from a MAC.
+                                                         Set this for more conservative behavior. Clear
+                                                         this for more aggressive, higher-performance
+                                                         behavior */
+	uint64_t intd_map                     : 2;  /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intc_map                     : 2;  /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t intb_map                     : 2;  /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t inta_map                     : 2;  /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+	uint64_t ctlp_ro                      : 1;  /**< Relaxed ordering enable for Completion TLPS. */
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ptlp_ro                      : 1;  /**< Relaxed ordering enable for Posted TLPS. */
+	uint64_t reserved_1_4                 : 4;
+	uint64_t wait_com                     : 1;  /**< When set '1' casues the SLI to wait for a commit
+                                                         from the L2C before sending additional stores to
+                                                         the L2C from a MAC.
+                                                         The SLI will request a commit on the last store
+                                                         if more than one STORE operation is required on
+                                                         the NCB.
+                                                         Most applications will not notice a difference, so
+                                                         should not set this bit. Setting the bit is more
+                                                         conservative on ordering, lower performance */
+#else
+	uint64_t wait_com                     : 1;
+	uint64_t reserved_1_4                 : 4;
+	uint64_t ptlp_ro                      : 1;
+	uint64_t reserved_6_6                 : 1;
+	uint64_t ctlp_ro                      : 1;
+	uint64_t inta_map                     : 2;
+	uint64_t intb_map                     : 2;
+	uint64_t intc_map                     : 2;
+	uint64_t intd_map                     : 2;
+	uint64_t waitl_com                    : 1;
+	uint64_t dis_port                     : 1;
+	uint64_t inta                         : 1;
+	uint64_t intb                         : 1;
+	uint64_t intc                         : 1;
+	uint64_t intd                         : 1;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} s;
+	struct cvmx_sli_ctl_portx_s           cn63xx;
+	struct cvmx_sli_ctl_portx_s           cn63xxp1;
+};
+typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
+
+/**
+ * cvmx_sli_ctl_status
+ *
+ * SLI_CTL_STATUS = SLI Control Status Register
+ *
+ * Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space.
+ * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space)
+ * that requires the value of this register to be updated.
+ */
+union cvmx_sli_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_sli_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t p1_ntags                     : 6;  /**< Number of tags available for MAC Port1.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t p0_ntags                     : 6;  /**< Number of tags available for MAC Port0.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+	uint64_t chip_rev                     : 8;  /**< The chip revision. */
+#else
+	uint64_t chip_rev                     : 8;
+	uint64_t p0_ntags                     : 6;
+	uint64_t p1_ntags                     : 6;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_sli_ctl_status_s          cn63xx;
+	struct cvmx_sli_ctl_status_s          cn63xxp1;
+};
+typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
+
+/**
+ * cvmx_sli_data_out_cnt
+ *
+ * SLI_DATA_OUT_CNT = SLI DATA OUT COUNT
+ *
+ * The EXEC data out fifo-count and the data unload counter.
+ */
+union cvmx_sli_data_out_cnt
+{
+	uint64_t u64;
+	struct cvmx_sli_data_out_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t p1_ucnt                      : 16; /**< MAC Port1 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+	uint64_t p1_fcnt                      : 6;  /**< MAC Port1 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the MAC port presently
+                                                         buffered in the FIFO. */
+	uint64_t p0_ucnt                      : 16; /**< MAC Port0 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+	uint64_t p0_fcnt                      : 6;  /**< MAC Port0 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the MAC port presently
+                                                         buffered in the FIFO. */
+#else
+	uint64_t p0_fcnt                      : 6;
+	uint64_t p0_ucnt                      : 16;
+	uint64_t p1_fcnt                      : 6;
+	uint64_t p1_ucnt                      : 16;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_sli_data_out_cnt_s        cn63xx;
+	struct cvmx_sli_data_out_cnt_s        cn63xxp1;
+};
+typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
+
+/**
+ * cvmx_sli_dbg_data
+ *
+ * SLI_DBG_DATA = SLI Debug Data Register
+ *
+ * Value returned on the debug-data lines from the RSLs
+ */
+union cvmx_sli_dbg_data
+{
+	uint64_t u64;
+	struct cvmx_sli_dbg_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+	uint64_t data                         : 17; /**< Value on the debug data lines. */
+#else
+	uint64_t data                         : 17;
+	uint64_t dsel_ext                     : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_sli_dbg_data_s            cn63xx;
+	struct cvmx_sli_dbg_data_s            cn63xxp1;
+};
+typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
+
+/**
+ * cvmx_sli_dbg_select
+ *
+ * SLI_DBG_SELECT = Debug Select Register
+ *
+ * Contains the debug select value last written to the RSLs.
+ */
+union cvmx_sli_dbg_select
+{
+	uint64_t u64;
+	struct cvmx_sli_dbg_select_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t adbg_sel                     : 1;  /**< When set '1' the SLI_DBG_DATA[DATA] will only be
+                                                         loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'.
+                                                         When the debug data comes from an Async-RSL bit
+                                                         16 is used to tell that the data present is valid. */
+	uint64_t dbg_sel                      : 32; /**< When this register is written the RML will write
+                                                         all "F"s to the previous RTL to disable it from
+                                                         sending Debug-Data. The RML will then send a write
+                                                         to the new RSL with the supplied Debug-Select
+                                                         value. Because it takes time for the new Debug
+                                                         Select value to take effect and the requested
+                                                         Debug-Data to return, time is needed to the new
+                                                         Debug-Data to arrive.  The inititator of the Debug
+                                                         Select should issue a read to a CSR before reading
+                                                         the Debug Data (this read could also be to the
+                                                         SLI_DBG_DATA but the returned value for the first
+                                                         read will return NS data. */
+#else
+	uint64_t dbg_sel                      : 32;
+	uint64_t adbg_sel                     : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_sli_dbg_select_s          cn63xx;
+	struct cvmx_sli_dbg_select_s          cn63xxp1;
+};
+typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
+
+/**
+ * cvmx_sli_dma#_cnt
+ *
+ * SLI_DMAx_CNT = SLI DMA Count
+ *
+ * The DMA Count value.
+ */
+union cvmx_sli_dmax_cnt
+{
+	uint64_t u64;
+	struct cvmx_sli_dmax_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< The DMA counter.
+                                                         Writing this field will cause the written value
+                                                         to be subtracted from DMA. HW will optionally
+                                                         increment this field after it completes an
+                                                         OUTBOUND or EXTERNAL-ONLY DMA instruction. These
+                                                         increments may cause interrupts. Refer to
+                                                         SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_dmax_cnt_s            cn63xx;
+	struct cvmx_sli_dmax_cnt_s            cn63xxp1;
+};
+typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
+
+/**
+ * cvmx_sli_dma#_int_level
+ *
+ * SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level
+ *
+ * Thresholds for DMA count and timer interrupts.
+ */
+union cvmx_sli_dmax_int_level
+{
+	uint64_t u64;
+	struct cvmx_sli_dmax_int_level_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t time                         : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
+                                                         this value, SLI_INT_SUM[DTIME<x>] is set.
+                                                         The SLI_DMAx_TIM[TIM] timer increments every SLI
+                                                         clock whenever SLI_DMAx_CNT[CNT]!=0, and is
+                                                         cleared when SLI_INT_SUM[DTIME<x>] is written with
+                                                         one. */
+	uint64_t cnt                          : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value,
+                                                         SLI_INT_SUM[DCNT<x>] is set. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t time                         : 32;
+#endif
+	} s;
+	struct cvmx_sli_dmax_int_level_s      cn63xx;
+	struct cvmx_sli_dmax_int_level_s      cn63xxp1;
+};
+typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
+
+/**
+ * cvmx_sli_dma#_tim
+ *
+ * SLI_DMAx_TIM = SLI DMA Timer
+ *
+ * The DMA Timer value.
+ */
+union cvmx_sli_dmax_tim
+{
+	uint64_t u64;
+	struct cvmx_sli_dmax_tim_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t tim                          : 32; /**< The DMA timer value.
+                                                         The timer will increment when SLI_DMAx_CNT[CNT]!=0
+                                                         and will clear when SLI_DMAx_CNT[CNT]==0 */
+#else
+	uint64_t tim                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_dmax_tim_s            cn63xx;
+	struct cvmx_sli_dmax_tim_s            cn63xxp1;
+};
+typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
+
+/**
+ * cvmx_sli_int_enb_ciu
+ *
+ * SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register
+ *
+ * Used to enable the various interrupting conditions of SLI
+ */
+union cvmx_sli_int_enb_ciu
+{
+	uint64_t u64;
+	struct cvmx_sli_int_enb_ciu_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_18_31               : 14;
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL.
+                                                         THIS SHOULD NEVER BE SET */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t reserved_18_31               : 14;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_sli_int_enb_ciu_s         cn63xx;
+	struct cvmx_sli_int_enb_ciu_s         cn63xxp1;
+};
+typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
+
+/**
+ * cvmx_sli_int_enb_port#
+ *
+ * SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port
+ *
+ * Used to allow the generation of interrupts (MSI/INTA) to the PORT X
+ *
+ * Notes:
+ * This CSR is not used when the corresponding MAC is sRIO.
+ *
+ */
+union cvmx_sli_int_enb_portx
+{
+	uint64_t u64;
+	struct cvmx_sli_int_enb_portx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
+	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
+	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
+	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
+	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
+	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
+	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
+	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
+	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
+	uint64_t reserved_20_31               : 12;
+	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE-Port1 for MSI/inta.
+                                                         The valuse of this bit has NO effect on PCIE Port0.
+                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
+	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE-Port0 for MSI/inta.
+                                                         The valus of this bit has NO effect on PCIE Port1.
+                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
+	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
+	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta.
+                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
+	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t reserved_20_31               : 12;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_sli_int_enb_portx_s       cn63xx;
+	struct cvmx_sli_int_enb_portx_s       cn63xxp1;
+};
+typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
+
+/**
+ * cvmx_sli_int_sum
+ *
+ * SLI_INT_SUM = SLI Interrupt Summary Register
+ *
+ * Set when an interrupt condition occurs, write '1' to clear.
+ */
+union cvmx_sli_int_sum
+{
+	uint64_t u64;
+	struct cvmx_sli_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_61_63               : 3;
+	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
+                                                         range of the Packet-CSR, but for an unused
+                                                         address. */
+	uint64_t reserved_58_59               : 2;
+	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
+                                                         this bit is set. */
+	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
+                                                         this bit is set. */
+	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
+                                                         See SLI_PKT_IN_BP */
+	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
+	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
+	uint64_t reserved_38_47               : 10;
+	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
+                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
+                                                         clock.
+                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
+                                                         SLI_DMAx_INT_LEVEL[TIME].
+                                                         DTIME[x] is normally cleared by clearing
+                                                         SLI_DMAx_CNT[CNT] (which also clears
+                                                         SLI_DMAx_TIM[TIM]). */
+	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
+                                                         SLI_DMAx_INT_LEVEL[CNT].
+                                                         DCNT[x] is normally cleared by decreasing
+                                                         SLI_DMAx_CNT[CNT]. */
+	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
+                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
+	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
+                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
+	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
+                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
+	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
+                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
+                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
+	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 1. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
+                                                         from MAC 0. This occurs when the window registers
+                                                         are disabeld and a window register access occurs. */
+	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
+                                                         This occurs when the BAR 0 address space is
+                                                         disabeled. */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in SLI_PKT_TIME_INT. */
+	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in SLI_PKT_CNT_INT. */
+	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
+	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+	uint64_t reserved_1_1                 : 1;
+	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
+                                                         within 0xffff core clocks. */
+#else
+	uint64_t rml_to                       : 1;
+	uint64_t reserved_1_1                 : 1;
+	uint64_t bar0_to                      : 1;
+	uint64_t iob2big                      : 1;
+	uint64_t pcnt                         : 1;
+	uint64_t ptime                        : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t m0_up_b0                     : 1;
+	uint64_t m0_up_wi                     : 1;
+	uint64_t m0_un_b0                     : 1;
+	uint64_t m0_un_wi                     : 1;
+	uint64_t m1_up_b0                     : 1;
+	uint64_t m1_up_wi                     : 1;
+	uint64_t m1_un_b0                     : 1;
+	uint64_t m1_un_wi                     : 1;
+	uint64_t mio_int0                     : 1;
+	uint64_t mio_int1                     : 1;
+	uint64_t mac0_int                     : 1;
+	uint64_t mac1_int                     : 1;
+	uint64_t reserved_20_31               : 12;
+	uint64_t dmafi                        : 2;
+	uint64_t dcnt                         : 2;
+	uint64_t dtime                        : 2;
+	uint64_t reserved_38_47               : 10;
+	uint64_t pidbof                       : 1;
+	uint64_t psldbof                      : 1;
+	uint64_t pout_err                     : 1;
+	uint64_t pin_bp                       : 1;
+	uint64_t pgl_err                      : 1;
+	uint64_t pdi_err                      : 1;
+	uint64_t pop_err                      : 1;
+	uint64_t pins_err                     : 1;
+	uint64_t sprt0_err                    : 1;
+	uint64_t sprt1_err                    : 1;
+	uint64_t reserved_58_59               : 2;
+	uint64_t ill_pad                      : 1;
+	uint64_t reserved_61_63               : 3;
+#endif
+	} s;
+	struct cvmx_sli_int_sum_s             cn63xx;
+	struct cvmx_sli_int_sum_s             cn63xxp1;
+};
+typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;
+
+/**
+ * cvmx_sli_last_win_rdata0
+ *
+ * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data Port0
+ *
+ * The data from the last initiated window read.
+ */
+union cvmx_sli_last_win_rdata0
+{
+	uint64_t u64;
+	struct cvmx_sli_last_win_rdata0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_last_win_rdata0_s     cn63xx;
+	struct cvmx_sli_last_win_rdata0_s     cn63xxp1;
+};
+typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;
+
+/**
+ * cvmx_sli_last_win_rdata1
+ *
+ * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data Port1
+ *
+ * The data from the last initiated window read.
+ */
+union cvmx_sli_last_win_rdata1
+{
+	uint64_t u64;
+	struct cvmx_sli_last_win_rdata1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Last window read data. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_last_win_rdata1_s     cn63xx;
+	struct cvmx_sli_last_win_rdata1_s     cn63xxp1;
+};
+typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
+
+/**
+ * cvmx_sli_mac_credit_cnt
+ *
+ * SLI_MAC_CREDIT_CNT = SLI MAC Credit Count
+ *
+ * Contains the number of credits for the MAC port FIFOs used by the SLI. This value needs to be set BEFORE S2M traffic
+ * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
+ * in this register.
+ */
+union cvmx_sli_mac_credit_cnt
+{
+	uint64_t u64;
+	struct cvmx_sli_mac_credit_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t p1_c_d                       : 1;  /**< When set does not allow writing of P1_CCNT. */
+	uint64_t p1_n_d                       : 1;  /**< When set does not allow writing of P1_NCNT. */
+	uint64_t p1_p_d                       : 1;  /**< When set does not allow writing of P1_PCNT. */
+	uint64_t p0_c_d                       : 1;  /**< When set does not allow writing of P0_CCNT. */
+	uint64_t p0_n_d                       : 1;  /**< When set does not allow writing of P0_NCNT. */
+	uint64_t p0_p_d                       : 1;  /**< When set does not allow writing of P0_PCNT. */
+	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p1_ncnt                      : 8;  /**< Port1 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p1_pcnt                      : 8;  /**< Port1 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ccnt                      : 8;  /**< Port0 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ncnt                      : 8;  /**< Port0 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p0_pcnt                      : 8;  /**< Port0 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+#else
+	uint64_t p0_pcnt                      : 8;
+	uint64_t p0_ncnt                      : 8;
+	uint64_t p0_ccnt                      : 8;
+	uint64_t p1_pcnt                      : 8;
+	uint64_t p1_ncnt                      : 8;
+	uint64_t p1_ccnt                      : 8;
+	uint64_t p0_p_d                       : 1;
+	uint64_t p0_n_d                       : 1;
+	uint64_t p0_c_d                       : 1;
+	uint64_t p1_p_d                       : 1;
+	uint64_t p1_n_d                       : 1;
+	uint64_t p1_c_d                       : 1;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_sli_mac_credit_cnt_s      cn63xx;
+	struct cvmx_sli_mac_credit_cnt_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p1_ncnt                      : 8;  /**< Port1 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p1_pcnt                      : 8;  /**< Port1 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ccnt                      : 8;  /**< Port0 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+	uint64_t p0_ncnt                      : 8;  /**< Port0 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+	uint64_t p0_pcnt                      : 8;  /**< Port0 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+#else
+	uint64_t p0_pcnt                      : 8;
+	uint64_t p0_ncnt                      : 8;
+	uint64_t p0_ccnt                      : 8;
+	uint64_t p1_pcnt                      : 8;
+	uint64_t p1_ncnt                      : 8;
+	uint64_t p1_ccnt                      : 8;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
+
+/**
+ * cvmx_sli_mac_number
+ *
+ * 0x13DA0 - 0x13DF0 reserved for ports 2 - 7
+ *
+ *                  SLI_MAC_NUMBER = SLI MAC Number
+ *
+ * When read from a MAC port it returns the MAC's port number.
+ * register.
+ */
+union cvmx_sli_mac_number
+{
+	uint64_t u64;
+	struct cvmx_sli_mac_number_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t num                          : 8;  /**< The mac number. */
+#else
+	uint64_t num                          : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sli_mac_number_s          cn63xx;
+};
+typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
+
+/**
+ * cvmx_sli_mem_access_ctl
+ *
+ * SLI_MEM_ACCESS_CTL = SLI's Memory Access Control
+ *
+ * Contains control for access to the MAC address space.
+ */
+union cvmx_sli_mem_access_ctl
+{
+	uint64_t u64;
+	struct cvmx_sli_mem_access_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t max_word                     : 4;  /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the MAC. Legal
+                                                         values are 1 to 16, where a '0' is treated as 16. */
+	uint64_t timer                        : 10; /**< When the SLI starts a PP to MAC write it waits
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+	uint64_t timer                        : 10;
+	uint64_t max_word                     : 4;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_sli_mem_access_ctl_s      cn63xx;
+	struct cvmx_sli_mem_access_ctl_s      cn63xxp1;
+};
+typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
+
+/**
+ * cvmx_sli_mem_access_subid#
+ *
+ * // *
+ * // * 8070 - 80C0 saved for ports 2 through 7
+ * // *
+ * // *
+ * // * 0x80d0 free
+ * // *
+ *
+ *                   SLI_MEM_ACCESS_SUBIDX = SLI Memory Access SubidX Register
+ *
+ *  Contains address index and control bits for access to memory from Core PPs.
+ */
+union cvmx_sli_mem_access_subidx
+{
+	uint64_t u64;
+	struct cvmx_sli_mem_access_subidx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_43_63               : 21;
+	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
+                                                         Returns to the EXEC a zero for all read data.
+                                                         This must be zero for sRIO ports. */
+	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
+                                                         this subid are sent to. Must be <= 1, as there are
+                                                         only two ports present. */
+	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
+	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space writes. */
+	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute
+                                                         For sRIO:
+                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
+                                                           entry */
+	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
+                                                         For PCIe:
+                                                         - ADDRTYPE<0> is the relaxed-order attribute
+                                                         - ADDRTYPE<1> is the no-snoop attribute
+                                                         For sRIO:
+                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
+                                                           entry */
+	uint64_t ba                           : 30; /**< Address Bits <63:34> for reads/writes that use
+                                                         this subid. */
+#else
+	uint64_t ba                           : 30;
+	uint64_t rtype                        : 2;
+	uint64_t wtype                        : 2;
+	uint64_t esw                          : 2;
+	uint64_t esr                          : 2;
+	uint64_t nmerge                       : 1;
+	uint64_t port                         : 3;
+	uint64_t zero                         : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_sli_mem_access_subidx_s   cn63xx;
+	struct cvmx_sli_mem_access_subidx_s   cn63xxp1;
+};
+typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
+
+/**
+ * cvmx_sli_msi_enb0
+ *
+ * SLI_MSI_ENB0 = SLI MSI Enable0
+ *
+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.
+ */
+union cvmx_sli_msi_enb0
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_enb0_s            cn63xx;
+	struct cvmx_sli_msi_enb0_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
+
+/**
+ * cvmx_sli_msi_enb1
+ *
+ * SLI_MSI_ENB1 = SLI MSI Enable1
+ *
+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.
+ */
+union cvmx_sli_msi_enb1
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_enb1_s            cn63xx;
+	struct cvmx_sli_msi_enb1_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
+
+/**
+ * cvmx_sli_msi_enb2
+ *
+ * SLI_MSI_ENB2 = SLI MSI Enable2
+ *
+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.
+ */
+union cvmx_sli_msi_enb2
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_enb2_s            cn63xx;
+	struct cvmx_sli_msi_enb2_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
+
+/**
+ * cvmx_sli_msi_enb3
+ *
+ * SLI_MSI_ENB3 = SLI MSI Enable3
+ *
+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.
+ */
+union cvmx_sli_msi_enb3
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */
+#else
+	uint64_t enb                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_enb3_s            cn63xx;
+	struct cvmx_sli_msi_enb3_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
+
+/**
+ * cvmx_sli_msi_rcv0
+ *
+ * SLI_MSI_RCV0 = SLI MSI Receive0
+ *
+ * Contains bits [63:0] of the 256 bits of MSI interrupts.
+ */
+union cvmx_sli_msi_rcv0
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_rcv0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_rcv0_s            cn63xx;
+	struct cvmx_sli_msi_rcv0_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
+
+/**
+ * cvmx_sli_msi_rcv1
+ *
+ * SLI_MSI_RCV1 = SLI MSI Receive1
+ *
+ * Contains bits [127:64] of the 256 bits of MSI interrupts.
+ */
+union cvmx_sli_msi_rcv1
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_rcv1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_rcv1_s            cn63xx;
+	struct cvmx_sli_msi_rcv1_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
+
+/**
+ * cvmx_sli_msi_rcv2
+ *
+ * SLI_MSI_RCV2 = SLI MSI Receive2
+ *
+ * Contains bits [191:128] of the 256 bits of MSI interrupts.
+ */
+union cvmx_sli_msi_rcv2
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_rcv2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_rcv2_s            cn63xx;
+	struct cvmx_sli_msi_rcv2_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
+
+/**
+ * cvmx_sli_msi_rcv3
+ *
+ * SLI_MSI_RCV3 = SLI MSI Receive3
+ *
+ * Contains bits [255:192] of the 256 bits of MSI interrupts.
+ */
+union cvmx_sli_msi_rcv3
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_rcv3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t intr                         : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
+#else
+	uint64_t intr                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_rcv3_s            cn63xx;
+	struct cvmx_sli_msi_rcv3_s            cn63xxp1;
+};
+typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
+
+/**
+ * cvmx_sli_msi_rd_map
+ *
+ * SLI_MSI_RD_MAP = SLI MSI Read MAP
+ *
+ * Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
+ */
+union cvmx_sli_msi_rd_map
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_rd_map_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t rd_int                       : 8;  /**< The value of the map at the location PREVIOUSLY
+                                                         written to the MSI_INT field of this register. */
+	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
+                                                         SLI_PCIE_MSI_RCV register is written. */
+#else
+	uint64_t msi_int                      : 8;
+	uint64_t rd_int                       : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_sli_msi_rd_map_s          cn63xx;
+	struct cvmx_sli_msi_rd_map_s          cn63xxp1;
+};
+typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
+
+/**
+ * cvmx_sli_msi_w1c_enb0
+ *
+ * SLI_MSI_W1C_ENB0 = SLI MSI Write 1 To Clear Enable0
+ *
+ * Used to clear bits in SLI_MSI_ENB0.
+ */
+union cvmx_sli_msi_w1c_enb0
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1c_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in SLI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1c_enb0_s        cn63xx;
+	struct cvmx_sli_msi_w1c_enb0_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
+
+/**
+ * cvmx_sli_msi_w1c_enb1
+ *
+ * SLI_MSI_W1C_ENB1 = SLI MSI Write 1 To Clear Enable1
+ *
+ * Used to clear bits in SLI_MSI_ENB1.
+ */
+union cvmx_sli_msi_w1c_enb1
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1c_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in SLI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1c_enb1_s        cn63xx;
+	struct cvmx_sli_msi_w1c_enb1_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
+
+/**
+ * cvmx_sli_msi_w1c_enb2
+ *
+ * SLI_MSI_W1C_ENB2 = SLI MSI Write 1 To Clear Enable2
+ *
+ * Used to clear bits in SLI_MSI_ENB2.
+ */
+union cvmx_sli_msi_w1c_enb2
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1c_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in SLI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1c_enb2_s        cn63xx;
+	struct cvmx_sli_msi_w1c_enb2_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
+
+/**
+ * cvmx_sli_msi_w1c_enb3
+ *
+ * SLI_MSI_W1C_ENB3 = SLI MSI Write 1 To Clear Enable3
+ *
+ * Used to clear bits in SLI_MSI_ENB3.
+ */
+union cvmx_sli_msi_w1c_enb3
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1c_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in SLI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t clr                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1c_enb3_s        cn63xx;
+	struct cvmx_sli_msi_w1c_enb3_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
+
+/**
+ * cvmx_sli_msi_w1s_enb0
+ *
+ * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable0
+ *
+ * Used to set bits in SLI_MSI_ENB0.
+ */
+union cvmx_sli_msi_w1s_enb0
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1s_enb0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in SLI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1s_enb0_s        cn63xx;
+	struct cvmx_sli_msi_w1s_enb0_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
+
+/**
+ * cvmx_sli_msi_w1s_enb1
+ *
+ * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1
+ *
+ * Used to set bits in SLI_MSI_ENB1.
+ */
+union cvmx_sli_msi_w1s_enb1
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1s_enb1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in SLI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1s_enb1_s        cn63xx;
+	struct cvmx_sli_msi_w1s_enb1_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
+
+/**
+ * cvmx_sli_msi_w1s_enb2
+ *
+ * SLI_MSI_W1S_ENB2 = SLI MSI Write 1 To Set Enable2
+ *
+ * Used to set bits in SLI_MSI_ENB2.
+ */
+union cvmx_sli_msi_w1s_enb2
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1s_enb2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in SLI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1s_enb2_s        cn63xx;
+	struct cvmx_sli_msi_w1s_enb2_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
+
+/**
+ * cvmx_sli_msi_w1s_enb3
+ *
+ * SLI_MSI_W1S_ENB3 = SLI MSI Write 1 To Set Enable3
+ *
+ * Used to set bits in SLI_MSI_ENB3.
+ */
+union cvmx_sli_msi_w1s_enb3
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_w1s_enb3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in SLI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+	uint64_t set                          : 64;
+#endif
+	} s;
+	struct cvmx_sli_msi_w1s_enb3_s        cn63xx;
+	struct cvmx_sli_msi_w1s_enb3_s        cn63xxp1;
+};
+typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
+
+/**
+ * cvmx_sli_msi_wr_map
+ *
+ * SLI_MSI_WR_MAP = SLI MSI Write MAP
+ *
+ * Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
+ */
+union cvmx_sli_msi_wr_map
+{
+	uint64_t u64;
+	struct cvmx_sli_msi_wr_map_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ciu_int                      : 8;  /**< Selects which bit in the SLI_MSI_RCV# (0-255)
+                                                         will be set when the value specified in the
+                                                         MSI_INT of this register is recevied during a
+                                                         write to the SLI_PCIE_MSI_RCV register. */
+	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
+                                                         SLI_PCIE_MSI_RCV register is written. */
+#else
+	uint64_t msi_int                      : 8;
+	uint64_t ciu_int                      : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_sli_msi_wr_map_s          cn63xx;
+	struct cvmx_sli_msi_wr_map_s          cn63xxp1;
+};
+typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
+
+/**
+ * cvmx_sli_pcie_msi_rcv
+ *
+ * SLI_PCIE_MSI_RCV = SLI MAC MSI Receive
+ *
+ * Register where MSI writes are directed from the MAC.
+ */
+union cvmx_sli_pcie_msi_rcv
+{
+	uint64_t u64;
+	struct cvmx_sli_pcie_msi_rcv_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the SLI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the SLI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+#else
+	uint64_t intr                         : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sli_pcie_msi_rcv_s        cn63xx;
+	struct cvmx_sli_pcie_msi_rcv_s        cn63xxp1;
+};
+typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
+
+/**
+ * cvmx_sli_pcie_msi_rcv_b1
+ *
+ * SLI_PCIE_MSI_RCV_B1 = SLI MAC MSI Receive Byte 1
+ *
+ * Register where MSI writes are directed from the MAC.
+ *
+ * Notes:
+ * This CSR can be used by PCIe and sRIO MACs.
+ *
+ */
+union cvmx_sli_pcie_msi_rcv_b1
+{
+	uint64_t u64;
+	struct cvmx_sli_pcie_msi_rcv_b1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the SLI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the SLI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t intr                         : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xx;
+	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xxp1;
+};
+typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
+
+/**
+ * cvmx_sli_pcie_msi_rcv_b2
+ *
+ * SLI_PCIE_MSI_RCV_B2 = SLI MAC MSI Receive Byte 2
+ *
+ * Register where MSI writes are directed from the MAC.
+ *
+ * Notes:
+ * This CSR can be used by PCIe and sRIO MACs.
+ *
+ */
+union cvmx_sli_pcie_msi_rcv_b2
+{
+	uint64_t u64;
+	struct cvmx_sli_pcie_msi_rcv_b2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the SLI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the SLI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t intr                         : 8;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xx;
+	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xxp1;
+};
+typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
+
+/**
+ * cvmx_sli_pcie_msi_rcv_b3
+ *
+ * SLI_PCIE_MSI_RCV_B3 = SLI MAC MSI Receive Byte 3
+ *
+ * Register where MSI writes are directed from the MAC.
+ *
+ * Notes:
+ * This CSR can be used by PCIe and sRIO MACs.
+ *
+ */
+union cvmx_sli_pcie_msi_rcv_b3
+{
+	uint64_t u64;
+	struct cvmx_sli_pcie_msi_rcv_b3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
+                                                         one of the SLI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the SLI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+	uint64_t reserved_0_23                : 24;
+#else
+	uint64_t reserved_0_23                : 24;
+	uint64_t intr                         : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xx;
+	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xxp1;
+};
+typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
+
+/**
+ * cvmx_sli_pkt#_cnts
+ *
+ * SLI_PKT[0..31]_CNTS = SLI Packet ring# Counts
+ *
+ * The counters for output rings.
+ */
+union cvmx_sli_pktx_cnts
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t timer                        : 22; /**< Timer incremented every 1024 core clocks
+                                                         when SLI_PKTS#_CNTS[CNT] is non zero. Field
+                                                         cleared when SLI_PKTS#_CNTS[CNT] goes to 0.
+                                                         Field is also cleared when SLI_PKT_TIME_INT is
+                                                         cleared.
+                                                         The first increment of this count can occur
+                                                         between 0 to 1023 core clocks. */
+	uint64_t cnt                          : 32; /**< ring counter. This field is incremented as
+                                                         packets are sent out and decremented in response to
+                                                         writes to this field.
+                                                         When SLI_PKT_OUT_BMODE is '0' a value of 1 is
+                                                         added to the register for each packet, when '1'
+                                                         and the info-pointer is NOT used the length of the
+                                                         packet plus 8 is added, when '1' and info-pointer
+                                                         mode IS used the packet length is added to this
+                                                         field. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t timer                        : 22;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_sli_pktx_cnts_s           cn63xx;
+	struct cvmx_sli_pktx_cnts_s           cn63xxp1;
+};
+typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
+
+/**
+ * cvmx_sli_pkt#_in_bp
+ *
+ * SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure
+ *
+ * The counters and thresholds for input packets to apply backpressure to processing of the packets.
+ */
+union cvmx_sli_pktx_in_bp
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_in_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wmark                        : 32; /**< When CNT is greater than this threshold no more
+                                                         packets will be processed for this ring.
+                                                         When writing this field of the SLI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+	uint64_t cnt                          : 32; /**< ring counter. This field is incremented by one
+                                                         whenever OCTEON receives, buffers, and creates a
+                                                         work queue entry for a packet that arrives by the
+                                                         cooresponding input ring. A write to this field
+                                                         will be subtracted from the field value.
+                                                         When writing this field of the SLI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t wmark                        : 32;
+#endif
+	} s;
+	struct cvmx_sli_pktx_in_bp_s          cn63xx;
+	struct cvmx_sli_pktx_in_bp_s          cn63xxp1;
+};
+typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
+
+/**
+ * cvmx_sli_pkt#_instr_baddr
+ *
+ * SLI_PKT[0..31]_INSTR_BADDR = SLI Packet ring# Instruction Base Address
+ *
+ * Start of Instruction for input packets.
+ */
+union cvmx_sli_pktx_instr_baddr
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_instr_baddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 61; /**< Base address for Instructions. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t addr                         : 61;
+#endif
+	} s;
+	struct cvmx_sli_pktx_instr_baddr_s    cn63xx;
+	struct cvmx_sli_pktx_instr_baddr_s    cn63xxp1;
+};
+typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
+
+/**
+ * cvmx_sli_pkt#_instr_baoff_dbell
+ *
+ * SLI_PKT[0..31]_INSTR_BAOFF_DBELL = SLI Packet ring# Instruction Base Address Offset and Doorbell
+ *
+ * The doorbell and base address offset for next read.
+ */
+union cvmx_sli_pktx_instr_baoff_dbell
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
+                                                         where the next instruction will be read. */
+	uint64_t dbell                        : 32; /**< Instruction doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. A write of 0xffffffff will set the
+                                                         DBELL and AOFF fields to '0'. */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t aoff                         : 32;
+#endif
+	} s;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
+};
+typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
+
+/**
+ * cvmx_sli_pkt#_instr_fifo_rsize
+ *
+ * SLI_PKT[0..31]_INSTR_FIFO_RSIZE = SLI Packet ring# Instruction FIFO and Ring Size.
+ *
+ * Fifo field and ring size for Instructions.
+ */
+union cvmx_sli_pktx_instr_fifo_rsize
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t max                          : 9;  /**< Max Fifo Size. */
+	uint64_t rrp                          : 9;  /**< Fifo read pointer. */
+	uint64_t wrp                          : 9;  /**< Fifo write pointer. */
+	uint64_t fcnt                         : 5;  /**< Fifo count. */
+	uint64_t rsize                        : 32; /**< Instruction ring size. */
+#else
+	uint64_t rsize                        : 32;
+	uint64_t fcnt                         : 5;
+	uint64_t wrp                          : 9;
+	uint64_t rrp                          : 9;
+	uint64_t max                          : 9;
+#endif
+	} s;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
+};
+typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
+
+/**
+ * cvmx_sli_pkt#_instr_header
+ *
+ * SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header.
+ *
+ * VAlues used to build input packet header.
+ */
+union cvmx_sli_pktx_instr_header
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_instr_header_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode. */
+	uint64_t reserved_38_42               : 5;
+	uint64_t rparmode                     : 2;  /**< Parse Mode. Used when packet is raw and PBP==0. */
+	uint64_t reserved_35_35               : 1;
+	uint64_t rskp_len                     : 7;  /**< Skip Length. Used when packet is raw and PBP==0. */
+	uint64_t reserved_26_27               : 2;
+	uint64_t rnqos                        : 1;  /**< RNQOS. Used when packet is raw and PBP==0. */
+	uint64_t rngrp                        : 1;  /**< RNGRP. Used when packet is raw and PBP==0. */
+	uint64_t rntt                         : 1;  /**< RNTT. Used when packet is raw and PBP==0. */
+	uint64_t rntag                        : 1;  /**< RNTAG. Used when packet is raw and PBP==0. */
+	uint64_t use_ihdr                     : 1;  /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+	uint64_t reserved_16_20               : 5;
+	uint64_t par_mode                     : 2;  /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t reserved_13_13               : 1;
+	uint64_t skp_len                      : 7;  /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+	uint64_t reserved_4_5                 : 2;
+	uint64_t nqos                         : 1;  /**< NQOS. Used when packet is raw and PBP==0. */
+	uint64_t ngrp                         : 1;  /**< NGRP. Used when packet is raw and PBP==0. */
+	uint64_t ntt                          : 1;  /**< NTT. Used when packet is raw and PBP==0. */
+	uint64_t ntag                         : 1;  /**< NTAG. Used when packet is raw and PBP==0. */
+#else
+	uint64_t ntag                         : 1;
+	uint64_t ntt                          : 1;
+	uint64_t ngrp                         : 1;
+	uint64_t nqos                         : 1;
+	uint64_t reserved_4_5                 : 2;
+	uint64_t skp_len                      : 7;
+	uint64_t reserved_13_13               : 1;
+	uint64_t par_mode                     : 2;
+	uint64_t reserved_16_20               : 5;
+	uint64_t use_ihdr                     : 1;
+	uint64_t rntag                        : 1;
+	uint64_t rntt                         : 1;
+	uint64_t rngrp                        : 1;
+	uint64_t rnqos                        : 1;
+	uint64_t reserved_26_27               : 2;
+	uint64_t rskp_len                     : 7;
+	uint64_t reserved_35_35               : 1;
+	uint64_t rparmode                     : 2;
+	uint64_t reserved_38_42               : 5;
+	uint64_t pbp                          : 1;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_sli_pktx_instr_header_s   cn63xx;
+	struct cvmx_sli_pktx_instr_header_s   cn63xxp1;
+};
+typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
+
+/**
+ * cvmx_sli_pkt#_out_size
+ *
+ * SLI_PKT[0..31]_OUT_SIZE = SLI Packet Out Size
+ *
+ * Contains the BSIZE and ISIZE for output packet ports.
+ */
+union cvmx_sli_pktx_out_size
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_out_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t isize                        : 7;  /**< INFO BYTES size (bytes) for ring X. Legal sizes
+                                                         are 0 to 120. Not used in buffer-pointer-only mode. */
+	uint64_t bsize                        : 16; /**< BUFFER SIZE (bytes) for ring X. */
+#else
+	uint64_t bsize                        : 16;
+	uint64_t isize                        : 7;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_sli_pktx_out_size_s       cn63xx;
+	struct cvmx_sli_pktx_out_size_s       cn63xxp1;
+};
+typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
+
+/**
+ * cvmx_sli_pkt#_slist_baddr
+ *
+ * SLI_PKT[0..31]_SLIST_BADDR = SLI Packet ring# Scatter List Base Address
+ *
+ * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
+ */
+union cvmx_sli_pktx_slist_baddr
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_slist_baddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t addr                         : 60; /**< Base address for scatter list pointers. */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t addr                         : 60;
+#endif
+	} s;
+	struct cvmx_sli_pktx_slist_baddr_s    cn63xx;
+	struct cvmx_sli_pktx_slist_baddr_s    cn63xxp1;
+};
+typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
+
+/**
+ * cvmx_sli_pkt#_slist_baoff_dbell
+ *
+ * SLI_PKT[0..31]_SLIST_BAOFF_DBELL = SLI Packet ring# Scatter List Base Address Offset and Doorbell
+ *
+ * The doorbell and base address offset for next read.
+ */
+union cvmx_sli_pktx_slist_baoff_dbell
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR
+                                                         where the next SList pointer will be read.
+                                                         A write of 0xFFFFFFFF to the DBELL field will
+                                                         clear DBELL and AOFF */
+	uint64_t dbell                        : 32; /**< Scatter list doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. The value of this field is
+                                                         decremented as read operations are ISSUED for
+                                                         scatter pointers.
+                                                         A write of 0xFFFFFFFF will clear DBELL and AOFF */
+#else
+	uint64_t dbell                        : 32;
+	uint64_t aoff                         : 32;
+#endif
+	} s;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
+};
+typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
+
+/**
+ * cvmx_sli_pkt#_slist_fifo_rsize
+ *
+ * SLI_PKT[0..31]_SLIST_FIFO_RSIZE = SLI Packet ring# Scatter List FIFO and Ring Size.
+ *
+ * The number of scatter pointer pairs in the scatter list.
+ */
+union cvmx_sli_pktx_slist_fifo_rsize
+{
+	uint64_t u64;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t rsize                        : 32; /**< The number of scatter pointer pairs contained in
+                                                         the scatter list ring. */
+#else
+	uint64_t rsize                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
+};
+typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
+
+/**
+ * cvmx_sli_pkt_cnt_int
+ *
+ * SLI_PKT_CNT_INT = SLI Packet Counter Interrupt
+ *
+ * The packets rings that are interrupting because of Packet Counters.
+ */
+union cvmx_sli_pkt_cnt_int
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_cnt_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Output ring packet counter interrupt bits
+                                                         SLI sets PORT<i> whenever
+                                                         SLI_PKTi_CNTS[CNT] > SLI_PKT_INT_LEVELS[CNT].
+                                                         SLI_PKT_CNT_INT_ENB[PORT<i>] is the corresponding
+                                                         enable. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_cnt_int_s         cn63xx;
+	struct cvmx_sli_pkt_cnt_int_s         cn63xxp1;
+};
+typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
+
+/**
+ * cvmx_sli_pkt_cnt_int_enb
+ *
+ * SLI_PKT_CNT_INT_ENB = SLI Packet Counter Interrupt Enable
+ *
+ * Enable for the packets rings that are interrupting because of Packet Counters.
+ */
+union cvmx_sli_pkt_cnt_int_enb
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_cnt_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Output ring packet counter interrupt enables
+                                                         When both PORT<i> and corresponding
+                                                         SLI_PKT_CNT_INT[PORT<i>] are set, for any i,
+                                                         then SLI_INT_SUM[PCNT] is set, which can cause
+                                                         an interrupt. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xx;
+	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xxp1;
+};
+typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
+
+/**
+ * cvmx_sli_pkt_ctl
+ *
+ * SLI_PKT_CTL = SLI Packet Control
+ *
+ * Control for packets.
+ */
+union cvmx_sli_pkt_ctl
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t ring_en                      : 1;  /**< When '0' forces "relative Q position" received
+                                                         from PKO to be zero, and replicates the back-
+                                                         pressure indication for the first ring attached
+                                                         to a PKO port across all the rings attached to a
+                                                         PKO port. When '1' backpressure is on a per
+                                                         port/ring. */
+	uint64_t pkt_bp                       : 4;  /**< When set '1' enable the port level backpressure for
+                                                         PKO ports associated with the bit. */
+#else
+	uint64_t pkt_bp                       : 4;
+	uint64_t ring_en                      : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_sli_pkt_ctl_s             cn63xx;
+	struct cvmx_sli_pkt_ctl_s             cn63xxp1;
+};
+typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
+
+/**
+ * cvmx_sli_pkt_data_out_es
+ *
+ * SLI_PKT_DATA_OUT_ES = SLI's Packet Data Out Endian Swap
+ *
+ * The Endian Swap for writing Data Out.
+ */
+union cvmx_sli_pkt_data_out_es
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_data_out_es_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t es                           : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes.
+                                                         ES<2i+1:2i> becomes either ES<1:0> or
+                                                         MACADD<63:62> for writes to buffer/info pair
+                                                         MAC memory space addresses fetched from packet
+                                                         output ring i. ES<1:0> if SLI_PKT_DPADDR[DPTR<i>]=1
+                                                         , else MACADD<63:62>.
+                                                         In the latter case, ES<1:0> comes from DPTR<63:62>.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space writes. */
+#else
+	uint64_t es                           : 64;
+#endif
+	} s;
+	struct cvmx_sli_pkt_data_out_es_s     cn63xx;
+	struct cvmx_sli_pkt_data_out_es_s     cn63xxp1;
+};
+typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
+
+/**
+ * cvmx_sli_pkt_data_out_ns
+ *
+ * SLI_PKT_DATA_OUT_NS = SLI's Packet Data Out No Snoop
+ *
+ * The NS field for the TLP when writing packet data.
+ */
+union cvmx_sli_pkt_data_out_ns
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_data_out_ns_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nsr                          : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes.
+                                                         NSR<i> becomes either ADDRTYPE<1> or MACADD<61>
+                                                         for writes to buffer/info pair MAC memory space
+                                                         addresses fetched from packet output ring i.
+                                                         ADDRTYPE<1> if SLI_PKT_DPADDR[DPTR<i>]=1, else
+                                                         MACADD<61>.
+                                                         In the latter case,ADDRTYPE<1> comes from DPTR<61>.
+                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t nsr                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_data_out_ns_s     cn63xx;
+	struct cvmx_sli_pkt_data_out_ns_s     cn63xxp1;
+};
+typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;
+
+/**
+ * cvmx_sli_pkt_data_out_ror
+ *
+ * SLI_PKT_DATA_OUT_ROR = SLI's Packet Data Out Relaxed Ordering
+ *
+ * The ROR field for the TLP when writing Packet Data.
+ */
+union cvmx_sli_pkt_data_out_ror
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_data_out_ror_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ror                          : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes.
+                                                         ROR<i> becomes either ADDRTYPE<0> or MACADD<60>
+                                                         for writes to buffer/info pair MAC memory space
+                                                         addresses fetched from packet output ring i.
+                                                         ADDRTYPE<0> if SLI_PKT_DPADDR[DPTR<i>]=1, else
+                                                         MACADD<60>.
+                                                         In the latter case,ADDRTYPE<0> comes from DPTR<60>.
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t ror                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_data_out_ror_s    cn63xx;
+	struct cvmx_sli_pkt_data_out_ror_s    cn63xxp1;
+};
+typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;
+
+/**
+ * cvmx_sli_pkt_dpaddr
+ *
+ * SLI_PKT_DPADDR = SLI's Packet Data Pointer Addr
+ *
+ * Used to detemine address and attributes for packet data writes.
+ */
+union cvmx_sli_pkt_dpaddr
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_dpaddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t dptr                         : 32; /**< Determines whether buffer/info pointers are
+                                                         DPTR format 0 or DPTR format 1.
+                                                         When DPTR<i>=1, the buffer/info pointers fetched
+                                                         from packet output ring i are DPTR format 0.
+                                                         When DPTR<i>=0, the buffer/info pointers fetched
+                                                         from packet output ring i are DPTR format 1.
+                                                         (Replace SLI_PKT_INPUT_CONTROL[D_ESR,D_NSR,D_ROR]
+                                                         in the HRM descriptions of DPTR format 0/1 with
+                                                         SLI_PKT_DATA_OUT_ES[ES<2i+1:2i>],
+                                                         SLI_PKT_DATA_OUT_NS[NSR<i>], and
+                                                         SLI_PKT_DATA_OUT_ROR[ROR<i>], respectively,
+                                                         though.) */
+#else
+	uint64_t dptr                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_dpaddr_s          cn63xx;
+	struct cvmx_sli_pkt_dpaddr_s          cn63xxp1;
+};
+typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;
+
+/**
+ * cvmx_sli_pkt_in_bp
+ *
+ * SLI_PKT_IN_BP = SLI Packet Input Backpressure
+ *
+ * Which input rings have backpressure applied.
+ */
+union cvmx_sli_pkt_in_bp
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_in_bp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bp                           : 32; /**< A packet input  ring that has its count greater
+                                                         than its WMARK will have backpressure applied.
+                                                         Each of the 32 bits coorespond to an input ring.
+                                                         When '1' that ring has backpressure applied an
+                                                         will fetch no more instructions, but will process
+                                                         any previously fetched instructions. */
+#else
+	uint64_t bp                           : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_in_bp_s           cn63xx;
+	struct cvmx_sli_pkt_in_bp_s           cn63xxp1;
+};
+typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;
+
+/**
+ * cvmx_sli_pkt_in_done#_cnts
+ *
+ * SLI_PKT_IN_DONE[0..31]_CNTS = SLI Instruction Done ring# Counts
+ *
+ * Counters for instructions completed on Input rings.
+ */
+union cvmx_sli_pkt_in_donex_cnts
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_in_donex_cnts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< This field is incrmented by '1' when an instruction
+                                                         is completed. This field is incremented as the
+                                                         last of the data is read from the MAC. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn63xx;
+	struct cvmx_sli_pkt_in_donex_cnts_s   cn63xxp1;
+};
+typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;
+
+/**
+ * cvmx_sli_pkt_in_instr_counts
+ *
+ * SLI_PKT_IN_INSTR_COUNTS = SLI Packet Input Instrutction Counts
+ *
+ * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
+ */
+union cvmx_sli_pkt_in_instr_counts
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_in_instr_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_cnt                       : 32; /**< Shows the number of packets sent to the IPD. */
+	uint64_t rd_cnt                       : 32; /**< Shows the value of instructions that have had reads
+                                                         issued for them.
+                                                         to the Packet-ring is in reset. */
+#else
+	uint64_t rd_cnt                       : 32;
+	uint64_t wr_cnt                       : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
+	struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
+};
+typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;
+
+/**
+ * cvmx_sli_pkt_in_pcie_port
+ *
+ * SLI_PKT_IN_PCIE_PORT = SLI's Packet In To MAC Port Assignment
+ *
+ * Assigns Packet Input rings to MAC ports.
+ */
+union cvmx_sli_pkt_in_pcie_port
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_in_pcie_port_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pp                           : 64; /**< The MAC port that the Packet ring number is
+                                                         assigned. Two bits are used per ring (i.e. ring 0
+                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to MAC Port 0, a '1'
+                                                         MAC Port 1, '2' and '3' are reserved. */
+#else
+	uint64_t pp                           : 64;
+#endif
+	} s;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn63xx;
+	struct cvmx_sli_pkt_in_pcie_port_s    cn63xxp1;
+};
+typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;
+
+/**
+ * cvmx_sli_pkt_input_control
+ *
+ * SLI_PKT_INPUT_CONTROL = SLI's Packet Input Control
+ *
+ * Control for reads for gather list and instructions.
+ */
+union cvmx_sli_pkt_input_control
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_input_control_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_23_63               : 41;
+	uint64_t pkt_rr                       : 1;  /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet ring is fixed in priority,
+                                                         where the lower ring number has higher priority. */
+	uint64_t pbp_dhi                      : 13; /**< PBP_DHI replaces address bits that are used
+                                                         for parse mode and skip-length when
+                                                         SLI_PKTi_INSTR_HEADER[PBP]=1.
+                                                         PBP_DHI becomes either MACADD<63:55> or MACADD<59:51>
+                                                         for the instruction DPTR reads in this case.
+                                                         The instruction DPTR reads are called
+                                                         "First Direct" or "First Indirect" in the HRM.
+                                                         When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI
+                                                         becomes MACADD<59:51>, else MACADD<63:55>. */
+	uint64_t d_nsr                        : 1;  /**< ADDRTYPE<1> or MACADD<61> for packet input data
+                                                         reads.
+                                                         D_NSR becomes either ADDRTYPE<1> or MACADD<61>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ADDRTYPE<1> if USE_CSR=1, else MACADD<61>.
+                                                         In the latter case, ADDRTYPE<1> comes from DPTR<61>.
+                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t d_esr                        : 2;  /**< ES<1:0> or MACADD<63:62> for packet input data
+                                                         reads.
+                                                         D_ESR becomes either ES<1:0> or MACADD<63:62>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ES<1:0> if USE_CSR=1, else MACADD<63:62>.
+                                                         In the latter case, ES<1:0> comes from DPTR<63:62>.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t d_ror                        : 1;  /**< ADDRTYPE<0> or MACADD<60> for packet input data
+                                                         reads.
+                                                         D_ROR becomes either ADDRTYPE<0> or MACADD<60>
+                                                         for MAC memory space reads of packet input data
+                                                         fetched for any packet input ring.
+                                                         ADDRTYPE<0> if USE_CSR=1, else MACADD<60>.
+                                                         In the latter case, ADDRTYPE<0> comes from DPTR<60>.
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t use_csr                      : 1;  /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+	uint64_t nsr                          : 1;  /**< ADDRTYPE<1> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+	uint64_t esr                          : 2;  /**< ES<1:0> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+	uint64_t ror                          : 1;  /**< ADDRTYPE<0> for packet input instruction reads and
+                                                         gather list (i.e. DPI component) reads from MAC
+                                                         memory space.
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t ror                          : 1;
+	uint64_t esr                          : 2;
+	uint64_t nsr                          : 1;
+	uint64_t use_csr                      : 1;
+	uint64_t d_ror                        : 1;
+	uint64_t d_esr                        : 2;
+	uint64_t d_nsr                        : 1;
+	uint64_t pbp_dhi                      : 13;
+	uint64_t pkt_rr                       : 1;
+	uint64_t reserved_23_63               : 41;
+#endif
+	} s;
+	struct cvmx_sli_pkt_input_control_s   cn63xx;
+	struct cvmx_sli_pkt_input_control_s   cn63xxp1;
+};
+typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;
+
+/**
+ * cvmx_sli_pkt_instr_enb
+ *
+ * SLI_PKT_INSTR_ENB = SLI's Packet Instruction Enable
+ *
+ * Enables the instruction fetch for a Packet-ring.
+ */
+union cvmx_sli_pkt_instr_enb
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_instr_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enb                          : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */
+#else
+	uint64_t enb                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_instr_enb_s       cn63xx;
+	struct cvmx_sli_pkt_instr_enb_s       cn63xxp1;
+};
+typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;
+
+/**
+ * cvmx_sli_pkt_instr_rd_size
+ *
+ * SLI_PKT_INSTR_RD_SIZE = SLI Instruction Read Size
+ *
+ * The number of instruction allowed to be read at one time.
+ */
+union cvmx_sli_pkt_instr_rd_size
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_instr_rd_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rdsize                       : 64; /**< Number of instructions to be read in one MAC read
+                                                         request for the 4 ports - 8 rings. Every two bits
+                                                         (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
+                                                         combinations.
+                                                         - 15:0  PKIPort0,Ring 7..0  31:16 PKIPort1,Ring 7..0
+                                                         - 47:32 PKIPort2,Ring 7..0  63:48 PKIPort3,Ring 7..0
+                                                         Two bit value are:
+                                                         0 - 1 Instruction
+                                                         1 - 2 Instructions
+                                                         2 - 3 Instructions
+                                                         3 - 4 Instructions */
+#else
+	uint64_t rdsize                       : 64;
+#endif
+	} s;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn63xx;
+	struct cvmx_sli_pkt_instr_rd_size_s   cn63xxp1;
+};
+typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;
+
+/**
+ * cvmx_sli_pkt_instr_size
+ *
+ * SLI_PKT_INSTR_SIZE = SLI's Packet Instruction Size
+ *
+ * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
+ */
+union cvmx_sli_pkt_instr_size
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_instr_size_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t is_64b                       : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B
+                                                         instructions, else 32B instructions. */
+#else
+	uint64_t is_64b                       : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_instr_size_s      cn63xx;
+	struct cvmx_sli_pkt_instr_size_s      cn63xxp1;
+};
+typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;
+
+/**
+ * cvmx_sli_pkt_int_levels
+ *
+ * 0x90F0 reserved SLI_PKT_PCIE_PORT2
+ *
+ *
+ *                  SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels
+ *
+ * Output packet interrupt levels.
+ */
+union cvmx_sli_pkt_int_levels
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_int_levels_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t time                         : 22; /**< Output ring counter time interrupt threshold
+                                                         SLI sets SLI_PKT_TIME_INT[PORT<i>] whenever
+                                                         SLI_PKTi_CNTS[TIMER] > TIME */
+	uint64_t cnt                          : 32; /**< Output ring counter interrupt threshold
+                                                         SLI sets SLI_PKT_CNT_INT[PORT<i>] whenever
+                                                         SLI_PKTi_CNTS[CNT] > CNT */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t time                         : 22;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_sli_pkt_int_levels_s      cn63xx;
+	struct cvmx_sli_pkt_int_levels_s      cn63xxp1;
+};
+typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;
+
+/**
+ * cvmx_sli_pkt_iptr
+ *
+ * SLI_PKT_IPTR = SLI's Packet Info Poitner
+ *
+ * Controls using the Info-Pointer to store length and data.
+ */
+union cvmx_sli_pkt_iptr
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_iptr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t iptr                         : 32; /**< When IPTR<i>=1, packet output ring i is in info-
+                                                         pointer mode, else buffer-pointer-only mode. */
+#else
+	uint64_t iptr                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_iptr_s            cn63xx;
+	struct cvmx_sli_pkt_iptr_s            cn63xxp1;
+};
+typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;
+
+/**
+ * cvmx_sli_pkt_out_bmode
+ *
+ * SLI_PKT_OUT_BMODE = SLI's Packet Out Byte Mode
+ *
+ * Control the updating of the SLI_PKT#_CNT register.
+ */
+union cvmx_sli_pkt_out_bmode
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_out_bmode_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bmode                        : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or
+                                                         packet counter.
+                                                         When BMODE<i>=1, SLI_PKTi_CNTS[CNT] is a byte
+                                                         counter, else SLI_PKTi_CNTS[CNT] is a packet
+                                                         counter. */
+#else
+	uint64_t bmode                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_out_bmode_s       cn63xx;
+	struct cvmx_sli_pkt_out_bmode_s       cn63xxp1;
+};
+typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t;
+
+/**
+ * cvmx_sli_pkt_out_enb
+ *
+ * SLI_PKT_OUT_ENB = SLI's Packet Output Enable
+ *
+ * Enables the output packet engines.
+ */
+union cvmx_sli_pkt_out_enb
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_out_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enb                          : 32; /**< When ENB<i>=1, packet output ring i is enabled.
+                                                         If an error occurs on reading pointers for an
+                                                         output ring, the ring will be disabled by clearing
+                                                         the bit associated with the ring to '0'. */
+#else
+	uint64_t enb                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_out_enb_s         cn63xx;
+	struct cvmx_sli_pkt_out_enb_s         cn63xxp1;
+};
+typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;
+
+/**
+ * cvmx_sli_pkt_output_wmark
+ *
+ * SLI_PKT_OUTPUT_WMARK = SLI's Packet Output Water Mark
+ *
+ * Value that when the SLI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
+ */
+union cvmx_sli_pkt_output_wmark
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_output_wmark_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t wmark                        : 32; /**< Value when DBELL count drops below backpressure
+                                                         for the ring will be applied to the PKO. */
+#else
+	uint64_t wmark                        : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_output_wmark_s    cn63xx;
+	struct cvmx_sli_pkt_output_wmark_s    cn63xxp1;
+};
+typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;
+
+/**
+ * cvmx_sli_pkt_pcie_port
+ *
+ * SLI_PKT_PCIE_PORT = SLI's Packet To MAC Port Assignment
+ *
+ * Assigns Packet Ports to MAC ports.
+ */
+union cvmx_sli_pkt_pcie_port
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_pcie_port_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t pp                           : 64; /**< The physical MAC  port that the output ring uses.
+                                                         Two bits are used per ring (i.e. ring 0 [1:0],
+                                                         ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to MAC Port 0, a '1'
+                                                         MAC Port 1, '2' and '3' are reserved. */
+#else
+	uint64_t pp                           : 64;
+#endif
+	} s;
+	struct cvmx_sli_pkt_pcie_port_s       cn63xx;
+	struct cvmx_sli_pkt_pcie_port_s       cn63xxp1;
+};
+typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;
+
+/**
+ * cvmx_sli_pkt_port_in_rst
+ *
+ * 91c0 reserved
+ * 91d0 reserved
+ * 91e0 reserved
+ *
+ *
+ *                   SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset
+ *
+ *  Vector bits related to ring-port for ones that are reset.
+ */
+union cvmx_sli_pkt_port_in_rst
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_port_in_rst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t in_rst                       : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the inbound Packet-ring is in reset. */
+	uint64_t out_rst                      : 32; /**< When asserted '1' the vector bit cooresponding
+                                                         to the outbound Packet-ring is in reset. */
+#else
+	uint64_t out_rst                      : 32;
+	uint64_t in_rst                       : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_port_in_rst_s     cn63xx;
+	struct cvmx_sli_pkt_port_in_rst_s     cn63xxp1;
+};
+typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;
+
+/**
+ * cvmx_sli_pkt_slist_es
+ *
+ * SLI_PKT_SLIST_ES = SLI's Packet Scatter List Endian Swap
+ *
+ * The Endian Swap for Scatter List Read.
+ */
+union cvmx_sli_pkt_slist_es
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_slist_es_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t es                           : 64; /**< ES<1:0> for the packet output ring reads that
+                                                         fetch buffer/info pointer pairs.
+                                                         ES<2i+1:2i> becomes ES<1:0> in DPI/SLI reads that
+                                                         fetch buffer/info pairs from packet output ring i
+                                                         (from address SLI_PKTi_SLIST_BADDR+ in MAC memory
+                                                         space.)
+                                                         ES<1:0> is the endian-swap attribute for these MAC
+                                                         memory space reads. */
+#else
+	uint64_t es                           : 64;
+#endif
+	} s;
+	struct cvmx_sli_pkt_slist_es_s        cn63xx;
+	struct cvmx_sli_pkt_slist_es_s        cn63xxp1;
+};
+typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;
+
+/**
+ * cvmx_sli_pkt_slist_ns
+ *
+ * SLI_PKT_SLIST_NS = SLI's Packet Scatter List No Snoop
+ *
+ * The NS field for the TLP when fetching Scatter List.
+ */
+union cvmx_sli_pkt_slist_ns
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_slist_ns_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t nsr                          : 32; /**< ADDRTYPE<1> for the packet output ring reads that
+                                                         fetch buffer/info pointer pairs.
+                                                         NSR<i> becomes ADDRTYPE<1> in DPI/SLI reads that
+                                                         fetch buffer/info pairs from packet output ring i
+                                                         (from address SLI_PKTi_SLIST_BADDR+ in MAC memory
+                                                         space.)
+                                                         ADDRTYPE<1> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t nsr                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_slist_ns_s        cn63xx;
+	struct cvmx_sli_pkt_slist_ns_s        cn63xxp1;
+};
+typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;
+
+/**
+ * cvmx_sli_pkt_slist_ror
+ *
+ * SLI_PKT_SLIST_ROR = SLI's Packet Scatter List Relaxed Ordering
+ *
+ * The ROR field for the TLP when fetching Scatter List.
+ */
+union cvmx_sli_pkt_slist_ror
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_slist_ror_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t ror                          : 32; /**< ADDRTYPE<0> for the packet output ring reads that
+                                                         fetch buffer/info pointer pairs.
+                                                         ROR<i> becomes ADDRTYPE<0> in DPI/SLI reads that
+                                                         fetch buffer/info pairs from packet output ring i
+                                                         (from address SLI_PKTi_SLIST_BADDR+ in MAC memory
+                                                         space.)
+                                                         ADDRTYPE<0> is the relaxed-order attribute for PCIe
+                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
+#else
+	uint64_t ror                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_slist_ror_s       cn63xx;
+	struct cvmx_sli_pkt_slist_ror_s       cn63xxp1;
+};
+typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;
+
+/**
+ * cvmx_sli_pkt_time_int
+ *
+ * SLI_PKT_TIME_INT = SLI Packet Timer Interrupt
+ *
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+union cvmx_sli_pkt_time_int
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_time_int_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Output ring packet timer interrupt bits
+                                                         SLI sets PORT<i> whenever
+                                                         SLI_PKTi_CNTS[TIMER] > SLI_PKT_INT_LEVELS[TIME].
+                                                         SLI_PKT_TIME_INT_ENB[PORT<i>] is the corresponding
+                                                         enable. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_time_int_s        cn63xx;
+	struct cvmx_sli_pkt_time_int_s        cn63xxp1;
+};
+typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;
+
+/**
+ * cvmx_sli_pkt_time_int_enb
+ *
+ * SLI_PKT_TIME_INT_ENB = SLI Packet Timer Interrupt Enable
+ *
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+union cvmx_sli_pkt_time_int_enb
+{
+	uint64_t u64;
+	struct cvmx_sli_pkt_time_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t port                         : 32; /**< Output ring packet timer interrupt enables
+                                                         When both PORT<i> and corresponding
+                                                         SLI_PKT_TIME_INT[PORT<i>] are set, for any i,
+                                                         then SLI_INT_SUM[PTIME] is set, which can cause
+                                                         an interrupt. */
+#else
+	uint64_t port                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_pkt_time_int_enb_s    cn63xx;
+	struct cvmx_sli_pkt_time_int_enb_s    cn63xxp1;
+};
+typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;
+
+/**
+ * cvmx_sli_s2m_port#_ctl
+ *
+ * SLI_S2M_PORTX_CTL = SLI's S2M Port 0 Control
+ *
+ * Contains control for access from SLI to a MAC port.
+ * Writes to this register are not ordered with writes/reads to the MAC Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. MAC memory space) that requires the value of this register to be updated.
+ */
+union cvmx_sli_s2m_portx_ctl
+{
+	uint64_t u64;
+	struct cvmx_sli_s2m_portx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t wind_d                       : 1;  /**< When set '1' disables access to the Window
+                                                         Registers from the MAC-Port. */
+	uint64_t bar0_d                       : 1;  /**< When set '1' disables access from MAC to
+                                                         BAR-0 address offsets: Less Than 0x330,
+                                                         0x3CD0, and greater than 0x3D70. */
+	uint64_t mrrs                         : 3;  /**< Max Read Request Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                                 2 = 512B
+                                                                 3 = 1024B
+                                                                 4 = 2048B
+                                                                 5-7 = Reserved
+                                                         This field should not exceed the desired
+                                                               max read request size. This field is used to
+                                                               determine if an IOBDMA is too large.
+                                                         For a PCIe MAC, this field should not exceed
+                                                               PCIE*_CFG030[MRRS].
+                                                         For a sRIO MAC, this field should indicate a size
+                                                               of 256B or smaller. */
+#else
+	uint64_t mrrs                         : 3;
+	uint64_t bar0_d                       : 1;
+	uint64_t wind_d                       : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_sli_s2m_portx_ctl_s       cn63xx;
+	struct cvmx_sli_s2m_portx_ctl_s       cn63xxp1;
+};
+typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;
+
+/**
+ * cvmx_sli_scratch_1
+ *
+ * SLI_SCRATCH_1 = SLI's Scratch 1
+ *
+ * A general purpose 64 bit register for SW use.
+ */
+union cvmx_sli_scratch_1
+{
+	uint64_t u64;
+	struct cvmx_sli_scratch_1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_scratch_1_s           cn63xx;
+	struct cvmx_sli_scratch_1_s           cn63xxp1;
+};
+typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;
+
+/**
+ * cvmx_sli_scratch_2
+ *
+ * SLI_SCRATCH_2 = SLI's Scratch 2
+ *
+ * A general purpose 64 bit register for SW use.
+ */
+union cvmx_sli_scratch_2
+{
+	uint64_t u64;
+	struct cvmx_sli_scratch_2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< The value in this register is totaly SW dependent. */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_sli_scratch_2_s           cn63xx;
+	struct cvmx_sli_scratch_2_s           cn63xxp1;
+};
+typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;
+
+/**
+ * cvmx_sli_state1
+ *
+ * SLI_STATE1 = SLI State 1
+ *
+ * State machines in SLI. For debug.
+ */
+union cvmx_sli_state1
+{
+	uint64_t u64;
+	struct cvmx_sli_state1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cpl1                         : 12; /**< CPL1 State */
+	uint64_t cpl0                         : 12; /**< CPL0 State */
+	uint64_t arb                          : 1;  /**< ARB State */
+	uint64_t csr                          : 39; /**< CSR State */
+#else
+	uint64_t csr                          : 39;
+	uint64_t arb                          : 1;
+	uint64_t cpl0                         : 12;
+	uint64_t cpl1                         : 12;
+#endif
+	} s;
+	struct cvmx_sli_state1_s              cn63xx;
+	struct cvmx_sli_state1_s              cn63xxp1;
+};
+typedef union cvmx_sli_state1 cvmx_sli_state1_t;
+
+/**
+ * cvmx_sli_state2
+ *
+ * SLI_STATE2 = SLI State 2
+ *
+ * State machines in SLI. For debug.
+ */
+union cvmx_sli_state2
+{
+	uint64_t u64;
+	struct cvmx_sli_state2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t nnp1                         : 8;  /**< NNP1 State */
+	uint64_t reserved_47_47               : 1;
+	uint64_t rac                          : 1;  /**< RAC State */
+	uint64_t csm1                         : 15; /**< CSM1 State */
+	uint64_t csm0                         : 15; /**< CSM0 State */
+	uint64_t nnp0                         : 8;  /**< NNP0 State */
+	uint64_t nnd                          : 8;  /**< NND State */
+#else
+	uint64_t nnd                          : 8;
+	uint64_t nnp0                         : 8;
+	uint64_t csm0                         : 15;
+	uint64_t csm1                         : 15;
+	uint64_t rac                          : 1;
+	uint64_t reserved_47_47               : 1;
+	uint64_t nnp1                         : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_sli_state2_s              cn63xx;
+	struct cvmx_sli_state2_s              cn63xxp1;
+};
+typedef union cvmx_sli_state2 cvmx_sli_state2_t;
+
+/**
+ * cvmx_sli_state3
+ *
+ * SLI_STATE3 = SLI State 3
+ *
+ * State machines in SLI. For debug.
+ */
+union cvmx_sli_state3
+{
+	uint64_t u64;
+	struct cvmx_sli_state3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t psm1                         : 15; /**< PSM1 State */
+	uint64_t psm0                         : 15; /**< PSM0 State */
+	uint64_t nsm1                         : 13; /**< NSM1 State */
+	uint64_t nsm0                         : 13; /**< NSM0 State */
+#else
+	uint64_t nsm0                         : 13;
+	uint64_t nsm1                         : 13;
+	uint64_t psm0                         : 15;
+	uint64_t psm1                         : 15;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_sli_state3_s              cn63xx;
+	struct cvmx_sli_state3_s              cn63xxp1;
+};
+typedef union cvmx_sli_state3 cvmx_sli_state3_t;
+
+/**
+ * cvmx_sli_win_rd_addr
+ *
+ * SLI_WIN_RD_ADDR = SLI Window Read Address Register
+ *
+ * The address to be read when the SLI_WIN_RD_DATA register is read.
+ * This register should NOT be used to read SLI_* registers.
+ */
+union cvmx_sli_win_rd_addr
+{
+	uint64_t u64;
+	struct cvmx_sli_win_rd_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_51_63               : 13;
+	uint64_t ld_cmd                       : 2;  /**< The load command sent wit hthe read.
+                                                         0x3 == Load 8-bytes, 0x2 == Load 4-bytes,
+                                                         0x1 == Load 2-bytes, 0x0 == Load 1-bytes, */
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but will not be used
+                                                         in address generation. */
+	uint64_t rd_addr                      : 48; /**< The address to be read from.
+                                                         [47:40] = NCB_ID
+                                                         [39:0]  = Address
+                                                         When [47:43] == SLI & [42:40] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:24] == RSL_ID
+                                                              [23:0]  == RSL Register Offset */
+#else
+	uint64_t rd_addr                      : 48;
+	uint64_t iobit                        : 1;
+	uint64_t ld_cmd                       : 2;
+	uint64_t reserved_51_63               : 13;
+#endif
+	} s;
+	struct cvmx_sli_win_rd_addr_s         cn63xx;
+	struct cvmx_sli_win_rd_addr_s         cn63xxp1;
+};
+typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;
+
+/**
+ * cvmx_sli_win_rd_data
+ *
+ * SLI_WIN_RD_DATA = SLI Window Read Data Register
+ *
+ * Reading this register causes a window read operation to take place. Address read is that contained in the SLI_WIN_RD_ADDR
+ * register.
+ */
+union cvmx_sli_win_rd_data
+{
+	uint64_t u64;
+	struct cvmx_sli_win_rd_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rd_data                      : 64; /**< The read data. */
+#else
+	uint64_t rd_data                      : 64;
+#endif
+	} s;
+	struct cvmx_sli_win_rd_data_s         cn63xx;
+	struct cvmx_sli_win_rd_data_s         cn63xxp1;
+};
+typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;
+
+/**
+ * cvmx_sli_win_wr_addr
+ *
+ * Add Lock Register (Set on Read, Clear on write), SW uses to control access to BAR0 space.
+ *
+ * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
+ *
+ * General  5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
+ * PktMem  10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
+ * Rsvd     1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
+ *
+ *                  SLI_WIN_WR_ADDR = SLI Window Write Address Register
+ *
+ * Contains the address to be writen to when a write operation is started by writing the
+ * SLI_WIN_WR_DATA register (see below).
+ *
+ * This register should NOT be used to write SLI_* registers.
+ */
+union cvmx_sli_win_wr_addr
+{
+	uint64_t u64;
+	struct cvmx_sli_win_wr_addr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_49_63               : 15;
+	uint64_t iobit                        : 1;  /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+	uint64_t wr_addr                      : 45; /**< The address that will be written to when the
+                                                         SLI_WIN_WR_DATA register is written.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == SLI & [42:40] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:24] == RSL_ID
+                                                              [23:3]  == RSL Register Offset */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t wr_addr                      : 45;
+	uint64_t iobit                        : 1;
+	uint64_t reserved_49_63               : 15;
+#endif
+	} s;
+	struct cvmx_sli_win_wr_addr_s         cn63xx;
+	struct cvmx_sli_win_wr_addr_s         cn63xxp1;
+};
+typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;
+
+/**
+ * cvmx_sli_win_wr_data
+ *
+ * SLI_WIN_WR_DATA = SLI Window Write Data Register
+ *
+ * Contains the data to write to the address located in the SLI_WIN_WR_ADDR Register.
+ * Writing the least-significant-byte of this register will cause a write operation to take place.
+ */
+union cvmx_sli_win_wr_data
+{
+	uint64_t u64;
+	struct cvmx_sli_win_wr_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_data                      : 64; /**< The data to be written. Whenever the LSB of this
+                                                         register is written, the Window Write will take
+                                                         place. */
+#else
+	uint64_t wr_data                      : 64;
+#endif
+	} s;
+	struct cvmx_sli_win_wr_data_s         cn63xx;
+	struct cvmx_sli_win_wr_data_s         cn63xxp1;
+};
+typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;
+
+/**
+ * cvmx_sli_win_wr_mask
+ *
+ * SLI_WIN_WR_MASK = SLI Window Write Mask Register
+ *
+ * Contains the mask for the data in the SLI_WIN_WR_DATA Register.
+ */
+union cvmx_sli_win_wr_mask
+{
+	uint64_t u64;
+	struct cvmx_sli_win_wr_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t wr_mask                      : 8;  /**< The data to be written. When a bit is '1'
+                                                         the corresponding byte will be written. The values
+                                                         of this field must be contiguos and for 1, 2, 4, or
+                                                         8 byte operations and aligned to operation size.
+                                                         A Value of 0 will produce unpredictable results */
+#else
+	uint64_t wr_mask                      : 8;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_sli_win_wr_mask_s         cn63xx;
+	struct cvmx_sli_win_wr_mask_s         cn63xxp1;
+};
+typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;
+
+/**
+ * cvmx_sli_window_ctl
+ *
+ * // *
+ * // * 81e0 - 82d0 Reserved for future subids
+ * // *
+ *
+ *                   SLI_WINDOW_CTL = SLI's Window Control
+ *
+ *  Access to register space on the NCB (caused by Window Reads/Writes) will wait for a period of time specified
+ *  by this register before timeing out. Because a Window Access can access the RML, which has a fixed timeout of 0xFFFF
+ *  core clocks, the value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
+ *  occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the MAC.
+ */
+union cvmx_sli_window_ctl
+{
+	uint64_t u64;
+	struct cvmx_sli_window_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t time                         : 32; /**< Time to wait in core clocks for a
+                                                         BAR0 access to completeon the NCB
+                                                         before timing out. A value of 0 will cause no
+                                                         timeouts. A minimum value of 0x200000 should be
+                                                         used when this register is not set to 0x0. */
+#else
+	uint64_t time                         : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sli_window_ctl_s          cn63xx;
+	struct cvmx_sli_window_ctl_s          cn63xxp1;
+};
+typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-smi-defs.h b/sys/contrib/octeon-sdk/cvmx-smi-defs.h
new file mode 100644
index 0000000..c77802f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-smi-defs.h
@@ -0,0 +1,101 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-smi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon smi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SMI_TYPEDEFS_H__
+#define __CVMX_SMI_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SMI_DRV_CTL CVMX_SMI_DRV_CTL_FUNC()
+static inline uint64_t CVMX_SMI_DRV_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_SMI_DRV_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180000001828ull);
+}
+#else
+#define CVMX_SMI_DRV_CTL (CVMX_ADD_IO_SEG(0x0001180000001828ull))
+#endif
+
+/**
+ * cvmx_smi_drv_ctl
+ *
+ * SMI_DRV_CTL = SMI Drive Strength Control
+ *
+ */
+union cvmx_smi_drv_ctl
+{
+	uint64_t u64;
+	struct cvmx_smi_drv_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t pctl                         : 6;  /**< PCTL Drive strength control bits
+                                                         Assuming a 50ohm termination
+                                                         3.3v supply = 19
+                                                         2.5v supply = TBD */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t nctl                         : 6;  /**< NCTL Drive strength control bits
+                                                         Assuming a 50ohm termination
+                                                         3.3v supply = 15
+                                                         2.5v supply = TBD */
+#else
+	uint64_t nctl                         : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t pctl                         : 6;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_smi_drv_ctl_s             cn63xx;
+	struct cvmx_smi_drv_ctl_s             cn63xxp1;
+};
+typedef union cvmx_smi_drv_ctl cvmx_smi_drv_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-smix-defs.h b/sys/contrib/octeon-sdk/cvmx-smix-defs.h
new file mode 100644
index 0000000..9474666
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-smix-defs.h
@@ -0,0 +1,450 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-smix-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon smix.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SMIX_TYPEDEFS_H__
+#define __CVMX_SMIX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256;
+}
+#else
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256;
+}
+#else
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256;
+}
+#else
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256;
+}
+#else
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+		cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n", offset);
+	return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256;
+}
+#else
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
+#endif
+
+/**
+ * cvmx_smi#_clk
+ *
+ * SMI_CLK = Clock Control Register
+ *
+ */
+union cvmx_smix_clk
+{
+	uint64_t u64;
+	struct cvmx_smix_clk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t mode                         : 1;  /**< IEEE operating mode
+                                                         0=Clause 22 complient
+                                                         1=Clause 45 complient */
+	uint64_t reserved_21_23               : 3;
+	uint64_t sample_hi                    : 5;  /**< When to sample read data (extended bits) */
+	uint64_t sample_mode                  : 1;  /**< Read Data sampling mode
+                                                         According to the 802.3 spec, on reads, the STA
+                                                         transitions MDC and the PHY drives MDIO with
+                                                         some delay relative to that edge.  This is edge1.
+                                                         The STA then samples MDIO on the next rising edge
+                                                         of MDC.  This is edge2. Octeon can sample the
+                                                         read data relative to either edge.
+                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge2
+                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge1 */
+	uint64_t reserved_14_14               : 1;
+	uint64_t clk_idle                     : 1;  /**< Do not toggle MDC on idle cycles */
+	uint64_t preamble                     : 1;  /**< Send PREAMBLE on SMI transacton
+                                                         PREAMBLE must be set 1 when MODE=1 in order
+                                                         for the receiving PHY to correctly frame the
+                                                         transaction. */
+	uint64_t sample                       : 4;  /**< When to sample read data
+                                                         (number of eclks after the rising edge of mdc)
+                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
+                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
+	uint64_t phase                        : 8;  /**< MDC Clock Phase
+                                                         (number of eclks that make up an mdc phase)
+                                                         (PHASE > 2) */
+#else
+	uint64_t phase                        : 8;
+	uint64_t sample                       : 4;
+	uint64_t preamble                     : 1;
+	uint64_t clk_idle                     : 1;
+	uint64_t reserved_14_14               : 1;
+	uint64_t sample_mode                  : 1;
+	uint64_t sample_hi                    : 5;
+	uint64_t reserved_21_23               : 3;
+	uint64_t mode                         : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_smix_clk_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_21_63               : 43;
+	uint64_t sample_hi                    : 5;  /**< When to sample read data (extended bits) */
+	uint64_t sample_mode                  : 1;  /**< Read Data sampling mode
+                                                         According to the 802.3 spec, on reads, the STA
+                                                         transitions MDC and the PHY drives MDIO with
+                                                         some delay relative to that edge.  This is edge1.
+                                                         The STA then samples MDIO on the next rising edge
+                                                         of MDC.  This is edge2. Octeon can sample the
+                                                         read data relative to either edge.
+                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge2
+                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge1 */
+	uint64_t reserved_14_14               : 1;
+	uint64_t clk_idle                     : 1;  /**< Do not toggle MDC on idle cycles */
+	uint64_t preamble                     : 1;  /**< Send PREAMBLE on SMI transacton */
+	uint64_t sample                       : 4;  /**< When to sample read data
+                                                         (number of eclks after the rising edge of mdc)
+                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
+                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
+	uint64_t phase                        : 8;  /**< MDC Clock Phase
+                                                         (number of eclks that make up an mdc phase)
+                                                         (PHASE > 2) */
+#else
+	uint64_t phase                        : 8;
+	uint64_t sample                       : 4;
+	uint64_t preamble                     : 1;
+	uint64_t clk_idle                     : 1;
+	uint64_t reserved_14_14               : 1;
+	uint64_t sample_mode                  : 1;
+	uint64_t sample_hi                    : 5;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} cn30xx;
+	struct cvmx_smix_clk_cn30xx           cn31xx;
+	struct cvmx_smix_clk_cn30xx           cn38xx;
+	struct cvmx_smix_clk_cn30xx           cn38xxp2;
+	struct cvmx_smix_clk_s                cn50xx;
+	struct cvmx_smix_clk_s                cn52xx;
+	struct cvmx_smix_clk_s                cn52xxp1;
+	struct cvmx_smix_clk_s                cn56xx;
+	struct cvmx_smix_clk_s                cn56xxp1;
+	struct cvmx_smix_clk_cn30xx           cn58xx;
+	struct cvmx_smix_clk_cn30xx           cn58xxp1;
+	struct cvmx_smix_clk_s                cn63xx;
+	struct cvmx_smix_clk_s                cn63xxp1;
+};
+typedef union cvmx_smix_clk cvmx_smix_clk_t;
+
+/**
+ * cvmx_smi#_cmd
+ *
+ * SMI_CMD = Force a Read/Write command to the PHY
+ *
+ *
+ * Notes:
+ * Writes to this register will create SMI xactions.  Software will poll on (depending on the xaction type).
+ *
+ */
+union cvmx_smix_cmd
+{
+	uint64_t u64;
+	struct cvmx_smix_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t phy_op                       : 2;  /**< PHY Opcode depending on SMI_CLK[MODE]
+                                                         SMI_CLK[MODE] == 0 (<=1Gbs / Clause 22)
+                                                          x0=write
+                                                          x1=read
+                                                         SMI_CLK[MODE] == 1 (>1Gbs / Clause 45)
+                                                          00=address
+                                                          01=write
+                                                          11=read
+                                                          10=post-read-increment-address */
+	uint64_t reserved_13_15               : 3;
+	uint64_t phy_adr                      : 5;  /**< PHY Address */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t reg_adr                      : 5;  /**< PHY Register Offset */
+#else
+	uint64_t reg_adr                      : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t phy_adr                      : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t phy_op                       : 2;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_smix_cmd_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t phy_op                       : 1;  /**< PHY Opcode
+                                                         0=write
+                                                         1=read */
+	uint64_t reserved_13_15               : 3;
+	uint64_t phy_adr                      : 5;  /**< PHY Address */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t reg_adr                      : 5;  /**< PHY Register Offset */
+#else
+	uint64_t reg_adr                      : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t phy_adr                      : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t phy_op                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn30xx;
+	struct cvmx_smix_cmd_cn30xx           cn31xx;
+	struct cvmx_smix_cmd_cn30xx           cn38xx;
+	struct cvmx_smix_cmd_cn30xx           cn38xxp2;
+	struct cvmx_smix_cmd_s                cn50xx;
+	struct cvmx_smix_cmd_s                cn52xx;
+	struct cvmx_smix_cmd_s                cn52xxp1;
+	struct cvmx_smix_cmd_s                cn56xx;
+	struct cvmx_smix_cmd_s                cn56xxp1;
+	struct cvmx_smix_cmd_cn30xx           cn58xx;
+	struct cvmx_smix_cmd_cn30xx           cn58xxp1;
+	struct cvmx_smix_cmd_s                cn63xx;
+	struct cvmx_smix_cmd_s                cn63xxp1;
+};
+typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
+
+/**
+ * cvmx_smi#_en
+ *
+ * SMI_EN = Enable the SMI interface
+ *
+ */
+union cvmx_smix_en
+{
+	uint64_t u64;
+	struct cvmx_smix_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Interface enable
+                                                         0=SMI Interface is down / no transactions, no MDC
+                                                         1=SMI Interface is up */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_smix_en_s                 cn30xx;
+	struct cvmx_smix_en_s                 cn31xx;
+	struct cvmx_smix_en_s                 cn38xx;
+	struct cvmx_smix_en_s                 cn38xxp2;
+	struct cvmx_smix_en_s                 cn50xx;
+	struct cvmx_smix_en_s                 cn52xx;
+	struct cvmx_smix_en_s                 cn52xxp1;
+	struct cvmx_smix_en_s                 cn56xx;
+	struct cvmx_smix_en_s                 cn56xxp1;
+	struct cvmx_smix_en_s                 cn58xx;
+	struct cvmx_smix_en_s                 cn58xxp1;
+	struct cvmx_smix_en_s                 cn63xx;
+	struct cvmx_smix_en_s                 cn63xxp1;
+};
+typedef union cvmx_smix_en cvmx_smix_en_t;
+
+/**
+ * cvmx_smi#_rd_dat
+ *
+ * SMI_RD_DAT = SMI Read Data
+ *
+ *
+ * Notes:
+ * VAL will assert when the read xaction completes.  A read to this register
+ * will clear VAL.  PENDING indicates that an SMI RD transaction is in flight.
+ */
+union cvmx_smix_rd_dat
+{
+	uint64_t u64;
+	struct cvmx_smix_rd_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t pending                      : 1;  /**< Read Xaction Pending */
+	uint64_t val                          : 1;  /**< Read Data Valid */
+	uint64_t dat                          : 16; /**< Read Data */
+#else
+	uint64_t dat                          : 16;
+	uint64_t val                          : 1;
+	uint64_t pending                      : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_smix_rd_dat_s             cn30xx;
+	struct cvmx_smix_rd_dat_s             cn31xx;
+	struct cvmx_smix_rd_dat_s             cn38xx;
+	struct cvmx_smix_rd_dat_s             cn38xxp2;
+	struct cvmx_smix_rd_dat_s             cn50xx;
+	struct cvmx_smix_rd_dat_s             cn52xx;
+	struct cvmx_smix_rd_dat_s             cn52xxp1;
+	struct cvmx_smix_rd_dat_s             cn56xx;
+	struct cvmx_smix_rd_dat_s             cn56xxp1;
+	struct cvmx_smix_rd_dat_s             cn58xx;
+	struct cvmx_smix_rd_dat_s             cn58xxp1;
+	struct cvmx_smix_rd_dat_s             cn63xx;
+	struct cvmx_smix_rd_dat_s             cn63xxp1;
+};
+typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
+
+/**
+ * cvmx_smi#_wr_dat
+ *
+ * SMI_WR_DAT = SMI Write Data
+ *
+ *
+ * Notes:
+ * VAL will assert when the write xaction completes.  A read to this register
+ * will clear VAL.  PENDING indicates that an SMI WR transaction is in flight.
+ */
+union cvmx_smix_wr_dat
+{
+	uint64_t u64;
+	struct cvmx_smix_wr_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t pending                      : 1;  /**< Write Xaction Pending */
+	uint64_t val                          : 1;  /**< Write Data Valid */
+	uint64_t dat                          : 16; /**< Write Data */
+#else
+	uint64_t dat                          : 16;
+	uint64_t val                          : 1;
+	uint64_t pending                      : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_smix_wr_dat_s             cn30xx;
+	struct cvmx_smix_wr_dat_s             cn31xx;
+	struct cvmx_smix_wr_dat_s             cn38xx;
+	struct cvmx_smix_wr_dat_s             cn38xxp2;
+	struct cvmx_smix_wr_dat_s             cn50xx;
+	struct cvmx_smix_wr_dat_s             cn52xx;
+	struct cvmx_smix_wr_dat_s             cn52xxp1;
+	struct cvmx_smix_wr_dat_s             cn56xx;
+	struct cvmx_smix_wr_dat_s             cn56xxp1;
+	struct cvmx_smix_wr_dat_s             cn58xx;
+	struct cvmx_smix_wr_dat_s             cn58xxp1;
+	struct cvmx_smix_wr_dat_s             cn63xx;
+	struct cvmx_smix_wr_dat_s             cn63xxp1;
+};
+typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-spi.c b/sys/contrib/octeon-sdk/cvmx-spi.c
index cbb48a5..6cd7c08 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-spi.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,35 @@
 
 
 
+
 /**
  * @file
  *
  * Support library for the SPI
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
+#include <asm/octeon/cvmx-srxx-defs.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-clock.h>
+#else
 #include "cvmx.h"
-#include "cvmx-mio.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#endif
+#include "cvmx-sysinfo.h"
 #include "cvmx-pko.h"
 #include "cvmx-spi.h"
-#include "cvmx-sysinfo.h"
+#include "cvmx-clock.h"
+#endif
+
 
 #define INVOKE_CB(function_p, args...) \
         do { \
@@ -164,7 +182,9 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
     if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
         return res;
 
+#if CVMX_ENABLE_DEBUG_PRINTS
     cvmx_dprintf ("SPI%d: Restart %s\n", interface, modes[mode]);
+#endif
 
     // Callback to perform SPI4 reset
     INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface,mode);
@@ -186,6 +206,9 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
 
     return res;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_spi_restart_interface);
+#endif
 
 /**
  * Callback to perform SPI4 reset
@@ -207,7 +230,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
     cvmx_stxx_int_msk_t stxx_int_msk;
     cvmx_spxx_trn4_ctl_t spxx_trn4_ctl;
     int index;
-    uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    uint64_t MS = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
 
     /* Disable SPI error events while we run BIST */
     spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
@@ -257,7 +280,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
     spxx_clk_ctl.s.clkdly = 0x10;
     spxx_clk_ctl.s.runbist = 0;
     spxx_clk_ctl.s.statdrv = 0;
-    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */ 
+    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */
     spxx_clk_ctl.s.sndtrn = 0;
     spxx_clk_ctl.s.drptrn = 0;
     spxx_clk_ctl.s.rcvtrn = 0;
@@ -417,7 +440,7 @@ int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
     int                          clock_transitions;
     cvmx_spxx_clk_stat_t         stat;
     uint64_t                     timeout_time;
-    uint64_t                     MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    uint64_t                     MS = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
 
     /* Regardless of operating mode, both Tx and Rx clocks must be present
         for the SPI interface to operate. */
@@ -488,7 +511,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
 {
     cvmx_spxx_trn4_ctl_t         spxx_trn4_ctl;
     cvmx_spxx_clk_stat_t         stat;
-    uint64_t                     MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    uint64_t                     MS = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
     uint64_t                     timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
     int                          rx_training_needed;
 
@@ -499,7 +522,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
     spxx_clk_ctl.s.clkdly = 0x10;
     spxx_clk_ctl.s.runbist = 0;
     spxx_clk_ctl.s.statdrv = 0;
-    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */ 
+    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */
     spxx_clk_ctl.s.sndtrn = 1;
     spxx_clk_ctl.s.drptrn = 1;
     spxx_clk_ctl.s.rcvtrn = 1;
@@ -555,7 +578,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
  */
 int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
 {
-    uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    uint64_t MS = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
     if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
         // SRX0 interface should be good, send calendar data
         cvmx_srxx_com_ctl_t srxx_com_ctl;
diff --git a/sys/contrib/octeon-sdk/cvmx-spi.h b/sys/contrib/octeon-sdk/cvmx-spi.h
index 0da6bec..9a47250 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi.h
+++ b/sys/contrib/octeon-sdk/cvmx-spi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,23 +42,28 @@
 
 
 
+
 /**
  * @file
  *
  * This file contains defines for the SPI interface
 
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
 #ifndef __CVMX_SPI_H__
 #define __CVMX_SPI_H__
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-gmxx-defs.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-spi-defs.h */
 
 typedef enum
 {
diff --git a/sys/contrib/octeon-sdk/cvmx-spi4000.c b/sys/contrib/octeon-sdk/cvmx-spi4000.c
index 7358ff5..0a15fae 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi4000.c
+++ b/sys/contrib/octeon-sdk/cvmx-spi4000.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,25 @@
 
 
 
+
 /**
  * @file
  *
  * Support library for the SPI4000 card
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-twsi.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#else
 #include "cvmx.h"
-#include "cvmx-mio.h"
 #include "cvmx-spi.h"
 #include "cvmx-twsi.h"
+#endif
 
 /* If someone is using an old config, make the SPI4000 act like RGMII for backpressure */
 #ifndef CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE
@@ -116,7 +125,6 @@ static CVMX_SHARED int interface_is_spi4000[2] = {0,0};
 static void __cvmx_spi4000_write(int interface, int address, uint32_t data)
 {
     int status;
-
     cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address);
     cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data);
 
@@ -479,6 +487,9 @@ cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port)
 
     return link;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_spi4000_check_speed);
+#endif
 
 
 /**
diff --git a/sys/contrib/octeon-sdk/cvmx-spinlock.h b/sys/contrib/octeon-sdk/cvmx-spinlock.h
index a0725d6..b87602e 100644
--- a/sys/contrib/octeon-sdk/cvmx-spinlock.h
+++ b/sys/contrib/octeon-sdk/cvmx-spinlock.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Implementation of spinlocks.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx-spx0-defs.h b/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
new file mode 100644
index 0000000..ff5b5a4
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
@@ -0,0 +1,120 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-spx0-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon spx0.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SPX0_TYPEDEFS_H__
+#define __CVMX_SPX0_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+		cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180090000388ull);
+}
+#else
+#define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+		cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180090000380ull);
+}
+#else
+#define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
+#endif
+
+/**
+ * cvmx_spx0_pll_bw_ctl
+ */
+union cvmx_spx0_pll_bw_ctl
+{
+	uint64_t u64;
+	struct cvmx_spx0_pll_bw_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
+#else
+	uint64_t bw_ctl                       : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_spx0_pll_bw_ctl_s         cn38xx;
+	struct cvmx_spx0_pll_bw_ctl_s         cn38xxp2;
+};
+typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
+
+/**
+ * cvmx_spx0_pll_setting
+ */
+union cvmx_spx0_pll_setting
+{
+	uint64_t u64;
+	struct cvmx_spx0_pll_setting_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t setting                      : 17; /**< Core PLL setting */
+#else
+	uint64_t setting                      : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_spx0_pll_setting_s        cn38xx;
+	struct cvmx_spx0_pll_setting_s        cn38xxp2;
+};
+typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-spxx-defs.h b/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
new file mode 100644
index 0000000..890cbf8
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
@@ -0,0 +1,1434 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-spxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon spxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SPXX_TYPEDEFS_H__
+#define __CVMX_SPXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_spx#_bckprs_cnt
+ */
+union cvmx_spxx_bckprs_cnt
+{
+	uint64_t u64;
+	struct cvmx_spxx_bckprs_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Counts the number of core clock cycles in which
+                                                         the SPI-4.2 receiver receives data once the TPA
+                                                         for a particular port has been deasserted. The
+                                                         desired port to watch can be selected with the
+                                                         SPX_TPA_SEL[PRTSEL] field. CNT can be cleared by
+                                                         writing all 1s to it. */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_spxx_bckprs_cnt_s         cn38xx;
+	struct cvmx_spxx_bckprs_cnt_s         cn38xxp2;
+	struct cvmx_spxx_bckprs_cnt_s         cn58xx;
+	struct cvmx_spxx_bckprs_cnt_s         cn58xxp1;
+};
+typedef union cvmx_spxx_bckprs_cnt cvmx_spxx_bckprs_cnt_t;
+
+/**
+ * cvmx_spx#_bist_stat
+ *
+ * Notes:
+ * Bist results encoding
+ * - 0: good (or bist in progress/never run)
+ * - 1: bad
+ */
+union cvmx_spxx_bist_stat
+{
+	uint64_t u64;
+	struct cvmx_spxx_bist_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t stat2                        : 1;  /**< Bist Results/No Repair (Tx calendar table)
+                                                         (spx.stx.cal.calendar) */
+	uint64_t stat1                        : 1;  /**< Bist Results/No Repair (Rx calendar table)
+                                                         (spx.srx.spi4.cal.calendar) */
+	uint64_t stat0                        : 1;  /**< Bist Results/No Repair (Spi4 receive datapath FIFO)
+                                                         (spx.srx.spi4.dat.dpr) */
+#else
+	uint64_t stat0                        : 1;
+	uint64_t stat1                        : 1;
+	uint64_t stat2                        : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_spxx_bist_stat_s          cn38xx;
+	struct cvmx_spxx_bist_stat_s          cn38xxp2;
+	struct cvmx_spxx_bist_stat_s          cn58xx;
+	struct cvmx_spxx_bist_stat_s          cn58xxp1;
+};
+typedef union cvmx_spxx_bist_stat cvmx_spxx_bist_stat_t;
+
+/**
+ * cvmx_spx#_clk_ctl
+ *
+ * Notes:
+ * * SRXDLCK
+ *   When asserted, this bit locks the Spi4 receive DLLs.  This bit also
+ *   acts as the Spi4 receiver reset and must be asserted before the
+ *   training sequences are used to initialize the interface.  This bit
+ *   only applies to the receiver interface.
+ *
+ * * RCVTRN
+ *   Once the SRXDLCK bit is asserted and the DLLs have locked and the
+ *   system has been programmed, software should assert this bit in order
+ *   to start looking for valid training sequence and synchronize the
+ *   interface. This bit only applies to the receiver interface.
+ *
+ * * DRPTRN
+ *   The Spi4 receiver can either convert training packets into NOPs or
+ *   drop them entirely.  Dropping ticks allows the interface to deskew
+ *   periodically if the dclk and eclk ratios are close. This bit only
+ *   applies to the receiver interface.
+ *
+ * * SNDTRN
+ *   When software sets this bit, it indicates that the Spi4 transmit
+ *   interface has been setup and has seen the calendare status.  Once the
+ *   transmitter begins sending training data, the receiving device is free
+ *   to start traversing the calendar table to synch the link.
+ *
+ * * STATRCV
+ *   This bit determines which status clock edge to sample the status
+ *   channel in Spi4 mode.  Since the status channel is in the opposite
+ *   direction to the datapath, the STATRCV actually effects the
+ *   transmitter/TX block.
+ *
+ * * STATDRV
+ *   This bit determines which status clock edge to drive the status
+ *   channel in Spi4 mode.  Since the status channel is in the opposite
+ *   direction to the datapath, the STATDRV actually effects the
+ *   receiver/RX block.
+ *
+ * * RUNBIST
+ *   RUNBIST will beginning BIST/BISR in all the SPX compilied memories.
+ *   These memories are...
+ *
+ *       * spx.srx.spi4.dat.dpr        // FIFO Spi4 to IMX
+ *       * spx.stx.cal.calendar        // Spi4 TX calendar table
+ *       * spx.srx.spi4.cal.calendar   // Spi4 RX calendar table
+ *
+ *   RUNBIST must never be asserted when the interface is enabled.
+ *   Furthmore, setting RUNBIST at any other time is destructive and can
+ *   cause data and configuration corruption.  The entire interface must be
+ *   reconfigured when this bit is set.
+ *
+ * * CLKDLY
+ *   CLKDLY should be kept at its reset value during normal operation.  This
+ *   register controls the SPI4.2 static clock positioning which normally only is
+ *   set to the non-reset value in quarter clocking schemes.  In this mode, the
+ *   delay window is not large enough for slow clock freq, therefore clock and
+ *   data must be statically positioned with CSRs.  By changing the clock position
+ *   relative to the data bits, we give the system a wider window.
+ *
+ * * SEETRN
+ *   In systems in which no training data is sent to N2 or N2 cannot
+ *   correctly sample the training data, software may pulse this bit by
+ *   writing a '1' followed by a '0' in order to correctly set the
+ *   receivers state.  The receive data bus should be idle at this time
+ *   (only NOPs on the bus).  If N2 cannot see at least on training
+ *   sequence, the data bus will not send any data to the core.  The
+ *   interface will hang.
+ */
+union cvmx_spxx_clk_ctl
+{
+	uint64_t u64;
+	struct cvmx_spxx_clk_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t seetrn                       : 1;  /**< Force the Spi4 receive into seeing a traing
+                                                         sequence */
+	uint64_t reserved_12_15               : 4;
+	uint64_t clkdly                       : 5;  /**< Set the spx__clkdly lines to this value to
+                                                         control the delay on the incoming dclk
+                                                         (spx__clkdly) */
+	uint64_t runbist                      : 1;  /**< Write this bit to begin BIST testing in SPX */
+	uint64_t statdrv                      : 1;  /**< Spi4 status channel drive mode
+                                                         - 1: Drive STAT on posedge of SCLK
+                                                         - 0: Drive STAT on negedge of SCLK */
+	uint64_t statrcv                      : 1;  /**< Spi4 status channel sample mode
+                                                         - 1: Sample STAT on posedge of SCLK
+                                                         - 0: Sample STAT on negedge of SCLK */
+	uint64_t sndtrn                       : 1;  /**< Start sending training patterns on the Spi4
+                                                         Tx Interface */
+	uint64_t drptrn                       : 1;  /**< Drop blocks of training packets */
+	uint64_t rcvtrn                       : 1;  /**< Write this bit once the DLL is locked to sync
+                                                         on the training seqeunce */
+	uint64_t srxdlck                      : 1;  /**< Write this bit to lock the Spi4 receive DLL */
+#else
+	uint64_t srxdlck                      : 1;
+	uint64_t rcvtrn                       : 1;
+	uint64_t drptrn                       : 1;
+	uint64_t sndtrn                       : 1;
+	uint64_t statrcv                      : 1;
+	uint64_t statdrv                      : 1;
+	uint64_t runbist                      : 1;
+	uint64_t clkdly                       : 5;
+	uint64_t reserved_12_15               : 4;
+	uint64_t seetrn                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_spxx_clk_ctl_s            cn38xx;
+	struct cvmx_spxx_clk_ctl_s            cn38xxp2;
+	struct cvmx_spxx_clk_ctl_s            cn58xx;
+	struct cvmx_spxx_clk_ctl_s            cn58xxp1;
+};
+typedef union cvmx_spxx_clk_ctl cvmx_spxx_clk_ctl_t;
+
+/**
+ * cvmx_spx#_clk_stat
+ */
+union cvmx_spxx_clk_stat
+{
+	uint64_t u64;
+	struct cvmx_spxx_clk_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_11_63               : 53;
+	uint64_t stxcal                       : 1;  /**< The transistion from Sync to Calendar on status
+                                                         channel */
+	uint64_t reserved_9_9                 : 1;
+	uint64_t srxtrn                       : 1;  /**< Saw a good data training sequence */
+	uint64_t s4clk1                       : 1;  /**< Saw '1' on Spi4 transmit status forward clk input */
+	uint64_t s4clk0                       : 1;  /**< Saw '0' on Spi4 transmit status forward clk input */
+	uint64_t d4clk1                       : 1;  /**< Saw '1' on Spi4 receive data forward clk input */
+	uint64_t d4clk0                       : 1;  /**< Saw '0' on Spi4 receive data forward clk input */
+	uint64_t reserved_0_3                 : 4;
+#else
+	uint64_t reserved_0_3                 : 4;
+	uint64_t d4clk0                       : 1;
+	uint64_t d4clk1                       : 1;
+	uint64_t s4clk0                       : 1;
+	uint64_t s4clk1                       : 1;
+	uint64_t srxtrn                       : 1;
+	uint64_t reserved_9_9                 : 1;
+	uint64_t stxcal                       : 1;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_spxx_clk_stat_s           cn38xx;
+	struct cvmx_spxx_clk_stat_s           cn38xxp2;
+	struct cvmx_spxx_clk_stat_s           cn58xx;
+	struct cvmx_spxx_clk_stat_s           cn58xxp1;
+};
+typedef union cvmx_spxx_clk_stat cvmx_spxx_clk_stat_t;
+
+/**
+ * cvmx_spx#_dbg_deskew_ctl
+ *
+ * Notes:
+ * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
+ * that Spec for more details.
+ *
+ *   The basic idea is to allow software to disable the auto-deskew widgets
+ *   and make any adjustments by hand.  These steps should only be taken
+ *   once the RCVTRN bit is set and before any real traffic is sent on the
+ *   Spi4 bus.  Great care should be taken when messing with these bits as
+ *   improper programmings can cause catestrophic or intermitent problems.
+ *
+ *   The params we have to test are the MUX tap selects and the XCV delay
+ *   tap selects.
+ *
+ *   For the muxes, we can set each tap to a random value and then read
+ *   back the taps.  To write...
+ *
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_CTL[OFFSET]   = mux tap value (2-bits)
+ *    SPXX_DBG_DESKEW_CTL[MUX]      = go bit
+ *
+ *   Notice this can all happen with a single CSR write.  To read, first
+ *   set the bit you to look at with the SPXX_DBG_DESKEW_CTL[BITSEL], then
+ *   simply read SPXX_DBG_DESKEW_STATE[MUXSEL]...
+ *
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_STATE[MUXSEL] = 2-bit value
+ *
+ *   For the xcv delay taps, the CSR controls increment and decrement the
+ *   5-bit count value in the XCV.  This is a saturating counter, so it
+ *   will not wrap when decrementing below zero or incrementing above 31.
+ *
+ *   To write...
+ *
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_CTL[OFFSET]   = tap value increment or decrement amount (5-bits)
+ *    SPXX_DBG_DESKEW_CTL[INC|DEC]  = go bit
+ *
+ *   These values are copied in SPX, so that they can be read back by
+ *   software by a similar mechanism to the MUX selects...
+ *
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_STATE[OFFSET] = 5-bit value
+ *
+ *   In addition, there is a reset bit that sets all the state back to the
+ *   default/starting value of 0x10.
+ *
+ *    SPXX_DBG_DESKEW_CTL[CLRDLY]   = 1
+ *
+ * SINGLE STEP TRAINING MODE (WILMA)
+ *     Debug feature that will enable the user to single-step the debug
+ *     logic to watch initial movement and trends by putting the training
+ *     machine in single step mode.
+ *
+ * * SPX*_DBG_DESKEW_CTL[SSTEP]
+ *        This will put the training control logic into single step mode.  We
+ *        will not deskew in this scenario and will require the TX device to
+ *        send continuous training sequences.
+ *
+ *        It is required that SRX*_COM_CTL[INF_EN] be clear so that suspect
+ *        data does not flow into the chip.
+ *
+ *        Deasserting SPX*_DBG_DESKEW_CTL[SSTEP] will attempt to deskew as per
+ *        the normal definition.  Single step mode is for debug only.  Special
+ *        care must be given to correctly deskew the interface if normal
+ *        operation is desired.
+ *
+ * * SPX*_DBG_DESKEW_CTL[SSTEP_GO]
+ *        Each write of '1' to SSTEP_GO will go through a single training
+ *        iteration and will perform...
+ *
+ *        - DLL update, if SPX*_DBG_DESKEW_CTL[DLLDIS] is clear
+ *        - coarse update, if SPX*_TRN4_CTL[MUX_EN] is set
+ *        - single fine update, if SPX*_TRN4_CTL[MACRO_EN] is set and an edge
+ *       was detected after walked +/- SPX*_TRN4_CTL[MAXDIST] taps.
+ *
+ *        Writes to this register have no effect if the interface is not in
+ *        SSTEP mode (SPX*_DBG_DESKEW_CTL[SSTEP]).
+ *
+ *        The WILMA mode will be cleared at the final state transition, so
+ *        that software can set SPX*_DBG_DESKEW_CTL[SSTEP] and
+ *        SPX*_DBG_DESKEW_CTL[SSTEP_GO] before setting SPX*_CLK_CTL[RCVTRN]
+ *        and the machine will go through the initial iteration and stop -
+ *        waiting for another SPX*_DBG_DESKEW_CTL[SSTEP_GO] or an interface
+ *        enable.
+ *
+ * * SPX*_DBG_DESKEW_CTL[FALL8]
+ *   Determines how many pattern matches are required during training
+ *   operations to fallout of training and begin processing the normal data
+ *   stream.  The default value is 10 pattern matches.  The pattern that is
+ *   used is dependent on the SPX*_DBG_DESKEW_CTL[FALLNOP] CSR which
+ *   determines between non-training packets (the default) and NOPs.
+ *
+ * * SPX*_DBG_DESKEW_CTL[FALLNOP]
+ *   Determines the pattern that is required during training operations to
+ *   fallout of training and begin processing the normal data stream.  The
+ *   default value is to match against non-training data.  Setting this
+ *   bit, changes the behavior to watch for NOPs packet instead.
+ *
+ *   This bit should not be changed dynamically while the link is
+ *   operational.
+ */
+union cvmx_spxx_dbg_deskew_ctl
+{
+	uint64_t u64;
+	struct cvmx_spxx_dbg_deskew_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_30_63               : 34;
+	uint64_t fallnop                      : 1;  /**< Training fallout on NOP matches instead of
+                                                         non-training matches.
+                                                         (spx_csr__spi4_fallout_nop) */
+	uint64_t fall8                        : 1;  /**< Training fallout at 8 pattern matches instead of 10
+                                                         (spx_csr__spi4_fallout_8_match) */
+	uint64_t reserved_26_27               : 2;
+	uint64_t sstep_go                     : 1;  /**< Single Step Training Sequence
+                                                         (spx_csr__spi4_single_step_go) */
+	uint64_t sstep                        : 1;  /**< Single Step Training Mode
+                                                         (spx_csr__spi4_single_step_mode) */
+	uint64_t reserved_22_23               : 2;
+	uint64_t clrdly                       : 1;  /**< Resets the offset control in the XCV
+                                                         (spx_csr__spi4_dll_clr_dly) */
+	uint64_t dec                          : 1;  /**< Decrement the offset by OFFSET for the Spi4
+                                                         bit selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_dec) */
+	uint64_t inc                          : 1;  /**< Increment the offset by OFFSET for the Spi4
+                                                         bit selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_inc) */
+	uint64_t mux                          : 1;  /**< Set the mux select tap for the Spi4 bit
+                                                         selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_mux) */
+	uint64_t offset                       : 5;  /**< Adds or subtracts (Based on INC or DEC) the
+                                                         offset to Spi4 bit BITSEL.
+                                                         (spx_csr__spi4_dbg_trn_offset) */
+	uint64_t bitsel                       : 5;  /**< Select the Spi4 CTL or DAT bit
+                                                         15-0 : Spi4 DAT[15:0]
+                                                         16   : Spi4 CTL
+                                                         - 31-17: Invalid
+                                                         (spx_csr__spi4_dbg_trn_bitsel) */
+	uint64_t offdly                       : 6;  /**< Set the spx__offset lines to this value when
+                                                         not in macro sequence
+                                                         (spx_csr__spi4_mac_offdly) */
+	uint64_t dllfrc                       : 1;  /**< Force the Spi4 RX DLL to update
+                                                         (spx_csr__spi4_dll_force) */
+	uint64_t dlldis                       : 1;  /**< Disable sending the update signal to the Spi4
+                                                         RX DLL when set
+                                                         (spx_csr__spi4_dll_trn_en) */
+#else
+	uint64_t dlldis                       : 1;
+	uint64_t dllfrc                       : 1;
+	uint64_t offdly                       : 6;
+	uint64_t bitsel                       : 5;
+	uint64_t offset                       : 5;
+	uint64_t mux                          : 1;
+	uint64_t inc                          : 1;
+	uint64_t dec                          : 1;
+	uint64_t clrdly                       : 1;
+	uint64_t reserved_22_23               : 2;
+	uint64_t sstep                        : 1;
+	uint64_t sstep_go                     : 1;
+	uint64_t reserved_26_27               : 2;
+	uint64_t fall8                        : 1;
+	uint64_t fallnop                      : 1;
+	uint64_t reserved_30_63               : 34;
+#endif
+	} s;
+	struct cvmx_spxx_dbg_deskew_ctl_s     cn38xx;
+	struct cvmx_spxx_dbg_deskew_ctl_s     cn38xxp2;
+	struct cvmx_spxx_dbg_deskew_ctl_s     cn58xx;
+	struct cvmx_spxx_dbg_deskew_ctl_s     cn58xxp1;
+};
+typedef union cvmx_spxx_dbg_deskew_ctl cvmx_spxx_dbg_deskew_ctl_t;
+
+/**
+ * cvmx_spx#_dbg_deskew_state
+ *
+ * Notes:
+ * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
+ * that Spec for more details.
+ */
+union cvmx_spxx_dbg_deskew_state
+{
+	uint64_t u64;
+	struct cvmx_spxx_dbg_deskew_state_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t testres                      : 1;  /**< Training Test Mode Result
+                                                         (srx_spi4__test_mode_result) */
+	uint64_t unxterm                      : 1;  /**< Unexpected training terminiation
+                                                         (srx_spi4__top_unxexp_trn_term) */
+	uint64_t muxsel                       : 2;  /**< The mux select value of the bit selected by
+                                                         SPX_DBG_DESKEW_CTL[BITSEL]
+                                                         (srx_spi4__trn_mux_sel) */
+	uint64_t offset                       : 5;  /**< The counter value of the bit selected by
+                                                         SPX_DBG_DESKEW_CTL[BITSEL]
+                                                         (srx_spi4__xcv_tap_select) */
+#else
+	uint64_t offset                       : 5;
+	uint64_t muxsel                       : 2;
+	uint64_t unxterm                      : 1;
+	uint64_t testres                      : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_spxx_dbg_deskew_state_s   cn38xx;
+	struct cvmx_spxx_dbg_deskew_state_s   cn38xxp2;
+	struct cvmx_spxx_dbg_deskew_state_s   cn58xx;
+	struct cvmx_spxx_dbg_deskew_state_s   cn58xxp1;
+};
+typedef union cvmx_spxx_dbg_deskew_state cvmx_spxx_dbg_deskew_state_t;
+
+/**
+ * cvmx_spx#_drv_ctl
+ *
+ * Notes:
+ * These bits all come from Duke - he will provide documentation and
+ * explanation.  I'll just butcher it.
+ */
+union cvmx_spxx_drv_ctl
+{
+	uint64_t u64;
+	struct cvmx_spxx_drv_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_0_63                : 64;
+#else
+	uint64_t reserved_0_63                : 64;
+#endif
+	} s;
+	struct cvmx_spxx_drv_ctl_cn38xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t stx4ncmp                     : 4;  /**< Duke (spx__spi4_tx_nctl_comp) */
+	uint64_t stx4pcmp                     : 4;  /**< Duke (spx__spi4_tx_pctl_comp) */
+	uint64_t srx4cmp                      : 8;  /**< Duke (spx__spi4_rx_rctl_comp) */
+#else
+	uint64_t srx4cmp                      : 8;
+	uint64_t stx4pcmp                     : 4;
+	uint64_t stx4ncmp                     : 4;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn38xx;
+	struct cvmx_spxx_drv_ctl_cn38xx       cn38xxp2;
+	struct cvmx_spxx_drv_ctl_cn58xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t stx4ncmp                     : 4;  /**< Duke (spx__spi4_tx_nctl_comp) */
+	uint64_t stx4pcmp                     : 4;  /**< Duke (spx__spi4_tx_pctl_comp) */
+	uint64_t reserved_10_15               : 6;
+	uint64_t srx4cmp                      : 10; /**< Duke (spx__spi4_rx_rctl_comp) */
+#else
+	uint64_t srx4cmp                      : 10;
+	uint64_t reserved_10_15               : 6;
+	uint64_t stx4pcmp                     : 4;
+	uint64_t stx4ncmp                     : 4;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} cn58xx;
+	struct cvmx_spxx_drv_ctl_cn58xx       cn58xxp1;
+};
+typedef union cvmx_spxx_drv_ctl cvmx_spxx_drv_ctl_t;
+
+/**
+ * cvmx_spx#_err_ctl
+ *
+ * SPX_ERR_CTL - Spi error control register
+ *
+ *
+ * Notes:
+ * * DIPPAY, DIPCLS, PRTNXA
+ * These bits control whether or not the packet's ERR bit is set when any of
+ * the these error is detected.  If the corresponding error's bit is clear,
+ * the packet ERR will be set.  If the error bit is set, the SPX will simply
+ * pass through the ERR bit without modifying it in anyway - the error bit
+ * may or may not have been set by the transmitter device.
+ */
+union cvmx_spxx_err_ctl
+{
+	uint64_t u64;
+	struct cvmx_spxx_err_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t prtnxa                       : 1;  /**< Spi4 - set the ERR bit on packets in which the
+                                                         port is out-of-range */
+	uint64_t dipcls                       : 1;  /**< Spi4 DIPERR on closing control words cause the
+                                                         ERR bit to be set */
+	uint64_t dippay                       : 1;  /**< Spi4 DIPERR on payload control words cause the
+                                                         ERR bit to be set */
+	uint64_t reserved_4_5                 : 2;
+	uint64_t errcnt                       : 4;  /**< Number of Dip4 errors before bringing down the
+                                                         interface */
+#else
+	uint64_t errcnt                       : 4;
+	uint64_t reserved_4_5                 : 2;
+	uint64_t dippay                       : 1;
+	uint64_t dipcls                       : 1;
+	uint64_t prtnxa                       : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_spxx_err_ctl_s            cn38xx;
+	struct cvmx_spxx_err_ctl_s            cn38xxp2;
+	struct cvmx_spxx_err_ctl_s            cn58xx;
+	struct cvmx_spxx_err_ctl_s            cn58xxp1;
+};
+typedef union cvmx_spxx_err_ctl cvmx_spxx_err_ctl_t;
+
+/**
+ * cvmx_spx#_int_dat
+ *
+ * SPX_INT_DAT - Interrupt Data Register
+ *
+ *
+ * Notes:
+ * Note: The SPX_INT_DAT[MUL] bit is set when multiple errors have been
+ * detected that would set any of the data fields: PRT, RSVOP, and CALBNK.
+ *
+ * The following errors will cause MUL to assert for PRT conflicts.
+ * - ABNORM
+ * - APERR
+ * - DPERR
+ *
+ * The following errors will cause MUL to assert for RSVOP conflicts.
+ * - RSVERR
+ *
+ * The following errors will cause MUL to assert for CALBNK conflicts.
+ * - CALERR
+ *
+ * The following errors will cause MUL to assert if multiple interrupts are
+ * asserted.
+ * - TPAOVR
+ *
+ * The MUL bit will be cleared once all outstanding errors have been
+ * cleared by software (not just MUL errors - all errors).
+ */
+union cvmx_spxx_int_dat
+{
+	uint64_t u64;
+	struct cvmx_spxx_int_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t mul                          : 1;  /**< Multiple errors have occured */
+	uint64_t reserved_14_30               : 17;
+	uint64_t calbnk                       : 2;  /**< Spi4 Calendar table parity error bank */
+	uint64_t rsvop                        : 4;  /**< Spi4 reserved control word */
+	uint64_t prt                          : 8;  /**< Port associated with error */
+#else
+	uint64_t prt                          : 8;
+	uint64_t rsvop                        : 4;
+	uint64_t calbnk                       : 2;
+	uint64_t reserved_14_30               : 17;
+	uint64_t mul                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_spxx_int_dat_s            cn38xx;
+	struct cvmx_spxx_int_dat_s            cn38xxp2;
+	struct cvmx_spxx_int_dat_s            cn58xx;
+	struct cvmx_spxx_int_dat_s            cn58xxp1;
+};
+typedef union cvmx_spxx_int_dat cvmx_spxx_int_dat_t;
+
+/**
+ * cvmx_spx#_int_msk
+ *
+ * SPX_INT_MSK - Interrupt Mask Register
+ *
+ */
+union cvmx_spxx_int_msk
+{
+	uint64_t u64;
+	struct cvmx_spxx_int_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t calerr                       : 1;  /**< Spi4 Calendar table parity error */
+	uint64_t syncerr                      : 1;  /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+	uint64_t diperr                       : 1;  /**< Spi4 DIP4 error */
+	uint64_t tpaovr                       : 1;  /**< Selected port has hit TPA overflow */
+	uint64_t rsverr                       : 1;  /**< Spi4 reserved control word detected */
+	uint64_t drwnng                       : 1;  /**< Spi4 receive FIFO drowning/overflow */
+	uint64_t clserr                       : 1;  /**< Spi4 packet closed on non-16B alignment without EOP */
+	uint64_t spiovr                       : 1;  /**< Spi async FIFO overflow (Spi3 or Spi4) */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t abnorm                       : 1;  /**< Abnormal packet termination (ERR bit) */
+	uint64_t prtnxa                       : 1;  /**< Port out of range */
+#else
+	uint64_t prtnxa                       : 1;
+	uint64_t abnorm                       : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t spiovr                       : 1;
+	uint64_t clserr                       : 1;
+	uint64_t drwnng                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t tpaovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t syncerr                      : 1;
+	uint64_t calerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_spxx_int_msk_s            cn38xx;
+	struct cvmx_spxx_int_msk_s            cn38xxp2;
+	struct cvmx_spxx_int_msk_s            cn58xx;
+	struct cvmx_spxx_int_msk_s            cn58xxp1;
+};
+typedef union cvmx_spxx_int_msk cvmx_spxx_int_msk_t;
+
+/**
+ * cvmx_spx#_int_reg
+ *
+ * SPX_INT_REG - Interrupt Register
+ *
+ *
+ * Notes:
+ * * PRTNXA
+ *   This error indicates that the port on the Spi bus was not a valid port
+ *   for the system.  Spi4 accesses occur on payload control bit-times. The
+ *   SRX can be configured with the exact number of ports available (by
+ *   SRX_COM_CTL[PRTS] register).  Any Spi access to anthing outside the range
+ *   of 0 .. (SRX_COM_CTL[PRTS] - 1) is considered an error.  The offending
+ *   port is logged in SPX_INT_DAT[PRT] if there are no pending interrupts in
+ *   SPX_INT_REG that require SPX_INT_DAT[PRT].
+ *
+ *   SRX will not drop the packet with the bogus port address.  Instead, the
+ *   port will be mapped into the supported port range.  The remapped address
+ *   in simply...
+ *
+ *            Address = [ interfaceId, ADR[3:0] ]
+ *
+ *   If the SPX detects that a PRTNXA error has occured, the packet will
+ *   have its ERR bit set (or'ed in with the ERR bit from the transmitter)
+ *   if the SPX_ERR_CTL[PRTNXA] bit is clear.
+ *
+ *   In Spi4 mode, SPX will generate an interrupt for every 8B data burst
+ *   associated with the invalid address.  The SPX_INT_DAT[MUL] bit will never
+ *   be set.
+ *
+ * * ABNORM
+ *   This bit simply indicates that a given packet had abnormal terminiation.
+ *   In Spi4 mode, this means that packet completed with an EOPS[1:0] code of
+ *   2'b01.  This error can also be thought of as the application specific
+ *   error (as mentioned in the Spi4 spec).  The offending port is logged in
+ *   SPX_INT_DAT[PRT] if there are no pending interrupts in SPX_INT_REG that
+ *   require SPX_INT_DAT[PRT].
+ *
+ *   The ABNORM error is only raised when the ERR bit that comes from the
+ *   Spi interface is set.  It will never assert if any internal condition
+ *   causes the ERR bit to assert (e.g. PRTNXA or DPERR).
+ *
+ * * SPIOVR
+ *   This error indicates that the FIFOs that manage the async crossing from
+ *   the Spi clocks to the core clock domains have overflowed.  This is a
+ *   fatal error and can cause much data/control corruption since ticks will
+ *   be dropped and reordered.  This is purely a function of clock ratios and
+ *   correct system ratios should make this an impossible condition.
+ *
+ * * CLSERR
+ *   This is a Spi4 error that indicates that a given data transfer burst
+ *   that did not terminate with an EOP, did not end with the 16B alignment
+ *   as per the Spi4 spec.  The offending port cannot be logged since the
+ *   block does not know the streamm terminated until the port switches.
+ *   At that time, that packet has already been pushed down the pipe.
+ *
+ *   The CLSERR bit does not actually check the Spi4 burst - just how data
+ *   is accumulated for the downstream logic.  Bursts that are separted by
+ *   idles or training will still be merged into accumulated transfers and
+ *   will not fire the CLSERR condition.  The checker is really checking
+ *   non-8B aligned, non-EOP data ticks that are sent downstream.  These
+ *   ticks are what will really mess up the core.
+ *
+ *   This is an expensive fix, so we'll probably let it ride.  We never
+ *   claim to check Spi4 protocol anyway.
+ *
+ * * DRWNNG
+ *   This error indicates that the Spi4 FIFO that services the GMX has
+ *   overflowed.  Like the SPIOVR error condition, correct system ratios
+ *   should make this an impossible condition.
+ *
+ * * RSVERR
+ *   This Spi4 error indicates that the Spi4 receiver has seen a reserve
+ *   control packet.  A reserve control packet is an invalid combiniation
+ *   of bits on DAT[15:12].  Basically this is DAT[15] == 1'b0 and DAT[12]
+ *   == 1'b1 (an SOP without a payload command).  The RSVERR indicates an
+ *   error has occured and SPX_INT_DAT[RSVOP] holds the first reserved
+ *   opcode and will be set if there are no pending interrupts in
+ *   SPX_INT_REG that require SPX_INT_DAT[RSVOP].
+ *
+ * * TPAOVR
+ *   This bit indicates that the TPA Watcher has flagged an event.  See the
+ *   TPA Watcher for a more detailed discussion.
+ *
+ * * DIPERR
+ *   This bit indicates that the Spi4 receiver has encountered a DIP4
+ *   miscompare on the datapath.  A DIPERR can occur in an IDLE or a
+ *   control word that frames a data burst.  If the DIPERR occurs on a
+ *   framing word there are three cases.
+ *
+ *   1) DIPERR occurs at the end of a data burst.  The previous packet is
+ *      marked with the ERR bit to be processed later if
+ *      SPX_ERR_CTL[DIPCLS] is clear.
+ *   2) DIPERR occurs on a payload word.  The subsequent packet is marked
+ *      with the ERR bit to be processed later if SPX_ERR_CTL[DIPPAY] is
+ *      clear.
+ *   3) DIPERR occurs on a control word that closes on packet and is a
+ *      payload for another packet.  In this case, both packets will have
+ *      their ERR bit marked depending on the respective values of
+ *      SPX_ERR_CTL[DIPCLS] and SPX_ERR_CTL[DIPPAY] as discussed above.
+ *
+ * * SYNCERR
+ *   This bit indicates that the Spi4 receiver has encountered
+ *   SPX_ERR_CTL[ERRCNT] consecutive Spi4 DIP4 errors and the interface
+ *   should be synched.
+ *
+ * * CALERR
+ *   This bit indicates that the Spi4 calendar table encountered a parity
+ *   error.  This error bit is associated with the calendar table on the RX
+ *   interface - the interface that receives the Spi databus.  Parity errors
+ *   can occur during normal operation when the calendar table is constantly
+ *   being read for the port information, or during initialization time, when
+ *   the user has access.  Since the calendar table is split into two banks,
+ *   SPX_INT_DAT[CALBNK] indicates which banks have taken a parity error.
+ *   CALBNK[1] indicates the error occured in the upper bank, while CALBNK[0]
+ *   indicates that the error occured in the lower bank.  SPX_INT_DAT[CALBNK]
+ *   will be set if there are no pending interrupts in SPX_INT_REG that
+ *   require SPX_INT_DAT[CALBNK].
+ *
+ * * SPF
+ *   This bit indicates that a Spi fatal error has occurred.  A fatal error
+ *   is defined as any error condition for which the corresponding
+ *   SPX_INT_SYNC bit is set.  Therefore, conservative systems can halt the
+ *   interface on any error condition although this is not strictly
+ *   necessary.  Some error are much more fatal in nature than others.
+ *
+ *   PRTNXA, SPIOVR, CLSERR, DRWNNG, DIPERR, CALERR, and SYNCERR are examples
+ *   of fatal error for different reasons - usually because multiple port
+ *   streams could be effected.  ABNORM, RSVERR, and TPAOVR are conditions
+ *   that are contained to a single packet which allows the interface to drop
+ *   a single packet and remain up and stable.
+ */
+union cvmx_spxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_spxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t spf                          : 1;  /**< Spi interface down */
+	uint64_t reserved_12_30               : 19;
+	uint64_t calerr                       : 1;  /**< Spi4 Calendar table parity error */
+	uint64_t syncerr                      : 1;  /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+	uint64_t diperr                       : 1;  /**< Spi4 DIP4 error */
+	uint64_t tpaovr                       : 1;  /**< Selected port has hit TPA overflow */
+	uint64_t rsverr                       : 1;  /**< Spi4 reserved control word detected */
+	uint64_t drwnng                       : 1;  /**< Spi4 receive FIFO drowning/overflow */
+	uint64_t clserr                       : 1;  /**< Spi4 packet closed on non-16B alignment without EOP */
+	uint64_t spiovr                       : 1;  /**< Spi async FIFO overflow */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t abnorm                       : 1;  /**< Abnormal packet termination (ERR bit) */
+	uint64_t prtnxa                       : 1;  /**< Port out of range */
+#else
+	uint64_t prtnxa                       : 1;
+	uint64_t abnorm                       : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t spiovr                       : 1;
+	uint64_t clserr                       : 1;
+	uint64_t drwnng                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t tpaovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t syncerr                      : 1;
+	uint64_t calerr                       : 1;
+	uint64_t reserved_12_30               : 19;
+	uint64_t spf                          : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_spxx_int_reg_s            cn38xx;
+	struct cvmx_spxx_int_reg_s            cn38xxp2;
+	struct cvmx_spxx_int_reg_s            cn58xx;
+	struct cvmx_spxx_int_reg_s            cn58xxp1;
+};
+typedef union cvmx_spxx_int_reg cvmx_spxx_int_reg_t;
+
+/**
+ * cvmx_spx#_int_sync
+ *
+ * SPX_INT_SYNC - Interrupt Sync Register
+ *
+ *
+ * Notes:
+ * This mask set indicates which exception condition should cause the
+ * SPX_INT_REG[SPF] bit to assert
+ *
+ * It is recommended that software set the PRTNXA, SPIOVR, CLSERR, DRWNNG,
+ * DIPERR, CALERR, and SYNCERR errors as synchronization events.  Software is
+ * free to synchronize the bus on other conditions, but this is the minimum
+ * recommended set.
+ */
+union cvmx_spxx_int_sync
+{
+	uint64_t u64;
+	struct cvmx_spxx_int_sync_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_12_63               : 52;
+	uint64_t calerr                       : 1;  /**< Spi4 Calendar table parity error */
+	uint64_t syncerr                      : 1;  /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+	uint64_t diperr                       : 1;  /**< Spi4 DIP4 error */
+	uint64_t tpaovr                       : 1;  /**< Selected port has hit TPA overflow */
+	uint64_t rsverr                       : 1;  /**< Spi4 reserved control word detected */
+	uint64_t drwnng                       : 1;  /**< Spi4 receive FIFO drowning/overflow */
+	uint64_t clserr                       : 1;  /**< Spi4 packet closed on non-16B alignment without EOP */
+	uint64_t spiovr                       : 1;  /**< Spi async FIFO overflow (Spi3 or Spi4) */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t abnorm                       : 1;  /**< Abnormal packet termination (ERR bit) */
+	uint64_t prtnxa                       : 1;  /**< Port out of range */
+#else
+	uint64_t prtnxa                       : 1;
+	uint64_t abnorm                       : 1;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t spiovr                       : 1;
+	uint64_t clserr                       : 1;
+	uint64_t drwnng                       : 1;
+	uint64_t rsverr                       : 1;
+	uint64_t tpaovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t syncerr                      : 1;
+	uint64_t calerr                       : 1;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_spxx_int_sync_s           cn38xx;
+	struct cvmx_spxx_int_sync_s           cn38xxp2;
+	struct cvmx_spxx_int_sync_s           cn58xx;
+	struct cvmx_spxx_int_sync_s           cn58xxp1;
+};
+typedef union cvmx_spxx_int_sync cvmx_spxx_int_sync_t;
+
+/**
+ * cvmx_spx#_tpa_acc
+ *
+ * SPX_TPA_ACC - TPA watcher byte accumulator
+ *
+ *
+ * Notes:
+ * This field allows the user to access the TPA watcher accumulator counter.
+ * This register reflects the number of bytes sent to IMX once the port
+ * specified by SPX_TPA_SEL[PRTSEL] has lost its TPA.  The SPX_INT_REG[TPAOVR]
+ * bit is asserted when CNT >= SPX_TPA_MAX[MAX].  The CNT will continue to
+ * increment until the TPA for the port is asserted.  At that point the CNT
+ * value is frozen until software clears the interrupt bit.
+ */
+union cvmx_spxx_tpa_acc
+{
+	uint64_t u64;
+	struct cvmx_spxx_tpa_acc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< TPA watcher accumulate count */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_spxx_tpa_acc_s            cn38xx;
+	struct cvmx_spxx_tpa_acc_s            cn38xxp2;
+	struct cvmx_spxx_tpa_acc_s            cn58xx;
+	struct cvmx_spxx_tpa_acc_s            cn58xxp1;
+};
+typedef union cvmx_spxx_tpa_acc cvmx_spxx_tpa_acc_t;
+
+/**
+ * cvmx_spx#_tpa_max
+ *
+ * SPX_TPA_MAX - TPA watcher assertion threshold
+ *
+ *
+ * Notes:
+ * The TPA watcher has the ability to notify the system with an interrupt when
+ * too much data has been received on loss of TPA.  The user sets the
+ * SPX_TPA_MAX[MAX] register and when the watcher has accumulated that many
+ * ticks, then the interrupt is conditionally raised (based on interrupt mask
+ * bits).  This feature will be disabled if the programmed count is zero.
+ */
+union cvmx_spxx_tpa_max
+{
+	uint64_t u64;
+	struct cvmx_spxx_tpa_max_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t max                          : 32; /**< TPA watcher TPA threshold */
+#else
+	uint64_t max                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_spxx_tpa_max_s            cn38xx;
+	struct cvmx_spxx_tpa_max_s            cn38xxp2;
+	struct cvmx_spxx_tpa_max_s            cn58xx;
+	struct cvmx_spxx_tpa_max_s            cn58xxp1;
+};
+typedef union cvmx_spxx_tpa_max cvmx_spxx_tpa_max_t;
+
+/**
+ * cvmx_spx#_tpa_sel
+ *
+ * SPX_TPA_SEL - TPA watcher port selector
+ *
+ *
+ * Notes:
+ * The TPA Watcher is primarily a debug vehicle used to help initial bringup
+ * of a system.  The TPA watcher counts bytes that roll in from the Spi
+ * interface.  The user programs the Spi port to watch using
+ * SPX_TPA_SEL[PRTSEL].  Once the TPA is deasserted for that port, the watcher
+ * begins to count the data ticks that have been delivered to the inbound
+ * datapath (and eventually to the IOB).  The result is that we can derive
+ * turn-around times of the other device by watching how much data was sent
+ * after a loss of TPA through the SPX_TPA_ACC[CNT] register.  An optional
+ * interrupt may be raised as well.  See SPX_TPA_MAX for further information.
+ *
+ * TPA's can be deasserted for a number of reasons...
+ *
+ * 1) IPD indicates backpressure
+ * 2) The GMX inbound FIFO is filling up and should BP
+ * 3) User has out an override on the TPA wires
+ */
+union cvmx_spxx_tpa_sel
+{
+	uint64_t u64;
+	struct cvmx_spxx_tpa_sel_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t prtsel                       : 4;  /**< TPA watcher port select */
+#else
+	uint64_t prtsel                       : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_spxx_tpa_sel_s            cn38xx;
+	struct cvmx_spxx_tpa_sel_s            cn38xxp2;
+	struct cvmx_spxx_tpa_sel_s            cn58xx;
+	struct cvmx_spxx_tpa_sel_s            cn58xxp1;
+};
+typedef union cvmx_spxx_tpa_sel cvmx_spxx_tpa_sel_t;
+
+/**
+ * cvmx_spx#_trn4_ctl
+ *
+ * Notes:
+ * These bits are controls for the Spi4 RX bit deskew logic.  See that Spec
+ * for further details.
+ *
+ * * BOOT_BIT
+ *   On the initial training synchronization sequence, the hardware has the
+ *   BOOT_BIT set which means that it will continueously perform macro
+ *   operations.  Once the BOOT_BIT is cleared, the macro machine will finish
+ *   the macro operation is working on and then return to the idle state.
+ *   Subsequent training sequences will only go through a single macro
+ *   operation in order to do slight deskews.
+ *
+ * * JITTER
+ *   Minimum value is 1.  This parameter must be set for Spi4 mode using
+ *   auto-bit deskew.  Regardless of the original intent, this field must be
+ *   set non-zero for deskew to function correctly.
+ *
+ *   The thought is the JITTER range is no longer required since the macro
+ *   machine was enhanced to understand about edge direction.  Originally
+ *   these bits were intended to compensate for clock jitter.
+ *
+ *   dly:    this is the intrinsic delay of each delay element
+ *              tap currently, it is 70ps-110ps.
+ *   jitter: amount of jitter we expect in the system (~200ps)
+ *   j:      number of taps to account for jitter
+ *
+ *   j = ((jitter / dly) + 1)
+ *
+ * * TRNTEST
+ *   This mode is used to test systems to make sure that the bit deskew
+ *   parameters have been correctly setup.  After configuration, software can
+ *   set the TRNTEST mode bit.  This should be done before SRX_COM_CTL[ST_EN]
+ *   is set such that we can be sure that the TX device is simply sending
+ *   continuous training patterns.
+ *
+ *   The test mode samples every incoming bit-time and makes sure that it is
+ *   either a training control or a training data packet.  If any other data
+ *   is observed, then SPX_DBG_DESKEW_STATE[TESTRES] will assert signaling a
+ *   test failure.
+ *
+ *   Software must clear TRNTEST before training is terminated.
+ *
+ * * Example Spi4 RX init flow...
+ *
+ * 1) set the CLKDLY lines (SPXX_CLK_CTL[CLKDLY])
+ *    - these bits must be set before the DLL can successfully lock
+ *
+ * 2) set the SRXDLCK (SPXX_CLK_CTL[SRXDLCK])
+ *    - this is the DLL lock bit which also acts as a block reset
+ *
+ * 3) wait for the DLLs lock
+ *
+ * 4) set any desired fields in SPXX_DBG_DESKEW_CTL
+ *    - This register has only one field that most users will care about.
+ *      When set, DLLDIS will disable sending update pulses to the Spi4 RX
+ *      DLLs.  This pulse allows the DLL to adjust to clock variations over
+ *      time.  In general, it is desired behavior.
+ *
+ * 5) set fields in SPXX_TRN4_CTL
+ *    - These fields deal with the MUX training sequence
+ *      * MUX_EN
+ *        This is the enable bit for the mux select.  The MUX select will
+ *        run in the training sequence between the DLL and the Macro
+ *        sequence when enabled.  Once the MUX selects are selected, the
+ *        entire macro sequence must be rerun.  The expectation is that
+ *        this is only run at boot time and this is bit cleared at/around
+ *        step \#8.
+ *    - These fields deal with the Macro training sequence
+ *      * MACRO_EN
+ *        This is the enable bit for the macro sequence.  Macro sequences
+ *        will run after the DLL and MUX training sequences.  Each macro
+ *        sequence can move the offset by one value.
+ *      * MAXDIST
+ *        This is how far we will search for an edge.  Example...
+ *
+ *           dly:    this is the intrinsic delay of each delay element
+ *                   tap currently, it is 70ps-110ps.
+ *           U:      bit time period in time units.
+ *
+ *           MAXDIST = MIN(16, ((bit_time / 2) / dly)
+ *
+ *           Each MAXDIST iteration consists of an edge detect in the early
+ *           and late (+/-) directions in an attempt to center the data.  This
+ *           requires two training transistions, the control/data and
+ *           data/control transistions which comprise a training sequence.
+ *           Therefore, the number of training sequences required for a single
+ *           macro operation is simply MAXDIST.
+ *
+ * 6) set the RCVTRN go bit (SPXX_CLK_CTL[RCVTRN])
+ *    - this bit synchs on the first valid complete training cycle and
+ *      starts to process the training packets
+ *
+ * 6b) This is where software could manually set the controls as opposed to
+ *     letting the hardware do it.  See the SPXX_DBG_DESKEW_CTL register
+ *        description for more detail.
+ *
+ * 7) the TX device must continue to send training packets for the initial
+ *    time period.
+ *    - this can be determined by...
+ *
+ *      DLL: one training sequence for the DLL adjustment (regardless of enable/disable)
+ *      MUX: one training sequence for the Flop MUX taps (regardless of enable/disable)
+ *      INIT_SEQUENCES: max number of taps that we must move
+ *
+ *         INIT_SEQUENCES = MIN(16, ((bit_time / 2) / dly))
+ *
+ *         INIT_TRN = DLL + MUX + ROUNDUP((INIT_SEQUENCES * (MAXDIST + 2)))
+ *
+ *
+ *    - software can either wait a fixed amount of time based on the clock
+ *      frequencies or poll the SPXX_CLK_STAT[SRXTRN] register.  Each
+ *      assertion of SRXTRN means that at least one training sequence has
+ *      been received.  Software can poll, clear, and repeat on this bit to
+ *      eventually count all required transistions.
+ *
+ *      int cnt = 0;
+ *      while (cnt < INIT_TRN) [
+ *             if (SPXX_CLK_STAT[SRXTRN]) [
+ *                cnt++;
+ *                SPXX_CLK_STAT[SRXTRN] = 0;
+ *             ]
+ *      ]
+ *
+ *   - subsequent training sequences will normally move the taps only
+ *     one position, so the ALPHA equation becomes...
+ *
+ *     MAC   = (MAXDIST == 0) ? 1 : ROUNDUP((1 * (MAXDIST + 2))) + 1
+ *
+ *        ALPHA = DLL + MUX + MAC
+ *
+ *     ergo, MAXDIST simplifies to...
+ *
+ *        ALPHA = (MAXDIST == 0) ? 3 : MAXDIST + 5
+ *
+ *        DLL and MUX and MAC will always require at least a training sequence
+ *        each - even if disabled.  If the macro sequence is enabled, an
+ *        additional training sequenece at the end is necessary.  The extra
+ *        sequence allows for all training state to be cleared before resuming
+ *        normal operation.
+ *
+ * 8) after the recevier gets enough training sequences in order to achieve
+ *    deskew lock, set SPXX_TRN4_CTL[CLR_BOOT]
+ *    - this disables the continuous macro sequences and puts into into one
+ *      macro sequnence per training operation
+ *    - optionally, the machine can choose to fall out of training if
+ *      enough NOPs follow the training operation (require at least 32 NOPs
+ *      to follow the training sequence).
+ *
+ *    There must be at least MAXDIST + 3 training sequences after the
+ *    SPXX_TRN4_CTL[CLR_BOOT] is set or sufficient NOPs from the TX device.
+ *
+ * 9) the TX device continues to send training sequences until the RX
+ *    device sends a calendar transistion.  This is controlled by
+ *    SRXX_COM_CTL[ST_EN].  Other restrictions require other Spi parameters
+ *    (e.g. the calendar table) to be setup before this bit can be enabled.
+ *    Once the entire interface is properly programmed, software writes
+ *    SRXX_COM_CTL[INF_EN].  At this point, the Spi4 packets will begin to
+ *    be sent into the N2K core and processed by the chip.
+ */
+union cvmx_spxx_trn4_ctl
+{
+	uint64_t u64;
+	struct cvmx_spxx_trn4_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t trntest                      : 1;  /**< Training Test Mode
+                                                         This bit is only for initial bringup
+                                                         (spx_csr__spi4_trn_test_mode) */
+	uint64_t jitter                       : 3;  /**< Accounts for jitter when the macro sequence is
+                                                         locking.  The value is how many consecutive
+                                                         transititions before declaring en edge.  Minimum
+                                                         value is 1.  This parameter must be set for Spi4
+                                                         mode using auto-bit deskew.
+                                                         (spx_csr__spi4_mac_jitter) */
+	uint64_t clr_boot                     : 1;  /**< Clear the macro boot sequence mode bit
+                                                         (spx_csr__spi4_mac_clr_boot) */
+	uint64_t set_boot                     : 1;  /**< Enable the macro boot sequence mode bit
+                                                         (spx_csr__spi4_mac_set_boot) */
+	uint64_t maxdist                      : 5;  /**< This field defines how far from center the
+                                                         deskew logic will search in a single macro
+                                                          sequence (spx_csr__spi4_mac_iters) */
+	uint64_t macro_en                     : 1;  /**< Allow the macro sequence to center the sample
+                                                         point in the data window through hardware
+                                                         (spx_csr__spi4_mac_trn_en) */
+	uint64_t mux_en                       : 1;  /**< Enable the hardware machine that selects the
+                                                         proper coarse FLOP selects
+                                                         (spx_csr__spi4_mux_trn_en) */
+#else
+	uint64_t mux_en                       : 1;
+	uint64_t macro_en                     : 1;
+	uint64_t maxdist                      : 5;
+	uint64_t set_boot                     : 1;
+	uint64_t clr_boot                     : 1;
+	uint64_t jitter                       : 3;
+	uint64_t trntest                      : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_spxx_trn4_ctl_s           cn38xx;
+	struct cvmx_spxx_trn4_ctl_s           cn38xxp2;
+	struct cvmx_spxx_trn4_ctl_s           cn58xx;
+	struct cvmx_spxx_trn4_ctl_s           cn58xxp1;
+};
+typedef union cvmx_spxx_trn4_ctl cvmx_spxx_trn4_ctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-srio.c b/sys/contrib/octeon-sdk/cvmx-srio.c
new file mode 100644
index 0000000..f8511c6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-srio.c
@@ -0,0 +1,1239 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+/**
+ * @file
+ *
+ * Interface to SRIO
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-srio.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-atomic.h>
+#ifdef CONFIG_CAVIUM_DECODE_RSL
+#include <asm/octeon/cvmx-error.h>
+#endif
+#include <asm/octeon/cvmx-sriox-defs.h>
+#include <asm/octeon/cvmx-sriomaintx-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-helper.h>
+#else
+#include "cvmx.h"
+#include "cvmx-srio.h"
+#include "cvmx-clock.h"
+#include "cvmx-helper.h"
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+#include "cvmx-atomic.h"
+#include "cvmx-error.h"
+#include "cvmx-helper-errata.h"
+#endif
+#endif
+
+#define CVMX_SRIO_USE_FIFO_FOR_MAINT    1
+#define CVMX_SRIO_CONFIG_TIMEOUT        10000 /* 10ms */
+#define CVMX_SRIO_DOORBELL_TIMEOUT      10000 /* 10ms */
+#define CVMX_SRIO_CONFIG_PRIORITY       0
+#define ULL unsigned long long
+
+typedef union
+{
+    uint64_t    u64;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
+        uint64_t    reserved_49_61  : 13;   /* Must be zero */
+        uint64_t    io              : 1;    /* 1 for IO space access */
+        uint64_t    did             : 5;    /* DID = 3 */
+        uint64_t    subdid          : 3;    /* SubDID = 3-6 */
+        uint64_t    reserved_36_39  : 4;    /* Must be zero */
+        uint64_t    se              : 2;    /* SubDID extender */
+        uint64_t    reserved_32_33  : 2;    /* Must be zero */
+        uint64_t    hopcount        : 8;    /* Hopcount */
+        uint64_t    address         : 24;   /* Mem address */
+#else
+        uint64_t    address         : 24;
+        uint64_t    hopcount        : 8;
+        uint64_t    reserved_32_33  : 2;
+        uint64_t    se              : 2;
+        uint64_t    reserved_36_39  : 4;
+        uint64_t    subdid          : 3;
+        uint64_t    did             : 5;
+        uint64_t    io              : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    upper           : 2;
+#endif
+    } config;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
+        uint64_t    reserved_49_61  : 13;   /* Must be zero */
+        uint64_t    io              : 1;    /* 1 for IO space access */
+        uint64_t    did             : 5;    /* DID = 3 */
+        uint64_t    subdid          : 3;    /* SubDID = 3-6 */
+        uint64_t    reserved_36_39  : 4;    /* Must be zero */
+        uint64_t    se              : 2;    /* SubDID extender */
+        uint64_t    address         : 34;   /* Mem address */
+#else
+        uint64_t    address         : 34;
+        uint64_t    se              : 2;
+        uint64_t    reserved_36_39  : 4;
+        uint64_t    subdid          : 3;
+        uint64_t    did             : 5;
+        uint64_t    io              : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    upper           : 2;
+#endif
+    } mem;
+} cvmx_sli_address_t;
+
+typedef struct
+{
+    cvmx_srio_initialize_flags_t flags;
+    int32_t subidx_ref_count[16];   /* Reference count for SLI_MEM_ACCESS_SUBID[12-27]. Index=X-12 */
+    int32_t s2m_ref_count[16];   /* Reference count for SRIOX_S2M_TYPE[0-15]. */
+} __cvmx_srio_state_t;
+
+static CVMX_SHARED __cvmx_srio_state_t __cvmx_srio_state[2];
+
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * @INTERNAL
+ * Allocate a SRIOX_S2M_TYPEX register for mapping a remote SRIO
+ * device's address range into Octeons SLI address space. Reference
+ * counting is used to allow sharing of duplicate setups. The current
+ * implementation treats reads and writes as paired, but this could be
+ * changed if we have trouble running out of indexes.
+ *
+ * @param srio_port SRIO port device is on
+ * @param s2m       SRIOX_S2M_TYPEX setup required
+ *
+ * @return Index of CSR, or negative on failure
+ */
+static int __cvmx_srio_alloc_s2m(int srio_port, cvmx_sriox_s2m_typex_t s2m)
+{
+    int s2m_index;
+    /* Search through the S2M_TYPE registers looking for an unsed one or one
+        setup the way we need it */
+    for (s2m_index=0; s2m_index<16; s2m_index++)
+    {
+        /* Increment ref count by 2 since we count read and write
+            independently. We might need a more complicated search in the
+            future */
+        int ref_count = cvmx_atomic_fetch_and_add32(&__cvmx_srio_state[srio_port].s2m_ref_count[s2m_index], 2);
+        if (ref_count == 0)
+        {
+            /* Unused location. Write our value */
+            cvmx_write_csr(CVMX_SRIOX_S2M_TYPEX(s2m_index, srio_port), s2m.u64);
+            return s2m_index;
+        }
+        else
+        {
+            /* In use, see if we can use it */
+            if (cvmx_read_csr(CVMX_SRIOX_S2M_TYPEX(s2m_index, srio_port)) == s2m.u64)
+                return s2m_index;
+            else
+                cvmx_atomic_add32(&__cvmx_srio_state[srio_port].s2m_ref_count[s2m_index], -2);
+        }
+    }
+    cvmx_dprintf("SRIO%d: Unable to find free SRIOX_S2M_TYPEX\n", srio_port);
+    return -1;
+}
+
+
+/**
+ * @INTERNAL
+ * Free a handle allocated by __cvmx_srio_alloc_s2m
+ *
+ * @param srio_port SRIO port
+ * @param index     Index to free
+ */
+static void __cvmx_srio_free_s2m(int srio_port, int index)
+{
+    /* Read to force pending transactions to complete */
+    cvmx_read_csr(CVMX_SRIOX_S2M_TYPEX(index, srio_port));
+    cvmx_atomic_add32(&__cvmx_srio_state[srio_port].s2m_ref_count[index], -2);
+}
+
+
+/**
+ * @INTERNAL
+ * Allocate a SLI SubID to map a region of memory. Reference
+ * counting is used to allow sharing of duplicate setups.
+ *
+ * @param subid  SLI_MEM_ACCESS_SUBIDX we need an index for
+ *
+ * @return Index of CSR, or negative on failure
+ */
+static int __cvmx_srio_alloc_subid(cvmx_sli_mem_access_subidx_t subid)
+{
+    int mem_index;
+    /* Search through the mem access subid registers looking for an unsed one
+        or one setup the way we need it. PCIe uses the low indexes, so search
+        backwards */
+    for (mem_index=27; mem_index>=12; mem_index--)
+    {
+        int ref_count = cvmx_atomic_fetch_and_add32(&__cvmx_srio_state[0].subidx_ref_count[mem_index-12], 1);
+        if (ref_count == 0)
+        {
+            /* Unused location. Write our value */
+            cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(mem_index), subid.u64);
+            return mem_index;
+        }
+        else
+        {
+            /* In use, see if we can use it */
+            if (cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(mem_index)) == subid.u64)
+                return mem_index;
+            else
+                cvmx_atomic_add32(&__cvmx_srio_state[0].subidx_ref_count[mem_index-12], -1);
+        }
+    }
+    cvmx_dprintf("SRIO: Unable to find free SLI_MEM_ACCESS_SUBIDX\n");
+    return -1;
+}
+
+
+/**
+ * @INTERNAL
+ * Free a handle allocated by __cvmx_srio_alloc_subid
+ *
+ * @param index  Index to free
+ */
+static void __cvmx_srio_free_subid(int index)
+{
+    /* Read to force pending transactions to complete */
+    cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(index));
+    cvmx_atomic_add32(&__cvmx_srio_state[0].subidx_ref_count[index-12], -1);
+}
+#endif
+
+
+/**
+ * @INTERNAL
+ * Read 32bits from a local port
+ *
+ * @param srio_port SRIO port the device is on
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param result    Result of the read. This will be unmodified on failure.
+ *
+ * @return Zero on success, negative on failure.
+ */
+static int __cvmx_srio_local_read32(int srio_port, uint32_t offset, uint32_t *result)
+{
+    cvmx_sriox_maint_op_t maint_op;
+    cvmx_sriox_maint_rd_data_t maint_rd_data;
+    maint_op.u64 = 0;
+    maint_op.s.op = 0; /* Read */
+    maint_op.s.addr = offset;
+
+    /* Make sure SRIO isn't already busy */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_MAINT_OP(srio_port), cvmx_sriox_maint_op_t, pending, ==, 0, CVMX_SRIO_CONFIG_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Pending bit stuck before config read\n", srio_port);
+        return -1;
+    }
+
+    /* Issue the read to the hardware */
+    cvmx_write_csr(CVMX_SRIOX_MAINT_OP(srio_port), maint_op.u64);
+
+    /* Wait for the hardware to complete the operation */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_MAINT_OP(srio_port), cvmx_sriox_maint_op_t, pending, ==, 0, CVMX_SRIO_CONFIG_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Config read timeout\n", srio_port);
+        return -1;
+    }
+
+    /* Display and error and return if the operation failed to issue */
+    maint_op.u64 = cvmx_read_csr(CVMX_SRIOX_MAINT_OP(srio_port));
+    if (maint_op.s.fail)
+    {
+        cvmx_dprintf("SRIO%d: Config read addressing error (offset=0x%x)\n", srio_port, (unsigned int)offset);
+        return -1;
+    }
+
+    /* Wait for the read data to become valid */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_MAINT_RD_DATA(srio_port), cvmx_sriox_maint_rd_data_t, valid, ==, 1, CVMX_SRIO_CONFIG_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Config read data timeout\n", srio_port);
+        return -1;
+    }
+
+    /* Get the read data */
+    maint_rd_data.u64 = cvmx_read_csr(CVMX_SRIOX_MAINT_RD_DATA(srio_port));
+    *result = maint_rd_data.s.rd_data;
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Write 32bits to a local port
+ * @param srio_port SRIO port the device is on
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param data      Data to write.
+ *
+ * @return Zero on success, negative on failure.
+ */
+static int __cvmx_srio_local_write32(int srio_port, uint32_t offset, uint32_t data)
+{
+    cvmx_sriox_maint_op_t maint_op;
+    maint_op.u64 = 0;
+    maint_op.s.wr_data = data;
+    maint_op.s.op = 1; /* Write */
+    maint_op.s.addr = offset;
+
+    /* Make sure SRIO isn't already busy */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_MAINT_OP(srio_port), cvmx_sriox_maint_op_t, pending, ==, 0, CVMX_SRIO_CONFIG_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Pending bit stuck before config write\n", srio_port);
+        return -1;
+    }
+
+    /* Issue the write to the hardware */
+    cvmx_write_csr(CVMX_SRIOX_MAINT_OP(srio_port), maint_op.u64);
+
+    /* Wait for the hardware to complete the operation */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_MAINT_OP(srio_port), cvmx_sriox_maint_op_t, pending, ==, 0, CVMX_SRIO_CONFIG_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Config write timeout\n", srio_port);
+        return -1;
+    }
+
+    /* Display and error and return if the operation failed to issue */
+    maint_op.u64 = cvmx_read_csr(CVMX_SRIOX_MAINT_OP(srio_port));
+    if (maint_op.s.fail)
+    {
+        cvmx_dprintf("SRIO%d: Config write addressing error (offset=0x%x)\n", srio_port, (unsigned int)offset);
+        return -1;
+    }
+    return 0;
+}
+
+
+/**
+ * Initialize a SRIO port for use.
+ *
+ * @param srio_port SRIO port to initialize
+ * @param flags     Optional flags
+ *
+ * @return Zero on success
+ */
+int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags)
+{
+    cvmx_sriomaintx_port_lt_ctl_t port_lt_ctl;
+    cvmx_sriomaintx_port_rt_ctl_t port_rt_ctl;
+    cvmx_sriomaintx_port_0_ctl_t port_0_ctl;
+    cvmx_sriomaintx_core_enables_t core_enables;
+    cvmx_sriomaintx_port_gen_ctl_t port_gen_ctl;
+    cvmx_sriox_status_reg_t sriox_status_reg;
+    cvmx_mio_rst_ctlx_t mio_rst_ctl;
+    cvmx_sriox_imsg_vport_thr_t sriox_imsg_vport_thr;
+    cvmx_dpi_sli_prtx_cfg_t prt_cfg;
+    cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
+
+    sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
+    if (!sriox_status_reg.s.srio)
+    {
+        cvmx_dprintf("SRIO%d: Initialization called on a port not in SRIO mode\n", srio_port);
+        return -1;
+    }
+
+    __cvmx_srio_state[srio_port].flags = flags;
+
+    /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be
+        programmed */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
+    {
+        if (srio_port)
+        {
+            cvmx_ciu_qlm1_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+        }
+        else
+        {
+            cvmx_ciu_qlm0_t ciu_qlm;
+            ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+            ciu_qlm.s.txbypass = 1;
+            ciu_qlm.s.txdeemph = 5;
+            ciu_qlm.s.txmargin = 0x17;
+            cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+        }
+    }
+
+    mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(srio_port));
+    cvmx_dprintf("SRIO%d: Port in %s mode\n", srio_port,
+        (mio_rst_ctl.s.prtmode) ? "host" : "endpoint");
+
+    /* Bring the port out of reset if necessary */
+    if (srio_port)
+    {
+        cvmx_ciu_soft_prst1_t prst;
+        prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        if (prst.s.soft_prst)
+        {
+            prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST1, prst.u64);
+            cvmx_wait_usec(10000); /* 10ms for new link to stabalize */
+        }
+    }
+    else
+    {
+        cvmx_ciu_soft_prst_t prst;
+        prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        if (prst.s.soft_prst)
+        {
+            prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST, prst.u64);
+            cvmx_wait_usec(10000); /* 10ms for new link to stabalize */
+        }
+    }
+
+    /* Disable the link while we make changes */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), &port_0_ctl.u32))
+        return -1;
+    port_0_ctl.s.disable = 1;
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), port_0_ctl.u32))
+        return -1;
+
+    /* Errata SRIO-14485: Link speed is reported incorrectly in CN63XX
+        pass 1.x */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        cvmx_sriomaintx_port_0_ctl2_t port_0_ctl2;
+        if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port), &port_0_ctl2.u32))
+            return -1;
+        if (port_0_ctl2.s.enb_500g)
+        {
+            port_0_ctl2.u32 = 0;
+            port_0_ctl2.s.enb_625g = 1;
+        }
+        else if (port_0_ctl2.s.enb_312g)
+        {
+            port_0_ctl2.u32 = 0;
+            port_0_ctl2.s.enb_500g = 1;
+        }
+        else if (port_0_ctl2.s.enb_250g)
+        {
+            port_0_ctl2.u32 = 0;
+            port_0_ctl2.s.enb_312g = 1;
+        }
+        else if (port_0_ctl2.s.enb_125g)
+        {
+            port_0_ctl2.u32 = 0;
+            port_0_ctl2.s.enb_250g = 1;
+        }
+        else
+        {
+            port_0_ctl2.u32 = 0;
+            port_0_ctl2.s.enb_125g = 1;
+        }
+        if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port), port_0_ctl2.u32))
+            return -1;
+    }
+
+    /* Set the link layer timeout to 10us. The default is too high and causes
+        core bus errors */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_LT_CTL(srio_port), &port_lt_ctl.u32))
+        return -1;
+    port_lt_ctl.s.timeout = 10000 / 200; /* 10us = 10000ns / 200ns */
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_LT_CTL(srio_port), port_lt_ctl.u32))
+        return -1;
+
+    /* Set the logical layer timeout to 10ms. The default is too high and causes
+        core bus errors */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_RT_CTL(srio_port), &port_rt_ctl.u32))
+        return -1;
+    port_rt_ctl.s.timeout = 10000000 / 200; /* 10ms = 10000000ns / 200ns */
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_RT_CTL(srio_port), port_rt_ctl.u32))
+        return -1;
+
+    /* Allow memory and doorbells. Messaging is enabled later */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), &core_enables.u32))
+        return -1;
+    core_enables.s.doorbell = 1;
+    core_enables.s.memory = 1;
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), core_enables.u32))
+        return -1;
+
+    /* Allow us to master transactions */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_GEN_CTL(srio_port), &port_gen_ctl.u32))
+        return -1;
+    port_gen_ctl.s.menable = 1;
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_GEN_CTL(srio_port), port_gen_ctl.u32))
+        return -1;
+
+    /* Set the MRRS and MPS for optimal SRIO performance */
+    prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(srio_port));
+    prt_cfg.s.mps = 1;
+    prt_cfg.s.mrrs = 1;
+    cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(srio_port), prt_cfg.u64);
+
+    sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(srio_port));
+    sli_s2m_portx_ctl.s.mrrs = 1;
+    cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(srio_port), sli_s2m_portx_ctl.u64);
+
+    /* Setup RX messaging thresholds */
+    sriox_imsg_vport_thr.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_VPORT_THR(srio_port));
+    sriox_imsg_vport_thr.s.max_tot = 48;
+    sriox_imsg_vport_thr.s.max_s1 = 24;
+    sriox_imsg_vport_thr.s.max_s0 = 24;
+    sriox_imsg_vport_thr.s.sp_vport = 1;
+    sriox_imsg_vport_thr.s.buf_thr = 4;
+    sriox_imsg_vport_thr.s.max_p1 = 12;
+    sriox_imsg_vport_thr.s.max_p0 = 12;
+    cvmx_write_csr(CVMX_SRIOX_IMSG_VPORT_THR(srio_port), sriox_imsg_vport_thr.u64);
+
+    /* Errata SRIO-X: SRIO error behavior may not be optimal in CN63XX pass 1.x */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+    {
+        cvmx_sriox_tx_ctrl_t sriox_tx_ctrl;
+        sriox_tx_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_TX_CTRL(srio_port));
+        sriox_tx_ctrl.s.tag_th2 = 2;
+        sriox_tx_ctrl.s.tag_th1 = 3;
+        sriox_tx_ctrl.s.tag_th0 = 4;
+        cvmx_write_csr(CVMX_SRIOX_TX_CTRL(srio_port), sriox_tx_ctrl.u64);
+    }
+
+    /* Clear any pending interrupts */
+    cvmx_write_csr(CVMX_SRIOX_INT_REG(srio_port), cvmx_read_csr(CVMX_SRIOX_INT_REG(srio_port)));
+
+    /* Enable error reporting */
+#if (!defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_LINUX_KERNEL)) || defined(CONFIG_CAVIUM_DECODE_RSL)
+    cvmx_error_enable_group(CVMX_ERROR_GROUP_SRIO, srio_port);
+#endif
+
+    /* Finally enable the link */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), &port_0_ctl.u32))
+        return -1;
+    port_0_ctl.s.o_enable = 1;
+    port_0_ctl.s.i_enable = 1;
+    port_0_ctl.s.disable = 0;
+    port_0_ctl.s.prt_lock = 0;
+    if (__cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_PORT_0_CTL(srio_port), port_0_ctl.u32))
+        return -1;
+
+    return 0;
+}
+
+
+/**
+ * Read 32bits from a Device's config space
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID, or -1 for the local Octeon.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param hopcount  Number of hops to the remote device. Use 0 for the local Octeon.
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param result    Result of the read. This will be unmodified on failure.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_config_read32(int srio_port, int srcid_index, int destid,
+                            int is16bit, uint8_t hopcount, uint32_t offset,
+                            uint32_t *result)
+{
+    if (destid == -1)
+    {
+        int status = __cvmx_srio_local_read32(srio_port, offset, result);
+
+        if ((status == 0) && (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG))
+            cvmx_dprintf("SRIO%d: Local read [0x%06x] <= 0x%08x\n", srio_port, (unsigned int)offset, (unsigned int)*result);
+
+        return status;
+    }
+    else
+    {
+#if CVMX_SRIO_USE_FIFO_FOR_MAINT
+        int return_code;
+        uint32_t pkt = 0;
+        uint32_t sourceid;
+        uint64_t stop_cycle;
+        char rx_buffer[64];
+
+        /* Tell the user */
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, (unsigned int)offset);
+
+        /* Read the proper source ID */
+        if (srcid_index)
+            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
+        else
+            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
+
+        if (is16bit)
+        {
+            /* Use the 16bit source ID */
+            sourceid &= 0xffff;
+
+            /* MAINT Reads are 11 bytes */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 11<<16);
+
+            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+            pkt |= 1 << 28;                         /* tt       [29:28] */
+            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+            pkt |= destid << 8;                     /* destID   [23:8] */
+            pkt |= sourceid >> 8;                   /* sourceID [7:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= sourceid << 24;                  /* sourceID [31:24] */
+            pkt |= 0 << 20;                         /* transaction [23:20] */
+            pkt |= 8 << 16;                         /* rdsize [19:16] */
+            pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
+            pkt |= hopcount;                        /* hopcount [7:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+        }
+        else
+        {
+            /* Use the 8bit source ID */
+            sourceid = (sourceid >> 16) & 0xff;
+
+            /* MAINT Reads are 9 bytes */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 9<<16);
+
+            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+            pkt |= 0 << 28;                         /* tt       [29:28] */
+            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+            pkt |= destid << 16;                    /* destID   [23:16] */
+            pkt |= sourceid << 8;                   /* sourceID [15:8] */
+            pkt |= 0 << 4;                          /* transaction [7:4] */
+            pkt |= 8 << 0;                          /* rdsize [3:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
+            pkt |= hopcount << 16;                  /* hopcount [23:16] */
+            pkt |= offset >> 8;                     /* offset [15:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+        }
+
+        stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+        do
+        {
+            return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
+            if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+            {
+                if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                    cvmx_dprintf("timeout\n");
+                return_code = -1;
+            }
+        } while (return_code == 0);
+
+        if (return_code == ((is16bit) ? 23 : 19))
+        {
+            if (is16bit)
+            {
+                if (offset & 4)
+                    *result = *(uint32_t*)(rx_buffer + 15);
+                else
+                    *result = *(uint32_t*)(rx_buffer + 11);
+            }
+            else
+            {
+                if (offset & 4)
+                    *result = *(uint32_t*)(rx_buffer + 13);
+                else
+                    *result = *(uint32_t*)(rx_buffer + 9);
+            }
+            if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                cvmx_dprintf("0x%08x\n", (unsigned int)*result);
+            return_code = 0;
+        }
+        else
+        {
+            *result = 0xffffffff;
+            return_code = -1;
+        }
+
+        return return_code;
+#elif !defined(CVMX_BUILD_FOR_LINUX_HOST)
+        uint64_t physical;
+        physical = cvmx_srio_physical_map(srio_port,
+            CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+            CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+            srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
+        if (!physical)
+            return -1;
+
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Remote read [id=0x%04x hop=%3d offset=0x%06x] <= ", srio_port, destid, hopcount, offset);
+
+        /* Finally do the maintenance read to complete the config request */
+        *result = cvmx_read64_uint32(CVMX_ADD_IO_SEG(physical));
+        cvmx_srio_physical_unmap(physical, 4);
+
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("0x%08x\n", *result);
+
+        return 0;
+#else
+        return -1;
+#endif
+    }
+}
+
+
+/**
+ * Write 32bits to a Device's config space
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID, or -1 for the local Octeon.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param hopcount  Number of hops to the remote device. Use 0 for the local Octeon.
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param data      Data to write.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_config_write32(int srio_port, int srcid_index, int destid,
+                             int is16bit, uint8_t hopcount, uint32_t offset,
+                             uint32_t data)
+{
+    if (destid == -1)
+    {
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Local write[0x%06x] => 0x%08x\n", srio_port, (unsigned int)offset, (unsigned int)data);
+
+        return __cvmx_srio_local_write32(srio_port, offset, data);
+    }
+    else
+    {
+#if CVMX_SRIO_USE_FIFO_FOR_MAINT
+        int return_code;
+        uint32_t pkt = 0;
+        uint32_t sourceid;
+        uint64_t stop_cycle;
+        char rx_buffer[64];
+
+        /* Tell the user */
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, (unsigned int)offset, (unsigned int)data);
+
+        /* Read the proper source ID */
+        if (srcid_index)
+            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_SEC_DEV_ID(srio_port), &sourceid);
+        else
+            __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_PRI_DEV_ID(srio_port), &sourceid);
+
+        if (is16bit)
+        {
+            /* Use the 16bit source ID */
+            sourceid &= 0xffff;
+
+            /* MAINT Writes are 19 bytes */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 19<<16);
+
+            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+            pkt |= 1 << 28;                         /* tt       [29:28] */
+            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+            pkt |= destid << 8;                     /* destID   [23:8] */
+            pkt |= sourceid >> 8;                   /* sourceID [7:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= sourceid << 24;                  /* sourceID [31:24] */
+            pkt |= 1 << 20;                         /* transaction [23:20] */
+            pkt |= 8 << 16;                         /* wrsize [19:16] */
+            pkt |= 0xc0 << 8;                       /* srcTID [15:8] */
+            pkt |= hopcount;                        /* hopcount [7:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= offset << 8;                     /* offset [31:11, wdptr[10], reserved[9:8] */
+            if ((offset & 4) == 0)
+                pkt |= 0xff & (data >> 24);       /* data [7:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            if (offset & 4)
+            {
+                pkt = 0xff & (data >> 24);
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = data << 8;
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            }
+            else
+            {
+                pkt = data << 8;
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
+            }
+        }
+        else
+        {
+            /* Use the 8bit source ID */
+            sourceid = (sourceid >> 16) & 0xff;
+
+            /* MAINT Writes are 17 bytes */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_CTRL(srio_port), 17<<16);
+
+            pkt |= CVMX_SRIO_CONFIG_PRIORITY << 30; /* priority [31:30] */
+            pkt |= 0 << 28;                         /* tt       [29:28] */
+            pkt |= 0x8 << 24;                       /* ftype    [27:24] */
+            pkt |= destid << 16;                    /* destID   [23:16] */
+            pkt |= sourceid << 8;                   /* sourceID [15:8] */
+            pkt |= 1 << 4;                          /* transaction [7:4] */
+            pkt |= 8 << 0;                          /* wrsize [3:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= 0xc0 << 24;                      /* srcTID [31:24] */
+            pkt |= hopcount << 16;                  /* hopcount [23:16] */
+            pkt |= offset >> 8;                     /* offset [15:0] */
+            __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            pkt = 0;
+            pkt |= offset << 24;                    /* offset [31:27, wdptr[26], reserved[25:24] */
+            if (offset & 4)
+            {
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = data >> 8;
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = data << 24;
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+            }
+            else
+            {
+                pkt |= data >> 8;                    /* data [23:0] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                pkt = data << 24;                    /* data [31:24] */
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), pkt);
+                __cvmx_srio_local_write32(srio_port, CVMX_SRIOMAINTX_IR_SP_TX_DATA(srio_port), 0);
+            }
+        }
+
+        stop_cycle = cvmx_clock_get_rate(CVMX_CLOCK_CORE)/10 + cvmx_clock_get_count(CVMX_CLOCK_CORE);
+        do
+        {
+            return_code = cvmx_srio_receive_spf(srio_port, rx_buffer, sizeof(rx_buffer));
+            if ((return_code == 0) && (cvmx_clock_get_count(CVMX_CLOCK_CORE) > stop_cycle))
+            {
+                if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+                    cvmx_dprintf("timeout\n");
+                return_code = -1;
+            }
+        } while (return_code == 0);
+
+        if (return_code == ((is16bit) ? 15 : 11))
+            return_code = 0;
+        else
+        {
+            cvmx_dprintf("SRIO%d: Remote write failed\n", srio_port);
+            return_code = -1;
+        }
+
+        return return_code;
+#elif !defined(CVMX_BUILD_FOR_LINUX_HOST)
+        uint64_t physical = cvmx_srio_physical_map(srio_port,
+                CVMX_SRIO_WRITE_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                CVMX_SRIO_READ_MODE_MAINTENANCE, CVMX_SRIO_CONFIG_PRIORITY,
+                srcid_index, destid, is16bit, offset + (hopcount<<24), 4);
+        if (!physical)
+            return -1;
+
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Remote write[id=0x%04x hop=%3d offset=0x%06x] => 0x%08x\n", srio_port, destid, hopcount, offset, data);
+
+        /* Finally do the maintenance write to complete the config request */
+        cvmx_write64_uint32(CVMX_ADD_IO_SEG(physical), data);
+        return cvmx_srio_physical_unmap(physical, 4);
+#else
+        return -1;
+#endif
+    }
+}
+
+
+/**
+ * Send a RapidIO doorbell to a remote device
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param priority  Doorbell priority (0-3)
+ * @param data      Data for doorbell.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid, int is16bit, int priority, uint16_t data)
+{
+    cvmx_sriox_tx_bell_t tx_bell;
+    tx_bell.u64 = 0;
+    tx_bell.s.data = data;
+    tx_bell.s.dest_id = destid;
+    tx_bell.s.src_id = srcid_index;
+    tx_bell.s.id16 = !!is16bit;
+    tx_bell.s.priority = priority;
+
+    /* Make sure the previous doorbell has completed */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_SRIOX_TX_BELL(srio_port), cvmx_sriox_tx_bell_t, pending, ==, 0, CVMX_SRIO_DOORBELL_TIMEOUT))
+    {
+        cvmx_dprintf("SRIO%d: Pending bit stuck before doorbell\n", srio_port);
+        return -1;
+    }
+
+    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+        cvmx_dprintf("SRIO%d: Send doorbell destid=0x%x, priority=%d, data=0x%x\n", srio_port, destid, priority, 0xffff & data);
+
+    /* Send the doorbell. We don't wait for it to complete. The next doorbell
+        may delay on the pending bit, but this gives the caller the ability to
+        do other stuff while the doorbell processes */
+    cvmx_write_csr(CVMX_SRIOX_TX_BELL(srio_port), tx_bell.u64);
+    return 0;
+}
+
+
+/**
+ * Get the status of the last doorbell sent. If the dooorbell
+ * hardware is done, then the status is cleared to get ready for
+ * the next doorbell (or retry).
+ *
+ * @param srio_port SRIO port to check doorbell on
+ *
+ * @return Doorbell status
+ */
+cvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port)
+{
+    cvmx_sriox_tx_bell_t tx_bell;
+    cvmx_sriox_tx_bell_info_t tx_bell_info;
+    cvmx_sriox_int_reg_t int_reg;
+    cvmx_sriox_int_reg_t int_reg_clear;
+
+    /* Return busy if the doorbell is still processing */
+    tx_bell.u64 = cvmx_read_csr(CVMX_SRIOX_TX_BELL(srio_port));
+    if (tx_bell.s.pending)
+        return CVMX_SRIO_DOORBELL_BUSY;
+
+    /* Read and clear the TX doorbell interrupts */
+    int_reg.u64 = cvmx_read_csr(CVMX_SRIOX_INT_REG(srio_port));
+    int_reg_clear.u64 = 0;
+    int_reg_clear.s.bell_err = int_reg.s.bell_err;
+    int_reg_clear.s.txbell = int_reg.s.txbell;
+    cvmx_write_csr(CVMX_SRIOX_INT_REG(srio_port), int_reg_clear.u64);
+
+    /* Check for errors */
+    if (int_reg.s.bell_err)
+    {
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf("SRIO%d: Send doorbell failed\n", srio_port);
+        tx_bell_info.u64 = cvmx_read_csr(CVMX_SRIOX_TX_BELL_INFO(srio_port));
+        if (tx_bell_info.s.timeout || tx_bell_info.s.error)
+            return CVMX_SRIO_DOORBELL_ERROR;
+        if (tx_bell_info.s.retry)
+            return CVMX_SRIO_DOORBELL_RETRY;
+    }
+
+    /* Check if we're done */
+    if (int_reg.s.txbell)
+        return CVMX_SRIO_DOORBELL_DONE;
+
+    /* No doorbell found */
+    return CVMX_SRIO_DOORBELL_NONE;
+}
+
+
+/**
+ * Read a received doorbell and report data about it.
+ *
+ * @param srio_port SRIO port to check for the received doorbell
+ * @param destid_index
+ *                  Which Octeon destination ID was the doorbell for
+ * @param sequence_num
+ *                  Sequence number of doorbell (32bits)
+ * @param srcid     RapidIO source ID of the doorbell sender
+ * @param priority  Priority of the doorbell (0-3)
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param data      Data in the doorbell (16 bits)
+ *
+ * @return Doorbell status. Either DONE, NONE, or ERROR.
+ */
+cvmx_srio_doorbell_status_t cvmx_srio_receive_doorbell(int srio_port,
+        int *destid_index, uint32_t *sequence_num, int *srcid, int *priority,
+        int *is16bit, uint16_t *data)
+{
+    cvmx_sriox_rx_bell_seq_t rx_bell_seq;
+    cvmx_sriox_rx_bell_t rx_bell;
+
+    /* Check if there are any pending doorbells */
+    rx_bell_seq.u64 = cvmx_read_csr(CVMX_SRIOX_RX_BELL_SEQ(srio_port));
+    if (!rx_bell_seq.s.count)
+        return CVMX_SRIO_DOORBELL_NONE;
+
+    /* Read the doorbell and write our return parameters */
+    rx_bell.u64 = cvmx_read_csr(CVMX_SRIOX_RX_BELL(srio_port));
+    *sequence_num = rx_bell_seq.s.seq;
+    *srcid = rx_bell.s.src_id;
+    *priority = rx_bell.s.priority;
+    *is16bit = rx_bell.s.id16;
+    *data = rx_bell.s.data;
+    *destid_index = rx_bell.s.dest_id;
+
+    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+        cvmx_dprintf("SRIO%d: Receive doorbell sequence=0x%x, srcid=0x%x, priority=%d, data=0x%x\n",
+            srio_port, rx_bell_seq.s.seq, rx_bell.s.src_id, rx_bell.s.priority, rx_bell.s.data);
+
+    return CVMX_SRIO_DOORBELL_DONE;
+}
+
+
+/**
+ * Receive a packet from the Soft Packet FIFO (SPF).
+ *
+ * @param srio_port SRIO port to read the packet from.
+ * @param buffer    Buffer to receive the packet.
+ * @param buffer_length
+ *                  Length of the buffer in bytes.
+ *
+ * @return Returns the length of the packet read. Negative on failure.
+ *         Zero if no packets are available.
+ */
+int cvmx_srio_receive_spf(int srio_port, void *buffer, int buffer_length)
+{
+    uint32_t *ptr = (uint32_t *)buffer;
+    cvmx_sriomaintx_ir_sp_rx_stat_t sriomaintx_ir_sp_rx_stat;
+
+    /* Read the SFP status */
+    if (__cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_IR_SP_RX_STAT(srio_port), &sriomaintx_ir_sp_rx_stat.u32))
+        return -1;
+
+    /* Return zero if there isn't a packet available */
+    if (sriomaintx_ir_sp_rx_stat.s.buffers < 1)
+        return 0;
+
+    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+        cvmx_dprintf("SRIO%d: Soft packet FIFO received %d bytes", srio_port, sriomaintx_ir_sp_rx_stat.s.octets);
+
+    /* Return error if the packet is larger than our buffer */
+    if (sriomaintx_ir_sp_rx_stat.s.octets > buffer_length)
+        return -1;
+
+    /* Read out the packet four bytes at a time */
+    buffer_length = sriomaintx_ir_sp_rx_stat.s.octets;
+    while (buffer_length > 0)
+    {
+        __cvmx_srio_local_read32(srio_port, CVMX_SRIOMAINTX_IR_SP_RX_DATA(srio_port), ptr);
+        if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+            cvmx_dprintf(" %08x", (unsigned int)*ptr);
+        ptr++;
+        buffer_length-=4;
+    }
+
+    if (__cvmx_srio_state[srio_port].flags & CVMX_SRIO_INITIALIZE_DEBUG)
+        cvmx_dprintf("\n");
+
+    /* Return the number of bytes in the buffer */
+    return sriomaintx_ir_sp_rx_stat.s.octets;
+}
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * Map a remote device's memory region into Octeon's physical
+ * address area. The caller can then map this into a core using
+ * the TLB or XKPHYS.
+ *
+ * @param srio_port SRIO port to map the device on
+ * @param write_op  Type of operation to perform on a write to the device.
+ *                  Normally should be CVMX_SRIO_WRITE_MODE_AUTO.
+ * @param write_priority
+ *                  SRIO priority of writes (0-3)
+ * @param read_op   Type of operation to perform on reads to the device.
+ *                  Normally should be CVMX_SRIO_READ_MODE_NORMAL.
+ * @param read_priority
+ *                  SRIO priority of reads (0-3)
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param base      Device base address to start the mapping
+ * @param size      Size of the mapping in bytes
+ *
+ * @return Octeon 64bit physical address that accesses the remote device,
+ *         or zero on failure.
+ */
+uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
+        int write_priority, cvmx_srio_read_mode_t read_op, int read_priority,
+        int srcid_index, int destid, int is16bit, uint64_t base, uint64_t size)
+{
+    cvmx_sriox_s2m_typex_t needed_s2m_type;
+    cvmx_sli_mem_access_subidx_t needed_subid;
+    int s2m_index;
+    int subdid;
+    cvmx_sli_address_t sli_address;
+
+    /* We currently don't support mapping regions that span a 34 bit boundary.
+        Keeping track of multiple regions to span 34 bits is hard and not
+        likely to be needed */
+    if (((base+size-1)>>34) != (base>>34))
+    {
+        cvmx_dprintf("SRIO%d: Failed to map range 0x%llx-0x%llx spanning a 34bit boundary\n",
+            srio_port, (ULL)base, (ULL)base+size-1);
+        return 0;
+    }
+
+    /* Build the S2M_TYPE we are going to need */
+    needed_s2m_type.u64 = 0;
+    needed_s2m_type.s.wr_op = write_op;
+    needed_s2m_type.s.rd_op = read_op;
+    needed_s2m_type.s.wr_prior = write_priority;
+    needed_s2m_type.s.rd_prior = read_priority;
+    needed_s2m_type.s.src_id = srcid_index;
+    needed_s2m_type.s.id16 = !!is16bit;
+
+    /* Build the needed SubID config */
+    needed_subid.u64 = 0;
+    needed_subid.s.port = srio_port;
+    needed_subid.s.nmerge = 1;
+
+    /* FIXME: We might want to use the device ID swapping modes so the device
+        ID is part of the lower address bits. This would allow many more
+        devices to share S2M_TYPE indexes. This would require "base+size-1"
+        to fit in bits [17:0] or bits[25:0] for 8 bits of device ID */
+    if (base < (1ull<<34))
+    {
+        needed_subid.s.ba = destid;
+        needed_s2m_type.s.iaow_sel = 0;
+    }
+    else if (base < (1ull<<42))
+    {
+        needed_subid.s.ba = (base>>34) & 0xff;
+        needed_subid.s.ba |= ((uint64_t)destid & 0xff) << (42-34);
+        needed_subid.s.ba |= (((uint64_t)destid>>8) & 0xff) << (51-34);
+        needed_s2m_type.s.iaow_sel = 1;
+    }
+    else
+    {
+        if (destid>>8)
+        {
+            cvmx_dprintf("SRIO%d: Attempt to map 16bit device ID 0x%x using 66bit addressing\n", srio_port, destid);
+            return 0;
+        }
+        if (base>>50)
+        {
+            cvmx_dprintf("SRIO%d: Attempt to map address 0x%llx using 66bit addressing\n", srio_port, (ULL)base);
+            return 0;
+        }
+        needed_subid.s.ba = (base>>34) & 0xffff;
+        needed_subid.s.ba |= ((uint64_t)destid & 0xff) << (51-34);
+        needed_s2m_type.s.iaow_sel = 2;
+    }
+
+    /* Find a S2M_TYPE index to use. If this fails return 0 */
+    s2m_index = __cvmx_srio_alloc_s2m(srio_port, needed_s2m_type);
+    if (s2m_index == -1)
+        return 0;
+
+    /* Attach the SubID to the S2M_TYPE index */
+    needed_subid.s.rtype = s2m_index & 3;
+    needed_subid.s.wtype = s2m_index & 3;
+    needed_subid.s.ba |= (((uint64_t)s2m_index >> 2) & 1) << (50-34);
+    needed_subid.s.ba |= (((uint64_t)s2m_index >> 3) & 1) << (59-34);
+
+    /* Allocate a SubID for use */
+    subdid = __cvmx_srio_alloc_subid(needed_subid);
+    if (subdid == -1)
+    {
+        /* Free the s2m_index as we aren't using it */
+        __cvmx_srio_free_s2m(srio_port, s2m_index);
+        return 0;
+    }
+
+    /* Build the final core physical address */
+    sli_address.u64 = 0;
+    sli_address.mem.io = 1;
+    sli_address.mem.did = 3;
+    sli_address.mem.subdid = subdid>>2;
+    sli_address.mem.se = subdid & 3;
+    sli_address.mem.address = base; /* Bits[33:0] of full address */
+    return sli_address.u64;
+}
+
+
+/**
+ * Unmap a physical address window created by cvmx_srio_phys_map().
+ *
+ * @param physical_address
+ *               Physical address returned by cvmx_srio_phys_map().
+ * @param size   Size used on original call.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size)
+{
+    cvmx_sli_mem_access_subidx_t subid;
+    int subdid = (physical_address >> 40) & 7;
+    int extender = (physical_address >> 34) & 3;
+    int mem_index = subdid * 4 + extender;
+    int read_s2m_type;
+
+    /* Get the subid setup so we can figure out where this mapping was for */
+    subid.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(mem_index));
+    /* Type[0] is mapped to the Relaxed Ordering
+       Type[1] is mapped to the No Snoop
+       Type[2] is mapped directly to bit 50 of the SLI address
+       Type[3] is mapped directly to bit 59 of the SLI address */
+    read_s2m_type = ((subid.s.ba>>(50-34))&1<<2) | ((subid.s.ba>>(59-34))&1<<3);
+    read_s2m_type |= subid.s.rtype;
+    __cvmx_srio_free_subid(mem_index);
+    __cvmx_srio_free_s2m(subid.s.port, read_s2m_type);
+    return 0;
+}
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-srio.h b/sys/contrib/octeon-sdk/cvmx-srio.h
new file mode 100644
index 0000000..e53813c
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-srio.h
@@ -0,0 +1,525 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+/**
+ * @file
+ *
+ * Interface to SRIO
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_SRIO_H__
+#define __CVMX_SRIO_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of the type of operations that can be performed
+ * by a mapped write operation.
+ */
+typedef enum
+{
+    CVMX_SRIO_WRITE_MODE_NWRITE = 0,        /**< Only create NWrite operations */
+    CVMX_SRIO_WRITE_MODE_NWRITE_RESP = 1,   /**< Create NWrite with response */
+    CVMX_SRIO_WRITE_MODE_AUTO = 2,          /**< Intelligently breaks writes into multiple transactions based on alignment */
+    CVMX_SRIO_WRITE_MODE_AUTO_RESP = 3,     /**< CVMX_SRIO_WRITE_MODE_WRITE followed with a response */
+    CVMX_SRIO_WRITE_MODE_MAINTENANCE = 6,   /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_write32() instead */
+    CVMX_SRIO_WRITE_MODE_PORT = 7           /**< Port Write? */
+} cvmx_srio_write_mode_t;
+
+/**
+ * Enumeration of the type of operations that can be performed
+ * by a mapped read operation.
+ */
+typedef enum
+{
+    CVMX_SRIO_READ_MODE_NORMAL = 0,         /**< Perform a normal read */
+    CVMX_SRIO_READ_MODE_ATOMIC_SET = 2,     /**< Atomically sets bits in data on remote device */
+    CVMX_SRIO_READ_MODE_ATOMIC_CLEAR = 3,   /**< Atomically clears bits in data on remote device */
+    CVMX_SRIO_READ_MODE_ATOMIC_INCREMENT = 4,/**< Atomically increments data on remote device */
+    CVMX_SRIO_READ_MODE_ATOMIC_DECREMENT = 5,/**< Atomically decrements data on remote device */
+    CVMX_SRIO_READ_MODE_MAINTENANCE = 6     /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_read32() instead */
+} cvmx_srio_read_mode_t;
+
+/**
+ * Initialization flags for SRIO
+ */
+typedef enum
+{
+    CVMX_SRIO_INITIALIZE_DEBUG = 1,
+} cvmx_srio_initialize_flags_t;
+
+/**
+ * The possible results from a doorbell operation
+ */
+typedef enum
+{
+    CVMX_SRIO_DOORBELL_DONE,    /**< The doorbell is complete */
+    CVMX_SRIO_DOORBELL_NONE,    /**< There wasn't an outstanding doorbell */
+    CVMX_SRIO_DOORBELL_BUSY,    /**< The doorbell is still processing */
+    CVMX_SRIO_DOORBELL_RETRY,   /**< The doorbell needs to be retried */
+    CVMX_SRIO_DOORBELL_ERROR    /**< The doorbell failed with an error */
+} cvmx_srio_doorbell_status_t;
+
+/**
+ * This structure represents the SRIO header received from SRIO on
+ * the top of every received message. This header passes through
+ * IPD/PIP unmodified.
+ */
+typedef struct
+{
+    union
+    {
+        uint64_t u64;
+        struct
+        {
+#if __BYTE_ORDER == __BIG_ENDIAN
+            uint64_t prio   : 2; /**< The sRIO prio (priority) field in the
+                                    first sRIO message segment received for the
+                                    message. */
+            uint64_t tt     : 1; /**< When set, indicates that the first sRIO
+                                    message segment received for the message had
+                                    16-bit source and destination ID's. When
+                                    clear, indicates 8-bit ID were present. */
+            uint64_t dis    : 1; /**< When set, indicates that the destination
+                                    ID in the first sRIO message segment received
+                                    for the message matched the 63xx's secondary
+                                    ID. When clear, indicates that the destination
+                                    ID in the first sRIO message segment
+                                    received for the message matched the 63xx's
+                                    primary ID. Note that the full destination
+                                    ID in the received sRIO message can be
+                                    determined via the combination of
+                                    WORD0[DIS] in the sRIO inbound message
+                                    header and WORD1[iprt] in the work queue
+                                    entry created by PIP/IPD. */
+            uint64_t ssize  : 4; /**< The RIO ssize (standard message packet data
+                                    size) field used for the message. */
+            uint64_t sid    : 16; /**< The source ID in the first sRIO message
+                                    segment received for the message. When TT is
+                                    clear, the most-significant 8 bits are zero. */
+            uint64_t xmbox  : 4; /**< The RIO xmbox (recipient mailbox extension)
+                                    field in the first sRIO message segment
+                                    received for the message. Always zero for
+                                    multi-segment messages. */
+            uint64_t mbox   : 2; /**< The RIO mbox (recipient mailbox) field in
+                                    the first sRIO message segment received for
+                                    the message. */
+            uint64_t letter : 2; /**< The RIO letter (slot within a mailbox)
+                                    field in the first sRIO message segment
+                                    received for the message. */
+            uint64_t seq    : 32; /**< A sequence number. Whenever the OCTEON
+                                    63xx sRIO hardware accepts the first sRIO
+                                    segment of either a message or doorbell, it
+                                    samples the current value of a counter
+                                    register and increments the counter
+                                    register. SEQ is the value sampled for the
+                                    message. The counter increments once per
+                                    message/doorbell. SEQ can be used to
+                                    determine the relative order of
+                                    packets/doorbells. Note that the SEQ-implied
+                                    order may differ from the order that the
+                                    WQE's are received by software for a number
+                                    of reasons, including the fact that the WQE
+                                    is not created until the end of the message,
+                                    while SEQ is sampled when the first segment. */
+#else
+            uint64_t seq    : 32;
+            uint64_t letter : 2;
+            uint64_t mbox   : 2;
+            uint64_t xmbox  : 4;
+            uint64_t sid    : 16;
+            uint64_t ssize  : 4;
+            uint64_t dis    : 1;
+            uint64_t tt     : 1;
+            uint64_t prio   : 2;
+#endif
+        } s;
+    } word0;
+    union
+    {
+        uint64_t u64;
+        struct
+        {
+#if __BYTE_ORDER == __BIG_ENDIAN
+            uint64_t r      : 1; /**< When set, WORD1[R]/PKT_INST_HDR[R] selects
+                                    either RAWFULL or RAWSCHED special PIP
+                                    instruction form. WORD1[R] may commonly be
+                                    set so that WORD1[QOS,GRP] will be directly
+                                    used by the PIP hardware. */
+            uint64_t reserved_62_58 : 5;
+            uint64_t pm     : 2; /**< WORD1[PM]/PKT_INST_HDR[PM] selects the PIP
+                                    parse mode (uninterpreted, skip-to-L2,
+                                    skip-to-IP), and chooses between
+                                    RAWFULL/RAWSCHED when WORD1[R] is set. */
+            uint64_t reserved_55 : 1;
+            uint64_t sl     : 7; /**< WORD1[SL]/PKT_INST_HDR[SL] selects the
+                                    skip II length. WORD1[SL] may typically be
+                                    set to 8 (or larger) so that PIP skips this
+                                    WORD1. */
+            uint64_t reserved_47_46 : 2;
+            uint64_t nqos   : 1; /**< WORD1[NQOS] must not be set when WORD1[R]
+                                    is clear and PIP interprets WORD1 as a
+                                    PKT_INST_HDR. When set, WORD1[NQOS]/PKT_INST_HDR[NQOS]
+                                    prevents PIP from directly using
+                                    WORD1[QOS]/PKT_INST_HDR[QOS] for the QOS
+                                    value in the work queue entry created by
+                                    PIP. WORD1[NQOS] may commonly be clear so
+                                    that WORD1[QOS] will be directly used by the
+                                    PIP hardware. PKT_INST_HDR[NQOS] is new to
+                                    63xx - this functionality did not exist in
+                                    prior OCTEON's. */
+            uint64_t ngrp   : 1; /**< WORD1[NGRP] must not be set when WORD1[R]
+                                    is clear and PIP interprets WORD1 as a
+                                    PKT_INST_HDR. When set, WORD1[NGRP]/PKT_INST_HDR[NGRP]
+                                    prevents PIP from directly using
+                                    WORD1[GRP]/PKT_INST_HDR[GRP] for the GRP
+                                    value in the work queue entry created by
+                                    PIP. WORD1[NGRP] may commonly be clear so
+                                    that WORD1[GRP] will be directly used by the
+                                    PIP hardware. PKT_INST_HDR[NGRP] is new to
+                                    63xx - this functionality did not exist in
+                                    prior OCTEON's. */
+            uint64_t ntt    : 1; /**< WORD1[NTT] must not be set when WORD1[R]
+                                    is clear and PIP interprets WORD1 as a
+                                    PKT_INST_HDR. When set, WORD1[NTT]/PKT_INST_HDR[NTT]
+                                    prevents PIP from directly using
+                                    WORD1[TT]/PKT_INST_HDR[TT] for the TT value
+                                    in the work queue entry created by PIP.
+                                    PKT_INST_HDR[NTT] is new to 63xx - this
+                                    functionality did not exist in prior OCTEON's. */
+            uint64_t ntag   : 1; /**< WORD1[NTAG] must not be set when WORD1[R]
+                                    is clear and PIP interprets WORD1 as a
+                                    PKT_INST_HDR. When set, WORD1[NTAG]/PKT_INST_HDR[NTAG]
+                                    prevents PIP from directly using
+                                    WORD1[TAG]/PKT_INST_HDR[TAG] for the TAG
+                                    value in the work queue entry created by PIP.
+                                    PKT_INST_HDR[NTAG] is new to 63xx - this
+                                    functionality did not exist in prior OCTEON's. */
+            uint64_t qos    : 3; /**< Created by the hardware from an entry in a
+                                    256-entry table. The 8-bit value
+                                    WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
+                                    table entry. When WORD1[R] is set and WORD1[NQOS]
+                                    is clear, WORD1[QOS] becomes the QOS value
+                                    in the work queue entry created by PIP. The
+                                    QOS value in the work queue entry determines
+                                    the priority that SSO/POW will schedule the
+                                    work, and can also control how/if the sRIO
+                                    message gets dropped by PIP/IPD. The 256-entry
+                                    table is unique to each sRIO core, but
+                                    shared by the two controllers associated
+                                    with the sRIO core. */
+            uint64_t grp    : 4; /**< Created by the hardware from an entry in a
+                                    256-entry table. The 8-bit value
+                                    WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
+                                    table entry. When WORD1[R] is set and WORD1[NGRP]
+                                    is clear, WORD1[GRP] becomes the GRP value
+                                    in the work queue entry created by PIP. The
+                                    GRP value in the work queue entry can direct
+                                    the work to particular cores or particular
+                                    groups of cores. The 256-entry table is
+                                    unique to each sRIO core, but shared by the
+                                    two controllers associated with the sRIO core. */
+            uint64_t rs     : 1; /**< In some configurations, enables the sRIO
+                                    message to be buffered solely in the work
+                                    queue entry, and not otherwise in L2/DRAM. */
+            uint64_t tt     : 2; /**< When WORD1[R] is set and WORD1[NTT] is
+                                    clear, WORD1[TT]/PKT_INST_HDR[TT] becomes
+                                    the TT value in the work queue entry created
+                                    by PIP. The TT and TAG values in the work
+                                    queue entry determine the scheduling/synchronization
+                                    constraints for the work (no constraints,
+                                    tag order, atomic tag order). */
+            uint64_t tag    : 32; /**< Created by the hardware from a CSR
+                                    associated with the sRIO inbound message
+                                    controller. When WORD1[R] is set and WORD1[NTAG]
+                                    is clear, WORD1[TAG]/PKT_INST_HDR[TAG]
+                                    becomes the TAG value in the work queue
+                                    entry created by PIP. The TT and TAG values
+                                    in the work queue entry determine the
+                                    scheduling/synchronization constraints for
+                                    the work (no constraints, tag order, atomic
+                                    tag order). */
+#else
+            uint64_t tag    : 32;
+            uint64_t tt     : 2;
+            uint64_t rs     : 1;
+            uint64_t grp    : 4;
+            uint64_t qos    : 3;
+            uint64_t ntag   : 1;
+            uint64_t ntt    : 1;
+            uint64_t ngrp   : 1;
+            uint64_t nqos   : 1;
+            uint64_t reserved_47_46 : 2;
+            uint64_t sl     : 7;
+            uint64_t reserved_55 : 1;
+            uint64_t pm     : 2;
+            uint64_t reserved_62_58 : 5;
+            uint64_t r      : 1;
+#endif
+        } s;
+    } word1;
+} cvmx_srio_rx_message_header_t;
+
+/**
+ * This structure represents the SRIO header required on the front
+ * of PKO packets destine for SRIO message queues.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t prio   : 2;    /**< The sRIO prio (priority) field for all
+                                    segments in the message. */
+        uint64_t tt     : 1;    /**< When set, the sRIO message segments use a
+                                    16-bit source and destination ID for all the
+                                    segments in the message. When clear, the
+                                    message segments use an 8-bit ID. */
+        uint64_t sis    : 1;    /**< When set, the sRIO message segments use the
+                                    63xx's secondary ID as the source ID. When
+                                    clear, the sRIO message segments use the
+                                    primary ID as the source ID. */
+        uint64_t ssize  : 4;    /**< The RIO ssize (standard message segment
+                                    data size) field used for the message. */
+        uint64_t did    : 16;   /**< The destination ID in the sRIO message
+                                    segments of the message. When TT is clear,
+                                    the most-significant 8 bits must be zero. */
+        uint64_t xmbox  : 4;    /**< The RIO xmbox (recipient mailbox extension)
+                                    field in the sRIO message segment for a
+                                    single-segment message. Must be zero for
+                                    multi-segment messages. */
+        uint64_t mbox   : 2;    /**< The RIO mbox (recipient mailbox) field in
+                                    the sRIO message segments of the message. */
+        uint64_t letter : 2;    /**< The RIO letter (slot within mailbox) field
+                                    in the sRIO message segments of the message
+                                    when LNS is clear. When LNS is set, this
+                                    LETTER field is not used and must be zero. */
+        uint64_t reserved_31_2 : 30;
+        uint64_t lns    : 1;    /**< When set, the outbound message controller
+                                    will dynamically selects an sRIO letter
+                                    field for the message (based on LETTER_SP or
+                                    LETTER_MP - see appendix A), and the LETTER
+                                    field in this sRIO outbound message
+                                    descriptor is unused. When clear, the LETTER
+                                    field in this sRIO outbound message
+                                    descriptor selects the sRIO letter used for
+                                    the message. */
+        uint64_t intr   : 1;    /**< When set, the outbound message controller
+                                    will set an interrupt bit after all sRIO
+                                    segments of the message receive a message
+                                    DONE response. If the message transfer has
+                                    errors, the interrupt bit is not set (but
+                                    others are). */
+#else
+        uint64_t intr   : 1;
+        uint64_t lns    : 1;
+        uint64_t reserved_31_2 : 30;
+        uint64_t letter : 2;
+        uint64_t mbox   : 2;
+        uint64_t xmbox  : 4;
+        uint64_t did    : 16;
+        uint64_t ssize  : 4;
+        uint64_t sis    : 1;
+        uint64_t tt     : 1;
+        uint64_t prio   : 2;
+#endif
+    } s;
+} cvmx_srio_tx_message_header_t;
+
+/**
+ * Initialize a SRIO port for use.
+ *
+ * @param srio_port SRIO port to initialize
+ * @param flags     Optional flags
+ *
+ * @return Zero on success
+ */
+int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags);
+
+/**
+ * Read 32bits from a Device's config space
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID, or -1 for the local Octeon.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param hopcount  Number of hops to the remote device. Use 0 for the local Octeon.
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param result    Result of the read. This will be unmodified on failure.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_config_read32(int srio_port, int srcid_index, int destid,
+                            int is16bit, uint8_t hopcount, uint32_t offset,
+                            uint32_t *result);
+
+/**
+ * Write 32bits to a Device's config space
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID, or -1 for the local Octeon.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param hopcount  Number of hops to the remote device. Use 0 for the local Octeon.
+ * @param offset    Offset in config space. This must be a multiple of 32 bits.
+ * @param data      Data to write.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_config_write32(int srio_port, int srcid_index, int destid,
+                             int is16bit, uint8_t hopcount, uint32_t offset,
+                             uint32_t data);
+
+/**
+ * Send a RapidIO doorbell to a remote device
+ *
+ * @param srio_port SRIO port the device is on
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param priority  Doorbell priority (0-3)
+ * @param data      Data for doorbell.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid,
+                            int is16bit, int priority, uint16_t data);
+
+/**
+ * Get the status of the last doorbell sent. If the dooorbell
+ * hardware is done, then the status is cleared to get ready for
+ * the next doorbell (or retry).
+ *
+ * @param srio_port SRIO port to check doorbell on
+ *
+ * @return Doorbell status
+ */
+cvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port);
+
+/**
+ * Read a received doorbell and report data about it.
+ *
+ * @param srio_port SRIO port to check for the received doorbell
+ * @param destid_index
+ *                  Which Octeon destination ID was the doorbell for
+ * @param sequence_num
+ *                  Sequence number of doorbell (32bits)
+ * @param srcid     RapidIO source ID of the doorbell sender
+ * @param priority  Priority of the doorbell (0-3)
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param data      Data in the doorbell (16 bits)
+ *
+ * @return Doorbell status. Either DONE, NONE, or ERROR.
+ */
+cvmx_srio_doorbell_status_t cvmx_srio_receive_doorbell(int srio_port,
+        int *destid_index, uint32_t *sequence_num, int *srcid, int *priority,
+        int *is16bit, uint16_t *data);
+
+/**
+ * Receive a packet from the Soft Packet FIFO (SPF).
+ *
+ * @param srio_port SRIO port to read the packet from.
+ * @param buffer    Buffer to receive the packet.
+ * @param buffer_length
+ *                  Length of the buffer in bytes.
+ *
+ * @return Returns the length of the packet read. Negative on failure.
+ *         Zero if no packets are available.
+ */
+int cvmx_srio_receive_spf(int srio_port, void *buffer, int buffer_length);
+
+/**
+ * Map a remote device's memory region into Octeon's physical
+ * address area. The caller can then map this into a core using
+ * the TLB or XKPHYS.
+ *
+ * @param srio_port SRIO port to map the device on
+ * @param write_op  Type of operation to perform on a write to the device.
+ *                  Normally should be CVMX_SRIO_WRITE_MODE_AUTO.
+ * @param write_priority
+ *                  SRIO priority of writes (0-3)
+ * @param read_op   Type of operation to perform on reads to the device.
+ *                  Normally should be CVMX_SRIO_READ_MODE_NORMAL.
+ * @param read_priority
+ *                  SRIO priority of reads (0-3)
+ * @param srcid_index
+ *                  Which SRIO source ID to use. 0 = Primary, 1 = Secondary
+ * @param destid    RapidIO device ID.
+ * @param is16bit   Non zero if the transactions should use 16bit device IDs. Zero
+ *                  if transactions should use 8bit device IDs.
+ * @param base      Device base address to start the mapping
+ * @param size      Size of the mapping in bytes
+ *
+ * @return Octeon 64bit physical address that accesses the remote device,
+ *         or zero on failure.
+ */
+uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
+        int write_priority, cvmx_srio_read_mode_t read_op, int read_priority,
+        int srcid_index, int destid, int is16bit, uint64_t base, uint64_t size);
+
+/**
+ * Unmap a physical address window created by cvmx_srio_phys_map().
+ *
+ * @param physical_address
+ *               Physical address returned by cvmx_srio_phys_map().
+ * @param size   Size used on original call.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h b/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
new file mode 100644
index 0000000..f54e851
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
@@ -0,0 +1,4392 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-sriomaintx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon sriomaintx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SRIOMAINTX_TYPEDEFS_H__
+#define __CVMX_SRIOMAINTX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000008ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000000Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4;
+}
+#else
+#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200080ull;
+}
+#else
+#define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000006Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200070ull;
+}
+#else
+#define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000004ull;
+}
+#else
+#define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000001Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002048ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002040ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002068ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002044ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000206Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002010ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002014ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000201Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002028ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002018ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002008ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000200Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002050ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002054ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000002058ull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000204Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000068ull;
+}
+#else
+#define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000102000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000102004ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107028ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000010702Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107020ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107024ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000010700Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107014ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107010ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107008ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000107004ull;
+}
+#else
+#define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32;
+}
+#else
+#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000058ull;
+}
+#else
+#define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000005Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200004ull;
+}
+#else
+#define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200008ull;
+}
+#else
+#define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000020000Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200050ull;
+}
+#else
+#define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200068ull;
+}
+#else
+#define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000010ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000004Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000015Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000154ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000158ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000140ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000144ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000148ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000013Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000120ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000100ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000124ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000000012Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000060ull;
+}
+#else
+#define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200064ull;
+}
+#else
+#define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000200060ull;
+}
+#else
+#define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000001000ull;
+}
+#else
+#define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id);
+	return 0x0000000000000018ull;
+}
+#else
+#define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id);
+	return 0x000000000020006Cull;
+}
+#else
+#define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull)
+#endif
+
+/**
+ * cvmx_sriomaint#_asmbly_id
+ *
+ * SRIOMAINT_ASMBLY_ID = SRIO Assembly ID
+ *
+ * The Assembly ID register shows the Assembly ID and Vendor
+ *
+ * Notes:
+ * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ASMBLY_ID       hclk    hrst_n
+ */
+union cvmx_sriomaintx_asmbly_id
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_asmbly_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t assy_id                      : 16; /**< Assembly Identifer */
+	uint32_t assy_ven                     : 16; /**< Assembly Vendor Identifer */
+#else
+	uint32_t assy_ven                     : 16;
+	uint32_t assy_id                      : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_asmbly_id_s    cn63xx;
+	struct cvmx_sriomaintx_asmbly_id_s    cn63xxp1;
+};
+typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t;
+
+/**
+ * cvmx_sriomaint#_asmbly_info
+ *
+ * SRIOMAINT_ASMBLY_INFO = SRIO Assembly Information
+ *
+ * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO
+ *
+ * Notes:
+ * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended
+ *  Feature Pointer.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ASMBLY_INFO     hclk    hrst_n
+ */
+union cvmx_sriomaintx_asmbly_info
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_asmbly_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t assy_rev                     : 16; /**< Assembly Revision */
+	uint32_t ext_fptr                     : 16; /**< Pointer to the first entry in the extended feature
+                                                         list. */
+#else
+	uint32_t ext_fptr                     : 16;
+	uint32_t assy_rev                     : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_asmbly_info_s  cn63xx;
+	struct cvmx_sriomaintx_asmbly_info_s  cn63xxp1;
+};
+typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t;
+
+/**
+ * cvmx_sriomaint#_bar1_idx#
+ *
+ * SRIOMAINT_BAR1_IDXX = SRIO BAR1 IndexX Register
+ *
+ * Contains address index and control bits for access to memory ranges of BAR1.
+ *
+ * Notes:
+ * This register specifies the Octeon address, endian swap and cache status associated with each of
+ *  the 16 BAR1 entries.  The local address bits used are based on the BARSIZE field located in the
+ *  SRIOMAINT(0..1)_M2S_BAR1_START0 register.  This register is only writeable over SRIO if the
+ *  SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_BAR1_IDX[0:15]  hclk    hrst_n
+ */
+union cvmx_sriomaintx_bar1_idxx
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_bar1_idxx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t la                           : 22; /**< L2/DRAM Address bits [37:16]
+                                                         Not all LA[21:0] bits are used by SRIO hardware,
+                                                         depending on SRIOMAINT(0..1)_M2S_BAR1_START1[BARSIZE].
+
+                                                                                 Become
+                                                                                 L2/DRAM
+                                                                                 Address  Entry
+                                                         BARSIZE   LA Bits Used   Bits    Size
+                                                            0        LA[21:0]    [37:16]   64KB
+                                                            1        LA[21:1]    [37:17]  128KB
+                                                            2        LA[21:2]    [37:18]  256KB
+                                                            3        LA[21:3]    [37:19]  512KB
+                                                            4        LA[21:4]    [37:20]    1MB
+                                                            5        LA[21:5]    [37:21]    2MB
+                                                            6        LA[21:6]    [37:22]    4MB
+                                                            7        LA[21:7]    [37:23]    8MB
+                                                            8        ** not in pass 1
+                                                            9        ** not in pass 1
+                                                           10        ** not in pass 1
+                                                           11        ** not in pass 1
+                                                           12        ** not in pass 1
+                                                           13        ** not in pass 1 */
+	uint32_t reserved_6_7                 : 2;
+	uint32_t es                           : 2;  /**< Endian Swap Mode.
+                                                         0 = No Swap
+                                                         1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA]
+                                                         2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE]
+                                                         3 = 32-bit Word Exch  [ABCD_EFGH] -> [EFGH_ABCD] */
+	uint32_t nca                          : 1;  /**< Non-Cacheable Access Mode.  When set, transfers
+                                                         through this window are not cacheable. */
+	uint32_t reserved_1_2                 : 2;
+	uint32_t enable                       : 1;  /**< When set the selected index address is valid. */
+#else
+	uint32_t enable                       : 1;
+	uint32_t reserved_1_2                 : 2;
+	uint32_t nca                          : 1;
+	uint32_t es                           : 2;
+	uint32_t reserved_6_7                 : 2;
+	uint32_t la                           : 22;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_sriomaintx_bar1_idxx_s    cn63xx;
+	struct cvmx_sriomaintx_bar1_idxx_s    cn63xxp1;
+};
+typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t;
+
+/**
+ * cvmx_sriomaint#_bell_status
+ *
+ * SRIOMAINT_BELL_STATUS = SRIO Incoming Doorbell Status
+ *
+ * The SRIO Incoming (RX) Doorbell Status
+ *
+ * Notes:
+ * This register displays the status of the doorbells received.  If FULL is set the SRIO device will
+ *  retry incoming transactions.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_BELL_STATUS     hclk    hrst_n
+ */
+union cvmx_sriomaintx_bell_status
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_bell_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_1_31                : 31;
+	uint32_t full                         : 1;  /**< Not able to receive Doorbell Transactions */
+#else
+	uint32_t full                         : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_sriomaintx_bell_status_s  cn63xx;
+	struct cvmx_sriomaintx_bell_status_s  cn63xxp1;
+};
+typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t;
+
+/**
+ * cvmx_sriomaint#_comp_tag
+ *
+ * SRIOMAINT_COMP_TAG = SRIO Component Tag
+ *
+ * Component Tag
+ *
+ * Notes:
+ * This register contains a component tag value for the processing element and the value can be
+ *  assigned by software when the device is initialized.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_COMP_TAG        hclk    hrst_n
+ */
+union cvmx_sriomaintx_comp_tag
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_comp_tag_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t comp_tag                     : 32; /**< Component Tag for Firmware Use */
+#else
+	uint32_t comp_tag                     : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_comp_tag_s     cn63xx;
+	struct cvmx_sriomaintx_comp_tag_s     cn63xxp1;
+};
+typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t;
+
+/**
+ * cvmx_sriomaint#_core_enables
+ *
+ * SRIOMAINT_CORE_ENABLES = SRIO Core Control
+ *
+ * Core Control
+ *
+ * Notes:
+ * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running.
+ *  The bit should be set after the software has initialized the chip to allow memory operations.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_CORE_ENABLES    hclk    hrst_n, srst_n
+ */
+union cvmx_sriomaintx_core_enables
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_core_enables_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t halt                         : 1;  /**< OCTEON currently in Reset
+                                                         0 = All OCTEON resources are available.
+                                                         1 = The OCTEON is in reset. When this bit is set,
+                                                             SRIO maintenance registers can be accessed,
+                                                             but BAR0, BAR1, and BAR2 cannot be. */
+	uint32_t imsg1                        : 1;  /**< Allow Incoming Message Unit 1 Operations
+                                                         Note: This bit is cleared when the C63XX is reset
+                                                          0 = SRIO Incoming Messages to Unit 1 ignored and
+                                                              return error response
+                                                          1 = SRIO Incoming Messages to Unit 1 */
+	uint32_t imsg0                        : 1;  /**< Allow Incoming Message Unit 0 Operations
+                                                         Note: This bit is cleared when the C63XX is reset
+                                                          0 = SRIO Incoming Messages to Unit 0 ignored and
+                                                              return error response
+                                                          1 = SRIO Incoming Messages to Unit 0 */
+	uint32_t doorbell                     : 1;  /**< Allow Inbound Doorbell Operations
+                                                         Note: This bit is cleared when the C63XX is reset
+                                                          0 = SRIO Doorbell OPs ignored and return error
+                                                              response
+                                                          1 = SRIO Doorbell OPs Allowed */
+	uint32_t memory                       : 1;  /**< Allow Inbound/Outbound Memory Operations
+                                                         Note: This bit is cleared when the C63XX is reset
+                                                          0 = SRIO Incoming Nwrites and Swrites are
+                                                              dropped.  Incoming Nreads, Atomics and
+                                                              NwriteRs return responses with ERROR status.
+                                                              SRIO Incoming Maintenance BAR Memory Accesses
+                                                              are processed normally.
+                                                              Outgoing Store Operations are Dropped
+                                                              Outgoing Load Operations are not issued and
+                                                              return all 1's with an ERROR status.
+                                                              In Flight Operations started while the bit is
+                                                              set in both directions will complete normally.
+                                                          1 = SRIO Memory Read/Write OPs Allowed */
+#else
+	uint32_t memory                       : 1;
+	uint32_t doorbell                     : 1;
+	uint32_t imsg0                        : 1;
+	uint32_t imsg1                        : 1;
+	uint32_t halt                         : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_sriomaintx_core_enables_s cn63xx;
+	struct cvmx_sriomaintx_core_enables_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t;
+
+/**
+ * cvmx_sriomaint#_dev_id
+ *
+ * SRIOMAINT_DEV_ID = SRIO Device ID
+ *
+ * The DeviceVendor Identity field identifies the vendor that manufactured the device
+ *
+ * Notes:
+ * This register identifies Cavium Networks and the Product ID.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_DEV_ID  hclk    hrst_n
+ */
+union cvmx_sriomaintx_dev_id
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_dev_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t device                       : 16; /**< Product Identity */
+	uint32_t vendor                       : 16; /**< Cavium Vendor Identity */
+#else
+	uint32_t vendor                       : 16;
+	uint32_t device                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_dev_id_s       cn63xx;
+	struct cvmx_sriomaintx_dev_id_s       cn63xxp1;
+};
+typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t;
+
+/**
+ * cvmx_sriomaint#_dev_rev
+ *
+ * SRIOMAINT_DEV_REV = SRIO Device Revision
+ *
+ * The Device Revision register identifies the chip pass and revision
+ *
+ * Notes:
+ * This register identifies the chip pass and revision derived from the fuses.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_DEV_REV hclk    hrst_n
+ */
+union cvmx_sriomaintx_dev_rev
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_dev_rev_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_8_31                : 24;
+	uint32_t revision                     : 8;  /**< Chip Pass/Revision */
+#else
+	uint32_t revision                     : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_sriomaintx_dev_rev_s      cn63xx;
+	struct cvmx_sriomaintx_dev_rev_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t;
+
+/**
+ * cvmx_sriomaint#_dst_ops
+ *
+ * SRIOMAINT_DST_OPS = SRIO Source Operations
+ *
+ * The logical operations supported from external devices.
+ *
+ * Notes:
+ * The logical operations supported from external devices.   The Destination OPs register shows the
+ *  operations specified in the SRIO(0..1)_IP_FEATURE.OPS register.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_DST_OPS hclk    hrst_n
+ */
+union cvmx_sriomaintx_dst_ops
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_dst_ops_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t gsm_read                     : 1;  /**< PE does not support Read Home operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
+	uint32_t i_read                       : 1;  /**< PE does not support Instruction Read.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */
+	uint32_t rd_own                       : 1;  /**< PE does not support Read for Ownership.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */
+	uint32_t d_invald                     : 1;  /**< PE does not support Data Cache Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */
+	uint32_t castout                      : 1;  /**< PE does not support Castout Operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */
+	uint32_t d_flush                      : 1;  /**< PE does not support Data Cache Flush.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */
+	uint32_t io_read                      : 1;  /**< PE does not support IO Read.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */
+	uint32_t i_invald                     : 1;  /**< PE does not support Instruction Cache Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */
+	uint32_t tlb_inv                      : 1;  /**< PE does not support TLB Entry Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */
+	uint32_t tlb_invs                     : 1;  /**< PE does not support TLB Entry Invalidate Sync.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */
+	uint32_t reserved_16_21               : 6;
+	uint32_t read                         : 1;  /**< PE can support Nread operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */
+	uint32_t write                        : 1;  /**< PE can support Nwrite operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */
+	uint32_t swrite                       : 1;  /**< PE can support Swrite operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */
+	uint32_t write_r                      : 1;  /**< PE can support Write with Response operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */
+	uint32_t msg                          : 1;  /**< PE can support Data Message operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */
+	uint32_t doorbell                     : 1;  /**< PE can support Doorbell operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */
+	uint32_t compswap                     : 1;  /**< PE does not support Atomic Compare and Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */
+	uint32_t testswap                     : 1;  /**< PE does not support Atomic Test and Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */
+	uint32_t atom_inc                     : 1;  /**< PE can support Atomic increment operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */
+	uint32_t atom_dec                     : 1;  /**< PE can support Atomic decrement operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */
+	uint32_t atom_set                     : 1;  /**< PE can support Atomic set operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */
+	uint32_t atom_clr                     : 1;  /**< PE can support Atomic clear operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */
+	uint32_t atom_swp                     : 1;  /**< PE does not support Atomic Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */
+	uint32_t port_wr                      : 1;  /**< PE can Port Write operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t port_wr                      : 1;
+	uint32_t atom_swp                     : 1;
+	uint32_t atom_clr                     : 1;
+	uint32_t atom_set                     : 1;
+	uint32_t atom_dec                     : 1;
+	uint32_t atom_inc                     : 1;
+	uint32_t testswap                     : 1;
+	uint32_t compswap                     : 1;
+	uint32_t doorbell                     : 1;
+	uint32_t msg                          : 1;
+	uint32_t write_r                      : 1;
+	uint32_t swrite                       : 1;
+	uint32_t write                        : 1;
+	uint32_t read                         : 1;
+	uint32_t reserved_16_21               : 6;
+	uint32_t tlb_invs                     : 1;
+	uint32_t tlb_inv                      : 1;
+	uint32_t i_invald                     : 1;
+	uint32_t io_read                      : 1;
+	uint32_t d_flush                      : 1;
+	uint32_t castout                      : 1;
+	uint32_t d_invald                     : 1;
+	uint32_t rd_own                       : 1;
+	uint32_t i_read                       : 1;
+	uint32_t gsm_read                     : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_dst_ops_s      cn63xx;
+	struct cvmx_sriomaintx_dst_ops_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t;
+
+/**
+ * cvmx_sriomaint#_erb_attr_capt
+ *
+ * SRIOMAINT_ERB_ATTR_CAPT = SRIO Attributes Capture
+ *
+ * Attributes Capture
+ *
+ * Notes:
+ * This register contains the information captured during the error.
+ *  The HW will not update this register (i.e. this register is locked) while
+ *  VALID is set in this CSR.
+ *  The HW sets SRIO_INT_REG[PHY_ERB] every time it sets VALID in this CSR.
+ *  To handle the interrupt, the following procedure may be best:
+ *       (1) clear SRIO_INT_REG[PHY_ERB],
+ *       (2) read this CSR, corresponding SRIOMAINT*_ERB_ERR_DET, SRIOMAINT*_ERB_PACK_SYM_CAPT,
+ *           SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3
+ *       (3) Write VALID in this CSR to 0.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_ATTR_CAPT   hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_attr_capt
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_attr_capt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t inf_type                     : 3;  /**< Type of Information Logged.
+                                                         000 - Packet
+                                                         010 - Short Control Symbol
+                                                               (use only first capture register)
+                                                         All Others Reserved */
+	uint32_t err_type                     : 5;  /**< The encoded value of the 31 minus the bit in
+                                                         SRIOMAINT(0..1)_ERB_ERR_DET that describes the error
+                                                         captured in SRIOMAINT(0..1)_ERB_*CAPT Registers.
+                                                         (For example a value of 5 indicates 31-5 = bit 26) */
+	uint32_t err_info                     : 20; /**< Error Info.  (Pass 2)
+                                                         ERR_TYPE Bits   Description
+                                                            0     23     TX Protocol Error
+                                                                  22     RX Protocol Error
+                                                                  21     TX Link Response Timeout
+                                                                  20     TX ACKID Timeout
+                                                                  - 19:16  Reserved
+                                                                  - 15:12  TX Protocol ID
+                                                                         1 = Rcvd Unexpected Link Response
+                                                                         2 = Rcvd Link Response before Req
+                                                                         3 = Rcvd NACK servicing NACK
+                                                                         4 = Rcvd NACK
+                                                                         5 = Rcvd RETRY servicing RETRY
+                                                                         6 = Rcvd RETRY servicing NACK
+                                                                         7 = Rcvd ACK servicing RETRY
+                                                                         8 = Rcvd ACK servicing NACK
+                                                                         9 = Unexp ACKID on ACK or RETRY
+                                                                        10 = Unexp ACK or RETRY
+                                                                  - 11:8   Reserved
+                                                                  - 7:4   RX Protocol ID
+                                                                         1 = Rcvd EOP w/o Prev SOP
+                                                                         2 = Rcvd STOMP w/o Prev SOP
+                                                                         3 = Unexp RESTART
+                                                                         4 = Redundant Status from LinkReq
+                                                          9-16    23:20  RX K Bits
+                                                                  - 19:0   Reserved
+                                                           26     23:20  RX K Bits
+                                                                  - 19:0   Reserved
+                                                           27     23:12  Type
+                                                                           0x000 TX
+                                                                           0x010 RX
+                                                                  - 11:8   RX or TX Protocol ID (see above)
+                                                                  - 7:4   Reserved
+                                                           30     23:20  RX K Bits
+                                                                  - 19:0   Reserved
+                                                           31     23:16  ACKID Timeout 0x2
+                                                                  - 15:14  Reserved
+                                                                  - 13:8   AckID
+                                                                  - 7:4   Reserved
+                                                           All others ERR_TYPEs are reserved. */
+	uint32_t reserved_1_3                 : 3;
+	uint32_t valid                        : 1;  /**< This bit is set by hardware to indicate that the
+                                                         Packet/control symbol capture registers contain
+                                                         valid information. For control symbols, only
+                                                         capture register 0 will contain meaningful
+                                                         information.  This bit must be cleared by software
+                                                         to allow capture of other errors. */
+#else
+	uint32_t valid                        : 1;
+	uint32_t reserved_1_3                 : 3;
+	uint32_t err_info                     : 20;
+	uint32_t err_type                     : 5;
+	uint32_t inf_type                     : 3;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_attr_capt_s cn63xx;
+	struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t inf_type                     : 3;  /**< Type of Information Logged.
+                                                         000 - Packet
+                                                         010 - Short Control Symbol
+                                                               (use only first capture register)
+                                                         All Others Reserved */
+	uint32_t err_type                     : 5;  /**< The encoded value of the 31 minus the bit in
+                                                         SRIOMAINT(0..1)_ERB_ERR_DET that describes the error
+                                                         captured in SRIOMAINT(0..1)_ERB_*CAPT Registers.
+                                                         (For example a value of 5 indicates 31-5 = bit 26) */
+	uint32_t reserved_1_23                : 23;
+	uint32_t valid                        : 1;  /**< This bit is set by hardware to indicate that the
+                                                         Packet/control symbol capture registers contain
+                                                         valid information. For control symbols, only
+                                                         capture register 0 will contain meaningful
+                                                         information.  This bit must be cleared by software
+                                                         to allow capture of other errors. */
+#else
+	uint32_t valid                        : 1;
+	uint32_t reserved_1_23                : 23;
+	uint32_t err_type                     : 5;
+	uint32_t inf_type                     : 3;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t;
+
+/**
+ * cvmx_sriomaint#_erb_err_det
+ *
+ * SRIOMAINT_ERB_ERR_DET = SRIO Error Detect
+ *
+ * Error Detect
+ *
+ * Notes:
+ * The Error Detect Register indicates physical layer transmission errors detected by the hardware.
+ *  The HW will not update this register (i.e. this register is locked) while
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_DET     hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_err_det
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_err_det_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t imp_err                      : 1;  /**< Implementation Specific Error added for Pass 2. */
+	uint32_t reserved_23_30               : 8;
+	uint32_t ctl_crc                      : 1;  /**< Received a control symbol with a bad CRC value
+                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t uns_id                       : 1;  /**< Received an acknowledge control symbol with an
+                                                         unexpected ackID (packet-accepted or packet_retry)
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t nack                         : 1;  /**< Received packet-not-accepted acknowledge control
+                                                         symbols.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t out_ack                      : 1;  /**< Received packet with unexpected ackID value
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t pkt_crc                      : 1;  /**< Received a packet with a bad CRC value
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t size                         : 1;  /**< Received packet which exceeds the maximum allowed
+                                                         size of 276 bytes.
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t inv_char                     : 1;  /**< Received illegal, 8B/10B error  or undefined
+                                                         codegroup within a packet.  (Pass 2)
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t inv_data                     : 1;  /**< Received data codegroup or 8B/10B error within an
+                                                         IDLE sequence.  (Pass 2)
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t reserved_6_14                : 9;
+	uint32_t bad_ack                      : 1;  /**< Link_response received with an ackID that is not
+                                                         outstanding.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t proterr                      : 1;  /**< An unexpected packet or control symbol was
+                                                         received.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t f_toggle                     : 1;  /**< Reserved. */
+	uint32_t del_err                      : 1;  /**< Received illegal or undefined codegroup.
+                                                         (either INV_DATA or INV_CHAR) (Pass 2)
+                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t uns_ack                      : 1;  /**< An unexpected acknowledge control symbol was
+                                                         received.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t lnk_tout                     : 1;  /**< An acknowledge or link-response control symbol is
+                                                         not received within the specified timeout interval
+                                                         Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+#else
+	uint32_t lnk_tout                     : 1;
+	uint32_t uns_ack                      : 1;
+	uint32_t del_err                      : 1;
+	uint32_t f_toggle                     : 1;
+	uint32_t proterr                      : 1;
+	uint32_t bad_ack                      : 1;
+	uint32_t reserved_6_14                : 9;
+	uint32_t inv_data                     : 1;
+	uint32_t inv_char                     : 1;
+	uint32_t size                         : 1;
+	uint32_t pkt_crc                      : 1;
+	uint32_t out_ack                      : 1;
+	uint32_t nack                         : 1;
+	uint32_t uns_id                       : 1;
+	uint32_t ctl_crc                      : 1;
+	uint32_t reserved_23_30               : 8;
+	uint32_t imp_err                      : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_err_det_s  cn63xx;
+	struct cvmx_sriomaintx_erb_err_det_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_23_31               : 9;
+	uint32_t ctl_crc                      : 1;  /**< Received a control symbol with a bad CRC value
+                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t uns_id                       : 1;  /**< Received an acknowledge control symbol with an
+                                                         unexpected ackID (packet-accepted or packet_retry)
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t nack                         : 1;  /**< Received packet-not-accepted acknowledge control
+                                                         symbols.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t out_ack                      : 1;  /**< Received packet with unexpected ackID value
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t pkt_crc                      : 1;  /**< Received a packet with a bad CRC value
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t size                         : 1;  /**< Received packet which exceeds the maximum allowed
+                                                         size of 276 bytes.
+                                                         Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t reserved_6_16                : 11;
+	uint32_t bad_ack                      : 1;  /**< Link_response received with an ackID that is not
+                                                         outstanding.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t proterr                      : 1;  /**< An unexpected packet or control symbol was
+                                                         received.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t f_toggle                     : 1;  /**< Reserved. */
+	uint32_t del_err                      : 1;  /**< Received illegal or undefined codegroup.
+                                                         (either INV_DATA or INV_CHAR) (Pass 2)
+                                                         Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t uns_ack                      : 1;  /**< An unexpected acknowledge control symbol was
+                                                         received.
+                                                         Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+	uint32_t lnk_tout                     : 1;  /**< An acknowledge or link-response control symbol is
+                                                         not received within the specified timeout interval
+                                                         Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
+#else
+	uint32_t lnk_tout                     : 1;
+	uint32_t uns_ack                      : 1;
+	uint32_t del_err                      : 1;
+	uint32_t f_toggle                     : 1;
+	uint32_t proterr                      : 1;
+	uint32_t bad_ack                      : 1;
+	uint32_t reserved_6_16                : 11;
+	uint32_t size                         : 1;
+	uint32_t pkt_crc                      : 1;
+	uint32_t out_ack                      : 1;
+	uint32_t nack                         : 1;
+	uint32_t uns_id                       : 1;
+	uint32_t ctl_crc                      : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t;
+
+/**
+ * cvmx_sriomaint#_erb_err_rate
+ *
+ * SRIOMAINT_ERB_ERR_RATE = SRIO Error Rate
+ *
+ * Error Rate
+ *
+ * Notes:
+ * The Error Rate register is used with the Error Rate Threshold register to monitor and control the
+ *  reporting of transmission errors.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE    hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_err_rate
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_err_rate_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t err_bias                     : 8;  /**< These bits provide the error rate bias value.
+                                                         0x00 - do not decrement the error rate counter
+                                                         0x01 - decrement every 1ms (+/-34%)
+                                                         0x02 - decrement every 10ms (+/-34%)
+                                                         0x04 - decrement every 100ms (+/-34%)
+                                                         0x08 - decrement every 1s (+/-34%)
+                                                         0x10 - decrement every 10s (+/-34%)
+                                                         0x20 - decrement every 100s (+/-34%)
+                                                         0x40 - decrement every 1000s (+/-34%)
+                                                         0x80 - decrement every 10000s (+/-34%)
+                                                         All other values are reserved */
+	uint32_t reserved_18_23               : 6;
+	uint32_t rate_lim                     : 2;  /**< These bits limit the incrementing of the error
+                                                         rate counter above the failed threshold trigger.
+                                                           00 - only count 2 errors above
+                                                           01 - only count 4 errors above
+                                                           10 - only count 16 error above
+                                                           11 - do not limit incrementing the error rate ct */
+	uint32_t pk_rate                      : 8;  /**< Peak Value attainted by the error rate counter */
+	uint32_t rate_cnt                     : 8;  /**< These bits maintain a count of the number of
+                                                         transmission errors that have been detected by the
+                                                         port, decremented by the Error Rate Bias
+                                                         mechanism, to create an indication of the link
+                                                         error rate. */
+#else
+	uint32_t rate_cnt                     : 8;
+	uint32_t pk_rate                      : 8;
+	uint32_t rate_lim                     : 2;
+	uint32_t reserved_18_23               : 6;
+	uint32_t err_bias                     : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_err_rate_s cn63xx;
+	struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t;
+
+/**
+ * cvmx_sriomaint#_erb_err_rate_en
+ *
+ * SRIOMAINT_ERB_ERR_RATE_EN = SRIO Error Rate Enable
+ *
+ * Error Rate Enable
+ *
+ * Notes:
+ * This register contains the bits that control when an error condition is allowed to increment the
+ *  error rate counter in the Error Rate Threshold Register and lock the Error Capture registers.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE_EN hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_err_rate_en
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_err_rate_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t imp_err                      : 1;  /**< Enable Implementation Specific Error (Pass 2). */
+	uint32_t reserved_23_30               : 8;
+	uint32_t ctl_crc                      : 1;  /**< Enable error rate counting of control symbols with
+                                                         bad CRC values */
+	uint32_t uns_id                       : 1;  /**< Enable error rate counting of acknowledge control
+                                                         symbol with unexpected ackIDs
+                                                         (packet-accepted or packet_retry) */
+	uint32_t nack                         : 1;  /**< Enable error rate counting of packet-not-accepted
+                                                         acknowledge control symbols. */
+	uint32_t out_ack                      : 1;  /**< Enable error rate counting of received packet with
+                                                         unexpected ackID value */
+	uint32_t pkt_crc                      : 1;  /**< Enable error rate counting of received a packet
+                                                         with a bad CRC value */
+	uint32_t size                         : 1;  /**< Enable error rate counting of received packet
+                                                         which exceeds the maximum size of 276 bytes. */
+	uint32_t inv_char                     : 1;  /**< Enable error rate counting of received illegal
+                                                         illegal, 8B/10B error or undefined codegroup
+                                                         within a packet.  (Pass 2) */
+	uint32_t inv_data                     : 1;  /**< Enable error rate counting of received data
+                                                         codegroup or 8B/10B error within IDLE sequence.
+                                                         (Pass 2) */
+	uint32_t reserved_6_14                : 9;
+	uint32_t bad_ack                      : 1;  /**< Enable error rate counting of link_responses with
+                                                         an ackID that is not outstanding. */
+	uint32_t proterr                      : 1;  /**< Enable error rate counting of unexpected packet or
+                                                         control symbols received. */
+	uint32_t f_toggle                     : 1;  /**< Reserved. */
+	uint32_t del_err                      : 1;  /**< Enable error rate counting of illegal or undefined
+                                                         codegroups (either INV_DATA or INV_CHAR). (Pass 2) */
+	uint32_t uns_ack                      : 1;  /**< Enable error rate counting of unexpected
+                                                         acknowledge control symbols received. */
+	uint32_t lnk_tout                     : 1;  /**< Enable error rate counting of acknowledge or
+                                                         link-response control symbols not received within
+                                                         the specified timeout interval */
+#else
+	uint32_t lnk_tout                     : 1;
+	uint32_t uns_ack                      : 1;
+	uint32_t del_err                      : 1;
+	uint32_t f_toggle                     : 1;
+	uint32_t proterr                      : 1;
+	uint32_t bad_ack                      : 1;
+	uint32_t reserved_6_14                : 9;
+	uint32_t inv_data                     : 1;
+	uint32_t inv_char                     : 1;
+	uint32_t size                         : 1;
+	uint32_t pkt_crc                      : 1;
+	uint32_t out_ack                      : 1;
+	uint32_t nack                         : 1;
+	uint32_t uns_id                       : 1;
+	uint32_t ctl_crc                      : 1;
+	uint32_t reserved_23_30               : 8;
+	uint32_t imp_err                      : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx;
+	struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_23_31               : 9;
+	uint32_t ctl_crc                      : 1;  /**< Enable error rate counting of control symbols with
+                                                         bad CRC values */
+	uint32_t uns_id                       : 1;  /**< Enable error rate counting of acknowledge control
+                                                         symbol with unexpected ackIDs
+                                                         (packet-accepted or packet_retry) */
+	uint32_t nack                         : 1;  /**< Enable error rate counting of packet-not-accepted
+                                                         acknowledge control symbols. */
+	uint32_t out_ack                      : 1;  /**< Enable error rate counting of received packet with
+                                                         unexpected ackID value */
+	uint32_t pkt_crc                      : 1;  /**< Enable error rate counting of received a packet
+                                                         with a bad CRC value */
+	uint32_t size                         : 1;  /**< Enable error rate counting of received packet
+                                                         which exceeds the maximum size of 276 bytes. */
+	uint32_t reserved_6_16                : 11;
+	uint32_t bad_ack                      : 1;  /**< Enable error rate counting of link_responses with
+                                                         an ackID that is not outstanding. */
+	uint32_t proterr                      : 1;  /**< Enable error rate counting of unexpected packet or
+                                                         control symbols received. */
+	uint32_t f_toggle                     : 1;  /**< Reserved. */
+	uint32_t del_err                      : 1;  /**< Enable error rate counting of illegal or undefined
+                                                         codegroups (either INV_DATA or INV_CHAR). (Pass 2) */
+	uint32_t uns_ack                      : 1;  /**< Enable error rate counting of unexpected
+                                                         acknowledge control symbols received. */
+	uint32_t lnk_tout                     : 1;  /**< Enable error rate counting of acknowledge or
+                                                         link-response control symbols not received within
+                                                         the specified timeout interval */
+#else
+	uint32_t lnk_tout                     : 1;
+	uint32_t uns_ack                      : 1;
+	uint32_t del_err                      : 1;
+	uint32_t f_toggle                     : 1;
+	uint32_t proterr                      : 1;
+	uint32_t bad_ack                      : 1;
+	uint32_t reserved_6_16                : 11;
+	uint32_t size                         : 1;
+	uint32_t pkt_crc                      : 1;
+	uint32_t out_ack                      : 1;
+	uint32_t nack                         : 1;
+	uint32_t uns_id                       : 1;
+	uint32_t ctl_crc                      : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t;
+
+/**
+ * cvmx_sriomaint#_erb_err_rate_thr
+ *
+ * SRIOMAINT_ERB_ERR_RATE_THR = SRIO Error Rate Threshold
+ *
+ * Error Rate Threshold
+ *
+ * Notes:
+ * The Error Rate Threshold register is used to control the reporting of errors to the link status.
+ *  Typically the Degraded Threshold is less than the Fail Threshold.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_ERR_RATE_THR        hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_err_rate_thr
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_err_rate_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t fail_th                      : 8;  /**< These bits provide the threshold value for
+                                                         reporting an error condition due to a possibly
+                                                         broken link.
+                                                           0x00 - Disable the Error Rate Failed Threshold
+                                                                  Trigger
+                                                           0x01 - Set the error reporting threshold to 1
+                                                           0x02 - Set the error reporting threshold to 2
+                                                           - ...
+                                                           0xFF - Set the error reporting threshold to 255 */
+	uint32_t dgrad_th                     : 8;  /**< These bits provide the threshold value for
+                                                         reporting an error condition due to a possibly
+                                                         degrading link.
+                                                           0x00 - Disable the Degrade Rate Failed Threshold
+                                                                  Trigger
+                                                           0x01 - Set the error reporting threshold to 1
+                                                           0x02 - Set the error reporting threshold to 2
+                                                           - ...
+                                                           0xFF - Set the error reporting threshold to 255 */
+	uint32_t reserved_0_15                : 16;
+#else
+	uint32_t reserved_0_15                : 16;
+	uint32_t dgrad_th                     : 8;
+	uint32_t fail_th                      : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx;
+	struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t;
+
+/**
+ * cvmx_sriomaint#_erb_hdr
+ *
+ * SRIOMAINT_ERB_HDR = SRIO Error Reporting Block Header
+ *
+ * Error Reporting Block Header
+ *
+ * Notes:
+ * The error management extensions block header register contains the EF_PTR to the next EF_BLK and
+ *  the EF_ID that identifies this as the error management extensions block header. In this
+ *  implementation this is the last block and therefore the EF_PTR is a NULL pointer.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_HDR hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_hdr
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ef_ptr                       : 16; /**< Pointer to the next block in the extended features
+                                                         data structure. */
+	uint32_t ef_id                        : 16; /**< Single Port ID */
+#else
+	uint32_t ef_id                        : 16;
+	uint32_t ef_ptr                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_hdr_s      cn63xx;
+	struct cvmx_sriomaintx_erb_hdr_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_addr_capt_h
+ *
+ * SRIOMAINT_ERB_LT_ADDR_CAPT_H = SRIO Logical/Transport Layer High Address Capture
+ *
+ * Logical/Transport Layer High Address Capture
+ *
+ * Notes:
+ * This register contains error information. It is locked when a Logical/Transport error is detected
+ *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be
+ *  written only when error detection is disabled.  This register is only required for end point
+ *  transactions of 50 or 66 bits.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_H      hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_addr_capt_h
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr                         : 32; /**< Most significant 32 bits of the address associated
+                                                         with the error. Information supplied for requests
+                                                         and responses if available. */
+#else
+	uint32_t addr                         : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_addr_capt_l
+ *
+ * SRIOMAINT_ERB_LT_ADDR_CAPT_L = SRIO Logical/Transport Layer Low Address Capture
+ *
+ * Logical/Transport Layer Low Address Capture
+ *
+ * Notes:
+ * This register contains error information. It is locked when a Logical/Transport error is detected
+ *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  written only when error detection is disabled.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_L      hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_addr_capt_l
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr                         : 29; /**< Least significant 29 bits of the address
+                                                         associated with the error.  Bits 31:24 specify the
+                                                         request HOP count for Maintenance Operations.
+                                                         Information supplied for requests and responses if
+                                                         available. */
+	uint32_t reserved_2_2                 : 1;
+	uint32_t xaddr                        : 2;  /**< Extended address bits of the address associated
+                                                         with the error.  Information supplied for requests
+                                                         and responses if available. */
+#else
+	uint32_t xaddr                        : 2;
+	uint32_t reserved_2_2                 : 1;
+	uint32_t addr                         : 29;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_ctrl_capt
+ *
+ * SRIOMAINT_ERB_LT_CTRL_CAPT = SRIO Logical/Transport Layer Control Capture
+ *
+ * Logical/Transport Layer Control Capture
+ *
+ * Notes:
+ * This register contains error information. It is locked when a Logical/Transport error is detected
+ *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  written only when error detection is disabled.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_CTRL_CAPT        hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_ctrl_capt
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ftype                        : 4;  /**< Format Type associated with the error */
+	uint32_t ttype                        : 4;  /**< Transaction Type associated with the error
+                                                         (For Messages)
+                                                         Message Length */
+	uint32_t extra                        : 8;  /**< Additional Information
+                                                         (For Messages)
+                                                         - 23:22 Letter
+                                                         - 21:20 Mbox
+                                                         - 19:16 Msgseg/xmbox
+                                                         Information for the last message request sent
+                                                         for the mailbox that had an error
+                                                         (For Responses)
+                                                         - 23:20 Response Request FTYPE
+                                                         - 19:16 Response Request TTYPE
+                                                         (For all other types)
+                                                         Reserved. */
+	uint32_t status                       : 4;  /**< Response Status.
+                                                         (For all other Requests)
+                                                         Reserved. */
+	uint32_t size                         : 4;  /**< Size associated with the transaction. */
+	uint32_t tt                           : 1;  /**< Transfer Type 0=ID8, 1=ID16. */
+	uint32_t wdptr                        : 1;  /**< Word Pointer associated with the error. */
+	uint32_t reserved_5_5                 : 1;
+	uint32_t capt_idx                     : 5;  /**< Capture Index. 31 - Bit set in
+                                                         SRIOMAINT(0..1)_ERB_LT_ERR_DET. */
+#else
+	uint32_t capt_idx                     : 5;
+	uint32_t reserved_5_5                 : 1;
+	uint32_t wdptr                        : 1;
+	uint32_t tt                           : 1;
+	uint32_t size                         : 4;
+	uint32_t status                       : 4;
+	uint32_t extra                        : 8;
+	uint32_t ttype                        : 4;
+	uint32_t ftype                        : 4;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_dev_id
+ *
+ * SRIOMAINT_ERB_LT_DEV_ID = SRIO Port-write Target deviceID
+ *
+ * Port-write Target deviceID
+ *
+ * Notes:
+ * This SRIO interface does not support generating Port-Writes based on ERB Errors.  This register is
+ *  currently unused and should be treated as reserved.
+ *
+ * Clk_Rst:        SRIOMAINT_ERB_LT_DEV_ID hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_dev_id
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_dev_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t id16                         : 8;  /**< This is the most significant byte of the
+                                                         port-write destination deviceID (large transport
+                                                         systems only)
+                                                         destination ID used for Port Write errors */
+	uint32_t id8                          : 8;  /**< This is the port-write destination deviceID */
+	uint32_t tt                           : 1;  /**< Transport Type used for Port Write
+                                                         0 = Small Transport, ID8 Only
+                                                         1 = Large Transport, ID16 and ID8 */
+	uint32_t reserved_0_14                : 15;
+#else
+	uint32_t reserved_0_14                : 15;
+	uint32_t tt                           : 1;
+	uint32_t id8                          : 8;
+	uint32_t id16                         : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_dev_id_capt
+ *
+ * SRIOMAINT_ERB_LT_DEV_ID_CAPT = SRIO Logical/Transport Layer Device ID Capture
+ *
+ * Logical/Transport Layer Device ID Capture
+ *
+ * Notes:
+ * This register contains error information. It is locked when a Logical/Transport error is detected
+ *  and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero.  This register should be
+ *  written only when error detection is disabled.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_DEV_ID_CAPT      hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_dev_id_capt
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dst_id16                     : 8;  /**< Most significant byte of the large transport
+                                                         destination ID associated with the error */
+	uint32_t dst_id8                      : 8;  /**< Least significant byte of the large transport
+                                                         destination ID or the 8-bit small transport
+                                                         destination ID associated with the error */
+	uint32_t src_id16                     : 8;  /**< Most significant byte of the large transport
+                                                         source ID associated with the error */
+	uint32_t src_id8                      : 8;  /**< Least significant byte of the large transport
+                                                         source ID or the 8-bit small transport source ID
+                                                         associated with the error */
+#else
+	uint32_t src_id8                      : 8;
+	uint32_t src_id16                     : 8;
+	uint32_t dst_id8                      : 8;
+	uint32_t dst_id16                     : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_err_det
+ *
+ * SRIOMAINT_ERB_LT_ERR_DET = SRIO Logical/Transport Layer Error Detect
+ *
+ * SRIO Logical/Transport Layer Error Detect
+ *
+ * Notes:
+ * This register indicates the error that was detected by the Logical or Transport logic layer.
+ *  Once a bit is set in this CSR, HW will lock the register until SW writes a zero to clear all the
+ *  fields.  The HW sets SRIO_INT_REG[LOG_ERB] every time it sets one of the bits.
+ *  To handle the interrupt, the following procedure may be best:
+ *       (1) clear SRIO_INT_REG[LOG_ERB],
+ *       (2) read this CSR, corresponding SRIOMAINT*_ERB_LT_ADDR_CAPT_H, SRIOMAINT*_ERB_LT_ADDR_CAPT_L,
+ *           SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT
+ *       (3) Write this CSR to 0.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ERR_DET  hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_err_det
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_err_det_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t io_err                       : 1;  /**< Received a response of ERROR for an IO Logical
+                                                         Layer Request.  This includes all Maintenance and
+                                                         Memory Responses not destined for the RX Soft
+                                                         Packet FIFO. When SRIO receives an ERROR response
+                                                         for a read, the issuing core or DPI DMA engine
+                                                         receives result bytes with all bits set. In the
+                                                         case of writes with response, this bit is the only
+                                                         indication of failure. */
+	uint32_t msg_err                      : 1;  /**< Received a response of ERROR for an outgoing
+                                                         message segment. This bit is the only direct
+                                                         indication of a MSG_ERR. When a MSG_ERR occurs,
+                                                         SRIO drops the message segment and will not set
+                                                         SRIO*_INT_REG[OMSG*] after the message
+                                                         "transfer". NOTE: SRIO can continue to send or
+                                                         retry other segments from the same message after
+                                                         a MSG_ERR. */
+	uint32_t gsm_err                      : 1;  /**< Received a response of ERROR for an GSM Logical
+                                                         Request.  SRIO hardware never sets this bit. GSM
+                                                         operations are not supported (outside of the Soft
+                                                         Packet FIFO). */
+	uint32_t msg_fmt                      : 1;  /**< Received an incoming Message Segment with a
+                                                         formating error.  A MSG_FMT error occurs when SRIO
+                                                         receives a message segment with a reserved SSIZE,
+                                                         or a illegal data payload size, or a MSGSEG greater
+                                                         than MSGLEN, or a MSGSEG that is the duplicate of
+                                                         one already received by an inflight message.
+                                                         When a non-duplicate MSG_FMT error occurs, SRIO
+                                                         drops the segment and sends an ERROR response.
+                                                         When a duplicate MSG_FMT error occurs, SRIO
+                                                         (internally) terminates the currently-inflight
+                                                         message with an error and processes the duplicate,
+                                                         which may result in a new message being generated
+                                                         internally for the duplicate. */
+	uint32_t ill_tran                     : 1;  /**< Received illegal fields in the request/response
+                                                         packet for a supported transaction or any packet
+                                                         with a reserved transaction type. When an ILL_TRAN
+                                                         error occurs, SRIO ignores the packet. ILL_TRAN
+                                                         errors are 2nd priority after ILL_TGT and may mask
+                                                         other problems. Packets with ILL_TRAN errors cannot
+                                                         enter the RX Soft Packet FIFO.
+                                                         There are two things that can set ILL_TRAN:
+                                                         (1) SRIO received a packet with a tt value is not
+                                                         0 or 1, or (2) SRIO received a response to an
+                                                         outstanding message segment whose status was not
+                                                         DONE, RETRY, or ERROR. */
+	uint32_t ill_tgt                      : 1;  /**< Received a packet that contained a destination ID
+                                                         other than SRIOMAINT*_PRI_DEV_ID or
+                                                         SRIOMAINT*_SEC_DEV_ID. When an ILL_TGT error
+                                                         occurs, SRIO drops the packet. ILL_TGT errors are
+                                                         highest priority, so may mask other problems.
+                                                         Packets with ILL_TGT errors cannot enter the RX
+                                                         soft packet fifo. */
+	uint32_t msg_tout                     : 1;  /**< An expected incoming message request has not been
+                                                         received within the time-out interval specified in
+                                                         SRIOMAINT(0..1)_PORT_RT_CTL. When a MSG_TOUT occurs,
+                                                         SRIO (internally) terminates the inflight message
+                                                         with an error. */
+	uint32_t pkt_tout                     : 1;  /**< A required response has not been received to an
+                                                         outgoing memory, maintenance or message request
+                                                         before the time-out interval specified in
+                                                         SRIOMAINT(0..1)_PORT_RT_CTL.  When an IO or maintenance
+                                                         read request operation has a PKT_TOUT, the issuing
+                                                         core load or DPI DMA engine receive all ones for
+                                                         the result. When an IO NWRITE_R has a PKT_TOUT,
+                                                         this bit is the only indication of failure. When a
+                                                         message request operation has a PKT_TOUT, SRIO
+                                                         discards the the outgoing message segment,  and
+                                                         this bit is the only direct indication of failure.
+                                                         NOTE: SRIO may continue to send or retry other
+                                                         segments from the same message. When one or more of
+                                                         the segments in an outgoing message have a
+                                                         PKT_TOUT, SRIO will not set SRIO*_INT_REG[OMSG*]
+                                                         after the message "transfer". */
+	uint32_t uns_resp                     : 1;  /**< An unsolicited/unexpected memory, maintenance or
+                                                         message response packet was received that was not
+                                                         destined for the RX Soft Packet FIFO.  When this
+                                                         condition is detected, the packet is dropped. */
+	uint32_t uns_tran                     : 1;  /**< A transaction is received that is not supported.
+                                                         SRIO HW will never set this bit - SRIO routes all
+                                                         unsupported transactions to the RX soft packet
+                                                         FIFO. */
+	uint32_t reserved_1_21                : 21;
+	uint32_t resp_sz                      : 1;  /**< Received an incoming Memory or Maintenance
+                                                         Read response packet with a DONE status and less
+                                                         data then expected.  This condition causes the
+                                                         Read to be completed and an error response to be
+                                                         returned with all the data bits set to the issuing
+                                                         Core or DMA Engine. */
+#else
+	uint32_t resp_sz                      : 1;
+	uint32_t reserved_1_21                : 21;
+	uint32_t uns_tran                     : 1;
+	uint32_t uns_resp                     : 1;
+	uint32_t pkt_tout                     : 1;
+	uint32_t msg_tout                     : 1;
+	uint32_t ill_tgt                      : 1;
+	uint32_t ill_tran                     : 1;
+	uint32_t msg_fmt                      : 1;
+	uint32_t gsm_err                      : 1;
+	uint32_t msg_err                      : 1;
+	uint32_t io_err                       : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t;
+
+/**
+ * cvmx_sriomaint#_erb_lt_err_en
+ *
+ * SRIOMAINT_ERB_LT_ERR_EN = SRIO Logical/Transport Layer Error Enable
+ *
+ * SRIO Logical/Transport Layer Error Enable
+ *
+ * Notes:
+ * This register contains the bits that control if an error condition locks the Logical/Transport
+ *  Layer Error Detect and Capture registers and is reported to the system host.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_LT_ERR_EN   hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_lt_err_en
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_lt_err_en_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t io_err                       : 1;  /**< Enable reporting of an IO error response. Save and
+                                                         lock original request transaction information in
+                                                         all Logical/Transport Layer Capture CSRs. */
+	uint32_t msg_err                      : 1;  /**< Enable reporting of a Message error response. Save
+                                                         and lock original request transaction information
+                                                         in all Logical/Transport Layer Capture CSRs. */
+	uint32_t gsm_err                      : 1;  /**< Enable reporting of a GSM error response. Save and
+                                                         lock original request transaction capture
+                                                         information in all Logical/Transport Layer Capture
+                                                         CSRs. */
+	uint32_t msg_fmt                      : 1;  /**< Enable reporting of a message format error. Save
+                                                         and lock transaction capture information in
+                                                         Logical/Transport Layer Device ID and Control
+                                                         Capture CSRs. */
+	uint32_t ill_tran                     : 1;  /**< Enable reporting of an illegal transaction decode
+                                                         error Save and lock transaction capture
+                                                         information in Logical/Transport Layer Device ID
+                                                         and Control Capture CSRs. */
+	uint32_t ill_tgt                      : 1;  /**< Enable reporting of an illegal transaction target
+                                                         error. Save and lock transaction capture
+                                                         information in Logical/Transport Layer Device ID
+                                                         and Control Capture CSRs. */
+	uint32_t msg_tout                     : 1;  /**< Enable reporting of a Message Request time-out
+                                                         error. Save and lock transaction capture
+                                                         information in Logical/Transport Layer Device ID
+                                                         and Control Capture CSRs for the last Message
+                                                         request segment packet received. */
+	uint32_t pkt_tout                     : 1;  /**< Enable reporting of a packet response time-out
+                                                         error.  Save and lock original request address in
+                                                         Logical/Transport Layer Address Capture CSRs.
+                                                         Save and lock original request Destination ID in
+                                                         Logical/Transport Layer Device ID Capture CSR. */
+	uint32_t uns_resp                     : 1;  /**< Enable reporting of an unsolicited response error.
+                                                         Save and lock transaction capture information in
+                                                         Logical/Transport Layer Device ID and Control
+                                                         Capture CSRs. */
+	uint32_t uns_tran                     : 1;  /**< Enable reporting of an unsupported transaction
+                                                         error.  Save and lock transaction capture
+                                                         information in Logical/Transport Layer Device ID
+                                                         and Control Capture CSRs. */
+	uint32_t reserved_1_21                : 21;
+	uint32_t resp_sz                      : 1;  /**< Enable reporting of an incoming response with
+                                                         unexpected data size */
+#else
+	uint32_t resp_sz                      : 1;
+	uint32_t reserved_1_21                : 21;
+	uint32_t uns_tran                     : 1;
+	uint32_t uns_resp                     : 1;
+	uint32_t pkt_tout                     : 1;
+	uint32_t msg_tout                     : 1;
+	uint32_t ill_tgt                      : 1;
+	uint32_t ill_tran                     : 1;
+	uint32_t msg_fmt                      : 1;
+	uint32_t gsm_err                      : 1;
+	uint32_t msg_err                      : 1;
+	uint32_t io_err                       : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx;
+	struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t;
+
+/**
+ * cvmx_sriomaint#_erb_pack_capt_1
+ *
+ * SRIOMAINT_ERB_PACK_CAPT_1 = SRIO Packet Capture 1
+ *
+ * Packet Capture 1
+ *
+ * Notes:
+ * Error capture register 1 contains either long symbol capture information or bytes 4 through 7 of
+ *  the packet header.
+ *  The HW will not update this register (i.e. this register is locked) while
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_1 hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_pack_capt_1
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_pack_capt_1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t capture                      : 32; /**< Bytes 4 thru 7 of the packet header. */
+#else
+	uint32_t capture                      : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx;
+	struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t;
+
+/**
+ * cvmx_sriomaint#_erb_pack_capt_2
+ *
+ * SRIOMAINT_ERB_PACK_CAPT_2 = SRIO Packet Capture 2
+ *
+ * Packet Capture 2
+ *
+ * Notes:
+ * Error capture register 2 contains bytes 8 through 11 of the packet header.
+ *  The HW will not update this register (i.e. this register is locked) while
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_2 hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_pack_capt_2
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_pack_capt_2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t capture                      : 32; /**< Bytes 8 thru 11 of the packet header. */
+#else
+	uint32_t capture                      : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx;
+	struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t;
+
+/**
+ * cvmx_sriomaint#_erb_pack_capt_3
+ *
+ * SRIOMAINT_ERB_PACK_CAPT_3 = SRIO Packet Capture 3
+ *
+ * Packet Capture 3
+ *
+ * Notes:
+ * Error capture register 3 contains bytes 12 through 15 of the packet header.
+ *  The HW will not update this register (i.e. this register is locked) while
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_CAPT_3 hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_pack_capt_3
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_pack_capt_3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t capture                      : 32; /**< Bytes 12 thru 15 of the packet header. */
+#else
+	uint32_t capture                      : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx;
+	struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t;
+
+/**
+ * cvmx_sriomaint#_erb_pack_sym_capt
+ *
+ * SRIOMAINT_ERB_PACK_SYM_CAPT = SRIO Packet/Control Symbol Capture
+ *
+ * Packet/Control Symbol Capture
+ *
+ * Notes:
+ * This register contains either captured control symbol information or the first 4 bytes of captured
+ *  packet information.  The Errors that generate Partial Control Symbols can be found in
+ *  SRIOMAINT*_ERB_ERR_DET.  The HW will not update this register (i.e. this register is locked) while
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.  This register should only be read while this bit is set.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT       hclk    hrst_n
+ */
+union cvmx_sriomaintx_erb_pack_sym_capt
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_erb_pack_sym_capt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t capture                      : 32; /**< Control Character and Control Symbol or Bytes 0 to
+                                                         3 of Packet Header
+                                                         The Control Symbol consists of
+                                                           - 31:24 - SC Character (0 in Partial Symbol)
+                                                           - 23:21 - Stype 0
+                                                           - 20:16 - Parameter 0
+                                                           - 15:11 - Parameter 1
+                                                           - 10: 8 - Stype 1 (0 in Partial Symbol)
+                                                           - 7: 5 - Command (0 in Partial Symbol)
+                                                           - 4: 0 - CRC5    (0 in Partial Symbol) */
+#else
+	uint32_t capture                      : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx;
+	struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t;
+
+/**
+ * cvmx_sriomaint#_hb_dev_id_lock
+ *
+ * SRIOMAINT_HB_DEV_ID_LOCK = SRIO Host Device ID Lock
+ *
+ * The Host Base Device ID
+ *
+ * Notes:
+ * This register contains the Device ID of the Host responsible for initializing this SRIO device.
+ *  The register contains a special write once function that captures the first HOSTID written to it
+ *  after reset.  The function allows several potential hosts to write to this register and then read
+ *  it to see if they have responsibility for initialization.  The register can be unlocked by
+ *  rewriting the current host value.  This will reset the lock and restore the value to 0xFFFF.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_HB_DEV_ID_LOCK  hclk    hrst_n
+ */
+union cvmx_sriomaintx_hb_dev_id_lock
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_hb_dev_id_lock_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t hostid                       : 16; /**< Primary 16-bit Device ID */
+#else
+	uint32_t hostid                       : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx;
+	struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t;
+
+/**
+ * cvmx_sriomaint#_ir_buffer_config
+ *
+ * SRIOMAINT_IR_BUFFER_CONFIG = SRIO Buffer Configuration
+ *
+ * Buffer Configuration
+ *
+ * Notes:
+ * This register controls the operation of the SRIO Core buffer mux logic.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_BUFFER_CONFIG        hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_buffer_config
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_buffer_config_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t tx_wm0                       : 4;  /**< Transmitter Flow Control Priority 0 Threshold.
+                                                         Number of Receive Buffers available before packet
+                                                         can be scheduled for transmission.
+                                                         Maximum Value 8.
+                                                         Generally, TX_WM0 Must be > TX_WM1 to reserve
+                                                         buffers for priority 1-3 packets when transmitting
+                                                         in transmitter-controlled flow control mode.
+                                                         TX_WM0 is not used by the hardware when TX_FLOW=0
+                                                         or whenever transmitting in
+                                                         receiver-controlled flow-control mode. */
+	uint32_t tx_wm1                       : 4;  /**< Transmitter Flow Control Priority 1 Threshold.
+                                                         Number of Receive Buffers available before packet
+                                                         can be scheduled for transmission.
+                                                         Maximum Value 8.
+                                                         Generally, TX_WM1 Must be > TX_WM2 to reserve
+                                                         buffers for priority 2-3 packets when transmitting
+                                                         in transmitter-controlled flow control mode.
+                                                         TX_WM1 is not used by the hardware when TX_FLOW=0
+                                                         or whenever transmitting in
+                                                         receiver-controlled flow-control mode. */
+	uint32_t tx_wm2                       : 4;  /**< Transmitter Flow Control Priority 2 Threshold.
+                                                         Number of Receive Buffers available before packet
+                                                         can be scheduled for transmission.
+                                                         Maximum Value 8.
+                                                         Generally, TX_WM2 Must be > 0 to reserve a
+                                                         buffer for priority 3 packets when transmitting
+                                                         in transmitter-controlled flow control mode.
+                                                         TX_WM2 is not used by the hardware when TX_FLOW=0
+                                                         or whenever transmitting in
+                                                         receiver-controlled flow-control mode. */
+	uint32_t reserved_3_19                : 17;
+	uint32_t tx_flow                      : 1;  /**< Controls whether Transmitter Flow Control is
+                                                         permitted on this device.
+                                                           0 - Disabled
+                                                           1 - Permitted
+                                                         The reset value of this field is
+                                                         SRIO*_IP_FEATURE[TX_FLOW]. */
+	uint32_t tx_sync                      : 1;  /**< Controls whether the synchronizers are enabled
+                                                         between the SRIO TXCLK and the Internal Clocks.
+                                                           0 - Synchronizers are enabled
+                                                           1 - Synchronizers are disabled */
+	uint32_t rx_sync                      : 1;  /**< Controls whether the synchronizers are enabled
+                                                         between the SRIO RXCLK and the Internal Clocks.
+                                                           0 - Synchronizers are enabled
+                                                           1 - Synchronizers are disabled */
+#else
+	uint32_t rx_sync                      : 1;
+	uint32_t tx_sync                      : 1;
+	uint32_t tx_flow                      : 1;
+	uint32_t reserved_3_19                : 17;
+	uint32_t tx_wm2                       : 4;
+	uint32_t tx_wm1                       : 4;
+	uint32_t tx_wm0                       : 4;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_buffer_config_s cn63xx;
+	struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t;
+
+/**
+ * cvmx_sriomaint#_ir_buffer_config2
+ *
+ * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 (Pass 2)
+ *
+ * Buffer Configuration 2
+ *
+ * Notes:
+ * This register controls the RX and TX Buffer availablility by priority.  The typical values are
+ *  optimized for normal operation.  Care must be taken when changing these values to avoid values
+ *  which can result in deadlocks.  Disabling a priority is not recommended and can result in system
+ *  level failures.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_BUFFER_CONFIG2       hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_buffer_config2
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_buffer_config2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t tx_wm3                       : 4;  /**< Number of buffers free before a priority 3 packet
+                                                         will be transmitted.  A value of 9 will disable
+                                                         this priority. */
+	uint32_t tx_wm2                       : 4;  /**< Number of buffers free before a priority 2 packet
+                                                         will be transmitted.  A value of 9 will disable
+                                                         this priority. */
+	uint32_t tx_wm1                       : 4;  /**< Number of buffers free before a priority 1 packet
+                                                         will be transmitted.  A value of 9 will disable
+                                                         this priority. */
+	uint32_t tx_wm0                       : 4;  /**< Number of buffers free before a priority 0 packet
+                                                         will be transmitted.  A value of 9 will disable
+                                                         this priority. */
+	uint32_t rx_wm3                       : 4;  /**< Number of buffers free before a priority 3 packet
+                                                         will be accepted.  A value of 9 will disable this
+                                                         priority and always cause a physical layer RETRY. */
+	uint32_t rx_wm2                       : 4;  /**< Number of buffers free before a priority 2 packet
+                                                         will be accepted.  A value of 9 will disable this
+                                                         priority and always cause a physical layer RETRY. */
+	uint32_t rx_wm1                       : 4;  /**< Number of buffers free before a priority 1 packet
+                                                         will be accepted.  A value of 9 will disable this
+                                                         priority and always cause a physical layer RETRY. */
+	uint32_t rx_wm0                       : 4;  /**< Number of buffers free before a priority 0 packet
+                                                         will be accepted.  A value of 9 will disable this
+                                                         priority and always cause a physical layer RETRY. */
+#else
+	uint32_t rx_wm0                       : 4;
+	uint32_t rx_wm1                       : 4;
+	uint32_t rx_wm2                       : 4;
+	uint32_t rx_wm3                       : 4;
+	uint32_t tx_wm0                       : 4;
+	uint32_t tx_wm1                       : 4;
+	uint32_t tx_wm2                       : 4;
+	uint32_t tx_wm3                       : 4;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx;
+};
+typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t;
+
+/**
+ * cvmx_sriomaint#_ir_pd_phy_ctrl
+ *
+ * SRIOMAINT_IR_PD_PHY_CTRL = SRIO Platform Dependent PHY Control
+ *
+ * Platform Dependent PHY Control
+ *
+ * Notes:
+ * This register can be used for testing.  The register is otherwise unused by the hardware.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_PD_PHY_CTRL  hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_pd_phy_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pd_ctrl                      : 32; /**< Unused Register available for testing */
+#else
+	uint32_t pd_ctrl                      : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx;
+	struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_ir_pd_phy_stat
+ *
+ * SRIOMAINT_IR_PD_PHY_STAT = SRIO Platform Dependent PHY Status
+ *
+ * Platform Dependent PHY Status
+ *
+ * Notes:
+ * This register is used to monitor PHY status on each lane.  They are documented here to assist in
+ *  debugging only.  The lane numbers take into account the lane swap pin.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_PD_PHY_STAT  hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_pd_phy_stat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_pd_phy_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t ln3_rx                       : 3;  /**< Phy Lane 3 RX Status
+                                                         0XX = Normal Operation
+                                                         100 = 8B/10B Error
+                                                         101 = Elastic Buffer Overflow (Data Lost)
+                                                         110 = Elastic Buffer Underflow (Data Corrupted)
+                                                         111 = Disparity Error */
+	uint32_t ln3_dis                      : 1;  /**< Lane 3 Phy Clock Disabled
+                                                         0 = Phy Clock Valid
+                                                         1 = Phy Clock InValid */
+	uint32_t ln2_rx                       : 3;  /**< Phy Lane 2 RX Status
+                                                         0XX = Normal Operation
+                                                         100 = 8B/10B Error
+                                                         101 = Elastic Buffer Overflow (Data Lost)
+                                                         110 = Elastic Buffer Underflow (Data Corrupted)
+                                                         111 = Disparity Error */
+	uint32_t ln2_dis                      : 1;  /**< Lane 2 Phy Clock Disabled
+                                                         0 = Phy Clock Valid
+                                                         1 = Phy Clock InValid */
+	uint32_t ln1_rx                       : 3;  /**< Phy Lane 1 RX Status
+                                                         0XX = Normal Operation
+                                                         100 = 8B/10B Error
+                                                         101 = Elastic Buffer Overflow (Data Lost)
+                                                         110 = Elastic Buffer Underflow (Data Corrupted)
+                                                         111 = Disparity Error */
+	uint32_t ln1_dis                      : 1;  /**< Lane 1 Phy Clock Disabled
+                                                         0 = Phy Clock Valid
+                                                         1 = Phy Clock InValid */
+	uint32_t ln0_rx                       : 3;  /**< Phy Lane 0 RX Status
+                                                         0XX = Normal Operation
+                                                         100 = 8B/10B Error
+                                                         101 = Elastic Buffer Overflow (Data Lost)
+                                                         110 = Elastic Buffer Underflow (Data Corrupted)
+                                                         111 = Disparity Error */
+	uint32_t ln0_dis                      : 1;  /**< Lane 0 Phy Clock Disabled
+                                                         0 = Phy Clock Valid
+                                                         1 = Phy Clock InValid */
+#else
+	uint32_t ln0_dis                      : 1;
+	uint32_t ln0_rx                       : 3;
+	uint32_t ln1_dis                      : 1;
+	uint32_t ln1_rx                       : 3;
+	uint32_t ln2_dis                      : 1;
+	uint32_t ln2_rx                       : 3;
+	uint32_t ln3_dis                      : 1;
+	uint32_t ln3_rx                       : 3;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx;
+	struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t;
+
+/**
+ * cvmx_sriomaint#_ir_pi_phy_ctrl
+ *
+ * SRIOMAINT_IR_PI_PHY_CTRL = SRIO Platform Independent PHY Control
+ *
+ * Platform Independent PHY Control
+ *
+ * Notes:
+ * This register is used to control platform independent operating modes of the transceivers. These
+ *  control bits are uniform across all platforms.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_PI_PHY_CTRL  hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_pi_phy_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t tx_reset                     : 1;  /**< Outgoing PHY Logic Reset.  0=Reset, 1=Normal Op */
+	uint32_t rx_reset                     : 1;  /**< Incoming PHY Logic Reset.  0=Reset, 1=Normal Op */
+	uint32_t reserved_29_29               : 1;
+	uint32_t loopback                     : 2;  /**< These bits control the state of the loopback
+                                                         control vector on the transceiver interface.  The
+                                                         loopback modes are enumerated as follows:
+                                                           00 - No Loopback
+                                                           01 - Near End PCS Loopback
+                                                           10 - Far End PCS Loopback
+                                                           11 - Both Near and Far End PCS Loopback */
+	uint32_t reserved_0_26                : 27;
+#else
+	uint32_t reserved_0_26                : 27;
+	uint32_t loopback                     : 2;
+	uint32_t reserved_29_29               : 1;
+	uint32_t rx_reset                     : 1;
+	uint32_t tx_reset                     : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx;
+	struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_ir_pi_phy_stat
+ *
+ * SRIOMAINT_IR_PI_PHY_STAT = SRIO Platform Independent PHY Status
+ *
+ * Platform Independent PHY Status
+ *
+ * Notes:
+ * This register displays the status of the link initialization state machine.  Changes to this state
+ *  cause the SRIO(0..1)_INT_REG.LINK_UP or SRIO(0..1)_INT_REG.LINK_DOWN interrupts.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_PI_PHY_STAT  hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_pi_phy_stat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_pi_phy_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_12_31               : 20;
+	uint32_t tx_rdy                       : 1;  /**< Minimum number of Status Transmitted  (Pass 2) */
+	uint32_t rx_rdy                       : 1;  /**< Minimum number of Good Status Received (Pass 2) */
+	uint32_t init_sm                      : 10; /**< Initialization State Machine
+                                                         001 - Silent
+                                                         002 - Seek
+                                                         004 - Discovery
+                                                         008 - 1x_Mode_Lane0
+                                                         010 - 1x_Mode_Lane1
+                                                         020 - 1x_Mode_Lane2
+                                                         040 - 1x_Recovery
+                                                         080 - 2x_Mode
+                                                         100 - 2x_Recovery
+                                                         200 - 4x_Mode
+                                                         All others are reserved */
+#else
+	uint32_t init_sm                      : 10;
+	uint32_t rx_rdy                       : 1;
+	uint32_t tx_rdy                       : 1;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx;
+	struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_10_31               : 22;
+	uint32_t init_sm                      : 10; /**< Initialization State Machine
+                                                         001 - Silent
+                                                         002 - Seek
+                                                         004 - Discovery
+                                                         008 - 1x_Mode_Lane0
+                                                         010 - 1x_Mode_Lane1
+                                                         020 - 1x_Mode_Lane2
+                                                         040 - 1x_Recovery
+                                                         080 - 2x_Mode
+                                                         100 - 2x_Recovery
+                                                         200 - 4x_Mode
+                                                         All others are reserved */
+#else
+	uint32_t init_sm                      : 10;
+	uint32_t reserved_10_31               : 22;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_rx_ctrl
+ *
+ * SRIOMAINT_IR_SP_RX_CTRL = SRIO Soft Packet FIFO Receive Control
+ *
+ * Soft Packet FIFO Receive Control
+ *
+ * Notes:
+ * This register is used to configure events generated by the reception of packets using the soft
+ * packet FIFO.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_CTRL   hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_rx_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_1_31                : 31;
+	uint32_t overwrt                      : 1;  /**< When clear, SRIO drops received packets that should
+                                                         enter the soft packet FIFO when the FIFO is full.
+                                                         When set, SRIO
+                                                         stalls received packets that should enter the soft
+                                                         packet FIFO when the FIFO is full. SRIO may stop
+                                                         receiving any packets in this stall case if
+                                                         software does not drain the receive soft packet
+                                                         FIFO. */
+#else
+	uint32_t overwrt                      : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_rx_data
+ *
+ * SRIOMAINT_IR_SP_RX_DATA = SRIO Soft Packet FIFO Receive Data
+ *
+ * Soft Packet FIFO Receive Data
+ *
+ * Notes:
+ * This register is used to read data from the soft packet FIFO.  The Soft Packet FIFO contains the
+ *  majority of the packet data received from the SRIO link.  The packet does not include the Control
+ *  Symbols or the initial byte containing AckId, 2 Reserved Bits and the CRF.  In the case of packets
+ *  with less than 80 bytes (including AckId byte) both the trailing CRC and Pad (if present) are
+ *  included in the FIFO and Octet Count.  In the case of a packet with exactly 80 bytes (including
+ *  the AckId byte) the CRC is removed and the Pad is maintained so the Octet Count will read 81 bytes
+ *  instead of the expected 83.  In cases over 80 bytes the CRC at 80 bytes is removed but the
+ *  trailing CRC and Pad (if necessary) are present.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_DATA   hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_rx_data
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_rx_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_data                     : 32; /**< This register is used to read packet data from the
+                                                         RX FIFO. */
+#else
+	uint32_t pkt_data                     : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_rx_stat
+ *
+ * SRIOMAINT_IR_SP_RX_STAT = SRIO Soft Packet FIFO Receive Status
+ *
+ * Soft Packet FIFO Receive Status
+ *
+ * Notes:
+ * This register is used to monitor the reception of packets using the soft packet FIFO.
+ *  The HW sets SRIO_INT_REG[SOFT_RX] every time a packet arrives in the soft packet FIFO. To read
+ *  out (one or more) packets, the following procedure may be best:
+ *       (1) clear SRIO_INT_REG[SOFT_RX],
+ *       (2) read this CSR to determine how many packets there are,
+ *       (3) read the packets out (via SRIOMAINT*_IR_SP_RX_DATA).
+ *  This procedure could lead to situations where SOFT_RX will be set even though there are currently
+ *  no packets - the SW interrupt handler would need to properly handle this case
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_RX_STAT   hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_rx_stat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_rx_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t octets                       : 16; /**< This field shows how many octets are remaining
+                                                         in the current packet in the RX FIFO. */
+	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
+                                                         stored in the Rx FIFO. */
+	uint32_t drop_cnt                     : 7;  /**< Number of Packets Received when the RX FIFO was
+                                                         full and then discarded.
+                                                         This field always reads zero in Pass 1 */
+	uint32_t full                         : 1;  /**< This bit is set when the value of Buffers Filled
+                                                         equals the number of available reception buffers.
+                                                         This bit always reads zero in Pass 1 */
+	uint32_t fifo_st                      : 4;  /**< These bits display the state of the state machine
+                                                         that controls loading of packet data into the RX
+                                                         FIFO. The enumeration of states are as follows:
+                                                           0000 - Idle
+                                                           0001 - Armed
+                                                           0010 - Active
+                                                           All other states are reserved. */
+#else
+	uint32_t fifo_st                      : 4;
+	uint32_t full                         : 1;
+	uint32_t drop_cnt                     : 7;
+	uint32_t buffers                      : 4;
+	uint32_t octets                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t octets                       : 16; /**< This field shows how many octets are remaining
+                                                         in the current packet in the RX FIFO. */
+	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
+                                                         stored in the Rx FIFO. */
+	uint32_t reserved_5_11                : 7;
+	uint32_t full                         : 1;  /**< This bit is set when the value of Buffers Filled
+                                                         equals the number of available reception buffers.
+                                                         This bit always reads zero in Pass 1 */
+	uint32_t fifo_st                      : 4;  /**< These bits display the state of the state machine
+                                                         that controls loading of packet data into the RX
+                                                         FIFO. The enumeration of states are as follows:
+                                                           0000 - Idle
+                                                           0001 - Armed
+                                                           0010 - Active
+                                                           All other states are reserved. */
+#else
+	uint32_t fifo_st                      : 4;
+	uint32_t full                         : 1;
+	uint32_t reserved_5_11                : 7;
+	uint32_t buffers                      : 4;
+	uint32_t octets                       : 16;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_tx_ctrl
+ *
+ * SRIOMAINT_IR_SP_TX_CTRL = SRIO Soft Packet FIFO Transmit Control
+ *
+ * Soft Packet FIFO Transmit Control
+ *
+ * Notes:
+ * This register is used to configure and control the transmission of packets using the soft packet
+ *  FIFO.
+ *
+ * Clk_Rst:        SRIOMAINT_IR_SP_TX_CTRL hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_tx_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t octets                       : 16; /**< Writing a non-zero value (N) to this field arms
+                                                         the packet FIFO for packet transmission. The FIFO
+                                                         control logic will transmit the next N bytes
+                                                         written 4-bytes at a time to the
+                                                         SRIOMAINT(0..1)_IR_SP_TX_DATA Register and create a
+                                                         single RapidIO packet. */
+	uint32_t reserved_0_15                : 16;
+#else
+	uint32_t reserved_0_15                : 16;
+	uint32_t octets                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_tx_data
+ *
+ * SRIOMAINT_IR_SP_TX_DATA = SRIO Soft Packet FIFO Transmit Data
+ *
+ * Soft Packet FIFO Transmit Data
+ *
+ * Notes:
+ * This register is used to write data to the soft packet FIFO.  The format of the packet follows the
+ * Internal Packet Format (add link here).  Care must be taken on creating TIDs for the packets which
+ * generate a response.  Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated
+ * packets.  TID values of 0x00 - 0xBF are reserved for hardware generated Tags.  The remainer of the
+ * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received
+ * in the SRIOMAINT(0..1)_IR_SP_RX_DATA register.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_TX_DATA   hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_tx_data
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_tx_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pkt_data                     : 32; /**< This register is used to write packet data to the
+                                                         Tx FIFO. Reads of this register will return zero. */
+#else
+	uint32_t pkt_data                     : 32;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t;
+
+/**
+ * cvmx_sriomaint#_ir_sp_tx_stat
+ *
+ * SRIOMAINT_IR_SP_TX_STAT = SRIO Soft Packet FIFO Transmit Status
+ *
+ * Soft Packet FIFO Transmit Status
+ *
+ * Notes:
+ * This register is used to monitor the transmission of packets using the soft packet FIFO.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_IR_SP_TX_STAT   hclk    hrst_n
+ */
+union cvmx_sriomaintx_ir_sp_tx_stat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_ir_sp_tx_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t octets                       : 16; /**< This field shows how many octets are still to be
+                                                         loaded in the current packet. */
+	uint32_t buffers                      : 4;  /**< This field indicates how many complete packets are
+                                                         stored in the Tx FIFO.  The field always reads
+                                                         zero in the current hardware. */
+	uint32_t reserved_5_11                : 7;
+	uint32_t full                         : 1;  /**< This bit is set when the value of Buffers Filled
+                                                         equals the number of available transmission
+                                                         buffers. */
+	uint32_t fifo_st                      : 4;  /**< These bits display the state of the state machine
+                                                         that controls loading of packet data into the TX
+                                                         FIFO. The enumeration of states are as follows:
+                                                           0000 - Idle
+                                                           0001 - Armed
+                                                           0010 - Active
+                                                           All other states are reserved. */
+#else
+	uint32_t fifo_st                      : 4;
+	uint32_t full                         : 1;
+	uint32_t reserved_5_11                : 7;
+	uint32_t buffers                      : 4;
+	uint32_t octets                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx;
+	struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t;
+
+/**
+ * cvmx_sriomaint#_lane_#_status_0
+ *
+ * SRIOMAINT_LANE_X_STATUS_0 = SRIO Lane X Status 0
+ *
+ * SRIO Lane Status 0
+ *
+ * Notes:
+ * This register contains status information about the local lane transceiver.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_LANE_[0:3]_STATUS_0     hclk    hrst_n
+ */
+union cvmx_sriomaintx_lane_x_status_0
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_lane_x_status_0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t port                         : 8;  /**< The number of the port within the device to which
+                                                         the lane is assigned. */
+	uint32_t lane                         : 4;  /**< Lane Number within the port. */
+	uint32_t tx_type                      : 1;  /**< Transmitter Type
+                                                         0 = Short Run
+                                                         1 = Long Run */
+	uint32_t tx_mode                      : 1;  /**< Transmitter Operating Mode
+                                                         0 = Short Run
+                                                         1 = Long Run */
+	uint32_t rx_type                      : 2;  /**< Receiver Type
+                                                         0 = Short Run
+                                                         1 = Medium Run
+                                                         2 = Long Run
+                                                         3 = Reserved */
+	uint32_t rx_inv                       : 1;  /**< Receiver Input Inverted
+                                                         0 = No Inversion
+                                                         1 = Input Inverted */
+	uint32_t rx_adapt                     : 1;  /**< Receiver Trained
+                                                         0 = One or more adaptive equalizers are
+                                                             controlled by the lane receiver and at least
+                                                             one is not trained.
+                                                         1 = The lane receiver controls no adaptive
+                                                             equalizers or all the equalizers are trained. */
+	uint32_t rx_sync                      : 1;  /**< Receiver Lane Sync'd */
+	uint32_t rx_train                     : 1;  /**< Receiver Lane Trained */
+	uint32_t dec_err                      : 4;  /**< 8Bit/10Bit Decoding Errors
+                                                         0    = No Errors since last read
+                                                         1-14 = Number of Errors since last read
+                                                         15   = Fifteen or more Errors since last read */
+	uint32_t xsync                        : 1;  /**< Receiver Lane Sync Change
+                                                         0 = Lane Sync has not changed since last read
+                                                         1 = Lane Sync has changed since last read */
+	uint32_t xtrain                       : 1;  /**< Receiver Training Change
+                                                         0 = Training has not changed since last read
+                                                         1 = Training has changed since last read */
+	uint32_t reserved_4_5                 : 2;
+	uint32_t status1                      : 1;  /**< Status 1 CSR Implemented */
+	uint32_t statusn                      : 3;  /**< Status 2-7 Not Implemented */
+#else
+	uint32_t statusn                      : 3;
+	uint32_t status1                      : 1;
+	uint32_t reserved_4_5                 : 2;
+	uint32_t xtrain                       : 1;
+	uint32_t xsync                        : 1;
+	uint32_t dec_err                      : 4;
+	uint32_t rx_train                     : 1;
+	uint32_t rx_sync                      : 1;
+	uint32_t rx_adapt                     : 1;
+	uint32_t rx_inv                       : 1;
+	uint32_t rx_type                      : 2;
+	uint32_t tx_mode                      : 1;
+	uint32_t tx_type                      : 1;
+	uint32_t lane                         : 4;
+	uint32_t port                         : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_lane_x_status_0_s cn63xx;
+	struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t;
+
+/**
+ * cvmx_sriomaint#_lcs_ba0
+ *
+ * SRIOMAINT_LCS_BA0 = SRIO Local Configuration Space MSB Base Address
+ *
+ * MSBs of SRIO Address Space mapped to Maintenance BAR.
+ *
+ * Notes:
+ * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR.  This window has
+ *  the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows.  Note:  Address bits
+ *  not supplied in the transfer are considered zero.  For example, SRIO Address 65:35 must be set to
+ *  zero to match in a 34-bit access.  SRIO Address 65:50 must be set to zero to match in a 50-bit
+ *  access.  This coding allows the Maintenance Bar window to appear in specific address spaces. The
+ *  remaining bits are located in SRIOMAINT(0..1)_LCS_BA1. This SRIO maintenance BAR is effectively
+ *  disabled when LCSBA[30] is set with 34 or 50-bit addressing.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_LCS_BA0 hclk    hrst_n
+ */
+union cvmx_sriomaintx_lcs_ba0
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_lcs_ba0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t lcsba                        : 31; /**< SRIO Address 65:35 */
+#else
+	uint32_t lcsba                        : 31;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_lcs_ba0_s      cn63xx;
+	struct cvmx_sriomaintx_lcs_ba0_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t;
+
+/**
+ * cvmx_sriomaint#_lcs_ba1
+ *
+ * SRIOMAINT_LCS_BA1 = SRIO Local Configuration Space LSB Base Address
+ *
+ * LSBs of SRIO Address Space mapped to Maintenance BAR.
+ *
+ * Notes:
+ * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR.  This window has
+ *  the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Address bits not
+ *  supplied in the transfer are considered zero.  For example, SRIO Address 65:35 must be set to zero
+ *  to match in a 34-bit access and SRIO Address 65:50 must be set to zero to match in a 50-bit access.
+ *  This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses
+ *  through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes.
+ *  Accesses which violate this rule will return an error response if possible and be otherwise
+ *  ignored.  The remaining bits are located in SRIOMAINT(0..1)_LCS_BA0.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_LCS_BA1 hclk    hrst_n
+ */
+union cvmx_sriomaintx_lcs_ba1
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_lcs_ba1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lcsba                        : 11; /**< SRIO Address 34:24 */
+	uint32_t reserved_0_20                : 21;
+#else
+	uint32_t reserved_0_20                : 21;
+	uint32_t lcsba                        : 11;
+#endif
+	} s;
+	struct cvmx_sriomaintx_lcs_ba1_s      cn63xx;
+	struct cvmx_sriomaintx_lcs_ba1_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t;
+
+/**
+ * cvmx_sriomaint#_m2s_bar0_start0
+ *
+ * SRIOMAINT_M2S_BAR0_START0 = SRIO Device Access BAR0 MSB Start
+ *
+ * The starting SRIO address to forwarded to the NPEI Configuration Space.
+ *
+ * Notes:
+ * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space.  See
+ *  SRIOMAINT(0..1)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the
+ *  SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR0_START0 hclk    hrst_n
+ */
+union cvmx_sriomaintx_m2s_bar0_start0
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_m2s_bar0_start0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
+	uint32_t addr48                       : 16; /**< SRIO Address 47:32 */
+#else
+	uint32_t addr48                       : 16;
+	uint32_t addr64                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx;
+	struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t;
+
+/**
+ * cvmx_sriomaint#_m2s_bar0_start1
+ *
+ * SRIOMAINT_M2S_BAR0_START1 = SRIO Device Access BAR0 LSB Start
+ *
+ * The starting SRIO address to forwarded to the NPEI Configuration Space.
+ *
+ * Notes:
+ * This register specifies the SRIO Address mapped to the BAR0 RSL Space.  If the transaction has not
+ *  already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers, if
+ *  ENABLE is set and the address bits match then the SRIO Memory transactions will map to Octeon SLI
+ *  Registers.  34-bit address transactions require a match in SRIO Address 33:14 and require all the
+ *  other bits in ADDR48, ADDR64 and ADDR66 fields to be zero.  50-bit address transactions a match of
+ *  SRIO Address 49:14 and require all the other bits of ADDR64 and ADDR66 to be zero.  66-bit address
+ *  transactions require matches of all valid address field bits.  Reads and  Writes through Bar0
+ *  have a size limit of 8 bytes and cannot cross a 64-bit boundry.  All accesses with sizes greater
+ *  than this limit will be ignored and return an error on any SRIO responses.  Note: ADDR48 and
+ *  ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR0_START0.  This register is only writeable over
+ *  SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR0_START1 hclk    hrst_n
+ */
+union cvmx_sriomaintx_m2s_bar0_start1
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_m2s_bar0_start1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr32                       : 18; /**< SRIO Address 31:14 */
+	uint32_t reserved_3_13                : 11;
+	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
+	uint32_t enable                       : 1;  /**< Enable BAR0 Access */
+#else
+	uint32_t enable                       : 1;
+	uint32_t addr66                       : 2;
+	uint32_t reserved_3_13                : 11;
+	uint32_t addr32                       : 18;
+#endif
+	} s;
+	struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx;
+	struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t;
+
+/**
+ * cvmx_sriomaint#_m2s_bar1_start0
+ *
+ * SRIOMAINT_M2S_BAR1_START0 = SRIO Device Access BAR1 MSB Start
+ *
+ * The starting SRIO address to forwarded to the BAR1 Memory Space.
+ *
+ * Notes:
+ * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space.  See
+ *  SRIOMAINT(0..1)_M2S_BAR1_START1 for more details.  This register is only writeable over SRIO if the
+ *  SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR1_START0 hclk    hrst_n
+ */
+union cvmx_sriomaintx_m2s_bar1_start0
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_m2s_bar1_start0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
+	uint32_t addr48                       : 16; /**< SRIO Address 47:32 */
+#else
+	uint32_t addr48                       : 16;
+	uint32_t addr64                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx;
+	struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t;
+
+/**
+ * cvmx_sriomaint#_m2s_bar1_start1
+ *
+ * SRIOMAINT_M2S_BAR1_START1 = SRIO Device to BAR1 Start
+ *
+ * The starting SRIO address to forwarded to the BAR1 Memory Space.
+ *
+ * Notes:
+ * This register specifies the SRIO Address mapped to the BAR1 Space.  If the transaction has not
+ *  already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the
+ *  address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the
+ *  BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by
+ *  SRIOMAINT(0..1)_BAR1_IDX[31:0] registers.  The BARSIZE field determines the size of BAR1, the entry
+ *  select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches
+ *  SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero.
+ *  A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the
+ *  other bits of ADDR64 and ADDR66 are zero.  A 66-bit address matches BAR1 when all of
+ *  SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits.  Note: ADDR48 and
+ *  ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR1_START0. This register is only writeable from SRIO
+ *  if the SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR1_START1 hclk    hrst_n
+ */
+union cvmx_sriomaintx_m2s_bar1_start1
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_m2s_bar1_start1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr32                       : 12; /**< SRIO Address 31:20
+                                                         With BARSIZE < 12, the upper 12-BARSIZE
+                                                         bits of this field are used, and the lower BARSIZE
+                                                         bits of this field are unused by the SRIO hardware. */
+	uint32_t reserved_7_19                : 13;
+	uint32_t barsize                      : 4;  /**< Bar Size.
+                                                                              SRIO_Address*
+                                                                         ---------------------
+                                                                        /                     \
+                                                         BARSIZE         BAR     Entry   Entry    Entry
+                                                         Value   BAR    compare  Select  Offset   Size
+                                                                 Size    bits    bits    bits
+                                                          0       1MB    65:20   19:16   15:0     64KB
+                                                          1       2MB    65:21   20:17   16:0    128KB
+                                                          2       4MB    65:22   21:18   17:0    256KB
+                                                          3       8MB    65:23   22:19   18:0    512KB
+                                                          4      16MB    65:24   23:20   19:0      1MB
+                                                          5      32MB    65:25   24:21   20:0      2MB
+                                                          6      64MB    65:26   25:22   21:0      4MB
+                                                          7     128MB    65:27   26:23   22:0      8MB
+                                                          8     256MB  ** not in pass 1
+                                                          9     512MB  ** not in pass 1
+                                                         10       1GB  ** not in pass 1
+                                                         11       2GB  ** not in pass 1
+                                                         12       4GB  ** not in pass 1
+                                                         13       8GB  ** not in pass 1
+
+                                                         *The SRIO Transaction Address
+                                                         The entry select bits is the X that  select an
+                                                         SRIOMAINT(0..1)_BAR1_IDXX entry.
+
+                                                         In O63 pass 2, BARSIZE is 4 bits (6:3 in this
+                                                         CSR), and BARSIZE values 8-13 are implemented,
+                                                         providing a total possible BAR1 size range from
+                                                         1MB up to 8GB. */
+	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
+	uint32_t enable                       : 1;  /**< Enable BAR1 Access */
+#else
+	uint32_t enable                       : 1;
+	uint32_t addr66                       : 2;
+	uint32_t barsize                      : 4;
+	uint32_t reserved_7_19                : 13;
+	uint32_t addr32                       : 12;
+#endif
+	} s;
+	struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx;
+	struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr32                       : 12; /**< SRIO Address 31:20
+                                                         With BARSIZE < 12, the upper 12-BARSIZE
+                                                         bits of this field are used, and the lower BARSIZE
+                                                         bits of this field are unused by the SRIO hardware. */
+	uint32_t reserved_6_19                : 14;
+	uint32_t barsize                      : 3;  /**< Bar Size.
+                                                                              SRIO_Address*
+                                                                         ---------------------
+                                                                        /                     \
+                                                         BARSIZE         BAR     Entry   Entry    Entry
+                                                         Value   BAR    compare  Select  Offset   Size
+                                                                 Size    bits    bits    bits
+                                                          0       1MB    65:20   19:16   15:0     64KB
+                                                          1       2MB    65:21   20:17   16:0    128KB
+                                                          2       4MB    65:22   21:18   17:0    256KB
+                                                          3       8MB    65:23   22:19   18:0    512KB
+                                                          4      16MB    65:24   23:20   19:0      1MB
+                                                          5      32MB    65:25   24:21   20:0      2MB
+                                                          6      64MB    65:26   25:22   21:0      4MB
+                                                          7     128MB    65:27   26:23   22:0      8MB
+                                                          8     256MB  ** not in pass 1
+                                                          9     512MB  ** not in pass 1
+                                                         10       1GB  ** not in pass 1
+                                                         11       2GB  ** not in pass 1
+                                                         12       4GB  ** not in pass 1
+                                                         13       8GB  ** not in pass 1
+
+                                                         *The SRIO Transaction Address
+                                                         The entry select bits is the X that  select an
+                                                         SRIOMAINT(0..1)_BAR1_IDXX entry.
+
+                                                         In O63 pass 2, BARSIZE is 4 bits (6:3 in this
+                                                         CSR), and BARSIZE values 8-13 are implemented,
+                                                         providing a total possible BAR1 size range from
+                                                         1MB up to 8GB. */
+	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
+	uint32_t enable                       : 1;  /**< Enable BAR1 Access */
+#else
+	uint32_t enable                       : 1;
+	uint32_t addr66                       : 2;
+	uint32_t barsize                      : 3;
+	uint32_t reserved_6_19                : 14;
+	uint32_t addr32                       : 12;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t;
+
+/**
+ * cvmx_sriomaint#_m2s_bar2_start
+ *
+ * SRIOMAINT_M2S_BAR2_START = SRIO Device to BAR2 Start
+ *
+ * The starting SRIO address to forwarded to the BAR2 Memory Space.
+ *
+ * Notes:
+ * This register specifies the SRIO Address mapped to the BAR2 Space.  If ENABLE is set and the
+ *  address bits do not match and other enabled BAR address and match the BAR2 addresses then the SRIO
+ *  Memory transactions will map to Octeon BAR2 Memory Space.  34-bit address transactions require
+ *  ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34.
+ *  50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64
+ *  and ADDR66 to be zero.  66-bit address transactions require matches of all valid address field
+ *  bits.  This register is only writeable over SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR2 bit is zero.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_M2S_BAR2_START  hclk    hrst_n
+ */
+union cvmx_sriomaintx_m2s_bar2_start
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_m2s_bar2_start_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t addr64                       : 16; /**< SRIO Address 63:48 */
+	uint32_t addr48                       : 7;  /**< SRIO Address 47:41 */
+	uint32_t reserved_6_8                 : 3;
+	uint32_t esx                          : 2;  /**< Endian Swap Mode used for SRIO 34-bit access.
+                                                         For 50/66-bit assesses Endian Swap is determine
+                                                         by ESX XOR'd with SRIO Addr 39:38.
+                                                         0 = No Swap
+                                                         1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA]
+                                                         2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE]
+                                                         3 = 32-bit Word Exch  [ABCD_EFGH] -> [EFGH_ABCD] */
+	uint32_t cax                          : 1;  /**< Cacheable Access Mode.  When set transfer is
+                                                         cached.  This bit is used for SRIO 34-bit access.
+                                                         For 50/66-bit accessas NCA is determine by CAX
+                                                         XOR'd with SRIO Addr 40. */
+	uint32_t addr66                       : 2;  /**< SRIO Address 65:64 */
+	uint32_t enable                       : 1;  /**< Enable BAR2 Access */
+#else
+	uint32_t enable                       : 1;
+	uint32_t addr66                       : 2;
+	uint32_t cax                          : 1;
+	uint32_t esx                          : 2;
+	uint32_t reserved_6_8                 : 3;
+	uint32_t addr48                       : 7;
+	uint32_t addr64                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx;
+	struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t;
+
+/**
+ * cvmx_sriomaint#_mac_ctrl
+ *
+ * SRIOMAINT_MAC_CTRL = SRIO MAC Control (Pass 2)
+ *
+ * Control for MAC Features
+ *
+ * Notes:
+ * This register enables MAC optimizations that may not be supported by all SRIO devices.  The
+ *  default values should be supported.  This register can be changed at any time while the MAC is
+ *  out of reset.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_MAC_CTRL        hclk    hrst_n
+ */
+union cvmx_sriomaintx_mac_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_mac_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_19_31               : 13;
+	uint32_t rx_spf                       : 1;  /**< Route all received packets to RX Soft Packet FIFO.
+                                                         No logical layer ERB Errors will be reported.
+                                                         Used for Diagnostics Only. */
+	uint32_t eop_mrg                      : 1;  /**< Transmitted Packets can eliminate EOP Symbol on
+                                                         back to back packets. */
+	uint32_t type_mrg                     : 1;  /**< Allow STYPE Merging on Transmit. */
+	uint32_t lnk_rtry                     : 16; /**< Number of times MAC will reissue Link Request
+                                                         after timeout.  If retry count is exceeded Fatal
+                                                         Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */
+#else
+	uint32_t lnk_rtry                     : 16;
+	uint32_t type_mrg                     : 1;
+	uint32_t eop_mrg                      : 1;
+	uint32_t rx_spf                       : 1;
+	uint32_t reserved_19_31               : 13;
+#endif
+	} s;
+	struct cvmx_sriomaintx_mac_ctrl_s     cn63xx;
+};
+typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_pe_feat
+ *
+ * SRIOMAINT_PE_FEAT = SRIO Processing Element Features
+ *
+ * The Supported Processing Element Features.
+ *
+ * Notes:
+ * The Processing Element Feature register describes the major functionality provided by the SRIO
+ *  device.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PE_FEAT hclk    hrst_n
+ */
+union cvmx_sriomaintx_pe_feat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_pe_feat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bridge                       : 1;  /**< Bridge Functions not supported. */
+	uint32_t memory                       : 1;  /**< PE contains addressable memory. */
+	uint32_t proc                         : 1;  /**< PE contains a local processor. */
+	uint32_t switchf                      : 1;  /**< Switch Functions not supported. */
+	uint32_t mult_prt                     : 1;  /**< Multiport Functions not supported. */
+	uint32_t reserved_7_26                : 20;
+	uint32_t suppress                     : 1;  /**< Error Recovery Suppression not supported. */
+	uint32_t crf                          : 1;  /**< Critical Request Flow not supported. */
+	uint32_t lg_tran                      : 1;  /**< Large Transport (16-bit Device IDs) supported. */
+	uint32_t ex_feat                      : 1;  /**< Extended Feature Pointer is valid. */
+	uint32_t ex_addr                      : 3;  /**< PE supports 66, 50 and 34-bit addresses.
+                                                         [2:1] are a RO copy of SRIO*_IP_FEATURE[A66,A50]. */
+#else
+	uint32_t ex_addr                      : 3;
+	uint32_t ex_feat                      : 1;
+	uint32_t lg_tran                      : 1;
+	uint32_t crf                          : 1;
+	uint32_t suppress                     : 1;
+	uint32_t reserved_7_26                : 20;
+	uint32_t mult_prt                     : 1;
+	uint32_t switchf                      : 1;
+	uint32_t proc                         : 1;
+	uint32_t memory                       : 1;
+	uint32_t bridge                       : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_pe_feat_s      cn63xx;
+	struct cvmx_sriomaintx_pe_feat_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t;
+
+/**
+ * cvmx_sriomaint#_pe_llc
+ *
+ * SRIOMAINT_PE_LLC = SRIO Processing Element Logical Layer Control
+ *
+ * Addresses supported by the SRIO Device.
+ *
+ * Notes:
+ * The Processing Element Logical Layer is used for general configuration for the logical interface.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PE_LLC  hclk    hrst_n
+ */
+union cvmx_sriomaintx_pe_llc
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_pe_llc_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t ex_addr                      : 3;  /**< Controls the number of address bits generated by
+                                                         PE as a source and processed by the PE as a
+                                                         target of an operation.
+                                                          001 = 34-bit Addresses
+                                                          010 = 50-bit Addresses
+                                                          100 = 66-bit Addresses
+                                                          All other encodings are reserved. */
+#else
+	uint32_t ex_addr                      : 3;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_sriomaintx_pe_llc_s       cn63xx;
+	struct cvmx_sriomaintx_pe_llc_s       cn63xxp1;
+};
+typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t;
+
+/**
+ * cvmx_sriomaint#_port_0_ctl
+ *
+ * SRIOMAINT_PORT_0_CTL = SRIO Port 0 Control
+ *
+ * Port 0 Control
+ *
+ * Notes:
+ * This register contains assorted control bits.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_CTL      hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_ctl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pt_width                     : 2;  /**< Hardware Port Width.
+                                                         00 = One Lane supported.
+                                                         01 = One/Two Lanes supported.
+                                                         10 = One/Four Lanes supported.
+                                                         11 = One/Two/Four Lanes supported.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[PT_WIDTH]. */
+	uint32_t it_width                     : 3;  /**< Initialized Port Width
+                                                         000 = Single-lane, Lane 0
+                                                         001 = Single-lane, Lane 1 or 2
+                                                         010 = Four-lane
+                                                         011 = Two-lane
+                                                         Others = Reserved */
+	uint32_t ov_width                     : 3;  /**< Override Port Width.  Writing this register causes
+                                                         the port to reinitialize.
+                                                         000 = No Override all lanes possible
+                                                         001 = Reserved
+                                                         010 = Force Single-lane, Lane 0
+                                                         011 = Force Single-lane, Lane 2
+                                                               (Lane 1 if only lanes 0,1 are connected)
+                                                         100 = Reserved
+                                                         101 = Force Two-lane, Disable Four-Lane
+                                                         110 = Force Four-lane, Disable Two-Lane
+                                                         111 = All lanes sizes enabled */
+	uint32_t disable                      : 1;  /**< Port Disable.  Setting this bit disables both
+                                                         drivers and receivers. */
+	uint32_t o_enable                     : 1;  /**< Port Output Enable.  When cleared, port will
+                                                         generate control symbols and respond to
+                                                         maintenance transactions only.  When set, all
+                                                         transactions are allowed. */
+	uint32_t i_enable                     : 1;  /**< Port Input Enable.  When cleared, port will
+                                                         generate control symbols and respond to
+                                                         maintenance packets only.  All other packets will
+                                                         not be accepted. */
+	uint32_t dis_err                      : 1;  /**< Disable Error Checking.  Diagnostic Only. */
+	uint32_t mcast                        : 1;  /**< Reserved. */
+	uint32_t reserved_18_18               : 1;
+	uint32_t enumb                        : 1;  /**< Enumeration Boundry. SW can use this bit to
+                                                         determine port enumeration. */
+	uint32_t reserved_16_16               : 1;
+	uint32_t ex_width                     : 2;  /**< Extended Port Width not supported. */
+	uint32_t ex_stat                      : 2;  /**< Extended Port Width Status. 00 = not supported */
+	uint32_t suppress                     : 8;  /**< Retransmit Suppression Mask.  CRF not Supported. */
+	uint32_t stp_port                     : 1;  /**< Stop on Failed Port.  This bit is used with the
+                                                         DROP_PKT bit to force certain behavior when the
+                                                         Error Rate Failed Threshold has been met or
+                                                         exceeded. */
+	uint32_t drop_pkt                     : 1;  /**< Drop on Failed Port.  This bit is used with the
+                                                         STP_PORT bit to force certain behavior when the
+                                                         Error Rate Failed Threshold has been met or
+                                                         exceeded. */
+	uint32_t prt_lock                     : 1;  /**< When this bit is cleared, the packets that may be
+                                                         received and issued are controlled by the state of
+                                                         the O_ENABLE and I_ENABLE bits.  When this bit is
+                                                         set, this port is stopped and is not enabled to
+                                                         issue or receive any packets; the input port can
+                                                         still follow the training procedure and can still
+                                                         send and respond to link-requests; all received
+                                                         packets return packet-not-accepted control symbols
+                                                         to force an error condition to be signaled by the
+                                                         sending device. */
+	uint32_t pt_type                      : 1;  /**< Port Type.  1 = Serial port. */
+#else
+	uint32_t pt_type                      : 1;
+	uint32_t prt_lock                     : 1;
+	uint32_t drop_pkt                     : 1;
+	uint32_t stp_port                     : 1;
+	uint32_t suppress                     : 8;
+	uint32_t ex_stat                      : 2;
+	uint32_t ex_width                     : 2;
+	uint32_t reserved_16_16               : 1;
+	uint32_t enumb                        : 1;
+	uint32_t reserved_18_18               : 1;
+	uint32_t mcast                        : 1;
+	uint32_t dis_err                      : 1;
+	uint32_t i_enable                     : 1;
+	uint32_t o_enable                     : 1;
+	uint32_t disable                      : 1;
+	uint32_t ov_width                     : 3;
+	uint32_t it_width                     : 3;
+	uint32_t pt_width                     : 2;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_ctl_s   cn63xx;
+	struct cvmx_sriomaintx_port_0_ctl_s   cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t;
+
+/**
+ * cvmx_sriomaint#_port_0_ctl2
+ *
+ * SRIOMAINT_PORT_0_CTL2 = SRIO Port 0 Control 2
+ *
+ * Port 0 Control 2
+ *
+ * Notes:
+ * These registers are accessed when a local processor or an external device wishes to examine the
+ *  port baudrate information.  WARNING:  Writes to this register will reinitialize the SRIO link.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_CTL2     hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_ctl2
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_ctl2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t sel_baud                     : 4;  /**< Link Baud Rate Selected.
+                                                           0000 - No rate selected
+                                                           0001 - 1.25 GBaud
+                                                           0010 - 2.5 GBaud
+                                                           0011 - 3.125 GBaud
+                                                           0100 - 5.0 GBaud
+                                                           0101 - 6.25 GBaud (reserved)
+                                                           0110 - 0b1111 - Reserved
+                                                         Indicates the speed of the interface SERDES lanes
+                                                         (should match the value selected by SUP_* /ENB_*
+                                                         below). */
+	uint32_t baud_sup                     : 1;  /**< Automatic Baud Rate Discovery not supported. */
+	uint32_t baud_enb                     : 1;  /**< Auto Baud Rate Discovery Enable. */
+	uint32_t sup_125g                     : 1;  /**< 1.25GB Rate Operation supported.
+                                                         Set when the interface SERDES lanes are operating
+                                                         at 1.25 Gbaud (as selected by QLM*_SPD straps). */
+	uint32_t enb_125g                     : 1;  /**< 1.25GB Rate Operation enable.
+                                                         Reset to 1 when the interface SERDES lanes are
+                                                         operating at 1.25 Gbaud (as selected by QLM*_SPD
+                                                         straps). Reset to 0 otherwise. */
+	uint32_t sup_250g                     : 1;  /**< 2.50GB Rate Operation supported.
+                                                         Set when the interface SERDES lanes are operating
+                                                         at 2.5 Gbaud (as selected by QLM*_SPD straps). */
+	uint32_t enb_250g                     : 1;  /**< 2.50GB Rate Operation enable.
+                                                         Reset to 1 when the interface SERDES lanes are
+                                                         operating at 2.5 Gbaud (as selected by QLM*_SPD
+                                                         straps). Reset to 0 otherwise. */
+	uint32_t sup_312g                     : 1;  /**< 3.125GB Rate Operation supported.
+                                                         Set when the interface SERDES lanes are operating
+                                                         at 3.125 Gbaud (as selected by QLM*_SPD straps). */
+	uint32_t enb_312g                     : 1;  /**< 3.125GB Rate Operation enable.
+                                                         Reset to 1 when the interface SERDES lanes are
+                                                         operating at 3.125 Gbaud (as selected by QLM*_SPD
+                                                         straps). Reset to 0 otherwise. */
+	uint32_t sub_500g                     : 1;  /**< 5.0GB Rate Operation supported.
+                                                         Set when the interface SERDES lanes are operating
+                                                         at 5.0 Gbaud (as selected by QLM*_SPD straps). */
+	uint32_t enb_500g                     : 1;  /**< 5.0GB Rate Operation enable.
+                                                         Reset to 1 when the interface SERDES lanes are
+                                                         operating at 5.0 Gbaud (as selected by QLM*_SPD
+                                                         straps). Reset to 0 otherwise. */
+	uint32_t sup_625g                     : 1;  /**< 6.25GB Rate Operation (not supported). */
+	uint32_t enb_625g                     : 1;  /**< 6.25GB Rate Operation enable. */
+	uint32_t reserved_2_15                : 14;
+	uint32_t tx_emph                      : 1;  /**< Indicates whether is port is able to transmit
+                                                         commands to control the transmit emphasis in the
+                                                         connected port. */
+	uint32_t emph_en                      : 1;  /**< Controls whether a port may adjust the
+                                                         transmit emphasis in the connected port.  This bit
+                                                         should be cleared for normal operation. */
+#else
+	uint32_t emph_en                      : 1;
+	uint32_t tx_emph                      : 1;
+	uint32_t reserved_2_15                : 14;
+	uint32_t enb_625g                     : 1;
+	uint32_t sup_625g                     : 1;
+	uint32_t enb_500g                     : 1;
+	uint32_t sub_500g                     : 1;
+	uint32_t enb_312g                     : 1;
+	uint32_t sup_312g                     : 1;
+	uint32_t enb_250g                     : 1;
+	uint32_t sup_250g                     : 1;
+	uint32_t enb_125g                     : 1;
+	uint32_t sup_125g                     : 1;
+	uint32_t baud_enb                     : 1;
+	uint32_t baud_sup                     : 1;
+	uint32_t sel_baud                     : 4;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_ctl2_s  cn63xx;
+	struct cvmx_sriomaintx_port_0_ctl2_s  cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
+
+/**
+ * cvmx_sriomaint#_port_0_err_stat
+ *
+ * SRIOMAINT_PORT_0_ERR_STAT = SRIO Port 0 Error and Status
+ *
+ * Port 0 Error and Status
+ *
+ * Notes:
+ * This register displays port error and status information.  Several port error conditions are
+ *  captured here and must be cleared by writing 1's to the individual bits.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_ERR_STAT hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_err_stat
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_err_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_27_31               : 5;
+	uint32_t pkt_drop                     : 1;  /**< Output Packet Dropped. */
+	uint32_t o_fail                       : 1;  /**< Output Port has encountered a failure condition,
+                                                         meaning the port's failed error threshold has
+                                                         reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_FAIL value. */
+	uint32_t o_dgrad                      : 1;  /**< Output Port has encountered a degraded condition,
+                                                         meaning the port's degraded threshold has
+                                                         reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_DGRAD
+                                                         value. */
+	uint32_t reserved_21_23               : 3;
+	uint32_t o_retry                      : 1;  /**< Output Retry Encountered.  This bit is set when
+                                                         bit 18 is set. */
+	uint32_t o_rtried                     : 1;  /**< Output Port has received a packet-retry condition
+                                                         and cannot make forward progress.  This bit is set
+                                                         when  bit 18 is set and is cleared when a packet-
+                                                         accepted or a packet-not-accepted control symbol
+                                                         is received. */
+	uint32_t o_sm_ret                     : 1;  /**< Output Port State Machine has received a
+                                                         packet-retry control symbol and is retrying the
+                                                         packet. */
+	uint32_t o_error                      : 1;  /**< Output Error Encountered and possibly recovered
+                                                         from.  This sticky bit is set with bit 16. */
+	uint32_t o_sm_err                     : 1;  /**< Output Port State Machine has encountered an
+                                                         error. */
+	uint32_t reserved_11_15               : 5;
+	uint32_t i_sm_ret                     : 1;  /**< Input Port State Machine has received a
+                                                         packet-retry control symbol and is retrying the
+                                                         packet. */
+	uint32_t i_error                      : 1;  /**< Input Error Encountered and possibly recovered
+                                                         from.  This sticky bit is set with bit 8. */
+	uint32_t i_sm_err                     : 1;  /**< Input Port State Machine has encountered an
+                                                         error. */
+	uint32_t reserved_5_7                 : 3;
+	uint32_t pt_write                     : 1;  /**< Port has encountered a condition which required it
+                                                         initiate a Maintenance Port-Write Operation. */
+	uint32_t reserved_3_3                 : 1;
+	uint32_t pt_error                     : 1;  /**< Input or Output Port has encountered an
+                                                         unrecoverable error condition. */
+	uint32_t pt_ok                        : 1;  /**< Input or Output Port are intitialized and the port
+                                                         is exchanging error free control symbols with
+                                                         attached device. */
+	uint32_t pt_uinit                     : 1;  /**< Port is uninitialized.  This bit and bit 1 are
+                                                         mutually exclusive. */
+#else
+	uint32_t pt_uinit                     : 1;
+	uint32_t pt_ok                        : 1;
+	uint32_t pt_error                     : 1;
+	uint32_t reserved_3_3                 : 1;
+	uint32_t pt_write                     : 1;
+	uint32_t reserved_5_7                 : 3;
+	uint32_t i_sm_err                     : 1;
+	uint32_t i_error                      : 1;
+	uint32_t i_sm_ret                     : 1;
+	uint32_t reserved_11_15               : 5;
+	uint32_t o_sm_err                     : 1;
+	uint32_t o_error                      : 1;
+	uint32_t o_sm_ret                     : 1;
+	uint32_t o_rtried                     : 1;
+	uint32_t o_retry                      : 1;
+	uint32_t reserved_21_23               : 3;
+	uint32_t o_dgrad                      : 1;
+	uint32_t o_fail                       : 1;
+	uint32_t pkt_drop                     : 1;
+	uint32_t reserved_27_31               : 5;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_err_stat_s cn63xx;
+	struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t;
+
+/**
+ * cvmx_sriomaint#_port_0_link_req
+ *
+ * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request (Pass 2)
+ *
+ * Port 0 Manual Link Request
+ *
+ * Notes:
+ * Writing this register generates the link request symbol or eight device reset symbols.   The
+ *  progress of the request can be determined by reading SRIOMAINT(0..1)_PORT_0_LINK_RESP.  Only a single
+ *  request should be generated at a time.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LINK_REQ hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_link_req
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_link_req_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t cmd                          : 3;  /**< Link Request Command.
+                                                         011 - Reset Device
+                                                         100 - Link Request
+                                                         All other values reserved. */
+#else
+	uint32_t cmd                          : 3;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_link_req_s cn63xx;
+};
+typedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t;
+
+/**
+ * cvmx_sriomaint#_port_0_link_resp
+ *
+ * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response (Pass 2)
+ *
+ * Port 0 Manual Link Response
+ *
+ * Notes:
+ * This register only returns responses generated by writes to SRIOMAINT(0..1)_PORT_0_LINK_REQ.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LINK_RESP        hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_link_resp
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_link_resp_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t valid                        : 1;  /**< Link Response Valid.
+                                                         1 = Link Response Received or Reset Device
+                                                             Symbols Transmitted.  Value cleared on read.
+                                                         0 = No response received. */
+	uint32_t reserved_11_30               : 20;
+	uint32_t ackid                        : 6;  /**< AckID received from link response.
+                                                         Reset Device symbol response is always zero.
+                                                         Bit 10 is used for IDLE2 and always reads zero. */
+	uint32_t status                       : 5;  /**< Link Response Status.
+                                                         Status supplied by link response.
+                                                         Reset Device symbol response is always zero. */
+#else
+	uint32_t status                       : 5;
+	uint32_t ackid                        : 6;
+	uint32_t reserved_11_30               : 20;
+	uint32_t valid                        : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_link_resp_s cn63xx;
+};
+typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t;
+
+/**
+ * cvmx_sriomaint#_port_0_local_ackid
+ *
+ * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID (Pass 2)
+ *
+ * Port 0 Local AckID Control
+ *
+ * Notes:
+ * This register is typically only written when recovering from a failed link.  It may be read at any
+ *  time the MAC is out of reset.  Writes to the O_ACKID field will be used for both the O_ACKID and
+ *  E_ACKID.  Care must be taken to ensure that no packets are pending at the time of a write.  The
+ *  number of pending packets can be read in the TX_INUSE field of SRIO(0..1)_MAC_BUFFERS.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_0_LOCAL_ACKID      hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_0_local_ackid
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_0_local_ackid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t i_ackid                      : 6;  /**< Next Expected Inbound AckID.
+                                                         Bit 29 is used for IDLE2 and should be zero. */
+	uint32_t reserved_14_23               : 10;
+	uint32_t e_ackid                      : 6;  /**< Next Expected Unacknowledged AckID.
+                                                         Bit 13 is used for IDLE2 and should be zero. */
+	uint32_t reserved_6_7                 : 2;
+	uint32_t o_ackid                      : 6;  /**< Next Outgoing Packet AckID.
+                                                         Bit 5 is used for IDLE2 and should be zero. */
+#else
+	uint32_t o_ackid                      : 6;
+	uint32_t reserved_6_7                 : 2;
+	uint32_t e_ackid                      : 6;
+	uint32_t reserved_14_23               : 10;
+	uint32_t i_ackid                      : 6;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx;
+};
+typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t;
+
+/**
+ * cvmx_sriomaint#_port_gen_ctl
+ *
+ * SRIOMAINT_PORT_GEN_CTL = SRIO Port General Control
+ *
+ * Port General Control
+ *
+ * Notes:
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_GEN_CTL    hclk    hrst_n
+ *
+ */
+union cvmx_sriomaintx_port_gen_ctl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_gen_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t host                         : 1;  /**< Host Device.
+                                                         The HOST reset value is based on corresponding
+                                                         MIO_RST_CTL*[PRTMODE], whose reset value is
+                                                         selected by the corresponding QLM*_HOST_MODE strap
+                                                         on a chip cold reset (and can be later modified by
+                                                         software). HOST resets to 1 when
+                                                         MIO_RST_CTL*[PRTMODE] selects RC (i.e. host) mode,
+                                                         else 0. */
+	uint32_t menable                      : 1;  /**< Master Enable.  Must be set for device to issue
+                                                         read, write, doorbell, message requests. */
+	uint32_t discover                     : 1;  /**< Discovered. The device has been discovered by the
+                                                         host responsible for initialization. */
+	uint32_t reserved_0_28                : 29;
+#else
+	uint32_t reserved_0_28                : 29;
+	uint32_t discover                     : 1;
+	uint32_t menable                      : 1;
+	uint32_t host                         : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_gen_ctl_s cn63xx;
+	struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t;
+
+/**
+ * cvmx_sriomaint#_port_lt_ctl
+ *
+ * SRIOMAINT_PORT_LT_CTL = SRIO Link Layer Timeout Control
+ *
+ * Link Layer Timeout Control
+ *
+ * Notes:
+ * This register controls the timeout for link layer transactions.  It is used as the timeout between
+ *  sending a packet (of any type) or link request to receiving the corresponding link acknowledge or
+ *  link-response.  Each count represents 200ns.  The minimum timeout period is the TIMEOUT x 200nS
+ *  and the maximum is twice that number.  A value less than 32 may not guarantee that all timeout
+ *  errors will be reported correctly.  When the timeout period expires the packet or link request is
+ *  dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0..1)_ERB_ERR_DET register.  A
+ *  value of 0 in this register will allow the packet or link request to be issued but it will timeout
+ *  immediately.  This value is not recommended for normal operation.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_LT_CTL     hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_lt_ctl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_lt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t timeout                      : 24; /**< Timeout Value */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t timeout                      : 24;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_lt_ctl_s  cn63xx;
+	struct cvmx_sriomaintx_port_lt_ctl_s  cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t;
+
+/**
+ * cvmx_sriomaint#_port_mbh0
+ *
+ * SRIOMAINT_PORT_MBH0 = SRIO Port Maintenance Block Header 0
+ *
+ * Port Maintenance Block Header 0
+ *
+ * Notes:
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_MBH0       hclk    hrst_n
+ *
+ */
+union cvmx_sriomaintx_port_mbh0
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_mbh0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ef_ptr                       : 16; /**< Pointer to Error Management Block. */
+	uint32_t ef_id                        : 16; /**< Extended Feature ID (Generic Endpoint Device) */
+#else
+	uint32_t ef_id                        : 16;
+	uint32_t ef_ptr                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_mbh0_s    cn63xx;
+	struct cvmx_sriomaintx_port_mbh0_s    cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t;
+
+/**
+ * cvmx_sriomaint#_port_rt_ctl
+ *
+ * SRIOMAINT_PORT_RT_CTL = SRIO Logical Layer Timeout Control
+ *
+ * Logical Layer Timeout Control
+ *
+ * Notes:
+ * This register controls the timeout for logical layer transactions.  It is used under two
+ *  conditions.  First, it is used as the timeout period between sending a packet requiring a packet
+ *  response being sent to receiving the corresponding response.  This is used for all outgoing packet
+ *  types including memory, maintenance, doorbells and message operations.  When the timeout period
+ *  expires the packet is disgarded and the error is logged in the PKT_TOUT field of the
+ *  SRIOMAINT(0..1)_ERB_LT_ERR_DET register.  The second use of this register is as a timeout period
+ *  between incoming message segments of the same message.  If a message segment is received then the
+ *  MSG_TOUT field of the SRIOMAINT(0..1)_ERB_LT_ERR_DET register is set if the next segment has not been
+ *  received before the time expires.  In both cases, each count represents 200ns.  The minimum
+ *  timeout period is the TIMEOUT x 200nS and the maximum is twice that number.  A value less than 32
+ *  may not guarantee that all timeout errors will be reported correctly.  A value of 0 disables the
+ *  logical layer timeouts and is not recommended for normal operation.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_RT_CTL     hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_rt_ctl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_rt_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t timeout                      : 24; /**< Timeout Value */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t timeout                      : 24;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_rt_ctl_s  cn63xx;
+	struct cvmx_sriomaintx_port_rt_ctl_s  cn63xxp1;
+};
+typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t;
+
+/**
+ * cvmx_sriomaint#_port_ttl_ctl
+ *
+ * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control (Pass 2)
+ *
+ * Packet Time to Live
+ *
+ * Notes:
+ * This register controls the timeout for outgoing packets.  It is used to make sure packets are
+ *  being transmitted and acknowledged within a reasonable period of time.   The timeout value
+ *  corresponds to TIMEOUT x 200ns and a value of 0 disables the timer.  The actualy value of the
+ *  should be greater than the physical layer timout specified in SRIOMAINT(0..1)_PORT_LT_CTL and is
+ *  typically a less SRIOMAINT(0..1)_PORT_LT_CTL timeout than the response timeout specified in
+ *  SRIOMAINT(0..1)_PORT_RT_CTL.  When the timeout expires the TTL interrupt is asserted, any packets
+ *  currently being transmitted are dropped, the SRIOMAINT(0..1)_TX_DROP.DROP bit is set (causing any
+ *  scheduled packets to be dropped), the SRIOMAINT(0..1)_TX_DROP.DROP_CNT is incremented and the SRIO
+ *  output state is set to IDLE (all errors are cleared).  Software must clear the
+ *  SRIOMAINT(0..1)_TX_DROP.DROP bit to resume transmitting packets.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PORT_RT_CTL     hclk    hrst_n
+ */
+union cvmx_sriomaintx_port_ttl_ctl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_port_ttl_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t timeout                      : 24; /**< Timeout Value */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t timeout                      : 24;
+#endif
+	} s;
+	struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx;
+};
+typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t;
+
+/**
+ * cvmx_sriomaint#_pri_dev_id
+ *
+ * SRIOMAINT_PRI_DEV_ID = SRIO Primary Device ID
+ *
+ * Primary 8 and 16 bit Device IDs
+ *
+ * Notes:
+ * This register defines the primary 8 and 16 bit device IDs used for large and small transport.  An
+ *  optional secondary set of device IDs are located in SRIOMAINT(0..1)_SEC_DEV_ID.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_PRI_DEV_ID      hclk    hrst_n
+ */
+union cvmx_sriomaintx_pri_dev_id
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_pri_dev_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t id8                          : 8;  /**< Primary 8-bit Device ID */
+	uint32_t id16                         : 16; /**< Primary 16-bit Device ID */
+#else
+	uint32_t id16                         : 16;
+	uint32_t id8                          : 8;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_pri_dev_id_s   cn63xx;
+	struct cvmx_sriomaintx_pri_dev_id_s   cn63xxp1;
+};
+typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t;
+
+/**
+ * cvmx_sriomaint#_sec_dev_ctrl
+ *
+ * SRIOMAINT_SEC_DEV_CTRL = SRIO Secondary Device ID Control
+ *
+ * Control for Secondary Device IDs
+ *
+ * Notes:
+ * This register enables the secondary 8 and 16 bit device IDs used for large and small transport.
+ *  The corresponding secondary ID must be written before the ID is enabled.  The secondary IDs should
+ *  not be enabled if the values of the primary and secondary IDs are identical.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_SEC_DEV_CTRL    hclk    hrst_n
+ */
+union cvmx_sriomaintx_sec_dev_ctrl
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_sec_dev_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_2_31                : 30;
+	uint32_t enable8                      : 1;  /**< Enable matches to secondary 8-bit Device ID */
+	uint32_t enable16                     : 1;  /**< Enable matches to secondary 16-bit Device ID */
+#else
+	uint32_t enable16                     : 1;
+	uint32_t enable8                      : 1;
+	uint32_t reserved_2_31                : 30;
+#endif
+	} s;
+	struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx;
+	struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t;
+
+/**
+ * cvmx_sriomaint#_sec_dev_id
+ *
+ * SRIOMAINT_SEC_DEV_ID = SRIO Secondary Device ID
+ *
+ * Secondary 8 and 16 bit Device IDs
+ *
+ * Notes:
+ * This register defines the secondary 8 and 16 bit device IDs used for large and small transport.
+ *  The corresponding secondary ID must be written before the ID is enabled in the
+ *  SRIOMAINT(0..1)_SEC_DEV_CTRL register.  The primary set of device IDs are located in
+ *  SRIOMAINT(0..1)_PRI_DEV_ID register.  The secondary IDs should not be written to the same values as the
+ *  corresponding primary IDs.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_SEC_DEV_ID      hclk    hrst_n
+ */
+union cvmx_sriomaintx_sec_dev_id
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_sec_dev_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t id8                          : 8;  /**< Secondary 8-bit Device ID */
+	uint32_t id16                         : 16; /**< Secondary 16-bit Device ID */
+#else
+	uint32_t id16                         : 16;
+	uint32_t id8                          : 8;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_sriomaintx_sec_dev_id_s   cn63xx;
+	struct cvmx_sriomaintx_sec_dev_id_s   cn63xxp1;
+};
+typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t;
+
+/**
+ * cvmx_sriomaint#_serial_lane_hdr
+ *
+ * SRIOMAINT_SERIAL_LANE_HDR = SRIO Serial Lane Header
+ *
+ * SRIO Serial Lane Header
+ *
+ * Notes:
+ * The error management extensions block header register contains the EF_PTR to the next EF_BLK and
+ *  the EF_ID that identifies this as the Serial Lane Status Block.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_SERIAL_LANE_HDR hclk    hrst_n
+ */
+union cvmx_sriomaintx_serial_lane_hdr
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_serial_lane_hdr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ef_ptr                       : 16; /**< Pointer to the next block in the extended features
+                                                         data structure. */
+	uint32_t ef_id                        : 16;
+#else
+	uint32_t ef_id                        : 16;
+	uint32_t ef_ptr                       : 16;
+#endif
+	} s;
+	struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx;
+	struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1;
+};
+typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t;
+
+/**
+ * cvmx_sriomaint#_src_ops
+ *
+ * SRIOMAINT_SRC_OPS = SRIO Source Operations
+ *
+ * The logical operations initiated by the Octeon.
+ *
+ * Notes:
+ * The logical operations initiated by the Cores.   The Source OPs register shows the operations
+ *  specified in the SRIO(0..1)_IP_FEATURE.OPS register.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_SRC_OPS hclk    hrst_n
+ */
+union cvmx_sriomaintx_src_ops
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_src_ops_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t gsm_read                     : 1;  /**< PE does not support Read Home operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
+	uint32_t i_read                       : 1;  /**< PE does not support Instruction Read.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */
+	uint32_t rd_own                       : 1;  /**< PE does not support Read for Ownership.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */
+	uint32_t d_invald                     : 1;  /**< PE does not support Data Cache Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */
+	uint32_t castout                      : 1;  /**< PE does not support Castout Operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */
+	uint32_t d_flush                      : 1;  /**< PE does not support Data Cache Flush.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */
+	uint32_t io_read                      : 1;  /**< PE does not support IO Read.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */
+	uint32_t i_invald                     : 1;  /**< PE does not support Instruction Cache Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */
+	uint32_t tlb_inv                      : 1;  /**< PE does not support TLB Entry Invalidate.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */
+	uint32_t tlb_invs                     : 1;  /**< PE does not support TLB Entry Invalidate Sync.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */
+	uint32_t reserved_16_21               : 6;
+	uint32_t read                         : 1;  /**< PE can support Nread operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */
+	uint32_t write                        : 1;  /**< PE can support Nwrite operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */
+	uint32_t swrite                       : 1;  /**< PE can support Swrite operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */
+	uint32_t write_r                      : 1;  /**< PE can support Write with Response operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */
+	uint32_t msg                          : 1;  /**< PE can support Data Message operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */
+	uint32_t doorbell                     : 1;  /**< PE can support Doorbell operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */
+	uint32_t compswap                     : 1;  /**< PE does not support Atomic Compare and Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */
+	uint32_t testswap                     : 1;  /**< PE does not support Atomic Test and Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */
+	uint32_t atom_inc                     : 1;  /**< PE can support Atomic increment operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */
+	uint32_t atom_dec                     : 1;  /**< PE can support Atomic decrement operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */
+	uint32_t atom_set                     : 1;  /**< PE can support Atomic set operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */
+	uint32_t atom_clr                     : 1;  /**< PE can support Atomic clear operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */
+	uint32_t atom_swp                     : 1;  /**< PE does not support Atomic Swap.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */
+	uint32_t port_wr                      : 1;  /**< PE can Port Write operations.
+                                                         This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t port_wr                      : 1;
+	uint32_t atom_swp                     : 1;
+	uint32_t atom_clr                     : 1;
+	uint32_t atom_set                     : 1;
+	uint32_t atom_dec                     : 1;
+	uint32_t atom_inc                     : 1;
+	uint32_t testswap                     : 1;
+	uint32_t compswap                     : 1;
+	uint32_t doorbell                     : 1;
+	uint32_t msg                          : 1;
+	uint32_t write_r                      : 1;
+	uint32_t swrite                       : 1;
+	uint32_t write                        : 1;
+	uint32_t read                         : 1;
+	uint32_t reserved_16_21               : 6;
+	uint32_t tlb_invs                     : 1;
+	uint32_t tlb_inv                      : 1;
+	uint32_t i_invald                     : 1;
+	uint32_t io_read                      : 1;
+	uint32_t d_flush                      : 1;
+	uint32_t castout                      : 1;
+	uint32_t d_invald                     : 1;
+	uint32_t rd_own                       : 1;
+	uint32_t i_read                       : 1;
+	uint32_t gsm_read                     : 1;
+#endif
+	} s;
+	struct cvmx_sriomaintx_src_ops_s      cn63xx;
+	struct cvmx_sriomaintx_src_ops_s      cn63xxp1;
+};
+typedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t;
+
+/**
+ * cvmx_sriomaint#_tx_drop
+ *
+ * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop (Pass 2)
+ *
+ * Outging SRIO Packet Drop Control/Status
+ *
+ * Notes:
+ * This register controls and provides status for dropping outgoing SRIO packets.  The DROP bit
+ *  should only be cleared when no packets are currently being dropped.  This can be guaranteed by
+ *  clearing the SRIOMAINT(0..1)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the
+ *  O_ENABLE afterwards.
+ *
+ * Clk_Rst:        SRIOMAINT(0..1)_MAC_CTRL        hclk    hrst_n
+ */
+union cvmx_sriomaintx_tx_drop
+{
+	uint32_t u32;
+	struct cvmx_sriomaintx_tx_drop_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_17_31               : 15;
+	uint32_t drop                         : 1;  /**< All outgoing packets are dropped.  Any packets
+                                                         requiring a response will return 1's after the
+                                                         SRIOMAINT(0..1)_PORT_RT_CTL Timeout expires.  This bit
+                                                         is set automatically when the TTL Timeout occurs
+                                                         or can be set by software and must always be
+                                                         cleared by software. */
+	uint32_t drop_cnt                     : 16; /**< Number of packets dropped by transmit logic.
+                                                         Packets are dropped whenever a packet is ready to
+                                                         be transmitted and a TTL Timeouts occur, the  DROP
+                                                         bit is set or the SRIOMAINT(0..1)_ERB_ERR_RATE_THR
+                                                         FAIL_TH has been reached and the DROP_PKT bit is
+                                                         set in SRIOMAINT(0..1)_PORT_0_CTL. */
+#else
+	uint32_t drop_cnt                     : 16;
+	uint32_t drop                         : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_sriomaintx_tx_drop_s      cn63xx;
+};
+typedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sriox-defs.h b/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
new file mode 100644
index 0000000..0055a54
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
@@ -0,0 +1,3703 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-sriox-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon sriox.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SRIOX_TYPEDEFS_H__
+#define __CVMX_SRIOX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64;
+}
+#else
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
+}
+#else
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+
+/**
+ * cvmx_srio#_acc_ctrl
+ *
+ * SRIO_ACC_CTRL = SRIO Access Control
+ *
+ * General access control of the incoming BAR registers.
+ *
+ * Notes:
+ * This register controls write access to the BAR registers via SRIO Maintenance Operations.  At
+ *  powerup the BAR registers can be accessed via RSL and Maintenance Operations.  If the DENY_BAR*
+ *  bits are set then Maintenance Writes to the corresponding BAR registers are ignored.  This
+ *  register does not effect read operations.
+ *
+ * Clk_Rst:        SRIO(0..1)_ACC_CTRL     hclk    hrst_n
+ */
+union cvmx_sriox_acc_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_acc_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t deny_bar2                    : 1;  /**< Deny SRIO Write Access to BAR2 Registers */
+	uint64_t deny_bar1                    : 1;  /**< Deny SRIO Write Access to BAR1 Registers */
+	uint64_t deny_bar0                    : 1;  /**< Deny SRIO Write Access to BAR0 Registers */
+#else
+	uint64_t deny_bar0                    : 1;
+	uint64_t deny_bar1                    : 1;
+	uint64_t deny_bar2                    : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_sriox_acc_ctrl_s          cn63xx;
+	struct cvmx_sriox_acc_ctrl_s          cn63xxp1;
+};
+typedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t;
+
+/**
+ * cvmx_srio#_asmbly_id
+ *
+ * SRIO_ASMBLY_ID = SRIO Assembly ID
+ *
+ * The Assembly ID register controls the Assembly ID and Vendor
+ *
+ * Notes:
+ * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0..1)_ASMBLY_ID register.  The
+ *  Assembly Vendor ID is typically supplied by the RapidIO Trade Association.  This register is only
+ *  reset during COLD boot and may only be modified while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *
+ * Clk_Rst:        SRIO(0..1)_ASMBLY_ID    sclk    srst_cold_n
+ */
+union cvmx_sriox_asmbly_id
+{
+	uint64_t u64;
+	struct cvmx_sriox_asmbly_id_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t assy_id                      : 16; /**< Assembly Identifer */
+	uint64_t assy_ven                     : 16; /**< Assembly Vendor Identifer */
+#else
+	uint64_t assy_ven                     : 16;
+	uint64_t assy_id                      : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_asmbly_id_s         cn63xx;
+	struct cvmx_sriox_asmbly_id_s         cn63xxp1;
+};
+typedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t;
+
+/**
+ * cvmx_srio#_asmbly_info
+ *
+ * SRIO_ASMBLY_INFO = SRIO Assembly Information
+ *
+ * The Assembly Info register controls the Assembly Revision
+ *
+ * Notes:
+ * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the
+ *  SRIOMAINT(0..1)_ASMBLY_INFO register.  This register is only reset during COLD boot and may only be
+ *  modified while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *
+ * Clk_Rst:        SRIO(0..1)_ASMBLY_INFO  sclk    srst_cold_n
+ */
+union cvmx_sriox_asmbly_info
+{
+	uint64_t u64;
+	struct cvmx_sriox_asmbly_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t assy_rev                     : 16; /**< Assembly Revision */
+	uint64_t reserved_0_15                : 16;
+#else
+	uint64_t reserved_0_15                : 16;
+	uint64_t assy_rev                     : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_asmbly_info_s       cn63xx;
+	struct cvmx_sriox_asmbly_info_s       cn63xxp1;
+};
+typedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t;
+
+/**
+ * cvmx_srio#_bell_resp_ctrl
+ *
+ * SRIO_BELL_RESP_CTRL = SRIO Doorbell Response Control
+ *
+ * The SRIO Doorbell Response Control Register
+ *
+ * Notes:
+ * This register is used to override the response priority of the outgoing doorbell responses.
+ *
+ * Clk_Rst:        SRIO(0..1)_BELL_RESP_CTRL       hclk    hrst_n
+ */
+union cvmx_sriox_bell_resp_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_bell_resp_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t rp1_sid                      : 1;  /**< Sets response priority for incomimg doorbells
+                                                         of priority 1 on the secondary ID (0=2, 1=3) */
+	uint64_t rp0_sid                      : 2;  /**< Sets response priority for incomimg doorbells
+                                                         of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
+	uint64_t rp1_pid                      : 1;  /**< Sets response priority for incomimg doorbells
+                                                         of priority 1 on the primary ID (0=2, 1=3) */
+	uint64_t rp0_pid                      : 2;  /**< Sets response priority for incomimg doorbells
+                                                         of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
+#else
+	uint64_t rp0_pid                      : 2;
+	uint64_t rp1_pid                      : 1;
+	uint64_t rp0_sid                      : 2;
+	uint64_t rp1_sid                      : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_sriox_bell_resp_ctrl_s    cn63xx;
+	struct cvmx_sriox_bell_resp_ctrl_s    cn63xxp1;
+};
+typedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t;
+
+/**
+ * cvmx_srio#_bist_status
+ *
+ * SRIO_BIST_STATUS = SRIO Bist Status
+ *
+ * Results from BIST runs of SRIO's memories.
+ *
+ * Notes:
+ * BIST Results.
+ *
+ * Clk_Rst:        SRIO(0..1)_BIST_STATUS  hclk    hrst_n
+ */
+union cvmx_sriox_bist_status
+{
+	uint64_t u64;
+	struct cvmx_sriox_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t mram                         : 2;  /**< Incoming Message SLI FIFO. */
+	uint64_t cram                         : 2;  /**< Incoming Rd/Wr/Response Command FIFO. */
+	uint64_t bell                         : 2;  /**< Incoming Doorbell FIFO. */
+	uint64_t otag                         : 2;  /**< Outgoing Tag Data. */
+	uint64_t itag                         : 1;  /**< Incoming TAG Data. */
+	uint64_t ofree                        : 1;  /**< Outgoing Free Pointer RAM (OFIFO) */
+	uint64_t rtn                          : 2;  /**< Outgoing Response Return FIFO. */
+	uint64_t obulk                        : 4;  /**< Outgoing Bulk Data RAMs (OFIFO) */
+	uint64_t optrs                        : 4;  /**< Outgoing Priority Pointer RAMs (OFIFO) */
+	uint64_t reserved_22_23               : 2;
+	uint64_t rxbuf2                       : 2;  /**< Additional Incoming SRIO MAC Buffers (Pass 2). */
+	uint64_t oarb                         : 2;  /**< Outgoing Priority RAMs (OARB) */
+	uint64_t ispf                         : 1;  /**< Incoming Soft Packet FIFO */
+	uint64_t ospf                         : 1;  /**< Outgoing Soft Packet FIFO */
+	uint64_t txbuf                        : 2;  /**< Outgoing SRIO MAC Buffer. */
+	uint64_t rxbuf                        : 2;  /**< Incoming SRIO MAC Buffer. */
+	uint64_t imsg                         : 5;  /**< Incoming Message RAMs. */
+	uint64_t omsg                         : 7;  /**< Outgoing Message RAMs. */
+#else
+	uint64_t omsg                         : 7;
+	uint64_t imsg                         : 5;
+	uint64_t rxbuf                        : 2;
+	uint64_t txbuf                        : 2;
+	uint64_t ospf                         : 1;
+	uint64_t ispf                         : 1;
+	uint64_t oarb                         : 2;
+	uint64_t rxbuf2                       : 2;
+	uint64_t reserved_22_23               : 2;
+	uint64_t optrs                        : 4;
+	uint64_t obulk                        : 4;
+	uint64_t rtn                          : 2;
+	uint64_t ofree                        : 1;
+	uint64_t itag                         : 1;
+	uint64_t otag                         : 2;
+	uint64_t bell                         : 2;
+	uint64_t cram                         : 2;
+	uint64_t mram                         : 2;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} s;
+	struct cvmx_sriox_bist_status_s       cn63xx;
+	struct cvmx_sriox_bist_status_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_44_63               : 20;
+	uint64_t mram                         : 2;  /**< Incoming Message SLI FIFO. */
+	uint64_t cram                         : 2;  /**< Incoming Rd/Wr/Response Command FIFO. */
+	uint64_t bell                         : 2;  /**< Incoming Doorbell FIFO. */
+	uint64_t otag                         : 2;  /**< Outgoing Tag Data. */
+	uint64_t itag                         : 1;  /**< Incoming TAG Data. */
+	uint64_t ofree                        : 1;  /**< Outgoing Free Pointer RAM (OFIFO) */
+	uint64_t rtn                          : 2;  /**< Outgoing Response Return FIFO. */
+	uint64_t obulk                        : 4;  /**< Outgoing Bulk Data RAMs (OFIFO) */
+	uint64_t optrs                        : 4;  /**< Outgoing Priority Pointer RAMs (OFIFO) */
+	uint64_t reserved_20_23               : 4;
+	uint64_t oarb                         : 2;  /**< Outgoing Priority RAMs (OARB) */
+	uint64_t ispf                         : 1;  /**< Incoming Soft Packet FIFO */
+	uint64_t ospf                         : 1;  /**< Outgoing Soft Packet FIFO */
+	uint64_t txbuf                        : 2;  /**< Outgoing SRIO MAC Buffer. */
+	uint64_t rxbuf                        : 2;  /**< Incoming SRIO MAC Buffer. */
+	uint64_t imsg                         : 5;  /**< Incoming Message RAMs. */
+	uint64_t omsg                         : 7;  /**< Outgoing Message RAMs. */
+#else
+	uint64_t omsg                         : 7;
+	uint64_t imsg                         : 5;
+	uint64_t rxbuf                        : 2;
+	uint64_t txbuf                        : 2;
+	uint64_t ospf                         : 1;
+	uint64_t ispf                         : 1;
+	uint64_t oarb                         : 2;
+	uint64_t reserved_20_23               : 4;
+	uint64_t optrs                        : 4;
+	uint64_t obulk                        : 4;
+	uint64_t rtn                          : 2;
+	uint64_t ofree                        : 1;
+	uint64_t itag                         : 1;
+	uint64_t otag                         : 2;
+	uint64_t bell                         : 2;
+	uint64_t cram                         : 2;
+	uint64_t mram                         : 2;
+	uint64_t reserved_44_63               : 20;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t;
+
+/**
+ * cvmx_srio#_imsg_ctrl
+ *
+ * SRIO_IMSG_CTRL = SRIO Incoming Message Control
+ *
+ * The SRIO Incoming Message Control Register
+ *
+ * Notes:
+ * RSP_THR should not typically be modified from reset value.
+ *
+ * Clk_Rst:        SRIO(0..1)_IMSG_CTRL    hclk    hrst_n
+ */
+union cvmx_sriox_imsg_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_imsg_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t to_mode                      : 1;  /**< MP message timeout mode:
+                                                         - 0: The timeout counter gets reset whenever the
+                                                             next sequential segment is received, regardless
+                                                             of whether it is accepted
+                                                         - 1: The timeout counter gets reset only when the
+                                                             next sequential segment is received and
+                                                             accepted */
+	uint64_t reserved_30_30               : 1;
+	uint64_t rsp_thr                      : 6;  /**< Sets max number of msg responses in queue before
+                                                         sending link-layer retries (field value is added
+                                                         to 16 to create threshold value) */
+	uint64_t reserved_22_23               : 2;
+	uint64_t rp1_sid                      : 1;  /**< Sets msg response priority for incomimg messages
+                                                         of priority 1 on the secondary ID (0=2, 1=3) */
+	uint64_t rp0_sid                      : 2;  /**< Sets msg response priority for incomimg messages
+                                                         of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
+	uint64_t rp1_pid                      : 1;  /**< Sets msg response priority for incomimg messages
+                                                         of priority 1 on the primary ID (0=2, 1=3) */
+	uint64_t rp0_pid                      : 2;  /**< Sets msg response priority for incomimg messages
+                                                         of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
+	uint64_t reserved_15_15               : 1;
+	uint64_t prt_sel                      : 3;  /**< Port/Controller selection method:
+                                                         - 0: Table lookup based on mailbox
+                                                         - 1: Table lookup based on priority
+                                                         - 2: Table lookup based on letter
+                                                         - 3: Size-based (SP to port 0, MP to port 1)
+                                                         - 4: ID-based (pri ID to port 0, sec ID to port 1) */
+	uint64_t lttr                         : 4;  /**< Port/Controller selection letter table */
+	uint64_t prio                         : 4;  /**< Port/Controller selection priority table */
+	uint64_t mbox                         : 4;  /**< Port/Controller selection mailbox table */
+#else
+	uint64_t mbox                         : 4;
+	uint64_t prio                         : 4;
+	uint64_t lttr                         : 4;
+	uint64_t prt_sel                      : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t rp0_pid                      : 2;
+	uint64_t rp1_pid                      : 1;
+	uint64_t rp0_sid                      : 2;
+	uint64_t rp1_sid                      : 1;
+	uint64_t reserved_22_23               : 2;
+	uint64_t rsp_thr                      : 6;
+	uint64_t reserved_30_30               : 1;
+	uint64_t to_mode                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_ctrl_s         cn63xx;
+	struct cvmx_sriox_imsg_ctrl_s         cn63xxp1;
+};
+typedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t;
+
+/**
+ * cvmx_srio#_imsg_inst_hdr#
+ *
+ * SRIO_IMSG_INST_HDRX = SRIO Incoming Message Packet Instruction Header
+ *
+ * The SRIO Port/Controller X Incoming Message Packet Instruction Header Register
+ *
+ * Notes:
+ * SRIO HW generates most of the SRIO_WORD1 fields from these values. SRIO_WORD1 is the 2nd of two
+ *  header words that SRIO inserts in front of all received messages. SRIO_WORD1 may commonly be used
+ *  as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS
+ *  and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields.
+ *
+ * Clk_Rst:        SRIO(0..1)_IMSG_INST_HDR[0:1]   hclk    hrst_n
+ */
+union cvmx_sriox_imsg_inst_hdrx
+{
+	uint64_t u64;
+	struct cvmx_sriox_imsg_inst_hdrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t r                            : 1;  /**< Port/Controller X R */
+	uint64_t reserved_58_62               : 5;
+	uint64_t pm                           : 2;  /**< Port/Controller X PM */
+	uint64_t reserved_55_55               : 1;
+	uint64_t sl                           : 7;  /**< Port/Controller X SL */
+	uint64_t reserved_46_47               : 2;
+	uint64_t nqos                         : 1;  /**< Port/Controller X NQOS */
+	uint64_t ngrp                         : 1;  /**< Port/Controller X NGRP */
+	uint64_t ntt                          : 1;  /**< Port/Controller X NTT */
+	uint64_t ntag                         : 1;  /**< Port/Controller X NTAG */
+	uint64_t reserved_35_41               : 7;
+	uint64_t rs                           : 1;  /**< Port/Controller X RS */
+	uint64_t tt                           : 2;  /**< Port/Controller X TT */
+	uint64_t tag                          : 32; /**< Port/Controller X TAG */
+#else
+	uint64_t tag                          : 32;
+	uint64_t tt                           : 2;
+	uint64_t rs                           : 1;
+	uint64_t reserved_35_41               : 7;
+	uint64_t ntag                         : 1;
+	uint64_t ntt                          : 1;
+	uint64_t ngrp                         : 1;
+	uint64_t nqos                         : 1;
+	uint64_t reserved_46_47               : 2;
+	uint64_t sl                           : 7;
+	uint64_t reserved_55_55               : 1;
+	uint64_t pm                           : 2;
+	uint64_t reserved_58_62               : 5;
+	uint64_t r                            : 1;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_inst_hdrx_s    cn63xx;
+	struct cvmx_sriox_imsg_inst_hdrx_s    cn63xxp1;
+};
+typedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t;
+
+/**
+ * cvmx_srio#_imsg_qos_grp#
+ *
+ * SRIO_IMSG_QOS_GRPX = SRIO Incoming Message QOS/GRP Table
+ *
+ * The SRIO Incoming Message QOS/GRP Table Entry X
+ *
+ * Notes:
+ * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total.
+ *       HW selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is
+ *       used for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc.  HW
+ *       selects the QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as
+ *       shown above. HW then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly
+ *       be used for the PIP/IPD PKT_INST_HDR[QOS,GRP] fields.
+ *
+ * Clk_Rst:        SRIO(0..1)_IMSG_QOS_GRP[0:1]    hclk    hrst_n
+ */
+union cvmx_sriox_imsg_qos_grpx
+{
+	uint64_t u64;
+	struct cvmx_sriox_imsg_qos_grpx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_63_63               : 1;
+	uint64_t qos7                         : 3;  /**< Entry X:7 QOS (ID=1, LETTER=3) */
+	uint64_t grp7                         : 4;  /**< Entry X:7 GRP (ID=1, LETTER=3) */
+	uint64_t reserved_55_55               : 1;
+	uint64_t qos6                         : 3;  /**< Entry X:6 QOS (ID=1, LETTER=2) */
+	uint64_t grp6                         : 4;  /**< Entry X:6 GRP (ID=1, LETTER=2) */
+	uint64_t reserved_47_47               : 1;
+	uint64_t qos5                         : 3;  /**< Entry X:5 QOS (ID=1, LETTER=1) */
+	uint64_t grp5                         : 4;  /**< Entry X:5 GRP (ID=1, LETTER=1) */
+	uint64_t reserved_39_39               : 1;
+	uint64_t qos4                         : 3;  /**< Entry X:4 QOS (ID=1, LETTER=0) */
+	uint64_t grp4                         : 4;  /**< Entry X:4 GRP (ID=1, LETTER=0) */
+	uint64_t reserved_31_31               : 1;
+	uint64_t qos3                         : 3;  /**< Entry X:3 QOS (ID=0, LETTER=3) */
+	uint64_t grp3                         : 4;  /**< Entry X:3 GRP (ID=0, LETTER=3) */
+	uint64_t reserved_23_23               : 1;
+	uint64_t qos2                         : 3;  /**< Entry X:2 QOS (ID=0, LETTER=2) */
+	uint64_t grp2                         : 4;  /**< Entry X:2 GRP (ID=0, LETTER=2) */
+	uint64_t reserved_15_15               : 1;
+	uint64_t qos1                         : 3;  /**< Entry X:1 QOS (ID=0, LETTER=1) */
+	uint64_t grp1                         : 4;  /**< Entry X:1 GRP (ID=0, LETTER=1) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t qos0                         : 3;  /**< Entry X:0 QOS (ID=0, LETTER=0) */
+	uint64_t grp0                         : 4;  /**< Entry X:0 GRP (ID=0, LETTER=0) */
+#else
+	uint64_t grp0                         : 4;
+	uint64_t qos0                         : 3;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t grp1                         : 4;
+	uint64_t qos1                         : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t grp2                         : 4;
+	uint64_t qos2                         : 3;
+	uint64_t reserved_23_23               : 1;
+	uint64_t grp3                         : 4;
+	uint64_t qos3                         : 3;
+	uint64_t reserved_31_31               : 1;
+	uint64_t grp4                         : 4;
+	uint64_t qos4                         : 3;
+	uint64_t reserved_39_39               : 1;
+	uint64_t grp5                         : 4;
+	uint64_t qos5                         : 3;
+	uint64_t reserved_47_47               : 1;
+	uint64_t grp6                         : 4;
+	uint64_t qos6                         : 3;
+	uint64_t reserved_55_55               : 1;
+	uint64_t grp7                         : 4;
+	uint64_t qos7                         : 3;
+	uint64_t reserved_63_63               : 1;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_qos_grpx_s     cn63xx;
+	struct cvmx_sriox_imsg_qos_grpx_s     cn63xxp1;
+};
+typedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t;
+
+/**
+ * cvmx_srio#_imsg_status#
+ *
+ * SRIO_IMSG_STATUSX = SRIO Incoming Message Status Table
+ *
+ * The SRIO Incoming Message Status Table Entry X
+ *
+ * Notes:
+ * Clk_Rst:        SRIO(0..1)_IMSG_STATUS[0:1]     hclk    hrst_n
+ *
+ */
+union cvmx_sriox_imsg_statusx
+{
+	uint64_t u64;
+	struct cvmx_sriox_imsg_statusx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t val1                         : 1;  /**< Entry X:1 Valid */
+	uint64_t err1                         : 1;  /**< Entry X:1 Error */
+	uint64_t toe1                         : 1;  /**< Entry X:1 Timeout Error */
+	uint64_t toc1                         : 1;  /**< Entry X:1 Timeout Count */
+	uint64_t prt1                         : 1;  /**< Entry X:1 Port */
+	uint64_t reserved_58_58               : 1;
+	uint64_t tt1                          : 1;  /**< Entry X:1 TT ID */
+	uint64_t dis1                         : 1;  /**< Entry X:1 Dest ID */
+	uint64_t seg1                         : 4;  /**< Entry X:1 Next Segment */
+	uint64_t mbox1                        : 2;  /**< Entry X:1 Mailbox */
+	uint64_t lttr1                        : 2;  /**< Entry X:1 Letter */
+	uint64_t sid1                         : 16; /**< Entry X:1 Source ID */
+	uint64_t val0                         : 1;  /**< Entry X:0 Valid */
+	uint64_t err0                         : 1;  /**< Entry X:0 Error */
+	uint64_t toe0                         : 1;  /**< Entry X:0 Timeout Error */
+	uint64_t toc0                         : 1;  /**< Entry X:0 Timeout Count */
+	uint64_t prt0                         : 1;  /**< Entry X:0 Port */
+	uint64_t reserved_26_26               : 1;
+	uint64_t tt0                          : 1;  /**< Entry X:0 TT ID */
+	uint64_t dis0                         : 1;  /**< Entry X:0 Dest ID */
+	uint64_t seg0                         : 4;  /**< Entry X:0 Next Segment */
+	uint64_t mbox0                        : 2;  /**< Entry X:0 Mailbox */
+	uint64_t lttr0                        : 2;  /**< Entry X:0 Letter */
+	uint64_t sid0                         : 16; /**< Entry X:0 Source ID */
+#else
+	uint64_t sid0                         : 16;
+	uint64_t lttr0                        : 2;
+	uint64_t mbox0                        : 2;
+	uint64_t seg0                         : 4;
+	uint64_t dis0                         : 1;
+	uint64_t tt0                          : 1;
+	uint64_t reserved_26_26               : 1;
+	uint64_t prt0                         : 1;
+	uint64_t toc0                         : 1;
+	uint64_t toe0                         : 1;
+	uint64_t err0                         : 1;
+	uint64_t val0                         : 1;
+	uint64_t sid1                         : 16;
+	uint64_t lttr1                        : 2;
+	uint64_t mbox1                        : 2;
+	uint64_t seg1                         : 4;
+	uint64_t dis1                         : 1;
+	uint64_t tt1                          : 1;
+	uint64_t reserved_58_58               : 1;
+	uint64_t prt1                         : 1;
+	uint64_t toc1                         : 1;
+	uint64_t toe1                         : 1;
+	uint64_t err1                         : 1;
+	uint64_t val1                         : 1;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_statusx_s      cn63xx;
+	struct cvmx_sriox_imsg_statusx_s      cn63xxp1;
+};
+typedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t;
+
+/**
+ * cvmx_srio#_imsg_vport_thr
+ *
+ * SRIO_IMSG_VPORT_THR = SRIO Incoming Message Virtual Port Threshold
+ *
+ * The SRIO Incoming Message Virtual Port Threshold Register
+ *
+ * Notes:
+ * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR + SRIO1_IMSG_VPORT_THR.BUF_THR
+ * This register can be accessed regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS and is not
+ * effected by MAC reset.
+ *
+ * Clk_Rst:        SRIO(0..1)_IMSG_VPORT_THR       sclk    srst_n
+ */
+union cvmx_sriox_imsg_vport_thr
+{
+	uint64_t u64;
+	struct cvmx_sriox_imsg_vport_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_54_63               : 10;
+	uint64_t max_tot                      : 6;  /**< Sets max number of vports available to SRIO0+SRIO1
+                                                         This field is only used in SRIO0.
+                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_TOT]. */
+	uint64_t reserved_46_47               : 2;
+	uint64_t max_s1                       : 6;  /**< Sets max number of vports available to SRIO1
+                                                         This field is only used in SRIO0.
+                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S1]. */
+	uint64_t reserved_38_39               : 2;
+	uint64_t max_s0                       : 6;  /**< Sets max number of vports available to SRIO0
+                                                         This field is only used in SRIO0.
+                                                         SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S0]. */
+	uint64_t sp_vport                     : 1;  /**< Single-segment vport pre-allocation.
+                                                         When set, single-segment messages use pre-allocated
+                                                         vport slots (that do not count toward thresholds).
+                                                         When clear, single-segment messages must allocate
+                                                         vport slots just like multi-segment messages do. */
+	uint64_t reserved_20_30               : 11;
+	uint64_t buf_thr                      : 4;  /**< Sets number of vports to be buffered by this
+                                                         interface. BUF_THR must not be zero when receiving
+                                                         messages. The max BUF_THR value is 8.
+                                                         Recommend BUF_THR values 1-4. If the 46 available
+                                                         vports are not statically-allocated across the two
+                                                         SRIO's, smaller BUF_THR values may leave more
+                                                         vports available for the other SRIO. Lack of a
+                                                         buffered vport can force a retry for a received
+                                                         first segment, so, particularly if SP_VPORT=0
+                                                         (which is not recommended) or the segment size is
+                                                         small, larger BUF_THR values may improve
+                                                         performance. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t max_p1                       : 6;  /**< Sets max number of open vports in port 1 */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t max_p0                       : 6;  /**< Sets max number of open vports in port 0 */
+#else
+	uint64_t max_p0                       : 6;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t max_p1                       : 6;
+	uint64_t reserved_14_15               : 2;
+	uint64_t buf_thr                      : 4;
+	uint64_t reserved_20_30               : 11;
+	uint64_t sp_vport                     : 1;
+	uint64_t max_s0                       : 6;
+	uint64_t reserved_38_39               : 2;
+	uint64_t max_s1                       : 6;
+	uint64_t reserved_46_47               : 2;
+	uint64_t max_tot                      : 6;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_sriox_imsg_vport_thr_s    cn63xx;
+	struct cvmx_sriox_imsg_vport_thr_s    cn63xxp1;
+};
+typedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t;
+
+/**
+ * cvmx_srio#_int2_enable
+ *
+ * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable (Pass 2)
+ *
+ * Allows SRIO to generate additional interrupts when corresponding enable bit is set.
+ *
+ * Notes:
+ * This register enables interrupts in SRIO(0..1)_INT2_REG that can be asserted while the MAC is in reset.
+ *  The register can be accessed/modified regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT2_ENABLE  sclk    srst_n
+ */
+union cvmx_sriox_int2_enable
+{
+	uint64_t u64;
+	struct cvmx_sriox_int2_enable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t pko_rst                      : 1;  /**< PKO Reset Error Enable */
+#else
+	uint64_t pko_rst                      : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_sriox_int2_enable_s       cn63xx;
+};
+typedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t;
+
+/**
+ * cvmx_srio#_int2_reg
+ *
+ * SRIO_INT2_REG = SRIO Interrupt 2 Register (Pass 2)
+ *
+ * Displays and clears which enabled interrupts have occured
+ *
+ * Notes:
+ * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed
+ *  whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not.
+ *  INT_SUM shows the status of the interrupts in SRIO(0..1)_INT_REG.  Any set bits written to this
+ *  register clear the corresponding interrupt.  The register can be accessed/modified regardless of
+ *  the value of SRIO(0..1)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO
+ *  interrupt occurs.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT2_REG     sclk    srst_n
+ */
+union cvmx_sriox_int2_reg
+{
+	uint64_t u64;
+	struct cvmx_sriox_int2_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t int_sum                      : 1;  /**< Interrupt Set and Enabled in SRIO(0..1)_INT_REG */
+	uint64_t reserved_1_30                : 30;
+	uint64_t pko_rst                      : 1;  /**< PKO Reset Error - Message Received from PKO while
+                                                         MAC in reset. */
+#else
+	uint64_t pko_rst                      : 1;
+	uint64_t reserved_1_30                : 30;
+	uint64_t int_sum                      : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_int2_reg_s          cn63xx;
+};
+typedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t;
+
+/**
+ * cvmx_srio#_int_enable
+ *
+ * SRIO_INT_ENABLE = SRIO Interrupt Enable
+ *
+ * Allows SRIO to generate interrupts when corresponding enable bit is set.
+ *
+ * Notes:
+ * This register enables interrupts.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_ENABLE   hclk    hrst_n
+ */
+union cvmx_sriox_int_enable
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_enable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_26_63               : 38;
+	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout (Pass 2) */
+	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count (Pass 2) */
+	uint64_t degrade                      : 1;  /**< ERB Error Rate reached Degrade Count (Pass 2) */
+	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error (Pass 2) */
+	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
+	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded */
+	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
+	uint64_t omsg_err                     : 1;  /**< Outbound Message Invalid Descriptor Error */
+	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete */
+	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete */
+	uint64_t link_up                      : 1;  /**< Serial Link going from Inactive to Active */
+	uint64_t link_dwn                     : 1;  /**< Serial Link going from Active to Inactive */
+	uint64_t phy_erb                      : 1;  /**< Physical Layer Error detected in ERB */
+	uint64_t log_erb                      : 1;  /**< Logical/Transport Layer Error detected in ERB */
+	uint64_t soft_rx                      : 1;  /**< Incoming Packet received by Soft Packet FIFO */
+	uint64_t soft_tx                      : 1;  /**< Outgoing Packet sent by Soft Packet FIFO */
+	uint64_t mce_rx                       : 1;  /**< Incoming Multicast Event Symbol */
+	uint64_t mce_tx                       : 1;  /**< Outgoing Multicast Event Transmit Complete */
+	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received. */
+	uint64_t sli_err                      : 1;  /**< Unsupported S2M Transaction Received. */
+	uint64_t deny_wr                      : 1;  /**< Incoming Maint_Wr Access to Denied Bar Registers. */
+	uint64_t bar_err                      : 1;  /**< Incoming Access Crossing/Missing BAR Address */
+	uint64_t maint_op                     : 1;  /**< Internal Maintenance Operation Complete. */
+	uint64_t rxbell                       : 1;  /**< One or more Incoming Doorbells Received. */
+	uint64_t bell_err                     : 1;  /**< Outgoing Doorbell Timeout, Retry or Error. */
+	uint64_t txbell                       : 1;  /**< Outgoing Doorbell Complete. */
+#else
+	uint64_t txbell                       : 1;
+	uint64_t bell_err                     : 1;
+	uint64_t rxbell                       : 1;
+	uint64_t maint_op                     : 1;
+	uint64_t bar_err                      : 1;
+	uint64_t deny_wr                      : 1;
+	uint64_t sli_err                      : 1;
+	uint64_t wr_done                      : 1;
+	uint64_t mce_tx                       : 1;
+	uint64_t mce_rx                       : 1;
+	uint64_t soft_tx                      : 1;
+	uint64_t soft_rx                      : 1;
+	uint64_t log_erb                      : 1;
+	uint64_t phy_erb                      : 1;
+	uint64_t link_dwn                     : 1;
+	uint64_t link_up                      : 1;
+	uint64_t omsg0                        : 1;
+	uint64_t omsg1                        : 1;
+	uint64_t omsg_err                     : 1;
+	uint64_t pko_err                      : 1;
+	uint64_t rtry_err                     : 1;
+	uint64_t f_error                      : 1;
+	uint64_t mac_buf                      : 1;
+	uint64_t degrade                      : 1;
+	uint64_t fail                         : 1;
+	uint64_t ttl_tout                     : 1;
+	uint64_t reserved_26_63               : 38;
+#endif
+	} s;
+	struct cvmx_sriox_int_enable_s        cn63xx;
+	struct cvmx_sriox_int_enable_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
+	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded */
+	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
+	uint64_t omsg_err                     : 1;  /**< Outbound Message Invalid Descriptor Error */
+	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete */
+	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete */
+	uint64_t link_up                      : 1;  /**< Serial Link going from Inactive to Active */
+	uint64_t link_dwn                     : 1;  /**< Serial Link going from Active to Inactive */
+	uint64_t phy_erb                      : 1;  /**< Physical Layer Error detected in ERB */
+	uint64_t log_erb                      : 1;  /**< Logical/Transport Layer Error detected in ERB */
+	uint64_t soft_rx                      : 1;  /**< Incoming Packet received by Soft Packet FIFO */
+	uint64_t soft_tx                      : 1;  /**< Outgoing Packet sent by Soft Packet FIFO */
+	uint64_t mce_rx                       : 1;  /**< Incoming Multicast Event Symbol */
+	uint64_t mce_tx                       : 1;  /**< Outgoing Multicast Event Transmit Complete */
+	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received. */
+	uint64_t sli_err                      : 1;  /**< Unsupported S2M Transaction Received. */
+	uint64_t deny_wr                      : 1;  /**< Incoming Maint_Wr Access to Denied Bar Registers. */
+	uint64_t bar_err                      : 1;  /**< Incoming Access Crossing/Missing BAR Address */
+	uint64_t maint_op                     : 1;  /**< Internal Maintenance Operation Complete. */
+	uint64_t rxbell                       : 1;  /**< One or more Incoming Doorbells Received. */
+	uint64_t bell_err                     : 1;  /**< Outgoing Doorbell Timeout, Retry or Error. */
+	uint64_t txbell                       : 1;  /**< Outgoing Doorbell Complete. */
+#else
+	uint64_t txbell                       : 1;
+	uint64_t bell_err                     : 1;
+	uint64_t rxbell                       : 1;
+	uint64_t maint_op                     : 1;
+	uint64_t bar_err                      : 1;
+	uint64_t deny_wr                      : 1;
+	uint64_t sli_err                      : 1;
+	uint64_t wr_done                      : 1;
+	uint64_t mce_tx                       : 1;
+	uint64_t mce_rx                       : 1;
+	uint64_t soft_tx                      : 1;
+	uint64_t soft_rx                      : 1;
+	uint64_t log_erb                      : 1;
+	uint64_t phy_erb                      : 1;
+	uint64_t link_dwn                     : 1;
+	uint64_t link_up                      : 1;
+	uint64_t omsg0                        : 1;
+	uint64_t omsg1                        : 1;
+	uint64_t omsg_err                     : 1;
+	uint64_t pko_err                      : 1;
+	uint64_t rtry_err                     : 1;
+	uint64_t f_error                      : 1;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t;
+
+/**
+ * cvmx_srio#_int_info0
+ *
+ * SRIO_INT_INFO0 = SRIO Interrupt Information
+ *
+ * The SRIO Interrupt Information
+ *
+ * Notes:
+ * This register contains the first header word of the illegal s2m transaction associated with the
+ *  SLI_ERR interrupt.  The remaining information is located in SRIO(0..1)_INT_INFO1.   This register is
+ *  only updated when the SLI_ERR is initially detected.  Once the interrupt is cleared then
+ *  additional information can be captured.
+ *  Common Errors Include:
+ *   1.  Load/Stores with Length over 32
+ *   2.  Load/Stores that translate to Maintenance Ops with a length over 8
+ *   3.  Load Ops that translate to Atomic Ops with other than 1, 2 and 4 byte accesses
+ *   4.  Load/Store Ops with a Length 0
+ *   5.  Unexpected Responses
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ */
+union cvmx_sriox_int_info0
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_info0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cmd                          : 4;  /**< Command
+                                                         0 = Load, Outgoing Read Request
+                                                         4 = Store, Outgoing Write Request
+                                                         8 = Response, Outgoing Read Response
+                                                         All Others are reserved and generate errors */
+	uint64_t type                         : 4;  /**< Command Type
+                                                         Load/Store SRIO_S2M_TYPE used
+                                                         Response (Reserved) */
+	uint64_t tag                          : 8;  /**< Internal Transaction Number */
+	uint64_t reserved_42_47               : 6;
+	uint64_t length                       : 10; /**< Data Length in 64-bit Words (Load/Store Only) */
+	uint64_t status                       : 3;  /**< Response Status
+                                                         0 = Success
+                                                         1 = Error
+                                                         All others reserved */
+	uint64_t reserved_16_28               : 13;
+	uint64_t be0                          : 8;  /**< First 64-bit Word Byte Enables (Load/Store Only) */
+	uint64_t be1                          : 8;  /**< Last 64-bit Word Byte Enables (Load/Store Only) */
+#else
+	uint64_t be1                          : 8;
+	uint64_t be0                          : 8;
+	uint64_t reserved_16_28               : 13;
+	uint64_t status                       : 3;
+	uint64_t length                       : 10;
+	uint64_t reserved_42_47               : 6;
+	uint64_t tag                          : 8;
+	uint64_t type                         : 4;
+	uint64_t cmd                          : 4;
+#endif
+	} s;
+	struct cvmx_sriox_int_info0_s         cn63xx;
+	struct cvmx_sriox_int_info0_s         cn63xxp1;
+};
+typedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t;
+
+/**
+ * cvmx_srio#_int_info1
+ *
+ * SRIO_INT_INFO1 = SRIO Interrupt Information
+ *
+ * The SRIO Interrupt Information
+ *
+ * Notes:
+ * This register contains the second header word of the illegal s2m transaction associated with the
+ *  SLI_ERR interrupt.  The remaining information is located in SRIO(0..1)_INT_INFO0.   This register is
+ *  only updated when the SLI_ERR is initially detected.  Once the interrupt is cleared then
+ *  additional information can be captured.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ */
+union cvmx_sriox_int_info1
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_info1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t info1                        : 64; /**< Address (Load/Store) or First 64-bit Word of
+                                                         Response Data Associated with Interrupt */
+#else
+	uint64_t info1                        : 64;
+#endif
+	} s;
+	struct cvmx_sriox_int_info1_s         cn63xx;
+	struct cvmx_sriox_int_info1_s         cn63xxp1;
+};
+typedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t;
+
+/**
+ * cvmx_srio#_int_info2
+ *
+ * SRIO_INT_INFO2 = SRIO Interrupt Information
+ *
+ * The SRIO Interrupt Information
+ *
+ * Notes:
+ * This register contains the invalid outbound message descriptor associated with the OMSG_ERR
+ *  interrupt.  This register is only updated when the OMSG_ERR is initially detected.  Once the
+ *  interrupt is cleared then additional information can be captured.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ */
+union cvmx_sriox_int_info2
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_info2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t prio                         : 2;  /**< PRIO field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t tt                           : 1;  /**< TT field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t sis                          : 1;  /**< SIS field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t ssize                        : 4;  /**< SSIZE field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t did                          : 16; /**< DID field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t xmbox                        : 4;  /**< XMBOX field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t mbox                         : 2;  /**< MBOX field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t letter                       : 2;  /**< LETTER field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t rsrvd                        : 30; /**< RSRVD field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t lns                          : 1;  /**< LNS field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+	uint64_t intr                         : 1;  /**< INT field of outbound message descriptor
+                                                         associated with the OMSG_ERR interrupt */
+#else
+	uint64_t intr                         : 1;
+	uint64_t lns                          : 1;
+	uint64_t rsrvd                        : 30;
+	uint64_t letter                       : 2;
+	uint64_t mbox                         : 2;
+	uint64_t xmbox                        : 4;
+	uint64_t did                          : 16;
+	uint64_t ssize                        : 4;
+	uint64_t sis                          : 1;
+	uint64_t tt                           : 1;
+	uint64_t prio                         : 2;
+#endif
+	} s;
+	struct cvmx_sriox_int_info2_s         cn63xx;
+	struct cvmx_sriox_int_info2_s         cn63xxp1;
+};
+typedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t;
+
+/**
+ * cvmx_srio#_int_info3
+ *
+ * SRIO_INT_INFO3 = SRIO Interrupt Information
+ *
+ * The SRIO Interrupt Information
+ *
+ * Notes:
+ * This register contains the retry response associated with the RTRY_ERR interrupt.  This register
+ *  is only updated when the RTRY_ERR is initially detected.  Once the interrupt is cleared then
+ *  additional information can be captured.
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ */
+union cvmx_sriox_int_info3
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_info3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t prio                         : 2;  /**< Priority of received retry response message */
+	uint64_t tt                           : 2;  /**< TT of received retry response message */
+	uint64_t type                         : 4;  /**< Type of received retry response message
+                                                         (should be 13) */
+	uint64_t other                        : 48; /**< Other fields of received retry response message
+                                                         If TT==0 (8-bit ID's)
+                                                          OTHER<47:40> => destination ID
+                                                          OTHER<39:32> => source ID
+                                                          OTHER<31:28> => transaction (should be 1 - msg)
+                                                          OTHER<27:24> => status (should be 3 - retry)
+                                                          OTHER<23:22> => letter
+                                                          OTHER<21:20> => mbox
+                                                          OTHER<19:16> => msgseg
+                                                          OTHER<15:0>  => unused
+                                                         If TT==1 (16-bit ID's)
+                                                          OTHER<47:32> => destination ID
+                                                          OTHER<31:16> => source ID
+                                                          OTHER<15:12> => transaction (should be 1 - msg)
+                                                          OTHER<11:8>  => status (should be 3 - retry)
+                                                          OTHER<7:6>   => letter
+                                                          OTHER<5:4>   => mbox
+                                                          OTHER<3:0>   => msgseg */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t other                        : 48;
+	uint64_t type                         : 4;
+	uint64_t tt                           : 2;
+	uint64_t prio                         : 2;
+#endif
+	} s;
+	struct cvmx_sriox_int_info3_s         cn63xx;
+	struct cvmx_sriox_int_info3_s         cn63xxp1;
+};
+typedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t;
+
+/**
+ * cvmx_srio#_int_reg
+ *
+ * SRIO_INT_REG = SRIO Interrupt Register
+ *
+ * Displays and clears which enabled interrupts have occured
+ *
+ * Notes:
+ * This register provides interrupt status.  Like most SRIO CSRs, this register can only
+ *  be read/written when the corresponding SRIO is both present and not in reset. (SRIO*_INT2_REG
+ *  can be accessed when SRIO is in reset.) Any set bits written to this register clear the
+ *  corresponding interrupt.  The RXBELL interrupt is cleared by reading all the entries in the
+ *  incoming Doorbell FIFO.  The LOG_ERB interrupt must be cleared before writing zeroes
+ *  to clear the bits in the SRIOMAINT*_ERB_LT_ERR_DET register.  Otherwise a new interrupt may be
+ *  lost. The PHY_ERB interrupt must be cleared before writing a zero to
+ *  SRIOMAINT*_ERB_ATTR_CAPT[VALID]. Otherwise, a new interrupt may be lost.  OMSG_ERR is set when an
+ *  invalid outbound message descriptor is received.  The descriptor is deemed to be invalid if the
+ *  SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would
+ *  result in more than 16 message segments, or the packet only contains a descriptor (no data).
+ *
+ * Clk_Rst:        SRIO(0..1)_INT_REG      hclk    hrst_n
+ */
+union cvmx_sriox_int_reg
+{
+	uint64_t u64;
+	struct cvmx_sriox_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t int2_sum                     : 1;  /**< Interrupt Set and Enabled in SRIO(0..1)_INT2_REG
+                                                         (Pass 2) */
+	uint64_t reserved_26_30               : 5;
+	uint64_t ttl_tout                     : 1;  /**< Outgoing Packet Time to Live Timeout (Pass 2)
+                                                         See SRIOMAINT(0..1)_DROP_PACKET */
+	uint64_t fail                         : 1;  /**< ERB Error Rate reached Fail Count (Pass 2)
+                                                         See SRIOMAINT(0..1)_ERB_ERR_RATE */
+	uint64_t degrad                       : 1;  /**< ERB Error Rate reached Degrade Count (Pass 2)
+                                                         See SRIOMAINT(0..1)_ERB_ERR_RATE */
+	uint64_t mac_buf                      : 1;  /**< SRIO MAC Buffer CRC Error (Pass 2)
+                                                         See SRIO(0..1)_MAC_BUFFERS */
+	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
+	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded
+                                                         See SRIO(0..1)_INT_INFO3
+                                                         When one or more of the segments in an outgoing
+                                                         message have a RTRY_ERR, SRIO will not set
+                                                         OMSG* after the message "transfer". */
+	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
+	uint64_t omsg_err                     : 1;  /**< Outbound Message Invalid Descriptor Error
+                                                         See SRIO(0..1)_INT_INFO2 */
+	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete */
+	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete */
+	uint64_t link_up                      : 1;  /**< Serial Link going from Inactive to Active */
+	uint64_t link_dwn                     : 1;  /**< Serial Link going from Active to Inactive */
+	uint64_t phy_erb                      : 1;  /**< Physical Layer Error detected in ERB
+                                                         See SRIOMAINT*_ERB_ATTR_CAPT */
+	uint64_t log_erb                      : 1;  /**< Logical/Transport Layer Error detected in ERB
+                                                         See SRIOMAINT(0..1)_ERB_LT_ERR_DET */
+	uint64_t soft_rx                      : 1;  /**< Incoming Packet received by Soft Packet FIFO */
+	uint64_t soft_tx                      : 1;  /**< Outgoing Packet sent by Soft Packet FIFO */
+	uint64_t mce_rx                       : 1;  /**< Incoming Multicast Event Symbol */
+	uint64_t mce_tx                       : 1;  /**< Outgoing Multicast Event Transmit Complete */
+	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received. */
+	uint64_t sli_err                      : 1;  /**< Unsupported S2M Transaction Received.
+                                                         See SRIO(0..1)_INT_INFO[1:0] */
+	uint64_t deny_wr                      : 1;  /**< Incoming Maint_Wr Access to Denied Bar Registers. */
+	uint64_t bar_err                      : 1;  /**< Incoming Access Crossing/Missing BAR Address */
+	uint64_t maint_op                     : 1;  /**< Internal Maintenance Operation Complete.
+                                                         See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */
+	uint64_t rxbell                       : 1;  /**< One or more Incoming Doorbells Received.
+                                                         Read SRIO(0..1)_RX_BELL to empty FIFO */
+	uint64_t bell_err                     : 1;  /**< Outgoing Doorbell Timeout, Retry or Error.
+                                                         See SRIO(0..1)_TX_BELL_INFO */
+	uint64_t txbell                       : 1;  /**< Outgoing Doorbell Complete.
+                                                         TXBELL will not be asserted if a Timeout, Retry or
+                                                         Error occurs. */
+#else
+	uint64_t txbell                       : 1;
+	uint64_t bell_err                     : 1;
+	uint64_t rxbell                       : 1;
+	uint64_t maint_op                     : 1;
+	uint64_t bar_err                      : 1;
+	uint64_t deny_wr                      : 1;
+	uint64_t sli_err                      : 1;
+	uint64_t wr_done                      : 1;
+	uint64_t mce_tx                       : 1;
+	uint64_t mce_rx                       : 1;
+	uint64_t soft_tx                      : 1;
+	uint64_t soft_rx                      : 1;
+	uint64_t log_erb                      : 1;
+	uint64_t phy_erb                      : 1;
+	uint64_t link_dwn                     : 1;
+	uint64_t link_up                      : 1;
+	uint64_t omsg0                        : 1;
+	uint64_t omsg1                        : 1;
+	uint64_t omsg_err                     : 1;
+	uint64_t pko_err                      : 1;
+	uint64_t rtry_err                     : 1;
+	uint64_t f_error                      : 1;
+	uint64_t mac_buf                      : 1;
+	uint64_t degrad                       : 1;
+	uint64_t fail                         : 1;
+	uint64_t ttl_tout                     : 1;
+	uint64_t reserved_26_30               : 5;
+	uint64_t int2_sum                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_int_reg_s           cn63xx;
+	struct cvmx_sriox_int_reg_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_22_63               : 42;
+	uint64_t f_error                      : 1;  /**< SRIO Fatal Port Error (MAC reset required) */
+	uint64_t rtry_err                     : 1;  /**< Outbound Message Retry Threshold Exceeded
+                                                         See SRIO(0..1)_INT_INFO3
+                                                         When one or more of the segments in an outgoing
+                                                         message have a RTRY_ERR, SRIO will not set
+                                                         OMSG* after the message "transfer". */
+	uint64_t pko_err                      : 1;  /**< Outbound Message Received PKO Error */
+	uint64_t omsg_err                     : 1;  /**< Outbound Message Invalid Descriptor Error
+                                                         See SRIO(0..1)_INT_INFO2 */
+	uint64_t omsg1                        : 1;  /**< Controller 1 Outbound Message Complete */
+	uint64_t omsg0                        : 1;  /**< Controller 0 Outbound Message Complete */
+	uint64_t link_up                      : 1;  /**< Serial Link going from Inactive to Active */
+	uint64_t link_dwn                     : 1;  /**< Serial Link going from Active to Inactive */
+	uint64_t phy_erb                      : 1;  /**< Physical Layer Error detected in ERB
+                                                         See SRIOMAINT*_ERB_ATTR_CAPT */
+	uint64_t log_erb                      : 1;  /**< Logical/Transport Layer Error detected in ERB
+                                                         See SRIOMAINT(0..1)_ERB_LT_ERR_DET */
+	uint64_t soft_rx                      : 1;  /**< Incoming Packet received by Soft Packet FIFO */
+	uint64_t soft_tx                      : 1;  /**< Outgoing Packet sent by Soft Packet FIFO */
+	uint64_t mce_rx                       : 1;  /**< Incoming Multicast Event Symbol */
+	uint64_t mce_tx                       : 1;  /**< Outgoing Multicast Event Transmit Complete */
+	uint64_t wr_done                      : 1;  /**< Outgoing Last Nwrite_R DONE Response Received. */
+	uint64_t sli_err                      : 1;  /**< Unsupported S2M Transaction Received.
+                                                         See SRIO(0..1)_INT_INFO[1:0] */
+	uint64_t deny_wr                      : 1;  /**< Incoming Maint_Wr Access to Denied Bar Registers. */
+	uint64_t bar_err                      : 1;  /**< Incoming Access Crossing/Missing BAR Address */
+	uint64_t maint_op                     : 1;  /**< Internal Maintenance Operation Complete.
+                                                         See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */
+	uint64_t rxbell                       : 1;  /**< One or more Incoming Doorbells Received.
+                                                         Read SRIO(0..1)_RX_BELL to empty FIFO */
+	uint64_t bell_err                     : 1;  /**< Outgoing Doorbell Timeout, Retry or Error.
+                                                         See SRIO(0..1)_TX_BELL_INFO */
+	uint64_t txbell                       : 1;  /**< Outgoing Doorbell Complete.
+                                                         TXBELL will not be asserted if a Timeout, Retry or
+                                                         Error occurs. */
+#else
+	uint64_t txbell                       : 1;
+	uint64_t bell_err                     : 1;
+	uint64_t rxbell                       : 1;
+	uint64_t maint_op                     : 1;
+	uint64_t bar_err                      : 1;
+	uint64_t deny_wr                      : 1;
+	uint64_t sli_err                      : 1;
+	uint64_t wr_done                      : 1;
+	uint64_t mce_tx                       : 1;
+	uint64_t mce_rx                       : 1;
+	uint64_t soft_tx                      : 1;
+	uint64_t soft_rx                      : 1;
+	uint64_t log_erb                      : 1;
+	uint64_t phy_erb                      : 1;
+	uint64_t link_dwn                     : 1;
+	uint64_t link_up                      : 1;
+	uint64_t omsg0                        : 1;
+	uint64_t omsg1                        : 1;
+	uint64_t omsg_err                     : 1;
+	uint64_t pko_err                      : 1;
+	uint64_t rtry_err                     : 1;
+	uint64_t f_error                      : 1;
+	uint64_t reserved_22_63               : 42;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t;
+
+/**
+ * cvmx_srio#_ip_feature
+ *
+ * SRIO_IP_FEATURE = SRIO IP Feature Select
+ *
+ * Debug Register used to enable IP Core Features
+ *
+ * Notes:
+ * This register is used to override powerup values used by the SRIOMAINT Registers and QLM
+ *  configuration.  The register is only reset during COLD boot.  It should only be modified only
+ *  while SRIO(0..1)_STATUS_REG.ACCESS is zero.
+ *
+ * Clk_Rst:        SRIO(0..1)_IP_FEATURE   sclk    srst_cold_n
+ */
+union cvmx_sriox_ip_feature
+{
+	uint64_t u64;
+	struct cvmx_sriox_ip_feature_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t ops                          : 32; /**< Reset Value for the OPs fields in both the
+                                                         SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS
+                                                         registers. */
+	uint64_t reserved_14_31               : 18;
+	uint64_t a66                          : 1;  /**< 66-bit Address Support.  Value for bit 2 of the
+                                                         EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */
+	uint64_t a50                          : 1;  /**< 50-bit Address Support.  Value for bit 1 of the
+                                                         EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */
+	uint64_t reserved_11_11               : 1;
+	uint64_t tx_flow                      : 1;  /**< Reset Value for the TX_FLOW field in the
+                                                         SRIOMAINT(0..1)_IR_BUFFER_CONFIG register. */
+	uint64_t pt_width                     : 2;  /**< Value for the PT_WIDTH field in the
+                                                         SRIOMAINT(0..1)_PORT_0_CTL register. */
+	uint64_t tx_pol                       : 4;  /**< TX Serdes Polarity Lanes 3-0
+                                                         0 = Normal Operation
+                                                         1 = Invert, Swap +/- Tx SERDES Pins */
+	uint64_t rx_pol                       : 4;  /**< RX Serdes Polarity Lanes 3-0
+                                                         0 = Normal Operation
+                                                         1 = Invert, Swap +/- Rx SERDES Pins */
+#else
+	uint64_t rx_pol                       : 4;
+	uint64_t tx_pol                       : 4;
+	uint64_t pt_width                     : 2;
+	uint64_t tx_flow                      : 1;
+	uint64_t reserved_11_11               : 1;
+	uint64_t a50                          : 1;
+	uint64_t a66                          : 1;
+	uint64_t reserved_14_31               : 18;
+	uint64_t ops                          : 32;
+#endif
+	} s;
+	struct cvmx_sriox_ip_feature_s        cn63xx;
+	struct cvmx_sriox_ip_feature_s        cn63xxp1;
+};
+typedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t;
+
+/**
+ * cvmx_srio#_mac_buffers
+ *
+ * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control (Pass 2)
+ *
+ * Reports errors and controls buffer usage on the main MAC buffers
+ *
+ * Notes:
+ * Register displays errors status for each of the eight RX and TX buffers and controls use of the
+ *  buffer in future operations.  It also displays the number of RX and TX buffers currently used by
+ *  the MAC.
+ *
+ * Clk_Rst:        SRIO(0..1)_MAC_BUFFERS  hclk    hrst_n
+ */
+union cvmx_sriox_mac_buffers
+{
+	uint64_t u64;
+	struct cvmx_sriox_mac_buffers_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_56_63               : 8;
+	uint64_t tx_enb                       : 8;  /**< TX Buffer Enable.  Each bit enables a specific TX
+                                                         Buffer.  At least 2 of these bits must be set for
+                                                         proper operation.  These bits must be cleared to
+                                                         and then set again to reuese the buffer after an
+                                                         error occurs. */
+	uint64_t reserved_44_47               : 4;
+	uint64_t tx_inuse                     : 4;  /**< Number of TX buffers containing packets waiting
+                                                         to be transmitted or to be acknowledged. */
+	uint64_t tx_stat                      : 8;  /**< Errors detected in main SRIO Transmit Buffers.
+                                                         CRC error detected in buffer sets bit of buffer \#
+                                                         until the corresponding TX_ENB is disabled.  Each
+                                                         bit set causes the SRIO(0..1)_INT_REG.MAC_BUF
+                                                         interrupt. */
+	uint64_t reserved_24_31               : 8;
+	uint64_t rx_enb                       : 8;  /**< RX Buffer Enable.  Each bit enables a specific RX
+                                                         Buffer.  At least 2 of these bits must be set for
+                                                         proper operation.  These bits must be cleared to
+                                                         and then set again to reuese the buffer after an
+                                                         error occurs. */
+	uint64_t reserved_12_15               : 4;
+	uint64_t rx_inuse                     : 4;  /**< Number of RX buffers containing valid packets
+                                                         waiting to be processed by the logical layer. */
+	uint64_t rx_stat                      : 8;  /**< Errors detected in main SRIO Receive Buffers.  CRC
+                                                         error detected in buffer sets bit of buffer \#
+                                                         until the corresponding RX_ENB is disabled.  Each
+                                                         bit set causes the SRIO(0..1)_INT_REG.MAC_BUF
+                                                         interrupt. */
+#else
+	uint64_t rx_stat                      : 8;
+	uint64_t rx_inuse                     : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t rx_enb                       : 8;
+	uint64_t reserved_24_31               : 8;
+	uint64_t tx_stat                      : 8;
+	uint64_t tx_inuse                     : 4;
+	uint64_t reserved_44_47               : 4;
+	uint64_t tx_enb                       : 8;
+	uint64_t reserved_56_63               : 8;
+#endif
+	} s;
+	struct cvmx_sriox_mac_buffers_s       cn63xx;
+};
+typedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t;
+
+/**
+ * cvmx_srio#_maint_op
+ *
+ * SRIO_MAINT_OP = SRIO Maintenance Operation
+ *
+ * Allows access to maintenance registers.
+ *
+ * Notes:
+ * This register allows write access to the local SRIOMAINT registers.  A write to this register
+ *  posts a read or write operation selected by the OP bit to the local SRIOMAINT register selected by
+ *  ADDR.  This write also sets the PENDING bit.  The PENDING bit is cleared by hardware when the
+ *  operation is complete.  The MAINT_OP Interrupt is also set as the PENDING bit is cleared.  While
+ *  this bit is set, additional writes to this register stall the RSL.  The FAIL bit is set with the
+ *  clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write
+ *  operations.  Only 32-bit Maintenance Operations are supported.
+ *
+ * Clk_Rst:        SRIO(0..1)_MAINT_OP     hclk    hrst_n
+ */
+union cvmx_sriox_maint_op
+{
+	uint64_t u64;
+	struct cvmx_sriox_maint_op_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t wr_data                      : 32; /**< Write Data[31:0]. */
+	uint64_t reserved_27_31               : 5;
+	uint64_t fail                         : 1;  /**< Maintenance Operation Address Error */
+	uint64_t pending                      : 1;  /**< Maintenance Operation Pending */
+	uint64_t op                           : 1;  /**< Operation. 0=Read, 1=Write */
+	uint64_t addr                         : 24; /**< Address. Addr[1:0] are ignored. */
+#else
+	uint64_t addr                         : 24;
+	uint64_t op                           : 1;
+	uint64_t pending                      : 1;
+	uint64_t fail                         : 1;
+	uint64_t reserved_27_31               : 5;
+	uint64_t wr_data                      : 32;
+#endif
+	} s;
+	struct cvmx_sriox_maint_op_s          cn63xx;
+	struct cvmx_sriox_maint_op_s          cn63xxp1;
+};
+typedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t;
+
+/**
+ * cvmx_srio#_maint_rd_data
+ *
+ * SRIO_MAINT_RD_DATA = SRIO Maintenance Read Data
+ *
+ * Allows read access of maintenance registers.
+ *
+ * Notes:
+ * This register allows read access of the local SRIOMAINT registers.  A write to the SRIO(0..1)_MAINT_OP
+ *  register with the OP bit set to zero initiates a read request and clears the VALID bit.  The
+ *  resulting read is returned here and the VALID bit is set.  Access to the register will not stall
+ *  the RSL but the VALID bit should be read.
+ *
+ * Clk_Rst:        SRIO(0..1)_MAINT_RD_DATA        hclk    hrst_n
+ */
+union cvmx_sriox_maint_rd_data
+{
+	uint64_t u64;
+	struct cvmx_sriox_maint_rd_data_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_33_63               : 31;
+	uint64_t valid                        : 1;  /**< Read Data Valid. */
+	uint64_t rd_data                      : 32; /**< Read Data[31:0]. */
+#else
+	uint64_t rd_data                      : 32;
+	uint64_t valid                        : 1;
+	uint64_t reserved_33_63               : 31;
+#endif
+	} s;
+	struct cvmx_sriox_maint_rd_data_s     cn63xx;
+	struct cvmx_sriox_maint_rd_data_s     cn63xxp1;
+};
+typedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t;
+
+/**
+ * cvmx_srio#_mce_tx_ctl
+ *
+ * SRIO_MCE_TX_CTL = SRIO Multicast Event Transmit Control
+ *
+ * Multicast Event TX Control
+ *
+ * Notes:
+ * Writes to this register cause the SRIO device to generate a Multicast Event.  Setting the MCE bit
+ *  requests the logic to generate the Multicast Event Symbol.  Reading the MCS bit shows the status
+ *  of the transmit event.  The hardware will clear the bit when the event has been transmitted and
+ *  set the MCS_TX Interrupt.
+ *
+ * Clk_Rst:        SRIO(0..1)_MCE_TX_CTL   hclk    hrst_n
+ */
+union cvmx_sriox_mce_tx_ctl
+{
+	uint64_t u64;
+	struct cvmx_sriox_mce_tx_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t mce                          : 1;  /**< Multicast Event Transmit. */
+#else
+	uint64_t mce                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_sriox_mce_tx_ctl_s        cn63xx;
+	struct cvmx_sriox_mce_tx_ctl_s        cn63xxp1;
+};
+typedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t;
+
+/**
+ * cvmx_srio#_mem_op_ctrl
+ *
+ * SRIO_MEM_OP_CTRL = SRIO Memory Operation Control
+ *
+ * The SRIO Memory Operation Control
+ *
+ * Notes:
+ * This register is used to control memory operations.  Bits are provided to override the priority of
+ *  the outgoing responses to memory operations.  The memory operations with responses include NREAD,
+ *  NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR.
+ *
+ * Clk_Rst:        SRIO(0..1)_MEM_OP_CTRL  hclk    hrst_n
+ */
+union cvmx_sriox_mem_op_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_mem_op_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t rr_ro                        : 1;  /**< Read Response Relaxed Ordering.  Controls ordering
+                                                         rules for incoming memory operations
+                                                          0 = Normal Ordering
+                                                          1 = Relaxed Ordering */
+	uint64_t w_ro                         : 1;  /**< Write Relaxed Ordering.  Controls ordering rules
+                                                         for incoming memory operations
+                                                          0 = Normal Ordering
+                                                          1 = Relaxed Ordering */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rp1_sid                      : 1;  /**< Sets response priority for incomimg memory ops
+                                                         of priority 1 on the secondary ID (0=2, 1=3) */
+	uint64_t rp0_sid                      : 2;  /**< Sets response priority for incomimg memory ops
+                                                         of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
+	uint64_t rp1_pid                      : 1;  /**< Sets response priority for incomimg memory ops
+                                                         of priority 1 on the primary ID (0=2, 1=3) */
+	uint64_t rp0_pid                      : 2;  /**< Sets response priority for incomimg memory ops
+                                                         of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
+#else
+	uint64_t rp0_pid                      : 2;
+	uint64_t rp1_pid                      : 1;
+	uint64_t rp0_sid                      : 2;
+	uint64_t rp1_sid                      : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t w_ro                         : 1;
+	uint64_t rr_ro                        : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_sriox_mem_op_ctrl_s       cn63xx;
+	struct cvmx_sriox_mem_op_ctrl_s       cn63xxp1;
+};
+typedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t;
+
+/**
+ * cvmx_srio#_omsg_ctrl#
+ *
+ * SRIO_OMSG_CTRLX = SRIO Outbound Message Control
+ *
+ * The SRIO Controller X Outbound Message Control Register
+ *
+ * Notes:
+ * 1) If IDM_TT, IDM_SIS, and IDM_DID are all clear, then the "ID match" will always be false.
+ * 2) LTTR_SP and LTTR_MP must be non-zero at all times, otherwise the message output queue can
+ *        get blocked
+ * 3) TESTMODE has no function on controller 1
+ * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO
+ *        zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_CTRL[0:1]       hclk    hrst_n
+ */
+union cvmx_sriox_omsg_ctrlx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_ctrlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t testmode                     : 1;  /**< Controller X test mode (keep as RSVD in HRM) */
+	uint64_t reserved_37_62               : 26;
+	uint64_t silo_max                     : 5;  /**< Sets max number outgoing segments for controller X
+                                                         (Pass 2) */
+	uint64_t rtry_thr                     : 16; /**< Controller X Retry threshold */
+	uint64_t rtry_en                      : 1;  /**< Controller X Retry threshold enable */
+	uint64_t reserved_11_14               : 4;
+	uint64_t idm_tt                       : 1;  /**< Controller X ID match includes TT ID */
+	uint64_t idm_sis                      : 1;  /**< Controller X ID match includes SIS */
+	uint64_t idm_did                      : 1;  /**< Controller X ID match includes DID */
+	uint64_t lttr_sp                      : 4;  /**< Controller X SP allowable letters in dynamic
+                                                         letter select mode (LNS) */
+	uint64_t lttr_mp                      : 4;  /**< Controller X MP allowable letters in dynamic
+                                                         letter select mode (LNS) */
+#else
+	uint64_t lttr_mp                      : 4;
+	uint64_t lttr_sp                      : 4;
+	uint64_t idm_did                      : 1;
+	uint64_t idm_sis                      : 1;
+	uint64_t idm_tt                       : 1;
+	uint64_t reserved_11_14               : 4;
+	uint64_t rtry_en                      : 1;
+	uint64_t rtry_thr                     : 16;
+	uint64_t silo_max                     : 5;
+	uint64_t reserved_37_62               : 26;
+	uint64_t testmode                     : 1;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_ctrlx_s        cn63xx;
+	struct cvmx_sriox_omsg_ctrlx_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t testmode                     : 1;  /**< Controller X test mode (keep as RSVD in HRM) */
+	uint64_t reserved_32_62               : 31;
+	uint64_t rtry_thr                     : 16; /**< Controller X Retry threshold */
+	uint64_t rtry_en                      : 1;  /**< Controller X Retry threshold enable */
+	uint64_t reserved_11_14               : 4;
+	uint64_t idm_tt                       : 1;  /**< Controller X ID match includes TT ID */
+	uint64_t idm_sis                      : 1;  /**< Controller X ID match includes SIS */
+	uint64_t idm_did                      : 1;  /**< Controller X ID match includes DID */
+	uint64_t lttr_sp                      : 4;  /**< Controller X SP allowable letters in dynamic
+                                                         letter select mode (LNS) */
+	uint64_t lttr_mp                      : 4;  /**< Controller X MP allowable letters in dynamic
+                                                         letter select mode (LNS) */
+#else
+	uint64_t lttr_mp                      : 4;
+	uint64_t lttr_sp                      : 4;
+	uint64_t idm_did                      : 1;
+	uint64_t idm_sis                      : 1;
+	uint64_t idm_tt                       : 1;
+	uint64_t reserved_11_14               : 4;
+	uint64_t rtry_en                      : 1;
+	uint64_t rtry_thr                     : 16;
+	uint64_t reserved_32_62               : 31;
+	uint64_t testmode                     : 1;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t;
+
+/**
+ * cvmx_srio#_omsg_done_counts#
+ *
+ * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts (Pass 2)
+ *
+ * The SRIO Controller X Outbound Message Complete Counts Register
+ *
+ * Notes:
+ * This register shows the number of successful and unsuccessful Outgoing Messages issued through
+ *  this controller.  The only messages considered are the ones with the INT field set in the PKO
+ *  message header.  This register is typically not written while Outbound SRIO Memory traffic is
+ *  enabled.  The sum of the GOOD and BAD counts should equal the number of messages sent unless
+ *  the MAC has been reset.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_DONE_COUNTS[0:1]        hclk    hrst_n
+ */
+union cvmx_sriox_omsg_done_countsx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_done_countsx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bad                          : 16; /**< Number of Outbound Messages requesting an INT that
+                                                         did not increment GOOD. (One or more segment of the
+                                                         message either timed out, reached the retry limit,
+                                                         or received an ERROR response.) */
+	uint64_t good                         : 16; /**< Number of Outbound Messages requesting an INT that
+                                                         received a DONE response for every segment. */
+#else
+	uint64_t good                         : 16;
+	uint64_t bad                          : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_done_countsx_s cn63xx;
+};
+typedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t;
+
+/**
+ * cvmx_srio#_omsg_fmp_mr#
+ *
+ * SRIO_OMSG_FMP_MRX = SRIO Outbound Message FIRSTMP Message Restriction
+ *
+ * The SRIO Controller X Outbound Message FIRSTMP Message Restriction Register
+ *
+ * Notes:
+ * This CSR controls when FMP candidate message segments (from the two different controllers) can enter
+ * the message segment silo to be sent out. A segment remains in the silo until after is has
+ * been transmitted and either acknowledged or errored out.
+ *
+ * Candidates and silo entries are one of 4 types:
+ *  SP  - a single-segment message
+ *  FMP - the first segment of a multi-segment message
+ *  NMP - the other segments in a multi-segment message
+ *  PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
+ *        a multi-segment message into the silo and can match against segments generated by
+ *        the other controller
+ *
+ * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
+ * By default (i.e. zeroes in this CSR), the FMP candidate matches against all entries in the
+ * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and
+ * can enter the silo more freely, probably providing better performance.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_FMP_MR[0:1]     hclk    hrst_n
+ */
+union cvmx_sriox_omsg_fmp_mrx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_fmp_mrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t ctlr_sp                      : 1;  /**< Controller X FIRSTMP enable controller SP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed SP segments that were created
+                                                         by the same controller. When clear, this FMP-SP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t ctlr_fmp                     : 1;  /**< Controller X FIRSTMP enable controller FIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed FMP segments that were created
+                                                         by the same controller. When clear, this FMP-FMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t ctlr_nmp                     : 1;  /**< Controller X FIRSTMP enable controller NFIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed NMP segments that were created
+                                                         by the same controller. When clear, this FMP-NMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t id_sp                        : 1;  /**< Controller X FIRSTMP enable ID SP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed SP segments that "ID match" the
+                                                         candidate. When clear, this FMP-SP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t id_fmp                       : 1;  /**< Controller X FIRSTMP enable ID FIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed FMP segments that "ID match" the
+                                                         candidate. When clear, this FMP-FMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t id_nmp                       : 1;  /**< Controller X FIRSTMP enable ID NFIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed NMP segments that "ID match" the
+                                                         candidate. When clear, this FMP-NMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t id_psd                       : 1;  /**< Controller X FIRSTMP enable ID PSEUDO
+                                                         When set, the FMP candidate message segment can
+                                                         only match the silo pseudo (for the other
+                                                         controller) when it is an "ID match". When clear,
+                                                         this FMP-PSD match can occur with any ID values.
+                                                         Not used by the hardware when ALL_PSD is set. */
+	uint64_t mbox_sp                      : 1;  /**< Controller X FIRSTMP enable MBOX SP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed SP segments with the same 2-bit
+                                                         mbox value as the candidate. When clear, this
+                                                         FMP-SP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t mbox_fmp                     : 1;  /**< Controller X FIRSTMP enable MBOX FIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed FMP segments with the same 2-bit
+                                                         mbox value as the candidate. When clear, this
+                                                         FMP-FMP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t mbox_nmp                     : 1;  /**< Controller X FIRSTMP enable MBOX NFIRSTMP
+                                                         When set, the FMP candidate message segment can
+                                                         only match siloed NMP segments with the same 2-bit
+                                                         mbox value as the candidate. When clear, this
+                                                         FMP-NMP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t mbox_psd                     : 1;  /**< Controller X FIRSTMP enable MBOX PSEUDO
+                                                         When set, the FMP candidate message segment can
+                                                         only match the silo pseudo (for the other
+                                                         controller) if the pseudo has the same 2-bit mbox
+                                                         value as the candidate. When clear, this FMP-PSD
+                                                         match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_PSD is set. */
+	uint64_t all_sp                       : 1;  /**< Controller X FIRSTMP enable all SP
+                                                         When set, no FMP candidate message segments ever
+                                                         match siloed SP segments and ID_SP
+                                                         and MBOX_SP are not used. When clear, FMP-SP
+                                                         matches can occur. */
+	uint64_t all_fmp                      : 1;  /**< Controller X FIRSTMP enable all FIRSTMP
+                                                         When set, no FMP candidate message segments ever
+                                                         match siloed FMP segments and ID_FMP and MBOX_FMP
+                                                         are not used. When clear, FMP-FMP matches can
+                                                         occur. */
+	uint64_t all_nmp                      : 1;  /**< Controller X FIRSTMP enable all NFIRSTMP
+                                                         When set, no FMP candidate message segments ever
+                                                         match siloed NMP segments and ID_NMP and MBOX_NMP
+                                                         are not used. When clear, FMP-NMP matches can
+                                                         occur. */
+	uint64_t all_psd                      : 1;  /**< Controller X FIRSTMP enable all PSEUDO
+                                                         When set, no FMP candidate message segments ever
+                                                         match the silo pseudo (for the other controller)
+                                                         and ID_PSD and MBOX_PSD are not used. When clear,
+                                                         FMP-PSD matches can occur. */
+#else
+	uint64_t all_psd                      : 1;
+	uint64_t all_nmp                      : 1;
+	uint64_t all_fmp                      : 1;
+	uint64_t all_sp                       : 1;
+	uint64_t mbox_psd                     : 1;
+	uint64_t mbox_nmp                     : 1;
+	uint64_t mbox_fmp                     : 1;
+	uint64_t mbox_sp                      : 1;
+	uint64_t id_psd                       : 1;
+	uint64_t id_nmp                       : 1;
+	uint64_t id_fmp                       : 1;
+	uint64_t id_sp                        : 1;
+	uint64_t ctlr_nmp                     : 1;
+	uint64_t ctlr_fmp                     : 1;
+	uint64_t ctlr_sp                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_fmp_mrx_s      cn63xx;
+	struct cvmx_sriox_omsg_fmp_mrx_s      cn63xxp1;
+};
+typedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t;
+
+/**
+ * cvmx_srio#_omsg_nmp_mr#
+ *
+ * SRIO_OMSG_NMP_MRX = SRIO Outbound Message NFIRSTMP Message Restriction
+ *
+ * The SRIO Controller X Outbound Message NFIRSTMP Message Restriction Register
+ *
+ * Notes:
+ * This CSR controls when NMP candidate message segments (from the two different controllers) can enter
+ * the message segment silo to be sent out. A segment remains in the silo until after is has
+ * been transmitted and either acknowledged or errored out.
+ *
+ * Candidates and silo entries are one of 4 types:
+ *  SP  - a single-segment message
+ *  FMP - the first segment of a multi-segment message
+ *  NMP - the other segments in a multi-segment message
+ *  PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
+ *        a multi-segment message into the silo and can match against segments generated by
+ *        the other controller
+ *
+ * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
+ * By default (i.e. zeroes in this CSR), the NMP candidate matches against all entries in the
+ * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and
+ * can enter the silo more freely, probably providing better performance.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_NMP_MR[0:1]     hclk    hrst_n
+ */
+union cvmx_sriox_omsg_nmp_mrx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_nmp_mrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t ctlr_sp                      : 1;  /**< Controller X NFIRSTMP enable controller SP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed SP segments that were created
+                                                         by the same controller. When clear, this NMP-SP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t ctlr_fmp                     : 1;  /**< Controller X NFIRSTMP enable controller FIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed FMP segments that were created
+                                                         by the same controller. When clear, this NMP-FMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t ctlr_nmp                     : 1;  /**< Controller X NFIRSTMP enable controller NFIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed NMP segments that were created
+                                                         by the same controller. When clear, this NMP-NMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t id_sp                        : 1;  /**< Controller X NFIRSTMP enable ID SP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed SP segments that "ID match" the
+                                                         candidate. When clear, this NMP-SP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t id_fmp                       : 1;  /**< Controller X NFIRSTMP enable ID FIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed FMP segments that "ID match" the
+                                                         candidate. When clear, this NMP-FMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t id_nmp                       : 1;  /**< Controller X NFIRSTMP enable ID NFIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed NMP segments that "ID match" the
+                                                         candidate. When clear, this NMP-NMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t mbox_sp                      : 1;  /**< Controller X NFIRSTMP enable MBOX SP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed SP segments with the same 2-bit
+                                                         mbox  value as the candidate. When clear, this
+                                                         NMP-SP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t mbox_fmp                     : 1;  /**< Controller X NFIRSTMP enable MBOX FIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed FMP segments with the same 2-bit
+                                                         mbox value as the candidate. When clear, this
+                                                         NMP-FMP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t mbox_nmp                     : 1;  /**< Controller X NFIRSTMP enable MBOX NFIRSTMP
+                                                         When set, the NMP candidate message segment can
+                                                         only match siloed NMP segments with the same 2-bit
+                                                         mbox value as the candidate. When clear, this
+                                                         NMP-NMP match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t reserved_4_4                 : 1;
+	uint64_t all_sp                       : 1;  /**< Controller X NFIRSTMP enable all SP
+                                                         When set, no NMP candidate message segments ever
+                                                         match siloed SP segments and ID_SP
+                                                         and MBOX_SP are not used. When clear, NMP-SP
+                                                         matches can occur. */
+	uint64_t all_fmp                      : 1;  /**< Controller X NFIRSTMP enable all FIRSTMP
+                                                         When set, no NMP candidate message segments ever
+                                                         match siloed FMP segments and ID_FMP and MBOX_FMP
+                                                         are not used. When clear, NMP-FMP matches can
+                                                         occur. */
+	uint64_t all_nmp                      : 1;  /**< Controller X NFIRSTMP enable all NFIRSTMP
+                                                         When set, no NMP candidate message segments ever
+                                                         match siloed NMP segments and ID_NMP and MBOX_NMP
+                                                         are not used. When clear, NMP-NMP matches can
+                                                         occur. */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t all_nmp                      : 1;
+	uint64_t all_fmp                      : 1;
+	uint64_t all_sp                       : 1;
+	uint64_t reserved_4_4                 : 1;
+	uint64_t mbox_nmp                     : 1;
+	uint64_t mbox_fmp                     : 1;
+	uint64_t mbox_sp                      : 1;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t id_nmp                       : 1;
+	uint64_t id_fmp                       : 1;
+	uint64_t id_sp                        : 1;
+	uint64_t ctlr_nmp                     : 1;
+	uint64_t ctlr_fmp                     : 1;
+	uint64_t ctlr_sp                      : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_nmp_mrx_s      cn63xx;
+	struct cvmx_sriox_omsg_nmp_mrx_s      cn63xxp1;
+};
+typedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t;
+
+/**
+ * cvmx_srio#_omsg_port#
+ *
+ * SRIO_OMSG_PORTX = SRIO Outbound Message Port
+ *
+ * The SRIO Controller X Outbound Message Port Register
+ *
+ * Notes:
+ * PORT maps the PKO port to SRIO interface \# / controller X as follows:
+ *
+ *    00 == PKO port 40
+ *    01 == PKO port 41
+ *    10 == PKO port 42
+ *    11 == PKO port 43
+ *
+ *  No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value.
+ *  The register is only reset during COLD boot.  The register can be accessed/modified regardless of
+ *  the value in SRIO(0..1)_STATUS_REG.ACCESS.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_PORT[0:1]       sclk    srst_n
+ */
+union cvmx_sriox_omsg_portx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_portx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t enable                       : 1;  /**< Controller X enable */
+	uint64_t reserved_2_30                : 29;
+	uint64_t port                         : 2;  /**< Controller X PKO port */
+#else
+	uint64_t port                         : 2;
+	uint64_t reserved_2_30                : 29;
+	uint64_t enable                       : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_portx_s        cn63xx;
+	struct cvmx_sriox_omsg_portx_s        cn63xxp1;
+};
+typedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t;
+
+/**
+ * cvmx_srio#_omsg_silo_thr
+ *
+ * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds (Pass 2)
+ *
+ * The SRIO Outgoing Message SILO Thresholds
+ *
+ * Notes:
+ * Limits the number of Outgoing Message Segments in flight at a time.  This register is reserved in
+ *  pass 1 and the threshold is set to 16.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_SILO_THR        hclk    hrst_n
+ */
+union cvmx_sriox_omsg_silo_thr
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_silo_thr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t tot_silo                     : 5;  /**< Sets max number segments in flight for all
+                                                         controllers. */
+#else
+	uint64_t tot_silo                     : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_silo_thr_s     cn63xx;
+};
+typedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t;
+
+/**
+ * cvmx_srio#_omsg_sp_mr#
+ *
+ * SRIO_OMSG_SP_MRX = SRIO Outbound Message SP Message Restriction
+ *
+ * The SRIO Controller X Outbound Message SP Message Restriction Register
+ *
+ * Notes:
+ * This CSR controls when SP candidate message segments (from the two different controllers) can enter
+ * the message segment silo to be sent out. A segment remains in the silo until after is has
+ * been transmitted and either acknowledged or errored out.
+ *
+ * Candidates and silo entries are one of 4 types:
+ *  SP  - a single-segment message
+ *  FMP - the first segment of a multi-segment message
+ *  NMP - the other segments in a multi-segment message
+ *  PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
+ *        a multi-segment message into the silo and can match against segments generated by
+ *        the other controller
+ *
+ * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
+ * By default (i.e. zeroes in this CSR), the SP candidate matches against all entries in the
+ * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and
+ * can enter the silo more freely, probably providing better performance.
+ *
+ * Clk_Rst:        SRIO(0..1)_OMSG_SP_MR[0:1]      hclk    hrst_n
+ */
+union cvmx_sriox_omsg_sp_mrx
+{
+	uint64_t u64;
+	struct cvmx_sriox_omsg_sp_mrx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t xmbox_sp                     : 1;  /**< Controller X SP enable XMBOX SP
+                                                         When set, the SP candidate message can only
+                                                         match siloed SP segments with the same 4-bit xmbox
+                                                         value as the candidate. When clear, this SP-SP
+                                                         match can occur with any xmbox values.
+                                                         When XMBOX_SP is set, MBOX_SP will commonly be set.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t ctlr_sp                      : 1;  /**< Controller X SP enable controller SP
+                                                         When set, the SP candidate message can
+                                                         only match siloed SP segments that were created
+                                                         by the same controller. When clear, this SP-SP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t ctlr_fmp                     : 1;  /**< Controller X SP enable controller FIRSTMP
+                                                         When set, the SP candidate message can
+                                                         only match siloed FMP segments that were created
+                                                         by the same controller. When clear, this SP-FMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t ctlr_nmp                     : 1;  /**< Controller X SP enable controller NFIRSTMP
+                                                         When set, the SP candidate message can
+                                                         only match siloed NMP segments that were created
+                                                         by the same controller. When clear, this SP-NMP
+                                                         match can also occur when the segments were
+                                                         created by the other controller.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t id_sp                        : 1;  /**< Controller X SP enable ID SP
+                                                         When set, the SP candidate message can
+                                                         only match siloed SP segments that "ID match" the
+                                                         candidate. When clear, this SP-SP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t id_fmp                       : 1;  /**< Controller X SP enable ID FIRSTMP
+                                                         When set, the SP candidate message can
+                                                         only match siloed FMP segments that "ID match" the
+                                                         candidate. When clear, this SP-FMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t id_nmp                       : 1;  /**< Controller X SP enable ID NFIRSTMP
+                                                         When set, the SP candidate message can
+                                                         only match siloed NMP segments that "ID match" the
+                                                         candidate. When clear, this SP-NMP match can occur
+                                                         with any ID values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t id_psd                       : 1;  /**< Controller X SP enable ID PSEUDO
+                                                         When set, the SP candidate message can
+                                                         only match the silo pseudo (for the other
+                                                         controller) when it is an "ID match". When clear,
+                                                         this SP-PSD match can occur with any ID values.
+                                                         Not used by the hardware when ALL_PSD is set. */
+	uint64_t mbox_sp                      : 1;  /**< Controller X SP enable MBOX SP
+                                                         When set, the SP candidate message can only
+                                                         match siloed SP segments with the same 2-bit mbox
+                                                         value as the candidate. When clear, this SP-SP
+                                                         match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_SP is set. */
+	uint64_t mbox_fmp                     : 1;  /**< Controller X SP enable MBOX FIRSTMP
+                                                         When set, the SP candidate message can only
+                                                         match siloed FMP segments with the same 2-bit mbox
+                                                         value as the candidate. When clear, this SP-FMP
+                                                         match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_FMP is set. */
+	uint64_t mbox_nmp                     : 1;  /**< Controller X SP enable MBOX NFIRSTMP
+                                                         When set, the SP candidate message can only
+                                                         match siloed NMP segments with the same 2-bit mbox
+                                                         value as the candidate. When clear, this SP-NMP
+                                                         match can occur with any mbox values.
+                                                         Not used by the hardware when ALL_NMP is set. */
+	uint64_t mbox_psd                     : 1;  /**< Controller X SP enable MBOX PSEUDO
+                                                         When set, the SP candidate message can only
+                                                         match the silo pseudo (for the other controller)
+                                                         if the pseudo has the same 2-bit mbox value as the
+                                                         candidate. When clear, this SP-PSD match can occur
+                                                         with any mbox values.
+                                                         Not used by the hardware when ALL_PSD is set. */
+	uint64_t all_sp                       : 1;  /**< Controller X SP enable all SP
+                                                         When set, no SP candidate messages ever
+                                                         match siloed SP segments, and XMBOX_SP, ID_SP,
+                                                         and MBOX_SP are not used. When clear, SP-SP
+                                                         matches can occur. */
+	uint64_t all_fmp                      : 1;  /**< Controller X SP enable all FIRSTMP
+                                                         When set, no SP candidate messages ever
+                                                         match siloed FMP segments and ID_FMP and MBOX_FMP
+                                                         are not used. When clear, SP-FMP matches can
+                                                         occur. */
+	uint64_t all_nmp                      : 1;  /**< Controller X SP enable all NFIRSTMP
+                                                         When set, no SP candidate messages ever
+                                                         match siloed NMP segments and ID_NMP and MBOX_NMP
+                                                         are not used. When clear, SP-NMP matches can
+                                                         occur. */
+	uint64_t all_psd                      : 1;  /**< Controller X SP enable all PSEUDO
+                                                         When set, no SP candidate messages ever
+                                                         match the silo pseudo (for the other controller)
+                                                         and ID_PSD and MBOX_PSD are not used. When clear,
+                                                         SP-PSD matches can occur. */
+#else
+	uint64_t all_psd                      : 1;
+	uint64_t all_nmp                      : 1;
+	uint64_t all_fmp                      : 1;
+	uint64_t all_sp                       : 1;
+	uint64_t mbox_psd                     : 1;
+	uint64_t mbox_nmp                     : 1;
+	uint64_t mbox_fmp                     : 1;
+	uint64_t mbox_sp                      : 1;
+	uint64_t id_psd                       : 1;
+	uint64_t id_nmp                       : 1;
+	uint64_t id_fmp                       : 1;
+	uint64_t id_sp                        : 1;
+	uint64_t ctlr_nmp                     : 1;
+	uint64_t ctlr_fmp                     : 1;
+	uint64_t ctlr_sp                      : 1;
+	uint64_t xmbox_sp                     : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_sriox_omsg_sp_mrx_s       cn63xx;
+	struct cvmx_sriox_omsg_sp_mrx_s       cn63xxp1;
+};
+typedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t;
+
+/**
+ * cvmx_srio#_prio#_in_use
+ *
+ * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS (Pass 2)
+ *
+ * SRIO S2M Priority X FIFO Inuse counts
+ *
+ * Notes:
+ * These registers provide status information on the number of read/write requests pending in the S2M
+ *  Priority FIFOs.  The information can be used to help determine when an S2M_TYPE register can be
+ *  reallocated.  For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has
+ *  completed.  The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine
+ *  the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least
+ *  START_CNT+N.   These registers can be accessed regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS
+ *  but are reset by either the MAC or Core being reset.
+ *
+ * Clk_Rst:        SRIO(0..1)_PRIO[0:3]_IN_USE     sclk    srst_n, hrst_n
+ */
+union cvmx_sriox_priox_in_use
+{
+	uint64_t u64;
+	struct cvmx_sriox_priox_in_use_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t end_cnt                      : 16; /**< Count of Packets with S2M_TYPES completed for this
+                                                         Priority X FIFO */
+	uint64_t start_cnt                    : 16; /**< Count of Packets with S2M_TYPES started for this
+                                                         Priority X FIFO */
+#else
+	uint64_t start_cnt                    : 16;
+	uint64_t end_cnt                      : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_priox_in_use_s      cn63xx;
+};
+typedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t;
+
+/**
+ * cvmx_srio#_rx_bell
+ *
+ * SRIO_RX_BELL = SRIO Receive Doorbell
+ *
+ * The SRIO Incoming (RX) Doorbell
+ *
+ * Notes:
+ * This register contains the SRIO Information, Device ID, Transaction Type and Priority of the
+ *  incoming Doorbell Transaction as well as the number of transactions waiting to be read.  Reading
+ *  this register causes a Doorbell to be removed from the RX Bell FIFO and the COUNT to be
+ *  decremented.  If the COUNT is zero then the FIFO is empty and the other fields should be
+ *  considered invalid.  When the FIFO is full an ERROR is automatically issued.  The RXBELL Interrupt
+ *  can be used to detect posts to this FIFO.
+ *
+ * Clk_Rst:        SRIO(0..1)_RX_BELL      hclk    hrst_n
+ */
+union cvmx_sriox_rx_bell
+{
+	uint64_t u64;
+	struct cvmx_sriox_rx_bell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t data                         : 16; /**< Information field from received doorbell */
+	uint64_t src_id                       : 16; /**< Doorbell Source Device ID[15:0] */
+	uint64_t count                        : 8;  /**< RX Bell FIFO Count
+                                                         Note:  Count must be > 0 for entry to be valid. */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t dest_id                      : 1;  /**< Destination Device ID 0=Primary, 1=Secondary */
+	uint64_t id16                         : 1;  /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t priority                     : 2;  /**< Doorbell Priority */
+#else
+	uint64_t priority                     : 2;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t id16                         : 1;
+	uint64_t dest_id                      : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t count                        : 8;
+	uint64_t src_id                       : 16;
+	uint64_t data                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_sriox_rx_bell_s           cn63xx;
+	struct cvmx_sriox_rx_bell_s           cn63xxp1;
+};
+typedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t;
+
+/**
+ * cvmx_srio#_rx_bell_seq
+ *
+ * SRIO_RX_BELL_SEQ = SRIO Receive Doorbell Sequence Count
+ *
+ * The SRIO Incoming (RX) Doorbell Sequence Count
+ *
+ * Notes:
+ * This register contains the value of the sequence counter when the doorbell was received and a
+ *  shadow copy of the Bell FIFO Count that can be read without emptying the FIFO.  This register must
+ *  be read prior to SRIO(0..1)_RX_BELL to guarantee that the information corresponds to the correct
+ *  doorbell.
+ *
+ * Clk_Rst:        SRIO(0..1)_RX_BELL_SEQ  hclk    hrst_n
+ */
+union cvmx_sriox_rx_bell_seq
+{
+	uint64_t u64;
+	struct cvmx_sriox_rx_bell_seq_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t count                        : 8;  /**< RX Bell FIFO Count
+                                                         Note:  Count must be > 0 for entry to be valid. */
+	uint64_t seq                          : 32; /**< 32-bit Sequence \# associated with Doorbell Message */
+#else
+	uint64_t seq                          : 32;
+	uint64_t count                        : 8;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_sriox_rx_bell_seq_s       cn63xx;
+	struct cvmx_sriox_rx_bell_seq_s       cn63xxp1;
+};
+typedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t;
+
+/**
+ * cvmx_srio#_rx_status
+ *
+ * SRIO_RX_STATUS = SRIO Inbound Credits/Response Status
+ *
+ * Specifies the current number of credits/responses by SRIO for Inbound Traffic
+ *
+ * Notes:
+ * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic.
+ *  The maximum value for COMP, N_POST and POST is set in SRIO(0..1)_TLP_CREDITS.  When all inbound traffic
+ *  has stopped the values should eventually return to the maximum values.  The RTN_PR[3:1] entry
+ *  counts should eventually return to the reset values.
+ *
+ * Clk_Rst:        SRIO(0..1)_RX_STATUS    hclk    hrst_n
+ */
+union cvmx_sriox_rx_status
+{
+	uint64_t u64;
+	struct cvmx_sriox_rx_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t rtn_pr3                      : 8;  /**< Number of pending Priority 3 Response Entries. */
+	uint64_t rtn_pr2                      : 8;  /**< Number of pending Priority 2 Response Entries. */
+	uint64_t rtn_pr1                      : 8;  /**< Number of pending Priority 1 Response Entries. */
+	uint64_t reserved_28_39               : 12;
+	uint64_t mbox                         : 4;  /**< Credits for Mailbox Data used in M2S. */
+	uint64_t comp                         : 8;  /**< Credits for Read Completions used in M2S. */
+	uint64_t reserved_13_15               : 3;
+	uint64_t n_post                       : 5;  /**< Credits for Read Requests used in M2S. */
+	uint64_t post                         : 8;  /**< Credits for Write Request Postings used in M2S. */
+#else
+	uint64_t post                         : 8;
+	uint64_t n_post                       : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t comp                         : 8;
+	uint64_t mbox                         : 4;
+	uint64_t reserved_28_39               : 12;
+	uint64_t rtn_pr1                      : 8;
+	uint64_t rtn_pr2                      : 8;
+	uint64_t rtn_pr3                      : 8;
+#endif
+	} s;
+	struct cvmx_sriox_rx_status_s         cn63xx;
+	struct cvmx_sriox_rx_status_s         cn63xxp1;
+};
+typedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t;
+
+/**
+ * cvmx_srio#_s2m_type#
+ *
+ * SRIO_S2M_TYPE[0:15] = SLI to SRIO MAC Operation Type
+ *
+ * SRIO Operation Type selected by PP or DMA Accesses
+ *
+ * Notes:
+ * This CSR table specifies how to convert a SLI/DPI MAC read or write into sRIO operations.
+ *  Each SLI/DPI read or write access supplies a 64-bit address (MACADD[63:0]), 2-bit ADDRTYPE, and
+ *  2-bit endian-swap. This SRIO*_S2M_TYPE* CSR description specifies a table with 16 CSRs. SRIO
+ *  selects one of the table entries with TYPEIDX[3:0], which it creates from the SLI/DPI MAC memory
+ *  space read or write as follows:
+ *    TYPEIDX[1:0] = ADDRTYPE[1:0] (ADDRTYPE[1] is no-snoop to the PCIe MAC,
+ *                                  ADDRTYPE[0] is relaxed-ordering to the PCIe MAC)
+ *    TYPEIDX[2] = MACADD[50]
+ *    TYPEIDX[3] = MACADD[59]
+ *
+ * Clk_Rst:        SRIO(0..1)_S2M_TYPE[0:15]       hclk    hrst_n
+ */
+union cvmx_sriox_s2m_typex
+{
+	uint64_t u64;
+	struct cvmx_sriox_s2m_typex_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t wr_op                        : 3;  /**< sRIO operation for SLI/DPI writes
+
+                                                         SLI/DPI hardware break MAC memory space writes
+                                                         that they generate into pieces of maximum size
+                                                         256B. For NWRITE/NWRITE_R/SWRITE WR_OP variants
+                                                         below, SRIO will, if necessary to obey sRIO
+                                                         requirements, automatically break the write into
+                                                         even smaller writes. The same is not true for
+                                                         MAINTENANCE writes and port-writes. Additional
+                                                         SW/usage restrictions are required for these
+                                                         MAINTENANCE WR_OP's to work correctly. SW must
+                                                         restrict the alignment and length of DPI pointers,
+                                                         limit the store sizes that the cores issue, and
+                                                         possibly also set SLI_MEM_ACCESS_SUBID*[NMERGE]
+                                                         so that all MAC memory space writes with
+                                                         MAINTENANCE write and port-write WR_OP's can be
+                                                         serviced in a single sRIO operation.
+
+                                                         SRIO always sends the write data (64-bit) words
+                                                         out in order.
+
+                                                          WR_OP = 0 = Normal Write (NWRITE)
+                                                                 SRIO breaks a MAC memory space write into
+                                                                 the minimum number of required sRIO NWRITE
+                                                                 operations. This will be 1-5 total NWRITEs,
+                                                                 depending on endian-swap, alignment, and
+                                                                 length.
+
+                                                          WR_OP = 1 = Normal Write w/Response (NWRITE_R)
+                                                                 SRIO breaks a MAC memory space write into
+                                                                 the minimum number of required sRIO
+                                                                 NWRITE_R operations. This will be 1-5 total
+                                                                 NWRITE_R's, depending on endian-swap,
+                                                                 alignment, and length.
+
+                                                                 SRIO sets SRIO*_INT_REG[WR_DONE] after it
+                                                                 receives the DONE response for the last
+                                                                 NWRITE_R sent.
+
+                                                          WR_OP = 2 = NWRITE, Streaming write (SWRITE),
+                                                                      NWRITE
+                                                                 SRIO attempts to turn the MAC memory space
+                                                                 write into an SWRITE operation. There will
+                                                                 be 1-5 total sRIO operations (0-2 NWRITE's
+                                                                 followed by 0-1 SWRITE's followed by 0-2
+                                                                 NWRITE's) generated to complete the MAC
+                                                                 memory space write, depending on
+                                                                 endian-swap, alignment, and length.
+
+                                                                 If the starting address is not 64-bit
+                                                                 aligned, SRIO first creates 1-4 NWRITE's to
+                                                                 either align it or complete the write. Then
+                                                                 SRIO creates a SWRITE including all aligned
+                                                                 64-bit words. (SRIO won't create an SWRITE
+                                                                 when there are none.) If store data
+                                                                 remains, SRIO finally creates another 1 or
+                                                                 2 NWRITE's.
+
+                                                          WR_OP = 3 = NWRITE, SWRITE, NWRITE_R
+                                                                 SRIO attempts to turn the MAC memory space
+                                                                 write into an SWRITE operation followed by
+                                                                 a NWRITE_R operation. The last operation
+                                                                 is always NWRITE_R. There will be 1-5
+                                                                 total sRIO operations (0-2 NWRITE's,
+                                                                 followed by 0-1 SWRITE, followed by 1-4
+                                                                 NWRITE_R's) generated to service the MAC
+                                                                 memory space write, depending on
+                                                                 endian-swap, alignment, and length.
+
+                                                                 If the write is contained in one aligned
+                                                                 64-bit word, SRIO will completely service
+                                                                 the MAC memory space write with 1-4
+                                                                 NWRITE_R's.
+
+                                                                 Otherwise, if the write spans multiple
+                                                                 words, SRIO services the write as follows.
+                                                                 First, if the start of the write is not
+                                                                 word-aligned, SRIO creates 1 or 2 NWRITE's
+                                                                 to align it. Then SRIO creates an SWRITE
+                                                                 that includes all aligned 64-bit words,
+                                                                 leaving data for the final NWRITE_R(s).
+                                                                 (SRIO won't create the SWRITE when there is
+                                                                 no data for it.) Then SRIO finally creates
+                                                                 1 or 2 NWRITE_R's.
+
+                                                                 In any case, SRIO sets
+                                                                 SRIO*_INT_REG[WR_DONE] after it receives
+                                                                 the DONE response for the last NWRITE_R
+                                                                 sent.
+
+                                                          WR_OP = 4 = NWRITE, NWRITE_R
+                                                                 SRIO attempts to turn the MAC memory space
+                                                                 write into an NWRITE operation followed by
+                                                                 a NWRITE_R operation. The last operation
+                                                                 is always NWRITE_R. There will be 1-5
+                                                                 total sRIO operations (0-3 NWRITE's
+                                                                 followed by 1-4 NWRITE_R's) generated to
+                                                                 service the MAC memory space write,
+                                                                 depending on endian-swap, alignment, and
+                                                                 length.
+
+                                                                 If the write is contained in one aligned
+                                                                 64-bit word, SRIO will completely service
+                                                                 the MAC memory space write with 1-4
+                                                                 NWRITE_R's.
+
+                                                                 Otherwise, if the write spans multiple
+                                                                 words, SRIO services the write as follows.
+                                                                 First, if the start of the write is not
+                                                                 word-aligned, SRIO creates 1 or 2 NWRITE's
+                                                                 to align it. Then SRIO creates an NWRITE
+                                                                 that includes all aligned 64-bit words,
+                                                                 leaving data for the final NWRITE_R(s).
+                                                                 (SRIO won't create this NWRITE when there
+                                                                 is no data for it.) Then SRIO finally
+                                                                 creates 1 or 2 NWRITE_R's.
+
+                                                                 In any case, SRIO sets
+                                                                 SRIO*_INT_REG[WR_DONE] after it receives
+                                                                 the DONE response for the last NWRITE_R
+                                                                 sent.
+
+                                                          WR_OP = 5 = Reserved
+
+                                                          WR_OP = 6 = Maintenance Write
+                                                               - SRIO will create one sRIO MAINTENANCE write
+                                                                 operation to service the MAC memory space
+                                                                 write
+                                                               - IAOW_SEL must be zero. (see description
+                                                                 below.)
+                                                               - MDS must be zero. (MDS is MACADD[63:62] -
+                                                                 see IAOW_SEL description below.)
+                                                               - Hop Cnt is MACADD[31:24]/SRIOAddress[31:24]
+                                                               - MACADD[23:0]/SRIOAddress[23:0] selects
+                                                                 maintenance register (i.e. config_offset)
+                                                               - sRIODestID[15:0] is MACADD[49:34].
+                                                                 (MACADD[49:42] unused when ID16=0)
+                                                               - Write size/alignment must obey sRIO rules
+                                                                 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte
+                                                                 lengths allowed)
+
+                                                          WR_OP = 7 = Maintenance Port Write
+                                                               - SRIO will create one sRIO MAINTENANCE port
+                                                                 write operation to service the MAC memory
+                                                                 space write
+                                                               - IAOW_SEL must be zero. (see description
+                                                                 below.)
+                                                               - MDS must be zero. (MDS is MACADD[63:62] -
+                                                                 see IAOW_SEL description below.)
+                                                               - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24]
+                                                               - MACADD[23:0]/sRIOAddress[23:0] MBZ
+                                                                 (config_offset field reserved by sRIO)
+                                                               - sRIODestID[15:0] is MACADD[49:34].
+                                                                 (MACADD[49:42] unused when ID16=0)
+                                                               - Write size/alignment must obey sRIO rules
+                                                                 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte
+                                                                 lengths allowed) */
+	uint64_t reserved_15_15               : 1;
+	uint64_t rd_op                        : 3;  /**< sRIO operation for SLI/DPI reads
+
+                                                         SLI/DPI hardware and sRIO configuration
+                                                         restrictions guarantee that SRIO can service any
+                                                         MAC memory space read that it receives from SLI/DPI
+                                                         with a single NREAD, assuming that RD_OP selects
+                                                         NREAD. DPI will break a read into multiple MAC
+                                                         memory space reads to ensure this holds. The same
+                                                         is not true for the ATOMIC and MAINTENANCE RD_OP
+                                                         values. Additional SW/usage restrictions are
+                                                         required for ATOMIC and MAINTENANCE RD_OP to work
+                                                         correctly. SW must restrict the alignment and
+                                                         length of DPI pointers and limit the load sizes
+                                                         that the cores issue such that all MAC memory space
+                                                         reads with ATOMIC and MAINTENANCE RD_OP's can be
+                                                         serviced in a single sRIO operation.
+
+                                                          RD_OP = 0 = Normal Read (NREAD)
+                                                               - SRIO will create one sRIO NREAD
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (up to 256 byte lengths). (This requirement
+                                                                 is guaranteed by SLI/DPI usage restrictions
+                                                                 and configuration.)
+
+                                                          RD_OP = 1 = Reserved
+
+                                                          RD_OP = 2 = Atomic Set
+                                                               - SRIO will create one sRIO ATOMIC set
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (1, 2, and 4 byte lengths allowed)
+
+                                                          RD_OP = 3 = Atomic Clear
+                                                               - SRIO will create one sRIO ATOMIC clr
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (1, 2, and 4 byte lengths allowed)
+
+                                                          RD_OP = 4 = Atomic Increment
+                                                               - SRIO will create one sRIO ATOMIC inc
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (1, 2, and 4 byte lengths allowed)
+
+                                                          RD_OP = 5 = Atomic Decrement
+                                                               - SRIO will create one sRIO ATOMIC dec
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (1, 2, and 4 byte lengths allowed)
+
+                                                          RD_OP = 6 = Maintenance Read
+                                                               - SRIO will create one sRIO MAINTENANCE read
+                                                                 operation to service the MAC memory
+                                                                 space read
+                                                               - IAOW_SEL must be zero. (see description
+                                                                 below.)
+                                                               - MDS must be zero. (MDS is MACADD[63:62] -
+                                                                 see IAOW_SEL description below.)
+                                                               - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24]
+                                                               - MACADD[23:0]/sRIOAddress[23:0] selects
+                                                                 maintenance register (i.e. config_offset)
+                                                               - sRIODestID[15:0] is MACADD[49:34].
+                                                                 (MACADD[49:42] unused when ID16=0)
+                                                               - Read size/alignment must obey sRIO rules
+                                                                 (4, 8, 16, 32 and 64 byte lengths allowed)
+
+                                                          RD_OP = 7 = Reserved */
+	uint64_t wr_prior                     : 2;  /**< Transaction Priority 0-3 used for writes */
+	uint64_t rd_prior                     : 2;  /**< Transaction Priority 0-3 used for reads/ATOMICs */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t src_id                       : 1;  /**< Source ID
+
+                                                         0 = Use Primary ID as Source ID
+                                                             (SRIOMAINT*_PRI_DEV_ID[ID16 or ID8], depending
+                                                             on SRIO TT ID (i.e. ID16 below))
+
+                                                         1 = Use Secondary ID as Source ID
+                                                             (SRIOMAINT*_SEC_DEV_ID[ID16 or ID8], depending
+                                                             on SRIO TT ID (i.e. ID16 below)) */
+	uint64_t id16                         : 1;  /**< SRIO TT ID 0=8bit, 1=16-bit
+                                                         IAOW_SEL must not be 2 when ID16=1. */
+	uint64_t reserved_2_3                 : 2;
+	uint64_t iaow_sel                     : 2;  /**< Internal Address Offset Width Select
+
+                                                         IAOW_SEL determines how to convert the
+                                                         MACADD[63:62,58:51,49:0] recieved from SLI/DPI with
+                                                         read/write into an sRIO address (sRIOAddress[...])
+                                                         and sRIO destination ID (sRIODestID[...]). The sRIO
+                                                         address width mode (SRIOMAINT_PE_LLC[EX_ADDR]) and
+                                                         ID16, determine the  width of the sRIO address and
+                                                         ID in the outgoing request(s), respectively.
+
+                                                         MACADD[61:60] is always unused.
+
+                                                         MACADD[59] is always TYPEIDX[3]
+                                                         MACADD[50] is always TYPEIDX[2]
+                                                          (TYPEIDX[3:0] selects one of these
+                                                          SRIO*_S2M_TYPE* table entries.)
+
+                                                         MACADD[17:0] always becomes sRIOAddress[17:0].
+
+                                                          IAOW_SEL = 0 = 34-bit Address Offset
+
+                                                              Must be used when sRIO link is in 34-bit
+                                                               address width mode.
+                                                              When sRIO is in 50-bit address width mode,
+                                                               sRIOAddress[49:34]=0 in the outgoing request.
+                                                              When sRIO is in 66-bit address width mode,
+                                                               sRIOAddress[65:34]=0 in the outgoing request.
+
+                                                              Usage of the SLI/DPI MAC address when
+                                                              IAOW_SEL = 0:
+                                                               MACADD[63:62] = Multi-Device Swap (MDS)
+                                                                 MDS value affects MACADD[49:18] usage
+                                                               MACADD[58:51] => unused
+                                                               MACADD[49:18] usage depends on MDS value
+                                                                MDS = 0
+                                                                  MACADD[49:34] => sRIODestID[15:0]
+                                                                    (MACADD[49:42] unused when ID16=0)
+                                                                  MACADD[33:18] => sRIOAddress[33:18]
+                                                                MDS = 1
+                                                                  MACADD[49:42] => sRIODestID[15:8]
+                                                                    (MACADD[49:42] unused when ID16 = 0)
+                                                                  MACADD[41:34] => sRIOAddress[33:26]
+                                                                  MACADD[33:26] => sRIODestID[7:0]
+                                                                  MACADD[25:18] => sRIOAddress[25:18]
+                                                                MDS = 2
+                                                                  ID16 must be one.
+                                                                  MACADD[49:34] => sRIOAddress[33:18]
+                                                                  MACADD[33:18] => sRIODestID[15:0]
+                                                                MDS = 3 = Reserved
+
+                                                          IAOW_SEL = 1 = 42-bit Address Offset
+
+                                                              Must not be used when sRIO link is in 34-bit
+                                                               address width mode.
+                                                              When sRIO is in 50-bit address width mode,
+                                                               sRIOAddress[49:42]=0 in the outgoing request.
+                                                              When sRIO is in 66-bit address width mode,
+                                                               sRIOAddress[65:42]=0 in the outgoing request.
+
+                                                              Usage of the SLI/DPI MAC address when
+                                                              IAOW_SEL = 1:
+                                                               MACADD[63:62] => Multi-Device Swap (MDS)
+                                                                 MDS value affects MACADD[58:51,49:42,33:18]
+                                                                   use
+                                                               MACADD[41:34] => sRIOAddress[41:34]
+                                                               MACADD[58:51,49:42,33:18] usage depends on
+                                                               MDS value:
+                                                                MDS = 0
+                                                                  MACADD[58:51] => sRIODestID[15:8]
+                                                                  MACADD[49:42] => sRIODestID[7:0]
+                                                                    (MACADD[58:51] unused when ID16=0)
+                                                                  MACADD[33:18] => sRIOAddress[33:18]
+                                                                MDS = 1
+                                                                  MACADD[58:51] => sRIODestID[15:8]
+                                                                    (MACADD[58:51] unused when ID16 = 0)
+                                                                  MACADD[49:42] => sRIOAddress[33:26]
+                                                                  MACADD[33:26] => sRIODestID[7:0]
+                                                                  MACADD[25:18] => sRIOAddress[25:18]
+                                                                MDS = 2
+                                                                  ID16 must be one.
+                                                                  MACADD[58:51] => sRIOAddress[33:26]
+                                                                  MACADD[49:42] => sRIOAddress[25:18]
+                                                                  MACADD[33:18] => sRIODestID[15:0]
+                                                                MDS = 3 = Reserved
+
+                                                          IAOW_SEL = 2 = 50-bit Address Offset
+
+                                                              Must not be used when sRIO link is in 34-bit
+                                                               address width mode.
+                                                              Must not be used when ID16=1.
+                                                              When sRIO is in 66-bit address width mode,
+                                                               sRIOAddress[65:50]=0 in the outgoing request.
+
+                                                              Usage of the SLI/DPI MAC address when
+                                                              IAOW_SEL = 2:
+                                                               MACADD[63:62] => Multi-Device Swap (MDS)
+                                                                 MDS value affects MACADD[58:51,33:26] use
+                                                                 MDS value 3 is reserved
+                                                               MACADD[49:34] => sRIOAddress[49:34]
+                                                               MACADD[25:18] => sRIOAddress[25:18]
+                                                               MACADD[58:51,33:26] usage depends on
+                                                               MDS value:
+                                                                MDS = 0
+                                                                  MACADD[58:51] => sRIODestID[7:0]
+                                                                  MACADD[33:26] => sRIOAddress[33:26]
+                                                                MDS = 1
+                                                                  MACADD[58:51] => sRIOAddress[33:26]
+                                                                  MACADD[33:26] => sRIODestID[7:0]
+                                                                MDS = 2 = Reserved
+                                                                MDS = 3 = Reserved
+
+                                                          IAOW_SEL = 3 = Reserved */
+#else
+	uint64_t iaow_sel                     : 2;
+	uint64_t reserved_2_3                 : 2;
+	uint64_t id16                         : 1;
+	uint64_t src_id                       : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t rd_prior                     : 2;
+	uint64_t wr_prior                     : 2;
+	uint64_t rd_op                        : 3;
+	uint64_t reserved_15_15               : 1;
+	uint64_t wr_op                        : 3;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_sriox_s2m_typex_s         cn63xx;
+	struct cvmx_sriox_s2m_typex_s         cn63xxp1;
+};
+typedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t;
+
+/**
+ * cvmx_srio#_seq
+ *
+ * SRIO_SEQ = SRIO Sequence Count
+ *
+ * The SRIO Sequence Count
+ *
+ * Notes:
+ * This register contains the current value of the sequence counter.  This counter increments every
+ *  time a doorbell or the first segment of a message is accepted.
+ *
+ * Clk_Rst:        SRIO(0..1)_SEQ  hclk    hrst_n
+ */
+union cvmx_sriox_seq
+{
+	uint64_t u64;
+	struct cvmx_sriox_seq_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t seq                          : 32; /**< 32-bit Sequence \# */
+#else
+	uint64_t seq                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_seq_s               cn63xx;
+	struct cvmx_sriox_seq_s               cn63xxp1;
+};
+typedef union cvmx_sriox_seq cvmx_sriox_seq_t;
+
+/**
+ * cvmx_srio#_status_reg
+ *
+ * SRIO_STATUS_REG = SRIO Status Register
+ *
+ * General status of the SRIO.
+ *
+ * Notes:
+ * The SRIO field displays if the port has been configured for SRIO operation.  This register can be
+ *  read regardless of whether the SRIO is selected or being reset.  Although some other registers can
+ *  be accessed while the ACCESS bit is zero (see individual registers for details), the majority of
+ *  SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted.
+ *
+ * Clk_Rst:        SRIO(0..1)_STATUS_REG   sclk    srst_n
+ */
+union cvmx_sriox_status_reg
+{
+	uint64_t u64;
+	struct cvmx_sriox_status_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t access                       : 1;  /**< SRIO and SRIOMAINT Register Access.
+                                                         0 - Register Access Disabled.
+                                                         1 - Register Access Enabled. */
+	uint64_t srio                         : 1;  /**< SRIO Port Enabled.
+                                                         0 - All SRIO functions disabled.
+                                                         1 - All SRIO Operations permitted. */
+#else
+	uint64_t srio                         : 1;
+	uint64_t access                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_sriox_status_reg_s        cn63xx;
+	struct cvmx_sriox_status_reg_s        cn63xxp1;
+};
+typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
+
+/**
+ * cvmx_srio#_tag_ctrl
+ *
+ * SRIO_TAG_CTRL = SRIO TAG Control
+ *
+ * The SRIO TAG Control
+ *
+ * Notes:
+ * This register is used to show the state of the internal transaction tags and provides a manual
+ *  reset of the outgoing tags.
+ *
+ * Clk_Rst:        SRIO(0..1)_TAG_CTRL     hclk    hrst_n
+ */
+union cvmx_sriox_tag_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_tag_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t o_clr                        : 1;  /**< Manual OTAG Clear.  This bit manually resets the
+                                                         number of OTAGs back to 16 and loses track of any
+                                                         outgoing packets.  This function is automatically
+                                                         performed when the SRIO MAC is reset but it may be
+                                                         necessary after a chip reset while the MAC is in
+                                                         operation.  This bit must be set then cleared to
+                                                         return to normal operation.  Typically, Outgoing
+                                                         SRIO packets must be halted 6 seconds prior to
+                                                         this bit is set to avoid generating duplicate tags
+                                                         and unexpected response errors. */
+	uint64_t reserved_13_15               : 3;
+	uint64_t otag                         : 5;  /**< Number of Available Outbound Tags.  Tags are
+                                                         required for all outgoing memory and maintenance
+                                                         operations that require a response. (Max 16) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t itag                         : 5;  /**< Number of Available Inbound Tags.  Tags are
+                                                         required for all incoming memory operations that
+                                                         require a response. (Max 16) */
+#else
+	uint64_t itag                         : 5;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t otag                         : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t o_clr                        : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_sriox_tag_ctrl_s          cn63xx;
+	struct cvmx_sriox_tag_ctrl_s          cn63xxp1;
+};
+typedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t;
+
+/**
+ * cvmx_srio#_tlp_credits
+ *
+ * SRIO_TLP_CREDITS = SRIO TLP Credits
+ *
+ * Specifies the number of credits the SRIO can use for incoming Commands and Messages.
+ *
+ * Notes:
+ * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages.
+ *
+ * Clk_Rst:        SRIO(0..1)_TLP_CREDITS  hclk    hrst_n
+ */
+union cvmx_sriox_tlp_credits
+{
+	uint64_t u64;
+	struct cvmx_sriox_tlp_credits_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_28_63               : 36;
+	uint64_t mbox                         : 4;  /**< Credits for Mailbox Data used in M2S.
+                                                         Legal values are 0x2 to 0x8. */
+	uint64_t comp                         : 8;  /**< Credits for Read Completions used in M2S.
+                                                         Legal values are 0x22 to 0x80. */
+	uint64_t reserved_13_15               : 3;
+	uint64_t n_post                       : 5;  /**< Credits for Read Requests used in M2S.
+                                                         Legal values are 0x4 to 0x10. */
+	uint64_t post                         : 8;  /**< Credits for Write Request Postings used in M2S.
+                                                         Legal values are 0x22 to 0x80. */
+#else
+	uint64_t post                         : 8;
+	uint64_t n_post                       : 5;
+	uint64_t reserved_13_15               : 3;
+	uint64_t comp                         : 8;
+	uint64_t mbox                         : 4;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_sriox_tlp_credits_s       cn63xx;
+	struct cvmx_sriox_tlp_credits_s       cn63xxp1;
+};
+typedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t;
+
+/**
+ * cvmx_srio#_tx_bell
+ *
+ * SRIO_TX_BELL = SRIO Transmit Doorbell
+ *
+ * The SRIO Outgoing (TX) Doorbell
+ *
+ * Notes:
+ * This register specifies SRIO Information, Device ID, Transaction Type and Priority of the outgoing
+ *  Doorbell Transaction.  Writes to this register causes the Doorbell to be issued using these bits.
+ *  The write also causes the PENDING bit to be set. The hardware automatically clears bit when the
+ *  Doorbell operation has been acknowledged.  A write to this register while the PENDING bit is set
+ *  should be avoided as it will stall the RSL until the first Doorbell has completed.
+ *
+ * Clk_Rst:        SRIO(0..1)_TX_BELL      hclk    hrst_n
+ */
+union cvmx_sriox_tx_bell
+{
+	uint64_t u64;
+	struct cvmx_sriox_tx_bell_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t data                         : 16; /**< Information field for next doorbell operation */
+	uint64_t dest_id                      : 16; /**< Doorbell Destination Device ID[15:0] */
+	uint64_t reserved_9_15                : 7;
+	uint64_t pending                      : 1;  /**< Doorbell Transmit in Progress */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t src_id                       : 1;  /**< Source Device ID 0=Primary, 1=Secondary */
+	uint64_t id16                         : 1;  /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t priority                     : 2;  /**< Doorbell Priority */
+#else
+	uint64_t priority                     : 2;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t id16                         : 1;
+	uint64_t src_id                       : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t pending                      : 1;
+	uint64_t reserved_9_15                : 7;
+	uint64_t dest_id                      : 16;
+	uint64_t data                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_sriox_tx_bell_s           cn63xx;
+	struct cvmx_sriox_tx_bell_s           cn63xxp1;
+};
+typedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t;
+
+/**
+ * cvmx_srio#_tx_bell_info
+ *
+ * SRIO_TX_BELL_INFO = SRIO Transmit Doorbell Interrupt Information
+ *
+ * The SRIO Outgoing (TX) Doorbell Interrupt Information
+ *
+ * Notes:
+ * This register is only updated if the BELL_ERR bit is clear in SRIO(0..1)_INT_REG.  This register
+ *  displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction
+ *  that generated the BELL_ERR Interrupt.  The register includes either a RETRY, ERROR or TIMEOUT
+ *  Status.
+ *
+ * Clk_Rst:        SRIO(0..1)_TX_BELL_INFO hclk    hrst_n
+ */
+union cvmx_sriox_tx_bell_info
+{
+	uint64_t u64;
+	struct cvmx_sriox_tx_bell_info_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t data                         : 16; /**< Information field from last doorbell operation */
+	uint64_t dest_id                      : 16; /**< Doorbell Destination Device ID[15:0] */
+	uint64_t reserved_8_15                : 8;
+	uint64_t timeout                      : 1;  /**< Transmit Doorbell Failed with Timeout. */
+	uint64_t error                        : 1;  /**< Transmit Doorbell Destination returned Error. */
+	uint64_t retry                        : 1;  /**< Transmit Doorbell Requests a retransmission. */
+	uint64_t src_id                       : 1;  /**< Source Device ID 0=Primary, 1=Secondary */
+	uint64_t id16                         : 1;  /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
+	uint64_t reserved_2_2                 : 1;
+	uint64_t priority                     : 2;  /**< Doorbell Priority */
+#else
+	uint64_t priority                     : 2;
+	uint64_t reserved_2_2                 : 1;
+	uint64_t id16                         : 1;
+	uint64_t src_id                       : 1;
+	uint64_t retry                        : 1;
+	uint64_t error                        : 1;
+	uint64_t timeout                      : 1;
+	uint64_t reserved_8_15                : 8;
+	uint64_t dest_id                      : 16;
+	uint64_t data                         : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_sriox_tx_bell_info_s      cn63xx;
+	struct cvmx_sriox_tx_bell_info_s      cn63xxp1;
+};
+typedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t;
+
+/**
+ * cvmx_srio#_tx_ctrl
+ *
+ * SRIO_TX_CTRL = SRIO Transmit Control
+ *
+ * The SRIO Transmit Control
+ *
+ * Notes:
+ * This register is used to control SRIO Outgoing Packet Allocation.  TX_TH[2:0] set the thresholds
+ *  to allow each priority traffic to be queued for transmission.  8 TX Buffer are available.  A
+ *  threshold greater than 8 stops all traffic on that priority and should be avoided.  TAG_TH[2:0]
+ *  set the thresholds to allow priority traffic requiring responses to be queued based on the number
+ *  of outgoing tags (TIDs) available.  16 Tags are available.  If a priority is blocked for lack of
+ *  tags then all lower priority packets are also blocked irregardless of whether they require tags.
+ *
+ * Clk_Rst:        SRIO(0..1)_TX_CTRL      hclk    hrst_n
+ */
+union cvmx_sriox_tx_ctrl
+{
+	uint64_t u64;
+	struct cvmx_sriox_tx_ctrl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_53_63               : 11;
+	uint64_t tag_th2                      : 5;  /**< Sets threshold for minimum number of OTAGs
+                                                         required before a packet of priority 2 requiring a
+                                                         response will be queued for transmission. (Max 16)
+                                                         There generally should be no priority 3 request
+                                                         packets which require a response/tag, so a TAG_THR
+                                                         value as low as 0 is allowed. */
+	uint64_t reserved_45_47               : 3;
+	uint64_t tag_th1                      : 5;  /**< Sets threshold for minimum number of OTAGs
+                                                         required before a packet of priority 1 requiring a
+                                                         response will be queued for transmission. (Max 16)
+                                                         Generally, TAG_TH1 must be > TAG_TH2 to leave OTAGs
+                                                         for outgoing priority 2 (or 3) requests. */
+	uint64_t reserved_37_39               : 3;
+	uint64_t tag_th0                      : 5;  /**< Sets threshold for minimum number of OTAGs
+                                                         required before a packet of priority 0 requiring a
+                                                         response will be queued for transmission. (Max 16)
+                                                         Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs
+                                                         for outgoing priority 1 or 2 (or 3) requests. */
+	uint64_t reserved_20_31               : 12;
+	uint64_t tx_th2                       : 4;  /**< Sets threshold for minimum number of TX buffers
+                                                         before a Priority 2 Packet will be queued for
+                                                         transmission. (Max 8)
+                                                         Generally, TX_TH2 must be > 0 to leave space for
+                                                         outgoing priority 3 packets. */
+	uint64_t reserved_12_15               : 4;
+	uint64_t tx_th1                       : 4;  /**< Sets threshold for minimum number of TX buffers
+                                                         before a Priority 1 Packet will be queued for
+                                                         transmission. (Max 8)
+                                                         Generally, TX_TH1 must be > TX_TH2 to leave space
+                                                         for outgoing priority 2 or 3 packets. */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t tx_th0                       : 4;  /**< Sets threshold for minimum number of TX buffers
+                                                         before a Priority 0 Packet will be queued for
+                                                         transmission. (Max 8)
+                                                         Generally, TX_TH0 must be > TX_TH1 to leave space
+                                                         for outgoing priority 1 or 2 or 3 packets. */
+#else
+	uint64_t tx_th0                       : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t tx_th1                       : 4;
+	uint64_t reserved_12_15               : 4;
+	uint64_t tx_th2                       : 4;
+	uint64_t reserved_20_31               : 12;
+	uint64_t tag_th0                      : 5;
+	uint64_t reserved_37_39               : 3;
+	uint64_t tag_th1                      : 5;
+	uint64_t reserved_45_47               : 3;
+	uint64_t tag_th2                      : 5;
+	uint64_t reserved_53_63               : 11;
+#endif
+	} s;
+	struct cvmx_sriox_tx_ctrl_s           cn63xx;
+	struct cvmx_sriox_tx_ctrl_s           cn63xxp1;
+};
+typedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t;
+
+/**
+ * cvmx_srio#_tx_emphasis
+ *
+ * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis (Pass 2)
+ *
+ * Controls TX Emphasis used by the SRIO SERDES
+ *
+ * Notes:
+ * This controls the emphasis value used by the SRIO SERDES.  This register is only reset during COLD
+ *  boot and may be modified regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS.
+ *
+ * Clk_Rst:        SRIO(0..1)_TX_EMPHASIS  sclk    srst_cold_n
+ */
+union cvmx_sriox_tx_emphasis
+{
+	uint64_t u64;
+	struct cvmx_sriox_tx_emphasis_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t emph                         : 4;  /**< Emphasis Value used for all lanes.  Default value
+                                                         is 0x0 for 1.25G b/s and 0xA for all other rates. */
+#else
+	uint64_t emph                         : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_sriox_tx_emphasis_s       cn63xx;
+};
+typedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t;
+
+/**
+ * cvmx_srio#_tx_status
+ *
+ * SRIO_TX_STATUS = SRIO Outbound Credits/Ops Status
+ *
+ * Specifies the current number of credits/ops by SRIO for Outbound Traffic
+ *
+ * Notes:
+ * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic.
+ *  When all outbound traffic has stopped the values should eventually return to the reset values.
+ *
+ * Clk_Rst:        SRIO(0..1)_TX_STATUS    hclk    hrst_n
+ */
+union cvmx_sriox_tx_status
+{
+	uint64_t u64;
+	struct cvmx_sriox_tx_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t s2m_pr3                      : 8;  /**< Number of pending S2M Priority 3 Entries. */
+	uint64_t s2m_pr2                      : 8;  /**< Number of pending S2M Priority 2 Entries. */
+	uint64_t s2m_pr1                      : 8;  /**< Number of pending S2M Priority 1 Entries. */
+	uint64_t s2m_pr0                      : 8;  /**< Number of pending S2M Priority 0 Entries. */
+#else
+	uint64_t s2m_pr0                      : 8;
+	uint64_t s2m_pr1                      : 8;
+	uint64_t s2m_pr2                      : 8;
+	uint64_t s2m_pr3                      : 8;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_tx_status_s         cn63xx;
+	struct cvmx_sriox_tx_status_s         cn63xxp1;
+};
+typedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t;
+
+/**
+ * cvmx_srio#_wr_done_counts
+ *
+ * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts (Pass 2)
+ *
+ * The SRIO Outbound Write Done Counts
+ *
+ * Notes:
+ * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC.
+ *  These count only considers the last NwriteR generated by each Store Instruction.  If any NwriteR
+ *  in the series receives an ERROR Status then it is reported in SRIOMAINT(0..1)_ERB_LT_ERR_DET.IO_ERR.
+ *  If any NwriteR does not receive a response within the timeout period then it is reported in
+ *  SRIOMAINT(0..1)_ERB_LT_ERR_DET.PKT_TOUT.  Only errors on the last NwriteR's are counted as BAD.  This
+ *  register is typically not written while Outbound SRIO Memory traffic is enabled.
+ *
+ * Clk_Rst:        SRIO(0..1)_WR_DONE_COUNTS       hclk    hrst_n
+ */
+union cvmx_sriox_wr_done_counts
+{
+	uint64_t u64;
+	struct cvmx_sriox_wr_done_counts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t bad                          : 16; /**< Count of the final outbound NwriteR in the series
+                                                         associated with a Store Operation that have timed
+                                                         out or received a response with an ERROR status. */
+	uint64_t good                         : 16; /**< Count of the final outbound NwriteR in the series
+                                                         associated with a Store operation that has
+                                                         received a response with a DONE status. */
+#else
+	uint64_t good                         : 16;
+	uint64_t bad                          : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_sriox_wr_done_counts_s    cn63xx;
+};
+typedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-srxx-defs.h b/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
new file mode 100644
index 0000000..75bfeeb
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
@@ -0,0 +1,375 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-srxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon srxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_SRXX_TYPEDEFS_H__
+#define __CVMX_SRXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_srx#_com_ctl
+ *
+ * SRX_COM_CTL - Spi receive common control
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be completely
+ * setup before writing the Interface enable (INF_EN) and Status channel
+ * enabled (ST_EN) asserted.
+ */
+union cvmx_srxx_com_ctl
+{
+	uint64_t u64;
+	struct cvmx_srxx_com_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t prts                         : 4;  /**< Number of ports in the receiver (write: ports - 1)
+                                                         - 0:  1 port
+                                                         - 1:  2 ports
+                                                         - 2:  3 ports
+                                                          - ...
+                                                          - 15: 16 ports */
+	uint64_t st_en                        : 1;  /**< Status channel enabled
+                                                         This is to allow configs without a status channel.
+                                                         This bit should not be modified once the
+                                                         interface is enabled. */
+	uint64_t reserved_1_2                 : 2;
+	uint64_t inf_en                       : 1;  /**< Interface enable
+                                                         The master switch that enables the entire
+                                                         interface. SRX will not validiate any data until
+                                                         this bit is set. This bit should not be modified
+                                                         once the interface is enabled. */
+#else
+	uint64_t inf_en                       : 1;
+	uint64_t reserved_1_2                 : 2;
+	uint64_t st_en                        : 1;
+	uint64_t prts                         : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_srxx_com_ctl_s            cn38xx;
+	struct cvmx_srxx_com_ctl_s            cn38xxp2;
+	struct cvmx_srxx_com_ctl_s            cn58xx;
+	struct cvmx_srxx_com_ctl_s            cn58xxp1;
+};
+typedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t;
+
+/**
+ * cvmx_srx#_ign_rx_full
+ *
+ * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure
+ *
+ *
+ * Notes:
+ * * IGNORE
+ * If a device can not or should not assert backpressure, then setting DROP
+ * will force STARVING status on the status channel for all ports.  This
+ * eliminates any back pressure from N2.
+ *
+ * This implies that it's ok drop packets when the FIFOS fill up.
+ *
+ * A side effect of this mode is that the TPA Watcher will effectively be
+ * disabled.  Since the DROP mode forces all TPA lines asserted, the TPA
+ * Watcher will never find a cycle where the TPA for the selected port is
+ * deasserted in order to increment its count.
+ */
+union cvmx_srxx_ign_rx_full
+{
+	uint64_t u64;
+	struct cvmx_srxx_ign_rx_full_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t ignore                       : 16; /**< This port should ignore backpressure hints from
+                                                          GMX when the RX FIFO fills up
+                                                         - 0: Use GMX backpressure
+                                                         - 1: Ignore GMX backpressure */
+#else
+	uint64_t ignore                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_srxx_ign_rx_full_s        cn38xx;
+	struct cvmx_srxx_ign_rx_full_s        cn38xxp2;
+	struct cvmx_srxx_ign_rx_full_s        cn58xx;
+	struct cvmx_srxx_ign_rx_full_s        cn58xxp1;
+};
+typedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t;
+
+/**
+ * cvmx_srx#_spi4_cal#
+ *
+ * specify the RSL base addresses for the block
+ * SRX_SPI4_CAL - Spi4 Calender table
+ * direct_calendar_write / direct_calendar_read
+ *
+ * Notes:
+ * There are 32 calendar table CSR's, each containing 4 entries for a
+ *     total of 128 entries.  In the above definition...
+ *
+ *           n = calendar table offset * 4
+ *
+ *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
+ *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
+ *        and would contain entries (16*4) = 64, 65, 66, and 67.
+ *
+ * Restrictions:
+ *          Calendar table entry accesses (read or write) can only occur
+ *          if the interface is disabled.  All other accesses will be
+ *          unpredictable.
+ *
+ *          Both the calendar table and the LEN and M parameters must be
+ *          completely setup before writing the Interface enable (INF_EN) and
+ *          Status channel enabled (ST_EN) asserted.
+ */
+union cvmx_srxx_spi4_calx
+{
+	uint64_t u64;
+	struct cvmx_srxx_spi4_calx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t oddpar                       : 1;  /**< Odd parity over SRX_SPI4_CAL[15:0]
+                                                         (^SRX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
+	uint64_t prt3                         : 4;  /**< Status for port n+3 */
+	uint64_t prt2                         : 4;  /**< Status for port n+2 */
+	uint64_t prt1                         : 4;  /**< Status for port n+1 */
+	uint64_t prt0                         : 4;  /**< Status for port n+0 */
+#else
+	uint64_t prt0                         : 4;
+	uint64_t prt1                         : 4;
+	uint64_t prt2                         : 4;
+	uint64_t prt3                         : 4;
+	uint64_t oddpar                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_srxx_spi4_calx_s          cn38xx;
+	struct cvmx_srxx_spi4_calx_s          cn38xxp2;
+	struct cvmx_srxx_spi4_calx_s          cn58xx;
+	struct cvmx_srxx_spi4_calx_s          cn58xxp1;
+};
+typedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t;
+
+/**
+ * cvmx_srx#_spi4_stat
+ *
+ * SRX_SPI4_STAT - Spi4 status channel control
+ *
+ *
+ * Notes:
+ * Restrictions:
+ *    Both the calendar table and the LEN and M parameters must be
+ *    completely setup before writing the Interface enable (INF_EN) and
+ *    Status channel enabled (ST_EN) asserted.
+ *
+ * Current rev only supports LVTTL status IO
+ */
+union cvmx_srxx_spi4_stat
+{
+	uint64_t u64;
+	struct cvmx_srxx_spi4_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t m                            : 8;  /**< CALENDAR_M (from spi4.2 spec) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t len                          : 7;  /**< CALENDAR_LEN (from spi4.2 spec) */
+#else
+	uint64_t len                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t m                            : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_srxx_spi4_stat_s          cn38xx;
+	struct cvmx_srxx_spi4_stat_s          cn38xxp2;
+	struct cvmx_srxx_spi4_stat_s          cn58xx;
+	struct cvmx_srxx_spi4_stat_s          cn58xxp1;
+};
+typedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t;
+
+/**
+ * cvmx_srx#_sw_tick_ctl
+ *
+ * SRX_SW_TICK_CTL - Create a software tick of Spi4 data.  A write to this register will create a data tick.
+ *
+ */
+union cvmx_srxx_sw_tick_ctl
+{
+	uint64_t u64;
+	struct cvmx_srxx_sw_tick_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t eop                          : 1;  /**< SW Tick EOP
+                                                         (PASS3 only) */
+	uint64_t sop                          : 1;  /**< SW Tick SOP
+                                                         (PASS3 only) */
+	uint64_t mod                          : 4;  /**< SW Tick MOD - valid byte count
+                                                         (PASS3 only) */
+	uint64_t opc                          : 4;  /**< SW Tick ERR - packet had an error
+                                                         (PASS3 only) */
+	uint64_t adr                          : 4;  /**< SW Tick port address
+                                                         (PASS3 only) */
+#else
+	uint64_t adr                          : 4;
+	uint64_t opc                          : 4;
+	uint64_t mod                          : 4;
+	uint64_t sop                          : 1;
+	uint64_t eop                          : 1;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} s;
+	struct cvmx_srxx_sw_tick_ctl_s        cn38xx;
+	struct cvmx_srxx_sw_tick_ctl_s        cn58xx;
+	struct cvmx_srxx_sw_tick_ctl_s        cn58xxp1;
+};
+typedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t;
+
+/**
+ * cvmx_srx#_sw_tick_dat
+ *
+ * SRX_SW_TICK_DAT - Create a software tick of Spi4 data
+ *
+ */
+union cvmx_srxx_sw_tick_dat
+{
+	uint64_t u64;
+	struct cvmx_srxx_sw_tick_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t dat                          : 64; /**< Data tick when SRX_SW_TICK_CTL is written
+                                                         (PASS3 only) */
+#else
+	uint64_t dat                          : 64;
+#endif
+	} s;
+	struct cvmx_srxx_sw_tick_dat_s        cn38xx;
+	struct cvmx_srxx_sw_tick_dat_s        cn58xx;
+	struct cvmx_srxx_sw_tick_dat_s        cn58xxp1;
+};
+typedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-stxx-defs.h b/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
new file mode 100644
index 0000000..614ea0a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
@@ -0,0 +1,896 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-stxx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon stxx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_STXX_TYPEDEFS_H__
+#define __CVMX_STXX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+		cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
+}
+#else
+#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+		cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull;
+}
+#else
+#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
+#endif
+
+/**
+ * cvmx_stx#_arb_ctl
+ *
+ * STX_ARB_CTL - Spi transmit arbitration control
+ *
+ *
+ * Notes:
+ * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
+ * parameter will have to be adjusted.  Please see the
+ * STX_SPI4_DAT[MAX_T] section for additional information.  In
+ * addition, the min_burst can only be guaranteed on the initial data
+ * burst of a given packet (i.e. the first data burst which contains
+ * the SOP tick).  All subsequent bursts could be truncated by training
+ * sequences at any point during transmission and could be arbitrarily
+ * small.  This mode is only for use in Spi4 mode.
+ */
+union cvmx_stxx_arb_ctl
+{
+	uint64_t u64;
+	struct cvmx_stxx_arb_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t mintrn                       : 1;  /**< Hold off training cycles until STX_MIN_BST[MINB]
+                                                         is satisfied */
+	uint64_t reserved_4_4                 : 1;
+	uint64_t igntpa                       : 1;  /**< User switch to ignore any TPA information from the
+                                                         Spi interface. This CSR forces all TPA terms to
+                                                         be masked out.  It is only intended as backdoor
+                                                         or debug feature. */
+	uint64_t reserved_0_2                 : 3;
+#else
+	uint64_t reserved_0_2                 : 3;
+	uint64_t igntpa                       : 1;
+	uint64_t reserved_4_4                 : 1;
+	uint64_t mintrn                       : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_stxx_arb_ctl_s            cn38xx;
+	struct cvmx_stxx_arb_ctl_s            cn38xxp2;
+	struct cvmx_stxx_arb_ctl_s            cn58xx;
+	struct cvmx_stxx_arb_ctl_s            cn58xxp1;
+};
+typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t;
+
+/**
+ * cvmx_stx#_bckprs_cnt
+ *
+ * Notes:
+ * This register reports the total number of cycles (STX data clks -
+ * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA
+ * or is otherwise receiving backpressure.
+ *
+ * In Spi4 mode, this is defined as a loss of TPA which is indicated when
+ * the receiving device reports SATISFIED for the given port.  The calendar
+ * status is brought into N2 on the spi4_tx*_sclk and synchronized into the
+ * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk
+ * clock (internally, this the stx_clk).  The counter will update on the
+ * rising edge in which backpressure is reported.
+ *
+ * This register will be cleared when software writes all '1's to
+ * the STX_BCKPRS_CNT.
+ */
+union cvmx_stxx_bckprs_cnt
+{
+	uint64_t u64;
+	struct cvmx_stxx_bckprs_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Number of cycles when back-pressure is received
+                                                         for port defined in STX_STAT_CTL[BCKPRS] */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_stxx_bckprs_cnt_s         cn38xx;
+	struct cvmx_stxx_bckprs_cnt_s         cn38xxp2;
+	struct cvmx_stxx_bckprs_cnt_s         cn58xx;
+	struct cvmx_stxx_bckprs_cnt_s         cn58xxp1;
+};
+typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t;
+
+/**
+ * cvmx_stx#_com_ctl
+ *
+ * STX_COM_CTL - TX Common Control Register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be
+ * completely setup before writing the Interface enable (INF_EN) and
+ * Status channel enabled (ST_EN) asserted.
+ */
+union cvmx_stxx_com_ctl
+{
+	uint64_t u64;
+	struct cvmx_stxx_com_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t st_en                        : 1;  /**< Status channel enabled */
+	uint64_t reserved_1_2                 : 2;
+	uint64_t inf_en                       : 1;  /**< Interface enable */
+#else
+	uint64_t inf_en                       : 1;
+	uint64_t reserved_1_2                 : 2;
+	uint64_t st_en                        : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_stxx_com_ctl_s            cn38xx;
+	struct cvmx_stxx_com_ctl_s            cn38xxp2;
+	struct cvmx_stxx_com_ctl_s            cn58xx;
+	struct cvmx_stxx_com_ctl_s            cn58xxp1;
+};
+typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t;
+
+/**
+ * cvmx_stx#_dip_cnt
+ *
+ * Notes:
+ * * DIPMAX
+ *   This counts the number of consecutive DIP2 states in which the the
+ *   received DIP2 is bad.  The expected range is 1-15 cycles with the
+ *   value of 0 meaning disabled.
+ *
+ * * FRMMAX
+ *   This counts the number of consecutive unexpected framing patterns (11)
+ *   states.  The expected range is 1-15 cycles with the value of 0 meaning
+ *   disabled.
+ */
+union cvmx_stxx_dip_cnt
+{
+	uint64_t u64;
+	struct cvmx_stxx_dip_cnt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t frmmax                       : 4;  /**< Number of consecutive unexpected framing patterns
+                                                         before loss of sync */
+	uint64_t dipmax                       : 4;  /**< Number of consecutive DIP2 error before loss
+                                                         of sync */
+#else
+	uint64_t dipmax                       : 4;
+	uint64_t frmmax                       : 4;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_stxx_dip_cnt_s            cn38xx;
+	struct cvmx_stxx_dip_cnt_s            cn38xxp2;
+	struct cvmx_stxx_dip_cnt_s            cn58xx;
+	struct cvmx_stxx_dip_cnt_s            cn58xxp1;
+};
+typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t;
+
+/**
+ * cvmx_stx#_ign_cal
+ *
+ * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
+ *
+ */
+union cvmx_stxx_ign_cal
+{
+	uint64_t u64;
+	struct cvmx_stxx_ign_cal_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t igntpa                       : 16; /**< Ignore Calendar Status from Spi4 Status Channel
+                                                          per Spi4 port
+                                                         - 0: Use the status channel info
+                                                         - 1: Grant the given port MAX_BURST1 credits */
+#else
+	uint64_t igntpa                       : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_stxx_ign_cal_s            cn38xx;
+	struct cvmx_stxx_ign_cal_s            cn38xxp2;
+	struct cvmx_stxx_ign_cal_s            cn58xx;
+	struct cvmx_stxx_ign_cal_s            cn58xxp1;
+};
+typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t;
+
+/**
+ * cvmx_stx#_int_msk
+ *
+ * Notes:
+ * If the bit is enabled, then the coresponding exception condition will
+ * result in an interrupt to the system.
+ */
+union cvmx_stxx_int_msk
+{
+	uint64_t u64;
+	struct cvmx_stxx_int_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+	uint64_t unxfrm                       : 1;  /**< Unexpected framing sequence */
+	uint64_t nosync                       : 1;  /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+	uint64_t diperr                       : 1;  /**< DIP2 error on the Spi4 Status channel */
+	uint64_t datovr                       : 1;  /**< Spi4 FIFO overflow error */
+	uint64_t ovrbst                       : 1;  /**< Transmit packet burst too big */
+	uint64_t calpar1                      : 1;  /**< STX Calendar Table Parity Error Bank1 */
+	uint64_t calpar0                      : 1;  /**< STX Calendar Table Parity Error Bank0 */
+#else
+	uint64_t calpar0                      : 1;
+	uint64_t calpar1                      : 1;
+	uint64_t ovrbst                       : 1;
+	uint64_t datovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t nosync                       : 1;
+	uint64_t unxfrm                       : 1;
+	uint64_t frmerr                       : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_stxx_int_msk_s            cn38xx;
+	struct cvmx_stxx_int_msk_s            cn38xxp2;
+	struct cvmx_stxx_int_msk_s            cn58xx;
+	struct cvmx_stxx_int_msk_s            cn58xxp1;
+};
+typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t;
+
+/**
+ * cvmx_stx#_int_reg
+ *
+ * Notes:
+ * * CALPAR0
+ *   This bit indicates that the Spi4 calendar table encountered a parity
+ *   error on bank0 of the calendar table memory.  This error bit is
+ *   associated with the calendar table on the TX interface - the interface
+ *   that drives the Spi databus.  The calendar table is used in Spi4 mode
+ *   when using the status channel.  Parity errors can occur during normal
+ *   operation when the calendar table is constantly being read for the port
+ *   information, or during initialization time, when the user has access.
+ *   This errors will force the the status channel to the reset state and
+ *   begin driving training sequences.  The status channel will also reset.
+ *   Software must follow the init sequence to resynch the interface.  This
+ *   includes toggling INF_EN which will cancel all outstanding accumulated
+ *   credits.
+ *
+ * * CALPAR1
+ *   Identical to CALPAR0 except that it indicates that the error occured
+ *   on bank1 (instead of bank0).
+ *
+ * * OVRBST
+ *   STX can track upto a 512KB data burst.  Any packet larger than that is
+ *   illegal and will cause confusion in the STX state machine.  BMI is
+ *   responsible for throwing away these out of control packets from the
+ *   input and the Execs should never generate them on the output.  This is
+ *   a fatal error and should have STX_INT_SYNC[OVRBST] set.
+ *
+ * * DATOVR
+ *   FIFO where the Spi4 data ramps upto its transmit frequency has
+ *   overflowed.  This is a fatal error and should have
+ *   STX_INT_SYNC[DATOVR] set.
+ *
+ * * DIPERR
+ *   This bit will fire if any DIP2 error is caught by the Spi4 status
+ *   channel.
+ *
+ * * NOSYNC
+ *   This bit indicates that the number of consecutive DIP2 errors exceeds
+ *   STX_DIP_CNT[MAXDIP] and that the interface should be taken down.  The
+ *   datapath will be notified and send continuous training sequences until
+ *   software resynchronizes the interface.  This error condition should
+ *   have STX_INT_SYNC[NOSYNC] set.
+ *
+ * * UNXFRM
+ *   Unexpected framing data was seen on the status channel.
+ *
+ * * FRMERR
+ *   This bit indicates that the number of consecutive unexpected framing
+ *   sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken
+ *   down.  The datapath will be notified and send continuous training
+ *   sequences until software resynchronizes the interface.  This error
+ *   condition should have STX_INT_SYNC[FRMERR] set.
+ *
+ * * SYNCERR
+ *   Indicates that an exception marked in STX_INT_SYNC has occured and the
+ *   TX datapath is disabled.  It is recommended that the OVRBST, DATOVR,
+ *   NOSYNC, and FRMERR error conditions all have their bits set in the
+ *   STX_INT_SYNC register.
+ */
+union cvmx_stxx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_stxx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t syncerr                      : 1;  /**< Interface encountered a fatal error */
+	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+	uint64_t unxfrm                       : 1;  /**< Unexpected framing sequence */
+	uint64_t nosync                       : 1;  /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+	uint64_t diperr                       : 1;  /**< DIP2 error on the Spi4 Status channel */
+	uint64_t datovr                       : 1;  /**< Spi4 FIFO overflow error */
+	uint64_t ovrbst                       : 1;  /**< Transmit packet burst too big */
+	uint64_t calpar1                      : 1;  /**< STX Calendar Table Parity Error Bank1 */
+	uint64_t calpar0                      : 1;  /**< STX Calendar Table Parity Error Bank0 */
+#else
+	uint64_t calpar0                      : 1;
+	uint64_t calpar1                      : 1;
+	uint64_t ovrbst                       : 1;
+	uint64_t datovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t nosync                       : 1;
+	uint64_t unxfrm                       : 1;
+	uint64_t frmerr                       : 1;
+	uint64_t syncerr                      : 1;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_stxx_int_reg_s            cn38xx;
+	struct cvmx_stxx_int_reg_s            cn38xxp2;
+	struct cvmx_stxx_int_reg_s            cn58xx;
+	struct cvmx_stxx_int_reg_s            cn58xxp1;
+};
+typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t;
+
+/**
+ * cvmx_stx#_int_sync
+ *
+ * Notes:
+ * If the bit is enabled, then the coresponding exception condition is flagged
+ * to be fatal.  In Spi4 mode, the exception condition will result in a loss
+ * of sync condition on the Spi4 interface and the datapath will send
+ * continuous traing sequences.
+ *
+ * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and
+ * FRMERR errors as synchronization events.  Software is free to
+ * synchronize the bus on other conditions, but this is the minimum
+ * recommended set.
+ */
+union cvmx_stxx_int_sync
+{
+	uint64_t u64;
+	struct cvmx_stxx_int_sync_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t frmerr                       : 1;  /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+	uint64_t unxfrm                       : 1;  /**< Unexpected framing sequence */
+	uint64_t nosync                       : 1;  /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+	uint64_t diperr                       : 1;  /**< DIP2 error on the Spi4 Status channel */
+	uint64_t datovr                       : 1;  /**< Spi4 FIFO overflow error */
+	uint64_t ovrbst                       : 1;  /**< Transmit packet burst too big */
+	uint64_t calpar1                      : 1;  /**< STX Calendar Table Parity Error Bank1 */
+	uint64_t calpar0                      : 1;  /**< STX Calendar Table Parity Error Bank0 */
+#else
+	uint64_t calpar0                      : 1;
+	uint64_t calpar1                      : 1;
+	uint64_t ovrbst                       : 1;
+	uint64_t datovr                       : 1;
+	uint64_t diperr                       : 1;
+	uint64_t nosync                       : 1;
+	uint64_t unxfrm                       : 1;
+	uint64_t frmerr                       : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_stxx_int_sync_s           cn38xx;
+	struct cvmx_stxx_int_sync_s           cn38xxp2;
+	struct cvmx_stxx_int_sync_s           cn58xx;
+	struct cvmx_stxx_int_sync_s           cn58xxp1;
+};
+typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t;
+
+/**
+ * cvmx_stx#_min_bst
+ *
+ * STX_MIN_BST - Min Burst to enforce when inserting training sequence
+ *
+ */
+union cvmx_stxx_min_bst
+{
+	uint64_t u64;
+	struct cvmx_stxx_min_bst_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_9_63                : 55;
+	uint64_t minb                         : 9;  /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
+                                                         the number of 8B blocks to send before inserting
+                                                         a training sequence.  Normally MINB will be set
+                                                         to GMX_TX_SPI_THRESH[THRESH].  MINB should always
+                                                         be set to an even number (ie. multiple of 16B) */
+#else
+	uint64_t minb                         : 9;
+	uint64_t reserved_9_63                : 55;
+#endif
+	} s;
+	struct cvmx_stxx_min_bst_s            cn38xx;
+	struct cvmx_stxx_min_bst_s            cn38xxp2;
+	struct cvmx_stxx_min_bst_s            cn58xx;
+	struct cvmx_stxx_min_bst_s            cn58xxp1;
+};
+typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t;
+
+/**
+ * cvmx_stx#_spi4_cal#
+ *
+ * specify the RSL base addresses for the block
+ * STX_SPI4_CAL - Spi4 Calender table
+ * direct_calendar_write / direct_calendar_read
+ *
+ * Notes:
+ * There are 32 calendar table CSR's, each containing 4 entries for a
+ *     total of 128 entries.  In the above definition...
+ *
+ *           n = calendar table offset * 4
+ *
+ *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
+ *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
+ *        and would contain entries (16*4) = 64, 65, 66, and 67.
+ *
+ * Restrictions:
+ *        Calendar table entry accesses (read or write) can only occur
+ *        if the interface is disabled.  All other accesses will be
+ *        unpredictable.
+ *
+ *     Both the calendar table and the LEN and M parameters must be
+ *     completely setup before writing the Interface enable (INF_EN) and
+ *     Status channel enabled (ST_EN) asserted.
+ */
+union cvmx_stxx_spi4_calx
+{
+	uint64_t u64;
+	struct cvmx_stxx_spi4_calx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t oddpar                       : 1;  /**< Odd parity over STX_SPI4_CAL[15:0]
+                                                         (^STX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
+	uint64_t prt3                         : 4;  /**< Status for port n+3 */
+	uint64_t prt2                         : 4;  /**< Status for port n+2 */
+	uint64_t prt1                         : 4;  /**< Status for port n+1 */
+	uint64_t prt0                         : 4;  /**< Status for port n+0 */
+#else
+	uint64_t prt0                         : 4;
+	uint64_t prt1                         : 4;
+	uint64_t prt2                         : 4;
+	uint64_t prt3                         : 4;
+	uint64_t oddpar                       : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_stxx_spi4_calx_s          cn38xx;
+	struct cvmx_stxx_spi4_calx_s          cn38xxp2;
+	struct cvmx_stxx_spi4_calx_s          cn58xx;
+	struct cvmx_stxx_spi4_calx_s          cn58xxp1;
+};
+typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t;
+
+/**
+ * cvmx_stx#_spi4_dat
+ *
+ * STX_SPI4_DAT - Spi4 datapath channel control register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * * DATA_MAX_T must be in MOD 4 cycles
+ *
+ * * DATA_MAX_T must at least 0x20
+ *
+ * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce
+ *
+ * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall
+ *   waiting for min bursts to complete.  In the worst case, this will
+ *   add the entire min burst transmission time to the interval between
+ *   trainging sequence.  The observed MAX_T on the Spi4 bus will be...
+ *
+ *                STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4)
+ *
+ *      If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
+ *      parameter will have to be adjusted.  Please see the
+ *      STX_SPI4_DAT[MAX_T] section for additional information.  In
+ *      addition, the min_burst can only be guaranteed on the initial data
+ *      burst of a given packet (i.e. the first data burst which contains
+ *      the SOP tick).  All subsequent bursts could be truncated by training
+ *      sequences at any point during transmission and could be arbitrarily
+ *      small.  This mode is only for use in Spi4 mode.
+ */
+union cvmx_stxx_spi4_dat
+{
+	uint64_t u64;
+	struct cvmx_stxx_spi4_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t alpha                        : 16; /**< alpha (from spi4.2 spec) */
+	uint64_t max_t                        : 16; /**< DATA_MAX_T (from spi4.2 spec) */
+#else
+	uint64_t max_t                        : 16;
+	uint64_t alpha                        : 16;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_stxx_spi4_dat_s           cn38xx;
+	struct cvmx_stxx_spi4_dat_s           cn38xxp2;
+	struct cvmx_stxx_spi4_dat_s           cn58xx;
+	struct cvmx_stxx_spi4_dat_s           cn58xxp1;
+};
+typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t;
+
+/**
+ * cvmx_stx#_spi4_stat
+ *
+ * STX_SPI4_STAT - Spi4 status channel control register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be
+ * completely setup before writing the Interface enable (INF_EN) and
+ * Status channel enabled (ST_EN) asserted.
+ *
+ * The calendar table will only be enabled when LEN > 0.
+ *
+ * Current rev will only support LVTTL status IO.
+ */
+union cvmx_stxx_spi4_stat
+{
+	uint64_t u64;
+	struct cvmx_stxx_spi4_stat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t m                            : 8;  /**< CALENDAR_M (from spi4.2 spec) */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t len                          : 7;  /**< CALENDAR_LEN (from spi4.2 spec) */
+#else
+	uint64_t len                          : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t m                            : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_stxx_spi4_stat_s          cn38xx;
+	struct cvmx_stxx_spi4_stat_s          cn38xxp2;
+	struct cvmx_stxx_spi4_stat_s          cn58xx;
+	struct cvmx_stxx_spi4_stat_s          cn58xxp1;
+};
+typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t;
+
+/**
+ * cvmx_stx#_stat_bytes_hi
+ */
+union cvmx_stxx_stat_bytes_hi
+{
+	uint64_t u64;
+	struct cvmx_stxx_stat_bytes_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Number of bytes sent (CNT[63:32]) */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_stxx_stat_bytes_hi_s      cn38xx;
+	struct cvmx_stxx_stat_bytes_hi_s      cn38xxp2;
+	struct cvmx_stxx_stat_bytes_hi_s      cn58xx;
+	struct cvmx_stxx_stat_bytes_hi_s      cn58xxp1;
+};
+typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t;
+
+/**
+ * cvmx_stx#_stat_bytes_lo
+ */
+union cvmx_stxx_stat_bytes_lo
+{
+	uint64_t u64;
+	struct cvmx_stxx_stat_bytes_lo_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Number of bytes sent (CNT[31:0]) */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_stxx_stat_bytes_lo_s      cn38xx;
+	struct cvmx_stxx_stat_bytes_lo_s      cn38xxp2;
+	struct cvmx_stxx_stat_bytes_lo_s      cn58xx;
+	struct cvmx_stxx_stat_bytes_lo_s      cn58xxp1;
+};
+typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t;
+
+/**
+ * cvmx_stx#_stat_ctl
+ */
+union cvmx_stxx_stat_ctl
+{
+	uint64_t u64;
+	struct cvmx_stxx_stat_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t clr                          : 1;  /**< Clear all statistics counters
+                                                         - STX_STAT_PKT_XMT
+                                                         - STX_STAT_BYTES_HI
+                                                         - STX_STAT_BYTES_LO */
+	uint64_t bckprs                       : 4;  /**< The selected port for STX_BCKPRS_CNT */
+#else
+	uint64_t bckprs                       : 4;
+	uint64_t clr                          : 1;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_stxx_stat_ctl_s           cn38xx;
+	struct cvmx_stxx_stat_ctl_s           cn38xxp2;
+	struct cvmx_stxx_stat_ctl_s           cn58xx;
+	struct cvmx_stxx_stat_ctl_s           cn58xxp1;
+};
+typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t;
+
+/**
+ * cvmx_stx#_stat_pkt_xmt
+ */
+union cvmx_stxx_stat_pkt_xmt
+{
+	uint64_t u64;
+	struct cvmx_stxx_stat_pkt_xmt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t cnt                          : 32; /**< Number of packets sent */
+#else
+	uint64_t cnt                          : 32;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_stxx_stat_pkt_xmt_s       cn38xx;
+	struct cvmx_stxx_stat_pkt_xmt_s       cn38xxp2;
+	struct cvmx_stxx_stat_pkt_xmt_s       cn58xx;
+	struct cvmx_stxx_stat_pkt_xmt_s       cn58xxp1;
+};
+typedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-swap.h b/sys/contrib/octeon-sdk/cvmx-swap.h
index 2678fd6..38cbaab 100644
--- a/sys/contrib/octeon-sdk/cvmx-swap.h
+++ b/sys/contrib/octeon-sdk/cvmx-swap.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 /**
  * @file
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-sysinfo.c b/sys/contrib/octeon-sdk/cvmx-sysinfo.c
index 8146ded..1522c69 100644
--- a/sys/contrib/octeon-sdk/cvmx-sysinfo.c
+++ b/sys/contrib/octeon-sdk/cvmx-sysinfo.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,18 +42,27 @@
 
 
 
+
 /**
  * @file
  *
  * This module provides system/board/application information obtained by the bootloader.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-spinlock.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+#else
 #include "cvmx.h"
 #include "cvmx-spinlock.h"
 #include "cvmx-sysinfo.h"
+#endif
 
 
 /**
@@ -75,7 +85,7 @@ static struct {
 #else
 CVMX_SHARED static struct {
 
-    cvmx_sysinfo_t   sysinfo;      /**< system information */
+    struct cvmx_sysinfo   sysinfo;      /**< system information */
     cvmx_spinlock_t  lock;         /**< mutex spinlock */
 
 } state = {
@@ -103,10 +113,13 @@ uint64_t linux_mem32_offset = 0;
  * @return  Pointer to the boot information structure
  *
  */
-cvmx_sysinfo_t * cvmx_sysinfo_get(void)
+struct cvmx_sysinfo *cvmx_sysinfo_get(void)
 {
     return &(state.sysinfo);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_sysinfo_get);
+#endif
 
 
 /**
@@ -117,8 +130,9 @@ cvmx_sysinfo_t * cvmx_sysinfo_get(void)
  * Locking (if required) must be handled outside of this
  * function
  *
- * @param phy_mem_desc_ptr
- *                   Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param phy_mem_desc_addr
+ *                   Address of the global physical memory descriptor (bootmem
+ *                   descriptor)
  * @param board_type Octeon board type enumeration
  *
  * @param board_rev_major
@@ -131,13 +145,13 @@ cvmx_sysinfo_t * cvmx_sysinfo_get(void)
  * @return 0: Failure
  *         1: success
  */
-int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, uint8_t board_rev_major,
+int cvmx_sysinfo_minimal_initialize(uint64_t phy_mem_desc_addr, uint16_t board_type, uint8_t board_rev_major,
                                     uint8_t board_rev_minor, uint32_t cpu_clock_hz)
 {
 
 
     memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo));
-    state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr;
+    state.sysinfo.phy_mem_desc_addr = phy_mem_desc_addr;
     state.sysinfo.board_type = board_type;
     state.sysinfo.board_rev_major = board_rev_major;
     state.sysinfo.board_rev_minor = board_rev_minor;
@@ -183,7 +197,7 @@ void cvmx_sysinfo_linux_userspace_initialize(void)
             if (strcmp(field, "dram_size:") == 0)
                 system_info->system_dram_size = value;
             else if (strcmp(field, "phy_mem_desc_addr:") == 0)
-                system_info->phy_mem_desc_ptr = cvmx_phys_to_ptr(value);
+                system_info->phy_mem_desc_addr = value;
             else if (strcmp(field, "eclock_hz:") == 0)
                 system_info->cpu_clock_hz = value;
             else if (strcmp(field, "dclock_hz:") == 0)
@@ -216,5 +230,7 @@ void cvmx_sysinfo_linux_userspace_initialize(void)
                 linux_mem32_wired = value;
         }
     }
+
+    system_info->cpu_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_CORE);
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-sysinfo.h b/sys/contrib/octeon-sdk/cvmx-sysinfo.h
index 199a48b..0daa9cf 100644
--- a/sys/contrib/octeon-sdk/cvmx-sysinfo.h
+++ b/sys/contrib/octeon-sdk/cvmx-sysinfo.h
@@ -1,52 +1,49 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
  * This module provides system/board information obtained by the bootloader.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -54,7 +51,9 @@
 #ifndef __CVMX_SYSINFO_H__
 #define __CVMX_SYSINFO_H__
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-app-init.h"
+#endif
 
 #ifdef	__cplusplus
 extern "C" {
@@ -64,55 +63,63 @@ extern "C" {
 /**
  * Structure describing application specific information.
  * __cvmx_app_init() populates this from the cvmx boot descriptor.
- * This structure is private to simple executive applications, so
- * no versioning is required.
- *
- * This structure must be provided with some fields set in order to use
- * simple executive functions in other applications (Linux kernel, u-boot, etc.)
- * The cvmx_sysinfo_minimal_initialize() function is provided to set the required values
- * in these cases.
+ * This structure is private to simple executive applications, so no
+ * versioning is required.
  *
+ * This structure must be provided with some fields set in order to
+ * use simple executive functions in other applications (Linux kernel,
+ * u-boot, etc.)  The cvmx_sysinfo_minimal_initialize() function is
+ * provided to set the required values in these cases.
  *
  */
-typedef struct {
-    /* System wide variables */
-    uint64_t system_dram_size;  /**< installed DRAM in system, in bytes */
-    void *phy_mem_desc_ptr;  /**< ptr to memory descriptor block */
-
-    /* Application image specific variables */
-    uint64_t stack_top;  /**< stack top address (virtual) */
-    uint64_t heap_base;  /**< heap base address (virtual) */
-    uint32_t stack_size; /**< stack size in bytes */
-    uint32_t heap_size;  /**< heap size in bytes */
-    uint32_t core_mask;  /**< coremask defining cores running application */
-    uint32_t init_core;  /**< Deprecated, use cvmx_coremask_first_core() to select init core */
-    uint64_t exception_base_addr;  /**< exception base address, as set by bootloader */
-    uint32_t cpu_clock_hz;     /**< cpu clock speed in hz */
-    uint32_t dram_data_rate_hz;  /**< dram data rate in hz (data rate = 2 * clock rate */
-
-    uint16_t board_type;
-    uint8_t  board_rev_major;
-    uint8_t  board_rev_minor;
-    uint8_t  mac_addr_base[6];
-    uint8_t  mac_addr_count;
-    char     board_serial_number[OCTEON_SERIAL_LEN];
-    /* Several boards support compact flash on the Octeon boot bus.  The CF
-    ** memory spaces may be mapped to different addresses on different boards.
-    ** These values will be 0 if CF is not present.
-    ** Note that these addresses are physical addresses, and it is up to the application
-    ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
-    uint64_t compact_flash_common_base_addr;
-    uint64_t compact_flash_attribute_base_addr;
-    /* Base address of the LED display (as on EBT3000 board)
-    ** This will be 0 if LED display not present.
-    ** Note that this address is a physical address, and it is up to the application
-    ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
-    uint64_t led_display_base_addr;
-    uint32_t dfa_ref_clock_hz;  /**< DFA reference clock in hz (if applicable)*/
-    uint32_t bootloader_config_flags;  /**< configuration flags from bootloader */
-    uint8_t  console_uart_num;         /** < Uart number used for console */
-} cvmx_sysinfo_t;
-
+struct cvmx_sysinfo {
+	/* System wide variables */
+	uint64_t system_dram_size;  /**< installed DRAM in system, in bytes */
+	uint64_t phy_mem_desc_addr;  /**< Address of the memory descriptor block */
+
+	/* Application image specific variables */
+	uint64_t stack_top;  /**< stack top address (virtual) */
+	uint64_t heap_base;  /**< heap base address (virtual) */
+	uint32_t stack_size; /**< stack size in bytes */
+	uint32_t heap_size;  /**< heap size in bytes */
+	uint32_t core_mask;  /**< coremask defining cores running application */
+	uint32_t init_core;  /**< Deprecated, use cvmx_coremask_first_core() to select init core */
+	uint64_t exception_base_addr;  /**< exception base address, as set by bootloader */
+	uint32_t cpu_clock_hz;     /**< cpu clock speed in hz */
+	uint32_t dram_data_rate_hz;  /**< dram data rate in hz (data rate = 2 * clock rate */
+
+	uint16_t board_type;
+	uint8_t  board_rev_major;
+	uint8_t  board_rev_minor;
+	uint8_t  mac_addr_base[6];
+	uint8_t  mac_addr_count;
+	char     board_serial_number[OCTEON_SERIAL_LEN];
+	/*
+	 * Several boards support compact flash on the Octeon boot
+	 * bus.  The CF memory spaces may be mapped to different
+	 * addresses on different boards.  These values will be 0 if
+	 * CF is not present.  Note that these addresses are physical
+	 * addresses, and it is up to the application to use the
+	 * proper addressing mode (XKPHYS, KSEG0, etc.)
+	 */
+	uint64_t compact_flash_common_base_addr;
+	uint64_t compact_flash_attribute_base_addr;
+	/*
+	 * Base address of the LED display (as on EBT3000 board) This
+	 * will be 0 if LED display not present.  Note that this
+	 * address is a physical address, and it is up to the
+	 * application to use the proper addressing mode (XKPHYS,
+	 * KSEG0, etc.)
+	 */
+	uint64_t led_display_base_addr;
+	uint32_t dfa_ref_clock_hz;  /**< DFA reference clock in hz (if applicable)*/
+	uint32_t bootloader_config_flags;  /**< configuration flags from bootloader */
+	uint8_t  console_uart_num;         /** < Uart number used for console */
+};
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+typedef struct cvmx_sysinfo cvmx_sysinfo_t;
+#endif
 
 /**
  * This function returns the system/board information as obtained
@@ -123,9 +130,9 @@ typedef struct {
  *
  */
 
-extern cvmx_sysinfo_t * cvmx_sysinfo_get(void);
-
+extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 /**
  * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
  * to configure the minimal fields that are required to use
@@ -134,8 +141,9 @@ extern cvmx_sysinfo_t * cvmx_sysinfo_get(void);
  * Locking (if required) must be handled outside of this
  * function
  *
- * @param phy_mem_desc_ptr
- *                   Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param phy_mem_desc_addr
+ *                   Address of the global physical memory descriptor (bootmem
+ *                   descriptor)
  * @param board_type Octeon board type enumeration
  *
  * @param board_rev_major
@@ -148,8 +156,9 @@ extern cvmx_sysinfo_t * cvmx_sysinfo_get(void);
  * @return 0: Failure
  *         1: success
  */
-extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, uint8_t board_rev_major,
+extern int cvmx_sysinfo_minimal_initialize(uint64_t phy_mem_desc_addr, uint16_t board_type, uint8_t board_rev_major,
                                     uint8_t board_rev_minor, uint32_t cpu_clock_hz);
+#endif
 
 #ifdef CVMX_BUILD_FOR_LINUX_USER
 /**
diff --git a/sys/contrib/octeon-sdk/cvmx-thunder.c b/sys/contrib/octeon-sdk/cvmx-thunder.c
index 8b81a29..8032c18 100644
--- a/sys/contrib/octeon-sdk/cvmx-thunder.c
+++ b/sys/contrib/octeon-sdk/cvmx-thunder.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the Thunder specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-thunder.h b/sys/contrib/octeon-sdk/cvmx-thunder.h
index 662dcfa..3b63563 100644
--- a/sys/contrib/octeon-sdk/cvmx-thunder.h
+++ b/sys/contrib/octeon-sdk/cvmx-thunder.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,6 +42,7 @@
 
 
 
+
 #ifndef __CVMX_THUNDER_H__
 #define __CVMX_THUNDER_H__
 
@@ -49,7 +51,7 @@
  *
  * Interface to the Thunder specific devices
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
diff --git a/sys/contrib/octeon-sdk/cvmx-tim-defs.h b/sys/contrib/octeon-sdk/cvmx-tim-defs.h
new file mode 100644
index 0000000..90d684f
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-tim-defs.h
@@ -0,0 +1,510 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-tim-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon tim.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_TIM_TYPEDEFS_H__
+#define __CVMX_TIM_TYPEDEFS_H__
+
+#define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull))
+#define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull))
+#define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull))
+#define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull))
+#define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull))
+#define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull))
+#define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull))
+#define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull))
+#define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull))
+#define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull))
+
+/**
+ * cvmx_tim_mem_debug0
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.ctl[47:0]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_tim_mem_debug0
+{
+	uint64_t u64;
+	struct cvmx_tim_mem_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t ena                          : 1;  /**< Ring timer enable */
+	uint64_t reserved_46_46               : 1;
+	uint64_t count                        : 22; /**< Time offset for the ring
+                                                         Set to INTERVAL and counts down by 1 every 1024
+                                                         cycles when ENA==1. The HW forces a bucket
+                                                         traversal (and resets COUNT to INTERVAL) whenever
+                                                         the decrement would cause COUNT to go negative.
+                                                         COUNT is unpredictable whenever ENA==0.
+                                                         COUNT is reset to INTERVAL whenever TIM_MEM_RING1
+                                                         is written for the ring. */
+	uint64_t reserved_22_23               : 2;
+	uint64_t interval                     : 22; /**< Timer interval - 1 */
+#else
+	uint64_t interval                     : 22;
+	uint64_t reserved_22_23               : 2;
+	uint64_t count                        : 22;
+	uint64_t reserved_46_46               : 1;
+	uint64_t ena                          : 1;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_tim_mem_debug0_s          cn30xx;
+	struct cvmx_tim_mem_debug0_s          cn31xx;
+	struct cvmx_tim_mem_debug0_s          cn38xx;
+	struct cvmx_tim_mem_debug0_s          cn38xxp2;
+	struct cvmx_tim_mem_debug0_s          cn50xx;
+	struct cvmx_tim_mem_debug0_s          cn52xx;
+	struct cvmx_tim_mem_debug0_s          cn52xxp1;
+	struct cvmx_tim_mem_debug0_s          cn56xx;
+	struct cvmx_tim_mem_debug0_s          cn56xxp1;
+	struct cvmx_tim_mem_debug0_s          cn58xx;
+	struct cvmx_tim_mem_debug0_s          cn58xxp1;
+	struct cvmx_tim_mem_debug0_s          cn63xx;
+	struct cvmx_tim_mem_debug0_s          cn63xxp1;
+};
+typedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t;
+
+/**
+ * cvmx_tim_mem_debug1
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.sta[63:0]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_tim_mem_debug1
+{
+	uint64_t u64;
+	struct cvmx_tim_mem_debug1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t bucket                       : 13; /**< Current bucket[12:0]
+                                                         Reset to 0 whenever TIM_MEM_RING0 is written for
+                                                         the ring. Incremented (modulo BSIZE) once per
+                                                         bucket traversal.
+                                                         See TIM_MEM_DEBUG2[BUCKET]. */
+	uint64_t base                         : 31; /**< Pointer[35:5] to bucket[0] */
+	uint64_t bsize                        : 20; /**< Number of buckets - 1 */
+#else
+	uint64_t bsize                        : 20;
+	uint64_t base                         : 31;
+	uint64_t bucket                       : 13;
+#endif
+	} s;
+	struct cvmx_tim_mem_debug1_s          cn30xx;
+	struct cvmx_tim_mem_debug1_s          cn31xx;
+	struct cvmx_tim_mem_debug1_s          cn38xx;
+	struct cvmx_tim_mem_debug1_s          cn38xxp2;
+	struct cvmx_tim_mem_debug1_s          cn50xx;
+	struct cvmx_tim_mem_debug1_s          cn52xx;
+	struct cvmx_tim_mem_debug1_s          cn52xxp1;
+	struct cvmx_tim_mem_debug1_s          cn56xx;
+	struct cvmx_tim_mem_debug1_s          cn56xxp1;
+	struct cvmx_tim_mem_debug1_s          cn58xx;
+	struct cvmx_tim_mem_debug1_s          cn58xxp1;
+	struct cvmx_tim_mem_debug1_s          cn63xx;
+	struct cvmx_tim_mem_debug1_s          cn63xxp1;
+};
+typedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t;
+
+/**
+ * cvmx_tim_mem_debug2
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.sta[95:64]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_tim_mem_debug2
+{
+	uint64_t u64;
+	struct cvmx_tim_mem_debug2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_24_63               : 40;
+	uint64_t cpool                        : 3;  /**< Free list used to free chunks */
+	uint64_t csize                        : 13; /**< Number of words per chunk */
+	uint64_t reserved_7_7                 : 1;
+	uint64_t bucket                       : 7;  /**< Current bucket[19:13]
+                                                         See TIM_MEM_DEBUG1[BUCKET]. */
+#else
+	uint64_t bucket                       : 7;
+	uint64_t reserved_7_7                 : 1;
+	uint64_t csize                        : 13;
+	uint64_t cpool                        : 3;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_tim_mem_debug2_s          cn30xx;
+	struct cvmx_tim_mem_debug2_s          cn31xx;
+	struct cvmx_tim_mem_debug2_s          cn38xx;
+	struct cvmx_tim_mem_debug2_s          cn38xxp2;
+	struct cvmx_tim_mem_debug2_s          cn50xx;
+	struct cvmx_tim_mem_debug2_s          cn52xx;
+	struct cvmx_tim_mem_debug2_s          cn52xxp1;
+	struct cvmx_tim_mem_debug2_s          cn56xx;
+	struct cvmx_tim_mem_debug2_s          cn56xxp1;
+	struct cvmx_tim_mem_debug2_s          cn58xx;
+	struct cvmx_tim_mem_debug2_s          cn58xxp1;
+	struct cvmx_tim_mem_debug2_s          cn63xx;
+	struct cvmx_tim_mem_debug2_s          cn63xxp1;
+};
+typedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t;
+
+/**
+ * cvmx_tim_mem_ring0
+ *
+ * Notes:
+ * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring.
+ * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is
+ * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].)
+ * BASE is a 32-byte aligned pointer[35:0].  Only pointer[35:5] are stored because pointer[4:0] = 0.
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_tim_mem_ring0
+{
+	uint64_t u64;
+	struct cvmx_tim_mem_ring0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_55_63               : 9;
+	uint64_t first_bucket                 : 31; /**< Pointer[35:5] to bucket[0] */
+	uint64_t num_buckets                  : 20; /**< Number of buckets - 1 */
+	uint64_t ring                         : 4;  /**< Ring ID */
+#else
+	uint64_t ring                         : 4;
+	uint64_t num_buckets                  : 20;
+	uint64_t first_bucket                 : 31;
+	uint64_t reserved_55_63               : 9;
+#endif
+	} s;
+	struct cvmx_tim_mem_ring0_s           cn30xx;
+	struct cvmx_tim_mem_ring0_s           cn31xx;
+	struct cvmx_tim_mem_ring0_s           cn38xx;
+	struct cvmx_tim_mem_ring0_s           cn38xxp2;
+	struct cvmx_tim_mem_ring0_s           cn50xx;
+	struct cvmx_tim_mem_ring0_s           cn52xx;
+	struct cvmx_tim_mem_ring0_s           cn52xxp1;
+	struct cvmx_tim_mem_ring0_s           cn56xx;
+	struct cvmx_tim_mem_ring0_s           cn56xxp1;
+	struct cvmx_tim_mem_ring0_s           cn58xx;
+	struct cvmx_tim_mem_ring0_s           cn58xxp1;
+	struct cvmx_tim_mem_ring0_s           cn63xx;
+	struct cvmx_tim_mem_ring0_s           cn63xxp1;
+};
+typedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t;
+
+/**
+ * cvmx_tim_mem_ring1
+ *
+ * Notes:
+ * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring
+ * if it was pending or active prior to the transition. (SW must delay to ensure the completion
+ * of the traversal before reprogramming the ring.)
+ * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value.
+ * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].)
+ * CSIZE must be at least 16.  It is illegal to program CSIZE to a value that is less than 16.
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+union cvmx_tim_mem_ring1
+{
+	uint64_t u64;
+	struct cvmx_tim_mem_ring1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_43_63               : 21;
+	uint64_t enable                       : 1;  /**< Ring timer enable
+                                                         When clear, the ring is disabled and TIM
+                                                         will not traverse any new buckets for the ring. */
+	uint64_t pool                         : 3;  /**< Free list used to free chunks */
+	uint64_t words_per_chunk              : 13; /**< Number of words per chunk */
+	uint64_t interval                     : 22; /**< Timer interval - 1, measured in 1024 cycle ticks */
+	uint64_t ring                         : 4;  /**< Ring ID */
+#else
+	uint64_t ring                         : 4;
+	uint64_t interval                     : 22;
+	uint64_t words_per_chunk              : 13;
+	uint64_t pool                         : 3;
+	uint64_t enable                       : 1;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_tim_mem_ring1_s           cn30xx;
+	struct cvmx_tim_mem_ring1_s           cn31xx;
+	struct cvmx_tim_mem_ring1_s           cn38xx;
+	struct cvmx_tim_mem_ring1_s           cn38xxp2;
+	struct cvmx_tim_mem_ring1_s           cn50xx;
+	struct cvmx_tim_mem_ring1_s           cn52xx;
+	struct cvmx_tim_mem_ring1_s           cn52xxp1;
+	struct cvmx_tim_mem_ring1_s           cn56xx;
+	struct cvmx_tim_mem_ring1_s           cn56xxp1;
+	struct cvmx_tim_mem_ring1_s           cn58xx;
+	struct cvmx_tim_mem_ring1_s           cn58xxp1;
+	struct cvmx_tim_mem_ring1_s           cn63xx;
+	struct cvmx_tim_mem_ring1_s           cn63xxp1;
+};
+typedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t;
+
+/**
+ * cvmx_tim_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_tim_reg_bist_result
+{
+	uint64_t u64;
+	struct cvmx_tim_reg_bist_result_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t sta                          : 2;  /**< BiST result of the STA   memories (0=pass, !0=fail) */
+	uint64_t ncb                          : 1;  /**< BiST result of the NCB   memories (0=pass, !0=fail) */
+	uint64_t ctl                          : 1;  /**< BiST result of the CTL   memories (0=pass, !0=fail) */
+#else
+	uint64_t ctl                          : 1;
+	uint64_t ncb                          : 1;
+	uint64_t sta                          : 2;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_tim_reg_bist_result_s     cn30xx;
+	struct cvmx_tim_reg_bist_result_s     cn31xx;
+	struct cvmx_tim_reg_bist_result_s     cn38xx;
+	struct cvmx_tim_reg_bist_result_s     cn38xxp2;
+	struct cvmx_tim_reg_bist_result_s     cn50xx;
+	struct cvmx_tim_reg_bist_result_s     cn52xx;
+	struct cvmx_tim_reg_bist_result_s     cn52xxp1;
+	struct cvmx_tim_reg_bist_result_s     cn56xx;
+	struct cvmx_tim_reg_bist_result_s     cn56xxp1;
+	struct cvmx_tim_reg_bist_result_s     cn58xx;
+	struct cvmx_tim_reg_bist_result_s     cn58xxp1;
+	struct cvmx_tim_reg_bist_result_s     cn63xx;
+	struct cvmx_tim_reg_bist_result_s     cn63xxp1;
+};
+typedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t;
+
+/**
+ * cvmx_tim_reg_error
+ *
+ * Notes:
+ * A ring is in error if its interval has elapsed more than once without having been serviced.
+ * During a CSR write to this register, the write data is used as a mask to clear the selected mask
+ * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]).
+ */
+union cvmx_tim_reg_error
+{
+	uint64_t u64;
+	struct cvmx_tim_reg_error_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Bit mask indicating the rings in error */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_tim_reg_error_s           cn30xx;
+	struct cvmx_tim_reg_error_s           cn31xx;
+	struct cvmx_tim_reg_error_s           cn38xx;
+	struct cvmx_tim_reg_error_s           cn38xxp2;
+	struct cvmx_tim_reg_error_s           cn50xx;
+	struct cvmx_tim_reg_error_s           cn52xx;
+	struct cvmx_tim_reg_error_s           cn52xxp1;
+	struct cvmx_tim_reg_error_s           cn56xx;
+	struct cvmx_tim_reg_error_s           cn56xxp1;
+	struct cvmx_tim_reg_error_s           cn58xx;
+	struct cvmx_tim_reg_error_s           cn58xxp1;
+	struct cvmx_tim_reg_error_s           cn63xx;
+	struct cvmx_tim_reg_error_s           cn63xxp1;
+};
+typedef union cvmx_tim_reg_error cvmx_tim_reg_error_t;
+
+/**
+ * cvmx_tim_reg_flags
+ *
+ * Notes:
+ * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all
+ * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.)
+ * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there
+ * are no more new bucket traversals (for any ring).
+ *
+ * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may
+ * have been previous ones. If there are ring bucket traversals that were already pending but
+ * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet)
+ * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until
+ * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete
+ * after the 1->0 ENA_TIM transition, though.
+ */
+union cvmx_tim_reg_flags
+{
+	uint64_t u64;
+	struct cvmx_tim_reg_flags_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for free-running structures */
+	uint64_t enable_dwb                   : 1;  /**< Enables non-zero DonwWriteBacks when set
+                                                         When set, enables the use of
+                                                         DontWriteBacks during the buffer freeing
+                                                         operations. */
+	uint64_t enable_timers                : 1;  /**< Enables the TIM section when set
+                                                         When set, TIM is in normal operation.
+                                                         When clear, time is effectively stopped for all
+                                                         rings in TIM. */
+#else
+	uint64_t enable_timers                : 1;
+	uint64_t enable_dwb                   : 1;
+	uint64_t reset                        : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_tim_reg_flags_s           cn30xx;
+	struct cvmx_tim_reg_flags_s           cn31xx;
+	struct cvmx_tim_reg_flags_s           cn38xx;
+	struct cvmx_tim_reg_flags_s           cn38xxp2;
+	struct cvmx_tim_reg_flags_s           cn50xx;
+	struct cvmx_tim_reg_flags_s           cn52xx;
+	struct cvmx_tim_reg_flags_s           cn52xxp1;
+	struct cvmx_tim_reg_flags_s           cn56xx;
+	struct cvmx_tim_reg_flags_s           cn56xxp1;
+	struct cvmx_tim_reg_flags_s           cn58xx;
+	struct cvmx_tim_reg_flags_s           cn58xxp1;
+	struct cvmx_tim_reg_flags_s           cn63xx;
+	struct cvmx_tim_reg_flags_s           cn63xxp1;
+};
+typedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t;
+
+/**
+ * cvmx_tim_reg_int_mask
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ * When mask bit is set, the interrupt is enabled.
+ */
+union cvmx_tim_reg_int_mask
+{
+	uint64_t u64;
+	struct cvmx_tim_reg_int_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t mask                         : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */
+#else
+	uint64_t mask                         : 16;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_tim_reg_int_mask_s        cn30xx;
+	struct cvmx_tim_reg_int_mask_s        cn31xx;
+	struct cvmx_tim_reg_int_mask_s        cn38xx;
+	struct cvmx_tim_reg_int_mask_s        cn38xxp2;
+	struct cvmx_tim_reg_int_mask_s        cn50xx;
+	struct cvmx_tim_reg_int_mask_s        cn52xx;
+	struct cvmx_tim_reg_int_mask_s        cn52xxp1;
+	struct cvmx_tim_reg_int_mask_s        cn56xx;
+	struct cvmx_tim_reg_int_mask_s        cn56xxp1;
+	struct cvmx_tim_reg_int_mask_s        cn58xx;
+	struct cvmx_tim_reg_int_mask_s        cn58xxp1;
+	struct cvmx_tim_reg_int_mask_s        cn63xx;
+	struct cvmx_tim_reg_int_mask_s        cn63xxp1;
+};
+typedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t;
+
+/**
+ * cvmx_tim_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "TIM_MEM_".
+ * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+union cvmx_tim_reg_read_idx
+{
+	uint64_t u64;
+	struct cvmx_tim_reg_read_idx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
+	uint64_t index                        : 8;  /**< Index to use for next memory CSR read */
+#else
+	uint64_t index                        : 8;
+	uint64_t inc                          : 8;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} s;
+	struct cvmx_tim_reg_read_idx_s        cn30xx;
+	struct cvmx_tim_reg_read_idx_s        cn31xx;
+	struct cvmx_tim_reg_read_idx_s        cn38xx;
+	struct cvmx_tim_reg_read_idx_s        cn38xxp2;
+	struct cvmx_tim_reg_read_idx_s        cn50xx;
+	struct cvmx_tim_reg_read_idx_s        cn52xx;
+	struct cvmx_tim_reg_read_idx_s        cn52xxp1;
+	struct cvmx_tim_reg_read_idx_s        cn56xx;
+	struct cvmx_tim_reg_read_idx_s        cn56xxp1;
+	struct cvmx_tim_reg_read_idx_s        cn58xx;
+	struct cvmx_tim_reg_read_idx_s        cn58xxp1;
+	struct cvmx_tim_reg_read_idx_s        cn63xx;
+	struct cvmx_tim_reg_read_idx_s        cn63xxp1;
+};
+typedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tim.c b/sys/contrib/octeon-sdk/cvmx-tim.c
index 57e9c75..1c88b64 100644
--- a/sys/contrib/octeon-sdk/cvmx-tim.c
+++ b/sys/contrib/octeon-sdk/cvmx-tim.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Support library for the hardware work queue timers.
  *
- * <hr>$Revision: 42180 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 #include "executive-config.h"
 #include "cvmx-config.h"
@@ -55,7 +57,7 @@
 #include "cvmx-tim.h"
 #include "cvmx-bootmem.h"
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-tim-defs.h */
 
 /**
  * Global structure holding the state of all timers.
@@ -84,12 +86,7 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     cvmx_tim_mem_ring1_t    config_ring1;
     uint64_t                timer_id;
     int                     error = -1;
-#if !(defined(__KERNEL__) && defined(linux))
-    cvmx_sysinfo_t         *sys_info_ptr = cvmx_sysinfo_get();
-    uint64_t                cpu_clock_hz = sys_info_ptr->cpu_clock_hz;
-#else
-    uint64_t                cpu_clock_hz = octeon_get_clock_rate();
-#endif
+    uint64_t                tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM);
     uint64_t                hw_tick_ns;
     uint64_t                hw_tick_ns_allowed;
     uint64_t                tick_ns = 1000 * tick;
@@ -97,30 +94,30 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     uint32_t                temp;
 
     /* for the simulator */
-    if (cpu_clock_hz == 0)
-      cpu_clock_hz = 333000000;
+    if (tim_clock_hz == 0)
+      tim_clock_hz = 333000000;
 
-    hw_tick_ns = 1024 * 1000000000ull / cpu_clock_hz;
-    /* 
-     * Doulbe the minmal allowed tick to 2* HW tick.  tick between
-     * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval 
+    hw_tick_ns = 1024 * 1000000000ull / tim_clock_hz;
+    /*
+     * Double the minimal allowed tick to 2 * HW tick.  tick between
+     * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
      * to zero, or 1024 cycles. This is not enough time for the timer unit
-     * to fetch the bucket data, Resulting in timer ring error interrupt 
-     * be always generated. Avoid such setting in software 
+     * to fetch the bucket data, Resulting in timer ring error interrupt
+     * be always generated. Avoid such setting in software.
      */
-    hw_tick_ns_allowed = hw_tick_ns *2;
+    hw_tick_ns_allowed = hw_tick_ns * 2;
 
     /* Make sure the timers are stopped */
     cvmx_tim_stop();
 
     /* Reinitialize out timer state */
     memset(&cvmx_tim, 0, sizeof(cvmx_tim));
-    
+
 
     if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns))
       {
-	cvmx_dprintf("init: tick wrong size. Requested tick %lu(ns) is smaller than" 
-		     " the minimal ticks allowed by hardware %lu(ns)\n", 
+	cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
+		     " the minimal ticks allowed by hardware %lu(ns)\n",
 		     tick_ns, hw_tick_ns_allowed);
 	return error;
       }
@@ -133,7 +130,7 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
 
     cvmx_tim.max_ticks = (uint32_t)max_ticks;
     cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
-    cvmx_tim.tick_cycles = tick * cpu_clock_hz / 1000000;
+    cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000;
 
     temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
 
@@ -149,7 +146,7 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
     /* ensure input params fall into permitted ranges */
     if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
       {
-	cvmx_dprintf("init: num_buckets out of range\n");
+	cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n");
 	return error;
       }
 
@@ -158,7 +155,7 @@ int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
 					 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
     if (cvmx_tim.bucket == NULL)
       {
-	cvmx_dprintf("init: allocation problem\n");
+	cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n");
 	return error;
       }
     memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
@@ -202,7 +199,7 @@ void cvmx_tim_start(void)
     control.s.enable_timers = 1;
 
     /* Remember when we started the timers */
-    cvmx_tim.start_time = cvmx_get_cycle();
+    cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM);
     cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-tim.h b/sys/contrib/octeon-sdk/cvmx-tim.h
index 19a1c8a..bd49eb1 100644
--- a/sys/contrib/octeon-sdk/cvmx-tim.h
+++ b/sys/contrib/octeon-sdk/cvmx-tim.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,19 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the hardware work queue timers.
  *
-`* <hr>$Revision: 42186 $<hr>
+`* <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_TIM_H__
 #define __CVMX_TIM_H__
 
+#include "cvmx-clock.h"
 #include "cvmx-fpa.h"
 #include "cvmx-wqe.h"
 
@@ -207,7 +210,7 @@ static inline cvmx_tim_status_t cvmx_tim_add_entry(cvmx_wqe_t *work_entry, uint6
     volatile uint64_t         * tim_entry_ptr;  /* pointer to wqe address in timer chunk */
     uint64_t                    entries_per_chunk;
 
-    const uint64_t  cycles  = cvmx_get_cycle(); /* Get our reference time early for accuracy */
+    const uint64_t  cycles  = cvmx_clock_get_count(CVMX_CLOCK_TIM); /* Get our reference time early for accuracy */
     const uint64_t  core_num    = cvmx_get_core_num();  /* One timer per processor, so use this to select */
 
     /* Make sure the specified time won't wrap our bucket list */
@@ -311,7 +314,7 @@ static inline cvmx_tim_status_t cvmx_tim_add_entry(cvmx_wqe_t *work_entry, uint6
  */
 static inline cvmx_tim_status_t cvmx_tim_delete_entry(cvmx_tim_delete_t *delete_info)
 {
-    const uint64_t cycles = cvmx_get_cycle();
+    const uint64_t cycles = cvmx_clock_get_count(CVMX_CLOCK_TIM);
 
     if ((int64_t)(cycles - delete_info->commit_cycles) < 0)
     {
diff --git a/sys/contrib/octeon-sdk/cvmx-tlb.c b/sys/contrib/octeon-sdk/cvmx-tlb.c
new file mode 100644
index 0000000..08c5e28
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-tlb.c
@@ -0,0 +1,470 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+/**
+ * @file
+ *
+ * cvmx-tlb supplies per core TLB access functions for simple executive
+ * applications.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-tlb.h"
+
+//#define DEBUG
+
+/**
+ * @INTERNAL
+ * Convert page mask to string
+ */
+static inline const char* __mask_to_str(uint64_t mask)
+{
+    /* Most OCTEON processor does not support 1K page sizes */
+    uint64_t non_1k_mask = mask + CVMX_TLB_PAGEMASK_4K;
+
+    switch (non_1k_mask) {
+    case CVMX_TLB_PAGEMASK_4K:     return "4kb";
+    case CVMX_TLB_PAGEMASK_16K:    return "16kb";
+    case CVMX_TLB_PAGEMASK_64K:    return "64kb";
+    case CVMX_TLB_PAGEMASK_256K:   return "256kb";
+    case CVMX_TLB_PAGEMASK_1M:     return "1Mb";
+    case CVMX_TLB_PAGEMASK_4M:     return "4Mb";
+    case CVMX_TLB_PAGEMASK_16M:    return "16Mb";
+    case CVMX_TLB_PAGEMASK_64M:    return "64Mb";
+    case CVMX_TLB_PAGEMASK_256M:   return "256Mb";
+    }
+
+    return "";
+}
+
+/**
+ * @INTERNAL
+ * issue the tlb read instruction
+ */
+static inline void __tlb_read(void){
+    CVMX_EHB;
+    CVMX_TLBR;
+    CVMX_EHB;
+}
+
+/**
+ * @INTERNAL
+ * issue the tlb write instruction
+ */
+static inline void __tlb_write(void){
+
+    CVMX_EHB;
+    CVMX_TLBWI;
+    CVMX_EHB;
+}
+
+/**
+ * @INTERNAL
+ * issue the tlb read instruction
+ */
+static inline int __tlb_probe(uint64_t hi){
+    int index;
+    CVMX_EHB;
+    CVMX_MT_ENTRY_HIGH(hi);
+    CVMX_TLBP;
+    CVMX_EHB;
+
+    CVMX_MF_TLB_INDEX(index);
+
+    if (index < 0) index = -1;
+
+    return index;
+}
+
+/**
+ * @INTERNAL
+ * read a single tlb entry
+ *
+ * return 0: tlb entry is read
+ *    -1: index is invalid
+ */
+static inline int __tlb_read_index(uint32_t tlbi){
+
+    if (tlbi >= cvmx_tlb_size_limit()) {
+        return -1;
+    }
+
+    CVMX_MT_TLB_INDEX(tlbi);
+    __tlb_read();
+
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * write a single tlb entry
+ *
+ * return 0: tlb entry is read
+ *    -1: index is invalid
+ */
+static inline int __tlb_write_index(uint32_t tlbi,
+        			    uint64_t hi, uint64_t lo0,
+				    uint64_t lo1, uint64_t pagemask)
+{
+
+    if (tlbi >= cvmx_tlb_size_limit()) {
+        return -1;
+    }
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx-tlb-dbg: "
+	    "write TLB %d: hi %lx, lo0 %lx, lo1 %lx, pagemask %lx \n",
+		tlbi, hi, lo0, lo1, pagemask);
+#endif
+
+    CVMX_MT_TLB_INDEX(tlbi);
+    CVMX_MT_ENTRY_HIGH(hi);
+    CVMX_MT_ENTRY_LO_0(lo0);
+    CVMX_MT_ENTRY_LO_1(lo1);
+    CVMX_MT_PAGEMASK(pagemask);
+    __tlb_write();
+
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Determine if a TLB entry is free to use
+ */
+static inline int __tlb_entry_is_free(uint32_t tlbi) {
+    int ret = 0;
+    uint64_t lo0 = 0, lo1 = 0;
+
+    if (tlbi < cvmx_tlb_size_limit()) {
+
+        __tlb_read_index(tlbi);
+
+        /* Unused entries have neither even nor odd page mapped */
+    	CVMX_MF_ENTRY_LO_0(lo0);
+    	CVMX_MF_ENTRY_LO_1(lo1);
+
+        if ( !(lo0 & TLB_VALID) && !(lo1 & TLB_VALID)) {
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+
+/**
+ * @INTERNAL
+ * dump a single tlb entry
+ */
+static inline void __tlb_dump_index(uint32_t tlbi)
+{
+    if (tlbi < cvmx_tlb_size_limit()) {
+
+        if (__tlb_entry_is_free(tlbi)) {
+#ifdef DEBUG
+            cvmx_dprintf("Index: %3d Free \n", tlbi);
+#endif
+        } else {
+            uint64_t lo0, lo1, pgmask;
+            uint32_t hi, c0, c1;
+#ifdef DEBUG
+            int width = 13;
+#endif
+
+            __tlb_read_index(tlbi);
+
+            CVMX_MF_ENTRY_HIGH(hi);
+            CVMX_MF_ENTRY_LO_0(lo0);
+            CVMX_MF_ENTRY_LO_1(lo1);
+            CVMX_MF_PAGEMASK(pgmask);
+
+
+#ifdef DEBUG
+            cvmx_dprintf("Index: %3d pgmask=%s ", tlbi, __mask_to_str(pgmask));
+#endif
+
+            c0 = ( lo0 >> 3 ) & 7;
+            c1 = ( lo1 >> 3 ) & 7;
+
+#ifdef DEBUG
+            cvmx_dprintf("va=%0*lx asid=%02x\n",
+                               width, (hi & ~0x1fffUL), hi & 0xff);
+
+            cvmx_dprintf("\t[pa=%0*lx c=%d d=%d v=%d g=%d] ",
+                               width,
+                               (lo0 << 6) & PAGE_MASK, c0,
+                               (lo0 & 4) ? 1 : 0,
+                               (lo0 & 2) ? 1 : 0,
+                               (lo0 & 1) ? 1 : 0);
+            cvmx_dprintf("[pa=%0*lx c=%d d=%d v=%d g=%d]\n",
+                               width,
+                               (lo1 << 6) & PAGE_MASK, c1,
+                               (lo1 & 4) ? 1 : 0,
+                               (lo1 & 2) ? 1 : 0,
+                               (lo1 & 1) ? 1 : 0);
+
+#endif
+        }
+    }
+}
+
+/**
+ * @INTERNAL
+ * dump a single tlb entry
+ */
+static inline uint32_t __tlb_wired_index() {
+    uint32_t  tlbi;
+
+    CVMX_MF_TLB_WIRED(tlbi);
+    return tlbi;
+}
+
+/**
+ *  Set up a wired entry. This function is designed to be used by Simple
+ *  Executive to set up its virtual to physical address mapping at start up
+ *  time. After the mapping is set up, the remaining unused TLB entries can
+ *  be use for run time shared memory mapping.
+ *
+ *  Calling this function causes the C0 wired index register to increase.
+ *  Wired index register points to the separation between fixed TLB mapping
+ *  and run time shared memory mapping.
+ *
+ *  @param  hi      Entry Hi
+ *  @param  lo0     Entry Low0
+ *  @param  lo1     Entry Low1
+ *  @param  pagemask Pagemask
+ *
+ *  @return 0: the entry is added
+ *  @return -1: out of TLB entry
+ */
+int cvmx_tlb_add_wired_entry( uint64_t hi, uint64_t lo0,
+                              uint64_t lo1, uint64_t pagemask)
+{
+    uint64_t index;
+    int ret = -1;
+
+    index = __tlb_wired_index();
+
+    /* Check to make sure if the index is free to use */
+    if (index < cvmx_tlb_size_limit() && __tlb_entry_is_free(index) ) {
+        /* increase the wired index by 1*/
+        __tlb_write_index(index, hi, lo0, lo1, pagemask);
+        CVMX_MT_TLB_WIRED(index + 1);
+        ret = 0;
+    }
+
+    return ret;
+}
+
+/**
+ *  Find a free entry that can be used for share memory mapping.
+ *
+ *  @return -1: no free entry found
+ *  @return :  a free entry
+ */
+int cvmx_tlb_allocate_runtime_entry(void)
+{
+    uint32_t i, ret = -1;
+
+    for (i = __tlb_wired_index(); i< cvmx_tlb_size_limit(); i++) {
+
+    	/* Check to make sure the index is free to use */
+        if (__tlb_entry_is_free(i)) {
+		/* Found and return */
+        	ret = i;
+        	break;
+	}
+    }
+
+    return ret;
+}
+
+/**
+ *  Invalidate the TLB entry. Remove previous mapping if one was set up
+ */
+void cvmx_tlb_free_runtime_entry(uint32_t tlbi)
+{
+    /* Invalidate an unwired TLB entry */
+    if ((tlbi < cvmx_tlb_size_limit()) && (tlbi >= __tlb_wired_index())) {
+        __tlb_write_index(tlbi, 0xffffffff80000000ULL, 0, 0, 0);
+    }
+}
+
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *
+ *  @param index  Index of the TLB entry
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ */
+
+void cvmx_tlb_write_entry(int index, uint64_t vaddr, uint64_t paddr,
+			uint64_t size, uint64_t tlb_flags) {
+	uint64_t lo0, lo1, hi, pagemask;
+
+	if ( __is_power_of_two(size) ) {
+		if ( (__log2(size) & 1 ) == 0) {
+			/* size is not power of 4,  we only need to map
+  			   one page, figure out even or odd page to map */
+			if ((vaddr >> __log2(size) & 1))  {
+				lo0 =  0;
+				lo1 =  ((paddr >> 12) << 6) | tlb_flags;
+				hi =   ((vaddr - size) >> 12) << 12;
+			}else {
+				lo0 =  ((paddr >> 12) << 6) | tlb_flags;
+				lo1 =  0;
+				hi =   ((vaddr) >> 12) << 12;
+			}
+			pagemask = (size - 1) & (~1<<11);
+		}else {
+			lo0 =  ((paddr >> 12)<< 6) | tlb_flags;
+			lo1 =  (((paddr + size /2) >> 12) << 6) | tlb_flags;
+			hi =   ((vaddr) >> 12) << 12;
+			pagemask = ((size/2) -1) & (~1<<11);
+		}
+
+
+        	__tlb_write_index(index, hi, lo0, lo1, pagemask);
+
+	}
+}
+
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *  This version adds a wired entry that should not be changed at run time
+ *
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ *  @return -1: TLB out of entries
+ * 	     0:  fixed entry added
+ */
+int cvmx_tlb_add_fixed_entry( uint64_t vaddr, uint64_t paddr, uint64_t size, uint64_t tlb_flags) {
+
+    uint64_t index;
+    int ret = 0;
+
+    CVMX_MF_TLB_WIRED(index);
+
+    /* Check to make sure if the index is free to use */
+    if (index < cvmx_tlb_size_limit() && __tlb_entry_is_free(index) ) {
+	cvmx_tlb_write_entry(index, vaddr, paddr, size, tlb_flags);
+
+	if (!__tlb_entry_is_free(index)) {
+        	/* Bump up the wired register*/
+        	CVMX_MT_TLB_WIRED(index + 1);
+		ret  = 1;
+	}
+    }
+    return ret;
+}
+
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *  This version writes a runtime entry. It will check the index to make sure
+ *  not to overwrite any fixed entries.
+ *
+ *  @param index  Index of the TLB entry
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ */
+void cvmx_tlb_write_runtime_entry(int index, uint64_t vaddr, uint64_t paddr,
+                          uint64_t size, uint64_t tlb_flags)
+{
+
+    int wired_index;
+    CVMX_MF_TLB_WIRED(wired_index);
+
+    if (index >= wired_index) {
+	cvmx_tlb_write_entry(index, vaddr, paddr, size, tlb_flags);
+    }
+
+}
+
+
+
+/**
+ * Find the TLB index of a given virtual address
+ *
+ *  @param vaddr  The virtual address to look up
+ *  @return  -1  not TLB mapped
+ *           >=0 TLB TLB index
+ */
+int cvmx_tlb_lookup(uint64_t vaddr) {
+	uint64_t hi= (vaddr >> 12 ) << 12; /* We always use ASID 0 */
+
+	return  __tlb_probe(hi);
+}
+
+/**
+ *  Debug routine to show all shared memory mapping
+ */
+void cvmx_tlb_dump_shared_mapping(void) {
+    uint32_t tlbi;
+
+    for ( tlbi = __tlb_wired_index(); tlbi<cvmx_tlb_size_limit(); tlbi++ ) {
+        __tlb_dump_index(tlbi);
+    }
+}
+
+/**
+ *  Debug routine to show all TLB entries of this core
+ *
+ */
+void cvmx_tlb_dump_all(void) {
+
+    uint32_t tlbi;
+
+    for (tlbi = 0; tlbi<= cvmx_tlb_size_limit(); tlbi++ ) {
+        __tlb_dump_index(tlbi);
+    }
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-tlb.h b/sys/contrib/octeon-sdk/cvmx-tlb.h
new file mode 100644
index 0000000..bc20362
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-tlb.h
@@ -0,0 +1,270 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+#ifndef __CVMX_TLB_H__
+#define __CVMX_TLB_H__
+
+/**
+ * @file
+ *
+ * cvmx-tlb provides access functions for setting up TLB entries for simple
+ * executive applications.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_TLB_PAGEMASK_4K		(0x3     << 11)
+#define CVMX_TLB_PAGEMASK_16K		(0xF     << 11)
+#define CVMX_TLB_PAGEMASK_64K		(0x3F    << 11)
+#define CVMX_TLB_PAGEMASK_256K		(0xFF    << 11)
+#define CVMX_TLB_PAGEMASK_1M		(0x3FF   << 11)
+#define CVMX_TLB_PAGEMASK_4M		(0xFFF   << 11)
+#define CVMX_TLB_PAGEMASK_16M		(0x3FFF  << 11)
+#define CVMX_TLB_PAGEMASK_64M		(0xFFFF  << 11)
+#define CVMX_TLB_PAGEMASK_256M		(0x3FFFF << 11)
+
+#define PAGE_MASK 			( ~(( 1<< 12 ) -1))
+
+/**
+ *  Set up a wired entry. This function is designed to be used by Simple
+ *  Executive to set up its virtual to physical address mapping at start up
+ *  time. After the mapping is set up, the remaining unused TLB entries can
+ *  be use for run time shared memory mapping.
+ *
+ *  Calling this function causes the C0 wired index register to increase.
+ *  Wired index register points to the separation between fixed TLB mapping
+ *  and run time shared memory mapping.
+ *
+ *  @param  hi		Entry Hi
+ *  @param  lo0		Entry Low0
+ *  @param  lo1		Entry Low1
+ *  @pagam  pagemask    Pagemask
+ *
+ *  @return 0: the entry is added
+ *  @return -1: out of TLB entry
+ */
+int cvmx_tlb_add_wired_entry( uint64_t hi, uint64_t lo0,
+			      uint64_t lo1, uint64_t pagemask);
+
+
+/**
+ *  Find a free entry that can be used for share memory mapping.
+ *
+ *  @return -1: no free entry found
+ *  @return :  a free entry
+ */
+int cvmx_tlb_allocate_runtime_entry(void);
+
+/**
+ *  Invalidate the TLB entry. Remove previous mapping if one was set up
+ *  @param tlbi
+ */
+void cvmx_tlb_free_runtime_entry(uint32_t tlbi);
+
+/**
+ *  Debug routine to show all shared memory mapping
+ */
+void cvmx_tlb_dump_shared_mapping(void);
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *
+ *  @param index  Index of the TLB entry
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ */
+void cvmx_tlb_write_entry(int index, uint64_t vaddr, uint64_t paddr,
+                          uint64_t size, uint64_t tlb_flags);
+
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *  This version adds a wired entry that should not be changed at run time
+ *
+ *  @param index  Index of the TLB entry
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ *  @return -1: TLB out of entries
+ *           0:  fixed entry added
+ *
+ */
+int cvmx_tlb_add_fixed_entry(uint64_t vaddr, uint64_t paddr,
+                          uint64_t size, uint64_t tlb_flags);
+
+/**
+ *  Program a single TLB entry to enable the provided vaddr to paddr mapping.
+ *  This version writes a runtime entry. It will check the index to make sure
+ *  not to overwrite any fixed entries.
+ *
+ *  @param index  Index of the TLB entry
+ *  @param vaddr  The virtual address for this mapping
+ *  @param paddr  The physical address for this mapping
+ *  @param size   Size of the mapping
+ *  @param tlb_flags  Entry mapping flags
+ */
+void cvmx_tlb_write_runtime_entry(int index, uint64_t vaddr, uint64_t paddr,
+                          uint64_t size, uint64_t tlb_flags);
+
+
+/**
+ *  Find the TLB index of a given virtual address
+ *
+ *  @param vaddr  The virtual address to look up
+ *  @return  -1  not TLB mapped
+ *  	     >=0 TLB TLB index
+ */
+int cvmx_tlb_lookup(uint64_t vaddr);
+
+/**
+ *  Debug routine to show all TLB entries of this core
+ *
+ */
+void cvmx_tlb_dump_all(void);
+
+/**
+ *  Query for total number of TLBs of the core
+ *
+ *  @return Total number of TLB entries available on the core
+ */
+static inline uint32_t cvmx_tlb_size_limit(void)
+{
+	uint32_t tlb_size_limit = 0;
+
+	if      (OCTEON_IS_MODEL(OCTEON_CN63XX))  tlb_size_limit = 128;
+	else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))  tlb_size_limit =  64;
+	else if (OCTEON_IS_MODEL(OCTEON_CN3XXX))  tlb_size_limit =  32;
+
+	return tlb_size_limit;
+}
+
+/*
+ * @INTERNAL
+ * return the next power of two value for the given input <v>
+ *
+ * @param v input value
+ * @return next power of two value for v
+ */
+static inline uint64_t __upper_power_of_two(uint64_t v)
+{
+    v--;
+    v |= v >> 1;
+    v |= v >> 2;
+    v |= v >> 4;
+    v |= v >> 8;
+    v |= v >> 16;
+    v |= v >> 32;
+    v++;
+    return v;
+}
+
+/**
+ * @INTERNAL
+ * Check if the given value 'v' is power of two.
+ *
+ * @param v input value
+ * @return 1  yes
+ * 	   0  no
+ */
+static inline int __is_power_of_two(uint64_t v)
+{
+	int num_of_1s = 0;
+
+	CVMX_DPOP(num_of_1s, v);
+	return (num_of_1s  ==  1 );
+}
+
+
+/**
+ * @INTERNAL
+ *
+ * Find last bit set 64bit version
+ *
+ * @param x the integer to find leading 1
+ *
+ * @return >=0 the bit position (0..63) of the most significant 1 bit in a word
+ *   	   -1 if no 1 bit exists
+ */
+static inline uint64_t __fls64(uint64_t x)
+{
+	int lz;
+
+	if (sizeof(x) != 8) return 0;
+
+	__asm__(
+	"	.set	push						\n"
+	"	.set	mips64						\n"
+	"	dclz	%0, %1						\n"
+	"	.set	pop						\n"
+	: "=r" (lz)
+	: "r" (x));
+
+	return 63 - lz;
+}
+
+/**
+ * @INTERNAL
+ * Compute  log2(v), only works if v is power of two.
+ *
+ * @param v  the input value
+ * @return  log2(v)
+ */
+static inline uint32_t __log2(uint64_t v)
+{
+	uint32_t log2 = 0 ;
+
+	if (v) log2 =  __fls64(v);
+
+	return log2;
+}
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra-defs.h b/sys/contrib/octeon-sdk/cvmx-tra-defs.h
new file mode 100644
index 0000000..1bc2bd6
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-tra-defs.h
@@ -0,0 +1,3176 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-tra-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon tra.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_TRA_TYPEDEFS_H__
+#define __CVMX_TRA_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
+}
+#else
+#define CVMX_TRA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
+static inline uint64_t CVMX_TRA_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
+}
+#else
+#define CVMX_TRA_CTL (CVMX_ADD_IO_SEG(0x00011800A8000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
+}
+#else
+#define CVMX_TRA_CYCLES_SINCE (CVMX_ADD_IO_SEG(0x00011800A8000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
+}
+#else
+#define CVMX_TRA_CYCLES_SINCE1 (CVMX_ADD_IO_SEG(0x00011800A8000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
+}
+#else
+#define CVMX_TRA_FILT_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000058ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
+}
+#else
+#define CVMX_TRA_FILT_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A8000060ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
+static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
+}
+#else
+#define CVMX_TRA_FILT_CMD (CVMX_ADD_IO_SEG(0x00011800A8000040ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
+}
+#else
+#define CVMX_TRA_FILT_DID (CVMX_ADD_IO_SEG(0x00011800A8000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
+}
+#else
+#define CVMX_TRA_FILT_SID (CVMX_ADD_IO_SEG(0x00011800A8000048ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
+}
+#else
+#define CVMX_TRA_INT_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
+static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
+}
+#else
+#define CVMX_TRA_READ_DAT (CVMX_ADD_IO_SEG(0x00011800A8000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_READ_DAT_HI CVMX_TRA_READ_DAT_HI_FUNC()
+static inline uint64_t CVMX_TRA_READ_DAT_HI_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_READ_DAT_HI not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000030ull);
+}
+#else
+#define CVMX_TRA_READ_DAT_HI (CVMX_ADD_IO_SEG(0x00011800A8000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
+}
+#else
+#define CVMX_TRA_TRIG0_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
+}
+#else
+#define CVMX_TRA_TRIG0_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
+}
+#else
+#define CVMX_TRA_TRIG0_CMD (CVMX_ADD_IO_SEG(0x00011800A8000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
+}
+#else
+#define CVMX_TRA_TRIG0_DID (CVMX_ADD_IO_SEG(0x00011800A8000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
+}
+#else
+#define CVMX_TRA_TRIG0_SID (CVMX_ADD_IO_SEG(0x00011800A8000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
+}
+#else
+#define CVMX_TRA_TRIG1_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A80000D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
+}
+#else
+#define CVMX_TRA_TRIG1_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000E0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
+}
+#else
+#define CVMX_TRA_TRIG1_CMD (CVMX_ADD_IO_SEG(0x00011800A80000C0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
+}
+#else
+#define CVMX_TRA_TRIG1_DID (CVMX_ADD_IO_SEG(0x00011800A80000D0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
+}
+#else
+#define CVMX_TRA_TRIG1_SID (CVMX_ADD_IO_SEG(0x00011800A80000C8ull))
+#endif
+
+/**
+ * cvmx_tra_bist_status
+ *
+ * TRA_BIST_STATUS = Trace Buffer BiST Status
+ *
+ * Description:
+ */
+union cvmx_tra_bist_status
+{
+	uint64_t u64;
+	struct cvmx_tra_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t reserved_0_0                 : 1;
+#else
+	uint64_t reserved_0_0                 : 1;
+	uint64_t tdf1                         : 1;
+	uint64_t tcf                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_tra_bist_status_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t tcf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf1                         : 1;  /**< Bist Results for TDF memory 1
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+	uint64_t tdf0                         : 1;  /**< Bist Results for TCF memory 0
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t tdf0                         : 1;
+	uint64_t tdf1                         : 1;
+	uint64_t tcf                          : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn31xx;
+	struct cvmx_tra_bist_status_cn31xx    cn38xx;
+	struct cvmx_tra_bist_status_cn31xx    cn38xxp2;
+	struct cvmx_tra_bist_status_cn31xx    cn52xx;
+	struct cvmx_tra_bist_status_cn31xx    cn52xxp1;
+	struct cvmx_tra_bist_status_cn31xx    cn56xx;
+	struct cvmx_tra_bist_status_cn31xx    cn56xxp1;
+	struct cvmx_tra_bist_status_cn31xx    cn58xx;
+	struct cvmx_tra_bist_status_cn31xx    cn58xxp1;
+	struct cvmx_tra_bist_status_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t tdf                          : 1;  /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+	uint64_t tdf                          : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} cn63xx;
+	struct cvmx_tra_bist_status_cn63xx    cn63xxp1;
+};
+typedef union cvmx_tra_bist_status cvmx_tra_bist_status_t;
+
+/**
+ * cvmx_tra_ctl
+ *
+ * TRA_CTL = Trace Buffer Control
+ *
+ * Description:
+ *
+ * Notes:
+ * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1).
+ * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O
+ */
+union cvmx_tra_ctl
+{
+	uint64_t u64;
+	struct cvmx_tra_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t rdat_md                      : 1;  /**< TRA_READ_DAT mode bit
+                                                         If set, the TRA_READ_DAT reads will return the lower
+                                                         64 bits of the TRA entry and the upper bits must be
+                                                         read through TRA_READ_DAT_HI.  If not set the return
+                                                         value from TRA_READ_DAT accesses will switch between
+                                                         the lower bits and the upper bits of the TRA entry. */
+	uint64_t clkalways                    : 1;  /**< Conditional clock enable
+                                                         If set, the TRA clock is never disabled. */
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 1024 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t clkalways                    : 1;
+	uint64_t rdat_md                      : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_tra_ctl_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_15_63               : 49;
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 256 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t reserved_15_63               : 49;
+#endif
+	} cn31xx;
+	struct cvmx_tra_ctl_cn31xx            cn38xx;
+	struct cvmx_tra_ctl_cn31xx            cn38xxp2;
+	struct cvmx_tra_ctl_cn31xx            cn52xx;
+	struct cvmx_tra_ctl_cn31xx            cn52xxp1;
+	struct cvmx_tra_ctl_cn31xx            cn56xx;
+	struct cvmx_tra_ctl_cn31xx            cn56xxp1;
+	struct cvmx_tra_ctl_cn31xx            cn58xx;
+	struct cvmx_tra_ctl_cn31xx            cn58xxp1;
+	struct cvmx_tra_ctl_s                 cn63xx;
+	struct cvmx_tra_ctl_cn63xxp1
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t clkalways                    : 1;  /**< Conditional clock enable
+                                                         If set, the TRA clock is never disabled. */
+	uint64_t ignore_o                     : 1;  /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+	uint64_t mcd0_ena                     : 1;  /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+	uint64_t mcd0_thr                     : 1;  /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+	uint64_t ciu_thr                      : 1;  /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t ciu_trg                      : 1;  /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+	uint64_t full_thr                     : 2;  /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+	uint64_t time_grn                     : 3;  /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+	uint64_t trig_ctl                     : 2;  /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+	uint64_t wrap                         : 1;  /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 1024 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+	uint64_t ena                          : 1;  /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+	uint64_t ena                          : 1;
+	uint64_t wrap                         : 1;
+	uint64_t trig_ctl                     : 2;
+	uint64_t time_grn                     : 3;
+	uint64_t full_thr                     : 2;
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t mcd0_ena                     : 1;
+	uint64_t ignore_o                     : 1;
+	uint64_t clkalways                    : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn63xxp1;
+};
+typedef union cvmx_tra_ctl cvmx_tra_ctl_t;
+
+/**
+ * cvmx_tra_cycles_since
+ *
+ * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is obsolete.  Use TRA_CYCLES_SINCE1 instead.
+ *
+ */
+union cvmx_tra_cycles_since
+{
+	uint64_t u64;
+	struct cvmx_tra_cycles_since_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cycles                       : 48; /**< Cycles since the last entry was written */
+	uint64_t rptr                         : 8;  /**< Read pointer */
+	uint64_t wptr                         : 8;  /**< Write pointer */
+#else
+	uint64_t wptr                         : 8;
+	uint64_t rptr                         : 8;
+	uint64_t cycles                       : 48;
+#endif
+	} s;
+	struct cvmx_tra_cycles_since_s        cn31xx;
+	struct cvmx_tra_cycles_since_s        cn38xx;
+	struct cvmx_tra_cycles_since_s        cn38xxp2;
+	struct cvmx_tra_cycles_since_s        cn52xx;
+	struct cvmx_tra_cycles_since_s        cn52xxp1;
+	struct cvmx_tra_cycles_since_s        cn56xx;
+	struct cvmx_tra_cycles_since_s        cn56xxp1;
+	struct cvmx_tra_cycles_since_s        cn58xx;
+	struct cvmx_tra_cycles_since_s        cn58xxp1;
+	struct cvmx_tra_cycles_since_s        cn63xx;
+	struct cvmx_tra_cycles_since_s        cn63xxp1;
+};
+typedef union cvmx_tra_cycles_since cvmx_tra_cycles_since_t;
+
+/**
+ * cvmx_tra_cycles_since1
+ *
+ * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ *
+ * Description:
+ */
+union cvmx_tra_cycles_since1
+{
+	uint64_t u64;
+	struct cvmx_tra_cycles_since1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t cycles                       : 40; /**< Cycles since the last entry was written */
+	uint64_t reserved_22_23               : 2;
+	uint64_t rptr                         : 10; /**< Read pointer */
+	uint64_t reserved_10_11               : 2;
+	uint64_t wptr                         : 10; /**< Write pointer */
+#else
+	uint64_t wptr                         : 10;
+	uint64_t reserved_10_11               : 2;
+	uint64_t rptr                         : 10;
+	uint64_t reserved_22_23               : 2;
+	uint64_t cycles                       : 40;
+#endif
+	} s;
+	struct cvmx_tra_cycles_since1_s       cn52xx;
+	struct cvmx_tra_cycles_since1_s       cn52xxp1;
+	struct cvmx_tra_cycles_since1_s       cn56xx;
+	struct cvmx_tra_cycles_since1_s       cn56xxp1;
+	struct cvmx_tra_cycles_since1_s       cn58xx;
+	struct cvmx_tra_cycles_since1_s       cn58xxp1;
+	struct cvmx_tra_cycles_since1_s       cn63xx;
+	struct cvmx_tra_cycles_since1_s       cn63xxp1;
+};
+typedef union cvmx_tra_cycles_since1 cvmx_tra_cycles_since1_t;
+
+/**
+ * cvmx_tra_filt_adr_adr
+ *
+ * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_tra_filt_adr_adr
+{
+	uint64_t u64;
+	struct cvmx_tra_filt_adr_adr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_filt_adr_adr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn38xx;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn38xxp2;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn52xx;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn52xxp1;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn56xx;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn56xxp1;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn58xx;
+	struct cvmx_tra_filt_adr_adr_cn31xx   cn58xxp1;
+	struct cvmx_tra_filt_adr_adr_s        cn63xx;
+	struct cvmx_tra_filt_adr_adr_s        cn63xxp1;
+};
+typedef union cvmx_tra_filt_adr_adr cvmx_tra_filt_adr_adr_t;
+
+/**
+ * cvmx_tra_filt_adr_msk
+ *
+ * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_tra_filt_adr_msk
+{
+	uint64_t u64;
+	struct cvmx_tra_filt_adr_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
+                                                         is set, TRA_FILT_ADR_MSK must be zero to
+                                                         guarantee that any IOBDMAs enter the trace. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_filt_adr_msk_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
+                                                         is set, TRA_FILT_ADR_MSK must be zero to
+                                                         guarantee that any IOBDMAs enter the trace. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn38xx;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn38xxp2;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn52xx;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn52xxp1;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn56xx;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn56xxp1;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn58xx;
+	struct cvmx_tra_filt_adr_msk_cn31xx   cn58xxp1;
+	struct cvmx_tra_filt_adr_msk_s        cn63xx;
+	struct cvmx_tra_filt_adr_msk_s        cn63xxp1;
+};
+typedef union cvmx_tra_filt_adr_msk cvmx_tra_filt_adr_msk_t;
+
+/**
+ * cvmx_tra_filt_cmd
+ *
+ * TRA_FILT_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * enter the trace.
+ */
+union cvmx_tra_filt_cmd
+{
+	uint64_t u64;
+	struct cvmx_tra_filt_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_tra_filt_cmd_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_tra_filt_cmd_cn31xx       cn38xx;
+	struct cvmx_tra_filt_cmd_cn31xx       cn38xxp2;
+	struct cvmx_tra_filt_cmd_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_tra_filt_cmd_cn52xx       cn52xxp1;
+	struct cvmx_tra_filt_cmd_cn52xx       cn56xx;
+	struct cvmx_tra_filt_cmd_cn52xx       cn56xxp1;
+	struct cvmx_tra_filt_cmd_cn52xx       cn58xx;
+	struct cvmx_tra_filt_cmd_cn52xx       cn58xxp1;
+	struct cvmx_tra_filt_cmd_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn63xx;
+	struct cvmx_tra_filt_cmd_cn63xx       cn63xxp1;
+};
+typedef union cvmx_tra_filt_cmd cvmx_tra_filt_cmd_t;
+
+/**
+ * cvmx_tra_filt_did
+ *
+ * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_filt_did
+{
+	uint64_t u64;
+	struct cvmx_tra_filt_did_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_tra_filt_did_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable tracing of requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_tra_filt_did_cn31xx       cn38xx;
+	struct cvmx_tra_filt_did_cn31xx       cn38xxp2;
+	struct cvmx_tra_filt_did_cn31xx       cn52xx;
+	struct cvmx_tra_filt_did_cn31xx       cn52xxp1;
+	struct cvmx_tra_filt_did_cn31xx       cn56xx;
+	struct cvmx_tra_filt_did_cn31xx       cn56xxp1;
+	struct cvmx_tra_filt_did_cn31xx       cn58xx;
+	struct cvmx_tra_filt_did_cn31xx       cn58xxp1;
+	struct cvmx_tra_filt_did_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable tracing of FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable tracing of DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable tracing of RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable tracing of USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable tracing of PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable tracing of IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable tracing of requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable tracing of MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xx;
+	struct cvmx_tra_filt_did_cn63xx       cn63xxp1;
+};
+typedef union cvmx_tra_filt_did cvmx_tra_filt_did_t;
+
+/**
+ * cvmx_tra_filt_sid
+ *
+ * TRA_FILT_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_filt_sid
+{
+	uint64_t u64;
+	struct cvmx_tra_filt_sid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_tra_filt_sid_s            cn31xx;
+	struct cvmx_tra_filt_sid_s            cn38xx;
+	struct cvmx_tra_filt_sid_s            cn38xxp2;
+	struct cvmx_tra_filt_sid_s            cn52xx;
+	struct cvmx_tra_filt_sid_s            cn52xxp1;
+	struct cvmx_tra_filt_sid_s            cn56xx;
+	struct cvmx_tra_filt_sid_s            cn56xxp1;
+	struct cvmx_tra_filt_sid_s            cn58xx;
+	struct cvmx_tra_filt_sid_s            cn58xxp1;
+	struct cvmx_tra_filt_sid_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable tracing of requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable tracing of read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable tracing of write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_tra_filt_sid_cn63xx       cn63xxp1;
+};
+typedef union cvmx_tra_filt_sid cvmx_tra_filt_sid_t;
+
+/**
+ * cvmx_tra_int_status
+ *
+ * TRA_INT_STATUS = Trace Buffer Interrupt Status
+ *
+ * Description:
+ *
+ * Notes:
+ * During a CSR write to this register, the write data is used as a mask to clear the selected status
+ * bits (status'[3:0] = status[3:0] & ~write_data[3:0]).
+ */
+union cvmx_tra_int_status
+{
+	uint64_t u64;
+	struct cvmx_tra_int_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t mcd0_thr                     : 1;  /**< MCD0 full threshold interrupt status
+                                                         0=trace buffer did not generate MCD0 wire pulse
+                                                         1=trace buffer did     generate MCD0 wire pulse
+                                                           and prevents additional MCD0_THR MCD0 wire pulses */
+	uint64_t mcd0_trg                     : 1;  /**< MCD0 end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt
+                                                           and prevents additional MCD0_TRG MCD0 wire pulses */
+	uint64_t ciu_thr                      : 1;  /**< CIU full threshold interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+	uint64_t ciu_trg                      : 1;  /**< CIU end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+#else
+	uint64_t ciu_trg                      : 1;
+	uint64_t ciu_thr                      : 1;
+	uint64_t mcd0_trg                     : 1;
+	uint64_t mcd0_thr                     : 1;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_tra_int_status_s          cn31xx;
+	struct cvmx_tra_int_status_s          cn38xx;
+	struct cvmx_tra_int_status_s          cn38xxp2;
+	struct cvmx_tra_int_status_s          cn52xx;
+	struct cvmx_tra_int_status_s          cn52xxp1;
+	struct cvmx_tra_int_status_s          cn56xx;
+	struct cvmx_tra_int_status_s          cn56xxp1;
+	struct cvmx_tra_int_status_s          cn58xx;
+	struct cvmx_tra_int_status_s          cn58xxp1;
+	struct cvmx_tra_int_status_s          cn63xx;
+	struct cvmx_tra_int_status_s          cn63xxp1;
+};
+typedef union cvmx_tra_int_status cvmx_tra_int_status_t;
+
+/**
+ * cvmx_tra_read_dat
+ *
+ * TRA_READ_DAT = Trace Buffer Read Data
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is a memory of 1024 entries.  When the trace was enabled, the read pointer was set to entry
+ * 0 by hardware.  Each read to this address increments the read pointer.
+ */
+union cvmx_tra_read_dat
+{
+	uint64_t u64;
+	struct cvmx_tra_read_dat_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t data                         : 64; /**< Trace buffer data for current entry */
+#else
+	uint64_t data                         : 64;
+#endif
+	} s;
+	struct cvmx_tra_read_dat_s            cn31xx;
+	struct cvmx_tra_read_dat_s            cn38xx;
+	struct cvmx_tra_read_dat_s            cn38xxp2;
+	struct cvmx_tra_read_dat_s            cn52xx;
+	struct cvmx_tra_read_dat_s            cn52xxp1;
+	struct cvmx_tra_read_dat_s            cn56xx;
+	struct cvmx_tra_read_dat_s            cn56xxp1;
+	struct cvmx_tra_read_dat_s            cn58xx;
+	struct cvmx_tra_read_dat_s            cn58xxp1;
+	struct cvmx_tra_read_dat_s            cn63xx;
+	struct cvmx_tra_read_dat_s            cn63xxp1;
+};
+typedef union cvmx_tra_read_dat cvmx_tra_read_dat_t;
+
+/**
+ * cvmx_tra_read_dat_hi
+ *
+ * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0
+ *
+ * Description:
+ *
+ * Notes:
+ * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer.  The
+ * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg.
+ */
+union cvmx_tra_read_dat_hi
+{
+	uint64_t u64;
+	struct cvmx_tra_read_dat_hi_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t data                         : 5;  /**< Trace buffer data[68:64] for current entry */
+#else
+	uint64_t data                         : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_tra_read_dat_hi_s         cn63xx;
+};
+typedef union cvmx_tra_read_dat_hi cvmx_tra_read_dat_hi_t;
+
+/**
+ * cvmx_tra_trig0_adr_adr
+ *
+ * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_tra_trig0_adr_adr
+{
+	uint64_t u64;
+	struct cvmx_tra_trig0_adr_adr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_trig0_adr_adr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn38xx;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn38xxp2;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn52xx;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn52xxp1;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn56xx;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn56xxp1;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn58xx;
+	struct cvmx_tra_trig0_adr_adr_cn31xx  cn58xxp1;
+	struct cvmx_tra_trig0_adr_adr_s       cn63xx;
+	struct cvmx_tra_trig0_adr_adr_s       cn63xxp1;
+};
+typedef union cvmx_tra_trig0_adr_adr cvmx_tra_trig0_adr_adr_t;
+
+/**
+ * cvmx_tra_trig0_adr_msk
+ *
+ * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig0_adr_msk
+{
+	uint64_t u64;
+	struct cvmx_tra_trig0_adr_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_trig0_adr_msk_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn38xx;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn38xxp2;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn52xx;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn52xxp1;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn56xx;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn56xxp1;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn58xx;
+	struct cvmx_tra_trig0_adr_msk_cn31xx  cn58xxp1;
+	struct cvmx_tra_trig0_adr_msk_s       cn63xx;
+	struct cvmx_tra_trig0_adr_msk_s       cn63xxp1;
+};
+typedef union cvmx_tra_trig0_adr_msk cvmx_tra_trig0_adr_msk_t;
+
+/**
+ * cvmx_tra_trig0_cmd
+ *
+ * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+union cvmx_tra_trig0_cmd
+{
+	uint64_t u64;
+	struct cvmx_tra_trig0_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_tra_trig0_cmd_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig0_cmd_cn31xx      cn38xx;
+	struct cvmx_tra_trig0_cmd_cn31xx      cn38xxp2;
+	struct cvmx_tra_trig0_cmd_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_tra_trig0_cmd_cn52xx      cn52xxp1;
+	struct cvmx_tra_trig0_cmd_cn52xx      cn56xx;
+	struct cvmx_tra_trig0_cmd_cn52xx      cn56xxp1;
+	struct cvmx_tra_trig0_cmd_cn52xx      cn58xx;
+	struct cvmx_tra_trig0_cmd_cn52xx      cn58xxp1;
+	struct cvmx_tra_trig0_cmd_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig0_cmd_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig0_cmd cvmx_tra_trig0_cmd_t;
+
+/**
+ * cvmx_tra_trig0_did
+ *
+ * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig0_did
+{
+	uint64_t u64;
+	struct cvmx_tra_trig0_did_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_tra_trig0_did_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig0_did_cn31xx      cn38xx;
+	struct cvmx_tra_trig0_did_cn31xx      cn38xxp2;
+	struct cvmx_tra_trig0_did_cn31xx      cn52xx;
+	struct cvmx_tra_trig0_did_cn31xx      cn52xxp1;
+	struct cvmx_tra_trig0_did_cn31xx      cn56xx;
+	struct cvmx_tra_trig0_did_cn31xx      cn56xxp1;
+	struct cvmx_tra_trig0_did_cn31xx      cn58xx;
+	struct cvmx_tra_trig0_did_cn31xx      cn58xxp1;
+	struct cvmx_tra_trig0_did_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig0_did_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig0_did cvmx_tra_trig0_did_t;
+
+/**
+ * cvmx_tra_trig0_sid
+ *
+ * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig0_sid
+{
+	uint64_t u64;
+	struct cvmx_tra_trig0_sid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_tra_trig0_sid_s           cn31xx;
+	struct cvmx_tra_trig0_sid_s           cn38xx;
+	struct cvmx_tra_trig0_sid_s           cn38xxp2;
+	struct cvmx_tra_trig0_sid_s           cn52xx;
+	struct cvmx_tra_trig0_sid_s           cn52xxp1;
+	struct cvmx_tra_trig0_sid_s           cn56xx;
+	struct cvmx_tra_trig0_sid_s           cn56xxp1;
+	struct cvmx_tra_trig0_sid_s           cn58xx;
+	struct cvmx_tra_trig0_sid_s           cn58xxp1;
+	struct cvmx_tra_trig0_sid_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig0_sid_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig0_sid cvmx_tra_trig0_sid_t;
+
+/**
+ * cvmx_tra_trig1_adr_adr
+ *
+ * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address
+ *
+ * Description:
+ */
+union cvmx_tra_trig1_adr_adr
+{
+	uint64_t u64;
+	struct cvmx_tra_trig1_adr_adr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Unmasked Address
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_trig1_adr_adr_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Unmasked Address
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn38xx;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn38xxp2;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn52xx;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn52xxp1;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn56xx;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn56xxp1;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn58xx;
+	struct cvmx_tra_trig1_adr_adr_cn31xx  cn58xxp1;
+	struct cvmx_tra_trig1_adr_adr_s       cn63xx;
+	struct cvmx_tra_trig1_adr_adr_s       cn63xxp1;
+};
+typedef union cvmx_tra_trig1_adr_adr cvmx_tra_trig1_adr_adr_t;
+
+/**
+ * cvmx_tra_trig1_adr_msk
+ *
+ * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig1_adr_msk
+{
+	uint64_t u64;
+	struct cvmx_tra_trig1_adr_msk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t adr                          : 38; /**< Address Mask
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 38;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_tra_trig1_adr_msk_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t adr                          : 36; /**< Address Mask
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+	uint64_t adr                          : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn38xx;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn38xxp2;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn52xx;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn52xxp1;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn56xx;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn56xxp1;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn58xx;
+	struct cvmx_tra_trig1_adr_msk_cn31xx  cn58xxp1;
+	struct cvmx_tra_trig1_adr_msk_s       cn63xx;
+	struct cvmx_tra_trig1_adr_msk_s       cn63xxp1;
+};
+typedef union cvmx_tra_trig1_adr_msk cvmx_tra_trig1_adr_msk_t;
+
+/**
+ * cvmx_tra_trig1_cmd
+ *
+ * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask
+ *
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+union cvmx_tra_trig1_cmd
+{
+	uint64_t u64;
+	struct cvmx_tra_trig1_cmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_32_35               : 4;
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_16_19               : 4;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_0_13                : 14;
+#else
+	uint64_t reserved_0_13                : 14;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_19               : 4;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t reserved_32_35               : 4;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} s;
+	struct cvmx_tra_trig1_cmd_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_16_63               : 48;
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t reserved_16_63               : 48;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig1_cmd_cn31xx      cn38xx;
+	struct cvmx_tra_trig1_cmd_cn31xx      cn38xxp2;
+	struct cvmx_tra_trig1_cmd_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t saa                          : 1;  /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst                        : 1;  /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t dwb                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t ldd                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t stf                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst                        : 1;
+	uint64_t iobdma                       : 1;
+	uint64_t saa                          : 1;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} cn52xx;
+	struct cvmx_tra_trig1_cmd_cn52xx      cn52xxp1;
+	struct cvmx_tra_trig1_cmd_cn52xx      cn56xx;
+	struct cvmx_tra_trig1_cmd_cn52xx      cn56xxp1;
+	struct cvmx_tra_trig1_cmd_cn52xx      cn58xx;
+	struct cvmx_tra_trig1_cmd_cn52xx      cn58xxp1;
+	struct cvmx_tra_trig1_cmd_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t saa64                        : 1;  /**< Enable SAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t saa32                        : 1;  /**< Enable SAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_60_61               : 2;
+	uint64_t faa64                        : 1;  /**< Enable FAA64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t faa32                        : 1;  /**< Enable FAA32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_56_57               : 2;
+	uint64_t decr64                       : 1;  /**< Enable DECR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr32                       : 1;  /**< Enable DECR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr16                       : 1;  /**< Enable DECR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t decr8                        : 1;  /**< Enable DECR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr64                       : 1;  /**< Enable INCR64  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr32                       : 1;  /**< Enable INCR32  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr16                       : 1;  /**< Enable INCR16  tracing
+                                                         0=disable, 1=enable */
+	uint64_t incr8                        : 1;  /**< Enable INCR8   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr64                        : 1;  /**< Enable CLR64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr32                        : 1;  /**< Enable CLR32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr16                        : 1;  /**< Enable CLR16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t clr8                         : 1;  /**< Enable CLR8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t set64                        : 1;  /**< Enable SET64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set32                        : 1;  /**< Enable SET32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set16                        : 1;  /**< Enable SET16   tracing
+                                                         0=disable, 1=enable */
+	uint64_t set8                         : 1;  /**< Enable SET8    tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst64                      : 1;  /**< Enable IOBST64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst32                      : 1;  /**< Enable IOBST32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst16                      : 1;  /**< Enable IOBST16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobst8                       : 1;  /**< Enable IOBST8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld64                      : 1;  /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld32                      : 1;  /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld16                      : 1;  /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobld8                       : 1;  /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+	uint64_t lckl2                        : 1;  /**< Enable LCKL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbl2                         : 1;  /**< Enable WBL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2                        : 1;  /**< Enable WBIL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t invl2                        : 1;  /**< Enable INVL2   tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_27_27               : 1;
+	uint64_t stgl2i                       : 1;  /**< Enable STGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t ltgl2i                       : 1;  /**< Enable LTGL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t wbil2i                       : 1;  /**< Enable WBIL2I  tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas64                        : 1;  /**< Enable FAS64   tracing
+                                                         0=disable, 1=enable */
+	uint64_t fas32                        : 1;  /**< Enable FAS32   tracing
+                                                         0=disable, 1=enable */
+	uint64_t sttil1                       : 1;  /**< Enable STTIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stfil1                       : 1;  /**< Enable STFIL1  tracing
+                                                         0=disable, 1=enable */
+	uint64_t stc                          : 1;  /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stp                          : 1;  /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stt                          : 1;  /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t stf                          : 1;  /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+	uint64_t iobdma                       : 1;  /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_10_14               : 5;
+	uint64_t psl1                         : 1;  /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldd                          : 1;  /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+	uint64_t reserved_6_7                 : 2;
+	uint64_t dwb                          : 1;  /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+	uint64_t rpl2                         : 1;  /**< Enable RPL2    tracing
+                                                         0=disable, 1=enable */
+	uint64_t pl2                          : 1;  /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldi                          : 1;  /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+	uint64_t ldt                          : 1;  /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+	uint64_t nop                          : 1;  /**< Enable NOP     tracing
+                                                         0=disable, 1=enable */
+#else
+	uint64_t nop                          : 1;
+	uint64_t ldt                          : 1;
+	uint64_t ldi                          : 1;
+	uint64_t pl2                          : 1;
+	uint64_t rpl2                         : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_6_7                 : 2;
+	uint64_t ldd                          : 1;
+	uint64_t psl1                         : 1;
+	uint64_t reserved_10_14               : 5;
+	uint64_t iobdma                       : 1;
+	uint64_t stf                          : 1;
+	uint64_t stt                          : 1;
+	uint64_t stp                          : 1;
+	uint64_t stc                          : 1;
+	uint64_t stfil1                       : 1;
+	uint64_t sttil1                       : 1;
+	uint64_t fas32                        : 1;
+	uint64_t fas64                        : 1;
+	uint64_t wbil2i                       : 1;
+	uint64_t ltgl2i                       : 1;
+	uint64_t stgl2i                       : 1;
+	uint64_t reserved_27_27               : 1;
+	uint64_t invl2                        : 1;
+	uint64_t wbil2                        : 1;
+	uint64_t wbl2                         : 1;
+	uint64_t lckl2                        : 1;
+	uint64_t iobld8                       : 1;
+	uint64_t iobld16                      : 1;
+	uint64_t iobld32                      : 1;
+	uint64_t iobld64                      : 1;
+	uint64_t iobst8                       : 1;
+	uint64_t iobst16                      : 1;
+	uint64_t iobst32                      : 1;
+	uint64_t iobst64                      : 1;
+	uint64_t set8                         : 1;
+	uint64_t set16                        : 1;
+	uint64_t set32                        : 1;
+	uint64_t set64                        : 1;
+	uint64_t clr8                         : 1;
+	uint64_t clr16                        : 1;
+	uint64_t clr32                        : 1;
+	uint64_t clr64                        : 1;
+	uint64_t incr8                        : 1;
+	uint64_t incr16                       : 1;
+	uint64_t incr32                       : 1;
+	uint64_t incr64                       : 1;
+	uint64_t decr8                        : 1;
+	uint64_t decr16                       : 1;
+	uint64_t decr32                       : 1;
+	uint64_t decr64                       : 1;
+	uint64_t reserved_56_57               : 2;
+	uint64_t faa32                        : 1;
+	uint64_t faa64                        : 1;
+	uint64_t reserved_60_61               : 2;
+	uint64_t saa32                        : 1;
+	uint64_t saa64                        : 1;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig1_cmd_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig1_cmd cvmx_tra_trig1_cmd_t;
+
+/**
+ * cvmx_tra_trig1_did
+ *
+ * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig1_did
+{
+	uint64_t u64;
+	struct cvmx_tra_trig1_did_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_13_63               : 51;
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t reserved_9_11                : 3;
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t reserved_3_3                 : 1;
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t reserved_3_3                 : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t reserved_9_11                : 3;
+	uint64_t pow                          : 1;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_tra_trig1_did_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal                      : 19; /**< Illegal destinations */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 3;  /**< Illegal destinations */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t pci                          : 1;  /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on CIU and GPIO CSR's */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t pci                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t illegal2                     : 3;
+	uint64_t pow                          : 1;
+	uint64_t illegal                      : 19;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn31xx;
+	struct cvmx_tra_trig1_did_cn31xx      cn38xx;
+	struct cvmx_tra_trig1_did_cn31xx      cn38xxp2;
+	struct cvmx_tra_trig1_did_cn31xx      cn52xx;
+	struct cvmx_tra_trig1_did_cn31xx      cn52xxp1;
+	struct cvmx_tra_trig1_did_cn31xx      cn56xx;
+	struct cvmx_tra_trig1_did_cn31xx      cn56xxp1;
+	struct cvmx_tra_trig1_did_cn31xx      cn58xx;
+	struct cvmx_tra_trig1_did_cn31xx      cn58xxp1;
+	struct cvmx_tra_trig1_did_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t illegal5                     : 1;  /**< Illegal destinations */
+	uint64_t fau                          : 1;  /**< Enable triggering on FAU accesses */
+	uint64_t illegal4                     : 2;  /**< Illegal destinations */
+	uint64_t dpi                          : 1;  /**< Enable triggering on DPI accesses
+                                                         (DPI NCB CSRs) */
+	uint64_t illegal                      : 12; /**< Illegal destinations */
+	uint64_t rad                          : 1;  /**< Enable triggering on RAD accesses
+                                                         (doorbells) */
+	uint64_t usb0                         : 1;  /**< Enable triggering on USB0 accesses
+                                                         (UAHC0 EHCI and OHCI NCB CSRs) */
+	uint64_t pow                          : 1;  /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+	uint64_t illegal2                     : 1;  /**< Illegal destination */
+	uint64_t pko                          : 1;  /**< Enable triggering on PKO accesses
+                                                         (doorbells) */
+	uint64_t ipd                          : 1;  /**< Enable triggering on IPD CSR accesses
+                                                         (IPD CSRs) */
+	uint64_t rng                          : 1;  /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+	uint64_t zip                          : 1;  /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+	uint64_t dfa                          : 1;  /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+	uint64_t fpa                          : 1;  /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+	uint64_t key                          : 1;  /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+	uint64_t sli                          : 1;  /**< Enable triggering on requests to SLI and RSL-type
+                                                         CSR's (RSL CSR's, PCI/sRIO bus operations, SLI
+                                                         CSR's) */
+	uint64_t illegal3                     : 2;  /**< Illegal destinations */
+	uint64_t mio                          : 1;  /**< Enable triggering on MIO accesses
+                                                         (CIU and GPIO CSR's, boot bus accesses) */
+#else
+	uint64_t mio                          : 1;
+	uint64_t illegal3                     : 2;
+	uint64_t sli                          : 1;
+	uint64_t key                          : 1;
+	uint64_t fpa                          : 1;
+	uint64_t dfa                          : 1;
+	uint64_t zip                          : 1;
+	uint64_t rng                          : 1;
+	uint64_t ipd                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t illegal2                     : 1;
+	uint64_t pow                          : 1;
+	uint64_t usb0                         : 1;
+	uint64_t rad                          : 1;
+	uint64_t illegal                      : 12;
+	uint64_t dpi                          : 1;
+	uint64_t illegal4                     : 2;
+	uint64_t fau                          : 1;
+	uint64_t illegal5                     : 1;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig1_did_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig1_did cvmx_tra_trig1_did_t;
+
+/**
+ * cvmx_tra_trig1_sid
+ *
+ * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask
+ *
+ * Description:
+ */
+union cvmx_tra_trig1_sid
+{
+	uint64_t u64;
+	struct cvmx_tra_trig1_sid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t pp                           : 16; /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 16;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_tra_trig1_sid_s           cn31xx;
+	struct cvmx_tra_trig1_sid_s           cn38xx;
+	struct cvmx_tra_trig1_sid_s           cn38xxp2;
+	struct cvmx_tra_trig1_sid_s           cn52xx;
+	struct cvmx_tra_trig1_sid_s           cn52xxp1;
+	struct cvmx_tra_trig1_sid_s           cn56xx;
+	struct cvmx_tra_trig1_sid_s           cn56xxp1;
+	struct cvmx_tra_trig1_sid_s           cn58xx;
+	struct cvmx_tra_trig1_sid_s           cn58xxp1;
+	struct cvmx_tra_trig1_sid_cn63xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t dwb                          : 1;  /**< Enable triggering on requests from the IOB DWB engine */
+	uint64_t iobreq                       : 1;  /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+	uint64_t pko                          : 1;  /**< Enable triggering on read requests from PKO */
+	uint64_t pki                          : 1;  /**< Enable triggering on write requests from PIP/IPD */
+	uint64_t reserved_8_15                : 8;
+	uint64_t pp                           : 8;  /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+	uint64_t pp                           : 8;
+	uint64_t reserved_8_15                : 8;
+	uint64_t pki                          : 1;
+	uint64_t pko                          : 1;
+	uint64_t iobreq                       : 1;
+	uint64_t dwb                          : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn63xx;
+	struct cvmx_tra_trig1_sid_cn63xx      cn63xxp1;
+};
+typedef union cvmx_tra_trig1_sid cvmx_tra_trig1_sid_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra.c b/sys/contrib/octeon-sdk/cvmx-tra.c
index 02b1da2..e1585ec 100644
--- a/sys/contrib/octeon-sdk/cvmx-tra.c
+++ b/sys/contrib/octeon-sdk/cvmx-tra.c
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  *
@@ -47,8 +49,14 @@
  *
  * <hr>$Revision: 30644 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-tra.h>
+#else
 #include "cvmx.h"
 #include "cvmx-tra.h"
+#endif
 
 static const char *TYPE_ARRAY[] = {
     "DWB - Don't write back",
@@ -85,6 +93,73 @@ static const char *TYPE_ARRAY[] = {
     "RSVD31"
 };
 
+static const char *TYPE_ARRAY2[] = {
+    "NOP - None",
+    "LDT - Icache/IO fill, skip L2",
+    "LDI - Icache/IO fill",
+    "PL2 - Prefetch into L2",
+    "RPL2 - Mark for replacement in L2",
+    "DWB - Don't write back",
+    "RSVD6",
+    "RSVD7",
+    "LDD - Dcache fill",
+    "PSL1 - Prefetch L1, skip L2",
+    "RSVD10",
+    "RSVD11",
+    "RSVD12",
+    "RSVD13",
+    "RSVD14",
+    "IOBDMA - Async IOB",
+    "STF - Store full",
+    "STT - Store full, skip L2",
+    "STP - Store partial",
+    "STC - Store conditional",
+    "STFIL1 - Store full, invalidate L1",
+    "STTIL1 - Store full, skip L2, invalidate L1",
+    "FAS32 - Atomic 32bit swap",
+    "FAS64 - Atomic 64bit swap",
+    "WBIL2i - Writeback, invalidate, by index/way",
+    "LTGL2i - Read tag@index/way",
+    "STGL2i - Write tag@index/way",
+    "RSVD27",
+    "INVL2 - Invalidate, by address",
+    "WBIL2 - Writeback, invalidate, by address",
+    "WBL2 - Writeback, by address",
+    "LCKL2 - Allocate, lock, by address",
+    "IOBLD8 - IOB 8bit load",
+    "IOBLD16 - IOB 16bit load",
+    "IOBLD32 - IOB 32bit load",
+    "IOBLD64 - IOB 64bit load",
+    "IOBST8 - IOB 8bit store",
+    "IOBST16 - IOB 16bit store",
+    "IOBST32 - IOB 32bit store",
+    "IOBST64 - IOB 64bit store",
+    "SET8 - 8bit Atomic swap with 1's",
+    "SET16 - 16bit Atomic swap with 1's",
+    "SET32 - 32bit Atomic swap with 1's",
+    "SET64 - 64bit Atomic swap with 1's",
+    "CLR8 - 8bit Atomic swap with 0's",
+    "CLR16 - 16bit Atomic swap with 0's",
+    "CLR32 - 32bit Atomic swap with 0's",
+    "CLR64 - 64bit Atomic swap with 0's",
+    "INCR8 - 8bit Atomic fetch & add by 1",
+    "INCR16 - 16bit Atomic fetch & add by 1",
+    "INCR32 - 32bit Atomic fetch & add by 1",
+    "INCR64 - 64bit Atomic fetch & add by 1",
+    "DECR8 - 8bit Atomic fetch & add by -1",
+    "DECR16 - 16bit Atomic fetch & add by -1",
+    "DECR32 - 32bit Atomic fetch & add by -1",
+    "DECR64 - 64bit Atomic fetch & add by -1",
+    "RSVD56",
+    "RSVD57",
+    "FAA32 - 32bit Atomic fetch and add",
+    "FAA64 - 64bit Atomic fetch and add",
+    "RSVD60",
+    "RSVD61",
+    "SAA32 - 32bit Atomic add",
+    "SAA64 - 64bit Atomic add"
+};
+
 static const char *SOURCE_ARRAY[] = {
     "PP0",
     "PP1",
@@ -124,7 +199,7 @@ static const char *DEST_ARRAY[] = {
     "CIU/GPIO",
     "RSVD1",
     "RSVD2",
-    "PCI/PCIe",
+    "PCI/PCIe/SLI",
     "KEY",
     "FPA",
     "DFA",
@@ -134,8 +209,8 @@ static const char *DEST_ARRAY[] = {
     "PKO",
     "RSVD11",
     "POW",
-    "RSVD13",
-    "RSVD14",
+    "USB0",
+    "RAD",
     "RSVD15",
     "RSVD16",
     "RSVD17",
@@ -148,13 +223,92 @@ static const char *DEST_ARRAY[] = {
     "RSVD24",
     "RSVD25",
     "RSVD26",
-    "RSVD27",
+    "DPI",
     "RSVD28",
     "RSVD29",
-    "RSVD30",
+    "FAU",
     "RSVD31"
 };
 
+#define CVMX_TRA_SOURCE_MASK       (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 0xf00ff : 0xfffff)
+#define CVMX_TRA_DESTINATION_MASK  0xfffffffful
+
+/**
+ * @INTERNAL
+ * Setup the trace buffer filter command mask. The bit position of filter commands
+ * are different for each Octeon model.
+ *
+ * @param filter    Which event to log
+ * @return          Bitmask of filter command based on the event.
+ */
+static uint64_t __cvmx_tra_set_filter_cmd_mask(cvmx_tra_filt_t filter)
+{
+    cvmx_tra_filt_cmd_t filter_command;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+    {
+        /* Bit positions of filter commands are different, map it accordingly */
+        uint64_t cmd = 0;
+        if ((filter & CVMX_TRA_FILT_ALL) == -1ull)
+        {
+            if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+                cmd = 0x1ffff;
+            else
+                cmd = 0xffff;
+        }
+        if (filter & CVMX_TRA_FILT_DWB)
+            cmd |= 1ull<<0;
+        if (filter & CVMX_TRA_FILT_PL2)
+            cmd |= 1ull<<1;
+        if (filter & CVMX_TRA_FILT_PSL1)
+            cmd |= 1ull<<2;
+        if (filter & CVMX_TRA_FILT_LDD)
+            cmd |= 1ull<<3;
+        if (filter & CVMX_TRA_FILT_LDI)
+            cmd |= 1ull<<4;
+        if (filter & CVMX_TRA_FILT_LDT)
+            cmd |= 1ull<<5;
+        if (filter & CVMX_TRA_FILT_STF)
+            cmd |= 1ull<<6;
+        if (filter & CVMX_TRA_FILT_STC)
+            cmd |= 1ull<<7;
+        if (filter & CVMX_TRA_FILT_STP)
+            cmd |= 1ull<<8;
+        if (filter & CVMX_TRA_FILT_STT)
+            cmd |= 1ull<<9;
+        if (filter & CVMX_TRA_FILT_IOBLD8)
+            cmd |= 1ull<<10;
+        if (filter & CVMX_TRA_FILT_IOBLD16)
+            cmd |= 1ull<<11;
+        if (filter & CVMX_TRA_FILT_IOBLD32)
+            cmd |= 1ull<<12;
+        if (filter & CVMX_TRA_FILT_IOBLD64)
+            cmd |= 1ull<<13;
+        if (filter & CVMX_TRA_FILT_IOBST)
+            cmd |= 1ull<<14;
+        if (filter & CVMX_TRA_FILT_IOBDMA)
+            cmd |= 1ull<<15;
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) && (filter & CVMX_TRA_FILT_SAA))
+            cmd |= 1ull<<16;
+
+        filter_command.u64 = cmd;
+    }
+    else
+    {
+        if ((filter & CVMX_TRA_FILT_ALL) == -1ull)
+            filter_command.u64 = CVMX_TRA_FILT_ALL;
+        else
+            filter_command.u64 = filter;
+
+        filter_command.cn63xx.reserved_60_61 = 0;
+        filter_command.cn63xx.reserved_56_57 = 0;
+        filter_command.cn63xx.reserved_10_14 = 0;
+        filter_command.cn63xx.reserved_6_7 = 0;
+    }
+    return filter_command.u64;
+}
+
+
 /**
  * Setup the TRA buffer for use
  *
@@ -168,17 +322,28 @@ static const char *DEST_ARRAY[] = {
  * @param address_mask
  *                Address mask
  */
-void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
-                    cvmx_tra_filt_sid_t source_filter, cvmx_tra_filt_did_t dest_filter,
+void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
+                    cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
                     uint64_t address, uint64_t address_mask)
 {
+    cvmx_tra_filt_cmd_t filt_cmd;
+    cvmx_tra_filt_sid_t filt_sid;
+    cvmx_tra_filt_did_t filt_did;
+
+    filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
+    filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
+    filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
+
     cvmx_write_csr(CVMX_TRA_CTL,            control.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_CMD,       filter.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_SID,       source_filter.u64);
-    cvmx_write_csr(CVMX_TRA_FILT_DID,       dest_filter.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_CMD,       filt_cmd.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_SID,       filt_sid.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_DID,       filt_did.u64);
     cvmx_write_csr(CVMX_TRA_FILT_ADR_ADR,   address);
     cvmx_write_csr(CVMX_TRA_FILT_ADR_MSK,   address_mask);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_setup);
+#endif
 
 
 /**
@@ -195,16 +360,27 @@ void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
  * @param address_mask
  *                Trigger address mask
  */
-void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
-                         cvmx_tra_filt_sid_t source_filter, cvmx_tra_trig0_did_t dest_filter,
+void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
+                         cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
                          uint64_t address, uint64_t address_mask)
 {
-    cvmx_write_csr(CVMX_TRA_TRIG0_CMD + trigger * 64,       filter.u64);
-    cvmx_write_csr(CVMX_TRA_TRIG0_SID + trigger * 64,       source_filter.u64);
-    cvmx_write_csr(CVMX_TRA_TRIG0_DID + trigger * 64,       dest_filter.u64);
+    cvmx_tra_filt_cmd_t tra_filt_cmd;
+    cvmx_tra_filt_sid_t tra_filt_sid;
+    cvmx_tra_filt_did_t tra_filt_did;
+
+    tra_filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter);
+    tra_filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK;
+    tra_filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK;
+
+    cvmx_write_csr(CVMX_TRA_TRIG0_CMD + trigger * 64,       tra_filt_cmd.u64);
+    cvmx_write_csr(CVMX_TRA_TRIG0_SID + trigger * 64,       tra_filt_sid.u64);
+    cvmx_write_csr(CVMX_TRA_TRIG0_DID + trigger * 64,       tra_filt_did.u64);
     cvmx_write_csr(CVMX_TRA_TRIG0_ADR_ADR + trigger * 64,   address);
     cvmx_write_csr(CVMX_TRA_TRIG0_ADR_MSK + trigger * 64,   address_mask);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_trig_setup);
+#endif
 
 
 /**
@@ -214,12 +390,26 @@ void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
  */
 cvmx_tra_data_t cvmx_tra_read(void)
 {
+    uint64_t address = CVMX_TRA_READ_DAT;
     cvmx_tra_data_t result;
-    result.u64 = cvmx_read_csr(CVMX_TRA_READ_DAT);
+
+    /* The trace buffer format is wider than 64-bits in Octeon2 model,
+       read the register again to get the second part of the data. */
+    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN5XXX))
+    {
+        /* These reads need to be as close as possible to each other */
+        result.u128.data = cvmx_read_csr(address);
+        result.u128.datahi = cvmx_read_csr(address);
+    }
+    else
+    {
+        result.u128.data = cvmx_read_csr(address);
+        result.u128.datahi = 0;
+    }
+
     return result;
 }
 
-
 /**
  * Decode a TRA entry into human readable output
  *
@@ -228,48 +418,52 @@ cvmx_tra_data_t cvmx_tra_read(void)
  */
 void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
 {
-    /* The type is a five bit field for some entries and 4 for other. The four
-        bit entries can be mis-typed if the top is set */
-    int type = data.cmn.type;
-    if (type >= 0x1a)
-        type &= 0xf;
-    switch (type)
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
     {
-        case CVMX_TRA_DATA_DWB:
-        case CVMX_TRA_DATA_PL2:
-        case CVMX_TRA_DATA_PSL1:
-        case CVMX_TRA_DATA_LDD:
-        case CVMX_TRA_DATA_LDI:
-        case CVMX_TRA_DATA_LDT:
-            cvmx_dprintf("0x%016llx %c%+10d %s %s 0x%016llx\n",
-                   (unsigned long long)data.u64,
-                   (data.cmn.discontinuity) ? 'D' : ' ',
-                   data.cmn.timestamp << (tra_ctl.s.time_grn*3),
-                   TYPE_ARRAY[type],
-                   SOURCE_ARRAY[data.cmn.source],
-                   (unsigned long long)data.cmn.address);
-            break;
-        case CVMX_TRA_DATA_STC:
-        case CVMX_TRA_DATA_STF:
-        case CVMX_TRA_DATA_STP:
-        case CVMX_TRA_DATA_STT:
-        case CVMX_TRA_DATA_SAA:
-            cvmx_dprintf("0x%016llx %c%+10d %s %s mask=0x%02x 0x%016llx\n",
-                   (unsigned long long)data.u64,
+        /* The type is a five bit field for some entries and 4 for other. The four
+           bit entries can be mis-typed if the top is set */
+        int type = data.cmn.type;
+
+        if (type >= 0x1a)
+            type &= 0xf;
+
+        switch (type)
+        {
+            case 0:  /* DWB */
+            case 1:  /* PL2 */
+            case 2:  /* PSL1 */
+            case 3:  /* LDD */
+            case 4:  /* LDI */
+            case 5:  /* LDT */
+                cvmx_dprintf("0x%016llx %c%+10d %s %s 0x%016llx\n",
+                    (unsigned long long)data.u128.data,
+                    (data.cmn.discontinuity) ? 'D' : ' ',
+                    data.cmn.timestamp << (tra_ctl.s.time_grn*3),
+                    TYPE_ARRAY[type],
+                    SOURCE_ARRAY[data.cmn.source],
+                    (unsigned long long)data.cmn.address);
+                break;
+            case 6:  /* STF */
+            case 7:  /* STC */
+            case 8:  /* STP */
+            case 9:  /* STT */
+            case 16: /* SAA */
+                cvmx_dprintf("0x%016llx %c%+10d %s %s mask=0x%02x 0x%016llx\n",
+                   (unsigned long long)data.u128.data,
                    (data.cmn.discontinuity) ? 'D' : ' ',
                    data.cmn.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY[type],
                    SOURCE_ARRAY[data.store.source],
                    (unsigned int)data.store.mask,
                    (unsigned long long)data.store.address << 3);
-            break;
-        case CVMX_TRA_DATA_IOBLD8:
-        case CVMX_TRA_DATA_IOBLD16:
-        case CVMX_TRA_DATA_IOBLD32:
-        case CVMX_TRA_DATA_IOBLD64:
-        case CVMX_TRA_DATA_IOBST:
-            cvmx_dprintf("0x%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx\n",
-                   (unsigned long long)data.u64,
+                break;
+            case 10:  /* IOBLD8 */
+            case 11:  /* IOBLD16 */
+            case 12:  /* IOBLD32 */
+            case 13:  /* IOBLD64 */
+            case 14:  /* IOBST */
+                cvmx_dprintf("0x%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx\n",
+                   (unsigned long long)data.u128.data,
                    (data.cmn.discontinuity) ? 'D' : ' ',
                    data.cmn.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY[type],
@@ -277,10 +471,10 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
                    DEST_ARRAY[data.iobld.dest],
                    (unsigned int)data.iobld.subid,
                    (unsigned long long)data.iobld.address);
-            break;
-        case CVMX_TRA_DATA_IOBDMA:
-            cvmx_dprintf("0x%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx\n",
-                   (unsigned long long)data.u64,
+                break;
+            case 15:  /* IOBDMA */
+                cvmx_dprintf("0x%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx\n",
+                   (unsigned long long)data.u128.data,
                    (data.cmn.discontinuity) ? 'D' : ' ',
                    data.cmn.timestamp << (tra_ctl.s.time_grn*3),
                    TYPE_ARRAY[type],
@@ -288,16 +482,116 @@ void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
                    DEST_ARRAY[data.iob.dest],
                    (unsigned int)data.iob.mask,
                    (unsigned long long)data.iob.address << 3);
-            break;
-        default:
-            cvmx_dprintf("0x%016llx %c%+10d Unknown format\n",
-                   (unsigned long long)data.u64,
+                break;
+            default:
+                cvmx_dprintf("0x%016llx %c%+10d Unknown format\n",
+                   (unsigned long long)data.u128.data,
                    (data.cmn.discontinuity) ? 'D' : ' ',
                    data.cmn.timestamp << (tra_ctl.s.time_grn*3));
-            break;
+                break;
+        }
     }
-}
+    else
+    {
+        int type;
 
+        type = data.cmn2.type;
+
+        switch (1ull<<type)
+        {
+            case CVMX_TRA_FILT_DECR64:
+            case CVMX_TRA_FILT_DECR32:
+            case CVMX_TRA_FILT_DECR16:
+            case CVMX_TRA_FILT_DECR8:
+            case CVMX_TRA_FILT_INCR64:
+            case CVMX_TRA_FILT_INCR32:
+            case CVMX_TRA_FILT_INCR16:
+            case CVMX_TRA_FILT_INCR8:
+            case CVMX_TRA_FILT_CLR64:
+            case CVMX_TRA_FILT_CLR32:
+            case CVMX_TRA_FILT_CLR16:
+            case CVMX_TRA_FILT_CLR8:
+            case CVMX_TRA_FILT_SET64:
+            case CVMX_TRA_FILT_SET32:
+            case CVMX_TRA_FILT_SET16:
+            case CVMX_TRA_FILT_SET8:
+            case CVMX_TRA_FILT_WBL2:
+            case CVMX_TRA_FILT_DWB:
+            case CVMX_TRA_FILT_RPL2:
+            case CVMX_TRA_FILT_PL2:
+            case CVMX_TRA_FILT_LDI:
+            case CVMX_TRA_FILT_LDT:
+                cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s 0x%016llx%llx\n",
+                   (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
+                   (data.cmn2.discontinuity) ? 'D' : ' ',
+                   data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY2[type],
+                   SOURCE_ARRAY[data.cmn2.source],
+                   (unsigned long long)data.cmn2.addresshi,
+                   (unsigned long long)data.cmn2.addresslo);
+                break;
+            case CVMX_TRA_FILT_PSL1:
+            case CVMX_TRA_FILT_LDD:
+            case CVMX_TRA_FILT_FAS64:
+            case CVMX_TRA_FILT_FAS32:
+            case CVMX_TRA_FILT_FAA64:
+            case CVMX_TRA_FILT_FAA32:
+            case CVMX_TRA_FILT_SAA64:
+            case CVMX_TRA_FILT_SAA32:
+            case CVMX_TRA_FILT_STC:
+            case CVMX_TRA_FILT_STF:
+            case CVMX_TRA_FILT_STP:
+            case CVMX_TRA_FILT_STT:
+                cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s mask=0x%02x 0x%016llx%llx\n",
+                   (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
+                   (data.cmn2.discontinuity) ? 'D' : ' ',
+                   data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY2[type],
+                   SOURCE_ARRAY[data.store2.source],
+                   (unsigned int)data.store2.mask,
+                   (unsigned long long)data.store2.addresshi,
+                   (unsigned long long)data.store2.addresslo);
+                break;
+            case CVMX_TRA_FILT_IOBST64:
+            case CVMX_TRA_FILT_IOBST32:
+            case CVMX_TRA_FILT_IOBST16:
+            case CVMX_TRA_FILT_IOBST8:
+            case CVMX_TRA_FILT_IOBLD64:
+            case CVMX_TRA_FILT_IOBLD32:
+            case CVMX_TRA_FILT_IOBLD16:
+            case CVMX_TRA_FILT_IOBLD8:
+                cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx%llx\n",
+                   (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
+                   (data.cmn2.discontinuity) ? 'D' : ' ',
+                   data.cmn2.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY2[type],
+                   SOURCE_ARRAY[data.iobld2.source],
+                   DEST_ARRAY[data.iobld2.dest],
+                   (unsigned int)data.iobld2.subid,
+                   (unsigned long long)data.iobld2.addresshi,
+                   (unsigned long long)data.iobld2.addresslo);
+                break;
+            case CVMX_TRA_FILT_IOBDMA:
+                cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx%llx\n",
+                   (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
+                   (data.iob2.discontinuity) ? 'D' : ' ',
+                   data.iob2.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY2[type],
+                   SOURCE_ARRAY[data.iob2.source],
+                   DEST_ARRAY[data.iob2.dest],
+                   (unsigned int)data.iob2.mask,
+                   (unsigned long long)data.iob2.addresshi << 3,
+                   (unsigned long long)data.iob2.addresslo << 3);
+                break;
+            default:
+                cvmx_dprintf("0x%016llx%016llx %c%+10d Unknown format\n",
+                   (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data,
+                   (data.cmn2.discontinuity) ? 'D' : ' ',
+                   data.cmn2.timestamp << (tra_ctl.s.time_grn*3));
+                break;
+        }
+    }
+}
 
 /**
  * Display the entire trace buffer. It is advised that you
@@ -309,14 +603,25 @@ void cvmx_tra_display(void)
 {
     cvmx_tra_ctl_t tra_ctl;
     cvmx_tra_data_t data;
+    int valid = 0;
 
     tra_ctl.u64 = cvmx_read_csr(CVMX_TRA_CTL);
 
     do
     {
         data = cvmx_tra_read();
-        if (data.cmn.valid)
+        if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) && data.cmn.valid)
+            valid = 1;
+        else if (data.cmn2.valid)
+            valid = 1;
+        else
+            valid = 0;
+
+        if (valid)
             cvmx_tra_decode_text(tra_ctl, data);
-    } while (data.cmn.valid);
-}
 
+    } while (valid);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_tra_display);
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-tra.h b/sys/contrib/octeon-sdk/cvmx-tra.h
index 709fde8..74f6192 100644
--- a/sys/contrib/octeon-sdk/cvmx-tra.h
+++ b/sys/contrib/octeon-sdk/cvmx-tra.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -42,6 +43,7 @@
 
 
 
+
 /**
  * @file
  *
@@ -69,6 +71,11 @@
  * Each entry of the trace buffer is read by a CSR read command.  The trace buffer services each read in order,
  * as soon as it has access to the (single-ported) trace buffer.
  *
+ * On Octeon2, each entry of the trace buffer is read by two CSR memory read operations.  The first read accesses
+ * bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer
+ * services each read in order, as soon as it has access to the (single-ported) trace buffer.  Buffer's read pointer
+ * increments after two CSR memory read operations.
+ *
  *
  * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
  *
@@ -125,7 +132,23 @@
  * |sta|                     * or address[35:3]                          | * or length   | src id| dest id |IOBDMA | diff timestamp|
  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  *
+ *
+ * Trace buffer entry format in Octeon2 is different
+ *
+ *                 6                   5                   4                   3                   2                   1                   0
+ * 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[37:0]                                  |       0           |  src id |  Group 1    | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[37:0]                                  | 0 |  xmd mask     |  src id |  Group 2    | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[37:0]                                  | 0 |s-did| dest id |  src id |  Group 3    | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                         *address[37:3]                            | *Length       | dest id |  src id |  Group 4    | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
  * notes:
+ * - diff timestamp is the difference in time from the previous trace event to this event - 1.  the granularity of the timestamp is programmable
  * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time.  Note that the
  * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
  * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
@@ -139,8 +162,8 @@
  * 0x3=LDD
  * 0x4=LDI
  * 0x5=LDT
- * 0x6=STC
- * 0x7=STF
+ * 0x6=STF
+ * 0x7=STC
  * 0x8=STP
  * 0x9=STT
  * 0xa=IOBLD8
@@ -149,6 +172,24 @@
  * 0xd=IOBLD64
  * 0xe=IOBST
  * 0xf=IOBDMA
+ * - In Octeon2 the commands are grouped as follows:
+ * Group1:
+ *   XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2,
+ *   XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64,
+ *   XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64,
+ *   XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64,
+ *   XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64
+ * Group2:
+ *   XMC_STF, XMC_STT, XMC_STP, XMC_STC,
+ *   XMC_LDD, XMC_PSL1
+ *   XMC_SAA32, XMC_SAA64,
+ *   XMC_FAA32, XMC_FAA64,
+ *   XMC_FAS32, XMC_FAS64
+ * Group3:
+ *   XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64,
+ *   XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64
+ * Group4:
+ *   XMC_IOBDMA
  * - For non IOB* commands
  * - source id is encoded as follows:
  * 0x00-0x0f=PP[n]
@@ -158,133 +199,234 @@
  * 0x13=IOB(DWB)
  * 0x14-0x1e=illegal
  * 0x1f=IOB(generic)
- * - dest   id is unused (can only be L2c)
+ * - dest id is unused (can only be L2c)
  * - For IOB* commands
  * - source id is encoded as follows:
  * 0x00-0x0f = PP[n]
  * - dest   id is encoded as follows:
- * 0x00-0x0f=PP[n]
- * 0x10=IOB(Packet)
- * 0x11=IOB(PKO)
- * 0x12=IOB(ReqLoad, ReqStore)
- * 0x13=IOB(DWB)
- * 0x14-0x1e=illegal
- * 0x1f=IOB(generic)
- *
- * Source of data for each command
- * command source id    dest id      address                 length/mask
- * -------+------------+------------+-----------------------+----------------------------------------------
- * LDI     xmc_sid[8:3] x            xmc_adr[35:3]           x
- * LDT     xmc_sid[8:3] x            xmc_adr[35:3]           x
- * STF     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
- * STC     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
- * STP     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
- * STT     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
- * DWB     xmc_sid[8:3] x            xmc_adr[35:3]           x
- * PL2     xmc_sid[8:3] x            xmc_adr[35:3]           x
- * PSL1    xmc_sid[8:3] x            xmc_adr[35:3]           x
- * IOBLD8  xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:0]           x
- * IOBLD16 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:1]           x
- * IOBLD32 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:2]           x
- * IOBLD64 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3]           x
- * IOBST   xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
- * IOBDMA  xmc_sid[8:3] xmc_did[8:3] (xmd_[wrval,eow,dat[]]) length(xmd_[wrval,eow,dat[]])
- * IOBRSP  not traced, but monitored to keep XMC and XMD data in sync.
+ * 0   = CIU/GPIO (for CSRs)
+ * 1-2 = illegal
+ * 3   = PCIe (access to RSL-type CSRs)
+ * 4   = KEY (read/write operations)
+ * 5   = FPA (free pool allocate/free operations)
+ * 6   = DFA
+ * 7   = ZIP (doorbell operations)
+ * 8   = RNG (load/IOBDMA operations)
+ * 10  = PKO (doorbell operations)
+ * 11  = illegal
+ * 12  = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations)
+ * 13-31 = illegal
  * @endverbatim
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49484 $<hr>
  */
 
 #ifndef __CVMX_TRA_H__
 #define __CVMX_TRA_H__
 
 #include "cvmx.h"
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-tra-defs.h"
+#endif
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-tra-defs.h */
+
+/* The 'saa' filter command is renamed as 'saa64' */
+#define CVMX_TRA_FILT_SAA       CVMX_TRA_FILT_SAA64
+/* The 'iobst' filter command is renamed as 'iobst64' */
+#define CVMX_TRA_FILT_IOBST     CVMX_TRA_FILT_IOBST64
 
 /**
- * Enumeration of the data types stored in cvmx_tra_data_t
+ * Enumeration of the bitmask of all the filter commands. The bit positions
+ * correspond to Octeon2 model.
+ */
+typedef enum
+{
+    CVMX_TRA_FILT_NOP     = 1ull<<0,  /**< none */
+    CVMX_TRA_FILT_LDT     = 1ull<<1,  /**< don't allocate L2 or L1 */
+    CVMX_TRA_FILT_LDI     = 1ull<<2,  /**< don't allocate L1 */
+    CVMX_TRA_FILT_PL2     = 1ull<<3,  /**< pref L2 */
+    CVMX_TRA_FILT_RPL2    = 1ull<<4,  /**< mark for replacement in L2 */
+    CVMX_TRA_FILT_DWB     = 1ull<<5,  /**< clear L2 dirty bit (no writeback) + RPL2 */
+    CVMX_TRA_FILT_LDD     = 1ull<<8,  /**< normal load */
+    CVMX_TRA_FILT_PSL1    = 1ull<<9,  /**< pref L1, bypass L2 */
+    CVMX_TRA_FILT_IOBDMA  = 1ull<<15,  /**< store reflection by IOB for prior load */
+    CVMX_TRA_FILT_STF     = 1ull<<16, /**< full block store to L2, fill 0's */
+    CVMX_TRA_FILT_STT     = 1ull<<17, /**< full block store bypass-L2, fill 0's */
+    CVMX_TRA_FILT_STP     = 1ull<<18, /**< partial store to L2 */
+    CVMX_TRA_FILT_STC     = 1ull<<19, /**< partial store to L2, if duptag valid */
+    CVMX_TRA_FILT_STFIL1  = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */
+    CVMX_TRA_FILT_STTIL1  = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */
+    CVMX_TRA_FILT_FAS32   = 1ull<<22, /**< to load from and write a word of memory atomically */
+    CVMX_TRA_FILT_FAS64   = 1ull<<23, /**< to load from and write a doubleword of memory atomically */
+    CVMX_TRA_FILT_WBIL2I  = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */
+    CVMX_TRA_FILT_LTGL2I  = 1ull<<25, /**< read tag @ index/way into CSR */
+    CVMX_TRA_FILT_STGL2I  = 1ull<<26, /**< write tag @ index/way from CSR */
+    CVMX_TRA_FILT_INVL2   = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */
+    CVMX_TRA_FILT_WBIL2   = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */
+    CVMX_TRA_FILT_WBL2    = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */
+    CVMX_TRA_FILT_LCKL2   = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */
+    CVMX_TRA_FILT_IOBLD8  = 1ull<<32, /**< load reflection 8bit */
+    CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */
+    CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */
+    CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */
+    CVMX_TRA_FILT_IOBST8  = 1ull<<36, /**< store reflection 8bit */
+    CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */
+    CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */
+    CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */
+    CVMX_TRA_FILT_SET8    = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */
+    CVMX_TRA_FILT_SET16   = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */
+    CVMX_TRA_FILT_SET32   = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */
+    CVMX_TRA_FILT_SET64   = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */
+    CVMX_TRA_FILT_CLR8    = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */
+    CVMX_TRA_FILT_CLR16   = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */
+    CVMX_TRA_FILT_CLR32   = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */
+    CVMX_TRA_FILT_CLR64   = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */
+    CVMX_TRA_FILT_INCR8   = 1ull<<48, /**< to load and increment 8bit of memory atomically */
+    CVMX_TRA_FILT_INCR16  = 1ull<<49, /**< to load and increment 16bit of memory atomically */
+    CVMX_TRA_FILT_INCR32  = 1ull<<50, /**< to load and increment 32bit of memory atomically */
+    CVMX_TRA_FILT_INCR64  = 1ull<<51, /**< to load and increment 64bit of memory atomically */
+    CVMX_TRA_FILT_DECR8   = 1ull<<52, /**< to load and decrement 8bit of memory atomically */
+    CVMX_TRA_FILT_DECR16  = 1ull<<53, /**< to load and decrement 16bit of memory atomically */
+    CVMX_TRA_FILT_DECR32  = 1ull<<54, /**< to load and decrement 32bit of memory atomically */
+    CVMX_TRA_FILT_DECR64  = 1ull<<55, /**< to load and decrement 64bit of memory atomically */
+    CVMX_TRA_FILT_FAA32   = 1ull<<58, /**< to load from and add to a word of memory atomically */
+    CVMX_TRA_FILT_FAA64   = 1ull<<59, /**< to load from and add to a doubleword of memory atomically  */
+    CVMX_TRA_FILT_SAA32   = 1ull<<62, /**< to atomically add a word to a memory location */
+    CVMX_TRA_FILT_SAA64   = 1ull<<63, /**< to atomically add a doubleword to a memory location */
+    CVMX_TRA_FILT_ALL     = -1ull     /**< all the above filter commands */
+} cvmx_tra_filt_t;
+
+/*
+ * Enumeration of the bitmask of all source commands.
  */
 typedef enum
 {
-    CVMX_TRA_DATA_DWB       = 0x0,
-    CVMX_TRA_DATA_PL2       = 0x1,
-    CVMX_TRA_DATA_PSL1      = 0x2,
-    CVMX_TRA_DATA_LDD       = 0x3,
-    CVMX_TRA_DATA_LDI       = 0x4,
-    CVMX_TRA_DATA_LDT       = 0x5,
-    CVMX_TRA_DATA_STC       = 0x6,
-    CVMX_TRA_DATA_STF       = 0x7,
-    CVMX_TRA_DATA_STP       = 0x8,
-    CVMX_TRA_DATA_STT       = 0x9,
-    CVMX_TRA_DATA_IOBLD8    = 0xa,
-    CVMX_TRA_DATA_IOBLD16   = 0xb,
-    CVMX_TRA_DATA_IOBLD32   = 0xc,
-    CVMX_TRA_DATA_IOBLD64   = 0xd,
-    CVMX_TRA_DATA_IOBST     = 0xe,
-    CVMX_TRA_DATA_IOBDMA    = 0xf,
-    CVMX_TRA_DATA_SAA       = 0x10,
-} cvmx_tra_data_type_t;
+    CVMX_TRA_SID_PP0      = 1ull<<0,  /**< Enable tracing from PP0 with matching sourceID */
+    CVMX_TRA_SID_PP1      = 1ull<<1,  /**< Enable tracing from PP1 with matching sourceID */
+    CVMX_TRA_SID_PP2      = 1ull<<2,  /**< Enable tracing from PP2 with matching sourceID */
+    CVMX_TRA_SID_PP3      = 1ull<<3,  /**< Enable tracing from PP3 with matching sourceID */
+    CVMX_TRA_SID_PP4      = 1ull<<4,  /**< Enable tracing from PP4 with matching sourceID */
+    CVMX_TRA_SID_PP5      = 1ull<<5,  /**< Enable tracing from PP5 with matching sourceID */
+    CVMX_TRA_SID_PP6      = 1ull<<6,  /**< Enable tracing from PP6 with matching sourceID */
+    CVMX_TRA_SID_PP7      = 1ull<<7,  /**< Enable tracing from PP7 with matching sourceID */
+    CVMX_TRA_SID_PP8      = 1ull<<8,  /**< Enable tracing from PP8 with matching sourceID */
+    CVMX_TRA_SID_PP9      = 1ull<<9,  /**< Enable tracing from PP9 with matching sourceID */
+    CVMX_TRA_SID_PP10     = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */
+    CVMX_TRA_SID_PP11     = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */
+    CVMX_TRA_SID_PP12     = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */
+    CVMX_TRA_SID_PP13     = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */
+    CVMX_TRA_SID_PP14     = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */
+    CVMX_TRA_SID_PP15     = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */
+    CVMX_TRA_SID_PKI      = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */
+    CVMX_TRA_SID_PKO      = 1ull<<17, /**< Enable tracing of write requests from PKO */
+    CVMX_TRA_SID_IOBREQ   = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */
+    CVMX_TRA_SID_DWB      = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */
+    CVMX_TRA_SID_ALL      = -1ull     /**< Enable tracing all the above source commands */
+} cvmx_tra_sid_t;
+
+
+#define CVMX_TRA_DID_SLI  CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */
+/*
+ * Enumeration of the bitmask of all destination commands.
+ */
+typedef enum
+{
+    CVMX_TRA_DID_MIO      = 1ull<<0,  /**< Enable tracing of CIU and GPIO CSR's */
+    CVMX_TRA_DID_PCI      = 1ull<<3,  /**< Enable tracing of requests to PCI and RSL type CSR's */
+    CVMX_TRA_DID_KEY      = 1ull<<4,  /**< Enable tracing of requests to KEY memory */
+    CVMX_TRA_DID_FPA      = 1ull<<5,  /**< Enable tracing of requests to FPA */
+    CVMX_TRA_DID_DFA      = 1ull<<6,  /**< Enable tracing of requests to DFA */
+    CVMX_TRA_DID_ZIP      = 1ull<<7,  /**< Enable tracing of requests to ZIP */
+    CVMX_TRA_DID_RNG      = 1ull<<8,  /**< Enable tracing of requests to RNG */
+    CVMX_TRA_DID_IPD      = 1ull<<9,  /**< Enable tracing of IPD CSR accesses */
+    CVMX_TRA_DID_PKO      = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */
+    CVMX_TRA_DID_POW      = 1ull<<12, /**< Enable tracing of requests to RNG */
+    CVMX_TRA_DID_USB0     = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */
+    CVMX_TRA_DID_RAD      = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */
+    CVMX_TRA_DID_DPI      = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */
+    CVMX_TRA_DID_FAU      = 1ull<<30, /**< Enable tracing FAU accesses */
+    CVMX_TRA_DID_ALL      = -1ull     /**< Enable tracing all the above destination commands */
+} cvmx_tra_did_t;
 
 /**
  * TRA data format definition. Use the type field to
  * determine which union element to use.
+ *
+ * In Octeon 2, the trace buffer is 69 bits,
+ * the first read accesses bits 63:0 of the trace buffer entry, and
+ * the second read accesses bits 68:64 of the trace buffer entry.
  */
 typedef union
 {
-    uint64_t u64;
     struct
     {
 #if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t  datahi;
+        uint64_t  data;
+#else
+        uint64_t  data;
+        uint64_t  datahi;
+#endif
+    } u128;
+
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
         uint64_t    address     : 36;
         uint64_t    reserved    : 5;
         uint64_t    source      : 5;
         uint64_t    reserved2   : 3;
-        cvmx_tra_data_type_t type:5;
+        uint64_t    type        : 5;
         uint64_t    timestamp   : 8;
 #else
         uint64_t    timestamp   : 8;
-        cvmx_tra_data_type_t type:5;
+        uint64_t    type        : 5;
         uint64_t    reserved2   : 3;
         uint64_t    source      : 5;
         uint64_t    reserved    : 5;
         uint64_t    address     : 36;
         uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    reserved3   : 64;
 #endif
     } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
     struct
     {
 #if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
         uint64_t    address     : 33;
         uint64_t    mask        : 8;
         uint64_t    source      : 5;
         uint64_t    reserved2   : 3;
-        cvmx_tra_data_type_t type:5;
+        uint64_t    type        : 5;
         uint64_t    timestamp   : 8;
 #else
         uint64_t    timestamp   : 8;
-        cvmx_tra_data_type_t type:5;
+        uint64_t    type        : 5;
         uint64_t    reserved2   : 3;
         uint64_t    source      : 5;
         uint64_t    mask        : 8;
         uint64_t    address     : 33;
         uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    reserved3   : 64;
 #endif
     } store; /**< STC, STF, STP, STT */
     struct
     {
 #if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
         uint64_t    address     : 36;
@@ -304,11 +446,13 @@ typedef union
         uint64_t    address     : 36;
         uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    reserved3   : 64;
 #endif
     } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
     struct
     {
 #if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved3   : 64;
         uint64_t    valid       : 1;
         uint64_t    discontinuity:1;
         uint64_t    address     : 33;
@@ -326,8 +470,114 @@ typedef union
         uint64_t    address     : 33;
         uint64_t    discontinuity:1;
         uint64_t    valid       : 1;
+        uint64_t    reserved3   : 64;
 #endif
     } iob; /**< for IOBDMA */
+
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved1   : 59;
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
+        uint64_t    addresslo   : 35;  /* and lower 64-bits. */
+        uint64_t    reserved    : 10;
+        uint64_t    source      : 5;
+        uint64_t    type        : 6;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 6;
+        uint64_t    source      : 5;
+        uint64_t    reserved    : 10;
+        uint64_t    addresslo   : 35;
+        uint64_t    addresshi   : 3;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+        uint64_t    reserved1   : 59;
+#endif
+    } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, SET*, CLR*, INCR*, DECR* */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved1   : 59;
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
+        uint64_t    addresslo   : 35;  /* and lower 64-bits */
+        uint64_t    reserved    : 2;
+        uint64_t    mask        : 8;
+        uint64_t    source      : 5;
+        uint64_t    type        : 6;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 6;
+        uint64_t    source      : 5;
+        uint64_t    mask        : 8;
+        uint64_t    reserved    : 2;
+        uint64_t    addresslo   : 35;
+        uint64_t    addresshi   : 3;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+        uint64_t    reserved1   : 59;
+#endif
+    } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64 */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved1   : 59;
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
+        uint64_t    addresslo   : 35;  /* and lower 64-bits */
+        uint64_t    reserved    : 2;
+        uint64_t    subid       : 3;
+        uint64_t    dest        : 5;
+        uint64_t    source      : 5;
+        uint64_t    type        : 6;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 6;
+        uint64_t    source      : 5;
+        uint64_t    dest        : 5;
+        uint64_t    subid       : 3;
+        uint64_t    reserved    : 2;
+        uint64_t    addresslo   : 35;
+        uint64_t    addresshi   : 3;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+        uint64_t    reserved1   : 59;
+#endif
+    } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved1   : 59;
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    addresshi   : 3;   /* Split the address to fit in upper 64 bits  */
+        uint64_t    addresslo   : 32;  /* and lower 64-bits */
+        uint64_t    mask        : 8;
+        uint64_t    dest        : 5;
+        uint64_t    source      : 5;
+        uint64_t    type        : 6;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 6;
+        uint64_t    source      : 5;
+        uint64_t    dest        : 5;
+        uint64_t    mask        : 8;
+        uint64_t    addresslo   : 32;
+	uint64_t    addresshi   : 3;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+        uint64_t    reserved1   : 59;
+#endif
+    } iob2; /**< for IOBDMA */
 } cvmx_tra_data_t;
 
 
@@ -344,8 +594,8 @@ typedef union
  * @param address_mask
  *                Address mask
  */
-extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
-                           cvmx_tra_filt_sid_t source_filter, cvmx_tra_filt_did_t dest_filter,
+extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
+                           cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
                            uint64_t address, uint64_t address_mask);
 
 /**
@@ -362,12 +612,13 @@ extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
  * @param address_mask
  *                Trigger address mask
  */
-extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
-                                cvmx_tra_filt_sid_t source_filter, cvmx_tra_trig0_did_t dest_filter,
+extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
+                                cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
                                 uint64_t address, uint64_t address_mask);
 
 /**
- * Read an entry from the TRA buffer
+ * Read an entry from the TRA buffer. The trace buffer format is
+ * different in Octeon2, need to read twice from TRA_READ_DAT.
  *
  * @return Value return. High bit will be zero if there wasn't any data
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi-raw.c b/sys/contrib/octeon-sdk/cvmx-twsi-raw.c
deleted file mode 100644
index 0b82325..0000000
--- a/sys/contrib/octeon-sdk/cvmx-twsi-raw.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
- *
- * This software file (the "File") is owned and distributed by Cavium
- * Networks ("Cavium") under the following dual licensing option: The dual
- * licensing option gives you, the licensee, the choice between the following
- * alternative licensing terms.  Once you have made an election to use the
- * File under one of the following alternative licensing terms (license
- * types) you are bound by the respective terms and you may distribute the
- * file (or any derivative thereof), to the extent allowed by the respective
- * licensing term, only if you (i) delete this introductory statement
- * regarding the dual licensing option from the file you will distribute,
- * (ii) delete the licensing term that you have elected NOT to use from the
- * file you will distribute and (iii) follow the respective licensing term
- * that you have elected to use with respect to the correct attribution or
- * licensing term that you have to include with your distribution.
- *
- * ***
- * OCTEON SDK License Type 2:
- *
- * IMPORTANT: Read this Agreement carefully before clicking on the "I accept"
- * button to download the Software and/or before using the Software.  This
- * License Agreement (the "Agreement") is a legal agreement between you,
- * either an individual or a single legal entity ("You" or "you"), and Cavium
- * Networks ("Cavium").  This Agreement governs your use of the Cavium
- * software that can be downloaded after accepting this Agreement and/or that
- * is accompanied by this Agreement (the "Software").  You must accept the
- * terms of this Agreement before downloading and/or using the Software.  By
- * clicking on the "I accept" button to download and/or by using the
- * Software, you are indicating that you have read and understood, and assent
- * to be bound by, the terms of this Agreement.  If you do not agree to the
- * terms of the Agreement, you are not granted any rights whatsoever in the
- * Software.  If you are not willing to be bound by these terms and
- * conditions, you should not use or cease all use of the Software.  This
- * Software is the property of Cavium Networks and constitutes the
- * proprietary information of Cavium Networks.  You agree to take reasonable
- * steps to prevent the disclosure, unauthorized use or unauthorized
- * distribution of the Software to any third party.
- *
- * License Grant.  Subject to the terms and conditions of this Agreement,
- * Cavium grants you a nonexclusive, non-transferable, worldwide, fully-paid
- * and royalty-free license to
- *
- * (a) install, reproduce, and execute the executable version of the Software
- * solely for your internal use and only (a) on hardware manufactured by
- * Cavium, or (b) software of Cavium that simulates Cavium hardware;
- *
- * (b) create derivative works of any portions of the Software provided to
- * you by Cavium in source code form, which portions enable features of the
- * Cavium hardware products you or your licensees are entitled to use,
- * provided that any such derivative works must be used only (a) on hardware
- * manufactured by Cavium, or (b) software of Cavium that simulates Cavium
- * hardware; and
- *
- * (c) distribute derivative works you created in accordance with clause (b)
- * above, only in executable form and only if such distribution (i)
- * reproduces the copyright notice that can be found at the very end of this
- * Agreement and (ii) is pursuant to a binding license agreement that
- * contains terms no less restrictive and no less protective of Cavium than
- * this Agreement.  You will immediately notify Cavium if you become aware of
- * any breach of any such license agreement.
- *
- * Restrictions.  The rights granted to you in this Agreement are subject to
- * the following restrictions: Except as expressly set forth in this
- * Agreement (a) you will not license, sell, rent, lease, transfer, assign,
- * display, host, outsource, disclose or otherwise commercially exploit or
- * make the Software, or any derivatives you create under this Agreement,
- * available to any third party; (b) you will not modify or create derivative
- * works of any part of the Software; (c) you will not access or use the
- * Software in order to create similar or competitive products, components,
- * or services; and (d), no part of the Software may be copied (except for
- * the making of a single archival copy), reproduced, distributed,
- * republished, downloaded, displayed, posted or transmitted in any form or
- * by any means.
- *
- * Ownership.  You acknowledge and agree that, subject to the license grant
- * contained in this Agreement and as between you and Cavium (a) Cavium owns
- * all copies of and intellectual property rights to the Software, however
- * made, and retains all rights in and to the Software, including all
- * intellectual property rights therein, and (b) you own all the derivate
- * works of the Software created by you under this Agreement, subject to
- * Cavium's rights in the Software.  There are no implied licenses under this
- * Agreement, and any rights not expressly granted to your hereunder are
- * reserved by Cavium.  You will not, at any time, contest anywhere in the
- * world Cavium's ownership of the intellectual property rights in and to the
- * Software.
- *
- * Disclaimer of Warranties.  The Software is provided to you free of charge,
- * and on an "As-Is" basis.  Cavium provides no technical support, warranties
- * or remedies for the Software.  Cavium and its suppliers disclaim all
- * express, implied or statutory warranties relating to the Software,
- * including but not limited to, merchantability, fitness for a particular
- * purpose, title, and non-infringement.  Cavium does not warrant that the
- * Software and the use thereof will be error-free, that defects will be
- * corrected, or that the Software is free of viruses or other harmful
- * components.  If applicable law requires any warranties with respect to the
- * Software, all such warranties are limited in duration to thirty (30) days
- * from the date of download or first use, whichever comes first.
- *
- * Limitation of Liability.  Neither Cavium nor its suppliers shall be
- * responsible or liable with respect to any subject matter of this Agreement
- * or terms or conditions related thereto under any contract, negligence,
- * strict liability or other theory (a) for loss or inaccuracy of data or
- * cost of procurement of substitute goods, services or technology, or (b)
- * for any indirect, incidental or consequential damages including, but not
- * limited to loss of revenues and loss of profits.  Cavium's aggregate
- * cumulative liability hereunder shall not exceed the greater of Fifty U.S.
- * Dollars (U.S.$50.00) or the amount paid by you for the Software that
- * caused the damage.  Certain states and/or jurisdictions do not allow the
- * exclusion of implied warranties or limitation of liability for incidental
- * or consequential damages, so the exclusions set forth above may not apply
- * to you.
- *
- * Basis of Bargain.  The warranty disclaimer and limitation of liability set
- * forth above are fundamental elements of the basis of the agreement between
- * Cavium and you.  Cavium would not provide the Software without such
- * limitations.  The warranty disclaimer and limitation of liability inure to
- * the benefit of Cavium and Cavium's suppliers.
- *
- * Term and Termination.  This Agreement and the licenses granted hereunder
- * are effective on the date you accept the terms of this Agreement, download
- * the Software, or use the Software, whichever comes first, and shall
- * continue unless this Agreement is terminated pursuant to this section.
- * This Agreement immediately terminates in the event that you materially
- * breach any of the terms hereof.  You may terminate this Agreement at any
- * time, with or without cause, by destroying any copies of the Software in
- * your possession.  Upon termination, the license granted hereunder shall
- * terminate but the Sections titled "Restrictions", "Ownership", "Disclaimer
- * of Warranties", "Limitation of Liability", "Basis of Bargain", "Term and
- * Termination", "Export", and "Miscellaneous" will remain in effect.
- *
- * Export.  The Software and related technology are subject to U.S.  export
- * control laws and may be subject to export or import regulations in other
- * countries.  You agree to strictly comply with all such laws and
- * regulations and acknowledges that you have the responsibility to obtain
- * authorization to export, re-export, or import the Software and related
- * technology, as may be required.  You will indemnify and hold Cavium
- * harmless from any and all claims, losses, liabilities, damages, fines,
- * penalties, costs and expenses (including attorney's fees) arising from or
- * relating to any breach by you of your obligations under this section.
- * Your obligations under this section shall survive the expiration or
- * termination of this Agreement.
- *
- * Miscellaneous.  Neither the rights nor the obligations arising under this
- * Agreement are assignable by you, and any such attempted assignment or
- * transfer shall be void and without effect.  This Agreement shall be
- * governed by and construed in accordance with the laws of the State of
- * California without regard to any conflicts of laws provisions that would
- * require application of the laws of another jurisdiction.  Any action under
- * or relating to this Agreement shall be brought in the state and federal
- * courts located in California, with venue in the courts located in Santa
- * Clara County and each party hereby submits to the personal jurisdiction of
- * such courts; provided, however, that nothing herein will operate to
- * prohibit or restrict Cavium from filing for and obtaining injunctive
- * relief from any court of competent jurisdiction.  The United Nations
- * Convention on Contracts for the International Sale of Goods shall not
- * apply to this Agreement.  In the event that any provision of this
- * Agreement is found to be contrary to law, then such provision shall be
- * construed as nearly as possible to reflect the intention of the parties,
- * with the other provisions remaining in full force and effect.  Any notice
- * to you may be provided by email.  This Agreement constitutes the entire
- * agreement between the parties and supersedes all prior or contemporaneous,
- * agreements, understandings and communications between the parties, whether
- * written or oral, pertaining to the subject matter hereof.  Any
- * modifications of this Agreement must be in writing and agreed to by both
- * parties.
- *
- * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
- *
- * ***
- *
- * OCTEON SDK License Type 4:
- *
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2007 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as published by
- * the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
- * See the GNU General Public License for more details.
- * it under the terms of the GNU General Public License, Version 2, as published by
- * the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-
-/*
- * This code is an example of using twsi core in raw mode, bypasing High 
- * Level Controller (HLC). It is recommended to use HLC if only possible as 
- * it is more efficient and robust mechanism. 
- * The example code shows use of twsi for generating long (more that 8 bytes HLC limit) 
- * read - write transactions using 7-bit addressing. Different types of 
- * transactions can be generated if needed. Make sure that commands written to twsi core 
- * follow core state transitions outlinged in OCTEON documentation. The core state is 
- * reported in stat register after the command colpletion. In each state core will accept
- *  only the allowed commands.
- */
- 
-#include <stdio.h>
-#include <cvmx.h>
-#include <cvmx-csr-typedefs.h>
-#include "cvmx-twsi-raw.h"
-
-/*
- * uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
- * twsi core register read
- * twsi_id - twsi core index
- * reg 0 - 8-bit register
- * returns 8-bit register contetn
- */
-uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
-{
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.op = 6;
-    sw_twsi_val.s.eop_ia = reg;
-    sw_twsi_val.s.r = 1;
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-    return sw_twsi_val.s.d ;
-}
-
-/*
- * uint8_t cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
- *
- * twsi core register write
- * twsi_id - twsi core index
- * reg 0 - 8-bit register
- * data - data to write
- * returns 0;
- */
-
-int cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
-{
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.op = 6;
-    sw_twsi_val.s.eop_ia = reg;
-    sw_twsi_val.s.d = data;
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-
-    return 0;
-}
-
-/*
- * cvmx_twsi_wait_iflg(int twsi_id)
- * cvmx_twsi_wait_stop(int twsi_id)
- *
- * Helper functions. 
- * Busy wait for interrupt flag or stop bit on control register. This implementation is for OS-less 
- * application. With OS services available it could be implemented with semaphore
- * block and interrupt wake up. 
- * TWSI_WAIT for loop must be defined large enough to allow on-wire transaction to finish - that is 
- * about 10 twsi clocks
- */
-#define TWSI_WAIT 10000000
-static inline int cvmx_twsi_wait_iflg(int twsi_id)
-{
-    octeon_twsi_ctl_t ctl_reg;
-    int wait = TWSI_WAIT;
-    do{
-        ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
-    } while((ctl_reg.s.iflg ==0) && (wait-- >0));
-    if(wait == 0) return -1;
-    return 0;
-}
-
-static inline int cvmx_twsi_wait_stop(int twsi_id)
-{
-    octeon_twsi_ctl_t ctl_reg;
-    int wait = TWSI_WAIT;
-    do{
-        ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
-    } while((ctl_reg.s.stp ==1) && (wait-- >0));
-    if(wait == 0) return -1;
-    return 0;
-}
-
-
-/*
- * uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack) 
- * uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
- *
- * helper functions - read or write byte to data reg and reads the TWSI core status
- */
-static uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
-{
-    octeon_twsi_ctl_t ctl_reg;
-    octeon_twsi_data_t data;
-    octeon_twsi_stat_t stat;
-
-    /* clear interrupt flag, set aak for requested ACK signal level */
-    ctl_reg.u8 =0;
-    ctl_reg.s.aak = (ack==0) ?0:1;
-    ctl_reg.s.enab =1;
-    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
-
-    /* wait for  twsi_ctl[iflg] to be set */
-    if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
-
-    /* read the byte */
-    data.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_DATA_REG);
-    *byte = data.s.data;
-error:
-    /* read the status */
-    stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
-    return stat.s.stat;
-}
-
-static uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
-{
-    octeon_twsi_ctl_t ctl_reg;
-    octeon_twsi_data_t data;
-    octeon_twsi_stat_t stat;
-
-    /* tx data byte - write to twsi_data reg, then clear twsi_ctl[iflg] */
-    data.s.data = byte;
-    cvmx_twsix_write_ctr(twsi_id, TWSI_DATA_REG, data.u8);
-
-    ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
-    ctl_reg.s.iflg =0;
-    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
-
-    /* wait for  twsi_ctl[iflg] to be set */
-    if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
-error:
-     /* read the status */
-     stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
-     return stat.s.stat;
-}
-
-/*
- * int octeon_i2c_xfer_msg_raw(struct i2c_msg *msg)
- *
- * Send (read or write) a message with 7-bit address device over direct control of 
- * TWSI core, bypassind HLC. Will try to finish the transaction on failure, so core state
- * expected to be idle with HLC enabled on exit.
- *
- * dev - TWSI controller index (0 for cores with single controler)
- * msg - message to transfer
- * returns 0 on success, TWSI core state on error. Will try to finish the transaction on failure, so core state expected to be idle
- */
-int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg)
-{
-    int i =0;
-    octeon_twsi_ctl_t ctl_reg;
-    octeon_twsi_addr_t addr;
-    octeon_twsi_stat_t stat;
-    int is_read = msg->flags & I2C_M_RD;
-    int ret =0;
-
-    /* check the core state, quit if not idle */
-    stat.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
-    if(stat.s.stat != TWSI_IDLE) {
-       msg->len =0; return stat.s.stat;
-    }
-
-    /* first send start - set twsi_ctl[sta] to 1 */
-    ctl_reg.u8 =0;
-    ctl_reg.s.enab =1;
-    ctl_reg.s.sta =1;
-    ctl_reg.s.iflg =0;
-    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
-    /* wait for  twsi_ctl[iflg] to be set */
-    if(cvmx_twsi_wait_iflg(twsi_id)) goto stop;
-
-    /* Write 7-bit addr to twsi_data; set read bit */
-    addr.s.slave_addr7 = msg->addr;
-    if(is_read) addr.s.r =1;
-    else addr.s.r =0;
-    stat.s.stat =octeon_twsi_write_byte(twsi_id, addr.u8);
-
-    /* Data read loop */
-    if( is_read) {
-    /* any status but ACK_RXED means failure - we try to send stop and go idle */
-      if(!(stat.s.stat == TWSI_ADDR_R_TX_ACK_RXED)) {
-      ret = stat.s.stat;
-      msg->len =0;
-      goto stop;
-     }
-     /* We read data from the buffer and send ACK back.
-       The last byte we read with negative ACK */
-      for(i =0; i<msg->len-1; i++)
-      {
-        stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 1);
-        if(stat.s.stat != TWSI_DATA_RX_ACK_TXED)
-           goto stop;
-      }
-      /* last read we send negACK */
-      stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 0);
-        if(stat.s.stat != TWSI_DATA_RX_NACK_TXED)
-             return stat.s.stat;
-    } /* read loop */
-
-    /* Data write loop */
-    else {
-    /* any status but ACK_RXED means failure - we try to send stop and go idle */
-      if(stat.s.stat != TWSI_ADDR_W_TX_ACK_RXED) {
-          ret = stat.s.stat;
-          msg->len =0;
-          goto stop;
-      }
-      /* We write data to the buffer and check for ACK. */
-      for(i =0; i<msg->len; i++)
-      {
-          stat.s.stat =octeon_twsi_write_byte(twsi_id, msg->buf[i]);
-          if(stat.s.stat == TWSI_DATA_TX_NACK_RXED) {
-              /* Negative ACK means slave can not RX more */
-              msg->len =i-1;
-              goto stop;
-          }
-          else if(stat.s.stat != TWSI_DATA_TX_ACK_RXED) {
-              /* lost arbitration? try to send stop and go idle. This current byte likely was not written */
-              msg->len = (i-2) >0? (i-2):0;
-              goto stop;
-          }
-      }
-    }  /* write loop */
-
-stop:
-    ctl_reg.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
-    ctl_reg.s.stp =1;
-    ctl_reg.s.iflg =0;
-    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
-    /* wait for  twsi_ctl[stp] to clear */
-    cvmx_twsi_wait_stop(twsi_id);
-#if 0
-    stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
-    if(stat.s.stat == TWSI_IDLE)
-#endif
-    /* Leave TWSI core with HLC eabled */
-    {
-       ctl_reg.u8 =0;
-       ctl_reg.s.ce =1;
-       ctl_reg.s.enab =1;
-       ctl_reg.s.aak =1;
-       cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
-    }
-
-    return ret;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi-raw.h b/sys/contrib/octeon-sdk/cvmx-twsi-raw.h
deleted file mode 100644
index 17fe39d..0000000
--- a/sys/contrib/octeon-sdk/cvmx-twsi-raw.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
- *
- * This software file (the "File") is owned and distributed by Cavium
- * Networks ("Cavium") under the following dual licensing option: The dual
- * licensing option gives you, the licensee, the choice between the following
- * alternative licensing terms.  Once you have made an election to use the
- * File under one of the following alternative licensing terms (license
- * types) you are bound by the respective terms and you may distribute the
- * file (or any derivative thereof), to the extent allowed by the respective
- * licensing term, only if you (i) delete this introductory statement
- * regarding the dual licensing option from the file you will distribute,
- * (ii) delete the licensing term that you have elected NOT to use from the
- * file you will distribute and (iii) follow the respective licensing term
- * that you have elected to use with respect to the correct attribution or
- * licensing term that you have to include with your distribution.
- *
- * ***
- * OCTEON SDK License Type 2:
- *
- * IMPORTANT: Read this Agreement carefully before clicking on the "I accept"
- * button to download the Software and/or before using the Software.  This
- * License Agreement (the "Agreement") is a legal agreement between you,
- * either an individual or a single legal entity ("You" or "you"), and Cavium
- * Networks ("Cavium").  This Agreement governs your use of the Cavium
- * software that can be downloaded after accepting this Agreement and/or that
- * is accompanied by this Agreement (the "Software").  You must accept the
- * terms of this Agreement before downloading and/or using the Software.  By
- * clicking on the "I accept" button to download and/or by using the
- * Software, you are indicating that you have read and understood, and assent
- * to be bound by, the terms of this Agreement.  If you do not agree to the
- * terms of the Agreement, you are not granted any rights whatsoever in the
- * Software.  If you are not willing to be bound by these terms and
- * conditions, you should not use or cease all use of the Software.  This
- * Software is the property of Cavium Networks and constitutes the
- * proprietary information of Cavium Networks.  You agree to take reasonable
- * steps to prevent the disclosure, unauthorized use or unauthorized
- * distribution of the Software to any third party.
- *
- * License Grant.  Subject to the terms and conditions of this Agreement,
- * Cavium grants you a nonexclusive, non-transferable, worldwide, fully-paid
- * and royalty-free license to
- *
- * (a) install, reproduce, and execute the executable version of the Software
- * solely for your internal use and only (a) on hardware manufactured by
- * Cavium, or (b) software of Cavium that simulates Cavium hardware;
-*
- * (b) create derivative works of any portions of the Software provided to
- * you by Cavium in source code form, which portions enable features of the
- * Cavium hardware products you or your licensees are entitled to use,
- * provided that any such derivative works must be used only (a) on hardware
- * manufactured by Cavium, or (b) software of Cavium that simulates Cavium
- * hardware; and
- *
- * (c) distribute derivative works you created in accordance with clause (b)
- * above, only in executable form and only if such distribution (i)
- * reproduces the copyright notice that can be found at the very end of this
- * Agreement and (ii) is pursuant to a binding license agreement that
- * contains terms no less restrictive and no less protective of Cavium than
- * this Agreement.  You will immediately notify Cavium if you become aware of
- * any breach of any such license agreement.
- *
- * Restrictions.  The rights granted to you in this Agreement are subject to
- * the following restrictions: Except as expressly set forth in this
- * Agreement (a) you will not license, sell, rent, lease, transfer, assign,
- * display, host, outsource, disclose or otherwise commercially exploit or
- * make the Software, or any derivatives you create under this Agreement,
- * available to any third party; (b) you will not modify or create derivative
- * works of any part of the Software; (c) you will not access or use the
- * Software in order to create similar or competitive products, components,
- * or services; and (d), no part of the Software may be copied (except for
- * the making of a single archival copy), reproduced, distributed,
- * republished, downloaded, displayed, posted or transmitted in any form or
- * by any means.
- *
- * Ownership.  You acknowledge and agree that, subject to the license grant
- * contained in this Agreement and as between you and Cavium (a) Cavium owns
- * all copies of and intellectual property rights to the Software, however
- * made, and retains all rights in and to the Software, including all
- * intellectual property rights therein, and (b) you own all the derivate
- * works of the Software created by you under this Agreement, subject to
- * Cavium's rights in the Software.  There are no implied licenses under this
- * Agreement, and any rights not expressly granted to your hereunder are
- * reserved by Cavium.  You will not, at any time, contest anywhere in the
- * world Cavium's ownership of the intellectual property rights in and to the
- * Software.
- *
- * Disclaimer of Warranties.  The Software is provided to you free of charge,
- * and on an "As-Is" basis.  Cavium provides no technical support, warranties
- * or remedies for the Software.  Cavium and its suppliers disclaim all
-* express, implied or statutory warranties relating to the Software,
- * including but not limited to, merchantability, fitness for a particular
- * purpose, title, and non-infringement.  Cavium does not warrant that the
- * Software and the use thereof will be error-free, that defects will be
- * corrected, or that the Software is free of viruses or other harmful
- * components.  If applicable law requires any warranties with respect to the
- * Software, all such warranties are limited in duration to thirty (30) days
- * from the date of download or first use, whichever comes first.
- *
- * Limitation of Liability.  Neither Cavium nor its suppliers shall be
- * responsible or liable with respect to any subject matter of this Agreement
- * or terms or conditions related thereto under any contract, negligence,
- * strict liability or other theory (a) for loss or inaccuracy of data or
- * cost of procurement of substitute goods, services or technology, or (b)
- * for any indirect, incidental or consequential damages including, but not
- * limited to loss of revenues and loss of profits.  Cavium's aggregate
- * cumulative liability hereunder shall not exceed the greater of Fifty U.S.
- * Dollars (U.S.$50.00) or the amount paid by you for the Software that
- * caused the damage.  Certain states and/or jurisdictions do not allow the
- * exclusion of implied warranties or limitation of liability for incidental
- * or consequential damages, so the exclusions set forth above may not apply
- * to you.
- *
- * Basis of Bargain.  The warranty disclaimer and limitation of liability set
- * forth above are fundamental elements of the basis of the agreement between
- * Cavium and you.  Cavium would not provide the Software without such
- * limitations.  The warranty disclaimer and limitation of liability inure to
- * the benefit of Cavium and Cavium's suppliers.
- *
- * Term and Termination.  This Agreement and the licenses granted hereunder
- * are effective on the date you accept the terms of this Agreement, download
- * the Software, or use the Software, whichever comes first, and shall
- * continue unless this Agreement is terminated pursuant to this section.
- * This Agreement immediately terminates in the event that you materially
- * breach any of the terms hereof.  You may terminate this Agreement at any
- * time, with or without cause, by destroying any copies of the Software in
- * your possession.  Upon termination, the license granted hereunder shall
- * terminate but the Sections titled "Restrictions", "Ownership", "Disclaimer
- * of Warranties", "Limitation of Liability", "Basis of Bargain", "Term and
- * Termination", "Export", and "Miscellaneous" will remain in effect.
- *
- * Export.  The Software and related technology are subject to U.S.  export
- * control laws and may be subject to export or import regulations in other
- * countries.  You agree to strictly comply with all such laws and
- * regulations and acknowledges that you have the responsibility to obtain
- * authorization to export, re-export, or import the Software and related
- * technology, as may be required.  You will indemnify and hold Cavium
- * harmless from any and all claims, losses, liabilities, damages, fines,
- * penalties, costs and expenses (including attorney's fees) arising from or
- * relating to any breach by you of your obligations under this section.
- * Your obligations under this section shall survive the expiration or
- * termination of this Agreement.
- *
- * Miscellaneous.  Neither the rights nor the obligations arising under this
- * Agreement are assignable by you, and any such attempted assignment or
- * transfer shall be void and without effect.  This Agreement shall be
- * governed by and construed in accordance with the laws of the State of
- * California without regard to any conflicts of laws provisions that would
- * require application of the laws of another jurisdiction.  Any action under
- * or relating to this Agreement shall be brought in the state and federal
- * courts located in California, with venue in the courts located in Santa
- * Clara County and each party hereby submits to the personal jurisdiction of
- * such courts; provided, however, that nothing herein will operate to
- * prohibit or restrict Cavium from filing for and obtaining injunctive
- * relief from any court of competent jurisdiction.  The United Nations
- * Convention on Contracts for the International Sale of Goods shall not
- * apply to this Agreement.  In the event that any provision of this
- * Agreement is found to be contrary to law, then such provision shall be
- * construed as nearly as possible to reflect the intention of the parties,
- * with the other provisions remaining in full force and effect.  Any notice
- * to you may be provided by email.  This Agreement constitutes the entire
- * agreement between the parties and supersedes all prior or contemporaneous,
- * agreements, understandings and communications between the parties, whether
- * written or oral, pertaining to the subject matter hereof.  Any
- * modifications of this Agreement must be in writing and agreed to by both
- * parties.
- *
- * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
- *
- * ***
- *
- * OCTEON SDK License Type 4:
- *
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2007 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as published by
- * the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
- * See the GNU General Public License for more details.
- * it under the terms of the GNU General Public License, Version 2, as published by
- * the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-
-#ifndef __CVMX_TWSI_RAW_H__
-#define __CVMX_TWSI_RAW_H__
-
-/* Addresses for twsi 8-bit registers. Gets written to EOP_IA field of MIO_TWS_SW_TWSI reg
-*  when OP = 6 and SLONLY =0 */
-#define TWSI_SLAVE_ADD_REG      0
-#define TWSI_DATA_REG           1
-#define TWSI_CTL_REG            2
-#define TWSI_STAT_REG	        3 /* read only */
-#define TWSI_CLKCTL_REG 	3 /* write only */
-#define TWSI_SLAVE_EXTADD_REG   4       
-#define TWSI_RST_REG            7
-
-/* twsi core slave address reg */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t slave_addr7     : 7;
-        uint8_t gce    : 1;
-
-    }s;
-} octeon_twsi_slave_add_t;
-
-/* twsi core 10-bit slave address reg */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t slave_addr8     : 8;
-    }s;
-} octeon_twsi_slave_extadd_t;
-
-/* twsi core control register */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t ce     : 1;  /* enable HLC*/
-        uint8_t enab   : 1;  /* bus enable */
-        uint8_t sta    : 1;  /* start request */
-        uint8_t stp    : 1;  /* stop request */
-        uint8_t iflg   : 1;  /* interrupt flag - request completed (1) start new (0) */
-        uint8_t aak    : 1;  /* assert ack (1) -neg ack at end of Rx sequence */ 
-        uint8_t rsv    : 2;  /* not used */
-    }s;
-} octeon_twsi_ctl_t;
-
-/* clock dividers register */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t m_divider   : 4;
-        uint8_t n_divider   : 3;
-    }s;
-} octeon_twsi_clkctl_t;
-
-/* address of the remote slave + r/w bit */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t slave_addr7     : 7; 
-	uint8_t r		: 1; /* read (1) write (0) bit */
-    }s;
-} octeon_twsi_addr_t;
-
-/* core state reg */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t stat    : 8;
-    }s;
-} octeon_twsi_stat_t;
-
- /* data byte reg */
-typedef union{
-    uint8_t u8;
-    struct{
-        uint8_t data    : 8;
-    }s;
-} octeon_twsi_data_t;
-
-/* twsi core states as reported in twsi core stat register */
-#define TWSI_BUS_ERROR 			0x00
-#define TWSI_START_TXED 		0x08
-#define TWSI_ADDR_W_TX_ACK_RXED 	0x18
-#define TWSI_ADDR_W_TX_NACK_RXED 	0x20
-
-#define TWSI_DATA_TX_ACK_RXED 		0x28
-#define TWSI_DATA_TX_NACK_RXED 	0x30
-#define TWSI_ARB_LOST			0x38
-#define TWSI_ADDR_R_TX_ACK_RXED		0x40
-
-#define TWSI_ADDR_R_TX_NACK_RXED	0x48
-#define TWSI_DATA_RX_ACK_TXED		0x50
-#define TWSI_DATA_RX_NACK_TXED		0x58
-#define TWSI_SLAVE_ADDR_RX_ACK_TXED	0x60
-
-#define TWSI_ARB_LOST_SLAVE_ADDR_RX	0x68
-#define TWSI_GEN_ADDR_RXED_ACK_TXED	0x70
-#define TWSI_ARB_LOST_GEN_ADDR_RXED	0x78
-#define TWSI_SLAVE_DATA_RX_ACK_TXED	0x80
-
-#define TWSI_SLAVE_DATA_RX_NACK_TXED	0x88
-#define TWSI_GEN_DATA_RX_ACK_TXED	0x90
-#define TWSI_GEN_DATA_RX_NACK_TXED	0x98
-#define TWSI_SLAVE_STOP_OR_START_RXED	0xa0
-
-#define TWSI_SLAVE_ADDR_R_RX_ACK_TXED	0xa8
-#define TWSI_ARB_LOST_SLAVE_ADDR_R_RX_ACK_TXED 0xb0
-#define TWSI_SLAVE_DATA_TX_ACK_RXED	0xb8
-#define TWSI_SLAVE_DATA_TX_NACK_RXED	0xc0
-
-#define TWSI_SLAVE_LAST_DATA_TX_ACK_RXED 0xc8
-#define TWSI_SECOND_ADDR_W_TX_ACK_RXED	0xd0
-#define TWSI_SECOND_ADDR_W_TX_NACK_RXED	0xd8
-#define TWSI_IDLE			0xf8
-
-#ifndef LINUX
-/* msg definition similar to Linux */
-struct i2c_msg {
-        uint16_t addr;     /* slave address                        */
-        uint16_t flags;
-        uint16_t len;              /* msg length                           */
-        uint8_t *buf;              /* pointer to msg data                  */
-};
-#define I2C_M_TEN       0x10    /* we have a ten bit chip address       */
-#define I2C_M_RD        0x01
-#endif
-
-int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg);
-
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi.c b/sys/contrib/octeon-sdk/cvmx-twsi.c
index 06daabb..30e8081 100644
--- a/sys/contrib/octeon-sdk/cvmx-twsi.c
+++ b/sys/contrib/octeon-sdk/cvmx-twsi.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,26 +42,69 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the TWSI / I2C bus
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/i2c.h>
 
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-twsi.h>
+#else
 #include "cvmx.h"
 #include "cvmx-twsi.h"
-
-
-
+#include "cvmx-csr-db.h"
+#endif
+
+//#define PRINT_TWSI_CONFIG
+#ifdef PRINT_TWSI_CONFIG
+#define twsi_printf printf
+#else
+#define twsi_printf(...)
+#define cvmx_csr_db_decode(...)
+#endif
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
+{
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+	struct octeon_i2c {
+		wait_queue_head_t queue;
+		struct i2c_adapter adap;
+		int irq;
+		int twsi_freq;
+		int sys_freq;
+		resource_size_t twsi_phys;
+		void __iomem *twsi_base;
+		resource_size_t regsize;
+		struct device *dev;
+		int broken_irq_mode;
+	};
+	struct i2c_adapter *adapter;
+	struct octeon_i2c *i2c;
+
+	adapter = i2c_get_adapter(0);
+	if (adapter == NULL)
+		return NULL;
+	i2c = container_of(adapter, struct octeon_i2c, adap);
+	return &i2c[twsi_id].adap;
+#else
+	return NULL;
+#endif
+}
+#endif
 
 
 /**
  * Do a twsi read from a 7 bit device address using an (optional) internal address.
  * Up to 8 bytes can be read at a time.
- * 
+ *
  * @param twsi_id   which Octeon TWSI bus to use
  * @param dev_addr  Device address (7 bit)
  * @param internal_addr
@@ -69,153 +113,272 @@
  * @param ia_width_bytes
  *                  Internal address size in bytes (0, 1, or 2)
  * @param data      Pointer argument where the read data is returned.
- * 
+ *
  * @return read data returned in 'data' argument
  *         Number of bytes read on success
  *         -1 on failure
  */
 int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data)
 {
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
-
-    if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
-        return -1;
-
-    twsi_ext.u64 = 0;
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.r = 1;
-    sw_twsi_val.s.sovr = 1;
-    sw_twsi_val.s.size = num_bytes - 1;
-    sw_twsi_val.s.a = dev_addr;
-
-    if (ia_width_bytes > 0)
-    {
-        sw_twsi_val.s.op = 1;
-        sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
-        sw_twsi_val.s.eop_ia = internal_addr & 0x7;
-    } 
-    if (ia_width_bytes == 2)
-    {
-        sw_twsi_val.s.eia = 1;
-        twsi_ext.s.ia = internal_addr >> 8;
-        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
-    }
-
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-    if (!sw_twsi_val.s.r)
-        return -1;
-
-    *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
-    if (num_bytes > 4)
-    {
-        twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
-        *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
-
-    }
-    return num_bytes;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+	struct i2c_adapter *adapter;
+	u8 data_buf[8];
+	u8 addr_buf[8];
+	struct i2c_msg msg[2];
+	uint64_t r;
+	int i, j;
+
+	if (ia_width_bytes == 0)
+		return cvmx_twsix_read(twsi_id, dev_addr, num_bytes, data);
+
+	BUG_ON(ia_width_bytes > 2);
+	BUG_ON(num_bytes > 8 || num_bytes < 1);
+
+	adapter = __cvmx_twsix_get_adapter(twsi_id);
+	if (adapter == NULL)
+		return -1;
+
+	for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
+		addr_buf[j] = (u8)(internal_addr >> (i * 8));
+
+	msg[0].addr = dev_addr;
+	msg[0].flags = 0;
+	msg[0].len = ia_width_bytes;
+	msg[0].buf = addr_buf;
+
+	msg[1].addr = dev_addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = num_bytes;
+	msg[1].buf = data_buf;
+
+	i = i2c_transfer(adapter, msg, 2);
+
+	i2c_put_adapter(adapter);
+
+	if (i == 2) {
+		r = 0;
+		for (i = 0; i < num_bytes; i++)
+			r = (r << 8) | data_buf[i];
+		*data = r;
+		return num_bytes;
+	} else {
+		return -1;
+	}
+# else
+	BUG(); /* The I2C driver is not compiled in */
+# endif
+#else
+	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+	cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+
+	if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
+		return -1;
+
+	twsi_ext.u64 = 0;
+	sw_twsi_val.u64 = 0;
+	sw_twsi_val.s.v = 1;
+	sw_twsi_val.s.r = 1;
+	sw_twsi_val.s.sovr = 1;
+	sw_twsi_val.s.size = num_bytes - 1;
+	sw_twsi_val.s.a = dev_addr;
+
+	if (ia_width_bytes > 0) {
+		sw_twsi_val.s.op = 1;
+		sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
+		sw_twsi_val.s.eop_ia = internal_addr & 0x7;
+	}
+	if (ia_width_bytes == 2) {
+		sw_twsi_val.s.eia = 1;
+		twsi_ext.s.ia = internal_addr >> 8;
+		cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+	}
+
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+		;
+	twsi_printf("Results:\n");
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	if (!sw_twsi_val.s.r)
+		return -1;
+
+	*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
+	if (num_bytes > 4) {
+		twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
+		*data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
+	}
+	return num_bytes;
+#endif
 }
 
-
-
-
 /**
  * Read from a TWSI device (7 bit device address only) without generating any
  * internal addresses.
  * Read from 1-8 bytes and returns them in the data pointer.
- * 
+ *
  * @param twsi_id   TWSI interface on Octeon to use
  * @param dev_addr  TWSI device address (7 bit only)
  * @param num_bytes number of bytes to read
  * @param data      Pointer to data read from TWSI device
- * 
+ *
  * @return Number of bytes read on success
  *         -1 on error
  */
 int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data)
 {
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
-
-    if (num_bytes > 8 || num_bytes < 1)
-        return -1;
-
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.r = 1;
-    sw_twsi_val.s.a = dev_addr;
-    sw_twsi_val.s.sovr = 1;
-    sw_twsi_val.s.size = num_bytes - 1;
-
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-    if (!sw_twsi_val.s.r)
-        return -1;
-
-    *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
-    if (num_bytes > 4)
-    {
-        twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
-        *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
-
-    }
-    return num_bytes;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+	struct i2c_adapter *adapter;
+	u8 data_buf[8];
+	struct i2c_msg msg[1];
+	uint64_t r;
+	int i;
+
+	BUG_ON(num_bytes > 8 || num_bytes < 1);
+
+	adapter = __cvmx_twsix_get_adapter(twsi_id);
+	if (adapter == NULL)
+		return -1;
+
+	msg[0].addr = dev_addr;
+	msg[0].flags = I2C_M_RD;
+	msg[0].len = num_bytes;
+	msg[0].buf = data_buf;
+
+	i = i2c_transfer(adapter, msg, 1);
+
+	i2c_put_adapter(adapter);
+
+	if (i == 1) {
+		r = 0;
+		for (i = 0; i < num_bytes; i++)
+			r = (r << 8) | data_buf[i];
+		*data = r;
+		return num_bytes;
+	} else {
+		return -1;
+	}
+# else
+	BUG(); /* The I2C driver is not compiled in */
+# endif
+#else
+	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+	cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+
+	if (num_bytes > 8 || num_bytes < 1)
+		return -1;
+
+	sw_twsi_val.u64 = 0;
+	sw_twsi_val.s.v = 1;
+	sw_twsi_val.s.r = 1;
+	sw_twsi_val.s.a = dev_addr;
+	sw_twsi_val.s.sovr = 1;
+	sw_twsi_val.s.size = num_bytes - 1;
+
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+		;
+	twsi_printf("Results:\n");
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	if (!sw_twsi_val.s.r)
+		return -1;
+
+	*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
+	if (num_bytes > 4) {
+		twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
+		*data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
+	}
+	return num_bytes;
+#endif
 }
 
-
 /**
  * Perform a twsi write operation to a 7 bit device address.
- * 
+ *
  * Note that many eeprom devices have page restrictions regarding address boundaries
  * that can be crossed in one write operation.  This is device dependent, and this routine
  * does nothing in this regard.
  * This command does not generate any internal addressess.
- * 
+ *
  * @param twsi_id   Octeon TWSI interface to use
  * @param dev_addr  TWSI device address
  * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
  * @param data      Data to write
- * 
+ *
  * @return 0 on success
  *         -1 on failure
  */
 int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data)
 {
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-
-    if (num_bytes > 8 || num_bytes < 1)
-        return -1;
-
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.a = dev_addr;
-    sw_twsi_val.s.d = data & 0xffffffff;
-    sw_twsi_val.s.sovr = 1;
-    sw_twsi_val.s.size = num_bytes - 1;
-    if (num_bytes > 4)
-    {
-        /* Upper four bytes go into a separate register */
-        cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
-        twsi_ext.u64 = 0;
-        twsi_ext.s.d = data >> 32;
-        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
-    }
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-    if (!sw_twsi_val.s.r)
-        return -1;
-
-    return 0;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+	struct i2c_adapter *adapter;
+	u8 data_buf[8];
+	struct i2c_msg msg[1];
+	int i, j;
+
+	BUG_ON(num_bytes > 8 || num_bytes < 1);
+
+	adapter = __cvmx_twsix_get_adapter(twsi_id);
+	if (adapter == NULL)
+		return -1;
+
+	for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
+		data_buf[j] = (u8)(data >> (i * 8));
+
+	msg[1].addr = dev_addr;
+	msg[1].flags = 0;
+	msg[1].len = num_bytes;
+	msg[1].buf = data_buf;
+
+	i = i2c_transfer(adapter, msg, 1);
+
+	i2c_put_adapter(adapter);
+
+	if (i == 1)
+		return num_bytes;
+	else
+		return -1;
+# else
+	BUG(); /* The I2C driver is not compiled in */
+# endif
+#else
+	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+
+	if (num_bytes > 8 || num_bytes < 1)
+		return -1;
+
+	sw_twsi_val.u64 = 0;
+	sw_twsi_val.s.v = 1;
+	sw_twsi_val.s.a = dev_addr;
+	sw_twsi_val.s.d = data & 0xffffffff;
+	sw_twsi_val.s.sovr = 1;
+	sw_twsi_val.s.size = num_bytes - 1;
+	if (num_bytes > 4) {
+		/* Upper four bytes go into a separate register */
+		cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+		twsi_ext.u64 = 0;
+		twsi_ext.s.d = data >> 32;
+		cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+	}
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+		;
+	twsi_printf("Results:\n");
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	if (!sw_twsi_val.s.r)
+		return -1;
+
+	return 0;
+#endif
 }
 
 /**
  * Write 1-8 bytes to a TWSI device using an internal address.
- * 
+ *
  * @param twsi_id   which TWSI interface on Octeon to use
  * @param dev_addr  TWSI device address (7 bit only)
  * @param internal_addr
@@ -226,60 +389,118 @@ int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data
  * @param data      Data to write.  Data is written MSB first on the twsi bus, and only the lower
  *                  num_bytes bytes of the argument are valid.  (If a 2 byte write is done, only
  *                  the low 2 bytes of the argument is used.
- * 
+ *
  * @return Number of bytes read on success,
  *         -1 on error
  */
 int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
 {
-    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
-    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
-    int to;
-
-    if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
-        return -1;
-
-    twsi_ext.u64 = 0;
-
-    sw_twsi_val.u64 = 0;
-    sw_twsi_val.s.v = 1;
-    sw_twsi_val.s.sovr = 1;
-    sw_twsi_val.s.size = num_bytes - 1;
-    sw_twsi_val.s.a = dev_addr;
-    sw_twsi_val.s.d = 0xFFFFFFFF & data;
-
-    if (ia_width_bytes > 0)
-    {
-        sw_twsi_val.s.op = 1;
-        sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
-        sw_twsi_val.s.eop_ia = internal_addr & 0x7;
-    } 
-    if (ia_width_bytes == 2)
-    {
-        sw_twsi_val.s.eia = 1;
-        twsi_ext.s.ia = internal_addr >> 8;
-        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
-    }
-    if (num_bytes > 4)
-        twsi_ext.s.d = data >> 32;
-
-
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
-    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
-    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
-        ;
-
-    /* Poll until reads succeed, or polling times out */
-    to = 100;
-    while (to-- > 0)
-    {
-        uint64_t data;
-        if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
-            break;
-    }
-    if (to <= 0)
-        return -1;
-
-    return num_bytes;
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+	struct i2c_adapter *adapter;
+	u8 data_buf[8];
+	u8 addr_buf[8];
+	struct i2c_msg msg[2];
+	int i, j;
+
+	if (ia_width_bytes == 0)
+		return cvmx_twsix_write(twsi_id, dev_addr, num_bytes, data);
+
+	BUG_ON(ia_width_bytes > 2);
+	BUG_ON(num_bytes > 8 || num_bytes < 1);
+
+	adapter = __cvmx_twsix_get_adapter(twsi_id);
+	if (adapter == NULL)
+		return -1;
+
+
+	for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
+		addr_buf[j] = (u8)(internal_addr >> (i * 8));
+
+	for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
+		data_buf[j] = (u8)(data >> (i * 8));
+
+	msg[0].addr = dev_addr;
+	msg[0].flags = 0;
+	msg[0].len = ia_width_bytes;
+	msg[0].buf = addr_buf;
+
+	msg[1].addr = dev_addr;
+	msg[1].flags = 0;
+	msg[1].len = num_bytes;
+	msg[1].buf = data_buf;
+
+	i = i2c_transfer(adapter, msg, 2);
+
+	i2c_put_adapter(adapter);
+
+	if (i == 2) {
+		/* Poll until reads succeed, or polling times out */
+		int to = 100;
+		while (to-- > 0) {
+			uint64_t data;
+			if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
+				break;
+		}
+	}
+
+	if (i == 2)
+		return num_bytes;
+	else
+		return -1;
+# else
+	BUG(); /* The I2C driver is not compiled in */
+# endif
+#else
+	cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+	cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+	int to;
+
+	if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
+		return -1;
+
+	twsi_ext.u64 = 0;
+
+	sw_twsi_val.u64 = 0;
+	sw_twsi_val.s.v = 1;
+	sw_twsi_val.s.sovr = 1;
+	sw_twsi_val.s.size = num_bytes - 1;
+	sw_twsi_val.s.a = dev_addr;
+	sw_twsi_val.s.d = 0xFFFFFFFF & data;
+
+	if (ia_width_bytes > 0) {
+		sw_twsi_val.s.op = 1;
+		sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
+		sw_twsi_val.s.eop_ia = internal_addr & 0x7;
+	}
+	if (ia_width_bytes == 2) {
+		sw_twsi_val.s.eia = 1;
+		twsi_ext.s.ia = internal_addr >> 8;
+	}
+	if (num_bytes > 4)
+		twsi_ext.s.d = data >> 32;
+
+	twsi_printf("%s: twsi_id=%x, dev_addr=%x, internal_addr=%x\n\tnum_bytes=%d, ia_width_bytes=%d, data=%lx\n",
+		    __FUNCTION__, twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+	while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+		;
+	twsi_printf("Results:\n");
+	cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+
+	/* Poll until reads succeed, or polling times out */
+	to = 100;
+	while (to-- > 0) {
+		uint64_t data;
+		if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
+			break;
+	}
+	if (to <= 0)
+		return -1;
+
+	return num_bytes;
+#endif
 }
-
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi.h b/sys/contrib/octeon-sdk/cvmx-twsi.h
index e2a4295..7ca8798 100644
--- a/sys/contrib/octeon-sdk/cvmx-twsi.h
+++ b/sys/contrib/octeon-sdk/cvmx-twsi.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,14 +42,15 @@
 
 
 
+
 /**
  * @file
  *
  * Interface to the TWSI / I2C bus
- * 
+ *
  * Note: Currently on 7 bit device addresses are supported
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 
@@ -60,11 +62,20 @@ extern "C" {
 #endif
 
 
+    /* Extra TWSI Bus Opcodes */
+#define TWSI_SLAVE_ADD     0
+#define TWSI_DATA          1
+#define TWSI_CTL           2
+#define TWSI_CLKCTL_STAT   3       /* R=0 selects CLKCTL, R=1 selects STAT */
+#define TWSI_STAT          3       /* when R = 1 */
+#define TWSI_SLAVE_ADD_EXT 4
+#define TWSI_RST           7
+
 
 /**
  * Do a twsi read from a 7 bit device address using an (optional) internal address.
  * Up to 8 bytes can be read at a time.
- * 
+ *
  * @param twsi_id   which Octeon TWSI bus to use
  * @param dev_addr  Device address (7 bit)
  * @param internal_addr
@@ -73,7 +84,7 @@ extern "C" {
  * @param ia_width_bytes
  *                  Internal address size in bytes (0, 1, or 2)
  * @param data      Pointer argument where the read data is returned.
- * 
+ *
  * @return read data returned in 'data' argument
  *         Number of bytes read on success
  *         -1 on failure
@@ -88,13 +99,13 @@ int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, in
  * only supports 8 bit internal addresses.
  * Reads up to 7 bytes, and returns both the value read or error
  * value in the return value
- * 
+ *
  * @param twsi_id   which Octeon TWSI bus to use
  * @param dev_addr  Device address (7 bit only)
  * @param internal_addr
  *                  Internal address (8 bit only)
  * @param num_bytes Number of bytes to read (0-7)
- * 
+ *
  * @return Value read from TWSI on success
  *         -1 on error
  */
@@ -113,13 +124,13 @@ static inline int64_t cvmx_twsix_read_ia8(int twsi_id, uint8_t dev_addr, uint8_t
  * only supports 16 bit internal addresses.
  * Reads up to 7 bytes, and returns both the value read or error
  * value in the return value
- * 
+ *
  * @param twsi_id   which Octeon TWSI bus to use
  * @param dev_addr  Device address (7 bit only)
  * @param internal_addr
  *                  Internal address (16 bit only)
  * @param num_bytes Number of bytes to read (0-7)
- * 
+ *
  * @return Value read from TWSI on success
  *         -1 on error
  */
@@ -139,12 +150,12 @@ static inline int64_t cvmx_twsix_read_ia16(int twsi_id, uint8_t dev_addr, uint16
  * Read from a TWSI device (7 bit device address only) without generating any
  * internal addresses.
  * Read from 1-8 bytes and returns them in the data pointer.
- * 
+ *
  * @param twsi_id   TWSI interface on Octeon to use
  * @param dev_addr  TWSI device address (7 bit only)
  * @param num_bytes number of bytes to read
  * @param data      Pointer to data read from TWSI device
- * 
+ *
  * @return Number of bytes read on success
  *         -1 on error
  */
@@ -154,17 +165,17 @@ int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data
 
 /**
  * Perform a twsi write operation to a 7 bit device address.
- * 
+ *
  * Note that many eeprom devices have page restrictions regarding address boundaries
  * that can be crossed in one write operation.  This is device dependent, and this routine
  * does nothing in this regard.
  * This command does not generate any internal addressess.
- * 
+ *
  * @param twsi_id   Octeon TWSI interface to use
  * @param dev_addr  TWSI device address
  * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
  * @param data      Data to write
- * 
+ *
  * @return 0 on success
  *         -1 on failure
  */
@@ -172,7 +183,7 @@ int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data
 
 /**
  * Write 1-8 bytes to a TWSI device using an internal address.
- * 
+ *
  * @param twsi_id   which TWSI interface on Octeon to use
  * @param dev_addr  TWSI device address (7 bit only)
  * @param internal_addr
@@ -183,7 +194,7 @@ int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data
  * @param data      Data to write.  Data is written MSB first on the twsi bus, and only the lower
  *                  num_bytes bytes of the argument are valid.  (If a 2 byte write is done, only
  *                  the low 2 bytes of the argument is used.
- * 
+ *
  * @return Number of bytes read on success,
  *         -1 on error
  */
diff --git a/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h b/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
new file mode 100644
index 0000000..d5cd1c1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
@@ -0,0 +1,2536 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-uahcx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon uahcx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_UAHCX_TYPEDEFS_H__
+#define __CVMX_UAHCX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
+}
+#else
+#define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000008ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_HCCPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000004ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_HCSPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000004ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000090ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_INSNREG00(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000009Cull);
+}
+#else
+#define CVMX_UAHCX_EHCI_INSNREG03(block_id) (CVMX_ADD_IO_SEG(0x00016F000000009Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F00000000A0ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_INSNREG04(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG06(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F00000000E8ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000E8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_INSNREG07(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F00000000ECull);
+}
+#else
+#define CVMX_UAHCX_EHCI_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000ECull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_PERIODICLISTBASE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000024ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_PERIODICLISTBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000024ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
+		cvmx_warn("CVMX_UAHCX_EHCI_PORTSCX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
+}
+#else
+#define CVMX_UAHCX_EHCI_PORTSCX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_USBCMD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000010ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_USBCMD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_USBINTR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000018ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_USBINTR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_EHCI_USBSTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000014ull);
+}
+#else
+#define CVMX_UAHCX_EHCI_USBSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000014ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKCURRENTED(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000042Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCBULKCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000042Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKHEADED(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000428ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCBULKHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000428ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000408ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000404ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCCONTROL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000404ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000424ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000424ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLHEADED(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000420ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCCONTROLHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000420ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCDONEHEAD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000430ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCDONEHEAD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000430ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMINTERVAL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000434ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCFMINTERVAL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000434ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMNUMBER(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000043Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCFMNUMBER(block_id) (CVMX_ADD_IO_SEG(0x00016F000000043Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCFMREMAINING(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000438ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCFMREMAINING(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000438ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCHCCA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000418ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCHCCA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000418ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000414ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000414ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000410ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000410ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000040Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F000000040Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000444ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000444ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000041Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000041Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODICSTART(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000440ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCPERIODICSTART(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000440ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCREVISION(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000400ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCREVISION(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000400ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000448ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000448ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000044Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(block_id) (CVMX_ADD_IO_SEG(0x00016F000000044Cull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_HCRHSTATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000450ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_HCRHSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG06(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000498ull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000498ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG07(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F000000049Cull);
+}
+#else
+#define CVMX_UAHCX_OHCI0_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F000000049Cull))
+#endif
+
+/**
+ * cvmx_uahc#_ehci_asynclistaddr
+ *
+ * ASYNCLISTADDR = Current Asynchronous List Address Register
+ *
+ * This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host
+ * controller is in 64-bit mode (as indicated by a one in 64-bit Addressing Capability field in the
+ * HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from
+ * the CTRLDSSEGMENT register (See Section 2.3.5). Bits [4:0] of this register cannot be modified by system
+ * software and will always return a zero when read. The memory structure referenced by this physical memory
+ * pointer is assumed to be 32-byte (cache line) aligned.
+ */
+union cvmx_uahcx_ehci_asynclistaddr
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_asynclistaddr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t lpl                          : 27; /**< Link Pointer Low (LPL). These bits correspond to memory address signals [31:5],
+                                                         respectively. This field may only reference a Queue Head (QH). */
+	uint32_t reserved_0_4                 : 5;
+#else
+	uint32_t reserved_0_4                 : 5;
+	uint32_t lpl                          : 27;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn63xx;
+	struct cvmx_uahcx_ehci_asynclistaddr_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t;
+
+/**
+ * cvmx_uahc#_ehci_configflag
+ *
+ * CONFIGFLAG = Configure Flag Register
+ * This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially
+ * applied or in response to a host controller reset.
+ */
+union cvmx_uahcx_ehci_configflag
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_configflag_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_1_31                : 31;
+	uint32_t cf                           : 1;  /**< Configure Flag (CF) .Host software sets this bit as the last action in
+                                                         its process of configuring the Host Controller (see Section 4.1). This bit controls the
+                                                         default port-routing control logic. Bit values and side-effects are listed below.
+                                                          0b: Port routing control logic default-routes each port to an implementation
+                                                              dependent classic host controller.
+                                                          1b: Port routing control logic default-routes all ports to this host controller. */
+#else
+	uint32_t cf                           : 1;
+	uint32_t reserved_1_31                : 31;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_configflag_s   cn63xx;
+	struct cvmx_uahcx_ehci_configflag_s   cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t;
+
+/**
+ * cvmx_uahc#_ehci_ctrldssegment
+ *
+ * CTRLDSSEGMENT = Control Data Structure Segment Register
+ *
+ * This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If
+ * the 64-bit Addressing Capability field in HCCPARAMS is a zero, then this register is not used. Software
+ * cannot write to it and a read from this register will return zeros.
+ *
+ * If the 64-bit Addressing Capability field in HCCPARAMS is a one, then this register is used with the link
+ * pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the
+ * link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link
+ * field to construct a 64-bit address.
+ *
+ * This register allows the host software to locate all control data structures within the same 4 Gigabyte
+ * memory segment.
+ */
+union cvmx_uahcx_ehci_ctrldssegment
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_ctrldssegment_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ctrldsseg                    : 32; /**< Control Data Strucute Semgent Address Bit [63:32] */
+#else
+	uint32_t ctrldsseg                    : 32;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn63xx;
+	struct cvmx_uahcx_ehci_ctrldssegment_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t;
+
+/**
+ * cvmx_uahc#_ehci_frindex
+ *
+ * FRINDEX = Frame Index Register
+ * This register is used by the host controller to index into the periodic frame list. The register updates every
+ * 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic
+ * Frame List during periodic schedule execution. The number of bits used for the index depends on the size of
+ * the frame list as set by system software in the Frame List Size field in the USBCMD register.
+ * This register cannot be written unless the Host Controller is in the Halted state as indicated by the
+ * HCHalted bit. A write to this register while the Run/Stop bit is set to a one (USBCMD register) produces
+ * undefined results. Writes to this register also affect the SOF value.
+ */
+union cvmx_uahcx_ehci_frindex
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_frindex_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t fi                           : 14; /**< Frame Index. The value in this register increments at the end of each time frame (e.g.
+                                                         micro-frame). Bits [N:3] are used for the Frame List current index. This means that each
+                                                         location of the frame list is accessed 8 times (frames or micro-frames) before moving to
+                                                         the next index. The following illustrates values of N based on the value of the Frame List
+                                                         Size field in the USBCMD register.
+                                                         USBCMD[Frame List Size] Number Elements N
+                                                            00b (1024) 12
+                                                            01b (512) 11
+                                                            10b (256) 10
+                                                            11b Reserved */
+#else
+	uint32_t fi                           : 14;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_frindex_s      cn63xx;
+	struct cvmx_uahcx_ehci_frindex_s      cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t;
+
+/**
+ * cvmx_uahc#_ehci_hccapbase
+ *
+ * HCCAPBASE = Host Controller BASE Capability Register
+ *
+ */
+union cvmx_uahcx_ehci_hccapbase
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_hccapbase_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t hciversion                   : 16; /**< Host Controller Interface Version Number */
+	uint32_t reserved_8_15                : 8;
+	uint32_t caplength                    : 8;  /**< Capabitlity Registers Length */
+#else
+	uint32_t caplength                    : 8;
+	uint32_t reserved_8_15                : 8;
+	uint32_t hciversion                   : 16;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn63xx;
+	struct cvmx_uahcx_ehci_hccapbase_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t;
+
+/**
+ * cvmx_uahc#_ehci_hccparams
+ *
+ * HCCPARAMS = Host Controller Capability Parameters
+ * Multiple Mode control (time-base bit functionality), addressing capability
+ */
+union cvmx_uahcx_ehci_hccparams
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_hccparams_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t eecp                         : 8;  /**< EHCI Extended Capabilities Pointer. Default = Implementation Dependent.
+                                                         This optional field indicates the existence of a capabilities list. A value of 00h indicates
+                                                         no extended capabilities are implemented. A non-zero value in this register indicates the
+                                                         offset in PCI configuration space of the first EHCI extended capability. The pointer value
+                                                         must be 40h or greater if implemented to maintain the consistency of the PCI header
+                                                         defined for this class of device. */
+	uint32_t ist                          : 4;  /**< Isochronous Scheduling Threshold. Default = implementation dependent. This field
+                                                         indicates, relative to the current position of the executing host controller, where software
+                                                         can reliably update the isochronous schedule. When bit [7] is zero, the value of the least
+                                                         significant 3 bits indicates the number of micro-frames a host controller can hold a set of
+                                                         isochronous data structures (one or more) before flushing the state. When bit [7] is a
+                                                         one, then host software assumes the host controller may cache an isochronous data
+                                                         structure for an entire frame. Refer to Section 4.7.2.1 for details on how software uses
+                                                         this information for scheduling isochronous transfers. */
+	uint32_t reserved_3_3                 : 1;
+	uint32_t aspc                         : 1;  /**< Asynchronous Schedule Park Capability. Default = Implementation dependent. If this
+                                                         bit is set to a one, then the host controller supports the park feature for high-speed
+                                                         queue heads in the Asynchronous Schedule. The feature can be disabled or enabled
+                                                         and set to a specific level by using the Asynchronous Schedule Park Mode Enable and
+                                                         Asynchronous Schedule Park Mode Count fields in the USBCMD register. */
+	uint32_t pflf                         : 1;  /**< Programmable Frame List Flag. Default = Implementation dependent. If this bit is set
+                                                         to a zero, then system software must use a frame list length of 1024 elements with this
+                                                         host controller. The USBCMD register Frame List Size field is a read-only register and
+                                                         should be set to zero.
+                                                         If set to a one, then system software can specify and use a smaller frame list and
+                                                         configure the host controller via the USBCMD register Frame List Size field. The frame
+                                                         list must always be aligned on a 4K page boundary. This requirement ensures that the
+                                                         frame list is always physically contiguous. */
+	uint32_t ac64                         : 1;  /**< 64-bit Addressing Capability1 . This field documents the addressing range capability of
+                                                          this implementation. The value of this field determines whether software should use the
+                                                          data structures defined in Section 3 (32-bit) or those defined in Appendix B (64-bit).
+                                                          Values for this field have the following interpretation:
+                                                         - 0: data structures using 32-bit address memory pointers
+                                                         - 1: data structures using 64-bit address memory pointers */
+#else
+	uint32_t ac64                         : 1;
+	uint32_t pflf                         : 1;
+	uint32_t aspc                         : 1;
+	uint32_t reserved_3_3                 : 1;
+	uint32_t ist                          : 4;
+	uint32_t eecp                         : 8;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_hccparams_s    cn63xx;
+	struct cvmx_uahcx_ehci_hccparams_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t;
+
+/**
+ * cvmx_uahc#_ehci_hcsparams
+ *
+ * HCSPARAMS = Host Controller Structural Parameters
+ * This is a set of fields that are structural parameters: Number of downstream ports, etc.
+ */
+union cvmx_uahcx_ehci_hcsparams
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_hcsparams_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t dpn                          : 4;  /**< Debug Port Number. Optional. This register identifies which of the host controller ports
+                                                         is the debug port. The value is the port number (one-based) of the debug port. A nonzero
+                                                         value in this field indicates the presence of a debug port. The value in this register
+                                                         must not be greater than N_PORTS (see below). */
+	uint32_t reserved_17_19               : 3;
+	uint32_t p_indicator                  : 1;  /**< Port Indicator. This bit indicates whether the ports support port
+                                                         indicator control. When this bit is a one, the port status and control
+                                                         registers include a read/writeable field for controlling the state of
+                                                         the port indicator. */
+	uint32_t n_cc                         : 4;  /**< Number of Companion Controller. This field indicates the number of
+                                                         companion controllers associated with this USB 2.0 host controller.
+                                                         A zero in this field indicates there are no companion host controllers.
+                                                         Port-ownership hand-off is not supported. Only high-speed devices are
+                                                         supported on the host controller root ports.
+                                                         A value larger than zero in this field indicates there are companion USB 1.1 host
+                                                         controller(s). Port-ownership hand-offs are supported. High, Full-and Low-speed
+                                                         devices are supported on the host controller root ports. */
+	uint32_t n_pcc                        : 4;  /**< Number of Ports per Companion Controller (N_PCC). This field indicates
+                                                         the number of ports supported per companion host controller. It is used to
+                                                         indicate the port routing  configuration to system software. */
+	uint32_t prr                          : 1;  /**< Port Routing Rules. This field indicates the method used by this implementation for
+                                                         how all ports are mapped to companion controllers. The value of this field has
+                                                         the following interpretation:
+                                                         0 The first N_PCC ports are routed to the lowest numbered function
+                                                           companion host controller, the next N_PCC port are routed to the next
+                                                           lowest function companion controller, and so on.
+                                                         1 The port routing is explicitly enumerated by the first N_PORTS elements
+                                                           of the HCSP-PORTROUTE array. */
+	uint32_t reserved_5_6                 : 2;
+	uint32_t ppc                          : 1;  /**< Port Power Control. This field indicates whether the host controller
+                                                         implementation includes port power control. A one in this bit indicates the ports have
+                                                         port power switches. A zero in this bit indicates the port do not have port power
+                                                         switches. The value of this field affects the functionality of the Port Power field
+                                                         in each port status and control register (see Section 2.3.8). */
+	uint32_t n_ports                      : 4;  /**< This field specifies the number of physical downstream ports implemented
+                                                         on this host controller. The value of this field determines how many port registers are
+                                                         addressable in the Operational Register Space (see Table 2-8). Valid values are in the
+                                                         range of 1H to FH. A zero in this field is undefined. */
+#else
+	uint32_t n_ports                      : 4;
+	uint32_t ppc                          : 1;
+	uint32_t reserved_5_6                 : 2;
+	uint32_t prr                          : 1;
+	uint32_t n_pcc                        : 4;
+	uint32_t n_cc                         : 4;
+	uint32_t p_indicator                  : 1;
+	uint32_t reserved_17_19               : 3;
+	uint32_t dpn                          : 4;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn63xx;
+	struct cvmx_uahcx_ehci_hcsparams_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t;
+
+/**
+ * cvmx_uahc#_ehci_insnreg00
+ *
+ * EHCI_INSNREG00 = EHCI Programmable Microframe Base Value Register (Synopsys Speicific)
+ * This register allows you to change the microframe length value (default is microframe SOF = 125 s) to reduce the simulation time.
+ */
+union cvmx_uahcx_ehci_insnreg00
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_insnreg00_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t mfmc                         : 13; /**< For byte interface (8-bits), <13:1> is used as the 1-microframe counter.
+                                                         For word interface (16_bits> <12:1> is used as the 1-microframe counter with word
+                                                           interface (16-bits). */
+	uint32_t en                           : 1;  /**< Writing 1b1 enables this register.
+                                                         Note: Do not enable this register for the gate-level netlist */
+#else
+	uint32_t en                           : 1;
+	uint32_t mfmc                         : 13;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn63xx;
+	struct cvmx_uahcx_ehci_insnreg00_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t;
+
+/**
+ * cvmx_uahc#_ehci_insnreg03
+ *
+ * EHCI_INSNREG03 = EHCI Timing Adjust Register (Synopsys Speicific)
+ * This register allows you to change the timing of Phy Tx turnaround delay etc.
+ */
+union cvmx_uahcx_ehci_insnreg03
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_insnreg03_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_13_31               : 19;
+	uint32_t txtx_tadao                   : 3;  /**< Tx-Tx turnaround Delay Add on. This field specifies the extra delays in phy_clks to
+                                                         be added to the "Transmit to Transmit turnaround delay" value maintained in the core.
+                                                         The default value of this register field is 0. This default value of 0 is sufficient
+                                                         for most PHYs. But for some PHYs which puts wait states during the token packet, it
+                                                         may be required to program a value greater than 0 to meet the transmit to transmit
+                                                         minimum turnaround time. The recommendation to use the default value of 0 and change
+                                                         it only if there is an issue with minimum transmit-to- transmit turnaround time. This
+                                                         value should be programmed during core initialization and should not be changed afterwards. */
+	uint32_t reserved_9_9                 : 1;
+	uint32_t ta_off                       : 8;  /**< Time-Available Offset. This value indicates the additional number of bytes to be
+                                                         accommodated for the time-available calculation. The USB traffic on the bus can be started
+                                                         only when sufficient time is available to complete the packet within the EOF1 point. Refer
+                                                         to the USB 2.0 specification for details of the EOF1 point. This time-available
+                                                         calculation is done in the hardware, and can be further offset by programming a value in
+                                                         this location.
+                                                         Note: Time-available calculation is added for future flexibility. The application is not
+                                                         required to program this field by default. */
+	uint32_t reserved_0_0                 : 1;
+#else
+	uint32_t reserved_0_0                 : 1;
+	uint32_t ta_off                       : 8;
+	uint32_t reserved_9_9                 : 1;
+	uint32_t txtx_tadao                   : 3;
+	uint32_t reserved_13_31               : 19;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn63xx;
+	struct cvmx_uahcx_ehci_insnreg03_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t;
+
+/**
+ * cvmx_uahc#_ehci_insnreg04
+ *
+ * EHCI_INSNREG04 = EHCI Debug Register (Synopsys Speicific)
+ * This register is used only for debug purposes.
+ */
+union cvmx_uahcx_ehci_insnreg04
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_insnreg04_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_6_31                : 26;
+	uint32_t auto_dis                     : 1;  /**< Automatic feature disable.
+                                                          1'b0: 0 by default, the automatic feature is enabled. The Suspend signal is deasserted
+                                                                (logic level 1'b1) when run/stop is reset by software, but the hchalted bit is not
+                                                                yet set.
+                                                          1'b1: Disables the automatic feature, which takes all ports out of suspend when software
+                                                                clears the run/stop bit. This is for backward compatibility.
+                                                         This bit has an added functionality in release 2.80a and later. For systems where the host
+                                                         is halted without waking up all ports out of suspend, the port can become stuck because
+                                                         the PHYCLK is not running when the halt is programmed. To avoid this, the DWC H20AHB host
+                                                         core automatically pulls ports out of suspend when the host is halted by software. This bit
+                                                         is used to disable this automatic function. */
+	uint32_t nakrf_dis                    : 1;  /**< NAK Reload Fix Disable.
+                                                         1b0: NAK reload fix enabled.
+                                                         1b1: NAK reload fix disabled. (Incorrect NAK reload transition at the end of a microframe
+                                                              for backward compatibility with Release 2.40c. For more information see the USB 2.0
+                                                              Host-AHB Release Notes. */
+	uint32_t reserved_3_3                 : 1;
+	uint32_t pesd                         : 1;  /**< Scales down port enumeration time.
+                                                          1'b1: scale down enabled
+                                                          1'b0:  scale downd disabled
+                                                         This is for simulation only. */
+	uint32_t hcp_fw                       : 1;  /**< HCCPARAMS Field Writeable.
+                                                         1'b1: The HCCPARAMS register's bits 17, 15:4, and 2:0 become writable.
+                                                         1'b0: The HCCPARAMS register's bits 17, 15:4, and 2:0 are not writable. */
+	uint32_t hcp_rw                       : 1;  /**< HCCPARAMS Reigster Writeable.
+                                                         1'b1: The HCCPARAMS register becomes writable.
+                                                         1'b0: The HCCPARAMS register is not writable. */
+#else
+	uint32_t hcp_rw                       : 1;
+	uint32_t hcp_fw                       : 1;
+	uint32_t pesd                         : 1;
+	uint32_t reserved_3_3                 : 1;
+	uint32_t nakrf_dis                    : 1;
+	uint32_t auto_dis                     : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn63xx;
+	struct cvmx_uahcx_ehci_insnreg04_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t;
+
+/**
+ * cvmx_uahc#_ehci_insnreg06
+ *
+ * EHCI_INSNREG06 = EHCI  AHB Error Status Register (Synopsys Speicific)
+ * This register contains AHB Error Status.
+ */
+union cvmx_uahcx_ehci_insnreg06
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_insnreg06_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t vld                          : 1;  /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
+                                                         To clear this field the application must write a 0 to it. */
+	uint32_t reserved_0_30                : 31;
+#else
+	uint32_t reserved_0_30                : 31;
+	uint32_t vld                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn63xx;
+	struct cvmx_uahcx_ehci_insnreg06_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t;
+
+/**
+ * cvmx_uahc#_ehci_insnreg07
+ *
+ * EHCI_INSNREG07 = EHCI  AHB Error Address Register (Synopsys Speicific)
+ * This register contains AHB Error Status.
+ */
+union cvmx_uahcx_ehci_insnreg07
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_insnreg07_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t err_addr                     : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
+#else
+	uint32_t err_addr                     : 32;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn63xx;
+	struct cvmx_uahcx_ehci_insnreg07_s    cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t;
+
+/**
+ * cvmx_uahc#_ehci_periodiclistbase
+ *
+ * PERIODICLISTBASE = Periodic Frame List Base Address Register
+ *
+ * This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the
+ * host controller is in 64-bit mode (as indicated by a one in the 64-bit Addressing Capability field in the
+ * HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes
+ * from the CTRLDSSEGMENT register (see Section 2.3.5). System software loads this register prior to
+ * starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this
+ * physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with
+ * the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List
+ * in sequence.
+ */
+union cvmx_uahcx_ehci_periodiclistbase
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_periodiclistbase_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t baddr                        : 20; /**< Base Address (Low). These bits correspond to memory address signals [31:12],respectively. */
+	uint32_t reserved_0_11                : 12;
+#else
+	uint32_t reserved_0_11                : 12;
+	uint32_t baddr                        : 20;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn63xx;
+	struct cvmx_uahcx_ehci_periodiclistbase_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_t;
+
+/**
+ * cvmx_uahc#_ehci_portsc#
+ *
+ * PORTSCX = Port X Status and Control Register
+ * Default: 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero)
+ */
+union cvmx_uahcx_ehci_portscx
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_portscx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_23_31               : 9;
+	uint32_t wkoc_e                       : 1;  /**< Wake on Over-current Enable.Writing this bit to a
+                                                         one enables the port to be sensitive to over-current conditions as wake-up events.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t wkdscnnt_e                   : 1;  /**< Wake on Disconnect Enable. Writing this bit to a one enables the port to be
+                                                         sensitive to device disconnects as wake-up events.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t wkcnnt_e                     : 1;  /**< Wake on Connect Enable. Writing this bit to a one enables the port to be
+                                                         sensitive to device connects as wake-up events.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t ptc                          : 4;  /**< Port Test Control. When this field is zero, the port is NOT
+                                                         operating in a test mode. A non-zero value indicates that it is operating
+                                                         in test mode and the specific test mode is indicated by the specific value.
+                                                         The encoding of the test mode bits are (0110b - 1111b are reserved):
+                                                         Bits Test Mode
+                                                          0000b Test mode not enabled
+                                                          0001b Test J_STATE
+                                                          0010b Test K_STATE
+                                                          0011b Test SE0_NAK
+                                                          0100b Test Packet
+                                                          0101b Test FORCE_ENABLE */
+	uint32_t pic                          : 2;  /**< Port Indicator Control. Writing to these bits has no effect if the
+                                                         P_INDICATOR bit in the HCSPARAMS register is a zero. If P_INDICATOR bit is a one,
+                                                         then the bit encodings are:
+                                                         Bit Value Meaning
+                                                          00b Port indicators are off
+                                                          01b Amber
+                                                          10b Green
+                                                          11b Undefined
+                                                         This field is zero if Port Power is zero. */
+	uint32_t po                           : 1;  /**< Port Owner.This bit unconditionally goes to a 0b when the
+                                                         Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit
+                                                         unconditionally goes to 1b whenever the Configured bit is zero.
+                                                         System software uses this field to release ownership of the port to a selected host
+                                                         controller (in the event that the attached device is not a high-speed device). Software
+                                                         writes a one to this bit when the attached device is not a high-speed device. A one in
+                                                         this bit means that a companion host controller owns and controls the port. */
+	uint32_t pp                           : 1;  /**< Port Power. The function of this bit depends on the value of the Port
+                                                         Power Control (PPC) field in the HCSPARAMS register. The behavior is as follows:
+                                                         PPC PP    Operation
+                                                          0b 1b    RO  - Host controller does not have port power control switches.
+                                                                         Each port is hard-wired to power.
+                                                          1b 1b/0b R/W - Host controller has port power control switches. This bit
+                                                                         represents the current setting of the switch (0 = off, 1 = on). When
+                                                                         power is not available on a port (i.e. PP equals a 0), the port is
+                                                                         nonfunctional  and will not report attaches, detaches, etc.
+                                                         When an over-current condition is detected on a powered port and PPC is a one, the PP
+                                                         bit in each affected port may be transitioned by the host controller from a 1 to 0
+                                                         (removing power from the port). */
+	uint32_t lsts                         : 2;  /**< Line Status.These bits reflect the current logical levels of the D+ (bit 11) and D(bit 10)
+                                                          signal lines. These bits are used for detection of low-speed USB devices prior to
+                                                          the port reset and enable sequence. This field is valid only when the port enable bit is
+                                                          zero and the current connect status bit is set to a one.
+                                                          The encoding of the bits are:
+                                                           Bits[11:10] USB State   Interpretation
+                                                           00b         SE0         Not Low-speed device, perform EHCI reset
+                                                           10b         J-state     Not Low-speed device, perform EHCI reset
+                                                           01b         K-state     Low-speed device, release ownership of port
+                                                           11b         Undefined   Not Low-speed device, perform EHCI reset.
+                                                         This value of this field is undefined if Port Power is zero. */
+	uint32_t reserved_9_9                 : 1;
+	uint32_t prst                         : 1;  /**< Port Reset.1=Port is in Reset. 0=Port is not in Reset. Default = 0. When
+                                                         software writes a one to this bit (from a zero), the bus reset sequence as defined in the
+                                                         USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate
+                                                         the bus reset sequence. Software must keep this bit at a one long enough to ensure the
+                                                         reset sequence, as specified in the USB Specification Revision 2.0, completes. Note:
+                                                         when software writes this bit to a one, it must also write a zero to the Port Enable bit.
+                                                         Note that when software writes a zero to this bit there may be a delay before the bit
+                                                         status changes to a zero. The bit status will not read as a zero until after the reset has
+                                                         completed. If the port is in high-speed mode after reset is complete, the host controller
+                                                         will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller
+                                                         must terminate the reset and stabilize the state of the port within 2 milliseconds of
+                                                         software transitioning this bit from a one to a zero. For example: if the port detects that
+                                                         the attached device is high-speed during reset, then the host controller must have the
+                                                         port in the enabled state within 2ms of software writing this bit to a zero.
+                                                         The HCHalted bit in the USBSTS register should be a zero before software attempts to
+                                                         use this bit. The host controller may hold Port Reset asserted to a one when the
+                                                         HCHalted bit is a one.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t spd                          : 1;  /**< Suspend. 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port
+                                                         Enabled Bit and Suspend bit of this register define the port states as follows:
+                                                         Bits [Port Enabled, Suspend]     Port State
+                                                                      0X                  Disable
+                                                                      10                  Enable
+                                                                      11                  Suspend
+                                                         When in suspend state, downstream propagation of data is blocked on this port, except
+                                                         for port reset. The blocking occurs at the end of the current transaction, if a transaction
+                                                         was in progress when this bit was written to 1. In the suspend state, the port is sensitive
+                                                         to resume detection. Note that the bit status does not change until the port is
+                                                         suspended and that there may be a delay in suspending a port if there is a transaction
+                                                         currently in progress on the USB.
+                                                         A write of zero to this bit is ignored by the host controller. The host controller will
+                                                         unconditionally set this bit to a zero when:
+                                                         . Software sets the Force Port Resume bit to a zero (from a one).
+                                                         . Software sets the Port Reset bit to a one (from a zero).
+                                                         If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is
+                                                         a zero) the results are undefined.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t fpr                          : 1;  /**< Force Port Resume.
+                                                         1= Resume detected/driven on port. 0=No resume (Kstate)
+                                                         detected/driven on port. Default = 0. This functionality defined for manipulating
+                                                         this bit depends on the value of the Suspend bit. For example, if the port is not
+                                                         suspended (Suspend and Enabled bits are a one) and software transitions this bit to a
+                                                         one, then the effects on the bus are undefined.
+                                                         Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to
+                                                         a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit
+                                                         transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in
+                                                         the USBSTS register is also set to a one. If software sets this bit to a one, the host
+                                                         controller must not set the Port Change Detect bit.
+                                                         Note that when the EHCI controller owns the port, the resume sequence follows the
+                                                         defined sequence documented in the USB Specification Revision 2.0. The resume
+                                                         signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. Software
+                                                         must appropriately time the Resume and set this bit to a zero when the appropriate
+                                                         amount of time has elapsed. Writing a zero (from one) causes the port to return to high-
+                                                         speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a
+                                                         one until the port has switched to the high-speed idle. The host controller must complete
+                                                         this transition within 2 milliseconds of software setting this bit to a zero.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t occ                          : 1;  /**< Over-current Change. 1=This bit gets set to a one when there is a change to Over-current Active.
+                                                         Software clears this bit by writing a one to this bit position. */
+	uint32_t oca                          : 1;  /**< Over-current Active. 1=This port currently has an over-current condition. 0=This port does not
+                                                         have an over-current condition. This bit will automatically transition from a one to a zero when
+                                                         the over current condition is removed. */
+	uint32_t pedc                         : 1;  /**< Port Enable/Disable Change. 1=Port enabled/disabled status has changed.
+                                                         0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is
+                                                               disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of
+                                                         the USB Specification for the definition of a Port Error). Software clears this bit by writing
+                                                         a 1 to it.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t ped                          : 1;  /**< Port Enabled/Disabled. 1=Enable. 0=Disable. Ports can only be
+                                                         enabled by the host controller as a part of the reset and enable. Software cannot enable
+                                                         a port by writing a one to this field. The host controller will only set this bit to a one when
+                                                         the reset sequence determines that the attached device is a high-speed device.
+                                                         Ports can be disabled by either a fault condition (disconnect event or other fault
+                                                         condition) or by host software. Note that the bit status does not change until the port
+                                                         state actually changes. There may be a delay in disabling or enabling a port due to other
+                                                         host controller and bus events. See Section 4.2 for full details on port reset and enable.
+                                                         When the port is disabled (0b) downstream propagation of data is blocked on this port,
+                                                         except for reset.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t csc                          : 1;  /**< Connect Status Change. 1=Change in Current Connect Status. 0=No change. Indicates a change
+                                                         has occurred in the port's Current Connect Status. The host controller sets this bit for all
+                                                         changes to the port device connect status, even if system software has not cleared an existing
+                                                         connect status change. For example, the insertion status changes twice before system software
+                                                         has cleared the changed condition, hub hardware will be setting an already-set bit
+                                                         (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it.
+                                                         This field is zero if Port Power is zero. */
+	uint32_t ccs                          : 1;  /**< Current Connect Status. 1=Device is present on port. 0=No device is present.
+                                                         This value reflects the current state of the port, and may not correspond
+                                                         directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
+                                                         This field is zero if Port Power is zero. */
+#else
+	uint32_t ccs                          : 1;
+	uint32_t csc                          : 1;
+	uint32_t ped                          : 1;
+	uint32_t pedc                         : 1;
+	uint32_t oca                          : 1;
+	uint32_t occ                          : 1;
+	uint32_t fpr                          : 1;
+	uint32_t spd                          : 1;
+	uint32_t prst                         : 1;
+	uint32_t reserved_9_9                 : 1;
+	uint32_t lsts                         : 2;
+	uint32_t pp                           : 1;
+	uint32_t po                           : 1;
+	uint32_t pic                          : 2;
+	uint32_t ptc                          : 4;
+	uint32_t wkcnnt_e                     : 1;
+	uint32_t wkdscnnt_e                   : 1;
+	uint32_t wkoc_e                       : 1;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_portscx_s      cn63xx;
+	struct cvmx_uahcx_ehci_portscx_s      cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t;
+
+/**
+ * cvmx_uahc#_ehci_usbcmd
+ *
+ * USBCMD = USB Command Register
+ * The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed.
+ */
+union cvmx_uahcx_ehci_usbcmd
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_usbcmd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_24_31               : 8;
+	uint32_t itc                          : 8;  /**< Interrupt Threshold Control. This field is used by system software
+                                                         to select the maximum rate at which the host controller will issue interrupts. The only
+                                                         valid values are defined below. If software writes an invalid value to this register, the
+                                                         results are undefined. Value Maximum Interrupt Interval
+                                                           00h Reserved
+                                                           01h 1 micro-frame
+                                                           02h 2 micro-frames
+                                                           04h 4 micro-frames
+                                                           08h 8 micro-frames (default, equates to 1 ms)
+                                                           10h 16 micro-frames (2 ms)
+                                                           20h 32 micro-frames (4 ms)
+                                                           40h 64 micro-frames (8 ms) */
+	uint32_t reserved_12_15               : 4;
+	uint32_t aspm_en                      : 1;  /**< Asynchronous Schedule Park Mode Enable. */
+	uint32_t reserved_10_10               : 1;
+	uint32_t aspmc                        : 2;  /**< Asynchronous Schedule Park Mode Count. */
+	uint32_t lhcr                         : 1;  /**< Light Host Controller Reset */
+	uint32_t iaa_db                       : 1;  /**< Interrupt on Async Advance Doorbell.This bit is used as a doorbell by
+                                                         software to tell the host controller to issue an interrupt the next time it advances
+                                                         asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
+                                                         When the host controller has evicted all appropriate cached schedule state, it sets the
+                                                         Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async
+                                                         Advance Enable bit in the USBINTR register is a one then the host controller will assert
+                                                         an interrupt at the next interrupt threshold. */
+	uint32_t as_en                        : 1;  /**< Asynchronous Schedule Enable .This bit controls whether the host
+                                                         controller skips processing the Asynchronous Schedule. Values mean:
+                                                          - 0: Do not process the Asynchronous Schedule
+                                                          - 1: Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */
+	uint32_t ps_en                        : 1;  /**< Periodic Schedule Enable. This bit controls whether the host
+                                                         controller skips processing the Periodic Schedule. Values mean:
+                                                            - 0: Do not process the Periodic Schedule
+                                                            - 1: Use the PERIODICLISTBASE register to access the Periodic Schedule. */
+	uint32_t fls                          : 2;  /**< Frame List Size. This field is R/W only if Programmable
+                                                         Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the
+                                                         size of the frame list. The size the frame list controls which bits in the Frame Index
+                                                         Register should be used for the Frame List Current index. Values mean:
+                                                              00b: 1024 elements (4096 bytes) Default value
+                                                              01b: 512 elements  (2048 bytes)
+                                                              10b: 256 elements  (1024 bytes) - for resource-constrained environments
+                                                              11b: Reserved */
+	uint32_t hcreset                      : 1;  /**< Host Controller Reset (HCRESET). This control bit is used by software to reset
+                                                         the host controller. The effects of this on Root Hub registers are similar to a Chip
+                                                         Hardware Reset. When software writes a one to this bit, the Host Controller resets
+                                                         its internal pipelines, timers, counters, state machines, etc. to their initial
+                                                         value. Any transaction currently in progress on USB is immediately terminated.
+                                                         A USB reset is not driven on downstream ports.
+                                                         This bit is set to zero by the Host Controller when the reset process is complete. Software can not
+                                                         terminate the reset process early by writing zero to this register.
+                                                         Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.
+                                                         Attempting to reset an activtely running host controller will result in undefined behavior. */
+	uint32_t rs                           : 1;  /**< Run/Stop (RS).
+                                                           1=Run. 0=Stop.
+                                                         When set to a 1, the Host Controller proceeds with execution of the schedule.
+                                                         The Host Controller continues execution as long as this bit is set to a 1.
+                                                         When this bit is set to 0, the Host Controller completes the current and any
+                                                         actively pipelined transactions on the USB and then halts. The Host
+                                                         Controller must halt within 16 micro-frames after software clears the Run bit. The HC
+                                                         Halted bit in the status register indicates when the Host Controller has finished its
+                                                         pending pipelined transactions and has entered the stopped state. Software must not
+                                                         write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in
+                                                         the USBSTS register is a one). Doing so will yield undefined results. */
+#else
+	uint32_t rs                           : 1;
+	uint32_t hcreset                      : 1;
+	uint32_t fls                          : 2;
+	uint32_t ps_en                        : 1;
+	uint32_t as_en                        : 1;
+	uint32_t iaa_db                       : 1;
+	uint32_t lhcr                         : 1;
+	uint32_t aspmc                        : 2;
+	uint32_t reserved_10_10               : 1;
+	uint32_t aspm_en                      : 1;
+	uint32_t reserved_12_15               : 4;
+	uint32_t itc                          : 8;
+	uint32_t reserved_24_31               : 8;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn63xx;
+	struct cvmx_uahcx_ehci_usbcmd_s       cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t;
+
+/**
+ * cvmx_uahc#_ehci_usbintr
+ *
+ * USBINTR = USB Interrupt Enable Register
+ * This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set
+ * and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are
+ * disabled in this register still appear in the USBSTS to allow the software to poll for events.
+ * Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism.
+ * Note: for all enable register bits, 1= Enabled, 0= Disabled
+ */
+union cvmx_uahcx_ehci_usbintr
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_usbintr_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_6_31                : 26;
+	uint32_t ioaa_en                      : 1;  /**< Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on
+                                                         Async Advance bit in the USBSTS register is a one, the host controller will issue an
+                                                         interrupt at the next interrupt threshold. The interrupt is acknowledged by software
+                                                         clearing the Interrupt on Async Advance bit. */
+	uint32_t hserr_en                     : 1;  /**< Host System Error Enable When this bit is a one, and the Host System
+                                                         Error Status bit in the USBSTS register is a one, the host controller will issue an
+                                                         interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. */
+	uint32_t flro_en                      : 1;  /**< Frame List Rollover Enable. When this bit is a one, and the Frame List
+                                                         Rollover bit in the USBSTS register is a one, the host controller will issue an
+                                                         interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. */
+	uint32_t pci_en                       : 1;  /**< Port Change Interrupt Enable. When this bit is a one, and the Port Change Detect bit in
+                                                         the USBSTS register is a one, the host controller will issue an interrupt.
+                                                         The interrupt is acknowledged by software clearing the Port Change Detect bit. */
+	uint32_t usberrint_en                 : 1;  /**< USB Error Interrupt Enable. When this bit is a one, and the USBERRINT
+                                                         bit in the USBSTS register is a one, the host controller will issue an interrupt at the next
+                                                         interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. */
+	uint32_t usbint_en                    : 1;  /**< USB Interrupt Enable. When this bit is a one, and the USBINT bit in the USBSTS register
+                                                         is a one, the host controller will issue an interrupt at the next interrupt threshold.
+                                                         The interrupt is acknowledged by software clearing the USBINT bit. */
+#else
+	uint32_t usbint_en                    : 1;
+	uint32_t usberrint_en                 : 1;
+	uint32_t pci_en                       : 1;
+	uint32_t flro_en                      : 1;
+	uint32_t hserr_en                     : 1;
+	uint32_t ioaa_en                      : 1;
+	uint32_t reserved_6_31                : 26;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_usbintr_s      cn63xx;
+	struct cvmx_uahcx_ehci_usbintr_s      cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t;
+
+/**
+ * cvmx_uahc#_ehci_usbsts
+ *
+ * USBSTS = USB Status Register
+ * This register indicates pending interrupts and various states of the Host Controller. The status resulting from
+ * a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by
+ * writing a 1 to it.
+ */
+union cvmx_uahcx_ehci_usbsts
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ehci_usbsts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t ass                          : 1;  /**< Asynchronous Schedule Status. The bit reports the current real
+                                                         status of the Asynchronous Schedule. If this bit is a zero then the status of the
+                                                         Asynchronous Schedule is disabled. If this bit is a one then the status of the
+                                                         Asynchronous Schedule is enabled. The Host Controller is not required to immediately
+                                                         disable or enable the Asynchronous Schedule when software transitions the
+                                                         Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the
+                                                         Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is
+                                                         either enabled (1) or disabled (0). */
+	uint32_t pss                          : 1;  /**< Periodic Schedule Status. The bit reports the current real status of
+                                                         the Periodic Schedule. If this bit is a zero then the status of the Periodic
+                                                         Schedule is disabled. If this bit is a one then the status of the Periodic Schedule
+                                                         is enabled. The Host Controller is not required to immediately disable or enable the
+                                                         Periodic Schedule when software transitions the Periodic Schedule Enable bit in
+                                                         the USBCMD register. When this bit and the Periodic Schedule Enable bit are the
+                                                         same value, the Periodic Schedule is either enabled (1) or disabled (0). */
+	uint32_t reclm                        : 1;  /**< Reclamation.This is a read-only status bit, which is used to detect an
+                                                         empty asynchronous schedule. */
+	uint32_t hchtd                        : 1;  /**< HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The
+                                                         Host Controller sets this bit to one after it has stopped executing as a result of the
+                                                         Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
+                                                         internal error). */
+	uint32_t reserved_6_11                : 6;
+	uint32_t ioaa                         : 1;  /**< Interrupt on Async Advance. System software can force the host
+                                                         controller to issue an interrupt the next time the host controller advances the
+                                                         asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit
+                                                         in the USBCMD register. This status bit indicates the assertion of that interrupt source. */
+	uint32_t hsyserr                      : 1;  /**< Host System Error. The Host Controller sets this bit to 1 when a serious error
+                                                         occurs during a host system access involving the Host Controller module. */
+	uint32_t flro                         : 1;  /**< Frame List Rollover. The Host Controller sets this bit to a one when the
+                                                         Frame List Index rolls over from its maximum value to zero. The exact value at
+                                                         which the rollover occurs depends on the frame list size. For example, if
+                                                         the frame list size (as programmed in the Frame List Size field of the USBCMD register)
+                                                         is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly,
+                                                         if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12]
+                                                         toggles. */
+	uint32_t pcd                          : 1;  /**< Port Change Detect. The Host Controller sets this bit to a one when any port
+                                                         for which the Port Owner bit is set to zero (see Section 2.3.9) has a change bit transition
+                                                         from a zero to a one or a Force Port Resume bit transition from a zero to a one as a
+                                                         result of a J-K transition detected on a suspended port. This bit will also be set as a
+                                                         result of the Connect Status Change being set to a one after system software has
+                                                         relinquished ownership of a connected port by writing a one to a port's Port Owner bit. */
+	uint32_t usberrint                    : 1;  /**< USB Error Interrupt. The Host Controller sets this bit to 1 when completion of a USB
+                                                         transaction results in an error condition (e.g., error counter underflow). If the TD on
+                                                         which the error interrupt occurred also had its IOC bit set, both this bit and USBINT
+                                                         bit are set. */
+	uint32_t usbint                       : 1;  /**< USB Interrupt. The Host Controller sets this bit to 1 on the completion of a USB
+                                                         transaction, which results in the retirement of a Transfer Descriptor that had its
+                                                         IOC bit set. The Host Controller also sets this bit to 1 when a short packet is
+                                                         detected (actual number of bytes received was less than the expected number of bytes). */
+#else
+	uint32_t usbint                       : 1;
+	uint32_t usberrint                    : 1;
+	uint32_t pcd                          : 1;
+	uint32_t flro                         : 1;
+	uint32_t hsyserr                      : 1;
+	uint32_t ioaa                         : 1;
+	uint32_t reserved_6_11                : 6;
+	uint32_t hchtd                        : 1;
+	uint32_t reclm                        : 1;
+	uint32_t pss                          : 1;
+	uint32_t ass                          : 1;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_uahcx_ehci_usbsts_s       cn63xx;
+	struct cvmx_uahcx_ehci_usbsts_s       cn63xxp1;
+};
+typedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcbulkcurrented
+ *
+ * HCBULKCURRENTED = Host Controller Bulk Current ED Register
+ *
+ * The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin
+ * fashion, the endpoints will be ordered according to their insertion to the list.
+ */
+union cvmx_uahcx_ohci0_hcbulkcurrented
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bced                         : 28; /**< BulkCurrentED. This is advanced to the next ED after the HC has served the
+                                                         present one. HC continues processing the list from where it left off in the
+                                                         last Frame. When it reaches the end of the Bulk list, HC checks the
+                                                         ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED
+                                                         to HcBulkCurrentED and clears the bit. If it is not set, it does nothing.
+                                                         HCD is only allowed to modify this register when the BulkListEnable of
+                                                         HcControl is cleared. When set, the HCD only reads the instantaneous value of
+                                                         this register. This is initially set to zero to indicate the end of the Bulk
+                                                         list. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t bced                         : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcbulkheaded
+ *
+ * HCBULKHEADED = Host Controller Bulk Head ED Register
+ *
+ * The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list.
+ */
+union cvmx_uahcx_ohci0_hcbulkheaded
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t bhed                         : 28; /**< BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED
+                                                         pointer. The content is loaded from HCCA during the initialization of HC. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t bhed                         : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t;
+
+/**
+ * cvmx_uahc#_ohci0_hccommandstatus
+ *
+ * HCCOMMANDSTATUS = Host Controller Command Status Register
+ *
+ * The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the
+ * current status of the Host Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure
+ * that bits written as '1' become set in the register while bits written as '0' remain unchanged in the register. The Host Controller Driver
+ * may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver
+ * has normal read access to all bits.
+ * The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This
+ * occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter
+ * and sets the SchedulingOverrun field in the HcInterruptStatus register.
+ */
+union cvmx_uahcx_ohci0_hccommandstatus
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_18_31               : 14;
+	uint32_t soc                          : 2;  /**< SchedulingOverrunCount. These bits are incremented on each scheduling overrun
+                                                         error. It is initialized to 00b and wraps around at 11b. This will be
+                                                         incremented when a scheduling overrun is detected even if SchedulingOverrun
+                                                         in HcInterruptStatus has already been set. This is used by HCD to monitor
+                                                         any persistent scheduling problems. */
+	uint32_t reserved_4_15                : 12;
+	uint32_t ocr                          : 1;  /**< OwnershipChangeRequest. This bit is set by an OS HCD to request a change of
+                                                         control of the HC. When set HC will set the OwnershipChange field in
+                                                         HcInterruptStatus. After the changeover, this bit is cleared and remains so
+                                                         until the next request from OS HCD. */
+	uint32_t blf                          : 1;  /**< BulkListFilled This bit is used to indicate whether there are any TDs on the
+                                                         Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list.
+                                                         When HC begins to process the head of the Bulk list, it checks BF. As long
+                                                         as BulkListFilled is 0, HC will not start processing the Bulk list. If
+                                                         BulkListFilled is 1, HC will start processing the Bulk list and will set BF
+                                                         to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1
+                                                         causing the Bulk list processing to continue. If no TD is found on the Bulk
+                                                         list,and if HCD does not set BulkListFilled, then BulkListFilled will still
+                                                         be 0 when HC completes processing the Bulk list and Bulk list processing will
+                                                         stop. */
+	uint32_t clf                          : 1;  /**< ControlListFilled. This bit is used to indicate whether there are any TDs
+                                                         on the Control list. It is set by HCD whenever it adds a TD to an ED in the
+                                                         Control list. When HC begins to process the head of the Control list, it
+                                                         checks CLF. As long as ControlListFilled is 0, HC will not start processing
+                                                         the Control list. If CF is 1, HC will start processing the Control list and
+                                                         will set ControlListFilled to 0. If HC finds a TD on the list, then HC will
+                                                         set ControlListFilled to 1 causing the Control list processing to continue.
+                                                         If no TD is found on the Control list, and if the HCD does not set
+                                                         ControlListFilled, then ControlListFilled will still be 0 when HC completes
+                                                         processing the Control list and Control list processing will stop. */
+	uint32_t hcr                          : 1;  /**< HostControllerReset. This bit is set by HCD to initiate a software reset of
+                                                         HC. Regardless of the functional state of HC, it moves to the USBSUSPEND
+                                                         state in which most of the operational registers are reset except those
+                                                         stated otherwise; e.g., the InterruptRouting field of HcControl, and no
+                                                         Host bus accesses are allowed. This bit is cleared by HC upon the
+                                                         completion of the reset operation. The reset operation must be completed
+                                                         within 10 ms. This bit, when set, should not cause a reset to the Root Hub
+                                                         and no subsequent reset signaling should be asserted to its downstream ports. */
+#else
+	uint32_t hcr                          : 1;
+	uint32_t clf                          : 1;
+	uint32_t blf                          : 1;
+	uint32_t ocr                          : 1;
+	uint32_t reserved_4_15                : 12;
+	uint32_t soc                          : 2;
+	uint32_t reserved_18_31               : 14;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xx;
+	struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_t;
+
+/**
+ * cvmx_uahc#_ohci0_hccontrol
+ *
+ * HCCONTROL = Host Controller Control Register
+ *
+ * The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller
+ * Driver, except HostControllerFunctionalState and RemoteWakeupConnected.
+ */
+union cvmx_uahcx_ohci0_hccontrol
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hccontrol_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_11_31               : 21;
+	uint32_t rwe                          : 1;  /**< RemoteWakeupEnable. This bit is used by HCD to enable or disable the remote wakeup
+                                                         feature upon the detection of upstream resume signaling. When this bit is set and
+                                                         the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled
+                                                         to the host system. Setting this bit has no impact on the generation of hardware
+                                                         interrupt. */
+	uint32_t rwc                          : 1;  /**< RemoteWakeupConnected.This bit indicates whether HC supports remote wakeup signaling.
+                                                         If remote wakeup is supported and used by the system it is the responsibility of
+                                                         system firmware to set this bit during POST. HC clears the bit upon a hardware reset
+                                                         but does not alter it upon a software reset. Remote wakeup signaling of the host
+                                                         system is host-bus-specific and is not described in this specification. */
+	uint32_t ir                           : 1;  /**< InterruptRouting
+                                                         This bit determines the routing of interrupts generated by events registered in
+                                                         HcInterruptStatus. If clear, all interrupts are routed to the normal host bus
+                                                         interrupt mechanism. If set, interrupts are routed to the System Management
+                                                         Interrupt. HCD clears this bit upon a hardware reset, but it does not alter
+                                                         this bit upon a software reset. HCD uses this bit as a tag to indicate the
+                                                         ownership of HC. */
+	uint32_t hcfs                         : 2;  /**< HostControllerFunctionalState for USB
+                                                          00b: USBRESET
+                                                          01b: USBRESUME
+                                                          10b: USBOPERATIONAL
+                                                          11b: USBSUSPEND
+                                                         A transition to USBOPERATIONAL from another state causes SOF generation to begin
+                                                         1 ms later. HCD may determine whether HC has begun sending SOFs by reading the
+                                                         StartofFrame field of HcInterruptStatus.
+                                                         This field may be changed by HC only when in the USBSUSPEND state. HC may move from
+                                                         the USBSUSPEND state to the USBRESUME state after detecting the resume signaling
+                                                         from a downstream port.
+                                                         HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a
+                                                         hardware reset. The latter also resets the Root Hub and asserts subsequent reset
+                                                         signaling to downstream ports. */
+	uint32_t ble                          : 1;  /**< BulkListEnable. This bit is set to enable the processing of the Bulk list in the
+                                                         next Frame. If cleared by HCD, processing of the Bulk list does not occur after
+                                                         the next SOF. HC checks this bit whenever it determines to process the list. When
+                                                         disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be
+                                                         removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling
+                                                         processing of the list. */
+	uint32_t cle                          : 1;  /**< ControlListEnable. This bit is set to enable the processing of the Control list in
+                                                         the next Frame. If cleared by HCD, processing of the Control list does not occur
+                                                         after the next SOF. HC must check this bit whenever it determines to process the
+                                                         list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to
+                                                         an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED
+                                                         before re-enabling processing of the list. */
+	uint32_t ie                           : 1;  /**< IsochronousEnable This bit is used by HCD to enable/disable processing of
+                                                         isochronous EDs. While processing the periodic list in a Frame, HC checks the
+                                                         status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
+                                                         continues processing the EDs. If cleared (disabled), HC halts processing of the
+                                                         periodic list (which now contains only isochronous EDs) and begins processing the
+                                                         Bulk/Control lists. Setting this bit is guaranteed to take effect in the next
+                                                         Frame (not the current Frame). */
+	uint32_t ple                          : 1;  /**< PeriodicListEnable. This bit is set to enable the processing of the periodic list
+                                                         in the next Frame. If cleared by HCD, processing of the periodic list does not
+                                                         occur after the next SOF. HC must check this bit before it starts processing
+                                                         the list. */
+	uint32_t cbsr                         : 2;  /**< ControlBulkServiceRatio. This specifies the service ratio between Control and
+                                                         Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the
+                                                         ratio specified with its internal count on how many nonempty Control EDs have
+                                                         been processed, in determining whether to continue serving another Control ED
+                                                         or switching to Bulk EDs. The internal count will be retained when crossing
+                                                         the frame boundary. In case of reset, HCD is responsible for restoring this
+                                                         value.
+
+                                                           CBSR   No. of Control EDs Over Bulk EDs Served
+                                                            0             1:1
+                                                            1             2:1
+                                                            2             3:1
+                                                            3             4:1 */
+#else
+	uint32_t cbsr                         : 2;
+	uint32_t ple                          : 1;
+	uint32_t ie                           : 1;
+	uint32_t cle                          : 1;
+	uint32_t ble                          : 1;
+	uint32_t hcfs                         : 2;
+	uint32_t ir                           : 1;
+	uint32_t rwc                          : 1;
+	uint32_t rwe                          : 1;
+	uint32_t reserved_11_31               : 21;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn63xx;
+	struct cvmx_uahcx_ohci0_hccontrol_s   cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t;
+
+/**
+ * cvmx_uahc#_ohci0_hccontrolcurrented
+ *
+ * HCCONTROLCURRENTED = Host Controller Control Current ED Register
+ *
+ * The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list.
+ */
+union cvmx_uahcx_ohci0_hccontrolcurrented
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t cced                         : 28; /**< ControlCurrentED. This pointer is advanced to the next ED after serving the
+                                                         present one. HC will continue processing the list from where it left off in
+                                                         the last Frame. When it reaches the end of the Control list, HC checks the
+                                                         ControlListFilled of in HcCommandStatus. If set, it copies the content of
+                                                         HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it
+                                                         does nothing. HCD is allowed to modify this register only when the
+                                                         ControlListEnable of HcControl is cleared. When set, HCD only reads the
+                                                         instantaneous value of this register. Initially, this is set to zero to
+                                                         indicate the end of the Control list. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t cced                         : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xx;
+	struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurrented_t;
+
+/**
+ * cvmx_uahc#_ohci0_hccontrolheaded
+ *
+ * HCCONTROLHEADED = Host Controller Control Head ED Register
+ *
+ * The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list.
+ */
+union cvmx_uahcx_ohci0_hccontrolheaded
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ched                         : 28; /**< ControlHeadED. HC traverses the Control list starting with the HcControlHeadED
+                                                         pointer. The content is loaded from HCCA during the initialization of HC. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t ched                         : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xx;
+	struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcdonehead
+ *
+ * HCDONEHEAD = Host Controller Done Head Register
+ *
+ * The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation,
+ * the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA.
+ */
+union cvmx_uahcx_ohci0_hcdonehead
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcdonehead_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dh                           : 28; /**< DoneHead. When a TD is completed, HC writes the content of HcDoneHead to the
+                                                         NextTD field of the TD. HC then overwrites the content of HcDoneHead with the
+                                                         address of this TD. This is set to zero whenever HC writes the content of
+                                                         this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t dh                           : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn63xx;
+	struct cvmx_uahcx_ohci0_hcdonehead_s  cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcfminterval
+ *
+ * HCFMINTERVAL = Host Controller Frame Interval Register
+ *
+ * The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value
+ * indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver
+ * may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for
+ * the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset.
+ */
+union cvmx_uahcx_ohci0_hcfminterval
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcfminterval_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t fit                          : 1;  /**< FrameIntervalToggle. HCD toggles this bit whenever it loads a new value to
+                                                         FrameInterval. */
+	uint32_t fsmps                        : 15; /**< FSLargestDataPacket. This field specifies a value which is loaded into the
+                                                         Largest Data Packet Counter at the beginning of each frame. The counter value
+                                                         represents the largest amount of data in bits which can be sent or received by
+                                                         the HC in a single transaction at any given time without causing scheduling
+                                                         overrun. The field value is calculated by the HCD. */
+	uint32_t reserved_14_15               : 2;
+	uint32_t fi                           : 14; /**< FrameInterval. This specifies the interval between two consecutive SOFs in bit
+                                                         times. The nominal value is set to be 11,999. HCD should store the current
+                                                         value of this field before resetting HC. By setting the HostControllerReset
+                                                         field of HcCommandStatus as this will cause the HC to reset this field to its
+                                                         nominal value. HCD may choose to restore the stored value upon the completion
+                                                         of the Reset sequence. */
+#else
+	uint32_t fi                           : 14;
+	uint32_t reserved_14_15               : 2;
+	uint32_t fsmps                        : 15;
+	uint32_t fit                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcfminterval_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcfmnumber
+ *
+ * HCFMNUMBER = Host Cotroller Frame Number Register
+ *
+ * The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver.
+ * The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to
+ * the register.
+ */
+union cvmx_uahcx_ohci0_hcfmnumber
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t fn                           : 16; /**< FrameNumber. This is incremented when HcFmRemaining is re-loaded. It will be
+                                                         rolled over to 0h after ffffh. When entering the USBOPERATIONAL state,
+                                                         this will be incremented automatically. The content will be written to HCCA
+                                                         after HC has incremented the FrameNumber at each frame boundary and sent a
+                                                         SOF but before HC reads the first ED in that Frame. After writing to HCCA,
+                                                         HC will set the StartofFrame in HcInterruptStatus. */
+#else
+	uint32_t fn                           : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn63xx;
+	struct cvmx_uahcx_ohci0_hcfmnumber_s  cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcfmremaining
+ *
+ * HCFMREMAINING = Host Controller Frame Remaining Register
+ * The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame.
+ */
+union cvmx_uahcx_ohci0_hcfmremaining
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t frt                          : 1;  /**< FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field
+                                                         of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD
+                                                         for the synchronization between FrameInterval and FrameRemaining. */
+	uint32_t reserved_14_30               : 17;
+	uint32_t fr                           : 14; /**< FrameRemaining. This counter is decremented at each bit time. When it
+                                                         reaches zero, it is reset by loading the FrameInterval value specified in
+                                                         HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL
+                                                         state, HC re-loads the content with the FrameInterval of HcFmInterval and uses
+                                                         the updated value from the next SOF. */
+#else
+	uint32_t fr                           : 14;
+	uint32_t reserved_14_30               : 17;
+	uint32_t frt                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t;
+
+/**
+ * cvmx_uahc#_ohci0_hchcca
+ *
+ * HCHCCA =  Host Controller Host Controller Communication Area Register
+ *
+ * The HcHCCA register contains the physical address of the Host Controller Communication Area. The Host Controller Driver determines the alignment restrictions
+ * by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The
+ * minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. Detailed description can be found in Chapter 4. This area
+ * is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver.
+ */
+union cvmx_uahcx_ohci0_hchcca
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hchcca_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t hcca                         : 24; /**< This is the base address (bits [31:8]) of the Host Controller Communication Area. */
+	uint32_t reserved_0_7                 : 8;
+#else
+	uint32_t reserved_0_7                 : 8;
+	uint32_t hcca                         : 24;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn63xx;
+	struct cvmx_uahcx_ohci0_hchcca_s      cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcinterruptdisable
+ *
+ * HCINTERRUPTDISABLE = Host Controller InterruptDisable Register
+ *
+ * Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable
+ * register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable
+ * register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current
+ * value of the HcInterruptEnable register is returned.
+ */
+union cvmx_uahcx_ohci0_hcinterruptdisable
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mie                          : 1;  /**< A '0' written to this field is ignored by HC.
+                                                         A '1' written to this field disables interrupt generation due to events
+                                                         specified in the other bits of this register. This field is set after a
+                                                         hardware or software reset. */
+	uint32_t oc                           : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Ownership Change. */
+	uint32_t reserved_7_29                : 23;
+	uint32_t rhsc                         : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Root Hub Status Change. */
+	uint32_t fno                          : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Frame Number Overflow. */
+	uint32_t ue                           : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Unrecoverable Error. */
+	uint32_t rd                           : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Resume Detect. */
+	uint32_t sf                           : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Start of Frame. */
+	uint32_t wdh                          : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to HcDoneHead Writeback. */
+	uint32_t so                           : 1;  /**< 0 - Ignore; 1 - Disable interrupt generation due to Scheduling Overrun. */
+#else
+	uint32_t so                           : 1;
+	uint32_t wdh                          : 1;
+	uint32_t sf                           : 1;
+	uint32_t rd                           : 1;
+	uint32_t ue                           : 1;
+	uint32_t fno                          : 1;
+	uint32_t rhsc                         : 1;
+	uint32_t reserved_7_29                : 23;
+	uint32_t oc                           : 1;
+	uint32_t mie                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdisable_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcinterruptenable
+ *
+ * HCINTERRUPTENABLE = Host Controller InterruptEnable Register
+ *
+ * Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable
+ * register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit
+ * in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
+ * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit
+ * unchanged. On read, the current value of this register is returned.
+ */
+union cvmx_uahcx_ohci0_hcinterruptenable
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t mie                          : 1;  /**< A '0' written to this field is ignored by HC.
+                                                         A '1' written to this field enables interrupt generation due to events
+                                                         specified in the other bits of this register. This is used by HCD as a Master
+                                                         Interrupt Enable. */
+	uint32_t oc                           : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Ownership Change. */
+	uint32_t reserved_7_29                : 23;
+	uint32_t rhsc                         : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Root Hub Status Change. */
+	uint32_t fno                          : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Frame Number Overflow. */
+	uint32_t ue                           : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Unrecoverable Error. */
+	uint32_t rd                           : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Resume Detect. */
+	uint32_t sf                           : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Start of Frame. */
+	uint32_t wdh                          : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to HcDoneHead Writeback. */
+	uint32_t so                           : 1;  /**< 0 - Ignore; 1 - Enable interrupt generation due to Scheduling Overrun. */
+#else
+	uint32_t so                           : 1;
+	uint32_t wdh                          : 1;
+	uint32_t sf                           : 1;
+	uint32_t rd                           : 1;
+	uint32_t ue                           : 1;
+	uint32_t fno                          : 1;
+	uint32_t rhsc                         : 1;
+	uint32_t reserved_7_29                : 23;
+	uint32_t oc                           : 1;
+	uint32_t mie                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptenable_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcinterruptstatus
+ *
+ * HCINTERRUPTSTATUS = Host Controller InterruptStatus Register
+ *
+ * This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit
+ * in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register
+ * and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions
+ * to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit.
+ */
+union cvmx_uahcx_ohci0_hcinterruptstatus
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t oc                           : 1;  /**< OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest
+                                                         field in HcCommandStatus. This event, when unmasked, will always generate an
+                                                         System Management Interrupt (SMI) immediately. This bit is tied to 0b when the
+                                                         SMI pin is not implemented. */
+	uint32_t reserved_7_29                : 23;
+	uint32_t rhsc                         : 1;  /**< RootHubStatusChange. This bit is set when the content of HcRhStatus or the
+                                                         content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. */
+	uint32_t fno                          : 1;  /**< FrameNumberOverflow. This bit is set when the MSb of HcFmNumber (bit 15)
+                                                         changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been
+                                                         updated. */
+	uint32_t ue                           : 1;  /**< UnrecoverableError. This bit is set when HC detects a system error not related
+                                                         to USB. HC should not proceed with any processing nor signaling before the
+                                                         system error has been corrected. HCD clears this bit after HC has been reset. */
+	uint32_t rd                           : 1;  /**< ResumeDetected. This bit is set when HC detects that a device on the USB is
+                                                          asserting resume signaling. It is the transition from no resume signaling to
+                                                         resume signaling causing this bit to be set. This bit is not set when HCD
+                                                         sets the USBRESUME state. */
+	uint32_t sf                           : 1;  /**< StartofFrame. This bit is set by HC at each start of a frame and after the
+                                                         update of HccaFrameNumber. HC also generates a SOF token at the same time. */
+	uint32_t wdh                          : 1;  /**< WritebackDoneHead. This bit is set immediately after HC has written
+                                                         HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not
+                                                         occur until this bit has been cleared. HCD should only clear this bit after
+                                                         it has saved the content of HccaDoneHead. */
+	uint32_t so                           : 1;  /**< SchedulingOverrun. This bit is set when the USB schedule for the current
+                                                         Frame overruns and after the update of HccaFrameNumber. A scheduling overrun
+                                                         will also cause the SchedulingOverrunCount of HcCommandStatus to be
+                                                         incremented. */
+#else
+	uint32_t so                           : 1;
+	uint32_t wdh                          : 1;
+	uint32_t sf                           : 1;
+	uint32_t rd                           : 1;
+	uint32_t ue                           : 1;
+	uint32_t fno                          : 1;
+	uint32_t rhsc                         : 1;
+	uint32_t reserved_7_29                : 23;
+	uint32_t oc                           : 1;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptstatus_t;
+
+/**
+ * cvmx_uahc#_ohci0_hclsthreshold
+ *
+ * HCLSTHRESHOLD = Host Controller LS Threshold Register
+ *
+ * The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte
+ * LS packet before EOF. Neither the Host Controller nor the Host Controller Driver are allowed to change this value.
+ */
+union cvmx_uahcx_ohci0_hclsthreshold
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_12_31               : 20;
+	uint32_t lst                          : 12; /**< LSThreshold
+                                                         This field contains a value which is compared to the FrameRemaining field
+                                                         prior to initiating a Low Speed transaction. The transaction is started only
+                                                         if FrameRemaining >= this field. The value is calculated by HCD
+                                                         with the consideration of transmission and setup overhead. */
+#else
+	uint32_t lst                          : 12;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xx;
+	struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcperiodcurrented
+ *
+ * HCPERIODCURRENTED = Host Controller Period Current ED Register
+ *
+ * The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+ */
+union cvmx_uahcx_ohci0_hcperiodcurrented
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t pced                         : 28; /**< PeriodCurrentED. This is used by HC to point to the head of one of the
+                                                         Periodic lists which will be processed in the current Frame. The content of
+                                                         this register is updated by HC after a periodic ED has been processed. HCD
+                                                         may read the content in determining which ED is currently being processed
+                                                         at the time of reading. */
+	uint32_t reserved_0_3                 : 4;
+#else
+	uint32_t reserved_0_3                 : 4;
+	uint32_t pced                         : 28;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurrented_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcperiodicstart
+ *
+ * HCPERIODICSTART = Host Controller Periodic Start Register
+ *
+ * The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list.
+ */
+union cvmx_uahcx_ohci0_hcperiodicstart
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_14_31               : 18;
+	uint32_t ps                           : 14; /**< PeriodicStart After a hardware reset, this field is cleared. This is then set
+                                                         by HCD during the HC initialization. The value is calculated roughly as 10%
+                                                         off from HcFmInterval.. A typical value will be 3E67h. When HcFmRemaining
+                                                         reaches the value specified, processing of the periodic lists will have
+                                                         priority over Control/Bulk processing. HC will therefore start processing
+                                                         the Interrupt list after completing the current Control or Bulk transaction
+                                                         that is in progress. */
+#else
+	uint32_t ps                           : 14;
+	uint32_t reserved_14_31               : 18;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcrevision
+ *
+ * HCREVISION = Host Controller Revision Register
+ *
+ */
+union cvmx_uahcx_ohci0_hcrevision
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcrevision_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_8_31                : 24;
+	uint32_t rev                          : 8;  /**< Revision This read-only field contains the BCD representation of the version
+                                                         of the HCI specification that is implemented by this HC. For example, a value
+                                                         of 11h corresponds to version 1.1. All of the HC implementations that are
+                                                         compliant with this specification will have a value of 10h. */
+#else
+	uint32_t rev                          : 8;
+	uint32_t reserved_8_31                : 24;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn63xx;
+	struct cvmx_uahcx_ohci0_hcrevision_s  cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcrhdescriptora
+ *
+ * HCRHDESCRIPTORA = Host Controller Root Hub DescriptorA Register
+ *
+ * The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific.
+ * The descriptor length (11), descriptor type (TBD), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All
+ * other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers.
+ */
+union cvmx_uahcx_ohci0_hcrhdescriptora
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t potpgt                       : 8;  /**< PowerOnToPowerGoodTime. This byte specifies the duration HCD has to wait before
+                                                         accessing a powered-on port of the Root Hub. It is implementation-specific. The
+                                                         unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. */
+	uint32_t reserved_13_23               : 11;
+	uint32_t nocp                         : 1;  /**< NoOverCurrentProtection. This bit describes how the overcurrent status for the
+                                                         Root Hub ports are reported. When this bit is cleared, the
+                                                         OverCurrentProtectionMode field specifies global or per-port reporting.
+                                                         - 0: Over-current status is reported  collectively for all downstream ports
+                                                         - 1: No overcurrent protection supported */
+	uint32_t ocpm                         : 1;  /**< OverCurrentProtectionMode. This bit describes how the overcurrent status for
+                                                         the Root Hub ports are reported. At reset, this fields should reflect the same
+                                                         mode as PowerSwitchingMode. This field is valid only if the
+                                                         NoOverCurrentProtection field is cleared. 0: over-current status is reported
+                                                         collectively for all downstream ports 1: over-current status is reported on a
+                                                         per-port basis */
+	uint32_t dt                           : 1;  /**< DeviceType. This bit specifies that the Root Hub is not a compound device. The
+                                                         Root Hub is not permitted to be a compound device. This field should always
+                                                         read/write 0. */
+	uint32_t psm                          : 1;  /**< PowerSwitchingMode. This bit is used to specify how the power switching of
+                                                         the Root Hub ports is controlled. It is implementation-specific. This field
+                                                         is only valid if the NoPowerSwitching field is cleared. 0: all ports are
+                                                         powered at the same time. 1: each port is powered individually.  This mode
+                                                         allows port power to be controlled by either the global switch or per-port
+                                                         switching. If the PortPowerControlMask bit is set, the port responds only
+                                                         to port power commands (Set/ClearPortPower). If the port mask is cleared,
+                                                         then the port is controlled only by the global power switch
+                                                         (Set/ClearGlobalPower). */
+	uint32_t nps                          : 1;  /**< NoPowerSwitching These bits are used to specify whether power switching is
+                                                         supported or port are always powered. It is implementation-specific. When
+                                                         this bit is cleared, the PowerSwitchingMode specifies global or per-port
+                                                         switching.
+                                                          - 0: Ports are power switched
+                                                          - 1: Ports are always powered on when the HC is powered on */
+	uint32_t ndp                          : 8;  /**< NumberDownstreamPorts. These bits specify the number of downstream ports
+                                                         supported by the Root Hub. It is implementation-specific. The minimum number
+                                                         of ports is 1. The maximum number of ports supported by OpenHCI is 15. */
+#else
+	uint32_t ndp                          : 8;
+	uint32_t nps                          : 1;
+	uint32_t psm                          : 1;
+	uint32_t dt                           : 1;
+	uint32_t ocpm                         : 1;
+	uint32_t nocp                         : 1;
+	uint32_t reserved_13_23               : 11;
+	uint32_t potpgt                       : 8;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcrhdescriptorb
+ *
+ * HCRHDESCRIPTORB = Host Controller Root Hub DescriptorB Register
+ *
+ * The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during
+ * initialization to correspond with the system implementation. Reset values are implementation-specific.
+ */
+union cvmx_uahcx_ohci0_hcrhdescriptorb
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ppcm                         : 16; /**< PortPowerControlMask.
+                                                         Each bit indicates if a port is affected by a global power control command
+                                                         when PowerSwitchingMode is set. When set, the port's power state is only
+                                                         affected by per-port power control (Set/ClearPortPower). When cleared, the
+                                                         port is controlled by the global power switch (Set/ClearGlobalPower). If
+                                                         the device is configured to global switching mode (PowerSwitchingMode=0),
+                                                         this field is not valid.
+                                                            bit 0: Reserved
+                                                            bit 1: Ganged-power mask on Port \#1
+                                                            bit 2: Ganged-power mask on Port \#2
+                                                            - ...
+                                                            bit15: Ganged-power mask on Port \#15 */
+	uint32_t dr                           : 16; /**< DeviceRemovable.
+                                                         Each bit is dedicated to a port of the Root Hub. When cleared,the attached
+                                                         device is removable. When set, the attached device is not removable.
+                                                             bit 0: Reserved
+                                                             bit 1: Device attached to Port \#1
+                                                             bit 2: Device attached to Port \#2
+                                                             - ...
+                                                             bit15: Device attached to Port \#15 */
+#else
+	uint32_t dr                           : 16;
+	uint32_t ppcm                         : 16;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcrhportstatus#
+ *
+ * HCRHPORTSTATUSX = Host Controller Root Hub Port X Status Registers
+ *
+ * The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number
+ * of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects
+ * the status change bits. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is
+ * in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes.
+ * Reserved bits should always be written '0'.
+ */
+union cvmx_uahcx_ohci0_hcrhportstatusx
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t prsc                         : 1;  /**< PortResetStatusChange. This bit is set at the end of the 10-ms port reset
+                                                         signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect.
+                                                            0 = port reset is not complete
+                                                            1 = port reset is complete */
+	uint32_t ocic                         : 1;  /**< PortOverCurrentIndicatorChange. This bit is valid only if overcurrent
+                                                         conditions are reported on a per-port basis. This bit is set when Root Hub
+                                                         changes the PortOverCurrentIndicator bit. The HCD writes a '1' to clear this
+                                                         bit. Writing a  '0'  has no effect.
+                                                            0 = no change in PortOverCurrentIndicator
+                                                            1 = PortOverCurrentIndicator has changed */
+	uint32_t pssc                         : 1;  /**< PortSuspendStatusChange. This bit is set when the full resume sequence has
+                                                         been completed. This sequence includes the 20-s resume pulse, LS EOP, and
+                                                         3-ms resychronization delay.
+                                                         The HCD writes a '1' to clear this bit. Writing a '0' has no effect. This
+                                                         bit is also cleared when ResetStatusChange is set.
+                                                            0 = resume is not completed
+                                                            1 = resume completed */
+	uint32_t pesc                         : 1;  /**< PortEnableStatusChange. This bit is set when hardware events cause the
+                                                         PortEnableStatus bit to be cleared. Changes from HCD writes do not set this
+                                                         bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect.
+                                                           0 = no change in PortEnableStatus
+                                                           1 = change in PortEnableStatus */
+	uint32_t csc                          : 1;  /**< ConnectStatusChange. This bit is set whenever a connect or disconnect event
+                                                         occurs. The HCD writes a '1' to clear this bit. Writing a '0' has no
+                                                         effect. If CurrentConnectStatus is cleared when a SetPortReset,SetPortEnable,
+                                                         or SetPortSuspend write occurs, this bit is set to force the driver to
+                                                         re-evaluate the connection status since these writes should not occur if the
+                                                         port is disconnected.
+                                                           0 = no change in CurrentConnectStatus
+                                                           1 = change in CurrentConnectStatus
+                                                         Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a
+                                                          Root Hub reset to inform the system that the device is attached. Description */
+	uint32_t reserved_10_15               : 6;
+	uint32_t lsda                         : 1;  /**< (read) LowSpeedDeviceAttached. This bit indicates the speed of the device
+                                                              attached to this port. When set, a Low Speed device is attached to this
+                                                              port. When clear, a Full Speed device is attached to this port. This
+                                                              field is valid only when the CurrentConnectStatus is set.
+                                                                 0 = full speed device attached
+                                                                 1 = low speed device attached
+                                                         (write) ClearPortPower. The HCD clears the PortPowerStatus bit by writing a
+                                                              '1' to this bit. Writing a '0' has no effect. */
+	uint32_t pps                          : 1;  /**< (read) PortPowerStatus. This bit reflects the port's power status, regardless
+                                                             of the type of power switching implemented. This bit is cleared if an
+                                                             overcurrent condition is detected. HCD sets this bit by writing
+                                                             SetPortPower or SetGlobalPower. HCD clears this bit by writing
+                                                             ClearPortPower or ClearGlobalPower. Which power control switches are
+                                                             enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP].
+                                                             In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower
+                                                               controls this bit. In per-port power switching (PowerSwitchingMode=1),
+                                                               if the PortPowerControlMask[NDP] bit for the port is set, only
+                                                               Set/ClearPortPower commands are enabled. If the mask is not set, only
+                                                               Set/ClearGlobalPower commands are enabled. When port power is disabled,
+                                                               CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and
+                                                               PortResetStatus should be reset.
+                                                                  0 = port power is off
+                                                                  1 = port power is on
+                                                         (write) SetPortPower. The HCD writes a '1' to set the PortPowerStatus bit.
+                                                               Writing a '0' has no effect. Note: This bit is always reads '1'
+                                                               if power switching is not supported. */
+	uint32_t reserved_5_7                 : 3;
+	uint32_t prs                          : 1;  /**< (read) PortResetStatus. When this bit is set by a write to SetPortReset, port
+                                                               reset signaling is asserted. When reset is completed, this bit is
+                                                               cleared when PortResetStatusChange is set. This bit cannot be set if
+                                                               CurrentConnectStatus is cleared.
+                                                                  0 = port reset signal is not active
+                                                               1 = port reset signal is active
+                                                         (write) SetPortReset. The HCD sets the port reset signaling by writing a '1'
+                                                               to this bit. Writing a '0'has no effect. If CurrentConnectStatus is
+                                                               cleared, this write does not set PortResetStatus, but instead sets
+                                                               ConnectStatusChange. This informs the driver that it attempted to reset
+                                                               a disconnected port. Description */
+	uint32_t poci                         : 1;  /**< (read) PortOverCurrentIndicator. This bit is only valid when the Root Hub is
+                                                                configured in such a way that overcurrent conditions are reported on a
+                                                                per-port basis. If per-port overcurrent reporting is not supported, this
+                                                                bit is set to 0. If cleared, all power operations are normal for this
+                                                                port. If set, an overcurrent condition exists on this port. This bit
+                                                                always reflects the overcurrent input signal
+                                                                  0 = no overcurrent condition.
+                                                                  1 = overcurrent condition detected.
+                                                         (write) ClearSuspendStatus. The HCD writes a '1' to initiate a resume.
+                                                                 Writing  a '0' has no effect. A resume is initiated only if
+                                                                 PortSuspendStatus is set. */
+	uint32_t pss                          : 1;  /**< (read) PortSuspendStatus. This bit indicates the port is suspended or in the
+                                                              resume sequence. It is set by a SetSuspendState write and cleared when
+                                                              PortSuspendStatusChange is set at the end of the resume interval. This
+                                                              bit cannot be set if CurrentConnectStatus is cleared. This bit is also
+                                                              cleared when PortResetStatusChange is set at the end of the port reset
+                                                              or when the HC is placed in the USBRESUME state. If an upstream resume is
+                                                              in progress, it should propagate to the HC.
+                                                                 0 = port is not suspended
+                                                                 1 = port is suspended
+                                                         (write) SetPortSuspend. The HCD sets the PortSuspendStatus bit by writing a
+                                                              '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus
+                                                                is cleared, this write does not set PortSuspendStatus; instead it sets
+                                                                ConnectStatusChange.This informs the driver that it attempted to suspend
+                                                                a disconnected port. */
+	uint32_t pes                          : 1;  /**< (read) PortEnableStatus. This bit indicates whether the port is enabled or
+                                                              disabled. The Root Hub may clear this bit when an overcurrent condition,
+                                                              disconnect event, switched-off power, or operational bus error such
+                                                              as babble is detected. This change also causes PortEnabledStatusChange
+                                                              to be set. HCD sets this bit by writing SetPortEnable and clears it by
+                                                              writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus
+                                                              is cleared. This bit is also set, if not already, at the completion of a
+                                                              port reset when ResetStatusChange is set or port suspend when
+                                                              SuspendStatusChange is set.
+                                                                0 = port is disabled
+                                                                1 = port is enabled
+                                                         (write) SetPortEnable. The HCD sets PortEnableStatus by writing a '1'.
+                                                              Writing a '0' has no effect. If CurrentConnectStatus is cleared, this
+                                                              write does not set PortEnableStatus, but instead sets ConnectStatusChange.
+                                                              This informs the driver that it attempted to enable a disconnected port. */
+	uint32_t ccs                          : 1;  /**< (read) CurrentConnectStatus. This bit reflects the current state of the
+                                                               downstream port.
+                                                                 0 = no device connected
+                                                                 1 = device connected
+                                                         (write) ClearPortEnable.
+                                                                The HCD writes a '1' to this bit to clear the PortEnableStatus bit.
+                                                                Writing a '0' has no effect. The CurrentConnectStatus is not
+                                                                affected by any write.
+                                                          Note: This bit is always read '1b' when the attached device is
+                                                                nonremovable (DeviceRemoveable[NDP]). */
+#else
+	uint32_t ccs                          : 1;
+	uint32_t pes                          : 1;
+	uint32_t pss                          : 1;
+	uint32_t poci                         : 1;
+	uint32_t prs                          : 1;
+	uint32_t reserved_5_7                 : 3;
+	uint32_t pps                          : 1;
+	uint32_t lsda                         : 1;
+	uint32_t reserved_10_15               : 6;
+	uint32_t csc                          : 1;
+	uint32_t pesc                         : 1;
+	uint32_t pssc                         : 1;
+	uint32_t ocic                         : 1;
+	uint32_t prsc                         : 1;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xx;
+	struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_t;
+
+/**
+ * cvmx_uahc#_ohci0_hcrhstatus
+ *
+ * HCRHSTATUS = Host Controller Root Hub Status Register
+ *
+ * The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub
+ * Status Change field. Reserved bits should always be written '0'.
+ */
+union cvmx_uahcx_ohci0_hcrhstatus
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t crwe                         : 1;  /**< (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable.
+                                                         Writing a '0' has no effect. */
+	uint32_t reserved_18_30               : 13;
+	uint32_t ccic                         : 1;  /**< OverCurrentIndicatorChange. This bit is set by hardware when a change has
+                                                         occurred to the OCI field of this register. The HCD clears this bit by
+                                                         writing a '1'. Writing a '0' has no effect. */
+	uint32_t lpsc                         : 1;  /**< (read) LocalPowerStatusChange. The Root Hub does not support the local power
+                                                                status feature; thus, this bit is always read as '0'.
+                                                         (write) SetGlobalPower In global power mode (PowerSwitchingMode=0), This bit
+                                                                 is written to '1' to turn on power to all ports (clear PortPowerStatus).
+                                                                 In per-port power mode, it sets PortPowerStatus only on ports whose
+                                                                 PortPowerControlMask bit is not set. Writing a '0' has no effect. */
+	uint32_t drwe                         : 1;  /**< (read) DeviceRemoteWakeupEnable. This bit enables a ConnectStatusChange bit as
+                                                                a resume event, causing a USBSUSPEND to USBRESUME state transition and
+                                                                setting the ResumeDetected interrupt. 0 = ConnectStatusChange is not a
+                                                                remote wakeup event. 1 = ConnectStatusChange is a remote wakeup event.
+                                                         (write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable.
+                                                                 Writing a '0' has no effect. */
+	uint32_t reserved_2_14                : 13;
+	uint32_t oci                          : 1;  /**< OverCurrentIndicator. This bit reports overcurrent conditions when the global
+                                                         reporting is implemented. When set, an overcurrent condition exists. When
+                                                         cleared, all power operations are normal. If per-port overcurrent protection
+                                                         is implemented this bit is always '0' */
+	uint32_t lps                          : 1;  /**< (read)  LocalPowerStatus. The Root Hub does not support the local power status
+                                                                 feature; thus, this bit is always read as '0.
+                                                         (write) ClearGlobalPower. In global power mode (PowerSwitchingMode=0), This
+                                                                 bit is written to '1' to turn off power to all ports
+                                                                 (clear PortPowerStatus). In per-port power mode, it clears
+                                                                 PortPowerStatus only on ports whose PortPowerControlMask bit is not
+                                                                 set. Writing a '0' has no effect. Description */
+#else
+	uint32_t lps                          : 1;
+	uint32_t oci                          : 1;
+	uint32_t reserved_2_14                : 13;
+	uint32_t drwe                         : 1;
+	uint32_t lpsc                         : 1;
+	uint32_t ccic                         : 1;
+	uint32_t reserved_18_30               : 13;
+	uint32_t crwe                         : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn63xx;
+	struct cvmx_uahcx_ohci0_hcrhstatus_s  cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t;
+
+/**
+ * cvmx_uahc#_ohci0_insnreg06
+ *
+ * OHCI0_INSNREG06 = OHCI  AHB Error Status Register (Synopsys Speicific)
+ *
+ * This register contains AHB Error Status.
+ */
+union cvmx_uahcx_ohci0_insnreg06
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_insnreg06_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t vld                          : 1;  /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
+                                                         To clear this field the application must write a 0 to it. */
+	uint32_t reserved_0_30                : 31;
+#else
+	uint32_t reserved_0_30                : 31;
+	uint32_t vld                          : 1;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn63xx;
+	struct cvmx_uahcx_ohci0_insnreg06_s   cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t;
+
+/**
+ * cvmx_uahc#_ohci0_insnreg07
+ *
+ * OHCI0_INSNREG07 = OHCI  AHB Error Address Register (Synopsys Speicific)
+ *
+ * This register contains AHB Error Status.
+ */
+union cvmx_uahcx_ohci0_insnreg07
+{
+	uint32_t u32;
+	struct cvmx_uahcx_ohci0_insnreg07_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t err_addr                     : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
+#else
+	uint32_t err_addr                     : 32;
+#endif
+	} s;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn63xx;
+	struct cvmx_uahcx_ohci0_insnreg07_s   cn63xxp1;
+};
+typedef union cvmx_uahcx_ohci0_insnreg07 cvmx_uahcx_ohci0_insnreg07_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-uart.c b/sys/contrib/octeon-sdk/cvmx-uart.c
new file mode 100644
index 0000000..aead3e1
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-uart.c
@@ -0,0 +1,171 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-uart.h>
+#else
+#include "executive-config.h"
+#include "cvmx.h"
+#include "cvmx-uart.h"
+#include "cvmx-interrupt.h"
+#endif
+
+#ifndef __OCTEON_NEWLIB__
+void cvmx_uart_enable_intr(int uart, cvmx_uart_intr_handler_t handler)
+{
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+    cvmx_uart_ier_t ier;
+
+    cvmx_interrupt_register(CVMX_IRQ_UART0 + uart, handler, NULL);
+    /* Enable uart interrupts for debugger Control-C processing */
+    ier.u64 = cvmx_read_csr(CVMX_MIO_UARTX_IER(uart));
+    ier.s.erbfi = 1;
+    cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64);
+
+    cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0 + uart);
+#endif
+}
+#endif
+
+static int cvmx_uart_simulator_p(void)
+{
+#ifndef __OCTEON_NEWLIB__
+  return cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM;
+#else
+  extern int __octeon_simulator_p;
+  return __octeon_simulator_p;
+#endif
+}
+
+
+/**
+ * Function that does the real work of setting up the Octeon uart.
+ * Takes all parameters as arguments, so it does not require gd
+ * structure to be set up.
+ * 
+ * @param uart_index Index of uart to configure
+ * @param cpu_clock_hertz
+ *                   CPU clock frequency in Hz
+ * @param baudrate   Baudrate to configure
+ * 
+ * @return 0 on success
+ *         !0 on error
+ */
+int cvmx_uart_setup2(int uart_index, int cpu_clock_hertz, int baudrate)
+{
+    uint16_t divisor;
+    cvmx_uart_fcr_t fcrval;
+    cvmx_uart_mcr_t mcrval;
+    cvmx_uart_lcr_t lcrval;
+
+    fcrval.u64 = 0;
+    fcrval.s.en = 1;    /* enable the FIFO's */
+    fcrval.s.rxfr = 1;  /* reset the RX fifo */
+    fcrval.s.txfr = 1;  /* reset the TX fifo */
+
+    if (cvmx_uart_simulator_p())
+        divisor = 1;
+    else
+        divisor = ((unsigned long)(cpu_clock_hertz + 8 * baudrate) / (unsigned long)(16 * baudrate));
+
+    cvmx_write_csr(CVMX_MIO_UARTX_FCR(uart_index), fcrval.u64);
+
+    mcrval.u64 = 0;
+    if (uart_index == 1 && cvmx_uart_simulator_p())
+      mcrval.s.afce = 1;  /* enable auto flow control for simulator. Needed for  gdb regression callfuncs.exp. */
+    else
+      mcrval.s.afce = 0;  /* disable auto flow control so board can power on without serial port connected */
+
+    mcrval.s.rts = 1;   /* looks like this must be set for auto flow control to work */
+
+    cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart_index));
+
+    lcrval.u64 = 0;
+    lcrval.s.cls = CVMX_UART_BITS8;
+    lcrval.s.stop = 0;  /* stop bit included? */
+    lcrval.s.pen = 0;   /* no parity? */
+    lcrval.s.eps = 1;   /* even parity? */
+    lcrval.s.dlab = 1;  /* temporary to program the divisor */
+    cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64);
+
+    cvmx_write_csr(CVMX_MIO_UARTX_DLL(uart_index), divisor & 0xff);
+    cvmx_write_csr(CVMX_MIO_UARTX_DLH(uart_index), (divisor>>8) & 0xff);
+
+    lcrval.s.dlab = 0;  /* divisor is programmed now, set this back to normal */
+    cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64);
+
+    /* spec says need to wait after you program the divisor */
+    if (!cvmx_uart_simulator_p())
+    {
+        uint64_t read_cycle;
+        CVMX_MF_CYCLE (read_cycle);
+        read_cycle += (2 * divisor * 16) + 10000;
+
+        /* Spin */
+        while (1)
+        {
+            uint64_t new_cycle;
+            CVMX_MF_CYCLE (new_cycle);
+            if (new_cycle >= read_cycle)
+                break;
+        }
+    }
+
+    /* Don't enable flow control until after baud rate is configured. - we don't want
+    ** to allow characters in until after the baud rate is fully configured */
+    cvmx_write_csr(CVMX_MIO_UARTX_MCR(uart_index), mcrval.u64);
+    return 0;
+
+}
+
+/**
+ * Setup a uart for use
+ *
+ * @param uart_index Uart to setup (0 or 1)
+ * @return Zero on success
+ */
+int cvmx_uart_setup (int uart_index)
+{
+    return cvmx_uart_setup2(uart_index, cvmx_clock_get_rate (CVMX_CLOCK_SCLK), 115200);
+}
+
diff --git a/sys/contrib/octeon-sdk/cvmx-uart.h b/sys/contrib/octeon-sdk/cvmx-uart.h
index 9c5a0af..cb05d11 100644
--- a/sys/contrib/octeon-sdk/cvmx-uart.h
+++ b/sys/contrib/octeon-sdk/cvmx-uart.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * interface to the serial port UART hardware
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  *
  */
 
@@ -61,12 +63,105 @@ extern "C" {
 #define CVMX_UART_TX_FIFO_SIZE  64
 #define CVMX_UART_RX_FIFO_SIZE  64
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-uart-defs.h */
+
+typedef void (*cvmx_uart_intr_handler_t)(int, uint64_t[], void *);
+
+extern void cvmx_uart_enable_intr(int, cvmx_uart_intr_handler_t);
+extern int cvmx_uart_setup2(int, int, int);
+extern int cvmx_uart_setup(int);
 
 /* Defined in libc.  */
 unsigned __octeon_uart_trylock (void);
 void __octeon_uart_unlock (void);
 
+/**
+ * Get a single byte from serial port.
+ *
+ * @param uart_index Uart to read from (0 or 1)
+ * @return The byte read
+ */
+static inline uint8_t cvmx_uart_read_byte(int uart_index)
+{
+    cvmx_uart_lsr_t lsrval;
+
+    /* Spin until data is available */
+    do
+    {
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart_index));
+    } while (!lsrval.s.dr);
+
+    /* Read and return the data */
+    return cvmx_read_csr(CVMX_MIO_UARTX_RBR(uart_index));
+}
+
+/**
+ * Get a single byte from serial port with a timeout.
+ *     
+ * @param uart_index Uart to read from (0 or 1)
+ * @param timedout Record if a timeout has happened
+ * @param timeout the timeout count
+ * @return The byte read
+ */
+static inline uint8_t cvmx_uart_read_byte_with_timeout(int uart_index, int *timedout, volatile unsigned timeout)
+{
+    cvmx_uart_lsr_t lsrval;
+
+    /* Spin until data is available */
+    *timedout = 0;
+    do
+    {
+        if(timeout == 0)
+        {
+            *timedout = 1;
+            return -1;
+        }
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart_index));
+        timeout --;
+    } while (!lsrval.s.dr);
+
+    /* Read and return the data */
+    return cvmx_read_csr(CVMX_MIO_UARTX_RBR(uart_index));
+}
+
+
+/**
+ * Put a single byte to uart port.
+ *
+ * @param uart_index Uart to write to (0 or 1)
+ * @param ch         Byte to write
+ */
+static inline void cvmx_uart_write_byte(int uart_index, uint8_t ch)
+{
+    cvmx_uart_lsr_t lsrval;
+
+    /* Spin until there is room */
+    do
+    {
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart_index));
+    }
+    while (lsrval.s.thre == 0);
+
+    /* Write the byte */
+    cvmx_write_csr(CVMX_MIO_UARTX_THR(uart_index), ch);
+}
+
+/**
+ * Write a string to the uart
+ *
+ * @param uart_index Uart to use (0 or 1)
+ * @param str        String to write
+ */
+static inline void cvmx_uart_write_string(int uart_index, const char *str)
+{
+    /* Just loop writing one byte at a time */
+    while (*str)
+    {
+        cvmx_uart_write_byte(uart_index, *str);
+        str++;
+    }
+}
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h b/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
new file mode 100644
index 0000000..c864c82
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
@@ -0,0 +1,850 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-uctlx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon uctlx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F0000A0ull);
+}
+#else
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000000ull);
+}
+#else
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000080ull);
+}
+#else
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F0000A8ull);
+}
+#else
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000090ull);
+}
+#else
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000030ull);
+}
+#else
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000028ull);
+}
+#else
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000020ull);
+}
+#else
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000088ull);
+}
+#else
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000098ull);
+}
+#else
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000038ull);
+}
+#else
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000008ull);
+}
+#else
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
+}
+#else
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+#endif
+
+/**
+ * cvmx_uctl#_bist_status
+ *
+ * UCTL_BIST_STATUS = UCTL Bist Status
+ *
+ * Results from BIST runs of UCTL's memories.
+ */
+union cvmx_uctlx_bist_status
+{
+	uint64_t u64;
+	struct cvmx_uctlx_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t data_bis                     : 1;  /**< UAHC EHCI Data Ram Bist Status */
+	uint64_t desc_bis                     : 1;  /**< UAHC EHCI Descriptor Ram Bist Status */
+	uint64_t erbm_bis                     : 1;  /**< UCTL EHCI Read Buffer Memory Bist Status */
+	uint64_t orbm_bis                     : 1;  /**< UCTL OHCI Read Buffer Memory Bist Status */
+	uint64_t wrbm_bis                     : 1;  /**< UCTL Write Buffer Memory Bist Sta */
+	uint64_t ppaf_bis                     : 1;  /**< PP Access FIFO Memory Bist Status */
+#else
+	uint64_t ppaf_bis                     : 1;
+	uint64_t wrbm_bis                     : 1;
+	uint64_t orbm_bis                     : 1;
+	uint64_t erbm_bis                     : 1;
+	uint64_t desc_bis                     : 1;
+	uint64_t data_bis                     : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_uctlx_bist_status_s       cn63xx;
+	struct cvmx_uctlx_bist_status_s       cn63xxp1;
+};
+typedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t;
+
+/**
+ * cvmx_uctl#_clk_rst_ctl
+ *
+ * CLK_RST_CTL = Clock and Reset Control Reigster
+ * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists.
+ */
+union cvmx_uctlx_clk_rst_ctl
+{
+	uint64_t u64;
+	struct cvmx_uctlx_clk_rst_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_25_63               : 39;
+	uint64_t clear_bist                   : 1;  /**< Clear BIST on the HCLK memories */
+	uint64_t start_bist                   : 1;  /**< Starts BIST on the HCLK memories during 0-to-1
+                                                         transition. */
+	uint64_t ehci_sm                      : 1;  /**< Only set it during simulation time. When set to 1,
+                                                         this bit sets the PHY in a non-driving mode so the
+                                                         EHCI can detect device connection.
+                                                         Note: it must not be set to 1, during normal
+                                                         operation. */
+	uint64_t ohci_clkcktrst               : 1;  /**< Clear clock reset. Active low.  OHCI initial reset
+                                                         signal for the DPLL block. This is only needed by
+                                                         simulation. The duration of the reset  in simulation
+                                                         must be the same as HRST.
+                                                         Note: it must be set to 1 during normal operation. */
+	uint64_t ohci_sm                      : 1;  /**< OHCI Simulation Mode. It selects the counter value
+                                                          for simulation or real time for 1 ms.
+                                                         - 0: counter full 1ms; 1: simulation time. */
+	uint64_t ohci_susp_lgcy               : 1;  /**< OHCI Clock Control Signal. Note: This bit must be
+                                                         set to 0 if the OHCI 48/12Mhz clocks must be
+                                                         suspended when the EHCI and OHCI controllers are
+                                                         not active. */
+	uint64_t app_start_clk                : 1;  /**< OHCI Clock Control Signal. When the OHCI clocks are
+                                                         suspended, the system has to assert this signal to
+                                                         start the clocks (12 and 48 Mhz). */
+	uint64_t o_clkdiv_rst                 : 1;  /**< OHCI 12Mhz  clock divider reset. Active low. When
+                                                         set to 0, divider is held in reset.
+                                                         The reset to the divider is also asserted when core
+                                                         reset is asserted. */
+	uint64_t h_clkdiv_byp                 : 1;  /**< Used to enable the bypass input to the USB_CLK_DIV */
+	uint64_t h_clkdiv_rst                 : 1;  /**< Host clock divider reset. Active low. When set to 0,
+                                                         divider is held in reset. This must be set to 0
+                                                         before change H_DIV0 and H_DIV1.
+                                                         The reset to the divider is also asserted when core
+                                                         reset is asserted. */
+	uint64_t h_clkdiv_en                  : 1;  /**< Hclk enable. When set to 1, the hclk is gernerated. */
+	uint64_t o_clkdiv_en                  : 1;  /**< OHCI 48Mhz/12MHz clock enable. When set to 1, the
+                                                         clocks are gernerated. */
+	uint64_t h_div                        : 4;  /**< The hclk frequency is sclk frequency divided by
+                                                         H_DIV. The maximum frequency of hclk is 200Mhz.
+                                                         The minimum frequency of hclk is no less than the
+                                                         UTMI clock frequency which is 60Mhz. After writing a
+                                                         value to this field, the software should read the
+                                                         field for the value written. The [H_ENABLE] field of
+                                                         this register should not be set until after this
+                                                         field is set and  then read.
+                                                         Only the following values are valid:
+                                                            1, 2, 3, 4, 6, 8, 12.
+                                                         All other values are reserved and will be coded as
+                                                         following:
+                                                            0        -> 1
+                                                            5        -> 4
+                                                            7        -> 6
+                                                            9,10,11  -> 8
+                                                            13,14,15 -> 12 */
+	uint64_t p_refclk_sel                 : 2;  /**< PHY PLL Reference Clock Select.
+                                                         - 00: uses 12Mhz crystal at USB_XO and USB_XI;
+                                                         - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO.
+                                                             USB_XI should be tied to GND.
+                                                         1x: Reserved. */
+	uint64_t p_refclk_div                 : 2;  /**< PHY Reference Clock Frequency Select.
+                                                         - 00: 12MHz, 01: 24Mhz, 10: 48Mhz, 11: Reserved.
+                                                         Note: This value must be set during POR is active.
+                                                         If a crystal is used as a reference clock,this field
+                                                         must be set to 12 MHz. Values 01 and 10 are reserved
+                                                         when a crystal is used. */
+	uint64_t reserved_4_4                 : 1;
+	uint64_t p_com_on                     : 1;  /**< PHY Common Block Power-Down Control.
+                                                         - 1: The XO, Bias, and PLL blocks are powered down in
+                                                             Suspend mode.
+                                                         - 0: The XO, Bias, and PLL blocks remain powered in
+                                                             suspend mode.
+                                                          Note: This bit must be set to 0 during POR is active
+                                                          in current design. */
+	uint64_t p_por                        : 1;  /**< Power on reset for PHY. Resets all the PHY's
+                                                         registers and state machines. */
+	uint64_t p_prst                       : 1;  /**< PHY Clock Reset. The is the value for phy_rst_n,
+                                                         utmi_rst_n[1] and utmi_rst_n[0]. It is synchronized
+                                                         to each clock domain to generate the corresponding
+                                                         reset signal. This should not be set to 1 until the
+                                                         time it takes for six clock cycles (HCLK and
+                                                         PHY CLK, which ever is slower) has passed. */
+	uint64_t hrst                         : 1;  /**< Host Clock Reset. This is the value for hreset_n.
+                                                         This should not be set to 1 until 12ms after PHY CLK
+                                                         is stable. */
+#else
+	uint64_t hrst                         : 1;
+	uint64_t p_prst                       : 1;
+	uint64_t p_por                        : 1;
+	uint64_t p_com_on                     : 1;
+	uint64_t reserved_4_4                 : 1;
+	uint64_t p_refclk_div                 : 2;
+	uint64_t p_refclk_sel                 : 2;
+	uint64_t h_div                        : 4;
+	uint64_t o_clkdiv_en                  : 1;
+	uint64_t h_clkdiv_en                  : 1;
+	uint64_t h_clkdiv_rst                 : 1;
+	uint64_t h_clkdiv_byp                 : 1;
+	uint64_t o_clkdiv_rst                 : 1;
+	uint64_t app_start_clk                : 1;
+	uint64_t ohci_susp_lgcy               : 1;
+	uint64_t ohci_sm                      : 1;
+	uint64_t ohci_clkcktrst               : 1;
+	uint64_t ehci_sm                      : 1;
+	uint64_t start_bist                   : 1;
+	uint64_t clear_bist                   : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
+	struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
+};
+typedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t;
+
+/**
+ * cvmx_uctl#_ehci_ctl
+ *
+ * UCTL_EHCI_CTL = UCTL EHCI Control Register
+ * This register controls the general behavior of UCTL EHCI datapath.
+ */
+union cvmx_uctlx_ehci_ctl
+{
+	uint64_t u64;
+	struct cvmx_uctlx_ehci_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t desc_rbm                     : 1;  /**< Descriptor Read Burst Mode on AHB bus
+                                                         - 1: A read burst can be interruprted after 16 AHB
+                                                             clock cycle
+                                                         - 0: A read burst will not be interrupted until it
+                                                             finishes or no more data available */
+	uint64_t reg_nb                       : 1;  /**< 1: EHCI register access will not be blocked by EHCI
+                                                          buffer/descriptor access on AHB
+                                                         - 0: Buffer/descriptor and register access will be
+                                                             mutually exclusive */
+	uint64_t l2c_dc                       : 1;  /**< When set to 1, set the commit bit in the descriptor
+                                                         store commands to L2C. */
+	uint64_t l2c_bc                       : 1;  /**< When set to 1, set the commit bit in the buffer
+                                                         store commands to L2C. */
+	uint64_t l2c_0pag                     : 1;  /**< When set to 1, sets the zero-page bit in store
+                                                         command to  L2C. */
+	uint64_t l2c_stt                      : 1;  /**< When set to 1, use STT when store to L2C. */
+	uint64_t l2c_buff_emod                : 2;  /**< Endian format for buffer from/to the L2C.
+                                                         IN:       A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t l2c_desc_emod                : 2;  /**< Endian format for descriptor from/to the L2C.
+                                                         IN:        A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t inv_reg_a2                   : 1;  /**< UAHC register address  bit<2> invert. When set to 1,
+                                                         for a 32-bit NCB I/O register access, the address
+                                                         offset will be flipped between 0x4 and 0x0. */
+	uint64_t ehci_64b_addr_en             : 1;  /**< EHCI AHB Master 64-bit Addressing Enable.
+                                                         - 1: enable ehci 64-bit addressing mode;
+                                                         - 0: disable ehci 64-bit addressing mode.
+                                                          When ehci 64-bit addressing mode is disabled,
+                                                          UCTL_EHCI_CTL[L2C_ADDR_MSB] is used as the address
+                                                          bit[39:32]. */
+	uint64_t l2c_addr_msb                 : 8;  /**< This is the bit [39:32] of an address sent to L2C
+                                                         for ehci whenUCTL_EHCI_CFG[EHCI_64B_ADDR_EN=0]). */
+#else
+	uint64_t l2c_addr_msb                 : 8;
+	uint64_t ehci_64b_addr_en             : 1;
+	uint64_t inv_reg_a2                   : 1;
+	uint64_t l2c_desc_emod                : 2;
+	uint64_t l2c_buff_emod                : 2;
+	uint64_t l2c_stt                      : 1;
+	uint64_t l2c_0pag                     : 1;
+	uint64_t l2c_bc                       : 1;
+	uint64_t l2c_dc                       : 1;
+	uint64_t reg_nb                       : 1;
+	uint64_t desc_rbm                     : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_uctlx_ehci_ctl_s          cn63xx;
+	struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
+};
+typedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t;
+
+/**
+ * cvmx_uctl#_ehci_fla
+ *
+ * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register
+ * This register configures the EHCI Frame Length Adjustment.
+ */
+union cvmx_uctlx_ehci_fla
+{
+	uint64_t u64;
+	struct cvmx_uctlx_ehci_fla_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t fla                          : 6;  /**< EHCI Frame Length Adjustment. This feature
+                                                         adjusts any offset from the clock source that drives
+                                                         the uSOF counter.  The default value is 32(0x20),
+                                                         which gives an SOF cycle time of 60,0000 (each
+                                                         microframe has 60,000 bit times).
+                                                         Note: keep this value to 0x20 (decimal 32) for no
+                                                         offset. */
+#else
+	uint64_t fla                          : 6;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_uctlx_ehci_fla_s          cn63xx;
+	struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
+};
+typedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t;
+
+/**
+ * cvmx_uctl#_erto_ctl
+ *
+ * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register
+ * This register controls timeout for EHCI Readbuffer.
+ */
+union cvmx_uctlx_erto_ctl
+{
+	uint64_t u64;
+	struct cvmx_uctlx_erto_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t to_val                       : 27; /**< Read buffer timeout value
+                                                         (value 0 means timeout disabled) */
+	uint64_t reserved_0_4                 : 5;
+#else
+	uint64_t reserved_0_4                 : 5;
+	uint64_t to_val                       : 27;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_uctlx_erto_ctl_s          cn63xx;
+	struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
+};
+typedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t;
+
+/**
+ * cvmx_uctl#_if_ena
+ *
+ * UCTL_IF_ENA = UCTL Interface Enable Register
+ *
+ * Register to enable the uctl interface clock.
+ */
+union cvmx_uctlx_if_ena
+{
+	uint64_t u64;
+	struct cvmx_uctlx_if_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Turns on the USB UCTL interface clock */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_uctlx_if_ena_s            cn63xx;
+	struct cvmx_uctlx_if_ena_s            cn63xxp1;
+};
+typedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t;
+
+/**
+ * cvmx_uctl#_int_ena
+ *
+ * UCTL_INT_ENA = UCTL Interrupt Enable Register
+ *
+ * Register to enable individual interrupt source in corresponding to UCTL_INT_REG
+ */
+union cvmx_uctlx_int_ena
+{
+	uint64_t u64;
+	struct cvmx_uctlx_int_ena_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ec_ovf_e                     : 1;  /**< Ehci Commit OVerFlow Error */
+	uint64_t oc_ovf_e                     : 1;  /**< Ohci Commit OVerFlow Error */
+	uint64_t wb_pop_e                     : 1;  /**< Write Buffer FIFO Poped When Empty */
+	uint64_t wb_psh_f                     : 1;  /**< Write Buffer FIFO Pushed When Full */
+	uint64_t cf_psh_f                     : 1;  /**< Command FIFO Pushed When Full */
+	uint64_t or_psh_f                     : 1;  /**< OHCI Read Buffer FIFO Pushed When Full */
+	uint64_t er_psh_f                     : 1;  /**< EHCI Read Buffer FIFO Pushed When Full */
+	uint64_t pp_psh_f                     : 1;  /**< PP Access FIFO  Pushed When Full */
+#else
+	uint64_t pp_psh_f                     : 1;
+	uint64_t er_psh_f                     : 1;
+	uint64_t or_psh_f                     : 1;
+	uint64_t cf_psh_f                     : 1;
+	uint64_t wb_psh_f                     : 1;
+	uint64_t wb_pop_e                     : 1;
+	uint64_t oc_ovf_e                     : 1;
+	uint64_t ec_ovf_e                     : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_uctlx_int_ena_s           cn63xx;
+	struct cvmx_uctlx_int_ena_s           cn63xxp1;
+};
+typedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t;
+
+/**
+ * cvmx_uctl#_int_reg
+ *
+ * UCTL_INT_REG = UCTL Interrupt Register
+ *
+ * Summary of different bits of RSL interrupt status.
+ */
+union cvmx_uctlx_int_reg
+{
+	uint64_t u64;
+	struct cvmx_uctlx_int_reg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_8_63                : 56;
+	uint64_t ec_ovf_e                     : 1;  /**< Ehci Commit OVerFlow Error
+                                                         When the error happenes, the whole NCB system needs
+                                                         to be reset. */
+	uint64_t oc_ovf_e                     : 1;  /**< Ohci Commit OVerFlow Error
+                                                         When the error happenes, the whole NCB system needs
+                                                         to be reset. */
+	uint64_t wb_pop_e                     : 1;  /**< Write Buffer FIFO Poped When Empty */
+	uint64_t wb_psh_f                     : 1;  /**< Write Buffer FIFO Pushed When Full */
+	uint64_t cf_psh_f                     : 1;  /**< Command FIFO Pushed When Full */
+	uint64_t or_psh_f                     : 1;  /**< OHCI Read Buffer FIFO Pushed When Full */
+	uint64_t er_psh_f                     : 1;  /**< EHCI Read Buffer FIFO Pushed When Full */
+	uint64_t pp_psh_f                     : 1;  /**< PP Access FIFO  Pushed When Full */
+#else
+	uint64_t pp_psh_f                     : 1;
+	uint64_t er_psh_f                     : 1;
+	uint64_t or_psh_f                     : 1;
+	uint64_t cf_psh_f                     : 1;
+	uint64_t wb_psh_f                     : 1;
+	uint64_t wb_pop_e                     : 1;
+	uint64_t oc_ovf_e                     : 1;
+	uint64_t ec_ovf_e                     : 1;
+	uint64_t reserved_8_63                : 56;
+#endif
+	} s;
+	struct cvmx_uctlx_int_reg_s           cn63xx;
+	struct cvmx_uctlx_int_reg_s           cn63xxp1;
+};
+typedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t;
+
+/**
+ * cvmx_uctl#_ohci_ctl
+ *
+ * RSL registers starting from 0x10 can be accessed only after hclk is active and hreset is deasserted.
+ *
+ * UCTL_OHCI_CTL = UCTL OHCI Control Register
+ * This register controls the general behavior of UCTL OHCI datapath.
+ */
+union cvmx_uctlx_ohci_ctl
+{
+	uint64_t u64;
+	struct cvmx_uctlx_ohci_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_19_63               : 45;
+	uint64_t reg_nb                       : 1;  /**< 1: OHCI register access will not be blocked by EHCI
+                                                          buffer/descriptor access on AHB
+                                                         - 0: Buffer/descriptor and register access will be
+                                                             mutually exclusive */
+	uint64_t l2c_dc                       : 1;  /**< When set to 1, set the commit bit in the descriptor
+                                                         store commands to L2C. */
+	uint64_t l2c_bc                       : 1;  /**< When set to 1, set the commit bit in the buffer
+                                                         store commands to L2C. */
+	uint64_t l2c_0pag                     : 1;  /**< When set to 1, sets the zero-page bit in store
+                                                         command to  L2C. */
+	uint64_t l2c_stt                      : 1;  /**< When set to 1, use STT when store to L2C. */
+	uint64_t l2c_buff_emod                : 2;  /**< Endian format for buffer from/to the L2C.
+                                                         IN:       A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t l2c_desc_emod                : 2;  /**< Endian format for descriptor from/to the L2C.
+                                                         IN:        A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t inv_reg_a2                   : 1;  /**< UAHC register address  bit<2> invert. When set to 1,
+                                                         for a 32-bit NCB I/O register access, the address
+                                                         offset will be flipped between 0x4 and 0x0. */
+	uint64_t reserved_8_8                 : 1;
+	uint64_t l2c_addr_msb                 : 8;  /**< This is the bit [39:32] of an address sent to L2C
+                                                         for ohci. */
+#else
+	uint64_t l2c_addr_msb                 : 8;
+	uint64_t reserved_8_8                 : 1;
+	uint64_t inv_reg_a2                   : 1;
+	uint64_t l2c_desc_emod                : 2;
+	uint64_t l2c_buff_emod                : 2;
+	uint64_t l2c_stt                      : 1;
+	uint64_t l2c_0pag                     : 1;
+	uint64_t l2c_bc                       : 1;
+	uint64_t l2c_dc                       : 1;
+	uint64_t reg_nb                       : 1;
+	uint64_t reserved_19_63               : 45;
+#endif
+	} s;
+	struct cvmx_uctlx_ohci_ctl_s          cn63xx;
+	struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
+};
+typedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t;
+
+/**
+ * cvmx_uctl#_orto_ctl
+ *
+ * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register
+ * This register controls timeout for OHCI Readbuffer.
+ */
+union cvmx_uctlx_orto_ctl
+{
+	uint64_t u64;
+	struct cvmx_uctlx_orto_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_32_63               : 32;
+	uint64_t to_val                       : 24; /**< Read buffer timeout value
+                                                         (value 0 means timeout disabled) */
+	uint64_t reserved_0_7                 : 8;
+#else
+	uint64_t reserved_0_7                 : 8;
+	uint64_t to_val                       : 24;
+	uint64_t reserved_32_63               : 32;
+#endif
+	} s;
+	struct cvmx_uctlx_orto_ctl_s          cn63xx;
+	struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
+};
+typedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t;
+
+/**
+ * cvmx_uctl#_ppaf_wm
+ *
+ * UCTL_PPAF_WM = UCTL PP Access FIFO WaterMark Register
+ *
+ * Register to set PP access FIFO full watermark.
+ */
+union cvmx_uctlx_ppaf_wm
+{
+	uint64_t u64;
+	struct cvmx_uctlx_ppaf_wm_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_5_63                : 59;
+	uint64_t wm                           : 5;  /**< Number of entries when PP Access FIFO will assert
+                                                         full (back pressure) */
+#else
+	uint64_t wm                           : 5;
+	uint64_t reserved_5_63                : 59;
+#endif
+	} s;
+	struct cvmx_uctlx_ppaf_wm_s           cn63xx;
+	struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
+};
+typedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t;
+
+/**
+ * cvmx_uctl#_uphy_ctl_status
+ *
+ * UPHY_CTL_STATUS = USB PHY Control and Status Reigster
+ * This register controls the USB PHY test and Bist.
+ */
+union cvmx_uctlx_uphy_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_uctlx_uphy_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_10_63               : 54;
+	uint64_t bist_done                    : 1;  /**< PHY BIST DONE.  Asserted at the end of the PHY BIST
+                                                         sequence. */
+	uint64_t bist_err                     : 1;  /**< PHY BIST Error.  Valid when BIST_ENB is high.
+                                                         Indicates an internal error was detected during the
+                                                         BIST sequence. */
+	uint64_t hsbist                       : 1;  /**< High-Speed BIST Enable */
+	uint64_t fsbist                       : 1;  /**< Full-Speed BIST Enable */
+	uint64_t lsbist                       : 1;  /**< Low-Speed BIST Enable */
+	uint64_t siddq                        : 1;  /**< Drives the PHY SIDDQ input. Normally should be set
+                                                         to zero. Customers not using USB PHY interface
+                                                         should do the following:
+                                                           Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V
+                                                           supply and Set SIDDQ to 1. */
+	uint64_t vtest_en                     : 1;  /**< Analog Test Pin Enable.
+                                                         1 = The PHY's ANALOG _TEST pin is enabled for the
+                                                             input and output of applicable analog test
+                                                             signals.
+                                                         0 = The ANALOG_TEST pin is disabled. */
+	uint64_t uphy_bist                    : 1;  /**< When set to 1,  it makes sure that during PHY BIST,
+                                                         utmi_txvld == 0. */
+	uint64_t bist_en                      : 1;  /**< PHY BIST ENABLE */
+	uint64_t ate_reset                    : 1;  /**< Reset Input from ATE. This is a test signal. When
+                                                         the USB core is powered up (not in suspend mode), an
+                                                         automatic tester can use this to disable PHYCLOCK
+                                                         and FREECLK, then re-enable them with an aligned
+                                                         phase.
+                                                         - 1:  PHYCLOCKs and FREECLK outputs are disable.
+                                                         - 0: PHYCLOCKs and FREECLK are available within a
+                                                             specific period after ATERESET is de-asserted. */
+#else
+	uint64_t ate_reset                    : 1;
+	uint64_t bist_en                      : 1;
+	uint64_t uphy_bist                    : 1;
+	uint64_t vtest_en                     : 1;
+	uint64_t siddq                        : 1;
+	uint64_t lsbist                       : 1;
+	uint64_t fsbist                       : 1;
+	uint64_t hsbist                       : 1;
+	uint64_t bist_err                     : 1;
+	uint64_t bist_done                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
+	struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
+};
+typedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t;
+
+/**
+ * cvmx_uctl#_uphy_port#_ctl_status
+ *
+ * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters
+ * This register controls the each port of the USB PHY.
+ */
+union cvmx_uctlx_uphy_portx_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_43_63               : 21;
+	uint64_t tdata_out                    : 4;  /**< PHY test data out. Presents either interlly
+                                                         generated signals or test register contenets, based
+                                                         upon the value of TDATA_SEL */
+	uint64_t txbiststuffenh               : 1;  /**< High-Byte Transmit Bit-Stuffing Enable. It must be
+                                                         set to 1'b1 in normal operation. */
+	uint64_t txbiststuffen                : 1;  /**< Low-Byte Transmit Bit-Stuffing Enable. It must be
+                                                         set to 1'b1 in normal operation. */
+	uint64_t dmpulldown                   : 1;  /**< D- Pull-Down Resistor Enable. It must be set to 1'b1
+                                                         in normal operation. */
+	uint64_t dppulldown                   : 1;  /**< D+ Pull-Down Resistor Enable. It must be set to 1'b1
+                                                         in normal operation. */
+	uint64_t vbusvldext                   : 1;  /**< In host mode, this input is not used and can be tied
+                                                         to 1'b0. */
+	uint64_t portreset                    : 1;  /**< Per-port reset */
+	uint64_t txhsvxtune                   : 2;  /**< Transmitter High-Speed Crossover Adjustment */
+	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
+	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
+	uint64_t txpreemphasistune            : 1;  /**< HS transmitter pre-emphasis enable. */
+	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedance Adjustment */
+	uint64_t sqrxtune                     : 3;  /**< Squelch Threshold Adjustment */
+	uint64_t compdistune                  : 3;  /**< Disconnect Threshold Adjustment */
+	uint64_t loop_en                      : 1;  /**< Port Loop back Test Enable
+                                                         - 1: During data transmission, the receive logic is
+                                                             enabled
+                                                         - 0: During data transmission, the receive logic is
+                                                             disabled */
+	uint64_t tclk                         : 1;  /**< PHY port test clock, used to load TDATA_IN to the
+                                                         UPHY. */
+	uint64_t tdata_sel                    : 1;  /**< Test Data out select
+                                                         - 1: Mode-defined test register contents are output
+                                                         - 0: internally generated signals are output */
+	uint64_t taddr_in                     : 4;  /**< Mode address for test interface. Specifies the
+                                                         register address for writing to or reading from the
+                                                         PHY test interface register. */
+	uint64_t tdata_in                     : 8;  /**< Internal testing Register input data and select.
+                                                         This is a test bus. Data presents on [3:0] and the
+                                                         corresponding select (enable) presents on bits[7:4]. */
+#else
+	uint64_t tdata_in                     : 8;
+	uint64_t taddr_in                     : 4;
+	uint64_t tdata_sel                    : 1;
+	uint64_t tclk                         : 1;
+	uint64_t loop_en                      : 1;
+	uint64_t compdistune                  : 3;
+	uint64_t sqrxtune                     : 3;
+	uint64_t txfslstune                   : 4;
+	uint64_t txpreemphasistune            : 1;
+	uint64_t txrisetune                   : 1;
+	uint64_t txvreftune                   : 4;
+	uint64_t txhsvxtune                   : 2;
+	uint64_t portreset                    : 1;
+	uint64_t vbusvldext                   : 1;
+	uint64_t dppulldown                   : 1;
+	uint64_t dmpulldown                   : 1;
+	uint64_t txbiststuffen                : 1;
+	uint64_t txbiststuffenh               : 1;
+	uint64_t tdata_out                    : 4;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
+	struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+};
+typedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-usb.c b/sys/contrib/octeon-sdk/cvmx-usb.c
index 67cedc8..d660f0e 100644
--- a/sys/contrib/octeon-sdk/cvmx-usb.c
+++ b/sys/contrib/octeon-sdk/cvmx-usb.c
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
- *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  *
@@ -47,13 +49,33 @@
  *
  * <hr>$Revision: 32636 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/cvmx-usbnx-defs.h>
+#include <asm/octeon/cvmx-usbcx-defs.h>
+#include <asm/octeon/cvmx-usb.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#include <asm/octeon/cvmx-swap.h>
+#if 0
+   /* Do not use cvmx-error.h for now. When the cvmx-error.h is properly
+    * ported, remove the above #if 0, and all #ifdef __CVMX_ERROR_H__ within
+    * this file */
+   #include <asm/octeon/cvmx-error.h>
+#endif
+#else
 #include "cvmx.h"
+#include "cvmx-clock.h"
 #include "cvmx-sysinfo.h"
 #include "cvmx-usb.h"
 #include "cvmx-helper.h"
 #include "cvmx-helper-board.h"
 #include "cvmx-csr-db.h"
 #include "cvmx-swap.h"
+#include "cvmx-error.h"
+#endif
 
 #define MAX_RETRIES         3   /* Maximum number of times to retry failed transactions */
 #define MAX_PIPES           32  /* Maximum number of pipes that can be open at once */
@@ -62,6 +84,8 @@
 #define MAX_USB_ADDRESS     127 /* The highest valid USB device address */
 #define MAX_USB_ENDPOINT    15  /* The highest valid USB endpoint number */
 #define MAX_USB_HUB_PORT    15  /* The highest valid port number on a hub */
+#define MAX_TRANSFER_BYTES  ((1<<19)-1) /* The low level hardware can transfer a maximum of this number of bytes in each transfer. The field is 19 bits wide */
+#define MAX_TRANSFER_PACKETS ((1<<10)-1) /* The low level hardware can transfer a maximum of this number of packets in each transfer. The field is 10 bits wide */
 #define ALLOW_CSR_DECODES   0   /* CSR decoding when CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS is set
                                     enlarges the code a lot. This define overrides the ability to do CSR
                                     decoding since it isn't necessary 99% of the time. Change this to a
@@ -134,8 +158,8 @@ typedef struct cvmx_usb_pipe
     struct cvmx_usb_pipe *next;         /**< Pipe after this one in the list */
     cvmx_usb_transaction_t *head;       /**< The first pending transaction */
     cvmx_usb_transaction_t *tail;       /**< The last pending transaction */
-    uint64_t interval;                  /**< For periodic pipes, the interval between packets in cycles */
-    uint64_t next_tx_cycle;             /**< The next cycle this pipe is allowed to transmit on */
+    uint64_t interval;                  /**< For periodic pipes, the interval between packets in frames */
+    uint64_t next_tx_frame;             /**< The next frame this pipe is allowed to transmit on */
     cvmx_usb_pipe_flags_t flags;        /**< State flags for this pipe */
     cvmx_usb_speed_t device_speed;      /**< Speed of device connected to this pipe */
     cvmx_usb_transfer_t transfer_type;  /**< Type of transaction supported by this pipe */
@@ -157,6 +181,18 @@ typedef struct
     cvmx_usb_pipe_t *tail;              /**< Tail if the list, or NULL if empty */
 } cvmx_usb_pipe_list_t;
 
+typedef struct
+{
+    struct
+    {
+        int channel;
+        int size;
+        uint64_t address;
+    } entry[MAX_CHANNELS+1];
+    int head;
+    int tail;
+} cvmx_usb_tx_fifo_t;
+
 /**
  * The state of the USB block is stored in this structure
  */
@@ -165,7 +201,6 @@ typedef struct
     int init_flags;                     /**< Flags passed to initialize */
     int index;                          /**< Which USB block this is for */
     int idle_hardware_channels;         /**< Bit set for every idle hardware channel */
-    int active_transactions;            /**< Number of active transactions across all pipes */
     cvmx_usbcx_hprt_t usbcx_hprt;       /**< Stored port status so we don't need to read a CSR to determine splits */
     cvmx_usb_pipe_t *pipe_for_channel[MAX_CHANNELS];    /**< Map channels to pipes */
     cvmx_usb_transaction_t *free_transaction_head;      /**< List of free transactions head */
@@ -179,6 +214,10 @@ typedef struct
     cvmx_usb_pipe_list_t free_pipes;    /**< List of all pipes that are currently closed */
     cvmx_usb_pipe_list_t idle_pipes;    /**< List of open pipes that have no transactions */
     cvmx_usb_pipe_list_t active_pipes[4]; /**< Active pipes indexed by transfer type */
+    uint64_t frame_number;              /**< Increments every SOF interrupt for time keeping */
+    cvmx_usb_transaction_t *active_split; /**< Points to the current active split, or NULL */
+    cvmx_usb_tx_fifo_t periodic;
+    cvmx_usb_tx_fifo_t nonperiodic;
 } cvmx_usb_internal_state_t;
 
 /* This macro logs out whenever a function is called if debugging is on */
@@ -213,7 +252,7 @@ typedef struct
     ({int result;                                                       \
     do {                                                                \
         uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec *     \
-                           cvmx_sysinfo_get()->cpu_clock_hz / 1000000;  \
+                           cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;  \
         type c;                                                         \
         while (1)                                                       \
         {                                                               \
@@ -240,6 +279,8 @@ typedef struct
         __cvmx_usb_write_csr32(usb, address, c.u32);\
     } while (0)
 
+/* Returns the IO address to push/pop stuff data from the FIFOs */
+#define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
 
 /**
  * @INTERNAL
@@ -288,6 +329,7 @@ static inline void __cvmx_usb_write_csr32(cvmx_usb_internal_state_t *usb,
     }
 #endif
     cvmx_write64_uint32(address ^ 4, value);
+    cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
 }
 
 
@@ -341,7 +383,7 @@ static inline void __cvmx_usb_write_csr64(cvmx_usb_internal_state_t *usb,
 
 /**
  * @INTERNAL
- * Uitility function to convert complete codes into strings
+ * Utility function to convert complete codes into strings
  *
  * @param complete_code
  *               Code to convert
@@ -408,7 +450,7 @@ static inline int __cvmx_usb_get_data_pid(cvmx_usb_pipe_t *pipe)
  * cvmx_usb_state_t structures.
  *
  * This utilizes cvmx_helper_board_usb_get_num_ports()
- * to get any board specific variatons.
+ * to get any board specific variations.
  *
  * @return Number of port, zero if usb isn't supported
  */
@@ -416,17 +458,24 @@ int cvmx_usb_get_num_ports(void)
 {
     int arch_ports = 0;
 
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+        arch_ports = 1;
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
         arch_ports = 2;
+    else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+        arch_ports = 1;
     else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
-        arch_ports = 0; /* This chip has USB but it doesn't support DMA */
-    else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
-        arch_ports = 0;
-    else
         arch_ports = 1;
+    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+        arch_ports = 1;
+    else
+        arch_ports = 0;
 
     return __cvmx_helper_board_usb_get_num_ports(arch_ports);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_get_num_ports);
+#endif
 
 
 /**
@@ -534,114 +583,6 @@ static inline void __cvmx_usb_remove_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_p
 
 
 /**
- * @INTERNAL
- * Perfrom USB device mode initialization after a reset completes.
- * This should be called after USBC0/1_GINTSTS[USBRESET] and
- * coresponds to section 22.6.1.1, "Initialization on USB Reset",
- * in the manual.
- *
- * @param usb    USB device state populated by
- *               cvmx_usb_initialize().
- *
- * @return CVMX_USB_SUCCESS or a negative error code defined in
- *         cvmx_usb_status_t.
- */
-static cvmx_usb_status_t __cvmx_usb_device_reset_complete(cvmx_usb_internal_state_t *usb)
-{
-    cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
-    int i;
-
-    CVMX_USB_LOG_CALLED();
-    CVMX_USB_LOG_PARAM("%p", usb);
-
-    /* 1. Set USBC0/1_DOEPCTLn[SNAK] = 1 (for all OUT endpoints, n = 0-4). */
-    for (i=0; i<5; i++)
-    {
-        USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(i, usb->index),
-                        cvmx_usbcx_doepctlx_t, snak, 1);
-    }
-
-    /* 2. Unmask the following interrupt bits:
-        USBC0/1_DAINTMSK[INEPMSK] = 1 (control 0 IN endpoint)
-        USBC0/1_DAINTMSK[OUTEPMSK] = 1 (control 0 OUT endpoint)
-        USBC0/1_DOEPMSK[SETUPMSK] = 1
-        USBC0/1_DOEPMSK[XFERCOMPLMSK] = 1
-        USBC0/1_DIEPMSK[XFERCOMPLMSK] = 1
-        USBC0/1_DIEPMSK[TIMEOUTMSK] = 1 */
-    USB_SET_FIELD32(CVMX_USBCX_DAINTMSK(usb->index), cvmx_usbcx_daintmsk_t,
-                    inepmsk, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DAINTMSK(usb->index), cvmx_usbcx_daintmsk_t,
-                    outepmsk, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DOEPMSK(usb->index), cvmx_usbcx_doepmsk_t,
-                    setupmsk, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DOEPMSK(usb->index), cvmx_usbcx_doepmsk_t,
-                    xfercomplmsk, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DIEPMSK(usb->index), cvmx_usbcx_diepmsk_t,
-                    xfercomplmsk, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DIEPMSK(usb->index), cvmx_usbcx_diepmsk_t,
-                    timeoutmsk, 1);
-
-    /* 3. To transmit or receive data, the device must initialize more
-        registers as specified in Section 22.6.1.7 */
-    /* Nothing needed */
-
-    /* 4. Set up the data FIFO RAM for each of the FIFOs:
-        Program USBC0/1_GRXFSIZ to be able to receive control OUT data and
-        SETUP data. This must equal at least one maximum packet size of
-        control endpoint 0 + 2 Dwords (for the status of the control OUT
-        data packet) + 10 Dwords (for SETUP packets).
-        Program USBC0/1_GNPTXFSIZ to be able to transmit control IN data. This
-        must equal at least one maximum packet size of control endpoint 0. */
-
-    /* Read the HWCFG3 register so we know how much space is in the FIFO */
-    usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
-
-    {
-        cvmx_usbcx_gnptxfsiz_t gnptxfsiz;
-        int fifo_space = usbcx_ghwcfg3.s.dfifodepth;
-        int i;
-
-        /* Start at the top of the FIFO and assign space for each periodic
-            fifo */
-        for (i=4;i>0;i--)
-        {
-            cvmx_usbcx_dptxfsizx_t siz;
-            siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index));
-            fifo_space -= siz.s.dptxfsize;
-            siz.s.dptxfstaddr = fifo_space;
-            __cvmx_usb_write_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index), siz.u32);
-        }
-
-        /* Assign half the leftover space to the non periodic tx fifo */
-        gnptxfsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
-        gnptxfsiz.s.nptxfdep = fifo_space / 2;
-        fifo_space -= gnptxfsiz.s.nptxfdep;
-        gnptxfsiz.s.nptxfstaddr = fifo_space;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), gnptxfsiz.u32);
-
-        /* Assign the remain space to the RX fifo */
-        USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz_t,
-                        rxfdep, fifo_space);
-    }
-
-    /* 5. Program the following fields in the endpoint-specific registers for
-        control OUT endpoint 0 to receive a SETUP packet
-        USBC0/1_DOEPTSIZ0[SUPCNT] = 0x3 (to receive up to three back-to-back
-        SETUP packets)
-        In DMA mode, USBC0/1_DOEPDMA0 register with a memory address to
-        store any SETUP packets received */
-    USB_SET_FIELD32(CVMX_USBCX_DOEPTSIZX(0, usb->index),
-                    cvmx_usbcx_doeptsizx_t, mc, 3);
-    // FIXME
-
-    /* At this point, all initialization required to receive SETUP packets is
-        done. */
-
-    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
-}
-
-
-/**
  * Initialize a USB port for use. This must be called before any
  * other access to the Octeon USB port is made. The port starts
  * off in the disabled state.
@@ -791,7 +732,7 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
         setting USBN0/1_CLK_CTL[ENABLE] = 1.  Divide the core clock down such
         that USB is as close as possible to 125Mhz */
     {
-        int divisor = (cvmx_sysinfo_get()->cpu_clock_hz+125000000-1)/125000000;
+        int divisor = (cvmx_clock_get_rate(CVMX_CLOCK_CORE)+125000000-1)/125000000;
         if (divisor < 4)  /* Lower than 4 doesn't seem to work properly */
             divisor = 4;
         usbn_clk_ctl.s.divide = divisor;
@@ -833,16 +774,7 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
     /* 9. Program the USBP control and status register to select host or
         device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
         device */
-    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
-    {
-        usbn_usbp_ctl_status.s.hst_mode = 1;
-        usbn_usbp_ctl_status.s.dm_pulld = 0;
-        usbn_usbp_ctl_status.s.dp_pulld = 0;
-    }
-    else
-    {
-        usbn_usbp_ctl_status.s.hst_mode = 0;
-    }
+    usbn_usbp_ctl_status.s.hst_mode = 0;
     __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
                            usbn_usbp_ctl_status.u64);
     /* 10. Wait 1 µs */
@@ -874,14 +806,17 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
         Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 */
     {
         cvmx_usbcx_gahbcfg_t usbcx_gahbcfg;
+        /* Due to an errata, CN31XX doesn't support DMA */
+        if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+            usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
         usbcx_gahbcfg.u32 = 0;
-        usbcx_gahbcfg.s.dmaen = !OCTEON_IS_MODEL(OCTEON_CN31XX);
-        /* If we are using DMA, start off with 8 idle channels. Without
-            DMA we emulate a single channel */
-        if (usbcx_gahbcfg.s.dmaen)
-            usb->idle_hardware_channels = 0xff;
+        usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+            usb->idle_hardware_channels = 0x1;  /* Only use one channel with non DMA */
+        else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
+            usb->idle_hardware_channels = 0xf7; /* CN5XXX have an errata with channel 3 */
         else
-            usb->idle_hardware_channels = 0x1;
+            usb->idle_hardware_channels = 0xff;
         usbcx_gahbcfg.s.hbstlen = 0;
         usbcx_gahbcfg.s.nptxfemplvl = 1;
         usbcx_gahbcfg.s.ptxfemplvl = 1;
@@ -910,8 +845,6 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
         Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 */
     {
         cvmx_usbcx_gintmsk_t usbcx_gintmsk;
-        cvmx_usbcx_hcintmskx_t usbc_hcintmsk;
-        cvmx_usbcx_haintmsk_t usbc_haintmsk;
         int channel;
 
         usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
@@ -919,23 +852,17 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
         usbcx_gintmsk.s.modemismsk = 1;
         usbcx_gintmsk.s.hchintmsk = 1;
         usbcx_gintmsk.s.sofmsk = 0;
+        /* We need RX FIFO interrupts if we don't have DMA */
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+            usbcx_gintmsk.s.rxflvlmsk = 1;
         __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
                                usbcx_gintmsk.u32);
 
-        /* Enable the channel halt interrupt */
-        usbc_hcintmsk.u32 = 0;
-        usbc_hcintmsk.s.chhltdmsk = 1;
+        /* Disable all channel interrupts. We'll enable them per channel later */
         for (channel=0; channel<8; channel++)
-            if (usb->idle_hardware_channels & (1<<channel))
-                __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
-
-        /* Enable the channel interrupt to propagate */
-        usbc_haintmsk.u32 = 0;
-        usbc_haintmsk.s.haintmsk = usb->idle_hardware_channels;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
+            __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
     }
 
-    if ((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0)
     {
         /* Host Port Initialization */
         if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
@@ -962,53 +889,15 @@ cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
 
         /* Steps 4-15 from the manual are done later in the port enable */
     }
-    else
-    {
-        /* Device Port Initialization */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: USB%d is in device mode\n", __FUNCTION__, usb->index);
-
-        /* 1. Program the following fields in the USBC0/1_DCFG register:
-            Device speed, USBC0/1_DCFG[DEVSPD] = 0 (high speed)
-            Non-zero-length status OUT handshake, USBC0/1_DCFG[NZSTSOUTHSHK]=0
-            Periodic frame interval (if periodic endpoints are supported),
-            USBC0/1_DCFG[PERFRINT] = 1 */
-        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
-                        devspd, 0);
-        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
-                        nzstsouthshk, 0);
-        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
-                        perfrint, 1);
-
-        /* 2. Program the USBC0/1_GINTMSK register to unmask the following
-            interrupts:
-            USB Reset, USBC0/1_GINTMSK[USBRSTMSK] = 1
-            Enumeration done, USBC0/1_GINTMSK[ENUMDONEMSK] = 1
-            SOF, USBC0/1_GINTMSK[SOFMSK] = 1 */
-        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
-                        usbrstmsk, 1);
-        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
-                        enumdonemsk, 1);
-        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
-                        sofmsk, 1);
-
-        /* 3. Wait for the USBC0/1_GINTSTS[USBRESET] interrupt, which
-            indicates a reset has been detected on the USB and lasts for
-            about 10 ms. On receiving this interrupt, the application must
-            perform the steps listed in Section 22.6.1.1, "Initialization on
-            USB Reset". */
-        /* Handled in cvmx_poll() usbc_gintsts.s.usbrst processing */
-
-        /* 4. Wait for the USBC0/1_GINTSTS[ENUMERATIONDONE] interrupt, which
-            indicates the end of reset on the USB. On receiving this interrupt,
-            the application must read the USBC0/1_DSTS register to determine
-            the enumeration speed and perform the steps listed in Section
-            22.6.1.2, "Initialization on Enumeration Completion". */
-        /* Handled in cvmx_poll() usbc_gintsts.s.enumdone processing */
-    }
 
+#ifdef __CVMX_ERROR_H__
+    cvmx_error_enable_group(CVMX_ERROR_GROUP_USB, usb->index);
+#endif
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_initialize);
+#endif
 
 
 /**
@@ -1038,6 +927,10 @@ cvmx_usb_status_t cvmx_usb_shutdown(cvmx_usb_state_t *state)
         usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
         CVMX_USB_RETURN(CVMX_USB_BUSY);
 
+#ifdef __CVMX_ERROR_H__
+    cvmx_error_disable_group(CVMX_ERROR_GROUP_USB, usb->index);
+#endif
+
     /* Disable the clocks and put them in power on reset */
     usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
     usbn_clk_ctl.s.enable = 1;
@@ -1049,6 +942,9 @@ cvmx_usb_status_t cvmx_usb_shutdown(cvmx_usb_state_t *state)
                            usbn_clk_ctl.u64);
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_shutdown);
+#endif
 
 
 /**
@@ -1068,8 +964,6 @@ cvmx_usb_status_t cvmx_usb_enable(cvmx_usb_state_t *state)
 
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", state);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
 
@@ -1150,6 +1044,9 @@ cvmx_usb_status_t cvmx_usb_enable(cvmx_usb_state_t *state)
 
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_enable);
+#endif
 
 
 /**
@@ -1170,13 +1067,14 @@ cvmx_usb_status_t cvmx_usb_disable(cvmx_usb_state_t *state)
 
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", state);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     /* Disable the port */
     USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtena, 1);
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_disable);
+#endif
 
 
 /**
@@ -1223,6 +1121,9 @@ cvmx_usb_port_status_t cvmx_usb_get_status(cvmx_usb_state_t *state)
                      result.connect_change);
     return result;
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_get_status);
+#endif
 
 
 /**
@@ -1245,6 +1146,9 @@ void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t port_st
     usb->port_status = port_status;
     CVMX_USB_RETURN_NOTHING();
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_set_status);
+#endif
 
 
 /**
@@ -1305,7 +1209,7 @@ static inline int __cvmx_usb_get_pipe_handle(cvmx_usb_internal_state_t *usb,
  * @param max_packet The maximum packet length the device can
  *                   transmit/receive (low speed=0-8, full
  *                   speed=0-1023, high speed=0-1024). This value
- *                   comes from the stadnard endpoint descriptor
+ *                   comes from the standard endpoint descriptor
  *                   field wMaxPacketSize bits <10:0>.
  * @param transfer_type
  *                   The type of transfer this pipe is for.
@@ -1321,7 +1225,7 @@ static inline int __cvmx_usb_get_pipe_handle(cvmx_usb_internal_state_t *usb,
  *                   For high speed devices, this is the maximum
  *                   allowed number of packet per microframe.
  *                   Specify zero for non high speed devices. This
- *                   value comes from the stadnard endpoint descriptor
+ *                   value comes from the standard endpoint descriptor
  *                   field wMaxPacketSize bits <12:11>.
  * @param hub_device_addr
  *                   Hub device address this device is connected
@@ -1389,8 +1293,6 @@ int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     /* Find a free pipe */
     pipe = usb->free_pipes.head;
@@ -1412,15 +1314,21 @@ int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
         if one wasn't supplied */
     if (!interval)
         interval = 1;
-    if (device_speed == CVMX_USB_SPEED_HIGH)
-        pipe->interval = (uint64_t)interval * cvmx_sysinfo_get()->cpu_clock_hz / 8000;
+    if (__cvmx_usb_pipe_needs_split(usb, pipe))
+    {
+        pipe->interval = interval*8;
+        /* Force start splits to be schedule on uFrame 0 */
+        pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
+    }
     else
-        pipe->interval = (uint64_t)interval * cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    {
+        pipe->interval = interval;
+        pipe->next_tx_frame = usb->frame_number + pipe->interval;
+    }
     pipe->multi_count = multi_count;
     pipe->hub_device_addr = hub_device_addr;
     pipe->hub_port = hub_port;
     pipe->pid_toggle = 0;
-    pipe->next_tx_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT) + pipe->interval;
     pipe->split_sc_frame = -1;
     __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
 
@@ -1429,7 +1337,212 @@ int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
 
     CVMX_USB_RETURN(__cvmx_usb_get_pipe_handle(usb, pipe));
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_open_pipe);
+#endif
+
+
+/**
+ * @INTERNAL
+ * Poll the RX FIFOs and remove data as needed. This function is only used
+ * in non DMA mode. It is very important that this function be called quickly
+ * enough to prevent FIFO overflow.
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usb_initialize().
+ */
+static void __cvmx_usb_poll_rx_fifo(cvmx_usb_internal_state_t *usb)
+{
+    cvmx_usbcx_grxstsph_t rx_status;
+    int channel;
+    int bytes;
+    uint64_t address;
+    uint32_t *ptr;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+
+    rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
+    /* Only read data if IN data is there */
+    if (rx_status.s.pktsts != 2)
+        CVMX_USB_RETURN_NOTHING();
+    /* Check if no data is available */
+    if (!rx_status.s.bcnt)
+        CVMX_USB_RETURN_NOTHING();
+
+    channel = rx_status.s.chnum;
+    bytes = rx_status.s.bcnt;
+    if (!bytes)
+        CVMX_USB_RETURN_NOTHING();
+
+    /* Get where the DMA engine would have written this data */
+    address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
+    ptr = cvmx_phys_to_ptr(address);
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
+
+    /* Loop writing the FIFO data for this packet into memory */
+    while (bytes > 0)
+    {
+        *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
+        bytes -= 4;
+    }
+    CVMX_SYNCW;
+
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * Fill the TX hardware fifo with data out of the software
+ * fifos
+ *
+ * @param usb       USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param fifo      Software fifo to use
+ * @param available Amount of space in the hardware fifo
+ *
+ * @return Non zero if the hardware fifo was too small and needs
+ *         to be serviced again.
+ */
+static int __cvmx_usb_fill_tx_hw(cvmx_usb_internal_state_t *usb, cvmx_usb_tx_fifo_t *fifo, int available)
+{
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%p", fifo);
+    CVMX_USB_LOG_PARAM("%d", available);
+
+    /* We're done either when there isn't anymore space or the software FIFO
+        is empty */
+    while (available && (fifo->head != fifo->tail))
+    {
+        int i = fifo->tail;
+        const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
+        uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
+        int words = available;
+
+        /* Limit the amount of data to waht the SW fifo has */
+        if (fifo->entry[i].size <= available)
+        {
+            words = fifo->entry[i].size;
+            fifo->tail++;
+            if (fifo->tail > MAX_CHANNELS)
+                fifo->tail = 0;
+        }
+
+        /* Update the next locations and counts */
+        available -= words;
+        fifo->entry[i].address += words * 4;
+        fifo->entry[i].size -= words;
+
+        /* Write the HW fifo data. The read every three writes is due
+            to an errata on CN3XXX chips */
+        while (words > 3)
+        {
+            cvmx_write64_uint32(csr_address, *ptr++);
+            cvmx_write64_uint32(csr_address, *ptr++);
+            cvmx_write64_uint32(csr_address, *ptr++);
+            cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
+            words -= 3;
+        }
+        cvmx_write64_uint32(csr_address, *ptr++);
+        if (--words)
+        {
+            cvmx_write64_uint32(csr_address, *ptr++);
+            if (--words)
+                cvmx_write64_uint32(csr_address, *ptr++);
+        }
+        cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
+    }
+    CVMX_USB_RETURN(fifo->head != fifo->tail);
+}
+
+
+/**
+ * Check the hardware FIFOs and fill them as needed
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ */
+static void __cvmx_usb_poll_tx_fifo(cvmx_usb_internal_state_t *usb)
+{
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+
+    if (usb->periodic.head != usb->periodic.tail)
+    {
+        cvmx_usbcx_hptxsts_t tx_status;
+        tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
+        if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
+            USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 1);
+        else
+            USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 0);
+    }
+
+    if (usb->nonperiodic.head != usb->nonperiodic.tail)
+    {
+        cvmx_usbcx_gnptxsts_t tx_status;
+        tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
+        if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
+            USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 1);
+        else
+            USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 0);
+    }
+
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Fill the TX FIFO with an outgoing packet
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usb_initialize().
+ * @param channel Channel number to get packet from
+ */
+static void __cvmx_usb_fill_tx_fifo(cvmx_usb_internal_state_t *usb, int channel)
+{
+    cvmx_usbcx_hccharx_t hcchar;
+    cvmx_usbcx_hcspltx_t usbc_hcsplt;
+    cvmx_usbcx_hctsizx_t usbc_hctsiz;
+    cvmx_usb_tx_fifo_t *fifo;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%d", channel);
+
+    /* We only need to fill data on outbound channels */
+    hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
+    if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
+        CVMX_USB_RETURN_NOTHING();
+
+    /* OUT Splits only have data on the start and not the complete */
+    usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
+    if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
+        CVMX_USB_RETURN_NOTHING();
+
+    /* Find out how many bytes we need to fill and convert it into 32bit words */
+    usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
+    if (!usbc_hctsiz.s.xfersize)
+        CVMX_USB_RETURN_NOTHING();
+
+    if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
+        (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
+        fifo = &usb->periodic;
+    else
+        fifo = &usb->nonperiodic;
+
+    fifo->entry[fifo->head].channel = channel;
+    fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
+    fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
+    fifo->head++;
+    if (fifo->head > MAX_CHANNELS)
+        fifo->head = 0;
 
+    __cvmx_usb_poll_tx_fifo(usb);
+
+    CVMX_USB_RETURN_NOTHING();
+}
 
 /**
  * @INTERNAL
@@ -1449,6 +1562,7 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
     cvmx_usb_transaction_t *transaction = pipe->head;
     cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
     int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
+    int packets_to_transfer;
     cvmx_usbcx_hctsizx_t usbc_hctsiz;
 
     CVMX_USB_LOG_CALLED();
@@ -1466,7 +1580,7 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
         case CVMX_USB_STAGE_SETUP:
             usbc_hctsiz.s.pid = 3; /* Setup */
-            usbc_hctsiz.s.xfersize = sizeof(*header);
+            bytes_to_transfer = sizeof(*header);
             /* All Control operations start with a setup going OUT */
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
             /* Setup send the control header instead of the buffer data. The
@@ -1475,7 +1589,7 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
         case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
             usbc_hctsiz.s.pid = 3; /* Setup */
-            usbc_hctsiz.s.xfersize = 0;
+            bytes_to_transfer = 0;
             /* All Control operations start with a setup going OUT */
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
             USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
@@ -1484,12 +1598,11 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
             if (__cvmx_usb_pipe_needs_split(usb, pipe))
             {
-                usbc_hctsiz.s.xfersize = (header->s.request_type & 0x80) ? 0 : bytes_to_transfer;
-                if (usbc_hctsiz.s.xfersize > pipe->max_packet)
-                    usbc_hctsiz.s.xfersize = pipe->max_packet;
+                if (header->s.request_type & 0x80)
+                    bytes_to_transfer = 0;
+                else if (bytes_to_transfer > pipe->max_packet)
+                    bytes_to_transfer = pipe->max_packet;
             }
-            else
-                usbc_hctsiz.s.xfersize = bytes_to_transfer;
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
                             cvmx_usbcx_hccharx_t, epdir,
                             ((header->s.request_type & 0x80) ?
@@ -1498,7 +1611,8 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
         case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
             usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
-            usbc_hctsiz.s.xfersize = (header->s.request_type & 0x80) ? bytes_to_transfer : 0;
+            if (!(header->s.request_type & 0x80))
+                bytes_to_transfer = 0;
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
                             cvmx_usbcx_hccharx_t, epdir,
                             ((header->s.request_type & 0x80) ?
@@ -1508,7 +1622,7 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
         case CVMX_USB_STAGE_STATUS:
             usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
-            usbc_hctsiz.s.xfersize = 0;
+            bytes_to_transfer = 0;
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
                             ((header->s.request_type & 0x80) ?
                              CVMX_USB_DIRECTION_OUT :
@@ -1516,7 +1630,7 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
         case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
             usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
-            usbc_hctsiz.s.xfersize = 0;
+            bytes_to_transfer = 0;
             USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
                             ((header->s.request_type & 0x80) ?
                              CVMX_USB_DIRECTION_OUT :
@@ -1525,10 +1639,38 @@ static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
             break;
     }
 
-    /* Set the number of packets needed for this transfer */
-    usbc_hctsiz.s.pktcnt = (usbc_hctsiz.s.xfersize + pipe->max_packet - 1) / pipe->max_packet;
-    if (!usbc_hctsiz.s.pktcnt)
-        usbc_hctsiz.s.pktcnt = 1;
+    /* Make sure the transfer never exceeds the byte limit of the hardware.
+        Further bytes will be sent as continued transactions */
+    if (bytes_to_transfer > MAX_TRANSFER_BYTES)
+    {
+        /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
+        bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
+        bytes_to_transfer *= pipe->max_packet;
+    }
+
+    /* Calculate the number of packets to transfer. If the length is zero
+        we still need to transfer one packet */
+    packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
+    if (packets_to_transfer == 0)
+        packets_to_transfer = 1;
+    else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA))
+    {
+        /* Limit to one packet when not using DMA. Channels must be restarted
+            between every packet for IN transactions, so there is no reason to
+            do multiple packets in a row */
+        packets_to_transfer = 1;
+        bytes_to_transfer = packets_to_transfer * pipe->max_packet;
+    }
+    else if (packets_to_transfer > MAX_TRANSFER_PACKETS)
+    {
+        /* Limit the number of packet and data transferred to what the
+            hardware can handle */
+        packets_to_transfer = MAX_TRANSFER_PACKETS;
+        bytes_to_transfer = packets_to_transfer * pipe->max_packet;
+    }
+
+    usbc_hctsiz.s.xfersize = bytes_to_transfer;
+    usbc_hctsiz.s.pktcnt = packets_to_transfer;
 
     __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
     CVMX_USB_RETURN_NOTHING();
@@ -1549,7 +1691,6 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
                                      cvmx_usb_pipe_t *pipe)
 {
     cvmx_usb_transaction_t *transaction = pipe->head;
-    cvmx_usbcx_hfnum_t usbc_hfnum;
 
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", usb);
@@ -1566,10 +1707,6 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
     /* Make sure all writes to the DMA region get flushed */
     CVMX_SYNCW;
 
-    /* Read the current frame number for use with split, INTERRUPT,  and ISO
-        transactions */
-    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
-
     /* Attach the channel to the pipe */
     usb->pipe_for_channel[channel] = pipe;
     pipe->channel = channel;
@@ -1581,10 +1718,38 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
     /* Enable the channel interrupt bits */
     {
         cvmx_usbcx_hcintx_t usbc_hcint;
+        cvmx_usbcx_hcintmskx_t usbc_hcintmsk;
+        cvmx_usbcx_haintmsk_t usbc_haintmsk;
 
         /* Clear all channel status bits */
         usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
         __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
+
+        usbc_hcintmsk.u32 = 0;
+        usbc_hcintmsk.s.chhltdmsk = 1;
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+        {
+            /* Channels need these extra interrupts when we aren't in DMA mode */
+            usbc_hcintmsk.s.datatglerrmsk = 1;
+            usbc_hcintmsk.s.frmovrunmsk = 1;
+            usbc_hcintmsk.s.bblerrmsk = 1;
+            usbc_hcintmsk.s.xacterrmsk = 1;
+            if (__cvmx_usb_pipe_needs_split(usb, pipe))
+            {
+                /* Splits don't generate xfercompl, so we need ACK and NYET */
+                usbc_hcintmsk.s.nyetmsk = 1;
+                usbc_hcintmsk.s.ackmsk = 1;
+            }
+            usbc_hcintmsk.s.nakmsk = 1;
+            usbc_hcintmsk.s.stallmsk = 1;
+            usbc_hcintmsk.s.xfercomplmsk = 1;
+        }
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
+
+        /* Enable the channel interrupt to propagate */
+        usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
+        usbc_haintmsk.s.haintmsk |= 1<<channel;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
     }
 
     /* Setup the locations the DMA engines use  */
@@ -1600,6 +1765,7 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
     {
         cvmx_usbcx_hcspltx_t usbc_hcsplt = {.u32 = 0};
         cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = 0};
+        int packets_to_transfer;
         int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
 
         /* ISOCHRONOUS transactions store each individual transfer size in the
@@ -1617,9 +1783,9 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
             if ((transaction->stage&1) == 0)
             {
                 if (transaction->type == CVMX_USB_TRANSFER_BULK)
-                    pipe->split_sc_frame = (usbc_hfnum.s.frnum + 1) & 0x7f;
+                    pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
                 else
-                    pipe->split_sc_frame = (usbc_hfnum.s.frnum + 2) & 0x7f;
+                    pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
             }
             else
                 pipe->split_sc_frame = -1;
@@ -1641,7 +1807,10 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
                 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
                 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS))
             {
-                /* See if we've started this tranfer and sent data */
+                /* Clear the split complete frame number as there isn't going
+                    to be a split complete */
+                pipe->split_sc_frame = -1;
+                /* See if we've started this transfer and sent data */
                 if (transaction->actual_bytes == 0)
                 {
                     /* Nothing sent yet, this is either a begin or the
@@ -1666,10 +1835,38 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
             }
         }
 
+        /* Make sure the transfer never exceeds the byte limit of the hardware.
+            Further bytes will be sent as continued transactions */
+        if (bytes_to_transfer > MAX_TRANSFER_BYTES)
+        {
+            /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
+            bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
+            bytes_to_transfer *= pipe->max_packet;
+        }
+
+        /* Calculate the number of packets to transfer. If the length is zero
+            we still need to transfer one packet */
+        packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
+        if (packets_to_transfer == 0)
+            packets_to_transfer = 1;
+        else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA))
+        {
+            /* Limit to one packet when not using DMA. Channels must be restarted
+                between every packet for IN transactions, so there is no reason to
+                do multiple packets in a row */
+            packets_to_transfer = 1;
+            bytes_to_transfer = packets_to_transfer * pipe->max_packet;
+        }
+        else if (packets_to_transfer > MAX_TRANSFER_PACKETS)
+        {
+            /* Limit the number of packet and data transferred to what the
+                hardware can handle */
+            packets_to_transfer = MAX_TRANSFER_PACKETS;
+            bytes_to_transfer = packets_to_transfer * pipe->max_packet;
+        }
+
         usbc_hctsiz.s.xfersize = bytes_to_transfer;
-        usbc_hctsiz.s.pktcnt = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
-        if (!usbc_hctsiz.s.pktcnt)
-            usbc_hctsiz.s.pktcnt = 1;
+        usbc_hctsiz.s.pktcnt = packets_to_transfer;
 
         /* Update the DATA0/DATA1 toggle */
         usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
@@ -1685,9 +1882,8 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
     {
         cvmx_usbcx_hccharx_t usbc_hcchar = {.u32 = 0};
 
-        /* Make all transfers start on the next frame and not this one. This
-            way the time we spend processing doesn't affect USB timing */
-        usbc_hcchar.s.oddfrm = !(usbc_hfnum.s.frnum&1);
+        /* Set the startframe odd/even properly. This is only used for periodic */
+        usbc_hcchar.s.oddfrm = usb->frame_number&1;
 
         /* Set the number of back to back packets allowed by this endpoint.
             Split transactions interpret "ec" as the number of immediate
@@ -1724,7 +1920,7 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
         case CVMX_USB_TRANSFER_ISOCHRONOUS:
             if (!__cvmx_usb_pipe_needs_split(usb, pipe))
             {
-                /* ISO transactions require differnet PIDs depending on direction
+                /* ISO transactions require different PIDs depending on direction
                     and how many packets are needed */
                 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)
                 {
@@ -1741,7 +1937,12 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
         transaction->xfersize = usbc_hctsiz.s.xfersize;
         transaction->pktcnt = usbc_hctsiz.s.pktcnt;
     }
+    /* Remeber when we start a split transaction */
+    if (__cvmx_usb_pipe_needs_split(usb, pipe))
+        usb->active_split = transaction;
     USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, chena, 1);
+    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+        __cvmx_usb_fill_tx_fifo(usb, channel);
     CVMX_USB_RETURN_NOTHING();
 }
 
@@ -1749,22 +1950,23 @@ static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
 /**
  * @INTERNAL
  * Find a pipe that is ready to be scheduled to hardware.
- *
- * @param list       Pipe list to search
- * @param usbc_hfnum Current USB frame number
- * @param current_cycle
- *                   Cycle counter to use as a time reference.
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param list   Pipe list to search
+ * @param current_frame
+ *               Frame counter to use as a time reference.
  *
  * @return Pipe or NULL if none are ready
  */
-static cvmx_usb_pipe_t *__cvmx_usb_find_ready_pipe(cvmx_usb_pipe_list_t *list, cvmx_usbcx_hfnum_t usbc_hfnum, uint64_t current_cycle)
+static cvmx_usb_pipe_t *__cvmx_usb_find_ready_pipe(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_list_t *list, uint64_t current_frame)
 {
     cvmx_usb_pipe_t *pipe = list->head;
     while (pipe)
     {
         if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
-            (pipe->next_tx_cycle <= current_cycle) &&
-            ((pipe->split_sc_frame == -1) || ((((int)usbc_hfnum.s.frnum - (int)pipe->split_sc_frame) & 0x7f) < 0x40)))
+            (pipe->next_tx_frame <= current_frame) &&
+            ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
+            (!usb->active_split || (usb->active_split == pipe->head)))
         {
             CVMX_PREFETCH(pipe, 128);
             CVMX_PREFETCH(pipe->head, 0);
@@ -1789,13 +1991,20 @@ static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
 {
     int channel;
     cvmx_usb_pipe_t *pipe;
-    cvmx_usbcx_hfnum_t usbc_hfnum;
-    uint64_t current_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
+    int need_sof;
+    cvmx_usb_transfer_t ttype;
 
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", usb);
 
-    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+    {
+        /* Without DMA we need to be careful to not schedule something at the end of a frame and cause an overrun */
+        cvmx_usbcx_hfnum_t hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
+        cvmx_usbcx_hfir_t hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
+        if (hfnum.s.frrem < hfir.s.frint/4)
+            goto done;
+    }
 
     while (usb->idle_hardware_channels)
     {
@@ -1816,15 +2025,15 @@ static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
             /* Only process periodic pipes on SOF interrupts. This way we are
                 sure that the periodic data is sent in the beginning of the
                 frame */
-            pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usbc_hfnum, current_cycle);
+            pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
             if (cvmx_likely(!pipe))
-                pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usbc_hfnum, current_cycle);
+                pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
         }
         if (cvmx_likely(!pipe))
         {
-            pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usbc_hfnum, current_cycle);
+            pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
             if (cvmx_likely(!pipe))
-                pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_BULK, usbc_hfnum, current_cycle);
+                pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
         }
         if (!pipe)
             break;
@@ -1864,6 +2073,25 @@ static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
         }
         __cvmx_usb_start_channel(usb, channel, pipe);
     }
+
+done:
+    /* Only enable SOF interrupts when we have transactions pending in the
+        future that might need to be scheduled */
+    need_sof = 0;
+    for (ttype=CVMX_USB_TRANSFER_CONTROL; ttype<=CVMX_USB_TRANSFER_INTERRUPT; ttype++)
+    {
+        pipe = usb->active_pipes[ttype].head;
+        while (pipe)
+        {
+            if (pipe->next_tx_frame > usb->frame_number)
+            {
+                need_sof = 1;
+                break;
+            }
+            pipe=pipe->next;
+        }
+    }
+    USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, need_sof);
     CVMX_USB_RETURN_NOTHING();
 }
 
@@ -1951,19 +2179,23 @@ static void __cvmx_usb_perform_complete(cvmx_usb_internal_state_t * usb,
     CVMX_USB_LOG_PARAM("%p", transaction);
     CVMX_USB_LOG_PARAM("%d", complete_code);
 
+    /* If this was a split then clear our split in progress marker */
+    if (usb->active_split == transaction)
+        usb->active_split = NULL;
+
     /* Isochronous transactions need extra processing as they might not be done
         after a single data transfer */
     if (cvmx_unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS))
     {
-        /* Update the number of bytes transfered in this ISO packet */
+        /* Update the number of bytes transferred in this ISO packet */
         transaction->iso_packets[0].length = transaction->actual_bytes;
         transaction->iso_packets[0].status = complete_code;
 
-        /* If there are more ISOs pending and we suceeded, schedule the next
+        /* If there are more ISOs pending and we succeeded, schedule the next
             one */
         if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS))
         {
-            transaction->actual_bytes = 0;      /* No bytes transfered for this packet as of yet */
+            transaction->actual_bytes = 0;      /* No bytes transferred for this packet as of yet */
             transaction->iso_number_packets--;  /* One less ISO waiting to transfer */
             transaction->iso_packets++;         /* Increment to the next location in our packet array */
             transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
@@ -1990,10 +2222,6 @@ static void __cvmx_usb_perform_complete(cvmx_usb_internal_state_t * usb,
                                 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
                                 complete_code);
     __cvmx_usb_free_transaction(usb, transaction);
-    /* Disable SOF interrupts if we don't have any pending transactions */
-    usb->active_transactions--;
-    if (usb->active_transactions == 0)
-        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, 0);
 done:
     CVMX_USB_RETURN_NOTHING();
 }
@@ -2015,7 +2243,7 @@ done:
  * @param control_header
  *                  For control transactions, the 8 byte standard header
  * @param iso_start_frame
- *                  For ISO transactiosn, the start frame
+ *                  For ISO transactions, the start frame
  * @param iso_number_packets
  *                  For ISO, the number of packet in the transaction.
  * @param iso_packets
@@ -2056,11 +2284,6 @@ static int __cvmx_usb_submit_transaction(cvmx_usb_internal_state_t *usb,
     if (cvmx_unlikely(!transaction))
         CVMX_USB_RETURN(CVMX_USB_NO_MEMORY);
 
-    /* Enable SOF interrupts now that we have pending transactions */
-    if (usb->active_transactions == 0)
-        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, 1);
-    usb->active_transactions++;
-
     transaction->type = type;
     transaction->flags |= flags;
     transaction->buffer = buffer;
@@ -2084,6 +2307,9 @@ static int __cvmx_usb_submit_transaction(cvmx_usb_internal_state_t *usb,
     }
     else
     {
+        if (pipe->next_tx_frame < usb->frame_number)
+            pipe->next_tx_frame = usb->frame_number + pipe->interval -
+                (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
         transaction->prev = NULL;
         pipe->head = transaction;
         __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
@@ -2151,8 +2377,6 @@ int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely(buffer_length < 0))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
                                          CVMX_USB_TRANSFER_BULK,
@@ -2167,6 +2391,9 @@ int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
                                          user_data);
     CVMX_USB_RETURN(submit_handle);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_submit_bulk);
+#endif
 
 
 /**
@@ -2219,8 +2446,6 @@ int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely(buffer_length < 0))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
                                          CVMX_USB_TRANSFER_INTERRUPT,
@@ -2235,6 +2460,9 @@ int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
                                          user_data);
     CVMX_USB_RETURN(submit_handle);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_submit_interrupt);
+#endif
 
 
 /**
@@ -2297,8 +2525,6 @@ int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely(!buffer && (buffer_length != 0)))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
     if ((header->s.request_type & 0x80) == 0)
         buffer_length = cvmx_le16_to_cpu(header->s.length);
 
@@ -2315,6 +2541,9 @@ int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
                                          user_data);
     CVMX_USB_RETURN(submit_handle);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_submit_control);
+#endif
 
 
 /**
@@ -2396,8 +2625,6 @@ int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely(buffer_length < 0))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
                                          CVMX_USB_TRANSFER_ISOCHRONOUS,
@@ -2412,6 +2639,9 @@ int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
                                          user_data);
     CVMX_USB_RETURN(submit_handle);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_submit_isochronous);
+#endif
 
 
 /**
@@ -2447,8 +2677,6 @@ cvmx_usb_status_t cvmx_usb_cancel(cvmx_usb_state_t *state, int pipe_handle,
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
     if (cvmx_unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     /* Fail if the pipe isn't open */
     if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
@@ -2483,6 +2711,9 @@ cvmx_usb_status_t cvmx_usb_cancel(cvmx_usb_state_t *state, int pipe_handle,
     __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_cancel);
+#endif
 
 
 /**
@@ -2507,8 +2738,6 @@ cvmx_usb_status_t cvmx_usb_cancel_all(cvmx_usb_state_t *state, int pipe_handle)
     CVMX_USB_LOG_PARAM("%d", pipe_handle);
     if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     /* Fail if the pipe isn't open */
     if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
@@ -2524,6 +2753,9 @@ cvmx_usb_status_t cvmx_usb_cancel_all(cvmx_usb_state_t *state, int pipe_handle)
     }
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_cancel_all);
+#endif
 
 
 /**
@@ -2548,8 +2780,6 @@ cvmx_usb_status_t cvmx_usb_close_pipe(cvmx_usb_state_t *state, int pipe_handle)
     CVMX_USB_LOG_PARAM("%d", pipe_handle);
     if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
         CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
 
     /* Fail if the pipe isn't open */
     if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
@@ -2565,6 +2795,9 @@ cvmx_usb_status_t cvmx_usb_close_pipe(cvmx_usb_state_t *state, int pipe_handle)
 
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_close_pipe);
+#endif
 
 
 /**
@@ -2601,6 +2834,9 @@ cvmx_usb_status_t cvmx_usb_register_callback(cvmx_usb_state_t *state,
 
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_register_callback);
+#endif
 
 
 /**
@@ -2616,25 +2852,19 @@ int cvmx_usb_get_frame_number(cvmx_usb_state_t *state)
 {
     int frame_number;
     cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    cvmx_usbcx_hfnum_t usbc_hfnum;
 
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", state);
 
-    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
-    {
-        cvmx_usbcx_dsts_t usbc_dsts;
-        usbc_dsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DSTS(usb->index));
-        frame_number = usbc_dsts.s.soffn;
-    }
-    else
-    {
-        cvmx_usbcx_hfnum_t usbc_hfnum;
-        usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
-        frame_number = usbc_hfnum.s.frnum;
-    }
+    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+    frame_number = usbc_hfnum.s.frnum;
 
     CVMX_USB_RETURN(frame_number);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_get_frame_number);
+#endif
 
 
 /**
@@ -2664,18 +2894,70 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
     /* Read the interrupt status bits for the channel */
     usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
 
-    /* We ignore any interrupts where the channel hasn't halted yet. These
-        should be impossible since we don't enable any interrupts except for
-        channel halted */
-    if (!usbc_hcint.s.chhltd)
-        CVMX_USB_RETURN(0);
+#if 0
+    cvmx_dprintf("Channel %d%s%s%s%s%s%s%s%s%s%s%s\n", channel,
+        (usbc_hcint.s.datatglerr) ? " DATATGLERR" : "",
+        (usbc_hcint.s.frmovrun) ? " FRMOVRUN" : "",
+        (usbc_hcint.s.bblerr) ? " BBLERR" : "",
+        (usbc_hcint.s.xacterr) ? " XACTERR" : "",
+        (usbc_hcint.s.nyet) ? " NYET" : "",
+        (usbc_hcint.s.ack) ? " ACK" : "",
+        (usbc_hcint.s.nak) ? " NAK" : "",
+        (usbc_hcint.s.stall) ? " STALL" : "",
+        (usbc_hcint.s.ahberr) ? " AHBERR" : "",
+        (usbc_hcint.s.chhltd) ? " CHHLTD" : "",
+        (usbc_hcint.s.xfercompl) ? " XFERCOMPL" : "");
+#endif
 
-    /* Now that the channel has halted, clear all status bits before
-        processing. This way we don't have any race conditions caused by the
-        channel starting up and finishing before we clear the bits */
-    __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
-    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
+    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+    {
+        usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
+
+        if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis)
+        {
+            /* There seems to be a bug in CN31XX which can cause interrupt
+                IN transfers to get stuck until we do a write of HCCHARX
+                without changing things */
+            __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
+            CVMX_USB_RETURN(0);
+        }
 
+        /* In non DMA mode the channels don't halt themselves. We need to
+            manually disable channels that are left running */
+        if (!usbc_hcint.s.chhltd)
+        {
+            if (usbc_hcchar.s.chena)
+            {
+                cvmx_usbcx_hcintmskx_t hcintmsk;
+                /* Disable all interrupts except CHHLTD */
+                hcintmsk.u32 = 0;
+                hcintmsk.s.chhltdmsk = 1;
+                __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
+                usbc_hcchar.s.chdis = 1;
+                __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
+                CVMX_USB_RETURN(0);
+            }
+            else if (usbc_hcint.s.xfercompl)
+            {
+                /* Successful IN/OUT with transfer complete. Channel halt isn't needed */
+            }
+            else
+            {
+                cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
+                CVMX_USB_RETURN(0);
+            }
+        }
+    }
+    else
+    {
+        /* There is are no interrupts that we need to process when the channel is
+            still running */
+        if (!usbc_hcint.s.chhltd)
+            CVMX_USB_RETURN(0);
+    }
+
+    /* Disable the channel interrupts now that it is done */
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
     usb->idle_hardware_channels |= (1<<channel);
 
     /* Make sure this channel is tied to a valid pipe */
@@ -2697,7 +2979,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
     usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
     usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
 
-    /* Calculating the number of bytes successfully transfered is dependent on
+    /* Calculating the number of bytes successfully transferred is dependent on
         the transfer direction */
     packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
     if (usbc_hcchar.s.epdir)
@@ -2728,7 +3010,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
 
     /* As a special case, setup transactions output the setup header, not
         the user's data. For this reason we don't count setup data as bytes
-        transfered */
+        transferred */
     if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
         (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
         bytes_this_transfer = 0;
@@ -2742,7 +3024,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                      __cvmx_usb_get_submit_handle(usb, transaction),
                      transaction->stage, bytes_this_transfer);
 
-    /* Add the bytes transfered to the running total. It is important that
+    /* Add the bytes transferred to the running total. It is important that
         bytes_this_transfer doesn't count any data that needs to be
         retransmitted */
     transaction->actual_bytes += bytes_this_transfer;
@@ -2767,15 +3049,11 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
     {
         /* STALL as a response means this transaction cannot be completed
             because the device can't process transactions. Tell the user. Any
-            data that was transfered will be counted on the actual bytes
-            transfered */
+            data that was transferred will be counted on the actual bytes
+            transferred */
         pipe->pid_toggle = 0;
         __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
     }
-    else if (0 && usbc_hcint.s.xfercompl)
-    {
-        /* XferCompl is only useful in non DMA mode */
-    }
     else if (usbc_hcint.s.xacterr)
     {
         /* We know at least one packet worked if we get a ACK or NAK. Reset the retry counter */
@@ -2790,29 +3068,28 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
         }
         else
         {
+            /* If this was a split then clear our split in progress marker */
+            if (usb->active_split == transaction)
+                usb->active_split = NULL;
             /* Rewind to the beginning of the transaction by anding off the
                 split complete bit */
             transaction->stage &= ~1;
             pipe->split_sc_frame = -1;
-            pipe->next_tx_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT) + pipe->interval;
+            pipe->next_tx_frame += pipe->interval;
+            if (pipe->next_tx_frame < usb->frame_number)
+                pipe->next_tx_frame = usb->frame_number + pipe->interval -
+                    (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
         }
     }
-    else if (0 && usbc_hcint.s.datatglerr)
-    {
-        /* The hardware automatically handles Data Toggle Errors for us */
-    }
     else if (usbc_hcint.s.bblerr)
     {
         /* Babble Error (BblErr) */
         __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
     }
-    else if (usbc_hcint.s.frmovrun)
+    else if (usbc_hcint.s.datatglerr)
     {
-        /* Frame Overrun (FrmOvrun) */
-        /* Rewind to the beginning of the transaction by anding off the
-            split complete bit */
-        transaction->stage &= ~1;
-        pipe->split_sc_frame = -1;
+        /* We'll retry the exact same transaction again */
+        transaction->retries++;
     }
     else if (usbc_hcint.s.nyet)
     {
@@ -2890,7 +3167,19 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                         break;
                     case CVMX_USB_STAGE_DATA:
                         if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                        {
                             transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
+                            /* For setup OUT data that are splits, the hardware
+                                doesn't appear to count transferred data. Here
+                                we manually update the data transferred */
+                            if (!usbc_hcchar.s.epdir)
+                            {
+                                if (buffer_space_left < pipe->max_packet)
+                                    transaction->actual_bytes += buffer_space_left;
+                                else
+                                    transaction->actual_bytes += pipe->max_packet;
+                            }
+                        }
                         else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
                         {
                             pipe->pid_toggle = 1;
@@ -2936,7 +3225,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                         else
                         {
                             if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
-                                pipe->next_tx_cycle += pipe->interval;
+                                pipe->next_tx_frame += pipe->interval;
                             __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
                         }
                     }
@@ -2951,7 +3240,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                     if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet))
                     {
                         if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
-                            pipe->next_tx_cycle += pipe->interval;
+                            pipe->next_tx_frame += pipe->interval;
                         __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
                     }
                 }
@@ -2965,23 +3254,25 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                         the pipe sleeps until the next schedule interval */
                     if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)
                     {
-                        pipe->next_tx_cycle += pipe->interval;
                         /* If no space left or this wasn't a max size packet then
                             this transfer is complete. Otherwise start it again
                             to send the next 188 bytes */
                         if (!buffer_space_left || (bytes_this_transfer < 188))
+                        {
+                            pipe->next_tx_frame += pipe->interval;
                             __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                        }
                     }
                     else
                     {
                         if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE)
                         {
-                            /* We are in the incomming data phase. Keep getting
+                            /* We are in the incoming data phase. Keep getting
                                 data until we run out of space or get a small
                                 packet */
                             if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
                             {
-                                pipe->next_tx_cycle += pipe->interval;
+                                pipe->next_tx_frame += pipe->interval;
                                 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
                             }
                         }
@@ -2991,7 +3282,7 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
                 }
                 else
                 {
-                    pipe->next_tx_cycle += pipe->interval;
+                    pipe->next_tx_frame += pipe->interval;
                     __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
                 }
                 break;
@@ -2999,205 +3290,36 @@ static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
     }
     else if (usbc_hcint.s.nak)
     {
-        uint64_t ipd_clk_count;
+        /* If this was a split then clear our split in progress marker */
+        if (usb->active_split == transaction)
+            usb->active_split = NULL;
         /* NAK as a response means the device couldn't accept the transaction,
             but it should be retried in the future. Rewind to the beginning of
             the transaction by anding off the split complete bit. Retry in the
             next interval */
         transaction->retries = 0;
         transaction->stage &= ~1;
-        pipe->next_tx_cycle += pipe->interval;
-        ipd_clk_count = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
-        if (pipe->next_tx_cycle < ipd_clk_count)
-            pipe->next_tx_cycle = ipd_clk_count + pipe->interval;
+        pipe->next_tx_frame += pipe->interval;
+        if (pipe->next_tx_frame < usb->frame_number)
+            pipe->next_tx_frame = usb->frame_number + pipe->interval -
+                (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
     }
     else
     {
-        /* We get channel halted interrupts with no result bits sets when the
-            cable is unplugged */
-        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
-    }
-    CVMX_USB_RETURN(0);
-}
-
-
-/**
- * Poll a device mode endpoint for status
- *
- * @param usb    USB device state populated by
- *               cvmx_usb_initialize().
- * @param endpoint_num
- *               Endpoint to poll
- *
- * @return Zero on success
- */
-static int __cvmx_usb_poll_endpoint(cvmx_usb_internal_state_t *usb, int endpoint_num)
-{
-    cvmx_usbcx_diepintx_t usbc_diepint;
-    cvmx_usbcx_doepintx_t usbc_doepint;
-
-    CVMX_USB_LOG_CALLED();
-    CVMX_USB_LOG_PARAM("%p", usb);
-    CVMX_USB_LOG_PARAM("%d", endpoint_num);
-
-    usbc_diepint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index));
-    __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index), usbc_diepint.u32);
-    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_DIEPINTX(endpoint_num, usb->index), usbc_diepint.u32);
-    if (usbc_diepint.s.inepnakeff)
-    {
-        /* IN Endpoint NAK Effective (INEPNakEff)
-            Applies to periodic IN endpoints only.
-            Indicates that the IN endpoint NAK bit set by the application has
-            taken effect in the core. This bit can be cleared when the
-            application clears the IN endpoint NAK by writing to
-            DIEPCTLn.CNAK.
-            This interrupt indicates that the core has sampled the NAK bit
-            set (either by the application or by the core).
-            This interrupt does not necessarily mean that a NAK handshake
-            is sent on the USB. A STALL bit takes priority over a NAK bit. */
-        /* Nothing to do */
-    }
-    if (usbc_diepint.s.intknepmis)
-    {
-        /* IN Token Received with EP Mismatch (INTknEPMis)
-            Applies to non-periodic IN endpoints only.
-            Indicates that the data in the top of the non-periodic TxFIFO
-            belongs to an endpoint other than the one for which the IN
-            token was received. This interrupt is asserted on the endpoint
-            for which the IN token was received. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: Endpoint %d mismatch\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_diepint.s.intkntxfemp)
-    {
-        /* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-            Applies only to non-periodic IN endpoints.
-            Indicates that an IN token was received when the associated
-            TxFIFO (periodic/non-periodic) was empty. This interrupt is
-            asserted on the endpoint for which the IN token was received. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: Received IN token on endpoint %d without data\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_diepint.s.timeout)
-    {
-        /* Timeout Condition (TimeOUT)
-            Applies to non-isochronous IN endpoints only.
-            Indicates that the core has detected a timeout condition on the
-            USB for the last IN token on this endpoint. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: Received timeout on endpoint %d\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_diepint.s.ahberr)
-    {
-        /* AHB Error (AHBErr)
-            This is generated only in Internal DMA mode when there is an
-            AHB error during an AHB read/write. The application can read
-            the corresponding endpoint DMA address register to get the
-            error address. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: AHB error on endpoint %d\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_diepint.s.epdisbld)
-    {
-        /* Endpoint Disabled Interrupt (EPDisbld)
-            This bit indicates that the endpoint is disabled per the
-            application's request. */
-        /* Nothing to do */
-    }
-    if (usbc_diepint.s.xfercompl)
-    {
-        /* Transfer Completed Interrupt (XferCompl)
-            Indicates that the programmed transfer is complete on the AHB
-            as well as on the USB, for this endpoint. */
-        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
-                                    CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
-                                    CVMX_USB_COMPLETE_SUCCESS);
-    }
-
-    usbc_doepint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index));
-    __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index), usbc_doepint.u32);
-    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_DOEPINTX(endpoint_num, usb->index), usbc_doepint.u32);
-    if (usbc_doepint.s.outtknepdis)
-    {
-        /* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-            Applies only to control OUT endpoints.
-            Indicates that an OUT token was received when the endpoint
-            was not yet enabled. This interrupt is asserted on the endpoint
-            for which the OUT token was received. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: Received OUT token on disabled endpoint %d\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_doepint.s.setup)
-    {
-        /* SETUP Phase Done (SetUp)
-            Applies to control OUT endpoints only.
-            Indicates that the SETUP phase for the control endpoint is
-            complete and no more back-to-back SETUP packets were
-            received for the current control transfer. On this interrupt, the
-            application can decode the received SETUP data packet. */
-        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
-                                    CVMX_USB_CALLBACK_DEVICE_SETUP,
-                                    CVMX_USB_COMPLETE_SUCCESS);
-    }
-    if (usbc_doepint.s.ahberr)
-    {
-        /* AHB Error (AHBErr)
-            This is generated only in Internal DMA mode when there is an
-            AHB error during an AHB read/write. The application can read
-            the corresponding endpoint DMA address register to get the
-            error address. */
-        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-            cvmx_dprintf("%s: AHB error on endpoint %d\n", __FUNCTION__, endpoint_num);
-    }
-    if (usbc_doepint.s.epdisbld)
-    {
-        /* Endpoint Disabled Interrupt (EPDisbld)
-            This bit indicates that the endpoint is disabled per the
-            application's request. */
-        /* Nothing to do */
-    }
-    if (usbc_doepint.s.xfercompl)
-    {
-        /* Transfer Completed Interrupt (XferCompl)
-            Indicates that the programmed transfer is complete on the AHB
-            as well as on the USB, for this endpoint. */
-        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
-                                    CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
-                                    CVMX_USB_COMPLETE_SUCCESS);
-    }
-
-    CVMX_USB_RETURN(0);
-}
-
-
-/**
- * Poll the device mode endpoints for status
- *
- * @param usb  USB device state populated by
- *               cvmx_usb_initialize().
- *
- * @return Zero on success
- */
-static int __cvmx_usb_poll_endpoints(cvmx_usb_internal_state_t *usb)
-{
-    cvmx_usbcx_daint_t usbc_daint;
-    int active_endpoints;
-
-    CVMX_USB_LOG_CALLED();
-    CVMX_USB_LOG_PARAM("%p", usb);
-
-    usbc_daint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DAINT(usb->index));
-    active_endpoints = usbc_daint.s.inepint | usbc_daint.s.outepint;
-
-    while (active_endpoints)
-    {
-        int endpoint;
-        CVMX_CLZ(endpoint, active_endpoints);
-        endpoint = 31 - endpoint;
-        __cvmx_usb_poll_endpoint(usb, endpoint);
-        active_endpoints ^= 1<<endpoint;
+        cvmx_usb_port_status_t port;
+        port = cvmx_usb_get_status((cvmx_usb_state_t *)usb);
+        if (port.port_enabled)
+        {
+            /* We'll retry the exact same transaction again */
+            transaction->retries++;
+        }
+        else
+        {
+            /* We get channel halted interrupts with no result bits sets when the
+                cable is unplugged */
+            __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
+        }
     }
-
     CVMX_USB_RETURN(0);
 }
 
@@ -3216,6 +3338,7 @@ static int __cvmx_usb_poll_endpoints(cvmx_usb_internal_state_t *usb)
  */
 cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state)
 {
+    cvmx_usbcx_hfnum_t usbc_hfnum;
     cvmx_usbcx_gintsts_t usbc_gintsts;
     cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
 
@@ -3228,24 +3351,33 @@ cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state)
     CVMX_USB_LOG_CALLED();
     CVMX_USB_LOG_PARAM("%p", state);
 
+    /* Update the frame counter */
+    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+    if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
+        usb->frame_number += 0x4000;
+    usb->frame_number &= ~0x3fffull;
+    usb->frame_number |= usbc_hfnum.s.frnum;
+
     /* Read the pending interrupts */
     usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
 
-    if (usbc_gintsts.s.wkupint)
+    /* Clear the interrupts now that we know about them */
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
+
+    if (usbc_gintsts.s.rxflvl)
     {
-        /* Resume/Remote Wakeup Detected Interrupt (WkUpInt)
-            In Device mode, this interrupt is asserted when a resume is
-            detected on the USB. In Host mode, this interrupt is asserted
-            when a remote wakeup is detected on the USB. */
-        /* Octeon doesn't support suspend / resume */
+        /* RxFIFO Non-Empty (RxFLvl)
+            Indicates that there is at least one packet pending to be read
+            from the RxFIFO. */
+        /* In DMA mode this is handled by hardware */
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+            __cvmx_usb_poll_rx_fifo(usb);
     }
-    if (usbc_gintsts.s.sessreqint)
+    if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp)
     {
-        /* Session Request/New Session Detected Interrupt (SessReqInt)
-            In Host mode, this interrupt is asserted when a session request
-            is detected from the device. In Device mode, this interrupt is
-            asserted when the utmiotg_bvalid signal goes high. */
-        /* Octeon doesn't support OTG */
+        /* Fill the Tx FIFOs when not in DMA mode */
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
+            __cvmx_usb_poll_tx_fifo(usb);
     }
     if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint)
     {
@@ -3270,25 +3402,6 @@ cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state)
         usbc_hprt.s.prtena = 0;
         __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
     }
-    if (usbc_gintsts.s.conidstschng)
-    {
-        /* Connector ID Status Change (ConIDStsChng)
-            The core sets this bit when there is a change in connector ID
-            status. */
-        /* The USB core currently doesn't support dynamically changing from
-            host to device mode */
-    }
-    if (usbc_gintsts.s.ptxfemp)
-    {
-        /* Periodic TxFIFO Empty (PTxFEmp)
-            Asserted when the Periodic Transmit FIFO is either half or
-            completely empty and there is space for at least one entry to be
-            written in the Periodic Request Queue. The half or completely
-            empty status is determined by the Periodic TxFIFO Empty Level
-            bit in the Core AHB Configuration register
-            (GAHBCFG.PTxFEmpLvl). */
-        /* In DMA mode we don't care */
-    }
     if (usbc_gintsts.s.hchint)
     {
         /* Host Channels Interrupt (HChInt)
@@ -3311,342 +3424,14 @@ cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state)
             usbc_haint.u32 ^= 1<<channel;
         }
     }
-    if (usbc_gintsts.s.fetsusp)
-    {
-        /* Data Fetch Suspended (FetSusp)
-            This interrupt is valid only in DMA mode. This interrupt indicates
-            that the core has stopped fetching data for IN endpoints due to
-            the unavailability of TxFIFO space or Request Queue space.
-            This interrupt is used by the application for an endpoint
-            mismatch algorithm. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.incomplp)
-    {
-        /* Incomplete Periodic Transfer (incomplP)
-            In Host mode, the core sets this interrupt bit when there are
-            incomplete periodic transactions still pending which are
-            scheduled for the current microframe.
-            Incomplete Isochronous OUT Transfer (incompISOOUT)
-            The Device mode, the core sets this interrupt to indicate that
-            there is at least one isochronous OUT endpoint on which the
-            transfer is not completed in the current microframe. This
-            interrupt is asserted along with the End of Periodic Frame
-            Interrupt (EOPF) bit in this register. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.incompisoin)
-    {
-        /* Incomplete Isochronous IN Transfer (incompISOIN)
-            The core sets this interrupt to indicate that there is at least one
-            isochronous IN endpoint on which the transfer is not completed
-            in the current microframe. This interrupt is asserted along with
-            the End of Periodic Frame Interrupt (EOPF) bit in this register. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.oepint)
-    {
-        /* OUT Endpoints Interrupt (OEPInt)
-            The core sets this bit to indicate that an interrupt is pending on
-            one of the OUT endpoints of the core (in Device mode). The
-            application must read the Device All Endpoints Interrupt
-            (DAINT) register to determine the exact number of the OUT
-            endpoint on which the interrupt occurred, and then read the
-            corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
-            register to determine the exact cause of the interrupt. The
-            application must clear the appropriate status bit in the
-            corresponding DOEPINTn register to clear this bit. */
-        __cvmx_usb_poll_endpoints(usb);
-    }
-    if (usbc_gintsts.s.iepint)
-    {
-        /* IN Endpoints Interrupt (IEPInt)
-            The core sets this bit to indicate that an interrupt is pending on
-            one of the IN endpoints of the core (in Device mode). The
-            application must read the Device All Endpoints Interrupt
-            (DAINT) register to determine the exact number of the IN
-            endpoint on which the interrupt occurred, and then read the
-            corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
-            register to determine the exact cause of the interrupt. The
-            application must clear the appropriate status bit in the
-            corresponding DIEPINTn register to clear this bit. */
-        __cvmx_usb_poll_endpoints(usb);
-    }
-    if (usbc_gintsts.s.epmis)
-    {
-        /* Endpoint Mismatch Interrupt (EPMis)
-            Indicates that an IN token has been received for a non-periodic
-            endpoint, but the data for another endpoint is present in the top
-            of the Non-Periodic Transmit FIFO and the IN endpoint
-            mismatch count programmed by the application has expired. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.eopf)
-    {
-        /* End of Periodic Frame Interrupt (EOPF)
-            Indicates that the period specified in the Periodic Frame Interval
-            field of the Device Configuration register (DCFG.PerFrInt) has
-            been reached in the current microframe. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.isooutdrop)
-    {
-        /* Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
-            The core sets this bit when it fails to write an isochronous OUT
-            packet into the RxFIFO because the RxFIFO doesn't have
-            enough space to accommodate a maximum packet size packet
-            for the isochronous OUT endpoint. */
-        // FIXME
-    }
-    if (usbc_gintsts.s.enumdone)
-    {
-        /* Enumeration Done (EnumDone)
-            The core sets this bit to indicate that speed enumeration is
-            complete. The application must read the Device Status (DSTS)
-            register to obtain the enumerated speed. */
-        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
-        {
-            cvmx_usbcx_dsts_t usbc_dsts;
-            usbc_dsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DSTS(usb->index));
-            if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-                cvmx_dprintf("%s: USB%d Enumeration complete with %s speed\n",
-                             __FUNCTION__, usb->index,
-                             (usbc_dsts.s.enumspd == CVMX_USB_SPEED_HIGH) ? "high" :
-                             (usbc_dsts.s.enumspd == CVMX_USB_SPEED_FULL) ? "full" :
-                             "low");
-            USB_SET_FIELD32(CVMX_USBCX_DIEPCTLX(0, usb->index),
-                            cvmx_usbcx_diepctlx_t, mps,
-                            (usbc_dsts.s.enumspd == CVMX_USB_SPEED_LOW) ? 3 : 0);
-            USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(0, usb->index),
-                            cvmx_usbcx_doepctlx_t, epena, 1);
-        }
-    }
-    if (usbc_gintsts.s.usbrst)
-    {
-        /* USB Reset (USBRst)
-            The core sets this bit to indicate that a reset is
-            detected on the USB. */
-        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
-        {
-            if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
-                cvmx_dprintf("%s: USB%d Reset complete\n", __FUNCTION__, usb->index);
-            __cvmx_usb_device_reset_complete(usb);
-        }
-    }
-    if (usbc_gintsts.s.nptxfemp)
-    {
-        /* Non-Periodic TxFIFO Empty (NPTxFEmp)
-            This interrupt is asserted when the Non-Periodic TxFIFO is
-            either half or completely empty, and there is space for at least
-            one entry to be written to the Non-Periodic Transmit Request
-            Queue. The half or completely empty status is determined by
-            the Non-Periodic TxFIFO Empty Level bit in the Core AHB
-            Configuration register (GAHBCFG.NPTxFEmpLvl). */
-        /* In DMA mode this is handled by hardware */
-    }
-    if (usbc_gintsts.s.rxflvl)
-    {
-        /* RxFIFO Non-Empty (RxFLvl)
-            Indicates that there is at least one packet pending to be read
-            from the RxFIFO. */
-        /* In DMA mode this is handled by hardware */
-    }
-    if (usbc_gintsts.s.sof)
-    {
-        /* Start of (micro)Frame (Sof)
-            In Host mode, the core sets this bit to indicate that an SOF
-            (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
-            USB. The application must write a 1 to this bit to clear the
-            interrupt.
-            In Device mode, in the core sets this bit to indicate that an SOF
-            token has been received on the USB. The application can read
-            the Device Status register to get the current (micro)frame
-            number. This interrupt is seen only when the core is operating
-            at either HS or FS. */
-    }
-    if (usbc_gintsts.s.otgint)
-    {
-        /* OTG Interrupt (OTGInt)
-            The core sets this bit to indicate an OTG protocol event. The
-            application must read the OTG Interrupt Status (GOTGINT)
-            register to determine the exact event that caused this interrupt.
-            The application must clear the appropriate status bit in the
-            GOTGINT register to clear this bit. */
-        /* Octeon doesn't support OTG, so ignore */
-    }
-    if (usbc_gintsts.s.modemis)
-    {
-        /* Mode Mismatch Interrupt (ModeMis)
-            The core sets this bit when the application is trying to access:
-            * A Host mode register, when the core is operating in Device
-            mode
-            * A Device mode register, when the core is operating in Host
-            mode
-            The register access is completed on the AHB with an OKAY
-            response, but is ignored by the core internally and doesn't
-            affect the operation of the core. */
-        /* Ignored for now */
-    }
 
     __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
 
-    /* Clear the interrupts now that we know about them */
-    __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
-
-    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
-}
-
-
-/**
- * Enable an endpoint for use in device mode. After this call
- * transactions will be allowed over the endpoint. This must be
- * called after every usb reset.
- *
- * @param state  USB device state populated by
- *               cvmx_usb_initialize().
- * @param endpoint_num
- *               The endpoint number to enable (0-4)
- * @param transfer_type
- *               USB transfer type of this endpoint
- * @param transfer_dir
- *               Direction of transfer relative to Octeon
- * @param max_packet_size
- *               Maximum packet size support by this endpoint
- * @param buffer Buffer to send/receive
- * @param buffer_length
- *               Length of the buffer in bytes
- *
- * @return CVMX_USB_SUCCESS or a negative error code defined in
- *         cvmx_usb_status_t.
- */
-cvmx_usb_status_t cvmx_usb_device_enable_endpoint(cvmx_usb_state_t *state,
-                                                  int endpoint_num,
-                                                  cvmx_usb_transfer_t transfer_type,
-                                                  cvmx_usb_direction_t transfer_dir,
-                                                  int max_packet_size,
-                                                  uint64_t buffer,
-                                                  int buffer_length)
-{
-    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
-
-    CVMX_USB_LOG_CALLED();
-    CVMX_USB_LOG_PARAM("%p", state);
-    CVMX_USB_LOG_PARAM("%d", endpoint_num);
-    CVMX_USB_LOG_PARAM("%d", transfer_type);
-    CVMX_USB_LOG_PARAM("%d", transfer_dir);
-    CVMX_USB_LOG_PARAM("%d", max_packet_size);
-    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
-    CVMX_USB_LOG_PARAM("%d", buffer_length);
-
-    if (cvmx_unlikely((endpoint_num < 0) || (endpoint_num > 4)))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
-        (transfer_dir != CVMX_USB_DIRECTION_IN)))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely((max_packet_size < 0) || (max_packet_size > 512)))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(!buffer))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely(buffer_length < 0))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
-
-    if (transfer_dir == CVMX_USB_DIRECTION_IN)
-    {
-        cvmx_usbcx_doepctlx_t usbc_doepctl;
-        cvmx_usbcx_doeptsizx_t usbc_doeptsiz;
-
-        /* Setup the locations the DMA engines use  */
-        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + endpoint_num*8, buffer);
-        usbc_doeptsiz.u32 = 0;
-        usbc_doeptsiz.s.mc = 1; // FIXME
-        usbc_doeptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
-        if (usbc_doeptsiz.s.pktcnt == 0)
-            usbc_doeptsiz.s.pktcnt = 1;
-        usbc_doeptsiz.s.xfersize = buffer_length;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPTSIZX(endpoint_num, usb->index), usbc_doeptsiz.u32);
-
-        usbc_doepctl.u32 = 0;
-        usbc_doepctl.s.epena = 1;
-        usbc_doepctl.s.setd1pid = 0; // FIXME
-        usbc_doepctl.s.setd0pid = 0; // FIXME
-        usbc_doepctl.s.cnak = 1;
-        usbc_doepctl.s.eptype = transfer_type;
-        usbc_doepctl.s.usbactep = 1;
-        usbc_doepctl.s.mps = max_packet_size;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index), usbc_doepctl.u32);
-    }
-    else
-    {
-        cvmx_usbcx_diepctlx_t usbc_diepctl;
-        cvmx_usbcx_dieptsizx_t usbc_dieptsiz;
-
-        /* Setup the locations the DMA engines use  */
-        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + endpoint_num*8, buffer);
-        usbc_dieptsiz.u32 = 0;
-        usbc_dieptsiz.s.mc = 1; // FIXME
-        usbc_dieptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
-        if (usbc_dieptsiz.s.pktcnt == 0)
-            usbc_dieptsiz.s.pktcnt = 1;
-        usbc_dieptsiz.s.xfersize = buffer_length;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPTSIZX(endpoint_num, usb->index), usbc_dieptsiz.u32);
-
-        usbc_diepctl.u32 = 0;
-        usbc_diepctl.s.epena = 1;
-        usbc_diepctl.s.setd1pid = 0; // FIXME
-        usbc_diepctl.s.setd0pid = 0; // FIXME
-        usbc_diepctl.s.cnak = 1;
-        if ((transfer_type == CVMX_USB_TRANSFER_INTERRUPT) ||
-            (transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS))
-            usbc_diepctl.s.txfnum = endpoint_num; // FIXME
-        else
-            usbc_diepctl.s.txfnum = 0;
-        usbc_diepctl.s.eptype = transfer_type;
-        usbc_diepctl.s.usbactep = 1;
-        usbc_diepctl.s.nextep = endpoint_num - 1; // FIXME
-        usbc_diepctl.s.mps = max_packet_size;
-        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index), usbc_diepctl.u32);
-    }
-
-    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
-}
-
-
-/**
- * Disable an endpoint in device mode.
- *
- * @param state  USB device state populated by
- *               cvmx_usb_initialize().
- * @param endpoint_num
- *               The endpoint number to disable (0-4)
- *
- * @return CVMX_USB_SUCCESS or a negative error code defined in
- *         cvmx_usb_status_t.
- */
-cvmx_usb_status_t cvmx_usb_device_disable_endpoint(cvmx_usb_state_t *state,
-                                                   int endpoint_num)
-{
-    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
-
-    CVMX_USB_LOG_CALLED();
-    CVMX_USB_LOG_PARAM("%p", state);
-    CVMX_USB_LOG_PARAM("%d", endpoint_num);
-
-    if (cvmx_unlikely((endpoint_num < 0) || (endpoint_num > 4)))
-        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
-    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0))
-        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
-
-    USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index),
-                    cvmx_usbcx_doepctlx_t, epdis, 1);
-    USB_SET_FIELD32(CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index),
-                    cvmx_usbcx_diepctlx_t, epdis, 1);
-
     CVMX_USB_RETURN(CVMX_USB_SUCCESS);
 }
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usb_poll);
+#endif
 
 extern void cvmx_usb_set_toggle(cvmx_usb_state_t *state, int endpoint_num, int toggle)
 {
@@ -3665,3 +3450,4 @@ extern int cvmx_usb_get_toggle(cvmx_usb_state_t *state, int endpoint_num)
 	    return (1);
     return (0);
 }
+
diff --git a/sys/contrib/octeon-sdk/cvmx-usb.h b/sys/contrib/octeon-sdk/cvmx-usb.h
index bc228ff..b6a3e4c 100644
--- a/sys/contrib/octeon-sdk/cvmx-usb.h
+++ b/sys/contrib/octeon-sdk/cvmx-usb.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  *
@@ -566,8 +568,6 @@ typedef enum
                                         plugged a device in. The status parameter contains
                                         CVMX_USB_COMPLETE_SUCCESS. Use cvmx_usb_get_status() to get
                                         the new port status. */
-    CVMX_USB_CALLBACK_DEVICE_SETUP, /**< This is called in device mode when a control channels receives
-                                        a setup header */
     __CVMX_USB_CALLBACK_END         /**< Do not use. Used internally for array bounds */
 } cvmx_usb_callback_t;
 
@@ -616,12 +616,12 @@ typedef enum
                                                             source at USB_XO. USB_XI should be tied to GND.*/
     CVMX_USB_INITIALIZE_FLAGS_CLOCK_AUTO = 0,           /**< Automatically determine clock type based on function
                                                              in cvmx-helper-board.c. */
-    CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE = 1<<2,       /**< Program the USB port for device mode instead of host mode */
     CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK  = 3<<3,       /**< Mask for clock speed field */
     CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1<<3,       /**< Speed of reference clock or crystal */
     CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2<<3,       /**< Speed of reference clock */
     CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3<<3,       /**< Speed of reference clock */
     /* Bits 3-4 used to encode the clock frequency */
+    CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1<<5,            /**< Disable DMA and used polled IO for data transfer use for the USB  */
     CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS = 1<<16,  /**< Enable extra console output for debugging USB transfers */
     CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLBACKS = 1<<17,  /**< Enable extra console output for debugging USB callbacks */
     CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO = 1<<18,       /**< Enable extra console output for USB informational data */
@@ -767,7 +767,7 @@ extern void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t
  * @param max_packet The maximum packet length the device can
  *                   transmit/receive (low speed=0-8, full
  *                   speed=0-1023, high speed=0-1024). This value
- *                   comes from the stadnard endpoint descriptor
+ *                   comes from the standard endpoint descriptor
  *                   field wMaxPacketSize bits <10:0>.
  * @param transfer_type
  *                   The type of transfer this pipe is for.
@@ -783,7 +783,7 @@ extern void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t
  *                   For high speed devices, this is the maximum
  *                   allowed number of packet per microframe.
  *                   Specify zero for non high speed devices. This
- *                   value comes from the stadnard endpoint descriptor
+ *                   value comes from the standard endpoint descriptor
  *                   field wMaxPacketSize bits <12:11>.
  * @param hub_device_addr
  *                   Hub device address this device is connected
@@ -1078,50 +1078,6 @@ extern int cvmx_usb_get_frame_number(cvmx_usb_state_t *state);
  */
 extern cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state);
 
-/**
- * Enable an endpoint for use in device mode. After this call
- * transactions will be allowed over the endpoint. This must be
- * called after every usb reset.
- *
- * @param state  USB device state populated by
- *               cvmx_usb_initialize().
- * @param endpoint_num
- *               The endpoint number to enable (0-4)
- * @param transfer_type
- *               USB transfer type of this endpoint
- * @param transfer_dir
- *               Direction of transfer relative to Octeon
- * @param max_packet_size
- *               Maximum packet size support by this endpoint
- * @param buffer Buffer to send/receive
- * @param buffer_length
- *               Length of the buffer in bytes
- *
- * @return CVMX_USB_SUCCESS or a negative error code defined in
- *         cvmx_usb_status_t.
- */
-extern cvmx_usb_status_t cvmx_usb_device_enable_endpoint(cvmx_usb_state_t *state,
-                                                  int endpoint_num,
-                                                  cvmx_usb_transfer_t transfer_type,
-                                                  cvmx_usb_direction_t transfer_dir,
-                                                  int max_packet_size,
-                                                  uint64_t buffer,
-                                                  int buffer_length);
-
-/**
- * Disable an endpoint in device mode.
- *
- * @param state  USB device state populated by
- *               cvmx_usb_initialize().
- * @param endpoint_num
- *               The endpoint number to disable (0-4)
- *
- * @return CVMX_USB_SUCCESS or a negative error code defined in
- *         cvmx_usb_status_t.
- */
-extern cvmx_usb_status_t cvmx_usb_device_disable_endpoint(cvmx_usb_state_t *state,
-                                                          int endpoint_num);
-
 /*
  * The FreeBSD host driver uses these functions to manipulate the toggle to deal
  * more easily with endpoint management.
diff --git a/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h b/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
new file mode 100644
index 0000000..03dd07d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
@@ -0,0 +1,4359 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-usbcx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon usbcx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_USBCX_TYPEDEFS_H__
+#define __CVMX_USBCX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4;
+}
+#else
+#define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
+}
+#else
+#define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0))))))
+		cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096;
+}
+#else
+#define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+
+/**
+ * cvmx_usbc#_daint
+ *
+ * Device All Endpoints Interrupt Register (DAINT)
+ *
+ * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register
+ * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints
+ * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively).
+ * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
+ * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt
+ * bits are used. Bits in this register are set and cleared when the application sets and clears
+ * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
+ */
+union cvmx_usbcx_daint
+{
+	uint32_t u32;
+	struct cvmx_usbcx_daint_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t outepint                     : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt)
+                                                         One bit per OUT endpoint:
+                                                         Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
+	uint32_t inepint                      : 16; /**< IN Endpoint Interrupt Bits (InEpInt)
+                                                         One bit per IN Endpoint:
+                                                         Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */
+#else
+	uint32_t inepint                      : 16;
+	uint32_t outepint                     : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_daint_s             cn30xx;
+	struct cvmx_usbcx_daint_s             cn31xx;
+	struct cvmx_usbcx_daint_s             cn50xx;
+	struct cvmx_usbcx_daint_s             cn52xx;
+	struct cvmx_usbcx_daint_s             cn52xxp1;
+	struct cvmx_usbcx_daint_s             cn56xx;
+	struct cvmx_usbcx_daint_s             cn56xxp1;
+};
+typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t;
+
+/**
+ * cvmx_usbc#_daintmsk
+ *
+ * Device All Endpoints Interrupt Mask Register (DAINTMSK)
+ *
+ * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register
+ * to interrupt the application when an event occurs on a device endpoint. However, the Device
+ * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
+ * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
+ */
+union cvmx_usbcx_daintmsk
+{
+	uint32_t u32;
+	struct cvmx_usbcx_daintmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t outepmsk                     : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk)
+                                                         One per OUT Endpoint:
+                                                         Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
+	uint32_t inepmsk                      : 16; /**< IN EP Interrupt Mask Bits (InEpMsk)
+                                                         One bit per IN Endpoint:
+                                                         Bit 0 for IN EP 0, bit 15 for IN EP 15 */
+#else
+	uint32_t inepmsk                      : 16;
+	uint32_t outepmsk                     : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_daintmsk_s          cn30xx;
+	struct cvmx_usbcx_daintmsk_s          cn31xx;
+	struct cvmx_usbcx_daintmsk_s          cn50xx;
+	struct cvmx_usbcx_daintmsk_s          cn52xx;
+	struct cvmx_usbcx_daintmsk_s          cn52xxp1;
+	struct cvmx_usbcx_daintmsk_s          cn56xx;
+	struct cvmx_usbcx_daintmsk_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t;
+
+/**
+ * cvmx_usbc#_dcfg
+ *
+ * Device Configuration Register (DCFG)
+ *
+ * This register configures the core in Device mode after power-on or after certain control
+ * commands or enumeration. Do not make changes to this register after initial programming.
+ */
+union cvmx_usbcx_dcfg
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_23_31               : 9;
+	uint32_t epmiscnt                     : 5;  /**< IN Endpoint Mismatch Count (EPMisCnt)
+                                                         The application programs this filed with a count that determines
+                                                         when the core generates an Endpoint Mismatch interrupt
+                                                         (GINTSTS.EPMis). The core loads this value into an internal
+                                                         counter and decrements it. The counter is reloaded whenever
+                                                         there is a match or when the counter expires. The width of this
+                                                         counter depends on the depth of the Token Queue. */
+	uint32_t reserved_13_17               : 5;
+	uint32_t perfrint                     : 2;  /**< Periodic Frame Interval (PerFrInt)
+                                                         Indicates the time within a (micro)frame at which the application
+                                                         must be notified using the End Of Periodic Frame Interrupt. This
+                                                         can be used to determine if all the isochronous traffic for that
+                                                         (micro)frame is complete.
+                                                         * 2'b00: 80% of the (micro)frame interval
+                                                         * 2'b01: 85%
+                                                         * 2'b10: 90%
+                                                         * 2'b11: 95% */
+	uint32_t devaddr                      : 7;  /**< Device Address (DevAddr)
+                                                         The application must program this field after every SetAddress
+                                                         control command. */
+	uint32_t reserved_3_3                 : 1;
+	uint32_t nzstsouthshk                 : 1;  /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
+                                                         The application can use this field to select the handshake the
+                                                         core sends on receiving a nonzero-length data packet during
+                                                         the OUT transaction of a control transfer's Status stage.
+                                                         * 1'b1: Send a STALL handshake on a nonzero-length status
+                                                                 OUT transaction and do not send the received OUT packet to
+                                                                 the application.
+                                                         * 1'b0: Send the received OUT packet to the application (zero-
+                                                                 length or nonzero-length) and send a handshake based on
+                                                                 the NAK and STALL bits for the endpoint in the Device
+                                                                 Endpoint Control register. */
+	uint32_t devspd                       : 2;  /**< Device Speed (DevSpd)
+                                                         Indicates the speed at which the application requires the core to
+                                                         enumerate, or the maximum speed the application can support.
+                                                         However, the actual bus speed is determined only after the
+                                                         chirp sequence is completed, and is based on the speed of the
+                                                         USB host to which the core is connected. See "Device
+                                                         Initialization" on page 249 for details.
+                                                         * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
+                                                         * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
+                                                         * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
+                                                                  you select 6 MHz LS mode, you must do a soft reset.
+                                                         * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */
+#else
+	uint32_t devspd                       : 2;
+	uint32_t nzstsouthshk                 : 1;
+	uint32_t reserved_3_3                 : 1;
+	uint32_t devaddr                      : 7;
+	uint32_t perfrint                     : 2;
+	uint32_t reserved_13_17               : 5;
+	uint32_t epmiscnt                     : 5;
+	uint32_t reserved_23_31               : 9;
+#endif
+	} s;
+	struct cvmx_usbcx_dcfg_s              cn30xx;
+	struct cvmx_usbcx_dcfg_s              cn31xx;
+	struct cvmx_usbcx_dcfg_s              cn50xx;
+	struct cvmx_usbcx_dcfg_s              cn52xx;
+	struct cvmx_usbcx_dcfg_s              cn52xxp1;
+	struct cvmx_usbcx_dcfg_s              cn56xx;
+	struct cvmx_usbcx_dcfg_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t;
+
+/**
+ * cvmx_usbc#_dctl
+ *
+ * Device Control Register (DCTL)
+ *
+ */
+union cvmx_usbcx_dctl
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_12_31               : 20;
+	uint32_t pwronprgdone                 : 1;  /**< Power-On Programming Done (PWROnPrgDone)
+                                                         The application uses this bit to indicate that register
+                                                         programming is completed after a wake-up from Power Down
+                                                         mode. For more information, see "Device Mode Suspend and
+                                                         Resume With Partial Power-Down" on page 357. */
+	uint32_t cgoutnak                     : 1;  /**< Clear Global OUT NAK (CGOUTNak)
+                                                         A write to this field clears the Global OUT NAK. */
+	uint32_t sgoutnak                     : 1;  /**< Set Global OUT NAK (SGOUTNak)
+                                                         A write to this field sets the Global OUT NAK.
+                                                         The application uses this bit to send a NAK handshake on all
+                                                         OUT endpoints.
+                                                         The application should set the this bit only after making sure
+                                                         that the Global OUT NAK Effective bit in the Core Interrupt
+                                                         Register (GINTSTS.GOUTNakEff) is cleared. */
+	uint32_t cgnpinnak                    : 1;  /**< Clear Global Non-Periodic IN NAK (CGNPInNak)
+                                                         A write to this field clears the Global Non-Periodic IN NAK. */
+	uint32_t sgnpinnak                    : 1;  /**< Set Global Non-Periodic IN NAK (SGNPInNak)
+                                                         A write to this field sets the Global Non-Periodic IN NAK.The
+                                                         application uses this bit to send a NAK handshake on all non-
+                                                         periodic IN endpoints. The core can also set this bit when a
+                                                         timeout condition is detected on a non-periodic endpoint.
+                                                         The application should set this bit only after making sure that
+                                                         the Global IN NAK Effective bit in the Core Interrupt Register
+                                                         (GINTSTS.GINNakEff) is cleared. */
+	uint32_t tstctl                       : 3;  /**< Test Control (TstCtl)
+                                                         * 3'b000: Test mode disabled
+                                                         * 3'b001: Test_J mode
+                                                         * 3'b010: Test_K mode
+                                                         * 3'b011: Test_SE0_NAK mode
+                                                         * 3'b100: Test_Packet mode
+                                                         * 3'b101: Test_Force_Enable
+                                                         * Others: Reserved */
+	uint32_t goutnaksts                   : 1;  /**< Global OUT NAK Status (GOUTNakSts)
+                                                         * 1'b0: A handshake is sent based on the FIFO Status and the
+                                                                 NAK and STALL bit settings.
+                                                         * 1'b1: No data is written to the RxFIFO, irrespective of space
+                                                                 availability. Sends a NAK handshake on all packets, except
+                                                                 on SETUP transactions. All isochronous OUT packets are
+                                                                 dropped. */
+	uint32_t gnpinnaksts                  : 1;  /**< Global Non-Periodic IN NAK Status (GNPINNakSts)
+                                                         * 1'b0: A handshake is sent out based on the data availability
+                                                                 in the transmit FIFO.
+                                                         * 1'b1: A NAK handshake is sent out on all non-periodic IN
+                                                                 endpoints, irrespective of the data availability in the transmit
+                                                                 FIFO. */
+	uint32_t sftdiscon                    : 1;  /**< Soft Disconnect (SftDiscon)
+                                                         The application uses this bit to signal the O2P USB core to do a
+                                                         soft disconnect. As long as this bit is set, the host will not see
+                                                         that the device is connected, and the device will not receive
+                                                         signals on the USB. The core stays in the disconnected state
+                                                         until the application clears this bit.
+                                                         The minimum duration for which the core must keep this bit set
+                                                         is specified in Minimum Duration for Soft Disconnect  .
+                                                         * 1'b0: Normal operation. When this bit is cleared after a soft
+                                                         disconnect, the core drives the phy_opmode_o signal on the
+                                                         UTMI+ to 2'b00, which generates a device connect event to
+                                                         the USB host. When the device is reconnected, the USB host
+                                                         restarts device enumeration.
+                                                         * 1'b1: The core drives the phy_opmode_o signal on the
+                                                         UTMI+ to 2'b01, which generates a device disconnect event
+                                                         to the USB host. */
+	uint32_t rmtwkupsig                   : 1;  /**< Remote Wakeup Signaling (RmtWkUpSig)
+                                                         When the application sets this bit, the core initiates remote
+                                                         signaling to wake up the USB host.The application must set this
+                                                         bit to get the core out of Suspended state and must clear this bit
+                                                         after the core comes out of Suspended state. */
+#else
+	uint32_t rmtwkupsig                   : 1;
+	uint32_t sftdiscon                    : 1;
+	uint32_t gnpinnaksts                  : 1;
+	uint32_t goutnaksts                   : 1;
+	uint32_t tstctl                       : 3;
+	uint32_t sgnpinnak                    : 1;
+	uint32_t cgnpinnak                    : 1;
+	uint32_t sgoutnak                     : 1;
+	uint32_t cgoutnak                     : 1;
+	uint32_t pwronprgdone                 : 1;
+	uint32_t reserved_12_31               : 20;
+#endif
+	} s;
+	struct cvmx_usbcx_dctl_s              cn30xx;
+	struct cvmx_usbcx_dctl_s              cn31xx;
+	struct cvmx_usbcx_dctl_s              cn50xx;
+	struct cvmx_usbcx_dctl_s              cn52xx;
+	struct cvmx_usbcx_dctl_s              cn52xxp1;
+	struct cvmx_usbcx_dctl_s              cn56xx;
+	struct cvmx_usbcx_dctl_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t;
+
+/**
+ * cvmx_usbc#_diepctl#
+ *
+ * Device IN Endpoint-n Control Register (DIEPCTLn)
+ *
+ * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
+ */
+union cvmx_usbcx_diepctlx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_diepctlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t epena                        : 1;  /**< Endpoint Enable (EPEna)
+                                                         Indicates that data is ready to be transmitted on the endpoint.
+                                                         The core clears this bit before setting any of the following
+                                                         interrupts on this endpoint:
+                                                         * Endpoint Disabled
+                                                         * Transfer Completed */
+	uint32_t epdis                        : 1;  /**< Endpoint Disable (EPDis)
+                                                         The application sets this bit to stop transmitting data on an
+                                                         endpoint, even before the transfer for that endpoint is complete.
+                                                         The application must wait for the Endpoint Disabled interrupt
+                                                         before treating the endpoint as disabled. The core clears this bit
+                                                         before setting the Endpoint Disabled Interrupt. The application
+                                                         should set this bit only if Endpoint Enable is already set for this
+                                                         endpoint. */
+	uint32_t setd1pid                     : 1;  /**< For Interrupt/BULK enpoints:
+                                                          Set DATA1 PID (SetD1PID)
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA1.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetOddFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to odd (micro)frame. */
+	uint32_t setd0pid                     : 1;  /**< For Interrupt/BULK enpoints:
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA0.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetEvenFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to even (micro)frame. */
+	uint32_t snak                         : 1;  /**< Set NAK (SNAK)
+                                                         A write to this bit sets the NAK bit for the endpoint.
+                                                         Using this bit, the application can control the transmission of
+                                                         NAK handshakes on an endpoint. The core can also set this bit
+                                                         for an endpoint after a SETUP packet is received on the
+                                                         endpoint. */
+	uint32_t cnak                         : 1;  /**< Clear NAK (CNAK)
+                                                         A write to this bit clears the NAK bit for the endpoint. */
+	uint32_t txfnum                       : 4;  /**< TxFIFO Number (TxFNum)
+                                                         Non-periodic endpoints must set this bit to zero.  Periodic
+                                                         endpoints must map this to the corresponding Periodic TxFIFO
+                                                         number.
+                                                         * 4'h0: Non-Periodic TxFIFO
+                                                         * Others: Specified Periodic TxFIFO number */
+	uint32_t stall                        : 1;  /**< STALL Handshake (Stall)
+                                                         For non-control, non-isochronous endpoints:
+                                                          The application sets this bit to stall all tokens from the USB host
+                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
+                                                          Global OUT NAK is set along with this bit, the STALL bit takes
+                                                          priority.  Only the application can clear this bit, never the core.
+                                                         For control endpoints:
+                                                          The application can only set this bit, and the core clears it, when
+                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
+                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
+                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
+                                                          the core always responds to SETUP data packets with an ACK handshake. */
+	uint32_t reserved_20_20               : 1;
+	uint32_t eptype                       : 2;  /**< Endpoint Type (EPType)
+                                                         This is the transfer type supported by this logical endpoint.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+	uint32_t naksts                       : 1;  /**< NAK Status (NAKSts)
+                                                         Indicates the following:
+                                                         * 1'b0: The core is transmitting non-NAK handshakes based
+                                                                 on the FIFO status
+                                                         * 1'b1: The core is transmitting NAK handshakes on this
+                                                                 endpoint.
+                                                         When either the application or the core sets this bit:
+                                                         * For non-isochronous IN endpoints: The core stops
+                                                           transmitting any data on an IN endpoint, even if data is
+                                                           available in the TxFIFO.
+                                                         * For isochronous IN endpoints: The core sends out a zero-
+                                                           length data packet, even if data is available in the TxFIFO.
+                                                         Irrespective of this bit's setting, the core always responds to
+                                                         SETUP data packets with an ACK handshake. */
+	uint32_t dpid                         : 1;  /**< For interrupt/bulk IN and OUT endpoints:
+                                                          Endpoint Data PID (DPID)
+                                                          Contains the PID of the packet to be received or transmitted on
+                                                          this endpoint.  The application should program the PID of the first
+                                                          packet to be received or transmitted on this endpoint, after the
+                                                          endpoint is activated.  Applications use the SetD1PID and
+                                                          SetD0PID fields of this register to program either DATA0 or
+                                                          DATA1 PID.
+                                                          * 1'b0: DATA0
+                                                          * 1'b1: DATA1
+                                                         For isochronous IN and OUT endpoints:
+                                                          Even/Odd (Micro)Frame (EO_FrNum)
+                                                          Indicates the (micro)frame number in which the core transmits/
+                                                          receives isochronous data for this endpoint.  The application
+                                                          should program the even/odd (micro) frame number in which it
+                                                          intends to transmit/receive isochronous data for this endpoint
+                                                          using the SetEvnFr and SetOddFr fields in this register.
+                                                          * 1'b0: Even (micro)frame
+                                                          * 1'b1: Odd (micro)frame */
+	uint32_t usbactep                     : 1;  /**< USB Active Endpoint (USBActEP)
+                                                         Indicates whether this endpoint is active in the current
+                                                         configuration and interface.  The core clears this bit for all
+                                                         endpoints (other than EP 0) after detecting a USB reset.  After
+                                                         receiving the SetConfiguration and SetInterface commands, the
+                                                         application must program endpoint registers accordingly and set
+                                                         this bit. */
+	uint32_t nextep                       : 4;  /**< Next Endpoint (NextEp)
+                                                         Applies to non-periodic IN endpoints only.
+                                                         Indicates the endpoint number to be fetched after the data for
+                                                         the current endpoint is fetched. The core can access this field,
+                                                         even when the Endpoint Enable (EPEna) bit is not set. This
+                                                         field is not valid in Slave mode. */
+	uint32_t mps                          : 11; /**< Maximum Packet Size (MPS)
+                                                         Applies to IN and OUT endpoints.
+                                                         The application must program this field with the maximum
+                                                         packet size for the current logical endpoint.  This value is in
+                                                         bytes. */
+#else
+	uint32_t mps                          : 11;
+	uint32_t nextep                       : 4;
+	uint32_t usbactep                     : 1;
+	uint32_t dpid                         : 1;
+	uint32_t naksts                       : 1;
+	uint32_t eptype                       : 2;
+	uint32_t reserved_20_20               : 1;
+	uint32_t stall                        : 1;
+	uint32_t txfnum                       : 4;
+	uint32_t cnak                         : 1;
+	uint32_t snak                         : 1;
+	uint32_t setd0pid                     : 1;
+	uint32_t setd1pid                     : 1;
+	uint32_t epdis                        : 1;
+	uint32_t epena                        : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_diepctlx_s          cn30xx;
+	struct cvmx_usbcx_diepctlx_s          cn31xx;
+	struct cvmx_usbcx_diepctlx_s          cn50xx;
+	struct cvmx_usbcx_diepctlx_s          cn52xx;
+	struct cvmx_usbcx_diepctlx_s          cn52xxp1;
+	struct cvmx_usbcx_diepctlx_s          cn56xx;
+	struct cvmx_usbcx_diepctlx_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t;
+
+/**
+ * cvmx_usbc#_diepint#
+ *
+ * Device Endpoint-n Interrupt Register (DIEPINTn)
+ *
+ * This register indicates the status of an endpoint with respect to
+ * USB- and AHB-related events. The application must read this register
+ * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
+ * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt,
+ * respectively) is set. Before the application can read this register,
+ * it must first read the Device All Endpoints Interrupt (DAINT) register
+ * to get the exact endpoint number for the Device Endpoint-n Interrupt
+ * register. The application must clear the appropriate bit in this register
+ * to clear the corresponding bits in the DAINT and GINTSTS registers.
+ */
+union cvmx_usbcx_diepintx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_diepintx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_7_31                : 25;
+	uint32_t inepnakeff                   : 1;  /**< IN Endpoint NAK Effective (INEPNakEff)
+                                                         Applies to periodic IN endpoints only.
+                                                         Indicates that the IN endpoint NAK bit set by the application has
+                                                         taken effect in the core. This bit can be cleared when the
+                                                         application clears the IN endpoint NAK by writing to
+                                                         DIEPCTLn.CNAK.
+                                                         This interrupt indicates that the core has sampled the NAK bit
+                                                         set (either by the application or by the core).
+                                                         This interrupt does not necessarily mean that a NAK handshake
+                                                         is sent on the USB. A STALL bit takes priority over a NAK bit. */
+	uint32_t intknepmis                   : 1;  /**< IN Token Received with EP Mismatch (INTknEPMis)
+                                                         Applies to non-periodic IN endpoints only.
+                                                         Indicates that the data in the top of the non-periodic TxFIFO
+                                                         belongs to an endpoint other than the one for which the IN
+                                                         token was received. This interrupt is asserted on the endpoint
+                                                         for which the IN token was received. */
+	uint32_t intkntxfemp                  : 1;  /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp)
+                                                         Applies only to non-periodic IN endpoints.
+                                                         Indicates that an IN token was received when the associated
+                                                         TxFIFO (periodic/non-periodic) was empty. This interrupt is
+                                                         asserted on the endpoint for which the IN token was received. */
+	uint32_t timeout                      : 1;  /**< Timeout Condition (TimeOUT)
+                                                         Applies to non-isochronous IN endpoints only.
+                                                         Indicates that the core has detected a timeout condition on the
+                                                         USB for the last IN token on this endpoint. */
+	uint32_t ahberr                       : 1;  /**< AHB Error (AHBErr)
+                                                         This is generated only in Internal DMA mode when there is an
+                                                         AHB error during an AHB read/write. The application can read
+                                                         the corresponding endpoint DMA address register to get the
+                                                         error address. */
+	uint32_t epdisbld                     : 1;  /**< Endpoint Disabled Interrupt (EPDisbld)
+                                                         This bit indicates that the endpoint is disabled per the
+                                                         application's request. */
+	uint32_t xfercompl                    : 1;  /**< Transfer Completed Interrupt (XferCompl)
+                                                         Indicates that the programmed transfer is complete on the AHB
+                                                         as well as on the USB, for this endpoint. */
+#else
+	uint32_t xfercompl                    : 1;
+	uint32_t epdisbld                     : 1;
+	uint32_t ahberr                       : 1;
+	uint32_t timeout                      : 1;
+	uint32_t intkntxfemp                  : 1;
+	uint32_t intknepmis                   : 1;
+	uint32_t inepnakeff                   : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_usbcx_diepintx_s          cn30xx;
+	struct cvmx_usbcx_diepintx_s          cn31xx;
+	struct cvmx_usbcx_diepintx_s          cn50xx;
+	struct cvmx_usbcx_diepintx_s          cn52xx;
+	struct cvmx_usbcx_diepintx_s          cn52xxp1;
+	struct cvmx_usbcx_diepintx_s          cn56xx;
+	struct cvmx_usbcx_diepintx_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t;
+
+/**
+ * cvmx_usbc#_diepmsk
+ *
+ * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK)
+ *
+ * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers
+ * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
+ * for a specific status in the DIEPINTn register can be masked by writing to the corresponding
+ * bit in this register. Status bits are masked by default.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+union cvmx_usbcx_diepmsk
+{
+	uint32_t u32;
+	struct cvmx_usbcx_diepmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_7_31                : 25;
+	uint32_t inepnakeffmsk                : 1;  /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
+	uint32_t intknepmismsk                : 1;  /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
+	uint32_t intkntxfempmsk               : 1;  /**< IN Token Received When TxFIFO Empty Mask
+                                                         (INTknTXFEmpMsk) */
+	uint32_t timeoutmsk                   : 1;  /**< Timeout Condition Mask (TimeOUTMsk)
+                                                         (Non-isochronous endpoints) */
+	uint32_t ahberrmsk                    : 1;  /**< AHB Error Mask (AHBErrMsk) */
+	uint32_t epdisbldmsk                  : 1;  /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
+	uint32_t xfercomplmsk                 : 1;  /**< Transfer Completed Interrupt Mask (XferComplMsk) */
+#else
+	uint32_t xfercomplmsk                 : 1;
+	uint32_t epdisbldmsk                  : 1;
+	uint32_t ahberrmsk                    : 1;
+	uint32_t timeoutmsk                   : 1;
+	uint32_t intkntxfempmsk               : 1;
+	uint32_t intknepmismsk                : 1;
+	uint32_t inepnakeffmsk                : 1;
+	uint32_t reserved_7_31                : 25;
+#endif
+	} s;
+	struct cvmx_usbcx_diepmsk_s           cn30xx;
+	struct cvmx_usbcx_diepmsk_s           cn31xx;
+	struct cvmx_usbcx_diepmsk_s           cn50xx;
+	struct cvmx_usbcx_diepmsk_s           cn52xx;
+	struct cvmx_usbcx_diepmsk_s           cn52xxp1;
+	struct cvmx_usbcx_diepmsk_s           cn56xx;
+	struct cvmx_usbcx_diepmsk_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t;
+
+/**
+ * cvmx_usbc#_dieptsiz#
+ *
+ * Device Endpoint-n Transfer Size Register (DIEPTSIZn)
+ *
+ * The application must modify this register before enabling the endpoint.
+ * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna),
+ * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
+ * This register is used only for endpoints other than Endpoint 0.
+ */
+union cvmx_usbcx_dieptsizx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dieptsizx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t mc                           : 2;  /**< Multi Count (MC)
+                                                         Applies to IN endpoints only.
+                                                         For periodic IN endpoints, this field indicates the number of
+                                                         packets that must be transmitted per microframe on the USB.
+                                                         The core uses this field to calculate the data PID for
+                                                         isochronous IN endpoints.
+                                                         * 2'b01: 1 packet
+                                                         * 2'b10: 2 packets
+                                                         * 2'b11: 3 packets
+                                                         For non-periodic IN endpoints, this field is valid only in Internal
+                                                         DMA mode. It specifies the number of packets the core should
+                                                         fetch for an IN endpoint before it switches to the endpoint
+                                                         pointed to by the Next Endpoint field of the Device Endpoint-n
+                                                         Control register (DIEPCTLn.NextEp) */
+	uint32_t pktcnt                       : 10; /**< Packet Count (PktCnt)
+                                                         Indicates the total number of USB packets that constitute the
+                                                         Transfer Size amount of data for this endpoint.
+                                                         IN Endpoints: This field is decremented every time a packet
+                                                         (maximum size or short packet) is read from the TxFIFO. */
+	uint32_t xfersize                     : 19; /**< Transfer Size (XferSize)
+                                                         This field contains the transfer size in bytes for the current
+                                                         endpoint.
+                                                         The core only interrupts the application after it has exhausted
+                                                         the transfer size amount of data. The transfer size can be set to
+                                                         the maximum packet size of the endpoint, to be interrupted at
+                                                         the end of each packet.
+                                                         IN Endpoints: The core decrements this field every time a
+                                                         packet from the external memory is written to the TxFIFO. */
+#else
+	uint32_t xfersize                     : 19;
+	uint32_t pktcnt                       : 10;
+	uint32_t mc                           : 2;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_dieptsizx_s         cn30xx;
+	struct cvmx_usbcx_dieptsizx_s         cn31xx;
+	struct cvmx_usbcx_dieptsizx_s         cn50xx;
+	struct cvmx_usbcx_dieptsizx_s         cn52xx;
+	struct cvmx_usbcx_dieptsizx_s         cn52xxp1;
+	struct cvmx_usbcx_dieptsizx_s         cn56xx;
+	struct cvmx_usbcx_dieptsizx_s         cn56xxp1;
+};
+typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t;
+
+/**
+ * cvmx_usbc#_doepctl#
+ *
+ * Device OUT Endpoint-n Control Register (DOEPCTLn)
+ *
+ * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
+ */
+union cvmx_usbcx_doepctlx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_doepctlx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t epena                        : 1;  /**< Endpoint Enable (EPEna)
+                                                         Indicates that the application has allocated the memory tp start
+                                                         receiving data from the USB.
+                                                         The core clears this bit before setting any of the following
+                                                         interrupts on this endpoint:
+                                                         * SETUP Phase Done
+                                                         * Endpoint Disabled
+                                                         * Transfer Completed
+                                                         For control OUT endpoints in DMA mode, this bit must be set
+                                                         to be able to transfer SETUP data packets in memory. */
+	uint32_t epdis                        : 1;  /**< Endpoint Disable (EPDis)
+                                                         The application sets this bit to stop transmitting data on an
+                                                         endpoint, even before the transfer for that endpoint is complete.
+                                                         The application must wait for the Endpoint Disabled interrupt
+                                                         before treating the endpoint as disabled. The core clears this bit
+                                                         before setting the Endpoint Disabled Interrupt. The application
+                                                         should set this bit only if Endpoint Enable is already set for this
+                                                         endpoint. */
+	uint32_t setd1pid                     : 1;  /**< For Interrupt/BULK enpoints:
+                                                          Set DATA1 PID (SetD1PID)
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA1.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetOddFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to odd (micro)frame. */
+	uint32_t setd0pid                     : 1;  /**< For Interrupt/BULK enpoints:
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA0.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetEvenFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to even (micro)frame. */
+	uint32_t snak                         : 1;  /**< Set NAK (SNAK)
+                                                         A write to this bit sets the NAK bit for the endpoint.
+                                                         Using this bit, the application can control the transmission of
+                                                         NAK handshakes on an endpoint. The core can also set this bit
+                                                         for an endpoint after a SETUP packet is received on the
+                                                         endpoint. */
+	uint32_t cnak                         : 1;  /**< Clear NAK (CNAK)
+                                                         A write to this bit clears the NAK bit for the endpoint. */
+	uint32_t reserved_22_25               : 4;
+	uint32_t stall                        : 1;  /**< STALL Handshake (Stall)
+                                                         For non-control, non-isochronous endpoints:
+                                                          The application sets this bit to stall all tokens from the USB host
+                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
+                                                          Global OUT NAK is set along with this bit, the STALL bit takes
+                                                          priority.  Only the application can clear this bit, never the core.
+                                                         For control endpoints:
+                                                          The application can only set this bit, and the core clears it, when
+                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
+                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
+                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
+                                                          the core always responds to SETUP data packets with an ACK handshake. */
+	uint32_t snp                          : 1;  /**< Snoop Mode (Snp)
+                                                         This bit configures the endpoint to Snoop mode.  In Snoop mode,
+                                                         the core does not check the correctness of OUT packets before
+                                                         transferring them to application memory. */
+	uint32_t eptype                       : 2;  /**< Endpoint Type (EPType)
+                                                         This is the transfer type supported by this logical endpoint.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+	uint32_t naksts                       : 1;  /**< NAK Status (NAKSts)
+                                                         Indicates the following:
+                                                         * 1'b0: The core is transmitting non-NAK handshakes based
+                                                                 on the FIFO status
+                                                         * 1'b1: The core is transmitting NAK handshakes on this
+                                                                 endpoint.
+                                                         When either the application or the core sets this bit:
+                                                         * The core stops receiving any data on an OUT endpoint, even
+                                                           if there is space in the RxFIFO to accomodate the incoming
+                                                           packet. */
+	uint32_t dpid                         : 1;  /**< For interrupt/bulk IN and OUT endpoints:
+                                                          Endpoint Data PID (DPID)
+                                                          Contains the PID of the packet to be received or transmitted on
+                                                          this endpoint.  The application should program the PID of the first
+                                                          packet to be received or transmitted on this endpoint, after the
+                                                          endpoint is activated.  Applications use the SetD1PID and
+                                                          SetD0PID fields of this register to program either DATA0 or
+                                                          DATA1 PID.
+                                                          * 1'b0: DATA0
+                                                          * 1'b1: DATA1
+                                                         For isochronous IN and OUT endpoints:
+                                                          Even/Odd (Micro)Frame (EO_FrNum)
+                                                          Indicates the (micro)frame number in which the core transmits/
+                                                          receives isochronous data for this endpoint.  The application
+                                                          should program the even/odd (micro) frame number in which it
+                                                          intends to transmit/receive isochronous data for this endpoint
+                                                          using the SetEvnFr and SetOddFr fields in this register.
+                                                          * 1'b0: Even (micro)frame
+                                                          * 1'b1: Odd (micro)frame */
+	uint32_t usbactep                     : 1;  /**< USB Active Endpoint (USBActEP)
+                                                         Indicates whether this endpoint is active in the current
+                                                         configuration and interface.  The core clears this bit for all
+                                                         endpoints (other than EP 0) after detecting a USB reset.  After
+                                                         receiving the SetConfiguration and SetInterface commands, the
+                                                         application must program endpoint registers accordingly and set
+                                                         this bit. */
+	uint32_t reserved_11_14               : 4;
+	uint32_t mps                          : 11; /**< Maximum Packet Size (MPS)
+                                                         Applies to IN and OUT endpoints.
+                                                         The application must program this field with the maximum
+                                                         packet size for the current logical endpoint.  This value is in
+                                                         bytes. */
+#else
+	uint32_t mps                          : 11;
+	uint32_t reserved_11_14               : 4;
+	uint32_t usbactep                     : 1;
+	uint32_t dpid                         : 1;
+	uint32_t naksts                       : 1;
+	uint32_t eptype                       : 2;
+	uint32_t snp                          : 1;
+	uint32_t stall                        : 1;
+	uint32_t reserved_22_25               : 4;
+	uint32_t cnak                         : 1;
+	uint32_t snak                         : 1;
+	uint32_t setd0pid                     : 1;
+	uint32_t setd1pid                     : 1;
+	uint32_t epdis                        : 1;
+	uint32_t epena                        : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_doepctlx_s          cn30xx;
+	struct cvmx_usbcx_doepctlx_s          cn31xx;
+	struct cvmx_usbcx_doepctlx_s          cn50xx;
+	struct cvmx_usbcx_doepctlx_s          cn52xx;
+	struct cvmx_usbcx_doepctlx_s          cn52xxp1;
+	struct cvmx_usbcx_doepctlx_s          cn56xx;
+	struct cvmx_usbcx_doepctlx_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t;
+
+/**
+ * cvmx_usbc#_doepint#
+ *
+ * Device Endpoint-n Interrupt Register (DOEPINTn)
+ *
+ * This register indicates the status of an endpoint with respect to USB- and AHB-related events.
+ * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints
+ * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively)
+ * is set. Before the application can read this register, it must first read the Device All
+ * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n
+ * Interrupt register. The application must clear the appropriate bit in this register to clear the
+ * corresponding bits in the DAINT and GINTSTS registers.
+ */
+union cvmx_usbcx_doepintx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_doepintx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t outtknepdis                  : 1;  /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
+                                                         Applies only to control OUT endpoints.
+                                                         Indicates that an OUT token was received when the endpoint
+                                                         was not yet enabled. This interrupt is asserted on the endpoint
+                                                         for which the OUT token was received. */
+	uint32_t setup                        : 1;  /**< SETUP Phase Done (SetUp)
+                                                         Applies to control OUT endpoints only.
+                                                         Indicates that the SETUP phase for the control endpoint is
+                                                         complete and no more back-to-back SETUP packets were
+                                                         received for the current control transfer. On this interrupt, the
+                                                         application can decode the received SETUP data packet. */
+	uint32_t ahberr                       : 1;  /**< AHB Error (AHBErr)
+                                                         This is generated only in Internal DMA mode when there is an
+                                                         AHB error during an AHB read/write. The application can read
+                                                         the corresponding endpoint DMA address register to get the
+                                                         error address. */
+	uint32_t epdisbld                     : 1;  /**< Endpoint Disabled Interrupt (EPDisbld)
+                                                         This bit indicates that the endpoint is disabled per the
+                                                         application's request. */
+	uint32_t xfercompl                    : 1;  /**< Transfer Completed Interrupt (XferCompl)
+                                                         Indicates that the programmed transfer is complete on the AHB
+                                                         as well as on the USB, for this endpoint. */
+#else
+	uint32_t xfercompl                    : 1;
+	uint32_t epdisbld                     : 1;
+	uint32_t ahberr                       : 1;
+	uint32_t setup                        : 1;
+	uint32_t outtknepdis                  : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_usbcx_doepintx_s          cn30xx;
+	struct cvmx_usbcx_doepintx_s          cn31xx;
+	struct cvmx_usbcx_doepintx_s          cn50xx;
+	struct cvmx_usbcx_doepintx_s          cn52xx;
+	struct cvmx_usbcx_doepintx_s          cn52xxp1;
+	struct cvmx_usbcx_doepintx_s          cn56xx;
+	struct cvmx_usbcx_doepintx_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t;
+
+/**
+ * cvmx_usbc#_doepmsk
+ *
+ * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK)
+ *
+ * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers
+ * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt
+ * for a specific status in the DOEPINTn register can be masked by writing into the
+ * corresponding bit in this register. Status bits are masked by default.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+union cvmx_usbcx_doepmsk
+{
+	uint32_t u32;
+	struct cvmx_usbcx_doepmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t outtknepdismsk               : 1;  /**< OUT Token Received when Endpoint Disabled Mask
+                                                         (OUTTknEPdisMsk)
+                                                         Applies to control OUT endpoints only. */
+	uint32_t setupmsk                     : 1;  /**< SETUP Phase Done Mask (SetUPMsk)
+                                                         Applies to control endpoints only. */
+	uint32_t ahberrmsk                    : 1;  /**< AHB Error (AHBErrMsk) */
+	uint32_t epdisbldmsk                  : 1;  /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
+	uint32_t xfercomplmsk                 : 1;  /**< Transfer Completed Interrupt Mask (XferComplMsk) */
+#else
+	uint32_t xfercomplmsk                 : 1;
+	uint32_t epdisbldmsk                  : 1;
+	uint32_t ahberrmsk                    : 1;
+	uint32_t setupmsk                     : 1;
+	uint32_t outtknepdismsk               : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_usbcx_doepmsk_s           cn30xx;
+	struct cvmx_usbcx_doepmsk_s           cn31xx;
+	struct cvmx_usbcx_doepmsk_s           cn50xx;
+	struct cvmx_usbcx_doepmsk_s           cn52xx;
+	struct cvmx_usbcx_doepmsk_s           cn52xxp1;
+	struct cvmx_usbcx_doepmsk_s           cn56xx;
+	struct cvmx_usbcx_doepmsk_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t;
+
+/**
+ * cvmx_usbc#_doeptsiz#
+ *
+ * Device Endpoint-n Transfer Size Register (DOEPTSIZn)
+ *
+ * The application must modify this register before enabling the endpoint.
+ * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
+ * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application
+ * can only read this register once the core has cleared the Endpoint Enable bit.
+ * This register is used only for endpoints other than Endpoint 0.
+ */
+union cvmx_usbcx_doeptsizx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_doeptsizx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t mc                           : 2;  /**< Multi Count (MC)
+                                                         Received Data PID (RxDPID)
+                                                         Applies to isochronous OUT endpoints only.
+                                                         This is the data PID received in the last packet for this endpoint.
+                                                         2'b00: DATA0
+                                                         2'b01: DATA1
+                                                         2'b10: DATA2
+                                                         2'b11: MDATA
+                                                         SETUP Packet Count (SUPCnt)
+                                                         Applies to control OUT Endpoints only.
+                                                         This field specifies the number of back-to-back SETUP data
+                                                         packets the endpoint can receive.
+                                                         2'b01: 1 packet
+                                                         2'b10: 2 packets
+                                                         2'b11: 3 packets */
+	uint32_t pktcnt                       : 10; /**< Packet Count (PktCnt)
+                                                         Indicates the total number of USB packets that constitute the
+                                                         Transfer Size amount of data for this endpoint.
+                                                         OUT Endpoints: This field is decremented every time a
+                                                         packet (maximum size or short packet) is written to the
+                                                         RxFIFO. */
+	uint32_t xfersize                     : 19; /**< Transfer Size (XferSize)
+                                                         This field contains the transfer size in bytes for the current
+                                                         endpoint.
+                                                         The core only interrupts the application after it has exhausted
+                                                         the transfer size amount of data. The transfer size can be set to
+                                                         the maximum packet size of the endpoint, to be interrupted at
+                                                         the end of each packet.
+                                                         OUT Endpoints: The core decrements this field every time a
+                                                         packet is read from the RxFIFO and written to the external
+                                                         memory. */
+#else
+	uint32_t xfersize                     : 19;
+	uint32_t pktcnt                       : 10;
+	uint32_t mc                           : 2;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_doeptsizx_s         cn30xx;
+	struct cvmx_usbcx_doeptsizx_s         cn31xx;
+	struct cvmx_usbcx_doeptsizx_s         cn50xx;
+	struct cvmx_usbcx_doeptsizx_s         cn52xx;
+	struct cvmx_usbcx_doeptsizx_s         cn52xxp1;
+	struct cvmx_usbcx_doeptsizx_s         cn56xx;
+	struct cvmx_usbcx_doeptsizx_s         cn56xxp1;
+};
+typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t;
+
+/**
+ * cvmx_usbc#_dptxfsiz#
+ *
+ * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ)
+ *
+ * This register holds the memory start address of each periodic TxFIFO to implemented
+ * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
+ * This register is repeated for each periodic FIFO instantiated.
+ */
+union cvmx_usbcx_dptxfsizx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dptxfsizx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dptxfsize                    : 16; /**< Device Periodic TxFIFO Size (DPTxFSize)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 4
+                                                         * Maximum value is 768 */
+	uint32_t dptxfstaddr                  : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr)
+                                                         Holds the start address in the RAM for this periodic FIFO. */
+#else
+	uint32_t dptxfstaddr                  : 16;
+	uint32_t dptxfsize                    : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_dptxfsizx_s         cn30xx;
+	struct cvmx_usbcx_dptxfsizx_s         cn31xx;
+	struct cvmx_usbcx_dptxfsizx_s         cn50xx;
+	struct cvmx_usbcx_dptxfsizx_s         cn52xx;
+	struct cvmx_usbcx_dptxfsizx_s         cn52xxp1;
+	struct cvmx_usbcx_dptxfsizx_s         cn56xx;
+	struct cvmx_usbcx_dptxfsizx_s         cn56xxp1;
+};
+typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t;
+
+/**
+ * cvmx_usbc#_dsts
+ *
+ * Device Status Register (DSTS)
+ *
+ * This register indicates the status of the core with respect to USB-related events.
+ * It must be read on interrupts from Device All Interrupts (DAINT) register.
+ */
+union cvmx_usbcx_dsts
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dsts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_22_31               : 10;
+	uint32_t soffn                        : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN)
+                                                         When the core is operating at high speed, this field contains a
+                                                         microframe number. When the core is operating at full or low
+                                                         speed, this field contains a frame number. */
+	uint32_t reserved_4_7                 : 4;
+	uint32_t errticerr                    : 1;  /**< Erratic Error (ErrticErr)
+                                                         The core sets this bit to report any erratic errors
+                                                         (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
+                                                         least 2 ms, due to PHY error) seen on the UTMI+.
+                                                         Due to erratic errors, the O2P USB core goes into Suspended
+                                                         state and an interrupt is generated to the application with Early
+                                                         Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
+                                                         If the early suspend is asserted due to an erratic error, the
+                                                         application can only perform a soft disconnect recover. */
+	uint32_t enumspd                      : 2;  /**< Enumerated Speed (EnumSpd)
+                                                         Indicates the speed at which the O2P USB core has come up
+                                                         after speed detection through a chirp sequence.
+                                                         * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
+                                                         * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
+                                                         * 2'b10: Low speed (PHY clock is running at 6 MHz)
+                                                         * 2'b11: Full speed (PHY clock is running at 48 MHz)
+                                                         Low speed is not supported for devices using a UTMI+ PHY. */
+	uint32_t suspsts                      : 1;  /**< Suspend Status (SuspSts)
+                                                         In Device mode, this bit is set as long as a Suspend condition is
+                                                         detected on the USB. The core enters the Suspended state
+                                                         when there is no activity on the phy_line_state_i signal for an
+                                                         extended period of time. The core comes out of the suspend:
+                                                         * When there is any activity on the phy_line_state_i signal
+                                                         * When the application writes to the Remote Wakeup Signaling
+                                                           bit in the Device Control register (DCTL.RmtWkUpSig). */
+#else
+	uint32_t suspsts                      : 1;
+	uint32_t enumspd                      : 2;
+	uint32_t errticerr                    : 1;
+	uint32_t reserved_4_7                 : 4;
+	uint32_t soffn                        : 14;
+	uint32_t reserved_22_31               : 10;
+#endif
+	} s;
+	struct cvmx_usbcx_dsts_s              cn30xx;
+	struct cvmx_usbcx_dsts_s              cn31xx;
+	struct cvmx_usbcx_dsts_s              cn50xx;
+	struct cvmx_usbcx_dsts_s              cn52xx;
+	struct cvmx_usbcx_dsts_s              cn52xxp1;
+	struct cvmx_usbcx_dsts_s              cn56xx;
+	struct cvmx_usbcx_dsts_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t;
+
+/**
+ * cvmx_usbc#_dtknqr1
+ *
+ * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1)
+ *
+ * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token
+ * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number.
+ * A read from this register returns the first 5 endpoint entries of the IN Token Sequence
+ * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
+ * token is discarded.
+ */
+union cvmx_usbcx_dtknqr1
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dtknqr1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t eptkn                        : 24; /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 5
+                                                         * Bits [27:24]: Endpoint number of Token 4
+                                                         - .......
+                                                         * Bits [15:12]: Endpoint number of Token 1
+                                                         * Bits [11:8]: Endpoint number of Token 0 */
+	uint32_t wrapbit                      : 1;  /**< Wrap Bit (WrapBit)
+                                                         This bit is set when the write pointer wraps. It is cleared when
+                                                         the learning queue is cleared. */
+	uint32_t reserved_5_6                 : 2;
+	uint32_t intknwptr                    : 5;  /**< IN Token Queue Write Pointer (INTknWPtr) */
+#else
+	uint32_t intknwptr                    : 5;
+	uint32_t reserved_5_6                 : 2;
+	uint32_t wrapbit                      : 1;
+	uint32_t eptkn                        : 24;
+#endif
+	} s;
+	struct cvmx_usbcx_dtknqr1_s           cn30xx;
+	struct cvmx_usbcx_dtknqr1_s           cn31xx;
+	struct cvmx_usbcx_dtknqr1_s           cn50xx;
+	struct cvmx_usbcx_dtknqr1_s           cn52xx;
+	struct cvmx_usbcx_dtknqr1_s           cn52xxp1;
+	struct cvmx_usbcx_dtknqr1_s           cn56xx;
+	struct cvmx_usbcx_dtknqr1_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t;
+
+/**
+ * cvmx_usbc#_dtknqr2
+ *
+ * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2)
+ *
+ * A read from this register returns the next 8 endpoint entries of the learning queue.
+ */
+union cvmx_usbcx_dtknqr2
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dtknqr2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 13
+                                                         * Bits [27:24]: Endpoint number of Token 12
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 7
+                                                         * Bits [3:0]: Endpoint number of Token 6 */
+#else
+	uint32_t eptkn                        : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_dtknqr2_s           cn30xx;
+	struct cvmx_usbcx_dtknqr2_s           cn31xx;
+	struct cvmx_usbcx_dtknqr2_s           cn50xx;
+	struct cvmx_usbcx_dtknqr2_s           cn52xx;
+	struct cvmx_usbcx_dtknqr2_s           cn52xxp1;
+	struct cvmx_usbcx_dtknqr2_s           cn56xx;
+	struct cvmx_usbcx_dtknqr2_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t;
+
+/**
+ * cvmx_usbc#_dtknqr3
+ *
+ * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3)
+ *
+ * A read from this register returns the next 8 endpoint entries of the learning queue.
+ */
+union cvmx_usbcx_dtknqr3
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dtknqr3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 21
+                                                         * Bits [27:24]: Endpoint number of Token 20
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 15
+                                                         * Bits [3:0]: Endpoint number of Token 14 */
+#else
+	uint32_t eptkn                        : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_dtknqr3_s           cn30xx;
+	struct cvmx_usbcx_dtknqr3_s           cn31xx;
+	struct cvmx_usbcx_dtknqr3_s           cn50xx;
+	struct cvmx_usbcx_dtknqr3_s           cn52xx;
+	struct cvmx_usbcx_dtknqr3_s           cn52xxp1;
+	struct cvmx_usbcx_dtknqr3_s           cn56xx;
+	struct cvmx_usbcx_dtknqr3_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t;
+
+/**
+ * cvmx_usbc#_dtknqr4
+ *
+ * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4)
+ *
+ * A read from this register returns the last 8 endpoint entries of the learning queue.
+ */
+union cvmx_usbcx_dtknqr4
+{
+	uint32_t u32;
+	struct cvmx_usbcx_dtknqr4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t eptkn                        : 32; /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 29
+                                                         * Bits [27:24]: Endpoint number of Token 28
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 23
+                                                         * Bits [3:0]: Endpoint number of Token 22 */
+#else
+	uint32_t eptkn                        : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_dtknqr4_s           cn30xx;
+	struct cvmx_usbcx_dtknqr4_s           cn31xx;
+	struct cvmx_usbcx_dtknqr4_s           cn50xx;
+	struct cvmx_usbcx_dtknqr4_s           cn52xx;
+	struct cvmx_usbcx_dtknqr4_s           cn52xxp1;
+	struct cvmx_usbcx_dtknqr4_s           cn56xx;
+	struct cvmx_usbcx_dtknqr4_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t;
+
+/**
+ * cvmx_usbc#_gahbcfg
+ *
+ * Core AHB Configuration Register (GAHBCFG)
+ *
+ * This register can be used to configure the core after power-on or a change in mode of operation.
+ * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
+ * interface to the O2P USB core. In general, software need not know about this interface except to
+ * program the values as specified.
+ *
+ * The application must program this register as part of the O2P USB core initialization.
+ * Do not change this register after the initial programming.
+ */
+union cvmx_usbcx_gahbcfg
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gahbcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_9_31                : 23;
+	uint32_t ptxfemplvl                   : 1;  /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
+                                                         Software should set this bit to 0x1.
+                                                         Indicates when the Periodic TxFIFO Empty Interrupt bit in the
+                                                         Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
+                                                         bit is used only in Slave mode.
+                                                         * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
+                                                           TxFIFO is half empty
+                                                         * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
+                                                           TxFIFO is completely empty */
+	uint32_t nptxfemplvl                  : 1;  /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
+                                                         Software should set this bit to 0x1.
+                                                         Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
+                                                         the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
+                                                         This bit is used only in Slave mode.
+                                                         * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
+                                                            Periodic TxFIFO is half empty
+                                                         * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
+                                                            Periodic TxFIFO is completely empty */
+	uint32_t reserved_6_6                 : 1;
+	uint32_t dmaen                        : 1;  /**< DMA Enable (DMAEn)
+                                                         * 1'b0: Core operates in Slave mode
+                                                         * 1'b1: Core operates in a DMA mode */
+	uint32_t hbstlen                      : 4;  /**< Burst Length/Type (HBstLen)
+                                                         This field has not effect and should be left as 0x0. */
+	uint32_t glblintrmsk                  : 1;  /**< Global Interrupt Mask (GlblIntrMsk)
+                                                         Software should set this field to 0x1.
+                                                         The application uses this bit to mask  or unmask the interrupt
+                                                         line assertion to itself. Irrespective of this bit's setting, the
+                                                         interrupt status registers are updated by the core.
+                                                         * 1'b0: Mask the interrupt assertion to the application.
+                                                         * 1'b1: Unmask the interrupt assertion to the application. */
+#else
+	uint32_t glblintrmsk                  : 1;
+	uint32_t hbstlen                      : 4;
+	uint32_t dmaen                        : 1;
+	uint32_t reserved_6_6                 : 1;
+	uint32_t nptxfemplvl                  : 1;
+	uint32_t ptxfemplvl                   : 1;
+	uint32_t reserved_9_31                : 23;
+#endif
+	} s;
+	struct cvmx_usbcx_gahbcfg_s           cn30xx;
+	struct cvmx_usbcx_gahbcfg_s           cn31xx;
+	struct cvmx_usbcx_gahbcfg_s           cn50xx;
+	struct cvmx_usbcx_gahbcfg_s           cn52xx;
+	struct cvmx_usbcx_gahbcfg_s           cn52xxp1;
+	struct cvmx_usbcx_gahbcfg_s           cn56xx;
+	struct cvmx_usbcx_gahbcfg_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
+
+/**
+ * cvmx_usbc#_ghwcfg1
+ *
+ * User HW Config1 Register (GHWCFG1)
+ *
+ * This register contains the logical endpoint direction(s) of the O2P USB core.
+ */
+union cvmx_usbcx_ghwcfg1
+{
+	uint32_t u32;
+	struct cvmx_usbcx_ghwcfg1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t epdir                        : 32; /**< Endpoint Direction (epdir)
+                                                         Two bits per endpoint represent the direction.
+                                                         * 2'b00: BIDIR (IN and OUT) endpoint
+                                                         * 2'b01: IN endpoint
+                                                         * 2'b10: OUT endpoint
+                                                         * 2'b11: Reserved
+                                                         Bits [31:30]: Endpoint 15 direction
+                                                         Bits [29:28]: Endpoint 14 direction
+                                                         - ...
+                                                         Bits [3:2]: Endpoint 1 direction
+                                                         Bits[1:0]: Endpoint 0 direction (always BIDIR) */
+#else
+	uint32_t epdir                        : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_ghwcfg1_s           cn30xx;
+	struct cvmx_usbcx_ghwcfg1_s           cn31xx;
+	struct cvmx_usbcx_ghwcfg1_s           cn50xx;
+	struct cvmx_usbcx_ghwcfg1_s           cn52xx;
+	struct cvmx_usbcx_ghwcfg1_s           cn52xxp1;
+	struct cvmx_usbcx_ghwcfg1_s           cn56xx;
+	struct cvmx_usbcx_ghwcfg1_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t;
+
+/**
+ * cvmx_usbc#_ghwcfg2
+ *
+ * User HW Config2 Register (GHWCFG2)
+ *
+ * This register contains configuration options of the O2P USB core.
+ */
+union cvmx_usbcx_ghwcfg2
+{
+	uint32_t u32;
+	struct cvmx_usbcx_ghwcfg2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t tknqdepth                    : 5;  /**< Device Mode IN Token Sequence Learning Queue Depth
+                                                         (TknQDepth)
+                                                         Range: 0-30 */
+	uint32_t ptxqdepth                    : 2;  /**< Host Mode Periodic Request Queue Depth (PTxQDepth)
+                                                         * 2'b00: 2
+                                                         * 2'b01: 4
+                                                         * 2'b10: 8
+                                                         * Others: Reserved */
+	uint32_t nptxqdepth                   : 2;  /**< Non-Periodic Request Queue Depth (NPTxQDepth)
+                                                         * 2'b00: 2
+                                                         * 2'b01: 4
+                                                         * 2'b10: 8
+                                                         * Others: Reserved */
+	uint32_t reserved_20_21               : 2;
+	uint32_t dynfifosizing                : 1;  /**< Dynamic FIFO Sizing Enabled (DynFifoSizing)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t periosupport                 : 1;  /**< Periodic OUT Channels Supported in Host Mode
+                                                         (PerioSupport)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t numhstchnl                   : 4;  /**< Number of Host Channels (NumHstChnl)
+                                                         Indicates the number of host channels supported by the core in
+                                                         Host mode. The range of this field is 0-15: 0 specifies 1
+                                                         channel, 15 specifies 16 channels. */
+	uint32_t numdeveps                    : 4;  /**< Number of Device Endpoints (NumDevEps)
+                                                         Indicates the number of device endpoints supported by the core
+                                                         in Device mode in addition to control endpoint 0. The range of
+                                                         this field is 1-15. */
+	uint32_t fsphytype                    : 2;  /**< Full-Speed PHY Interface Type (FSPhyType)
+                                                         * 2'b00: Full-speed interface not supported
+                                                         * 2'b01: Dedicated full-speed interface
+                                                         * 2'b10: FS pins shared with UTMI+ pins
+                                                         * 2'b11: FS pins shared with ULPI pins */
+	uint32_t hsphytype                    : 2;  /**< High-Speed PHY Interface Type (HSPhyType)
+                                                         * 2'b00: High-Speed interface not supported
+                                                         * 2'b01: UTMI+
+                                                         * 2'b10: ULPI
+                                                         * 2'b11: UTMI+ and ULPI */
+	uint32_t singpnt                      : 1;  /**< Point-to-Point (SingPnt)
+                                                         * 1'b0: Multi-point application
+                                                         * 1'b1: Single-point application */
+	uint32_t otgarch                      : 2;  /**< Architecture (OtgArch)
+                                                         * 2'b00: Slave-Only
+                                                         * 2'b01: External DMA
+                                                         * 2'b10: Internal DMA
+                                                         * Others: Reserved */
+	uint32_t otgmode                      : 3;  /**< Mode of Operation (OtgMode)
+                                                         * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
+                                                         * 3'b001: SRP-Capable OTG (Host & Device)
+                                                         * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
+                                                         Device)
+                                                         * 3'b011: SRP-Capable Device
+                                                         * 3'b100: Non-OTG Device
+                                                         * 3'b101: SRP-Capable Host
+                                                         * 3'b110: Non-OTG Host
+                                                         * Others: Reserved */
+#else
+	uint32_t otgmode                      : 3;
+	uint32_t otgarch                      : 2;
+	uint32_t singpnt                      : 1;
+	uint32_t hsphytype                    : 2;
+	uint32_t fsphytype                    : 2;
+	uint32_t numdeveps                    : 4;
+	uint32_t numhstchnl                   : 4;
+	uint32_t periosupport                 : 1;
+	uint32_t dynfifosizing                : 1;
+	uint32_t reserved_20_21               : 2;
+	uint32_t nptxqdepth                   : 2;
+	uint32_t ptxqdepth                    : 2;
+	uint32_t tknqdepth                    : 5;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_ghwcfg2_s           cn30xx;
+	struct cvmx_usbcx_ghwcfg2_s           cn31xx;
+	struct cvmx_usbcx_ghwcfg2_s           cn50xx;
+	struct cvmx_usbcx_ghwcfg2_s           cn52xx;
+	struct cvmx_usbcx_ghwcfg2_s           cn52xxp1;
+	struct cvmx_usbcx_ghwcfg2_s           cn56xx;
+	struct cvmx_usbcx_ghwcfg2_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t;
+
+/**
+ * cvmx_usbc#_ghwcfg3
+ *
+ * User HW Config3 Register (GHWCFG3)
+ *
+ * This register contains the configuration options of the O2P USB core.
+ */
+union cvmx_usbcx_ghwcfg3
+{
+	uint32_t u32;
+	struct cvmx_usbcx_ghwcfg3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dfifodepth                   : 16; /**< DFIFO Depth (DfifoDepth)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 32
+                                                         * Maximum value is 32768 */
+	uint32_t reserved_13_15               : 3;
+	uint32_t ahbphysync                   : 1;  /**< AHB and PHY Synchronous (AhbPhySync)
+                                                         Indicates whether AHB and PHY clocks are synchronous to
+                                                         each other.
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes
+                                                         This bit is tied to 1. */
+	uint32_t rsttype                      : 1;  /**< Reset Style for Clocked always Blocks in RTL (RstType)
+                                                         * 1'b0: Asynchronous reset is used in the core
+                                                         * 1'b1: Synchronous reset is used in the core */
+	uint32_t optfeature                   : 1;  /**< Optional Features Removed (OptFeature)
+                                                         Indicates whether the User ID register, GPIO interface ports,
+                                                         and SOF toggle and counter ports were removed for gate count
+                                                         optimization. */
+	uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support
+                                                         * 1'b0: Vendor Control Interface is not available on the core.
+                                                         * 1'b1: Vendor Control Interface is available. */
+	uint32_t i2c_selection                : 1;  /**< I2C Selection
+                                                         * 1'b0: I2C Interface is not available on the core.
+                                                         * 1'b1: I2C Interface is available on the core. */
+	uint32_t otgen                        : 1;  /**< OTG Function Enabled (OtgEn)
+                                                         The application uses this bit to indicate the O2P USB core's
+                                                         OTG capabilities.
+                                                         * 1'b0: Not OTG capable
+                                                         * 1'b1: OTG Capable */
+	uint32_t pktsizewidth                 : 3;  /**< Width of Packet Size Counters (PktSizeWidth)
+                                                         * 3'b000: 4 bits
+                                                         * 3'b001: 5 bits
+                                                         * 3'b010: 6 bits
+                                                         * 3'b011: 7 bits
+                                                         * 3'b100: 8 bits
+                                                         * 3'b101: 9 bits
+                                                         * 3'b110: 10 bits
+                                                         * Others: Reserved */
+	uint32_t xfersizewidth                : 4;  /**< Width of Transfer Size Counters (XferSizeWidth)
+                                                         * 4'b0000: 11 bits
+                                                         * 4'b0001: 12 bits
+                                                         - ...
+                                                         * 4'b1000: 19 bits
+                                                         * Others: Reserved */
+#else
+	uint32_t xfersizewidth                : 4;
+	uint32_t pktsizewidth                 : 3;
+	uint32_t otgen                        : 1;
+	uint32_t i2c_selection                : 1;
+	uint32_t vendor_control_interface_support : 1;
+	uint32_t optfeature                   : 1;
+	uint32_t rsttype                      : 1;
+	uint32_t ahbphysync                   : 1;
+	uint32_t reserved_13_15               : 3;
+	uint32_t dfifodepth                   : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_ghwcfg3_s           cn30xx;
+	struct cvmx_usbcx_ghwcfg3_s           cn31xx;
+	struct cvmx_usbcx_ghwcfg3_s           cn50xx;
+	struct cvmx_usbcx_ghwcfg3_s           cn52xx;
+	struct cvmx_usbcx_ghwcfg3_s           cn52xxp1;
+	struct cvmx_usbcx_ghwcfg3_s           cn56xx;
+	struct cvmx_usbcx_ghwcfg3_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
+
+/**
+ * cvmx_usbc#_ghwcfg4
+ *
+ * User HW Config4 Register (GHWCFG4)
+ *
+ * This register contains the configuration options of the O2P USB core.
+ */
+union cvmx_usbcx_ghwcfg4
+{
+	uint32_t u32;
+	struct cvmx_usbcx_ghwcfg4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_30_31               : 2;
+	uint32_t numdevmodinend               : 4;  /**< Enable dedicatd transmit FIFO for device IN endpoints. */
+	uint32_t endedtrfifo                  : 1;  /**< Enable dedicatd transmit FIFO for device IN endpoints. */
+	uint32_t sessendfltr                  : 1;  /**< "session_end" Filter Enabled (SessEndFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t bvalidfltr                   : 1;  /**< "b_valid" Filter Enabled (BValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t avalidfltr                   : 1;  /**< "a_valid" Filter Enabled (AValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t vbusvalidfltr                : 1;  /**< "vbus_valid" Filter Enabled (VBusValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t iddgfltr                     : 1;  /**< "iddig" Filter Enable (IddgFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t numctleps                    : 4;  /**< Number of Device Mode Control Endpoints in Addition to
+                                                         Endpoint 0 (NumCtlEps)
+                                                         Range: 1-15 */
+	uint32_t phydatawidth                 : 2;  /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
+                                                         (PhyDataWidth)
+                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
+                                                         to UTMI+.
+                                                         * 2'b00: 8 bits
+                                                         * 2'b01: 16 bits
+                                                         * 2'b10: 8/16 bits, software selectable
+                                                         * Others: Reserved */
+	uint32_t reserved_6_13                : 8;
+	uint32_t ahbfreq                      : 1;  /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t enablepwropt                 : 1;  /**< Enable Power Optimization? (EnablePwrOpt)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t numdevperioeps               : 4;  /**< Number of Device Mode Periodic IN Endpoints
+                                                         (NumDevPerioEps)
+                                                         Range: 0-15 */
+#else
+	uint32_t numdevperioeps               : 4;
+	uint32_t enablepwropt                 : 1;
+	uint32_t ahbfreq                      : 1;
+	uint32_t reserved_6_13                : 8;
+	uint32_t phydatawidth                 : 2;
+	uint32_t numctleps                    : 4;
+	uint32_t iddgfltr                     : 1;
+	uint32_t vbusvalidfltr                : 1;
+	uint32_t avalidfltr                   : 1;
+	uint32_t bvalidfltr                   : 1;
+	uint32_t sessendfltr                  : 1;
+	uint32_t endedtrfifo                  : 1;
+	uint32_t numdevmodinend               : 4;
+	uint32_t reserved_30_31               : 2;
+#endif
+	} s;
+	struct cvmx_usbcx_ghwcfg4_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_25_31               : 7;
+	uint32_t sessendfltr                  : 1;  /**< "session_end" Filter Enabled (SessEndFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t bvalidfltr                   : 1;  /**< "b_valid" Filter Enabled (BValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t avalidfltr                   : 1;  /**< "a_valid" Filter Enabled (AValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t vbusvalidfltr                : 1;  /**< "vbus_valid" Filter Enabled (VBusValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t iddgfltr                     : 1;  /**< "iddig" Filter Enable (IddgFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+	uint32_t numctleps                    : 4;  /**< Number of Device Mode Control Endpoints in Addition to
+                                                         Endpoint 0 (NumCtlEps)
+                                                         Range: 1-15 */
+	uint32_t phydatawidth                 : 2;  /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
+                                                         (PhyDataWidth)
+                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
+                                                         to UTMI+.
+                                                         * 2'b00: 8 bits
+                                                         * 2'b01: 16 bits
+                                                         * 2'b10: 8/16 bits, software selectable
+                                                         * Others: Reserved */
+	uint32_t reserved_6_13                : 8;
+	uint32_t ahbfreq                      : 1;  /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t enablepwropt                 : 1;  /**< Enable Power Optimization? (EnablePwrOpt)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+	uint32_t numdevperioeps               : 4;  /**< Number of Device Mode Periodic IN Endpoints
+                                                         (NumDevPerioEps)
+                                                         Range: 0-15 */
+#else
+	uint32_t numdevperioeps               : 4;
+	uint32_t enablepwropt                 : 1;
+	uint32_t ahbfreq                      : 1;
+	uint32_t reserved_6_13                : 8;
+	uint32_t phydatawidth                 : 2;
+	uint32_t numctleps                    : 4;
+	uint32_t iddgfltr                     : 1;
+	uint32_t vbusvalidfltr                : 1;
+	uint32_t avalidfltr                   : 1;
+	uint32_t bvalidfltr                   : 1;
+	uint32_t sessendfltr                  : 1;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} cn30xx;
+	struct cvmx_usbcx_ghwcfg4_cn30xx      cn31xx;
+	struct cvmx_usbcx_ghwcfg4_s           cn50xx;
+	struct cvmx_usbcx_ghwcfg4_s           cn52xx;
+	struct cvmx_usbcx_ghwcfg4_s           cn52xxp1;
+	struct cvmx_usbcx_ghwcfg4_s           cn56xx;
+	struct cvmx_usbcx_ghwcfg4_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t;
+
+/**
+ * cvmx_usbc#_gintmsk
+ *
+ * Core Interrupt Mask Register (GINTMSK)
+ *
+ * This register works with the Core Interrupt register to interrupt the application.
+ * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
+ * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
+ * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
+ */
+union cvmx_usbcx_gintmsk
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gintmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wkupintmsk                   : 1;  /**< Resume/Remote Wakeup Detected Interrupt Mask
+                                                         (WkUpIntMsk) */
+	uint32_t sessreqintmsk                : 1;  /**< Session Request/New Session Detected Interrupt Mask
+                                                         (SessReqIntMsk) */
+	uint32_t disconnintmsk                : 1;  /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */
+	uint32_t conidstschngmsk              : 1;  /**< Connector ID Status Change Mask (ConIDStsChngMsk) */
+	uint32_t reserved_27_27               : 1;
+	uint32_t ptxfempmsk                   : 1;  /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */
+	uint32_t hchintmsk                    : 1;  /**< Host Channels Interrupt Mask (HChIntMsk) */
+	uint32_t prtintmsk                    : 1;  /**< Host Port Interrupt Mask (PrtIntMsk) */
+	uint32_t reserved_23_23               : 1;
+	uint32_t fetsuspmsk                   : 1;  /**< Data Fetch Suspended Mask (FetSuspMsk) */
+	uint32_t incomplpmsk                  : 1;  /**< Incomplete Periodic Transfer Mask (incomplPMsk)
+                                                         Incomplete Isochronous OUT Transfer Mask
+                                                         (incompISOOUTMsk) */
+	uint32_t incompisoinmsk               : 1;  /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */
+	uint32_t oepintmsk                    : 1;  /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */
+	uint32_t inepintmsk                   : 1;  /**< IN Endpoints Interrupt Mask (INEPIntMsk) */
+	uint32_t epmismsk                     : 1;  /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */
+	uint32_t reserved_16_16               : 1;
+	uint32_t eopfmsk                      : 1;  /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */
+	uint32_t isooutdropmsk                : 1;  /**< Isochronous OUT Packet Dropped Interrupt Mask
+                                                         (ISOOutDropMsk) */
+	uint32_t enumdonemsk                  : 1;  /**< Enumeration Done Mask (EnumDoneMsk) */
+	uint32_t usbrstmsk                    : 1;  /**< USB Reset Mask (USBRstMsk) */
+	uint32_t usbsuspmsk                   : 1;  /**< USB Suspend Mask (USBSuspMsk) */
+	uint32_t erlysuspmsk                  : 1;  /**< Early Suspend Mask (ErlySuspMsk) */
+	uint32_t i2cint                       : 1;  /**< I2C Interrupt Mask (I2CINT) */
+	uint32_t ulpickintmsk                 : 1;  /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk)
+                                                         I2C Carkit Interrupt Mask (I2CCKINTMsk) */
+	uint32_t goutnakeffmsk                : 1;  /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */
+	uint32_t ginnakeffmsk                 : 1;  /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */
+	uint32_t nptxfempmsk                  : 1;  /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */
+	uint32_t rxflvlmsk                    : 1;  /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */
+	uint32_t sofmsk                       : 1;  /**< Start of (micro)Frame Mask (SofMsk) */
+	uint32_t otgintmsk                    : 1;  /**< OTG Interrupt Mask (OTGIntMsk) */
+	uint32_t modemismsk                   : 1;  /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */
+	uint32_t reserved_0_0                 : 1;
+#else
+	uint32_t reserved_0_0                 : 1;
+	uint32_t modemismsk                   : 1;
+	uint32_t otgintmsk                    : 1;
+	uint32_t sofmsk                       : 1;
+	uint32_t rxflvlmsk                    : 1;
+	uint32_t nptxfempmsk                  : 1;
+	uint32_t ginnakeffmsk                 : 1;
+	uint32_t goutnakeffmsk                : 1;
+	uint32_t ulpickintmsk                 : 1;
+	uint32_t i2cint                       : 1;
+	uint32_t erlysuspmsk                  : 1;
+	uint32_t usbsuspmsk                   : 1;
+	uint32_t usbrstmsk                    : 1;
+	uint32_t enumdonemsk                  : 1;
+	uint32_t isooutdropmsk                : 1;
+	uint32_t eopfmsk                      : 1;
+	uint32_t reserved_16_16               : 1;
+	uint32_t epmismsk                     : 1;
+	uint32_t inepintmsk                   : 1;
+	uint32_t oepintmsk                    : 1;
+	uint32_t incompisoinmsk               : 1;
+	uint32_t incomplpmsk                  : 1;
+	uint32_t fetsuspmsk                   : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t prtintmsk                    : 1;
+	uint32_t hchintmsk                    : 1;
+	uint32_t ptxfempmsk                   : 1;
+	uint32_t reserved_27_27               : 1;
+	uint32_t conidstschngmsk              : 1;
+	uint32_t disconnintmsk                : 1;
+	uint32_t sessreqintmsk                : 1;
+	uint32_t wkupintmsk                   : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_gintmsk_s           cn30xx;
+	struct cvmx_usbcx_gintmsk_s           cn31xx;
+	struct cvmx_usbcx_gintmsk_s           cn50xx;
+	struct cvmx_usbcx_gintmsk_s           cn52xx;
+	struct cvmx_usbcx_gintmsk_s           cn52xxp1;
+	struct cvmx_usbcx_gintmsk_s           cn56xx;
+	struct cvmx_usbcx_gintmsk_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
+
+/**
+ * cvmx_usbc#_gintsts
+ *
+ * Core Interrupt Register (GINTSTS)
+ *
+ * This register interrupts the application for system-level events in the current mode of operation
+ * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
+ * while others are valid in Device mode only. This register also indicates the current mode of operation.
+ * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
+ * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
+ * interrupts, FIFO interrupt conditions are cleared automatically.
+ */
+union cvmx_usbcx_gintsts
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gintsts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t wkupint                      : 1;  /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
+                                                         In Device mode, this interrupt is asserted when a resume is
+                                                         detected on the USB. In Host mode, this interrupt is asserted
+                                                         when a remote wakeup is detected on the USB.
+                                                         For more information on how to use this interrupt, see "Partial
+                                                         Power-Down and Clock Gating Programming Model" on
+                                                         page 353. */
+	uint32_t sessreqint                   : 1;  /**< Session Request/New Session Detected Interrupt (SessReqInt)
+                                                         In Host mode, this interrupt is asserted when a session request
+                                                         is detected from the device. In Device mode, this interrupt is
+                                                         asserted when the utmiotg_bvalid signal goes high.
+                                                         For more information on how to use this interrupt, see "Partial
+                                                         Power-Down and Clock Gating Programming Model" on
+                                                         page 353. */
+	uint32_t disconnint                   : 1;  /**< Disconnect Detected Interrupt (DisconnInt)
+                                                         Asserted when a device disconnect is detected. */
+	uint32_t conidstschng                 : 1;  /**< Connector ID Status Change (ConIDStsChng)
+                                                         The core sets this bit when there is a change in connector ID
+                                                         status. */
+	uint32_t reserved_27_27               : 1;
+	uint32_t ptxfemp                      : 1;  /**< Periodic TxFIFO Empty (PTxFEmp)
+                                                         Asserted when the Periodic Transmit FIFO is either half or
+                                                         completely empty and there is space for at least one entry to be
+                                                         written in the Periodic Request Queue. The half or completely
+                                                         empty status is determined by the Periodic TxFIFO Empty Level
+                                                         bit in the Core AHB Configuration register
+                                                         (GAHBCFG.PTxFEmpLvl). */
+	uint32_t hchint                       : 1;  /**< Host Channels Interrupt (HChInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the channels of the core (in Host mode). The application
+                                                         must read the Host All Channels Interrupt (HAINT) register to
+                                                         determine the exact number of the channel on which the
+                                                         interrupt occurred, and then read the corresponding Host
+                                                         Channel-n Interrupt (HCINTn) register to determine the exact
+                                                         cause of the interrupt. The application must clear the
+                                                         appropriate status bit in the HCINTn register to clear this bit. */
+	uint32_t prtint                       : 1;  /**< Host Port Interrupt (PrtInt)
+                                                         The core sets this bit to indicate a change in port status of one
+                                                         of the O2P USB core ports in Host mode. The application must
+                                                         read the Host Port Control and Status (HPRT) register to
+                                                         determine the exact event that caused this interrupt. The
+                                                         application must clear the appropriate status bit in the Host Port
+                                                         Control and Status register to clear this bit. */
+	uint32_t reserved_23_23               : 1;
+	uint32_t fetsusp                      : 1;  /**< Data Fetch Suspended (FetSusp)
+                                                         This interrupt is valid only in DMA mode. This interrupt indicates
+                                                         that the core has stopped fetching data for IN endpoints due to
+                                                         the unavailability of TxFIFO space or Request Queue space.
+                                                         This interrupt is used by the application for an endpoint
+                                                         mismatch algorithm. */
+	uint32_t incomplp                     : 1;  /**< Incomplete Periodic Transfer (incomplP)
+                                                         In Host mode, the core sets this interrupt bit when there are
+                                                         incomplete periodic transactions still pending which are
+                                                         scheduled for the current microframe.
+                                                         Incomplete Isochronous OUT Transfer (incompISOOUT)
+                                                         The Device mode, the core sets this interrupt to indicate that
+                                                         there is at least one isochronous OUT endpoint on which the
+                                                         transfer is not completed in the current microframe. This
+                                                         interrupt is asserted along with the End of Periodic Frame
+                                                         Interrupt (EOPF) bit in this register. */
+	uint32_t incompisoin                  : 1;  /**< Incomplete Isochronous IN Transfer (incompISOIN)
+                                                         The core sets this interrupt to indicate that there is at least one
+                                                         isochronous IN endpoint on which the transfer is not completed
+                                                         in the current microframe. This interrupt is asserted along with
+                                                         the End of Periodic Frame Interrupt (EOPF) bit in this register. */
+	uint32_t oepint                       : 1;  /**< OUT Endpoints Interrupt (OEPInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the OUT endpoints of the core (in Device mode). The
+                                                         application must read the Device All Endpoints Interrupt
+                                                         (DAINT) register to determine the exact number of the OUT
+                                                         endpoint on which the interrupt occurred, and then read the
+                                                         corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
+                                                         register to determine the exact cause of the interrupt. The
+                                                         application must clear the appropriate status bit in the
+                                                         corresponding DOEPINTn register to clear this bit. */
+	uint32_t iepint                       : 1;  /**< IN Endpoints Interrupt (IEPInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the IN endpoints of the core (in Device mode). The
+                                                         application must read the Device All Endpoints Interrupt
+                                                         (DAINT) register to determine the exact number of the IN
+                                                         endpoint on which the interrupt occurred, and then read the
+                                                         corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
+                                                         register to determine the exact cause of the interrupt. The
+                                                         application must clear the appropriate status bit in the
+                                                         corresponding DIEPINTn register to clear this bit. */
+	uint32_t epmis                        : 1;  /**< Endpoint Mismatch Interrupt (EPMis)
+                                                         Indicates that an IN token has been received for a non-periodic
+                                                         endpoint, but the data for another endpoint is present in the top
+                                                         of the Non-Periodic Transmit FIFO and the IN endpoint
+                                                         mismatch count programmed by the application has expired. */
+	uint32_t reserved_16_16               : 1;
+	uint32_t eopf                         : 1;  /**< End of Periodic Frame Interrupt (EOPF)
+                                                         Indicates that the period specified in the Periodic Frame Interval
+                                                         field of the Device Configuration register (DCFG.PerFrInt) has
+                                                         been reached in the current microframe. */
+	uint32_t isooutdrop                   : 1;  /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
+                                                         The core sets this bit when it fails to write an isochronous OUT
+                                                         packet into the RxFIFO because the RxFIFO doesn't have
+                                                         enough space to accommodate a maximum packet size packet
+                                                         for the isochronous OUT endpoint. */
+	uint32_t enumdone                     : 1;  /**< Enumeration Done (EnumDone)
+                                                         The core sets this bit to indicate that speed enumeration is
+                                                         complete. The application must read the Device Status (DSTS)
+                                                         register to obtain the enumerated speed. */
+	uint32_t usbrst                       : 1;  /**< USB Reset (USBRst)
+                                                         The core sets this bit to indicate that a reset is detected on the
+                                                         USB. */
+	uint32_t usbsusp                      : 1;  /**< USB Suspend (USBSusp)
+                                                         The core sets this bit to indicate that a suspend was detected
+                                                         on the USB. The core enters the Suspended state when there
+                                                         is no activity on the phy_line_state_i signal for an extended
+                                                         period of time. */
+	uint32_t erlysusp                     : 1;  /**< Early Suspend (ErlySusp)
+                                                         The core sets this bit to indicate that an Idle state has been
+                                                         detected on the USB for 3 ms. */
+	uint32_t i2cint                       : 1;  /**< I2C Interrupt (I2CINT)
+                                                         This bit is always 0x0. */
+	uint32_t ulpickint                    : 1;  /**< ULPI Carkit Interrupt (ULPICKINT)
+                                                         This bit is always 0x0. */
+	uint32_t goutnakeff                   : 1;  /**< Global OUT NAK Effective (GOUTNakEff)
+                                                         Indicates that the Set Global OUT NAK bit in the Device Control
+                                                         register (DCTL.SGOUTNak), set by the application, has taken
+                                                         effect in the core. This bit can be cleared by writing the Clear
+                                                         Global OUT NAK bit in the Device Control register
+                                                         (DCTL.CGOUTNak). */
+	uint32_t ginnakeff                    : 1;  /**< Global IN Non-Periodic NAK Effective (GINNakEff)
+                                                         Indicates that the Set Global Non-Periodic IN NAK bit in the
+                                                         Device Control register (DCTL.SGNPInNak), set by the
+                                                         application, has taken effect in the core. That is, the core has
+                                                         sampled the Global IN NAK bit set by the application. This bit
+                                                         can be cleared by clearing the Clear Global Non-Periodic IN
+                                                         NAK bit in the Device Control register (DCTL.CGNPInNak).
+                                                         This interrupt does not necessarily mean that a NAK handshake
+                                                         is sent out on the USB. The STALL bit takes precedence over
+                                                         the NAK bit. */
+	uint32_t nptxfemp                     : 1;  /**< Non-Periodic TxFIFO Empty (NPTxFEmp)
+                                                         This interrupt is asserted when the Non-Periodic TxFIFO is
+                                                         either half or completely empty, and there is space for at least
+                                                         one entry to be written to the Non-Periodic Transmit Request
+                                                         Queue. The half or completely empty status is determined by
+                                                         the Non-Periodic TxFIFO Empty Level bit in the Core AHB
+                                                         Configuration register (GAHBCFG.NPTxFEmpLvl). */
+	uint32_t rxflvl                       : 1;  /**< RxFIFO Non-Empty (RxFLvl)
+                                                         Indicates that there is at least one packet pending to be read
+                                                         from the RxFIFO. */
+	uint32_t sof                          : 1;  /**< Start of (micro)Frame (Sof)
+                                                         In Host mode, the core sets this bit to indicate that an SOF
+                                                         (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
+                                                         USB. The application must write a 1 to this bit to clear the
+                                                         interrupt.
+                                                         In Device mode, in the core sets this bit to indicate that an SOF
+                                                         token has been received on the USB. The application can read
+                                                         the Device Status register to get the current (micro)frame
+                                                         number. This interrupt is seen only when the core is operating
+                                                         at either HS or FS. */
+	uint32_t otgint                       : 1;  /**< OTG Interrupt (OTGInt)
+                                                         The core sets this bit to indicate an OTG protocol event. The
+                                                         application must read the OTG Interrupt Status (GOTGINT)
+                                                         register to determine the exact event that caused this interrupt.
+                                                         The application must clear the appropriate status bit in the
+                                                         GOTGINT register to clear this bit. */
+	uint32_t modemis                      : 1;  /**< Mode Mismatch Interrupt (ModeMis)
+                                                         The core sets this bit when the application is trying to access:
+                                                         * A Host mode register, when the core is operating in Device
+                                                         mode
+                                                         * A Device mode register, when the core is operating in Host
+                                                           mode
+                                                           The register access is completed on the AHB with an OKAY
+                                                           response, but is ignored by the core internally and doesn't
+                                                         affect the operation of the core. */
+	uint32_t curmod                       : 1;  /**< Current Mode of Operation (CurMod)
+                                                         Indicates the current mode of operation.
+                                                         * 1'b0: Device mode
+                                                         * 1'b1: Host mode */
+#else
+	uint32_t curmod                       : 1;
+	uint32_t modemis                      : 1;
+	uint32_t otgint                       : 1;
+	uint32_t sof                          : 1;
+	uint32_t rxflvl                       : 1;
+	uint32_t nptxfemp                     : 1;
+	uint32_t ginnakeff                    : 1;
+	uint32_t goutnakeff                   : 1;
+	uint32_t ulpickint                    : 1;
+	uint32_t i2cint                       : 1;
+	uint32_t erlysusp                     : 1;
+	uint32_t usbsusp                      : 1;
+	uint32_t usbrst                       : 1;
+	uint32_t enumdone                     : 1;
+	uint32_t isooutdrop                   : 1;
+	uint32_t eopf                         : 1;
+	uint32_t reserved_16_16               : 1;
+	uint32_t epmis                        : 1;
+	uint32_t iepint                       : 1;
+	uint32_t oepint                       : 1;
+	uint32_t incompisoin                  : 1;
+	uint32_t incomplp                     : 1;
+	uint32_t fetsusp                      : 1;
+	uint32_t reserved_23_23               : 1;
+	uint32_t prtint                       : 1;
+	uint32_t hchint                       : 1;
+	uint32_t ptxfemp                      : 1;
+	uint32_t reserved_27_27               : 1;
+	uint32_t conidstschng                 : 1;
+	uint32_t disconnint                   : 1;
+	uint32_t sessreqint                   : 1;
+	uint32_t wkupint                      : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_gintsts_s           cn30xx;
+	struct cvmx_usbcx_gintsts_s           cn31xx;
+	struct cvmx_usbcx_gintsts_s           cn50xx;
+	struct cvmx_usbcx_gintsts_s           cn52xx;
+	struct cvmx_usbcx_gintsts_s           cn52xxp1;
+	struct cvmx_usbcx_gintsts_s           cn56xx;
+	struct cvmx_usbcx_gintsts_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
+
+/**
+ * cvmx_usbc#_gnptxfsiz
+ *
+ * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
+ *
+ * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
+ */
+union cvmx_usbcx_gnptxfsiz
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gnptxfsiz_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t nptxfdep                     : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep)
+                                                         This value is in terms of 32-bit words.
+                                                         Minimum value is 16
+                                                         Maximum value is 32768 */
+	uint32_t nptxfstaddr                  : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
+                                                         This field contains the memory start address for Non-Periodic
+                                                         Transmit FIFO RAM. */
+#else
+	uint32_t nptxfstaddr                  : 16;
+	uint32_t nptxfdep                     : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_gnptxfsiz_s         cn30xx;
+	struct cvmx_usbcx_gnptxfsiz_s         cn31xx;
+	struct cvmx_usbcx_gnptxfsiz_s         cn50xx;
+	struct cvmx_usbcx_gnptxfsiz_s         cn52xx;
+	struct cvmx_usbcx_gnptxfsiz_s         cn52xxp1;
+	struct cvmx_usbcx_gnptxfsiz_s         cn56xx;
+	struct cvmx_usbcx_gnptxfsiz_s         cn56xxp1;
+};
+typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
+
+/**
+ * cvmx_usbc#_gnptxsts
+ *
+ * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
+ *
+ * This read-only register contains the free space information for the Non-Periodic TxFIFO and
+ * the Non-Periodic Transmit Request Queue
+ */
+union cvmx_usbcx_gnptxsts
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gnptxsts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_31_31               : 1;
+	uint32_t nptxqtop                     : 7;  /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
+                                                         Entry in the Non-Periodic Tx Request Queue that is currently
+                                                         being processed by the MAC.
+                                                         * Bits [30:27]: Channel/endpoint number
+                                                         * Bits [26:25]:
+                                                           - 2'b00: IN/OUT token
+                                                           - 2'b01: Zero-length transmit packet (device IN/host OUT)
+                                                           - 2'b10: PING/CSPLIT token
+                                                           - 2'b11: Channel halt command
+                                                         * Bit [24]: Terminate (last entry for selected channel/endpoint) */
+	uint32_t nptxqspcavail                : 8;  /**< Non-Periodic Transmit Request Queue Space Available
+                                                         (NPTxQSpcAvail)
+                                                         Indicates the amount of free space available in the Non-
+                                                         Periodic Transmit Request Queue. This queue holds both IN
+                                                         and OUT requests in Host mode. Device mode has only IN
+                                                         requests.
+                                                         * 8'h0: Non-Periodic Transmit Request Queue is full
+                                                         * 8'h1: 1 location available
+                                                         * 8'h2: 2 locations available
+                                                         * n: n locations available (0..8)
+                                                         * Others: Reserved */
+	uint32_t nptxfspcavail                : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
+                                                         Indicates the amount of free space available in the Non-
+                                                         Periodic TxFIFO.
+                                                         Values are in terms of 32-bit words.
+                                                         * 16'h0: Non-Periodic TxFIFO is full
+                                                         * 16'h1: 1 word available
+                                                         * 16'h2: 2 words available
+                                                         * 16'hn: n words available (where 0..32768)
+                                                         * 16'h8000: 32768 words available
+                                                         * Others: Reserved */
+#else
+	uint32_t nptxfspcavail                : 16;
+	uint32_t nptxqspcavail                : 8;
+	uint32_t nptxqtop                     : 7;
+	uint32_t reserved_31_31               : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_gnptxsts_s          cn30xx;
+	struct cvmx_usbcx_gnptxsts_s          cn31xx;
+	struct cvmx_usbcx_gnptxsts_s          cn50xx;
+	struct cvmx_usbcx_gnptxsts_s          cn52xx;
+	struct cvmx_usbcx_gnptxsts_s          cn52xxp1;
+	struct cvmx_usbcx_gnptxsts_s          cn56xx;
+	struct cvmx_usbcx_gnptxsts_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
+
+/**
+ * cvmx_usbc#_gotgctl
+ *
+ * OTG Control and Status Register (GOTGCTL)
+ *
+ * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
+ */
+union cvmx_usbcx_gotgctl
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gotgctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t bsesvld                      : 1;  /**< B-Session Valid (BSesVld)
+                                                         Valid only when O2P USB core is configured as a USB device.
+                                                         Indicates the Device mode transceiver status.
+                                                         * 1'b0: B-session is not valid.
+                                                         * 1'b1: B-session is valid. */
+	uint32_t asesvld                      : 1;  /**< A-Session Valid (ASesVld)
+                                                         Valid only when O2P USB core is configured as a USB host.
+                                                         Indicates the Host mode transceiver status.
+                                                         * 1'b0: A-session is not valid
+                                                         * 1'b1: A-session is valid */
+	uint32_t dbnctime                     : 1;  /**< Long/Short Debounce Time (DbncTime)
+                                                         In the present version of the core this bit will only read as '0'. */
+	uint32_t conidsts                     : 1;  /**< Connector ID Status (ConIDSts)
+                                                         Indicates the connector ID status on a connect event.
+                                                         * 1'b0: The O2P USB core is in A-device mode
+                                                         * 1'b1: The O2P USB core is in B-device mode */
+	uint32_t reserved_12_15               : 4;
+	uint32_t devhnpen                     : 1;  /**< Device HNP Enabled (DevHNPEn)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+	uint32_t hstsethnpen                  : 1;  /**< Host Set HNP Enable (HstSetHNPEn)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+	uint32_t hnpreq                       : 1;  /**< HNP Request (HNPReq)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+	uint32_t hstnegscs                    : 1;  /**< Host Negotiation Success (HstNegScs)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+	uint32_t reserved_2_7                 : 6;
+	uint32_t sesreq                       : 1;  /**< Session Request (SesReq)
+                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
+	uint32_t sesreqscs                    : 1;  /**< Session Request Success (SesReqScs)
+                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
+#else
+	uint32_t sesreqscs                    : 1;
+	uint32_t sesreq                       : 1;
+	uint32_t reserved_2_7                 : 6;
+	uint32_t hstnegscs                    : 1;
+	uint32_t hnpreq                       : 1;
+	uint32_t hstsethnpen                  : 1;
+	uint32_t devhnpen                     : 1;
+	uint32_t reserved_12_15               : 4;
+	uint32_t conidsts                     : 1;
+	uint32_t dbnctime                     : 1;
+	uint32_t asesvld                      : 1;
+	uint32_t bsesvld                      : 1;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_usbcx_gotgctl_s           cn30xx;
+	struct cvmx_usbcx_gotgctl_s           cn31xx;
+	struct cvmx_usbcx_gotgctl_s           cn50xx;
+	struct cvmx_usbcx_gotgctl_s           cn52xx;
+	struct cvmx_usbcx_gotgctl_s           cn52xxp1;
+	struct cvmx_usbcx_gotgctl_s           cn56xx;
+	struct cvmx_usbcx_gotgctl_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t;
+
+/**
+ * cvmx_usbc#_gotgint
+ *
+ * OTG Interrupt Register (GOTGINT)
+ *
+ * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
+ * to clear the OTG interrupt. It is shown in Interrupt .:
+ */
+union cvmx_usbcx_gotgint
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gotgint_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_20_31               : 12;
+	uint32_t dbncedone                    : 1;  /**< Debounce Done (DbnceDone)
+                                                         In the present version of the code this bit is tied to '0'. */
+	uint32_t adevtoutchg                  : 1;  /**< A-Device Timeout Change (ADevTOUTChg)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+	uint32_t hstnegdet                    : 1;  /**< Host Negotiation Detected (HstNegDet)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+	uint32_t reserved_10_16               : 7;
+	uint32_t hstnegsucstschng             : 1;  /**< Host Negotiation Success Status Change (HstNegSucStsChng)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+	uint32_t sesreqsucstschng             : 1;  /**< Session Request Success Status Change
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+	uint32_t reserved_3_7                 : 5;
+	uint32_t sesenddet                    : 1;  /**< Session End Detected (SesEndDet)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+	uint32_t reserved_0_1                 : 2;
+#else
+	uint32_t reserved_0_1                 : 2;
+	uint32_t sesenddet                    : 1;
+	uint32_t reserved_3_7                 : 5;
+	uint32_t sesreqsucstschng             : 1;
+	uint32_t hstnegsucstschng             : 1;
+	uint32_t reserved_10_16               : 7;
+	uint32_t hstnegdet                    : 1;
+	uint32_t adevtoutchg                  : 1;
+	uint32_t dbncedone                    : 1;
+	uint32_t reserved_20_31               : 12;
+#endif
+	} s;
+	struct cvmx_usbcx_gotgint_s           cn30xx;
+	struct cvmx_usbcx_gotgint_s           cn31xx;
+	struct cvmx_usbcx_gotgint_s           cn50xx;
+	struct cvmx_usbcx_gotgint_s           cn52xx;
+	struct cvmx_usbcx_gotgint_s           cn52xxp1;
+	struct cvmx_usbcx_gotgint_s           cn56xx;
+	struct cvmx_usbcx_gotgint_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t;
+
+/**
+ * cvmx_usbc#_grstctl
+ *
+ * Core Reset Register (GRSTCTL)
+ *
+ * The application uses this register to reset various hardware features inside the core.
+ */
+union cvmx_usbcx_grstctl
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grstctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ahbidle                      : 1;  /**< AHB Master Idle (AHBIdle)
+                                                         Indicates that the AHB Master State Machine is in the IDLE
+                                                         condition. */
+	uint32_t dmareq                       : 1;  /**< DMA Request Signal (DMAReq)
+                                                         Indicates that the DMA request is in progress. Used for debug. */
+	uint32_t reserved_11_29               : 19;
+	uint32_t txfnum                       : 5;  /**< TxFIFO Number (TxFNum)
+                                                         This is the FIFO number that must be flushed using the TxFIFO
+                                                         Flush bit. This field must not be changed until the core clears
+                                                         the TxFIFO Flush bit.
+                                                         * 5'h0: Non-Periodic TxFIFO flush
+                                                         * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
+                                                         TxFIFO flush in Host mode
+                                                         * 5'h2: Periodic TxFIFO 2 flush in Device mode
+                                                         - ...
+                                                         * 5'hF: Periodic TxFIFO 15 flush in Device mode
+                                                         * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
+                                                         core */
+	uint32_t txfflsh                      : 1;  /**< TxFIFO Flush (TxFFlsh)
+                                                         This bit selectively flushes a single or all transmit FIFOs, but
+                                                         cannot do so if the core is in the midst of a transaction.
+                                                         The application must only write this bit after checking that the
+                                                         core is neither writing to the TxFIFO nor reading from the
+                                                         TxFIFO.
+                                                         The application must wait until the core clears this bit before
+                                                         performing any operations. This bit takes 8 clocks (of phy_clk or
+                                                         hclk, whichever is slower) to clear. */
+	uint32_t rxfflsh                      : 1;  /**< RxFIFO Flush (RxFFlsh)
+                                                         The application can flush the entire RxFIFO using this bit, but
+                                                         must first ensure that the core is not in the middle of a
+                                                         transaction.
+                                                         The application must only write to this bit after checking that the
+                                                         core is neither reading from the RxFIFO nor writing to the
+                                                         RxFIFO.
+                                                         The application must wait until the bit is cleared before
+                                                         performing any other operations. This bit will take 8 clocks
+                                                         (slowest of PHY or AHB clock) to clear. */
+	uint32_t intknqflsh                   : 1;  /**< IN Token Sequence Learning Queue Flush (INTknQFlsh)
+                                                         The application writes this bit to flush the IN Token Sequence
+                                                         Learning Queue. */
+	uint32_t frmcntrrst                   : 1;  /**< Host Frame Counter Reset (FrmCntrRst)
+                                                         The application writes this bit to reset the (micro)frame number
+                                                         counter inside the core. When the (micro)frame counter is reset,
+                                                         the subsequent SOF sent out by the core will have a
+                                                         (micro)frame number of 0. */
+	uint32_t hsftrst                      : 1;  /**< HClk Soft Reset (HSftRst)
+                                                         The application uses this bit to flush the control logic in the AHB
+                                                         Clock domain. Only AHB Clock Domain pipelines are reset.
+                                                         * FIFOs are not flushed with this bit.
+                                                         * All state machines in the AHB clock domain are reset to the
+                                                           Idle state after terminating the transactions on the AHB,
+                                                           following the protocol.
+                                                         * CSR control bits used by the AHB clock domain state
+                                                           machines are cleared.
+                                                         * To clear this interrupt, status mask bits that control the
+                                                           interrupt status and are generated by the AHB clock domain
+                                                           state machine are cleared.
+                                                         * Because interrupt status bits are not cleared, the application
+                                                           can get the status of any core events that occurred after it set
+                                                           this bit.
+                                                           This is a self-clearing bit that the core clears after all necessary
+                                                           logic is reset in the core. This may take several clocks,
+                                                           depending on the core's current state. */
+	uint32_t csftrst                      : 1;  /**< Core Soft Reset (CSftRst)
+                                                         Resets the hclk and phy_clock domains as follows:
+                                                         * Clears the interrupts and all the CSR registers except the
+                                                           following register bits:
+                                                           - PCGCCTL.RstPdwnModule
+                                                           - PCGCCTL.GateHclk
+                                                           - PCGCCTL.PwrClmp
+                                                           - PCGCCTL.StopPPhyLPwrClkSelclk
+                                                           - GUSBCFG.PhyLPwrClkSel
+                                                           - GUSBCFG.DDRSel
+                                                           - GUSBCFG.PHYSel
+                                                           - GUSBCFG.FSIntf
+                                                           - GUSBCFG.ULPI_UTMI_Sel
+                                                           - GUSBCFG.PHYIf
+                                                           - HCFG.FSLSPclkSel
+                                                           - DCFG.DevSpd
+                                                         * All module state machines (except the AHB Slave Unit) are
+                                                           reset to the IDLE state, and all the transmit FIFOs and the
+                                                           receive FIFO are flushed.
+                                                         * Any transactions on the AHB Master are terminated as soon
+                                                           as possible, after gracefully completing the last data phase of
+                                                           an AHB transfer. Any transactions on the USB are terminated
+                                                           immediately.
+                                                           The application can write to this bit any time it wants to reset
+                                                           the core. This is a self-clearing bit and the core clears this bit
+                                                           after all the necessary logic is reset in the core, which may take
+                                                           several clocks, depending on the current state of the core.
+                                                           Once this bit is cleared software should wait at least 3 PHY
+                                                           clocks before doing any access to the PHY domain
+                                                           (synchronization delay). Software should also should check that
+                                                           bit 31 of this register is 1 (AHB Master is IDLE) before starting
+                                                           any operation.
+                                                           Typically software reset is used during software development
+                                                           and also when you dynamically change the PHY selection bits
+                                                           in the USB configuration registers listed above. When you
+                                                           change the PHY, the corresponding clock for the PHY is
+                                                           selected and used in the PHY domain. Once a new clock is
+                                                           selected, the PHY domain has to be reset for proper operation. */
+#else
+	uint32_t csftrst                      : 1;
+	uint32_t hsftrst                      : 1;
+	uint32_t frmcntrrst                   : 1;
+	uint32_t intknqflsh                   : 1;
+	uint32_t rxfflsh                      : 1;
+	uint32_t txfflsh                      : 1;
+	uint32_t txfnum                       : 5;
+	uint32_t reserved_11_29               : 19;
+	uint32_t dmareq                       : 1;
+	uint32_t ahbidle                      : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_grstctl_s           cn30xx;
+	struct cvmx_usbcx_grstctl_s           cn31xx;
+	struct cvmx_usbcx_grstctl_s           cn50xx;
+	struct cvmx_usbcx_grstctl_s           cn52xx;
+	struct cvmx_usbcx_grstctl_s           cn52xxp1;
+	struct cvmx_usbcx_grstctl_s           cn56xx;
+	struct cvmx_usbcx_grstctl_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
+
+/**
+ * cvmx_usbc#_grxfsiz
+ *
+ * Receive FIFO Size Register (GRXFSIZ)
+ *
+ * The application can program the RAM size that must be allocated to the RxFIFO.
+ */
+union cvmx_usbcx_grxfsiz
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grxfsiz_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t rxfdep                       : 16; /**< RxFIFO Depth (RxFDep)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 16
+                                                         * Maximum value is 32768 */
+#else
+	uint32_t rxfdep                       : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_grxfsiz_s           cn30xx;
+	struct cvmx_usbcx_grxfsiz_s           cn31xx;
+	struct cvmx_usbcx_grxfsiz_s           cn50xx;
+	struct cvmx_usbcx_grxfsiz_s           cn52xx;
+	struct cvmx_usbcx_grxfsiz_s           cn52xxp1;
+	struct cvmx_usbcx_grxfsiz_s           cn56xx;
+	struct cvmx_usbcx_grxfsiz_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
+
+/**
+ * cvmx_usbc#_grxstspd
+ *
+ * Receive Status Debug Read Register, Device Mode (GRXSTSPD)
+ *
+ * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
+ * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSPH instead.
+ * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+union cvmx_usbcx_grxstspd
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grxstspd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_25_31               : 7;
+	uint32_t fn                           : 4;  /**< Frame Number (FN)
+                                                         This is the least significant 4 bits of the (micro)frame number in
+                                                         which the packet is received on the USB.  This field is supported
+                                                         only when the isochronous OUT endpoints are supported. */
+	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
+                                                         * 4'b0010: OUT data packet received
+                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
+                                                         * 4'b0110: SETUP data packet received
+                                                         * Others: Reserved */
+	uint32_t dpid                         : 2;  /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+	uint32_t bcnt                         : 11; /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received data packet */
+	uint32_t epnum                        : 4;  /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number to which the current received
+                                                         packet belongs. */
+#else
+	uint32_t epnum                        : 4;
+	uint32_t bcnt                         : 11;
+	uint32_t dpid                         : 2;
+	uint32_t pktsts                       : 4;
+	uint32_t fn                           : 4;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_usbcx_grxstspd_s          cn30xx;
+	struct cvmx_usbcx_grxstspd_s          cn31xx;
+	struct cvmx_usbcx_grxstspd_s          cn50xx;
+	struct cvmx_usbcx_grxstspd_s          cn52xx;
+	struct cvmx_usbcx_grxstspd_s          cn52xxp1;
+	struct cvmx_usbcx_grxstspd_s          cn56xx;
+	struct cvmx_usbcx_grxstspd_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t;
+
+/**
+ * cvmx_usbc#_grxstsph
+ *
+ * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
+ *
+ * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
+ * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSPD instead.
+ * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+union cvmx_usbcx_grxstsph
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grxstsph_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0010: IN data packet received
+                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
+                                                         * 4'b0101: Data toggle error (triggers an interrupt)
+                                                         * 4'b0111: Channel halted (triggers an interrupt)
+                                                         * Others: Reserved */
+	uint32_t dpid                         : 2;  /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+	uint32_t bcnt                         : 11; /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received IN data packet */
+	uint32_t chnum                        : 4;  /**< Channel Number (ChNum)
+                                                         Indicates the channel number to which the current received
+                                                         packet belongs. */
+#else
+	uint32_t chnum                        : 4;
+	uint32_t bcnt                         : 11;
+	uint32_t dpid                         : 2;
+	uint32_t pktsts                       : 4;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_usbcx_grxstsph_s          cn30xx;
+	struct cvmx_usbcx_grxstsph_s          cn31xx;
+	struct cvmx_usbcx_grxstsph_s          cn50xx;
+	struct cvmx_usbcx_grxstsph_s          cn52xx;
+	struct cvmx_usbcx_grxstsph_s          cn52xxp1;
+	struct cvmx_usbcx_grxstsph_s          cn56xx;
+	struct cvmx_usbcx_grxstsph_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
+
+/**
+ * cvmx_usbc#_grxstsrd
+ *
+ * Receive Status Debug Read Register, Device Mode (GRXSTSRD)
+ *
+ * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
+ * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSRH instead.
+ * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+union cvmx_usbcx_grxstsrd
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grxstsrd_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_25_31               : 7;
+	uint32_t fn                           : 4;  /**< Frame Number (FN)
+                                                         This is the least significant 4 bits of the (micro)frame number in
+                                                         which the packet is received on the USB.  This field is supported
+                                                         only when the isochronous OUT endpoints are supported. */
+	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
+                                                         * 4'b0010: OUT data packet received
+                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
+                                                         * 4'b0110: SETUP data packet received
+                                                         * Others: Reserved */
+	uint32_t dpid                         : 2;  /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+	uint32_t bcnt                         : 11; /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received data packet */
+	uint32_t epnum                        : 4;  /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number to which the current received
+                                                         packet belongs. */
+#else
+	uint32_t epnum                        : 4;
+	uint32_t bcnt                         : 11;
+	uint32_t dpid                         : 2;
+	uint32_t pktsts                       : 4;
+	uint32_t fn                           : 4;
+	uint32_t reserved_25_31               : 7;
+#endif
+	} s;
+	struct cvmx_usbcx_grxstsrd_s          cn30xx;
+	struct cvmx_usbcx_grxstsrd_s          cn31xx;
+	struct cvmx_usbcx_grxstsrd_s          cn50xx;
+	struct cvmx_usbcx_grxstsrd_s          cn52xx;
+	struct cvmx_usbcx_grxstsrd_s          cn52xxp1;
+	struct cvmx_usbcx_grxstsrd_s          cn56xx;
+	struct cvmx_usbcx_grxstsrd_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t;
+
+/**
+ * cvmx_usbc#_grxstsrh
+ *
+ * Receive Status Debug Read Register, Host Mode (GRXSTSRH)
+ *
+ * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
+ * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSRD instead.
+ * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+union cvmx_usbcx_grxstsrh
+{
+	uint32_t u32;
+	struct cvmx_usbcx_grxstsrh_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_21_31               : 11;
+	uint32_t pktsts                       : 4;  /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0010: IN data packet received
+                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
+                                                         * 4'b0101: Data toggle error (triggers an interrupt)
+                                                         * 4'b0111: Channel halted (triggers an interrupt)
+                                                         * Others: Reserved */
+	uint32_t dpid                         : 2;  /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+	uint32_t bcnt                         : 11; /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received IN data packet */
+	uint32_t chnum                        : 4;  /**< Channel Number (ChNum)
+                                                         Indicates the channel number to which the current received
+                                                         packet belongs. */
+#else
+	uint32_t chnum                        : 4;
+	uint32_t bcnt                         : 11;
+	uint32_t dpid                         : 2;
+	uint32_t pktsts                       : 4;
+	uint32_t reserved_21_31               : 11;
+#endif
+	} s;
+	struct cvmx_usbcx_grxstsrh_s          cn30xx;
+	struct cvmx_usbcx_grxstsrh_s          cn31xx;
+	struct cvmx_usbcx_grxstsrh_s          cn50xx;
+	struct cvmx_usbcx_grxstsrh_s          cn52xx;
+	struct cvmx_usbcx_grxstsrh_s          cn52xxp1;
+	struct cvmx_usbcx_grxstsrh_s          cn56xx;
+	struct cvmx_usbcx_grxstsrh_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t;
+
+/**
+ * cvmx_usbc#_gsnpsid
+ *
+ * Synopsys ID Register (GSNPSID)
+ *
+ * This is a read-only register that contains the release number of the core being used.
+ */
+union cvmx_usbcx_gsnpsid
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gsnpsid_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t synopsysid                   : 32; /**< 0x4F54\<version\>A, release number of the core being used.
+                                                         0x4F54220A => pass1.x,  0x4F54240A => pass2.x */
+#else
+	uint32_t synopsysid                   : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_gsnpsid_s           cn30xx;
+	struct cvmx_usbcx_gsnpsid_s           cn31xx;
+	struct cvmx_usbcx_gsnpsid_s           cn50xx;
+	struct cvmx_usbcx_gsnpsid_s           cn52xx;
+	struct cvmx_usbcx_gsnpsid_s           cn52xxp1;
+	struct cvmx_usbcx_gsnpsid_s           cn56xx;
+	struct cvmx_usbcx_gsnpsid_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t;
+
+/**
+ * cvmx_usbc#_gusbcfg
+ *
+ * Core USB Configuration Register (GUSBCFG)
+ *
+ * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
+ * It contains USB and USB-PHY related configuration parameters. The application must program this register
+ * before starting any transactions on either the AHB or the USB.
+ * Do not make changes to this register after the initial programming.
+ */
+union cvmx_usbcx_gusbcfg
+{
+	uint32_t u32;
+	struct cvmx_usbcx_gusbcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_17_31               : 15;
+	uint32_t otgi2csel                    : 1;  /**< UTMIFS or I2C Interface Select (OtgI2CSel)
+                                                         This bit is always 0x0. */
+	uint32_t phylpwrclksel                : 1;  /**< PHY Low-Power Clock Select (PhyLPwrClkSel)
+                                                         Software should set this bit to 0x0.
+                                                         Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
+                                                         FS and LS modes, the PHY can usually operate on a 48-MHz
+                                                         clock to save power.
+                                                         * 1'b0: 480-MHz Internal PLL clock
+                                                         * 1'b1: 48-MHz External Clock
+                                                         In 480 MHz mode, the UTMI interface operates at either 60 or
+                                                         30-MHz, depending upon whether 8- or 16-bit data width is
+                                                         selected. In 48-MHz mode, the UTMI interface operates at 48
+                                                         MHz in FS mode and at either 48 or 6 MHz in LS mode
+                                                         (depending on the PHY vendor).
+                                                         This bit drives the utmi_fsls_low_power core output signal, and
+                                                         is valid only for UTMI+ PHYs. */
+	uint32_t reserved_14_14               : 1;
+	uint32_t usbtrdtim                    : 4;  /**< USB Turnaround Time (USBTrdTim)
+                                                         Sets the turnaround time in PHY clocks.
+                                                         Specifies the response time for a MAC request to the Packet
+                                                         FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
+                                                         This must be programmed to 0x5. */
+	uint32_t hnpcap                       : 1;  /**< HNP-Capable (HNPCap)
+                                                         This bit is always 0x0. */
+	uint32_t srpcap                       : 1;  /**< SRP-Capable (SRPCap)
+                                                         This bit is always 0x0. */
+	uint32_t ddrsel                       : 1;  /**< ULPI DDR Select (DDRSel)
+                                                         Software should set this bit to 0x0. */
+	uint32_t physel                       : 1;  /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
+                                                         Software should set this bit to 0x0. */
+	uint32_t fsintf                       : 1;  /**< Full-Speed Serial Interface Select (FSIntf)
+                                                         Software should set this bit to 0x0. */
+	uint32_t ulpi_utmi_sel                : 1;  /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel)
+                                                         This bit is always 0x0. */
+	uint32_t phyif                        : 1;  /**< PHY Interface (PHYIf)
+                                                         This bit is always 0x1. */
+	uint32_t toutcal                      : 3;  /**< HS/FS Timeout Calibration (TOutCal)
+                                                         The number of PHY clocks that the application programs in this
+                                                         field is added to the high-speed/full-speed interpacket timeout
+                                                         duration in the core to account for any additional delays
+                                                         introduced by the PHY. This may be required, since the delay
+                                                         introduced by the PHY in generating the linestate condition may
+                                                         vary from one PHY to another.
+                                                         The USB standard timeout value for high-speed operation is
+                                                         736 to 816 (inclusive) bit times. The USB standard timeout
+                                                         value for full-speed operation is 16 to 18 (inclusive) bit times.
+                                                         The application must program this field based on the speed of
+                                                         enumeration. The number of bit times added per PHY clock are:
+                                                         High-speed operation:
+                                                         * One 30-MHz PHY clock = 16 bit times
+                                                         * One 60-MHz PHY clock = 8 bit times
+                                                         Full-speed operation:
+                                                         * One 30-MHz PHY clock = 0.4 bit times
+                                                         * One 60-MHz PHY clock = 0.2 bit times
+                                                         * One 48-MHz PHY clock = 0.25 bit times */
+#else
+	uint32_t toutcal                      : 3;
+	uint32_t phyif                        : 1;
+	uint32_t ulpi_utmi_sel                : 1;
+	uint32_t fsintf                       : 1;
+	uint32_t physel                       : 1;
+	uint32_t ddrsel                       : 1;
+	uint32_t srpcap                       : 1;
+	uint32_t hnpcap                       : 1;
+	uint32_t usbtrdtim                    : 4;
+	uint32_t reserved_14_14               : 1;
+	uint32_t phylpwrclksel                : 1;
+	uint32_t otgi2csel                    : 1;
+	uint32_t reserved_17_31               : 15;
+#endif
+	} s;
+	struct cvmx_usbcx_gusbcfg_s           cn30xx;
+	struct cvmx_usbcx_gusbcfg_s           cn31xx;
+	struct cvmx_usbcx_gusbcfg_s           cn50xx;
+	struct cvmx_usbcx_gusbcfg_s           cn52xx;
+	struct cvmx_usbcx_gusbcfg_s           cn52xxp1;
+	struct cvmx_usbcx_gusbcfg_s           cn56xx;
+	struct cvmx_usbcx_gusbcfg_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
+
+/**
+ * cvmx_usbc#_haint
+ *
+ * Host All Channels Interrupt Register (HAINT)
+ *
+ * When a significant event occurs on a channel, the Host All Channels Interrupt register
+ * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
+ * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
+ * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
+ * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
+ */
+union cvmx_usbcx_haint
+{
+	uint32_t u32;
+	struct cvmx_usbcx_haint_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t haint                        : 16; /**< Channel Interrupts (HAINT)
+                                                         One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
+#else
+	uint32_t haint                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_haint_s             cn30xx;
+	struct cvmx_usbcx_haint_s             cn31xx;
+	struct cvmx_usbcx_haint_s             cn50xx;
+	struct cvmx_usbcx_haint_s             cn52xx;
+	struct cvmx_usbcx_haint_s             cn52xxp1;
+	struct cvmx_usbcx_haint_s             cn56xx;
+	struct cvmx_usbcx_haint_s             cn56xxp1;
+};
+typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
+
+/**
+ * cvmx_usbc#_haintmsk
+ *
+ * Host All Channels Interrupt Mask Register (HAINTMSK)
+ *
+ * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
+ * register to interrupt the application when an event occurs on a channel. There is one
+ * interrupt mask bit per channel, up to a maximum of 16 bits.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+union cvmx_usbcx_haintmsk
+{
+	uint32_t u32;
+	struct cvmx_usbcx_haintmsk_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t haintmsk                     : 16; /**< Channel Interrupt Mask (HAINTMsk)
+                                                         One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
+#else
+	uint32_t haintmsk                     : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_haintmsk_s          cn30xx;
+	struct cvmx_usbcx_haintmsk_s          cn31xx;
+	struct cvmx_usbcx_haintmsk_s          cn50xx;
+	struct cvmx_usbcx_haintmsk_s          cn52xx;
+	struct cvmx_usbcx_haintmsk_s          cn52xxp1;
+	struct cvmx_usbcx_haintmsk_s          cn56xx;
+	struct cvmx_usbcx_haintmsk_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
+
+/**
+ * cvmx_usbc#_hcchar#
+ *
+ * Host Channel-n Characteristics Register (HCCHAR)
+ *
+ */
+union cvmx_usbcx_hccharx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hccharx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t chena                        : 1;  /**< Channel Enable (ChEna)
+                                                         This field is set by the application and cleared by the OTG host.
+                                                         * 1'b0: Channel disabled
+                                                         * 1'b1: Channel enabled */
+	uint32_t chdis                        : 1;  /**< Channel Disable (ChDis)
+                                                         The application sets this bit to stop transmitting/receiving data
+                                                         on a channel, even before the transfer for that channel is
+                                                         complete. The application must wait for the Channel Disabled
+                                                         interrupt before treating the channel as disabled. */
+	uint32_t oddfrm                       : 1;  /**< Odd Frame (OddFrm)
+                                                         This field is set (reset) by the application to indicate that the
+                                                         OTG host must perform a transfer in an odd (micro)frame. This
+                                                         field is applicable for only periodic (isochronous and interrupt)
+                                                         transactions.
+                                                         * 1'b0: Even (micro)frame
+                                                         * 1'b1: Odd (micro)frame */
+	uint32_t devaddr                      : 7;  /**< Device Address (DevAddr)
+                                                         This field selects the specific device serving as the data source
+                                                         or sink. */
+	uint32_t ec                           : 2;  /**< Multi Count (MC) / Error Count (EC)
+                                                         When the Split Enable bit of the Host Channel-n Split Control
+                                                         register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
+                                                         to the host the number of transactions that should be executed
+                                                         per microframe for this endpoint.
+                                                         * 2'b00: Reserved. This field yields undefined results.
+                                                         * 2'b01: 1 transaction
+                                                         * 2'b10: 2 transactions to be issued for this endpoint per
+                                                                  microframe
+                                                         * 2'b11: 3 transactions to be issued for this endpoint per
+                                                                  microframe
+                                                         When HCSPLTn.SpltEna is set (1'b1), this field indicates the
+                                                         number of immediate retries to be performed for a periodic split
+                                                         transactions on transaction errors. This field must be set to at
+                                                         least 2'b01. */
+	uint32_t eptype                       : 2;  /**< Endpoint Type (EPType)
+                                                         Indicates the transfer type selected.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+	uint32_t lspddev                      : 1;  /**< Low-Speed Device (LSpdDev)
+                                                         This field is set by the application to indicate that this channel is
+                                                         communicating to a low-speed device. */
+	uint32_t reserved_16_16               : 1;
+	uint32_t epdir                        : 1;  /**< Endpoint Direction (EPDir)
+                                                         Indicates whether the transaction is IN or OUT.
+                                                         * 1'b0: OUT
+                                                         * 1'b1: IN */
+	uint32_t epnum                        : 4;  /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number on the device serving as the
+                                                         data source or sink. */
+	uint32_t mps                          : 11; /**< Maximum Packet Size (MPS)
+                                                         Indicates the maximum packet size of the associated endpoint. */
+#else
+	uint32_t mps                          : 11;
+	uint32_t epnum                        : 4;
+	uint32_t epdir                        : 1;
+	uint32_t reserved_16_16               : 1;
+	uint32_t lspddev                      : 1;
+	uint32_t eptype                       : 2;
+	uint32_t ec                           : 2;
+	uint32_t devaddr                      : 7;
+	uint32_t oddfrm                       : 1;
+	uint32_t chdis                        : 1;
+	uint32_t chena                        : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_hccharx_s           cn30xx;
+	struct cvmx_usbcx_hccharx_s           cn31xx;
+	struct cvmx_usbcx_hccharx_s           cn50xx;
+	struct cvmx_usbcx_hccharx_s           cn52xx;
+	struct cvmx_usbcx_hccharx_s           cn52xxp1;
+	struct cvmx_usbcx_hccharx_s           cn56xx;
+	struct cvmx_usbcx_hccharx_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
+
+/**
+ * cvmx_usbc#_hcfg
+ *
+ * Host Configuration Register (HCFG)
+ *
+ * This register configures the core after power-on. Do not make changes to this register after initializing the host.
+ */
+union cvmx_usbcx_hcfg
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hcfg_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_3_31                : 29;
+	uint32_t fslssupp                     : 1;  /**< FS- and LS-Only Support (FSLSSupp)
+                                                         The application uses this bit to control the core's enumeration
+                                                         speed. Using this bit, the application can make the core
+                                                         enumerate as a FS host, even if the connected device supports
+                                                         HS traffic. Do not make changes to this field after initial
+                                                         programming.
+                                                         * 1'b0: HS/FS/LS, based on the maximum speed supported by
+                                                           the connected device
+                                                         * 1'b1: FS/LS-only, even if the connected device can support HS */
+	uint32_t fslspclksel                  : 2;  /**< FS/LS PHY Clock Select (FSLSPclkSel)
+                                                         When the core is in FS Host mode
+                                                         * 2'b00: PHY clock is running at 30/60 MHz
+                                                         * 2'b01: PHY clock is running at 48 MHz
+                                                         * Others: Reserved
+                                                         When the core is in LS Host mode
+                                                         * 2'b00: PHY clock is running at 30/60 MHz. When the
+                                                                  UTMI+/ULPI PHY Low Power mode is not selected, use
+                                                                  30/60 MHz.
+                                                         * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
+                                                                  PHY Low Power mode is selected, use 48MHz if the PHY
+                                                                  supplies a 48 MHz clock during LS mode.
+                                                         * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
+                                                                  use 6 MHz when the UTMI+ PHY Low Power mode is
+                                                                  selected and the PHY supplies a 6 MHz clock during LS
+                                                                  mode. If you select a 6 MHz clock during LS mode, you must
+                                                                  do a soft reset.
+                                                         * 2'b11: Reserved */
+#else
+	uint32_t fslspclksel                  : 2;
+	uint32_t fslssupp                     : 1;
+	uint32_t reserved_3_31                : 29;
+#endif
+	} s;
+	struct cvmx_usbcx_hcfg_s              cn30xx;
+	struct cvmx_usbcx_hcfg_s              cn31xx;
+	struct cvmx_usbcx_hcfg_s              cn50xx;
+	struct cvmx_usbcx_hcfg_s              cn52xx;
+	struct cvmx_usbcx_hcfg_s              cn52xxp1;
+	struct cvmx_usbcx_hcfg_s              cn56xx;
+	struct cvmx_usbcx_hcfg_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
+
+/**
+ * cvmx_usbc#_hcint#
+ *
+ * Host Channel-n Interrupt Register (HCINT)
+ *
+ * This register indicates the status of a channel with respect to USB- and AHB-related events.
+ * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
+ * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
+ * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
+ * Interrupt register. The application must clear the appropriate bit in this register to clear the
+ * corresponding bits in the HAINT and GINTSTS registers.
+ */
+union cvmx_usbcx_hcintx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hcintx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_11_31               : 21;
+	uint32_t datatglerr                   : 1;  /**< Data Toggle Error (DataTglErr) */
+	uint32_t frmovrun                     : 1;  /**< Frame Overrun (FrmOvrun) */
+	uint32_t bblerr                       : 1;  /**< Babble Error (BblErr) */
+	uint32_t xacterr                      : 1;  /**< Transaction Error (XactErr) */
+	uint32_t nyet                         : 1;  /**< NYET Response Received Interrupt (NYET) */
+	uint32_t ack                          : 1;  /**< ACK Response Received Interrupt (ACK) */
+	uint32_t nak                          : 1;  /**< NAK Response Received Interrupt (NAK) */
+	uint32_t stall                        : 1;  /**< STALL Response Received Interrupt (STALL) */
+	uint32_t ahberr                       : 1;  /**< This bit is always 0x0. */
+	uint32_t chhltd                       : 1;  /**< Channel Halted (ChHltd)
+                                                         Indicates the transfer completed abnormally either because of
+                                                         any USB transaction error or in response to disable request by
+                                                         the application. */
+	uint32_t xfercompl                    : 1;  /**< Transfer Completed (XferCompl)
+                                                         Transfer completed normally without any errors. */
+#else
+	uint32_t xfercompl                    : 1;
+	uint32_t chhltd                       : 1;
+	uint32_t ahberr                       : 1;
+	uint32_t stall                        : 1;
+	uint32_t nak                          : 1;
+	uint32_t ack                          : 1;
+	uint32_t nyet                         : 1;
+	uint32_t xacterr                      : 1;
+	uint32_t bblerr                       : 1;
+	uint32_t frmovrun                     : 1;
+	uint32_t datatglerr                   : 1;
+	uint32_t reserved_11_31               : 21;
+#endif
+	} s;
+	struct cvmx_usbcx_hcintx_s            cn30xx;
+	struct cvmx_usbcx_hcintx_s            cn31xx;
+	struct cvmx_usbcx_hcintx_s            cn50xx;
+	struct cvmx_usbcx_hcintx_s            cn52xx;
+	struct cvmx_usbcx_hcintx_s            cn52xxp1;
+	struct cvmx_usbcx_hcintx_s            cn56xx;
+	struct cvmx_usbcx_hcintx_s            cn56xxp1;
+};
+typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
+
+/**
+ * cvmx_usbc#_hcintmsk#
+ *
+ * Host Channel-n Interrupt Mask Register (HCINTMSKn)
+ *
+ * This register reflects the mask for each channel status described in the previous section.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+union cvmx_usbcx_hcintmskx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hcintmskx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_11_31               : 21;
+	uint32_t datatglerrmsk                : 1;  /**< Data Toggle Error Mask (DataTglErrMsk) */
+	uint32_t frmovrunmsk                  : 1;  /**< Frame Overrun Mask (FrmOvrunMsk) */
+	uint32_t bblerrmsk                    : 1;  /**< Babble Error Mask (BblErrMsk) */
+	uint32_t xacterrmsk                   : 1;  /**< Transaction Error Mask (XactErrMsk) */
+	uint32_t nyetmsk                      : 1;  /**< NYET Response Received Interrupt Mask (NyetMsk) */
+	uint32_t ackmsk                       : 1;  /**< ACK Response Received Interrupt Mask (AckMsk) */
+	uint32_t nakmsk                       : 1;  /**< NAK Response Received Interrupt Mask (NakMsk) */
+	uint32_t stallmsk                     : 1;  /**< STALL Response Received Interrupt Mask (StallMsk) */
+	uint32_t ahberrmsk                    : 1;  /**< AHB Error Mask (AHBErrMsk) */
+	uint32_t chhltdmsk                    : 1;  /**< Channel Halted Mask (ChHltdMsk) */
+	uint32_t xfercomplmsk                 : 1;  /**< Transfer Completed Mask (XferComplMsk) */
+#else
+	uint32_t xfercomplmsk                 : 1;
+	uint32_t chhltdmsk                    : 1;
+	uint32_t ahberrmsk                    : 1;
+	uint32_t stallmsk                     : 1;
+	uint32_t nakmsk                       : 1;
+	uint32_t ackmsk                       : 1;
+	uint32_t nyetmsk                      : 1;
+	uint32_t xacterrmsk                   : 1;
+	uint32_t bblerrmsk                    : 1;
+	uint32_t frmovrunmsk                  : 1;
+	uint32_t datatglerrmsk                : 1;
+	uint32_t reserved_11_31               : 21;
+#endif
+	} s;
+	struct cvmx_usbcx_hcintmskx_s         cn30xx;
+	struct cvmx_usbcx_hcintmskx_s         cn31xx;
+	struct cvmx_usbcx_hcintmskx_s         cn50xx;
+	struct cvmx_usbcx_hcintmskx_s         cn52xx;
+	struct cvmx_usbcx_hcintmskx_s         cn52xxp1;
+	struct cvmx_usbcx_hcintmskx_s         cn56xx;
+	struct cvmx_usbcx_hcintmskx_s         cn56xxp1;
+};
+typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
+
+/**
+ * cvmx_usbc#_hcsplt#
+ *
+ * Host Channel-n Split Control Register (HCSPLT)
+ *
+ */
+union cvmx_usbcx_hcspltx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hcspltx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t spltena                      : 1;  /**< Split Enable (SpltEna)
+                                                         The application sets this field to indicate that this channel is
+                                                         enabled to perform split transactions. */
+	uint32_t reserved_17_30               : 14;
+	uint32_t compsplt                     : 1;  /**< Do Complete Split (CompSplt)
+                                                         The application sets this field to request the OTG host to
+                                                         perform a complete split transaction. */
+	uint32_t xactpos                      : 2;  /**< Transaction Position (XactPos)
+                                                         This field is used to determine whether to send all, first, middle,
+                                                         or last payloads with each OUT transaction.
+                                                         * 2'b11: All. This is the entire data payload is of this transaction
+                                                                  (which is less than or equal to 188 bytes).
+                                                         * 2'b10: Begin. This is the first data payload of this transaction
+                                                                  (which is larger than 188 bytes).
+                                                         * 2'b00: Mid. This is the middle payload of this transaction
+                                                                  (which is larger than 188 bytes).
+                                                         * 2'b01: End. This is the last payload of this transaction (which
+                                                                  is larger than 188 bytes). */
+	uint32_t hubaddr                      : 7;  /**< Hub Address (HubAddr)
+                                                         This field holds the device address of the transaction
+                                                         translator's hub. */
+	uint32_t prtaddr                      : 7;  /**< Port Address (PrtAddr)
+                                                         This field is the port number of the recipient transaction
+                                                         translator. */
+#else
+	uint32_t prtaddr                      : 7;
+	uint32_t hubaddr                      : 7;
+	uint32_t xactpos                      : 2;
+	uint32_t compsplt                     : 1;
+	uint32_t reserved_17_30               : 14;
+	uint32_t spltena                      : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_hcspltx_s           cn30xx;
+	struct cvmx_usbcx_hcspltx_s           cn31xx;
+	struct cvmx_usbcx_hcspltx_s           cn50xx;
+	struct cvmx_usbcx_hcspltx_s           cn52xx;
+	struct cvmx_usbcx_hcspltx_s           cn52xxp1;
+	struct cvmx_usbcx_hcspltx_s           cn56xx;
+	struct cvmx_usbcx_hcspltx_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
+
+/**
+ * cvmx_usbc#_hctsiz#
+ *
+ * Host Channel-n Transfer Size Register (HCTSIZ)
+ *
+ */
+union cvmx_usbcx_hctsizx
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hctsizx_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t dopng                        : 1;  /**< Do Ping (DoPng)
+                                                         Setting this field to 1 directs the host to do PING protocol. */
+	uint32_t pid                          : 2;  /**< PID (Pid)
+                                                         The application programs this field with the type of PID to use
+                                                         for the initial transaction. The host will maintain this field for the
+                                                         rest of the transfer.
+                                                         * 2'b00: DATA0
+                                                         * 2'b01: DATA2
+                                                         * 2'b10: DATA1
+                                                         * 2'b11: MDATA (non-control)/SETUP (control) */
+	uint32_t pktcnt                       : 10; /**< Packet Count (PktCnt)
+                                                         This field is programmed by the application with the expected
+                                                         number of packets to be transmitted (OUT) or received (IN).
+                                                         The host decrements this count on every successful
+                                                         transmission or reception of an OUT/IN packet. Once this count
+                                                         reaches zero, the application is interrupted to indicate normal
+                                                         completion. */
+	uint32_t xfersize                     : 19; /**< Transfer Size (XferSize)
+                                                         For an OUT, this field is the number of data bytes the host will
+                                                         send during the transfer.
+                                                         For an IN, this field is the buffer size that the application has
+                                                         reserved for the transfer. The application is expected to
+                                                         program this field as an integer multiple of the maximum packet
+                                                         size for IN transactions (periodic and non-periodic). */
+#else
+	uint32_t xfersize                     : 19;
+	uint32_t pktcnt                       : 10;
+	uint32_t pid                          : 2;
+	uint32_t dopng                        : 1;
+#endif
+	} s;
+	struct cvmx_usbcx_hctsizx_s           cn30xx;
+	struct cvmx_usbcx_hctsizx_s           cn31xx;
+	struct cvmx_usbcx_hctsizx_s           cn50xx;
+	struct cvmx_usbcx_hctsizx_s           cn52xx;
+	struct cvmx_usbcx_hctsizx_s           cn52xxp1;
+	struct cvmx_usbcx_hctsizx_s           cn56xx;
+	struct cvmx_usbcx_hctsizx_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
+
+/**
+ * cvmx_usbc#_hfir
+ *
+ * Host Frame Interval Register (HFIR)
+ *
+ * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
+ */
+union cvmx_usbcx_hfir
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hfir_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_16_31               : 16;
+	uint32_t frint                        : 16; /**< Frame Interval (FrInt)
+                                                         The value that the application programs to this field specifies
+                                                         the interval between two consecutive SOFs (FS) or micro-
+                                                         SOFs (HS) or Keep-Alive tokens (HS). This field contains the
+                                                         number of PHY clocks that constitute the required frame
+                                                         interval. The default value set in this field for a FS operation
+                                                         when the PHY clock frequency is 60 MHz. The application can
+                                                         write a value to this register only after the Port Enable bit of
+                                                         the Host Port Control and Status register (HPRT.PrtEnaPort)
+                                                         has been set. If no value is programmed, the core calculates
+                                                         the value based on the PHY clock specified in the FS/LS PHY
+                                                         Clock Select field of the Host Configuration register
+                                                         (HCFG.FSLSPclkSel). Do not change the value of this field
+                                                         after the initial configuration.
+                                                         * 125 us (PHY clock frequency for HS)
+                                                         * 1 ms (PHY clock frequency for FS/LS) */
+#else
+	uint32_t frint                        : 16;
+	uint32_t reserved_16_31               : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_hfir_s              cn30xx;
+	struct cvmx_usbcx_hfir_s              cn31xx;
+	struct cvmx_usbcx_hfir_s              cn50xx;
+	struct cvmx_usbcx_hfir_s              cn52xx;
+	struct cvmx_usbcx_hfir_s              cn52xxp1;
+	struct cvmx_usbcx_hfir_s              cn56xx;
+	struct cvmx_usbcx_hfir_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
+
+/**
+ * cvmx_usbc#_hfnum
+ *
+ * Host Frame Number/Frame Time Remaining Register (HFNUM)
+ *
+ * This register indicates the current frame number.
+ * It also indicates the time remaining (in terms of the number of PHY clocks)
+ * in the current (micro)frame.
+ */
+union cvmx_usbcx_hfnum
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hfnum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t frrem                        : 16; /**< Frame Time Remaining (FrRem)
+                                                         Indicates the amount of time remaining in the current
+                                                         microframe (HS) or frame (FS/LS), in terms of PHY clocks.
+                                                         This field decrements on each PHY clock. When it reaches
+                                                         zero, this field is reloaded with the value in the Frame Interval
+                                                         register and a new SOF is transmitted on the USB. */
+	uint32_t frnum                        : 16; /**< Frame Number (FrNum)
+                                                         This field increments when a new SOF is transmitted on the
+                                                         USB, and is reset to 0 when it reaches 16'h3FFF. */
+#else
+	uint32_t frnum                        : 16;
+	uint32_t frrem                        : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_hfnum_s             cn30xx;
+	struct cvmx_usbcx_hfnum_s             cn31xx;
+	struct cvmx_usbcx_hfnum_s             cn50xx;
+	struct cvmx_usbcx_hfnum_s             cn52xx;
+	struct cvmx_usbcx_hfnum_s             cn52xxp1;
+	struct cvmx_usbcx_hfnum_s             cn56xx;
+	struct cvmx_usbcx_hfnum_s             cn56xxp1;
+};
+typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
+
+/**
+ * cvmx_usbc#_hprt
+ *
+ * Host Port Control and Status Register (HPRT)
+ *
+ * This register is available in both Host and Device modes.
+ * Currently, the OTG Host supports only one port.
+ * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
+ * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
+ * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
+ * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
+ * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
+ * to clear the interrupt.
+ */
+union cvmx_usbcx_hprt
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hprt_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_19_31               : 13;
+	uint32_t prtspd                       : 2;  /**< Port Speed (PrtSpd)
+                                                         Indicates the speed of the device attached to this port.
+                                                         * 2'b00: High speed
+                                                         * 2'b01: Full speed
+                                                         * 2'b10: Low speed
+                                                         * 2'b11: Reserved */
+	uint32_t prttstctl                    : 4;  /**< Port Test Control (PrtTstCtl)
+                                                         The application writes a nonzero value to this field to put
+                                                         the port into a Test mode, and the corresponding pattern is
+                                                         signaled on the port.
+                                                         * 4'b0000: Test mode disabled
+                                                         * 4'b0001: Test_J mode
+                                                         * 4'b0010: Test_K mode
+                                                         * 4'b0011: Test_SE0_NAK mode
+                                                         * 4'b0100: Test_Packet mode
+                                                         * 4'b0101: Test_Force_Enable
+                                                         * Others: Reserved
+                                                         PrtSpd must be zero (i.e. the interface must be in high-speed
+                                                         mode) to use the PrtTstCtl test modes. */
+	uint32_t prtpwr                       : 1;  /**< Port Power (PrtPwr)
+                                                         The application uses this field to control power to this port,
+                                                         and the core clears this bit on an overcurrent condition.
+                                                         * 1'b0: Power off
+                                                         * 1'b1: Power on */
+	uint32_t prtlnsts                     : 2;  /**< Port Line Status (PrtLnSts)
+                                                         Indicates the current logic level USB data lines
+                                                         * Bit [10]: Logic level of D-
+                                                         * Bit [11]: Logic level of D+ */
+	uint32_t reserved_9_9                 : 1;
+	uint32_t prtrst                       : 1;  /**< Port Reset (PrtRst)
+                                                         When the application sets this bit, a reset sequence is
+                                                         started on this port. The application must time the reset
+                                                         period and clear this bit after the reset sequence is
+                                                         complete.
+                                                         * 1'b0: Port not in reset
+                                                         * 1'b1: Port in reset
+                                                         The application must leave this bit set for at least a
+                                                         minimum duration mentioned below to start a reset on the
+                                                         port. The application can leave it set for another 10 ms in
+                                                         addition to the required minimum duration, before clearing
+                                                         the bit, even though there is no maximum limit set by the
+                                                         USB standard.
+                                                         * High speed: 50 ms
+                                                         * Full speed/Low speed: 10 ms */
+	uint32_t prtsusp                      : 1;  /**< Port Suspend (PrtSusp)
+                                                         The application sets this bit to put this port in Suspend
+                                                         mode. The core only stops sending SOFs when this is set.
+                                                         To stop the PHY clock, the application must set the Port
+                                                         Clock Stop bit, which will assert the suspend input pin of
+                                                         the PHY.
+                                                         The read value of this bit reflects the current suspend
+                                                         status of the port. This bit is cleared by the core after a
+                                                         remote wakeup signal is detected or the application sets
+                                                         the Port Reset bit or Port Resume bit in this register or the
+                                                         Resume/Remote Wakeup Detected Interrupt bit or
+                                                         Disconnect Detected Interrupt bit in the Core Interrupt
+                                                         register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
+                                                         respectively).
+                                                         * 1'b0: Port not in Suspend mode
+                                                         * 1'b1: Port in Suspend mode */
+	uint32_t prtres                       : 1;  /**< Port Resume (PrtRes)
+                                                         The application sets this bit to drive resume signaling on
+                                                         the port. The core continues to drive the resume signal
+                                                         until the application clears this bit.
+                                                         If the core detects a USB remote wakeup sequence, as
+                                                         indicated by the Port Resume/Remote Wakeup Detected
+                                                         Interrupt bit of the Core Interrupt register
+                                                         (GINTSTS.WkUpInt), the core starts driving resume
+                                                         signaling without application intervention and clears this bit
+                                                         when it detects a disconnect condition. The read value of
+                                                         this bit indicates whether the core is currently driving
+                                                         resume signaling.
+                                                         * 1'b0: No resume driven
+                                                         * 1'b1: Resume driven */
+	uint32_t prtovrcurrchng               : 1;  /**< Port Overcurrent Change (PrtOvrCurrChng)
+                                                         The core sets this bit when the status of the Port
+                                                         Overcurrent Active bit (bit 4) in this register changes. */
+	uint32_t prtovrcurract                : 1;  /**< Port Overcurrent Active (PrtOvrCurrAct)
+                                                         Indicates the overcurrent condition of the port.
+                                                         * 1'b0: No overcurrent condition
+                                                         * 1'b1: Overcurrent condition */
+	uint32_t prtenchng                    : 1;  /**< Port Enable/Disable Change (PrtEnChng)
+                                                         The core sets this bit when the status of the Port Enable bit
+                                                         [2] of this register changes. */
+	uint32_t prtena                       : 1;  /**< Port Enable (PrtEna)
+                                                         A port is enabled only by the core after a reset sequence,
+                                                         and is disabled by an overcurrent condition, a disconnect
+                                                         condition, or by the application clearing this bit. The
+                                                         application cannot set this bit by a register write. It can only
+                                                         clear it to disable the port. This bit does not trigger any
+                                                         interrupt to the application.
+                                                         * 1'b0: Port disabled
+                                                         * 1'b1: Port enabled */
+	uint32_t prtconndet                   : 1;  /**< Port Connect Detected (PrtConnDet)
+                                                         The core sets this bit when a device connection is detected
+                                                         to trigger an interrupt to the application using the Host Port
+                                                         Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
+                                                         The application must write a 1 to this bit to clear the
+                                                         interrupt. */
+	uint32_t prtconnsts                   : 1;  /**< Port Connect Status (PrtConnSts)
+                                                         * 0: No device is attached to the port.
+                                                         * 1: A device is attached to the port. */
+#else
+	uint32_t prtconnsts                   : 1;
+	uint32_t prtconndet                   : 1;
+	uint32_t prtena                       : 1;
+	uint32_t prtenchng                    : 1;
+	uint32_t prtovrcurract                : 1;
+	uint32_t prtovrcurrchng               : 1;
+	uint32_t prtres                       : 1;
+	uint32_t prtsusp                      : 1;
+	uint32_t prtrst                       : 1;
+	uint32_t reserved_9_9                 : 1;
+	uint32_t prtlnsts                     : 2;
+	uint32_t prtpwr                       : 1;
+	uint32_t prttstctl                    : 4;
+	uint32_t prtspd                       : 2;
+	uint32_t reserved_19_31               : 13;
+#endif
+	} s;
+	struct cvmx_usbcx_hprt_s              cn30xx;
+	struct cvmx_usbcx_hprt_s              cn31xx;
+	struct cvmx_usbcx_hprt_s              cn50xx;
+	struct cvmx_usbcx_hprt_s              cn52xx;
+	struct cvmx_usbcx_hprt_s              cn52xxp1;
+	struct cvmx_usbcx_hprt_s              cn56xx;
+	struct cvmx_usbcx_hprt_s              cn56xxp1;
+};
+typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
+
+/**
+ * cvmx_usbc#_hptxfsiz
+ *
+ * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
+ *
+ * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
+ */
+union cvmx_usbcx_hptxfsiz
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hptxfsiz_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ptxfsize                     : 16; /**< Host Periodic TxFIFO Depth (PTxFSize)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 16
+                                                         * Maximum value is 32768 */
+	uint32_t ptxfstaddr                   : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */
+#else
+	uint32_t ptxfstaddr                   : 16;
+	uint32_t ptxfsize                     : 16;
+#endif
+	} s;
+	struct cvmx_usbcx_hptxfsiz_s          cn30xx;
+	struct cvmx_usbcx_hptxfsiz_s          cn31xx;
+	struct cvmx_usbcx_hptxfsiz_s          cn50xx;
+	struct cvmx_usbcx_hptxfsiz_s          cn52xx;
+	struct cvmx_usbcx_hptxfsiz_s          cn52xxp1;
+	struct cvmx_usbcx_hptxfsiz_s          cn56xx;
+	struct cvmx_usbcx_hptxfsiz_s          cn56xxp1;
+};
+typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
+
+/**
+ * cvmx_usbc#_hptxsts
+ *
+ * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
+ *
+ * This read-only register contains the free space information for the Periodic TxFIFO and
+ * the Periodic Transmit Request Queue
+ */
+union cvmx_usbcx_hptxsts
+{
+	uint32_t u32;
+	struct cvmx_usbcx_hptxsts_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t ptxqtop                      : 8;  /**< Top of the Periodic Transmit Request Queue (PTxQTop)
+                                                         This indicates the entry in the Periodic Tx Request Queue that
+                                                         is currently being processes by the MAC.
+                                                         This register is used for debugging.
+                                                         * Bit [31]: Odd/Even (micro)frame
+                                                           - 1'b0: send in even (micro)frame
+                                                           - 1'b1: send in odd (micro)frame
+                                                         * Bits [30:27]: Channel/endpoint number
+                                                         * Bits [26:25]: Type
+                                                           - 2'b00: IN/OUT
+                                                           - 2'b01: Zero-length packet
+                                                           - 2'b10: CSPLIT
+                                                           - 2'b11: Disable channel command
+                                                         * Bit [24]: Terminate (last entry for the selected
+                                                           channel/endpoint) */
+	uint32_t ptxqspcavail                 : 8;  /**< Periodic Transmit Request Queue Space Available
+                                                         (PTxQSpcAvail)
+                                                         Indicates the number of free locations available to be written in
+                                                         the Periodic Transmit Request Queue. This queue holds both
+                                                         IN and OUT requests.
+                                                         * 8'h0: Periodic Transmit Request Queue is full
+                                                         * 8'h1: 1 location available
+                                                         * 8'h2: 2 locations available
+                                                         * n: n locations available (0..8)
+                                                         * Others: Reserved */
+	uint32_t ptxfspcavail                 : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
+                                                         Indicates the number of free locations available to be written to
+                                                         in the Periodic TxFIFO.
+                                                         Values are in terms of 32-bit words
+                                                         * 16'h0: Periodic TxFIFO is full
+                                                         * 16'h1: 1 word available
+                                                         * 16'h2: 2 words available
+                                                         * 16'hn: n words available (where 0..32768)
+                                                         * 16'h8000: 32768 words available
+                                                         * Others: Reserved */
+#else
+	uint32_t ptxfspcavail                 : 16;
+	uint32_t ptxqspcavail                 : 8;
+	uint32_t ptxqtop                      : 8;
+#endif
+	} s;
+	struct cvmx_usbcx_hptxsts_s           cn30xx;
+	struct cvmx_usbcx_hptxsts_s           cn31xx;
+	struct cvmx_usbcx_hptxsts_s           cn50xx;
+	struct cvmx_usbcx_hptxsts_s           cn52xx;
+	struct cvmx_usbcx_hptxsts_s           cn52xxp1;
+	struct cvmx_usbcx_hptxsts_s           cn56xx;
+	struct cvmx_usbcx_hptxsts_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
+
+/**
+ * cvmx_usbc#_nptxdfifo#
+ *
+ * NPTX Data Fifo (NPTXDFIFO)
+ *
+ * A slave mode application uses this register to access the Tx FIFO for channel n.
+ */
+union cvmx_usbcx_nptxdfifox
+{
+	uint32_t u32;
+	struct cvmx_usbcx_nptxdfifox_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t data                         : 32; /**< Reserved */
+#else
+	uint32_t data                         : 32;
+#endif
+	} s;
+	struct cvmx_usbcx_nptxdfifox_s        cn30xx;
+	struct cvmx_usbcx_nptxdfifox_s        cn31xx;
+	struct cvmx_usbcx_nptxdfifox_s        cn50xx;
+	struct cvmx_usbcx_nptxdfifox_s        cn52xx;
+	struct cvmx_usbcx_nptxdfifox_s        cn52xxp1;
+	struct cvmx_usbcx_nptxdfifox_s        cn56xx;
+	struct cvmx_usbcx_nptxdfifox_s        cn56xxp1;
+};
+typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t;
+
+/**
+ * cvmx_usbc#_pcgcctl
+ *
+ * Power and Clock Gating Control Register (PCGCCTL)
+ *
+ * The application can use this register to control the core's power-down and clock gating features.
+ */
+union cvmx_usbcx_pcgcctl
+{
+	uint32_t u32;
+	struct cvmx_usbcx_pcgcctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint32_t reserved_5_31                : 27;
+	uint32_t physuspended                 : 1;  /**< PHY Suspended. (PhySuspended)
+                                                         Indicates that the PHY has been suspended. After the
+                                                         application sets the Stop Pclk bit (bit 0), this bit is updated once
+                                                         the PHY is suspended.
+                                                         Since the UTMI+ PHY suspend is controlled through a port, the
+                                                         UTMI+ PHY is suspended immediately after Stop Pclk is set.
+                                                         However, the ULPI PHY takes a few clocks to suspend,
+                                                         because the suspend information is conveyed through the ULPI
+                                                         protocol to the ULPI PHY. */
+	uint32_t rstpdwnmodule                : 1;  /**< Reset Power-Down Modules (RstPdwnModule)
+                                                         This bit is valid only in Partial Power-Down mode. The
+                                                         application sets this bit when the power is turned off. The
+                                                         application clears this bit after the power is turned on and the
+                                                         PHY clock is up. */
+	uint32_t pwrclmp                      : 1;  /**< Power Clamp (PwrClmp)
+                                                         This bit is only valid in Partial Power-Down mode. The
+                                                         application sets this bit before the power is turned off to clamp
+                                                         the signals between the power-on modules and the power-off
+                                                         modules. The application clears the bit to disable the clamping
+                                                         before the power is turned on. */
+	uint32_t gatehclk                     : 1;  /**< Gate Hclk (GateHclk)
+                                                         The application sets this bit to gate hclk to modules other than
+                                                         the AHB Slave and Master and wakeup logic when the USB is
+                                                         suspended or the session is not valid. The application clears
+                                                         this bit when the USB is resumed or a new session starts. */
+	uint32_t stoppclk                     : 1;  /**< Stop Pclk (StopPclk)
+                                                         The application sets this bit to stop the PHY clock (phy_clk)
+                                                         when the USB is suspended, the session is not valid, or the
+                                                         device is disconnected. The application clears this bit when the
+                                                         USB is resumed or a new session starts. */
+#else
+	uint32_t stoppclk                     : 1;
+	uint32_t gatehclk                     : 1;
+	uint32_t pwrclmp                      : 1;
+	uint32_t rstpdwnmodule                : 1;
+	uint32_t physuspended                 : 1;
+	uint32_t reserved_5_31                : 27;
+#endif
+	} s;
+	struct cvmx_usbcx_pcgcctl_s           cn30xx;
+	struct cvmx_usbcx_pcgcctl_s           cn31xx;
+	struct cvmx_usbcx_pcgcctl_s           cn50xx;
+	struct cvmx_usbcx_pcgcctl_s           cn52xx;
+	struct cvmx_usbcx_pcgcctl_s           cn52xxp1;
+	struct cvmx_usbcx_pcgcctl_s           cn56xx;
+	struct cvmx_usbcx_pcgcctl_s           cn56xxp1;
+};
+typedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-usbd.c b/sys/contrib/octeon-sdk/cvmx-usbd.c
new file mode 100644
index 0000000..db2ab5d
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-usbd.c
@@ -0,0 +1,1041 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * "cvmx-usbd.c" defines a set of low level USB functions to help
+ * developers create Octeon USB devices for various operating
+ * systems. These functions provide a generic API to the Octeon
+ * USB blocks, hiding the internal hardware specific
+ * operations.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-clock.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+#include <asm/octeon/cvmx-usbnx-defs.h>
+#include <asm/octeon/cvmx-usbcx-defs.h>
+#include <asm/octeon/cvmx-usbd.h>
+#include <asm/octeon/cvmx-swap.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
+#else
+#include "cvmx.h"
+#include "cvmx-clock.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-usbd.h"
+#include "cvmx-swap.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+#endif
+
+#define ULL unsigned long long
+
+/**
+ * @INTERNAL
+ * Read a USB 32bit CSR. It performs the necessary address swizzle for 32bit
+ * CSRs.
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usbd_initialize().
+ * @param address 64bit address to read
+ *
+ * @return Result of the read
+ */
+static inline uint32_t __cvmx_usbd_read_csr32(cvmx_usbd_state_t *usb, uint64_t address)
+{
+    uint32_t result = cvmx_read64_uint32(address ^ 4);
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Write a USB 32bit CSR. It performs the necessary address swizzle for 32bit
+ * CSRs.
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usbd_initialize().
+ * @param address 64bit address to write
+ * @param value   Value to write
+ */
+static inline void __cvmx_usbd_write_csr32(cvmx_usbd_state_t *usb, uint64_t address, uint32_t value)
+{
+    cvmx_write64_uint32(address ^ 4, value);
+    cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
+}
+
+/**
+ * @INTERNAL
+ * Calls the user supplied callback when an event happens.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param reason Reason for the callback
+ * @param endpoint_num
+ *               Endpoint number
+ * @param bytes_transferred
+ *               Bytes transferred
+ */
+static void __cvmx_usbd_callback(cvmx_usbd_state_t *usb, cvmx_usbd_callback_t reason, int endpoint_num, int bytes_transferred)
+{
+    if (usb->callback[reason])
+    {
+        if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+            cvmx_dprintf("%s: Calling callback reason=%d endpoint=%d bytes=%d func=%p data=%p\n",
+                __FUNCTION__, reason, endpoint_num, bytes_transferred, usb->callback[reason], usb->callback_data[reason]);
+        usb->callback[reason](reason, endpoint_num, bytes_transferred, usb->callback_data[reason]);
+    }
+    else
+    {
+        if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+            cvmx_dprintf("%s: No callback for reason=%d endpoint=%d bytes=%d\n",
+                __FUNCTION__, reason, endpoint_num, bytes_transferred);
+    }
+}
+
+/**
+ * @INTERNAL
+ * Perform USB device mode initialization after a reset completes.
+ * This should be called after USBC0/1_GINTSTS[USBRESET] and
+ * corresponds to section 22.6.1.1, "Initialization on USB Reset",
+ * in the manual.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+static int __cvmx_usbd_device_reset_complete(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_ghwcfg2_t usbcx_ghwcfg2;
+    cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
+    cvmx_usbcx_doepmsk_t usbcx_doepmsk;
+    cvmx_usbcx_diepmsk_t usbcx_diepmsk;
+    cvmx_usbcx_daintmsk_t usbc_daintmsk;
+    cvmx_usbcx_gnptxfsiz_t gnptxfsiz;
+    int fifo_space;
+    int i;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: Processing reset\n", __FUNCTION__);
+
+    usbcx_ghwcfg2.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GHWCFG2(usb->index));
+    usbcx_ghwcfg3.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
+
+    /* Set up the data FIFO RAM for each of the FIFOs */
+    fifo_space = usbcx_ghwcfg3.s.dfifodepth;
+
+    /* Start at the top of the FIFO and assign space for each periodic fifo */
+    for (i=usbcx_ghwcfg2.s.numdeveps; i>0; i--)
+    {
+        cvmx_usbcx_dptxfsizx_t siz;
+        siz.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index));
+        fifo_space -= siz.s.dptxfsize;
+        siz.s.dptxfstaddr = fifo_space;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index), siz.u32);
+    }
+
+    /* Assign half the leftover space to the non periodic tx fifo */
+    gnptxfsiz.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
+    gnptxfsiz.s.nptxfdep = fifo_space / 2;
+    fifo_space -= gnptxfsiz.s.nptxfdep;
+    gnptxfsiz.s.nptxfstaddr = fifo_space;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), gnptxfsiz.u32);
+
+    /* Assign the remain space to the RX fifo */
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GRXFSIZ(usb->index), fifo_space);
+
+    /* Unmask the common endpoint interrupts */
+    usbcx_doepmsk.u32 = 0;
+    usbcx_doepmsk.s.setupmsk = 1;
+    usbcx_doepmsk.s.epdisbldmsk = 1;
+    usbcx_doepmsk.s.xfercomplmsk = 1;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPMSK(usb->index), usbcx_doepmsk.u32);
+    usbcx_diepmsk.u32 = 0;
+    usbcx_diepmsk.s.epdisbldmsk = 1;
+    usbcx_diepmsk.s.xfercomplmsk = 1;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPMSK(usb->index), usbcx_diepmsk.u32);
+
+    usbc_daintmsk.u32 = 0;
+    usbc_daintmsk.s.inepmsk = -1;
+    usbc_daintmsk.s.outepmsk = -1;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DAINTMSK(usb->index), usbc_daintmsk.u32);
+
+    /* Set all endpoints to NAK */
+    for (i=0; i<usbcx_ghwcfg2.s.numdeveps+1; i++)
+    {
+        cvmx_usbcx_doepctlx_t usbc_doepctl;
+        usbc_doepctl.u32 = 0;
+        usbc_doepctl.s.snak = 1;
+        usbc_doepctl.s.usbactep = 1;
+        usbc_doepctl.s.mps = (i==0) ? 0 : 64;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPCTLX(i, usb->index), usbc_doepctl.u32);
+    }
+
+    return 0;
+}
+
+
+/**
+ * Initialize a USB port for use. This must be called before any
+ * other access to the Octeon USB port is made. The port starts
+ * off in the disabled state.
+ *
+ * @param usb    Pointer to an empty cvmx_usbd_state_t structure
+ *               that will be populated by the initialize call.
+ *               This structure is then passed to all other USB
+ *               functions.
+ * @param usb_port_number
+ *               Which Octeon USB port to initialize.
+ * @param flags  Flags to control hardware initialization. See
+ *               cvmx_usbd_initialize_flags_t for the flag
+ *               definitions. Some flags are mandatory.
+ *
+ * @return Zero or a negative on error.
+ */
+int cvmx_usbd_initialize(cvmx_usbd_state_t *usb,
+                                      int usb_port_number,
+                                      cvmx_usbd_initialize_flags_t flags)
+{
+    cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
+    cvmx_usbnx_usbp_ctl_status_t usbn_usbp_ctl_status;
+
+    if (cvmx_unlikely(flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: Called\n", __FUNCTION__);
+
+    memset(usb, 0, sizeof(usb));
+    usb->init_flags = flags;
+    usb->index = usb_port_number;
+
+    /* Try to determine clock type automatically */
+    if ((usb->init_flags & (CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_XI |
+                  CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_GND)) == 0)
+    {
+        if (__cvmx_helper_board_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12)
+            usb->init_flags |= CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_XI;  /* Only 12 MHZ crystals are supported */
+        else
+            usb->init_flags |= CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_GND;
+    }
+
+    if (usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_GND)
+    {
+        /* Check for auto ref clock frequency */
+        if (!(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_CLOCK_MHZ_MASK))
+            switch (__cvmx_helper_board_usb_get_clock_type())
+            {
+                case USB_CLOCK_TYPE_REF_12:
+                    usb->init_flags |= CVMX_USBD_INITIALIZE_FLAGS_CLOCK_12MHZ;
+                    break;
+                case USB_CLOCK_TYPE_REF_24:
+                    usb->init_flags |= CVMX_USBD_INITIALIZE_FLAGS_CLOCK_24MHZ;
+                    break;
+                case USB_CLOCK_TYPE_REF_48:
+                default:
+                    usb->init_flags |= CVMX_USBD_INITIALIZE_FLAGS_CLOCK_48MHZ;
+                    break;
+            }
+    }
+
+    /* Power On Reset and PHY Initialization */
+
+    /* 1. Wait for DCOK to assert (nothing to do) */
+    /* 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
+        USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 */
+    usbn_clk_ctl.u64 = cvmx_read_csr(CVMX_USBNX_CLK_CTL(usb->index));
+    usbn_clk_ctl.s.por = 1;
+    usbn_clk_ctl.s.hrst = 0;
+    usbn_clk_ctl.s.prst = 0;
+    usbn_clk_ctl.s.hclk_rst = 0;
+    usbn_clk_ctl.s.enable = 0;
+    /* 2b. Select the USB reference clock/crystal parameters by writing
+        appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] */
+    if (usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_GND)
+    {
+        /* The USB port uses 12/24/48MHz 2.5V board clock
+            source at USB_XO. USB_XI should be tied to GND.
+            Most Octeon evaluation boards require this setting */
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            usbn_clk_ctl.cn31xx.p_rclk  = 1; /* From CN31XX,CN30XX manual */
+            usbn_clk_ctl.cn31xx.p_xenbn = 0;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+            usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
+        else
+            usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
+
+        switch (usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_CLOCK_MHZ_MASK)
+        {
+            case CVMX_USBD_INITIALIZE_FLAGS_CLOCK_12MHZ:
+                usbn_clk_ctl.s.p_c_sel = 0;
+                break;
+            case CVMX_USBD_INITIALIZE_FLAGS_CLOCK_24MHZ:
+                usbn_clk_ctl.s.p_c_sel = 1;
+                break;
+            case CVMX_USBD_INITIALIZE_FLAGS_CLOCK_48MHZ:
+                usbn_clk_ctl.s.p_c_sel = 2;
+                break;
+        }
+    }
+    else
+    {
+        /* The USB port uses a 12MHz crystal as clock source
+            at USB_XO and USB_XI */
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            usbn_clk_ctl.cn31xx.p_rclk  = 1; /* From CN31XX,CN30XX manual */
+            usbn_clk_ctl.cn31xx.p_xenbn = 1;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+            usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
+        else
+            usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
+
+        usbn_clk_ctl.s.p_c_sel = 0;
+    }
+    /* 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
+        setting USBN0/1_CLK_CTL[ENABLE] = 1.  Divide the core clock down such
+        that USB is as close as possible to 125Mhz */
+    {
+        int divisor = (cvmx_clock_get_rate(CVMX_CLOCK_CORE)+125000000-1)/125000000;
+        if (divisor < 4)  /* Lower than 4 doesn't seem to work properly */
+            divisor = 4;
+        usbn_clk_ctl.s.divide = divisor;
+        usbn_clk_ctl.s.divide2 = 0;
+    }
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
+    usbn_clk_ctl.s.hclk_rst = 1;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    /* 2e.  Wait 64 core-clock cycles for HCLK to stabilize */
+    cvmx_wait(64);
+    /* 3. Program the power-on reset field in the USBN clock-control register:
+        USBN_CLK_CTL[POR] = 0 */
+    usbn_clk_ctl.s.por = 0;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    /* 4. Wait 1 ms for PHY clock to start */
+    cvmx_wait_usec(1000);
+    /* 5. Program the Reset input from automatic test equipment field in the
+        USBP control and status register: USBN_USBP_CTL_STATUS[ATE_RESET] = 1 */
+    usbn_usbp_ctl_status.u64 = cvmx_read_csr(CVMX_USBNX_USBP_CTL_STATUS(usb->index));
+    usbn_usbp_ctl_status.s.ate_reset = 1;
+    cvmx_write_csr(CVMX_USBNX_USBP_CTL_STATUS(usb->index), usbn_usbp_ctl_status.u64);
+    /* 6. Wait 10 cycles */
+    cvmx_wait(10);
+    /* 7. Clear ATE_RESET field in the USBN clock-control register:
+        USBN_USBP_CTL_STATUS[ATE_RESET] = 0 */
+    usbn_usbp_ctl_status.s.ate_reset = 0;
+    cvmx_write_csr(CVMX_USBNX_USBP_CTL_STATUS(usb->index), usbn_usbp_ctl_status.u64);
+    /* 8. Program the PHY reset field in the USBN clock-control register:
+        USBN_CLK_CTL[PRST] = 1 */
+    usbn_clk_ctl.s.prst = 1;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    /* 9. Program the USBP control and status register to select host or
+        device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
+        device */
+    usbn_usbp_ctl_status.s.hst_mode = 1;
+    usbn_usbp_ctl_status.s.dm_pulld = 0;
+    usbn_usbp_ctl_status.s.dp_pulld = 0;
+    cvmx_write_csr(CVMX_USBNX_USBP_CTL_STATUS(usb->index), usbn_usbp_ctl_status.u64);
+    /* 10. Wait 1 µs */
+    cvmx_wait_usec(1);
+    /* 11. Program the hreset_n field in the USBN clock-control register:
+        USBN_CLK_CTL[HRST] = 1 */
+    usbn_clk_ctl.s.hrst = 1;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    /* 12. Proceed to USB core initialization */
+    usbn_clk_ctl.s.enable = 1;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    cvmx_wait_usec(1);
+
+    /* Program the following fields in the global AHB configuration
+        register (USBC_GAHBCFG)
+        DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
+        Burst length, USBC_GAHBCFG[HBSTLEN] = 0
+        Nonperiodic TxFIFO empty level (slave mode only),
+        USBC_GAHBCFG[NPTXFEMPLVL]
+        Periodic TxFIFO empty level (slave mode only),
+        USBC_GAHBCFG[PTXFEMPLVL]
+        Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 */
+    {
+        cvmx_usbcx_gahbcfg_t usbcx_gahbcfg;
+        usbcx_gahbcfg.u32 = 0;
+        usbcx_gahbcfg.s.dmaen = 1;
+        usbcx_gahbcfg.s.hbstlen = 0;
+        usbcx_gahbcfg.s.nptxfemplvl = 1;
+        usbcx_gahbcfg.s.ptxfemplvl = 1;
+        usbcx_gahbcfg.s.glblintrmsk = 1;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index), usbcx_gahbcfg.u32);
+    }
+
+    /* Program the following fields in USBC_GUSBCFG register.
+        HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
+        ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
+        USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
+        PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 */
+    {
+        cvmx_usbcx_gusbcfg_t usbcx_gusbcfg;
+        usbcx_gusbcfg.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
+        usbcx_gusbcfg.s.toutcal = 0;
+        usbcx_gusbcfg.s.ddrsel = 0;
+        usbcx_gusbcfg.s.usbtrdtim = 0x5;
+        usbcx_gusbcfg.s.phylpwrclksel = 0;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index), usbcx_gusbcfg.u32);
+    }
+
+    /* Program the following fields in the USBC0/1_DCFG register:
+        Device speed, USBC0/1_DCFG[DEVSPD] = 0 (high speed)
+        Non-zero-length status OUT handshake, USBC0/1_DCFG[NZSTSOUTHSHK]=0
+        Periodic frame interval (if periodic endpoints are supported),
+        USBC0/1_DCFG[PERFRINT] = 1 */
+    {
+        cvmx_usbcx_dcfg_t usbcx_dcfg;
+        usbcx_dcfg.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCFG(usb->index));
+        usbcx_dcfg.s.devspd = 0;
+        usbcx_dcfg.s.nzstsouthshk = 0;
+        usbcx_dcfg.s.perfrint = 1;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DCFG(usb->index), usbcx_dcfg.u32);
+    }
+
+    /* Program the USBC0/1_GINTMSK register */
+    {
+        cvmx_usbcx_gintmsk_t usbcx_gintmsk;
+        usbcx_gintmsk.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
+        usbcx_gintmsk.s.oepintmsk = 1;
+        usbcx_gintmsk.s.inepintmsk = 1;
+        usbcx_gintmsk.s.enumdonemsk = 1;
+        usbcx_gintmsk.s.usbrstmsk = 1;
+        usbcx_gintmsk.s.usbsuspmsk = 1;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index), usbcx_gintmsk.u32);
+    }
+
+    cvmx_usbd_disable(usb);
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_initialize);
+#endif
+
+
+/**
+ * Shutdown a USB port after a call to cvmx_usbd_initialize().
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return Zero or a negative on error.
+ */
+int cvmx_usbd_shutdown(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: Called\n", __FUNCTION__);
+
+    /* Disable the clocks and put them in power on reset */
+    usbn_clk_ctl.u64 = cvmx_read_csr(CVMX_USBNX_CLK_CTL(usb->index));
+    usbn_clk_ctl.s.enable = 1;
+    usbn_clk_ctl.s.por = 1;
+    usbn_clk_ctl.s.hclk_rst = 1;
+    usbn_clk_ctl.s.prst = 0;
+    usbn_clk_ctl.s.hrst = 0;
+    cvmx_write_csr(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_shutdown);
+#endif
+
+
+/**
+ * Enable a USB port. After this call succeeds, the USB port is
+ * online and servicing requests.
+ *
+ * @param usb  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_enable(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_dctl_t usbcx_dctl;
+    usbcx_dctl.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCTL(usb->index));
+    usbcx_dctl.s.cgoutnak = 1;
+    usbcx_dctl.s.sftdiscon = 0;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DCTL(usb->index), usbcx_dctl.u32);
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_enable);
+#endif
+
+
+/**
+ * Disable a USB port. After this call the USB port will not
+ * generate data transfers and will not generate events.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_disable(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_dctl_t usbcx_dctl;
+    usbcx_dctl.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCTL(usb->index));
+    usbcx_dctl.s.sgoutnak = 1;
+    usbcx_dctl.s.sftdiscon = 1;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DCTL(usb->index), usbcx_dctl.u32);
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_disable);
+#endif
+
+
+/**
+ * Register a callback function to process USB events
+ *
+ * @param usb       USB device state populated by
+ *                  cvmx_usbd_initialize().
+ * @param reason    The reason this callback should be called
+ * @param func      Function to call
+ * @param user_data User supplied data for the callback
+ *
+ * @return Zero on succes, negative on failure
+ */
+int cvmx_usbd_register(cvmx_usbd_state_t *usb, cvmx_usbd_callback_t reason, cvmx_usbd_callback_func_t func, void *user_data)
+{
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: Register reason=%d func=%p data=%p\n",
+            __FUNCTION__, reason, func, user_data);
+    usb->callback[reason] = func;
+    usb->callback_data[reason] = user_data;
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_register);
+#endif
+
+/**
+ * @INTERNAL
+ * Poll a device mode endpoint for status
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint to poll
+ *
+ * @return Zero on success
+ */
+static int __cvmx_usbd_poll_in_endpoint(cvmx_usbd_state_t *usb, int endpoint_num)
+{
+    cvmx_usbcx_diepintx_t usbc_diepint;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d\n", __FUNCTION__, endpoint_num);
+
+    usbc_diepint.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index));
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index), usbc_diepint.u32);
+
+    if (usbc_diepint.s.epdisbld)
+    {
+        /* Endpoint Disabled Interrupt (EPDisbld)
+            This bit indicates that the endpoint is disabled per the
+            application's request. */
+        /* Nothing to do */
+    }
+    if (usbc_diepint.s.xfercompl)
+    {
+        cvmx_usbcx_dieptsizx_t usbc_dieptsiz;
+        int bytes_transferred;
+        /* Transfer Completed Interrupt (XferCompl)
+            Indicates that the programmed transfer is complete on the AHB
+            as well as on the USB, for this endpoint. */
+        usbc_dieptsiz.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DIEPTSIZX(endpoint_num, usb->index));
+        bytes_transferred = usb->endpoint[endpoint_num].buffer_length - usbc_dieptsiz.s.xfersize;
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_IN_COMPLETE, endpoint_num, bytes_transferred);
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Poll a device mode endpoint for status
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint to poll
+ *
+ * @return Zero on success
+ */
+static int __cvmx_usbd_poll_out_endpoint(cvmx_usbd_state_t *usb, int endpoint_num)
+{
+    cvmx_usbcx_doepintx_t usbc_doepint;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d\n", __FUNCTION__, endpoint_num);
+
+    usbc_doepint.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index));
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index), usbc_doepint.u32);
+
+    if (usbc_doepint.s.setup)
+    {
+        /* SETUP Phase Done (SetUp)
+            Applies to control OUT endpoints only.
+            Indicates that the SETUP phase for the control endpoint is
+            complete and no more back-to-back SETUP packets were
+            received for the current control transfer. On this interrupt, the
+            application can decode the received SETUP data packet. */
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_DEVICE_SETUP, endpoint_num, 0);
+    }
+    if (usbc_doepint.s.epdisbld)
+    {
+        /* Endpoint Disabled Interrupt (EPDisbld)
+            This bit indicates that the endpoint is disabled per the
+            application's request. */
+        /* Nothing to do */
+    }
+    if (usbc_doepint.s.xfercompl)
+    {
+        cvmx_usbcx_doeptsizx_t usbc_doeptsiz;
+        int bytes_transferred;
+        /* Transfer Completed Interrupt (XferCompl)
+            Indicates that the programmed transfer is complete on the AHB
+            as well as on the USB, for this endpoint. */
+        usbc_doeptsiz.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DOEPTSIZX(endpoint_num, usb->index));
+        bytes_transferred = usb->endpoint[endpoint_num].buffer_length - usbc_doeptsiz.s.xfersize;
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_OUT_COMPLETE, endpoint_num, bytes_transferred);
+    }
+
+    return 0;
+}
+
+
+/**
+ * Poll the USB block for status and call all needed callback
+ * handlers. This function is meant to be called in the interrupt
+ * handler for the USB controller. It can also be called
+ * periodically in a loop for non-interrupt based operation.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_poll(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_gintsts_t usbc_gintsts;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: Called\n", __FUNCTION__);
+
+    /* Read the pending interrupts */
+    usbc_gintsts.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
+    usbc_gintsts.u32 &= __cvmx_usbd_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
+
+    /* Clear the interrupts now that we know about them */
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
+
+    if (usbc_gintsts.s.usbsusp)
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_SUSPEND, 0, 0);
+
+    if (usbc_gintsts.s.enumdone)
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_ENUM_COMPLETE, 0, 0);
+
+    if (usbc_gintsts.s.usbrst)
+    {
+        /* USB Reset (USBRst)
+            The core sets this bit to indicate that a reset is
+            detected on the USB. */
+        __cvmx_usbd_device_reset_complete(usb);
+        __cvmx_usbd_callback(usb, CVMX_USBD_CALLBACK_RESET, 0, 0);
+    }
+
+    if (usbc_gintsts.s.oepint || usbc_gintsts.s.iepint)
+    {
+        cvmx_usbcx_daint_t usbc_daint;
+        usbc_daint.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DAINT(usb->index));
+        if (usbc_daint.s.inepint)
+        {
+            int active_endpoints = usbc_daint.s.inepint;
+
+            while (active_endpoints)
+            {
+                int endpoint;
+                CVMX_CLZ(endpoint, active_endpoints);
+                endpoint = 31 - endpoint;
+                __cvmx_usbd_poll_in_endpoint(usb, endpoint);
+                active_endpoints ^= 1<<endpoint;
+            }
+        }
+        if (usbc_daint.s.outepint)
+        {
+            int active_endpoints = usbc_daint.s.outepint;
+
+            while (active_endpoints)
+            {
+                int endpoint;
+                CVMX_CLZ(endpoint, active_endpoints);
+                endpoint = 31 - endpoint;
+                __cvmx_usbd_poll_out_endpoint(usb, endpoint);
+                active_endpoints ^= 1<<endpoint;
+            }
+        }
+    }
+
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_poll);
+#endif
+
+/**
+ * Get the current USB address
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return The USB address
+ */
+int cvmx_usbd_get_address(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_dcfg_t usbc_dcfg;
+    usbc_dcfg.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCFG(usb->index));
+    return usbc_dcfg.s.devaddr;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_get_address);
+#endif
+
+/**
+ * Set the current USB address
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usbd_initialize().
+ * @param address Address to set
+ */
+void cvmx_usbd_set_address(cvmx_usbd_state_t *usb, int address)
+{
+    cvmx_usbcx_dcfg_t usbc_dcfg;
+    usbc_dcfg.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCFG(usb->index));
+    usbc_dcfg.s.devaddr = address;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DCFG(usb->index), usbc_dcfg.u32);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_set_address);
+#endif
+
+/**
+ * Get the current USB speed
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return The USB speed
+ */
+cvmx_usbd_speed_t cvmx_usbd_get_speed(cvmx_usbd_state_t *usb)
+{
+    cvmx_usbcx_dsts_t usbcx_dsts;
+    usbcx_dsts.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DSTS(usb->index));
+    return usbcx_dsts.s.enumspd;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_get_speed);
+#endif
+
+/**
+ * Set the current USB speed
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param speed  The requested speed
+ */
+void cvmx_usbd_set_speed(cvmx_usbd_state_t *usb, cvmx_usbd_speed_t speed)
+{
+    cvmx_usbcx_dcfg_t usbcx_dcfg;
+    usbcx_dcfg.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DCFG(usb->index));
+    usbcx_dcfg.s.devspd = speed;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DCFG(usb->index), usbcx_dcfg.u32);
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_set_speed);
+#endif
+
+/**
+ * Enable an endpoint to respond to an OUT transaction
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to enable
+ * @param transfer_type
+ *               Transfer type for the endpoint
+ * @param max_packet_size
+ *               Maximum packet size for the endpoint
+ * @param buffer Buffer to receive the data
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_out_endpoint_enable(cvmx_usbd_state_t *usb,
+    int endpoint_num, cvmx_usbd_transfer_t transfer_type,
+    int max_packet_size, uint64_t buffer, int buffer_length)
+{
+    cvmx_usbcx_doepctlx_t usbc_doepctl;
+    cvmx_usbcx_doeptsizx_t usbc_doeptsiz;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d buffer=0x%llx length=%d\n",
+            __FUNCTION__, endpoint_num, (ULL)buffer, buffer_length);
+
+    usb->endpoint[endpoint_num].buffer_length = buffer_length;
+
+    CVMX_SYNCW; /* Flush out pending writes before enable */
+
+    /* Clear any pending interrupts */
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index),
+        __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index)));
+
+    /* Setup the locations the DMA engines use  */
+    cvmx_write_csr(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + endpoint_num*8, buffer);
+
+    usbc_doeptsiz.u32 = 0;
+    usbc_doeptsiz.s.mc = 1;
+    usbc_doeptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
+    if (usbc_doeptsiz.s.pktcnt == 0)
+        usbc_doeptsiz.s.pktcnt = 1;
+    usbc_doeptsiz.s.xfersize = buffer_length;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPTSIZX(endpoint_num, usb->index), usbc_doeptsiz.u32);
+
+    usbc_doepctl.u32 = 0;
+    usbc_doepctl.s.epena = 1;
+    usbc_doepctl.s.setd1pid = 0;
+    usbc_doepctl.s.setd0pid = 0;
+    usbc_doepctl.s.cnak = 1;
+    usbc_doepctl.s.eptype = transfer_type;
+    usbc_doepctl.s.usbactep = 1;
+    if (endpoint_num == 0)
+    {
+        switch (max_packet_size)
+        {
+            case 8:
+                usbc_doepctl.s.mps = 3;
+                break;
+            case 16:
+                usbc_doepctl.s.mps = 2;
+                break;
+            case 32:
+                usbc_doepctl.s.mps = 1;
+                break;
+            default:
+                usbc_doepctl.s.mps = 0;
+                break;
+        }
+    }
+    else
+        usbc_doepctl.s.mps = max_packet_size;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index), usbc_doepctl.u32);
+
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_out_endpoint_enable);
+#endif
+
+
+/**
+ * Disable an OUT endpoint
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to disable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_out_endpoint_disable(cvmx_usbd_state_t *usb, int endpoint_num)
+{
+    cvmx_usbcx_doepctlx_t usbc_doepctl;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d\n", __FUNCTION__, endpoint_num);
+
+    usbc_doepctl.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index));
+    if (usbc_doepctl.s.epena && !usbc_doepctl.s.epdis)
+    {
+        usbc_doepctl.s.epdis = 1;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index), usbc_doepctl.u32);
+    }
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_out_endpoint_disable);
+#endif
+
+
+/**
+ * Enable an endpoint to respond to an IN transaction
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to enable
+ * @param transfer_type
+ *               Transfer type for the endpoint
+ * @param max_packet_size
+ *               Maximum packet size for the endpoint
+ * @param buffer Buffer to send
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_in_endpoint_enable(cvmx_usbd_state_t *usb,
+    int endpoint_num, cvmx_usbd_transfer_t transfer_type,
+    int max_packet_size, uint64_t buffer, int buffer_length)
+{
+    cvmx_usbcx_diepctlx_t usbc_diepctl;
+    cvmx_usbcx_dieptsizx_t usbc_dieptsiz;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d buffer=0x%llx length=%d\n",
+            __FUNCTION__, endpoint_num, (ULL)buffer, buffer_length);
+
+    usb->endpoint[endpoint_num].buffer_length = buffer_length;
+
+    CVMX_SYNCW; /* Flush out pending writes before enable */
+
+    /* Clear any pending interrupts */
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index),
+        __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index)));
+
+    usbc_dieptsiz.u32 = 0;
+    usbc_dieptsiz.s.mc = 1;
+    if (buffer)
+    {
+        cvmx_write_csr(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + endpoint_num*8, buffer);
+        usbc_dieptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
+        if (usbc_dieptsiz.s.pktcnt == 0)
+            usbc_dieptsiz.s.pktcnt = 1;
+        usbc_dieptsiz.s.xfersize = buffer_length;
+    }
+    else
+    {
+        usbc_dieptsiz.s.pktcnt = 0;
+        usbc_dieptsiz.s.xfersize = 0;
+    }
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPTSIZX(endpoint_num, usb->index), usbc_dieptsiz.u32);
+
+    usbc_diepctl.u32 = 0;
+    usbc_diepctl.s.epena = (buffer != 0);
+    usbc_diepctl.s.setd1pid = 0;
+    usbc_diepctl.s.setd0pid = (buffer == 0);
+    usbc_diepctl.s.cnak = 1;
+    usbc_diepctl.s.txfnum = endpoint_num;
+    usbc_diepctl.s.eptype = transfer_type;
+    usbc_diepctl.s.usbactep = 1;
+    usbc_diepctl.s.nextep = endpoint_num;
+    if (endpoint_num == 0)
+    {
+        switch (max_packet_size)
+        {
+            case 8:
+                usbc_diepctl.s.mps = 3;
+                break;
+            case 16:
+                usbc_diepctl.s.mps = 2;
+                break;
+            case 32:
+                usbc_diepctl.s.mps = 1;
+                break;
+            default:
+                usbc_diepctl.s.mps = 0;
+                break;
+        }
+    }
+    else
+        usbc_diepctl.s.mps = max_packet_size;
+    __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index), usbc_diepctl.u32);
+
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_in_endpoint_enable);
+#endif
+
+
+/**
+ * Disable an IN endpoint
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to disable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_in_endpoint_disable(cvmx_usbd_state_t *usb, int endpoint_num)
+{
+    cvmx_usbcx_diepctlx_t usbc_diepctl;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USBD_INITIALIZE_FLAGS_DEBUG))
+        cvmx_dprintf("%s: endpoint=%d\n", __FUNCTION__, endpoint_num);
+
+    usbc_diepctl.u32 = __cvmx_usbd_read_csr32(usb, CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index));
+    if (usbc_diepctl.s.epena && !usbc_diepctl.s.epdis)
+    {
+        usbc_diepctl.s.epdis = 1;
+        __cvmx_usbd_write_csr32(usb, CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index), usbc_diepctl.u32);
+    }
+    return 0;
+}
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_usbd_in_endpoint_disable);
+#endif
+
diff --git a/sys/contrib/octeon-sdk/cvmx-usbd.h b/sys/contrib/octeon-sdk/cvmx-usbd.h
new file mode 100644
index 0000000..a43d841
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-usbd.h
@@ -0,0 +1,300 @@
+#ifndef __CVMX_USBD_H__
+#define __CVMX_USBD_H__
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * "cvmx-usbd.h" defines a set of low level USB functions to help developers
+ * create Octeon USB devices for various operating systems. These functions
+ * provide a generic API to the Octeon USB blocks, hiding the internal hardware
+ * specific operations.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    CVMX_USBD_TRANSFER_CONTROL = 0,
+    CVMX_USBD_TRANSFER_ISOCHRONOUS = 1,
+    CVMX_USBD_TRANSFER_BULK = 2,
+    CVMX_USBD_TRANSFER_INTERRUPT = 3,
+} cvmx_usbd_transfer_t;
+
+typedef enum
+{
+    CVMX_USBD_SPEED_HIGH = 0,
+    CVMX_USBD_SPEED_FULL = 1,
+    CVMX_USBD_SPEED_LOW = 2,
+} cvmx_usbd_speed_t;
+
+typedef enum
+{
+    CVMX_USBD_CALLBACK_SUSPEND,
+    CVMX_USBD_CALLBACK_RESET,
+    CVMX_USBD_CALLBACK_ENUM_COMPLETE,
+    CVMX_USBD_CALLBACK_DEVICE_SETUP,
+    CVMX_USBD_CALLBACK_IN_COMPLETE,
+    CVMX_USBD_CALLBACK_OUT_COMPLETE,
+    __CVMX_USBD_CALLBACK_END
+} cvmx_usbd_callback_t;
+
+typedef enum
+{
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_XI = 1<<0,       /**< The USB port uses a 12MHz crystal as clock source
+                                                            at USB_XO and USB_XI. */
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_XO_GND = 1<<1,      /**< The USB port uses 12/24/48MHz 2.5V board clock
+                                                            source at USB_XO. USB_XI should be tied to GND.*/
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_AUTO = 0,           /**< Automatically determine clock type based on function
+                                                             in cvmx-helper-board.c. */
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_MHZ_MASK  = 3<<3,       /**< Mask for clock speed field */
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_12MHZ = 1<<3,       /**< Speed of reference clock or crystal */
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_24MHZ = 2<<3,       /**< Speed of reference clock */
+    CVMX_USBD_INITIALIZE_FLAGS_CLOCK_48MHZ = 3<<3,       /**< Speed of reference clock */
+    /* Bits 3-4 used to encode the clock frequency */
+    CVMX_USBD_INITIALIZE_FLAGS_DEBUG = 1<<16
+} cvmx_usbd_initialize_flags_t;
+
+typedef void (*cvmx_usbd_callback_func_t)(cvmx_usbd_callback_t reason, int endpoint_num, int bytes_transferred, void *user_data);
+
+typedef struct
+{
+    int init_flags;
+    int index;
+    cvmx_usbd_callback_func_t callback[__CVMX_USBD_CALLBACK_END];
+    void *callback_data[__CVMX_USBD_CALLBACK_END];
+    struct {
+        int buffer_length;
+    } endpoint[16];
+} cvmx_usbd_state_t;
+
+/**
+ * Initialize a USB port for use. This must be called before any
+ * other access to the Octeon USB port is made. The port starts
+ * off in the disabled state.
+ *
+ * @param usb    Pointer to an empty cvmx_usbd_state_t structure
+ *               that will be populated by the initialize call.
+ *               This structure is then passed to all other USB
+ *               functions.
+ * @param usb_port_number
+ *               Which Octeon USB port to initialize.
+ * @param flags  Flags to control hardware initialization. See
+ *               cvmx_usbd_initialize_flags_t for the flag
+ *               definitions. Some flags are mandatory.
+ *
+ * @return Zero or a negative on error.
+ */
+int cvmx_usbd_initialize(cvmx_usbd_state_t *usb, int usb_port_number,
+    cvmx_usbd_initialize_flags_t flags);
+
+/**
+ * Shutdown a USB port after a call to cvmx_usbd_initialize().
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return Zero or a negative on error.
+ */
+int cvmx_usbd_shutdown(cvmx_usbd_state_t *usb);
+
+/**
+ * Enable a USB port. After this call succeeds, the USB port is
+ * online and servicing requests.
+ *
+ * @param usb  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_enable(cvmx_usbd_state_t *usb);
+
+/**
+ * Disable a USB port. After this call the USB port will not
+ * generate data transfers and will not generate events.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_disable(cvmx_usbd_state_t *usb);
+
+/**
+ * Register a callback function to process USB events
+ *
+ * @param usb       USB device state populated by
+ *                  cvmx_usbd_initialize().
+ * @param reason    The reason this callback should be called
+ * @param func      Function to call
+ * @param user_data User supplied data for the callback
+ *
+ * @return Zero on succes, negative on failure
+ */
+int cvmx_usbd_register(cvmx_usbd_state_t *usb, cvmx_usbd_callback_t reason, cvmx_usbd_callback_func_t func, void *user_data);
+
+/**
+ * Poll the USB block for status and call all needed callback
+ * handlers. This function is meant to be called in the interrupt
+ * handler for the USB controller. It can also be called
+ * periodically in a loop for non-interrupt based operation.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return Zero or negative on error.
+ */
+int cvmx_usbd_poll(cvmx_usbd_state_t *usb);
+
+/**
+ * Get the current USB address
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return The USB address
+ */
+int cvmx_usbd_get_address(cvmx_usbd_state_t *usb);
+
+/**
+ * Set the current USB address
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usbd_initialize().
+ * @param address Address to set
+ */
+void cvmx_usbd_set_address(cvmx_usbd_state_t *usb, int address);
+
+/**
+ * Get the current USB speed
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ *
+ * @return The USB speed
+ */
+cvmx_usbd_speed_t cvmx_usbd_get_speed(cvmx_usbd_state_t *usb);
+
+/**
+ * Set the current USB speed
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param speed  The requested speed
+ */
+void cvmx_usbd_set_speed(cvmx_usbd_state_t *usb, cvmx_usbd_speed_t speed);
+
+/**
+ * Enable an endpoint to respond to an OUT transaction
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to enable
+ * @param transfer_type
+ *               Transfer type for the endpoint
+ * @param max_packet_size
+ *               Maximum packet size for the endpoint
+ * @param buffer Buffer to receive the data
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_out_endpoint_enable(cvmx_usbd_state_t *usb,
+    int endpoint_num, cvmx_usbd_transfer_t transfer_type,
+    int max_packet_size, uint64_t buffer, int buffer_length);
+
+/**
+ * Disable an OUT endpoint
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to disable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_out_endpoint_disable(cvmx_usbd_state_t *usb, int endpoint_num);
+
+/**
+ * Enable an endpoint to respond to an IN transaction
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to enable
+ * @param transfer_type
+ *               Transfer type for the endpoint
+ * @param max_packet_size
+ *               Maximum packet size for the endpoint
+ * @param buffer Buffer to send
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_in_endpoint_enable(cvmx_usbd_state_t *usb,
+    int endpoint_num, cvmx_usbd_transfer_t transfer_type,
+    int max_packet_size, uint64_t buffer, int buffer_length);
+
+/**
+ * Disable an IN endpoint
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usbd_initialize().
+ * @param endpoint_num
+ *               Endpoint number to disable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_usbd_in_endpoint_disable(cvmx_usbd_state_t *usb, int endpoint_num);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_USBD_H__ */
+
diff --git a/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h b/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
new file mode 100644
index 0000000..a8ce96a
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
@@ -0,0 +1,2386 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-usbnx-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon usbnx.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_USBNX_TYPEDEFS_H__
+#define __CVMX_USBNX_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull;
+}
+#else
+#define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull;
+}
+#else
+#define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull;
+}
+#else
+#define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull;
+}
+#else
+#define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull;
+}
+#else
+#define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
+{
+	if (!(
+	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
+		cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+	return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull;
+}
+#else
+#define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)
+#endif
+
+/**
+ * cvmx_usbn#_bist_status
+ *
+ * USBN_BIST_STATUS = USBN's Control and Status
+ *
+ * Contain general control bits and status information for the USBN.
+ */
+union cvmx_usbnx_bist_status
+{
+	uint64_t u64;
+	struct cvmx_usbnx_bist_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_7_63                : 57;
+	uint64_t u2nc_bis                     : 1;  /**< Bist status U2N CTL FIFO Memory. */
+	uint64_t u2nf_bis                     : 1;  /**< Bist status U2N FIFO Memory. */
+	uint64_t e2hc_bis                     : 1;  /**< Bist status E2H CTL FIFO Memory. */
+	uint64_t n2uf_bis                     : 1;  /**< Bist status N2U  FIFO Memory. */
+	uint64_t usbc_bis                     : 1;  /**< Bist status USBC FIFO Memory. */
+	uint64_t nif_bis                      : 1;  /**< Bist status for Inbound Memory. */
+	uint64_t nof_bis                      : 1;  /**< Bist status for Outbound Memory. */
+#else
+	uint64_t nof_bis                      : 1;
+	uint64_t nif_bis                      : 1;
+	uint64_t usbc_bis                     : 1;
+	uint64_t n2uf_bis                     : 1;
+	uint64_t e2hc_bis                     : 1;
+	uint64_t u2nf_bis                     : 1;
+	uint64_t u2nc_bis                     : 1;
+	uint64_t reserved_7_63                : 57;
+#endif
+	} s;
+	struct cvmx_usbnx_bist_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_3_63                : 61;
+	uint64_t usbc_bis                     : 1;  /**< Bist status USBC FIFO Memory. */
+	uint64_t nif_bis                      : 1;  /**< Bist status for Inbound Memory. */
+	uint64_t nof_bis                      : 1;  /**< Bist status for Outbound Memory. */
+#else
+	uint64_t nof_bis                      : 1;
+	uint64_t nif_bis                      : 1;
+	uint64_t usbc_bis                     : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} cn30xx;
+	struct cvmx_usbnx_bist_status_cn30xx  cn31xx;
+	struct cvmx_usbnx_bist_status_s       cn50xx;
+	struct cvmx_usbnx_bist_status_s       cn52xx;
+	struct cvmx_usbnx_bist_status_s       cn52xxp1;
+	struct cvmx_usbnx_bist_status_s       cn56xx;
+	struct cvmx_usbnx_bist_status_s       cn56xxp1;
+};
+typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t;
+
+/**
+ * cvmx_usbn#_clk_ctl
+ *
+ * USBN_CLK_CTL = USBN's Clock Control
+ *
+ * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
+ */
+union cvmx_usbnx_clk_ctl
+{
+	uint64_t u64;
+	struct cvmx_usbnx_clk_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t divide2                      : 2;  /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk.
+                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
+                                                         be zero because it is not implemented, so the maximum
+                                                         ratio of eclk/hclk is currently 16.
+                                                         The actual divide number for hclk is:
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
+	uint64_t hclk_rst                     : 1;  /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+	uint64_t p_x_on                       : 1;  /**< Force USB-PHY on during suspend.
+                                                         '1' USB-PHY XO block is powered-down during
+                                                             suspend.
+                                                         '0' USB-PHY XO block is powered-up during
+                                                             suspend.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t reserved_14_15               : 2;
+	uint64_t p_com_on                     : 1;  /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t p_c_sel                      : 2;  /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz (reserved when a crystal is used)
+                                                         '01': 24 MHz (reserved when a crystal is used)
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active.
+                                                         NOTE: if a crystal is used as a reference clock,
+                                                         this field must be set to 12 MHz. */
+	uint64_t cdiv_byp                     : 1;  /**< Used to enable the bypass input to the USB_CLK_DIV. */
+	uint64_t sd_mode                      : 2;  /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+	uint64_t s_bist                       : 1;  /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+	uint64_t por                          : 1;  /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+	uint64_t enable                       : 1;  /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. SEE DIVIDE
+                                                         field of this register. */
+	uint64_t prst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+	uint64_t hrst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+	uint64_t divide                       : 3;  /**< The frequency of 'hclk' used by the USB subsystem
+                                                         is the eclk frequency divided by the value of
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
+                                                         DIVIDE2 of this register.
+                                                         The hclk frequency should be less than 125Mhz.
+                                                         After writing a value to this field the SW should
+                                                         read the field for the value written.
+                                                         The ENABLE field of this register should not be set
+                                                         until AFTER this field is set and then read. */
+#else
+	uint64_t divide                       : 3;
+	uint64_t hrst                         : 1;
+	uint64_t prst                         : 1;
+	uint64_t enable                       : 1;
+	uint64_t por                          : 1;
+	uint64_t s_bist                       : 1;
+	uint64_t sd_mode                      : 2;
+	uint64_t cdiv_byp                     : 1;
+	uint64_t p_c_sel                      : 2;
+	uint64_t p_com_on                     : 1;
+	uint64_t reserved_14_15               : 2;
+	uint64_t p_x_on                       : 1;
+	uint64_t hclk_rst                     : 1;
+	uint64_t divide2                      : 2;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_usbnx_clk_ctl_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_18_63               : 46;
+	uint64_t hclk_rst                     : 1;  /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+	uint64_t p_x_on                       : 1;  /**< Force USB-PHY on during suspend.
+                                                         '1' USB-PHY XO block is powered-down during
+                                                             suspend.
+                                                         '0' USB-PHY XO block is powered-up during
+                                                             suspend.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t p_rclk                       : 1;  /**< Phy refrence clock enable.
+                                                         '1' The PHY PLL uses the XO block output as a
+                                                         reference.
+                                                         '0' Reserved. */
+	uint64_t p_xenbn                      : 1;  /**< Phy external clock enable.
+                                                         '1' The XO block uses the clock from a crystal.
+                                                         '0' The XO block uses an external clock supplied
+                                                             on the XO pin. USB_XI should be tied to
+                                                             ground for this usage. */
+	uint64_t p_com_on                     : 1;  /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t p_c_sel                      : 2;  /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz
+                                                         '01': 24 MHz
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t cdiv_byp                     : 1;  /**< Used to enable the bypass input to the USB_CLK_DIV. */
+	uint64_t sd_mode                      : 2;  /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+	uint64_t s_bist                       : 1;  /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+	uint64_t por                          : 1;  /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+	uint64_t enable                       : 1;  /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. */
+	uint64_t prst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+	uint64_t hrst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+	uint64_t divide                       : 3;  /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk. The eclk will be divided by the
+                                                         value of this field +1 to determine the hclk
+                                                         frequency. (Also see HRST of this register).
+                                                         The hclk frequency must be less than 125 MHz. */
+#else
+	uint64_t divide                       : 3;
+	uint64_t hrst                         : 1;
+	uint64_t prst                         : 1;
+	uint64_t enable                       : 1;
+	uint64_t por                          : 1;
+	uint64_t s_bist                       : 1;
+	uint64_t sd_mode                      : 2;
+	uint64_t cdiv_byp                     : 1;
+	uint64_t p_c_sel                      : 2;
+	uint64_t p_com_on                     : 1;
+	uint64_t p_xenbn                      : 1;
+	uint64_t p_rclk                       : 1;
+	uint64_t p_x_on                       : 1;
+	uint64_t hclk_rst                     : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} cn30xx;
+	struct cvmx_usbnx_clk_ctl_cn30xx      cn31xx;
+	struct cvmx_usbnx_clk_ctl_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_20_63               : 44;
+	uint64_t divide2                      : 2;  /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk.
+                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
+                                                         be zero because it is not implemented, so the maximum
+                                                         ratio of eclk/hclk is currently 16.
+                                                         The actual divide number for hclk is:
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
+	uint64_t hclk_rst                     : 1;  /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+	uint64_t reserved_16_16               : 1;
+	uint64_t p_rtype                      : 2;  /**< PHY reference clock type
+                                                         '0' The USB-PHY uses a 12MHz crystal as a clock
+                                                             source at the USB_XO and USB_XI pins
+                                                         '1' Reserved
+                                                         '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
+                                                             at the USB_XO pin. USB_XI should be tied to
+                                                             ground in this case.
+                                                         '3' Reserved
+                                                         (bit 14 was P_XENBN on 3xxx)
+                                                         (bit 15 was P_RCLK on 3xxx) */
+	uint64_t p_com_on                     : 1;  /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+	uint64_t p_c_sel                      : 2;  /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz (reserved when a crystal is used)
+                                                         '01': 24 MHz (reserved when a crystal is used)
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active.
+                                                         NOTE: if a crystal is used as a reference clock,
+                                                         this field must be set to 12 MHz. */
+	uint64_t cdiv_byp                     : 1;  /**< Used to enable the bypass input to the USB_CLK_DIV. */
+	uint64_t sd_mode                      : 2;  /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+	uint64_t s_bist                       : 1;  /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+	uint64_t por                          : 1;  /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+	uint64_t enable                       : 1;  /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. SEE DIVIDE
+                                                         field of this register. */
+	uint64_t prst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+	uint64_t hrst                         : 1;  /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+	uint64_t divide                       : 3;  /**< The frequency of 'hclk' used by the USB subsystem
+                                                         is the eclk frequency divided by the value of
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
+                                                         DIVIDE2 of this register.
+                                                         The hclk frequency should be less than 125Mhz.
+                                                         After writing a value to this field the SW should
+                                                         read the field for the value written.
+                                                         The ENABLE field of this register should not be set
+                                                         until AFTER this field is set and then read. */
+#else
+	uint64_t divide                       : 3;
+	uint64_t hrst                         : 1;
+	uint64_t prst                         : 1;
+	uint64_t enable                       : 1;
+	uint64_t por                          : 1;
+	uint64_t s_bist                       : 1;
+	uint64_t sd_mode                      : 2;
+	uint64_t cdiv_byp                     : 1;
+	uint64_t p_c_sel                      : 2;
+	uint64_t p_com_on                     : 1;
+	uint64_t p_rtype                      : 2;
+	uint64_t reserved_16_16               : 1;
+	uint64_t hclk_rst                     : 1;
+	uint64_t divide2                      : 2;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn50xx;
+	struct cvmx_usbnx_clk_ctl_cn50xx      cn52xx;
+	struct cvmx_usbnx_clk_ctl_cn50xx      cn52xxp1;
+	struct cvmx_usbnx_clk_ctl_cn50xx      cn56xx;
+	struct cvmx_usbnx_clk_ctl_cn50xx      cn56xxp1;
+};
+typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
+
+/**
+ * cvmx_usbn#_ctl_status
+ *
+ * USBN_CTL_STATUS = USBN's Control And Status Register
+ *
+ * Contains general control and status information for the USBN block.
+ */
+union cvmx_usbnx_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_usbnx_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_6_63                : 58;
+	uint64_t dma_0pag                     : 1;  /**< When '1' sets the DMA engine will set the zero-Page
+                                                         bit in the L2C store operation to the IOB. */
+	uint64_t dma_stt                      : 1;  /**< When '1' sets the DMA engine to use STT operations. */
+	uint64_t dma_test                     : 1;  /**< When '1' sets the DMA engine into Test-Mode.
+                                                         For normal operation this bit should be '0'. */
+	uint64_t inv_a2                       : 1;  /**< When '1' causes the address[2] driven on the AHB
+                                                         for USB-CORE FIFO access to be inverted. Also data
+                                                         writen to and read from the AHB will have it byte
+                                                         order swapped. If the orginal order was A-B-C-D the
+                                                         new byte order will be D-C-B-A. */
+	uint64_t l2c_emod                     : 2;  /**< Endian format for data from/to the L2C.
+                                                         IN:   A-B-C-D-E-F-G-H
+                                                         OUT0: A-B-C-D-E-F-G-H
+                                                         OUT1: H-G-F-E-D-C-B-A
+                                                         OUT2: D-C-B-A-H-G-F-E
+                                                         OUT3: E-F-G-H-A-B-C-D */
+#else
+	uint64_t l2c_emod                     : 2;
+	uint64_t inv_a2                       : 1;
+	uint64_t dma_test                     : 1;
+	uint64_t dma_stt                      : 1;
+	uint64_t dma_0pag                     : 1;
+	uint64_t reserved_6_63                : 58;
+#endif
+	} s;
+	struct cvmx_usbnx_ctl_status_s        cn30xx;
+	struct cvmx_usbnx_ctl_status_s        cn31xx;
+	struct cvmx_usbnx_ctl_status_s        cn50xx;
+	struct cvmx_usbnx_ctl_status_s        cn52xx;
+	struct cvmx_usbnx_ctl_status_s        cn52xxp1;
+	struct cvmx_usbnx_ctl_status_s        cn56xx;
+	struct cvmx_usbnx_ctl_status_s        cn56xxp1;
+};
+typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn0
+ *
+ * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel0.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn0
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn0_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn1
+ *
+ * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel1.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn1
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn1_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn2
+ *
+ * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel2.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn2
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn2_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn3
+ *
+ * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel3.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn3
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn3_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn4
+ *
+ * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel4.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn4
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn4_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn5
+ *
+ * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel5.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn5
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn5_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn6
+ *
+ * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel6.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn6
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn6_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t;
+
+/**
+ * cvmx_usbn#_dma0_inb_chn7
+ *
+ * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
+ *
+ * Contains the starting address for use when USB0 writes to L2C via Channel7.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_inb_chn7
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_inb_chn7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn30xx;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn31xx;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn50xx;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn52xx;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn52xxp1;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn56xx;
+	struct cvmx_usbnx_dma0_inb_chn7_s     cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn0
+ *
+ * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel0.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn0
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn0_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn1
+ *
+ * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel1.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn1
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn1_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn1_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn2
+ *
+ * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel2.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn2
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn2_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn2_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn3
+ *
+ * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel3.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn3
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn3_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn3_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn4
+ *
+ * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel4.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn4
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn4_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn4_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn5
+ *
+ * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel5.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn5
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn5_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn5_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn6
+ *
+ * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel6.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn6
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn6_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn6_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t;
+
+/**
+ * cvmx_usbn#_dma0_outb_chn7
+ *
+ * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
+ *
+ * Contains the starting address for use when USB0 reads from L2C via Channel7.
+ * Writing of this register sets the base address.
+ */
+union cvmx_usbnx_dma0_outb_chn7
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma0_outb_chn7_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_36_63               : 28;
+	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
+#else
+	uint64_t addr                         : 36;
+	uint64_t reserved_36_63               : 28;
+#endif
+	} s;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn30xx;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn31xx;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn50xx;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn52xx;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn52xxp1;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn56xx;
+	struct cvmx_usbnx_dma0_outb_chn7_s    cn56xxp1;
+};
+typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t;
+
+/**
+ * cvmx_usbn#_dma_test
+ *
+ * USBN_DMA_TEST = USBN's DMA TestRegister
+ *
+ * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
+ */
+union cvmx_usbnx_dma_test
+{
+	uint64_t u64;
+	struct cvmx_usbnx_dma_test_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_40_63               : 24;
+	uint64_t done                         : 1;  /**< This field is set when a DMA completes. Writing a
+                                                         '1' to this field clears this bit. */
+	uint64_t req                          : 1;  /**< DMA Request. Writing a 1 to this register
+                                                         will cause a DMA request as specified in the other
+                                                         fields of this register to take place. This field
+                                                         will always read as '0'. */
+	uint64_t f_addr                       : 18; /**< The address to read from in the Data-Fifo. */
+	uint64_t count                        : 11; /**< DMA Request Count. */
+	uint64_t channel                      : 5;  /**< DMA Channel/Enpoint. */
+	uint64_t burst                        : 4;  /**< DMA Burst Size. */
+#else
+	uint64_t burst                        : 4;
+	uint64_t channel                      : 5;
+	uint64_t count                        : 11;
+	uint64_t f_addr                       : 18;
+	uint64_t req                          : 1;
+	uint64_t done                         : 1;
+	uint64_t reserved_40_63               : 24;
+#endif
+	} s;
+	struct cvmx_usbnx_dma_test_s          cn30xx;
+	struct cvmx_usbnx_dma_test_s          cn31xx;
+	struct cvmx_usbnx_dma_test_s          cn50xx;
+	struct cvmx_usbnx_dma_test_s          cn52xx;
+	struct cvmx_usbnx_dma_test_s          cn52xxp1;
+	struct cvmx_usbnx_dma_test_s          cn56xx;
+	struct cvmx_usbnx_dma_test_s          cn56xxp1;
+};
+typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t;
+
+/**
+ * cvmx_usbn#_int_enb
+ *
+ * USBN_INT_ENB = USBN's Interrupt Enable
+ *
+ * The USBN's interrupt enable register.
+ */
+union cvmx_usbnx_int_enb
+{
+	uint64_t u64;
+	struct cvmx_usbnx_int_enb_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_dpe                     : 1;  /**< When set (1) and bit 36 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_rpf                     : 1;  /**< When set (1) and bit 35 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_rpe                     : 1;  /**< When set (1) and bit 34 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t ltl_f_pf                     : 1;  /**< When set (1) and bit 33 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t ltl_f_pe                     : 1;  /**< When set (1) and bit 32 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t u2n_c_pe                     : 1;  /**< When set (1) and bit 31 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t u2n_c_pf                     : 1;  /**< When set (1) and bit 30 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t u2n_d_pf                     : 1;  /**< When set (1) and bit 29 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t u2n_d_pe                     : 1;  /**< When set (1) and bit 28 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t n2u_pe                       : 1;  /**< When set (1) and bit 27 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t n2u_pf                       : 1;  /**< When set (1) and bit 26 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t uod_pf                       : 1;  /**< When set (1) and bit 25 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t uod_pe                       : 1;  /**< When set (1) and bit 24 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q3_e                      : 1;  /**< When set (1) and bit 23 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q3_f                      : 1;  /**< When set (1) and bit 22 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q2_e                      : 1;  /**< When set (1) and bit 21 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q2_f                      : 1;  /**< When set (1) and bit 20 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rg_fi_f                      : 1;  /**< When set (1) and bit 19 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rg_fi_e                      : 1;  /**< When set (1) and bit 18 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2_fi_f                      : 1;  /**< When set (1) and bit 17 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2_fi_e                      : 1;  /**< When set (1) and bit 16 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2c_a_f                      : 1;  /**< When set (1) and bit 15 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2c_s_e                      : 1;  /**< When set (1) and bit 14 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t dcred_f                      : 1;  /**< When set (1) and bit 13 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t dcred_e                      : 1;  /**< When set (1) and bit 12 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lt_pu_f                      : 1;  /**< When set (1) and bit 11 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lt_po_e                      : 1;  /**< When set (1) and bit 10 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nt_pu_f                      : 1;  /**< When set (1) and bit 9 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nt_po_e                      : 1;  /**< When set (1) and bit 8 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pt_pu_f                      : 1;  /**< When set (1) and bit 7 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pt_po_e                      : 1;  /**< When set (1) and bit 6 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lr_pu_f                      : 1;  /**< When set (1) and bit 5 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lr_po_e                      : 1;  /**< When set (1) and bit 4 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nr_pu_f                      : 1;  /**< When set (1) and bit 3 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nr_po_e                      : 1;  /**< When set (1) and bit 2 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pr_pu_f                      : 1;  /**< When set (1) and bit 1 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pr_po_e                      : 1;  /**< When set (1) and bit 0 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+#else
+	uint64_t pr_po_e                      : 1;
+	uint64_t pr_pu_f                      : 1;
+	uint64_t nr_po_e                      : 1;
+	uint64_t nr_pu_f                      : 1;
+	uint64_t lr_po_e                      : 1;
+	uint64_t lr_pu_f                      : 1;
+	uint64_t pt_po_e                      : 1;
+	uint64_t pt_pu_f                      : 1;
+	uint64_t nt_po_e                      : 1;
+	uint64_t nt_pu_f                      : 1;
+	uint64_t lt_po_e                      : 1;
+	uint64_t lt_pu_f                      : 1;
+	uint64_t dcred_e                      : 1;
+	uint64_t dcred_f                      : 1;
+	uint64_t l2c_s_e                      : 1;
+	uint64_t l2c_a_f                      : 1;
+	uint64_t l2_fi_e                      : 1;
+	uint64_t l2_fi_f                      : 1;
+	uint64_t rg_fi_e                      : 1;
+	uint64_t rg_fi_f                      : 1;
+	uint64_t rq_q2_f                      : 1;
+	uint64_t rq_q2_e                      : 1;
+	uint64_t rq_q3_f                      : 1;
+	uint64_t rq_q3_e                      : 1;
+	uint64_t uod_pe                       : 1;
+	uint64_t uod_pf                       : 1;
+	uint64_t n2u_pf                       : 1;
+	uint64_t n2u_pe                       : 1;
+	uint64_t u2n_d_pe                     : 1;
+	uint64_t u2n_d_pf                     : 1;
+	uint64_t u2n_c_pf                     : 1;
+	uint64_t u2n_c_pe                     : 1;
+	uint64_t ltl_f_pe                     : 1;
+	uint64_t ltl_f_pf                     : 1;
+	uint64_t nd4o_rpe                     : 1;
+	uint64_t nd4o_rpf                     : 1;
+	uint64_t nd4o_dpe                     : 1;
+	uint64_t nd4o_dpf                     : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_usbnx_int_enb_s           cn30xx;
+	struct cvmx_usbnx_int_enb_s           cn31xx;
+	struct cvmx_usbnx_int_enb_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_dpe                     : 1;  /**< When set (1) and bit 36 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_rpf                     : 1;  /**< When set (1) and bit 35 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nd4o_rpe                     : 1;  /**< When set (1) and bit 34 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t ltl_f_pf                     : 1;  /**< When set (1) and bit 33 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t ltl_f_pe                     : 1;  /**< When set (1) and bit 32 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t reserved_26_31               : 6;
+	uint64_t uod_pf                       : 1;  /**< When set (1) and bit 25 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t uod_pe                       : 1;  /**< When set (1) and bit 24 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q3_e                      : 1;  /**< When set (1) and bit 23 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q3_f                      : 1;  /**< When set (1) and bit 22 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q2_e                      : 1;  /**< When set (1) and bit 21 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rq_q2_f                      : 1;  /**< When set (1) and bit 20 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rg_fi_f                      : 1;  /**< When set (1) and bit 19 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t rg_fi_e                      : 1;  /**< When set (1) and bit 18 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2_fi_f                      : 1;  /**< When set (1) and bit 17 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2_fi_e                      : 1;  /**< When set (1) and bit 16 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2c_a_f                      : 1;  /**< When set (1) and bit 15 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t l2c_s_e                      : 1;  /**< When set (1) and bit 14 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t dcred_f                      : 1;  /**< When set (1) and bit 13 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t dcred_e                      : 1;  /**< When set (1) and bit 12 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lt_pu_f                      : 1;  /**< When set (1) and bit 11 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lt_po_e                      : 1;  /**< When set (1) and bit 10 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nt_pu_f                      : 1;  /**< When set (1) and bit 9 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nt_po_e                      : 1;  /**< When set (1) and bit 8 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pt_pu_f                      : 1;  /**< When set (1) and bit 7 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pt_po_e                      : 1;  /**< When set (1) and bit 6 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lr_pu_f                      : 1;  /**< When set (1) and bit 5 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t lr_po_e                      : 1;  /**< When set (1) and bit 4 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nr_pu_f                      : 1;  /**< When set (1) and bit 3 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t nr_po_e                      : 1;  /**< When set (1) and bit 2 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pr_pu_f                      : 1;  /**< When set (1) and bit 1 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+	uint64_t pr_po_e                      : 1;  /**< When set (1) and bit 0 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+#else
+	uint64_t pr_po_e                      : 1;
+	uint64_t pr_pu_f                      : 1;
+	uint64_t nr_po_e                      : 1;
+	uint64_t nr_pu_f                      : 1;
+	uint64_t lr_po_e                      : 1;
+	uint64_t lr_pu_f                      : 1;
+	uint64_t pt_po_e                      : 1;
+	uint64_t pt_pu_f                      : 1;
+	uint64_t nt_po_e                      : 1;
+	uint64_t nt_pu_f                      : 1;
+	uint64_t lt_po_e                      : 1;
+	uint64_t lt_pu_f                      : 1;
+	uint64_t dcred_e                      : 1;
+	uint64_t dcred_f                      : 1;
+	uint64_t l2c_s_e                      : 1;
+	uint64_t l2c_a_f                      : 1;
+	uint64_t l2_fi_e                      : 1;
+	uint64_t l2_fi_f                      : 1;
+	uint64_t rg_fi_e                      : 1;
+	uint64_t rg_fi_f                      : 1;
+	uint64_t rq_q2_f                      : 1;
+	uint64_t rq_q2_e                      : 1;
+	uint64_t rq_q3_f                      : 1;
+	uint64_t rq_q3_e                      : 1;
+	uint64_t uod_pe                       : 1;
+	uint64_t uod_pf                       : 1;
+	uint64_t reserved_26_31               : 6;
+	uint64_t ltl_f_pe                     : 1;
+	uint64_t ltl_f_pf                     : 1;
+	uint64_t nd4o_rpe                     : 1;
+	uint64_t nd4o_rpf                     : 1;
+	uint64_t nd4o_dpe                     : 1;
+	uint64_t nd4o_dpf                     : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn50xx;
+	struct cvmx_usbnx_int_enb_cn50xx      cn52xx;
+	struct cvmx_usbnx_int_enb_cn50xx      cn52xxp1;
+	struct cvmx_usbnx_int_enb_cn50xx      cn56xx;
+	struct cvmx_usbnx_int_enb_cn50xx      cn56xxp1;
+};
+typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t;
+
+/**
+ * cvmx_usbn#_int_sum
+ *
+ * USBN_INT_SUM = USBN's Interrupt Summary Register
+ *
+ * Contains the diffrent interrupt summary bits of the USBN.
+ */
+union cvmx_usbnx_int_sum
+{
+	uint64_t u64;
+	struct cvmx_usbnx_int_sum_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
+	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
+	uint64_t nd4o_rpf                     : 1;  /**< NCB DMA Out Request Fifo Push Full. */
+	uint64_t nd4o_rpe                     : 1;  /**< NCB DMA Out Request Fifo Pop Empty. */
+	uint64_t ltl_f_pf                     : 1;  /**< L2C Transfer Length Fifo Push Full. */
+	uint64_t ltl_f_pe                     : 1;  /**< L2C Transfer Length Fifo Pop Empty. */
+	uint64_t u2n_c_pe                     : 1;  /**< U2N Control Fifo Pop Empty. */
+	uint64_t u2n_c_pf                     : 1;  /**< U2N Control Fifo Push Full. */
+	uint64_t u2n_d_pf                     : 1;  /**< U2N Data Fifo Push Full. */
+	uint64_t u2n_d_pe                     : 1;  /**< U2N Data Fifo Pop Empty. */
+	uint64_t n2u_pe                       : 1;  /**< N2U Fifo Pop Empty. */
+	uint64_t n2u_pf                       : 1;  /**< N2U Fifo Push Full. */
+	uint64_t uod_pf                       : 1;  /**< UOD Fifo Push Full. */
+	uint64_t uod_pe                       : 1;  /**< UOD Fifo Pop Empty. */
+	uint64_t rq_q3_e                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
+	uint64_t rq_q3_f                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
+	uint64_t rq_q2_e                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
+	uint64_t rq_q2_f                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
+	uint64_t rg_fi_f                      : 1;  /**< Register Request Fifo Pushed When Full. */
+	uint64_t rg_fi_e                      : 1;  /**< Register Request Fifo Pushed When Full. */
+	uint64_t lt_fi_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t lt_fi_e                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t l2c_a_f                      : 1;  /**< L2C Credit Count Added When Full. */
+	uint64_t l2c_s_e                      : 1;  /**< L2C Credit Count Subtracted When Empty. */
+	uint64_t dcred_f                      : 1;  /**< Data CreditFifo Pushed When Full. */
+	uint64_t dcred_e                      : 1;  /**< Data Credit Fifo Pushed When Full. */
+	uint64_t lt_pu_f                      : 1;  /**< L2C Trasaction Fifo Pushed When Full. */
+	uint64_t lt_po_e                      : 1;  /**< L2C Trasaction Fifo Popped When Full. */
+	uint64_t nt_pu_f                      : 1;  /**< NPI Trasaction Fifo Pushed When Full. */
+	uint64_t nt_po_e                      : 1;  /**< NPI Trasaction Fifo Popped When Full. */
+	uint64_t pt_pu_f                      : 1;  /**< PP  Trasaction Fifo Pushed When Full. */
+	uint64_t pt_po_e                      : 1;  /**< PP  Trasaction Fifo Popped When Full. */
+	uint64_t lr_pu_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t lr_po_e                      : 1;  /**< L2C Request Fifo Popped When Empty. */
+	uint64_t nr_pu_f                      : 1;  /**< NPI Request Fifo Pushed When Full. */
+	uint64_t nr_po_e                      : 1;  /**< NPI Request Fifo Popped When Empty. */
+	uint64_t pr_pu_f                      : 1;  /**< PP  Request Fifo Pushed When Full. */
+	uint64_t pr_po_e                      : 1;  /**< PP  Request Fifo Popped When Empty. */
+#else
+	uint64_t pr_po_e                      : 1;
+	uint64_t pr_pu_f                      : 1;
+	uint64_t nr_po_e                      : 1;
+	uint64_t nr_pu_f                      : 1;
+	uint64_t lr_po_e                      : 1;
+	uint64_t lr_pu_f                      : 1;
+	uint64_t pt_po_e                      : 1;
+	uint64_t pt_pu_f                      : 1;
+	uint64_t nt_po_e                      : 1;
+	uint64_t nt_pu_f                      : 1;
+	uint64_t lt_po_e                      : 1;
+	uint64_t lt_pu_f                      : 1;
+	uint64_t dcred_e                      : 1;
+	uint64_t dcred_f                      : 1;
+	uint64_t l2c_s_e                      : 1;
+	uint64_t l2c_a_f                      : 1;
+	uint64_t lt_fi_e                      : 1;
+	uint64_t lt_fi_f                      : 1;
+	uint64_t rg_fi_e                      : 1;
+	uint64_t rg_fi_f                      : 1;
+	uint64_t rq_q2_f                      : 1;
+	uint64_t rq_q2_e                      : 1;
+	uint64_t rq_q3_f                      : 1;
+	uint64_t rq_q3_e                      : 1;
+	uint64_t uod_pe                       : 1;
+	uint64_t uod_pf                       : 1;
+	uint64_t n2u_pf                       : 1;
+	uint64_t n2u_pe                       : 1;
+	uint64_t u2n_d_pe                     : 1;
+	uint64_t u2n_d_pf                     : 1;
+	uint64_t u2n_c_pf                     : 1;
+	uint64_t u2n_c_pe                     : 1;
+	uint64_t ltl_f_pe                     : 1;
+	uint64_t ltl_f_pf                     : 1;
+	uint64_t nd4o_rpe                     : 1;
+	uint64_t nd4o_rpf                     : 1;
+	uint64_t nd4o_dpe                     : 1;
+	uint64_t nd4o_dpf                     : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} s;
+	struct cvmx_usbnx_int_sum_s           cn30xx;
+	struct cvmx_usbnx_int_sum_s           cn31xx;
+	struct cvmx_usbnx_int_sum_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
+	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
+	uint64_t nd4o_rpf                     : 1;  /**< NCB DMA Out Request Fifo Push Full. */
+	uint64_t nd4o_rpe                     : 1;  /**< NCB DMA Out Request Fifo Pop Empty. */
+	uint64_t ltl_f_pf                     : 1;  /**< L2C Transfer Length Fifo Push Full. */
+	uint64_t ltl_f_pe                     : 1;  /**< L2C Transfer Length Fifo Pop Empty. */
+	uint64_t reserved_26_31               : 6;
+	uint64_t uod_pf                       : 1;  /**< UOD Fifo Push Full. */
+	uint64_t uod_pe                       : 1;  /**< UOD Fifo Pop Empty. */
+	uint64_t rq_q3_e                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
+	uint64_t rq_q3_f                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
+	uint64_t rq_q2_e                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
+	uint64_t rq_q2_f                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
+	uint64_t rg_fi_f                      : 1;  /**< Register Request Fifo Pushed When Full. */
+	uint64_t rg_fi_e                      : 1;  /**< Register Request Fifo Pushed When Full. */
+	uint64_t lt_fi_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t lt_fi_e                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t l2c_a_f                      : 1;  /**< L2C Credit Count Added When Full. */
+	uint64_t l2c_s_e                      : 1;  /**< L2C Credit Count Subtracted When Empty. */
+	uint64_t dcred_f                      : 1;  /**< Data CreditFifo Pushed When Full. */
+	uint64_t dcred_e                      : 1;  /**< Data Credit Fifo Pushed When Full. */
+	uint64_t lt_pu_f                      : 1;  /**< L2C Trasaction Fifo Pushed When Full. */
+	uint64_t lt_po_e                      : 1;  /**< L2C Trasaction Fifo Popped When Full. */
+	uint64_t nt_pu_f                      : 1;  /**< NPI Trasaction Fifo Pushed When Full. */
+	uint64_t nt_po_e                      : 1;  /**< NPI Trasaction Fifo Popped When Full. */
+	uint64_t pt_pu_f                      : 1;  /**< PP  Trasaction Fifo Pushed When Full. */
+	uint64_t pt_po_e                      : 1;  /**< PP  Trasaction Fifo Popped When Full. */
+	uint64_t lr_pu_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
+	uint64_t lr_po_e                      : 1;  /**< L2C Request Fifo Popped When Empty. */
+	uint64_t nr_pu_f                      : 1;  /**< NPI Request Fifo Pushed When Full. */
+	uint64_t nr_po_e                      : 1;  /**< NPI Request Fifo Popped When Empty. */
+	uint64_t pr_pu_f                      : 1;  /**< PP  Request Fifo Pushed When Full. */
+	uint64_t pr_po_e                      : 1;  /**< PP  Request Fifo Popped When Empty. */
+#else
+	uint64_t pr_po_e                      : 1;
+	uint64_t pr_pu_f                      : 1;
+	uint64_t nr_po_e                      : 1;
+	uint64_t nr_pu_f                      : 1;
+	uint64_t lr_po_e                      : 1;
+	uint64_t lr_pu_f                      : 1;
+	uint64_t pt_po_e                      : 1;
+	uint64_t pt_pu_f                      : 1;
+	uint64_t nt_po_e                      : 1;
+	uint64_t nt_pu_f                      : 1;
+	uint64_t lt_po_e                      : 1;
+	uint64_t lt_pu_f                      : 1;
+	uint64_t dcred_e                      : 1;
+	uint64_t dcred_f                      : 1;
+	uint64_t l2c_s_e                      : 1;
+	uint64_t l2c_a_f                      : 1;
+	uint64_t lt_fi_e                      : 1;
+	uint64_t lt_fi_f                      : 1;
+	uint64_t rg_fi_e                      : 1;
+	uint64_t rg_fi_f                      : 1;
+	uint64_t rq_q2_f                      : 1;
+	uint64_t rq_q2_e                      : 1;
+	uint64_t rq_q3_f                      : 1;
+	uint64_t rq_q3_e                      : 1;
+	uint64_t uod_pe                       : 1;
+	uint64_t uod_pf                       : 1;
+	uint64_t reserved_26_31               : 6;
+	uint64_t ltl_f_pe                     : 1;
+	uint64_t ltl_f_pf                     : 1;
+	uint64_t nd4o_rpe                     : 1;
+	uint64_t nd4o_rpf                     : 1;
+	uint64_t nd4o_dpe                     : 1;
+	uint64_t nd4o_dpf                     : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn50xx;
+	struct cvmx_usbnx_int_sum_cn50xx      cn52xx;
+	struct cvmx_usbnx_int_sum_cn50xx      cn52xxp1;
+	struct cvmx_usbnx_int_sum_cn50xx      cn56xx;
+	struct cvmx_usbnx_int_sum_cn50xx      cn56xxp1;
+};
+typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t;
+
+/**
+ * cvmx_usbn#_usbp_ctl_status
+ *
+ * USBN_USBP_CTL_STATUS = USBP Control And Status Register
+ *
+ * Contains general control and status information for the USBN block.
+ */
+union cvmx_usbnx_usbp_ctl_status
+{
+	uint64_t u64;
+	struct cvmx_usbnx_usbp_ctl_status_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
+	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
+	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
+	uint64_t txhsxvtune                   : 2;  /**< Transmitter High-Speed Crossover Adjustment */
+	uint64_t sqrxtune                     : 3;  /**< Squelch Threshold Adjustment */
+	uint64_t compdistune                  : 3;  /**< Disconnect Threshold Adjustment */
+	uint64_t otgtune                      : 3;  /**< VBUS Valid Threshold Adjustment */
+	uint64_t otgdisable                   : 1;  /**< OTG Block Disable */
+	uint64_t portreset                    : 1;  /**< Per_Port Reset */
+	uint64_t drvvbus                      : 1;  /**< Drive VBUS */
+	uint64_t lsbist                       : 1;  /**< Low-Speed BIST Enable. */
+	uint64_t fsbist                       : 1;  /**< Full-Speed BIST Enable. */
+	uint64_t hsbist                       : 1;  /**< High-Speed BIST Enable. */
+	uint64_t bist_done                    : 1;  /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+	uint64_t bist_err                     : 1;  /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+	uint64_t tdata_out                    : 4;  /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+	uint64_t siddq                        : 1;  /**< Drives the USBP (USB-PHY) SIDDQ input.
+                                                         Normally should be set to zero.
+                                                         When customers have no intent to use USB PHY
+                                                         interface, they should:
+                                                           - still provide 3.3V to USB_VDD33, and
+                                                           - tie USB_REXT to 3.3V supply, and
+                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
+	uint64_t txpreemphasistune            : 1;  /**< HS Transmitter Pre-Emphasis Enable */
+	uint64_t dma_bmode                    : 1;  /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+	uint64_t usbc_end                     : 1;  /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+	uint64_t usbp_bist                    : 1;  /**< PHY, This is cleared '0' to run BIST on the USBP. */
+	uint64_t tclk                         : 1;  /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+	uint64_t dp_pulld                     : 1;  /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t dm_pulld                     : 1;  /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t hst_mode                     : 1;  /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+	uint64_t tuning                       : 4;  /**< Transmitter Tuning for High-Speed Operation.
+                                                         Tunes the current supply and rise/fall output
+                                                         times for high-speed operation.
+                                                         [20:19] == 11: Current supply increased
+                                                         approximately 9%
+                                                         [20:19] == 10: Current supply increased
+                                                         approximately 4.5%
+                                                         [20:19] == 01: Design default.
+                                                         [20:19] == 00: Current supply decreased
+                                                         approximately 4.5%
+                                                         [22:21] == 11: Rise and fall times are increased.
+                                                         [22:21] == 10: Design default.
+                                                         [22:21] == 01: Rise and fall times are decreased.
+                                                         [22:21] == 00: Rise and fall times are decreased
+                                                         further as compared to the 01 setting. */
+	uint64_t tx_bs_enh                    : 1;  /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+	uint64_t tx_bs_en                     : 1;  /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+	uint64_t loop_enb                     : 1;  /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+	uint64_t vtest_enb                    : 1;  /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+	uint64_t bist_enb                     : 1;  /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+	uint64_t tdata_sel                    : 1;  /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+	uint64_t taddr_in                     : 4;  /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+	uint64_t tdata_in                     : 8;  /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+	uint64_t ate_reset                    : 1;  /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+	uint64_t ate_reset                    : 1;
+	uint64_t tdata_in                     : 8;
+	uint64_t taddr_in                     : 4;
+	uint64_t tdata_sel                    : 1;
+	uint64_t bist_enb                     : 1;
+	uint64_t vtest_enb                    : 1;
+	uint64_t loop_enb                     : 1;
+	uint64_t tx_bs_en                     : 1;
+	uint64_t tx_bs_enh                    : 1;
+	uint64_t tuning                       : 4;
+	uint64_t hst_mode                     : 1;
+	uint64_t dm_pulld                     : 1;
+	uint64_t dp_pulld                     : 1;
+	uint64_t tclk                         : 1;
+	uint64_t usbp_bist                    : 1;
+	uint64_t usbc_end                     : 1;
+	uint64_t dma_bmode                    : 1;
+	uint64_t txpreemphasistune            : 1;
+	uint64_t siddq                        : 1;
+	uint64_t tdata_out                    : 4;
+	uint64_t bist_err                     : 1;
+	uint64_t bist_done                    : 1;
+	uint64_t hsbist                       : 1;
+	uint64_t fsbist                       : 1;
+	uint64_t lsbist                       : 1;
+	uint64_t drvvbus                      : 1;
+	uint64_t portreset                    : 1;
+	uint64_t otgdisable                   : 1;
+	uint64_t otgtune                      : 3;
+	uint64_t compdistune                  : 3;
+	uint64_t sqrxtune                     : 3;
+	uint64_t txhsxvtune                   : 2;
+	uint64_t txfslstune                   : 4;
+	uint64_t txvreftune                   : 4;
+	uint64_t txrisetune                   : 1;
+#endif
+	} s;
+	struct cvmx_usbnx_usbp_ctl_status_cn30xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_38_63               : 26;
+	uint64_t bist_done                    : 1;  /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+	uint64_t bist_err                     : 1;  /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+	uint64_t tdata_out                    : 4;  /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+	uint64_t reserved_30_31               : 2;
+	uint64_t dma_bmode                    : 1;  /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+	uint64_t usbc_end                     : 1;  /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+	uint64_t usbp_bist                    : 1;  /**< PHY, This is cleared '0' to run BIST on the USBP. */
+	uint64_t tclk                         : 1;  /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+	uint64_t dp_pulld                     : 1;  /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t dm_pulld                     : 1;  /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t hst_mode                     : 1;  /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+	uint64_t tuning                       : 4;  /**< Transmitter Tuning for High-Speed Operation.
+                                                         Tunes the current supply and rise/fall output
+                                                         times for high-speed operation.
+                                                         [20:19] == 11: Current supply increased
+                                                         approximately 9%
+                                                         [20:19] == 10: Current supply increased
+                                                         approximately 4.5%
+                                                         [20:19] == 01: Design default.
+                                                         [20:19] == 00: Current supply decreased
+                                                         approximately 4.5%
+                                                         [22:21] == 11: Rise and fall times are increased.
+                                                         [22:21] == 10: Design default.
+                                                         [22:21] == 01: Rise and fall times are decreased.
+                                                         [22:21] == 00: Rise and fall times are decreased
+                                                         further as compared to the 01 setting. */
+	uint64_t tx_bs_enh                    : 1;  /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+	uint64_t tx_bs_en                     : 1;  /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+	uint64_t loop_enb                     : 1;  /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+	uint64_t vtest_enb                    : 1;  /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+	uint64_t bist_enb                     : 1;  /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+	uint64_t tdata_sel                    : 1;  /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+	uint64_t taddr_in                     : 4;  /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+	uint64_t tdata_in                     : 8;  /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+	uint64_t ate_reset                    : 1;  /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+	uint64_t ate_reset                    : 1;
+	uint64_t tdata_in                     : 8;
+	uint64_t taddr_in                     : 4;
+	uint64_t tdata_sel                    : 1;
+	uint64_t bist_enb                     : 1;
+	uint64_t vtest_enb                    : 1;
+	uint64_t loop_enb                     : 1;
+	uint64_t tx_bs_en                     : 1;
+	uint64_t tx_bs_enh                    : 1;
+	uint64_t tuning                       : 4;
+	uint64_t hst_mode                     : 1;
+	uint64_t dm_pulld                     : 1;
+	uint64_t dp_pulld                     : 1;
+	uint64_t tclk                         : 1;
+	uint64_t usbp_bist                    : 1;
+	uint64_t usbc_end                     : 1;
+	uint64_t dma_bmode                    : 1;
+	uint64_t reserved_30_31               : 2;
+	uint64_t tdata_out                    : 4;
+	uint64_t bist_err                     : 1;
+	uint64_t bist_done                    : 1;
+	uint64_t reserved_38_63               : 26;
+#endif
+	} cn30xx;
+	struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
+	struct cvmx_usbnx_usbp_ctl_status_cn50xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
+	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
+	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
+	uint64_t txhsxvtune                   : 2;  /**< Transmitter High-Speed Crossover Adjustment */
+	uint64_t sqrxtune                     : 3;  /**< Squelch Threshold Adjustment */
+	uint64_t compdistune                  : 3;  /**< Disconnect Threshold Adjustment */
+	uint64_t otgtune                      : 3;  /**< VBUS Valid Threshold Adjustment */
+	uint64_t otgdisable                   : 1;  /**< OTG Block Disable */
+	uint64_t portreset                    : 1;  /**< Per_Port Reset */
+	uint64_t drvvbus                      : 1;  /**< Drive VBUS */
+	uint64_t lsbist                       : 1;  /**< Low-Speed BIST Enable. */
+	uint64_t fsbist                       : 1;  /**< Full-Speed BIST Enable. */
+	uint64_t hsbist                       : 1;  /**< High-Speed BIST Enable. */
+	uint64_t bist_done                    : 1;  /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+	uint64_t bist_err                     : 1;  /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+	uint64_t tdata_out                    : 4;  /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+	uint64_t reserved_31_31               : 1;
+	uint64_t txpreemphasistune            : 1;  /**< HS Transmitter Pre-Emphasis Enable */
+	uint64_t dma_bmode                    : 1;  /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+	uint64_t usbc_end                     : 1;  /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+	uint64_t usbp_bist                    : 1;  /**< PHY, This is cleared '0' to run BIST on the USBP. */
+	uint64_t tclk                         : 1;  /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+	uint64_t dp_pulld                     : 1;  /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t dm_pulld                     : 1;  /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t hst_mode                     : 1;  /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+	uint64_t reserved_19_22               : 4;
+	uint64_t tx_bs_enh                    : 1;  /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+	uint64_t tx_bs_en                     : 1;  /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+	uint64_t loop_enb                     : 1;  /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+	uint64_t vtest_enb                    : 1;  /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+	uint64_t bist_enb                     : 1;  /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+	uint64_t tdata_sel                    : 1;  /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+	uint64_t taddr_in                     : 4;  /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+	uint64_t tdata_in                     : 8;  /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+	uint64_t ate_reset                    : 1;  /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+	uint64_t ate_reset                    : 1;
+	uint64_t tdata_in                     : 8;
+	uint64_t taddr_in                     : 4;
+	uint64_t tdata_sel                    : 1;
+	uint64_t bist_enb                     : 1;
+	uint64_t vtest_enb                    : 1;
+	uint64_t loop_enb                     : 1;
+	uint64_t tx_bs_en                     : 1;
+	uint64_t tx_bs_enh                    : 1;
+	uint64_t reserved_19_22               : 4;
+	uint64_t hst_mode                     : 1;
+	uint64_t dm_pulld                     : 1;
+	uint64_t dp_pulld                     : 1;
+	uint64_t tclk                         : 1;
+	uint64_t usbp_bist                    : 1;
+	uint64_t usbc_end                     : 1;
+	uint64_t dma_bmode                    : 1;
+	uint64_t txpreemphasistune            : 1;
+	uint64_t reserved_31_31               : 1;
+	uint64_t tdata_out                    : 4;
+	uint64_t bist_err                     : 1;
+	uint64_t bist_done                    : 1;
+	uint64_t hsbist                       : 1;
+	uint64_t fsbist                       : 1;
+	uint64_t lsbist                       : 1;
+	uint64_t drvvbus                      : 1;
+	uint64_t portreset                    : 1;
+	uint64_t otgdisable                   : 1;
+	uint64_t otgtune                      : 3;
+	uint64_t compdistune                  : 3;
+	uint64_t sqrxtune                     : 3;
+	uint64_t txhsxvtune                   : 2;
+	uint64_t txfslstune                   : 4;
+	uint64_t txvreftune                   : 4;
+	uint64_t txrisetune                   : 1;
+#endif
+	} cn50xx;
+	struct cvmx_usbnx_usbp_ctl_status_cn52xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t txrisetune                   : 1;  /**< HS Transmitter Rise/Fall Time Adjustment */
+	uint64_t txvreftune                   : 4;  /**< HS DC Voltage Level Adjustment */
+	uint64_t txfslstune                   : 4;  /**< FS/LS Source Impedence Adjustment */
+	uint64_t txhsxvtune                   : 2;  /**< Transmitter High-Speed Crossover Adjustment */
+	uint64_t sqrxtune                     : 3;  /**< Squelch Threshold Adjustment */
+	uint64_t compdistune                  : 3;  /**< Disconnect Threshold Adjustment */
+	uint64_t otgtune                      : 3;  /**< VBUS Valid Threshold Adjustment */
+	uint64_t otgdisable                   : 1;  /**< OTG Block Disable */
+	uint64_t portreset                    : 1;  /**< Per_Port Reset */
+	uint64_t drvvbus                      : 1;  /**< Drive VBUS */
+	uint64_t lsbist                       : 1;  /**< Low-Speed BIST Enable. */
+	uint64_t fsbist                       : 1;  /**< Full-Speed BIST Enable. */
+	uint64_t hsbist                       : 1;  /**< High-Speed BIST Enable. */
+	uint64_t bist_done                    : 1;  /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+	uint64_t bist_err                     : 1;  /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+	uint64_t tdata_out                    : 4;  /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+	uint64_t siddq                        : 1;  /**< Drives the USBP (USB-PHY) SIDDQ input.
+                                                         Normally should be set to zero.
+                                                         When customers have no intent to use USB PHY
+                                                         interface, they should:
+                                                           - still provide 3.3V to USB_VDD33, and
+                                                           - tie USB_REXT to 3.3V supply, and
+                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
+	uint64_t txpreemphasistune            : 1;  /**< HS Transmitter Pre-Emphasis Enable */
+	uint64_t dma_bmode                    : 1;  /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+	uint64_t usbc_end                     : 1;  /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+	uint64_t usbp_bist                    : 1;  /**< PHY, This is cleared '0' to run BIST on the USBP. */
+	uint64_t tclk                         : 1;  /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+	uint64_t dp_pulld                     : 1;  /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t dm_pulld                     : 1;  /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+	uint64_t hst_mode                     : 1;  /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+	uint64_t reserved_19_22               : 4;
+	uint64_t tx_bs_enh                    : 1;  /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+	uint64_t tx_bs_en                     : 1;  /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+	uint64_t loop_enb                     : 1;  /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+	uint64_t vtest_enb                    : 1;  /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+	uint64_t bist_enb                     : 1;  /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+	uint64_t tdata_sel                    : 1;  /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+	uint64_t taddr_in                     : 4;  /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+	uint64_t tdata_in                     : 8;  /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+	uint64_t ate_reset                    : 1;  /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+	uint64_t ate_reset                    : 1;
+	uint64_t tdata_in                     : 8;
+	uint64_t taddr_in                     : 4;
+	uint64_t tdata_sel                    : 1;
+	uint64_t bist_enb                     : 1;
+	uint64_t vtest_enb                    : 1;
+	uint64_t loop_enb                     : 1;
+	uint64_t tx_bs_en                     : 1;
+	uint64_t tx_bs_enh                    : 1;
+	uint64_t reserved_19_22               : 4;
+	uint64_t hst_mode                     : 1;
+	uint64_t dm_pulld                     : 1;
+	uint64_t dp_pulld                     : 1;
+	uint64_t tclk                         : 1;
+	uint64_t usbp_bist                    : 1;
+	uint64_t usbc_end                     : 1;
+	uint64_t dma_bmode                    : 1;
+	uint64_t txpreemphasistune            : 1;
+	uint64_t siddq                        : 1;
+	uint64_t tdata_out                    : 4;
+	uint64_t bist_err                     : 1;
+	uint64_t bist_done                    : 1;
+	uint64_t hsbist                       : 1;
+	uint64_t fsbist                       : 1;
+	uint64_t lsbist                       : 1;
+	uint64_t drvvbus                      : 1;
+	uint64_t portreset                    : 1;
+	uint64_t otgdisable                   : 1;
+	uint64_t otgtune                      : 3;
+	uint64_t compdistune                  : 3;
+	uint64_t sqrxtune                     : 3;
+	uint64_t txhsxvtune                   : 2;
+	uint64_t txfslstune                   : 4;
+	uint64_t txvreftune                   : 4;
+	uint64_t txrisetune                   : 1;
+#endif
+	} cn52xx;
+	struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
+	struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx;
+	struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
+};
+typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-utils.h b/sys/contrib/octeon-sdk/cvmx-utils.h
index 32d87a1..50e1762 100644
--- a/sys/contrib/octeon-sdk/cvmx-utils.h
+++ b/sys/contrib/octeon-sdk/cvmx-utils.h
@@ -1,41 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
+
 /**
  * @file
  * Small utility functions and macros to ease programming of Octeon.
@@ -45,6 +47,10 @@
 #ifndef __CVMX_UTILS_H__
 #define __CVMX_UTILS_H__
 
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include <stdarg.h>
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -69,10 +75,17 @@ extern "C" {
 #if CVMX_ENABLE_DEBUG_PRINTS
     #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
         #define cvmx_dprintf        printk
+        #define cvmx_dvprintf       vprintk
     #else
         #define cvmx_dprintf        printf
+        #define cvmx_dvprintf       vprintf
     #endif
 #else
+    static inline void cvmx_dvprintf(const char *format, va_list ap)
+    {
+        /* Prints are disbled, do nothing */
+    }
+
     static inline void cvmx_dprintf(const char *format, ...) __attribute__ ((format(printf, 1, 2)));
     static inline void cvmx_dprintf(const char *format, ...)
     {
@@ -80,7 +93,7 @@ extern "C" {
     }
 #endif
 
-#define CAST64(v) ((long long)(long)(v))
+#define CAST64(v) ((long long)(long)(v)) // use only when 'v' is a pointer
 #define CASTPTR(type, v) ((type *)(long)(v))
 #define CVMX_MAX_CORES          (16)
 #define CVMX_CACHE_LINE_SIZE    (128)   // In bytes
@@ -99,8 +112,8 @@ extern "C" {
 #define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
     ({int result;                                                       \
     do {                                                                \
-        uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec *     \
-                           cvmx_sysinfo_get()->cpu_clock_hz / 1000000;  \
+        uint64_t done = cvmx_clock_get_count(CVMX_CLOCK_CORE) + (uint64_t)timeout_usec * \
+                        cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000; \
         type c;                                                         \
         while (1)                                                       \
         {                                                               \
@@ -108,7 +121,7 @@ extern "C" {
             if ((c.s.field) op (value)) {                               \
                 result = 0;                                             \
                 break;                                                  \
-            } else if (cvmx_get_cycle() > done) {                       \
+            } else if (cvmx_clock_get_count(CVMX_CLOCK_CORE) > done) {  \
                 result = -1;                                            \
                 break;                                                  \
             } else                                                      \
@@ -178,17 +191,6 @@ static inline uint32_t cvmx_octeon_num_cores(void)
 
 
 /**
- * Return true if Octeon is CN38XX pass 1
- *
- * @return
- */
-static inline int cvmx_octeon_is_pass1(void)
-{
-    return OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1);
-}
-
-
-/**
  * Return true if Octeon is CN36XX
  *
  * @return
@@ -196,7 +198,6 @@ static inline int cvmx_octeon_is_pass1(void)
 static inline int cvmx_octeon_model_CN36XX(void)
 {
     return(OCTEON_IS_MODEL(OCTEON_CN38XX)
-           && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
            &&cvmx_fuse_read(264));
 }
 
diff --git a/sys/contrib/octeon-sdk/cvmx-version.h b/sys/contrib/octeon-sdk/cvmx-version.h
index 292d291..c4901b2 100644
--- a/sys/contrib/octeon-sdk/cvmx-version.h
+++ b/sys/contrib/octeon-sdk/cvmx-version.h
@@ -1,3 +1,39 @@
+/***********************license start***************
+ * Copyright (c) 2003-2007  Cavium Networks (support@cavium.com). All rights 
+ * reserved.
+ * 
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ * 
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ * 
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.  
+ * 
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT 
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.  
+ * 
+ * 
+ **********************license end****************/
+
 /* Version information is made available at compile time in two forms:
 ** 1) a version string for printing
 ** 2) a combined SDK version and build number, suitable for comparisons
@@ -8,5 +44,5 @@
 **     10.9.0 == 10.09.00 > 09.10.00 == 9.10.0 
 ** 
 */ 
-#define OCTEON_SDK_VERSION_NUM  109000312ull
-#define OCTEON_SDK_VERSION_STRING   "Cavium Networks Octeon SDK version 1.9.0, build 312"
+#define OCTEON_SDK_VERSION_NUM  200000366ull
+#define OCTEON_SDK_VERSION_STRING   "Cavium Networks Octeon SDK version 2.0.0, build 366"
diff --git a/sys/contrib/octeon-sdk/cvmx-warn.c b/sys/contrib/octeon-sdk/cvmx-warn.c
index a450d13..f0c4d1d 100644
--- a/sys/contrib/octeon-sdk/cvmx-warn.c
+++ b/sys/contrib/octeon-sdk/cvmx-warn.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for warning users about errors and such.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 #include "cvmx.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-warn.h b/sys/contrib/octeon-sdk/cvmx-warn.h
index 57fa14a..264a613 100644
--- a/sys/contrib/octeon-sdk/cvmx-warn.h
+++ b/sys/contrib/octeon-sdk/cvmx-warn.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Functions for warning users about errors and such.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  */
 #ifndef __CVMX_WARN_H__
diff --git a/sys/contrib/octeon-sdk/cvmx-wqe.h b/sys/contrib/octeon-sdk/cvmx-wqe.h
index 98c7e10..0f8fb8f 100644
--- a/sys/contrib/octeon-sdk/cvmx-wqe.h
+++ b/sys/contrib/octeon-sdk/cvmx-wqe.h
@@ -1,46 +1,43 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
-
-
-
-
 /**
  * @file
  *
@@ -55,12 +52,11 @@
  * This file must not depend on any other header files, except for cvmx.h!!!
  *
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  *
  *
  */
 
-
 #ifndef __CVMX_WQE_H__
 #define __CVMX_WQE_H__
 
@@ -98,10 +94,10 @@ typedef union
         uint64_t               dec_ipsec     : 1; /**< the packet needs to be decrypted (ESP or AH) */
         uint64_t               is_v6         : 1; /**< the packet is IPv6 */
 
-        // (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.)
+      /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
 
         uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
-        // exceptional conditions below
+      /* exceptional conditions below */
         uint64_t               L4_error      : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
                                                     (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
                                                     failure indicated in err_code below, decode:
@@ -200,18 +196,11 @@ typedef union
 
         /* lower err_code = first-level descriptor of the work */
         /* zero for packet submitted by hardware that isn't on the slow path */
-        uint64_t               err_code       : 8; // type is cvmx_pip_err_t (union, so can't use directly
+      uint64_t               err_code       : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
     } snoip;
 
 } cvmx_pip_wqe_word2;
 
-
-
-
-
-
-
-
 /**
  * Work queue entry format
  *
diff --git a/sys/contrib/octeon-sdk/cvmx-zip-defs.h b/sys/contrib/octeon-sdk/cvmx-zip-defs.h
new file mode 100644
index 0000000..b1c7d23
--- /dev/null
+++ b/sys/contrib/octeon-sdk/cvmx-zip-defs.h
@@ -0,0 +1,434 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-zip-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon zip.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+#ifndef __CVMX_ZIP_TYPEDEFS_H__
+#define __CVMX_ZIP_TYPEDEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000080ull);
+}
+#else
+#define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000008ull);
+}
+#else
+#define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000000ull);
+}
+#else
+#define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
+static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
+}
+#else
+#define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
+static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000098ull);
+}
+#else
+#define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
+static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000088ull);
+}
+#else
+#define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
+static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000090ull);
+}
+#else
+#define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC()
+static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+		cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180038000010ull);
+}
+#else
+#define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull))
+#endif
+
+/**
+ * cvmx_zip_cmd_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+union cvmx_zip_cmd_bist_result
+{
+	uint64_t u64;
+	struct cvmx_zip_cmd_bist_result_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_43_63               : 21;
+	uint64_t zip_core                     : 39; /**< BiST result of the ZIP_CORE memories */
+	uint64_t zip_ctl                      : 4;  /**< BiST result of the ZIP_CTL  memories */
+#else
+	uint64_t zip_ctl                      : 4;
+	uint64_t zip_core                     : 39;
+	uint64_t reserved_43_63               : 21;
+#endif
+	} s;
+	struct cvmx_zip_cmd_bist_result_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_31_63               : 33;
+	uint64_t zip_core                     : 27; /**< BiST result of the ZIP_CORE memories */
+	uint64_t zip_ctl                      : 4;  /**< BiST result of the ZIP_CTL  memories */
+#else
+	uint64_t zip_ctl                      : 4;
+	uint64_t zip_core                     : 27;
+	uint64_t reserved_31_63               : 33;
+#endif
+	} cn31xx;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn38xx;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn56xx;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn58xx;
+	struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1;
+	struct cvmx_zip_cmd_bist_result_s     cn63xx;
+	struct cvmx_zip_cmd_bist_result_s     cn63xxp1;
+};
+typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t;
+
+/**
+ * cvmx_zip_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
+ * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
+ * pointer each time that the command buffer segment is exhausted.
+ * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
+ * this register to effectively reset the command buffer state machine.  New commands will then be
+ * read from the newly specified command buffer pointer.
+ */
+union cvmx_zip_cmd_buf
+{
+	uint64_t u64;
+	struct cvmx_zip_cmd_buf_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_58_63               : 6;
+	uint64_t dwb                          : 9;  /**< Number of DontWriteBacks */
+	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
+	uint64_t size                         : 13; /**< Number of uint64s per command buffer segment */
+	uint64_t ptr                          : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
+#else
+	uint64_t ptr                          : 33;
+	uint64_t size                         : 13;
+	uint64_t pool                         : 3;
+	uint64_t dwb                          : 9;
+	uint64_t reserved_58_63               : 6;
+#endif
+	} s;
+	struct cvmx_zip_cmd_buf_s             cn31xx;
+	struct cvmx_zip_cmd_buf_s             cn38xx;
+	struct cvmx_zip_cmd_buf_s             cn38xxp2;
+	struct cvmx_zip_cmd_buf_s             cn56xx;
+	struct cvmx_zip_cmd_buf_s             cn56xxp1;
+	struct cvmx_zip_cmd_buf_s             cn58xx;
+	struct cvmx_zip_cmd_buf_s             cn58xxp1;
+	struct cvmx_zip_cmd_buf_s             cn63xx;
+	struct cvmx_zip_cmd_buf_s             cn63xxp1;
+};
+typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t;
+
+/**
+ * cvmx_zip_cmd_ctl
+ */
+union cvmx_zip_cmd_ctl
+{
+	uint64_t u64;
+	struct cvmx_zip_cmd_ctl_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_2_63                : 62;
+	uint64_t forceclk                     : 1;  /**< Force zip_ctl__clock_on_b == 1 when set */
+	uint64_t reset                        : 1;  /**< Reset oneshot pulse for zip core */
+#else
+	uint64_t reset                        : 1;
+	uint64_t forceclk                     : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_zip_cmd_ctl_s             cn31xx;
+	struct cvmx_zip_cmd_ctl_s             cn38xx;
+	struct cvmx_zip_cmd_ctl_s             cn38xxp2;
+	struct cvmx_zip_cmd_ctl_s             cn56xx;
+	struct cvmx_zip_cmd_ctl_s             cn56xxp1;
+	struct cvmx_zip_cmd_ctl_s             cn58xx;
+	struct cvmx_zip_cmd_ctl_s             cn58xxp1;
+	struct cvmx_zip_cmd_ctl_s             cn63xx;
+	struct cvmx_zip_cmd_ctl_s             cn63xxp1;
+};
+typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t;
+
+/**
+ * cvmx_zip_constants
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+union cvmx_zip_constants
+{
+	uint64_t u64;
+	struct cvmx_zip_constants_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_48_63               : 16;
+	uint64_t depth                        : 16; /**< Maximum search depth for compression */
+	uint64_t onfsize                      : 12; /**< Output near full threshhold in bytes */
+	uint64_t ctxsize                      : 12; /**< Context size in bytes */
+	uint64_t reserved_1_7                 : 7;
+	uint64_t disabled                     : 1;  /**< 1=zip unit isdisabled, 0=zip unit not disabled */
+#else
+	uint64_t disabled                     : 1;
+	uint64_t reserved_1_7                 : 7;
+	uint64_t ctxsize                      : 12;
+	uint64_t onfsize                      : 12;
+	uint64_t depth                        : 16;
+	uint64_t reserved_48_63               : 16;
+#endif
+	} s;
+	struct cvmx_zip_constants_s           cn31xx;
+	struct cvmx_zip_constants_s           cn38xx;
+	struct cvmx_zip_constants_s           cn38xxp2;
+	struct cvmx_zip_constants_s           cn56xx;
+	struct cvmx_zip_constants_s           cn56xxp1;
+	struct cvmx_zip_constants_s           cn58xx;
+	struct cvmx_zip_constants_s           cn58xxp1;
+	struct cvmx_zip_constants_s           cn63xx;
+	struct cvmx_zip_constants_s           cn63xxp1;
+};
+typedef union cvmx_zip_constants cvmx_zip_constants_t;
+
+/**
+ * cvmx_zip_debug0
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+union cvmx_zip_debug0
+{
+	uint64_t u64;
+	struct cvmx_zip_debug0_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_17_63               : 47;
+	uint64_t asserts                      : 17; /**< FIFO assertion checks */
+#else
+	uint64_t asserts                      : 17;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_zip_debug0_cn31xx
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_14_63               : 50;
+	uint64_t asserts                      : 14; /**< FIFO assertion checks */
+#else
+	uint64_t asserts                      : 14;
+	uint64_t reserved_14_63               : 50;
+#endif
+	} cn31xx;
+	struct cvmx_zip_debug0_cn31xx         cn38xx;
+	struct cvmx_zip_debug0_cn31xx         cn38xxp2;
+	struct cvmx_zip_debug0_cn31xx         cn56xx;
+	struct cvmx_zip_debug0_cn31xx         cn56xxp1;
+	struct cvmx_zip_debug0_cn31xx         cn58xx;
+	struct cvmx_zip_debug0_cn31xx         cn58xxp1;
+	struct cvmx_zip_debug0_s              cn63xx;
+	struct cvmx_zip_debug0_s              cn63xxp1;
+};
+typedef union cvmx_zip_debug0 cvmx_zip_debug0_t;
+
+/**
+ * cvmx_zip_error
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+union cvmx_zip_error
+{
+	uint64_t u64;
+	struct cvmx_zip_error_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
+#else
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_zip_error_s               cn31xx;
+	struct cvmx_zip_error_s               cn38xx;
+	struct cvmx_zip_error_s               cn38xxp2;
+	struct cvmx_zip_error_s               cn56xx;
+	struct cvmx_zip_error_s               cn56xxp1;
+	struct cvmx_zip_error_s               cn58xx;
+	struct cvmx_zip_error_s               cn58xxp1;
+	struct cvmx_zip_error_s               cn63xx;
+	struct cvmx_zip_error_s               cn63xxp1;
+};
+typedef union cvmx_zip_error cvmx_zip_error_t;
+
+/**
+ * cvmx_zip_int_mask
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ */
+union cvmx_zip_int_mask
+{
+	uint64_t u64;
+	struct cvmx_zip_int_mask_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_1_63                : 63;
+	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to ZIP_ERROR[0] above */
+#else
+	uint64_t doorbell                     : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_zip_int_mask_s            cn31xx;
+	struct cvmx_zip_int_mask_s            cn38xx;
+	struct cvmx_zip_int_mask_s            cn38xxp2;
+	struct cvmx_zip_int_mask_s            cn56xx;
+	struct cvmx_zip_int_mask_s            cn56xxp1;
+	struct cvmx_zip_int_mask_s            cn58xx;
+	struct cvmx_zip_int_mask_s            cn58xxp1;
+	struct cvmx_zip_int_mask_s            cn63xx;
+	struct cvmx_zip_int_mask_s            cn63xxp1;
+};
+typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t;
+
+/**
+ * cvmx_zip_throttle
+ *
+ * Notes:
+ * The maximum number of inflight data fetch transactions.  Values > 8 are illegal.
+ * Writing 0 to this register causes the ZIP module to temporarily suspend NCB
+ * accesses; it is not recommended for normal operation, but may be useful for
+ * diagnostics.
+ */
+union cvmx_zip_throttle
+{
+	uint64_t u64;
+	struct cvmx_zip_throttle_s
+	{
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t reserved_4_63                : 60;
+	uint64_t max_infl                     : 4;  /**< Maximum number of inflight data fetch transactions on NCB */
+#else
+	uint64_t max_infl                     : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_zip_throttle_s            cn63xx;
+	struct cvmx_zip_throttle_s            cn63xxp1;
+};
+typedef union cvmx_zip_throttle cvmx_zip_throttle_t;
+
+#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-zip.c b/sys/contrib/octeon-sdk/cvmx-zip.c
index a80c54b..1cf5980 100644
--- a/sys/contrib/octeon-sdk/cvmx-zip.c
+++ b/sys/contrib/octeon-sdk/cvmx-zip.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Source file for the zip (deflate) block
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #include "executive-config.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-zip.h b/sys/contrib/octeon-sdk/cvmx-zip.h
index 0a7d876..f5f5859 100644
--- a/sys/contrib/octeon-sdk/cvmx-zip.h
+++ b/sys/contrib/octeon-sdk/cvmx-zip.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Header file for the zip (deflate) block
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
  */
 
 #ifndef __CVMX_ZIP_H__
@@ -90,7 +92,8 @@ typedef enum {
    CVMX_ZIP_COMPLETION_BADCODE  = 7,
    CVMX_ZIP_COMPLETION_BADCODE2 = 8,
    CVMX_ZIP_COMPLETION_ZERO_LEN = 9,
-   CVMX_ZIP_COMPLETION_PARITY   = 10
+   CVMX_ZIP_COMPLETION_PARITY   = 10,
+   CVMX_ZIP_COMPLETION_FATAL    = 11
 } cvmx_zip_completion_code_t;
 
 typedef union {
@@ -238,7 +241,7 @@ int cvmx_zip_shutdown(void);
  */
 int cvmx_zip_submit(cvmx_zip_command_t *command);
 
-/* CSR typedefs have been moved to cvmx-csr-*.h */
+/* CSR typedefs have been moved to cvmx-zip-defs.h */
 
 #ifdef	__cplusplus
 }
diff --git a/sys/contrib/octeon-sdk/cvmx-zone.c b/sys/contrib/octeon-sdk/cvmx-zone.c
index 932cde2..71ef679 100644
--- a/sys/contrib/octeon-sdk/cvmx-zone.c
+++ b/sys/contrib/octeon-sdk/cvmx-zone.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,12 +42,13 @@
 
 
 
+
 /**
  * @file
  *
  * Support library for the Zone Allocator.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52004 $<hr>
  */
 
 
@@ -58,6 +60,7 @@
 
 
 
+#ifndef CVMX_BUILD_FOR_LINUX_USER
 cvmx_zone_t cvmx_zone_create_from_addr(char *name, uint32_t elem_size, uint32_t num_elem,
                              void* mem_ptr, uint64_t mem_size, uint32_t flags)
 {
@@ -128,6 +131,7 @@ cvmx_zone_t cvmx_zone_create_from_arena(char *name, uint32_t elem_size, uint32_t
     return(zone);
 
 }
+#endif
 
 
 
diff --git a/sys/contrib/octeon-sdk/cvmx.h b/sys/contrib/octeon-sdk/cvmx.h
index f696a7a..9cb0a82 100644
--- a/sys/contrib/octeon-sdk/cvmx.h
+++ b/sys/contrib/octeon-sdk/cvmx.h
@@ -1,49 +1,51 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
+
 /**
  * @file
  *
  * Main Octeon executive header file (This should be the second header
  * file included by an application).
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49448 $<hr>
 */
 #ifndef __CVMX_H__
 #define __CVMX_H__
@@ -77,7 +79,9 @@ extern "C" {
 #include "cvmx-sysinfo.h"
 #include "octeon-model.h"
 #include "cvmx-csr.h"
+#include "octeon-feature.h"
 #include "cvmx-utils.h"
+#include "cvmx-clock.h"
 
 #if defined(__mips__) && !defined(CVMX_BUILD_FOR_LINUX_HOST)
 #include "cvmx-access-native.h"
diff --git a/sys/contrib/octeon-sdk/cvmx.mk b/sys/contrib/octeon-sdk/cvmx.mk
deleted file mode 100644
index becb04f..0000000
--- a/sys/contrib/octeon-sdk/cvmx.mk
+++ /dev/null
@@ -1,144 +0,0 @@
-#/***********************license start***************
-# Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
-# reserved.
-#
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#
-#     * Redistributions in binary form must reproduce the above
-#       copyright notice, this list of conditions and the following
-#       disclaimer in the documentation and/or other materials provided
-#       with the distribution.
-#
-#     * Neither the name of Cavium Networks nor the names of
-#       its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written
-#       permission.
-#
-# TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
-# AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
-# OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
-# RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
-# REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
-# DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
-# OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
-# PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
-# POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
-# OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
-#
-#
-# For any questions regarding licensing please contact marketing@caviumnetworks.com
-#
-# ***********************license end**************************************/
-
-#
-#  component Makefile fragment
-#
-
-#  standard component Makefile header
-sp              :=  $(sp).x
-dirstack_$(sp)  :=  $(d)
-d               :=  $(dir)
-
-#  component specification
-
-LIBRARY := $(OBJ_DIR)/libcvmx.a
-
-OBJS_$(d)  :=  \
-	$(OBJ_DIR)/cvmx-bootmem.o \
-	$(OBJ_DIR)/cvmx-cn3010-evb-hs5.o \
-	$(OBJ_DIR)/cvmx-core.o \
-	$(OBJ_DIR)/cvmx-coremask.o \
-	$(OBJ_DIR)/cvmx-cmd-queue.o \
-	$(OBJ_DIR)/cvmx-csr-db.o \
-	$(OBJ_DIR)/cvmx-csr-db-support.o \
-	$(OBJ_DIR)/cvmx-dfa.o \
-	$(OBJ_DIR)/cvmx-dma-engine.o \
-	$(OBJ_DIR)/cvmx-ebt3000.o \
-	$(OBJ_DIR)/cvmx-flash.o \
-	$(OBJ_DIR)/cvmx-fpa.o \
-	$(OBJ_DIR)/cvmx-helper-board.o \
-	$(OBJ_DIR)/cvmx-helper-errata.o \
-	$(OBJ_DIR)/cvmx-helper-fpa.o \
-	$(OBJ_DIR)/cvmx-helper-loop.o \
-	$(OBJ_DIR)/cvmx-helper-npi.o \
-	$(OBJ_DIR)/cvmx-helper-rgmii.o \
-	$(OBJ_DIR)/cvmx-helper-sgmii.o \
-	$(OBJ_DIR)/cvmx-helper-spi.o \
-	$(OBJ_DIR)/cvmx-helper-util.o \
-	$(OBJ_DIR)/cvmx-helper-xaui.o \
-	$(OBJ_DIR)/cvmx-helper.o \
-	$(OBJ_DIR)/cvmx-interrupt-rsl.o \
-	$(OBJ_DIR)/cvmx-interrupt-decodes.o \
-	$(OBJ_DIR)/cvmx-l2c.o \
-	$(OBJ_DIR)/cvmx-llm.o \
-	$(OBJ_DIR)/cvmx-log-arc.o \
-	$(OBJ_DIR)/cvmx-log.o \
-	$(OBJ_DIR)/cvmx-mgmt-port.o \
-	$(OBJ_DIR)/cvmx-nand.o \
-	$(OBJ_DIR)/cvmx-pcie.o \
-	$(OBJ_DIR)/cvmx-pko.o \
-	$(OBJ_DIR)/cvmx-pow.o \
-	$(OBJ_DIR)/cvmx-raid.o \
-	$(OBJ_DIR)/cvmx-spi.o \
-	$(OBJ_DIR)/cvmx-spi4000.o \
-	$(OBJ_DIR)/cvmx-sysinfo.o \
-	$(OBJ_DIR)/cvmx-thunder.o \
-	$(OBJ_DIR)/cvmx-tim.o \
-	$(OBJ_DIR)/cvmx-tra.o \
-	$(OBJ_DIR)/cvmx-twsi.o \
-	$(OBJ_DIR)/cvmx-usb.o \
-	$(OBJ_DIR)/cvmx-warn.o \
-	$(OBJ_DIR)/cvmx-zip.o \
-	$(OBJ_DIR)/cvmx-zone.o \
-	$(OBJ_DIR)/octeon-model.o \
-	$(OBJ_DIR)/octeon-pci-console.o
-ifeq (linux,$(findstring linux,$(OCTEON_TARGET)))
-OBJS_$(d)  +=  \
-	$(OBJ_DIR)/cvmx-app-init-linux.o
-else
-OBJS_$(d)  +=  \
-	$(OBJ_DIR)/cvmx-interrupt.o \
-	$(OBJ_DIR)/cvmx-interrupt-handler.o \
-	$(OBJ_DIR)/cvmx-app-init.o \
-	$(OBJ_DIR)/cvmx-malloc.o
-endif
-
-$(OBJS_$(d)):  CFLAGS_LOCAL := -I$(d) -O2 -g -W -Wall -Wno-unused-parameter -Wundef
-
-#  standard component Makefile rules
-
-DEPS_$(d)   :=  $(OBJS_$(d):.o=.d)
-
-LIBS_LIST   :=  $(LIBS_LIST) $(LIBRARY)
-
-CLEAN_LIST  :=  $(CLEAN_LIST) $(OBJS_$(d)) $(DEPS_$(d)) $(LIBRARY)
-
--include $(DEPS_$(d))
-
-$(LIBRARY): $(OBJS_$(d))
-	$(AR) -cr $@ $^
-
-$(OBJ_DIR)/%.o:	$(d)/%.c
-	$(COMPILE)
-
-$(OBJ_DIR)/%.o:	$(d)/%.S
-	$(ASSEMBLE)
-
-$(OBJ_DIR)/cvmx-app-init-linux.o: $(d)/cvmx-app-init-linux.c
-	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_LOCAL) -MD -c -Umain -o $@ $<
-
-CFLAGS_SPECIAL := -I$(d) -I$(d)/cvmx-malloc -O2 -g -DUSE_CVM_THREADS=1 -D_REENTRANT
-
-$(OBJ_DIR)/cvmx-malloc.o: $(d)/cvmx-malloc/malloc.c
-	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_SPECIAL) -MD -c -o $@ $<
-
-#  standard component Makefile footer
-
-d   :=  $(dirstack_$(sp))
-sp  :=  $(basename $(sp))
diff --git a/sys/contrib/octeon-sdk/executive-config.h.template b/sys/contrib/octeon-sdk/executive-config.h.template
deleted file mode 100644
index d44c9c7..0000000
--- a/sys/contrib/octeon-sdk/executive-config.h.template
+++ /dev/null
@@ -1,180 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *
- *     * Neither the name of Cavium Networks nor the names of
- *       its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written
- *       permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing@caviumnetworks.com
- *
- ***********************license end**************************************/
-
-
-
-/*! 
- * @file executive-config.h.template
- *
- * This file is a template for the executive-config.h file that each
- * application that uses the simple exec must provide.  Each application
- * should have an executive-config.h file in a directory named 'config'.
- * If the application uses other components, config files for those
- * components should be placed in the config directory as well.  The 
- * macros defined in this file control the configuration and functionality
- * provided by the simple executive.  Available macros are commented out
- * and documented in this file.
- */
-
-/*
- * File version info: $Id: executive-config.h.template 41588 2009-03-19 19:41:00Z vmalov $
- *
- */
-#ifndef __EXECUTIVE_CONFIG_H__
-#define __EXECUTIVE_CONFIG_H__
-
-/* Define to enable the use of simple executive DFA functions */
-//#define CVMX_ENABLE_DFA_FUNCTIONS
-
-/* Define to enable the use of simple executive packet output functions.
-** For packet I/O setup enable the helper functions below. 
-*/ 
-//#define CVMX_ENABLE_PKO_FUNCTIONS
-
-/* Define to enable the use of simple executive timer bucket functions. 
-** Refer to cvmx-tim.[ch] for more information
-*/
-//#define CVMX_ENABLE_TIMER_FUNCTIONS
-
-/* Define to enable the use of simple executive helper functions. These
-** include many harware setup functions.  See cvmx-helper.[ch] for
-** details.
-*/
-//#define CVMX_ENABLE_HELPER_FUNCTIONS
-
-/* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
-** the beginning of the packet. If necessary, override the default  
-** here.  See the IPD section of the hardware manual for MBUFF SKIP 
-** details.*/ 
-#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
-
-/* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
-** chained packet element. If necessary, override the default here */
-#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
-
-/* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
-** for all input ports. This controls if IPD sends backpressure to all ports if
-** Octeon's FPA pools don't have enough packet or work queue entries. Even when
-** this is off, it is still possible to get backpressure from individual
-** hardware ports. When configuring backpressure, also check
-** CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override the default
-** here */
-#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
-
-/* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
-**  function. Once it is enabled the hardware starts accepting packets. You
-**  might want to skip the IPD enable if configuration changes are need
-**  from the default helper setup. If necessary, override the default here */
-#define CVMX_HELPER_ENABLE_IPD 1
-
-/* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
-** to incoming packets. */
-#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
-
-/* The following select which fields are used by the PIP to generate
-** the tag on INPUT
-** 0: don't include
-** 1: include */
-#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP	0
-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP   	0
-#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 	0
-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 	0
-#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 	0
-#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP	0
-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP   	0
-#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 	0
-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 	0
-#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL	0
-#define CVMX_HELPER_INPUT_TAG_INPUT_PORT	1
-
-/* Select skip mode for input ports */
-#define CVMX_HELPER_INPUT_PORT_SKIP_MODE	CVMX_PIP_PORT_CFG_MODE_SKIPL2
-
-/* Define the number of queues per output port */
-#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0	1
-#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1	1
-
-/* Configure PKO to use per-core queues (PKO lockless operation). 
-** Please see the related SDK documentation for PKO that illustrates 
-** how to enable and configure this option. */
-//#define CVMX_ENABLE_PKO_LOCKLESS_OPERATION 1
-//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 8
-//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 8
-
-/* Force backpressure to be disabled.  This overrides all other
-** backpressure configuration */
-#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 1
-
-/* Disable the SPI4000's processing of backpressure packets and backpressure
-** generation. When this is 1, the SPI4000 will not stop sending packets when
-** receiving backpressure. It will also not generate backpressure packets when
-** its internal FIFOs are full. */
-#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE 1
-
-/* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
-** routines wait for SPI training. You can override the value using
-** executive-config.h if necessary */
-#define CVMX_HELPER_SPI_TIMEOUT 10
-
-/* Select the number of low latency memory ports (interfaces) that
-** will be configured.  Valid values are 1 and 2.
-*/
-#define CVMX_LLM_CONFIG_NUM_PORTS 2
-
-/* Enable the fix for PKI-100 errata ("Size field is 8 too large in WQE and next
-** pointers"). If CVMX_ENABLE_LEN_M8_FIX is set to 0, the fix for this errata will 
-** not be enabled. 
-** 0: Fix is not enabled
-** 1: Fix is enabled, if supported by hardware
-*/
-#define CVMX_ENABLE_LEN_M8_FIX  1
-
-#if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_ENABLE_PKO_FUNCTIONS)
-#define CVMX_ENABLE_PKO_FUNCTIONS
-#endif
-
-/* Enable setting up of TLB entries to trap NULL pointer references */
-#define CVMX_CONFIG_NULL_POINTER_PROTECT	1
-
-/* Enable debug and informational printfs */
-#define CVMX_CONFIG_ENABLE_DEBUG_PRINTS 	1
-
-/* Executive resource descriptions provided in cvmx-resources.config */
-#include "cvmx-resources.config"
-
-#endif
diff --git a/sys/contrib/octeon-sdk/octeon-boot-info.h b/sys/contrib/octeon-sdk/octeon-boot-info.h
new file mode 100644
index 0000000..0866822
--- /dev/null
+++ b/sys/contrib/octeon-sdk/octeon-boot-info.h
@@ -0,0 +1,152 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+/**
+ * @file
+ *
+ * Interface to Octeon boot structure
+ *
+ * <hr>$Revision:  $<hr>
+ */
+
+#ifndef __OCTEON_BOOT_INFO_H__
+#define __OCTEON_BOOT_INFO_H__
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/types.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This structure is access by bootloader, Linux kernel and the Linux
+ * user space utility "bootoct".
+
+ * In the bootloader, this structure is accessed by assembly code in start.S,
+ * so any changes to content or size must be reflected there as well.
+
+ * This is placed at a fixed address in DRAM, so that cores can access it
+ * when they come out of reset.  It is used to setup the minimal bootloader
+ * runtime environment (stack, but no heap, global data ptr) that is needed
+ * by the non-boot cores to setup the environment for the applications.
+ * The boot_info_addr is the address of a boot_info_block_t structure
+ * which contains more core-specific information.
+ *
+ * The Linux kernel and the Linux bootoct utility access this structure for
+ * implementing CPU hotplug functionality and booting of idle cores with SE
+ * apps respectively.
+ *
+ */
+typedef struct
+{
+    /* First stage address - in ram instead of flash */
+    uint64_t code_addr;
+    /* Setup code for application, NOT application entry point */
+    uint32_t app_start_func_addr;
+    /* k0 is used for global data - needs to be passed to other cores */
+    uint32_t k0_val;
+    /* Address of boot info block structure */
+    uint64_t boot_info_addr;
+    uint32_t flags;         /* flags */
+    uint32_t pad;
+} boot_init_vector_t;
+
+/*
+ * Definition of a data structure setup by the bootloader to enable Linux to
+ * launch SE apps on idle cores.
+ */
+
+struct linux_app_boot_info
+{
+    uint32_t labi_signature;
+    uint32_t start_core0_addr;
+    uint32_t avail_coremask;
+    uint32_t pci_console_active;
+    uint32_t icache_prefetch_disable;
+    uint64_t InitTLBStart_addr;
+    uint32_t start_app_addr;
+    uint32_t cur_exception_base;
+    uint32_t no_mark_private_data;
+    uint32_t compact_flash_common_base_addr;
+    uint32_t compact_flash_attribute_base_addr;
+    uint32_t led_display_base_addr;
+#ifndef __OCTEON_NEWLIB__
+#if defined(__U_BOOT__) || !defined(__KERNEL__)
+    gd_t gd;
+#endif
+#endif
+};
+typedef struct linux_app_boot_info linux_app_boot_info_t;
+
+#endif
+
+/* If not to copy a lot of bootloader's structures
+   here is only offset of requested member */
+#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK    0x765c
+
+/* hardcoded in bootloader */
+#define LABI_ADDR_IN_BOOTLOADER                         0x700
+
+#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
+
+#define LABI_SIGNATURE 0xAABBCC01
+
+/*  from uboot-headers/octeon_mem_map.h */
+#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(__OCTEON_NEWLIB__)
+#define EXCEPTION_BASE_INCR     (4 * 1024)
+#endif
+
+#define OCTEON_NUM_CORES    16
+/* Increment size for exception base addresses (4k minimum) */
+#define EXCEPTION_BASE_BASE     0
+#define BOOTLOADER_PRIV_DATA_BASE        (EXCEPTION_BASE_BASE + 0x800)
+#define BOOTLOADER_BOOT_VECTOR           (BOOTLOADER_PRIV_DATA_BASE)
+#define BOOTLOADER_DEBUG_TRAMPOLINE      (BOOTLOADER_BOOT_VECTOR + BOOT_VECTOR_SIZE)   /* WORD */
+#define BOOTLOADER_DEBUG_TRAMPOLINE_CORE (BOOTLOADER_DEBUG_TRAMPOLINE + 4)   /* WORD */
+
+#define OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE  (OCTEON_NUM_CORES*EXCEPTION_BASE_INCR) /* 16 4k blocks */
+#define BOOTLOADER_DEBUG_REG_SAVE_BASE  (EXCEPTION_BASE_BASE + OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE)
+
+#define BOOT_VECTOR_NUM_WORDS           (8)
+#define BOOT_VECTOR_SIZE                ((OCTEON_NUM_CORES*4)*BOOT_VECTOR_NUM_WORDS)
+
+
+#endif /* __OCTEON_BOOT_INFO_H__ */
diff --git a/sys/contrib/octeon-sdk/octeon-feature.h b/sys/contrib/octeon-sdk/octeon-feature.h
index 6e46f77..a53b9f6 100644
--- a/sys/contrib/octeon-sdk/octeon-feature.h
+++ b/sys/contrib/octeon-sdk/octeon-feature.h
@@ -1,45 +1,47 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  *
@@ -57,19 +59,22 @@ extern "C" {
 
 typedef enum
 {
-    OCTEON_FEATURE_SAAD,        /* Octeon models in the CN5XXX family and higher support atomic add instructions to memory (saa/saad) */
-    OCTEON_FEATURE_ZIP,         /* Does this Octeon support the ZIP offload engine? */
-    OCTEON_FEATURE_CRYPTO,      /* Does this Octeon support crypto acceleration using COP2? */
-    OCTEON_FEATURE_PCIE,        /* Does this Octeon support PCI express? */
-    OCTEON_FEATURE_KEY_MEMORY,  /* Some Octeon models support internal memory for storing cryptographic keys */
-    OCTEON_FEATURE_LED_CONTROLLER, /* Octeon has a LED controller for banks of external LEDs */
-    OCTEON_FEATURE_TRA,         /* Octeon has a trace buffer */
-    OCTEON_FEATURE_MGMT_PORT,   /* Octeon has a management port */
-    OCTEON_FEATURE_RAID,        /* Octeon has a raid unit */
-    OCTEON_FEATURE_USB,         /* Octeon has a builtin USB */
-    OCTEON_FEATURE_NO_WPTR,     /* Octeon IPD can run without using work queue entries */
-    OCTEON_FEATURE_DFA,         /* Octeon has DFA state machines */
-    OCTEON_FEATURE_MDIO_CLAUSE_45,     /* Octeon MDIO block supports clause 45 transactions for 10 Gig support */
+    OCTEON_FEATURE_SAAD,        /**<  Octeon models in the CN5XXX family and higher support atomic add instructions to memory (saa/saad) */
+    OCTEON_FEATURE_ZIP,         /**<  Does this Octeon support the ZIP offload engine? */
+    OCTEON_FEATURE_CRYPTO,      /**<  Does this Octeon support crypto acceleration using COP2? */
+    OCTEON_FEATURE_DORM_CRYPTO, /**<  Can crypto be enabled by calling cvmx_crypto_dormant_enable()? */
+    OCTEON_FEATURE_PCIE,        /**<  Does this Octeon support PCI express? */
+    OCTEON_FEATURE_SRIO,	/**<  Does this Octeon support SRIOs */
+    OCTEON_FEATURE_KEY_MEMORY,  /**<  Some Octeon models support internal memory for storing cryptographic keys */
+    OCTEON_FEATURE_LED_CONTROLLER, /**<  Octeon has a LED controller for banks of external LEDs */
+    OCTEON_FEATURE_TRA,         /**<  Octeon has a trace buffer */
+    OCTEON_FEATURE_MGMT_PORT,   /**<  Octeon has a management port */
+    OCTEON_FEATURE_RAID,        /**<  Octeon has a raid unit */
+    OCTEON_FEATURE_USB,         /**<  Octeon has a builtin USB */
+    OCTEON_FEATURE_NO_WPTR,     /**<  Octeon IPD can run without using work queue entries */
+    OCTEON_FEATURE_DFA,         /**<  Octeon has DFA state machines */
+    OCTEON_FEATURE_MDIO_CLAUSE_45,     /**<  Octeon MDIO block supports clause 45 transactions for 10 Gig support */
+    OCTEON_FEATURE_NPEI,        /**<  CN52XX and CN56XX used a block named NPEI for PCIe access. Newer chips replaced this with SLI+DPI */
 } octeon_feature_t;
 
 /**
@@ -93,42 +98,75 @@ static inline int octeon_has_feature(octeon_feature_t feature)
         case OCTEON_FEATURE_ZIP:
             if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
                 return 0;
-            else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
-                return 1;
             else
-                return (!cvmx_fuse_read(121));
+                return !cvmx_fuse_read(121);
 
         case OCTEON_FEATURE_CRYPTO:
-            return (!cvmx_fuse_read(90));
+	    if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                cvmx_mio_fus_dat2_t fus_2;
+                fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                if (fus_2.s.nocrypto || fus_2.s.nomul) {
+                    return 0;
+                } else if (!fus_2.s.dorm_crypto) {
+                    return 1;
+                } else {
+                    cvmx_rnm_ctl_status_t st;
+                    st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
+                    return st.s.eer_val;
+                }
+            } else {
+                return !cvmx_fuse_read(90);
+            }
+
+        case OCTEON_FEATURE_DORM_CRYPTO:
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                cvmx_mio_fus_dat2_t fus_2;
+                fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
+            } else {
+                return 0;
+            }
 
         case OCTEON_FEATURE_PCIE:
-            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX));
+
+	case OCTEON_FEATURE_SRIO:
+	    return (OCTEON_IS_MODEL(OCTEON_CN6XXX));
 
         case OCTEON_FEATURE_KEY_MEMORY:
+            return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_LED_CONTROLLER:
-            return (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX));
+            return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX);
+
         case OCTEON_FEATURE_TRA:
             return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX));
         case OCTEON_FEATURE_MGMT_PORT:
-            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+            return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_RAID:
-            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+            return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_USB:
             return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX));
+
         case OCTEON_FEATURE_NO_WPTR:
-            return ((OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) &&
-                    !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X));
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX)) &&
+                    !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+
         case OCTEON_FEATURE_DFA:
             if (!OCTEON_IS_MODEL(OCTEON_CN38XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN58XX))
                 return 0;
             else if (OCTEON_IS_MODEL(OCTEON_CN3020))
                 return 0;
-            else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
-                return 1;
             else
-                return(!cvmx_fuse_read(120));
+                return !cvmx_fuse_read(120);
+
         case OCTEON_FEATURE_MDIO_CLAUSE_45:
-            return (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)));
+            return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX));
+
+        case OCTEON_FEATURE_NPEI:
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
     }
     return 0;
 }
diff --git a/sys/contrib/octeon-sdk/octeon-model.c b/sys/contrib/octeon-sdk/octeon-model.c
index 9a4dd36..337d9d7 100644
--- a/sys/contrib/octeon-sdk/octeon-model.c
+++ b/sys/contrib/octeon-sdk/octeon-model.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,17 +42,23 @@
 
 
 
+
 /**
  * @file
  *
  * File defining functions for working with different Octeon
  * models.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 49922 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-clock.h>
+#else
 #include "cvmx.h"
 #include "cvmx-pow.h"
 #include "cvmx-warn.h"
+#endif
 
 #if defined(CVMX_BUILD_FOR_LINUX_USER) || defined(CVMX_BUILD_FOR_STANDALONE)
 #include <octeon-app-init.h>
@@ -71,19 +78,7 @@
 int octeon_model_version_check(uint32_t chip_id)
 {
     //printf("Model Number: %s\n", octeon_model_get_string(chip_id));
-#if OCTEON_IS_COMMON_BINARY()
-    if (chip_id == OCTEON_CN38XX_PASS1)
-    {
-        printf("Runtime Octeon Model checking binaries do not support OCTEON_CN38XX_PASS1 chips\n");
-#ifdef CVMX_BUILD_FOR_STANDALONE
-        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
-            CVMX_BREAK;
-        while (1);
-#else
-        exit(-1);
-#endif
-    }
-#else
+#if !OCTEON_IS_COMMON_BINARY()
     /* Check for special case of mismarked 3005 samples, and adjust cpuid */
     if (chip_id == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
         chip_id |= 0x10;
@@ -96,13 +91,7 @@ int octeon_model_version_check(uint32_t chip_id)
                    "         Expecting ID=0x%08x, Chip is 0x%08x\n", (OCTEON_MODEL & 0xffffff), (unsigned int)chip_id);
             if ((OCTEON_MODEL & 0xffffff) > chip_id)
                 printf("Refusing to run on older revision than program was compiled for.\n");
-#ifdef CVMX_BUILD_FOR_STANDALONE
-            if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
-                CVMX_BREAK;
-            while (1);
-#else
-            exit(-1);
-#endif
+	    exit(-1);
         }
         else
         {
@@ -119,6 +108,33 @@ int octeon_model_version_check(uint32_t chip_id)
     cvmx_warn_if(CVMX_ENABLE_CSR_ADDRESS_CHECKING, "CSR address checks are enabled. Expect some performance loss due to the extra checking\n");
     cvmx_warn_if(CVMX_ENABLE_POW_CHECKS, "POW state checks are enabled. Expect some performance loss due to the extra checking\n");
 
+    /* Core-14449 errata check. Generate a warning message if application 
+       compiled for OcteonPlus/Octeon models are run on Octeon II Pass1 chip */
+    {
+        uint32_t insn;
+
+        asm volatile (
+                      ".set push\n"            \
+                      ".set noreorder\n"       \
+                      "pref_errata:\tpref 0,0($zero)\n"      \
+                      "lw %0, pref_errata\n" \
+                      ".set pop"  : "=r" (insn) : : "memory");
+
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && ((insn >> 16) & 0x1f) != 28)
+        {
+            printf("\n###################################################\n");
+            printf("WARNING: Application not compiled for cn63xx pass1.x chips, use of\n"
+                   "         certain prefetch operations can cause dcache corruption.\n");
+            printf("###################################################\n\n");
+            return -1;
+        }
+        else if (!OCTEON_IS_MODEL(OCTEON_CN63XX) && ((insn >> 16) & 0x1f) == 28)
+        {
+            printf("\n###################################################\n");
+            printf("WARNING: Software configured with -mfix-cn63xxp1 (Core-14449 errata), expect some performance loss.\n");
+            printf("###################################################\n\n");
+        }
+    }
     return(0);
 }
 
@@ -148,9 +164,6 @@ const char *octeon_model_get_string(uint32_t chip_id)
 */
 const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
 {
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-    extern uint64_t octeon_get_clock_rate(void);
-#endif
     const char *        family;
     const char *        core_model;
     char                pass[4];
@@ -163,7 +176,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
     char fuse_model[10];
     uint32_t fuse_data = 0;
 
-    fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+    if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+        fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
     fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
     fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
     num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
@@ -306,7 +320,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
                 else
                     suffix = "SSP";
             }
-            else 
+            else
             {
                 if (fus_dat2.cn56xx.nocrypto)
                     suffix = "CP";
@@ -331,6 +345,17 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
             else
                 family = "52";
             break;
+	case 0x90: /* CN63XX */
+            family = "63";
+            if (num_cores == 6)
+                core_model = "35";
+            if (fus_dat2.cn63xx.nocrypto)
+                suffix = "CP";
+            else if (fus_dat2.cn63xx.dorm_crypto)
+                suffix = "DAP";
+            else
+                suffix = "AAP";
+            break;
         default:
             family = "XX";
             core_model = "XX";
@@ -339,16 +364,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
             break;
     }
 
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-    clock_mhz = octeon_get_clock_rate() / 1000000;
-#elif defined(CVMX_BUILD_FOR_LINUX_HOST)
-    clock_mhz = 0;
-#else
-    if (cvmx_sysinfo_get())
-        clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
-    else
-        clock_mhz = 0;
-#endif
+    clock_mhz = cvmx_clock_get_rate(CVMX_CLOCK_RCLK) / 1000000;
 
     if (family[0] != '3')
     {
diff --git a/sys/contrib/octeon-sdk/octeon-model.h b/sys/contrib/octeon-sdk/octeon-model.h
index 00c0a69..a1ab9b8 100644
--- a/sys/contrib/octeon-sdk/octeon-model.h
+++ b/sys/contrib/octeon-sdk/octeon-model.h
@@ -1,52 +1,54 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
 
 
 
+
 /**
  * @file
  *
  * File defining different Octeon model IDs and macros to
  * compare them.
  *
- * <hr>$Revision: 41586 $<hr>
+ * <hr>$Revision: 52119 $<hr>
  */
 
 #ifndef __OCTEON_MODEL_H__
@@ -88,6 +90,21 @@ extern "C" {
 #define OM_IGNORE_MINOR_REVISION  0x08000000      /* Ignores the minor revison on newer parts */
 #define OM_FLAG_MASK              0xff000000
 
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN63XX_PASS1_0   0x000d9000
+#define OCTEON_CN63XX_PASS1_1   0x000d9001
+#define OCTEON_CN63XX_PASS1_2   0x000d9002
+#define OCTEON_CN63XX_PASS2_0   0x000d9008
+
+#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -146,10 +163,10 @@ extern "C" {
 #define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
 #define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
 
-/* 
+/*
  * CN3XXX models with old revision enconding
  */
-#define OCTEON_CN38XX_PASS1     0x000d0000
+//#define OCTEON_CN38XX_PASS1     0x000d0000    // is not supported
 #define OCTEON_CN38XX_PASS2     0x000d0001
 #define OCTEON_CN38XX_PASS3     0x000d0003
 #define OCTEON_CN38XX           (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
@@ -189,24 +206,26 @@ extern "C" {
 
 /* This matches the complete family of CN3xxx CPUs, and not subsequent models */
 #define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
+#define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
 
 /* The revision byte (low byte) has two different encodings.
 ** CN3XXX:
-** 
+**
 **     bits
 **     <7:5>: reserved (0)
 **     <4>:   alternate package
 **     <3:0>: revision
-**     
+**
 ** CN5XXX:
-** 
+**
 **     bits
 **     <7>:   reserved (0)
 **     <6>:   alternate package
 **     <5:3>: major revision
 **     <2:0>: minor revision
-** 
-*/ 
+**
+*/
 
 /* Masks used for the various types of model/family/revision matching */
 #define OCTEON_38XX_FAMILY_MASK      0x00ffff00
@@ -220,6 +239,7 @@ extern "C" {
 #define OCTEON_58XX_MODEL_MASK       0x00ffffc0
 #define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
 #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
+#define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
 
 #define __OCTEON_MATCH_MASK__(x,y,z) (((x) & (z)) == ((y) & (z)))
@@ -250,11 +270,15 @@ extern "C" {
        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
      ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
+     ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
+       && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
+     ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
+       && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
      ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
     )))
 
-#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__)) || (defined(__FreeBSD__) && defined(_KERNEL))
+#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__)) || defined(__OCTEON_NEWLIB__) || (defined(__FreeBSD__) && defined(_KERNEL))
 
 /* NOTE: This for internal use only!!!!! */
 static inline int __octeon_is_model_runtime__(uint32_t model)
@@ -298,8 +322,6 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 const char *octeon_model_get_string(uint32_t chip_id);
 const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer);
 
-#include "octeon-feature.h"
-
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/contrib/octeon-sdk/octeon-pci-console.c b/sys/contrib/octeon-sdk/octeon-pci-console.c
index 7f4e5ab..a6aff5e 100644
--- a/sys/contrib/octeon-sdk/octeon-pci-console.c
+++ b/sys/contrib/octeon-sdk/octeon-pci-console.c
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -41,19 +42,27 @@
 
 
 
+
 #define CVMX_USE_1_TO_1_TLB_MAPPINGS 0
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/kernel.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-spinlock.h>
+#include <asm/octeon/octeon-pci-console.h>
+
+#define MIN(a,b) min((a),(b))
 
+#else
 #include "cvmx-platform.h"
 
 #include "cvmx.h"
 #include "cvmx-spinlock.h"
 #define	MIN(a,b) (((a)<(b))?(a):(b))
 
-#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL)
 #include "cvmx-bootmem.h"
+#include "octeon-pci-console.h"
 #endif
 
-#include "octeon-pci-console.h"
 
 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
 #include "octeon-pci.h"
@@ -84,7 +93,7 @@ int  __cvmx_pci_console_write (int fd, char *buf, int nbytes)
 
     if (!pci_console_desc_addr)
     {
-        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
+        const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
         pci_console_desc_addr = block_desc->base_addr;
     }
 
diff --git a/sys/contrib/octeon-sdk/octeon-pci-console.h b/sys/contrib/octeon-sdk/octeon-pci-console.h
index d5f0615..a0ab862 100644
--- a/sys/contrib/octeon-sdk/octeon-pci-console.h
+++ b/sys/contrib/octeon-sdk/octeon-pci-console.h
@@ -1,39 +1,40 @@
 /***********************license start***************
- *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
- *  reserved.
+ * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * reserved.
  *
  *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are
- *  met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
  *
- *      * Redistributions of source code must retain the above copyright
- *        notice, this list of conditions and the following disclaimer.
- *
- *      * Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials provided
- *        with the distribution.
- *
- *      * Neither the name of Cavium Networks nor the names of
- *        its contributors may be used to endorse or promote products
- *        derived from this software without specific prior written
- *        permission.
- *
- *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
- *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
  *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Networks nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  ***********************license end**************************************/
 
 
@@ -42,10 +43,13 @@
 
 
 
+
 #ifndef __OCTEON_PCI_CONSOLE_H__
 #define __OCTEON_PCI_CONSOLE_H__
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
 #include "cvmx-platform.h"
+#endif
 
 /* Current versions */
 #define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1